Datasheet HV214FG, HV214PJ, HV214X Datasheet (Supertex)

Page 1
250V Low Charge Injection
8-Channel High Voltage Analog Switch
HV214
HV214
Initial Release
Features
HVCMOS® technology for high performance ❏ Very low quiescent power dissipation – 10µA Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies Surface mount package available
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules
Block Diagram
D
IN
CLK
8 BIT
SHIFT
REGISTER
D
OUT
LATCHES
D LE CL
D LE CL
D LE CL
D LE CL
D LE CL
D LE CL
D LE CL
D LE CL
General Description
The Supertex HV214 is a low charge injection 8-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical MEMS modules.
Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. T o reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals.
The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-210V , +125V/-125V, +210V/-40V.
LEVEL
SHIFTERS
OUTPUT
SWITCHES
®
technology, this device combines high voltage
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
VNNV
PP
V
DD
07/26/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
CL
LE
1
Page 2
Ordering Information
Package Options
VPP – V
NN
28-lead plastic 48-lead TQFP Die
chip carrier
250V HV214PJ HV214FG HV214X
Electrical Characteristics
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T(
A
R
R R I
I I I I
f
I
I
I I I I C T
SNO
SNO
LNO
LOS
ffohctiwstesffoCD003VmR
nohctiwstesffoCD005VmR
QPP
QNN
QPP
QPP
WS
PP
NN
QDD
DD
ROS
KNIS
NI
A
VtnecseiuQ
PP
VtnecseiuQ
NN
VtnecseiuQ
PP
VtnecseiuQ
NN
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VegarevA
PP
VegarevA
NN
VtnecseiuQ
DD
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tnerrucknistuoataD54.0AmV
ecnaticapactupnicigoL01Fp
ecnatsiser-nohctiwslangisllamS
ecnatsiser-nohctiwslangisllamS02%I ecnatsiser-nohctiwslangisegraL32
hctiwsrepegakaelffohctiwS01
tnerrucylppus05
tnerrucylppus05-
tnerrucylppus05
tnerrucylppus05-
tnerruckaeptuptuohctiwS0.2AV
tnerrucylppus
tnerrucylppus
tnerrucylppus01
tnerruCylppusDDVegarevA0.4Amf
egnarerutarepmettneibmA007C°
55 94I 24I 63I 83I 23I
µA
I
V V
Am0.5=
GIS
GIS
GIS
GIS
GIS
GIS
GIS
Am002=
Am0.5=
Am002=
Am0.5=
Am002=
V,Am5=
V=
GIS
PP
V=
GIS
PP
K001=
DAOL
K001=
DAOL
µA µA µA µA
GIS
0.7
0.5
0.5
0.7-
0.5-
0.5-
V V V
Am
V V V
V,V04+=
PP
PP
PP
PP
PP
PP
NN
V,V521+= V,V012+=
V,V04+=
NN
V,V521+= V,V012+=
µA
KLC
V=
TUO
DD
V7.0=
TUO
HV214
)detonesiwrehtosselnusnoitidnocgnitarepodednemmocerrevo,C°52=
V
PP
V
NN
V
PP
V
NN
V
PP
V
NN
PP
I,V01-
A1=
GIS
VdnaV01-
NN
,V04+=
V012-=
,V521+=
V521-=
,V012+=
V04-=
V,V521+=
NN
V521-=
V01+
ffosehctiwsllA ffosehctiwsllA
I,nosehctiwsllA I,nosehctiwsllA
Am5=
WS
Am5=
WS
%1.0elcycytud
V012-=
V521-=
NN
V04-=
NN
V012-=
V521-=
NN
V04-=
NN
V,zHM5=
V0.5=
DD
sehctiwstuptuollA dnanOgninrutera
htiwzhK05taffO
.daolon
V7.0-
2
Page 3
Electrical Characteristics
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V(
t
DS
t
ELW
t
OD
t
LCW
t
US
t
H
f
KLC
tRt,
F
T
NO
T
FFO
td/vdVmumixaM
OKnoitalosiffO
K
RC
I
DI
C
)FFO(GS
C
)NO(GS
V+
KPS
V-
KPS
V+
KPS
V-
KPS
V+
KPS
V-
KPS
*ELfohtdiwemiT051sn
LCfohtdiwemiT051sn
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emitnonruT0.5 emitffonruT0.5
GIS
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etarwels
dnGotWSecnaticapacffO0.52171FpzHM1=f,V0 dnGotWSecnaticapacnO528305FpzHM1=f,V0
T,V5=
DD
A
µs µs
02 02VPPV,V521+=
02VPPV,V012+= 03­85-05,zHM0.5=f daol
tnerrucedoidnoitalosihctiwstuptuO003Amelcycytud%0.2,htdiweslupsn003
002 002 002 002 002 002
V
GIS
V
GIS
V
PP
sn/V
Bd
VmV
PP
VmV
PP
VmV
PP
HV214
)detonesiwrehtosselnusnoitidnocgnitarepodednemmocerrevo,C°52=
f=
2/
ATAD
KLC
V= V=
R,V01-
PP
R,V01-
PP
V,V04+=
NN
NN
NN
k01=
DAOL
k01=
DAOL
V012-=
V521-=
V04-=
K1,zHM0.5=f daolFp51/
V,V04+=
NN
V,V521+=
NN
V,V012+=
NN
R,V012-=
R,V521-=
R,V04-=
05=
DAOL
05=
DAOL
05=
DAOL
Absolute Maximum Ratings*
VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage 260V V
Positive high voltage supply -0.5V to VNN +250V
PP
VNN Negative high voltage supply +0.5V to -260V Logic input voltages -0.5V to VDD +0.3V Analog Signal Range V Peak analog signal current/channel 2.5A Storage temperature -65°C to +150°C Power dissipation 28-pin PLCC 1.2W
48 lead TQFP 1.0W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability.
NN
to V
PP
3
Page 4
Operating Conditions
Symbol Parameter Value
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Power Up/Down Sequence:
1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2V
must be VNN V
SIG
SIG
3 Rise and fall times of power supplies V
Logic power supply voltage 4.5V to 13.2V Positive high voltage supply 40V to VNN+ 250V Negative high voltage supply -40V to -210V High-level input voltage VDD -1.5V to V Low-level input voltage 0V to 1.5V Analog signal voltage peak to peak VNN +10V to VPP -10V Operating free air-temperature 0°C to 70°C
VPP or floating during power up/down transistion.
, VPP, and VNN should not be less than 1.0msec.
DD
HV214
DD
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
LLLOFF
HLLON
LLLOFF
HLLON
LLLOFF
HLLON
LLLOFF
HLLON
LLL OFF HLL ON
LLL OFF HLL ON
LLL OFF
HLL ON
LLL OFF
HLL ON
X XXXXXXXHL HOLD PREVIOUS STATE X XXXXXXX XHOFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch.
is high when switch 7 is on.
4. D
OUT
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
4
Page 5
Logic Timing Waveforms
HV214
V
OUT
(TYP)
DATA
LE
CLOCK
DATA
OUT
OFF
ON
CLR
D
N – 1
t
WCL
50%
t
SU
50%50%
IN
D
50%50%
50%
N
t
WLE
t
SD
t
50%
90%
DO
t
t
50%
h
OFF
50%
10%
D
N + 1
t
ON
Block Diagram
D
CLK
D
IN
OUT
8 BIT
SHIFT
REGISTER
V
DD
CL
LE
LATCHES
D LE CL
D LE
CL D
LE CL
D LE CL
D LE CL
D LE CL
D LE CL
D LE CL
LEVEL
SHIFTERS
VNNV
PP
OUTPUT
SWITCHES
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
5
Page 6
Test Circuits
I
SOL
–10
V
PP
HV214
VPP –10V
R
10K
V
OUT
L
V
OUT
VNN +10
V
OUT
V
V
VIN = 10 V
@5MHz
V
V
PP
NN
V
PP
V
NN
Switch OFF Leakage
P–P
R
L
PP
NN
V
PP
V
NN
V
GND
V
GND
100K R
DD
5V
V
SIG
L
V
PP
V
NN
V
PP
V
NN
DC Offset ON/OFF
I
ID
V
NN
V
GND
DD
5V
V
PP
V
NN
VIN = 10 V
@5MHz
P–P
V
PP
V
NN
TON/T
Test Circuit
OFF
V
GND
DD
5V
50
NC
50
DD
5V
V
PP
V
NN
V
PP
V
NN
V
GND
DD
5V
V
PP
V
NN
V
PP
V
NN
V
GND
DD
5V
V
V
SIG
V
OUT
OUT
1000pF
V
KO = 20Log
V
OUT
IN
OFF Isolation
V
PP
V
NN
Charge Injection
V
PP
V
NN
Q = 1000pF x V
V
GND
OUT
V
V
OUT
IN
Isolation Diode Current
+V
SPK
V
OUT
–V
SPK
KCR = 20Log
Crosstalk
50
1K R
L
DD
5V
V
PP
V
NN
V
PP
V
NN
V
GND
DD
5V
Output Voltage Spike
6
Page 7
Pin Configurations Package Outlines
HV214
HV214 28 Pin J-Lead
Pin Function Pin Function
1 SW3 15 N/C 2 SW3 16 D
IN
3 SW2 17 CLK 4 SW2 18 LE 5 SW1 19 CL 6 SW1 20 D
OUT
7 SW0 21 SW7 8 SW0 22 SW7 9 N/C 23 SW6 10 V
PP
24 SW6 11 N/C 25 SW5 12 V
NN
26 SW5 13 GND 27 SW4 14 V
DD
28 SW4
Pin Configurations
24 23 22 21 20
25
26
27
28
1
2
3
4
HV202, HV203
5
678910
top view
28-pin J-Lead Package
Package Outlines
19
18
17
16
15
14
13
12
11
HV214 48-Pin TQFP
Pin Function
1 SW5 2 N/C 3 SW4 4 N/C 5 SW4 6 N/C 7 N/C 8 SW3 9 N/C 10 SW3 11 N/C 12 SW2 13 N/C 14 SW2 15 N/C 16 SW1 17 N/C 18 SW1 19 N/C 20 SW0 21 N/C 22 SW0 23 N/C 24 V
PP
Pin Function
25 V
NN
26 N/C 27 N/C 28 GND 29 V
DD
30 N/C 31 N/C 32 N/C 33 D
IN
34 CLK 35 LE 36 CLR 37 D
OUT
38 N/C 39 SW7 40 N/C 41 SW7 42 N/C 43 SW6 44 N/C 45 SW6 46 N/C 47 SW5 48 N/C
Pin 1
Pin 12
HV202
HV214
top view
48-pin TQFP
Pin #1
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
07/26/02rev.2b
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
7
www.supertex.com
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