DAEWOO DG-K301 Service Manual

Service Manual

DVD PLAYER

MODEL: DG-K301

Caution :

In this Manual, some parts can be changed for improving, their performance without notice in the parts list. So, if you need the latest parts information,please refer to PPL(Parts Price List) in Service Information Center.

July. 2007

CONTENTS

CONTENTS
SPECIFICATIONS.........................................................................................................................	2
CIRCUIT OPERATIONAL DESCRIPTION.........................................................................................	3
VOLTAGE CHARTS.....................................................................................................................	16
CIRCUIT DIAGRAM...................................................................................................................	18
PCB CIRCUIT BOARD.................................................................................................................	24
WAVEFORMS............................................................................................................................	27
TROUBLE SHOOTING.................................................................................................................	36
INSTRUMENT DISASSEMBLY......................................................................................................	41
PARTLIST...................................................................................................................................	42

SPECIFICATIONS

			Laser		wavelength 650nm
			Video		PAL/AUTO/NTSC
	Frequency response				20Hz ~ 20KHz (±1dB)
	Signal/noise ratio				≥90dB
	Channel separation				≥85dB ( 1KHz)
	Dynamic range				≥80dB ( 1KHz)
				Analog	output level : 2.0 + 0/-0.2Vrms
Output					(Load impedance : 1,0KΩ)
Audio				Digital	output level : 0.5 ±0.1Vp-p
					(Load impedance : 75Ω)
				Composite	output level : 1.0 ±0.1Vp-p
					(Load impedance : 75Ω, imbalance, negative polarity)
Output
					output level : brightness(Luma) 1.0 ±0.1Vp-p Chromaticity (Color)
Video				S-video	0.286 ±20%
					(Load impedance : 75Ω)
				Component	Y: 1Vp-p, Pb/Pr: 0.7Vp-p (Load impedance : 75Ω)
			Power		100-240V~, 50Hz~60Hz 12W
Dimensiones				Body (W x H x D)	360 x 38 x 215 mm
				Packing	437 x 90 x 280 mm
	Weight (Gross / Net)				1.97Kg / 1.41Kg

Notes : Design and specifications in this instruction manual are subjected to change without prior notice toimprove quality and function.

DVD Audio output standards

	Output		Disc type
		DVD	VIDEO-CD	CD
	Analogue Audio output	48/96KHz sampling	44.1KHz sampling	44.1KHz sampling
	Digital Audio output	48KHz sampling	44.1KHz sampling	44.1KHz sampling

CIRCUIT OPERATIONAL DESCRIPTION

1. DVD Module

1) Summary

DVD One Board consists of: Loader part that reads and transmits audio and video data saved at Optic Discs (DVD, CD-DA, VCD, CD-R) to MPEG Decoder part; MPEG Decoder part, which, by decoding and encoding data received from the Loader, produces analog signals; and u-Com that controls the overall system including the loader and MPEG decoder.

2) How Does it Operate

Insert the power cord and then power transmitted to each IC, and the SET will be the STANDBY status which requires the least power for input the front panel key, input the STAND BY/ ON key, extinguished the LED. Once the Power On key is entered, u-Com recognizes it and initiates each chipset, performs sequential algorithms such as determining whether the disc is in or not, and if in, what type of disc is loaded.

Through this process, it can read disc data before transmitting it to the MPEG Decoder. The MPEG Decoder will then decode and encode such data before generating the final analog audio and video signal outputs.

DVD-MODULE Block Diagram

CIRCUIT OPERATIONAL DESCRIPTION

3) Loader Part

The loader which read the data of audio/video from optic disc and transfer them to MPEG decoder can be divided into Deck total DVD assay(in a short term, Mecha) and Servo. Mecha mounts with the optical pick-up which allows reading the signal of a disc using laser beam and makes it operates and consists of the deck mechanism which allows loading a disc and reading the data. Servo is a sort of circuit which allows operating the loader and recovering the data and consists of Motor Drive IC operating the spindle, the sled, the loading motor.

Loader Block Diagram

CIRCUIT OPERATIONAL DESCRIPTION

2. Overall Block Diagram--S5L5008(2CH)

1) 2CH

OVERALL BLOCK DIAGRAM
		SDRAM 3.3V
PLAYER
		3.3V
DVD-
		3.3V
S5L5008

DISC

CON5 UART Download				UART_RXD,TXD
IC104 16BIT32M SDRAM		MMSD416T216		MDA[00:11] DCLK CKE BA0 BA1 DQM NDWE NCAS
				MDB[00:15]
Q100	C108,D100			NSYS_RESET
IC101 29LV800 8M		FLASHROM		FDB[0:7]	1.2V/3.3V
				NSWE
				NSCSO
				NSOE
				FDA[0:20]

CD/DVD_SW,VR_CD,VR_DVD

PD,PREF

CD : A,B,C,D,E,F,RF

DVD : A,B,C,D,RF

SLED(FEEDING)MOTORM PICKUP

DECKMECHANISM

U1

2399

ECHO

MIC

U2

4558 AMP

MIC

+12V

R

L/R

12V

IC304

4558

-OPAMP

L

MUTE

+-

AL,AR

SPDF_R

Y C

Y C

R/Pr G/Y B/Pb

Q5~Q9,Q15 VIDEOBUFFER

R/PrG/Y B/Pb

CVBS

CVBS

IC100 S5L5008SAMSUNG

RF+MPEGIC

27MHz

RGB SW MODE1 MODE2

U1 6928

InputKEY

BOARD

REMOTE

IR

VSDA

VSCK

FRONT CONTROL

LED DISPLAY

CD/DVD

+5V

SPDSENSE SSTOP

OPENSW,CLOSE SW

CLOSE,SLDOPEN, PWM,FOD PWM,TRD,DRSPD MUTE,VREF

TRB2 TRB1

-12V

+12V

D5V POWER

1.2V

3.3V

BOARDD5V

Q13

TRK[+,-]

Q14

FCS[+,-]

SPN[+,-]

IC1 AT5669 DriveMotor

SLD[+,-]

90V~240VAC 50HZ/60Hz

LOAD[+,-]

CIRCUIT OPERATIONAL DESCRIPTION

3. MPEG Decoder

The signal read from DVD disc is output into the RF signal and Servo related signal through the RF IC and they are input into the MPEG decoder and processed the MPEG decoding and divided into video/audio signal. The video signal is output into the analog audio signal through the built-in encoder block and also the audio signal into the audio DAC through the audio decoder block.

MPEG decoder consists of existing MPEG-2 decoder and single chip combined the digital signal processing part which is the core technology of DVD player with the Servo controller.

1) DVD Servo And MPEG-2 Decoder : S5L5008

SAMSUNG S5L5008 DVD SoC is designed to provide a cost-effective, low power size and high performance DVD players solution for DVD-Video, DVD-Audio & many of CD applications. To reduce total system cost, S5L5008 also providesthe following features: a Optical RF,a front-end controller, a back-end decoder, a control CPU with separate 4KB Instruction and 4KB Data Cache, an improved audio DSP, a programmable video encoder with a dual output capability of interlaced and progressive scan, Memory controller, 4-channel Timers with PWM, I/O Ports, 1-channel 10-bit ADCsfor Servo control, 5-channel 10-bitVideo-DACs, 1-channel UART with handshake, IIC-BUS interface, IISBUS interface, SIO, 6-in-1 Card Interface, SPDIF in/out, Audio PWM outand PLL for clock generation.

The S5L5008 is fabricated in a standard 0.13um CMOS technology. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and powersensitive applications.

The S5L5008 is built around the outstanding CPU core: The ARM946E-S cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on- a-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM946E-S executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software.

CIRCUIT OPERATIONAL DESCRIPTION

OPU			AFE
Motor/			Servo/DP
Driver

MPEG

Stream

DEMUX

Decoder

CSS

Device Drive		ATAPI

16Mb SDR

4Mb Flash

16

8

MIU/Arbiter

Interface

ARM946E-S

BUS

(processor core)

4KB

4KB

I-cache

D-cache

AHBs

AHBsbit-32

InterfaceBUS

32-bit

CalmADM

( Audio DSP )

8KB

12KB

I-cache

D-cache

DRAM 5Mbit

Bus

Bridge

CCIR656

2D Graphic

Interface

Engine(GA)

OSD/Mixer

NTSC

Video

/PAL

5-DAC

Encoder

Video

Video

Output

Proces

( Scaling

Sub-pict

Decoder

MPEG

Audio

Video

Interface

Decoder

I2S_Out

Reverse

(5x)

I2S_In

playback

APB

SPDIF OUT

32-bit

SPDIF IN

Audio PWM

32-bit APB

Audio

DACs

Mic

SPDIF

Slave

SPDIF

Master

Audio

AMP

16 bit Timers

JTAG

PLLs

CLKRST GEN

SPI

I2C

IR

UART

WDT

GPIO

Debugger

XTL

Host IF/VFD

EPROM

RemoCon

PC debugger

Ext INT/ User IF

S5L5008 Block Diagram

CIRCUIT OPERATIONAL DESCRIPTION

P/U

Deck Mechanism

Display

S5L5008X(DVDP SOC)

IR

Key

Display

CPU + RF + Servo/DSP +

2-Ch DAC

Front VFD Display

A/V Decoder + DRAM

(SPI Interface)

5.1-Ch

DAC

Audio

AMP

SDRAM

Flash ROM

Peripherals

S5L5008 System Diagram(Servo Application)

DISC

VREF(1.65V)

Pick Up

FOD

TRD

LDODVD

MotorControl

SLDPWM

SPDPWM

PDDVD

FAN8026

FEU

MON(Idle)

LDOCD

PLLDFT

SERVO

A1

ENV

B1

ABCD

ENV

C1

TE

ABCD(RFO)

FE

TE

D1

E

MIRR

FE

F

FOKB

DFCT

MIRR

RFSUM

RF

DP

REFEQ

A

Maindata

B

C

D

ADC

EFM

Equalize

PLCK

Viterbi

Decode

Command

SDRAM

S5L5008 Servo Control Flow

CIRCUIT OPERATIONAL DESCRIPTION

216 FDA12(P5.3) 215 FDA13(P5.2) 214 FDA14(P5.4) 213 FDA15(P5.5) 212 FDA16(P5.6) 211 FDA19(P6.1) 210 VSSP9 209 VDDP8 208 EDRVSSA 207 EDRVCCA12 204 EDRVSSQ 205 EDRVPP33V 204 EDRVSSP 203 EDRVSSP12 202 FDB7(P7.1) 201 FDB6(P7.0) 200 FDB5(P6.7) 199 FDB4(P6.6) 198 FDB3(P6.5) 197 FDB2(P6.4) 196 FDB1(P6.3) 195 FDB0(P6.2) 194 NSOE 193 NSWE 192 NSCS0 191 FDA0(P3.6) 190 VSSC6 189 VDDC6 188 VSSP8 187 VDDP7 186 RXD(P3.5) 185 TXD(P3.4) 184 VSSC5 183 VDDC5 182 SPICLK(P3.3) 181 MISO(P3.2) 180 MOSO(P3.1) 179 IRIN(P3.0) 178 TDIADM(P1.6) 177 TCKDAM(P1.5) 176 TMSADM(P1.4) 175 NTRSTADM(P1.3) 174 NRESET 173 SPDP 172 SLDP 171 VSSSVO33A 170 TEO 169 FEO 168 TZCI 167 TE 166 VREF 165 RBIAS 164 PREF 163 FCB

FDA11(P5.1) 1 FDA10(P5.0) 2 FDA9(P4.7) 3 FDA8(P4.6) 4 FDA18(P6.0) 5 FDA17(P5.7) 6 FDA7(P4.5) 7 FDA6(P4.4) 8

VDDP0 9

VSSP0 10 FDA5(P4.3) 11 FDA4(P4.2) 12 FDA3(P4.1) 13 FDA2(P4.0) 14 FDA1(P3.7) 15

MDA4 16

VSSP1 17

MDA3 18

VDDC0 19

VSSC0 20

MDA5 21

MDA2 22

MDA6 23

MDA1 24

VDDP1 25

MDA7 26

MDA0 27

VSSP2 28

MDA8 29

MDA10 30

MDA9 31

MDA11 32 BA0 33 BA1_NDCS1 34 VDDP2 35 NDCS0 36 VSSP3 37 NRAS 38 DCLK 39 NCAS 40 VDDC1 41 VSSC1 42 NDWE 43 DQM 44 MDBB 45 VDDP3 46 MDB7 47 VSSP4 48 MDB9 49 MDB6 50 MDB10 51 MDB5 52 MDB11 53 MDB4 54

S5L5008

55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99	100 101 102 103 104 105 106 107	108
MDB12 VDDP4 VSSP5 MDB3 MDB13 MDB2 MDB14 MDB1 MDB15 VDDC2 VSSC2 MDB0 VSSP6 NTPST(P0.0) VDD5 VDDC3 VSSC3 TDI(P0.1) TCK(P0.2) TMS(P0.3) TDO(P0.4) HSYNC(P0.5) VSYNC(P0.6) BTCLK(P0.7) DACVDD33R VREFOUT CCOMP IRESET DACVSS33R DACVBB33A DAC0 DAC1 DAC2 DACVSS33A DACVDD33A DAC3 DAC4 DACVDD33D DACVSS33D PWMVSS3 I2SDO4(P2.4) I2SDO3(P2.3) PWMVDD33 I2SDO2(P2.2) I2SDO1(P2.1)
	I2SDO0(P2.0) VDDC4 VSSC4 I2SMCLK(P2.5) I2SWSO(P2.6) 12SBCKO(P2.7) I2CCK(P1.1) I2CDAT(P1.2) I2SDI(P1.0)

162	MPEI
161	ABCDO
160	MPEO
159	MCB
158	MCP
157	VDDSVO33A
156	PDDVD
155	LDOCD
154	LDODVD
153	F
152	E
151	D
150	C
149	B
148	A
147	D1
146	C1
145	B1
144	A1
143	MIRRI
142	ABCDI
141	RFSUM
140	VSSEQ33A
139	RFAGC0
138	AGCP
137	AGCB
136	AGCACN
135	AGCACP
134	AGCC
133	RFEQ0
132	VDDEQ33A
131	EFMI
130	VDDPLS33A
129	VSSPLS33A
128	MCHL
127	MCHR
126	ADCVDD33A
125	ADCVSS33A
124	DPLLVSS12A
123	LFCDPLL
122	LFDVDPLL
121	VCTLCD
120	VCTLDVD
119	DPLLVDD12A
118	PLLVDD12
117	PLL1FLT
116	PLL1VSS12
115	PLL0VDD12
114	PLL0FLT
113	PLL0VSS12
112	XI
111	XO
110	VSSP7
109	VDDP6

S5L5008 Pin Assignments (216-QFP)

CIRCUIT OPERATIONAL DESCRIPTION

2) Flash Memory : ES29LV800DB-70TG

Description

The ES29LV800 is a 8 megabit, 3.0 volt-only flash memory device, organized as 1M x 8 bits (Byte mode) or 512K x 16 bits (Word mode) which is configurable by BYTE#. Four boot sectors and fifteen main sectors are provided : 16Kbytes x 1, 8Kbytes x 2, 32Kbytes x 1 and 64Kbytes x 15. The device is manufactured with ESI’s proprietary, high performance and highly reliable 0.18um CMOS flash technology. The device can be programmed or erased in-system with standard 3.0 Volt Vcc supply ( 2.7V-3.6V) and can also be programmed in standard EPROM programmers. The device offers minimum endurance of 100,000 program/erase cycles and more than 10 years of data retention.

The ES29LV800 offers access time as fast as 70ns or 90ns, allowing operation of highspeed microprocessors without wait states. Three separate control pins are provided to eliminate bus contention : chip enable (CE#), write enable (WE#) and output enable (OE#).

All program and erase operation are automatically and internally performed and controlled by embedded program/erase algorithms built in the device. The device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verification, and counts the number of sequences. Some status bits (DQ7, DQ6 and DQ5) read by data# polling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed.

The ES29LV800 is completely compatible with the JEDEC standard command set of single power supply Flash. Commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other EPROM or flash devices.

10

CIRCUIT OPERATIONAL DESCRIPTION

		RY/BY#
	Vcc	Vcc Detector	Timer/		DQ0-DQ15(A-1)
	Vss		Counter
			Analog Bias
			Generator		Input/Output
	WE#	Command	Write		Buffers
		Register	State
	RESET#		Machine
					Data Latch/
			Sector Switches		Sense Amps
				Y-Decoder	Y-Decoder
	A<0:18>
	CE#		Latch	X-Decoder	Cell Array
		Chip Enable	Address
	OE#
		Output Enable
	BYTE#	Logic

FLASH ES29LV800 Block Diagram

A15 1

A14 2

A13 3

A12 4

A11 5

A10 6

A9 7

A8 8

NC 9

NC 10

WE# 11 RESET# 12 NC 13 NC 14

RY/BY# 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24

48-Pin Standard TSOP

ES29LV800

48		A16
47		BYTE#
46		Vss
45		DQ15/A-1
44		DQ7
43		DQ14
42		DQ6
41		DQ13
40		DQ5
39		DQ12
38		DQ4
37		Vcc
36		DQ11
35		DQ3
34		DQ10
33		DQ2
32		DQ9
31		DQ1
30		DQ8
29		DQ0
28		OE#
27		Vss
26		CE#
25		A0

FLASH ES29LV800 Pin Assignments

11

CIRCUIT OPERATIONAL DESCRIPTION

3) SDRAM : MMSD416T216-O

SDROM MMSD416T216-O Pin Assignments

12

CIRCUIT OPERATIONAL DESCRIPTION

4) AMPLIFIERS : AZ4558CM-E1

Description

The AZ4558 consists of two high performance operational amplifiers. The IC features high gain, high input resistance, excellent channel separation, wide range of operating voltage and internal frequency compensation. It can work with ± 18V maximum power supply voltage.

The AZ4558 is specifically suitable for applications in differential-in, differential-out as well as in potentialmetric amplifiers and where gain and phase matched channels are mandatory.

The AZ4558 is available in DIP-8 and SOIC-8 pack-age.

		3.1 KΩ			VCC
					150 Ω
	- Input
	+ Input				25 Ω
					Output
					25 Ω
					10pF
		87
	7.1	pF
		7.1	480 Ω	4.2 KΩ	36 KΩ
	KΩ	KΩ
					VEE

AMPLIFIERS AZ4558CM-E1 Block Diagram

M Package/P Package

(SOIC-8/DIP-8)

OUTPUT 1			1	8		VCC
INPUT 1-			2	7		OUTPUT 2
INPUT 1+			3	6		INPUT 2-
VEE			4	5		INPUT 2+

Top View

AMPLIFIERS AZ4558CM-E1 Pin Assignments

13

CIRCUIT OPERATIONAL DESCRIPTION

5) Motor Drive IC: AT5669

The AT5669 is a 5-channel BTL driver IC. Two of them can drive DC motors and two can drive coils, such as the focus and tracking actuators of a CD-ROM/DVD-ROM/DVD-Player system It also built-in one channel bi-direction DC motor driver for Tray. Using the built-in linear regulator, it can be save the PCB space. It also includes 1 comparator.

Motor Drive IC (AT5669) Block Diagram

14