Compal LA-8864P QMLE4 Eureka UMA, NP355V4C, NP355V5C, LA-8864P QMLE5 Eureka UMA Schematic
A
1 1
B
C
D
E
QMLE4/5
2 2
Eureka UMA
LA-8864P SchematicREV 0.3
3 3
4 4
AMD Trinity FS1r2 APU / Hudson M3 FCH
2012-03-14 Rev 0.3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
140Monday, March 26, 2012
140Monday, March 26, 2012
140Monday, March 26, 2012
E
A
A
A
of
of
of
A
B
C
D
E
RPM Fan Control
AMD APU
HDMI Conn.
1 1
page 20
DP2 (X4)
LVDS Translator
RTD2136S
page 17
LVDS Conn.
page 18
2 2
CRT
page 19
FS1r2 Processor
Trinity uPGA-722
page 5,6,7,8,9
DP0
(X2)
PCIe X1
1.2V 5GT/s
35mm*35mm
DP1
(X4)
UMI X4
2.5GT/s
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1333/1600 MT/s
PCIe X1
1.2V 5GT/s
USB2.0
5V 480MHz
USB2.0
5V 480MHz
page 5
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Right USB2.0 Right USB2.0
USB port 0
page 21
Left USB 3.0
USB port 10
page 24
USB port 1
page 21
Left USB 3.0
USB port 11
page 24
PCIeMini Card
WLAN + BT
USB port 3
APU PCIe port 1
page 22
GCLK
SLG3NB238VTR
page 10,11
Int. Camera
USB port 4
page 18
page 22
AMD FCH
RJ45
page 23
3 3
RTL8111E 1G
APU PCIe port 0
Cardreader Conn.
RTS5129
page 23
USB port 2
page 26
USB2.0
5V 480MHz
SPI Bus
3.3V 33 MHz
RTL8105E 10/100M
Hudson M3
FCBGA-656
24.5mm*24.5mm
page 12,13,14,15,16
LPC Bus
3.3V 33 MHz
HD Audio
SATA port 0
5V 6GHz(600MB/s)
SATA port 1
5V 6GHz(600MB/s)
USB 3.0
5GHz
USB 3.0
5GHz
3.3V 24MHz
SATA HDD
SATA port 0
page 21
SATA ODD
SATA port 1
page 21
USB 3.0
USB 3.0
USB3.0 port 0
page 24
USB3.0 port 1
page 24
HDA Codec
SPI ROM
(4MB)
page 14
RTC CKT.
page 12
ODD/B
DC/DC Interface CKT.
page 30
4 4
Power Circuit DC/DC
page 31,32,33,34,35
36,37,38,39
LS-8862P
Touchpad/B
LS-8863P
CR & Audio/B
LS-8864P
Power On/Off CKT.
page 29
A
USB & PWR/B
LS-8865P
page 21
page 29
page 40
page 31
B
Debug Port
page 28
ENE KB9012
Touch Pad
page 29
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
page 27
TPM 1.2
page 26
Int.KBD
page 28
Compal Secret Data
Compal Secret Data
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
MIC Conn
page 18
ALC259
page 25
SPK ConnInt.
page 25
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
JCRIO
(HP & MIC)
page 26
240Monday, March 26, 2012
240Monday, March 26, 2012
240Monday, March 26, 2012
E
of
of
of
A
A
A
5
4
3
2
1
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A
+3VL
+5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A
D D
SUSP
N-CHANNEL
SI4800
ODD_PWR
P-CHANNEL
AO-3413
DESIGN CURRENT 7A
DESIGN CURRENT 6A
DESIGN CURRENT 1.6A
+5VALW
+5VS
+5VS_ODD
RT8205LZQW
Ipeak=5A, Imax=3.5A, Iocp min=7.7A
WOL_EN#
P-CHANNEL
SUSP
AO-3413
N-CHANNEL
SI4800
C C
LCD_ENVDD
P-CHANNEL
AO-3413
+3VS
LDO
APL5508-25DC
FCH_PWR_EN
SY8036LDBC
Ipeak=5.3A, Imax=3.71A, Iocp min=6.814A
SUSP
N-CHANNEL
VR_ON
B B
ISL6277HRTZ-T
Ipeak=54A, Imax=36A, Iocp min=65A
Ipeak=27.5A, Imax=22A, Iocp min=35A
FDS6676AS
DESIGN CURRENT 5A
DESIGN CURRENT 330mA
DESIGN CURRENT 4A
DESIGN CURRENT 1.5A
DESIGN CURRENT 1A
DESIGN CURRENT 4A
DESIGN CURRENT 4A
DESIGN CURRENT 36A
DESIGN CURRENT 25A
+3VALW
+3V_LAN
+3VS
+LCD_VDD
+2.5VS
+1.1VALW
+1.1VS
+APU_CORE
+APU_CORE_NB
VR_ON
TPS51212DSCR
Ipeak=6.5A, Imax=4.55A, Iocp min=8.553A
DESIGN CURRENT 8.5A
+1.2VS
SYSON
Ipeak=20A, Imax=11.2A, Iocp min=24.136A
RT8207MZQW
SUSP#
A A
5
4
SUSP
N-CHANNEL
FDS6676AS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DESIGN CURRENT 12A
DESIGN CURRENT 1A
DESIGN CURRENT 1A
Compal Secret Data
Compal Secret Data
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
3
Compal Secret Data
+1.5V
+1.5VS
+0.75VS
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
340Monday, March 26, 2012
340Monday, March 26, 2012
340Monday, March 26, 2012
1
A
A
A
of
of
of
A
B
C
D
E
Voltage Rails
State
S0
S1
S3
S5 S4/AC
power
plane
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
B+
O
O
O
O
O
X
VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+1.1VALW
+VSB
O
O
O
O
X
X
+1.5V
+5VS
+3VS
+2.5VS
+1.5VS
+1.2VS
+1.1VS
+0.75VS
+APU_CORE
+APU_CORE_NB
OO
OO
O
X
XX
X
X
XX
BTO Option Table
Function
description
explain
BTO
Function
description
explain
BTO
R1
HUDM3R1@
10/100M GIGA
8105ELDO@
FCH
Hudson-M3
R3
HUDM3R3@
LAN
LAN
8111FVB@
UNBW
HUDM3UNBW@
Camera
Camera
Camera
CAM@
Clock
Clock
Green Clock
GCLK@ NOGCLK@
Internal Analog MIC
Internal Analog MIC
Internal Analog MIC
AMIC@
No Green Clock
TPM
TPM
9635 9655
TPM9635@
TPM9655@
FCH SM Bus Address (SCL0/SDA0)
HEX
Power
3 3
+3VS
+3VS
+3VS
Device
DDR SO-DIMM 0
DDR SO-DIMM 1
WLAN
EC SM Bus1 Address
Power
+3VL
+3VL
Device Address
Charger 12 H 0001 0010 b
HEX
16 H
EC SM Bus2 Address
4 4
+3VL
DevicePower
SB-TSI
A
HEX Address
98 H
Address
1010 000X bA0 H
1010 001X bA2 H
0001 0110 bSmart Battery
1001 1001 b
+3VS
EC SM Bus3 Address
HEX AddressDevicePower
94 H
1001 0100 bLVDS Translator
B
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G3 LOW LOW
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SIGNAL
D
SLP_S3#
HIGH HIGH
LOW
LOW
SLP_S5#
HIGHHIGH
HIGH
HIGH
LOWLOW
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
440Monday, March 26, 2012
440Monday, March 26, 2012
440Monday, March 26, 2012
E
A
A
A
of
of
of
A
JAPUA
JAPUA
AB8
AB7
AA9
AA8
AA5
1 1
LAN
WLAN
2 2
PCIE_FRX_C_LANTX_P0<23>
PCIE_FRX_C_LANTX_N0<23> PCIE_FTX_C_LANRX_N0 <23>
PCIE_FRX_WLANTX_P1<22>
PCIE_FRX_WLANTX_N1<22>
UMI_MTX_C_FRX_P0<12>
UMI_MTX_C_FRX_N0<12>
UMI_MTX_C_FRX_P1<12>
UMI_MTX_C_FRX_N1<12>
UMI_MTX_C_FRX_P2<12>
UMI_MTX_C_FRX_N2<12>
UMI_MTX_C_FRX_P3<12>
UMI_MTX_C_FRX_N3<12>
+1.2VS
PCIE_FRX_C_LANTX_P0
PCIE_FRX_C_LANTX_N0
PCIE_FRX_WLANTX_P1
PCIE_FRX_WLANTX_N1
UMI_MTX_C_FRX_P0
UMI_MTX_C_FRX_N0
UMI_MTX_C_FRX_P1
UMI_MTX_C_FRX_N1
UMI_MTX_C_FRX_P2
UMI_MTX_C_FRX_N2
UMI_MTX_C_FRX_P3
UMI_MTX_C_FRX_N3
1 2
R1 196_0402_1%R1 196_0402_1%
AA6
Y8
Y7
W9
W8
W5
W6
V8
V7
U9
U8
U5
U6
T8
T7
R9
R8
R5
R6
P8
P7
N9
N8
N5
N6
M8
M7
AE5
AE6
AD8
AD7
AC9
AC8
AC5
AC6
AG8
AG9
AG6
AG5
AF7
AF8
AE8
AE9
P_ZVDDP P_ZVSS
AG11
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
PCI EXPRESS
PCI EXPRESS
GPP GRAPHICS
GPP GRAPHICS
UMI
UMI
B
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
AB2
AB1
AA3
AA2
Y5
Y4
Y2
Y1
W3
W2
V5
V4
V2
V1
U3
U2
T5
T4
T2
T1
R3
R2
P5
P4
P2
P1
N3
N2
M5
M4
M2
M1
PCIE_FTX_LANRX_P0
AD5
PCIE_FTX_LANRX_N0
AD4
PCIE_FTX_WLANRX_P1
AD2
PCIE_FTX_WLANRX_N1
AD1
AC3
AC2
AB5
AB4
UMI_FTX_MRX_P0
AG2
UMI_FTX_MRX_N0
AG3
UMI_FTX_MRX_P1
AF4
UMI_FTX_MRX_N1
AF5
UMI_FTX_MRX_P2
AF1
UMI_FTX_MRX_N2
AF2
UMI_FTX_MRX_P3
AE2
UMI_FTX_MRX_N3
AE3
AH11
C50 0.1U_0402_16V7KC50 0.1U_0402_16V7K
C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K
C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K
C54 0.1U_0402_16V7KC54 0.1U_0402_16V7K
C59 0.1U_0402_16V7KC59 0.1U_0402_16V7K
C60 0.1U_0402_16V7KC60 0.1U_0402_16V7K
C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K
C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K
C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K
C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K
C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K
C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K
1 2
R2 196_0402_1%R2 196_0402_1%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C
PCIE_FTX_C_LANRX_P0 <23>
PCIE_FTX_C_WLANRX_P1 <22>
PCIE_FTX_C_WLANRX_N1 <22>
UMI_FTX_C_MRX_P0 <12>
UMI_FTX_C_MRX_N0 <12>
UMI_FTX_C_MRX_P1 <12>
UMI_FTX_C_MRX_N1 <12>
UMI_FTX_C_MRX_P2 <12>
UMI_FTX_C_MRX_N2 <12>
UMI_FTX_C_MRX_P3 <12>
UMI_FTX_C_MRX_N3 <12>
LAN
WLAN
D
E
3 3
FAN Control Circuit
+5VS
1A
C13
C13
10U_0603_6.3V6M
10U_0603_6.3V6M
U2
U2
1
EN
2
EN_DFAN1<27>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
+FAN
10mil
Deciphered Date
Deciphered Date
Deciphered Date
3
4
1
C17
C17
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
10U_0603_6.3V6M
10U_0603_6.3V6M
2
D
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
+FAN
2
2
C15
C15
1000P_0402_50V7K
1000P_0402_50V7K
@
@
1
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
1
2
3
4
5
ACES_85204-0300N
ACES_85204-0300N
R59 10K_0402_5%R59 10K_0402_5%
1
C14
C14
0.01U_0402_25V7K
0.01U_0402_25V7K
@
@
2
4019IS
4019IS
4019IS
E
JFAN
1
2
3
GND
GND
12
@JFAN
@
+3VS
FAN_SPEED1 <27>
540Monday, March 26, 2012
540Monday, March 26, 2012
540Monday, March 26, 2012
A
A
A
of
of
of
A
B
C
D
E
DDR_A_DQS[0..7]<10>
DDR_A_DQS#[0..7]<10>
1 1
JAPUB
JAPUB
MEMORY CHANNEL A
DDR_A_MA[0..15]<10>
DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>
DDR_A_DM[0..7]<10>
2 2
DDR_A_CLK0<10>
DDR_A_CLK0#<10>
DDR_A_CLK1<10>
DDR_A_CLK1#<10>
DDR_A_CKE0<10>
DDR_A_CKE1<10>
DDR_A_ODT0<10>
DDR_A_ODT1<10>
3 3
DDR_A_SCS0#<10>
DDR_A_SCS1#<10>
DDR_A_RAS#<10>
DDR_A_CAS#<10>
DDR_A_WE#<10>
MEM_MA_RST#<10>
MEM_MA_EVENT#<10>
+1.5V
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_CKE0
DDR_A_CKE1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_SCS0#
DDR_A_SCS1#
DDR_A_RAS#
DDR_A_CAS#
MEM_MA_RST#
MEM_MA_EVENT#
15mil
+MEM_VREF
M_ZVDDIO
1 2
R60 39.2_0402_1%R60 39.2_0402_1%
M21
M22
AA25
AD27
AC23
AD19
AC15
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15
AA27
AA26
W24
W23
W20
W21
U20
R20
R21
P22
P21
N24
N23
N20
N21
U23
L24
L21
L20
U24
U21
L23
E14
J17
E21
F25
G14
H14
G18
H18
J21
H21
E27
E26
T21
T22
R23
R24
H28
H27
Y25
V22
V21
H25
T24
MEMORY CHANNEL A
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CKE0
MA_CKE1
MA_ODT0
MA_ODT1
MA_CS_L0
MA_CS_L1
MA_RAS_L
MA_CAS_L
MA_WE_L
MA_RESET_L
MA_EVENT_L
M_VREF
M_ZVDDIO
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56DDR_A_WE#
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] <10>
DDR_B_DQS[0..7]<11>
DDR_B_DQS#[0..7]<11>
JAPUC
JAPUC
MEMORY CHANNEL B
DDR_B_MA[0..15]<11>
DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>
DDR_B_DM[0..7]<11>
DDR_B_CLK0<11>
DDR_B_CLK0#<11>
DDR_B_CLK1<11>
DDR_B_CLK1#<11>
DDR_B_CKE0<11>
DDR_B_CKE1<11>
DDR_B_ODT0<11>
DDR_B_ODT1<11>
DDR_B_SCS0#<11>
DDR_B_SCS1#<11>
DDR_B_RAS#<11>
DDR_B_CAS#<11>
DDR_B_WE#<11>
MEM_MB_RST#<11>
MEM_MB_EVENT#<11>
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_CKE0
DDR_B_CKE1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_SCS0#
DDR_B_SCS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
MEM_MB_RST#
MEM_MB_EVENT#
M28
M27
M24
M25
W26
AF25
AG22
AH18
AD14
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
W27
T27
P24
P25
N27
N26
L26
U26
L27
K27
K25
K24
U27
T28
K28
D14
A18
A22
C25
C15
B15
E18
D18
E22
D22
B26
A26
R26
R27
P27
P28
J26
J27
Y28
V25
Y27
V24
V27
V28
J25
T25
MEMORY CHANNEL B
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <11>
EVENT# pull high 0.75V Reference Voltage
+1.5V
4 4
R15 1K_0402_5%R15 1K_0402_5%
1 2
R61 1K_0402_5%R61 1K_0402_5%
1 2
MEM_MA_EVENT#
MEM_MB_EVENT#
A
R64
R64
1K_0402_1%
1K_0402_1%
R65
R65
1K_0402_1%
1K_0402_1%
+1.5V
1 2
1 2
B
1
C124
C124
1000P_0402_50V7K
1000P_0402_50V7K
2
15mil
+MEM_VREF
2
C125
C125
0.1U_0402_16V7K
0.1U_0402_16V7K
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/11/11 2011/11/11
2010/11/11 2011/11/11
2010/11/11 2011/11/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
640Monday, March 26, 2012
640Monday, March 26, 2012
640Monday, March 26, 2012
E
of
of
of
A
A
A
A
Close to APU
C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K
DP0_TXP0_C<17>
LVDS
1 1
CRT
(To FCH)
HDMI
DP0_TXN0_C<17>
DP0_TXP1_C<17>
DP0_TXN1_C<17>
ML_VGA_TXP0<14>
ML_VGA_TXN0<14>
ML_VGA_TXP1<14>
ML_VGA_TXN1<14>
ML_VGA_TXP2<14>
ML_VGA_TXN2<14>
ML_VGA_TXP3<14>
ML_VGA_TXN3<14>
UMA_HDMI_TX2+<20>
UMA_HDMI_TX2-<20>
UMA_HDMI_TX1+<20>
UMA_HDMI_TX1-<20>
UMA_HDMI_TX0+<20>
UMA_HDMI_TX0-<20>
UMA_HDMI_TXC+<20>
UMA_HDMI_TXC-<20>
100MHz (SS)
100MHz (NSS)
APU_SVC<37>
2 2
APU_SVD<37>
APU_SVT<37>
SB-TSI
APU_VDD_RUN_FB_L<37>
APU_VDDNB_SEN<37>
APU_VDD_SEN<37>
3 3
1 2
C48 0.1U_0402_16V7KC48 0.1U_0402_16V7K
1 2
C58 0.1U_0402_16V7KC58 0.1U_0402_16V7K
1 2
C53 0.1U_0402_16V7KC53 0.1U_0402_16V7K
1 2
C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K
1 2
C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K
1 2
C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K
1 2
C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K
1 2
C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K
1 2
C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K
1 2
C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K
1 2
C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K
1 2
APU_CLKP<12>
APU_CLKN<12>
APU_DISP_CLKP<12>
APU_DISP_CLKN<12>
R31 0_0402_5%@R31 0_0402_5%@
1 2
R32 0_0402_5%@R32 0_0402_5%@
1 2
R33 0_0402_5%@R33 0_0402_5%@
1 2
APU_SIC<9>
APU_SID<9>
APU_RST#<12>
APU_PWRGD<12,37>
APU_ALERT#<14>
R212 0_0402_5%R212 0_0402_5%
1 2
R214 0_0402_5%R214 0_0402_5%
1 2
R215 0_0402_5%R215 0_0402_5%
1 2
APU_PROCHOT#
APU_THERMTRIP#
APU_ALERT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
T9T9
T10T10
T13T13
UMA_HDMI_TX2+
UMA_HDMI_TX2-
UMA_HDMI_TX1+
UMA_HDMI_TX1-
UMA_HDMI_TX0+
UMA_HDMI_TX0-
UMA_HDMI_TXC+
UMA_HDMI_TXC-
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SVC_R
APU_SVD_R
APU_SVT_R
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
VSS_SENSE
VDDNB_SENSE
VDD_SENSE
DP0_TXP0
DP0_TXN0
DP0_TXN1
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
B
JAPUD
JAPUD
ANALOG/DISPLAY/MISC
ANALOG/DISPLAY/MISC
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
DP2_TXP0
DP2_TXN0
DP2_TXP1
DP2_TXN1
DP2_TXP2
DP2_TXN2
DP2_TXP3
DP2_TXN3
CLKIN_H
CLKIN_L
DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD
SVT
SIC
SID
RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
LOTES_ACA-ZIF-109-P12-A_FS1R2 @
DISPLAY PORT 0
DISPLAY PORT 0
DISPLAY PORT MISC.
DISPLAY PORT MISC.
DISPLAY PORT 2 DISPLAY PORT 1
DISPLAY PORT 2 DISPLAY PORT 1
TEST
TEST
CTRL SER. CLK
CTRL SER. CLK
JTAG
JTAG
SENSE
SENSE
AE11
AD11
AB11
AA11
AG12
AH12
AF10
AB12
AC10
AE12
AF12
L3
L2
K5
K4
K2
K1
J3
J2
H5
H4
H2
H1
G3
G2
F2
F1
L9
L8
L5
L6
K8
K7
J6
J5
B3
A3
C3
H10
J10
F10
G10
F9
G9
H9
B4
C5
A4
A5
C4
B5
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST10
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35
DMAACTIVE_L
RSVD
RSVD
TEST6
TEST9
FS1R2
TEST4
TEST5
RSVD1
RSVD2
RSVD3
RSVD4
DP0_AUXP
D1
DP0_AUXN
D2
DP1_AUXP
E1
DP1_AUXN
E2
UMA_HDMI_CLK
D5
UMA_HDMI_DATA
D6
E5
E6
F5
F6
G5
G6
LVDS_HPD
D3
FCH_CRT_HPD
E3
HDMI_HPD
D7
E7
F7
G7
C6
B6
A6
DP_AUX_ZVSS
C1
AD12
M18
N18
F11
G11
H11
J11
APU_TEST18
F12
APU_TEST19
G12
APU_TEST20
J12
APU_TEST24
H12
TEST25_H
AE10
TEST25_L
AD10
L10
M10
P19
R19
APU_TEST31
K22
T19
N19
APU_TEST35
AA12
FS1R2
W10
DMA_ACTIVE#
AC12
P18
R18
Y10
AA10
Y12
K21
C
C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K
1 2
C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K
1 2
C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K
1 2
C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K
1 2
LVDS_HPD <17>
FCH_CRT_HPD <14>
HDMI_HPD <20>
DP_INT_PWM <9>
1 2
R16 150_0402_1%R16 150_0402_1%
T5T5
T6T6
T1T1
T2T2
T3T3
T4T4
R18 1K_0402_5%R18 1K_0402_5%
1 2
R19 1K_0402_5%R19 1K_0402_5%
1 2
R21 1K_0402_5%R21 1K_0402_5%
1 2
R22 1K_0402_5%R22 1K_0402_5%
1 2
R23 510_0402_1%R23 510_0402_1%
1 2
R24 510_0402_1%R24 510_0402_1%
1 2
T7T7
T8T8
R27 39.2_0402_1%R27 39.2_0402_1%
1 2
R28 300_0402_5%R28 300_0402_5%
1 2
R29 300_0402_5%@R29 300_0402_5%@
1 2
R30 10K_0402_5%R30 10K_0402_5%
1 2
DMA_ACTIVE# <12>
T11T11
T12T12
DP0_AUXP_C <17>
DP0_AUXN_C <17>
ML_VGA_AUXP <14>
ML_VGA_AUXN <14>
UMA_HDMI_CLK <20>
UMA_HDMI_DATA <20>
3.3V Tolerance
+1.2VS
Change TEST35 to pull-high
+1.5V
for HDMI issue
+3VALW
D
LVDS
CRT (To FCH)
HDMI
E
DP0_AUXP
DP0_AUXNDP0_TXP1
DP1_AUXP
DP1_AUXN
LVDS_HPD
FCH_CRT_HPD
HDMI_HPD
APU_SVT_R
APU_SVC_R
APU_SVD_RDP_INT_PWM
APU_SIC
APU_SID
APU_ALERT#
DMA_ACTIVE#
DMA_ACTIVE#
APU_RST#
APU_PWRGD
Stuff C126 and C127 for EMI request on DVT
UMA_HDMI_CLK
UMA_HDMI_DATA
Aux signal are re-configured as I2C signals for DDC
APU AUX pin are 3.3V tolerant
+1.5V +1.5VS
R25 1.8K_0402_5%R25 1.8K_0402_5%
R58 1.8K_0402_5%R58 1.8K_0402_5%
R10 1.8K_0402_5%R10 1.8K_0402_5%
R11 1.8K_0402_5%R11 1.8K_0402_5%
R74 100K_0402_5%R74 100K_0402_5%
R75 100K_0402_5%R75 100K_0402_5%
R95 100K_0402_5%R95 100K_0402_5%
R36 1K_0402_5%@R36 1K_0402_5%@
R39 1K_0402_5%@R39 1K_0402_5%@
R41 1K_0402_5%@R41 1K_0402_5%@
R42 1K_0402_5%R42 1K_0402_5%
R44 1K_0402_5%R44 1K_0402_5%
R46 1K_0402_5%R46 1K_0402_5%
R48 1K_0402_5%R48 1K_0402_5%
R57 1K_0402_5%@R57 1K_0402_5%@
R52 300_0402_5%R52 300_0402_5%
R54 300_0402_5%R54 300_0402_5%
APU_RST#
APU_PWRGD
1 2
C126 1000P_0402_50V7KC126 1000P_0402_50V7K
1 2
C127 1000P_0402_50V7KC127 1000P_0402_50V7K
R66 4.7K_0402_5%R66 4.7K_0402_5%
R67 4.7K_0402_5%R67 4.7K_0402_5%
12
12
12
12
12
12
12
+1.5V
12
12
12
12
12
12
12
+1.5VS
12
12
12
+3VS
12
12
R77
R55
R55
1K_0402_5%
+1.5V
Close to JHDT
R97 1K_0402_5%R97 1K_0402_5%
1 2
R100 1K_0402_5%R100 1K_0402_5%
1 2
R110 1K_0402_5%R110 1K_0402_5%
1 2
R116 1K_0402_5%R116 1K_0402_5%
1 2
R117 1K_0402_5%R117 1K_0402_5%
1 2
4 4
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
@
@
1 2
R121 0_0402_5%
R121 0_0402_5%
@
@
1 2
R122 10K_0402_5%
R122 10K_0402_5%
@
@
1 2
R123 10K_0402_5%
R123 10K_0402_5%
@
@
1 2
R124 10K_0402_5%
R124 10K_0402_5%
A
HDT Debug conn
+1.5V
JHDT
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
SAMTE_ASP-136446-07-B
SAMTE_ASP-136446-07-B
B
@JHDT
@
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_PWRGD_RR
APU_RST#_R
APU_DBRDY
APU_DBREQ#
Close to APU side, Debug Stuff
R125 0_0402_5%
R125 0_0402_5%
R127 0_0402_5%
R127 0_0402_5%
@
@
1 2
R118 0_0402_5%
R118 0_0402_5%
@
@
1 2
R119 0_0402_5%
R119 0_0402_5%
@
@
1 2
@
@
1 2
APU_TEST19
APU_TEST18
Security Classification
Security Classification
Security Classification
APU_PWRGDAPU_TRST#
APU_RST#
2011/11/21 2011/12/11
2011/11/21 2011/12/11
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/11/21 2011/12/11
Asserted as an input to force the
processor into the HTC-active state
APU_PROCHOT#
Thermal Shutdown Temperature:
115 degree
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
APU_THERMTRIP#
1K_0402_5%
@
@
1 2
R136 0_0402_5%
R136 0_0402_5%
+1.5V
R68
R68
1K_0402_5%
1K_0402_5%
12
1 2
B
B
2
E
E
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
R77
1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
H_PROCHOT# <27,37>APU_PROCHOT#<12>
Reserve R77 and R85 for
DeepS3 leakage on DVT
+1.5VS
R69
R69
10K_0402_5%
10K_0402_5%
C
C
12
R85
R85
10K_0402_5%
10K_0402_5%
@
@
Q5
Q5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
H_THERMTRIP# <13>
E
A
A
A
of
of
of
740Monday, March 26, 2012
740Monday, March 26, 2012
740Monday, March 26, 2012
A
+APU_CORE
1 1
2 2
3 3
+2.5VS
FBMA-L11-201209-300LMA30T
FBMA-L11-201209-300LMA30T
4 4
L1
L1
1 2
C165
C165
1
2
C170
C170
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
A
+APU_CORE_NB
+1.2VS
C164
C164
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
12
2
+1.5V
3300P_0402_50V7K
3300P_0402_50V7K
+VDDA+VDDA
40mil
JAPUE
JAPUE
F8
VDD_1
H6
VDD_2
J1
VDD_3
J14
VDD_4
P6
VDD_5
P10
VDD_6
J16
VDD_7
J18
VDD_8
J9
VDD_9
K19
VDD_10
K3
VDD_11
K17
VDD_12
M3
VDD_13
K6
VDD_14
V10
VDD_15
V18
VDD_16
V3
VDD_17
50A
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
33A
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
3.2A
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDA
0.75A
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
AA28
AB10
F3
L18
V6
W1
T18
Y14
AA1
AB6
AC1
R1
P3
K10
H3
M19
C8
D10
B8
B12
C9
A9
A10
A8
A11
E10
E11
C10
H26
K20
J28
K23
K26
L22
L25
L28
M20
M23
M26
N22
N25
N28
P20
P23
P26
AH6
AH5
AH4
AH3
AH7
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23
VDDNB_CAP_1
VDDNB_CAP_2
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDR_1
VDDR_2
VDDR_3
3.5A5A
VDDR_4
C71
C71
+1.2VS
+APU_CORE
R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11
C11
C12
D9
D8
D12
D11
B11
A12
B10
E12
B9
K13
K12
T23
T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28
AG10
AH8
AH9
AH10
@
@
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C72
C72
B
C109
C109
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
B
+APU_CORE_NB
VDDNB_CAP
+1.5V
C110
C110
180P_0402_50V8J
180P_0402_50V8J
1
1
2
2
VDDP Decoupling
C73
C73
C74
C74
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
+1.5V
C81
C81
C80
C80
22U_0805_6.3V6M
22U_0805_6.3V6M
C79
C79
1
2
VDDR Decoupling
C111
C111
C115
C115
1000P_0402_50V7K
1000P_0402_50V7K
180P_0402_50V8J
180P_0402_50V8J
1
1
2
2
C105
C105
C106
C106
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
1
2
2
C
C82
C82
C83
C83
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C116
C116
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
2
C141
C141
180P_0402_50V8J
180P_0402_50V8J
1
2
C76
C76
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C89
C89
C88
C88
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C77
C77
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.2VS
C78
C78
C90
C90
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
2
2
C102
C102
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+1.5V
C92
C92
C91
C91
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
2
2
C103
C103
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C94
C94
C95
C95
C96
C93
C93
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C104
C104
1
1
2
2
C131
C131
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
1
2
2
C96
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
If the VSS plane is cut to
create a VDDIO plane,
place across the VDDIO
and VSS plane split
D
Co-layout with C100 on PVT
+1.5V
1
+
+
C147
C147
330U_D2_2V_Y
330U_D2_2V_Y
@
@
2
C130
C130
C99
C97
C97
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C99
C98
C98
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
1
1
2
2
+
+
C100
C100
330U_2.5V_M_R17
330U_2.5V_M_R17
2
E
JAPUF
JAPUF
J20
VSS_1
L4
VSS_2
R7
VSS_3
W18
VSS_4
A15
VSS_5
AB17
VSS_6
AC22
VSS_7
AE21
VSS_8
AF24
VSS_9
AH23
VSS_10
AH25
VSS_11
B7
VSS_12
C14
VSS_13
C16
VSS_14
C2
VSS_15
C20
VSS_16
C22
VSS_17
C24
VSS_18
C26
VSS_19
C28
VSS_20
D13
VSS_21
D15
VSS_22
D17
VSS_23
D19
VSS_24
D23
VSS_25
D25
VSS_26
D27
VSS_27
E4
VSS_28
E9
VSS_29
F14
VSS_30
F16
VSS_31
F18
VSS_32
F20
VSS_33
F22
VSS_34
F26
VSS_35
F28
VSS_36
G13
VSS_37
G15
VSS_38
G17
VSS_39
G19
VSS_40
G21
VSS_41
G23
VSS_42
G25
VSS_43
G4
VSS_44
J22
VSS_45
J24
VSS_46
J4
VSS_47
J7
VSS_48
K11
VSS_49
K14
VSS_50
K9
VSS_51
AC11
VSS_52
L19
VSS_53
L7
VSS_54
M11
VSS_55
AF11
VSS_56
V19
VSS_57
V9
VSS_58
W16
VSS_59
W4
VSS_60
W7
VSS_61
Y11
VSS_62
Y20
VSS_63
Y22
VSS_64
Y9
VSS_65
A17
VSS_66
A13
VSS_67
K16
VSS_68
F24
VSS_69
G8
VSS_70
H7
VSS_71
J8
VSS_72
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12
@
@
Demo Board Capacitor
CORE_NB_CAP
22uF x 2
180pF x 1
VDDA
4.7uF x 1
0.22uF x 1
3.3nF x 1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
VDDIO_SUS
(CPU side)
22uF x 4
4.7uF x 4
0.22uF x 6 +2(split)
180pF x 1 + 2(split)
VDDIO_SUS
(DIMM x2)
100uF x 2
0.1uF x 12
E
840Monday, March 26, 2012
840Monday, March 26, 2012
840Monday, March 26, 2012
A
A
A
of
of
of
C108
C108
C75
C107
C107
1
2
C75
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1000P_0402_50V7K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1000P_0402_50V7K
1
1
@
@
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
APU_CORE
22uF x 10
0.22uF x 2
0.01uF x 3
180pF x 2
VDDP
0.22uF x 2
180pF x 2
D
CORE_NB
22uF x 2
10uF x 1
0.22uF x 2
180pF x 3
VDDR
0.22uF x 2
1nF x 1
180pF x 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
5
4
3
2
1
SB-TSI
BSH111, the Vgs is:
@
D D
R535
R535
1 2
+3VS
31.6K_0402_1%
31.6K_0402_1%
APU_SID<7>
APU_SIC<7>
C C
BSH111_SOT23-3
BSH111_SOT23-3
APU_SIC
BSH111_SOT23-3
BSH111_SOT23-3
@
C935 0.1U_0402_16V4Z
C935 0.1U_0402_16V4Z
1 2
R536
R536
1 2
30K_0402_1%
30K_0402_1%
Vg = 1.607 V
G
G
2
Q14
Q14
13
D
S
D
S
G
G
2
Q15
Q15
13
D
S
D
S
When APU High -> MOS OFF (Vgs < 0.4V )
APU Low -> MOS ON (Vgs > 1.3V)
EC_SMB_DA2APU_SID
EC_SMB_CK2
min = 0.4V
Max = 1.3V
EC_SMB_DA2 <27>
EC_SMB_CK2 <27>
Panel PWM
+3VS
12
B B
DP_INT_PWM<7>
A A
5
4
1 2
R89 2.2K_0402_5%R89 2.2K_0402_5%
12
R76
R76
4.7K_0402_5%
4.7K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R92
R92
47K_0402_5%
47K_0402_5%
C
C
Q21
Q21
2
B
B
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
E
E
3 1
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
3
12
R93
R93
4.7K_0402_5%
4.7K_0402_5%
61
Q25A
Q25A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
APU_INVT_PWM <17>
Q25B in page30
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
940Monday, March 26, 2012
940Monday, March 26, 2012
940Monday, March 26, 2012
of
of
1
of
A
A
A
5
+VREF_DQA
D D
C C
B B
A A
+3VS
DDR_A_SCS1#<6>
C181
C181
DDR_A_BS2<6>
DDR_A_CLK0<6>
DDR_A_CLK0#<6>
DDR_A_BS0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C182
C182
2
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
R90
R90
1 2
10K_0402_5%
10K_0402_5%
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
+0.75VS
12
R91
R91
10K_0402_5%
10K_0402_5%
+1.5V
JDDR3H
JDDR3H
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
29
DQS1
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
61
VSS22
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0102
LCN_DAN06-K4806-0102
@
@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
BA1
S0#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
+1.5V
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
MEM_MA_RST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_CKE1
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDR_A_SCS0#
DDR_A_ODT0
DDR_A_ODT1
+VREF_CAA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
MEM_MA_EVENT#
FCH_SDATA0
FCH_SCLK0
+0.75VS
4
DDR3 SO-DIMM A
Standard Type
MEM_MA_RST# <6>
DDR_A_CKE1 <6>DDR_A_CKE0<6>
DDR_A_CLK1 <6>
DDR_A_CLK1# <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDR_A_SCS0# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
1
C101
C101
1000P_0402_50V7K
1000P_0402_50V7K
Close to JDDR3H.126
MEM_MA_EVENT# <6>
FCH_SDATA0 <11,13,22>
FCH_SCLK0 <11,13,22>
1
C162
C162
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@
@
1
C161
C161
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
+1.5V
12
1K_0402_1%
1K_0402_1%
12
1K_0402_1%
1K_0402_1%
3
DDR_A_DQS[0..7] <6>
DDR_A_DQS#[0..7] <6>
DDR_A_D[0..63] <6>
DDR_A_MA[0..15] <6>
DDR_A_DM[0..7] <6>
+VREF_DQA
1
C156
C156
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C157
C157
@
@
2
C114
C114
1000P_0402_50V7K
1000P_0402_50V7K
Close to JDDRH.1
Co-layout with C218 on PVT
+1.5V
1
+
+
C148
C148
330U_D2_2V_Y
R80
R80
330U_D2_2V_Y
2
Change C218 to SF000002080 (330U) on DVT
R82
R82
Layout Note:
Place near JDDRH
+1.5V
Compal Secret Data
Compal Secret Data
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
@
@
+
+
C218 330U_6.3V_M_R15
C218 330U_6.3V_M_R15
1 2
C166 0.1U_0402_16V4ZC166 0.1U_0402_16V4Z
1 2
C168 0.1U_0402_16V4ZC168 0.1U_0402_16V4Z
1 2
C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z
1 2
C174 0.1U_0402_16V4ZC174 0.1U_0402_16V4Z
1 2
C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z
1 2
C176 0.1U_0402_16V4ZC176 0.1U_0402_16V4Z
1 2
C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z
1 2
C178 0.1U_0402_16V4ZC178 0.1U_0402_16V4Z
1 2
C185 0.1U_0402_16V4ZC185 0.1U_0402_16V4Z
1 2
C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z
1 2
+1.5V
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
12
R79
R79
1K_0402_1%
1K_0402_1%
12
R81
R81
1K_0402_1%
1K_0402_1%
2
1
Layout Note:
Place near JDDRH.203 and 204
+0.75VS
@
@
C85 0.1U_0402_16V4Z
C85 0.1U_0402_16V4Z
1 2
C84 4.7U_0603_6.3V6KC84 4.7U_0603_6.3V6K
1 2
C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z
1 2
C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
+1.5V
of
of
of
10 40Monday, March 26, 2012
10 40Monday, March 26, 2012
10 40Monday, March 26, 2012
1
A
A
A
A
JDDR3L
+VREF_DQB
1 1
+3VS
DDR_B_CKE0<6>
DDR_B_BS2<6>
DDR_B_CLK0<6>
DDR_B_CLK0#<6>
DDR_B_BS0<6> DDR_B_RAS# <6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_B_SCS1#<6>
1
1
C207
C207
C208
C208
2
2
@
@
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2
3 3
4 4
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_SCS1#
DDR_B_D37
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R98
R98
1 2
10K_0402_5%
10K_0402_5%
A
+0.75VS
R99
R99
10K_0402_5%
10K_0402_5%
1 2
JDDR3L
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
@
@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
BA1
S0#
A15
A14
A11
A7
A6
A4
A2
A0
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
B
+1.5V+1.5V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
MEM_MB_RST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_CKE1
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDR_B_SCS0#
DDR_B_ODT0
DDR_B_ODT1
+VREF_CAB
DDR_B_D32
DDR_B_D33
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
MEM_MB_EVENT#
FCH_SDATA0
FCH_SCLK0
+0.75VS
B
DDR3 SO-DIMM B
Standard Type
MEM_MB_RST# <6>
DDR_B_CKE1 <6>
DDR_B_CLK1 <6>
DDR_B_CLK1# <6>
DDR_B_BS1 <6>
DDR_B_SCS0# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1
C113
C113
C188
C188
1000P_0402_50V7K
1000P_0402_50V7K
2
Close to JDDR3L.126
MEM_MB_EVENT# <6>
FCH_SDATA0 <10,13,22>
FCH_SCLK0 <10,13,22>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@
@
1
1
C187
C187
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
C
DDR_B_DQS#[0..7] <6>
DDR_B_DQS[0..7] <6>
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
DDR_B_DM[0..7] <6>
+VREF_DQB
1
1
C184
C184
C112
C112
0.1U_0402_16V7K
0.1U_0402_16V7K
1000P_0402_50V7K
1000P_0402_50V7K
2
2
Close to JDDRL.1
+1.5V
12
R86
R86
1K_0402_1%
1K_0402_1%
12
R94
R94
1K_0402_1%
1K_0402_1%
Compal Secret Data
Compal Secret Data
2011/11/21 2011/12/11
2011/11/21 2011/12/11
2011/11/21 2011/12/11
C
Compal Secret Data
Layout Note:
Place near JDDRH
+1.5V
Deciphered Date
Deciphered Date
Deciphered Date
@
@
+
+
C189 330U_B2_2.5VM_R15M
C189 330U_B2_2.5VM_R15M
1 2
C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z
1 2
C169 0.1U_0402_16V4ZC169 0.1U_0402_16V4Z
1 2
C172 0.1U_0402_16V4ZC172 0.1U_0402_16V4Z
1 2
C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z
1 2
C195 0.1U_0402_16V4ZC195 0.1U_0402_16V4Z
1 2
C177 0.1U_0402_16V4ZC177 0.1U_0402_16V4Z
1 2
C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z
1 2
C191 0.1U_0402_16V4ZC191 0.1U_0402_16V4Z
1 2
C192 0.1U_0402_16V4ZC192 0.1U_0402_16V4Z
1 2
C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z
1 2
1
C183
C183
@
@
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
D
+1.5V
12
1K_0402_1%
1K_0402_1%
12
1K_0402_1%
1K_0402_1%
D
R83
R83
R84
R84
E
Layout Note:
Place near JDDRH.203 and 204
+0.75VS
@
@
C87 0.1U_0402_16V4Z
C87 0.1U_0402_16V4Z
1 2
C86 4.7U_0603_6.3V6KC86 4.7U_0603_6.3V6K
1 2
C194 0.1U_0402_16V4ZC194 0.1U_0402_16V4Z
1 2
C206 0.1U_0402_16V4ZC206 0.1U_0402_16V4Z
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
+1.5V
of
of
of
11 40Monday, March 26, 2012
11 40Monday, March 26, 2012
11 40Monday, March 26, 2012
E
A
A
A
A
APU_PCIE_RST#_R
LPC_RST#_R
C202 0.1U_0402_16V7KC202 0.1U_0402_16V7K
UMI_MTX_C_FRX_P0<5>
UMI_MTX_C_FRX_N0<5>
UMI_MTX_C_FRX_P1<5>
UMI_MTX_C_FRX_N1<5>
UMI_MTX_C_FRX_P2<5>
UMI_MTX_C_FRX_N2<5>
UMI_MTX_C_FRX_P3<5>
1 1
2 2
UMI_MTX_C_FRX_N3<5>
UMI_FTX_C_MRX_P0<5>
UMI_FTX_C_MRX_N0<5>
UMI_FTX_C_MRX_P1<5>
UMI_FTX_C_MRX_N1<5>
UMI_FTX_C_MRX_P2<5>
UMI_FTX_C_MRX_N2<5>
UMI_FTX_C_MRX_P3<5>
UMI_FTX_C_MRX_N3<5>
+PCIE_VDDR_FCH
+1.1VS_CKVDD
SS
APU Display
1 2
C203 0.1U_0402_16V7KC203 0.1U_0402_16V7K
1 2
C204 0.1U_0402_16V7KC204 0.1U_0402_16V7K
1 2
C209 0.1U_0402_16V7KC209 0.1U_0402_16V7K
1 2
C210 0.1U_0402_16V7KC210 0.1U_0402_16V7K
1 2
C211 0.1U_0402_16V7KC211 0.1U_0402_16V7K
1 2
C213 0.1U_0402_16V7KC213 0.1U_0402_16V7K
1 2
C212 0.1U_0402_16V7KC212 0.1U_0402_16V7K
1 2
R220 590_0402_1%R220 590_0402_1%
1 2
R221 2K_0402_1%R221 2K_0402_1%
1 2
R228 2K_0402_1%R228 2K_0402_1%
1 2
Input from external clock generator
NC for internal clock generator
APU_DISP_CLKP<7>
APU_DISP_CLKN<7>
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
PCIE_CALRP
PCIE_CALRN
CLK_CALRN
APU_DISP_CLKP
APU_DISP_CLKN
NSS
APU
WLAN
SS
LAN
3 3
FCH_RTCX1_R<22>
APU_CLKP<7>
APU_CLKN<7>
CLK_WLAN<22>
CLK_WLAN#<22>
CLK_LAN<23>
CLK_LAN#<23>
Place close to Y2
FCH_X1_R<22>
Place close to Y1
NOGCLK@
NOGCLK@
C220 27P_0402_50V8J
C220 27P_0402_50V8J
1 2
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
NOGCLK@
NOGCLK@
1 2
C230 27P_0402_50V8J
C230 27P_0402_50V8J
4 4
C248 18P_0402_50V8J
C248 18P_0402_50V8J
1 2
NOGCLK@
NOGCLK@
20M_0402_5%
20M_0402_5%
C249 18P_0402_50V8J
C249 18P_0402_50V8J
1 2
NOGCLK@
NOGCLK@
A
R230
R230
NOGCLK@
NOGCLK@
12
Y1
Y1
NOGCLK@
NOGCLK@
12
1 2
APU_CLKP
APU_CLKN
CLK_WLAN
CLK_WLAN#
CLK_LAN
CLK_LAN#
GCLK@
GCLK@
1 2
R207 0_0402_5%
R207 0_0402_5%
GCLK@
GCLK@
1 2
R208 0_0402_5%
R208 0_0402_5%
R229
R229
1M_0402_5%
1M_0402_5%
NOGCLK@
NOGCLK@
Y2
Y2
32.768KHZ_12.5P_1TJF125DP1A000D
32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@
NOGCLK@
32K_X1
25M_X1
25M_X1
25M_X2
B
32K_X1
32K_X2
B
AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32
AB33
AB31
AB28
AB29
AF29
AF31
AB26
AB27
AA24
AA23
AA27
AA26
AD5
W30
W32
W27
W26
W24
W23
M23
M24
M27
M26
AE2
Y33
Y31
Y28
Y29
V33
V31
V27
V26
F27
G30
G28
R26
T26
H33
H31
T24
T23
J30
K29
H27
H28
J27
K26
F33
F31
E33
E31
N25
N26
R23
R24
N27
R27
J26
C31
C33
U1A
U1A
PCIE_RST#
A_RST#
UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N
UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
PCIE_CALRP
PCIE_CALRN
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
CLK_CALRN
PCIE_RCLKP
PCIE_RCLKN
DISP_CLKP
DISP_CLKN
DISP2_CLKP
DISP2_CLKN
APU_CLKP
APU_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
14M_25M_48M_OSC
25M_X1
25M_X2
HUDSON-M3_FCBGA656
HUDSON-M3_FCBGA656
HUDSON-2
HUDSON-2
PCI CLKS
PCI CLKS
PCICLK4/14M_OSC/GPO39
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
PCI INTERFACE
PCI INTERFACE
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLOCK GENERATOR
CLOCK GENERATOR
LPCAPUS5 PLUS
LPCAPUS5 PLUS
LDRQ1#/CLK_REQ6#/GPIO49
C
HUDM3R3@
HUDM3R3@
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
GNT0#
GNT1#/GPO44
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
SERIRQ/GPIO48
DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
32K_X1
32K_X2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
AF1
AF5
AG2
AF6
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
AF18
AE18
AC16
AD18
B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
G25
E28
E26
G26
F26
H7
F1
F3
E6
G2
G4
PCI_CLK1
PCI_CLK3
PCI_CLK4
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
GPIO30
GPIO31
LPC_CLK0
LPC_CLK1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SERIRQ
DMA_ACTIVE#
APU_PROCHOT#_R
APU_PWRGD_R
APU_RST#
RTC_CLK_R
+RTCVCC_R
32K_X1
32K_X2
PCI_CLK0
AF3
R257 22_0402_5%R257 22_0402_5%
1 2
PCI_CLK1 <15>
PCI_CLK3 <15>
PCI_CLK4 <15>
PCI_AD23 <15>
PCI_AD24 <15>
PCI_AD25 <15>
PCI_AD26 <15>
PCI_AD27 <15>
R255 22_0402_5%R255 22_0402_5%
1 2
R258 22_0402_5%R258 22_0402_5%
1 2
R259 0_0402_5%R259 0_0402_5%
1 2
R266 0_0402_5%R266 0_0402_5%
1 2
T25T25
1 2
R260 0_0402_5%R260 0_0402_5%
20 mils
C250
C250
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
2010/11/11 2011/11/11
2010/11/11 2011/11/11
2010/11/11 2011/11/11
Compal Secret Data
1
1
C252
C252
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
Deciphered Date
Deciphered Date
Deciphered Date
Strap
Strap
1 2
120_0402_5%
120_0402_5%
D
CLK_PCI_TPM_FCH <26>
APU_PCIE_RST#_R
LPC_RST#_R
CLK_PCI_EC <15,27>
CLK_PCI_DDR <15,28>
LPC_AD0 <26,27,28>
LPC_AD1 <26,27,28>
LPC_AD2 <26,27,28>
LPC_AD3 <26,27,28>
LPC_FRAME# <26,27,28>
SERIRQ <26,27>
DMA_ACTIVE# <7>
APU_PROCHOT# <7>
APU_PWRGD <7,37>
APU_RST# <7>
RTC_CLK <15,27>
R271
R271
CMOS Setting
Place under DDR
Door
D
Strap
Strap
Update RTC schematic on PVT
+RTCVCC
R277
R277
1 2
120_0402_5%
120_0402_5%
12
JCMOS@JCMOS
@
E
R225 33_0402_5%R225 33_0402_5%
1 2
150P_0402_50V8J
150P_0402_50V8J
R226 33_0402_5%R226 33_0402_5%
1 2
150P_0402_50V8J
150P_0402_50V8J
PCIE_RST# is for PCIE devices on APU
1
R223
2
R223
100K_0402_5%
100K_0402_5%
@
@
1 2
C221
C221
A_RST# is for LPC devices
1
R224
C222
C222
R224
100K_0402_5%
100K_0402_5%
@
@
2
1 2
@
@
1 2
R337 10K_0402_5%
R337 10K_0402_5%
@
@
1 2
R340 10K_0402_5%
R340 10K_0402_5%
GPIO30
GPIO31
APU_PCIE_RST# <22,23>
LPC_RST# <26,27,28>
R332 10K_0402_5%R332 10K_0402_5%
R339 10K_0402_5%R339 10K_0402_5%
Function GPIO30 GPIO31
PowerXpress
00
Reserved
Discrete
UMA
+RTCBATT_D +RTCBATT
1
C256
C256
2
+RTCBATT
11
NOGCLK@
NOGCLK@
12
D14
D14
0.1U_0402_10V7K
0.1U_0402_10V7K
RB751V-40_SOD323-2
RB751V-40_SOD323-2
If use GCLK, please delete D14
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
S5_CORE_EN is for S5+ mode
used to turn off +1.1VALW and
+3VALW of FCH on S5+ mode
+RTCBATT_D
R268
+RTCBATT_R
R268
1 2
1K_0402_5%
1K_0402_5%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
C295
C295
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
4019IS
4019IS
4019IS
E
1 2
1 2
10
01
12
D13
D13
RB751V-40_SOD323-2
RB751V-40_SOD323-2
+3VL
12 40Monday, March 26, 2012
12 40Monday, March 26, 2012
12 40Monday, March 26, 2012
+3VS
A
A
A
of
of
of
A
B
C
D
E
U1D
PCIE_RST2# is for PCIE devices on FCH
T50T50
@
@
@
@
@
@
EC_LID_OUT#
T57T57
SLP_S3#
SLP_S5#
PBTN_OUT#
FCH_PWRGD
TEST0
TEST1
TEST2
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
T31T31
FCH_PCIE_WAKE#
T55T55
H_THERMTRIP#
WD_PWRGD
EC_RSMRST#
CLKREQ_LAN#_R
FCH_SPKR
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
CLKREQ_WLAN#
T30T30
LAN_EN
T54T54
ODD_DA#_FCH
T59T59
ODD_PLUGIN#
T58T58
T56T56
USB_OC1#
USB_OC0#
HDA_BITCLK
HDA_SDOUT
AZ_SDIN0_HD
AZ_SDIN1_HD
AZ_SDIN2_HD
AZ_SDIN3_HD
HDA_SYNC
HDA_RST#
T26T26
T27T27
T33T33
T32T32
T35T35
T34T34
T37T37
T36T36
T38T38
T39T39
T45T45
T44T44
T46T46
T47T47
T41T41
T40T40
T42T42
T43T43
T49T49
T48T48
B
EC_LID_OUT#<27>
SLP_S3#<27>
SLP_S5#<27>
PBTN_OUT#<27>
FCH_PWRGD<27>
1 1
SM Bus 0-->S0 PWR domain
SM Bus 1-->S5 PWR domain
(for ASF device only)
2 2
USB_OC1# is for left USB3.0 ports
USB_OC0# is for right USB2.0 ports
AZ_BITCLK_HD<25>
AZ_SDOUT_HD<25>
AZ_SDIN0_HD<25>
AZ_SYNC_HD<25>
AZ_RST_HD#<25>
3 3
+3VALW_FCH
1 2
R278 10K_0402_5%R278 10K_0402_5%
@
@
1 2
R272 10K_0402_5%
R272 10K_0402_5%
1 2
R276 10K_0402_5%R276 10K_0402_5%
1 2
R318 10K_0402_5%R318 10K_0402_5%
1 2
R319 10K_0402_5%R319 10K_0402_5%
1 2
R288 10K_0402_5%R288 10K_0402_5%
1 2
R289 10K_0402_5%R289 10K_0402_5%
+3VS
1 2
R286 2.2K_0402_5%R286 2.2K_0402_5%
1 2
R287 2.2K_0402_5%R287 2.2K_0402_5%
@
@
1 2
R291 8.2K_0402_5%
R291 8.2K_0402_5%
@
@
1 2
R284 8.2K_0402_5%
R284 8.2K_0402_5%
4 4
R280 100K_0402_5%R280 100K_0402_5%
@
@
1 2
R324 10K_0402_5%
R324 10K_0402_5%
@
@
1 2
R325 10K_0402_5%
R325 10K_0402_5%
@
@
1 2
R331 10K_0402_5%
R331 10K_0402_5%
@
@
1 2
R333 10K_0402_5%
R333 10K_0402_5%
@
@
1 2
R335 10K_0402_5%
R335 10K_0402_5%
Internal Pull-up ?
H_THERMTRIP#
EC_LID_OUT#
FCH_PCIE_WAKE#
USB_OC0#
USB_OC1#
FCH_SCLK1
FCH_SDATA1
FCH_SCLK0
FCH_SDATA0
CLKREQ_WLAN#
CLKREQ_LAN#
EC_RSMRST#
12
HDA_BITCLK
AZ_SDIN0_HD
AZ_SDIN1_HD
AZ_SDIN2_HD
AZ_SDIN3_HD
A
GATEA20<27>
KB_RST#<27>
EC_SCI#<27>
EC_SMI#<27>
FCH_PCIE_WAKE#<23>
H_THERMTRIP#<7>
1 2
+3VS
R279 10K_0402_5%R279 10K_0402_5%
EC_RSMRST#<27>
CLKREQ_LAN#<23>
FCH_SPKR<25>
FCH_SCLK0<10,11,22>
FCH_SDATA0<10,11,22>
CLKREQ_WLAN#<22>
LAN_EN<23>
ODD_PLUGIN#<21>
USB_OC1#<24>
USB_OC0#<21>
R320 33_0402_5%R320 33_0402_5%
1 2
R321 33_0402_5%R321 33_0402_5%
1 2
R322 33_0402_5%R322 33_0402_5%
1 2
R323 33_0402_5%R323 33_0402_5%
1 2
For FCH internal debug use
+3VALW_FCH
(Internal 10K pull-down)
1 2
R273 2.2K_0402_5%
R273 2.2K_0402_5%
1 2
R274 2.2K_0402_5%
R274 2.2K_0402_5%
1 2
R275 2.2K_0402_5%
R275 2.2K_0402_5%
U1D
AB6
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVENT2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
AE24
CLK_REQ3#/SATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/SATA_IS3#/GPIO60
AH17
SATA_IS4#/FANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN#/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GPIO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GPIO167
Y5
AZ_SDIN1/GPIO168
Y3
AZ_SDIN2/GPIO169
Y1
AZ_SDIN3/GPIO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/SDA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
HUDSON-M3_FCBGA656
HUDSON-M3_FCBGA656
TEST0
TEST1
TEST2
HUDSON-2
HUDSON-2
EMBEDDED CTRL
EMBEDDED CTRL
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
USBCLK/14M_25M_48M_OSC
USB MISCUSB 1.1USB 2.0USB 3.0
USB MISCUSB 1.1USB 2.0USB 3.0
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
2010/11/11 2011/11/11
2010/11/11 2011/11/11
2010/11/11 2011/11/11
HUDM3R3@
HUDM3R3@
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
Compal Secret Data
Compal Secret Data
Compal Secret Data
G8
USB_RCOMP
B9
H1
H3
H6
H5
H10
G10
K10
J12
USB20_P11
G12
USB20_N11
F12
USB20_P10
K12
USB20_N10
K13
B11
D11
E10
F10
C10
A10
H9
G9
A8
C8
USB20_P4
F8
USB20_N4
E8
USB20_P3
C6
USB20_N3
A6
USB20_P2
C5
USB20_N2
A5
USB20_P1
C1
USB20_N1
C3
USB20_P0
E1
USB20_N0
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
A14
C14
C12
A12
D15
B15
E14
F14
USB30_TX1P
F15
USB30_TX1N
G15
USB30_RX1P
H13
USB30_RX1N
G13
USB30_TX0P
J16
USB30_TX0N
H16
USB30_RX0P
J15
USB30_RX0N
K15
R326 10K_0402_5%R326 10K_0402_5%
H19
R328 10K_0402_5%R328 10K_0402_5%
G19
R338 10K_0402_5%R338 10K_0402_5%
G22
R343 10K_0402_5%R343 10K_0402_5%
G21
E22
H22
EC_PWM2
J22
H21
K21
K22
F22
F24
E24
B23
C24
F18
Deciphered Date
Deciphered Date
Deciphered Date
R329 11.8K_0402_1%R329 11.8K_0402_1%
1 2
USB20_P11 <24>
USB20_N11 <24>
USB20_P10 <24>
USB20_N10 <24>
USB20_P4 <18>
USB20_N4 <18>
USB20_P3 <22>
USB20_N3 <22>
USB20_P2 <26>
USB20_N2 <26>
USB20_P1 <21>
USB20_N1 <21>
USB20_P0 <21>
USB20_N0 <21>
R330 1K_0402_1%R330 1K_0402_1%
1 2
R334 1K_0402_1%R334 1K_0402_1%
1 2
USB30_TX1P <24>
USB30_TX1N <24>
USB30_RX1P <24>
USB30_RX1N <24>
USB30_TX0P <24>
USB30_TX0N <24>
USB30_RX0P <24>
USB30_RX0N <24>
1 2
1 2
1 2
1 2
EC_PWM2 <15>
Place R425 and C363
close to FCH for ESD
ODD_DA#_FCH
R425 0_0402_5%
R425 0_0402_5%
1
C363
C363
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
2
D
@
@
1 2
Hudson-M2/M3
OHCI (DEV-20, FUN-5)
Hudson-M2
OHCI (DEV-22, FUN-0)
EHCI (DEV-22, FUN-2)
USB 3.0-Left2
USB 3.0-Left1
Hudson-M3
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)
Hudson-M2/M3
OHCI (DEV-19, FUN-0)
EHCI (DEV-19, FUN-2)
Int. Camera
WLAN (BT)
Cardreader
USB-Right2
USB-Right1
(Debug Port)
+FCH_VDD_11_SSUSB_S
Hudson-M2/M3
OHCI (DEV-18, FUN-0)
EHCI (DEV-18, FUN-2)
<Support Wakeup>
Hudson-M3
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)
USB 3.0-Left2
USB 3.0-Left1
SM Bus 2-->S5 PWR domain
SM Bus 3-->APU_VDDIO domain for SB-TSI
Strap
+3VALW_FCH
R312
R312
10K_0402_5%
10K_0402_5%
@
@
1 2
ODD_DA#_Q
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1 3
2N7002_SOT23-3
2N7002_SOT23-3
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
SCHEMATIC,MB LA-8864
+3VS
D
D
2
G
G
Q32
Q32
S
S
4019IS
4019IS
4019IS
+3VS
1 2
R311
R311
10K_0402_5%
10K_0402_5%
E
ODD_DA# <21>
A
A
13 40Monday, March 26, 2012
13 40Monday, March 26, 2012
13 40Monday, March 26, 2012
A
of
of
of
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