Compal LA-8862P QCLA4 Eureka 14, NP350V5C, LA-8862P QCLA5 Eureka 14, LA-8862P QCLA4 Eureka 15, LA-8862P QCLA5 Eureka 15 Schematic

A

B

C

D

E

1 1

QCLA4,5

2 2

Eureka 14" & 15"

LA-8862P SchematicREV 0.2

3 3

4 4

A

Intel Processor(Ivy Bridge / Sandy Bridge)
PCH(Panther Point)

2011-11-24 Rev 0.2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/01/31 2012/12/31

2011/01/31 2012/12/31

2011/01/31 2012/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS, MB A8862

SCHEMATICS, MB A8862

SCHEMATICS, MB A8862

4019IV

4019IV

4019IV

148Tuesday, March 27, 2012

148Tuesday, March 27, 2012

148Tuesday, March 27, 2012

E

B

B

B

of

of

of

A

B

C

D

E

Intel CPU
Ivy Bridge
Sandy Bridge

1 1

eDP Conn.

page 13

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

CRT

page 14

FDI X8

2.7GT/s

LVDS Conn.

page 13

2 2

EC SMBus

HDMI-CEC

page 15

HDMI Conn.

page 15

Intel PCH
Panther Point

RJ45

page 40

RTL8105E-VD 10/100M
RTL8111F-VB 1G

PCIe port 1

page 31

Cardreader
RTS5229

PCIe port4

3 3

page 29

SPI ROM
(4MB + 2MB)

page 16

PCIe Gen1 1x

1.5V 5GT/s

PCIe Gen1 1x

1.5V 5GT/s

Debug Port

page 36

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

ENE KB930/KB9012

page 35

DMI X4

5GT/s

HD Audio

3.3V 24MHz

USB30 4x

5V 5GT/s

USB20 4x

5V 480MHz

USB20 3x

5V 480MHz

USB20 3x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 port 1

5V 6GHz(600MB/s)

SATA Gen3 port 0

SATA port 2

5V 3GHz(300MB/s)

PCIe Gen2 2x

1.5V 5GT/s

HDA Codec

ALC280

page 33

USB Right

USB20 port 2,3
USB30 port 3,4 USB30 port 1,2

page 25

USB Left

USB20 port 0,1

page 30

FingerPrinter Int. Camera

USB port 8

page 29

PCIeMini Card
WiMax

USB port 9

page 27 page 27

USB port 11

page 13

PCIeMini Card

3G/TV#1
TV#2

PCIeMini Card
WLAN

5V 6GHz(600MB/s)

SATA ODD

PCIe port 2

page 27

SATA port 2

page 23

mSATA

SATA HDD

USB3.0 Right-side
UPD720202

PCIe port5

page 31

USB port 12
USB port 10

SATA port 1

page 27

SATA port 0

page 23

B-CAS

page 26

USB3.0 Left-side
UPD720202

PCIe port6

page 32

SIM

page 27

RTC CKT.

page 16

DC/DC Interface CKT.

page 38

4 4

Power Circuit DC/DC

page 39,40,41,42,43,
44,45,46,47,48,49

Power On/Off CKT.

page 37

A

Finger Printer/B

page 26

Power/B

page 37

Touch Pad

page 37

B

Int.KBD

page 36

EC ROM
(128KB)

page 36

CIR

page 35

G-Sensor

page 36

EC SMBus

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

SPK Conn

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

page 34

JPIO
(HP & MIC)

D

page 34

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A8862

SCHEMATICS, MB A8862

SCHEMATICS, MB A8862

4019IV

4019IV

4019IV

248Tuesday, March 27, 2012

248Tuesday, March 27, 2012

248Tuesday, March 27, 2012

E

of

of

of

B

B

B

5

B+

Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A

SUSP#

SY8033BDBC

D D

N-CHANNEL

SI4800

TPS51125

SY8036

C C

VCCPPWRGD

SY8037

LNB EN

APW7137

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

B B

N-CHANNEL

SI4800

SUSP

SUSP

4

SYSON

Ipeak=6A, Imax=4.2A, Iocp min=8A

Ipeak=6A, Imax=4.A, Iocp min=8

Imax=0.3A, Iocp min=0.8A

BCPWON

P-CHANNEL

AO-3413

KB_LED

P-CHANNEL

AO-3413

+5VS

LDO

G9191

ODD_EN#

P-CHANNEL

AO-3413

N-CHANNEL
FDS6676AS

N-CHANNEL
FDS6676AS

0.75VR_EN#

G2992

WOL_EN

P-CHANNEL

AO-3413

P-CHANNEL

AO-3415

SUSP

SUSP

UMA_ENVDD

3

DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A

DESIGN CURRENT 11A

DESIGN CURRENT 1.8A

DESIGN CURRENT 6.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.4A

DESIGN CURRENT 0.3A

DESIGN CURRENT 1.6A

DESIGN CURRENT 13.5A

DESIGN CURRENT 5A

DESIGN CURRENT 1.5A

DESIGN CURRENT 1A

DESIGN CURRENT 6A

DESIGN CURRENT 0.3A

DESIGN CURRENT 7.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 6A

DESIGN CURRENT 2A

+3VL
+5VL

+5VALW

+1.8VS

+5VS

+5VS_L_BCAS

+5VS_LED

+3VS_HDP

+5VS_ODD

+1.5V

+1.5V_CPU

+1.5VS

+0.75VS

+VCCSA

+16VS

+3VALW

+3V_LAN

+3VS

+LCD_VDD

2

1

FELICA_PWR

P-CHANNEL

VR_ON

AO-3413

NCP6132A

SUSP#

TPS51212

A A

Ipeak=14A, Imax=9.8A, Iocp min=16.92A

DESIGN CURRENT 0.1A

DESIGN CURRENT 94A

DESIGN CURRENT 50A

DESIGN CURRENT 15A

+FLICA_VCC

+CPU_CORE
+GFX_CORE

+1.05VS_VCCP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Power Tree

Power Tree

Power Tree

QFKAA

QFKAA

QFKAA

0.3

0.3

0.3

of

348Tuesday, March 27, 2012

of

348Tuesday, March 27, 2012

of

348Tuesday, March 27, 2012

1

A

B

C

D

E

Voltage Rails

1 1

power
plane

State

S0

S1

2 2

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

O
O
O
O
O
O

B+

O
O
O
O
O

X

+5VL
+3VL

O
O
O
O
O

X

+5VALW
+3VALW
+VSB

O
O
O
O

X
X

+1.5V

+5VS
+3VS
+1.8VS
+1.5VS
+1.05VS
+0.75VS
+CPU_CORE
+VGA_CORE
+GFX_CORE
+VTT
+VRAM_1.5VS
+3VS_DGPU
+1.05VS_DGPU

OO
OO

O

X
XX
X

X
XX

BTO Option Table

Function

description

explain

BTO

Function

description

explain

BTO

HDMI

HDMI

HDMI

HDMI@

SPI ROM

SPI ROM

WIN8

WIN8@

Digital MIC

Green CLK

Green CLK

Green CLK

GCLK@

Camera & Mic

Camera & Mic

CAM@

NOGCLK

NOGCLK@

Analog MIC

AMIC@

USB 3.0

USB 3.0

Internal

IUSB30@

TPM

TPM

SLB 9635

TPM9635@ TPM9655@

Sleep & Charge

Sleep & Charge

SLB 9655

10/100M Giga

8105ELDO@ 8111FVB@

MINI PCI-E SLOT

Half Card

WIMAX

WIMAX@

LAN

LAN

PCH SM Bus Address

HEX

A0 H

D2 H

0001 0110 bSmart Battery

Address

1010 0000 b
1010 0100 bA4 H
1101 0010 b

EC SM Bus2 Address

PowerPower

+3VS
+3VS
+3VS
+3VS Light Sensor

Device

NVIDIA GPUHDMI-CEC 34 H 0011 0100 b 1001 1010 b
G-Sensor

96 H
9A H
40 H
52 H

1001 0110 bPCH

0100 0000 b
0101 0010 b

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

HIGH

Power

+3VS

3 3

+3VS
+3VS
+3VS
+3VS
+3VS Clock Generator

Device

DDR SO-DIMM 0
DDR SO-DIMM 1
Clock Generator
New Card
WLAN/WIMAX

3G+3VS

EC SM Bus1 Address

Device Address Address

+3VL
+3VL

4 4

+3VL Cap. Sensor Virtual I2C

HEX HEX

16 H

HEXDevice AddressPower

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List

QFKAA

QFKAA

QFKAA

448Tuesday, March 27, 2012

448Tuesday, March 27, 2012

448Tuesday, March 27, 2012

E

0.3

0.3

0.3

of

of

of

5

@

@

PM_DRAM_PWRGD_R

CC631000P_0402_50V7K

CC631000P_0402_50V7K

12

@

@

12

D D

+1.05VS_VCCP

C C

+3VALW_PCH

PM_PWROK18,31
DRAMPWROK18

B B

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402_5%

RC11 200_0402_5%RC11 200_0402_5%

12

12

@

@

12

@

@

12

@

@

12

Please place near JCPU

12

10K_0402_5%

10K_0402_5%

RC13

RC13

+3VS

1 2

RC12 0_0402_5%@RC12 0_0402_5%@

CC621000P_0402_50V7K

CC621000P_0402_50V7K

CC701000P_0402_50V7K

CC701000P_0402_50V7K

CC711000P_0402_50V7K

CC711000P_0402_50V7K

CC661000P_0402_50V7K

CC661000P_0402_50V7K

DRAMPWROK

12

RC181 0_0402_5%@RC181 0_0402_5%@

H_PWRGOOD_R

H_PROCHOT#

H_PWRGOOD

H_PM_SYNC

BUF_CPU_RST#

+3VALW_PCH

1

B

2

A

1 2

SUSP9,34

H_PECI

12

0.1U_0402_10V7K

0.1U_0402_10V7K
CC33

CC33

UC1

UC1

5

74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

P

PM_SYS_PWRGD_BUF

4

O

G

3

SUSP

+1.5V_CPU

12

RC25

RC25
39_0402_5%

39_0402_5%
@

@

13

D

D

QC2

QC2
2N7002_SOT23

2N7002_SOT23

2

G

G

@

@

S

S

H_SNB_IVB#11,21

H_PROCHOT#31

H_THERMTRIP#21

H_PM_SYNC18

H_PWRGOOD21

12

H_PECI31

RC14

RC14
200_0402_5%

200_0402_5%

4

T1 PADT1 PAD

T2 PADT2 PAD

1 2

1 2

1 2

RC58 130_0402_5%RC58 130_0402_5%

BUF_CPU_RST#

RC159

RC159

RC187

RC187

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

H_PWRGOOD_R

0_0402_5%

0_0402_5%

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

JCPUB

JCPUB

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK
TMS

TRST#

TDI

TDO

DBR#

BPM#[0]
BPM#[1]

JTAG & BPM

JTAG & BPM

BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

100 MHz

CLK_CPU_DMI

A28

CLK_CPU_DMI#

A27

120 MHz

CLK_CPU_EDP

A16

CLK_CPU_EDP#

A15

H_DRAMRST#

R8

SM_RCOMP_0

AK1
A5
A4

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

RC56 140_0402_1%RC56 140_0402_1%

SM_RCOMP_1

RC59 25.5_0402_1%RC59 25.5_0402_1%

SM_RCOMP_2

RC61 200_0402_1%RC61 200_0402_1%

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

T4PAD T4PAD
T5PAD T5PAD

RC55 51_0402_5%RC55 51_0402_5%

T6PAD T6PAD
T7PAD T7PAD

Layout request for test point

2

CLK_CPU_DMI 17
CLK_CPU_DMI# 17

H_DRAMRST# 7

12
12
12

12

Stuff RC157 and RC158 if do not support eDP

CLK_CPU_EDP#
CLK_CPU_EDP

DDR3 Compensation Signals
Layout Note:Place these
resistors near Processor

H_DRAMRST#

by ESD requestion and place near CPU

1

1 2

RC157 1K_0402_5%RC157 1K_0402_5%

1 2

RC158 1K_0402_5%RC158 1K_0402_5%

@

@

1 2

CC34 180P_0402_50V8J

CC34 180P_0402_50V8J

+1.05VS_VCCP

FAN Control Circuit

Buffered Reset to CPU

+3VS

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CC36

CC36

PLT_RST# 20,26,27,28,31,32

UC2

PLT_RST#

A A

UC2

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

74AHC1G125GW_SOT353-5

VCC

OUT

2

5

4

5

+1.05VS_VCCP

12

RC38

RC38
75_0402_5%

75_0402_5%

RC35

RC35

43_0402_1%

BUFO_CPU_RST# BUF_CPU_RST#

43_0402_1%

1 2

12

RC40

RC40
0_0402_5%

0_0402_5%
@

@

EN_DFAN131

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VS

1A

C13

C13

10U_0805_6.3V6M

10U_0805_6.3V6M

U1

U1

1

EN

2

+FAN2

10mil

2

3
4

12

C17

C17

10U_0805_6.3V6M

10U_0805_6.3V6M

VIN
VOUT
VSET

APL5607KI-TRG_SO8

APL5607KI-TRG_SO8

8

GND

7

GND

6

GND

5

GND

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+FAN2

@

@

2

12

C15

C15
1000P_0402_50V7K

1000P_0402_50V7K

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

Sandy Bridge_JTAG/XDP/FAN

Sandy Bridge_JTAG/XDP/FAN

QFKAA

QFKAA

QFKAA

1
2
3

4
5

ACES_85204-0300N

ACES_85204-0300N

R24 10K_0402_5%R24 10K_0402_5%

FAN_SPEED1

1

C14

C14

0.01U_0402_25V7K

0.01U_0402_25V7K
@

@

2

1

JFAN

1
2
3

GND
GND

@JFAN

@

12

+3VS

FAN_SPEED1 31

0.3

0.3

548Tuesday, March 27, 2012

548Tuesday, March 27, 2012

548Tuesday, March 27, 2012

0.3

of

of

of

5

4

3

2

1

+1.05VS_VCCP

JCPUA

D D

DMI_PTX_CRX_N018
DMI_PTX_CRX_N118

C C

eDP_COMP signals should be
shorted near balls and
routed with typical
impedance <25m ohm

B B

+1.05VS_VCCP
+1.05VS_VCCP

DMI_PTX_CRX_N218
DMI_PTX_CRX_N318

DMI_PTX_CRX_P018
DMI_PTX_CRX_P118
DMI_PTX_CRX_P218
DMI_PTX_CRX_P318

DMI_CTX_PRX_N018
DMI_CTX_PRX_N118
DMI_CTX_PRX_N218
DMI_CTX_PRX_N318

DMI_CTX_PRX_P018
DMI_CTX_PRX_P118
DMI_CTX_PRX_P218
DMI_CTX_PRX_P318

FDI_CTX_PRX_N018
FDI_CTX_PRX_N118
FDI_CTX_PRX_N218
FDI_CTX_PRX_N318
FDI_CTX_PRX_N418
FDI_CTX_PRX_N518
FDI_CTX_PRX_N618
FDI_CTX_PRX_N718

FDI_CTX_PRX_P018
FDI_CTX_PRX_P118
FDI_CTX_PRX_P218
FDI_CTX_PRX_P318
FDI_CTX_PRX_P418
FDI_CTX_PRX_P518
FDI_CTX_PRX_P618
FDI_CTX_PRX_P718

FDI_FSYNC018
FDI_FSYNC118

FDI_INT18
FDI_LSYNC018

FDI_LSYNC118

RC2 24.9_0402_1%RC2 24.9_0402_1%

1 2
1 2

RC3 10K_0402_5%RC3 10K_0402_5%

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

EDP_COMP
H_EDP_HPD#

Reserve RC3 for HW Review demand

JCPUA

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_COMP

RC1

RC1

24.9_0402_1%

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

A A

5

4

Security Classification

Security Classification

Security Classification

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_DMI/PEG/FDI

Sandy Bridge_DMI/PEG/FDI

Sandy Bridge_DMI/PEG/FDI

QFKAA

QFKAA

QFKAA

648Tuesday, March 27, 2012

648Tuesday, March 27, 2012

648Tuesday, March 27, 2012

1

of

of

of

0.3

0.3

0.3

5

JCPUC

AP11

AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14
AH14

AL15

AK15

AL14

AK14

AJ15
AH15

AE10

AF10

F10
G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

K2
M8

N8

N7
M9

N9
M7

V6

J1
J5
J4
J2

JCPUC

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

DDR_A_D[0..63]11

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3

D D

C C

B B

DDR_A_BS011
DDR_A_BS111
DDR_A_BS211

DDR_A_CAS#11
DDR_A_RAS#11

DDR_A_WE#11

DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]
SA_ODT[1]

RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

4

DDR_B_D[0..63]12

DDRA_CLK0

AB6

DDRA_CLK0#

AA6

DDRA_CKE0

V9

DDRA_CLK1 DDRB_CLK1

AA5

DDRA_CLK1# DDRB_CLK1#

AB5

DDRA_CKE1 DDRB_CKE1

V10

AB4
AA4
W9

AB3
AA3
W10

DDRA_SCS0# DDRB_SCS0#

AK3

DDRA_SCS1#

AL3
AG1
AH1

DDRA_ODT0 DDRB_ODT0

AH3

DDRA_ODT1

AG3
AG2
AH2

DDR_A_DQS#0

C4

DDR_A_DQS#1

G6

DDR_A_DQS#2

J3

DDR_A_DQS#3

M6

DDR_A_DQS#4

AL6

DDR_A_DQS#5

AM8

DDR_A_DQS#6

AR12

DDR_A_DQS#7

AM15

DDR_A_DQS0

D4

DDR_A_DQS1

F6

DDR_A_DQS2

K3

DDR_A_DQS3

N6

DDR_A_DQS4

AL5

DDR_A_DQS5

AM9

DDR_A_DQS6

AR11

DDR_A_DQS7

AM14

DDR_A_MA0

AD10

DDR_A_MA1

W1

DDR_A_MA2

W2

DDR_A_MA3

W7

DDR_A_MA4

V3

DDR_A_MA5

V2

DDR_A_MA6

W3

DDR_A_MA7

W6

DDR_A_MA8

V1

DDR_A_MA9

W5

DDR_A_MA10

AD8

DDR_A_MA11

V4

DDR_A_MA12

W4

DDR_A_MA13

AF8

DDR_A_MA14

V5

DDR_A_MA15

V7

DDRA_CLK0 11 DDRB_CLK0 12
DDRA_CLK0# 11
DDRA_CKE0 11 DDRB_CKE0 12

DDRA_CLK1 11
DDRA_CLK1# 11 DDRB_CLK1# 12
DDRA_CKE1 11

DDRA_SCS0# 11
DDRA_SCS1# 11 DDRB_SCS1# 12

DDRA_ODT0 11 DDRB_ODT0 12
DDRA_ODT1 11 DDRB_ODT1 12

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

DDR_B_CAS#12
DDR_B_RAS#12

DDR_B_WE#12

3

JCPUD

JCPUD

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS012
DDR_B_BS112
DDR_B_BS212

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9

AA7

AA10

AB8

AB9

J10

C9

A7

C8

A9

A8
D9
D8
G4

F4

F1
G1
G5

F5

F2
G2

J7

J8

K9

J9

K8

K7
M5
N4
N2
N1
M4
N5
M2
M1

R6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

DDR_B_DQS#0

D7

DDR_B_DQS#1

F3

DDR_B_DQS#2

K6

DDR_B_DQS#3

N3

DDR_B_DQS#4

AN5

DDR_B_DQS#5

AP9

DDR_B_DQS#6

AK12

DDR_B_DQS#7

AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

DDRB_CLK0# 12

DDRB_CLK1 12
DDRB_CKE1 12

DDRB_SCS0# 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

DDR_B_MA[0..15] 12

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

RC75

RC75

0_0402_5%

0_0402_5%

1 2

@

@

QC3

QC3

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

CC37

CC37

0.047U_0402_25V6K

0.047U_0402_25V6K

2

H_DRAMRST#5

RC78

RC78

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH11,17
DRAMRST_CNTRL_EC31

5

4.99K_0402_1%

DRAMRST_CNTRL

1 2

RC73 0_0402_5%RC73 0_0402_5%

1 2

RC74 0_0402_5%@RC74 0_0402_5%@

RC76

RC76

1K_0402_5%

1K_0402_5%

+1.5V

12

1 2

4

RC77

RC77
1K_0402_5%

1K_0402_5%

SM_DRAMRST# 11,12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

Compal Secret Data

Compal Secret Data

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_DDR3

Sandy Bridge_DDR3

Sandy Bridge_DDR3

QFKAA

QFKAA

QFKAA

1

748Tuesday, March 27, 2012

748Tuesday, March 27, 2012

748Tuesday, March 27, 2012

of

of

of

0.3

0.3

0.3

5

4

3

2

1

+CPU_CORE

D D

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27

C C

B B

A A

AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

POWER

JCPUF

JCPUF

POWER

97A

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

CORE SUPPLY

CORE SUPPLY

5

PEG AND DDR

PEG AND DDR

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

8.5A

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

+1.05VS_VCCP

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10
A10

Close to CPU

0.1U_0402_10V7K

0.1U_0402_10V7K
1 2

CC50

CC50

@

@

RC94 0_0402_5%RC94 0_0402_5%

1 2

RC95 0_0402_5%RC95 0_0402_5%

1 2

RC96

RC96
10_0402_1%

10_0402_1%

12

RC98

RC98
10_0402_1%

10_0402_1%

12

+1.05VS_VCCP+1.05VS_VCCP

12

RC91

RC91
130_0402_5%

130_0402_5%

1 2

RC90 43_0402_1%RC90 43_0402_1%

1 2

RC88 0_0402_5%RC88 0_0402_5%

1 2

RC92 0_0402_5%RC92 0_0402_5%

VCCIO_SENSE 39

+1.05VS_VCCP

4

0.1U_0402_10V7K

0.1U_0402_10V7K
1 2

CC49

CC49

12

@

@

RC89

RC89
75_0402_5%

75_0402_5%

VR_SVID_ALRT# 42
VR_SVID_CLK 42
VR_SVID_DAT 42

Pull high resistor on VR side

+CPU_CORE

RC93

RC93

Close to CPU

100_0402_1%

100_0402_1%

1 2

12

RC97

RC97
100_0402_1%

100_0402_1%

VCCSENSE 42
VSSSENSE 42

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_POWER-1

Sandy Bridge_POWER-1

Sandy Bridge_POWER-1

QFKAA

QFKAA

QFKAA

1

848Tuesday, March 27, 2012

848Tuesday, March 27, 2012

848Tuesday, March 27, 2012

of

of

of

0.3

0.3

0.3

5

+GFX_CORE

AT24

1

CC61

CC61
1U_0402_6.3V6K

1U_0402_6.3V6K

2

AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18

AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24

AL23

AL21

AL20

AL18

AL17

AK24

AK23

AK21

AK20

AK18

AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17

AH24

AH23

AH21

AH20

AH18

AH17

D D

C C

VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

RC119

RC119

10U_0805_10V6K

B B

0_0805_5%

A A

1

+

+

CC58

CC58
@

@

2

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

10U_0805_10V6K

12

0_0805_5%

+1.8VS_VCCPLL

1

1

CC59

CC59

CC60

CC60

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

4

JCPUG

JCPUG

33A

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

1.5A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE
@

@

POWER

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

GRAPHICS

GRAPHICS

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

1.8V RAIL

1.8V RAIL

VAXG_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

AK35
AK34

AL1

SM_VREF

B4
D1

5A

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

Bottom Socket Cavity

6A

M27

VCCSA1

M26

VCCSA2

L26

VCCSA3

J26

VCCSA4

J25

VCCSA5

J24

VCCSA6

H26

VCCSA7

H25

VCCSA8

H23

C22
C24

A19

VCCIO_SEL

3

VCC_AXG_SENSE

VSS_AXG_SENSE

+V_SM_VREF should
have 20 mil trace width

+V_SM_VREF

+VREF_DQA_M3
+VREF_DQB_M3

10U_0805_10V6K

10U_0805_10V6K

1

CC55

CC55

2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

CC40

CC40

H_VCCSA_VID0
H_VCCSA_VID1

1

1

CC41

CC41

2

2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

CC42

CC42

0_0402_5% @

0_0402_5% @

RC120

RC120
1K_0402_0.5%

1K_0402_0.5%

1 2

1K_0402_0.5%

1K_0402_0.5%

1 2

RC109

1

1

CC52

CC52

2

2

10U_0805_10V6K

10U_0805_10V6K

RC109

10U_0805_10V6K

10U_0805_10V6K

CC53

CC53

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CC51

CC51

CC56

CC56

2

10U_0805_10V6K

10U_0805_10V6K

1

CC65

CC65

2

10U_0805_10V6K

10U_0805_10V6K

1

CC57

CC57

2

+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U

+VCCSA

Co-lay for Cost Down Plan

1 2

RC189 0_0402_5%RC189 0_0402_5%

1

CC43

CC43

2

10U_0805_10V6K

10U_0805_10V6K

Bottom Socket Edge

1 2

H_VCCSA_VID0 41
H_VCCSA_VID1 41

1

1

+

+

CC44

CC44

@

@

@

RC111

RC111

@

2

330U_D2_2VM_R6M

330U_D2_2VM_R6M

2

+VCCSA_SENSE 41

Please kindly check whether
pull down by 10k in PWR-Side

+1.5V_CPU +1.5V

CC46 0.1U_0402_10V7KCC46 0.1U_0402_10V7K
CC47 0.1U_0402_10V7KCC47 0.1U_0402_10V7K
CC48 0.1U_0402_10V7KCC48 0.1U_0402_10V7K
CC45 0.1U_0402_10V7KCC45 0.1U_0402_10V7K

+GFX_CORE

12

RC105

RC105

Close to CPU

10_0402_1%

10_0402_1%

RC106

RC106

1 2

10_0402_1%

10_0402_1%

+1.5V_CPU

+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U

+1.5V_CPU

ESR 6mohm

1

1

+

+

CC54

CC54

@

@

330U_D2_2VM_R6M

330U_D2_2VM_R6M

2

2

+VCCSA_SENSE

1 2
1 2
1 2
1 2

470_0805_5%

470_0805_5%

SUSP

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2

VCC_AXG_SENSE 42
VSS_AXG_SENSE 42

0

0

1

11

Vgs=10V,Id=14.5A,Rds=6mohm

1

CC68

CC68
10U_0805_10V6K

10U_0805_10V6K

2

1 2
3

0.1U_0402_25V6

0.1U_0402_25V6

4

QC5B

QC5B

RC192

RC192

5

CC69

CC69

0

1

0

2

JUMP_43X118

JUMP_43X118
QC4

QC4

1

S

2

S

3

S

4

G

FDS6676AS_SO8

FDS6676AS_SO8

1

2

PJ1

@PJ1

@

112

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

12

RC194

RC194
820K_0402_5%

820K_0402_5%

+VCCSAVCCSA_VID0 VCCSA_VID1

0.90 V

0.80 V

0.75 V

0.65 V

+1.5VS+1.5V_CPU

+1.5V

C469

C469

4.7U_0805_10V4Z

4.7U_0805_10V4Z

61

1

For Sandy Bridge

C464

C464

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 2

C463

C463

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

RC193

RC193

1 2

220K_0402_5%

220K_0402_5%

QC5A

QC5A

SUSP

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+VSB

SUSP 5,34

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_POWER-2

Sandy Bridge_POWER-2

Sandy Bridge_POWER-2

QFKAA

QFKAA

QFKAA

1

948Tuesday, March 27, 2012

948Tuesday, March 27, 2012

948Tuesday, March 27, 2012

of

of

of

0.3

0.3

0.3

5

JCPUH

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

AR25
AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

AT3

AR7
AR4
AR2

AP7
AP4
AP1

AN7
AN4

AM7
AM4
AM3
AM2
AM1

AK7
AK4

VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

D D

C C

B B

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

JCPUI

JCPUI

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

4

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

3

JCPUE

JCPUE

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

CFG4

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE
@

@

CFG

CFG

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7

RESERVED

RESERVED

RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

T3PAD T3PAD

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

CFG4

Embedded Display Port Presence Strap

CFG4

T64PAD T64PAD

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1

1: Normal Operation; Lane # definition matches
socket pin map definition

*

0:Lane Reversed

12

RC82

RC82
1K_0402_1%

1K_0402_1%
@

@

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB
de assertion

CFG7

0: PEG Wait for BIOS for training

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

Sandy Bridge_GND/RSVD/CFG

Sandy Bridge_GND/RSVD/CFG

QFKAA

QFKAA

QFKAA

1

of

of

of

10 48Tuesday, March 27, 2012

10 48Tuesday, March 27, 2012

10 48Tuesday, March 27, 2012

0.3

0.3

0.3

5

+VREF_DQA

1

CD2

CD2

CD1

CD1

0.1U_0402_10V7K

0.1U_0402_10V7K
2

D D

Close to JDDRL.1

C C

B B

A A

+3VS

CD25

CD25

DDR_A_BS27

DDRA_CLK07
DDRA_CLK0#7

DDR_A_BS07

DDR_A_WE#7

DDR_A_CAS#7

DDRA_SCS1#7

1
CD26

CD26

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

DDR_A_D0
DDR_A_D1

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
DDRA_CLK0

DDRA_CLK0#
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

RD8

RD8

1 2

10K_0402_5%

10K_0402_5%

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

5

+0.75VS

12

RD9

RD9
10K_0402_5%

10K_0402_5%

+1.5V

JDDR3L

JDDR3L

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103
@

@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD
RAS#

VDD
ODT0

VDD
ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

GND2

BOSS2

A15
A14

A11

CK1

BA1

S0#

SCL
VTT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122

NC

124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

+1.5V

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

SM_DRAMRST#
DDR_A_D14

DDR_A_D15
DDR_A_D20

DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDRA_CKE1
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDRA_CLK1

DDRA_CLK1#
DDR_A_BS1

DDR_A_RAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_ODT1

+VREF_CAA
DDR_A_D36

DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PM_SMBDATA
PM_SMBCLK

+0.75VS

4

DDR3 SO-DIMM A
Reverse Type

SM_DRAMRST# 7,12

DDRA_CKE1 7DDRA_CKE07

DDRA_CLK1 7
DDRA_CLK1# 7

DDR_A_BS1 7
DDR_A_RAS# 7

DDRA_SCS0# 7
DDRA_ODT0 7

DDRA_ODT1 7

+VREF_CAA_DIMMA

1

1

CD16

CD16

CD15

CD15

close to JDDRL.126

PM_SMBDATA 12,17,26
PM_SMBCLK 12,17,26

4

0.1U_0402_10V7K

0.1U_0402_10V7K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Intel DDR Vref M3

+VREF_DQA_M3

+VREF_DQB_M3

13

D

D

QC9

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

+1.5V

12

12

+1.5V

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

3

QC9

S

S

RD6

RD6

1K_0402_1%

1K_0402_1%

RD7

RD7

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRL

CD7 co-lay with CD14

+

+

1 2

CD14 330U_D2_2V_Y

CD14 330U_D2_2V_Y

+

+

@

@

1 2

CD7 330U_2.5V_M

CD7 330U_2.5V_M

CD8 10U_0603_6.3V6MCD8 10U_0603_6.3V6M

1 2

CD9 10U_0603_6.3V6MCD9 10U_0603_6.3V6M

1 2

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

1 2

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

1 2

CD12 10U_0603_6.3V6MCD12 10U_0603_6.3V6M

1 2

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

DDR_A_DQS[0..7] 7
DDR_A_DQS#[0..7] 7

DDR_A_D[0..63] 7
DDR_A_MA[0..15] 7

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

2

G

G

+1.5V

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

Deciphered Date

Deciphered Date

Deciphered Date

2

@

@

12

0_0402_5%

0_0402_5%

RC115

RC115

QC7

QC7

D

S

D

S

13

G

G

2

RH100

RH100

10K_0402_5%

10K_0402_5%

G

G

2

13

D

S

D

S

QC8

QC8

@

@

12

0_0402_5%

0_0402_5%

RC116

RC116

H_SNB_IVB# 5,21

1 2

CD50 33P_0402_50V8KCD50 33P_0402_50V8K

1 2

CD51 33P_0402_50V8KCD51 33P_0402_50V8K

1 2

CD52 33P_0402_50V8KCD52 33P_0402_50V8K

1 2

CD53 33P_0402_50V8KCD53 33P_0402_50V8K

1 2

CD54 33P_0402_50V8KCD54 33P_0402_50V8K

1 2

CD55 33P_0402_50V8KCD55 33P_0402_50V8K

+1.5V +0.75VS

CD20 0.1U_0402_10V7KCD20 0.1U_0402_10V7K

1 2

CD17 0.1U_0402_10V7KCD17 0.1U_0402_10V7K

1 2

CD18 0.1U_0402_10V7KCD18 0.1U_0402_10V7K

1 2

CD19 0.1U_0402_10V7KCD19 0.1U_0402_10V7K

1 2

2

+VREF_DQA

12

DRAMRST_CNTRL_PCH 7,17

+VREF_DQB

+VREF_DQA

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1

+1.5V

12

RD1

RD1

1K_0402_1%

1K_0402_1%

12

RD2

RD2

1K_0402_1%

1K_0402_1%

+1.5V

12

RD10

RD10

1K_0402_1%

1K_0402_1%

+VREF_DQB

12

RD11

RD11

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRL1.203 and 204

CD56 10U_0603_6.3V6MCD56 10U_0603_6.3V6M

1 2

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K

12

CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K

12

CD22 1U_0402_6.3V6KCD22 1U_0402_6.3V6K

12

CD23 1U_0402_6.3V6KCD23 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII-SODIMM0

DDRIII-SODIMM0

DDRIII-SODIMM0

QFKAA

QFKAA

QFKAA

1

0.3

0.3

11 48Tuesday, March 27, 2012

11 48Tuesday, March 27, 2012

11 48Tuesday, March 27, 2012

0.3

of

of

of

A

+VREF_DQB

1

CD28

CD28

CD27

CD27

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1 1

2

Close to JDDRH.1

DDRB_CKE07

2 2

3 3

4 4

+3VS

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
@

@
CD48

CD48

DDR_B_BS27

DDRB_CLK07
DDRB_CLK0#7

DDR_B_WE#7
DDR_B_CAS#7

DDRB_SCS1#7

1

2

1

CD49

CD49

2

0.1U_0402_10V7K

0.1U_0402_10V7K

DDR_B_D0
DDR_B_D1

1

DDR_B_D2
DDR_B_D3

0.1U_0402_10V7K

0.1U_0402_10V7K
2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDRB_CKE0

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
DDRB_CLK0

DDRB_CLK0#
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDRB_SCS1#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50 DDR_B_D55
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

RD14

RD14

1 2

10K_0402_5%

10K_0402_5%

RD15

RD15

1 2

10K_0402_5%

10K_0402_5%

A

+0.75VS

+1.5V

JDDR3H

JDDR3H

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

GND1
GND2

VREF_CA

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

FOX_AS0A626-UASN-7F_204P

FOX_AS0A626-UASN-7F_204P
@

@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD
RAS#

VDD
ODT0

VDD
ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

BOSS1
BOSS2

A15
A14

A11

CK1

BA1

S0#

SCL
VTT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122

NC

124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

B

+1.5V

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

SM_DRAMRST#
DDR_B_D14

DDR_B_D15
DDR_B_D20

DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDRB_CKE1
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
DDRB_CLK1

DDRB_CLK1#
DDR_B_BS1

DDR_B_RAS#
DDRB_SCS0#

DDRB_ODT0
DDRB_ODT1

+VREF_CAB +VREF_CAB_DIMMB
DDR_B_D36

DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PM_SMBDATA
PM_SMBCLK

+0.75VS

B

SM_DRAMRST# 7,11

DDRB_CKE1 7

DDRB_CLK1 7
DDRB_CLK1# 7

DDR_B_BS1 7
DDR_B_RAS# 7DDR_B_BS07

DDRB_SCS0# 7
DDRB_ODT0 7

DDRB_ODT1 7

CD46

CD46

Close to JDDRH.126

PM_SMBDATA 11,17,26
PM_SMBCLK 11,17,26

Reverse Type
DDR3 SO-DIMM B

1

1

CD47

CD47

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

0.1U_0402_10V7K

0.1U_0402_10V7K

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7] 7
DDR_B_DQS[0..7] 7
DDR_B_D[0..63] 7
DDR_B_MA[0..15] 7

+1.5V

12

RD12

RD12

1K_0402_1%

1K_0402_1%

12

RD13

RD13

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRH

+1.5V

C

@

@

+

+

CD31 330U_B2_2.5VM_R15M

CD31 330U_B2_2.5VM_R15M

1 2

CD41 10U_0603_6.3V6MCD41 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M

1 2

CD37 10U_0603_6.3V6MCD37 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M

1 2

CD39 10U_0603_6.3V6MCD39 10U_0603_6.3V6M

1 2

CD40 10U_0603_6.3V6MCD40 10U_0603_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

D

CD33 0.1U_0402_10V7KCD33 0.1U_0402_10V7K

1 2

CD29 0.1U_0402_10V7KCD29 0.1U_0402_10V7K

1 2

CD30 0.1U_0402_10V7KCD30 0.1U_0402_10V7K

1 2

CD32 0.1U_0402_10V7KCD32 0.1U_0402_10V7K

1 2

D

E

Layout Note:
Place near JDDRH.203 and 204

+0.75VS+1.5V

CD57 10U_0603_6.3V6MCD57 10U_0603_6.3V6M

1 2

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

12

CD43 1U_0402_6.3V6KCD43 1U_0402_6.3V6K

12

CD44 1U_0402_6.3V6KCD44 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM1

DDRIII-SODIMM1

DDRIII-SODIMM1

QFKAA

QFKAA

QFKAA

12 48Tuesday, March 27, 2012

12 48Tuesday, March 27, 2012

12 48Tuesday, March 27, 2012

E

of

of

of

0.3

0.3

0.3

A

LCD_TXOUT0+19

LCD_TXOUT0-19

LCD_TXOUT1+19

LCD_TXOUT1-19

LCD_TXOUT2+19

1 1

2 2

3 3

ACES_87036-1001-CP

ACES_87036-1001-CP

LCD_TXOUT2-19
LCD_TXCLK+19
LCD_TXCLK-19

LCD_EDID_CLK19
LCD_EDID_DATA19

JLVDS

JLVDS

31
32
33
34
35
36

STARC_107K30-000001-G2

STARC_107K30-000001-G2

JLVDS1

JLVDS1

GND1
GND2
GND3
GND4
GND5
GND6

GND
GND

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1 2

R388 0_0603_5%

R388 0_0603_5%

LCD_TZOUT0­LCD_TZOUT0+
LCD_TZOUT1­LCD_TZOUT1+
LCD_TZOUT2­LCD_TZOUT2+
LCD_TZCLK­LCD_TZCLK+

+3VS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

12
11
10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

@

@

LCD_EDID_CLK
LCD_EDID_DATA

CAM@

CAM@

+3VS_LVDS_CAM

USB20_N11_R
USB20_P11_R

INT_MIC_CLK
INT_MIC_DATA

LCD_EDID_CLK
LCD_EDID_DATA

LCD_TXOUT0­LCD_TXOUT0+

LCD_TXOUT1­LCD_TXOUT1+

LCD_TXOUT2­LCD_TXOUT2+

LCD_TXCLK­LCD_TXCLK+
LED_PWM
BKOFF#_R

1 2

C257 47P_0402_50V8J

C257 47P_0402_50V8J

LVDS cable JLVDS1.2 need to contact GND

B

LCD_TXOUT0+
LCD_TXOUT0­LCD_TXOUT1+
LCD_TXOUT1-

LCD_TXOUT2+

LCD_TXOUT2­LCD_TXCLK+
LCD_TXCLK-

W=20mils

1.5A

+LCD_INV

@

@

LVDS_SEL 17

+LCD_INV

C234

C234

68P_0402_50V8J

68P_0402_50V8J

LCD_TZOUT0+19

LCD_TZOUT0-19

LCD_TZOUT1+19

LCD_TZOUT1-19

LCD_TZOUT2+19
LCD_TZOUT2-19
LCD_TZCLK+19

LCD_TZCLK-19

@

For RF

1

2

@

C256 47P_0402_50V8J

C256 47P_0402_50V8J

1 2

CAM@

CAM@

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

C225

C225

2
3

D84 AZ5125-02S.R7G_SOT23-3

D84 AZ5125-02S.R7G_SOT23-3

@

@

+3VS

C248

C248

0.1U_0402_10V7K

0.1U_0402_10V7K

L2

L2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

1

C235

C235

0.1U_0402_25V6

0.1U_0402_25V6

2

2

1

INT_MIC_CLK 30

INT_MIC_DATA 30

1

C226

C226

0.1U_0402_10V7K

0.1U_0402_10V7K

2

LED_PWM

BKOFF#_R

12

B+

C

1

2

1 2

12

R131

R131
47K_0402_5%

47K_0402_5%

1 2

12

R113

R113
10K_0402_5%

10K_0402_5%

C247

C247

LCD_TZOUT0+
LCD_TZOUT0­LCD_TZOUT1+
LCD_TZOUT1-

LCD_TZOUT2+

LCD_TZOUT2­LCD_TZCLK+
LCD_TZCLK-

2A

C227

C227

4.7U_0805_10V4Z

4.7U_0805_10V4Z

D17 RB751V40_SC76-2D17 RB751V40_SC76-2

D15 RB751V40_SC76-2D15 RB751V40_SC76-2

12

For EMI1.5A

C269

C269

@

@

0.1U_0402_25V6

0.1U_0402_25V6

1

2

1

@

@

2

C258

C258
47P_0402_50V8J

47P_0402_50V8J
@

@

For RF

1

C489

C489

@

@

2

0.1U_0402_25V6

0.1U_0402_25V6

D

+LCD_VDD

PCH_PWM 19

BKOFF# 31

B+

C490

C490

@

@

0.1U_0402_25V6

0.1U_0402_25V6

1

2

0.1U_0402_25V6

0.1U_0402_25V6

UMA_ENVDD19

USB20_P11_R

USB20_N11_R

E

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Reserve for EMI request

1 2

R78 0_0402_5%CAM@R78 0_0402_5%CAM@
WCM-2012-900T_0805

WCM-2012-900T_0805

4

4

1

1

L55

@L55

@

1 2

R96 0_0402_5%CAM@R96 0_0402_5%CAM@

100_0805_5%

100_0805_5%

3

3

2

2

F

+LCD_VDD

R109

R109

Q1A

Q1A

12

100K_0402_5%

100K_0402_5%

61

2

R112

R112
100K_0402_5%

100K_0402_5%

1 2

USB20_P11 20

USB20_N11 20

+3VALW

12

R108

R108

3

5

Q1B

Q1B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

0.047U_0402_25V7K

0.047U_0402_25V7K
LCDPWR_GATE

R110

R110

1 2

68K_0402_5%

68K_0402_5%

4700P_0402_25V7K

4700P_0402_25V7K

G

+3VS

C228

C228

C230

C230

1

2
1

2

2

G

G

W=80mils

S

S

Q17

Q17
AO3413_SOT23

AO3413_SOT23

D

D

1 3

+LCD_VDD

1

2

H

W=80mils

C233

C233

0.1U_0402_10V7K

0.1U_0402_10V7K

4 4

A

B

C

Security Classification

Security Classification

Security Classification

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

E

F

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

LVDS/eDP

LVDS/eDP

LVDS/eDP

QFKAA

QFKAA

QFKAA

G

13 48Tuesday, March 27, 2012

13 48Tuesday, March 27, 2012

13 48Tuesday, March 27, 2012

of

of

of

H

0.3

0.3

0.3

A

B

C

D

E

CRT CONNECTOR

1 1

CRT_R_R
CRT_G_R
CRT_B_R

C238

C238

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

C251

C251

@

@

1 2

R189 0_0402_5%R189 0_0402_5%

1 2

R190 0_0402_5%R190 0_0402_5%

1 2

R191 0_0402_5%R191 0_0402_5%

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

UMA_CRT_R19

UMA_CRT_G19

UMA_CRT_B19

R139

R139

R138

R138

12

12

150_0402_1%

150_0402_1%

R140

R140

12

150_0402_1%

150_0402_1%

150_0402_1%

150_0402_1%

C249

C249

@

@

1

C250

C250

@

@

2

2.2P_0402_50V8C

2.2P_0402_50V8C

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

L3 NBQ100505T-800Y_0402L3 NBQ100505T-800Y_0402

1 2

L4 NBQ100505T-800Y_0402L4 NBQ100505T-800Y_0402

1 2

L5 NBQ100505T-800Y_0402L5 NBQ100505T-800Y_0402

1 2

1

1

C240

C240

C239

C239

2

2.2P_0402_50V8C

2.2P_0402_50V8C

2

2.2P_0402_50V8C

2.2P_0402_50V8C

C241

C241

1

C242

C242

2

2.2P_0402_50V8C

2.2P_0402_50V8C

1

C243

C243

2

2.2P_0402_50V8C

2.2P_0402_50V8C

1

2

CRT_R_L
CRT_G_L

2.2P_0402_50V8C

2.2P_0402_50V8C

CRT_B_L

+5VS +CRT_VCC_R +CRT_VCC

By EMI demand

+CRT_VCC

2 2

UMA_CRT_HSYNC19

UMA_CRT_VSYNC19

1 2

C244 0.1U_0402_10V7KC244 0.1U_0402_10V7K

SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

5

P

A2Y

G

3

1

OE#

U6

U6

4

+CRT_VCC

1 2

C252

C252

0.1U_0402_10V7K

0.1U_0402_10V7K

SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

R141 10K_0402_5%R141 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U7

U7

3

12

D_CRT_HSYNC

D_CRT_VSYNC

1 2

L6 10_0402_5%L6 10_0402_5%

1 2

L7 10_0402_5%L7 10_0402_5%

C245

C245
@

@

1

2

10P_0402_50V8J

10P_0402_50V8J

If=1A

D6

D6

2

RB491D_SOT23-3

RB491D_SOT23-3

3

+CRT_VCC

CHP3_SERDBG21

HSYNC

VSYNC

1

C246

C246
@

@

2

10P_0402_50V8J

10P_0402_50V8J

F1

F1

1

0.5A_8V_KMC3S050RY

0.5A_8V_KMC3S050RY

CRT_R_L
CRT_DDC_DAT

CRT_G_L
HSYNC

CRT_B_L
VSYNC

CHP3_SERDBG
CRT_DDC_CLK

+CRT_VCC

CRT_G_L

CRT_DDC_CLK

40 mils

21

0.1U_0402_10V7K

0.1U_0402_10V7K

T65 PADT65 PAD

D98

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

AZC099-04S.R7G_SOT23-6

D97

6

I/O4

1

C237

C237

2

@

@

JCRT

JCRT

6

11

1
7

12

2
8

G

G

13

G

G

3
9

14

4
10
15

5

SUYIN_070546FR015S251ZR

SUYIN_070546FR015S251ZR
@

@

@D98

@

I/O2

GND

I/O1

@D97

@

I/O2

16
17

3

2

1

3

CRT_B_LCRT_R_L

CHP3_SERDBG

HSYNC

3 3

+CRT_VCC

+3VS

+CRT_VCC

CRT_DDC_DAT

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

AZC099-04S.R7G_SOT23-6

GND

I/O1

2

VSYNC

1

2/9: Add for ESD request

R159

@

@

1 2

1 2

1

1

2

2

R159

4.7K_0402_5%

4.7K_0402_5%

CRT_DDC_CLK

CRT_DDC_DAT

C283

C283
470P_0402_50V8J

470P_0402_50V8J
@

@

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

CRT

CRT

CRT

QFKAA

QFKAA

QFKAA

E

of

14 48Tuesday, March 27, 2012

of

14 48Tuesday, March 27, 2012

of

14 48Tuesday, March 27, 2012

0.3

0.3

0.3

R153

R153

4.7K_0402_5%

4.7K_0402_5%

2

Q205A

UMA_CRT_CLK19

UMA_CRT_DATA19

1

C282

C282

33P_0402_50V8K

33P_0402_50V8K

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

@

@

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

Q205A

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q205B

Q205B

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

C285

C285
33P_0402_50V8K

33P_0402_50V8K

2

@

@

61

3

470P_0402_50V8J

470P_0402_50V8J

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C284

C284

5

4

3

2

1

D D

+3VS

C C

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

UMA_DVI_TXC+
UMA_DVI_TXC­UMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1+

UMA_DVI_TXD1-

UMA_DVI_TXD2+

UMA_DVI_TXD2-

UMA_HDMI_CLK19

UMA_HDMI_DATA19

D95

D95

@

@

1

1

1

2

2

2

HDMI_R_D2-

HDMI_R_D0+ HDMI_R_D0+
HDMI_R_D0- HDMI_R_D0-

4

4

4

HDMI_R_D2+

5

3

3

3

8

8

AZ1045-04F_DFN2510P10E-10-9

AZ1045-04F_DFN2510P10E-10-9

D94

D94

@

@

1

1

1

2

2

2

4

4

4
5

3

3

3

8

8

AZ1045-04F_DFN2510P10E-10-9

AZ1045-04F_DFN2510P10E-10-9

HDMI_R_D1-HDMI_R_D1-

10

10

9

HDMI_R_D1+HDMI_R_D1+

9

9

8

HDMI_R_D2-

7

7

7

HDMI_R_D2+

65

65

6

HDMI_R_CK+HDMI_R_CK+

10

10

9

HDMI_R_CK-HDMI_R_CK-

9

9

8

7

7

7

65

65

6

3 1

BSH111_SOT23-3

BSH111_SOT23-3

+HDMI_5V_OUT

2/9: Add for ESD request

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

3 1

2

SGD

SGD

BSH111_SOT23-3

BSH111_SOT23-3

SGD

SGD

Q19

Q19

HDMI@

HDMI@

HDMI_R_CK+
HDMI_R_CK­HDMI_R_D1­HDMI_R_D1+
HDMI_R_D0+

HDMI_R_D0­HDMI_R_D2-

HDMI_R_D2+

+5VS

HDMI_HPD_C

+5VS

2/9: Add for ESD request

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

CV308 0.1U_0402_10V7K HDMI@CV308 0.1U_0402_10V7K HDMI@

UMA_HDMI_TXC+19

UMA_HDMI_TXC-19
UMA_HDMI_TX0+19

UMA_HDMI_TX0-19

UMA_HDMI_TX1+19

UMA_HDMI_TX1-19

UMA_HDMI_TX2+19

UMA_HDMI_TX2-19

UMA_DVI_TXC-

B B

A A

UMA_DVI_TXC+

UMA_DVI_TXD0-

UMA_DVI_TXD0+

UMA_DVI_TXD1-

UMA_DVI_TXD1+

UMA_DVI_TXD2-

UMA_DVI_TXD2+

5

1 2

CV304 0.1U_0402_10V7K HDMI@CV304 0.1U_0402_10V7K HDMI@

1 2

CV306 0.1U_0402_10V7K HDMI@CV306 0.1U_0402_10V7K HDMI@

1 2

CV302 0.1U_0402_10V7K HDMI@CV302 0.1U_0402_10V7K HDMI@

1 2

CV303 0.1U_0402_10V7K HDMI@CV303 0.1U_0402_10V7K HDMI@

1 2

CV301 0.1U_0402_10V7K HDMI@CV301 0.1U_0402_10V7K HDMI@

1 2

CV307 0.1U_0402_10V7K HDMI@CV307 0.1U_0402_10V7K HDMI@

1 2

CV305 0.1U_0402_10V7K HDMI@CV305 0.1U_0402_10V7K HDMI@

1 2

@

@

1 2

R157 0_0402_5%

R157 0_0402_5%
L8

HDMI@L8

HDMI@

1

1

4

4

WCM-2012HS-670T_0805

WCM-2012HS-670T_0805

1 2

R173 0_0402_5%

R173 0_0402_5%

1 2

R175 0_0402_5%

R175 0_0402_5%
L9

3

3

2

2

WCM-2012HS-670T_0805

WCM-2012HS-670T_0805

1 2

R180 0_0402_5%

R180 0_0402_5%

1 2

R182 0_0402_5%

R182 0_0402_5%
L10

1

1

4

4

WCM-2012HS-670T_0805

WCM-2012HS-670T_0805

1 2

R183 0_0402_5%

R183 0_0402_5%

1 2

R187 0_0402_5%

R187 0_0402_5%
L11

3

3

2

2

WCM-2012HS-670T_0805

WCM-2012HS-670T_0805

1 2

R188 0_0402_5%

R188 0_0402_5%

@

@

@

@

@

@

@

@

@

@

@

@

@

@

HDMI@L9

HDMI@

HDMI@L10

HDMI@

HDMI@L11

HDMI@

2

2

3

3

4

4

1

1

2

2

3

3

4

4

1

1

+HDMI_5V_OUT

R184

R184

2.2K_0402_5%

2.2K_0402_5%
HDMI@

HDMI@

Q18

Q18

HDMI@

HDMI@

HDMI@

HDMI@

1 2

R195 680_0402_1%

R195 680_0402_1%

HDMI@

HDMI@

1 2

R197 680_0402_1%

R197 680_0402_1%

HDMI@

HDMI@

1 2

R198 680_0402_1%

R198 680_0402_1%

HDMI@

HDMI@

1 2

R202 680_0402_1%

R202 680_0402_1%

HDMI@

HDMI@

1 2

R201 680_0402_1%

R201 680_0402_1%

HDMI@

HDMI@

1 2

R203 680_0402_1%

R203 680_0402_1%

HDMI@

HDMI@

1 2

R205 680_0402_1%

R205 680_0402_1%

HDMI@

HDMI@

1 2

R206 680_0402_1%

R206 680_0402_1%

D96

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

AZC099-04S.R7G_SOT23-6

12

12

R185

R185

2.2K_0402_5%

2.2K_0402_5%
HDMI@

HDMI@

HDMI_SCLK

HDMI_SDATA

13

D

D

2

G

G

S

S

@D96

@

3

I/O2

2

GND

1

I/O1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Q24

Q24
2N7002_SOT23-3

2N7002_SOT23-3
HDMI@

HDMI@

HDMI_SDATA

HDMI_SCLK

2

C264

C264

0.1U_0402_10V7K

0.1U_0402_10V7K
HDMI@

HDMI@

PMEG2010AEH_SOD123

PMEG2010AEH_SOD123

2

1

HDMI@

HDMI@

D53

D53

2 1

+HDMI_5V_OUT

1

5

U9

U9

P

OE#

A2Y

G

SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5
HDMI@

HDMI@

3

HDMI_HPD

+HDMI_5V_OUT_F

1 2

1K_0402_5%

1K_0402_5%

HDMI_HPD

4

0.5A_8V_KMC3S050RY

0.5A_8V_KMC3S050RY

HDMI@

HDMI@
R145

R145

100K_0402_5%

100K_0402_5%

HDMI@

HDMI@

HDMI@

HDMI@

R571

R571

2.2K_0402_5%

2.2K_0402_5%

F2

F2

21

HDMI@

HDMI@

R186

R186

1 2

12

+3VS

1

C259

C259
HDMI@

HDMI@

0.1U_0402_10V7K

0.1U_0402_10V7K

2

HDMI_HPD_CHDMI_HPD_U

2

1

+HDMI_5V_OUT+5VS

HDMI Connector

JHDMI

+HDMI_5V_OUT

HDMI_HPD_C

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11
10

HDMI Conn./CEC

HDMI Conn./CEC

HDMI Conn./CEC

QFKAA

QFKAA

QFKAA

GND

CK_shield

GND

CK+

GND

9

D0-

GND

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

HONGL_13-13201904CP

HONGL_13-13201904CP
@

@

1

C265

C265

0.1U_0402_10V7K

0.1U_0402_10V7K
HDMI@

HDMI@

HDMI_HPD 19

20
21
22
23

15 48Tuesday, March 27, 2012

15 48Tuesday, March 27, 2012

15 48Tuesday, March 27, 2012

0.3

0.3

0.3

of

of

of