COMPAL LA-8862P Schematics

A

1 1

B

C

D

E

QCLA4,5

2 2

Eureka 14" & 15"

LA-8862P SchematicREV 0.2

3 3

Intel Processor(Ivy Bridge / Sandy Bridge) PCH(Panther Point)

2011-11-24 Rev 0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/01/31 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

B

Cover Page

QCLA4,5

0.2

1 48Thursday, February 16, 2012

E

0.2

A

B

C

D

E

Intel CPU Ivy Bridge

1 1

eDP Conn.

page 13

Sandy Bridge

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

CRT

page 14

LVDS Conn.

page 13

2 2

EC SMBus

HDMI-CEC

page 15

HDMI Conn.

page 15

FDI X8

2.7GT/s

Intel PCH Panther Point

RJ45

page 40

3 3

RTL8105E-VD 10/100M RTL8111F-VB 1G

PCIe port 1

Cardreader RTS5229

PCIe port4

SPI ROM (4MB + 2MB)

RTC CKT.

page 16

DC/DC Interface CKT.

page 38

4 4

Power Circuit DC/DC

page 39,40,41,42,43, 44,45,46,47,48,49

Power On/Off CKT.

page 37

A

Finger Printer/B

page 26

Power/B

page 37

page 16

Touch Pad

page 37

B

page 31

page 29

PCIe Gen1 1x

1.5V 5GT/s

PCIe Gen1 1x

1.5V 5GT/s

Debug Port

page 36

Int.KBD

page 36

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

ENE KB930/KB9012

EC ROM (128KB)

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 36

Issued Date

CIR

C

DMI X4

5GT/s

USB30 4x

5V 5GT/s

USB20 4x

5V 480MHz

USB20 3x

5V 480MHz

USB20 3x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 port 1

5V 6GHz(600MB/s)

SATA Gen3 port 0

SATA port 2

5V 3GHz(300MB/s)

PCIe Gen2 2x

page 36

1.5V 5GT/s

HDA Codec

ALC280

page 33

SPK Conn

page 34

page 35

HD Audio

3.3V 24MHz

G-Sensor

EC SMBus

Compal Secret Data

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

USB Right

USB20 port 2,3 USB30 port 3,4 USB30 port 1,2

page 25

USB Left

USB20 port 0,1

page 30

FingerPrinter Int. Camera

USB port 8

page 29

PCIeMini Card WiMax

USB port 9

page 27 page 27

PCIeMini Card WLAN

PCIe port 2

page 27

5V 6GHz(600MB/s)

SATA ODD

SATA port 2

page 23

USB3.0 Right-side UPD720202

PCIe port5

page 31

USB port 11

page 13

PCIeMini Card

3G/TV#1 TV#2

mSATA

SATA HDD

JPIO (HP & MIC)

page 34

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

USB port 12 USB port 10

SATA port 1

page 27

SATA port 0

page 23

USB3.0 Left-side UPD720202

PCIe port6

page 32

Compal Electronics, Inc.

Block Diagram

QCLA4,5

E

B-CAS

page 26

2 48Thursday, February 16, 2012

SIM

page 27

0.2

5

B+

Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A

SY8033BDBC

D D

N-CHANNEL

SI4800

TPS51125

SY8036

C C

VCCPPWRGD

SY8037

LNB EN

APW7137

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

B B

VR_ON

N-CHANNEL

SI4800

NCP6132A

SUSP#

TPS51212

Ipeak=14A, Imax=9.8A, Iocp min=16.92A

SUSP#

SUSP

4

SYSON

Ipeak=6A, Imax=4.2A, Iocp min=8A

Ipeak=6A, Imax=4.A, Iocp min=8

Imax=0.3A, Iocp min=0.8A

BCPWON

P-CHANNEL

AO-3413

KB_LED

P-CHANNEL

AO-3413

+5VS

LDO

G9191

ODD_EN#

P-CHANNEL

AO-3413

N-CHANNEL

FDS6676AS

N-CHANNEL

FDS6676AS

0.75VR_EN#

G2992

WOL_EN

P-CHANNEL

AO-3413

P-CHANNEL

AO-3415

FELICA_PWR

P-CHANNEL

AO-3413

SUSP

UMA_ENVDD

3

DESIGN CURRENT 0.1A

DESIGN CURRENT 11A

DESIGN CURRENT 1.8A

DESIGN CURRENT 6.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.4A

DESIGN CURRENT 0.3A

DESIGN CURRENT 1.6A

DESIGN CURRENT 13.5A

DESIGN CURRENT 5A

DESIGN CURRENT 1.5A

DESIGN CURRENT 1A

DESIGN CURRENT 6A

DESIGN CURRENT 0.3A

DESIGN CURRENT 7.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 6A

DESIGN CURRENT 2A

DESIGN CURRENT 0.1A

DESIGN CURRENT 94A

DESIGN CURRENT 50A

DESIGN CURRENT 15A

+3VL +5VL

+5VALW

+1.8VS

+5VS

+5VS_L_BCAS

+5VS_LED

+3VS_HDP

+5VS_ODD

+1.5V

+1.5V_CPU

+1.5VS

+0.75VS

+VCCSA

+16VS

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+FLICA_VCC

+CPU_CORE

+GFX_CORE

+1.05VS_VCCP

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Power Tree

QFKAA

0.2

3 48Thursday, February 16, 2012

1

A

B

C

D

E

Voltage Rails

1 1

State

S0

S1

2 2

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

power plane

+5VL

B+

O

X

+3VL

+5VALW

+3VALW

+VSB

O

X

O

X

+5VS

+1.5V

+3VS

+1.8VS

+1.5VS

+1.05VS

+0.75VS

+CPU_CORE

+VGA_CORE

+GFX_CORE

+VTT

+VRAM_1.5VS

+3VS_DGPU

+1.05VS_DGPU

O

X X

X

X X

BTO Option Table

Function

description

explain

BTO

Function

OO

X

description

explain

BTO

HDMI

HDMI@

SPI ROM

WIN8

WIN8@

Digital MIC

Green CLK

GCLK@

Camera & Mic

CAM@

NOGCLK

NOGCLK@

Analog MIC

AMIC@

USB 3.0

Internal

IUSB30@

TPM

SLB 9635

TPM9635@ TPM9655@

Sleep & Charge

SLB 9655

10/100M Giga

8105ELDO@ 8111FVB@

MINI PCI-E SLOT

Half Card

WIMAX

WIMAX@

LAN

X

PCH SM Bus Address

HEX

Device

Power

DDR SO-DIMM 0

+3VS

DDR SO-DIMM 1

+3VS

3 3

Clock Generator

+3VS

New Card

+3VS

WLAN/WIMAX

+3VS

+3VS Clock Generator

3G+3VS

EC SM Bus1 Address

Device Address Address

+3VL

4 4

+3VL Cap. Sensor Virtual I2C

HEX HEX

16 H

HEXDevice AddressPower

A

A0 H

D2 H

0001 0110 bSmart Battery

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

EC SM Bus2 Address

Device

PowerPower

+3VS

NVIDIA GPUHDMI-CEC 34 H 0011 0100 b 1001 1010 b

+3VS

G-Sensor

+3VS

+3VS Light Sensor

B

96 H

9A H

40 H

52 H

STATE

Full ON

S1(Power On Suspend)

1001 0110 bPCH

0100 0000 b

0101 0010 b

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

2010/09/03 2012/12/31

C

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

Compal Secret Data

Deciphered Date

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

QFKAA

4 48Thursday, February 16, 2012

E

0.2

5

@

12

PM_DRAM_PWRGD_ R

CC631000P_0402_ 50V7K@CC631000P_0402_ 50V7K

@

12

H_PWRGOOD_R

CC621000P_0402_ 50V7K@CC621000P_0402_ 50V7K

D D

+1.05VS_VCCP

12

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402 _5%

12

C C

+3VALW_PCH

B B

12

RC11 200_0402_5%RC11 200_0402_5%

+3VS

PM_PWROK18,31

DRAMPWROK18

H_PROCHOT#

H_PWRGOOD

@

12

CC701000P_0402_ 50V7K@CC701000P_0402_ 50V7K

@

12

CC711000P_0402_ 50V7K@CC711000P_0402_ 50V7K

@

CC661000P_0402_ 50V7K@CC661000P_0402_ 50V7K

12

H_PECI

H_PM_SYNC

BUF_CPU_RST#

Please place near JCPU

+3VALW_PCH

DRAMPWROK

0.1U_0402_10V7K

12

RC181 0_04 02_5%@RC181 0_04 02_5%@

1

B

2

A

1 2

SUSP9,34

0.1U_0402_10V7K

UC1

5

74AHC1G09GW _TSSOP5

P

O

G

3

10K_0402_5%

RC13

1 2

RC12 0_0402_5%@RC12 0_0402_5%@

12

CC33

4

PM_SYS_PWRGD_BUF

SUSP

12

RC25

RC25 39_0402_5%

39_0402_5%

@

13

D

2

G

S

H_SNB_IVB#11,21

H_PROCHOT#31

H_THERMTRIP#21

H_PM_SYNC18

H_PWRGOOD21

+1.5V_CPU

12

QC2

QC2 2N7002_SOT23

2N7002_SOT23

@

H_PECI31

RC14

RC14 200_0402_5%

200_0402_5%

4

T1 PADT1 PAD

T2 PADT2 PAD

1 2

RC58 130_0402_5%RC58 130_0402_5%

RC159

RC187

BUF_CPU_RST#

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

H_PWRGOOD_R

0_0402_5%

PM_DRAM_PWRGD_ RPM_SYS_PWRGD_BUF

JCPUB

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

@

3

100 MHz

A28

CLK_CPU_DMI

BCLK

A27

CLK_CPU_DMI#

BCLK#

120 MHz

A16

CLK_CPU_EDP

A15

CLK_CPU_EDP#

R8

H_DRAMRST#

AK1

SM_RCOMP_0

A5

SM_RCOMP_1

A4

SM_RCOMP_2

AP29

PRDY#

AP27

PREQ#

AR26

XDP_TCK_R

TCK

AR27

XDP_TMS_R

TMS

AP30

XDP_TRST#_R

TRST#

AR28

XDP_TDI_R

TDI

AP26

XDP_TDO_R

TDO

Layout request for test point

AL35

DBR#

AT28

BPM#[0]

AR29

BPM#[1]

AR30

BPM#[2]

AT30

BPM#[3]

AP32

BPM#[4]

AR31

BPM#[5]

AT31

BPM#[6]

AR32

BPM#[7]

CLOCKS

DDR3

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

MISC

MISCTHERMALPWR MANAGEMENT

2

CLK_CPU_DMI 17 CLK_CPU_DMI# 17

H_DRAMRST# 7

12

RC56 140_0402_1%R C56 140_0402_1% RC59 25.5_0402_1%R C59 25.5_0402_1%

12 12

RC61 200_0402_1%R C61 200_0402_1%

T4PAD T4PAD T5PAD T5PAD

12

RC55 51_0402_5%RC55 51_0402_5%

T6PAD T6PAD T7PAD T7PAD

Stuff RC157 and RC158 if do not support eDP

CLK_CPU_EDP#

RC157 1K_04 02_5%RC157 1K_04 02_5%

CLK_CPU_EDP

RC158 1K_04 02_5%RC158 1K_04 02_5%

DDR3 Compensation Signals Layout Note:Place these resistors near Processor

H_DRAMRST#

CC34 180P_04 02_50V8J

by ESD requestion and place near CPU

1 2

@

1 2

1

+1.05VS_VCCP

FAN Control Circuit

Buffered Reset to CPU

+3VS

0.1U_0402_10V7K

1

CC36

PLT_RST# 20,26,27,28,31,32

UC2

1

PLT_RST#

A A

OE#

2

IN

3

GND

74AHC1G125GW _SOT353-5

VCC

OUT

+1.05VS_VCCP

2

12

RC38

RC38 75_0402_5%

5

4

BUFO_CPU_RST# BUF_CPU_R ST#

75_0402_5%

RC35

43_0402_1%

1 2

12

RC40

RC40 0_0402_5%

0_0402_5%

@

EN_DFAN131

+FAN2

10mil

+5VS

12

10U_0805_6.3V6M

1A

U1

1 2 3 4

APL5607KI-TRG_SO8

C17

EN VIN VOUT VSET

10U_0805_6.3V6M

8

GND

7

GND

6

GND

5

GND

C13

+FAN2

@

2

12

C15

1000P_0402_50V7K

1

1 2 3

4 5

ACES_85204-0300N

R24 1 0K_0402_5%R24 10K_0402_5%

FAN_SPEED1

1

C14

0.01U_0402_25V7K

@

2

JFAN

@JFAN

@

1 2 3

GND GND

12

+3VS

FAN_SPEED1 31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Sandy Bridge_JTAG/XDP/FAN

Size Document Number Rev

Custom

QFKAA

Date: Sheet of

2

Date: Sheet of

1

0.2

5 48Thursday, February 16, 2012

5

D D

C C

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

B B

+1.05VS_VCCP

DMI_PTX_CRX_N018 DMI_PTX_CRX_N118 DMI_PTX_CRX_N218 DMI_PTX_CRX_N318

DMI_PTX_CRX_P018 DMI_PTX_CRX_P118 DMI_PTX_CRX_P218 DMI_PTX_CRX_P318

DMI_CTX_PRX_N018 DMI_CTX_PRX_N118 DMI_CTX_PRX_N218 DMI_CTX_PRX_N318

DMI_CTX_PRX_P018 DMI_CTX_PRX_P118 DMI_CTX_PRX_P218 DMI_CTX_PRX_P318

FDI_CTX_PRX_N018 FDI_CTX_PRX_N118 FDI_CTX_PRX_N218 FDI_CTX_PRX_N318 FDI_CTX_PRX_N418 FDI_CTX_PRX_N518 FDI_CTX_PRX_N618 FDI_CTX_PRX_N718

FDI_CTX_PRX_P018 FDI_CTX_PRX_P118 FDI_CTX_PRX_P218 FDI_CTX_PRX_P318 FDI_CTX_PRX_P418 FDI_CTX_PRX_P518 FDI_CTX_PRX_P618 FDI_CTX_PRX_P718

FDI_FSYNC018 FDI_FSYNC118

FDI_INT18

FDI_LSYNC018 FDI_LSYNC118

1 2

RC2 24.9_0402_1%RC2 24.9_0402_1%

1 2

RC3 10K_0402_5%RC3 10K_0402_5%

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

Reserve RC3 for HW Review demand

EDP_COMP

H_EDP_HPD#

4

JCPUA

B27

DMI_RX#[0 ]

B25

DMI_RX#[1 ]

A25

DMI_RX#[2 ]

B24

DMI_RX#[3 ]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0 ]

H19

FDI0_TX#[1 ]

E19

FDI0_TX#[2 ]

F18

FDI0_TX#[3 ]

B21

FDI1_TX#[0 ]

C20

FDI1_TX#[1 ]

D18

FDI1_TX#[2 ]

E17

FDI1_TX#[3 ]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

@

3

PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP

shorted and routed with - max length = 500 m ils - typical

12

impedance = 43 m ohm (4 mils)

RC1

24.9_0402_1%

J22

PEG_ICOM PI

PEG_ICOM PO

PEG_RCOM PO

PEG_RX# [0] PEG_RX# [1] PEG_RX# [2] PEG_RX# [3] PEG_RX# [4] PEG_RX# [5] PEG_RX# [6] PEG_RX# [7]

DMI

PEG_RX# [8]

PEG_RX# [9] PEG_RX# [10] PEG_RX# [11] PEG_RX# [12] PEG_RX# [13] PEG_RX# [14] PEG_RX# [15]

PEG_RX[0 ] PEG_RX[1 ] PEG_RX[2 ] PEG_RX[3 ] PEG_RX[4 ] PEG_RX[5 ] PEG_RX[6 ] PEG_RX[7 ] PEG_RX[8 ]

PEG_RX[9 ] PEG_RX[1 0] PEG_RX[1 1] PEG_RX[1 2] PEG_RX[1 3] PEG_RX[1 4] PEG_RX[1 5]

PEG_TX#[0 ] PEG_TX#[1 ] PEG_TX#[2 ] PEG_TX#[3 ] PEG_TX#[4 ] PEG_TX#[5 ]

Intel(R) FDI

PEG_TX#[6 ] PEG_TX#[7 ] PEG_TX#[8 ] PEG_TX#[9 ]

PEG_TX#[1 0] PEG_TX#[1 1] PEG_TX#[1 2]

PCI EXPRESS* - GRAPHICS

PEG_TX#[1 3] PEG_TX#[1 4] PEG_TX#[1 5]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

eDP

PEG_TX[10 ] PEG_TX[11 ] PEG_TX[12 ] PEG_TX[13 ] PEG_TX[14 ] PEG_TX[15 ]

PEG_COMP

J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_ICOMPO signals should be routed w ith max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Custom

QFKAA

Sandy Bridge_DMI/PEG/FDI

6 48Thursday, February 16, 2012

1

0.2

5

JCPUC

DDR_A_D[0..63]11

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3

D D

C C

B B

DDR_A_BS011 DDR_A_BS111 DDR_A_BS211

DDR_A_CAS#1 1 DDR_A_RAS#1 1

DDR_A_WE#11

DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

JCPUC

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

4

DDR_B_D[0..63]12

AB6

DDRA_CLK0

SA_CLK[0]

AA6

SA_CLK#[0]

SA_CLK#[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

RSVD_TP[7] RSVD_TP[8]

RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

DDR SYSTEM MEMORY A

DDRA_CLK0#

V9

DDRA_CKE0

SA_CKE[0]

AA5

DDRA_CLK1 DDRB_CLK1

SA_CLK[1]

AB5

DDRA_CLK1# DDRB_CLK1#

V10

DDRA_CKE1 DDRB_CKE1

SA_CKE[1]

AB4 AA4 W9

AB3 AA3 W10

AK3

DDRA_SCS0# DDRB_SCS0#

SA_CS#[0]

AL3

DDRA_SCS1#

SA_CS#[1]

AG1 AH1

AH3

DDRA_ODT0 DDRB_ODT0

SA_ODT[0]

AG3

DDRA_ODT1

SA_ODT[1]

AG2 AH2

C4

DDR_A_DQS#0

G6

DDR_A_DQS#1

J3

DDR_A_DQS#2

M6

DDR_A_DQS#3

AL6

DDR_A_DQS#4

AM8

DDR_A_DQS#5

AR12

DDR_A_DQS#6

AM15

DDR_A_DQS#7

D4

DDR_A_DQS0

SA_DQS[0]

F6

DDR_A_DQS1

SA_DQS[1]

K3

DDR_A_DQS2

SA_DQS[2]

N6

DDR_A_DQS3

SA_DQS[3]

AL5

DDR_A_DQS4

SA_DQS[4]

AM9

DDR_A_DQS5

SA_DQS[5]

AR11

DDR_A_DQS6

SA_DQS[6]

AM14

DDR_A_DQS7

SA_DQS[7]

AD10

DDR_A_MA0

SA_MA[0]

W1

DDR_A_MA1

SA_MA[1]

W2

DDR_A_MA2

SA_MA[2]

W7

DDR_A_MA3

SA_MA[3]

V3

DDR_A_MA4

SA_MA[4]

V2

DDR_A_MA5

SA_MA[5]

W3

DDR_A_MA6

SA_MA[6]

W6

DDR_A_MA7

SA_MA[7]

V1

DDR_A_MA8

SA_MA[8]

W5

DDR_A_MA9

SA_MA[9]

AD8

DDR_A_MA10

SA_MA[10]

V4

DDR_A_MA11

SA_MA[11]

W4

DDR_A_MA12

SA_MA[12]

AF8

DDR_A_MA13

SA_MA[13]

V5

DDR_A_MA14

SA_MA[14]

V7

DDR_A_MA15

SA_MA[15]

DDRA_CLK0 11 DDRB_CLK0 12 DDRA_CLK0# 11 DDRA_CKE0 11 DDRB_CKE0 1 2

DDRA_CLK1 11 DDRA_CLK1# 11 DDRB_CLK1# 12 DDRA_CKE1 11

DDRA_SCS0# 11 DDRA_SCS1# 11 DDRB_SCS1# 12

DDRA_ODT0 11 DDRB_ODT0 12 DDRA_ODT1 11 DDRB_ODT1 12

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

3

JCPUD

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS012 DDR_B_BS112 DDR_B_BS212

DDR_B_CAS#1 2 DDR_B_RAS#1 2

DDR_B_WE#12

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

2

AE2

DDRB_CLK0

SB_CLK[0]

AD2

SB_CKE[0]

SB_CLK[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

SB_CLK#[0]

SB_CLK#[1]

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

DDRB_CLK0# 12

DDRB_CLK1 12

DDRB_CKE1 12

DDRB_SCS0# 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

DDR_B_MA[0..15] 12

1

TYCO_2013620-2_IVY BRIDGE

@

RC75

0_0402_5%

1 2

@

QC3

D

S

D

S

13

1 2

BSS138_NL_SOT23-3

G

2

1

CC37

0.047U_0402_25V6K

2

DDR3_DRAMRST#_RH_DRAMRST#

H_DRAMRST#5

A A

DRAMRST_CNTRL_PCH11,17

DRAMRST_CNTRL_EC31

RC73 0_0402_5%RC73 0 _0402_5%

RC74 0_0402_5%@RC74 0_0402 _5%@

5

1 2

4.99K_0402_1%

DRAMRST_CNTRL

RC78

1K_0402_5%

+1.5V

12

RC76

RC77

RC77 1K_0402_5%

1K_0402_5%

1 2

4

SM_DRAMRST# 11 ,12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TYCO_2013620-2_IVY BRIDGE

@

Compal Secret Data

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Sandy Bridge_DDR3

QFKAA

1

7 48Thursday, February 16, 2012

0.2

5

4

3

2

1

+CPU_CORE

D D

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26

C C

AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26

V35 V34

B B

V33 V32 V31 V30 V29 V28 V27

V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32

A A

P31 P30 P29 P28 P27 P26

POWER

JCPUF

97A

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

TYCO_2013620-2_IVY BRIDGE

@

CORE SUPPLY

5

PEG AND DDR

VSS_SENSE_VCCIO

SENSE LINES SVID

8.5A

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

+1.05VS_VCCP

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29

H_CPU_SVIDALRT#

AJ30

H_CPU_SVIDCLK

AJ28

H_CPU_SVIDDAT

AJ35

VCCSENSE_R

AJ34

VSSSENSE_R

B10

VCCIO_SENSE

A10

Close to CPU

0.1U_0402_10V7K

1 2

CC50

@

RC94 0_0402 _5%RC94 0_0402 _5% RC95 0_0402 _5%RC95 0_0402 _5%

12

RC96

RC96 10_0402_1%

10_0402_1%

12

RC91

RC91 130_0402_5%

130_0402_5%

1 2

RC90 43_040 2_1%RC90 43_0402_1%

1 2 1 2

RC88 0_0402 _5%RC88 0_0402 _5% RC92 0_0402 _5%RC92 0_0402 _5%

1 2 1 2

VCCIO_SENSE 39

12

RC98

RC98 10_0402_1%

10_0402_1%

+1.05VS_VCCP

4

+1.05VS_VCCP+1.05VS_VCCP

0.1U_0402_10V7K

1 2

CC49

12

@

RC89

RC89 75_0402_5%

75_0402_5%

VR_SVID_ALRT# 42 VR_SVID_CLK 42 VR_SVID_DAT 42

Pull high resistor on VR side

+CPU_CORE

RC93

RC93 100_0402_1%

100_0402_1%

1 2

12

RC97

RC97 100_0402_1%

100_0402_1%

Close to CPU

VCCSENSE 4 2 VSSSENSE 42

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Sandy Bridge_POWER-1

QFKAA

1

0.2

8 48Thursday, February 16, 2012

5

+GFX_CORE

D D

C C

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

RC119

12

10U_0805_10V6K

0_0805_5%

B B

A A

1

+

2

330U_B2_2.5VM_R15M

CC58

@

1

CC59

2

1U_0402_6.3V6K

+1.8VS_VCCPLL

1

CC60

2

CC61

1U_0402_6.3V6K

JCPUG

33A

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

1.5A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

@

4

POWER

GRAPHICS

1.8V RAIL

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VAXG_SENSE

SM_VREF

5A

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

6A

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

3

AK35

VCC_AXG_SENSE

AK34

VSS_AXG_SENSE

+V_SM_VREF should have 20 mil trace width

AL1

+V_SM_VREF

B4

+VREF_DQA_M3

D1

+VREF_DQB_M3

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

10U_0805_10V6K

CC55

10U_0805_10V6K

Bottom Socket Cavity

10U_0805_10V6K

1

CC40

2

10U_0805_10V6K

H_VCCSA_VID0 H_VCCSA_VID1

CC41

10U_0805_10V6K

1

CC42

2

0_0402_5% @

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

1

CC65

0.1U_0402_10V7K

2

10U_0805_10V6K

1

CC56

2

10U_0805_10V6K

Bottom Socket Edge

1

CC51

CC52

CC57

2

10U_0805_10V6K

+VCCSA Decoupling: 1X 330U (6m ohm), 3X 10U

+VCCSA

Co-lay for Cost Down Plan

1 2

RC189 0_0402_5%RC189 0_0402_5%

1

CC43

+

CC44

@

2

330U_D2_2VM_R6M

2

RC111

1 2

H_VCCSA_VID0 4 1 H_VCCSA_VID1 4 1

+VCCSA_SENSE 41

Please kindly check whether pull down by 10k in PWR-Side

+1.5V_CPU +1.5V

+GFX_CORE

12

RC105

RC105 10_0402_1%

10_0402_1%

RC106

1 2

10_0402_1%

+1.5V_CPU

RC120

RC120 1K_0402_0.5%

1K_0402_0.5%

1 2

1K_0402_0.5%

1 2

RC109

+1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U

+1.5V_CPU

10U_0805_10V6K

ESR 6mohm

1

+

CC53

CC54

@

330U_D2_2VM_R6M

2

+VCCSA_SENSE

CC46 0.1U_0402_10V7KCC46 0.1U_0402_ 10V7K

1 2

CC47 0.1U_0402_10V7KCC47 0.1U_0402_ 10V7K

1 2

CC48 0.1U_0402_10V7KCC48 0.1U_0402_ 10V7K

1 2

CC45 0.1U_0402_10V7KCC45 0.1U_0402_ 10V7K

1 2

2N7002DW-T/R7_SOT363-6

2

Close to CPU

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

Vgs=10V,Id=14.5A,Rds=6mohm

RC192

470_0805_5%

QC5B

5

SUSP

1 2 3

4

0

1

1 1

1

CC68

CC68 10U_0805_10V6K

10U_0805_10V6K

2

CC69

0.1U_0402_25V6

0

1

0

1 2 3 4

FDS6676AS_SO8

1

2

PJ1

2

JUMP_43X118

QC4

S S S G

RUN_ON_CPU1.5VS3

12

RC194

RC194 820K_0402_5%

820K_0402_5%

@PJ1

@

112

D D D D

8 7 6 5

+VCCSAVCCSA_VID0 VCCSA_VID1

0.90 V

0.80 V

0.75 V

0.65 V

1

+1.5VS+1.5V_CPU

C464

4.7U_0805_10V4Z

1 2

C463

+1.5V

1 2

1U_0402_6.3V6K

1 2

C469

4.7U_0805_10V4Z

220K_0402_5%

61

QC5A

2N7002DW-T/R7_SOT363-6

For Sandy Bridge

RC193

1 2

2

SUSP

+VSB

SUSP 5,34

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Sandy Bridge_POWER-2

QFKAA

1

0.2

9 48Thursday, February 16, 2012

5

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

D D

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25

C C

AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7 AK4

AJ25

B B

VSS

VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

TYCO_2013620-2_IVY BRIDGE

@

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

JCPUI

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

@

VSS

4

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

3

JCPUE

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG4

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

@

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

CFG

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7

RESERVED

RSVD_NCTF8 RSVD_NCTF9

RSVD_NCTF10

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

2

CFG Straps for Processor

(CFG[17:0] internal pull hi gh to VCCIO)

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

T3PAD T3PAD

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

*

socket pin map definition

CFG2

0:Lane Reversed

CFG4

12

RC82

RC82 1K_0402_1%

1K_0402_1%

@

1

Embedded Display Port Presence Strap

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

KEY

T64PAD T64PAD

PCIE Port Bifurcation Straps

CFG[6:5]

1 : Disabled; No Physical D isplay Port

*

attached to Embedded Displa y Port

CFG4

0 : Enabled; An external Di splay Port device is connected to the Embedded D isplay Port

11: (Default) x16 - Device 1 functions 1 and 2 disabl ed

*

10: x8, x8 - Device 1 funct ion 1 enabled ; function 2 disabled 01: Reserved - (Device 1 fu nction 1 disabled ; functi on 2 enabled) 00: x8,x4,x4 - Device 1 fun ctions 1 and 2 enabled

PEG DEFER TRAINING

1: (Default) PEG Train imme diately following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for tr aining

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Sandy Bridge_GND/RSVD/CFG

Size Document Number Rev

Custom

QFKAA

Date: Sheet o f

2

Date: Sheet o f

1

0.2

10 48Thursday, February 16, 2012

5

+1.5V

JDDR3L

+0.75VS

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06- K4406-0103

@

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

GND2

BOSS2

VSS DQ4 DQ5

VSS

VSS DQ6 DQ7

VSS

VSS DM1

VSS

VSS DM2

VSS

VDD

A15 A14

VDD

A11

A7

VDD

A6 A4

VDD

A2 A0

VDD

CK1

VDD

BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS DM4

VSS

VSS DM6

VSS

SDA

SCL

VTT

+VREF_DQA

CD1

0.1U_0402_10V7K

D D

Close to JDDRL.1

C C

B B

A A

DDR_A_BS27

DDRA_CLK07 DDRA_CLK0#7

DDR_A_BS07

DDR_A_W E#7

DDR_A_CAS #7

DDRA_SCS1 #7

+3VS

CD25

DDR_A_D0 DDR_A_D1

1

CD2

2.2U_0603_6.3V4Z

2

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS #1 DDR_A_DQS 1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS #2 DDR_A_DQS 2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDRA_CLK0 DDRA_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_W E# DDR_A_CAS #

DDR_A_MA13 DDRA_SCS1 #

DDR_A_D32 DDR_A_D33

DDR_A_DQS #4 DDR_A_DQS 4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS #6 DDR_A_DQS 6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

RD8

RD8 10K_0402_5%

10K_0402_5%

1

CD26

2

2.2U_0603_6.3V4Z

12

RD9

2

10K_0402_5%

0.1U_0402_10V7K

5

4

+1.5V

2 4

DDR_A_D4

6

DDR_A_D5

8 10

DDR_A_DQS #0

12

DDR_A_DQS 0

14 16

DDR_A_D6

18

DDR_A_D7

20 22

DDR_A_D12

24

DDR_A_D13

26 28 30

SM_DRAMRST #

32 34

DDR_A_D14

36

DDR_A_D15

38 40

DDR_A_D20

42

DDR_A_D21

44 46 48 50

DDR_A_D22

52

DDR_A_D23

54 56

DDR_A_D28

58

DDR_A_D29

60 62

DDR_A_DQS #3

64

DDR_A_DQS 3

66 68

DDR_A_D30

70

DDR_A_D31

72

74

DDRA_CKE1

76 78

DDR_A_MA15

80

DDR_A_MA14

82 84

DDR_A_MA11

86

DDR_A_MA7

88 90

DDR_A_MA6

92

DDR_A_MA4

94 96

DDR_A_MA2

98

DDR_A_MA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDR_A_BS1

110

DDR_A_RAS #

112 114

DDRA_SCS0 #

116

DDRA_ODT 0

118 120

DDRA_ODT 1

122 124 126

+VREF_CAA

128 130

DDR_A_D36

132

DDR_A_D37

134 136 138 140

DDR_A_D38

142

DDR_A_D39

144 146

DDR_A_D44

148

DDR_A_D45

150 152

DDR_A_DQS #5

154

DDR_A_DQS 5

156 158

DDR_A_D46

160

DDR_A_D47

162 164

DDR_A_D52

166

DDR_A_D53

168 170 172 174

DDR_A_D54

176

DDR_A_D55

178 180

DDR_A_D60

182

DDR_A_D61

184 186

DDR_A_DQS #7

188

DDR_A_DQS 7

190 192

DDR_A_D62

194

DDR_A_D63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

+0.75VS

206 208

4

DDR3 SO-DIMM A Reverse Type

SM_DRAMRST # 7,12

DDRA_CKE1 7DDRA_CKE07

DDRA_CLK1 7 DDRA_CLK1# 7

DDR_A_BS1 7 DDR_A_RAS # 7

DDRA_SCS0 # 7 DDRA_ODT 0 7

DDRA_ODT 1 7

1

CD15

CD16

2.2U_0603_6.3V4Z

0.1U_0402_10V7K

2

close to JDDRL.126

PM_SMBDATA 12,17,26 PM_SMBCLK 12,17,26

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

3

Intel DDR Vref M3

+VREF_DQA_M 3

+VREF_DQB_M 3

BSS138_NL_SOT23- 3

+1.5V

12

RD6

1K_0402_1%

+VREF_CAA_D IMMA

12

RD7

1K_0402_1%

+1.5V

CD7 330U_2.5V_M

CD8 10U_0603_6 .3V6MCD8 10U_0603_6 .3V6M

CD9 10U_0603_6 .3V6MCD9 10U_0603_6 .3V6M

CD10 10U_0603_6.3V6MCD10 10U _0603_6.3V6M

CD11 10U_0603_6.3V6MCD11 10U _0603_6.3V6M

CD12 10U_0603_6.3V6MCD12 10U _0603_6.3V6M

CD13 10U_0603_6.3V6MCD1 3 10U_0603_6.3V6M

2010/09/03 2012/12/31

3

D

QC9

S

Layout Note: Place near JDDRL

+

1 2

Compal Secret Data

DDR_A_DQS [0..7] 7

DDR_A_DQS #[0..7] 7

DDR_A_D[0..63 ] 7

DDR_A_MA[0..15] 7

13

2

G

Deciphered Date

2

12

@

0_0402_5%

RC115

BSS138_NL_SOT23- 3

QC7

D

S

D

S

13

G

2

RH100

10K_0402_5%

G

2

13

D

S

D

S

QC8

BSS138_NL_SOT23- 3

12

@

0_0402_5%

RC116

H_SNB_IVB# 5,21

+1.5V

1 2

CD50 33P_0402_50V 8KCD50 33P_0402_50V 8K

1 2

CD51 33P_0402_50V 8KCD51 33P_0402_50V 8K

1 2

CD52 33P_0402_50V 8KCD52 33P_0402_50V 8K

1 2

CD53 33P_0402_50V 8KCD53 33P_0402_50V 8K

1 2

CD54 33P_0402_50V 8KCD54 33P_0402_50V 8K

1 2

CD55 33P_0402_50V 8KCD55 33P_0402_50V 8K

Layout Note: Place thes e 4 Caps near Command and Control signals of DIMMA

+1.5V +0.75VS

CD20 0.1U_0402_10V7KCD20 0.1U_0402_10V7K

CD17 0.1U_0402_10V7KCD17 0.1U_0402_10V7K

CD18 0.1U_0402_10V7KCD18 0.1U_0402_10V7K

CD19 0.1U_0402_10V7KCD19 0.1U_0402_10V7K

1 2

12

2

+VREF_DQA

DRAMRST_C NTRL_PCH 7,1 7

+VREF_DQB

1

+1.5V

12

RD1

1K_0402_1%

+VREF_DQA

+VREF_DQB

Layout Note: Place near JDDRL1.203 and 204

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Custom

QFKAA

Date: Sheet of

QFKAA

12

RD2

1K_0402_1%

+1.5V

12

RD10

1K_0402_1%

12

RD11

1K_0402_1%

1 2

CD56 10U_0603_6.3V6MCD56 10U_0603_ 6.3V6M

12

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K

12

CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K

12

CD22 1U_0402_6.3V6KCD22 1U_0402_6.3V6K

12

CD23 1U_0402_6.3V6KCD23 1U_0402_6.3V6K

DDRIII-SODIM M0

1

11 48Thursday, Feb ruary 16, 2012

0.2

A

+1.5V

JDDR3H

+0.75VS

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U ASN-7F_204P

@

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

BOSS1 BOSS2

VSS DQ4 DQ5

VSS

VSS DQ6 DQ7

VSS

VSS DM1

VSS

VSS DM2

VSS

VDD

A15 A14

VDD

A11

A7

VDD

A6 A4

VDD

A2 A0

VDD

CK1

VDD

BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS DM4

VSS

VSS DM6

VSS

SDA

SCL

VTT

+VREF_DQB

CD28

2.2U_0603_6.3V4Z

1 1

Close to JDDRH.1

DDRB_CKE07

2 2

3 3

4 4

+3VS

2.2U_0603_6.3V4Z

@

CD48

DDR_B_BS27

DDRB_CLK07 DDRB_CLK0#7

DDR_B_W E#7 DDR_B_CAS #7

DDRB_SCS1 #7

1

2

DDR_B_D0 DDR_B_D1

1

DDR_B_D2

CD27

DDR_B_D3

0.1U_0402_10V7K

2

DDR_B_D8 DDR_B_D9

DDR_B_DQS #1 DDR_B_DQS 1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS #2 DDR_B_DQS 2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDRB_CLK0 DDRB_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_W E# DDR_B_CAS #

DDR_B_MA13 DDRB_SCS1 #

DDR_B_D32 DDR_B_D33

DDR_B_DQS #4 DDR_B_DQS 4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS #6 DDR_B_DQS 6

DDR_B_D50 DDR_B_D55 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

RD14

RD14 10K_0402_5%

10K_0402_5%

1 2

RD15

1

10K_0402_5%

CD49

2

0.1U_0402_10V7K

A

B

+1.5V

2 4

DDR_B_D4

6

DDR_B_D5

8 10

DDR_B_DQS #0

12

DDR_B_DQS 0

14 16

DDR_B_D6

18

DDR_B_D7

20 22

DDR_B_D12

24

DDR_B_D13

26 28 30

SM_DRAMRST #

32 34

DDR_B_D14

36

DDR_B_D15

38 40

DDR_B_D20

42

DDR_B_D21

44 46 48 50

DDR_B_D22

52

DDR_B_D23

54 56

DDR_B_D28

58

DDR_B_D29

60 62

DDR_B_DQS #3

64

DDR_B_DQS 3

66 68

DDR_B_D30

70

DDR_B_D31

72

74

DDRB_CKE1

76 78

DDR_B_MA15

80

DDR_B_MA14

82 84

DDR_B_MA11

86

DDR_B_MA7

88 90

DDR_B_MA6

92

DDR_B_MA4

94 96

DDR_B_MA2

98

DDR_B_MA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDR_B_BS1

110

DDR_B_RAS #

112 114

DDRB_SCS0 #

116

DDRB_ODT 0

118 120

DDRB_ODT 1

122 124 126

+VREF_CAB +VREF_C AB_DIMMB

128 130

DDR_B_D36

132

DDR_B_D37

134 136 138 140

DDR_B_D38

142

DDR_B_D39

144 146

DDR_B_D44

148

DDR_B_D45

150 152

DDR_B_DQS #5

154

DDR_B_DQS 5

156 158

DDR_B_D46

160

DDR_B_D47

162 164

DDR_B_D52

166

DDR_B_D53

168 170 172 174

DDR_B_D54

176 178 180

DDR_B_D60

182

DDR_B_D61

184 186

DDR_B_DQS #7

188

DDR_B_DQS 7

190 192

DDR_B_D62

194

DDR_B_D63

196 198 200

PM_SMBDATA

202

PM_SMBCLK

204

+0.75VS

206 208

B

Reverse Type DDR3 SO-DIMM B

SM_DRAMRST # 7,11

DDRB_CKE1 7

DDRB_CLK1 7 DDRB_CLK1# 7

DDR_B_BS1 7 DDR_B_RAS # 7DDR_B_BS07

DDRB_SCS0 # 7 DDRB_ODT 0 7

DDRB_ODT 1 7

1

CD46

CD47

2.2U_0603_6.3V4Z

0.1U_0402_10V7K

2

Close to JDDRH.126

PM_SMBDATA 11,17,26 PM_SMBCLK 11,17,26

C

DDR_B_DQS #[0..7] 7

DDR_B_DQS [0..7] 7

DDR_B_D[0..63 ] 7

DDR_B_MA[0..15] 7

+1.5V

12

RD12

1K_0402_1%

12

RD13

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V

@

+

1 2

CD31 330U_B2_2.5VM_R15M

1 2

CD41 10U_0603_6.3V6MCD4 1 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6MCD3 6 10U_0603_6.3V6M

1 2

CD37 10U_0603_6.3V6MCD3 7 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6MCD3 8 10U_0603_6.3V6M

1 2

CD39 10U_0603_6.3V6MCD3 9 10U_0603_6.3V6M

1 2

CD40 10U_0603_6.3V6MCD4 0 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

D

Layout Note: Place thes e 4 Caps near Command and Control signals of DIMMB

1 2

CD33 0.1U_0402_10V7KCD33 0.1U_0402_10V7K

1 2

CD29 0.1U_0402_10V7KCD29 0.1U_0402_10V7K

1 2

CD30 0.1U_0402_10V7KCD30 0.1U_0402_10V7K

1 2

CD32 0.1U_0402_10V7KCD32 0.1U_0402_10V7K

D

E

Layout Note: Place near JDDRH.203 a nd 204

+0.75VS+1.5V

1 2

CD57 10U_0603_6.3V6MCD5 7 10U_0603_6.3V6M

12

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

12

CD43 1U_0402_6.3V6KCD43 1U_0402_6.3V6K

12

CD44 1U_0402_6.3V6KCD44 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Custom

Date: Sheet of

DDRIII-SODIM M1

QFKAA

12 48Thursday, Feb ruary 16, 2012

E

0.2

A

LCD_TXOUT0+19

LCD_TXOUT0-19

LCD_TXOUT1+19

LCD_TXOUT1-19

LCD_TXOUT2+19

LCD_TXOUT2-19

1 1

LCD_TXCLK+19

LCD_TXCLK-19

LCD_EDID_CLK19

LCD_EDID_DATA19

1 2

CAM@

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

R388 0_0603_5%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

LCD_TZOUT0LCD_TZOUT0+ LCD_TZOUT1LCD_TZOUT1+ LCD_TZOUT2LCD_TZOUT2+ LCD_TZCLKLCD_TZCLK+

CAM@

USB20_N11_R USB20_P11_R

INT_MIC_CLK INT_MIC_DATA

LCD_EDID_CLK LCD_EDID_DATA

LCD_TXOUT0LCD_TXOUT0+

LCD_TXOUT1LCD_TXOUT1+

LCD_TXOUT2LCD_TXOUT2+

LCD_TXCLKLCD_TXCLK+ LED_PWM BKOFF#_R

C257 47P_0402_50V8J

+3VS

JLVDS

2 2

31

GND1

32

GND2

33

GND3

34

GND4

35

GND5

36

GND6

STARC_107K30-000001-G2

JLVDS1

12

GND

11

GND

10

ACES_87036-1001-CP

10

9

8

7

6

5

4

3

2

1

@

3 3

LCD_TXOUT0+

LCD_TXOUT0-

LCD_TXOUT1+

LCD_TXOUT1-

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

LCD_EDID_CLK

LCD_EDID_DATA

W=20mils

+3VS_LVDS_CAM

1.5A

+LCD_INV

1 2

@

B

LCD_TZCLK-19

@

For RF

C256 47P_0402_50V8J

1 2

CAM@

0.1U_0402_10V7K

1 2

C225

2

3

D84 AZ5125-02S.R7G_SOT23-3

@

+3VS

1

C248

0.1U_0402_10V7K

2

LCD_TZOUT0+19

LCD_TZOUT0-19

LCD_TZOUT1+19

LCD_TZOUT1-19

LCD_TZOUT2+19

LCD_TZOUT2-19

LCD_TZCLK+19

1

INT_MIC_CLK 30

INT_MIC_DATA 30

1

C226

0.1U_0402_10V7K

2

LED_PWM

BKOFF#_R

C

1

2

1 2

D17 RB751V40_SC76-2D17 RB751V40_SC76-2

12

R131

R131 47K_0402_5%

47K_0402_5%

1 2

D15 RB751V40_SC76-2D15 RB751V40_SC76-2

12

R113

R113 10K_0402_5%

10K_0402_5%

LCD_TZOUT0+

LCD_TZOUT0-

LCD_TZOUT1+

LCD_TZOUT1-

LCD_TZOUT2+

LCD_TZOUT2-

LCD_TZCLK+

LCD_TZCLK-

2A

C227

4.7U_0805_10V4Z

12

C258

C258 47P_0402_50V8J

47P_0402_50V8J

@

For RF

LVDS cable JLVDS1.2 need to contact GND

LVDS_SEL 17

+LCD_INV

C234

68P_0402_50V8J

L2

FBMA-L11-201209-221LMA30T_0805

1

C235

0.1U_0402_25V6

2

B+

12

For EMI1.5A

1

C247

1

C489

C269

@

2

0.1U_0402_25V6

@

2

0.1U_0402_25V6

1

2

D

BKOFF# 31

0.1U_0402_25V6

+LCD_VDD

PCH_PWM 19

B+

1

C490

@

2

E

2N7002DW-T/R7_SOT363-6

UMA_ENVDD19

R109

150_0603_5%

Q1A

F

+LCD_VDD

12

61

100K_0402_5%

2

5

R112

R112 100K_0402_5%

100K_0402_5%

1 2

+3VS

12

R108

3

Q1B

Q1B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

0.1U_0402_10V7K

1 2

R110

47K_0402_5%

0.01U_0402_25V7K

G

C228

LCDPWR_GATE

C230

H

+3VS

2

W=80mils

S

G

1

2

Q17

Q17 AO3413_SOT23

AO3413_SOT23

1

D

1 3

+LCD_VDD

2

W=80mils

1

C233

0.1U_0402_10V7K

2

Reserve for EMI request

1 2

R78 0_0402_5%CAM@R78 0_0402_5%CAM@ WCM-2012-900T_0805

WCM-2012-900T_0805

USB20_P11_R

USB20_N11_R

0.1U_0402_25V6

4

1

4

1

L55

R96 0_0402_5%CAM@R96 0_0402_5%CAM@

@L55

@

1 2

3

2

USB20_P11 20

USB20_N11 20

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

D

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

Custom

QFKAA

G

LVDS/eDP

0.2

13 48Thursday, February 16, 2012

0.2

H

A

B

C

D

E

CRT CONNECTOR

If=1A

+5VS +CRT_VCC_R +CRT_VCC

D6

2

CHP3_SERDBG21

1

C246

@

2

10P_0402_50V8J

CRT_DDC_CLK

CRT_DDC_DAT

3

+CRT_VCC

HSYNC

VSYNC

1

2

10P_0402_50V8J

1 1

UMA_CRT_R19

UMA_CRT_G19

UMA_CRT_B19

R138

R139

R140

12

150_0402_1%

1

12

C250

C249

@

2

150_0402_1%

2.2P_0402_50V8C

1 2

R189 0_0402_5%R189 0_0402_5%

1 2

R190 0_0402_5%R190 0_0402_5%

1 2

R191 0_0402_5%R191 0_0402_5%

1

C251

@

2

2.2P_0402_50V8C

By EMI demand

2 2

UMA_CRT_HSYNC19

UMA_CRT_VSYNC19

3 3

4 4

CRT_R_R

CRT_G_R

CRT_B_R

C238

1 2

C244 0.1U_0402_10V7KC244 0.1U_0402_10V7K

SN74AHCT1G125GW_SOT353-5

UMA_CRT_CLK19

UMA_CRT_DATA19

1

2

+CRT_VCC

5

A2Y

3

C239

2.2P_0402_50V8C

1

P

OE#

G

1 2

L3 NBQ100505T-800Y_0402L3 NBQ100505T-800Y_0402

1 2

L4 NBQ100505T-800Y_0402L4 NBQ100505T-800Y_0402

1 2

L5 NBQ100505T-800Y_0402L5 NBQ100505T-800Y_0402

1

C241

2

4

U6

C240

2.2P_0402_50V8C

0.1U_0402_10V7K

33P_0402_50V8K

C241

2

2.2P_0402_50V8C

+CRT_VCC

1 2

C252

1

5

P

A2Y

G

SN74AHCT1G125GW_SOT353-5

3

1

C282

2

@

1

C242

2

2.2P_0402_50V8C

R141 10K_0402_5%R141 10K_0402_5%

D_CRT_HSYNC

4

D_CRT_VSYNC

OE#

U7

Q205A

5

2N7002DW-T/R7_SOT363-6

Q205B

4

2N7002DW-T/R7_SOT363-6

1

C285

C285 33P_0402_50V8K

33P_0402_50V8K

2

@

CRT_R_L

CRT_G_L

CRT_B_L

1

C243

2

2.2P_0402_50V8C

12

1 2

L6 10_0402_5%L6 10_0402_5%

1 2

+3VS

2

3

L7 10_0402_5%L7 10_0402_5%

4.7K_0402_5%

61

470P_0402_50V8J

C245

@

+CRT_VCC

R153

R159

4.7K_0402_5%

1 2

1

C283

C284

470P_0402_50V8J

2

@

1

RB491D_SOT23-3

CRT_R_L

CRT_DDC_DAT CRT_G_L

HSYNC CRT_B_L

VSYNC CHP3_SERDBG

CRT_DDC_CLK

+CRT_VCC

F1

40 mils

21

0.5A_8V_KMC3S050RY

0.1U_0402_10V7K

T65 PADT65 PAD

6

5

4

CRT_G_L

CRT_DDC_CLK

CRT_DDC_DAT

6

5

4

2/9: Add for ESD request

1

C237

2

@

JCRT

6

11

1 7

12

2 8

G

13

G

3 9

14

4 10 15

5

SUYIN_070546FR015S251ZR

@

D98

@D98

@

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04S.R7G_SOT23-6

D97

@D97

@

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04S.R7G_SOT23-6

16 17

3

2

1

3

2

1

CRT_B_LCRT_R_L

CHP3_SERDBG

HSYNC

VSYNC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

CRT

QFKAA

0.2

14 48Thursday, February 16, 2012

E

0.2

5

D D

4

3

2

1

+3VS

C C

1 2

UMA_HDMI_TXC+19

UMA_HDMI_TXC-19

UMA_HDMI_TX0+19

UMA_HDMI_TX0-19

UMA_HDMI_TX1+19

UMA_HDMI_TX1-19

UMA_HDMI_TX2+19

UMA_HDMI_TX2-19

B B

A A

CV308 0.1U_0402_10 V7K HDMI@CV308 0.1U_ 0402_10V7K HDMI@

CV304 0.1U_0402_10 V7K HDMI@CV304 0.1U_ 0402_10V7K HDMI@

CV306 0.1U_0402_10 V7K HDMI@CV306 0.1U_ 0402_10V7K HDMI@

CV302 0.1U_0402_10 V7K HDMI@CV302 0.1U_ 0402_10V7K HDMI@

CV303 0.1U_0402_10 V7K HDMI@CV303 0.1U_ 0402_10V7K HDMI@

CV301 0.1U_0402_10 V7K HDMI@CV301 0.1U_ 0402_10V7K HDMI@

CV307 0.1U_0402_10 V7K HDMI@CV307 0.1U_ 0402_10V7K HDMI@

CV305 0.1U_0402_10 V7K HDMI@CV305 0.1U_ 0402_10V7K HDMI@

UMA_DVI_TXC-

UMA_DVI_TXC+

UMA_DVI_TXD0-

UMA_DVI_TXD0+

UMA_DVI_TXD1-

UMA_DVI_TXD1+

UMA_DVI_TXD2-

UMA_DVI_TXD2+

5

1 2

@

R157 0_0402_5%

R157 0_0402_5% L8

HDMI@L8

HDMI@

112

4

WCM-2012HS-6 70T_0805

1 2

@

R173 0_0402_5%

1 2

@

R175 0_0402_5%

R175 0_0402_5% L9

HDMI@L9

HDMI@

334

2

WCM-2012HS-6 70T_0805

1 2

@

R180 0_0402_5%

1 2

@

R182 0_0402_5%

R182 0_0402_5% L10

HDMI@L10

HDMI@

112

4

WCM-2012HS-6 70T_0805

1 2

@

R183 0_0402_5%

1 2

@

R187 0_0402_5%

R187 0_0402_5% L11

HDMI@L11

HDMI@

334

2

WCM-2012HS-6 70T_0805

1 2

@

R188 0_0402_5%

3

1

3

1

UMA_DVI_TXC+

UMA_DVI_TXC-

UMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1+

UMA_DVI_TXD1-

UMA_DVI_TXD2+

UMA_DVI_TXD2-

HDMI_R_CK-

2

3

HDMI_R_CK+

HDMI_R_D0-

4

1

HDMI_R_D0+

HDMI_R_D1-

2

3

HDMI_R_D1+

HDMI_R_D2-

4

1

HDMI_R_D2+

4

HDMI_R_D2-

HDMI_R_D2+

HDMI_R_D0+ HDMI_R_D0+

HDMI_R_D0- HDMI_R_D0-

2/9: Add for ESD request

UMA_HDMI_CLK19

UMA_HDMI_DATA19

D95

@

1

10

1

10

2

9

2

9

4

7

4

7

4

5

65

3

8

AZ1045-04F_DFN25 10P10E-10-9

D94

@

1

10

1

10

2

9

2

9

4

7

4

7

4

5

65

3

8

AZ1045-04F_DFN25 10P10E-10-9

9

8

7

6

9

8

7

6

HDMI_R_CK+HDMI_R_CK+

HDMI_R_CK-HDMI_R_CK-

2

3 1

SGD

Q19

BSH111_SOT23-3

HDMI@

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D0+

HDMI_HPD_C

+HDMI_5V_OUT

HDMI_R_D0-

HDMI_R_D2-

HDMI_R_D2+

+5VS

HDMI_R_D1-HDMI_R_D 1-

HDMI_R_D1+HDMI_R _D1+

HDMI_R_D2-

HDMI_R_D2+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+HDMI_5V_OUT

12

R185

R184

2.2K_0402_5%

HDMI@

Q18

HDMI_SDATA

1 2

HDMI@

R195 680_0402_1%

1 2

HDMI@

R197 680_0402_1%

1 2

HDMI@

R198 680_0402_1%

1 2

HDMI@

R202 680_0402_1%

1 2

HDMI@

R201 680_0402_1%

1 2

HDMI@

R203 680_0402_1%

1 2

HDMI@

R205 680_0402_1%

1 2

HDMI@

R206 680_0402_1%

D96

@D 96

@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23 -6

2.2K_0402_5%

HDMI@

HDMI_SCLK

2

G

I/O2

GND

I/O1

13

3

2

1

D

Q24

Q24 2N7002_SOT23-3

2N7002_SOT23-3

HDMI@

S

HDMI_SDATA

HDMI_SCLK

2.2K_0402_5%

2

3 1

SGD

BSH111_SOT23-3

HDMI@

2/9: Add for ESD request

Compal Secret Data

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

2

C264

0.1U_0402_10V7K

HDMI@

PMEG2010AEH_SOD123

+HDMI_5V_OUT

2

5

1

A2Y

3

HDMI@

D53

2 1

+HDMI_5V_OUT_F

+HDMI_5V_OUT

Title

Size Document Number Rev

Date: Sheet o f

HDMI@

R145

1 2

1K_0402_5%

1

100K_0402_5%

U9

P

4

HDMI_HPD

OE#

G

SN74AHCT1G125GW _SOT353-5

HDMI@

R571

2.2K_0402_5%

HDMI_HPD

F2

21

0.5A_8V_KMC3S050RY

HDMI@

HDMI Connector

HDMI_HPD_C

HDMI_SDATA HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+ HDMI_R_D0-

HDMI_R_D0+ HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D2-

HDMI_R_D2+

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

Compal Electronics, Inc.

HDMI Conn./CEC

QFKAA

HDMI_HPD_CHDMI_H PD_U

R186

HDMI@

1 2

12

+3VS

1

C259

HDMI@

0.1U_0402_10V7K

2

JHDMI

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CK-

GND

CK_shield

GND

CK+

GND

D0-

GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

HONGL_13-1320 1904CP

@

1

2

C265

0.1U_0402_10V7K

HDMI@

1

HDMI_HPD 19

+HDMI_5V_OUT+5VS

20 21 22 23

0.2

15 48Thursday, February 16, 2012