Compal LA-8821P QAZA0, XPS 12 Schematic

A

MODEL NAME :

PCB NO :

1 1

BOM P/N :

QAZA0

LA-8821P ( DAB00000B00 )

ZZZ

ZZZ
MB_ PCB

MB_ PCB

B

C

D

E

4619J831L01 -> i5, 1.7G, DDR3L-4GB
4619J831L02 -> i5, 1.7G, DDR3L-8GB
4619J831L03 -> i7, 1.9G, DDR3L-4GB
4619J831L04 -> i7, 1.9G, DDR3L-8GB
4619J831L06 -> i5, 1.8G, DDR3L-4GB
4619J831L07 -> i5, 1.8G, DDR3L-8GB
4619J831L08 -> i7, 2.0G, DDR3L-4GB
4619J831L09 -> i7, 2.0G, DDR3L-8GB
4619J831L10 -> i5, 1.8G, DDR3L-4GB-NT
4619J831L11 -> i5, 1.8G, DDR3L-8GB-NT
4619J831L12 -> i7, 2.0G, DDR3L-4GB-NT

2 2

4619J831L13 -> i7, 2.0G, DDR3L-8GB-NT

Dell/Compal Confidential

4619J831L14 -> i5, 1.7G, DDR3L-4GB-NT
4619J831L15 -> i5, 1.7G, DDR3L-8GB-NT
4619J831L16 -> i7, 1.9G, DDR3L-4GB-NT

Schematic Document

4619J831L17 -> i7, 1.9G, DDR3L-8GB-NT

Murcielgo (Chief River SFF)

Ivy Bridge(BGA) + Panther Point(SFF, QS77)

3 3

2012-08-21

Rev: 1.0

Highlight the short pad for 0 ohm

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P01-Cover Page

P01-Cover Page

P01-Cover Page

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1 54Frida y, S ep tem ber 28, 20 12

1 54Frida y, S ep tem ber 28, 20 12

1 54Frida y, S ep tem ber 28, 20 12

E

1.0

1.0

1.0

A

B

C

D

E

1 1

eDP Panel

P.24

Conn x 2.

2 2

miniDP
Conn.

e-Compass +

Accelerometer

DE303DLHCTR

P.26

I2C

Sensor HUB

P.27

STM32F103RD

P.27

eDP

DP 1.1a

USB 2.0

Gyro Sensor

TX3GD20TR

3 3

Pressure Sensor

APS331APTR

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

4 4

PWM Fan Connector

De-pop

P.27

P.27

P.36 ~ 47

De-pop

NFC Module
Conn

P.33

P.32

P.34

SPI ROM
8M

TPM

AT97SC320 4-X2A14-AB

P.29

P.16

SMBus/I2C

SPI

P.27

Intel
Ivy Bridge
Processor

2C 17W

BGA 1023

Page 5, 6, 7, 8, 9, 10

100MHz 100MHz

2.7GT/s

DMI x4FDI x8

5GT/s

Intel

Panther Point SFF

PCH

QS77

BGA 1017 Balls

Page 16 ~ 23

LPC Bus

ENE KB9012BF

Touch Pad Int.KBD

P.34

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3L 1333 MHz

SATA3.0

USB2.0

PCI-E 2.0

USB2.0

USB2.0

USB3.0/USB2.0

USB3.0/USB2.0

HD Audio

P.35

Digital MIC

P.33

Channel A
DDR3L 2Gb or 4Gb (x8 ) * 8

Channel B
DDR3L 2Gb or 4Gb (x8 ) * 8

P.11, 12

P.13,14

Mini Card (Full)

# mSATA

Mini Card (Half)

WLAN
WiGig
BT

Touch Screnn

Digital Camera

USB 3.0 Conn.

( USB Charger Port )

USB 3.0 Conn.

Daughter Board

IOL BTB Conn

P.25

P.24

Audio Codec
ALC3260

P.29

P.28

P.24

P.24

P.30

P.30

Headphone Jack

( iPhone & Nokia compatible)

Int. Speaker

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/02/23 2013/10/28

2011/02/23 2013/10/28

2011/02/23 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

2 54Frida y, S ep tem ber 28, 20 12

2 54Frida y, S ep tem ber 28, 20 12

2 54Frida y, S ep tem ber 28, 20 12

E

1.0

1.0

1.0

A

B

C

D

E

Compal Confidential

Project Code : QAZA0
File Name : LA-88 21P

1 1

LS-8821P

Volume Up/Down , PWR, Rotation Button

2 2

Audio Jack

Keyboard

Keyboard Backlig ht

3 3

4 4

A

FPC

36 pin

FPC (main frame)

30 pin

FFC

4 pin

LA-8821P M/B

eDP Cable x 2

Coaxial and Wire

FFC

6 pin

Touch Pad

B

CABLE

9 pin

Battery Pack

FPC

16 pin to 15 pin

NFC Module

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

LS-8822P
Win8 Button
Hall S ensor

Camera

LCD Panel
Touch Panel Control Baord

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P03-DaughterB block diagram

P03-DaughterB block diagram

P03-DaughterB block diagram

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Date : She et of

Date : She et of

Date : She et of

E

3 54Frida y, S ep tem ber 28, 20 12

3 54Frida y, S ep tem ber 28, 20 12

3 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Board ID Rb V min

1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

SOURCE

KB930

KB930

PCH

PCH

AD_BID V t ypAD_BID V AD_BID max

0 V0

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

WLAN BATT DDR3 SPD

V V V

V V

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

NFCCharger

Touch Pad

V

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

ALS

V

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

Link

A

PCB Revision

0.1 Non Deep S3

0.1 Deep S 3

0.2 (X01)

0.4 (X02)

1.0 (A00)

PCH
USB
Port
Mapping

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

DESTINATION

External USB3

External USB3

MINI CARD-1 WLAN

Touch Panel

Camera

Sensor HUB

PCH

1 1

DDI
Port
Mapping

DESTINATION

SATA

SATA0

m-SATA

SATA1

SATA2

SATA3

SATA4

SATA5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

CLK

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

MINI CARD-1 WLAN

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

TPM

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

PCI CLKOUT DESTINATION

PCI0

PCI1

PCH_LOOPBACK

EC LPC

PCI2

PCI3

PCI4

DDI PORT# DESTINATION

B

C

D mini-DP

PCI EXPRESS

DESTINATION

Lane 1CLKOUT_PCIE0

Lane 2

Lane 3

MINI CARD-1 WLAN

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P04-Notes List

P04-Notes List

P04-Notes List

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

4 54Frida y, S ep tem ber 28, 20 12

4 54Frida y, S ep tem ber 28, 20 12

4 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

5

D D

C C

B B

SA00005K63L for i5-3317U-1.7G SA00005L92L for i5-3427U- 1.8G

eDP_COMPIO (A1 8)

UCPU1

UCPU1

IVB1.7G

IVB1.7G

CPU_ IVB 1.7 G@

CPU_ IVB 1.7 G@

Trace le ngth Ma x is 500 mi ls

eDP_ HPD[24]

RC13 8

RC13 8
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

R_COMP pla ce close to CP U

width 4 m ils

width 12 mils

2

G

G

12

Ivy Bridge i5-1.8G

UCPU1

UCPU1

IVB1.8G

IVB1.8G

CPU_ IVB 1.8 G@

CPU_ IVB 1.8 G@

R_COMPeDP_ICOMPO (A1 7)

VCC_IO

CPU_ eDP _HPD #

13

D

D

QC5

QC5
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

+VCC P

RC36 24.9 _0 402 _1 %RC36 24.9 _0 402 _1 %

RC13 7 1K_ 040 2_ 5%~ DRC13 7 1K_ 040 2_ 5%~ D

Ivy Bridge i7-1.9GIvy Bridge i5-1.7G

UCPU1

UCPU1

IVB1.9G

IVB1.9G

CPU_ IVB 1.9 G@

CPU_ IVB 1.9 G@

SA00005K53L for i7-3517U-1.9G

DMI_ CRX _PT X_ N0[18]
DMI_ CRX _PT X_ N1[18]
DMI_ CRX _PT X_ N2[18]
DMI_ CRX _PT X_ N3[18]

DMI_ CRX _PT X_ P0[18 ]
DMI_ CRX _PT X_ P1[18 ]
DMI_ CRX _PT X_ P2[18 ]
DMI_ CRX _PT X_ P3[18 ]

DMI_ CT X_P RX_ N0[18]
DMI_ CT X_P RX_ N1[18]
DMI_ CT X_P RX_ N2[18]
DMI_ CT X_P RX_ N3[18]

DMI_ CT X_P RX_ P0[18 ]
DMI_ CT X_P RX_ P1[18 ]
DMI_ CT X_P RX_ P2[18 ]
DMI_ CT X_P RX_ P3[18 ]

FDI_C TX _PR X_N0[18]
FDI_C TX _PR X_N1[18]
FDI_C TX _PR X_N2[18]
FDI_C TX _PR X_N3[18]
FDI_C TX _PR X_N4[18]
FDI_C TX _PR X_N5[18]
FDI_C TX _PR X_N6[18]
FDI_C TX _PR X_N7[18]

FDI_C TX _PR X_P 0[ 18]
FDI_C TX _PR X_P 1[ 18]
FDI_C TX _PR X_P 2[ 18]
FDI_C TX _PR X_P 3[ 18]
FDI_C TX _PR X_P 4[ 18]
FDI_C TX _PR X_P 5[ 18]
FDI_C TX _PR X_P 6[ 18]
FDI_C TX _PR X_P 7[ 18]

FDI_F SYN C0[18]
FDI_F SYN C1[18]

FDI_I NT[18]

FDI_L SY NC0[18 ]
FDI_L SY NC1[18 ]

1 2

4

12

eDP_ AUX N[24]
eDP_ AUX P[24]

eDP_ TX N_P 0[24]
eDP_ TX N_P 1[24]

eDP_ TX P_ P0[24 ]
eDP_ TX P_ P1[24 ]

Ivy Bridge i7-2.0G

SA00005LA2L for i7-3667U-2.0G

3

PEG_ICOMPI and RCOMPO signals should be shor ted and routed
with - max leng th = 500 mils - typical imped ance = 43 mohm s
PEG_ICOMPO sign als should be routed with - m ax length = 50 0 mils

- typical imped ance = 14.5 mo hms

@

@

UCPU1 A

+EDP _CO M

CPU_ eDP _HPD #

UCPU1

UCPU1

IVB2.0G

IVB2.0G

CPU_ IVB 2.0 G@

CPU_ IVB 2.0 G@

UCPU1 A

M2
P6
P1

P10

N3
P7
P3

P11

K1
M8
N4
R2

K3
M7
P4
T3

U7

W11

W1

AA6

W6

V4
Y2

AC9

U6

W10

W3

AA7

W7

T4
AA3
AC8

AA11
AC12

U11

AA10

AG8

AF3
AD2

AG11

AG4
AF4

AC3
AC4

AE11

AE7

AC1
AA4

AE10

AE6

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

eDP_AUX#
eDP_AUX

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

eDP

eDP

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

X76 4G

X76 4G

X7641131L01

X7641131L01

X76 _4G @

X76 _4G @

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

X76 8G

X76 8G

X7641131L04

X7641131L04

X76 _8G @

X76 _8G @

PEG _CO MP

+VCC P

12

RC2

RC2

24.9 _0 402 _1 %

24.9 _0 402 _1 %

2

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P05-CPU(1/6) DMI,FDI ,PEG

P05-CPU(1/6) DMI,FDI ,PEG

P05-CPU(1/6) DMI,FDI ,PEG

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

5 54Frida y, S ep tem ber 28, 20 12

5 54Frida y, S ep tem ber 28, 20 12

5 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

4

3

2

1

PM, XDP, CLK, S3 Reduce, PLTRST

PU/PD for JTAG signals

@

@

UCPU1 B

RC34
0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

1 3

D

D

12

R1035

100K_0402_5%~D

R1035

100K_0402_5%~D

QC2

QC2

BSS 138 -G_ SOT 23 -3

BSS 138 -G_ SOT 23 -3

G

G

2

1

CC69

CC69

.047 U_0 40 2_1 6V7 K~D

.047 U_0 40 2_1 6V7 K~D

2

DRAM RST _C NTRL [ 15]

UCPU1 B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

4.99 K_ 040 2_ 1%

4.99 K_ 040 2_ 1%

RC77

RC77

H_DRA MR ST #

12

S

S

Deep S3 Support

Non Deep S3(De-pop R1035)

MISC THERMAL PWR MANAGEMENT

MISC THERMAL PWR MANAGEMENT

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#
PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

JTAG & BPM

JTAG & BPM

BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

3

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

J3
H2

AG3
AG1

AT30

H_DRA MR ST #

BF44

SM_ RCO MP 0

BE43

SM_ RCO MP 1

BG43

SM_ RCO MP 2

DDR3 Compensation Signals

N53

XDP_ PRD Y#

N55

XDP_ PRE Q#

L56

XDP_ TC K

L55

XDP_ TM S

J58

XDP_ TR ST #

M60

XDP_ TD I

L59

XDP_ TD O

K58

XDP_ DBR ESE T# _R

G58
E55
E59
G55
G59
H60
J59
J61

POWEROK

Issued Date

Issued Date

Issued Date

CLK_ CPU _DM I [17]
CLK_ CPU _DM I# [17 ]

CLK_ CPU _DPL L [17 ]
CLK_ CPU _DPL L# [1 7]

1 2

RC55 1 40_ 04 02_ 1%R C55 1 40_ 040 2_ 1%

1 2

RC58 2 5.5 _.4 02_ 1%R C58 2 5.5_ .40 2_ 1%

1 2

RC60 2 00_ 04 02_ 1%R C60 2 00_ 040 2_ 1%

RC56 0 _04 02 _5% ~D

RC56 0 _04 02 _5% ~D

T22 4@ T2 24@
T22 5@ T2 25@
T22 6@ T2 26@
T22 7@ T2 27@
T22 8@ T2 28@
T22 9@ T2 29@
T23 0@ T2 30@
T23 1@ T2 31@

PM_ DRA M_ PWRG D[1 8]

CPU1 .5V _S3 _GA TE[32,3 5,4 2,9 ]

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Width 20 mils, Spacing 13mils, Length < 500mil

T24 1@ T2 41@

SHORT

1 2

@

@

+3V _PCH

RC4

RC4
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

1 2

SHORT

1 2

RC11 0_04 02_ 5% ~D

RC11 0_04 02_ 5% ~D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

XDP_ DBR ESE T#

@

@

2

XDP_ DBR ESE T# [18]

+3V _PCH

1

2

CC65

CC65

.1U_0402_16V7K~D

.1U_0402_16V7K~D

5

UC1

UC1

1

P

B

4

Y

2

A

G

74A HC1G 09 GW_T SS OP 5

74A HC1G 09 GW_T SS OP 5

3

RUN_O N_C PU1. 5VS 3#[32]

Place close to PCH or EC

D D

+VCC P

RC43

RC43

62_ 040 2_ 5%

62_ 040 2_ 5%

H_T HERM T RIP#[20]

H_PM _S YNC[18]

H_CP UPWR GD[20]

1 2

H_CP UPWR GD_R

1

2

CC68

CC68

.1U_0402_16V7K~D

.1U_0402_16V7K~D

5

UC2

UC2

P

4

BUFO _CP U_RS T#

Y

G

3

SN74 LV C1G 07DC KR_ SC7 0-5~ D

SN74 LV C1G 07DC KR_ SC7 0-5~ D

1 2

1 2

H_PR OCHO T#[35, 38]

C C

RC44 1 0K_ 040 2_ 5%~ DRC4 4 10K _04 02 _5% ~D

Avoid stub in the PWRGD path
while placing resistors RC44 & RC53

+3V S

PLT _RS T#[19, 27, 28, 35]

B B

1

NC

2

A

RC13 0 0_040 2_5 %~D@ RC13 0 0_040 2_5 %~ D@

Place close to PCH reset Logic Gate

For CPU S3 Power Reduce

10

1 2

DDR3_ DRA MRS T#[11, 12, 13, 14]

Deep S3 Support

A A

Non Deep S3

DRAM RST _C NTRL _E C[35]

DRAM RST _C NTRL _P CH[17]

DDR3_ DRA MRS T# _R

RC76 1 K_0 40 2_5 %~DRC76 1K _04 02_ 5% ~D

SHORT

1 2

RC14 5 0_0 402 _5 %~D

RC14 5 0_0 402 _5 %~D

1 2

RC72 0 _04 02 _5% ~D@R C72 0 _04 02_ 5% ~D@

@

@

H_PR OCHO T#

+VCC P

12

RC32

RC32

T24 8@ T2 48@

T1@ T1@

H_PE CI[2 0,35 ]

1 2

RC41 56_ 040 2_ 5%RC41 56_ 040 2_ 5%

SHORT

1 2

RC49 0_0 402 _5 %~D

RC49 0_0 402 _5 %~D

@

@

SHORT

1 2

RC53 0_0 402 _5 %~D

RC53 0_0 402 _5 %~D

@

@

75_0402_5%

75_0402_5%

1 2

RC33 4 3_0 40 2_1 %RC33 43_ 04 02_ 1%

+1.3 5V

12

RC75

RC75
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

H_CA TE RR#

H_PR OCHO T# _R

H_T HERM T RIP# _R

H_CP UPWR GD_R

VDDP WRGO OD_ R

BUF_ CPU_ RST #

BUF_ CPU_ RST #

12

@ RC34

@

RC74 0 _04 02 _5% ~D@RC7 4 0_ 040 2_5 %~ D@

DRAM RST _C NTRL

CPU DRAMRST# Control Option for Deep S3

5

4

XDP_ TM S

XDP_ TD I

XDP_ PRE Q#

XDP_ TD O

XDP_ TC K

XDP_ TR ST #

12

RC8

RC8
200 _04 02 _1%

200 _04 02 _1%

VDDP WRGO OD

RC19

@ RC19

@

39_ 040 2_ 1%

39_ 040 2_ 1%

1 2

13

D

D

@

@

S

S

QC1

QC1
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

1 2

RC42 1 K_0 402 _5 %~DRC42 1 K_0 402 _5 %~D

Place close to CPU

1 2

RC57 1 30_ 04 02_ 1%~ DRC57 13 0_0 402 _1 %~D

XDP_ DBR ESE T#

+1.3 5V_ CPU _VD DQ

2

G

G

1/17, Change P/N to SB0000 0UO00

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1

1 2

1 2

1 2

1 2

1 2

1 2

VDDP WRGO OD_ R

+VCC P

RC4551_ 040 2_ 5% RC4551_ 040 2_ 5%

RC4651_ 040 2_ 5% RC4651_ 040 2_ 5%

RC4751_ 040 2_ 5% @RC4751_04 02_ 5% @

RC4851_ 040 2_ 5% RC4851_ 040 2_ 5%

RC5251_ 040 2_ 5% RC5251_ 040 2_ 5%

RC5451_ 040 2_ 5% RC5451_ 040 2_ 5%

+3V S

1.0

1.0

1.0

6 54Frida y, S ep tem ber 28, 20 12

6 54Frida y, S ep tem ber 28, 20 12

6 54Frida y, S ep tem ber 28, 20 12

5

4

3

2

1

D D

DDR_A _D[ 0..6 3][11,1 2]

C C

B B

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D1 0
DDR_A _D1 1
DDR_A _D1 2
DDR_A _D1 3
DDR_A _D1 4
DDR_A _D1 5
DDR_A _D1 6
DDR_A _D1 7
DDR_A _D1 8
DDR_A _D1 9
DDR_A _D2 0
DDR_A _D2 1
DDR_A _D2 2
DDR_A _D2 3
DDR_A _D2 4
DDR_A _D2 5
DDR_A _D2 6
DDR_A _D2 7
DDR_A _D2 8
DDR_A _D2 9
DDR_A _D3 0
DDR_A _D3 1
DDR_A _D3 2
DDR_A _D3 3
DDR_A _D3 4
DDR_A _D3 5
DDR_A _D3 6
DDR_A _D3 7
DDR_A _D3 8
DDR_A _D3 9
DDR_A _D4 0
DDR_A _D4 1
DDR_A _D4 2
DDR_A _D4 3
DDR_A _D4 4
DDR_A _D4 5
DDR_A _D4 6
DDR_A _D4 7
DDR_A _D4 8
DDR_A _D4 9
DDR_A _D5 0
DDR_A _D5 1
DDR_A _D5 2
DDR_A _D5 3
DDR_A _D5 4
DDR_A _D5 5
DDR_A _D5 6
DDR_A _D5 7
DDR_A _D5 8
DDR_A _D5 9
DDR_A _D6 0
DDR_A _D6 1
DDR_A _D6 2
DDR_A _D6 3

DDR_A _B S0[1 1,1 2,15 ]
DDR_A _B S1[1 1,1 2,15 ]
DDR_A _B S2[1 1,1 2,15 ]

DDR_A _CA S#[1 1,1 2,1 5]
DDR_A _RA S#[1 1,1 2,1 5]
DDR_A _WE #[11,1 2,15 ]

@

@

UCPU1 C

UCPU1 C

AG6

AJ6

AP11

AL6

AJ10

AJ8
AL8
AL7

AR11

AP6
AU6
AV9
AR6
AP8

AT13
AU13

BC7
BB7

BA13
BB11

BA7
BA9
BB9

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48

AY48

BA49

AV49

BB51

AY53

BB49
AU49
BA53
BB55
BA55

AV56

AP50
AP53

AV54

AT54
AP56
AP52
AN57

AN53
AG56
AG53

AN55

AN52
AG55

AK56

BD37

BF36

BA28

BE39

BD39

AT41

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11

DDR_A _DQ S#0

SA_DQS#[0]

AR8

DDR_A _DQ S#1

SA_DQS#[1]

AV11

DDR_A _DQ S#2

SA_DQS#[2]

AT17

DDR_A _DQ S#3

SA_DQS#[3]

AV45

DDR_A _DQ S#4

SA_DQS#[4]

AY51

DDR_A _DQ S#5

SA_DQS#[5]

AT55

DDR_A _DQ S#6

SA_DQS#[6]

AK55

DDR_A _DQ S#7

SA_DQS#[7]

AJ11

DDR_A _DQ S0

SA_DQS[0]

AR10

DDR_A _DQ S1

SA_DQS[1]

AY11

DDR_A _DQ S2

SA_DQS[2]

AU17

DDR_A _DQ S3

SA_DQS[3]

AW45

DDR_A _DQ S4

SA_DQS[4]

AV51

DDR_A _DQ S5

SA_DQS[5]

AT56

DDR_A _DQ S6

SA_DQS[6]

AK54

DDR_A _DQ S7

SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

BG35

DDR_A _M A0

BB34

DDR_A _M A1

BE35

DDR_A _M A2

BD35

DDR_A _M A3

AT34

DDR_A _M A4

AU34

DDR_A _M A5

BB32

DDR_A _M A6

AT32

DDR_A _M A7

AY32

DDR_A _M A8

AV32

DDR_A _M A9

BE37

DDR_A _M A1 0

BA30

DDR_A _M A1 1

BC30

DDR_A _M A1 2

AW41

DDR_A _M A1 3

AY28

DDR_A _M A1 4

AU26

DDR_A _M A1 5

M_C LK_ DDR0 [11 ,12 ,15 ]
M_C LK_ DDR# 0 [11,1 2,1 5]
DDR_A _CK E0 [1 1,1 2,1 5]

DDR_A _CS 0# [1 1,1 2,1 5]

M_O DT 0 [11, 12, 15]

DDR_A _DQ S#[ 0..7 ] [11,1 2]

DDR_A _DQ S[0 ..7] [11 ,12 ]

DDR_A _M A[0 ..15 ] [11 ,12 ,15 ]

DDR_B _D[ 0..6 3][13,1 4]

DDR_B _B S0[1 3,1 4,15 ]
DDR_B _B S1[1 3,1 4,15 ]
DDR_B _B S2[1 3,1 4,15 ]

DDR_B _CA S#[1 3,1 4,1 5]
DDR_B _RA S#[1 3,1 4,1 5]
DDR_B _WE #[13,1 4,15 ]

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D1 0
DDR_B _D1 1
DDR_B _D1 2
DDR_B _D1 3
DDR_B _D1 4
DDR_B _D1 5
DDR_B _D1 6
DDR_B _D1 7
DDR_B _D1 8
DDR_B _D1 9
DDR_B _D2 0
DDR_B _D2 1
DDR_B _D2 2
DDR_B _D2 3
DDR_B _D2 4
DDR_B _D2 5
DDR_B _D2 6
DDR_B _D2 7
DDR_B _D2 8
DDR_B _D2 9
DDR_B _D3 0
DDR_B _D3 1
DDR_B _D3 2
DDR_B _D3 3
DDR_B _D3 4
DDR_B _D3 5
DDR_B _D3 6
DDR_B _D3 7
DDR_B _D3 8
DDR_B _D3 9
DDR_B _D4 0
DDR_B _D4 1
DDR_B _D4 2
DDR_B _D4 3
DDR_B _D4 4
DDR_B _D4 5
DDR_B _D4 6
DDR_B _D4 7
DDR_B _D4 8
DDR_B _D4 9
DDR_B _D5 0
DDR_B _D5 1
DDR_B _D5 2
DDR_B _D5 3
DDR_B _D5 4
DDR_B _D5 5
DDR_B _D5 6
DDR_B _D5 7
DDR_B _D5 8
DDR_B _D5 9
DDR_B _D6 0
DDR_B _D6 1
DDR_B _D6 2
DDR_B _D6 3

DDR structure 1R X 8

DDR structure 1R X 8

@

@

UCPU1 D

UCPU1 D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43

BF40

BD45

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3

DDR_B _DQ S#0

AV3

DDR_B _DQ S#1

BG11

DDR_B _DQ S#2

BD17

DDR_B _DQ S#3

BG51

DDR_B _DQ S#4

BA59

DDR_B _DQ S#5

AT60

DDR_B _DQ S#6

AK59

DDR_B _DQ S#7

AM2

DDR_B _DQ S0

AV1

DDR_B _DQ S1

BE11

DDR_B _DQ S2

BD18

DDR_B _DQ S3

BE51

DDR_B _DQ S4

BA61

DDR_B _DQ S5

AR59

DDR_B _DQ S6

AK61

DDR_B _DQ S7

BF32

DDR_B _M A0

BE33

DDR_B _M A1

BD33

DDR_B _M A2

AU30

DDR_B _M A3

BD30

DDR_B _M A4

AV30

DDR_B _M A5

BG30

DDR_B _M A6

BD29

DDR_B _M A7

BE30

DDR_B _M A8

BE28

DDR_B _M A9

BD43

DDR_B _M A1 0

AT28

DDR_B _M A1 1

AV28

DDR_B _M A1 2

BD46

DDR_B _M A1 3

AT26

DDR_B _M A1 4

AU22

DDR_B _M A1 5

M_C LK_ DDR2 [13 ,14 ,15 ]
M_C LK_ DDR# 2 [13,1 4,1 5]
DDR_B _CK E0 [1 3,1 4,1 5]

DDR_B _CS 0# [1 3,1 4,1 5]

M_O DT 2 [13, 14, 15]

DDR_B _DQ S#[ 0..7 ] [13,1 4]

DDR_B _DQ S[0 ..7] [13 ,14 ]

DDR_B _M A[0 ..15 ] [13 ,14 ,15 ]

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P07-CPU(3/6) DDRIII

P07-CPU(3/6) DDRIII

P07-CPU(3/6) DDRIII

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

7 54Frida y, S ep tem ber 28, 20 12

7 54Frida y, S ep tem ber 28, 20 12

7 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

D D

CFG Straps for Processor

12

CFG2

RC781K_ 040 2_1 %~ D @RC781K_ 040 2_1 %~ D @

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation;
Lane # definition matches socket pin
map definition

CFG2

0:Lane Reversed

*

12

CFG4

RC811K_ 040 2_1 %~ D RC8 11K_04 02 _1% ~D

Display Port Presence Strap

C C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display

*

Port device is connected to the
Embedded Display Port

12

RC871K_ 040 2_1 %~ D @RC871K_ 040 2_1 %~ D @

12

RC861K_ 040 2_1 %~ D @RC861K_ 040 2_1 %~ D @

CFG5

CFG6

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions

*

1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled
;function 2 disabled

CFG[6:5]

01: Reserved - (Device 1 function 1
disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1

B B

and 2 enabled

12

RC891K_ 040 2_1 %~ D @RC891K_ 040 2_1 %~ D @

CFG7

4

VCC_ DIE_ SE NSE

RC14 2

@ RC14 2

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

12

RC14 3

RC14 3
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

3

@

@

UCPU1 E

UCPU1 E

B50

CFG0

T23 2@ T2 32@

CFG1

T20 8@ T2 08@

CFG2
CFG3

T20 9@ T2 09@

CFG4
CFG5
CFG6
CFG7
CFG8

T21 3@ T2 13@

CFG9

T21 0@ T2 10@

CFG1 0

T21 1@ T2 11@

CFG1 1

T21 2@ T2 12@

CFG1 2

T23 5@ T2 35@

CFG1 3

T23 6@ T2 36@

CFG1 4

T23 7@ T2 37@

CFG1 5

T23 8@ T2 38@

CFG1 6

T21 4@ T2 14@

CFG1 7

T21 5@ T2 15@

CPU_ RSV D6
CPU_ RSV D7

12

RC14 4

RC14 4
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53

F53

G53

L51
F51

D52

L53

H43
K43

H45
K45

F48

H48
K48

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22

BE22

BG26

BE26
BF23
BE24

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RSVD6
RSVD7

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

RESERVED

RESERVED

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BD61
DC_TEST_BE61

DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

BCLK_ITP

BCLK_ITP#

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

N59
N58

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

CLK_ RES _IT P
CLK_ RES _IT P#

DC_T ES T_ C4_D 3

DC_T ES T_ A59 _C5 9

DC_T ES T_ A61 _C6 1

DC_T ES T_ BE6 1_B E5 9

DC_T ES T_ BG3 _BE 3

DC_T ES T_ BG1 _BE 1

2

T23 3@ T2 33@
T23 4@ T2 34@

1

PEG DEFER TRAINING

1: (Default) PEG Train immediately

*

following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for training

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P08-CPU(4/6) RSVD,CFG

P08-CPU(4/6) RSVD,CFG

P08-CPU(4/6) RSVD,CFG

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

8 54Frida y, S ep tem ber 28, 20 12

8 54Frida y, S ep tem ber 28, 20 12

8 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

ULV-DC Icc(max)=33A

D D

C C

B B

A A

+VCC _COR E

@

@

UCPU1 F

UCPU1 F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

POWER

POWER

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]

AB20

PEG IO AND DDR IO

PEG IO AND DDR IO

VCCIO[33]

AC13

CORE SUPPLY

CORE SUPPLY

5

VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50
VCCIO51

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

RAILS

RAILS

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

SENSE LINES SVID QUIET

+VCC _COR E

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
CC219

CC219

1

2

AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
CC220

CC220

H_VC CP_ SEL

VCCS ENS E_R

+VCC P

8.5A

+1.0 5VS _V CCPQ

1

CC22 4

CC22 4
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+VCC P

H_CP U_S VIDA LRT #
H_CP U_S VIDCL K
H_CP U_S VIDDA T

+VCC _COR E

RC97 1 00_ 04 02_ 1%~ DRC 97 10 0_ 040 2_1 %~D
RC98 0 _04 02 _5% ~D@RC9 8 0_ 040 2_5 %~ D@
RC99 0 _04 02 _5% ~D@RC9 9 0_ 040 2_5 %~ D@
RC10 0 100_0 402 _1 %~DRC100 100 _04 02 _1% ~D

+VCC P

1 2

RC12 6 10_ 040 2_ 5%~ DRC1 26 10 _04 02 _5% ~D

1 2

RC12 9 10_ 040 2_ 5%~ DRC1 29 10 _04 02 _5% ~D

Place the PU
resistors close to CPU

+VCC P

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

CC221

CC221

2

2

Close to JCPU1

4

+1.3 5V_ CPU _VD DQ

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC160

CC160

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC233

CC233

1

2

+1.8 VS

11

@

@

1 2

RC10 9 0_0 805 _5 %~D

RC10 9 0_0 805 _5 %~D

SHORT

@

T22 3@T22 3

+VCC P

RH28 0

@RH280

@

0_0 603 _5 %~D

0_0 603 _5 %~D

12

SHORT

1 2

RC93 7 5_0 40 2_5 %RC93 7 5_0 40 2_5 %

1 2

RC94 4 3_0 40 2_5 %~DRC9 4 43_ 04 02_ 5%~ D

1 2

RC92 0 _04 02 _5% ~D@RC9 2 0_ 040 2_5 %~ D@

1 2

RC96 0 _04 02 _5% ~D@RC9 6 0_ 040 2_5 %~ D@

1 2

RC95 1 30_ 04 02_ 5%~ DRC 95 13 0_ 040 2_5 %~D

RC95 close to CPU

1 2
1 2
1 2
1 2

+1.3 5V_ CPU _VD DQ

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CC222

CC222

CC223

CC223

2

4

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

+VCC SA

VIDALERT#
Connect one end of s eries-resistor 43±5% close t o
processor and pull-up to VCCI O through 75±5% on
the other end of the series-resist or towards Int el MVP 7.

1

2

1

1

1

CC164

CC164

CC162

CC162

CC163

CC163

CC161

CC161

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC238

CC238

1U_0402_6.3V6K~D

CC239

CC239

CC234

CC234

CC240

CC240

1

1

1

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

1

CC167

CC167

CC168

CC168

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC227

@

@ CC226

@

1

1

1

CC227

CC226

2

2

2

+1.8 VS_ VCC PLL

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC172

@

1

1

1

CC172

CC174

CC174

2

2

2

VR_S VID _AL RT# [4 4]
VR_S VID _CL K [44]
VR_S VID _DA T [44]

+VCC P

VIDSOUT:
Requires a pull-up t o VCCIO through a pull-up res istor of 130 ±5% c lose to t he processor, and a pull-up
to VCCIO through a pull-up res istor of 130 ±5% c lose to I ntel MVP 7.
VIDSCLK:
Required pull-up to VC CIO through 55 ±5% close to Intel IMVP 7.

VCCS ENS E [44]
VSS SEN SE [44]

VCCIO _S ENSE [ 41]
VSS IO_ SEN SE [41]

1

2

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CC169

CC169

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC228

@

CC228

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC175

CC175

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC165

CC165

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC235

CC235

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@ CC170

@

1

CC170

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC229

@

1

CC229

2

1

+

+

CC17 6

CC17 6
330 U_D2 _2 .5VM _R 6M ~D

330 U_D2 _2 .5VM _R 6M ~D

2

VCC_ AXG _S ENSE[44]
VSS _AX G_ SENS E[4 4]

CC231

CC231

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC241

CC241

1

2

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC232

CC232

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC236

CC236

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@ CC225

@

1

CC225

+

+

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC230

@

CC230

+VCC _GFX COR E_A XG

1

+

+

2

1

2

CC17 1

CC17 1
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

3

330U_B2_2VM_R15M

330U_B2_2VM_R15M

CC166

CC166

ULV-DC GT2 29A
ULV-DC GT1 18A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC242

CC242

12

12

3

+VCC _GFX COR E_A XG

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC237

CC237

1

2

RC13 5

RC13 5
100 _04 02 _5% ~D

100 _04 02 _5% ~D

RC13 6

RC13 6
100 _04 02 _5% ~D

100 _04 02 _5% ~D

1.2A

+1.8 VS_ VCC PLL

+VCC SA

4A (ULV-DC)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

@

@

UCPU1 G

UCPU1 G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

POWER

POWER

GRAPHICS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

1.8V RAIL

SA RAIL

SA RAIL

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SA_DIMM_VREFDQ

VREF

VREF

SB_DIMM_VREFDQ

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

QUIET RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

SENSE LINES

VCCSA_VID[0]
VCCSA_VID[1]

VCCSA VID

lines

VCCSA VID

lines

2

+V_SM_VREF should
have 10 mil trace width

AY43

SM_VREF

BE7
BG7

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

VDDQ[4]

AL30

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36

VDDQ[10]

AM40

VDDQ[11]

AN30

VDDQ[12]

AN34

VDDQ[13]

AN38

VDDQ[14]

AR26

VDDQ[15]

AR28

VDDQ[16]

AR30

VDDQ[17]

AR32

VDDQ[18]

AR34

VDDQ[19]

AR36

VDDQ[20]

AR40

VDDQ[21]

AV41

VDDQ[22]

AW26

VDDQ[23]

BA40

VDDQ[24]

BB28

VDDQ[25]

BG33

VDDQ[26]

AM28

VCCDQ[1]

AN26

VCCDQ[2]

BC43
BA43

U10

D48
D49

1

0_0 402 _5 %~D

0_0 402 _5 %~D

+VRE FDQ_ A

QC6

@ QC 6

+V_ SM_ VRE F

V_DD R_RE FA_ R [15]
V_DD R_RE FB_ R [15]

+1.3 5V_ CPU _VD DQ

5A

+0.6 75V S

RC10 6 0_0 402 _5 %~D@ RC 106 0 _04 02_ 5% ~D@

+1.3 5V_ CPU _VD DQ +1.3 5V

+1.3 5V_ CPU _VD DQ

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CC218

CC218

2

Tit le

Tit le

Tit le

P09-CPU(5/6) PWR,BYPASS

P09-CPU(5/6) PWR,BYPASS

P09-CPU(5/6) PWR,BYPASS

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

@

AP2 302 GN-H F_SO T2 3-3

AP2 302 GN-H F_SO T2 3-3

CPU1 .5V _S3 _GA TE[32,3 5,4 2,6 ]

+V_ SM_ VRE F

1 2

12

CC18 2 0 .1U_ 04 02_ 10V 7K ~DCC182 0.1U_0 40 2_1 0V 7K~ D

12

CC18 4 0 .1U_ 04 02_ 10V 7K ~DCC184 0.1U_0 40 2_1 0V 7K~ D

12

CC18 1 0 .1U_ 04 02_ 10V 7K ~DCC181 0.1U_0 40 2_1 0V 7K~ D

12

CC18 3 0 .1U_ 04 02_ 10V 7K ~DCC183 0.1U_0 40 2_1 0V 7K~ D

VCCS A_S ENS E [43 ]

VCCS A_V ID0 [4 3]
VCCS A_V ID1 [4 3]

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

RCU1

@ RCU 1

@

1 2

123

+1.3 5V_ CPU _VD DQ

12

RC11 2

RC11 2
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

12

RC11 6

RC11 6
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+V_ SM_ VRE F

12

RC14 1

@ RC1 41

@

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

9 54Frida y, S ep tem ber 28, 20 12

9 54Frida y, S ep tem ber 28, 20 12

9 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

@

@

UCPU1 H

UCPU1 H

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

A9

AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

@

@

UCPU1 I

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

UCPU1 I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

VSS

VSS

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11

NCTF

NCTF

VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P10-CPU(6/6) PWR,VSS

P10-CPU(6/6) PWR,VSS

P10-CPU(6/6) PWR,VSS

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

10 54Fri da y, S epte mb er 2 8, 201 2

10 54Fri da y, S epte mb er 2 8, 201 2

10 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

DDR_A _DQ S#[ 0..7 ][1 2,7 ]

DDR_A _DQ S[0 ..7][12, 7]

DDR_A _D[ 0..6 3][12 ,7]

DDR_A _M A[0 ..15 ][12, 15,7 ]

All VREF traces should
have 10 mil trace width

UD3

UD3

UD4

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD3

UD3

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD3

UD3

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD3

UD3

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD3

UD3

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD3

UD3

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD4

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD4

UD4

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD4

UD4

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD4

UD4

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD4

UD4

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD4

UD4

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD2

UD2

UD1

UD1

C C

B B

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD1

UD1

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD1

UD1

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD1

UD1

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD1

UD1

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD1

UD1

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD2

UD2

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD2

UD2

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD2

UD2

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD2

UD2

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD2

UD2

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_A _DQ S0
DDR_A _DQ S#0

DDR_A _D2
DDR_A _D1
DDR_A _D7
DDR_A _D4
DDR_A _D3
DDR_A _D0
DDR_A _D6
DDR_A _D5

12

RD1 240 _0 402 _1 %RD1 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

DDR_A _DQ S2
DDR_A _DQ S#2

DDR_A _D1 8
DDR_A _D1 6
DDR_A _D1 9
DDR_A _D2 2
DDR_A _D1 7
DDR_A _D2 0
DDR_A _D2 3
DDR_A _D2 1

12

RD3 240 _0 402 _1 %RD3 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

@

@

UD1

UD1

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD3

UD3

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

DDR_A _DQ S1
DDR_A _DQ S#1

DDR_A _D1 0
DDR_A _D1 2
DDR_A _D1 4
DDR_A _D1 3
DDR_A _D1 1
DDR_A _D8
DDR_A _D1 5
DDR_A _D9

12

RD2 240 _0 402 _1 %RD2 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _DQ S3
DDR_A _DQ S#3

DDR_A _D3 0
DDR_A _D2 5
DDR_A _D3 1
DDR_A _D2 4
DDR_A _D2 6
DDR_A _D2 8
DDR_A _D2 7
DDR_A _D2 9

12

RD4 240 _0 402 _1 %RD4 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

2

@

@

UD2

UD2

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD4

UD4

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

+1.3 5V

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

1

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

Memory Channel A SPD EEPROM

+1.3 5V +3V S

A A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD1

CD1

CD2

CD2

1

12

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD4

CD4

CD3

CD3

1

12

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD5

CD5

CD6

CD6

1

12

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD7

CD7

CD8

CD8

1

12

2

4

1

+

+

CD12 5

CD12 5
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

+3V S

PCH_ SM BCL K[1 3,1 7,3 4]
PCH_ SM BDA TA[13 ,17 ,34 ]

2

UD17

@ UD17

@

AT2 4C0 2C-X HM-T _T SS OP 8

AT2 4C0 2C-X HM-T _T SS OP 8

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND4SDA

Non-CIS part

@

@

1
2
3

12

RD39 1 K_ 040 2_5 %~ D

RD39 1 K_ 040 2_5 %~ D

12

RD40 1 K_ 040 2_5 %~ D

RD40 1 K_ 040 2_5 %~ D

@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P11-DDRIII C hannel_A Lower

P11-DDRIII C hannel_A Lower

P11-DDRIII C hannel_A Lower

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

@ CD127

@

1

1

CD12 7

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

11 54Fri da y, S epte mb er 2 8, 201 2

11 54Fri da y, S epte mb er 2 8, 201 2

11 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

D D

DDR_A _DQ S#[ 0..7 ][1 1,7 ]

DDR_A _DQ S[0 ..7][11, 7]

DDR_A _D[ 0..6 3][11 ,7]

DDR_A _M A[0 ..15 ][11, 15,7 ]

All VREF traces should
have 10 mil trace width

UD7

UD7

UD8

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD7

UD7

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD7

UD7

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD7

UD7

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD7

UD7

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD7

UD7

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD8

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD8

UD8

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD8

UD8

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD8

UD8

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD8

UD8

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD8

UD8

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD5

UD5

UD6

UD6

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD5

UD5

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD5

UD5

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD5

UD5

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD5

UD5

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD5

UD5

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5P R0L

UD6

UD6

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD6

UD6

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD6

UD6

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD6

UD6

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD6

UD6

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

C C

B B

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_A _DQ S4
DDR_A _DQ S#4

DDR_A _D3 5

DDR_A _D3 6
DDR_A _D3 9
DDR_A _D3 7
DDR_A _D3 8
DDR_A _D3 2
DDR_A _D3 4

12

RD5 240 _0 402 _1 %RD5 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

DDR_A _DQ S6
DDR_A _DQ S#6

DDR_A _D5 4
DDR_A _D4 9
DDR_A _D5 0
DDR_A _D5 1
DDR_A _D5 2
DDR_A _D4 8
DDR_A _D5 3
DDR_A _D5 5

12

RD7 240 _0 402 _1 %RD7 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

@

@

UD5

UD5

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD7

UD7

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

DDR_A _DQ S5
DDR_A _DQ S#5

DDR_A _D4 2
DDR_A _D4 1DDR_A _D3 3
DDR_A _D4 6
DDR_A _D4 4
DDR_A _D4 7
DDR_A _D4 5
DDR_A _D4 3
DDR_A _D4 0

12

RD6 240 _0 402 _1 %RD6 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _DQ S7
DDR_A _DQ S#7

DDR_A _D5 9
DDR_A _D5 7
DDR_A _D5 8
DDR_A _D6 0
DDR_A _D5 6
DDR_A _D6 1
DDR_A _D6 2
DDR_A _D6 3

12

RD8 240 _0 402 _1 %RD8 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

2

@

@

UD6

UD6

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD8

UD8

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

1

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0
M_C LK_ DDR0M_C LK_ DDR0
M_C LK_ DDR# 0
DDR_A _CK E0

DDR_A _CS 0#
DDR_A _RA S#
DDR_A _CA S#
DDR_A _WE #
DDR3_ DRA MRS T#

M_O DT 0
M_C LK_ DDR0M_C LK_ DDR0
M_C LK_ DDR# 0
DDR_A _CK E0

DDR_A _CS 0#
DDR_A _RA S#
DDR_A _CA S#
DDR_A _WE #
DDR3_ DRA MRS T#

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

+1.3 5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD30

CD30

CD29

CD29

1

A A

12

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD33

CD34

CD34

1

12

2

5

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD38

CD38

CD37

CD37

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD41

CD41

CD42

CD42

1

12

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P12-DDRIII C hannel_A Upper

P12-DDRIII C hannel_A Upper

P12-DDRIII C hannel_A Upper

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

12 54Fri da y, S epte mb er 2 8, 201 2

12 54Fri da y, S epte mb er 2 8, 201 2

12 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

DDR_B _DQ S#[ 0..7 ][1 4,7 ]

DDR_B _DQ S[0 ..7][14, 7]

DDR_B _D[ 0..6 3][14 ,7]

DDR_B _M A[0 ..15 ][14, 15,7 ]

All VREF traces should
have 10 mil trace width

UD9

UD9

UD10

UD10

C C

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@

X76 _M IC_4 G@

X76 _M IC_4 G@

SA0 000 5S O0L

SA0 000 5S O0L

SA0 000 5S O0L

SA0 000 5S O0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@

X76 _HY N_2 G@

X76 _HY N_2 G@

SA0 000 4RG 0L

SA0 000 4RG 0L

SA0 000 4RG 0L

SA0 000 4RG 0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@

X76 _HY N_4 G@

X76 _HY N_4 G@

SA0 000 5JT 0L

SA0 000 5JT 0L

SA0 000 5JT 0L

UD9

UD9

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD9

UD9

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5JT 0L

UD10

UD10

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD10

UD10

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

B B

UD11

UD11

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD11

UD11

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD11

UD11

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD11

UD11

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD11

UD11

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD11

UD11

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD12

UD12

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD12

UD12

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD12

UD12

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD12

UD12

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD12

UD12

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD12

UD12

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_B _DQ S0
DDR_B _DQ S#0

DDR_B _D3
DDR_B _D4
DDR_B _D2
DDR_B _D7
DDR_B _D0
DDR_B _D5
DDR_B _D6
DDR_B _D1

12

RD9 240 _0 402 _1 %RD9 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

DDR_B _DQ S2
DDR_B _DQ S#2

DDR_B _D2 2
DDR_B _D1 8
DDR_B _D1 6
DDR_B _D2 3
DDR_B _D2 0
DDR_B _D1 7
DDR_B _D1 9
DDR_B _D2 1

12

RD11 2 40_ 04 02_ 1%R D11 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

@

@

UD9

UD9

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD11

UD11

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

DDR_B _DQ S1
DDR_B _DQ S#1

DDR_B _D1 5
DDR_B _D1 2
DDR_B _D1 0
DDR_B _D9
DDR_B _D1 4
DDR_B _D8
DDR_B _D1 1
DDR_B _D1 3

12

RD10 2 40_ 04 02_ 1%R D10 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _DQ S3
DDR_B _DQ S#3

DDR_B _D3 0
DDR_B _D2 4
DDR_B _D2 6
DDR_B _D2 8
DDR_B _D2 7
DDR_B _D2 5
DDR_B _D3 1
DDR_B _D2 9

12

RD12 2 40_ 04 02_ 1%R D12 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

2

@

@

UD10

UD10

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD12

UD12

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

+1.3 5V

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

1

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

A A

1U_0402_6.3V6K~D

CD58

CD58

CD57

CD57

1

12

2

5

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD60

CD60

CD59

CD59

1

12

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD62

CD62

CD61

CD61

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD63

CD63

CD64

CD64

1

12

2

1

+

+

CD12 6

CD12 6
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Memory Channel B SPD EEPROM

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

+3V S

PCH_ SM BCL K[1 1,1 7,3 4]
PCH_ SM BDA TA[11 ,17 ,34 ]

2

UD18

@ UD18

@

AT2 4C0 2C-X HM-T _T SS OP 8

AT2 4C0 2C-X HM-T _T SS OP 8

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND4SDA

Non-CIS part

@

@

1

RD41 1 K_ 040 2_5 %~ D

RD41 1 K_ 040 2_5 %~ D

2

RD42 1 K_ 040 2_5 %~ D

RD42 1 K_ 040 2_5 %~ D

3

@

@

Tit le

Tit le

Tit le

P13-DDRIII C hannel_B Lower

P13-DDRIII C hannel_B Lower

P13-DDRIII C hannel_B Lower

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

+3V S

12
12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

+3V S

1

CD12 8

@ CD128

@

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

13 54Fri da y, S epte mb er 2 8, 201 2

13 54Fri da y, S epte mb er 2 8, 201 2

13 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

D D

DDR_B _DQ S#[ 0..7 ][1 3,7 ]

DDR_B _DQ S[0 ..7][13, 7]

DDR_B _D[ 0..6 3][13 ,7]

DDR_B _M A[0 ..15 ][13, 15,7 ]

All VREF traces should
have 10 mil trace width

UD13

UD13

UD14

UD14

UD15

UD15

UD16

UD16

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD13

UD13

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD13

UD13

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD13

UD13

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD13

UD13

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD13

UD13

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5P R0L

UD14

UD14

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD14

UD14

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD14

UD14

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD14

UD14

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD14

UD14

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

C C

B B

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD15

UD15

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD15

UD15

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD15

UD15

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD15

UD15

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD15

UD15

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD16

UD16

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD16

UD16

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD16

UD16

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD16

UD16

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD16

UD16

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_B _DQ S4
DDR_B _DQ S#4

DDR_B _D3 4

DDR_B _D3 5
DDR_B _D3 8
DDR_B _D3 2
DDR_B _D3 7
DDR_B _D3 9
DDR_B _D3 6

12

RD13 2 40_ 04 02_ 1%R D13 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

DDR_B _DQ S6
DDR_B _DQ S#6

DDR_B _D5 0
DDR_B _D4 9
DDR_B _D5 5
DDR_B _D5 1
DDR_B _D5 3
DDR_B _D4 8
DDR_B _D5 4
DDR_B _D5 2

12

RD15 2 40_ 04 02_ 1%R D15 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

@

@

UD13

UD13

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD15

UD15

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

DDR_B _DQ S5
DDR_B _DQ S#5

DDR_B _D4 2
DDR_B _D4 1DDR_B _D3 3
DDR_B _D4 7
DDR_B _D4 4
DDR_B _D4 5
DDR_B _D4 6
DDR_B _D4 3
DDR_B _D4 0

12

RD14 2 40_ 04 02_ 1%R D14 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _DQ S7
DDR_B _DQ S#7

DDR_B _D6 3
DDR_B _D5 6
DDR_B _D5 9
DDR_B _D5 7
DDR_B _D5 8
DDR_B _D6 1
DDR_B _D6 2
DDR_B _D6 0

12

RD16 2 40_ 04 02_ 1%R D16 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

2

@

@

UD14

UD14

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD16

UD16

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

1

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2
M_C LK_ DDR2M_C LK_ DDR2
M_C LK_ DDR# 2
DDR_B _CK E0

DDR_B _CS 0#
DDR_B _RA S#
DDR_B _CA S#
DDR_B _WE #
DDR3_ DRA MRS T#

M_O DT 2
M_C LK_ DDR2M_C LK_ DDR2
M_C LK_ DDR# 2
DDR_B _CK E0

DDR_B _CS 0#
DDR_B _RA S#
DDR_B _CA S#
DDR_B _WE #
DDR3_ DRA MRS T#

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

+1.3 5V +1.3 5V+1.3 5V +1.3 5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD85

CD85

CD86

CD86

1

A A

12

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD87

CD87

CD88

CD88

1

12

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD89

CD89

CD90

CD90

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD91

CD91

CD92

CD92

1

12

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P14-DDRIII C hannel_B Upper

P14-DDRIII C hannel_B Upper

P14-DDRIII C hannel_B Upper

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et

Date : She et of

Date : She et of

1

of

14 54Fri da y, S epte mb er 2 8, 201 2

14 54Fri da y, S epte mb er 2 8, 201 2

14 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

+1.3 5V

12

RD17

RD17
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD19
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

D D

1

CD113

CD113

2

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

12

RD19

+VRE FCA_ A

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

CD114

CD114

2

RD18

RD18
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD20

RD20
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

+1.3 5V

4

3

2

1

12

+VRE FCA_ B

.1U_0402_16V7K~D

.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

12

1

1

CD116

CD116

CD115

CD115

2

2

+1.3 5V

M1 M1

12

RD21

RD21
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

12

RD25

RD25
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

M3

C C

B B

A A

+VRE FDQ_ A

Deep S3 Support

+VRE FDQ_ B

Deep S3 Support

DRAM RST _C NTRL

DRAM RST _C NTRL

5

DRAM RST _C NTRL[6 ]

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

+VRE FDQ_ A

RD27 0 _04 02 _5% ~D@RD2 7 0_ 040 2_5 %~ D@

RD30 0 _04 02 _5% ~D@RD3 0 0_ 040 2_5 %~ D@

1 2

1 3

D

D

1 2

1 3

D

D

+VRE FDQ_ A

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

1

2

S

S

G

G

2

QD1

QD1

BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

S

S

G

G

2

QD2

QD2

BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

CD118

CD118

CD117

CD117

2

V_DD R_RE FA_ R [9]

12

RD29

@ RD29

@

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

V_DD R_RE FB_ R [9]

12

RD32

@ RD32

@

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+1.3 5V

12

12

RD22

RD22
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD26

RD26
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

4

+VRE FDQ_ B

+VRE FDQ_ B

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

1

CD119

CD119

CD120

CD120

2

2

+0.675VS +0.675VS

DDR_A _M A1 2
DDR_A _M A1 5
DDR_A _M A0

DDR_A _M A[0 ..15 ][11, 12,7 ]

DDR_B _M A[0 ..15 ][13, 14,7 ]

+0.675VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD12 9

CD12 9

2

+0.675VS

1

CD13 6

CD13 6

2

CD13 3

CD13 3

CD13 2

CD13 2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD13 9

CD13 9

CD14 0

CD14 0

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD13 5

CD13 5

2

2

DDR_A _CK E0[11 ,12 ,7]
DDR_A _RA S#[11 ,12 ,7]
DDR_A _CS 0#[1 1,1 2,7 ]
DDR_A _CA S#[11 ,12 ,7]

DDR_A _WE #[11 ,12, 7]
DDR_A _B S0[11, 12, 7]
DDR_A _B S2[11, 12, 7]
DDR_A _B S1[11, 12, 7]

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD14 2

CD14 2

2

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

M_O DT 0[11,12, 7] M_O DT 2[13,14, 7]

M_C LK_ DDR0[11 ,12, 7]

M_C LK_ DDR# 0[11,1 2,7 ]

Issued Date

Issued Date

Issued Date

DDR_A _M A1 0

DDR_A _M A4
DDR_A _M A2
DDR_A _M A1
DDR_A _M A6

DDR_A _M A3
DDR_A _M A9
DDR_A _M A1 1
DDR_A _M A5

DDR_A _M A1 4
DDR_A _M A7
DDR_A _M A8
DDR_A _M A1 3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

1 2

R103 6 36 _0 402 _1 %~DR 103 6 36 _0 402 _1 %~D

1 2

R103 8 36 _0 402 _1 %~DR 103 8 36 _0 402 _1 %~D

1 2

R104 0 36 _0 402 _1 %~DR 104 0 36 _0 402 _1 %~D

1 2

R104 2 36 _0 402 _1 %~DR 104 2 36 _0 402 _1 %~D

1 2

R104 4 36 _0 402 _1 %~DR 104 4 36 _0 402 _1 %~D

1 2

R104 6 36 _0 402 _1 %~DR 104 6 36 _0 402 _1 %~D

1 2

R104 8 36 _0 402 _1 %~DR 104 8 36 _0 402 _1 %~D

1 2

R105 0 36 _0 402 _1 %~DR 105 0 36 _0 402 _1 %~D

1 2

R105 2 36 _0 402 _1 %~DR 105 2 36 _0 402 _1 %~D

1 2

R105 4 36 _0 402 _1 %~DR 105 4 36 _0 402 _1 %~D

1 2

R105 6 36 _0 402 _1 %~DR 105 6 36 _0 402 _1 %~D

1 2

R105 8 36 _0 402 _1 %~DR 105 8 36 _0 402 _1 %~D

1 2

R106 0 36 _0 402 _1 %~DR 106 0 36 _0 402 _1 %~D

1 2

R106 2 36 _0 402 _1 %~DR 106 2 36 _0 402 _1 %~D

1 2

R106 4 36 _0 402 _1 %~DR 106 4 36 _0 402 _1 %~D

1 2

R106 6 36 _0 402 _1 %~DR 106 6 36 _0 402 _1 %~D

1 2

R106 8 36 _0 402 _1 %~DR 106 8 36 _0 402 _1 %~D

1 2

R107 0 36 _0 402 _1 %~DR 107 0 36 _0 402 _1 %~D

1 2

R107 2 36 _0 402 _1 %~DR 107 2 36 _0 402 _1 %~D

1 2

R107 4 36 _0 402 _1 %~DR 107 4 36 _0 402 _1 %~D

1 2

R107 6 36 _0 402 _1 %~DR 107 6 36 _0 402 _1 %~D

1 2

R107 8 36 _0 402 _1 %~DR 107 8 36 _0 402 _1 %~D

1 2

R108 0 36 _0 402 _1 %~DR 108 0 36 _0 402 _1 %~D

1 2

R108 2 36 _0 402 _1 %~DR 108 2 36 _0 402 _1 %~D

RD33

RD33
36_ 040 2_ 1%~ D

36_ 040 2_ 1%~ D

1 2

1 2

RD35 3 0_0 40 2_1 %~DRD3 5 30_ 04 02_ 1%~ D

1

CD12 1

CD12 1

1.5P _0 402 _5 0V8 C~D

1.5P _0 402 _5 0V8 C~D

2

1 2

RD37 3 0_0 40 2_1 %~DRD3 7 30_ 04 02_ 1%~ D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CD12 3

CD12 3

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

DDR_B _M A1 2
DDR_B _M A1 5
DDR_B _M A0
DDR_B _M A1 0

DDR_B _M A1 4
DDR_B _M A6
DDR_B _M A4
DDR_B _M A2

DDR_B _M A8
DDR_B _M A1
DDR_B _M A1 3
DDR_B _M A7

DDR_B _M A3
DDR_B _M A9
DDR_B _M A1 1
DDR_B _M A5

DDR_B _CK E0[13 ,14 ,7]
DDR_B _CS 0#[1 3,1 4,7 ]
DDR_B _CA S#[13 ,14 ,7]
DDR_B _RA S#[13 ,14 ,7]

DDR_B _B S1[13, 14, 7]
DDR_B _B S2[13, 14, 7]
DDR_B _B S0[13, 14, 7]
DDR_B _WE #[13 ,14, 7]

M_C LK_ DDR2[13 ,14, 7]

M_C LK_ DDR# 2[13,1 4,7 ]

1

2

Tit le

Tit le

Tit le

P15-DDRIII Vref & Ter mination

P15-DDRIII Vref & Ter mination

P15-DDRIII Vref & Ter mination

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et

Date : She et of

Date : She et of

1 2

R103 7 36 _0 402 _1 %~DR 103 7 36 _0 402 _1 %~D

1 2

R103 9 36 _0 402 _1 %~DR 103 9 36 _0 402 _1 %~D

1 2

R104 1 36 _0 402 _1 %~DR 104 1 36 _0 402 _1 %~D

1 2

R104 3 36 _0 402 _1 %~DR 104 3 36 _0 402 _1 %~D

1 2

R104 5 36 _0 402 _1 %~DR 104 5 36 _0 402 _1 %~D

1 2

R104 7 36 _0 402 _1 %~DR 104 7 36 _0 402 _1 %~D

1 2

R104 9 36 _0 402 _1 %~DR 104 9 36 _0 402 _1 %~D

1 2

R105 1 36 _0 402 _1 %~DR 105 1 36 _0 402 _1 %~D

1 2

R105 3 36 _0 402 _1 %~DR 105 3 36 _0 402 _1 %~D

1 2

R105 5 36 _0 402 _1 %~DR 105 5 36 _0 402 _1 %~D

1 2

R105 7 36 _0 402 _1 %~DR 105 7 36 _0 402 _1 %~D

1 2

R105 9 36 _0 402 _1 %~DR 105 9 36 _0 402 _1 %~D

1 2

R106 1 36 _0 402 _1 %~DR 106 1 36 _0 402 _1 %~D

1 2

R106 3 36 _0 402 _1 %~DR 106 3 36 _0 402 _1 %~D

1 2

R106 5 36 _0 402 _1 %~DR 106 5 36 _0 402 _1 %~D

1 2

R106 7 36 _0 402 _1 %~DR 106 7 36 _0 402 _1 %~D

1 2

R106 9 36 _0 402 _1 %~DR 106 9 36 _0 402 _1 %~D

1 2

R107 1 36 _0 402 _1 %~DR 107 1 36 _0 402 _1 %~D

1 2

R107 3 36 _0 402 _1 %~DR 107 3 36 _0 402 _1 %~D

1 2

R107 5 36 _0 402 _1 %~DR 107 5 36 _0 402 _1 %~D

1 2

R107 7 36 _0 402 _1 %~DR 107 7 36 _0 402 _1 %~D

1 2

R107 9 36 _0 402 _1 %~DR 107 9 36 _0 402 _1 %~D

1 2

R108 1 36 _0 402 _1 %~DR 108 1 36 _0 402 _1 %~D

1 2

R108 3 36 _0 402 _1 %~DR 108 3 36 _0 402 _1 %~D

RD34

RD34
36_ 040 2_ 1%~ D

36_ 040 2_ 1%~ D

1 2

1 2

RD36 3 0_0 40 2_1 %~DRD3 6 30_ 04 02_ 1%~ D

1

CD12 2

CD12 2

1.5P _0 402 _5 0V8 C~D

1.5P _0 402 _5 0V8 C~D

2

1 2

RD38 3 0_0 40 2_1 %~DRD3 8 30_ 04 02_ 1%~ D

CD12 4

CD12 4

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

15 54Fri da y, S epte mb er 2 8, 201 2

15 54Fri da y, S epte mb er 2 8, 201 2

15 54Fri da y, S epte mb er 2 8, 201 2

1

1

2

1.0

1.0

1.0

of

5

D D

+RT CVCC

1 2

1 2

LOW=Default
HIGH=No Reboot

+3V _PCH+3V _PC H+ 3V_ PCH

12

RH40

RH40

RH39

RH39

@

@

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

12

RH46

RH46

RH45

RH45

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

12

HDA_ SDO UT

HDA_ SDO UT

12

PCH_ INT VRM EN

HDA_ SPK R

HDA_ SYN C

PCH_ JTA G_ TM S
PCH_ JTA G_ TDI
PCH_ JTA G_ TDO

PCH_ JTA G_ TCK

RH53

RH53
51_ 040 2_ 5%

51_ 040 2_ 5%

RH31 330K _04 02 _5% ~DRH31 330 K_0 402 _5 %~D

RH34 330K _04 02 _5% ~D@ RH 34 330K_ 04 02_ 5% ~D@

INTVRMEN

H：Integrated VRM enable

*

C C

+3V S

RH37 1 K_0 402 _5 %~D@ R H37 1K _0 402 _5% ~D@

L：Integrated VRM disa ble

1 2

*

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in ef fect (default)

H=>Flash Descriptor Security will be overridde n

+3V _PCH

1 2

RH42 1 K_0 402 _5 %~D@ R H42 1K _0 402 _5% ~D@

Low = Disabl ed

*

High = Enabled

B B

HDA_SYNC

This si gnal h as a weak i nternal pu ll-down

is s upplied by

apled hi gh
mpled low
ulled Hi gh for Huron River p latfrom

+3V _PCH

1 2

RH27 9 1K_ 040 2_ 5%~ DRH27 9 1K_ 040 2_ 5%~ D

PCH JTAG

12

12

RH38

RH38

@

@

@

@

200_0402_5%

200_0402_5%

12

12

RH44

RH44

A A

100_0402_1%~D

100_0402_1%~D

CH10 3 10P _04 02 _50 V8J ~D@ C H10 3 10P _04 02_ 50 V8J ~D@

+RT CVCC

RH25 20K_0 402 _5 %~DRH25 20K_0 402 _5 %~D

RH23 20K_0 402 _5 %~DRH23 20K_0 402 _5 %~D

HDA_ SYN C_AU DIO[ 25]

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1 2

1 2

CH5

CH5

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1

CH4

CH4

2

1

2

Reserve for RF please close to UH1

5

4

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

CMOS

12

@

@

CLRP 1

CLRP 1
SHOR T P ADS

SHOR T P ADS

PCH_ RTC RST #

PCH_ SRT CRST #

12

@

@

CLRP 2

CLRP 2
SHOR T P ADS

SHOR T P ADS

ME CMOS

CLP1 & CLP2 place near DIMM

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

1 2

HDA_ SYN C_R HDA _S YNC

RH33 33_0 402 _5 %~DRH33 33_04 02 _5% ~D

1 2

4

CH2 1 8P _04 02 _50 V8J ~DCH 2 1 8P_ 04 02_ 50V 8J~ D

CH3 1 8P _04 02 _50 V8J ~DCH 3 1 8P_ 04 02_ 50V 8J~ D

far away hot spot

HDA_ BIT CLK _AU DIO

1

CH11 7

CH11 7

2

CH11 8

@ CH11 8

@

1 2

12P _04 02 _50 V8J ~D

12P _04 02 _50 V8J ~D

+5V S

G

G

2

S

S

1 2

RH36 0 _04 02 _5% ~D@R H36 0 _04 02_ 5% ~D@

RH27 5

RH27 5
1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

PCH_ SPI _CS #

PCH_ SPI _SO

2

8/20, Follow DFB suggest, modify YH1 footprint.

12

12

12

RH2

RH2

YH1

YH1

10M _0 402 _5 %

10M _0 402 _5 %

12

RH11

RH11

+RT CVCC

HDA_ SPK R[25]

HDA_ RST _A UDIO#[2 5]

HDA_ SDIN 0[25]

HDA_ SDO UT_ AUDI O[ 25]

HDA_ SDO[35]

From EC, for enable ME code progr aming

PCH_ SPI _CL K

QH1

QH1
BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

13

D

D

RH54

RH54

3.3K_0402_5%~D

3.3K_0402_5%~D

+3V _PCH

1 2

PCH_ SPI _WP #

1 2

PCH_ SPI _CL K_R

RH57

RH57

3.3K_0402_5%~D

3.3K_0402_5%~D

RH28 33_ 040 2_ 5%~ DRH28 33_ 04 02_ 5% ~D

RH30 33_ 040 2_ 5%~ DRH30 33_ 04 02_ 5% ~D

RH24 1K_ 040 2_ 5%~ DRH24 1K_0 40 2_5 %~D

1

2

3

W25Q64

3

UH1A

UH1A

A19

PCH_ RTC X1

PCH_ RTC X2

PCH_ RTC RST #

PCH_ SRT CRST #

1 2

SM_ INT RUDE R#

1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

PCH_ INT VRM EN

1 2

HDA_ BIT _CL K

HDA_ SYN C

RH27

RH27
47_ 040 2_ 5%~ D

47_ 040 2_ 5%~ D

HDA_ SPK R

1 2

HDA_ RST #

HDA_ SDIN 0

1 2

HDA_ SDO UT

1 2

PCH_ JTA G_ TCK

PCH_ JTA G_ TM S

PCH_ JTA G_ TDI

PCH_ JTA G_ TDO

@

@

1 2

PCH_ SPI _CL K

RH25 5 0_0 402 _5 %~D

RH25 5 0_0 402 _5 %~D

PCH_ SPI _CS #

SHORT

PCH_ SPI _SI

PCH_ SPI _SO

SPI ROM FOR ME ( 8MByte )
ROM is Dual Output IC

U48

U48

8

VCC

/CS

7

DO

/WP

GND4DIO

EN25 Q6 4-10 4HIP _S O8~ D

EN25 Q6 4-10 4HIP _S O8~ D

SPI BIOS Pinout

(1)CS# (5)I/O_ 0
(2)I/O_1(6)CLK
(3)WP# (7)HOLD #
(4)GND (8)VCC

PCH_ SPI _HO LD#

/HOLD

6

PCH_ SPI _CL K_R

CLK

5

PCH_ SPI _SI

3

RTCX1

C19

RTCX2

F19

RTCRST#

A23

SRTCRST#

K22

INTRUDER#

C21

INTVRMEN

H35

HDA_BCLK

H37

HDA_SYNC

N1

SPKR

F35

HDA_RST#

D36

HDA_SDIN0

B36

HDA_SDIN1

C35

HDA_SDIN2

A35

HDA_SDIN3

K37

HDA_SDO

K35

HDA_DOCK_EN# / GPIO33

M35

HDA_DOCK_RST# / GPIO13

M17

JTAG_TCK

M15

JTAG_TMS

U12

JTAG_TDI

M12

JTAG_TDO

AD12

SPI_CLK

AB8

SPI_CS0#

AB6

SPI_CS1#

W8

SPI_MOSI

Y2

SPI_MISO

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

1 2

RH56 3.3K_ 04 02_ 5% ~DRH56 3.3K_ 04 02_ 5% ~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

2

A37

FWH0 / LAD0

A39

FWH1 / LAD1

C39

FWH2 / LAD2

C37

FWH3 / LAD3

K40

FWH4 / LFRAME#

H40

LDRQ0#

F37

LDRQ1# / GPIO23

Y4

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATALED#

AN3
AN1
AU3
AU1

AN6
AN8
AR3
AR1

AD4
AD2
AL3
AL1

AD8
AD6
AG3
AG1

AE3
AE1
AH8
AH6

AC3
AC1
AJ3
AJ1

AB10

AB12

AF10

AF12

AH4

W10

M2

R1

SERI RQ

SAT A_ COM P

RH41 37.4 _04 02_ 1%RH41 37.4_0 402 _1 %

Width = 10 mil, Spac ing = 20 mil
Close PCH wi thin 500 mil

SAT A3 _CO MP

RH43 49.9 _04 02_ 1% ~DRH43 4 9.9 _04 02 _1% ~D

RBIA S_S AT A3

RH48 750_ 040 2_ 1%RH4 8 750_04 02 _1%

PCH_ SAT AL ED#

PCH_ GPI O21

BBS _BI T0 _R

1 2

1 2

1 2

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

LPC

LPC

SATA3

SATA3

SATA

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SATA1GP / GPIO19

Boot BIOS Strap

1 1

*

+3V _PCH

1

CH6

CH6
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

CH94

@ CH94

@

12

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

Reserve for EMI please close to U48

LPC_ AD0 [27,2 8,3 5]
LPC_ AD1 [27,2 8,3 5]
LPC_ AD2 [27,2 8,3 5]
LPC_ AD3 [27,2 8,3 5]

LPC_ FRA ME # [27,28 ,35 ]

SERI RQ [27,3 5]

+1.0 5VS _V CC_S AT A

12

RH35 10K_ 040 2_ 5%~ D@ RH3 5 10K_0 402 _5% ~D@

12

RH32 10K_ 040 2_ 5%~ DRH32 10K_0 402 _5 %~D

12

RH27 6 10K _04 02 _5% ~DRH27 6 10K _04 02 _5% ~D

Boot BIOS LocationBBS_BIT[0]B BS_BIT[1]

SPI

RH25 6

@ RH25 6

@

1 2

PCH_ SPI _CL K_R

33_ 040 2_ 5%~ D

33_ 040 2_ 5%~ D

1

SERI RQ

SAT A_ PRX _DT X_N 0 [2 9]
SAT A_ PRX _DT X_P 0 [29 ]HDA_ BIT CLK _AU DIO[ 25]
SAT A_ PT X_DR X_N 0 [2 9]
SAT A_ PT X_DR X_P 0 [29 ]

+VCC P

+3V S

Tit le

Tit le

Tit le

P16-PCH (1/8) SATA,HDA,SPI, LPC

P16-PCH (1/8) SATA,HDA,SPI, LPC

P16-PCH (1/8) SATA,HDA,SPI, LPC

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

12

RH29 10K _04 02 _5% ~DRH29 10K _04 02 _5% ~D

mSATA

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

+3V S

1.0

1.0

1.0

16 54Fri da y, S epte mb er 2 8, 201 2

16 54Fri da y, S epte mb er 2 8, 201 2

16 54Fri da y, S epte mb er 2 8, 201 2

5

MiniWLAN --->

PCIE _PR X_W LANT X_ N3[28]
PCIE _PR X_W LANT X_ P3[28 ]
PCIE _PT X_ WLA NRX_ N3[28]
PCIE _PT X_ WLA NRX_ P3[28 ]

CLK_ PCI E_M INI1 #[2 8]
CLK_ PCI E_M INI1[ 28]

MINI 1CL K_R EQ#[28]

1 2

CH11 0.1U _04 02 _10 V7K ~DC H11 0.1U _04 02_ 10 V7K ~D

1 2

CH16 0.1U _04 02 _10 V7K ~DC H16 0.1U _04 02_ 10 V7K ~D

RH91 1 0K_ 040 2_ 5%~ DRH9 1 10K _04 02 _5% ~D

+3V _PCH

RH95 10K _04 02 _5% ~DRH95 10K _04 02 _5% ~D

+3V S

RH10 0 10K _04 02 _5% ~DRH10 0 10K _04 02 _5% ~D

+3V S

RH10 3 10K _04 02 _5% ~DRH10 3 10K _04 02 _5% ~D

+3V _PCH

RH10 7 10K _04 02 _5% ~DRH10 7 10K _04 02 _5% ~D

+3V _PCH

RH11 0 10K_0 402 _5 %~DR H11 0 1 0K _04 02 _5% ~D

+3V _PCH

RH11 2 10K_0 402 _5 %~DR H11 2 1 0K _04 02 _5% ~D

+3V _PCH

RH11 6 10K_0 402 _5 %~DR H11 6 1 0K _04 02 _5% ~D

+3V _PCH

RH11 8 10K_0 402 _5 %~DR H11 8 1 0K _04 02 _5% ~D

+3V _PCH

D D

C C

B B

MiniWLAN --->

1 2

1 2

1 2

1 2

1 2

T23 9@ T2 39@
T24 0@ T2 40@

12

12

12

12

4

PCIE _PT X_ WLA NRX_ N3_ C
PCIE _PT X_ WLA NRX_ P3 _C

T81@ T8 1@
T82@ T8 2@

PCH_ GPI O73

PCH_ GPI O18

PCH_ GPI O20

MINI 1CL K_R EQ#

PCH_ GPI O26

PCH_ GPI O44

PEG _B_ CLK REQ #

PCH_ GPI O45

PCH_ GPI O46

CLK_ BCL K_ ITP #
CLK_ BCL K_ ITP

UH1B

UH1B

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0# / GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1# / GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2# / GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3# / GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4# / GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5# / GPIO44

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ# / GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6# / GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7# / GPIO46

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

PCI-E*

PCI-E*

CLOCKS

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

H12

F17

F10

H22

K12

A9

C9

D12

C11

L3

J1

M8

R8

AF44
AF46

BB24
AY24

AN10
AN12

BD17
BF17

BB26
AY26

M24
K24

AK8
AK6

J49

E51

W49
W51

AC49

H50

D48

G49

J51

SMB AL ERT #

SMB CLK

SMB DAT A

DRAM RST _C NTRL _P CH

SML 0CL K

SML 0DA TA

NFC_I RQ

SML 1CL K

SML 1DA TA

Total device

No support iAMT

PEG _A_ CLK RQ#

CLKI N_DM I#
CLKI N_DM I

CLKI N_DM I2 #
CLKI N_DM I2

CLKI N_DO T9 6#
CLKI N_DO T9 6

CLKI N_S AT A#
CLKI N_S AT A

CLK_ PCH _14 M

CLK_ PCI _LP BAC K

XTA L2 5_I N
XTA L2 5_O UT

XCLK _RC OM P

CLKF LEX 0

RH29 6 2 2_0 40 2_5 %~DRH29 6 2 2_0 40 2_5 %~D

KB_ DET #

KB_ DET #

SMB CLK [28]

SMB DAT A [2 8]

DRAM RST _C NTRL _P CH [6]

+3V _PCH

RH14 1

RH14 1
10K _04 02 _5% ~D

10K _04 02 _5% ~D

1 2

CLK_ CPU _DM I# [6]
CLK_ CPU _DM I [6]

CLK_ CPU _DPL L# [6 ]
CLK_ CPU _DPL L [6]

CLK_ PCI _LP BAC K [19 ]

1 2

RH11 3 90 .9_ 040 2_ 1%RH113 9 0.9 _04 02 _1%

1 2

1 2

RH30 2 100 K_0 40 2_5 %~DRH30 2 100 K_0 40 2_5 %~D

2

+VCC P

CLK_ PCI _T PM [27]

KB_ DET # [3 3]

+3V S

1

+3V _PCH

SMB CLK

SMB DAT A

SML 0CL K

SML 0DA TA

SML 1CL K

SML 1DA TA

DRAM RST _C NTRL _P CH

NFC_I RQ

SMB AL ERT #

NFC_I RQ

CLKI N_DM I2 #
CLKI N_DM I2
CLKI N_DM I#
CLKI N_DM I
CLKI N_DO T9 6#
CLKI N_DO T9 6
CLKI N_S AT A#
CLKI N_S AT A
CLK_ PCH _14 M

If use e xtenal CLK ge n, please place clos e to CLK gen
else, please place close to PCH

CLK_ PCH _14 M

Reserve for EMI please close to UH1

CLK_ PCI _LP BAC K

Reserve for EMI please close to UH1

XTA L2 5_I N

XTA L2 5_O UT

+3V S

+3V S

1 2

RH67 2 .2K _04 02_ 5% ~DRH67 2 .2K _04 02_ 5% ~D

1 2

RH69 2.2K_ 04 02_ 5% ~DRH69 2.2K_ 04 02_ 5% ~D

1 2

RH70 2 .2K _04 02_ 5% ~DRH70 2 .2K _04 02_ 5% ~D

1 2

RH72 2 .2K _04 02_ 5% ~DRH72 2 .2K _04 02_ 5% ~D

1 2

RH73 2 .2K _04 02_ 5% ~DRH73 2 .2K _04 02_ 5% ~D

1 2

RH74 2 .2K _04 02_ 5% ~DRH74 2 .2K _04 02_ 5% ~D

1 2

RH75 1K_0 402 _5 %~DRH75 1K_ 040 2_ 5%~ D

1 2

@

@

R517 10 K_0 402 _5 %~D

R517 10 K_0 402 _5 %~D

1 2

R812 10 K_0 402 _5 %~DR81 2 10 K_ 040 2_5 %~D

R110 0 10 0K _04 02 _5% ~DR11 00 1 00K _0 402 _5% ~D

1 2

RH76 10K_0 402 _5% ~DRH76 10K_0 402 _5% ~D

1 2

RH78 10K_0 402 _5% ~DRH78 10K_0 402 _5% ~D

1 2

RH77 10K_0 402 _5% ~DRH77 10K_0 402 _5% ~D

1 2

RH79 10K_0 402 _5% ~DRH79 10K_0 402 _5% ~D

1 2

RH80 10K_0 402 _5% ~DRH80 10K_0 402 _5% ~D

1 2

RH81 10K_0 402 _5% ~DRH81 10K_0 402 _5% ~D

1 2

RH82 10K_0 402 _5% ~DRH82 10K_0 402 _5% ~D

1 2

RH83 10K_0 402 _5% ~DRH83 10K_0 402 _5% ~D

1 2

RH84 10K_0 402 _5% ~DRH84 10K_0 402 _5% ~D

12

CH21

@ CH21

@

RH86 3 3_0 40 2_5 %~D@R H86 3 3_0 402 _5 %~D@

12

CH22

@ CH22

@

RH89 33_0 40 2_5 %~D@ RH89 33_ 040 2_ 5%~ D@

1 2

RH11 7 1M_04 02 _5% ~DRH117 1M_04 02 _5% ~D

YH2

YH2

25M HZ_ 18P F_X 3G0 25 000 DI1H -H~D

25M HZ_ 18P F_X 3G0 25 000 DI1H -H~D

1

IN

OUT

2

GND

GND

1

2

CH24

CH24
15P _04 02 _50 V8J ~D

15P _04 02 _50 V8J ~D

1 2

1 2

12

3

4

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

1

2

CH23

CH23
15P _04 02 _50 V8J ~D

15P _04 02 _50 V8J ~D

+3V S

QH3A

SML 1CL K

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

QH4A

QH4A

A A

5

4

SML 1DA TA

354

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

QH4B

QH4B

PCH_ SM LCL K [24,35 ]

PCH_ SM LDA TA [24,35 ]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2

6 1

SMB CLK

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

RH10 5 0 _0 402 _5 %~D@ RH1 05 0_0 402 _5 %~D@

SMB DAT A

Compal Secret Data

Compal Secret Data

Compal Secret Data

QH3A

6 1

1 2

Deciphered Date

Deciphered Date

Deciphered Date

2.2K _0 402 _5 %~D

2.2K _0 402 _5 %~D

2

QH3B

QH3B

354

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

1 2

RH11 1 0_0 402 _5 %~D@ RH 111 0 _04 02_ 5% ~D@

2

RH98

RH98

RH99

RH99

2.2K _0 402 _5 %~D

2.2K _0 402 _5 %~D

1 2

1 2

PCH_ SM BCL K [11,13 ,34 ]

Connect DDR SPD, TP

PCH_ SM BDA TA [11,1 3,3 4]

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P17-PCH (2/8) PCIE, SMB US, CLK

P17-PCH (2/8) PCIE, SMB US, CLK

P17-PCH (2/8) PCIE, SMB US, CLK

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

17 54Fri da y, S epte mb er 2 8, 201 2

17 54Fri da y, S epte mb er 2 8, 201 2

17 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

4

3

2

1

1 2

RH12 3 100K_ 040 2_ 5%~ DRH12 3 100K_ 040 2_ 5%~ D

1 2

RH15 8 100K_ 040 2_ 5%~ DRH15 8 100K_ 040 2_ 5%~ D

UH1C

UH1C

DMI_ IRCO MP

RBIA S_C PY

XDP_ DBR ESE T#

SYS _PW ROK

PM_ PWR OK_ R

APWR OK_ R

12

12

SUSW ARN#

12

PBT N_O UT #_R

12

AC_P RES ENT _R

PCH_ GPI O72

RI#

BL21

DMI0RXN

BL23

DMI1RXN

BJ19

DMI2RXN

BL17

DMI3RXN

BJ21

DMI0RXP

BJ23

DMI1RXP

BL19

DMI2RXP

BJ17

DMI3RXP

BD22

DMI0TXN

BB22

DMI1TXN

BB19

DMI2TXN

BB17

DMI3TXN

BF22

DMI0TXP

AY22

DMI1TXP

AY19

DMI2TXP

AY17

DMI3TXP

BF19

DMI_ZCOMP

BD19

DMI_IRCOMP

BK20

DMI2RBIAS

SUS power rail

F15

SUSACK#

L1

SYS_RESET#

M10

SYS_PWROK

M22

PWROK

G3

APWROK

B12

DRAMPWROK

B20

RSMRST#

C13

SUSWARN#/SUSPWRDNACK/GPIO30

K19

PWRBTN#

DSW power rai l

H19

ACPRESENT / GPIO31

DSW power rai l

H10

BATLOW# / GPIO72

F12

RI#

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

PCH Strap PIN

DSWO DVRE N

RH14 7 330 K_0 40 2_5 %~DRH14 7 330 K_0 40 2_5 %~D

DSWO DVRE N

RH15 1 330 K_0 40 2_5 %~D@ RH15 1 330 K_ 040 2_5 %~D@

DSWODVREN - On Die DSW VR Enabl e

H：Enable

*

L：Disa ble

SUSC LK

12

CH10 2 10P _04 02 _50 V8J ~D@ C H10 2 10P _04 02_ 50 V8J ~D@

Reserve for RF please close to UH1

DMI

DMI

System Power Management

System Power Management

DSW power rai l

12

12

D D

Width = 4 mil, Spaci ng = 20 mil
Close PCH wi thin 500 mil

Deep S3 support, connect to EC

C C

Deep S3 Support

PCH_ GPI O72

B B

RI#

WAKE #

SUSW ARN#

PCH_ RSM RST #

SYS _PW ROK

PCH_ PWRO K

AC_P RES ENT

DMI_ CT X_P RX_ N0[5 ]
DMI_ CT X_P RX_ N1[5 ]
DMI_ CT X_P RX_ N2[5 ]
DMI_ CT X_P RX_ N3[5 ]

DMI_ CT X_P RX_ P0[5 ]
DMI_ CT X_P RX_ P1[5 ]
DMI_ CT X_P RX_ P2[5 ]
DMI_ CT X_P RX_ P3[5 ]

DMI_ CRX _PT X_ N0[5 ]
DMI_ CRX _PT X_ N1[5 ]
DMI_ CRX _PT X_ N2[5 ]
DMI_ CRX _PT X_ N3[5 ]

DMI_ CRX _PT X_ P0[5 ]
DMI_ CRX _PT X_ P1[5 ]
DMI_ CRX _PT X_ P2[5 ]
DMI_ CRX _PT X_ P3[5 ]

+VCC P

RH12 4 49.9 _0 402 _1 %~DRH12 4 49. 9_0 402 _1 %~D

RH12 5 750 _04 02 _1%RH12 5 750 _0 402 _1%

4mil width and place

SUSA CK#[35]

XDP_ DBR ESE T#[6]

VGA TE[35, 44]

PCH_ PWRO K[35 ]

PM_ DRA M_ PWRG D[6]

PCH_ RSM RST #[ 35]

PCH_ SUS WARN#[ 35]

PBT N_O UT #[35]

AC_P RES ENT[35]

RH14 3 10K _04 02 _5% ~DRH14 3 10K _04 02 _5% ~D

RH14 5 10K _04 02 _5% ~DRH14 5 10K _04 02 _5% ~D

RH14 6 10K _04 02 _5% ~DRH14 6 10K _04 02 _5% ~D

RH15 4 10K _04 02 _5% ~DRH15 4 10K _04 02 _5% ~D

RH15 9 10K _04 02 _5% ~DRH15 9 10K _04 02 _5% ~D

RH27 2 47K _04 02 _5% ~DRH27 2 47K _04 02 _5% ~D

RH29 9 10K _04 02 _5% ~D@R H29 9 10K _04 02 _5% ~D@

8/21,change RH272 from 10K to 47K for
prevent voltage divi der less than 3V

within 500mil of the PCH

RH27 3 0 _04 02 _5% ~D@ RH2 73 0_040 2_ 5%~ D@

PCH_ PWRO K

RH13 0 0 _04 02 _5% ~D@ RH1 30 0_040 2_ 5%~ D@

RH13 1 0 _04 02 _5% ~D@ RH1 31 0_040 2_ 5%~ D@

PCH_ RSM RST # PCH_ RSM RST #_ R

RH13 3 0_0 402 _5 %~D@ RH13 3 0_0 40 2_5 %~D@

RH29 7 0_0 402 _5 %~D@ RH29 7 0_0 40 2_5 %~D@

RH29 3 0_0 402 _5 %~D@ RH29 3 0_0 40 2_5 %~D@

AC_P RES ENT

RH13 7 0_0 402 _5 %~D@ RH13 7 0_0 40 2_5 %~D@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

19

Deep S3 support, connect to DSW power r ail

1 2

RH15 0 10K _04 02 _5% ~DRH15 0 10K _04 02 _5% ~D

1 2

1 2

T21 8@ T2 18@

1 2

1 2

1 2

+3V _PCH

+3V _PCH _DS W

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

RTC power rail

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

+RT CVCC

BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10

BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10

BB10

BH12

BK8

BK12

BH8

F22

DSWO DVRE N

A21

PCH_ DPWR OK

D8

WAKE #

T2

PM_ CLK RUN#

G6

SUS_ ST AT #

D3

SUSC LK

RH13 2 0_0 402 _5 %~D

RH13 2 0_0 402 _5 %~D

F6

K10

PM_ SL P_S 4#

D4

C7

12

SUS_ A#

@

@

RH31 3 0_0 402 _5 %~D

RH31 3 0_0 402 _5 %~D

A15

SHORT

BB8

A7

If not usi ng integrated
LAN,signal may b e left as NC.

Can be left NC when IAMT is
not support on the pla tfrom

PM_ CLK RUN#

FDI_C TX _PR X_N0 [5 ]
FDI_C TX _PR X_N1 [5 ]
FDI_C TX _PR X_N2 [5 ]
FDI_C TX _PR X_N3 [5 ]
FDI_C TX _PR X_N4 [5 ]
FDI_C TX _PR X_N5 [5 ]
FDI_C TX _PR X_N6 [5 ]
FDI_C TX _PR X_N7 [5 ]

FDI_C TX _PR X_P 0 [5]
FDI_C TX _PR X_P 1 [5]
FDI_C TX _PR X_P 2 [5]
FDI_C TX _PR X_P 3 [5]
FDI_C TX _PR X_P 4 [5]
FDI_C TX _PR X_P 5 [5]
FDI_C TX _PR X_P 6 [5]
FDI_C TX _PR X_P 7 [5]

FDI_I NT [5 ]

FDI_F SYN C0 [5]

FDI_F SYN C1 [5]

FDI_L SY NC0 [5]

FDI_L SY NC1 [5]

PM_ CLK RUN# [27 ]

T76@ T7 6@

SHORT

12

@

@

T21 6@ T2 16@

12

T21 9@ T2 19@

RH24 8 8.2K _0 402 _5 %~DRH24 8 8.2K _0 402 _5 %~D

SUSC LK_ R [3 5]

PM_ SL P_S 5# [3 5]

PM_ SL P_S 4# [3 5]

PM_ SL P_S 3# [3 5]

PM_ SL P_S US# [32 ,35 ]

H_PM _S YNC [6]

12

PCH DPWROK Option for Deep S3

RH30 9

@ RH30 9

@

12

0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

1 2

RH12 6

@ RH12 6

@

0_0 402 _5 %~D

0_0 402 _5 %~D

Wak-up Option for Deep S3

PCH_ GPI O27[20]

WAKE #

Deep S3 Support

Non Deep S3 (De-pop RH313)

PM_SLP_SUS# : Deep Sx Indic ation
When ass erted(l ow), this s ignal indica tes PCH
is i n DeepSx state wherei nternal Sus power is
shut off for enhanc ed power savi ng.
When deasserted (hi gh), this s ignal indica tes exit from
DeepSx s tate and Sus po werc an be appl ied to PCH

+3V S

12

ENBK L[35]
PCH_ ENV DD[32]

PCH_ INV_ PWM[ 24]

12

RH31 0

@ RH31 0

@

0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

RH12 8

@ RH12 8

@

0_0 402 _5 %~D

0_0 402 _5 %~D

POK [37, 39]

PCH_ RSM RST #_ RPCH_ DPWR OK

12

12

ENBK L

PCH_ ENV DD

M44

ENBK L

M42

PCH_ ENV DD

L49

L51
K46

R42
M40

AH42
AH40

AG51
AG49

AK44
AK46

AR46
AN49
AN44

12

CRT_ IRE F

AK40

AR44
AN51
AN46
AK42

AH46
AH44

AM50
AL49

AJ51

AH50

AM48
AL51

AJ49

AH48

M46
R46
U46

R49
N49

M50
N51

R51
T48

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

Deep S3 Support

Non Deep S3

Deep S3 Support

WAKE _P CH# [35]

Non Deep S3

RH14 0

RH14 0
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

If VGA is us ing, change to 0.5% res istor

CRT_HSYNC and CRT_VSYNC resistor
33 ohm for Dir ectC onnect
20 ohm for Dock Supp ort
20 ohm for Switcha ble Graphi cs Devic e Down Topology
10 ohm for Switcha ble Graphi cs Dock Support

UH1D

UH1D

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

AU40

SDVO_TVCLKINN

AU42

SDVO_TVCLKINP

AR51

SDVO_STALLN

AR49

SDVO_STALLP

AT50

SDVO_INTN

AT48

SDVO_INTP

W42

SDVO_CTRLCLK

R44

SDVO_CTRLDATA

AW51

DDPB_AUXN

AW49

DDPB_AUXP

AY42

DDPB_HPD

AY48

DDPB_0N

AY50

DDPB_0P

AY44

DDPB_1N

LVDS

LVDS

Digital Display Interface

Digital Display Interface

CRT

CRT

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AY46
BB44
BB46
BA49
BA51

T50
U44

AU51
AU49
BE46

BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51

M48
U42

AU46
AU44
BK44

BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45

PCH_ DP_ CLK

PCH_ DP_ DAT

PCH_ DP_ HPD

PCH_ DP_ CLK

PCH_ DP_ CLK [2 6]

PCH_ DP_ DAT

PCH_ DP_ DAT [26 ]

PCH_ DP_ AUXN [26]
PCH_ DP_ AUXP [2 6]

PCH_ DP_ HPD

PCH_ DP_ HPD [26]

PCH_ DP_ N0 [26 ]
PCH_ DP_ P0 [26]
PCH_ DP_ N1 [26 ]
PCH_ DP_ P1 [26]
PCH_ DP_ N2 [26 ]
PCH_ DP_ P2 [26]
PCH_ DP_ N3 [26 ]
PCH_ DP_ P3 [26]

12

RH28 1 2.2K _0 402 _5 %~DRH28 1 2.2K _0 402 _5 %~D

12

RH28 2 2.2K _0 402 _5 %~DRH28 2 2.2K _0 402 _5 %~D

12

RH30 0 1M_ 04 02_ 5% ~DRH300 1M _0 402 _5 %~D

+3V S

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P18-PCH (3/8) DMI,FDI ,PM,GFX,DP

P18-PCH (3/8) DMI,FDI ,PM,GFX,DP

P18-PCH (3/8) DMI,FDI ,PM,GFX,DP

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

18 54Fri da y, S epte mb er 2 8, 201 2

18 54Fri da y, S epte mb er 2 8, 201 2

18 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

USB/USB3 Port Mapping

USB2[0]

USB2[1]

USB2[2]

USB2[3]

USB3 RN0[30]
USB3 RN1[30]

USB3 RP0[30]

Boot BIOS Strap

1 1

*

C C

B B

A A

RH29 1 1K_04 02_ 5% ~D@ RH2 91 1K_0 402 _5% ~D@

GNT3# A16 Top-Block Swap Override
( Internal PU 20K)

Low = Disabl ed
High = Enabled

*

RH30 6 1K_04 02_ 5% ~D@ RH3 06 1K_0 402 _5% ~D@

+3V S

1 2

RH32 5 8.2K _0 402 _5 %~DRH32 5 8.2K _0 402 _5 %~D

1 2

RH32 6 8.2K _0 402 _5 %~DRH32 6 8.2K _0 402 _5 %~D

1 2

RH32 7 8.2K _0 402 _5 %~DRH32 7 8.2K _0 402 _5 %~D

1 2

RH32 8 8.2K _0 402 _5 %~DRH32 8 8.2K _0 402 _5 %~D

1 2

RH32 9 8.2K _0 402 _5 %~DRH32 9 8.2K _0 402 _5 %~D

1 2

RH33 0 8.2K _0 402 _5 %~DRH33 0 8.2K _0 402 _5 %~D

1 2

RH33 1 8.2K _0 402 _5 %~DRH33 1 8.2K _0 402 _5 %~D

1 2

RH33 2 8.2K _0 402 _5 %~DRH33 2 8.2K _0 402 _5 %~D

1 2

RH33 3 8.2K _0 402 _5 %~DRH33 3 8.2K _0 402 _5 %~D

1 2

RH33 4 8.2K _0 402 _5 %~DRH33 4 8.2K _0 402 _5 %~D

1 2

RH33 5 8.2K _0 402 _5 %~DRH33 5 8.2K _0 402 _5 %~D

Boot BIOS LocationBBS_BIT[0]B BS_BIT[1]

SPI

12

BBS _BI T1

Internal P ull hi gh

12

WL_O FF#

CLK_ PCI _LP BAC K[17 ]
CLK_ PCI _LP C[3 5]
CLK_ LP C_DE BUG[28]

WL_O FF#
EN_T S
PCI_ PIRQ D#
PCH_ GPI O5

PCH_ GPI O52
PCH_ GPI O3
PCH_ GPI O54

PCI_ PIRQ C#
PCI_ PIRQ A#
PCI_ PIRQ B#
PCH_ GPI O2

USB3 RP1[30]

USB3 TN 0[ 30]
USB3 TN 1[ 30]

USB3 TP 0[30]
USB3 TP 1[30]

EN_T S[24]

EN_C AM[24]
WL_O FF#[28]

DP_C BL_ DET[26]

@

@

@

12

CH10 7 10P _04 02 _50 V8J ~D

CH10 7 10P _04 02 _50 V8J ~D

12

RH16 4 22_ 040 2_ 5%~ DRH1 64 22 _04 02 _5% ~D

1 2

RH16 5 22_ 040 2_ 5%~ DRH1 65 22 _04 02 _5% ~D

1 2

RH30 5 22_ 040 2_ 5%~ DRH3 05 22 _04 02 _5% ~D

12

CH99 1 0P_ 04 02_ 50V 8J~ D@ CH9 9 10P _0 402 _50 V8 J~D@

4

UH1E

UH1E

BH24

TP1

BK24

TP2

BH20

TP3

BK16

TP4

BH16

TP5

AN42

TP6

AN40

TP7

AR40

TP8

AR42

TP9

D20

TP10

M30

TP11

E3

TP12

AM4

TP13

AT4

TP14

AT2

TP15

AD10

TP16

B24

TP17

D24

TP18

AD44

TP19

AD46

CLK_ PCI 1
CLK_ PCI 2
CLK_ PCI 3
CLK_ PCI 4

TP20

BJ48

TP21

BL7

TP22

W40

TP23

K30

TP24

BH49

TP41

BB42

TP42

BJ25

USB3Rn1

BJ27

USB3Rn2

BJ31

USB3Rn3

BJ29

USB3Rn4

BL25

USB3Rp1

BL27

USB3Rp2

BL31

USB3Rp3

BL29

USB3Rp4

BF26

USB3Tn1

BB28

USB3Tn2

BF28

USB3Tn3

BF30

USB3Tn4

BD26

USB3Tp1

AY28

USB3Tp2

BD28

USB3Tp3

BD30

USB3Tp4

D49

PIRQA#

C48

PIRQB#

C47

PIRQC#

C45

PIRQD#

G46

REQ1# / GPIO50

K44

REQ2# / GPIO52

F46

REQ3# / GPIO54

F42

GNT1# / GPIO51

H42

GNT2# / GPIO53

D44

GNT3# / GPIO55

A47

PIRQE# / GPIO2

C41

PIRQF# / GPIO3

F45

PIRQG# / GPIO4

F40

PIRQH# / GPIO5

H2

PME#

F7

PLTRST#

G51

CLKOUT_PCI0

E49

CLKOUT_PCI1

H48

CLKOUT_PCI2

J43

CLKOUT_PCI3

G45

CLKOUT_PCI4

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

PLT _RS T#[ 27, 28,3 5,6 ]

RSVD

RSVD

USB3.0

USB3.0

PCI

PCI

USB3[1]

USB3[2]

USB3[3]

USB3[4]

PCI_ PIRQ A#
PCI_ PIRQ B#
PCI_ PIRQ C#
PCI_ PIRQ D#

EN_T S
PCH_ GPI O52
PCH_ GPI O54

BBS _BI T1

WL_O FF#

PCH_ GPI O2
PCH_ GPI O3

PCH_ GPI O5

T12 3@T12 3

PCH_ PLT RS T#

@

T16 6@T16 6

@

T20 4@T20 4

CLK_ PCI 1

RSVD

RSVD

USB2.0

USB2.0

12

RH17 1

RH17 1
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23

RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N

USBP0P
USBP1N

USBP1P
USBP2N

USBP2P
USBP3N

USBP3P
USBP4N

USBP4P
USBP5N

USBP5P
USBP6N

USBP6P
USBP7N

USBP7P
USBP8N

USBP8P
USBP9N

USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

4

O

RH16 8 0_ 040 2_ 5%~ D@RH1 68 0 _0 402 _5 %~D@

+3V S

5

P

IN1

IN2

G

3

3

BE3
BE1
AU8
BJ7

BA3
BH3

AU6
AW3
AW1
AY6
AY2
AY4
BC3
BC1
BG1
BG3
BE6
BH4
BF7
BJ4
BJ5
BK6

AY8

BL5

BB6

BD2
BD4

BA1
BF6

F24
H24
C25
A25
C27
A27
H28
F28
M26
K26
D28
B28
H26
F26
D32
B32
M28
K28
C29
A29
C31
A31
H33
F33
H30
F30
M33
K33

C33

USBR BIA S

A33

C17

USB_ OC0 #

A17

USB_ OC1 #

A13

USB_ OC2 #

D16

USB_ OC3 #CLK_ PCI 0

A11

USB_ OC4 #

B16

USB_ OC5 #

C23

PCH_ LID_ SW_ IN#

H15

ROT AT ION_ LOC K_S W#

1 2

1

2

UH5

UH5
SN74 AHC 1G0 8DCK R_S C70 -5~D

SN74 AHC 1G0 8DCK R_S C70 -5~D

USB2 0_ N0 [30 ]
USB2 0_ P0 [30]
USB2 0_ N1 [30 ]
USB2 0_ P1 [30]

USB2 0_ N4 [28 ]
USB2 0_ P4 [28]

USB2 0_ N9 [24 ]
USB2 0_ P9 [24]

USB2 0_ N12 [2 4]
USB2 0_ P12 [24 ]
USB2 0_ N13 [2 7]
USB2 0_ P13 [27 ]

Within 500 mils

1 2

RH16 3

RH16 3

22.6 _0 402 _1 %

22.6 _0 402 _1 %

RH33 6 0_040 2_5 %~D@ RH33 6 0_040 2_5 %~ D@

USB3.0(IO)

USB3.0 (Power Share )

Mini Card(WLAN)

Touch Panel

Camera

Sensors HUB

Net USB_BIAS route im pedacne s should be 50 -ohm
and len gth le ss than 500-mil spacing i s 15-mil.

1 2

SHORT

PCH_ PLT RS T#

@

@

RH18 3

RH18 3
10K _04 02 _5% ~D

10K _04 02 _5% ~D

1 2

Debug Port

Debug Port

USB_ OC0 # [3 0]
USB_ OC1 # [3 0]

EC_L ID_ OUT # [3 5]
ROT AT ION_ LOC K_S W# [2 5]

2

USB_ OC2 #
USB_ OC0 #
PCH_ LID_ SW_ IN#
USB_ OC3 #

USB_ OC1 #
USB_ OC5 #
USB_ OC4 #
ROT AT ION_ LOC K_S W#

USB OC Pin

PCH Mapping

OC#0

Port 0 & 1

OC#1

Port 2 & 3

OC#2

Port 4 & 5

OC#3

Port 6 & 7

OC#4

Port 8 & 9

OC#5

Port 10 & 11

OC#6

Port 12 & 13

OC#7

GPIO use

1 2

RH31 7 8.2K _0 402 _5 %~DRH31 7 8.2K _0 402 _5 %~D

1 2

RH31 8 8.2K _0 402 _5 %~DRH31 8 8.2K _0 402 _5 %~D

1 2

RH31 9 8.2K _0 402 _5 %~DRH31 9 8.2K _0 402 _5 %~D

1 2

RH32 0 8.2K _0 402 _5 %~DRH32 0 8.2K _0 402 _5 %~D

1 2

RH32 1 8.2K _0 402 _5 %~DRH32 1 8.2K _0 402 _5 %~D

1 2

RH32 2 8.2K _0 402 _5 %~DRH32 2 8.2K _0 402 _5 %~D

1 2

RH32 3 8.2K _0 402 _5 %~DRH32 3 8.2K _0 402 _5 %~D

1 2

RH32 4 10K _04 02 _5% ~DRH32 4 10K _04 02 _5% ~D

1

+3V _PCH

Reserve for RF please close t o UH1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P19-PCH (4/8) PCI, USB, NVRAM

P19-PCH (4/8) PCI, USB, NVRAM

P19-PCH (4/8) PCI, USB, NVRAM

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

19 54Fri da y, S epte mb er 2 8, 201 2

19 54Fri da y, S epte mb er 2 8, 201 2

19 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

+3V S +3 VS

RH29 8

25

12

1 2

12

PCH_ GPI O28

10K _04 02 _5% ~D

10K _04 02 _5% ~D

RH29 8
10K _04 02 _5% ~D

10K _04 02 _5% ~D

1 2

RH33 9

RH33 9

SHOR T P ADS

SHOR T P ADS

@

@

1 2

EC_S MI #

PCH_ GPI O12

mSA TA _DE T#

EC_S CI#

BT_ RAD IO_ DIS#

SH_P WR_ CNTR L

PCH_ GPI O36

PCIE _M CARD 1_DE T#

PCH_ GPI O39

RFSW_ VCO NT1

RFSW_ VCO NT2

PCH_ GPI O15

PCH_ GPI O37

PCH_ GPI O37

PCH_ GPI O27

PCH_ GPI O27

RH19 7

RH19 7
10K _04 02 _5% ~D

10K _04 02 _5% ~D

1 2

MEM _C HB_ EN M EM _C HA_ EN

RH33 8

RH33 8

SHOR T P ADS

SHOR T P ADS

@

@

D D

C C

B B

A A

1 2

+3V _PCH

+3V S

12

RH19 0 10K _04 02 _5% ~DRH19 0 10K _04 02 _5% ~D

12

RH29 0 10K _04 02 _5% ~DRH29 0 10K _04 02 _5% ~D

12

RH18 8 100 K_0 40 2_5 %~DRH18 8 100 K_0 40 2_5 %~D

1 2

R218 10 K_ 040 2_ 5%~ DR2 18 10K _0 402 _5 %~D

12

RH29 4 10K _04 02 _5% ~DRH29 4 10K _04 02 _5% ~D

12

RH25 7 10K _04 02 _5% ~DRH25 7 10K _04 02 _5% ~D

12

RH19 3 10K _04 02 _5% ~DRH19 3 10K _04 02 _5% ~D

12

RH26 2 100 K_0 40 2_5 %~DRH26 2 100 K_0 40 2_5 %~D

12

RH26 3 10K _04 02 _5% ~DRH26 3 10K _04 02 _5% ~D

12

RH30 4 10K _04 02 _5% ~DRH30 4 10K _04 02 _5% ~D

12

RH25 8 10K _04 02 _5% ~DRH25 8 10K _04 02 _5% ~D

PCH_GPIO15

TLS Confidentiality

Low - Intel ME Crypto Trans port Layer Security (TLS)
cipher s uite with no confi dentiali ty
High - Intel ME Crypto Tra nsport Layer Secur ity (TLS)

*

cipher s uite with confid entiali ty

+3V _PCH

RH27 0 1K_ 040 2_ 5%~ DRH27 0 1K_ 040 2_ 5%~ D

PCH_GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die vol tage regulator ena ble

*

L：On-Die PLL Voltage Regulator di sabl e

RH17 7 1K_ 040 2_ 5%~ D@ RH1 77 1K _04 02 _5% ~D@

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

*

LOW - Tx, Rx terminated
to same voltage
(DC Couplin g Mode)

+3V S

RH18 1 1K_ 040 2_ 5%~ D@RH1 81 1K _04 02 _5% ~D@

1 2

RH18 2

RH18 2

GPIO27

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

+3V _PCH _DS W

1 2

RH31 1 10K _04 02 _5% ~DRH31 1 10K _04 02 _5% ~D

1 2

RH18 6 1K_04 02_ 5% ~D@ RH1 86 1K_0 402 _5% ~D@

MEM_CHA_EN

DDR3
CH-A

MEM_CHB_EN

DDR3
CH-B

PCH GPIO35
For sensor hub PWRGATE
Power is ga ted when SH_PWR_CNTRL is low.
Power sent toSensor Hub when GPIO i s hi gh

+3V S

12

TPM @

TPM @

RH27 4

RH27 4
10K _04 02 _5% ~D

10K _04 02 _5% ~D

TPM _D ET

12

NTP M@

NTP M@

RH33 7

RH33 7
10K _04 02 _5% ~D

10K _04 02 _5% ~D

4

1 = Enable

0 = Disable

1 = Enable

0 = Disable

EC_S CI#[35 ]

EC_S MI #[35 ]

Deep S3 support,
PCH_GPIO27 conn ect from EC PCH_WAKE#

PCH_ GPI O27[18]

BT_ RAD IO_ DIS#[28]

SH_P WR_ CNTR L[2 7]

PCIE _M CARD 1_DE T#[28]

RFSW_ VCO NT1[28 ]

RFSW_ VCO NT2[28 ]

mSA TA _DE T#[29]

TPM BOM Optional

TPM_DET

TPM

1 = W/TPM

0 = W/O TPM

MEM _C ONFI G0

MEM _C ONFI G1

MEM _C ONFI G2

EC_S CI#

EC_S MI #

PCH_ GPI O12

PCH_ GPI O15

TPM _D ET

MEM _C HA_ EN

MEM _C HB_ EN

PCH_ GPI O27

PCH_ GPI O28

BT_ RAD IO_ DIS#

SH_P WR_ CNTR L

PCH_ GPI O36

PCH_ GPI O37

PCIE _M CARD 1_DE T#

PCH_ GPI O39

RFSW_ VCO NT1

RFSW_ VCO NT2

mSA TA _DE T#

UH1F

UH1F

W1

BMBUSY# / GPIO0

B40

TACH1 / GPIO1

C43

TACH2 / GPIO6

A45

TACH3 / GPIO7

H17

GPIO8

C5

LAN_PHY_PWR_CTRL / GPIO12

K6

GPIO15

AA3

SATA4GP / GPIO16

B44

TACH0 / GPIO17

W3

SCLOCK / GPIO22

K15

GPIO24 / MEM_LED

C15

GPIO27

G1

GPIO28

R3

STP_PCI# / GPIO34

W12

GPIO35

W6

SATA2GP / GPIO36

M6

SATA3GP / GPIO37

N3

SLOAD / GPIO38

U10

SDATAOUT0 / GPIO39

U1

SDATAOUT1 / GPIO48

AA1

SATA5GP / GPIO49

K17

GPIO57

A4

VSS_NCTF_1

A48

VSS_NCTF_2

A49

VSS_NCTF_3

A5

VSS_NCTF_4

A51

VSS_NCTF_5

BH1

VSS_NCTF_6

BH51

VSS_NCTF_7

BJ1

VSS_NCTF_8

BJ3

VSS_NCTF_9

BJ49

VSS_NCTF_10

BJ51

VSS_NCTF_11

BL1

VSS_NCTF_12

BL3

VSS_NCTF_13

BL4

VSS_NCTF_14

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

DDR Memory Configuratino Type Strap pin

+3V S

RH27 1 10K _04 02 _5% ~D@R H27 1 10K _04 02 _5% ~D@

RH18 0 10K _04 02 _5% ~D@R H18 0 10K _04 02 _5% ~D@

RH30 3 10K _04 02 _5% ~D@R H30 3 10K _04 02 _5% ~D@

GPIO Pin

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

3

GPIO68 -> DFU_ENA : Sensor HUB uC DFU mode enable (Active Low)

K42

A43

D40

A41

USB_ MC ARD1 _DE T#

U3

A20GATE

AU12

PECI

U6

RCIN#

AU10

BC9

THRMTRIP#

R6

INIT3_3V#

BC7

DF_TVS

AK10

TS_VSS1

AH12

TS_VSS2

AK12

TS_VSS3

AH10

TS_VSS4

U40

NC_1

BL48

BL49

BL51

C3

C49

C51

D1

D51

E1

MEM _C ONFI G2

MEM _C ONFI G1

MEM _C ONFI G0

00000

1

SH_D FU_E N#

PCH_ GPI O70

GAT EA 20

PCH_ PEC I_R

KB_ RST #

H_T HERM T RIP# _C

INIT 3_3 V#

1 1

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

GPIO

GPIO

CPU/MISC

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

NCTF

12

12

12

Pin Name

Micron 2G Micron 4G Hynix 4G Samsung 4GHynix 2G Samsung 2G

MEM_CONFIG0

0

MEM_CONFIG1

0

MEM_CONFIG2

0

RH17 5

@ RH17 5

@

0_0 402 _5 %~D

0_0 402 _5 %~D

RH17 6

RH17 6
390 _04 02 _5% ~D

390 _04 02 _5% ~D

RH31 4 10K _04 02 _5% ~D@R H31 4 10K _04 02 _5% ~D@

RH31 5 10K _04 02 _5% ~D@R H31 5 10K _04 02 _5% ~D@

RH31 6 10K _04 02 _5% ~D@R H31 6 10K _04 02 _5% ~D@

SH_D FU_E N# [ 27]

KB_ BL_ DET [33 ]

USB_ MC ARD1 _DE T# [2 8]

1 2

1 2

1

GAT EA 20 [35 ]

H_PE CI [3 5,6 ]

KB_ RST # [3 5]

H_CP UPWR GD [6]

H_T HERM T RIP# [6]

T12 7@ T1 27@

T24 7@ T2 47@

12

12

12

1 1

000

2

SH_D FU_E N#

PCH_ GPI O70

USB_ MC ARD1 _DE T#

GAT EA 20

KB_ RST #

1 2

RH30 7 10K _04 02 _5% ~DRH30 7 10K _04 02 _5% ~D

1 2

RH30 8 10K _04 02 _5% ~DRH30 8 10K _04 02 _5% ~D

1 2

RH30 1 10K _04 02 _5% ~DRH30 1 10K _04 02 _5% ~D

1 2

RH17 4 10K _04 02 _5% ~DRH17 4 10K _04 02 _5% ~D

1 2

RH19 6 10K _04 02 _5% ~DRH19 6 10K _04 02 _5% ~D

1

+3V S

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2

RH31 4

RH31 4

RH31 5

RH31 5

RH31 6

RH31 6

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

RH31 6

RH31 6

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@

RH31 6

RH31 6

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@

RH31 6

RH31 6

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@

RH30 3

RH30 3

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@

RH30 3

RH30 3

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@

1

X76 _M IC_2 G@

X76 _M IC_2 G@

RH31 5

RH31 5

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@

RH18 0

RH18 0

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@

RH18 0

RH18 0

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@

RH31 5

RH31 5

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@

RH31 5

RH31 5

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@

X76 _M IC_2 G@

X76 _M IC_2 G@

RH27 1

RH27 1

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@

RH31 4

RH31 4

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@

RH27 1

RH27 1

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@

RH31 4

RH31 4

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@

RH27 1

RH27 1

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@

0 0 0

DDR Micron 2G

0 0 1

DDR Micron 4G

0 01

DDR HYNIX 2G

1 1

0

DDR HYNIX 4G

1

0 0

DDR Samsung 2G

1 1

0

DDR Samsung 4G

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P20-PCH (5/8) GPIO, CPU, MISC

P20-PCH (5/8) GPIO, CPU, MISC

P20-PCH (5/8) GPIO, CPU, MISC

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et

Date : She et of

Date : She et of

1

of

20 54Fri da y, S epte mb er 2 8, 201 2

20 54Fri da y, S epte mb er 2 8, 201 2

20 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

4

3

2

1

+VCC P

1

1

1

D D

+VCC P

RH20 1 0_0 603 _5 %~D@ RH 201 0 _06 03_ 5% ~D@

+VCC P

C C

+3V S

+VCC P

RH20 8 0_0 603 _5 %~D@ RH 208 0 _06 03 _5% ~D@

B B

CH27

CH27

2

10U_0805_4VAM~D

10U_0805_4VAM~D

+VCC P

LH3

@ LH3

@

12

1 2

+VCC APL LEX P_ R +VCC APL LEX P

1UH_ LQM 21 FN1R 0N0 0D_ 30%

1UH_ LQM 21 FN1R 0N0 0D_ 30%

1

1

CH37

CH37

CH38

CH38

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH44

CH44

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

12

@

@

1

CH46

CH46
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH28

CH28

CH25

CH25

CH26

2

CH26

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH35

2

@ CH35

@

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

1

CH39

CH39

CH40

CH40

CH41

CH41

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCC AFDI_ VRM

+1.0 5VS _V CCAP LL _FDI

+VCC P

+VCC P

20mil

AB21
AB23
AC21
AC23
AE21
AE23
AF21
AF23
AG21
AG23
AG25
AG27

AJ21
AJ23
AJ25
AJ27
AJ29

AJ31
AK29
AK31
AK33
AM33
AM35

AM21

AP19

AR15

AT13

AR23

AR25

AR27

AR29

AU23

AU25

AU27

AU29

AU35

AW34

BK28

AU19
AW18

AP13
AP15

AK21

AU15
AW16

1

CH42

CH42

2

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

UH1G

UH1G

POWER

POWER

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]

VCC CORE

VCC CORE

VCCCORE[17]
VCCCORE[18]
VCCCORE[19]
VCCCORE[20]
VCCCORE[21]
VCCCORE[22]
VCCCORE[23]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO

VCCIO

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCC3_3[3]

VCCVRM[5]
VCCVRM[6]

VCCAFDPLL[1]
VCCAFDPLL[2]

VCCIO[27]

FDI

FDI

VCCDMI[2]
VCCDMI[3]

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

CRTLVDS

CRTLVDS

DMI

DMI

NAND / SPI HVCMOS

NAND / SPI HVCMOS

VCCADAC

VSSADAC

VCCALVDS[1]
VCCALVDS[2]

VSSALVDS[1]
VSSALVDS[2]

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]
VCCVRM[4]

VCCDMI[1]

VCCCLKDMI

VccDFTERM[1]

VccDFTERM[2]

VccDFTERM[3]

VccDFTERM[4]

VCCSPI

U51

V50

AF33
AG33

AC33
AE33

AF37

AG37

AG39

AJ37

T39

U37

AU21
AW21

AM23

AP39

AJ13

AJ15

AK15

AL13

Y19

@ RH21 1

@

0_0 603 _5 %~D

0_0 603 _5 %~D

+3V S

+VCC AFDI_ VRM

close PCH 100mil

+3V _VCC PSP I

SHORT

RH21 1

12

1

CH45

CH45

2

1

CH47

CH47
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+VCC AFDI_ VRM

+3V S

1

CH36

CH36

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

+VCC P

1

2

SHORT

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

RH21 0

@ RH21 0

@

1 2

0_0 603 _5 %~D

0_0 603 _5 %~D

CH43

CH43
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

20mil

@

@

1 2

RH20 7 0 _06 03 _5% ~D

RH20 7 0 _06 03 _5% ~D

SHORT

+3V _PCH

+VCC AFDI_ VRM+1.5 VS

+VCC P

+1.8 VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

0.001

0.001

5

0.266

0.001

0.08

0.08

1.3

0.042

1.05V ccIO 2.925

1.05V ccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0 .19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

0.119

3.3 / 1.5VccSusHDA

0.01

VccVRM 1.8 / 1.5 0.16

1.05V ccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3. 3

0.001

1.8VccTX_LVDS 0.06

VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P21-PCH (6/8) PWR

P21-PCH (6/8) PWR

P21-PCH (6/8) PWR

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

21 54Fri da y, S epte mb er 2 8, 201 2

21 54Fri da y, S epte mb er 2 8, 201 2

21 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

13

Deep S3 Support

Non Deep S3

D D

C C

B B

A A

+3V S

1 2

RH23 0 0 _08 05 _5% ~D

RH23 0 0 _08 05 _5% ~D

+VCC P

@

@

1 2

+VCC A_DP LL _L

RH24 7 0 _08 05 _5% ~D

RH24 7 0 _08 05 _5% ~D

SHORT

SHORT

@

@

+3V ALW

+3V _PCH

+VCC P

RH21 6

@RH2 16

@

1 2

0_0 805 _5 %~D

0_0 805 _5 %~D

+VCC P

RH23 4 0_0 603 _5 %~D@ RH 234 0 _06 03_ 5% ~D@

LH7

LH7

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

1 2

1 2

LH8

LH8

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

5

+VCC APL L_C PY

+VCC P

RH31 2 0_0 603 _5 %~D@ RH 312 0 _06 03 _5% ~D@

RH21 4 0_0 603 _5 %~D@ RH 214 0 _06 03 _5% ~D@

LH4

@ LH4

@

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

1 2

@ CH49

@

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

+3V S_V CC_C LKF 33

Modify PN

12

+1.0 5VM _V CCS US

+VCC P

+VCC P

+VCC P

1

CH79

CH79

4.7U _06 03 _6.3 V6 K~D

4.7U _06 03 _6.3 V6 K~D

2

1

+

+

CH86

CH86

220 U_B 2_2 .5V M_ R35 M~D

220 U_B 2_2 .5V M_ R35 M~D

2

1

+

+

CH88

CH88

220 U_B 2_2 .5V M_ R35 M~D

220 U_B 2_2 .5V M_ R35 M~D

2

SHORT

CH49

+VCC P

12

12

1

2

1

CH66

CH66

2

+VCC P

1

CH67

CH67

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CH72

CH72

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH74

CH74
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH77

CH77
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH80

CH80

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

1

CH87

CH87
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH89

CH89
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+VCC P

1

CH48

CH48

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

@

@

RH21 9 0 _06 03 _5% ~D

RH21 9 0 _06 03 _5% ~D

SHORT

+VCC SUS1

1

@

@

CH54

CH54
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH81

CH81

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

+RT CVCC

1

CH82

CH82

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

+1.0 5VS _V CCA_ A_ DPL

+1.0 5VS _V CCA_ B_ DPL

4

RH21 3 0_0 603 _5 %~D@ RH 213 0 _06 03_ 5% ~D@

CH51

@ CH51

@

12

1

CH57

CH57

2

1

CH60

CH60

2

1

CH71

CH71

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

+VCC SST

1

CH78

CH78

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

4

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCC RTCE XT

12

1

2

1

CH58

CH58

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

CH61

CH61

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCC ACLK

Deep S3 support

+3V _PCH _DS W

+3V _PCH _DS W

+PCH _VCC DSW

+3V S_V CC_C LKF 33

+VCC APL L_C PY_ PCH

+VCC DPLL _CP Y

+1.0 5VM _V CCS US

1

@

@

CH76

CH76
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH62

CH62

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCC AFDI_ VRM

+1.0 5VS _V CCA_ A_ DPL

+1.0 5VS _V CCA_ B_ DPL

1

CH83

CH83

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

UH1J

UH1J

AC51

VCCACLK

R12

VCCDSW3_3

R10

DCPSUSBYP

V37

VCC3_3[5]

V39

VCC3_3[6]

AW31

VCCAPLLDMI2

AP27

VCCIO[14]

V13

DCPSUS[1]

AR33

DCPSUS[2]

AU33

DCPSUS[3]

AB27

VCCASW[1]

AB29

VCCASW[2]

AB31

VCCASW[3]

AC27

VCCASW[4]

AC29

VCCASW[5]

AC31

VCCASW[6]

AE27

VCCASW[7]

AE29

VCCASW[8]

AE31

VCCASW[9]

U21

VCCASW[10]

V21

VCCASW[11]

V23

VCCASW[12]

V25

VCCASW[13]

Y21

VCCASW[14]

Y23

VCCASW[15]

Y25

VCCASW[16]

Y27

VCCASW[17]

Y29

VCCASW[18]

Y31

VCCASW[19]

R15

DCPRTC[1]

U15

DCPRTC[2]

AC39

VCCVRM[4]

BF40

VCCADPLLA

BD40

VCCADPLLB

AJ17

VCCIO[7]

AC37

VCCDIFFCLKN[1]

AE37

VCCDIFFCLKN[2]

AE39

VCCDIFFCLKN[3]

AC35

VCCSSC

U17

DCPSST

AM17

V_PROC_IO

N16

VCCRTC

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

1

CH84

CH84
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

3

POWER

POWER

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

Clock and Miscellaneous

Clock and Miscellaneous

VCC3_3[8]

PCI/GPIO/LPC

PCI/GPIO/LPC

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

SATA USB

SATA USB

VCCVRM[1]
VCCVRM[2]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

FUSE

FUSE

VCCASW[21]

CPURTC

CPURTC

VCCSUSHDA

HDA

HDA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

+VCC P

R23

R25

1

U23

U25

R27

R29

U27

U29

N27

CH50

CH50
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

CH52

CH52

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

N18

M37

+PCH _V5 REF_ SUS

AU31

+VCC A_US BS US

AM27

N36

+PCH _V5 REF_ RUN

R33

R35

U33

U35

AB19

AC19

R40

AF6

AA13

AG13

AG15

AF15

AM2

AE19
AF17

AB15

AC13

AC15

1

CH63

CH63
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+3V S

1

2

+VCC AFDI_ VRM

+VCC P

CH69

CH69

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

+1.0 5VS _S AT A3

+VCC SAT AP LL

+1.0 5VS _V CC_S AT A

U19

R19

V19

V31

+VCC SUSH DA

1

CH85

CH85

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

+3V _PCH

+3V _PCH

1

CH53

CH53

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

1

CH59

CH59

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

1

CH65

CH65

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

1

CH75

CH75
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

RH24 4 0 _06 03 _5% ~D

RH24 4 0 _06 03 _5% ~D

Deciphered Date

Deciphered Date

Deciphered Date

+3V _PCH

+3V _PCH

1

2

SHORT

@

@

RH29 2

RH29 2
0_0 603 _5 %~D

0_0 603 _5 %~D

@

@

SHORT

2

+VCC P

+3V S

+3V S

CH68

CH68

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

SHORT

@

@

1

RH23 3

RH23 3
0_0 603 _5 %~D

0_0 603 _5 %~D

CH70

CH70

2

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

Modify PN

12

+VCC P

12

2

VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec

+3V _PCH+5 V_ PCH

+VCC A_US BS US

1

@

@

CH55

CH55

2

12

+VCC P

LH6

@ LH6

@

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

10UH _LQ M2 1FN1 00 M8 0L_ 20% ~D

1 2

1

CH73

@ CH73

@

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

Place CH80 Near AK1 pin

2

+3V _PCH

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

RH22 2

RH22 2

100 _04 02 _1% ~D

100 _04 02 _1% ~D

+3V S+ 5VS

12

RH22 7

RH22 7

100 _04 02 _1% ~D

100 _04 02 _1% ~D

+VCC P

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P22-PCH (7/8) PWR

P22-PCH (7/8) PWR

P22-PCH (7/8) PWR

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1

21

DH2

DH2
RB75 1S 40T 1_ SOD 523 -2~D

RB75 1S 40T 1_ SOD 523 -2~D

+PCH _V5 REF_ SUS

1

CH56

CH56

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

21

DH3

DH3
RB75 1S 40T 1_ SOD 523 -2~D

RB75 1S 40T 1_ SOD 523 -2~D

+PCH _V5 REF_ RUN

1

CH64

CH64
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

1

1.0

1.0

1.0

22 54Fri da y, S epte mb er 2 8, 201 2

22 54Fri da y, S epte mb er 2 8, 201 2

22 54Fri da y, S epte mb er 2 8, 201 2

5

UH1H

UH1H

G7

D D

C C

B B

VSS[0]

AA11

VSS[1]

AA39

VSS[2]

AA41

VSS[3]

AA43

VSS[4]

AA45

VSS[5]

AA7

VSS[6]

AA9

VSS[7]

AB17

VSS[8]

AB2

VSS[9]

AB25

VSS[10]

AB33

VSS[11]

AB35

VSS[12]

AB37

VSS[13]

AB4

VSS[14]

AB48

VSS[15]

AB50

VSS[16]

AC11

VSS[17]

AC17

VSS[18]

AC25

VSS[19]

AC41

VSS[20]

AC43

VSS[21]

AC45

VSS[22]

AC7

VSS[23]

AE13

VSS[24]

AE15

VSS[25]

AE17

VSS[26]

AE25

VSS[27]

AE35

VSS[28]

AE41

VSS[29]

AE43

VSS[30]

AE45

VSS[31]

AE7

VSS[32]

AE9

VSS[33]

AF19

VSS[34]

AF2

VSS[35]

AF25

VSS[36]

AF27

VSS[37]

AF29

VSS[38]

AF31

VSS[39]

AF4

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AG11

VSS[43]

AG17

VSS[44]

AC9

VSS[45]

AE11

VSS[46]

AG19

VSS[47]

AG29

VSS[48]

AG31

VSS[49]

AG35

VSS[50]

AG41

VSS[51]

AG43

VSS[52]

AG45

VSS[53]

AG7

VSS[54]

AG9

VSS[55]

AH2

VSS[56]

AJ11

VSS[57]

AJ19

VSS[58]

AJ33

VSS[59]

AJ35

VSS[60]

AJ39

VSS[61]

AJ41

VSS[62]

AJ43

VSS[63]

AJ45

VSS[64]

AJ7

VSS[65]

AJ9

VSS[66]

AK17

VSS[67]

AK19

VSS[68]

AK2

VSS[69]

AK23

VSS[70]

AK25

VSS[71]

AK27

VSS[72]

AK35

VSS[73]

AK37

VSS[74]

AK4

VSS[75]

AK48

VSS[76]

AK50

VSS[77]

AL11

VSS[78]

AL39

VSS[79]

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

4

AL41
AL43
AL45
AL7
AL9
AM15
AM19
AM25
AM29
AM31
AM37
AP11
AP17
AP2
AP21
AP23
AP25
AP29
AP31
AP33
AP35
AP37
AP4
AP41
AP43
AP45
AP48
AP50
AP7
AP9
AR19
AR21
AR31
AR35
AR37
AT11
AT39
AT41
AT43
AT45
AT7
AT9
AU17
AU37
AV2
AV4
AV48
AV50
AW11
AW13
AW23
AW25
AW27
AW29
AW36
AW39
AW43
AW45
AW7
AW9
AY10
B10
B14
B18
B22
B26
B30
B34
B38
B42
B46
B6
BA11
BA13
BA16
AW41
BA18
BA21
BA23

3

UH1I

UH1I

BA25

VSS[159]

BA27

VSS[160]

BA29

VSS[161]

BA31

VSS[162]

BA34

VSS[163]

BA36

VSS[164]

BA39

VSS[165]

BA41

VSS[166]

BA43

VSS[167]

BA45

VSS[168]

BA7

VSS[169]

BA9

VSS[170]

BB4

VSS[171]

F2

VSS[172]

BB48

VSS[173]

BB50

VSS[174]

BC11

VSS[175]

BC13

VSS[176]

BC16

VSS[177]

BC18

VSS[178]

BC21

VSS[179]

BC23

VSS[180]

BC25

VSS[181]

BC27

VSS[182]

BC29

VSS[183]

BC31

VSS[184]

BC34

VSS[185]

BC36

VSS[186]

BC39

VSS[187]

BC41

VSS[188]

BC43

VSS[189]

BC45

VSS[190]

BE11

VSS[191]

BE13

VSS[192]

BE16

VSS[193]

BE21

VSS[194]

BE23

VSS[195]

BE27

VSS[196]

BE29

VSS[197]

BE31

VSS[198]

BE34

VSS[199]

BE36

VSS[200]

BE39

VSS[201]

BE41

VSS[202]

BE43

VSS[203]

BE45

VSS[204]

BE7

VSS[205]

BE9

VSS[206]

BE18

VSS[207]

BF2

VSS[208]

BF4

VSS[209]

BF48

VSS[210]

BF50

VSS[211]

BH10

VSS[212]

BH14

VSS[213]

BH26

VSS[214]

BH32

VSS[215]

BH34

VSS[216]

BH38

VSS[217]

BH42

VSS[218]

BH44

VSS[219]

BH46

VSS[220]

G21

VSS[221]

BH48

VSS[222]

BH6

VSS[223]

BK10

VSS[224]

BK14

VSS[225]

BK18

VSS[226]

BK22

VSS[227]

BK26

VSS[228]

D14

VSS[229]

BK32

VSS[230]

BK34

VSS[231]

BK38

VSS[232]

BK42

VSS[233]

BK46

VSS[234]

D10

VSS[235]

D18

VSS[236]

D22

VSS[237]

D26

VSS[238]

D30

VSS[239]

D34

VSS[240]

D38

VSS[241]

D42

VSS[242]

D46

VSS[243]

F48

VSS[244]

F50

VSS[245]

G11

VSS[246]

G13

VSS[247]

G16

VSS[248]

G18

VSS[249]

G23

VSS[250]

G27

VSS[251]

G29

VSS[252]

G31

VSS[253]

G34

VSS[254]

G36

VSS[255]

G39

VSS[256]

G41

VSS[257]

D6

VSS[258]

G43

VSS[259]

G9

VSS[260]

J11

VSS[261]

J13

VSS[262]

J16

VSS[263]

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[357]
VSS[358]
VSS[359]
VSS[360]
VSS[361]
VSS[362]
VSS[363]
VSS[364]
VSS[365]
VSS[366]
VSS[367]
VSS[368]
VSS[369]
VSS[370]
VSS[371]
VSS[372]
VSS[373]
VSS[374]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

2

J18
J21
J23
J25
J27
J29
J31
J34
J36
L25
J41
J45
J7
J9
K2
K4
K48
K50
L11
L13
L16
L18
L29
L21
L23
L27
L9
L31
L34
L36
L39
L41
L43
L45
L7
N13
N21
R37
N23
N29
N31
N34
N39
N41
N43
N45
N7
N9
P2
P4
P48
P50
R17
R21
R31
T11
T13
T41
T43
T45
T7
T9
BH28
N25
AF8
AF35
BB2
BE25
BH30
F4
G25
N11
BH18
BH22
BK30
AR17
J39
U31
U49
V11
V15
V17
V2
V27
V29
V33
V35
V4
V41
V43
V45
V48
V7
V9
Y15
Y17
Y33
Y35
Y37
AR8
AR6
BF15
BD15
BF24
BD24

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P23-PCH (8/8) VSS

P23-PCH (8/8) VSS

P23-PCH (8/8) VSS

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

23 54Fri da y, S epte mb er 2 8, 201 2

23 54Fri da y, S epte mb er 2 8, 201 2

23 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

+3V S

1

2

5

C119 9

C119 9
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

EN_T S[19 ]

SI23 01 CDS-T 1-G E3_ SO T2 3-3

SI23 01 CDS-T 1-G E3_ SO T2 3-3

12

R108 6

R108 6
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

13

D

D

2

Q33 6

Q33 6

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

EN_CAM# control circuit

+3V S_T S+3V S

1 2

R108 4 0_06 03 _5% ~D@R1 08 4 0_06 03_ 5%~ D@

Q33 5

Q33 5

S

S

D

D

13

G

G

2

1

2

Touch Screen Power

D D

eDP BackLight Power

B+

2

G

G

60mil

12

R535

R535
1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

12

R536

R536
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

13

D

D

Q71

Q71
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

R531 0_0 603 _5 %~D@R 531 0_0 603 _5% ~D@

SI34 57 CDV-T 1-G E3_ TS OP 6~D

SI34 57 CDV-T 1-G E3_ TS OP 6~D

4 5

PWR_ SRC_ ON

S

S

C C

12

C613

C613

0.1U _04 02 _25 V6K ~D

0.1U _04 02 _25 V6K ~D

R538

@ R53 8

@

0_0 402 _5 %~D

0_0 402 _5 %~D

12

EN_I NVP WR[3 5]

B B

SHORT

+LCD VDD_ R

Discharg Circuit

C120 0

C120 0
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1 2

Q70

Q70

D

D

6

2
1

G

G

Vgs(th) = -1 ~ -3, max 20V

3

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

+LCD VDD_ R

4

60mil

R542

@ R54 2

@

+INV _PWR _SR C

+3V ALW

12

61

2

1

C612

C612

0.1U _04 02 _25 V6K ~D

0.1U _04 02 _25 V6K ~D

2

+INV _PWR _SR C

12

@

@

R541

R541
820 _08 05 _1%

820 _08 05 _1%

3

5

Q30 5B

@ Q30 5B

@

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

4

Q30 5A

@ Q30 5A

@

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

3

D90

D90

6

V I/O

USB2 0_ P12[19 ]

USB2 0_ N12[19 ]

1 2

C106 1

C106 1

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

C106 3

C106 3

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

C106 0

C106 0

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

C106 2

C106 2

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

C106 4

C106 4

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

C106 5

C106 5

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

D50

D50

6

V I/O

5

4

V I/O

IP42 23 CZ6_ SO6 ~D

IP42 23 CZ6_ SO6 ~D

+3V ALW

R977

@ R97 7

@

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

1

C114 2

C114 2

2

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

5

4

V I/O

IP42 23 CZ6_ SO6 ~D

IP42 23 CZ6_ SO6 ~D

V I/O

Ground2V BUS

V I/O

R978

R978
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+3V S

eDP_ TX N_P 1[5 ]

eDP_ TX P_ P1[ 5]

eDP_ TX N_P 0[5 ]

eDP_ TX P_ P0[ 5]

eDP_ AUX P[5]

eDP_ AUX N[ 5]

DMIC _CL K USB20_ N12 _CON N

+3V S_CA M

DMIC 0

Win8 _B TN_ SW#[3 5]

1

V I/O

Ground2V BUS

3

V I/O

1 2

R100 4 0_04 02 _5% ~D@R1 00 4 0_04 02_ 5%~ D@

L55

L55

112

4

4

WCM2 01 2F2 S-90 0T 04_ 08 05

WCM2 01 2F2 S-90 0T 04_ 08 05

1 2

R100 5 0_04 02 _5% ~D@R1 00 5 0_04 02_ 5%~ D@

eDP_ TX N_P 1_C

eDP_ TX P_ P1_ C

eDP_ TX N_P 0_C

eDP_ TX P_ P0_ C

+3V S

@

@

R103 3

R103 3
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

eDP_ AUX N_C

@

@

R103 4

R103 4
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

1

3

USB2 0_ P12 _CO NN

12

Win8 _B TN_ SW# _C

USB2 0_ P9

USB2 0_ N9

2

3

3

R100 6 0_04 02 _5% ~DR10 06 0_0 40 2_5 %~D

@ L56

@

1 2

R100 7 0_04 02 _5% ~DR10 07 0_0 40 2_5 %~D

R100 8 0_04 02 _5% ~DR10 08 0_0 40 2_5 %~D

@ L57

@

1 2

R100 9 0_04 02 _5% ~DR10 09 0_0 40 2_5 %~D

R101 0 0_ 04 02_ 5% ~D

R101 0 0_ 04 02_ 5% ~D

@ L58

@

1 2

R101 1 0_ 04 02_ 5% ~D

R101 1 0_ 04 02_ 5% ~D

2

eDP Conn

+5V S

1

2

USB2 0_ P12 _CO NN

USB2 0_ N12 _CON N

DMIC _CL K[2 5]

1 2

L56

34

eDP_ TX N_P 1_C ONN

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

1 2

L57

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

SHORT

1 2

@

@

L58

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

@

@

1 2

SHORT

For ALS Sensor

To EC

eDP_ TX P_ P1_ CONN

34

eDP_ TX N_P 0_C ONN

eDP_ TX P_ P0_ CONN

14

34

eDP_ AUX P_ CONNeDP_ AUX P_ C

eDP_ AUX N_CO NN

14

PCH_ SM LCL K[1 7,3 5]

PCH_ SM LDA TA[17,3 5]

Default control from EC connect to PCH<->EC SMBus

USB2 0_ P12 _CO NN
USB2 0_ N12 _CON N

DMIC 0

DMIC 0[2 5]

DMIC _CL K_R
ALS _SM BC LK

C119 8

C119 8
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

ALS _SM BD ATA

Reserved Pin9 a nd Pin10 to +5VS for eDP converter board

LCD_ TE ST[35 ]

TAB LE T_ MO DE[35 ]

Win8 _B TN_ SW# _C

R537

R537
100 _04 02 _1% ~D

100 _04 02 _1% ~D

DISP OFF#
INV_ PWM _R

Touch Panel

Sen sor_I2 C_S CL[27]

To Sensor HUB

Sen sor_I2 C_S DA[27]

12

12

12

+LCD VDD

C113 3

C113 3

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

DMIC 0

C120 6

C120 6

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

eDP_ HPD[5]

+INV _PWR _SR C

+3V S_T S

USB2 0_ N9[1 9]
USB2 0_ P9[ 19]

1

C114 5

C114 5
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

DMIC _CL K_RDMIC _CL K

+3V S_CA M

+LCD VDD

+3V ALW

+5V S

eDP_ TX N_P 1_C ONN
eDP_ TX P_ P1_ CONN

eDP_ TX N_P 0_C ONN
eDP_ TX P_ P0_ CONN

eDP_ AUX P_ CONN
eDP_ AUX N_CO NN

USB2 0_ N9
USB2 0_ P9

1

C114 3

C114 3
1U_0 60 3_1 0V6 K~ D

1U_0 60 3_1 0V6 K~ D

2

@ R98 3

@

@ R98 4

@

R985

@ R98 5

@

0_0 402 _5 %~D

0_0 402 _5 %~D

R986

@ R98 6

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1

R983
0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

R984
0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

12

12

12

12

JLVD S2

JLVD S2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

ACES _5 040 6-02 07 1-00 1

ACES _5 040 6-02 07 1-00 1

CONN@

CONN@
SP0 100 16 L00

SP0 100 16 L00

SP010016L00

JLVD S1

JLVD S1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

G1

22

G2

23

G3

24

G4

ACES _5 040 6-02 07 1-00 1

ACES _5 040 6-02 07 1-00 1

CONN@

CONN@
SP0 100 16 L00

SP0 100 16 L00

SP010016L00

ALS _SM BC LK

ALS _SM BD ATA

Right HingeLeft Hinge

BackLight PWM Control

D72

D72

BKO FF# DISP OFF#

BKO FF#[35]

A A

EC_I NV_ PWM[35]

PCH_ INV_ PWM[ 18]

42

9/10, For fix panel adjusting on leagcy

and UEFI mode, pop D92

5

12

SDM K03 40 L-7-F_ SO D32 3-2~ D

SDM K03 40 L-7-F_ SO D32 3-2~ D

D73

D73
SDM K03 40 L-7-F_ SO D32 3-2~ D

SDM K03 40 L-7-F_ SO D32 3-2~ D

12

12

D92

D92
SDM K03 40 L-7-F_ SO D32 3-2~ D

SDM K03 40 L-7-F_ SO D32 3-2~ D

12

10K _04 02 _5% ~D

10K _04 02 _5% ~D

R540

R540

12

R545

R545
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

INV_ PWM _R

1

C115 1

@C1 15 1

@

680 P_0 40 2_5 0V7 K~D

680 P_0 40 2_5 0V7 K~D

2

4

Camera Power

+3V ALW

SI23 01 CDS-T 1-G E3_ SO T2 3-3

SI23 01 CDS-T 1-G E3_ SO T2 3-3

S

S

12

2

R543

C617

C617

.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

EN_C AM[19 ]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

R543
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1

13

D

D

2

Q42

Q42

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

EN_CAM# control circuit

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Q47

Q47

D

D

13

G

G

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

+3V S_CA M

Deciphered Date

Deciphered Date

Deciphered Date

+3V S_CA M

C115 8

C115 8
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

1

C115 9

C115 9
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P24-eDP/ Camera CONN

P24-eDP/ Camera CONN

P24-eDP/ Camera CONN

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

24 54Fri da y, S epte mb er 2 8, 201 2

24 54Fri da y, S epte mb er 2 8, 201 2

24 54Fri da y, S epte mb er 2 8, 201 2

1

1

2

2

1.0

1.0

1.0

5

D D

4

3

2

1

2

1

DMIC 0[2 4]

C C

B B

DMIC _CL K[2 4]

HDA_ SPK R[1 6]
HDA_ SDIN 0[16]
HDA_ SDO UT_ AUDI O[ 16] BAT T_ LO W_LE D# [35 ]

HDA_ RST _A UDIO#[1 6]
HDA_ SYN C_AU DIO[ 16]

HDA_ BIT CLK _AU DIO[ 16]

8/31, for EMI request, modify
LH9 P/N to SM01000LJ0L

1 2

HDA_ BIT CLK _AU DIO_ C

LH9

LH9

BLM 18 BD4 70S N1D

BLM 18 BD4 70S N1D

+RT CVCC

41

+3V S

+5V S

+5V S +3VA LW +3V S +5V ALW

C114 6

C114 6
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

C109 9

C109 9
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

1

JIOL 1

JIOL 1

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

20

20

18

18

16

16

14

14

12
10

8
6
4
2

E-T_ 10 01K -F36 E-03 L

E-T_ 10 01K -F36 E-03 L

CONN@

CONN@
DC03 120 11 60

DC03 120 11 60

SP01000Q5 10

GND37GND

35
33
31
29
27
25
23
21
19
17
15
13
111112

9910
778
556
334
112

35
33
31
29
27
25
23
21
19
17
15
13

2

C110 0

C110 0
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

1

VOL UME _UP _SW #_C
VOL UME _DO WN_S W#_ C
ROT AT ION_ LOC K_S W#_ C

+3V ALW
+5V ALW

+5V S

2

C110 1

C110 1
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

1

PBT N_S W# [35 ]
LID_ SW_ IN# [3 5]
BAT T_ CHG _LE D# [35 ]

EAP D# [35]
AUD_ MUT E# [3 5]
BEE P# [ 35]

2

C109 8

C109 8
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

1

VOL UME _UP _SW #_C

VOL UME _DO WN_S W#_ C

ROT AT ION_ LOC K_S W#_ C

Pull-up resistor is on EC page (10K)

1 2

R953

R953

1

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

C112 3

C112 3

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

2

Pull-up resistor is on EC page (10K)

1 2

R955

R955

1

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

C112 4

C112 4

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

2

Pull-up resistor is on PCH (10K)

1 2

R957

R957

1

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

C112 5

C112 5

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

2

VOL UME _UP _SW # [ 35]

VOL UME _DO WN_S W# [35 ]

ROT AT ION_ LOC K_S W# [1 9]

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P25-IOL Conn

P25-IOL Conn

P25-IOL Conn

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

25 54Fri da y, S epte mb er 2 8, 201 2

25 54Fri da y, S epte mb er 2 8, 201 2

25 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

4

3

2

1

Mini DP CONN

D D

SN74CBT3257CPWR Vcc spec is 5V

+5V S

1

CV13

CV13

0.1U _04 02 _10 V6K ~D

0.1U _04 02 _10 V6K ~D

2

12

PCH_ DP_ AUXP[ 18]
PCH_ DP_ CLK[18]
PCH_ DP_ AUXN[1 8]
PCH_ DP_ DAT[18]

C C

B B

12

CV80.1U_0 402 _10 V7 K~D CV80. 1U_0 40 2_1 0V 7K~ D

CV100. 1U_ 040 2_1 0V 7K~ D CV 100.1 U_0 402 _10 V7 K~D

PCH_ DP_ AUXN _C

S = L, A port = B1 port
S = H, A port = B2 port

SN74 CBT 32 57C PWR_ TS SOP 16 ~D

SN74 CBT 32 57C PWR_ TS SOP 16 ~D

DISP _DA T_ AUXN _CO NN

DISP _CL K_A UXP _CO NN

UV1

UV1

16

Vcc

4

1A

2

7

1B1

2A

3

9

1B2

3A

5

12

2B1

4A

6

2B2

11

15

3B1

OE#

1

10

S

3B2

14

4B1

8

13

GND

4B2

1 2

RV2 1 00K _04 02 _5% ~DRV2 10 0K_ 04 02_ 5%~ D

1 2

RV3 1 00K _04 02 _5% ~DRV3 10 0K_ 04 02_ 5%~ D

DISP _CL K_A UXP _CO NN
DISP _DA T_ AUXN _CO NNPCH_ DP_ AUXP _C

DP_C BL_ DET

1 : HDMI/DVI/VGA Dongle
0 : DP Port

+3V S

PCH_ DP_ P0[ 18]

PCH_ DP_ N0[1 8]

PCH_ DP_ P1[ 18]
PCH_ DP_ P3[ 18]
PCH_ DP_ N1[1 8]
PCH_ DP_ N3[1 8]

PCH_ DP_ P2[ 18]

PCH_ DP_ N2[1 8]

S

PCH_ DP_ HPD[18]

DP_C BL_ DET[19 ]

S

@ RV8

@

1 2

DP_C BL_ DET CAB_ DET _S INK

DP Signal ESD

Non CIS

DV1

DV1

1

10

8

8

DV2

DV2

8

8

RCLA MP 052 4P. TCT ~D

RCLA MP 052 4P. TCT ~D

Non CIS

PCH_ DP_ N0_ C

9

PCH_ DP_ P0_ C

7

PCH_ DP_ P1_ C

6

PCH_ DP_ N1_ C

10

PCH_ DP_ P3_ C

9

PCH_ DP_ N3_ C

7

PCH_ DP_ N2_ C

6

PCH_ DP_ P2_ CPCH_ DP_ P2_ C

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

PCH_ DP_ N0_ C

2

PCH_ DP_ P0_ C

4

PCH_ DP_ P1_ C

5

PCH_ DP_ N1_ C

3

RCLA MP 052 4P. TCT ~D

RCLA MP 052 4P. TCT ~D

Place close JD P1

1

PCH_ DP_ P3_ C

2

A A

5

PCH_ DP_ N3_ C

PCH_ DP_ N2_ C

4

4

5

3

+3V S

+5V S

G

G

2

13

D

D

QV1

QV1

BSS 138 -G_ SOT 23 -3

BSS 138 -G_ SOT 23 -3

RV8
0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

Co-lay

1 2

1.5A _6 V_1 206 L1 50P R~D

1.5A _6 V_1 206 L1 50P R~D

RV1 0_ 120 6_ 5%~ D@ R V1 0_ 120 6_5 %~D@

12

CV3.1U_ 040 2_1 6V 7K~ D CV 3.1U_04 02 _16 V7K ~D

12

CV4.1U_ 040 2_1 6V 7K~ D CV 4.1U_04 02 _16 V7K ~D

12

CV5.1U_ 040 2_1 6V 7K~ D CV 5.1U_04 02 _16 V7K ~D

12

CV6.1U_ 040 2_1 6V 7K~ D CV 6.1U_04 02 _16 V7K ~D

12

CV7.1U_ 040 2_1 6V 7K~ D CV 7.1U_04 02 _16 V7K ~D

12

CV9.1U_ 040 2_1 6V 7K~ D CV 9.1U_04 02 _16 V7K ~D

12

CV11.1U_0 40 2_1 6V 7K~ D CV1 1.1 U_0 402 _1 6V7 K~D

12

CV12.1U_0 40 2_1 6V 7K~ D CV1 2.1 U_0 402 _1 6V7 K~D

DISP _HP D_S INK

12

RV10

RV10
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

12

RV9

RV9
1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

FV1

FV1

12

DISP _HP D_S INK
PCH_ DP_ P0_ C
CAB_ DET _S INK
PCH_ DP_ N0_ C

PCH_ DP_ P1_ C
PCH_ DP_ P3_ C
PCH_ DP_ N1_ C
PCH_ DP_ N3_ C

PCH_ DP_ P2_ C
DISP _CL K_A UXP _CO NN
PCH_ DP_ N2_ C
DISP _DA T_ AUXN _CO NN

Tit le

Tit le

Tit le

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

C

C

C

Date : She et of

Date : She et of

Date : She et of

CV14 0.1U _0402_10V6K~DC V14 0.1U_0402_10V6K~D

1

2

CV1

10U_0603_6.3V6M~D

CV1

10U_0603_6.3V6M~D

1

2

DISP _CE C

CV15 22U_0805_6. 3V6M~DCV15 22U_0805_6.3V6M~D

RV4 5.1M_0402_5%RV4 5.1M_0402_5%

12

1

2

LA-8821P

LA-8821P

LA-8821P

CV2

.1U_0402_16V7K~D

CV2

.1U_0402_16V7K~D

1

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

JMDP 1

JMDP 1

1

GND

2

HPD

3

LANE0_P

4

CONFIG1

5

LANE0_N

6

CONFIG2

7

GND

8

GND

9

LANE1_P

10

LANE3_P

11

LANE1_N

12

LANE3_N

13

GND

14

GND

15

LANE2_P

16

AUX_CH_P

17

LANE2_N

GND1

18

AUX_CH_N

GND2

19

GND

GND3

DP_PWR20GND4

ACON _M AR2 B-20 K12 00

ACON _M AR2 B-20 K12 00

CONN@

CONN@
SP0 612 04 160

SP0 612 04 160

DC060007E00

P26-Mini DP CONN

P26-Mini DP CONN

P26-Mini DP CONN

1

21
22
23
24

1.0

1.0

1.0

26 54Fri da y, S epte mb er 2 8, 201 2

26 54Fri da y, S epte mb er 2 8, 201 2

26 54Fri da y, S epte mb er 2 8, 201 2

5

+3V S +3V NS_P WR

+3V S

R109 4

R109 4

1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

1 2

13

D

D

Q33 4

Q33 4

D D

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

Sen sor_I2 C_S CL

R854 2.2K _0 402 _5 %~DR854 2 .2K _0 402 _5% ~D

Sen sor_I2 C_S DA

R855 2.2K _0 402 _5 %~DR855 2 .2K _0 402 _5% ~D

+3V NS_P WR

R817

R817

1.5K _0 402 _1 %~D

1.5K _0 402 _1 %~D

C C

USB2 0_ N13[19 ]
USB2 0_ P13[19 ]

R110 4

R110 4

1.5K _0 402 _1 %~D @

1.5K _0 402 _1 %~D @

Sen sor_I2 C_S CL[24]
Sen sor_I2 C_S DA[24]

SH_D FU_E N#[20 ]

DFU_ENA : uC DFU mode enable (Active Low)

Y2

Y2

8MH Z_1 8PF _X1 H00 800 0DI 1H-W

8MH Z_1 8PF _X1 H00 800 0DI 1H-W

1

B B

C120 4

C120 4
27P _04 02 _50 V8J ~D

27P _04 02 _50 V8J ~D

2

2

G

G

1 2

1 2

12

12

R110 6

R110 6

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

Sen sor_I2 C_S CL
Sen sor_I2 C_S DA

34
21

QH8

QH8

AO3 419 L_ SOT 23 -3

AO3 419 L_ SOT 23 -3

S

S

G

G

2

12

1M_ 04 02_ 5% ~D @

1M_ 04 02_ 5% ~D @

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

ACC_ INT 1

GYRO _IN T#

MAG _DR DY
GYRO _DR DY

ACC_ INT 2

JTM S
JTCK
JTDI

BOOT1

JTDO
JNTR ST

STM 32 F10 3RCY 6T R_W LCSP 64

STM 32 F10 3RCY 6T R_W LCSP 64

1

C120 5

C120 5
27P _04 02 _50 V8J ~D

27P _04 02 _50 V8J ~D

2

D

D

13

R110 5

R110 5

C120 7

C120 7

+3V NS_P WR

SH_V BA T

1 2

SH_P WR_ CNTR L [ 20]

1

2

+3V NS_P WR

C979

C979

1 2

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

G8

A8

A1

G6

PA0-WKUP
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

VDD_3

VDD_4

VSS_3

VSS_4

F5

A7

HUB_ OSC _IN

HUB_ OSC _OUT

H1

VDDA

VDD_2

VDD_1

PC10
PC11
PC12
PC13
PC14
PC15

NRST

BOOT0

Vref+

Vbat

OSC_IN

OSC_OUT

BYPASS/V SS_2

VSSA

VSS_1

B1

E7

H2

U636

U636

F6
E6
H8

G7

H7

E5
G5
G4

E4

D2

D3

C1

C2

D4

B2

C3

H4

F4

H3
A4

B4
A5

B5

C5

D5

B6
G3

F3
G2
G1

F2

F1

+3V NS_P WR

E8

I2C_ INT #

PC0

F8

SBD_ WAK E#

PC1

D6

SBD_ INT #

PC2

H6

PC4

H5

PC5

E1

PC6

E2

PC7

E3

PC8

D1

PRES SUR E_I NT#

PC9

A2
B3
C4
C8
B8

SOS CI

B7

SOS CO

A3

PD2

C7

RESE T#

A6

BOO T0

F7
C6

R110 1 0_04 02 _5% ~D@R 110 1 0_04 02 _5% ~D@

D8

HUB_ OSC _IN

D7

HUB_ OSC _OUT

+3V NS_P WR

1

2

4

Sensor Fussion

1 2

R109 5 10 K_ 040 2_ 5%~ DR1 095 10K_ 04 02_ 5%~ D

1 2

R109 6 10 K_ 040 2_ 5%~ DR1 096 10K_ 04 02_ 5%~ D

1 2

R109 7 10 K_ 040 2_ 5%~ DR1 097 10K_ 04 02_ 5%~ D

1 2

R109 8 10 K_ 040 2_ 5%~ DR1 098 10K_ 04 02_ 5%~ D

1 2

R109 9 10 K_ 040 2_ 5%~ DR1 099 10K_ 04 02_ 5%~ D

T24 9@ T2 49@
T25 2@ T2 52@
T25 3@ T2 53@

T25 0@ T2 50@

+3V NS_P WR

12

+RT CVCC

12

0_0 402 _5 %~D

0_0 402 _5 %~D

+3V ALW

R110 2

R110 2

SH_V BA T

Place close to U636

1

C976

C976

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

C977

C977

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

JTM S

JTDO

JTDI

JNTR ST

JTCK

Sen sor_RS T#

@ R10 90

@

1 2

1 2

R108 9

R108 9
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+3V NS_P WR

SHORT

R109 0
0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

@

@

R109 2

R109 2
0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

R819

R819
0_0 402 _5 %~D

0_0 402 _5 %~D

@

@

1 2

1

C978

C978
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

JTM S [29 ]

JTDO [2 9]

JTDI [29 ]

JNTR ST [29 ]

JTCK [2 9]

Sen sor_RS T# [2 9]

Sen sor_RS T#

15

+3V NS_P WR

R100 3

R100 3
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

1

C115 2

@C1 15 2

@

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

3

8/20, Follow DFB suggest, modify Y1 footprint.

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

SOS CI S OS CO

1

CH12 02

CH12 02
18P _04 02 _50 V8J ~D

18P _04 02 _50 V8J ~D

2

3

Connect to mSATA card for
Debug/Programing used

Y1

Y1

12

1

CH12 03

CH12 03
18P _04 02 _50 V8J ~D

18P _04 02 _50 V8J ~D

2

C964 Should be low ESR (220mOhm) ceramic type

C968

C968

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

12

C964 0. 22U _04 02 _10 V6K ~DC964 0. 22U _04 02 _10 V6K ~D

1

MAG _DR DY

2

+3V NS_P WR

R110 7

R110 7
0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

+3V NS_P WR

Sen sor_I2 C_S CL

12

Sen sor_I2 C_S DA

R109 1

R109 1
0_0 402 _5 %~D

0_0 402 _5 %~D

GYRO _DR DY

GYRO _IN T#

+3V NS_P WR

2

e-Compass + Accelerometer

+3V NS_P WR + 3VN S_P WR

U637

U637

1

Vdd_IO

6

C1

12

SETP

13

SETC

8

Peserved

9

Peserved

10

Peserved

11

Peserved

7

GND

DE30 3DL HCT R_L GA1 4_ 3X5 ~D

DE30 3DL HCT R_L GA1 4_ 3X5 ~D

+3V NS_P WR

Place close to U637 Pin1, 14

1

C965

C965

0.22 U_0 40 2_1 0V6 K~D

0.22 U_0 40 2_1 0V6 K~D

2

14

Vdd

3

SDA

2

SCL

5

INT1

4

INT2

1

C966

C966

0.22 U_0 40 2_1 0V6 K~D

0.22 U_0 40 2_1 0V6 K~D

2

Sen sor_I2 C_S DA

Sen sor_I2 C_S CL

ACC_ INT 1

ACC_ INT 2

Gyro

U638

U638

1

VDD_IO

2

SCL/SPC

3

SDA/SDI/SDO

4

SDO/SA0

5

CS

6

DRDY/INT2

7

INT1

8

RES_0

TX3 GD2 0T R_L GA1 6_ 4X4 ~D

TX3 GD2 0T R_L GA1 6_ 4X4 ~D

9

RES_1

10

RES_2

11

RES_3

12

RES_4

13

GND

14

RES_5

15

RES_6

16

VDD

Place close to U638 Pin 1,15,16

C969

C969
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

1

C970

C970
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

1

2

+3V NS_P WR

R110 8

R110 8
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

1

C974

C974

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

2

1

ATMEL TPM

A A

CLK_ PCI _T PM

12

R976

@ R97 6

@

33_ 040 2_ 5%~ D

33_ 040 2_ 5%~ D

1

C114 1

@ C11 41

@

27P _04 02 _50 V8J ~D

27P _04 02 _50 V8J ~D

2

5

+3V S

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

1

C1135

C1135

C1136

TPM @

TPM @

LPC_ AD0[16, 28, 35]
LPC_ AD1[16, 28, 35]
LPC_ AD2[16, 28, 35]
LPC_ AD3[16, 28, 35]

CLK_ PCI _T PM[17 ]
LPC_ FRA ME #[16,2 8,3 5]
PLT _RS T#[ 19, 28,3 5,6 ]
SERI RQ[16,3 5]
PM_ CLK RUN#[18]

C1136

TPM @

TPM @

2

2

CLK_ PCI _T PM

+3V S

28

26
23
20
17

21
22
16
27
15

U652

TPM @U65 2

TPM @

5

SB3V

Non CIS

LPCPD#

LAD0
LAD1
LAD2
LAD3

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#

1

ATEST_1

2

ATEST_2

3

ATEST_3

AT9 7S C32 04-X 2A1 8-A B_T SS OP2 8

AT9 7S C32 04-X 2A1 8-A B_T SS OP2 8

4

NBO_13
NBO_14

GND_11
GND_18
GND_25

VCC_0
VCC_1
VCC_2

V_BAT

TESTBI

GND_4

GPIO6

TESTI

NC_7

10
19
24

12
13
14

6

9
8

7

PP

4
11
18
25

+3V S

2200P_0402_25V7K~D

2200P_0402_25V7K~D

2200P_0402_25V7K~D

2200P_0402_25V7K~D

1

1

C1137

C1137

2

2

TPM @

TPM @

TPM @

TPM @

TPM @

TPM @

@

@

1 2

R975 4.7K _0 402 _5 %~D

R975 4.7K _0 402 _5 %~D

2200P_0402_25V7K~D

2200P_0402_25V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

C1139

C1139

C1138

C1138

C1140

C1140

2

2

TPM @

TPM @

+3V S

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P27-Sensor Fussion / TPM

P27-Sensor Fussion / TPM

P27-Sensor Fussion / TPM

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

27 54Fri da y, S epte mb er 2 8, 201 2

27 54Fri da y, S epte mb er 2 8, 201 2

27 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

A

Wireless LAN

1 1

1 2

R942 10K _04 02 _5% ~D@ R94 2 10 K_0 40 2_5 %~D@

+3V S_WL AN

EC_W LAN _WAK E#[3 5]

MINI 1CL K_R EQ#[17]

CLK_ PCI E_M INI1 #[1 7]
CLK_ PCI E_M INI1[ 17]

CLK_ LP C_DE BUG[19 ]

PCIE _PR X_W LANT X_ N3[17]
PCIE _PR X_W LANT X_ P3[17 ]

PCIE _PT X_ WLA NRX_ N3[17]
PCIE _PT X_ WLA NRX_ P3[17 ]

PCIE _M CARD 1_DE T#[20]

2 2

EC_T X[35 ]
EC_R X[35]

BT_ RAD IO_ DIS#[20]

3 3

PLT _RS T#

16

@

@

SHORT

1 2

R728 0_0 402 _5 %~D

R728 0_0 402 _5 %~D

1 2

R729 0_0 402 _5 %~D

R729 0_0 402 _5 %~D

@

@

R730 100K _0 402 _5 %~DR730 100K _0 402 _5 %~D

USB2 0_ P4[ 19]

USB2 0_ N4[1 9]

WL_O FF# _R

SHORT

1 2

R101 7 0_04 02 _5% ~D@R1 01 7 0_04 02_ 5%~ D@

+3V S_WL AN

EC_T X_ R
EC_R X_R

12

1 2

R731 1K_ 040 2_1 %~ DR73 1 1K _04 02 _1% ~D

12

R102 0

R102 0

10K _04 02 _5% ~D

10K _04 02 _5% ~D

Internal PU about 50K

R741 0_0 402 _5 %~D@R 741 0_0 402 _5% ~D@

R742 0_0 402 _5 %~D@R 742 0_0 402 _5% ~D@

+3V S+3VS _WL AN

2

G

G

1 3

D

D

Prevent Backdriver from +3VS_WLAN to +3VS

4 4

16

SHORT

1 2

L49

@ L49

@

WCM2 01 2F2 S-90 0T 04_ 08 05

WCM2 01 2F2 S-90 0T 04_ 08 05

4

4

112

SHORT

1 2

16

Q32 8

Q32 8
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

JWLA N1

JWLA N1

112
334
556
778
9910
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
G153G2

BEL LW_ 800 19-1 02 1

BEL LW_ 800 19-1 02 1

CONN@

CONN@
DC04 000 4X 00

DC04 000 4X 00

DC040004X0 0

3

3

2

WL_O FF# [19 ]

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

USB2 0_ P4_ R

USB2 0_ N4_ R

B

+3V S_WL AN

+1.5 VS_ WLA N +3V S_WL AN

C707

4.7U_0603_6.3V6K~D

C707

4.7U_0603_6.3V6K~D

1

2

+1.5 VS_ WLA N

SHORT

1 2

R101 2 0_04 02 _5% ~D@R1 01 2 0_04 02_ 5%~ D@

1 2

R101 3 0_04 02 _5% ~D@R1 01 3 0_04 02_ 5%~ D@

1 2

R101 4 0_04 02 _5% ~D@R1 01 4 0_04 02_ 5%~ D@

1 2

R101 5 0_04 02 _5% ~D@R1 01 5 0_04 02_ 5%~ D@

1 2

R101 6 0_04 02 _5% ~D@R1 01 6 0_04 02_ 5%~ D@

Internal PU about 50K

WL_O FF# _R
PLT _RS T#

MINI 1_S MB CLK
MINI 1_S MB DAT A

USB2 0_ N4_ R
USB2 0_ P4_ R
USB_ MC ARD1 _DE T#

USB_ MC ARD1 _DE T# [2 0]

C

JP1

@ JP1

@

2

C709

.1U_0402_16V7K~D

C709

.1U_0402_16V7K~D

C710

0.01U_0402_16V7K~D

C710

0.01U_0402_16V7K~D

C708

.1U_0402_16V7K~D

C708

.1U_0402_16V7K~D

1

1

1

2

2

2

112

JUMP _4 3X3 9

JUMP _4 3X3 9

@ C711

@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

C711

47P_0402_50V8J~D

47P_0402_50V8J~D

1

1

2

2

LPC_ FRA ME # [16 ,27 ,35 ]
LPC_ AD3 [1 6,2 7,3 5]
LPC_ AD2 [1 6,2 7,3 5]
LPC_ AD1 [1 6,2 7,3 5]
LPC_ AD0 [1 6,2 7,3 5]

PLT _RS T# [1 9,2 7,3 5,6 ]

+1.5 VS_ WLA N+ 1.5V S

@ C714

C715

.1U_0402_16V7K~D

C715

.1U_0402_16V7K~D

C712

C712

1

2

@

C714

47P_0402_50V8J~D

47P_0402_50V8J~D

C713

0.01U_0402_16V7K~D

C713

0.01U_0402_16V7K~D

C716

.1U_0402_16V7K~D

C716

.1U_0402_16V7K~D

1

1

1

2

2

2

RF switcher

2.2K _0 402 _5 %~D

2.2K _0 402 _5 %~D

MINI 1_S MB CLK

MINI 1_S MB DAT A

D

+3V S_WL AN

R101 8

R101 8

R101 9

R101 9

2.2K _0 402 _5 %~D

1 2

2.2K _0 402 _5 %~D

1 2

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

Q32 7B

Q32 7B

R724 0_ 040 2_5 %~D@ R 724 0_0 40 2_5 %~D@

354

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

1 2

R725 0_ 040 2_5 %~D@ R 725 0_0 40 2_5 %~D@

2

1 2

Q32 7A

Q32 7A

61

E

SMB CLK [17]

SMB DAT A [1 7]

Antenna location Diagram (Top View)

1

2

PCH_GPIO48

PCH_GPIO49

RFSW_ VCO NT1[20 ]

RFSW_ VCO NT2[20 ]

JANT 2

@ JANT 2

@

1

G

2

2

3

G

HRS_ UPFL -R-SM T-1 (10 )

HRS_ UPFL -R-SM T-1 (10 )

RRF1 0_04 02 _5% ~D

RRF1 0_04 02 _5% ~D

RRF2 0_04 02 _5% ~D

RRF2 0_04 02 _5% ~D

WLAN

RFSW_ IN

@

@

@

@

12

12

Layout Diagram

To Panel side Antenna

6

5

2

Bottom

To WLAN

5

6

4

@ URF1

@

SKY 133 51 -378 LF_ QFN6 _1 X1

SKY 133 51 -378 LF_ QFN6 _1 X1

View

314

To Speaker side Antenna

URF1

1

IN

OUT1

3

VCONT1

OUT2

2

VCONT2

GND

SKY13351-378LF Truth Table

0

Insertion loss

1

Isolation

CRF2

@ CRF2

@

100 P_0 40 2_5 0V8 J~D

100 P_0 40 2_5 0V8 J~D

1 2

RFSW_ IN_ C

1

CRF4

@CR F4

@

33P _04 02 _50 V8J ~D

33P _04 02 _50 V8J ~D

2

1

CRF5

@CR F5

@

33P _04 02 _50 V8J ~D

33P _04 02 _50 V8J ~D

2

VCTL1 (Pin 6) VCTL2 (Pin 4) INPUT to OUTPUT1 Path INPUT to OUTPUT2 Path

1

0

RFSW_ OUT 1_ C

RFSW_ OUT 2_ C

ANT3

Panel side Antenna

CRF1

@ CRF1

@

100 P_0 40 2_5 0V8 J~D

100 P_0 40 2_5 0V8 J~D

1 2

RFSW_ OUT 1

CRF3

@ CRF3

@

100 P_0 40 2_5 0V8 J~D

100 P_0 40 2_5 0V8 J~D

1 2

RFSW_ OUT 2

Insertion loss

Isolation

3

ANT2

JANT 1

@ JANT 1

@

2

2

HRS_ UPFL -R-SM T-1 (10 )

HRS_ UPFL -R-SM T-1 (10 )

JANT 3

@ JANT 3

@

2

2

HRS_ UPFL -R-SM T-1 (10 )

HRS_ UPFL -R-SM T-1 (10 )

Speaker side Antenna

ANT1

1

G

3

G

1

G

3

G

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P28-WLAN / WiGig / BT

P28-WLAN / WiGig / BT

P28-WLAN / WiGig / BT

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

28 54Fri da y, S epte mb er 2 8, 201 2

28 54Fri da y, S epte mb er 2 8, 201 2

28 54Fri da y, S epte mb er 2 8, 201 2

E

1.0

1.0

1.0

5

4

3

2

1

mSATA Card

JSAT A1

JSAT A1

1

2

1

2

3

4

3

4

5

6

5

6

7

8

7

8

9

10

9

10

11

12

11

12

13

D D

1 2

SAT A_ PRX _DT X_P 0[16]
SAT A_ PRX _DT X_N 0[ 16]

SAT A_ PT X_DR X_N 0[ 16]
SAT A_ PT X_DR X_P 0[16]

C C

B B

CS54 0.0 1U_ 040 2_ 16V 7K~ DCS54 0.01 U_0 402 _16 V7 K~D

1 2

CS53 0.0 1U_ 040 2_ 16V 7K~ DCS53 0.01 U_0 402 _16 V7 K~D

1 2

CS43 0.0 1U_ 040 2_ 16V 7K~ DCS43 0.01 U_0 402 _16 V7 K~D

1 2

CS42 0.0 1U_ 040 2_ 16V 7K~ DCS42 0.01 U_0 402 _16 V7 K~D

mSA TA _DE T#[20]

+3V S

T24 4@ T2 44@
T24 5@ T2 45@
T24 6@ T2 46@

SAT A_ PRX _DT X_P 0_ C
SAT A_ PRX _DT X_N 0_C

SAT A_ PT X_DR X_N 0_C
SAT A_ PT X_DR X_P 0_ C

14

13

14

15

16

15

16

17

18

17

18

19

20

19

20

21

22

21

22

23

24

TX+

23

24

25

26

TX-

25

26

27

28

27

28

29

30

29

30

31

32

RX-

31

32

33

34

RX+

33

34

35

36

35

36

37

38

37

38

39

40

39

40

41

42

41

42

43

44

43

44

45

46

45

46

47

48

47

48

49

50

49

50

51

52

51

52

53

54

GND1

GND2

TYC O_2 04 111 9-1

TYC O_2 04 111 9-1

CONN@

CONN@
SP0 100 0JD 00

SP0 100 0JD 00

SP01000JD00

ME Decide using 16 pin conn
MB 16 <-------> 15 pin NFC (Reserved Connection)

JTM S [27 ]
JTDO [2 7]
JTDI [27 ]
JTCK [2 7]
JNTR ST [27 ]

Sen sor_RS T# [2 7]

+3V NS_P WR

T24 2@ T2 42@
T24 3@ T2 43@

+3V S

+3V S

Connect to Sensor HUB uC JTAG for
Debug/Programing used

C719

4.7U_0603_6.3V6K~D

C719

4.7U_0603_6.3V6K~D

C720

.1U_0402_16V7K~D

C720

.1U_0402_16V7K~D

1

1

1

2

2

2

C721

0.01U_0402_16V7K~D

C721

0.01U_0402_16V7K~D

C722

47P_0402_50V8J~D

C722

47P_0402_50V8J~D

1

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P29-mSATA / NFC Conn

P29-mSATA / NFC Conn

P29-mSATA / NFC Conn

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

C

C

C

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

29 54Fri da y, S epte mb er 2 8, 201 2

29 54Fri da y, S epte mb er 2 8, 201 2

29 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

A

USB IO Port

1 1

USB3 TP 1[19]

USB3 TN 1[19]

USB3 RN1[19]

USB3 RP1[19 ]

2 2

3 3

4 4

SW_U SB2 0_ P1

SW_U SB2 0_ N1

1 2

C621 0. 1U_ 040 2_ 10V 7K~ DC6 21 0.1 U_04 02 _10 V7 K~D

1 2

C623 0. 1U_ 040 2_ 10V 7K~ DC6 23 0.1 U_04 02 _10 V7 K~D

Power share

L auto detection charger identification active

H

PWRS HARE _OE #[35]
USB2 0_ N1[1 9]
USB2 0_ P1[ 19]

.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

USB2 0_ N0[1 9]

USB2 0_ P0[ 19]

USB3 TP 0[19]

USB3 TN 0[19]

USB3 RN0[19]

USB3 RP0[19 ]

A

USB3 TP 0

USB3 TN 0

USB3 RN0

DP/DM=TDP/TDM

C961

C961

USB2 0_ N0

C110 7

C110 7

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

1 2

1 2

C110 8

C110 8

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

FunctionCB

+5V ALW

2

1

USB3 TN 1_C

UI1

UI1

8

CB

7

TDM

6

TDP

5

VDD

Thermal Pad

SLG 555 84 AVT R_T DFN 8_2 X2

SLG 555 84 AVT R_T DFN 8_2 X2

USB3 TP 0_ C

USB3 TN 0_C

SELCDP

CEN

DM
DP

R262 0_0 402 _5 %~D@R 262 0_0 402 _5% ~D@

L40

L40

4

4

112

WCM2 01 2F2 S-90 0T 04_ 08 05

WCM2 01 2F2 S-90 0T 04_ 08 05

R222 0_0 402 _5 %~D@R 222 0_0 402 _5% ~D@

R555 0_0 402 _5 %~D@R 555 0_0 402 _5% ~D@

1 2

R556 0_0 402 _5 %~D@R 556 0_0 402 _5% ~D@

R560 0_0 402 _5 %~D@R 560 0_0 402 _5% ~D@

1 2

R565 0_0 402 _5 %~D@R 565 0_0 402 _5% ~D@

1

PWRS HARE _EN #

2

SW_U SB2 0_ N1

3

SW_U SB2 0_ P1

4
9

B

1 2

3

1 2

1 2

L45

L45

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

1 2

L46

L46

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

1 2

R888 0_0 402 _5 %~D@R 888 0_0 402 _5% ~D@

L52

L52

112

4

4

WCM2 01 2F2 S-90 0T 04_ 08 05

WCM2 01 2F2 S-90 0T 04_ 08 05

1 2

R889 0_0 402 _5 %~D@R 889 0_0 402 _5% ~D@

1 2

R890 0_0 402 _5 %~D@R 890 0_0 402 _5% ~D@

L53

L53

1 2

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

R891 0_0 402 _5 %~D@R 891 0_0 402 _5% ~D@

1 2

R892 0_0 402 _5 %~D@R 892 0_0 402 _5% ~D@

L54

L54

1 2

DLW2 1SN 670 HQ2 L_4 P~D

DLW2 1SN 670 HQ2 L_4 P~D

1 2

R893 0_0 402 _5 %~D@R 893 0_0 402 _5% ~D@

B

3

2

R807 0_0 402 _5 %~D@R 807 0_0 402 _5% ~D@

34

34

+5V ALW

3

USB2 0_ P1_ CONN

USB2 0_ N1_ CONN

L40 close to JUSB1

USB3 TP 1_ RC_CO NUSB3 TP 1_ C

USB3 TN 1_R C_CO N

USB3 RN1 _RC_ CON

USB3 RP1 _RC_ CON

1 2

12

R808

R808
10K _04 02 _5% ~D

10K _04 02 _5% ~D

12

R809

@ R80 9

@

10K _04 02 _5% ~D

10K _04 02 _5% ~D

2

3

34

34

USB2 0_ N0_ CONN

USB2 0_ P0_ CONNUSB2 0_ P0

USB3 TP 0_ RC_CO N

USB3 TN 0_R C_CO N

USB3 RN0 _RC_ CON

USB3 RP0 _RC_ CONUSB3 RP0

C

Modify JUSB1 connector mfr. P/N from USB014-107CRL-TW to
USB014-107CRL-TWD (remove mayla only)

PWRS HARE _EN _EC #[35]

PWRS HARE _EN _EC #

USB_ PWR _EN#[3 5]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

D

38

USBC HG_ DET #[35]

+3V ALW

12

R806

R806

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

PWRS HARE _EN _EC #

+3V ALW

12

R887

R887

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

+5V ALW

C117 2

C117 2

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

+5V _CHG USB

USB3 TP 1_ RC_CO N

USB3 TN 1_R C_CO N
USB2 0_ P1_ CONN

USB2 0_ N1_ CONN
USB3 RP1 _RC_ CON

USB3 RN1 _RC_ CON

For ESD request

D74

D74

USB3 RN1 _RC_ CON
USB3 RP1 _RC_ CON
USB3 TN 1_R C_CO N
USB3 TP 1_ RC_CO N

1

R-

2

R+

3

T-

4

Non CIS

T+

AZ10 65 -06Q .RDG _M SOP

AZ10 65 -06Q .RDG _M SOP

2A / Channel

+5V ALW +5V_CHG USB

U656

U656

1

GND

2

VIN3VOUT

4

EN

G54 7I2 P81 U_M SO P8

G54 7I2 P81 U_M SO P8

C962

C962

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

1

1

C117 3

C117 3

.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

2

+5V _USB _P 0

USB2 0_ N0_ CONN
USB2 0_ P0_ CONN

USB3 RN0 _RC_ CON
USB3 RP0 _RC_ CON

USB3 TN 0_R C_CO N
USB3 TP 0_ RC_CO N

USB3 RN0 _RC_ CON
USB3 RP0 _RC_ CON
USB3 TN 0_R C_CO N
USB3 TP 0_ RC_CO N

Deciphered Date

Deciphered Date

Deciphered Date

D

USB 3.0 CONN

JUSB 1

JUSB 1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

GND

D-

6

GND

SSRX+

4

GND

GND

5

SSRX-

GND

10

Plug_DET

TAI WI_U SB0 14-1 07 CRL-T WD

TAI WI_U SB0 14-1 07 CRL-T WD

CONN@

CONN@
DC23 120 10 90

DC23 120 10 90

DC23300DI 00

+5V _CHG USB

8

VCC

7

GND

6

USB2 0_ N1_ CONN

D-

5

USB2 0_ P1_ CONN

D+

8

VOUT
VOUT7VIN

6

5

FLG

+5V ALW

1

1

C963

C963

.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

2

2A / Channel

+5V _USB _P 0+5V ALW

U657

U657

1

8

GND

VOUT

2

VOUT7VIN

6

VIN3VOUT

5

4

FLG

EN

G54 7I2 P81 U_M SO P8

G54 7I2 P81 U_M SO P8

USB 3.0 CONN

NA CIS

JUSB 2

JUSB 2

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON _T ARA G-9R1 39 1

ACON _T ARA G-9R1 39 1

CONN@

CONN@

SP0 612 04 161

SP0 612 04 161

DC23300DK00

For ESD request

D82

D82

1

R-

VCC

2

R+

GND

3

D-

T-

4

Non CIS

D+

T+

AZ10 65 -06Q .RDG _M SOP

AZ10 65 -06Q .RDG _M SOP

E

USB_ OC1 # [1 9]

USB_ OC0 # [1 9]

close to JUSB1

+5V _CHG USB

2.0A

1

+

+

C303

C303

2

150U_B2_6.3V-M~D

150U_B2_6.3V-M~D

1

C265

C265

2

.1U_0402_16V7K~D

.1U_0402_16V7K~D

11
12
13
14

close to JUSB2

+5V _USB _P 0

10

GND

11

GND

12

GND

13

GND

+5V _USB _P 0

8
7
6

USB2 0_ N0_ CONN

5

USB2 0_ P0_ CONN

Tit le

Tit le

Tit le

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Date : She et of

Date : She et of

Date : She et of

2.0A

1

+

+

C110 9

C110 9

2

150U_B2_6.3V-M~D

150U_B2_6.3V-M~D

.1U_0402_16V7K~D

.1U_0402_16V7K~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P30-USB 3.0 IO CONN

P30-USB 3.0 IO CONN

P30-USB 3.0 IO CONN

LA-8821P

LA-8821P

LA-8821P

E

1

C111 0

C111 0

2

30 54Fri da y, S epte mb er 2 8, 201 2

30 54Fri da y, S epte mb er 2 8, 201 2

30 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

A

R906

R906
100K_0402_5%~D

BATT_LED#_LV1[35]

100K_0402_5%~D

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

1 1

B

+3VALW

32

R907

R907
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

61

2

Q316A

Q316A

3

5

4

BATT_LED_LV1

Q316B

Q316B
DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

C

D

SW1

SW1
SKRELGE010_2P

1

C1122

C1122
.1U_0402_16V7K~D

.1U_0402_16V7K~D

2

SKRELGE010_2P

BATBTN#[35]

E

21

F

G

H

+3VALW

32

R909

R908

R908
100K_0402_5%~D

100K_0402_5%~D

2 2

3 3

4 4

BATT_LED#_LV2[35]

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

R914

R914
100K_0402_5%~D

100K_0402_5%~D

BATT_LED#_LV3[35]

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

32

R917

R917
100K_0402_5%~D

100K_0402_5%~D

BATT_LED#_LV4[35]

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

R919

R919
100K_0402_5%~D

100K_0402_5%~D

BATT_LED#_LV5[35]

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

A

R909
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

61

2

Q317A

Q317A

32

+3VALW

R915

R915
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

61

2

Q318A

Q318A

+3VALW

R918

R918
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

61

2

Q319A

Q319A

+3VALW

32

R920

R920
100K_0402_5%~D

100K_0402_5%~D

1 2

1 2

61

2

Q320A

Q320A

B

3

5

4

3

5

4

3

5

4

3

5

4

BATT_LED_LV2

Q317B

Q317B
DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

BATT_LED_LV3

Q318B

Q318B
DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

BATT_LED_LV4

Q319B

Q319B
DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

BATT_LED_LV5

Q320B

Q320B
DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

C

BATT_LED_LV1

BATT_LED_LV2

BATT_LED_LV3

BATT_LED_LV4

BATT_LED_LV5

R910 820_0402_5%~DR910 820_0402_5%~D

R911 820_0402_5%~DR911 820_0402_5%~D

R912 820_0402_5%~DR912 820_0402_5%~D

R913 820_0402_5%~DR913 820_0402_5%~D

R916 820_0402_5%~DR916 820_0402_5%~D

D

LED1

LED1

12

27-11-T1D-CP1Q1RY-3C_WH ITE~D

27-11-T1D-CP1Q1RY-3C_WH ITE~D

LED2

LED2

12

27-11-T1D-CP1Q1RY-3C_WH ITE~D

27-11-T1D-CP1Q1RY-3C_WH ITE~D

LED3

LED3

12

27-11-T1D-CP1Q1RY-3C_WH ITE~D

27-11-T1D-CP1Q1RY-3C_WH ITE~D

LED4

LED4

12

27-11-T1D-CP1Q1RY-3C_WH ITE~D

27-11-T1D-CP1Q1RY-3C_WH ITE~D

LED5

LED5

12

27-11-T1D-CP1Q1RY-3C_WH ITE~D

27-11-T1D-CP1Q1RY-3C_WH ITE~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

+5VALW

21

21

21

21

21

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

E

Deciphered Date

Deciphered Date

Deciphered Date

Comp al Electronics , Inc.

Comp al Electronics , Inc.

Comp al Electronics , Inc.

Title

Title

Title

P31 -BAT LED

P31 -BAT LED

P31 -BAT LED

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

LA-8 821P

LA-8 821P

LA-8 821P

Date: Sheet of

Date: Sheet of

F

Date: Sheet of

G

31 54Friday, Septem ber 28, 2012

31 54Friday, Septem ber 28, 2012

31 54Friday, Septem ber 28, 2012

H

1.0

1.0

1.0

A

+5VALW to +5VS +3VALW to +3VS

PCH_ ENV DD[18]

EC_E NVD D[3 5]

1 1

2 2

WLAN _EN #[3 5]

2

3

D93

D93

BAT 54 CW-7-F _SO T3 23-3 ~D

BAT 54 CW-7-F _SO T3 23-3 ~D

SUSP #[32,3 5,4 0,41 ,42 ]

SHORT

1 2

R103 1 0_04 02_ 5% ~D

R103 1 0_04 02_ 5% ~D

@

@

1

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

SUSP #

ENVD D

+3V ALW

2

G

G

ENVD D

R102 6

R102 6

12

R103 0

R103 0
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

13

D

D

S

S

12

+5V ALW

+5V ALW

+3V ALW

WLAN _EN

Q33 3

Q33 3
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

+5V ALW

1

2

U655

U655

1

+3V ALW

2

+5V ALW

+3V ALW

3

4

5

6
7

WLAN _EN

SUSP #

12

R102 7

R102 7

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

3 3

14

VOUT1

VIN1

13

VOUT1

VIN1

12

CT1

ON1

11

GND

VBIAS

10

ON2

CT2

9

VIN2

VOUT2

8

VIN2

VOUT2

15

GPAD

TPS 22 966 DPUR _SO N14 _2X 3~ D

TPS 22 966 DPUR _SO N14 _2X 3~ D

U654

U654

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS 22 966 DPUR _SO N14 _2X 3~ D

TPS 22 966 DPUR _SO N14 _2X 3~ D

1/5, change to TI s olution

C116 7

C116 7

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

+3V S_WL AN

1 2

C116 9 47 0P _04 02 _50 V7K ~DC116 9 47 0P_ 040 2_ 50V 7K~ D

1 2

C117 0 47 0P _04 02 _50 V7K ~DC117 0 47 0P_ 040 2_ 50V 7K~ D

+5V ALW

1

C116 1

C116 1

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

14

VOUT1

13

VOUT1

12

C116 3 47 0P _04 02 _50 V7K ~DC116 3 47 0P_ 040 2_ 50V 7K~ D

CT1

11

GND

10

C116 4 1000 P_0 40 2_5 0V7 K~DC1 164 100 0P _04 02_ 50 V7K ~D

CT2

9

VOUT2

8

VOUT2

15

GPAD

B

12/20, Due to NVDC 2Cell ba ttery pack desi ng
change to SOC Load wi tch design

+LCD VDD

+5V S

1

C116 2

C116 2
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

+LCD VDD

1

C116 5

C116 5
1U_0 60 3_1 0V6 K~ D

1U_0 60 3_1 0V6 K~ D

2

+5V S

1 2

1 2

C

D

+3VALW to +3V_PCH, +5VALW to +5V_PCH

+5V ALW

12

R287

R287
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

12

PCH_ PWR_ EN#

R894

R894

13

D

D

10K _04 02 _5% ~D

10K _04 02 _5% ~D

PM_ SL P_S US#[ 18,3 5]

R290

R290
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

2

G

Q32

G

Q32
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

12

PM_SLP_SUS# : Deep Sx Indic ation
When ass erted(l ow), this s ignal indica tes PCH
is i n DeepSx state wherei nternal Sus power is
shut off for enhanc ed power savi ng.
When deasserted (hi gh), this s ignal indica tes exit from
DeepSx s tate and Sus po werc an be appl ied to PCH

QH7

QH7

AO3 419 L_ SOT 23 -3

AO3 419 L_ SOT 23 -3

D

S

D

S

13

G

G

2

1

CH11 6

CH11 6
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

12

RH29 5

RH29 5
20K _04 02 _5% ~D

20K _04 02 _5% ~D

+3V ALW

P-MOSP-MOS

Q41

Q41

AO3 419 L_ SOT 23 -3

AO3 419 L_ SOT 23 -3

S

S

G

G

E

D

D

13

2

Vgs(th) max is 2.0V

1

C355

@ C35 5

@

0.1U _06 03 _50 V7K ~D

0.1U _06 03 _50 V7K ~D

2

+3V _PCH+5V _PCH+5VAL W

1

2

40mil

C352

C352
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

+1.35V to +1.35V_CPU_VDDQ

NVDC Design, 6V ~ 8.4V

12

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

RC10 2

RC10 2
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

+3V S_WL AN

1

C116 8

C116 8
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+3V S

+3V S

1

C117 1

C117 1
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

SUSP #[32,3 5,4 0,41 ,42 ]

CPU1 .5V _S3 _GA TE[3 5,4 2,6, 9]

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

RC10 4

@ RC10 4

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

SHORT

1 2

RC10 7

@ RC10 7

@

0_0 402 _5 %~D

0_0 402 _5 %~D

17

QC4A

QC4A

1

@ CC21 7

@

2

RUN_O N_C PU1. 5VS 3#

61

2

CC21 7

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

+1.3 5V +1.3 5V_ CPU _VD DQ

QC3

QC3

+VS BP+3 VAL W

AO4 728 L_ SO8 ~D

AO4 728 L_ SO8 ~D

8

1

7

12

RC10 1

RC10 1

34

QC4B

QC4B

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

5

RUN_O N_C PU1. 5VS 3# [3 2,6 ]

RUN_O N_C PU1. 5VS 3

12

@ RC10 5

@

330 K_0 40 2_1 %

330 K_0 40 2_1 %

2

6

3

5

4

Vgs(th) max is 2.2V

1

RC10 5

CC13 9

CC13 9

2

0.1U _06 03 _50 V7K ~D

0.1U _06 03 _50 V7K ~D

1

CC13 8

CC13 8
10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

12

RC10 3

RC10 3
20K _04 02 _5% ~D

20K _04 02 _5% ~D

SYS ON#

@ Q35 A

@

+1.3 5V

12

R289

@ R28 9

@

470 _04 02 _5%

470 _04 02 _5%

+1.35V_D

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

61

RUN_O N_C PU1. 5VS 3#[32,6 ]

Q35 A

2

Discharge

+3V ALW

12

R102 4

@ R10 24

@

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

SUSP #

4 4

A

SUSP

13

D

D

2

Q33 0

@

Q33 0

@

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

B

+1.5 VS

12

@ R29 6

@

+1.5VS_D

Q34

@

Q34

@

13

D

D

2

SUSP

G

G

S

S

R296
470 _04 02 _5%

470 _04 02 _5%

DII-DMN 65D8LW-7~D

DII-DMN 65D8LW-7~D

+VCC P

12

R297

@ R29 7

@

470 _04 02 _5%

470 _04 02 _5%

+VCCP_D

DII-DMN 65D8LW-7~D

DII-DMN 65D8LW-7~D

Q4

@

Q4

@

13

D

D

2

G

G

S

S

C

+3V _PCH

12

R298

@ R29 8

@

470 _04 02 _5%

470 _04 02 _5%

+3V_D

DII-DMN 65D8LW-7~D

DII-DMN 65D8LW-7~D

Q5

@

Q5

@

13

D

D

2

PCH_ PWR_ EN#SU SP

G

G

S

S

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

SYS ON[ 35,4 2]

+5V ALW

12

R295

@ R29 5

@

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

3

5

Q35 B

@ Q35 B

@

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.3 5V_ CPU _VD DQ

DII-DMN 65D8LW-7~D

DII-DMN 65D8LW-7~D

D

D

Q37

Q37

S

S

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P32-DC/DC Interface

P32-DC/DC Interface

P32-DC/DC Interface

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

12

R292

R292
220 _04 02 _5%

220 _04 02 _5%

+1.35V_CPU_VDDQ_CH G

13

+0.6 75V S

12

R293

R293
22_ 040 2_ 5%~ D

22_ 040 2_ 5%~ D

+DDR_CHG

DII-DMN 65D8LW-7~D

DII-DMN 65D8LW-7~D

13

D

D

Q38

Q38

2

2

G

G

G

G

S

S

32 54Fri da y, S epte mb er 2 8, 201 2

32 54Fri da y, S epte mb er 2 8, 201 2

32 54Fri da y, S epte mb er 2 8, 201 2

E

1.0

1.0

1.0

A

FD2

FD2

FD3

FD1

FD1

@

@

1

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

1 1

FD3

@

@

@

@

1

1

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FD5

FD5

FD4

FD4

@

@

@

@

1

1

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

FIDUCI AL_ C40 M8 0

PCB Screw Hole

H8

H8

H3

H3

H1

H1

H_2P 3

H_2P 3

H_4P 0

H_4P 0

H_2P 3

H_2P 3

@

@

H5

H5

H_2P 3

H_2P 3

@

@

2 2

@

@

@

@

1

1

1

H6

H6

H7

H7

H_2P 3

H_2P 3

H_2P 3

H_2P 3

@

@

@

@

1

1

PCB Screw Hole for CPU (NUT)

CONN@

CONN@

CONN@

CONN@

1

H9

H9

H10

H10

H_3P 2

H_3P 2

H_3P 2

H_3P 2

CONN@

CONN@

1

1

H11

H11

H12

H12

H_3P 2

H_3P 2

H_3P 2

H_3P 2

CONN@

CONN@

1

1

H_4P 5N

H_4P 5N

CONN@

CONN@

H13

H13

1

PCB Screw Hole for K/B (NUT)

H14

H14

NUT

H_3P 2

H_3P 2

CONN@

CONN@

1

FD6

FD6

1

H_2P 0X 2P5 N

H_2P 0X 2P5 N

B

@

@

KSO 13

C117 4 10 0P _04 02 _50 V8J ~D@C11 74 1 00P _0 402 _5 0V8 J~D@

KSO 15

C117 5 10 0P _04 02 _50 V8J ~D@C11 75 1 00P _0 402 _5 0V8 J~D@

KSO 16

C117 6 10 0P _04 02 _50 V8J ~D@C11 76 1 00P _0 402 _5 0V8 J~D@

KSO 12

C117 7 10 0P _04 02 _50 V8J ~D@C11 77 1 00P _0 402 _5 0V8 J~D@

KSO 10

C117 8 10 0P _04 02 _50 V8J ~D@C11 78 1 00P _0 402 _5 0V8 J~D@

KSO 11

C117 9 10 0P _04 02 _50 V8J ~D@C11 79 1 00P _0 402 _5 0V8 J~D@

KSO 9

C118 0 10 0P _04 02 _50 V8J ~D@C11 80 1 00P _0 402 _5 0V8 J~D@

KSO 14

C118 1 10 0P _04 02 _50 V8J ~D@C11 81 1 00P _0 402 _5 0V8 J~D@

KSO 6

C118 2 10 0P _04 02 _50 V8J ~D@C11 82 1 00P _0 402 _5 0V8 J~D@

KSO 7

C118 3 10 0P _04 02 _50 V8J ~D@C11 83 1 00P _0 402 _5 0V8 J~D@

KSO 4

C118 4 10 0P _04 02 _50 V8J ~D@C11 84 1 00P _0 402 _5 0V8 J~D@

KSO 5

C118 5 10 0P _04 02 _50 V8J ~D@C11 85 1 00P _0 402 _5 0V8 J~D@

KSI2

C118 6 10 0P _04 02 _50 V8J ~D@C11 86 1 00P _0 402 _5 0V8 J~D@

KSI4

C118 7 10 0P _04 02 _50 V8J ~D@C11 87 1 00P _0 402 _5 0V8 J~D@

KSI6

C118 8 10 0P _04 02 _50 V8J ~D@C11 88 1 00P _0 402 _5 0V8 J~D@

KSI7

C118 9 10 0P _04 02 _50 V8J ~D@C11 89 1 00P _0 402 _5 0V8 J~D@

KSI0

C119 0 10 0P _04 02 _50 V8J ~D@C11 90 1 00P _0 402 _5 0V8 J~D@

KSI3

C119 1 10 0P _04 02 _50 V8J ~D@C11 91 1 00P _0 402 _5 0V8 J~D@

KSI1

C119 2 10 0P _04 02 _50 V8J ~D@C11 92 1 00P _0 402 _5 0V8 J~D@

KSI5

C119 3 10 0P _04 02 _50 V8J ~D@C11 93 1 00P _0 402 _5 0V8 J~D@

KSO 2

C119 4 10 0P _04 02 _50 V8J ~D@C11 94 1 00P _0 402 _5 0V8 J~D@

KSO 1

C119 5 10 0P _04 02 _50 V8J ~D@C11 95 1 00P _0 402 _5 0V8 J~D@

KSO 3

C119 6 10 0P _04 02 _50 V8J ~D@C11 96 1 00P _0 402 _5 0V8 J~D@

KSO 8

C119 7 10 0P _04 02 _50 V8J ~D@C11 97 1 00P _0 402 _5 0V8 J~D@

KSO 0

C107 8 10 0P _04 02 _50 V8J ~D@C10 78 1 00P _0 402 _5 0V8 J~D@

H_2P 0N

H_2P 0N

H16

H16

@

@

1

H17

H17

@

@

1

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2

C

CAPS _L ED#[35]

D

KSI[ 0..7 ]

KSI[ 0..7 ] [35]

KSO [0.. 16]

KSO [0.. 16] [3 5]

INT_KBD Conn.

+3V S + 5VS

R989

R989

G

G

2

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

13

D

S

D

S

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

Q32 6

Q32 6

E

40

8/27,Modify JKB1 connector mfr. P/N from 50699-03041-P01
to 50699-03001-P01 (remove mayla only)

JKB1

JKB1

1 : Diagnotisc

30 : Diagnotisc

C116 0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

ACES _5 069 9-03 00 1-P0 1

ACES _5 069 9-03 00 1-P0 1

CONN@

CONN@
DC01 111 22 70

DC01 111 22 70

SP01001LM00

1 2

R943

R943
820 _04 02 _5% ~D

820 _04 02 _5% ~D

31

GND

32

GND

CAPS _L ED

KB_ DET #[17]

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO 5
KSO 4
KSO 7
KSO 6
KSO 8
KSO 3
KSO 1
KSO 2
KSO 0
KSO 12
KSO 16
KSO 15
KSO 13
KSO 14
KSO 9
KSO 11
KSO 10
CAPS _L ED

Q32 9

Q32 9

+5V S

AO3 419 L_ SOT 23 -3

AO3 419 L_ SOT 23 -3

D

S

D

S

13

G

G

1 2

2

1

@ C11 60

@

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

EMI Shielding

H18

H18

EMI _Sp rin g

EMI _Sp rin g

CONN@

3 3

CONN@

RTC Battery

+3VLP

W=20mils W=20mil s

4 4

W=20mils

+RTCBATT

3

1

1

2

A

1

1

RH25 9

RH25 9
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

1 2

2

DH4

DH4
BAT 54 CW-7-F _SO T3 23-3 ~D

BAT 54 CW-7-F _SO T3 23-3 ~D

CH95

CH95
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

H19

H19

EMI _Sp rin g

EMI _Sp rin g

CONN@

CONN@

H20

H20

1

1

EMI _Sp rin g

EMI _Sp rin g

CONN@

CONN@

39

Modify JRTC1 P/N from SP020009Z0L

to SP02000UB00

+RTCBATT

+RTCVCC

1

1

JRTC 1

JRTC 1

1

1

2

2

3

G1

4

G2

ACES _5 027 1-00 20 1-00 1

ACES _5 027 1-00 20 1-00 1

CONN@

CONN@
SP0 200 0UB 00

SP0 200 0UB 00

H21

H21

EMI _Sp rin g

EMI _Sp rin g

CONN@

CONN@

1

1

13

D

20mil

F1

F1

0.75 A_ 24V _18 12 L07 5-2 4DR~ OK

0.75 A_ 24V _18 12 L07 5-2 4DR~ OK

1

C115 3

C115 3
1U_0 60 3_1 0V6 K~ D

1U_0 60 3_1 0V6 K~ D

2

B

+5V S_K BL+5V S

12

1

C105 9

C105 9

10U_ 06 03_ 6.3 V6M ~D

10U_ 06 03_ 6.3 V6M ~D

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

KB_ LED _PW M[35 ]

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

D

2

G

G

S

S

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

KB_ BL_ DET[20]

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

Q31 1

Q31 1
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

D

KB_ LED _PW M#

1 2

R944 47K _04 02 _5% ~DR9 44 4 7K _04 02 _5% ~D

+5V S_K BL

R945

R945

1 2

JBL1

JBL1

1

1

2

LED Maximum Current is 300mA

2

3

3

4

4

5

GND

6

GND

HAM BURG _A 810 420 -SB HR22

HAM BURG _A 810 420 -SB HR22

CONN@

CONN@
SP0 100 1HD 00

SP0 100 1HD 00

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P33-SCREWH/KB/RTC

P33-SCREWH/KB/RTC

P33-SCREWH/KB/RTC

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

33 54Fri da y, S epte mb er 2 8, 201 2

33 54Fri da y, S epte mb er 2 8, 201 2

33 54Fri da y, S epte mb er 2 8, 201 2

E

1.0

1.0

1.0

5

D D

4

3

2

1

FAN CONN

+3V S

R1103

R1103

1 2

1 2

R884

R884

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

SYS TE M_ FAN_ PWM[35]

C C

B B

1 2

C115 4

C115 4

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

L59 BLM 18 AG6 01S N1D _06 03 ~DL59 BLM 18 AG6 01S N1D _06 03 ~D

1 2

L60 BLM 18 AG6 01S N1D _06 03 ~DL60 BLM 18 AG6 01S N1D _06 03 ~D

12

C115 5

C115 5

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

TP_ DAT A[35]
TP_ CLK[35]

A A

12

SYS TE M_ FAN_ FB[3 5]

12

C115 6

C115 6

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

TP_ DAT A_ C
TP_ CLK _C

12

C115 7

C115 7

10P _04 02 _50 V8J ~D

10P _04 02 _50 V8J ~D

10K_0402_5%~D

SDM K03 40 L-7-F_ SO D32 3-2~ D

SDM K03 40 L-7-F_ SO D32 3-2~ D

+3V S

PCH_ SM BDA TA[11 ,13 ,17 ]
PCH_ SM BCL K[1 1,1 3,1 7]

DE2

@ DE2

@

PES D5V 0U2 BT_ SO T2 3-3~ D

PES D5V 0U2 BT_ SO T2 3-3~ D

+5V S

2

1

1 2

R886

R886

10K_0402_5%~D

10K_0402_5%~D

12

D81

D81

Touchpad CONN

1/12, modify touchpad pin define

TP_ DAT A_ C
TP_ CLK _C

2

3

2

3

1

1

C1102

C1102

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

JFAN1

JFAN1

4

6

4

G2

3

5

3

G1

2

2

1

1

CVIL U_CI 430 4M 2HR0 -NH

CVIL U_CI 430 4M 2HR0 -NH

CONN@

CONN@
SP0 200 0Y 500

SP0 200 0Y 500

JTP 1

JTP 1

1
2
3
4
5
6

TYC O_2 04 108 4-6~ D

TYC O_2 04 108 4-6~ D

CONN@

CONN@
SP0 100 0WD 0L

SP0 100 0WD 0L

SP01000WD0 L

DE1

@ DE1

@

PES D5V 0U2 BT_ SO T2 3-3~ D

PES D5V 0U2 BT_ SO T2 3-3~ D

1
2
3
4

7

5

G1

8

6

G2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P34-TP / FAN

P34-TP / FAN

P34-TP / FAN

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

34 54Fri da y, S epte mb er 2 8, 201 2

34 54Fri da y, S epte mb er 2 8, 201 2

34 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

C284

@ C28 4

@

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

CLK_ PCI _LP C[ 19]

R221 47K _04 02 _5% ~DR2 21 4 7K _04 02 _5% ~D

+3V ALW_ EC

C285 .1U_ 040 2_ 16V 7K~ DC 285 .1U_ 040 2_ 16V 7K~ D

@

@

1 2

R929 10K _04 02 _5% ~D

R929 10K _04 02 _5% ~D

1 2

R103 2 10K_ 04 02_ 5%~ D

R103 2 10K_ 04 02_ 5%~ D

@

@

+3V S

R244 4.7K _0 402 _5 %~DR244 4 .7K _0 402 _5% ~D

C C

R247 4.7K _0 402 _5 %~DR247 4 .7K _0 402 _5% ~D

+3V ALW_ EC

R229 4.7K _0 402 _5 %~DR229 4 .7K _0 402 _5% ~D

R230 4.7K _0 402 _5 %~DR230 4 .7K _0 402 _5% ~D

1 2

R604 10K _04 02 _5% ~D@ R60 4 10 K_0 40 2_5 %~D@

R954 10K _04 02 _5% ~DR9 54 1 0K _04 02 _5% ~D

B B

12

12

12

12

12

PLT _RS T#

KSO 3

PCH_ SM LCL K

PCH_ SM LDA TA

EC_S MB _CK 1

EC_S MB _DA 1

WAKE _P CH#

PU 10K to + 3V_PCH on P CH side

VOL UME _DO WN_S W#

AUD_MUTE# : Internal PU on Code c Chip (+3VS )

Deep S3 support

Default (No Function)

+3V ALW

@

@

SHORT

1 2

R216

R216

+3V LP

0_0 603 _5 %~D

0_0 603 _5 %~D

1 2

R811

@ R81 1

@

0_0 603 _5 %~D

0_0 603 _5 %~D

12

12

R226 33_ 040 2_ 5%~ D@ R2 26 3 3_0 40 2_5 %~D@

12

12

KSI[ 0..7 ][3 3]

KSO [0.. 16]

KSO [0.. 16][33]

Default (No Function)

PCH_ SUS WARN#[ 18]

Deep S3 Support

EC_S MB _CK 1[ 37,3 8]
EC_S MB _DA 1[ 37,3 8]
PCH_ SM LCL K[1 7,2 4]
PCH_ SM LDA TA[17,2 4]

PM_ SL P_S 3#[18]
PM_ SL P_S 5#[18]

EC_S MI #[20 ]
PS_ ID[37]

EC_W LAN _WAK E#[2 8]

EC_I NV_ PWM[24]
SYS TE M_ FAN_ FB[34]
WAKE _P CH#[18]
EC_T X[28 ]
EC_R X[28]
AUD_ MUT E#[25 ]
SUSA CK#[18]
USB_ PWR _EN#[3 0]

VOL UME _DO WN_S W#[25 ]

SUSC LK_ R[18]

H_PROCHOT# Control citcuits need place close to CPU and VR

R265

R265
0_0 402 _5 %~D

0_0 402 _5 %~D

@

@

SHORT

1 2

1

C656

C656
47P _04 02 _50 V8J ~D

47P _04 02 _50 V8J ~D

2

5

+3V S

U635

U635

5

SN74 LV C1G 06DC KR_ SC7 0-5

SN74 LV C1G 06DC KR_ SC7 0-5

P

Y4A

G3NC

1

1

C655

C655
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

2

H_PR OCHO T# _EC

R608

R608
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

VR_H OT #[ 44]

A A

18

H_PR OCHO T#[38 ,6]

USBC HG_ DET #[30]

KSI[ 0..7 ]

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

2

GAT EA 20[20]
KB_ RST #[20]
SERI RQ[16,2 7]
LPC_ FRA ME #[16,2 7,2 8]
LPC_ AD3[16, 27, 28]
LPC_ AD2[16, 27, 28]
LPC_ AD1[16, 27, 28]
LPC_ AD0[16, 27, 28]

PLT _RS T#[ 19, 27,2 8,6 ]

EC_S CI#[20 ]
BAT T_ LE D#_L V5[31 ]

R249 0_0 402 _5 %~D@R 249 0_0 402 _5% ~D@
R250 0_0 402 _5 %~D@R 250 0_0 402 _5% ~D@

@ R25 3

@

C277

C277

R253
0_0 402 _5 %~D

0_0 402 _5 %~D

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

2

SHORT

1 2
1 2

1 2

SHORT

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

4

.1U_0402_16V7K~D

.1U_0402_16V7K~D

C276

C276

1

2

EC_S MB _CK 1
EC_S MB _DA 1
PCH_ SM LCL K
PCH_ SM LDA TA

PBT N_S W#

USBC HG_ DET _EC #

WAKE _P CH#

VOL UME _DO WN_S W#
EC_C RY2

R607

R607

1 2

D83

D83
BAT 54 CW-7-F _SO T3 23-3 ~D

BAT 54 CW-7-F _SO T3 23-3 ~D

1

4

C278

C278

PLT _RS T#
EC_R ST #

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO 0
KSO 1
KSO 2
KSO 3
KSO 4
KSO 5
KSO 6
KSO 7
KSO 8
KSO 9
KSO 10
KSO 11
KSO 12
KSO 13
KSO 14
KSO 15
KSO 16

1

2

C279

.1U_0402_16V7K~D

C279

.1U_0402_16V7K~D

1

2

C654

C654
20P _04 02 _50 V8J ~D

20P _04 02 _50 V8J ~D

3

+3V LP

2

12

USBC HG_ DET _PW R_E N#

1 2

+3V ALW_ EC

C280

1000P_0402_50V7K~D

C280

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2

2

1

1

U34

U34

M2

GA20/GPIO00

L2

KBRST#/GPIO01

M3

SERIRQ#

K4

LFRAME#

N3

LAD3

M4

LAD2

K5

LAD1

N4

LPC & MISC

LPC & MISC

LAD0

N5

PCICLK

M5

PCIRST#/GPIO05

K13

ECRST#

N6

SCI#/GPIO0E

M6

CLKRUN#/GPIO1D

D9

KSI0/GPIO30

E12

KSI1/GPIO31

E13

KSI2/GPIO32

D12

KSI3/GPIO33

D13

KSI4/GPIO34

C12

KSI5/GPIO35

C13

KSI6/GPIO36

D10

KSI7/GPIO37

J13

KSO0/GPIO20

J12

KSO1/GPIO21

H12

KSO2/GPIO22

H13

KSO3/GPIO23

H10

KSO4/GPIO24

H9

KSO5/GPIO25

G9

KSO6/GPIO26

G10

KSO7/GPIO27

G13

KSO8/GPIO28

G12

KSO9/GPIO29

F13

KSO10/GPIO2A

F12

KSO11/GPIO2B

F10

KSO12/GPIO2C

F9

KSO13/GPIO2D

E10

KSO14/GPIO2E

E9

KSO15/GPIO2F

E8

KSO16/GPIO48

D8

KSO17/GPIO49

A8

SCL0/GPIO44

A7

SDA0/GPIO45

B8

SCL1/GPIO46

A6

SDA1/GPIO47

J5

PM_SLP_S3#/GPIO04

N9

PM_SLP_S5#/GPIO07

L13

EC_SMI#/GPIO08

K6

LID_SW#/GPIO0A

N7

SUSP#/GPIO0B

M7

PBTN_OUT#/GPIO0C

N8

EC_PME#/GPIO0D

K8

EC_THERM#/GPIO11

M11

FAN_SPEED1/FANFB0/GPIO14

N11

FANFB1/GPIO15

K10

EC_TX/GPIO16

K9

EC_RX/GPIO17

N12

ON_OFF/GPIO18

M13

PWR_LED#/GPIO19

L12

NUMLED#/GPIO1A

J1

GPIO5D

XCLKI

K1

GPIO5E

XCLKO

KB9 012 BF-A 3_L FBG A1 28

KB9 012 BF-A 3_L FBG A1 28

R935 10K_ 04 02_ 5% ~DR 935 10K_ 04 02_ 5%~ D

1 2

R939

R939
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

R941

@ R94 1

@

150 K_0 40 2_1 %~D

150 K_0 40 2_1 %~D

+3V ALW_ EC

C281

C281

Int. K/B

Int. K/B
Matrix

Matrix

L43

L43
FBM A-L1 1-1 608 08-8 00 LM T_0 60 3

FBM A-L1 1-1 608 08-8 00 LM T_0 60 3

1 2

J7

K12

M12

K7

J4

J6

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

PWM Output

AD Input

AD Input

DA Output

DA Output

PS2 Interface

PS2 Interface

SPI Device Interface

SPI Device Interface

SPI Flash ROM

SPI Flash ROM

GPIO

GPIO

SM Bus

SM Bus

GPO

GPO

GPIO

GPIO

GPI

GPI

GND

GND

GND

GND

GND

J8

J9

G2

J10

N13

+3V ALW_ EC

USBC HG_ DET _EC #

+3V LP

R938

R938
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

USBC HG_ DET _D [3 9]

13

D

D

2

Q32 1

Q32 1

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

3

+EC_ VCCA

C282 .1 U_0 402 _1 6V7 K~DC282 .1U_ 040 2_ 16V 7K~ D

R921

@ R92 1

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

SHORT

Pin J6 i s VCC_0 :
Power supply fo r 51ON power m anagem ent

B11

AVCC

INVT_PWM/PWM0/GPIO0F

BEEP#/PWM1/GPIO10

FANPWM0/GPIO12

ACOFF/FANPWM1/GPIO13

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

ADP_I/AD2/GPI3A

AD3/GPI3B

AD4/GPI42

SELIO2#/AD5/GPI43

DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D

IREF/DA2/GPO3E

DA3/GPO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B

PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXIOA00
SDICLK/GPXIOA01

SDIDO/GPXIOA02

SDIDI/GPXIOD00

MOSI

GPIO5C
GPIO5B

MISO

SPICLK/GPIO58

GPIO5A

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04

EC_ON/GPXIOA05

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

BKOFF#/GPXIOA08

WL_OFF#/GPXIOA09

GPXIOA10
GPXIOA11

PM_SLP_S4#/GPXIOD01

ENBKL/GPXIOD02

GPXIOD03
GPXIOD04
GPXIOD05
GPXIOD06
GPXIOD07

V18R

AGND

20mil

A11

L44

L44

ECAG ND

FBM A-L1 1-1 608 08-8 00 LM T_0 60 3

FBM A-L1 1-1 608 08-8 00 LM T_0 60 3

3

2

1 2

+3V LP

ECAG ND

8/20, Modify board ID for X- build

M9
M8
M10
N10

B13
A13
B12
A12

AD_B ID0

E7
D7

AOA C_T HER MAL

B10
A9

VOL UME _UP _SW #

A10
B9

D6

EAP D_R#

E6
E5
D5
A5

TP_ CLK

B5

TP_ DAT A

B1
A1

DRAM RST _C NTRL _E C

C1
C2

VCIN0 _P H_R

J2
K2
M1

WLAN _EN #

N2

TAB LE T_ MO DE

B6
B7
B4

BAT BT N#

A4
B3

CAPS _L ED#

A3
A2
B2

SYS ON

H5
N1

D4
D1
D2

VCIN1 _P H_R

E2

H_PR OCHO T# _EC

E4

VCOU T0 _PH #

E1
F4
F2

Win8 _B TN_ SW#

F1

HWPG

F5

ACIN

G1

EC_O N

G5

EC_O N_C TRL #

H1

LID_ SW_ IN#

G4
H4
H2

EC_P ECI

L1

+V1 8R

12

Only for Debug using

@

@

SW2

SW2

321

4

SKQ GAB E0 10_ 4P~ D

SKQ GAB E0 10_ 4P~ D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

KB_ LED _PW M [33 ]
BEE P# [ 25]
VGA TE [1 8,4 4]
SYS TE M_ FAN_ PWM [3 4]

BMO N [3 8]
ADP_ I [ 37,3 8]

PWRS HARE _EN _EC # [30 ]

BAT T_ LE D#_L V1 [3 1]
VOL UME _UP _SW # [ 25]
EC_E NVD D [ 32]
BAT T_ LE D#_L V2 [3 1]

SHORT

12

R228 0_0 402 _5 %~D@R 228 0_0 402 _5% ~D@

PWRS HARE _OE # [3 0]
AC_P RES ENT [18 ]
PCH_ PWRO K [1 8]
TP_ CLK [34]
TP_ DAT A [34 ]

EN_I NVP WR [2 4]
DRAM RST _C NTRL _E C [6 ]
HDA_ SDO [16 ]

R925 0_0 402 _5 %~D@R 925 0_0 402 _5% ~D@

SHORT

BAT T_ LE D#_L V4 [3 1]
BAT T_ LE D#_L V3 [3 1]
WLAN _EN # [3 2]
TAB LE T_ MO DE [24 ]

ENBK L [18]
PM_ SL P_S US# [18 ,32 ]

BAT T_ CHG _LE D# [25 ]
CAPS _L ED# [ 33]
LCD_ TE ST [ 24]
BAT T_ LO W_LE D# [25 ]
SYS ON [3 2,4 2]
VR_O N [44]
PM_ SL P_S 4# [1 8]

PCH_ RSM RST # [18]
EC_L ID_ OUT # [1 9]

R926 0_0 402 _5 %~D@R 926 0_0 402 _5% ~D@

SHORT

VCOU T0 _PH # [39 ]
BKO FF# [24 ]
CPU1 .5V _S3 _GA TE [32 ,42 ,6,9 ]
Win8 _B TN_ SW# [24]

ACIN [ 38]
EC_O N [39]

LID_ SW_ IN# [2 5]
SUSP # [32,4 0,4 1,4 2]
PBT N_O UT # [1 8]

1

C293

C293

4.7U _06 03 _6.3 V6 K~D

4.7U _06 03 _6.3 V6 K~D

2

PBT N_S W#

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

C286 100 P_ 040 2_5 0V 8J~DC286 1 00P _0 402 _50 V8 J~D

EAP D#

12

12

AC_IN
ALW_PWR_EN
ON/OFFBTN#

1 2

R240 43 _0 402 _5 %~DR2 40 43 _04 02 _5% ~D

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

ECAG ND

EC_B AT T_ PRS [37 ,38 ]

EAP D# [25]

Default (No Function)

VCIN0 _P H [3 7]

Deep S3 Support
(PM_SLP_SUS#, Input)

Default (PCH_PWR_EN, Output)

VCIN1 _P H [3 7]

VCC_0 power pl ane

H_PE CI [2 0,6 ]

+3V LP

BAT BT N#[31]

+3V LP

PBT N_S W#[2 5]

Deciphered Date

Deciphered Date

Deciphered Date

2

PBT N_S W#

Board ID

+3V ALW_ EC

Ra

1 2

TP_ CLK

TP_ DAT A

VOL UME _UP _SW #

EAP D_R#

DRAM RST _C NTRL _E C

WLAN _EN #

CAPS _L ED#

VCOU T0 _PH #

Win8 _B TN_ SW#

LID_ SW_ IN#

TAB LE T_ MO DE

SYS ON

ACIN

EC_O N

Rb

1 2

Analog Board ID definition,
Please see page 4.

R223 4.7K _0 402 _5 %~DR223 4 .7K _0 402 _5% ~D

R224 4.7K _0 402 _5 %~DR224 4 .7K _0 402 _5% ~D

R980 100 K_0 40 2_5 %~DR9 80 100K _0 402 _5% ~D

R923 100 K_0 40 2_5 %~DR9 23 100K _0 402 _5% ~D

R924 100 K_0 40 2_5 %~D@ R92 4 10 0K_ 04 02_ 5%~ D@

C111 6 100P _0 402 _5 0V8 J~DC111 6 100P _0 402 _5 0V8 J~D

C111 7 .1U_0 40 2_1 6V7 K~ DC1 11 7 .1U_0 402 _1 6V7 K~D

1

AOAC Thermal

100 K_0 40 2_1 %_T SM 0B 10 4F42 51 RZ

Acordding M13_EE_Implementation_Requirements
Thermistor need place a round CPU

100 K_0 40 2_1 %_T SM 0B 10 4F42 51 RZ

HW PWR GOOD

12

SA_ PGO OD[43]

+1.5 V_P WRO K[42]

+1.8 VS_ PWR OK[40 ]

+1.5 VS_ PWR OK[40 ]

R937 10K_ 04 02_ 5% ~DR 937 10K_ 04 02_ 5%~ D

1 2

R940 10K_ 04 02_ 5% ~DR 940 10K_ 04 02_ 5%~ D

1 2

R931 0_0 402 _5 %~D@R 931 0_0 402 _5% ~D@

SHORT

12

R933 0_0 402 _5 %~D@R 933 0_0 402 _5% ~D@

SHORT

12

R934 0_0 402 _5 %~D@R 934 0_0 402 _5% ~D@

SHORT

12

R982 0_0 402 _5 %~D@R 982 0_0 402 _5% ~D@

SHORT

D84

D84
DB2J 314 00 L_S OD3 23-2

DB2J 314 00 L_S OD3 23-2

21

D85

D85
DB2J 314 00 L_S OD3 23-2

DB2J 314 00 L_S OD3 23-2

21

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P35-EC ENE-KB9012

P35-EC ENE-KB9012

P35-EC ENE-KB9012

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1

R219

R219
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

AD_B ID0

1

R225

R225

C283

C283

56K _04 02 _5% ~D

56K _04 02 _5% ~D

.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

12

12

1 2

R952 10K _04 02 _5% ~DR9 52 1 0K _04 02 _5% ~D

1 2

R241 10K _04 02 _5% ~D@ R24 1 10 K_0 40 2_5 %~D@

1 2

R987 10K _04 02 _5% ~D@ R98 7 10 K_0 40 2_5 %~D@

1 2

R102 1 100K _0 402 _5 %~DR1 021 10 0K_ 04 02_ 5%~ D

1 2

R990 100 K_0 40 2_5 %~D@ R99 0 10 0K_ 04 02_ 5%~ D@

1 2

R922 10K _04 02 _5% ~D@ R92 2 10 K_0 40 2_5 %~D@

1 2

R981 10K _04 02 _5% ~DR9 81 1 0K _04 02 _5% ~D

12

R603 10K _04 02 _5% ~DR6 03 1 0K _04 02 _5% ~D

1 2

1 2

12

12

1 2

R927

R927

13.7 K_ 040 2_ 1%~ D

13.7 K_ 040 2_ 1%~ D

AOA C_T HER MAL

R928

R928

+3V ALW_ EC

12

R930

R930
10K _04 02 _5% ~D

10K _04 02 _5% ~D

+3V LP

R936

R936
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

1 2

EC_O N_C TRL #BAT BT N#

1

C111 8

C111 8
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

35 54Fri da y, S epte mb er 2 8, 201 2

35 54Fri da y, S epte mb er 2 8, 201 2

35 54Fri da y, S epte mb er 2 8, 201 2

1

+3V ALW_ EC

+3V LP

12

12

HWPG

+3V S

1.0

1.0

1.0

5

4

3

2

1

+VCC_CORE
TDC: 23A
ISL95836HRTZ-T

+VCC_GFXCORE_AXG
TDC: 20.3A
ISL95836HRTZ-T

+VCCP: TDC:8.3A
TPS51212DSCR

+1.35V: TDC:6.6A
+0.675VS: TDC:0.7A
RT8207M

+3VALW: TDC:3.9A
+5VALW: TDC:4.4A
RT8243A

Battery
(2S3P)

B+

DC IN

D D

C C

B B

NVDC
CHARGER
ISL9519

Page 44

Page 52

+VCC_GFXCOR E_AXG

Page 52

Page 47

Page 48

Page 45

+VCC_CORE

+VCCP

+1.35V

+0.675VS

+5VALW

+3VALW

+1.5VS: TDC:0.35A
SY8033BDBC

+VCCSAP: TDC:2.8A
TPS51463

+1.8V: TDC:0.85A
SY8033BDBC

+1.5VS

Page 46

+VCCSAP

Page 49

+1.8VS

Page 46

A A

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P36-PWR-POWER BLOCK DIAGRAM

P36-PWR-POWER BLOCK DIAGRAM

P36-PWR-POWER BLOCK DIAGRAM

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Date : She et

Date : She et

Date : She et

LA-8821P

LA-8821P

LA-8821P

1

36 54Frida y, S ep tem ber 28, 20 12

36 54Frida y, S ep tem ber 28, 20 12

36 54Frida y, S ep tem ber 28, 20 12

of

of

of

1.0

1.0

1.0

A

12

PC902

PC902

1000P_0402_50V7K~D

1000P_0402_50V7K~D

PR91 7

PR91 7

100_ 0402_ 5%~D

100_ 0402_ 5%~D

1 2

3

VIN

1

PL900

JDCIN 1

JDCIN 1

1

PSID

1

2

ADPIN

2

3

3

4

DCIN_ GNDDCIN_GN D

4

5

5

6

GND1

7

GND2

ACES_50 281-0 0501 -001

ACES_50 281-0 0501 -001

CONN @

CONN @

DC01 1201 162

DC01 1201 162

1 1

SP02000H510

12

PC904

PC904

2 2

100P_0402_50V8J~D

100P_0402_50V8J~D

JBATT battery connector PH901 under CPU botten side :

3 3

SMA RT
Bat tery :

1.GN D

2.GN D

3.BA T_A LER T

4.SY S_PR ES

5.BA TT_ PRS

6.DA T_SM B

7.CL K_SM B

8.BA TT+

9.BA TT+

4 4

1

1

@

@

2

2

PL902

PL902

FBMA-L11-4 53215 -800L MA90T_181 2

FBMA-L11-4 53215 -800L MA90T_181 2

BATT+

1 2

12

PC905

PC905

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

JBATT9

JBATT9

11

GND

10

GND

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

FOX_GS730 91-10 272M-7H

FOX_GS730 91-10 272M-7H

CONN @

CONN @
DC03 1201 130

DC03 1201 130

SP020013K00

PJP205

PJP205

12

CLK_ SMB
DAT_SMB
BATT_PRS
SYS_PRS

JUMP_43X118

JUMP_43X118

BATT++

PC906

PC906

12

PC900

PC900

PL903

PL903

@

@

1 2

1000P_0402_50V7K~D

1000P_0402_50V7K~D

FBMA-L11-453215-800LMA90T_1812

FBMA-L11-453215-800LMA90T_1812

BATT++BATT+

12

PC907

PC907

100P_0402_50V8J~D

100P_0402_50V8J~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

PL900

FBMA-L11-4 53215 -800L MA90T_181 2

FBMA-L11-4 53215 -800L MA90T_181 2

1 2

12

PC901

PC901

100P_0402_50V8J~D

100P_0402_50V8J~D

1

PD90 4

PD90 4
SM24_SO T23

SM24_SO T23

@

@

2

3

100_ 0402_ 5%~D

100_ 0402_ 5%~D

1 2

@

@

12

PR91 8

PR91 8
0_04 02_5% ~D

0_04 02_5% ~D

SHORT

4

PR91 3

PR91 3

12

1 2

2

PC903

PC903

100P_0402_50V8J~D

100P_0402_50V8J~D

PR91 5

PR91 5
100_ 0402_ 5%~D

100_ 0402_ 5%~D

PD90 5

@ PD90 5

@

SM24_SO T23

SM24_SO T23

B

EC_SMB_ CK1 [35,38 ]

EC_SMB_ DA1 [35,38 ]

PR91 6

PR91 6

10K_0 402_ 1%~D

10K_0 402_ 1%~D

1 2

EC_BATT_ PRS [35,3 8]

PL901

PL901

BLM18BD 102S N1D_0 603~D

BLM18BD 102S N1D_0 603~D

12

SM24_SO T23

SM24_SO T23

+3VALW

C

PR903

PR903

2

3

1 2

100K_0402_1%

100K_0402_1%

@

@

PD90 2

PD90 2

1

PR906

PR906

1 2

15K_0402_1%~D

15K_0402_1%~D

B+

B+ = 6V-8.4V

For Deep S3 support

+3VALW

PR91 0

PR91 0

@

@

@

@

1 2

12

PR90 5

PR90 5
10K_0 402_ 1%~D

10K_0 402_ 1%~D

12

PC911

PC911

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

4

@

@

PR91 1

PR91 1
0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

ADP_I[35,38]

PR937

PR937

13.7K_0402_1%~D

13.7K_0402_1%~D

1 2

@

@

1 2

PR93 6

PR93 6
0_04 02_5% ~D

0_04 02_5% ~D

100K_ 0402 _1%

100K_ 0402 _1%

POK[1 8,39]

VCIN1_P H[3 5] VCIN0_P H[35 ]

PQ900

PQ900
FDV301N _NL_ SOT23-3 ~D

FDV301N _NL_ SOT23-3 ~D

PSID-1

VSB_N_0 02

12

PC910

PC910

.1U_0402_16V7K~D

.1U_0402_16V7K~D

+5VALW +3VALW

PR90 0

PR90 0
0_04 02_5% ~D@

0_04 02_5% ~D@

1 2

PR90 2

PR90 2

33_0 402_5 %~D

PSID-3

S

S

G

G

2

PSID-2

C

C

PQ901

PQ901
MMST3904- 7-F_SOT32 3~D

MMST3904- 7-F_SOT32 3~D

3 1

33_0 402_5 %~D

1 2

PR90 4

PR90 4
10K_0 402_ 1%~D

10K_0 402_ 1%~D

1 2

1 3

2

B

B

D

D

E

E

26

12

12

PR908

PR908

110K_0402_1%~D

110K_0402_1%~D

PR90 9

PR90 9

22K_0 402_ 1%

22K_0 402_ 1%

1 2

VSB_N_003

13

D

D

2

PQ904

PQ904
DII-DMN6 5D8LW -7~D

DII-DMN6 5D8LW -7~D

G

G

S

S

CPU thermal protection at 85 degree C
Recovery at 50 degree C

+3VALW_EC

PR93 5

PR93 5

13.7K_ 0402 _1%~D

13.7K_ 0402 _1%~D

2

3

PD901

PD901

1

BAV99W-7-F_SOT323~D

BAV99W-7-F_SOT323~D

1/17, Modify to SC6AV99W01L

+5VALW

PJP702

@P JP702

@

PAD-OPEN 43x39

PAD-OPEN 43x39

PQ903

PQ903
TP0610 K-T1-E3 _SOT23- 3

TP0610 K-T1-E3 _SOT23- 3

PC908

PC908

2

0.22U_0603_25V7K

0.22U_0603_25V7K

VSB_N_0 01

12

13

1 2

12

PH90 1

PH90 1
100K_ 0402 _1%_ TSM0B104 F4251R Z

100K_ 0402 _1%_ TSM0B104 F4251R Z

D

PR901

PR901

1 2

2.2K_0402_5%~D

2.2K_0402_5%~D

PS_ID [35]

+VSBP

12

PC909

PC909

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

Comp al El ectron ics, I nc.

Comp al El ectron ics, I nc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

Title

Size Docum ent Nu mbe r Rev

Size Docum ent Nu mbe r Rev

Size Docum ent Nu mbe r Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Comp al El ectron ics, I nc.

P37-PW R_DCIN / BA TT CONN / OTP

P37-PW R_DCIN / BA TT CONN / OTP

P37-PW R_DCIN / BA TT CONN / OTP

LA-8821P

LA-8821P

LA-8821P

D

37 5 4Frida y, Septemb er 28, 20 12

37 5 4Frida y, Septemb er 28, 20 12

37 5 4Frida y, Septemb er 28, 20 12

1.0

1.0

1.0

5

PQ1 02

1 2

0.022U_0402_25V7K

0.022U_0402_25V7K

200K_0402_1%~D

200K_0402_1%~D

13

D

D

2

G

G

S

S

PR35

PR35
0_0 402 _5 %~D

0_0 402 _5 %~D

0.06 8U_ 04 02_ 10V 6K

0.06 8U_ 04 02_ 10V 6K

5

12

PC1918

PC1918

@

@

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

PQ1 02

FDMS 66 73B Z_P OWE R56 -8-5

FDMS 66 73B Z_P OWE R56 -8-5

1
2
3

12

PC41

PC41

@

@

PQ7

PQ7
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

VSM B

1 2

12

PC35

PC35

PD9

PD9

2

3

BAS 40C W_S OT3 23 -3

BAS 40C W_S OT3 23 -3

VIN

34

PQ1228B

PQ1228B

@

@

DMN66D0LDW -7_SOT363-6~D

DMN66D0LDW -7_SOT363-6~D

5

@

@

PC45

PC45

4

12

1500P_0402_50V7K

1500P_0402_50V7K

12

PR20

PR20

150K_0402_1%

150K_0402_1%

VIN

12

PR18

PR18

31

100K_0402_1%

100K_0402_1%

12

PC39

PC39

12

PR28

PR28

68K_0402_1%~D

68K_0402_1%~D

1 2

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1 2

PR31 1 K_ 040 2_1 %~DPR3 1 1K_ 04 02_ 1%~ D

VSM B

1 2

PR33 10K_0 40 2_1 %~D@ PR3 3 10K _04 02 _1% ~D@

VCOM P1

220 P_0 40 2_5 0V7 K

220 P_0 40 2_5 0V7 K

1

VSM B

PR966

PR966

PR965

PR965

PR964

PR964

1 2

1 2

1 2

2K_0402_1%~D

2K_0402_1%~D

1M_0402_1%~D

1M_0402_1%~D

@

@

@

@

@

@

61

PQ1 228 A

PQ1 228 A

2

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

@

@

PR968

PR968

@

@

1 2

1M_0402_1%~D

1M_0402_1%~D

AGA TE

PD10

PD10

1 2

RB751V-40_SOD323-2

RB751V-40_SOD323-2

PR24

PR24

1 2

10_ 080 5_ 1%

10_ 080 5_ 1%

PD11

PD11

GLZ5 .1B _L L34 -2

GLZ5 .1B _L L34 -2

1 2

PR34 1 K_0 40 2_1 %~DPR34 1 K_0 40 2_1 %~D

PC36

PC36

12

EC_S MB _DA 1[ 35,3 7]

EC_S MB _CK 1[ 35,3 7]

2K_0402_1%~D

2K_0402_1%~D

D D

VIN

PR16

PR16

12

PR94 2

PR94 2

3.3K _1 206 _5 %~D

3.3K _1 206 _5 %~D

@

@

@

@

13

D

D

2

PQ1 227

PQ1 227

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

PR94 3

PT2 0

PT2 0

PAD~ D

PAD~ D

PR94 3
0_0 402 _5 %~D

0_0 402 _5 %~D

@

@

1 2

PR41

PR41

@

@

1 2

0_0 402 _5 %~D

0_0 402 _5 %~D

ISL9 51 9_V DD

+3V ALW

C C

B B

Reserve Erp Lot 6 solution circuit into ST

PR96 7

PR96 7

@

A A

@

200 K_0 40 2_1 %~D

200 K_0 40 2_1 %~D

1 2

ACIN

5

PQ1 01

PQ1 01

FDMS 66 73B Z_P OWE R56 -8-5

FDMS 66 73B Z_P OWE R56 -8-5

5

4

PC23

PC23

12

DCIN

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

ADET

ICOM P

VCOM P

12

12

PR37

PR37

12

3K_ 040 2_ 1%

3K_ 040 2_ 1%

23

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

ADP_ I[35,3 7]

4

1
2
3

1

AGA TE

2

3

4

5

6

7

PC33

PC33

220 P_0 40 2_5 0V7 K

220 P_0 40 2_5 0V7 K

PR36

PR36
27K _04 02 _1%

27K _04 02 _1%

PC38

PC38

SHORT

PR95 5 0_040 2_ 5%~ D@ P R95 5 0_040 2_5 %~D@

PR95 6 0_040 2_ 5%~ D@ P R95 6 0_040 2_5 %~D@

SHORT

4

12

CSIP

PU2

PU2

28

AGATE

DCIN

ADET

VFSW

ISL9 51 9HRT Z-T _T QFN2 8_ 4X4

ISL9 51 9HRT Z-T _T QFN2 8_ 4X4

ICOMP

CELL

VCOMP

VFB

12

12

12

5

3

P1

PJP5 07

PJP5 07

@

@

JUMP _4 3X7 9

JUMP _4 3X7 9

2

112

PJP5 08

PJP5 08

@

@

JUMP _4 3X7 9

JUMP _4 3X7 9

PR95 4

@ PR9 54

@

0_0 402 _5 %~D

0_0 402 _5 %~D

SHORT

5

LGA TE

UGAT E

2

112

37

PT1PAD~D@PT1PAD~D

@

PT2 PAD~D@ PT2 PAD~D@

12

PR13

PR14

PR14

10_ 040 2_ 1%

10_ 040 2_ 1%

PC19

PC19

0.1U _04 02 _25 V6K ~D

0.1U _04 02 _25 V6K ~D

22

PGND

LGATE

VDDP

VDD

CSOP

CSON

BGATE

AGND

AGND

ACOK

14

PC37

PC37

1 2

+RT CVCC

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

342

12

12

.047 U_0 40 2_1 6V7 K~D

.047 U_0 40 2_1 6V7 K~D

CSIP

BOO T

21

LGA TE

20

19

18

CSOP

17

CSON

16

BGA TE

15

29

PR10 4

PR10 4

12

10K_0402_1%~D

10K_0402_1%~D

PR13

0.02 _1 206 _1 %

0.02 _1 206 _1 %

PC20

PC20

1 2

PR23

PR23

1 2

0_0 402 _5 %~D

0_0 402 _5 %~D

PR38

PR38

12

@

@

+3V ALW

PC32

PC32

ISL9 51 9_V DD

10K_0402_1%~D

10K_0402_1%~D

1

12

CSIN

12

1U_0603_10V6K~D

1U_0603_10V6K~D

ISL9 51 9_V DD

PR15

PR15
10_ 040 2_ 1%

10_ 040 2_ 1%

PC21

PC21

0.1U _04 02 _25 V6K ~D

0.1U _04 02 _25 V6K ~D

12

PC22

PC22

0.22 U_0 40 2_1 0V6 K~D

0.22 U_0 40 2_1 0V6 K~D

1 2

27

PR32

PR32

12

4.7_0603_5%

4.7_0603_5%

12

PC34

PC34

12

PR49

PR49

5.36 K_ 040 2_ 1%

5.36 K_ 040 2_ 1%

12

PR40

PR40
10K _04 02 _1% ~D

10K _04 02 _1% ~D

1U_0 60 3_1 0V6 K~ D

1U_0 60 3_1 0V6 K~ D

PR17

PR17

100K_0402_1%

100K_0402_1%

12

PR22

PR22

100K_0402_1%

100K_0402_1%

SGATE

UGATE

PHASE

BOOT

CSIN

25

24

26

23

27

CSIP

CSIN

BOOT

UGATE

SGATE

PHASE

RST#

VFB8AMON

SDA10SCL11VSMB

9

13

12

VSM B

5

4

5

4

ACIN [ 35]

Reserve for EMI

@

@

PQ1223

PQ1223

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5x6 Mos

PQ1221

PQ1221

321

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D

PC507

PC507

30

24

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

12

12

12

PC511

PC511

@

@

2200P_0402_50V7K~D

2200P_0402_50V7K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1 2

1 2

B+

B+=6V-8.4V

PL1 211

PL1 211

3.3U H_FD SD06 30 -H-3R3 M-P 3_6 .6A _2 0%

3.3U H_FD SD06 30 -H-3R3 M-P 3_6 .6A _2 0%

1 2

7x7x3

PR26

PR26

4.7_ 12 06_ 5%~ D

4.7_ 12 06_ 5%~ D

PC30

PC30

680 P_0 40 2_5 0V7 K~D

680 P_0 40 2_5 0V7 K~D

CHOCK DCR= 8.5mohm

SSI2

Battery Current Sensor - BMON circuits

2

(battery = 2S3P -->

2150mAh*3= 6450mAh

---->6450mAh*0.6C=3.9A)

---->6450mAh*0.9C=5.8A)
Design charger current around 6A for worst case
So far battery own by Q and
battery spec didn't release to Compal

12

12

12

PC15

PC15

PC16

PC16

PC18

PC18

PC17

PC17

12

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PC43

PC43

10U_ 08 05_ 25V 6K

10U_ 08 05_ 25V 6K

1 2

PC44

PC44
10U_ 08 05_ 25V 6K

10U_ 08 05_ 25V 6K

1 2

PC24

PC24

12

12

PC25

PC25

10U_0805_25V6K

10U_0805_25V6K

1U_0402_16V6K

1U_0402_16V6K

PR25

PR25

0.01 _1 206 _1 %

0.01 _1 206 _1 %

342

CSOP _B

12

PR29

PR29

PC26

PC26

2.2_0402_1%

2.2_0402_1%

10U_0805_25V6K

10U_0805_25V6K

1 2

PC31

PC31

CSOP

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

Charger voltage MAX = 8.4V

1

CSON _B

VCOM P1

12

12

PR30

PR30

PC27

PC27

@

@

SHORT

0_0402_5%~D

0_0402_5%~D

1 2

10U_0805_25V6K

10U_0805_25V6K

CSON

PR46

@ PR4 6

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

BGA TE

SHORT

Charger current MAX = 2A

H_PR OCHO T# [3 5,6 ]

12

PC12 4

PC12 4

1U_0 60 3_2 5V6 K

1U_0 60 3_2 5V6 K

13

D

D

2

PQ9 08

EC_B AT T_ PRS[ 35,3 7]

+3V ALW

1 2

PR95 9 0_0 40 2_5 %~D

PR95 9 0_0 40 2_5 %~D

1 2

PR96 1

PR96 1

0_0 402 _5 %~D

0_0 402 _5 %~D

PQ9 08

G

G

DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

@

@

@

@

@

@

@

@

PU70 2

PU70 2

1

Out6REF

2

GND

3

V+

INA1 99A 2DC KR_S C70 -6~D

INA1 99A 2DC KR_S C70 -6~D

12

PC1916

PC1916

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

Tit le

Tit le

Tit le

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Date : She et

Date : She et

Date : She et

1 2

BMO N_O UT

PR96 0

PR96 0
0_0 402 _5 %~D

0_0 402 _5 %~D

5

IN-

IN+

PR96 2

PR96 2
10_ 040 2_ 1% @

10_ 040 2_ 1% @

IN-

4

IN+

PC19 15

PC19 15

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1 2

12

@

@

CSON_B

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P38-PWR_Charger(ISL9519)

P38-PWR_Charger(ISL9519)

P38-PWR_Charger(ISL9519)

LA-8821P

LA-8821P

LA-8821P

1

PD5

PD5

SX3 4H_ SM A2

SX3 4H_ SM A2

AO4 407 A_ SO8

AO4 407 A_ SO8

1
2
3 6

4

PC28

PC28

10U_0805_25V6K

10U_0805_25V6K

5

12

PC29

PC29

1000P_0402_50V7K~D

1000P_0402_50V7K~D

@

@

@

@

PR96 3

PR96 3

@

@

10_ 040 2_ 1%

10_ 040 2_ 1%

1 2

CSOP_B

1

21

PQ1 03

PQ1 03

8
7

BAT T+

5

PR47

@ P R47

@

1 2

499K_0402_1%

499K_0402_1%

BMO N [3 5]

12

PC1914

PC1914

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1.0

1.0

1.0

38 54Frida y, S ep tem ber 28, 20 12

38 54Frida y, S ep tem ber 28, 20 12

38 54Frida y, S ep tem ber 28, 20 12

of

of

of

A

3.3VALWP
TDC 3.9A
Peak Current 5.6A

1 1

OCP current 6.6A

V-8.4V

B+

33

PJP200

@P JP200

@

2

112

JUMP_43 X118

JUMP_43 X118

1

+

PC19 21

@+PC19 21

@

100U _D2_ 16VM_R50 M

100U _D2_ 16VM_R50 M

2

2 2

+3VALW

B+

12

12

PC1913

PC1913

PC1912

PC1912

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

3 3

PQ204 A

DMN66D 0LDW -7_SOT36 3-6~D

DMN66D 0LDW -7_SOT36 3-6~D

USBCH G_DET_ D[35]

4 4

PQ204 A

EC_ON N_5V_001

EC_ON[35]

VCOUT0_ PH#[35,39]

B++

12

12

PC201

PC201

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

PJP202

@ PJP2 02

@

2

112

JUMP_43 X79

JUMP_43 X79

PJP204

@ PJP2 04

@

2

112

JUMP_43 X79

JUMP_43 X79

12

PC1917

PC1917

10U_0805_25V6K

10U_0805_25V6K

ENTRIP1ENTRIP1

61

2

12

PR96 9

PR96 9

1 2

10K_0 402_ 1%~D

10K_0 402_ 1%~D

PD90 6 RB751V-4 0_SOD 323-2PD90 6 RB751V-4 0_SOD 323-2

1 2

EC_ON

PR93 8 10K_0402 _1%~ DP R938 10K_ 0402_ 1%~D

PR97 1 1K_0402_ 1%~DPR971 1K_0402 _1%~D

PD90 3 RB751V-4 0_SOD 323-2PD90 3 RB751V-4 0_SOD 323-2

1 2

PD90 7 RB751V-4 0_SOD 323-2PD90 7 RB751V-4 0_SOD 323-2

12

PC203

PC203

PC202

PC202

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K~D

2200P_0402_50V7K~D

CHOCKDCR=25mohm

7x7

PL120 7

PL120 7

3.3UH _FDSD0 630-H -3R3M-P 3_6.6A_2 0%

3.3UH _FDSD0 630-H -3R3M-P 3_6.6A_2 0%

1 2

12

+

@

@

PC210

PC210

2

150U_B2_6.3V-M~D

150U_B2_6.3V-M~D

PD90 9 R B751V-4 0_SOD3 23-2

PD90 9 R B751V-4 0_SOD3 23-2

N_5V_0 01 N_3V_ 001

12

PR958

PR958

PC1911

PC1911

1M_0402_1%~D

1M_0402_1%~D

2.2U_0603_10V6K

2.2U_0603_10V6K

PC214

PC214

2

150U_B2_6.3V-M~D

150U_B2_6.3V-M~D

30

@

@

1 2

@

@

PR95 7

PR95 7

10K_0 402_ 1%~D

10K_0 402_ 1%~D

4.7_1206_5%~D

4.7_1206_5%~D

SNUB_3V

12

12

PR208

PR208

1

1

+

+

+

12

12

1 2

12

PC217

PC217

1U_0603_10V6K~D

A

1U_0603_10V6K~D

B

PQ120 7

PQ120 7

5

AON7406 L_DFN 8-5

AON7406 L_DFN 8-5

3x3 H/S

4

PT3

PT3

123

PAD~D

PAD~D

@

@

5

@

@

PAD~D

PAD~D
PT5

PT5

4

PQ1208

PQ1208

AON7212L_DFN8-5

AON7212L_DFN8-5

3x3 L/S

123

PC212

PC212

680P_0603_50V7K

680P_0603_50V7K

AON7406L

Rds(on) :19mohm , 23.5mohm

AON7212L

Rds(on) :6.2mohm , 7.8mohm

5

N_3V_0 01

POK[18,37]

PC20 8

PC20 8

0.22U _0603 _10V7K

0.22U _0603 _10V7K

12

@

@

12

PC221

PC221

.1U_0402_16V7K~D

.1U_0402_16V7K~D

TYP MAX

TYP MAX

ENTRIP2

34

PQ204 B

PQ204 B

DMN66D 0LDW -7_SOT36 3-6~D

DMN66D 0LDW -7_SOT36 3-6~D

BST1_3 V

12

PR970

PR970

1M_0402_1%~D

1M_0402_1%~D

B

@P R43

@

6

0_04 02_5% ~D

0_04 02_5% ~D

1 2

PR20 6

PR20 6

1 2

2.2_06 03_5 %~D

2.2_06 03_5 %~D

B++

VCOUT0_ PH#[35,39]

ENTRIP2

PR43
100K_ 0402 _1%

100K_ 0402 _1%

PR51 6@

PR51 6@

SHORT

C

PR19

PR19
100K_ 0402 _1%

100K_ 0402 _1%

8243_TON

3

TON

ENM

12

PR514

PR514

PC215

PC215

1U_0603_10V6K~D

1U_0603_10V6K~D

2

12

12

ENTRIP1

15

12

PC22 2

PC22 2
10U_ 0805_ 10V6K

10U_ 0805_ 10V6K

1 2

PC19 20

@P C192 0

@

1000 P_040 2_50V7K ~D

1000 P_040 2_50V7K ~D

1 2

PR21 6

PR21 6

37.4K_ 0402 _1%

37.4K_ 0402 _1%

1 2

PC21 9

PC21 9
100P_ 0402 _50V8J~D

100P_ 0402 _50V8J~D

1 2

PR20 1

PR20 1

30.9K_ 0402 _1%

30.9K_ 0402 _1%

1 2

PR20 3

PR20 3

20K_0 402_ 1%~D

20K_0 402_ 1%~D

1 2

PC12 5

PC12 5

1U_0 603_2 5V6K

1U_0 603_2 5V6K

1

21

FB1

PAD

20

BYP1

19

BOOT1

18

UGATE1

17

LX_5V

PHASE1

16

LGATE1

RT824 3BZQW_WQ FN20_3 X3

RT824 3BZQW_WQ FN20_3 X3

6

PR51 2@

PR51 2@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

PC20 5

PC20 5
10U_ 0805_ 6.3V6M~D

10U_ 0805_ 6.3V6M~D

PR51 3@

PR51 3@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

6

12

BST_5V

UG_5V

LG_5V

+3VLP

1 2

2.2_06 03_5 %~D

2.2_06 03_5 %~D

@P T19

@

PC19 19

@P C191 9

@

1000 P_040 2_50V7K ~D

1000 P_040 2_50V7K ~D

1 2

PR21 8

PR21 8

39K_0 402_ 1%~D

39K_0 402_ 1%~D

1 2

PC22 0

PC22 0
100P_ 0402 _50V8J~D

100P_ 0402 _50V8J~D

1 2

PR20 0

PR20 0

13.7K_ 0402 _1%~D

13.7K_ 0402 _1%~D

1 2

PR20 2

PR20 2

20K_0 402_ 1%~D

20K_0 402_ 1%~D

1 2

FB_3V

+3VLP

PU50 1

PU50 1

5

4

FB2

1 2

6

PGOOD

ENTRIP2

7

BOOT2

BST_3V

8

UG_3V

UGATE2

9

LX_3V

PHASE2

10

LG_3V

LGATE2

VIN11ENLDO12SECFB13LDO514LDO3

B++

12

PC216

PC216

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

PD20 0

@ PD2 00

@

BZT52-B 5V6S_SOD 323-2

BZT52-B 5V6S_SOD 323-2

21

1 2

PR21 9@ 0_0 402_ 5%~DPR2 19@ 0_ 0402 _5%~D

SHORT

1 2

0_04 02_5% ~D

0_04 02_5% ~D

6

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PR515

@ PR515

@

LDO_E N

499K_ 0402 _1%

499K_ 0402 _1%

1 2

@

@

PR21 1

PR21 1

0_0402_5%~D

0_0402_5%~D

PR21 0

PR21 0

C

+3VLP

0_0402_5%~D

0_0402_5%~D

12

12

PR212

PR212

200K_0402_1%~D

200K_0402_1%~D

ENTRIP1

1 2

PR20 7

PR20 7

PT19
PAD~D

PAD~D

PR941

PR941

1_0402_1%~D

1_0402_1%~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

B++

12

PC206

PC206

BST1_5 V

.1U_0 402_1 6V7K~D

.1U_0 402_1 6V7K~D

D

12

12

PC207

PC207

2200P_0402_50V7K~D

2200P_0402_50V7K~D

PC20 9

PC20 9

0.22U _0603 _10V7K

0.22U _0603 _10V7K

12

@

@

PC21 8

PC21 8

D

PC204

PC204

10U_0805_25V6K

10U_0805_25V6K

PT4

PT4
PAD~D

PAD~D

@

@

@

@

PAD~D

PAD~D
PT6

PT6

12

PQ121 0

PQ121 0

AON7212 L_DFN 8-5

AON7212 L_DFN 8-5

3x3 L/S

E

5VALWP
TDC 4.4A
Peak Current 6.4A
OCP current 7.5A

5

PQ120 9

PQ120 9
AON7406 L_DFN 8-5

AON7406 L_DFN 8-5

3x3 H/S

4

123

5

4

123

CHOCKDCR=16mohm

7x7

PL201

PL201

2.2UH _FDSD0 630-H -2R2M-P 3_8.3A_2 0%

2.2UH _FDSD0 630-H -2R2M-P 3_8.3A_2 0%

1 2

12

PR209

PR209

4.7_1206_5%~D

4.7_1206_5%~D

30

SNUB_5V

1

+

+

2

@ PJP2 01

@

2

@ PJP2 03

@

2

PC224

PC224

150U_B2_6.3V-M~D

150U_B2_6.3V-M~D

12

PC213

PC213

680P_0603_50V7K

680P_0603_50V7K

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P39-PWR_3.3VALWP/5VALWP-8243

P39-PWR_3.3VALWP/5VALWP-8243

P39-PWR_3.3VALWP/5VALWP-8243

Size Docum ent Num ber Rev

Size Docum ent Num ber Rev

Size Docum ent Num ber Rev

Date: Shee t of

Date: Shee t of

Date: Shee t of

LA-8821P

LA-8821P

LA-8821P

E

PJP201

JUMP_43 X79

JUMP_43 X79

PJP203

JUMP_43 X79

JUMP_43 X79

39 5 4Friday, Sep temb er 28, 20 12

39 5 4Friday, Sep temb er 28, 20 12

39 5 4Friday, Sep temb er 28, 20 12

112

+5VALW

112

1.0

1.0

1.0

A

1 1

PJP400

@ PJP4 00

@

2

112

JUMP_43 X79

JUMP_43 X79

SUSP#[3 2,35,40 ,41,42]

2 2

@ PJ P401

@

3 3

SUSP#[3 2,35,40 ,41,42]

PJP401

2

JUMP_43 X79

JUMP_43 X79

PR40 2 0 _0402 _5%~ DPR 402 0_0 402_ 5%~D

112

PR40 5 0 _0402 _5%~ DPR 405 0_0 402_ 5%~D

12

1 2

28

12

1 2

+1.8VS_P WROK[35]

28

PC40 0

PC40 0
22U_ 0805_ 6.3V6M~D

22U_ 0805_ 6.3V6M~D

EN_1 .8VSP

47K_0 402_ 5%

47K_0 402_ 5%

+1.5VS_P WROK[35]

PC41 0

PC41 0
22U_ 0805_ 6.3V6M~D

22U_ 0805_ 6.3V6M~D

EN_1 .5VSP

47K_0 402_ 5%

47K_0 402_ 5%

1.8VSP_VIN

@P R403

@

1.5VSP_VIN

PR40 7

@ PR40 7

@

12

PR40 3

12

20

PR51 7

@ PR51 7

@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

12

@

@

20

PR51 8

@P R518

@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

12

PC406

PC406

@

@

PC404

PC404

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

PU40 0

PU40 0

10

9

8

5

PU40 1

PU40 1

10

PVIN

9

PVIN

8

SVIN

5

EN

B

+3VALW

PR44

@ PR44

@

100K_ 0402 _1%

100K_ 0402 _1%

1 2

1.8V_PG

4

PVIN

PG

PVIN

SVIN

EN

TP

NC

7

11

SY8033 BDBC_ DFN10 _3X3

SY8033 BDBC_ DFN10 _3X3

+3VALW

PR45

@P R45

@

100K_ 0402 _1%

100K_ 0402 _1%

1 2

1.5V_PG

4

LX

PG

LX

FB

TP

NC

7

1

11

SY8033 BDBC_ DFN10 _3X3

SY8033 BDBC_ DFN10 _3X3

C

D

CHOCK DCR=27mohm

<Vo=1.8V> VFB= 0.6V

PL400

PL400

30

1UH_ NRS4 018T1R 0NDGJ _3.2A_30 %

2

1.8VSP_LX

LX

3

LX

6

1.8VSP_FB

FB

NC

1

2

1.5VSP_LX

3

6

1.5VSP_FB

NC

1UH_ NRS4 018T1R 0NDGJ _3.2A_30 %

1 2

12

4x4x2

PR400

PR400

4.7_1206_5%~D

4.7_1206_5%~D

SNUB_1.8VSP

12

PC405

PC405

680P_0603_50V7K

680P_0603_50V7K

PL401

PL401

30

1UH_ NRS4 018T1R 0NDGJ _3.2A_30 %

1UH_ NRS4 018T1R 0NDGJ _3.2A_30 %

1 2

12

4x4x2

15K_0 402_ 1%~D

15K_0 402_ 1%~D

PR406

PR406

4.7_1206_5%~D

4.7_1206_5%~D

SNUB_1.5VSP

12

10K_0 402_ 1%~D

10K_0 402_ 1%~D

PC409

PC409

680P_0603_50V7K

680P_0603_50V7K

PR40 1

PR40 1

20K_0 402_ 1%~D

20K_0 402_ 1%~D

PR40 4

PR40 4

10K_0 402_ 1%~D

10K_0 402_ 1%~D

PR40 8

PR40 8

PR40 9

PR40 9

12

12

PC401

PC401

12

22P_0402_50V8J~D

22P_0402_50V8J~D

PC402

12

12

PC407

PC407

12

PC402

22U_0805_6.3VAM

22U_0805_6.3VAM

@ PJ P403

@

12

12

22P_0402_50V8J~D

22P_0402_50V8J~D

12

PC411

PC411

22U_0805_6.3VAM

22U_0805_6.3VAM

Vo=VFB*(1+PR401 /PR404)=0.6*(1 +20K/10K)=1.8V

PJP402

@ PJP4 02

@

2

12

PJP403

2

JUMP_43 X79

JUMP_43 X79

PC408

PC408

+1.8VS+3VALW

112

JUMP_43 X79

JUMP_43 X79

PC403

PC403

22U_0805_6.3VAM

22U_0805_6.3VAM

+1.8VSP
TDC 0.9A
Peak Current 1. 2A

22U_0805_6.3VAM

22U_0805_6.3VAM

<Vo=1.5V> VFB= 0.6V
Vo=VFB*(1+PR401 /PR404)=0.6*(1 +15K/10K)=1.5V

+1.5VS+3VALW

112

+1.5VSP
TDC 0.35A
Peak Current 0. 5A

4 4

Comp al El ectron ics, I nc.

Comp al El ectron ics, I nc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

Title

Title

Title

Size Docum ent Nu mbe r R ev

Size Docum ent Nu mbe r R ev

Size Docum ent Nu mbe r R ev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Comp al El ectron ics, I nc.

P40-PW R_1.8V SP/1. 5VSP

P40-PW R_1.8V SP/1. 5VSP

P40-PW R_1.8V SP/1. 5VSP

LA-8821P

LA-8821P

LA-8821P

D

40 5 4Friday, Septe mbe r 28, 201 2

40 5 4Friday, Septe mbe r 28, 201 2

40 5 4Friday, Septe mbe r 28, 201 2

1.0

1.0

1.0

5

D D

+V1.05S_VCCP_PWRGOOD[43]

SUSP#[32,35,40,42]

C C

B B

PR503

PR503

0_0402_5%~D

0_0402_5%~D

1 2

@

@

.1U_0402_16V7K~D

.1U_0402_16V7K~D

PR502

PR502

33K_0402_1%~D

33K_0402_1%~D

1 2

12

PC505

PC505

PR510

PR510
10K_0402_1%~D

10K_0402_1%~D

1 2

1 2

TRIP_+V1.05S_VCCPP

EN_+V1.05S_VCCPP

FB_+V1.05S_VCCPP

RF_+V1.05S_VCCPP

12

PR505

PR505

470K_0402_1%

470K_0402_1%

7

PR509@

PR509@
0_0402_5%~D

0_0402_5%~D

SHORT

+3VS

PR500

PR500
100K_0402_5%~D

100K_0402_5%~D

1 2

PU500

PU500

1

PGOOD

2

TRIP

3

EN

4

VFB

5

TST

TPS51212DSCR_SON10_3X3

TPS51212DSCR_SON10_3X3

PC510

@ PC510

@

1000P_0402_50V7K~D

1000P_0402_50V7K~D

12

PR507

PR507

4.99K_0402_1%

4.99K_0402_1%

VSSIO_SENSE [9]

4

PR501

PR501

2.2_0603_5%~D

10

BST_+V1.05S_VCCPP

VBST

9

UG_+V1.05S_VCCPP

DRVH

8

SW_+V1.05S_VCCPP

SW

7

V5IN

6

LG_+V1.05S_VCCPP

DRVL

11

TP

12

PR506

@PR506

@

1.2K_0402_1%

1.2K_0402_1%

12

2.2_0603_5%~D

1 2

1 2

3

@

@

PT7

PT7

PC504

PC504

PAD~D

+5VALW

PAD~D

PT8

PT8
PAD~D

PAD~D

@

@

PC506

PC506
1U_0603_6.3V6M

1U_0603_6.3V6M

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

1 2

SIR472DP

Rds(on) :12mohm , 15mohm

SIR818DP

Rds(on) :2.7mohm , 3.3mohm

+V1.05S_VCCPP_B+

5

4

123

5x6 H/S

5

4

321

5x6 L/S

TYP MAX

TYP MAX

PQ1211

PQ1211

SIR472DP-T1-G E3_POWERPAK8-5~D

SIR472DP-T1-G E3_POWERPAK8-5~D

CHOCK DCR=10mohm

1UH_FDSD0630-H-1R0M-P3_11A_20%

1UH_FDSD0630-H-1R0M-P3_11A_20%

PQ1219

PQ1219

SIR818DP-T1_PO WERPAK-SO8-5~D

SIR818DP-T1_PO WERPAK-SO8-5~D

2

12

PC501

PC501

PC500

PC500

0.1U_040 2_25V6K~D

0.1U_040 2_25V6K~D

PL1212

PL1212

1 2

12

7x7

PR504

@PR504

@

4.7_1206_5%~D

4.7_1206_5%~D

12

PC508

@PC508

@

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

B+=6V-8.4V

PJP500

@ PJP500

@

2

JUMP_43X79

JUMP_43X79

12

12

12

PC503

PC503

PC502

PC502

10U_0805 _25V6K

10U_0805 _25V6K

10U_0805 _25V6K

10U_0805 _25V6K

2200P_04 02_50V7K~D

2200P_04 02_50V7K~D

@ PJP501

@

2

@ PJP502

@

2

PC509

PC509

@

@

1 2

0.1U_040 2_10V7K~D

0.1U_040 2_10V7K~D

B+

112

34

PJP501

112

JUMP_43X118

JUMP_43X118

PJP502

112

JUMP_43X118

JUMP_43X118

7

PR508@

PR508@
0_0402_5%~D

0_0402_5%~D

12

SHORT

+V1.05S_VCCPP
TDC 8.3A
Peak Current 11.8A
OCP current 14.1A

+VCCP

VCCIO_SENSE [9]

A A

Com pal El ectron ics, Inc.

Com pal El ectron ics, Inc.

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS C ONTAINS CONFIDE NTIAL
TRADE SECRET AN D OTHER PROPRI ETARY INFORMATI ON OF DELL INC . ("DELL") THI S DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHO RIZATION OF DE LL. IN ADDITION ,
NEITHER THIS SH EET NOR THE IN FORMATION IT CO NTAINS WAY BE USED BY OR DIS CLOSED TO ANY T HIRD
PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT .

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Com pal El ectron ics, Inc.

P41-P WR_V1.05S_VCCPP

P41-P WR_V1.05S_VCCPP

P41-P WR_V1.05S_VCCPP

LA-8821P

LA-8821P

LA-8821P

41 54Friday, September 28, 2012

41 54Friday, September 28, 2012

41 54Friday, September 28, 2012

1

1.0

1.0

1.0

5

4

3

2

1

35

PJP301

@ PJP301

D D

B+=6V-8.4V

C C

B B

A A

+1.35V

1.35VP
TDC 6.6A
Peak Current 9.4A
OCP current 11.2A

B+

@ PJP303

@

2

PJP303

112

JUMP_43X118

JUMP_43X118

1

+

+

2

@

2

PC981

PC981

JUMP_43X79

JUMP_43X79

+1.35VS

330U_B_2. 5VM_R9M

330U_B_2. 5VM_R9M

112

1

+

+

2

1.35V_B+

12

12

12

PC300

PC300

PC302

PC302

PC303

10U_0805 _25V6K

10U_0805 _25V6K

PC303

10U_0805 _25V6K

10U_0805 _25V6K

CHOCK DCR=16mohm

PL1210

PL1210

1UH_FDSD0630-H-1R0M-P3_11A_20%

1UH_FDSD0630-H-1R0M-P3_11A_20%

1 2

7x7

PC308

PC308

330U_B_2. 5VM_R9M

330U_B_2. 5VM_R9M

12

PC304

PC304

0.1U_040 2_25V6K~D

0.1U_040 2_25V6K~D
2200P_04 02_50V7K~D

2200P_04 02_50V7K~D

5

PT9

3x3 H/S

PQ1215

PQ1215

AON7406L_ DFN8-5

AON7406L_ DFN8-5

12

@

@

PR302

PR302

4.7_1206 _5%~D

4.7_1206 _5%~D

@

@

PC311

PC311

680P_060 3_50V7K~D

680P_060 3_50V7K~D

PQ1226

PQ1226

AON7212L_ DFN8-5

SNUB_1.5V

12

AON7212L_ DFN8-5

AON7406L

Rds(on) :19mohm , 23.5mohm

AON7212L

Rds(on) :6.2mohm , 7.8mohm

PT9
PAD~D

PAD~D

@

@

4

123

5

4

123

PT10

PT10

PAD~D

PAD~D

@

@

TYP MAX

TYP MAX

PR300

PR300

PC301

PC301

2.2_0603_5%~D

12

PR301

PR301

6.98K_0402_1%~D

6.98K_0402_1%~D

1 2

PC307

PC307

1U_0603_10V6K~D

1U_0603_10V6K~D

VDD_1.35V

PC310

PC310
1U_0603_10V6K~D

1U_0603_10V6K~D

+3VALW

21

12

PC313

PC313
.1U_0402_16V7K~D

.1U_0402_16V7K~D

@

@

2.2_0603_5%~D

1 2

DL_1.35V

CS_1.35V

+5VALW

PR48

@PR48

@

100K_0402_1%

100K_0402_1%

1 2

PR521@

PR521@
0_0402_5%~D

0_0402_5%~D

1 2

SHORT

1.35V_B+

12

PC1910

PC1910

0.1U_040 2_25V6K~D

0.1U_040 2_25V6K~D

BOOT_1.35V

DH_1.35V

SW_1.35V

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

1M_0402_1%~D

1M_0402_1%~D

PR305

PR305

1 2

S5_1.35V

16

18

17

BOOT

PHASE

UGATE

RT8207MZQW_WQFN20_3X3

RT8207MZQW_WQFN20_3X3

S5

PGOOD

TON

8

9

10

1.35V_TON

19

7

S3_1.35V

0.22U_0603_10V7K

0.22U_0603_10V7K

PR303

PR303

5.1_0603_5%~D

5.1_0603_5%~D

1 2

+5VALW

+1.5V_PWROK[ 35]

PR306

PR306

0_0402_5%~D

0_0402_5%~D

SYSON[32,35]

SUSP#[32,35,40,41]

CPU1.5V_S3_GATE[32,35,6,9]

1 2

PR308

@PR308

@

0_0402_5%~D

0_0402_5%~D

1 2

PR323

PR323
1K_0402_5%~D

1K_0402_5%~D

1 2

VLDOIN_1.35V

20

VTT

VLDOIN

VTTGND

VTTSNS

VTTREF

FB

S3

6

PU300

PU300

VDDQ

PAD

GND

1.35V_FB

21

PR119

@PR119

@

0_0603_5%~D

0_0603_5%~D

1 2

SHORT

21

1

2

3

4

VTTREF_1.35V

5

12

PR307

PR307
10K_0402_1%~D

10K_0402_1%~D

+1.35V

22

PR304

PR304

8.2K_0402_1%

8.2K_0402_1%

1 2

1 2

PC314

PC314
100P_0402_50V8J~D

100P_0402_50V8J~D

+0.675VSP

12

PC305

PC305

10U_0805 _6.3V6M~D

10U_0805 _6.3V6M~D

PC309

PC309

0.033U_0402_16V7K~D

0.033U_0402_16V7K~D

+1.35VS

12

PC312

PC312
.1U_0402_16V7K~D

.1U_0402_16V7K~D

@

@

0.675Volt +/- 5%
TDC 0.7A
Peak Current 0.9A
OCP Current 1.2A

PR120

PR120

0_0603_5%~D

0_0603_5%~D

1 2

12

PC306

PC306

10U_0805 _6.3V6M~D

10U_0805 _6.3V6M~D

+0.675VS

Com pal El ectron ics, Inc.

Com pal El ectron ics, Inc.

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS C ONTAINS CONFIDE NTIAL
TRADE SECRET AN D OTHER PROPRI ETARY INFORMATI ON OF DELL INC . ("DELL") THI S DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHO RIZATION OF DE LL. IN ADDITION ,
NEITHER THIS SH EET NOR THE IN FORMATION IT CO NTAINS WAY BE USED BY OR DIS CLOSED TO ANY T HIRD
PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT .

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Com pal El ectron ics, Inc.

P42-P WR_+1.35VP/0.675VSP

P42-P WR_+1.35VP/0.675VSP

P42-P WR_+1.35VP/0.675VSP

LA-8821P

LA-8821P

LA-8821P

42 54Friday, September 28, 2012

42 54Friday, September 28, 2012

42 54Friday, September 28, 2012

1

1.0

1.0

1.0

5

4

3

2

1

12/15 update value

VID [0] VID[1] VCCSA Vout
0 0 0.9V

The 1k PD on the VCCSA VIDs are empty.
Theseshould be stuffed to ensurethat

D D

SA_ PGO OD[35] VCCS A_V ID1 [9 ]

+5V ALW

PC60 1

PC60 1

2.2U _06 03 _10 V7K

2.2U _06 03 _10 V7K

1 2

C C

1

12

12

PC614

PC614

PC615

PC615

1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

+3V ALW

PC613

PC613

PC612

PC612

PJP6 00

@ PJP6 00

@

2

+VCC SA_ PWR_ SRC +VCCS A_ PWR_ SRC

112

JUMP _4 3X7 9

JUMP _4 3X7 9

2

2200P_0402_50V7K~D

2200P_0402_50V7K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

27

PC61 6

PC61 6

12

0.22 U_0 40 2_1 0V6 K~D

0.22 U_0 40 2_1 0V6 K~D

PC61 7

PC61 7

330 0P_ 04 02_ 50V 7K

330 0P_ 04 02_ 50V 7K

B B

PR60 3

PR60 3

10_ 040 2_ 1%

10_ 040 2_ 1%

PU60 0

PU60 0

19

20

21

22

23

24

12

0_0 402 _5 %~D

0_0 402 _5 %~D

PGND

PGND

PGND

VIN

VIN

VIN

+3V S

8

PR601

PR601

PR61 1@

PR61 1@

@

@

1 2

SHORT

1 2

12

18

17

V5FILT

V5DRV

TPS 51 463 RGE R QF N 24 P P WM

TPS 51 463 RGE R QF N 24 P P WM

GND

VREF

1

2

12

PR60 9

PR60 9

5.1K _0 402 _5 %

5.1K _0 402 _5 %

100K_0402_5%~D

100K_0402_5%~D

PC600

PC600

12

1U_0603_10V6K~D

1U_0603_10V6K~D

16

PGOOD

COMP

3

14

15

VID0

VID1

VOUT

SLEW

5

4

PC61 8

PC61 8

0.01 U_0 40 2_1 6V7 K~D

0.01 U_0 40 2_1 6V7 K~D

1 2

13

6

23

1 2

1 2

EN

BST

SW

SW

SW

SW

SW

TP

MODE

VCCSA VID is00 prior to VCCIO stability.

PR60 0

PR60 0
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

PR60 2

PR60 2
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

PC61 9

@ PC6 19

@

1 2

0.03 3U_ 04 02_ 16V 7K ~D

0.03 3U_ 04 02_ 16V 7K ~D

+VCC SA_ EN

2.2_ 06 03_ 5%~ D

2.2_ 06 03_ 5%~ D

1 2

12

11

+VCC SA_ PHA SE

10

9

8

7

25

PR60 7

PR60 7

12

100 K_0 40 2_1 %

100 K_0 40 2_1 %

PR60 4

PR60 4

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

PR60 5

PR60 5

0.1U _06 03 _50 V7K ~D

0.1U _06 03 _50 V7K ~D

+VCC SA_ BT _1+V CCSA _BT

12

PC60 3

@ P C60 3

@

100 0P_ 04 02_ 50V 7K ~D

100 0P_ 04 02_ 50V 7K ~D

12

PR60 6

@P R60 6

@

4.7_ 12 06_ 5%~ D

4.7_ 12 06_ 5%~ D

VCCS A_V ID0 [9 ]

+V1 .05S _V CCP_ PWRG OO D [41 ]

PC60 2

PC60 2

CHOCK DCR=36mohm

1 2

PL6 00

PL6 00

0.47 UH_ FDVE 063 0

0.47 UH_ FDVE 063 0

1 2

7x7

PC604

PC604

@

@

22U_0805_6.3V6M

22U_0805_6.3V6M

0 1 0.85V
1 0 0.775V
1 1 0.75V

output voltage adjustable network for ULV CPU

+VCC_SAP
TDC 2.8A
Peak Current 4A

12

PC607

PC607

PC606

PC606

1 2

1 2

PC605

PC605

@

@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

24

12

PC610

PC610

PC608

PC608

1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

1 2

1 2

PC609

PC609

22U_0805_6.3V6M

22U_0805_6.3V6M

2200P_0402_50V7K~D

2200P_0402_50V7K~D

29

PR60 8

PR60 8

100 _04 02 _1% ~D

100 _04 02 _1% ~D

12

8

PR61 0@

PR61 0@
0_0 402 _5 %~D

0_0 402 _5 %~D

12

SHORT

VCCS A_S ENS E [9]

PJP6 01

@ PJP 601

@

2

PC611

PC611

1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

JUMP _4 3X1 18

JUMP _4 3X1 18

+VCC SA

112

A A

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P43-PWR_+VCCSAP

P43-PWR_+VCCSAP

P43-PWR_+VCCSAP

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Date : She et

Date : She et

Date : She et

LA-8821P

LA-8821P

LA-8821P

1

43 54Frida y, S ep tem ber 28, 20 12

43 54Frida y, S ep tem ber 28, 20 12

43 54Frida y, S ep tem ber 28, 20 12

of

of

of

1.0

1.0

1.0

5

PR70 1

PR70 1

3.83K_ 0402 _1%~D

3.83K_ 0402 _1%~D

VSUMG+

D D

C C

B B

A A

VSUMG-

+VCCP

PR70 6

PR70 6

2.61K_ 0402 _1%~D

2.61K_ 0402 _1%~D

1 2

12

PH70 1

PH70 1
10K_0 402_ 5%_ER TJ0ER1 03J

10K_0 402_ 5%_ER TJ0ER1 03J

12

PC71 4

PC71 4
.1U_0 402_1 6V7K~D

.1U_0 402_1 6V7K~D

VR_SVID_C LK[9]

VR_SVID_ALR T#[9]

VR_SVID_D AT[9 ]

VR_HOT#[35]

12

470K_ 0402 _5%_ ERTJ0EV47 4J~D

470K_ 0402 _5%_ ERTJ0EV47 4J~D

1 2

PR70 4

PR70 4

27.4K_ 0402 _1%~D

27.4K_ 0402 _1%~D

+VCCP

12

PR72 5

@PR 725

@

1 2

499_ 0402_ 1%~D

499_ 0402_ 1%~D

5

12

PH70 0

PH70 0

PR717

PR717

130_0402_1%~D

130_0402_1%~D

1 2

3.83K_ 0402 _1%~D

3.83K_ 0402 _1%~D

PR72 6

PR72 6

1 2

12

12

Local s ense put on HW site

NTCG

VCC_AXG_SEN SE[9]

VSS_AXG_SENS E[9]

PR709

PR709

PC710

PC710

PC711

PC711

1 2

1 2

11K_0402_1%~D

11K_0402_1%~D

.1U_0402_16V7K~D

.1U_0402_16V7K~D

.047U_0402_16V7K~D

.047U_0402_16V7K~D

PR719

PR719

54.9_0402_1%~D

54.9_0402_1%~D

9

PR72 0@

PR72 0@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

+5VS

SHORT

VR_ON[35]

PC71 7

PC71 7

43P_0 603_ 50V8J

43P_0 603_ 50V8J

1 2

PH70 2

PH70 2

470K_ 0402 _5%_ ERTJ0EV47 4J~D

470K_ 0402 _5%_ ERTJ0EV47 4J~D

12

PR72 7

PR72 7

27.4K_ 0402 _1%~D

27.4K_ 0402 _1%~D

VSUM+

12

PR741

PR741

2.61K_0402_1%~D

2.61K_0402_1%~D
PH703

PH703

1 2

10K_0402_5%_ERTJ0ER103J

VSUM-

10K_0402_5%_ERTJ0ER103J

12

PC745

PC745

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1 2

PR72 3

PR72 3

0_04 02_5% ~D

0_04 02_5% ~D

+5VS

12

PR744

PR744

11K_0402_1%~D

11K_0402_1%~D

649_ 0402_ 1%~D

649_ 0402_ 1%~D

1 2

@

@

PR70 7

PR70 7

PR71 2

PR71 2

412_ 0402_ 1%

412_ 0402_ 1%

12

PC741

PC741

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

4

PC70 2

@PC 702

@

1 2

330P_ 0402 _50V7K~ D

330P_ 0402 _50V7K~ D

PC70 6

PC70 6

0.01U _0402 _16V7K~ D

0.01U _0402 _16V7K~ D

12

ISEN2G
NTCG

NTC

12

PC742

PC742

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

649_ 0402_ 1%~D

649_ 0402_ 1%~D

4

12

PC71 2

PC71 2

1 2

0.01U _0402 _16V7K~ D

0.01U _0402 _16V7K~ D

PU70 0

PU70 0

1

ISUMPG

2

ISEN1G

3

ISEN2G

4

NTCG

5

SCLK

6

ALERT#

7

SDA

8

VR_HOT#

9

VR_ON

10

NTC

41

TP

9

PR73 6@

PR73 6@

0_04 02_5% ~D

0_04 02_5% ~D

1 2

SHORT

12

PC743

PC743

.047U_0402_16V7K~D

.047U_0402_16V7K~D

1 2

PR75 0

PR75 0

1 2

@

@

PR74 8

PR74 8

470_ 0402_ 1%

470_ 0402_ 1%

1 2

PC70 0 330 P_040 2_50V7 K~DPC7 00 33 0P_0 402_5 0V7K~D

2.55K_ 0402 _1%

2.55K_ 0402 _1%

1 2

PR70 5

PR70 5

12

PC707

PC707

39

38

40

RTNG

ISUMNG

ISEN212FB17ISUMP14ISEN3/FB2

11

13

ISEN2

330P_0402_50V7K~D

330P_0402_50V7K~D

LGATE1G

37

36

35

34

FBG

COMPG

PWM2G

PGOODG

LGATE1G

RTN16ISEN1

15

12

100_ 0402_ 1%~D

100_ 0402_ 1%~D

12

PWMG2

PHASE1G

UGATE1G

BOOT1G

32

31

BOOT1G

PHASE1G33UGATE1G

BOOT2
UGATE2
PHASE2
LGATE2

VCCP

VDD

PWM3
LGATE1
PHASE1
UGATE1

COMP

PGOOD19ISUMN

BOOT1

18

20

ISL958 36HR TZ-T_TQFN4 0_5X5~D

ISL958 36HR TZ-T_TQFN4 0_5X5~D

BOOT1

COMP

FB

PR73 3

PR73 3

100_ 0402_ 1%~D

100_ 0402_ 1%~D

PR73 7

PR73 7

330P_ 0402 _50V7K~ D

330P_ 0402 _50V7K~ D

@

@

1 2

PC739

PC739

330P_0402_50V7K~D

330P_0402_50V7K~D

Local s ense put on HW site

PC74 6

PC74 6

0.01U _0402 _16V7K~ D

0.01U _0402 _16V7K~ D

1 2

12

PR70 2

PR70 2

PC70 3

PC70 3

1 2

1000 P_040 2_50V7K ~D

1000 P_040 2_50V7K ~D

PR70 8

PR70 8

33.2K_ 0402 _1%~D

33.2K_ 0402 _1%~D

PR71 6

@P R716

@

0_04 02_5% ~D

0_04 02_5% ~D

12

30
29
28
27
26
25
24
23
22
21

1 2

1.91K_ 0402 _1%~D

1.91K_ 0402 _1%~D

PC72 8

PC72 8

1 2

12

1000 P_040 2_50V7K ~D

1000 P_040 2_50V7K ~D

1 2

2K_04 02_1 %~D

2K_04 02_1 %~D

PC73 7

@PC73 7

@

1 2

PC73 8

PC73 8

0.01U _0402 _16V7K~ D

0.01U _0402 _16V7K~ D

1 2

3

PR70 0

PR70 0
2K_04 02_1 %~D

2K_04 02_1 %~D

PR70 3

PR70 3

44.2K_ 0402 _0.5%~ D

44.2K_ 0402 _0.5%~ D

+5VS

12

PC70 8

PC70 8

1 2

100P_ 0402 _50V8J~D

100P_ 0402 _50V8J~D

UGATE1G

1 2

BOOT1G

PR71 0

PR71 0

2.2_06 03_5 %~D

2.2_06 03_5 %~D

PC70 1

PC70 1

150P_ 0402 _50V8J~D

150P_ 0402 _50V8J~D

12

1 2

PR93 9 1_ 0603 _1%~DP R939 1_06 03_1 %~D

PHASE1G

PC71 3

PC71 3

12

0.22U _0603 _10V7K

0.22U _0603 _10V7K

LGATE1G

PT12

PT12
PAD~D

PAD~D

@

@

PT13

PT13
PAD~D

PAD~D

@

@

9

9

PR72 1@

PR72 1@

0_04 02_5% ~D

0_04 02_5% ~D

12

SHORT

1 2

12

PC718

PC718

1U_0603_10V6K~D

1U_0603_10V6K~D

PR73 4

PR73 4

42.2K_ 0402 _1%~D

42.2K_ 0402 _1%~D

1 2

UGATE1

1 2

PR74 2

PR74 2

2.2_06 03_5 %~D

2.2_06 03_5 %~D

PC719

PC719

1U_0603_10V6K~D

1U_0603_10V6K~D

SHORT

PR72 2

@PR 722

@

0_06 03_5% ~D

0_06 03_5% ~D

CPU_ B+

1 2

PR94 0 1_0 603_1 %~DP R940 1_060 3_1% ~D

PHASE1

PC74 0

PC74 0

0.22U _0603 _10V7K

0.22U _0603 _10V7K

12

LGATE1

PWM3
LGATE1
PHASE1
UGATE1

PR72 8

PR72 8

PR72 4

PR72 4

100P_ 0402 _50V8J~D

100P_ 0402 _50V8J~D

PR73 8

PR73 8
30K_0 402_ 1%~D

30K_0 402_ 1%~D

PR74 0

PR74 0

VCCSEN SE [9]

VSSSENSE [9]

3

12

1_06 03_5%

1_06 03_5%

+3VS

PC72 9

PC72 9

12

12

12

PC73 0

PC73 0

150P_ 0402 _50V8J~D

150P_ 0402 _50V8J~D

1 2

PC73 3

PC73 3

470P_ 0402 _50V8J~D

470P_ 0402 _50V8J~D

BOOT1

12

+5VS

VGATE [18,35 ]

1 2

2K_04 02_1 %~D

2K_04 02_1 %~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PT16

PT16
PAD~D

PAD~D

@

@

PT17

PT17
PAD~D

PAD~D

@

@

1

D2/S1

8

2

4

3

2

FDMS366 0S

FDMS366 0S

D1

D1

D1

G1

PQ121 7

PQ121 7

10

D1

S2

S2

S2

G2

6

7

5

PT14

PT14
PAD~D

PAD~D

@

@

+5VS

36

PJP701

@ PJP70 1

@

2

112

JUMP_43 X118

JUMP_43 X118

1

2

D1

G1

9

D2/S1

S2

G2

7

8

2

3

6

PT11

PT11

PAD~D

PAD~D

@

@

D1

S2

D1

4

5

PT18

PT18
PAD~D

PAD~D

@

@

D1

S2

GFX_B+

12

12

12

PC747

PC747

PC705

PC705

PC704

PC704

PC748

PC748

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

NA CIS

12

PR711

PR711

4.7_1206_5%~D

4.7_1206_5%~D

12

PC715

PC715

680P_0402_50V7K~D

680P_0402_50V7K~D

PR71 4

PR71 4

3.65K_ 0603 _1%~D

3.65K_ 0603 _1%~D

VSUMG+

VSUMG-

VCC_GFX C_AXG
TDC 21. 5A
Peak Cu rrent 2 9A
OCP cur rent 39. 6A

CHOCK D CR 0.97m ohm

H/S Rds (on) :8. 5mohm , 11mohm
L/S Rds (on) :1. 8mohm , 2.2mohm

VCC_cor e
TDC 16A
Peak Cu rrent 3 3A
OCP cur rent 39. 6A

CHOCK D CR 0.97m ohm

B+

H/S Rds (on) :8. 5mohm , 11mohm
L/S Rds (on) :1. 8mohm, 2.2mohm

CPU_ B+

12

12

PC749

PC749

PC734

PC734

PC750

PC750

PT15

10

PT15

PAD~D

PAD~D

@

@

FDMS366 0S

FDMS366 0S
PQ121 8

PQ121 8

NA CIS

PR743

PR743

4.7_1206_5%~D

4.7_1206_5%~D

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D
2200P_0402_50V7K~D

2200P_0402_50V7K~D

12

3.65K_ 0603 _1%~D

3.65K_ 0603 _1%~D

12

PC744

PC744

VSUM+

680P_0402_50V7K~D

680P_0402_50V7K~D

VSUM-

Title

Title

Title

Size D ocum ent Nu mbe r Re v

Size D ocum ent Nu mbe r Re v

Size D ocum ent Nu mbe r Re v

Date: Sheet

Date: Sheet

Date: Sheet

1

@ PJP70 0

@

2

12

12

12

PC709

PC709

PC1908

PC1908

JUMP_43 X118

JUMP_43 X118

@

@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PL701

PL701

0.22U H_FDU E0640 J-H_25 A_20%~ D

0.22U H_FDU E0640 J-H_25 A_20%~ D

1

4

3

2

12

PR71 5

PR71 5
1_04 02_5% ~D

1 2

1_04 02_5% ~D

TYP MAX

TYP MAX

12

12

PC1909

PC1909

12

12

PC735

PC735

PC736

PC736

@

@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PL704

PL704

0.22U H_FDU E0640 J-H_25 A_20%~ D

0.22U H_FDU E0640 J-H_25 A_20%~ D

4

3

PR74 7

PR74 7

1 2

Compal Electro nics, Inc.

Compal Electro nics, Inc.

Compal Electro nics, Inc.

P44-PWR-CPU_CORE

P44-PWR-CPU_CORE

P44-PWR-CPU_CORE

LA-8821P

LA-8821P

LA-8821P

1

36

PJP700

112

+VCC_GFXC ORE_AXG

1

2

12

PR74 9

PR74 9
1_04 02_5% ~D

1_04 02_5% ~D

44 54Friday, Sep temb er 28, 20 12

44 54Friday, Sep temb er 28, 20 12

44 54Friday, Sep temb er 28, 20 12

B+

+VCC_C ORE

of

of

of

1.0

1.0

1.0

5

D D

Below is 458544_CR_PDDG_0.8 Table 7-1.

+VCC_CORE

12

PC12 38

PC12 38

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 40

PC12 40

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 32

PC12 32

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

28

1

PC86 0

PC86 0
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

12

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

1

2

12

12

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

2.2U _04 02 _6.3 V6 M~D

C C

2.2U _04 02 _6.3 V6 M~D

PC12 37

PC12 37

PC12 33

PC12 33

PC12 39

PC12 39

PC12 36

PC12 36

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 28

PC12 28

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 35

PC12 35

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

+VCC_CORE

1

1

PC85 8

PC85 8

PC85 9

PC85 9

22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

22U_ 08 05_ 6.3 V6M ~D

2

PC12 25

PC12 25

PC12 34

PC12 34

PC12 31

PC12 31

PC86 1

PC86 1
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

4

+VCC_CORE

12

PC12 27

PC12 27

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 29

PC12 29

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

12

PC12 30

PC12 30

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

1

PC86 2

PC86 2
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

12

PC12 26

PC12 26

2.2U _04 02 _6.3 V6 M~D

2.2U _04 02 _6.3 V6 M~D

3

2

Below is 458544_CR_PDDG_0.8 Table 7-4. Below is 458544_CR_PDDG_0.8 Table 7-7.

+VCCP+VCC_GFXCORE_AXG

+VCC_GFXCOR E_AXG

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

PC851

PC851

PC850

PC850

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1257

PC1257

PC1256

PC1256

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1286

PC1286

PC1285

PC1285

12

12

28

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

PC852

PC852

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1258

PC1258

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1287

PC1287

12

12

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

PC853

PC853

PC854

PC854

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1259

PC1259

PC1260

PC1260

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1289

PC1289

PC1288

PC1288

12

@

@

PC855

PC855

PC856

PC856

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1261

PC1261

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1290

PC1290

12

+VCCP

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

PC1268

PC1268

PC1273

PC1273

PC1272

PC1272

12

12

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1266

PC1266

PC1267

PC1267

PC1262

PC1262

12

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1298

PC1298

PC1301

PC1301

PC1302

PC1302

12

12

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1269

PC1269

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

PC1263

PC1263

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1297

PC1297

@

@

PC1271

PC1271

PC1270

PC1270

12

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

PC1264

PC1264

PC1265

PC1265

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1299

PC1299

PC1300

PC1300

12

12

12

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1303

PC1303

PC1305

PC1305

PC1304

PC1304

12

12

1

PC89 0

PC89 0
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

PC91 6

PC91 6
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

B B

2

+VCC_CORE

1

+

+

PC980

PC980

2

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

Output Decoupling Recommendations
VCORE

1.330uF_6mohm*3 (near VR)

2.22uF*12 (Between VR&CPU)

3.2.2uF*16 (Bottom of CPU)

A A

5

1

PC89 1

PC89 1
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

PC91 3

PC91 3
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

+

+

PC984

PC984

2

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

1

PC89 2

PC89 2
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

@

@

PC91 4

PC91 4
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

PC89 3

PC89 3
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

@

@

PC91 5

PC91 5
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

+

+

2

PC986

PC986

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

1

PC89 4

PC89 4
22U_ 08 05_ 6.3 V6M ~D

22U_ 08 05_ 6.3 V6M ~D

2

1

+

+

PC993

PC993

2

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1312

PC1312

PC1311

PC1311

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1295

PC1295

PC1294

PC1294

12

12

12

1

1

+

+

+

+

PC987

PC987

PC994

2

1

1

+

+

+

+

PC1901

PC1901

PC1900

PC1900

2

2

@

@

@

@

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

Output Decoupling Recommendations
iGFX

1.470uF_4.5mohm*2 (near VR)

2.22uF*6 (Between VR&CPU)

3.10uF*6 (Between VR&CPU, near CPU)

4.1uF*11 (Bottom of CPU)

PC994

2

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

1

+

+

PC1903

PC1903

2

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@

PC1291

PC1291

PC1292

PC1292

12

330U_D2E_2VM_R6M

330U_D2E_2VM_R6M

3

@

PC1293

PC1293

PC1296

PC1296

12

12

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Output Decoupling Recommendations
VCCP_1.05V

1.330uF_6mohm*2 (near VR)

3.10uF*10 (Between VR&CPU)

4.1uF*27 (Bottom of CPU)

2

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1321

PC1321

PC1320

PC1320

12

12

12

1

+

+

PC990

PC990

2

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1307

PC1307

PC1310

PC1310

PC1309

PC1309

PC1308

PC1308

12

12

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

+

+

2

PC1318

PC1318

PC1319

PC1319

PC1316

PC1316

PC1317

PC1317

12

12

12

PC991

PC991

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

12

1

+

+

PC995

PC995

2

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P45-PWR_PROCESS OR DECOUPLING

P45-PWR_PROCESS OR DECOUPLING

P45-PWR_PROCESS OR DECOUPLING

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Size D ocum en t Nu mb er Rev

Date : She et

Date : She et

Date : She et

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1314

PC1314

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1323

PC1323

LA-8821P

LA-8821P

LA-8821P

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1313

PC1313

PC1306

PC1306

12

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

PC1322

PC1322

PC1315

PC1315

12

12

45 54Frida y, S ep tem ber 28, 20 12

45 54Frida y, S ep tem ber 28, 20 12

45 54Frida y, S ep tem ber 28, 20 12

of

of

1

of

1.0

1.0

1.0

A

B

C

D

E

PCH_SMBCLK

PCH_SMBDATA

+3VS

+3VS_WLAN

+3VNS_PWR

2.2K2.2K

2.2K2.2K

2.2K2.2K

e-Compass +
Accelerometer

Pressure Sensor

DIMM Channel A SPD ROM

DIMM Channel B SPD ROM

Touch Pad

WLAN

+3V_PCH

1 1

SMBUS Address [0x9a]

H14

SMBCLK

SMBDATA

C9

PCH

2.2K2.2K

+3V_PCH

2.2K2.2K

C8

SML0CLK

SML0DATA

G12

SML1CLK

SML1DATA

PCH_SMLCLK

PCH_SMLDATA

2.2K

+3V_PCH

2.2K

2.2K

0-ohm

0-ohm

+3VS

2.2K

2 2

+3VS

E14M16

DMN66D0 DMN66D0

A6 B8

NFC

ALS

@0-ohm@0-ohm

@0-ohm

+3VS

DMN66D0

DMN66D0

@0-ohm

@0-ohm

+3VS_WLAN

DMN66D0

DMN66D0

@0-ohm

Sensor HUB

Gyro Sensor

3 3

KBC

A8

A7

EC_SMB_CK1

EC_SMB_DA1

+3VALW_EC

2.2K2.2K

0-ohm

0-ohm

100-ohm

100-ohm

9

Charger

8

3

BATTERY

4

CONN

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P46-SMBus Block Diagram

P46-SMBus Block Diagram

P46-SMBus Block Diagram

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Date : She et of

Date : She et of

Date : She et of

46 54Fri da y, S epte mb er 2 8, 201 2

46 54Fri da y, S epte mb er 2 8, 201 2

46 54Fri da y, S epte mb er 2 8, 201 2

E

1.0

1.0

1.0

5

[AC in]

Vin

ACIN

Ta

B+

Tb

+3VLP

EC_ON

D D

C C

B B

A A

+5VALW

+3VALW

+VSBP

+3V_PCH_DSW Th

PCH_DPWROK Ti

PM_SLP_SUS # Tj

+3V_PCH/+5V_ PCH Tk

PBTN_SW#

Output

PCH_RSMRST#

SUSCLKPCH Output

Output

AC_PRESENT

Output

PBTN_OUT#

PCH_SUSWARN#

Output

SUSACK#

Input

PM_SLP_S5 #

Input

PM_SLP_S4 #

Input

Output

SYSON

+1.35V

+1.5V_PWROK

PM_SLP_S3 #Input

Output

SUSP#

+5VS

+3VS

POK

+1.5VS

+1.5VS_PWROK

+1.8VS

+1.8V_PWROK

+VCCP

+V1.05S_ VCCP_PWRGOOD

+VCCSA

SA_PGOOD

CPU1.5V_S3_ GATEOutput

+1.35V_CPU_ VDDQ

+0.675VS

Input

HWPG

VR_ON

Output

PCH_PWROK

Output

PM_DRAM_PWRGD

PCH Output

H_CPUPWRGD

SVID

+VCC_CORE

VGATEInput

SYS_PWROK

PCH_PLTRST#

PCH Output

Tc

Td

Te

Tf

Tg

1ns < Tl < 4s

T1

T2

T3 < 90ms

16ms < T4 < 4s

Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable

T5

T6

T7

30us < T8

T9

T10

T11

T12

30us < T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

5

4

[Battery only, AC absent]

B+

PBTN_SW#

EC_ON

+5VALW

+3VALW

+VSBP

+3V_PCH_DSW

PCH_DPWROK

PM_SLP_SUS #

+3V_PCH/+5V_ PCH

T23

T24

T25

T26

T27

4

3

EC pay attention timing

Tc+ 3VLP

1ns < Tl < 4s

Td

Te

Tf

Tg

Th

Ti

Tj

Tk

T28

T29

99ms < T30

T31

T32

5ms > T33

T34

T35

T36

T37

3

Discrete Power On Sequence

Ta

VIN

Tb

B+

Tc
Td

EC_ON +5VALW

Te

EC_ON

Tf

EC_ON

Tg

EC_ON

Th

+3V_PCH_DSW

Ti

PCH_DPWROK

Tj

PM_SLP_ SUS# +3V _PCH/+5V_PCH

Tk

PBTN_SW#

Tl

ITEM Measure Point

PBTN_SW#

T1

PCH_RSMRST# SUSCLK

T2

PCH_RSMRST# AC_PRES ENT

T3
T4

PCH_RSMRST#

T5

PCH_SUSWARN#

T6

SUSACK# PM_SL P_S5#

T7

PM_SLP_ S5# PM_ SLP_S4#

T8

PM_SLP_ S4# SYSO N

T9
T10

+1.35V

T11

PM_SLP_ S4# PM_ SLP_S3#

T12

PM_SLP_ S3# SUSP#

T13

SUSP# +5V S

T14

SUSP#

T15

+3VS POK

T16

SUSP#

T17

+1.5VS +1.5 VS_PWROK

T18

SUSP# +1. 8VS

T19

+1.8VS +1.8 V_PWROK

T20

SUSP# +VCCP

T21

+VCCP

T22

+V1.05S_VCCP_PWRGOOD

T23

+VCCSA SA_PGOOD

T24

SUSP#

T25

CPU1.5V_S3_ GATE +1 .35V_CPU_VDDQ

T26
T27

SA_PGOOD

T28

HWPG VR_ON

T29

HWPG PCH_PWROK

T30
T31
T32

VR_ON SVID

T33

H_CPUPWRGD +VCC_CORE

T34
T35
T36

SYS_PWROK PCH_PLTRST #

T37

2

[AC in]

ACINVIN

To

B+

To

+3VLP

To

EC_ON+3VLP

To
To

+3VALW

To

+VSBP

To

+3V_PCH_DSW

To

PCH_DPWROK

To

PM_SLP_ SUS#

To
To

Low pluse wi dth

PCH_RSMRST#

To
To
To

Low pluse wi dthPB TN_OUT#

To

PCH_SUSWARN#

To

SUSACK#

To
To
To
To

+1.35VS YSON

To

+1.5V_PWROK

To
To
To
To

+3VS

To
To

+1.5VS

To
To
To
To
To

+V1.05S_VCCP_PWRGOOD

To

+VCCSA

To
To

CPU1.5V_S3_ GATE

To
To

+0.675VSCPU1.5V_S3 _GATE

To

HWPG

To
To
To

PM_DRAM_P WRGDPCH_PWROK

To

H_CPUPWRGDPM_DRAM_PWRGD

To
To
To

VGATE+VCC_CORE

To

SYS_PWROKVGAT E

To
To

TimeMeasure PointITEM

N/A

Time

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

2

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

[Battery only, AC absent]

B+

Tc
Tl

+3VLP EC_ON

Td

EC_ON

Te

EC_ON

Tf

EC_ON

Tg

EC_ON +3V_PCH_DSW

Th

+3V_PCH_DSW

Ti

PCH_DPWROK

Tj

PM_SLP_ SUS# +3V _PCH/+5V_PCH

Tk

Com pal Se cret Data

Com pal Se cret Data

Com pal Se cret Data

Deciphered Date

Deciphered Date

Deciphered Date

Measure PointITEM Tim e

To
To

+3VLP

To
To
To

+5VALW

To

+3VALW

To

+VSBP

To
To

PCH_DPWROK

PM_SLP_ SUS#

Title

Title

Title

Size Doc ument Nu mber Rev

Size Doc ument Nu mber Rev

Size Doc ument Nu mber Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

N/AP BTN_SW# Low plu se width

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

P47-Power Sequence

P47-Power Sequence

P47-Power Sequence

1

of

47 54Friday, Septemb er 28, 2012

of

47 54Friday, Septemb er 28, 2012

of

47 54Friday, Septemb er 28, 2012

1.0

1.0

1.0

5

Item Issue Des cript ionDate

1

D D

C C

B B

A A

24 eDP/ Camera CONN 2012 -03-02 Compal_Vicent eDP touch sreen's power missing in BBU stage R1084 BOM structure is "@" (de-pop), change to POP X01

35 EC ENE-KB9012 2012-03-05 Compal_Vicent Debug power switch un-work, short to GND

3 35 EC ENE-KB9012 201 2-03-05 Compal_Vicent Insert USB device into power share port, the 3V/5V can't power-on automatic in S5/DC mode R922 need de-pop to avoid become voltage divider with R938 and PD906 X01

4 35 EC ENE-KB9012 201 2-03-05 Compal_Vicent WLAN power will be turn-on a short time while adapter plug in WLAN_EN# signal PU resistor R101 2 need pop to prevent Hi-Z state while EC during initial state X01

Sensor Fussion / TPM27 2012-03-065 Compal_Vicent Wrong power rail on Gyro sensor VDD_IO pin Correct Gyro sensor U638 VDD_IO power from +3VS to +3VNS_PWR X01

6 27 Sensor Fussion / TPM 2012-03-07 Compal_Vicent Follow Intel Sensor HUB HWDG v0.5 to modify design

067CPU(2/6) PM,XDP,CLK,S3,PLT

18 PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (7/8) PWR2 2 5. Pop RH312, De-pop RH214, PCH VCCDSW change to +3VALW

EC ENE-KB901235 6. R225 value change to 8.2K, Change Board ID to 1 for identify Deep S3 suuport PCBA

8 Sensor Fussion / TPM27 2012-03-12 Compal_Vicent Change e-Compass, Gyro, Pressure sensor to DELL P/N

27 Sensor Fussion / TPM

9

17 PCH (2/8) PCIE, SMBUS, CLK 2. Follow Vendor EA result, change 25MHz crystal Capacitor value 2. CH23 and CH24 value change from 15pF to 12pF

10 24 eDP/ Camera CONN 2012-03-15 Compal_Vicent Win8 Button doens't work, Double PU in P24 and P35 on net Win8_BTN_SW# Page24 R977 de-pop, R978 change from 10K to 1K X01

PCH (6/8) PWR

21

PCH (7/8) PWR

22

IOL Conn

25

12

13

14

15

16 5 CPU(1/6) DMI,FDI,PEG 20 12-03-28 Compal_Jay Update CPU to L-1 P/N Update CPU to L-1 P/N(i5-3317U/i5-3427U/i7-3517U/i7-3667U) X01

17

18 2012-04-02 Compal_Jay Add TPM BOM Optional (PCH_GPIO16), PU=WTPM/PD=W/O TPM

19

20

Sensor Fussion / TPM27

29 mSATA / NFC Conn

PCH (5/8) GPIO, CPU, MISC

2720Sensor Fussion / TPM

19

PCH (4/8) PCI, USB, NVRAM

20 PCH (5/8) GPIO, CPU, MISC

17

PCH (2/8) PCIE, SMBUS, CLK

19 PCH (4/8) PCI, USB, NVRAM

17 PCH (2/8) PCIE, SMBUS, CLK

29

mSATA / NFC Conn

20 PCH (5/8) GPIO, CPU, MISC

Sensor Fussion / TPM27

PCH (3/8) DMI,FDI,PM,GFX,DP18

35 EC ENE-KB9012

17 PCH (2/8) PCIE, SMBUS, CLK

29

mSATA / NFC Conn

5

2012-03-09 Compal_Vicent Change design to support Deep S3

2012-03-15 Compal_Vicent

2012-03-20

2012-03-21 Compal_Vicent Sensor HUB JDG1 is interference to ME design

2012-03-22

2012-03-22 Compal_Mandy Rotation Lock signal change connect from PCH GPIO48 to GPIO14Rotation lock can't detect by event trigger method X01

2012-03-23 Compal_Mandy Follow BIOS team suggestion, change EC_LID_OUT# connection from GPIO11 to GPIO10

2012-03-28 Compal_Jay Follow Intel NFC review result

2012-04-02 Compal_Jay

2012-04-03 Compal_Jay Modify net name from NFC_IRQ# to NFC_IRQ. X01Modify net name from NFC_IRQ# to NFC_IRQ.

4

3

Version Change List ( P. I. R. List )

Request
Owner

1. Follow Vendor EA result, change 8MHz crystal Capacitor value 1. C1204 and C1204 value change from 18pF to 27pF

Compal
Procurement

Intel &

Compal_Vicent

Change all TAIYO bead to MURATA

Follow Intel Sensor HUB design DG0.5, remove SBD_INT# connection to PCH

Intel DS3 known issue,
if GPIO11 drive low in DS3 then re-inserted AC the system will wake-up all way.

For meet ErP Lot 6, remove PM_SLP_S4# (PCH side) connection to EC. X01

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

3

2

Page 1

SW2 OrCard symbol is d ifferent with specification
Correct SW2 symbol

1. Sensor HUB uC (U636) VBAT power change from +RTCVCC to +3VALW power

2. Sensor HUB load switch power rail change from +3VALW to +3VS

1. De-pop RC72, Pop RC145 and R1035, DRAM_RST# gated by EC

2. Pop RH313, PCH Suspend power rail control by PCH

3. Pop RH310, De-pop RH128, Wake-up event change connect to PCH GPIO27

4. Pop RH309, De-pop RH126, PCH DPWROK change to +3VALW PG

1. U637 P/N change from SA00004MI00 to SA0000 4MI0L

2. U638 P/N change from SA00005HQ00 to SA000 05HQ0L

3. U653 P/N change from SA00004TT00 to SA0000 4TT0L

P21, LH3

P22, LH4, LH6, LH7, LH8

P25, LH9

Connect U636 JTAG interface to mSATA mini-card JSATA1

Pop R1090 0-ohm

Remove SBD_INT# connection to Sensor HUB uC and rename to PCH_GPIO15

Add Test poin on SBD_INT# net

Page17 R517 de-pop.

Page29 1. add R11 00 100K PD. 2. de-pop R973. 3. Pop R974 and change from 10K to 0 ohm.

1.Remove PM_SLP_S4# connection to EC and add test poin. 2.Rename POK to EC_DPWROK.

Rename PM_SLP_S4# to EC_DPWROK.

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

Solution Description Rev.Page# Tit le

X012

X01

X01

X01

X01

X0111

X01

X01

X01

X01

X01TPM@=support TPM, NTPM@=without TPM

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P48-EE-PIR-X01-P1

P48-EE-PIR-X01-P1

P48-EE-PIR-X01-P1

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t of

Date: Shee t of

Date: Shee t of

48 54Frida y, Septem ber 28, 2 012

48 54Frida y, Septem ber 28, 2 012

48 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

5

Item Issue Des cript ionDate

21

38 X01

D D

22 44 PWR-CPU_CORE 2012-04-05 Power_Jeff Follow intersil EA test result,modify PR737 form 1 .91K to 2.0K for CPU Load Line. Modify PR737 form 1.91K to 2.0K for CPU LL

23 44 PWR-CPU_CORE 2012-04-05 Power_Jeff Modify GFXC_ core and CPU_core TDC and OCP current note VCC_ GFXC_AXG TDC from 20.3A -->21.5A

25 1835PCH (3/8) DMI,FDI,PM,GFX,DP

26 27 Sensor Fuss ion / TPM 2012-04-09 Compal_Jay Follow TXC crystal EA report Follow TXC EA report modify CH1202/CH1203 from 6.8PF to 18PF

27 16 PCH (1/8) SATA,HDA,SPI, LPC 2 012-04-09 Compal_Jay Follow TXC crystal EA report X01Follow TXC EA report modify CH2/CH3 from 18PF to 22PF

28 35 EC ENE-KB9012 2012-04-09 Compal_Jay Modify board ID to Revision : X01 Modify R225 from 8.2K to 18K X01

29 38 PWR_ Charger(ISL9519) 201 2-04-09 Power_Jeff Follow Charg er EA, modify swiching frequence to slow Change PL1211 form 1uH to 3.3uH

C C

30 44 PWR-CPU_CORE 2012-04-09 Power_Jeff Follow intersil EA test result, modify CPU OCP Value. change PR748 from 422 to 442 ohm

31 44 PWR-CPU_CORE 2012-04-09 Power_Jeff Follow intersil EA test result, modify value for CPU compensator. Change PC729 from 47p to 100pF X01

32 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

33 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

34 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

35 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

36 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

37 44 PWR-CPU_CORE 2012-04-09 Power_Jeff

38 39 PWR_ 3.3VALWP/5VALWP-8243 2012-04-09 Power_Jeff Modify SECFB connection to LDO3 (DEM) Change PR514 form 0ohm to NC

39 39 PWR_ 3.3VALWP/5VALWP-8243 2012-04-09 Power_Jeff For 3/5V can't turn-off in S5 state while system change form AC to DC mode Change PC217 form 2 .2uf to NC

B B

40 42 PWR_ 3.3VALWP/5VALWP-8243 2012-04-09 Power_Jeff Avoid +1.35V output noise affect FB sensor result, modify net name from +1.35V to +1.35VS Modify net name from +1.35V to +1.35VS

41 11

42 16~23 PCH (1/8) SATA,HDA,SPI, LPC 201 2-04-10 Compal_Jay Modify PCH P/N for PT build SA00005L31L : S IC BD82QS77 SLJ8B C1 BGA 1017 PCH

43 42 PWR_ +1.35VP/0.675VSP 2 012-04-10 Power_Jeff Deley +1.35V and +0.675V sequece timing Change PR323 form 0ohm to 1Kohm add CAP 0.1uF connect PR323 to GND

44 38 PWR_ Charger(ISL9519) 201 2-04-10 Power_Jeff Reduce ADP_I slew rate too slow Change PC38 form 0.1uF to 0.01uF

45 27 Sensor Fuss ion / TPM 2012-04-11 Compal_Jay Remove Pressure Sensor function for PT build De-pop U653,D96,D97,C1148,C1149 and R1093 X01

46

A A

47 39 PWR_ 3.3VALWP/5VALWP-8243 Power_Jeff2012-04-11 Follow buyer suggest modify 10UF CAP CPN Modify PC222 CPN to SE000004 880 X01

PWR_Charger(ISL951 9) 2012-04-05 Power_J eff Add 0 ohm for EC_SMB_DA1 and EC_SMB_CK1 for charger test. Add 0 ohm for EC_SMB_DA1 and EC_SMB_CK1 for charge test.

33 SCREWH/KB/RTC 2012 -04-09 Compal_Jay Follow ME dxf file update24 Delete H15 and add H21 EMI_spring

EC ENE-KB9012

DDRIII Channel_A Lower

12

DDRIII Channel_A Upper

13

DDRIII Channel_B Lower

14

DDRIII Channel_B Upper

16 PCH (1/8) SATA,HDA,SPI, LPC

27 Sensor Fussion / TPM

5

2012-04-09 Compal_Jay Follow EC suggest modify back PM_SLP_S4# connection to EC.

2012-04-10 Compal_Jay Modify DDR3L P/N for PT build

2012-04-11 Compal_Jay Follow buyer suggest modify 32.768 crystal CPN Modify Y1 and YH1 CPN to SJ1000 0BM00

4

3

Version Change List ( P. I. R. List )

Request
Owner

Follow intersil EA test result, modify value for CPU compensator.

Follow intersil EA test result, modify GFX OCP value.

Follow intersil EA test result,modify PR737 form 1.91K to 2.0K for GFX Load Line.

Follow intersil EA test result, modify value for GFX compensator.

Follow intersil EA test result, modify value for GFX compensator.

Follow intersil suggest, change input caps from 4.7uF to 10uF.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

3

2

Page 2

OCP current from 34.5A to 39.6A

VCC_Core TDC from 23A -->16A

OCP current from 39A to 39.6A

1. Follow EC suggest modify back PM_SLP_S4# connection to EC.. 2.Modify EC_DPWROK back to POK. X01

Modify C_DPWROK back to PM_SLP_S4#.

Change PR738 from 267K to 220K ohm X01

change PR712 from 360 to 392 ohm

Change PR702 from 2.26K to 2.55K ohm

Change PC708 from 47p to 100pF

Change PR703 from 267K to 220K ohm

Change PC704,PC705,PC709,PC734,PC735,PC736 form 4.7uF to 10uF

Add PC1908, PC1909 to 10uF de-pop

Change PR515 form NC to 0ohm

MICRON 2Gb/1600/42nm :SA00005PR0L

MICRON 4Gb/1600/30nm :SA00005SO0L

HYNIX 2Gb/1600/38nm :SA00004R G0L

HYNIX 4Gb/1600/38nm :SA00005J T0L

SAMSUNG 2Gb/1600/35nm :SA00005P90 L

SAMSUNG 4Gb/1600/35nm :SA00005AT0L

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

Solution Description Rev.Page# Tit le

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P49-EE-PIR-X01-P2

P49-EE-PIR-X01-P2

P49-EE-PIR-X01-P2

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t

Date: Shee t

Date: Shee t

49 54Frida y, Septem ber 28, 2 012

49 54Frida y, Septem ber 28, 2 012

49 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

of

of

of

5

Item Issue Des cript ionDate

42

48

D D

49 39 PWR_ 3.3VALWP/5VALWP-8243 2012-04-11 Power_Jeff Combine the P/N Modify PD906,PD907 and PD903 P/N to SCS00000Z00 X01

50 44 2012-04-12 Power_Jeff Modify P/N to Green part PC708,PC729 change material form SE071101K8L to SE071 101J8L. X01PWR-CPU_CORE

51 27 Sensor Fuss ion / TPM 2012-04-16 Compal_Jay Option +3VALW and +RTCVCC for Sensor hub Vbat pin and default is +3VALW. Add R11 01 and R1102 for option +3VALW and +RTCVCC.

52 27 Sensor Fuss ion / TPM 2012-04-16 Compal_Jay Follow Intel suggest, pin 4 change from floating to GND. U638 pin 4 change from floating to GND.

53 29 mSATA / NFC Conn 2012-04-17 Compal_Jay mSATA don't need +5VS power,remove +5VS power rail from JSATA1 connector. Remove +5VS power rail

54 24 eDP/ Camera CONN 2012-04-18 Compal_Jay Add soultion for EMI fix DMIC noise issue R537 change to 100-ohm, C1133 pop 10pF and add C120 6 pop 10pF.

55 22 PCH (7/8) PWR 2012-04-18 Compal_Jay Modify P/N to COMMON part H=1.9 Modify CH86 and CH88 P/N to SGA0000170L

56 37 PWR_ DCIN / BATT CONN / OTP 201 2-04-19 Power_Jeff IPCC/ VC_IN function support De-pop PR937 and PR936 change to 0-ohm

57 30 PWR_ DCIN / BATT CONN / OTP 201 2-04-19 Compal_Jay Follow ME new connector list X14, modify JUSB2 P/N Change JUSB2 P/N to ACON_TARAG-9V1391

58 37 PWR_ DCIN / BATT CONN / OTP 201 2-04-20 Power_Jeff For fix EMI LX_ 3V and LX_5V nets cause the boardband noise X01Pop PR208,PR209, PC212,PC213

C C

59 35 EC ENE-KB9012 2012-04-20 Compal_Jay Change FAN to PWM control

60 34 TP / FAN 2012-04-20 Compal_Jay Change FAN to PWM control F ollow Thermal team request, change FAN to PWM control circuit. X01

61 38 PWR_ Charger(ISL9519) 201 2-04-20 Power_Jeff Remove ACOFF due to add FAN PWM control and BMON function Remove ACOFF net and add test PAD X01

62 39 PWR_ 3.3VALWP/5VALWP-8243 2012-04-23 Power_Jeff For B+ drop issue 1. Change PC203,PC204 form 4.7uF to 10uF

63 41 PWR_ V1.05S_VCCPP 2012-04-23 Power_Jeff For B+ drop issue Change PC502,PC503 form 4.7uF to 10uF X01

64 42 PWR_ +1.35VP/0.675VSP 2 012-04-23 Power_Jeff For B+ drop issue Change PC300,PC302 form 4.7uF to 10uF X0 1

65 42 PWR_ +1.35VP/0.675VSP 2 012-04-23 Power_Jeff For consider test efficiency Connect PR119 +1.35VS channge to +1.35V X01

B B

66 43 PWR_ +VCCSAP 2012-04-23 Power_J eff For adjustment voltage from 0.8V to 0.85V Change PR607 form 3 3K to 100K

67 38 2012-04-23 Power_Jeff Add Battery Current Sensor functionPWR_Charger(ISL9519) Add Battery Current Sensor - BMON circuits

68 26 Mini DP CONN 2012-04-23 Compal_Jay Follow ME new connector list X14, modify JMDP1 P/N Change JMDP1 P/N to ACON_MAR2B-20K1200 X01

69 31 BAT LED 201 2-04-24 Compal_Jay F ollow DELL request, modify SW1 P/N Change SW1 P/N to SN100006U0L X01

70 38 2012-04-25 Power_JeffPWR_Charger(ISL9519) Disable Reserved circuit for DT mode charger R emove reserved circuit for DT mode charger X01

71 37 2012-04-25 Power_JeffPWR_DCIN / BATT CONN / OTP Follow EMI request, add one bead on DC-IN GND pin Add PL903 on DC-IN GND pin X01

72 34 TP / FAN 2012-04-25 Compal_Jay Follow DELL suggest, modify JFAN1 P/N same with WIN8/B connector Change JFAN1 P/N to SP02000Y500 X 01

74 42 PWR_ +1.35VP/0.675VSP 2 012-04-25 Power_Jeff because 2nd Footprint is big size then main source,we suggest modify footprint in PT PQ1226 change Footprint form AON7212L_DFN8-5 to FDMC7672S _MLP8-5 X01

75 30 PWR_ DCIN / BATT CONN / OTP 201 2-04-25 Compal_Jay Follow ME new connector list X15, modify JUSB2 P/N Change JUSB2 P/N from ACON_TARAG-9V1391 to ACON_TARAG-9U1391

76 32 DC/DC Interface 2012-04-26 Compal_Jay For BBU measurement Add R894 on +3VALW to +3V_PCH, +5VALW to +5V_PCH

A A

77 29 mSATA / NFC Conn 2012-04-26 Compal_Jay Follow ME new connector list X15, modify JNFC1 P/N from temp P/N to CPN Update JNFC1 P/N to SP01001HI00 (CIS part) X01

PWR_+1.35VP/0.675VSP

39 PWR_3.3VALWP/5VALWP-8243

2012-04-11 Power_ Jeff Follow buyer suggest, modify 100pf CPN Modify PC129 ,PC220 and PC314 P/N to SE071101J 8L

4

3

Version Change List ( P. I. R. List )

Request
Owner

Add BMON function

Follow power team schematic review result73 39 PWR_ 3.3VALWP/5VALWP-8243 2012-04-25 Power_Jeff De-pop PR958 X01

2

Page 3

Solution Description Rev.Page# Tit le

1.Change GPIO13 from ACOFF to SYSTEM_FAN_PWM

2.Remove ACOFF PD R1022

3.Change GPI39 from VOLUME_UP_SW# to BMON

4.Change GPO3D from EN_DFAN1 to VOLUME_UP_SW#

2. Add PC1912,PC1913 and PC1917 of X5R 08 05 10uF to B+ connect GND

3. De-pop PC210,PC211

4. Add PR957(1 0Kohm), PR958 (100K ohm) ,PC1911 (2.2uF) and PD909

1

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

X01

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

5

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P50-EE-PIR-X01-P3

P50-EE-PIR-X01-P3

P50-EE-PIR-X01-P3

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t

Date: Shee t

2

Date: Shee t

50 54Frida y, Septem ber 28, 2 012

50 54Frida y, Septem ber 28, 2 012

50 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

of

of

of

5

Item Issue Des cript ionDate

D D

79

29 mSATA / NFC Conn 2012-04-27 Compal_Jay Remove NFC function De-pop C1134 and R974 X0 1

80 38 PWR_ Charger(ISL9519) 201 2-05-02 Power_Jeff For fix d erating issue Change PR942 1Kohm to 3.3K ohm X01

81 45 PWR_ PROCESSOR DECOUPLING 2012-05-03 Power_Jeff Main source(SANYO) can't supply so modify to other supplier Change PC987,PC994,PC190 0,PC1901 and PC1903 form S GA00002U00 to SGA00006A00. X01

82 27 Sensor Fuss ion / TPM 2012-06-05 Compal_Jay Follow Intel reference design Reserved R11 04 10 Kohm between USB_PP and uC PB5 X01.1

1 16 PCH (1/8) SATA,HDA,SPI, LPC 2012-06-21 Compal_Jay WINBOND SPI ROM have issue on other project, remove WINBOND from schematic. Change U48 P/N from SA000 039A2L to SA000046400 (EON) X02

2 20 PCH (5/8) GPIO, CPU, MISC 2012-06-21 Compal_Jay For DDR3L repair request, add strap pin for CH A and CH B Enable/Disable. Rserv ed RH338 and RH339 PD X02

3 39 PWR_3.3VALWP/5VALWP-8243 20 12-06-21 Power_Jeff For 3/5V can't turn-off in S5 state,while system change form AC to DC mode Change PR95 8 form de-pop to 1M ohm

4 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component Change the PR738 from 220kOhm to 30kOhm.

5 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component Change the PR733,PR705 from 499 Ohm to 100 Ohm.

6 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

7 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

C C

8 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

10 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

11 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

12 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

13 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

14 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

15 38 PWR_ Charger(ISL9519) 201 2-06-21 Power_Jeff Follow Erp 6 spec (low power mode) Change PR28 51.1Kohm to 68Kohm

16 44 PWR-CPU_CORE 2012-06-22 Power_Jeff MOS temperature is not meet Dell spec Change PQ12 17,PQ1218 form SB00000V8 00 to SB00000XE0L

17 42 PWR_ +1.35VP/0.675VSP 2 012-06-22 Power_Jeff Because unstable of phase waveform Change PL1210 form 2.2UH to 1UH

18 27 Sensor Fuss ion / TPM 2012-06-22 Compal_Jay Follow Intel DG V080 and double confirm with Intel Change R1094 to 1M ohm and add R 1105,R1106 and C120 7

B B

19 27 Sensor Fuss ion / TPM 2012-06-22 Compal_Jay Follow Intel DG V080 and double confirm with Intel Add R1107 on U638 pin 1

20 27 Sensor Fuss ion / TPM 2012-06-22 Compal_Jay Follow Intel DG V080 and double confirm with Intel De-pop R817 and change R1104 to 1.5K ohm (pop)

21 27 Sensor Fuss ion / TPM 2012-06-22 Compal_Jay Follow Intel DG V080 and double confirm with Intel Contect U636.F6 to U637.5 and U636.E4 to U637.4

22 27 Sensor Fuss ion / TPM 2012-06-22 Compal_Jay Follow Intel suggest Change U636 P/N for SA00004TV0 (STM32F103RDY6 TR) to SA00005P20(STM32F103RCY6 TR) X02

23 35 EC ENE-KB9012 2012-06-22 Compal_Jay Follow EC suggest Follow EC suggest, change TABLET_MODE from PU to PD. X02

24 31 BAT LED 201 2-06-22 Compal_Jay F ollow factory suggest, change LED to ESD protest LED Change LED P/N form S C500007G00 to SC5000 0D70L X02

25 06 CPU(2/6) PM,XDP,CLK,S3,PLT 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RC49, RC53, RC56, RC11 to short PAD type

26 09 CPU(5/6) PWR,BYPASS 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RH280, RC92, RC96, RC98, RC99 to short PAD type

27 16 PCH (1/8) SATA,HDA,SPI, LPC 2 012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RH255 to short PAD type

28 18 PCH (3/8) DMI,FDI,PM,GFX,DP 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RH273, RH130, RH131, RH133, RH297, RH293 ,RH137, RH132 to short PAD type

A A

29 19 PCH (4/8) PCI, USB, NVRAM 201 2-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Chang e RH336 to short PAD type

30 21 PCH (6/8) PWR 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RH20 7, RH210, RH211 to short PAD type

5

4

3

Version Change List ( P. I. R. List )

Request
Owner

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

3

2

Page 4

Change the PC728,PC703 from 680pF to 1000pF.

Change the PR748 from 442 Ohm to 470 Ohm.

Change the PC743, PC710 from 0.068uF to 0.047uF.

Change the PR750,PR707 from non-pop to 649 Ohm.

Change the PC746,PC712 from non-pop to 0.01uF.

Change the PC741 from 0.01uF to non-pop.

Change the PR703 from 220kOhm to 44.2k Ohm.

Change the PR708 from 137kOhm to 33.2kOhm.

Change the PR712 from 392 Ohm to 412 Ohm.

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

Solution Description Rev.Page# Tit le

X0178 37 PWR_ DCIN / BATT CONN / OTP 201 2-04-26 Compal_Jay Add PJP205 on DC-IN GND pinreserved power Jump on DC-IN GND pin

X02

X02

X02

X02

X02

X02

X029 44 PWR-CPU_CORE 2012-06-21 Power_Jeff Following FAE test result and modify component

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

X02

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P51-EE-PIR-X01-P4

P51-EE-PIR-X01-P4

P51-EE-PIR-X01-P4

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t of

Date: Shee t of

Date: Shee t of

51 54Frida y, Septem ber 28, 2 012

51 54Frida y, Septem ber 28, 2 012

51 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

5

Item Issue Des cript ionDate

31 22 PCH (7/8) PWR 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RH21 9, RH230, RH247, RH244, RH292, RH233 to short PAD type X02

D D

32 24 eDP/ Camera CONN 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change R983, R984, R538 to short PAD type

33 26 Mini DP CONN 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change RV8 to short PAD type

35 28 WLAN / WiGig / BT 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change R1 017, R1012, R1013 , R1014, R1015, R101 6 to short PAD type X02

36 32 DC/DC Interface 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change R 1031 to short PAD type X02

38 39 PWR_ 3.3VALWP/5VALWP-8243 2012-06-26 Power_Jeff OCP protection over Dell spce Change PR21 8 from 43kohm to 39Kohm and PR216 from 45 .3K to 37.4Kohm

39 42 PWR_ +1.35VP/0.675VSP 2 012-06-26 Power_Jeff OCP protection over Dell spce Change PR301 from 7.68Kohm to 6.98Kohm

40 11 DDRIII Channel_A Lower 2012-06 -26 Compal_Jay For cost down soultion, add SPD code into BIOS and remove SPD ROM. De-pop UD17,RD39,RD40 and CD127 X02

41 13 DDRIII Channel_B Lower 2 012-06-26 Compal_Jay For cost down soultion, add SPD code into BIOS and remove SPD ROM. De-pop UD18,RD41,RD42 and CD128 X02

42 38 PWR_ Charger(ISL9519) 201 2-06-27 Power_Jeff Reserve Erp L ot 6 solution circuit into ST Reserve PR964,PR965,PR966,PR967,PR968,PC191 8 and PQ1228 X 02

C C

43 38 PWR_ Charger(ISL9519) 201 2-06-27 Power_Jeff Because ISL9519 support, so de-pop component De-pop component to PQ1227,PQ7,PR942,PR943,PR41 X0 2

44 20 PCH (5/8) GPIO, CPU, MISC 201 2-06-28 Compal_Jay Modify GPIO name for TPM optional Modify GPIO PCH_GPIO16 to TPM_DET

45 20 PCH (5/8) GPIO, CPU, MISC 201 2-06-28 Compal_Jay Modify GPIO name for DDR3L strap Modify GPIO PCH_GPIO17 to MEM_CHA_EN and PCH_GPIO22 to MEM_CHB_EN

46 20 PCH (5/8) GPIO, CPU, MISC 201 2-06-28 Compal_Jay Modify GPIO name for sensor hub PWRGATE Modify GPIO PCH_GPIO35 to SH_PWR_CNTRL

27 Sensor Fussion / TPM

47 20 PCH (5/8) GPIO, CPU, MISC 201 2-06-28 Compal_Jay Modify GPIO name for sensor hub uC DFU mode enable

27 Sensor Fussion / TPM

48 16 PCH (1/8) SATA,HDA,SPI, LPC 2 012-06-28 Compal_Jay Follow EMI request, modify HDA_BIT_CLK R/C value Modify RH27 from 33 ohm to 47 ohm and CH117 from 10p to 22p X02

49 35 EC ENE-KB9012 2012-06-29 Compal_Jay M/B side power SW interference with cable reoting De-pop SW2 X02

50 38 PWR_ Charger(ISL9519) 201 2-06-29 Power_Jeff For cost down soultion De-pop BMON circuit X02

51 37 PWR_ DCIN / BATT CONN / OTP 201 2-06-29 Follow Inter new revisi on check list suggestCompal_Jay Reserve PR905 10K ohm PD on PCH_DPWROK X02

B B

52 30 USB 3 .0 IO CONN 20 12-07-02 Compal_Jay Follow connector list 2012-06-29 Modify connector Mfr. P/N form TARAG-9U1391 to TARAG-9R1391 X02

54 Follow connector list 2012-06-2933 SCREWH/KB/RTC 2012 -07-02 Compal_Jay Modify JBL1 P/N from LTCX003NB0 0 to SP01001HD00 X 02

55 37 PWR_ DCIN / BATT CONN / OTP Follow connector list 2012-06-292012-07-02 Compal_Jay Modify JBATT9 Mfr. P/N from GS7309 1-10272-7H to GS73091-10272M-7H X02

56 27 Sensor Fuss ion / TPM 2012-07-05 Compal_Jay Follow HWDG 0.85 update change R1107 and R109 1 to 0 ohm X02

57 27 Sensor Fuss ion / TPM 2012-07-05 Compal_Jay Follow HWDG 0.85 update De-pop R1104 X02

PWR_3.3VALWP/5VALWP-82433958 For 3/5V turn-off issuePower_Jeff2012-07-05 X02Reserve PC1919 and PC192 0 (de-pop)

59 35 EC ENE-KB9012 2012-07-05 Compal_Jay PLT_RST# double PD De-pop R929

16 PCH (1/8) SATA,HDA,SPI, LPC

60

27 Sensor Fussion / TPM

61 39 PWR_ 3.3VALWP/5VALWP-8243 Power_Jeff NEC can't support SGA00004H00 this part2012-07-06 Change PC210,PC214,PC211 and PC22 4 from SGA00004H00 to SGA00002N8 L X02

A A

62 39 PWR_ 3.3VALWP/5VALWP-8243 2012-07-06 Compal_Jay X02For fix OTP issue Add PR969 link EC_ON and N_5V_001 and pop PC217 (0.1U) and add PR970(1M ohm) PD.

63 27 Sensor Fuss ion / TPM 2012-07-06 Compal_Jay Delete PRESSURE sensor schematic for SSD nut space Re-move Pressure sensor circuit and add test pad X02

5

2012-07-05 Compal_Jay Follow DFB review suggest Change Y1/YH1 footprint from Y_CM31532768DZFT_2P to Y_FC-135_2P

4

3

Version Change List ( P. I. R. List )

Request
Owner

Follow connector list 2012-06-2953 33 SCR EWH/KB/RTC 2012-07-02 Compal_Jay Modify JKB1 Mfr. P/N from 50699-03041-001 to 50699-03041-P01 X02

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

3

2

Page 5

Modify GPIO PCH_GPIO68 to SH_DFU_EN#

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

Solution Description Rev.Page# Tit le

X02

X02

X0234 27 Sensor Fuss ion / TPM 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change R1090 to short PAD type

X0237 35 EC ENE-KB9012 2012-06-25 Compal_Jay Change 0 ohm resistors to short PAD type Change R216, R921, R2 49, R250, R253, R926 , R931,R933, R934, R98 2, R925, R228 to short PAD type

X02

X02

X02

X02

X02

X02

X02

X02

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P52-EE-PIR-X02-P5

P52-EE-PIR-X02-P5

P52-EE-PIR-X02-P5

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t of

Date: Shee t of

Date: Shee t of

52 54Frida y, Septem ber 28, 2 012

52 54Frida y, Septem ber 28, 2 012

52 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

5

Item Issue Des cript ionDate

64 32 DC/DC Interface 2012-07-06 Compal_Jay For meet LG panel power sequence Change C1165 and C1143 fr om 10uF to 1uF and C1164 form 470 P to 1000P X02

D D

C C

B B

A A

24 eDP/ Camera CONN

28 WLAN / WiGig / BT

65

20 PCH (5/8) GPIO, CPU, MISC

29 mSATA / NFC Conn

17 PCH (2/8) PCIE, SMBUS, CLK Move R1100 from page 29 to page 17

67 39 PWR_ 3.3VALWP/5VALWP-8243 2012-07-10 Compal_Jay For fix OTP issue Change PC217 to 1UF, PR938 to 10K ohm and add PR97 1 (1K ohm) X02

68 17 2012-07-11 Compal_Jay Follow crystal EA test resultPCH (2/8) PCIE, SMBUS, CLK Change CH23 and CH24 from 12P to 15P X02

69 16 2012-07-11 Compal_JayPCH (1/8) SATA,HDA,SPI, LPC Follow crystal EA test result Change CH2 and CH3 fr om 22P to 18P X 02

70 24 2012-07-17 Compal_JayeDP/ Camera CONN Pr event Q70 can't turn-off potential issue while battery work in low capacity Change R536 from 1M ohm to 100K ohm X02

71 27 Sensor Fuss ion / TPM 2012-07-17 Compal_Jay Follow INTEL schematic review result Pop R817 1.5K ohm

72 27 Sensor Fuss ion / TPM 2012-07-17 Compal_Jay Follow ST suggest, change supplier P/N for QAZA0 only Follow ST suggest, change U636 P/N for SA00005P20L (STM32F103RCY6TR) to

73 35 EC ENE-KB9012 2012-07-20 Compal_Jay Modify board ID setting Modify R225 form 18K ohm to 33K ohm X02

74 35 EC ENE-KB9012 2012-07-23 Compal_Jay Modify TABLET_MODE PU and PD valu setting Modify R9 80 form 10K ohm to 100K ohm (WIN8/B R1 form 1K ohm to 10K ohm) X02

1 35 EC ENE-KB9012 201 2-08-20 Compal_Jay Modify board ID setting Modify R225 form 33K ohm to 56K ohm A00

2 16 Compal_JayPCH (1/8) SATA,HDA,SPI, LPC Follow DFB review result2012-08-20

27 Sensor Fussion / TPM3 Compal_Jay2012-08-20 Follow DFB review r esult

37 PWR_DCIN / BATT CONN / OTP4 Change 0 ohm resistors to short PAD typePower_Jeff2012-08-20 Modify PR911 and PR918 to short PAD A00

5 38 PWR_Charger( ISL9519) 2012-08-21 Power_Jeff Change 0 ohm r esistors to short PAD type Modify PR30,PR4 6,PR954,PR955,PR956 to short PAD A00

6 39 PWR_3.3VALWP/5VALWP-8243 20 12-08-21 Power_Jeff Chang e 0 ohm resistors to short PAD type Modify PR 219,PR512,PR513,PR515 to short PAD A00

7 41 PWR_V1.05S _VCCPP 2012-08-21 Power_J eff Change 0 ohm resistors to short PAD type Modify PR508,PR509 to short PAD A00

8 43 PWR_+VCCSAP 2 012-08-21 Power_Jeff Change 0 ohm resistors to short PAD type Modify PR610, PR611 to short PAD A00

9 44 PWR-CPU_CORE 2012-08-21 Power_Jeff Change 0 ohm resistors to short PAD type Modify PR72 0,PR721,PR736,PR722 to short PAD A00

10 6 CPU(2/6) PM,XDP,CLK,S3,PLT 2012-08-21 Compal_Jay Change 0 ohm resistors to short PAD type Modify RC14 5 to short PAD A00

11 9 CPU(5/6) PWR,BYPASS 2012-08-21 Compal_Jay Change 0 ohm resistors to short PAD type Modify RC1 09 to short PAD

12 18 PCH (3/8) DMI,FDI,PM,GFX,DP 2012-08-21 Compal_Jay Change 0 ohm resistors to short PAD type Modify RH313, RH309, RH310 to short PAD

13 22 PCH (3/8) DMI,FDI,PM,GFX,DP 2012-08-21 Compal_Jay Change 0 ohm resistors to short PAD type Modify RH312 to short PAD

2414 eDP/ Camera CONN 2012-08-21 Compal_Jay Change 0 ohm resistors to short PAD type Modify R1084 , R101 0, R1011 to short PAD

27 Change 0 ohm resistors to short PAD typeCompal_Jay2012-08-21Sensor Fussion / TPM15 Modify R819 to short PAD

28 Change 0 ohm resistors to short PAD typeCompal_Jay2012-08-21WLAN / WiGig / BT16 Modify R741, R742 , R728 to short PAD and de-pop R729

32 Compal_Jay Change 0 ohm resistors to short PAD type17 DC/DC Interface 2012-08-21 Modify RC107 to short PAD

35 Compal_Jay Change 0 ohm resistors to short PAD type18 EC ENE-KB9012 2012-08-21 Modify R265 to short PAD

PCH (3/8) DMI,FDI,PM,GFX,DP1819 Change RH272 from 10K to 47K VGATE prevent voltage divider less than 3V Compal_Jay2012-08-21

2012-07-06 Compal_Jay Reserve RF switcher circuit

2012-07-06 Compal_Jay

2012-08-21PWR_1.8VSP/1.5VSP4020 Modify PR517,PR518 to short PAD Change 0 ohm resistors to short PAD typePower_Jeff A00

2012-08-21PWR_+1.35VP/0.675VSP4221 Modify PR521 and PR 119to short PAD Change 0 ohm resistors to short PAD typePower_Jeff A00

4

3

Version Change List ( P. I. R. List )

Request
Owner

Delete NFC schematic for RF switcher layout space66

2

Page 6

Solution Description Rev.Page# Tit le

Reserve RF switcher circuit

Modify PCH_GPIO48 to RFSW_VCONT1 and PCH_GPIO49 to RFSW_VCONT2

Delete NFC circuit

SA00005P21L (STM32F103RCY6TRC17)

Modify YH1 footprint

Modify Y1 footprint

1

X02

X02

X02

X02

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

5

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P53-EE-PIR-X02/A00-P6

P53-EE-PIR-X02/A00-P6

P53-EE-PIR-X02/A00-P6

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t of

Date: Shee t of

2

Date: Shee t of

53 54Frida y, Septem ber 28, 2 012

53 54Frida y, Septem ber 28, 2 012

53 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0

5

Item Issue Des cript ionDate

22 42 PWR_ +1.35VP/0.675VSP 2 012-08-22 Power_Jeff Follow Green specificiation change component Change PR304 form 8.2k 5% to 8.2K 1% A00

D D

C C

B B

38 PWR_Charger(ISL9519)

23

43 PWR_+VCCSAP Change PC618 from 0.01U_0402_25V7K to 0.01U_0 402_16V7K

38 PWR_Charger(ISL9519)

24

43 PWR_+VCCSAP Change PC606 from SE102104K00 to SE1021 04K8L

26 37 PWR_ DCIN / BATT CONN / OTP 201 2-08-22 Power_Jeff Follow Green specificiation change component Change PQ903 form SB906100 210 to SB90610021L A00

38 PWR_Charger(ISL9519)

27

43 PWR_+VCCSAP Change PC616 from SE095224K00 to SE0952 24K8L

28

29 43 PWR_ +VCCSAP 2012-08-22 Power_J eff Combine P/N for BPM request Change PR608 fr om SD034100080 to SD0341 0008L

30

31 38 PWR_ Charger(ISL9519) 201 2-08-22 Power_Jeff Combine P/N for BPM request Change PC39 from SE068102J8 0 to SE074102K8L

33 2012-08-23 Power_ Jeff39 PWR_3.3VALWP/5VALWP-8243 Follow DFB review result Re-move PL402

34 41 2012-08-23 Power_JeffPWR_V1.05S_VCCPP Follow DFB review result Re-move PL405

35 42 PWR_ +1.35VP/0.675VSP 2 012-08-23 Power_Jeff Follow DFB review result Re-move PL406

36 44 PWR-CPU_CORE 2012-08-23 Power_Jeff Follow DFB review r esult Re-move PL700 and PL702

38 Follow connector list 0810_X1 5 Modify JUSB1 connector mfr. P/N from USB014-107CRL-TW to

39 33 SCR EWH/KB/RTC 2012-08-27 Compal_Jay Follow connector list 0810_X15 Modify JRTC1 P/N from SP020009Z0L to SP02000UB00 A00

40 33 SCR EWH/KB/RTC 2012-08-27 Compal_Jay Follow connector list 0810_X15 A00Modify JKB1 connector mfr. P/N from 50699-03041-P01 to 50699-030 01-P01 (remove mayla only)

41 25 IOL Conn 2012-08-31 Compal_Jay Follow EMI test request Modify LH9 P/N to SM01000LJ0L A00

42 24 eDP/ Camera CONN 2012-09-10 Compal_Jay For fix panel adjusting on leagcy and UEFI mode Pop D92 for PCH_INV_PWM control A00

PWR_1.8VSP/1.5VSP40

PWR_PROCESSOR DECOUPLING45

38 PWR_Charger(ISL9519)

39 PWR_3.3VALWP/5VALWP-8243 Change PR208 and PR209 from SD001470B80 to SD0114 70B8L

40 PWR_1.8VSP/1.5VSP Change PR400 and PR406 from SD001470B80 to SD0114 70B8L

38 PWR_Charger(ISL9519)37 2012-08-23 Power_ Jeff Follow DFB review result Re-move PL403 and PL404 A00

30 USB 3.0 IO CONN 2012-08-27 Compal_Jay A00

2012-08-22 Power_ Jeff Combine P/N for BPM request

2012-08-22 Power_ Jeff Combine P/N for BPM request

2012-08-22 Power_ Jeff Combine P/N for BPM request

2012-08-22 Power_ Jeff Combine P/N for BPM request

4

3

Version Change List ( P. I. R. List )

Request
Owner

Combine P/N for BPM requestPower_Jeff2012-08-22

BATT_LED#_LVx PU power rail change to +3VALW because of EC those pin are not 5V tolerance Change BATT_LED#_LVx PU power rail from +5VALW to +3VALW32 31 BAT LED 201 2-08-23 Compal_Jay

2

Page 7

Solution Description Rev.Page# Tit le

Change PC38 from 0.01U_0402 _25V7K to 0.01U_0402_16V7K

Change PC37 from SE102104 K00 to SE102104K8L

Change RH338 and RH339 fr om 0603 pad to short padFor DDR3L chip repair requestCompal_Jay2012-08-22PCH (5/8) GPIO, CPU, MISC2025

Change PC22 from SE095224 K00 to SE095224K8L

Change PC400 and PC410 fr om SE000000I10 to SE00000 110L

Change PC400,PC410,PC850,PC851,PC852,PC853 ,PC854,PC855,PC858,PC859,PC860,PC861,PC862
,PC890,PC891,PC892,PC893,PC894,PC913,PC91 6 from SE000000I10 to SE00 000110L

Change PR26 from SD00147 0B80 to SD011470B8L

USB014-107CRL-TWD (remove mayla only)

1

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

A00

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D

ANDTRADESECRETINFORMATION.THISSHEETMAY NOTBETRANSFEREDFROMTHECUSTODYOF THECOMPETENTDIVISIONOFR&D
DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS

DEPARTMENTEXCEPTAS AUTHORIZEDBYCOMPAL ELECTRONICS,INC.NEITHERTHISSHEETNORTHEINFORMATIONITCONTAINS
MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

5

4

MAYBE USEDBY ORDISCLOSEDTOANY THIRDPARTYWITHOUTPRIORWRITTENCONSENTOFCOMPALELECTRONICS,INC.

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

P54-EE-PIR-A00-P7

P54-EE-PIR-A00-P7

P54-EE-PIR-A00-P7

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

Size D ocum ent Num ber Re v

LA-8821P

LA-8821P

LA-8821P

Date: Shee t of

Date: Shee t of

2

Date: Shee t of

54 54Frida y, Septem ber 28, 2 012

54 54Frida y, Septem ber 28, 2 012

54 54Frida y, Septem ber 28, 2 012

1

1.0

1.0

1.0