Compal LA-8821P QAZA0, XPS 12 Schematic

A

MODEL NAME :

PCB NO :

1 1

BOM P/N :

QAZA0

LA-8821P ( DAB00000B00 )

ZZZ

ZZZ
MB_ PCB

MB_ PCB

B

C

D

E

4619J831L01 -> i5, 1.7G, DDR3L-4GB
4619J831L02 -> i5, 1.7G, DDR3L-8GB
4619J831L03 -> i7, 1.9G, DDR3L-4GB
4619J831L04 -> i7, 1.9G, DDR3L-8GB
4619J831L06 -> i5, 1.8G, DDR3L-4GB
4619J831L07 -> i5, 1.8G, DDR3L-8GB
4619J831L08 -> i7, 2.0G, DDR3L-4GB
4619J831L09 -> i7, 2.0G, DDR3L-8GB
4619J831L10 -> i5, 1.8G, DDR3L-4GB-NT
4619J831L11 -> i5, 1.8G, DDR3L-8GB-NT
4619J831L12 -> i7, 2.0G, DDR3L-4GB-NT

2 2

4619J831L13 -> i7, 2.0G, DDR3L-8GB-NT

Dell/Compal Confidential

4619J831L14 -> i5, 1.7G, DDR3L-4GB-NT
4619J831L15 -> i5, 1.7G, DDR3L-8GB-NT
4619J831L16 -> i7, 1.9G, DDR3L-4GB-NT

Schematic Document

4619J831L17 -> i7, 1.9G, DDR3L-8GB-NT

Murcielgo (Chief River SFF)

Ivy Bridge(BGA) + Panther Point(SFF, QS77)

3 3

2012-08-21

Rev: 1.0

Highlight the short pad for 0 ohm

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P01-Cover Page

P01-Cover Page

P01-Cover Page

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1 54Frida y, S ep tem ber 28, 20 12

1 54Frida y, S ep tem ber 28, 20 12

1 54Frida y, S ep tem ber 28, 20 12

E

1.0

1.0

1.0

A

B

C

D

E

1 1

eDP Panel

P.24

Conn x 2.

2 2

miniDP
Conn.

e-Compass +

Accelerometer

DE303DLHCTR

P.26

I2C

Sensor HUB

P.27

STM32F103RD

P.27

eDP

DP 1.1a

USB 2.0

Gyro Sensor

TX3GD20TR

3 3

Pressure Sensor

APS331APTR

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

4 4

PWM Fan Connector

De-pop

P.27

P.27

P.36 ~ 47

De-pop

NFC Module
Conn

P.33

P.32

P.34

SPI ROM
8M

TPM

AT97SC320 4-X2A14-AB

P.29

P.16

SMBus/I2C

SPI

P.27

Intel
Ivy Bridge
Processor

2C 17W

BGA 1023

Page 5, 6, 7, 8, 9, 10

100MHz 100MHz

2.7GT/s

DMI x4FDI x8

5GT/s

Intel

Panther Point SFF

PCH

QS77

BGA 1017 Balls

Page 16 ~ 23

LPC Bus

ENE KB9012BF

Touch Pad Int.KBD

P.34

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3L 1333 MHz

SATA3.0

USB2.0

PCI-E 2.0

USB2.0

USB2.0

USB3.0/USB2.0

USB3.0/USB2.0

HD Audio

P.35

Digital MIC

P.33

Channel A
DDR3L 2Gb or 4Gb (x8 ) * 8

Channel B
DDR3L 2Gb or 4Gb (x8 ) * 8

P.11, 12

P.13,14

Mini Card (Full)

# mSATA

Mini Card (Half)

WLAN
WiGig
BT

Touch Screnn

Digital Camera

USB 3.0 Conn.

( USB Charger Port )

USB 3.0 Conn.

Daughter Board

IOL BTB Conn

P.25

P.24

Audio Codec
ALC3260

P.29

P.28

P.24

P.24

P.30

P.30

Headphone Jack

( iPhone & Nokia compatible)

Int. Speaker

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

B

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/02/23 2013/10/28

2011/02/23 2013/10/28

2011/02/23 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

2 54Frida y, S ep tem ber 28, 20 12

2 54Frida y, S ep tem ber 28, 20 12

2 54Frida y, S ep tem ber 28, 20 12

E

1.0

1.0

1.0

A

B

C

D

E

Compal Confidential

Project Code : QAZA0
File Name : LA-88 21P

1 1

LS-8821P

Volume Up/Down , PWR, Rotation Button

2 2

Audio Jack

Keyboard

Keyboard Backlig ht

3 3

4 4

A

FPC

36 pin

FPC (main frame)

30 pin

FFC

4 pin

LA-8821P M/B

eDP Cable x 2

Coaxial and Wire

FFC

6 pin

Touch Pad

B

CABLE

9 pin

Battery Pack

FPC

16 pin to 15 pin

NFC Module

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

D

LS-8822P
Win8 Button
Hall S ensor

Camera

LCD Panel
Touch Panel Control Baord

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P03-DaughterB block diagram

P03-DaughterB block diagram

P03-DaughterB block diagram

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Date : She et of

Date : She et of

Date : She et of

E

3 54Frida y, S ep tem ber 28, 20 12

3 54Frida y, S ep tem ber 28, 20 12

3 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Board ID Rb V min

1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

SOURCE

KB930

KB930

PCH

PCH

AD_BID V t ypAD_BID V AD_BID max

0 V0

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

WLAN BATT DDR3 SPD

V V V

V V

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

NFCCharger

Touch Pad

V

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

ALS

V

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

Link

A

PCB Revision

0.1 Non Deep S3

0.1 Deep S 3

0.2 (X01)

0.4 (X02)

1.0 (A00)

PCH
USB
Port
Mapping

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

DESTINATION

External USB3

External USB3

MINI CARD-1 WLAN

Touch Panel

Camera

Sensor HUB

PCH

1 1

DDI
Port
Mapping

DESTINATION

SATA

SATA0

m-SATA

SATA1

SATA2

SATA3

SATA4

SATA5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRAN SFERED FR OM THE CUSTODY OF THEC OMPETENTDI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

A

CLK

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

MINI CARD-1 WLAN

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

TPM

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

PCI CLKOUT DESTINATION

PCI0

PCI1

PCH_LOOPBACK

EC LPC

PCI2

PCI3

PCI4

DDI PORT# DESTINATION

B

C

D mini-DP

PCI EXPRESS

DESTINATION

Lane 1CLKOUT_PCIE0

Lane 2

Lane 3

MINI CARD-1 WLAN

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P04-Notes List

P04-Notes List

P04-Notes List

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

4 54Frida y, S ep tem ber 28, 20 12

4 54Frida y, S ep tem ber 28, 20 12

4 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

5

D D

C C

B B

SA00005K63L for i5-3317U-1.7G SA00005L92L for i5-3427U- 1.8G

eDP_COMPIO (A1 8)

UCPU1

UCPU1

IVB1.7G

IVB1.7G

CPU_ IVB 1.7 G@

CPU_ IVB 1.7 G@

Trace le ngth Ma x is 500 mi ls

eDP_ HPD[24]

RC13 8

RC13 8
100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

R_COMP pla ce close to CP U

width 4 m ils

width 12 mils

2

G

G

12

Ivy Bridge i5-1.8G

UCPU1

UCPU1

IVB1.8G

IVB1.8G

CPU_ IVB 1.8 G@

CPU_ IVB 1.8 G@

R_COMPeDP_ICOMPO (A1 7)

VCC_IO

CPU_ eDP _HPD #

13

D

D

QC5

QC5
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

S

S

+VCC P

RC36 24.9 _0 402 _1 %RC36 24.9 _0 402 _1 %

RC13 7 1K_ 040 2_ 5%~ DRC13 7 1K_ 040 2_ 5%~ D

Ivy Bridge i7-1.9GIvy Bridge i5-1.7G

UCPU1

UCPU1

IVB1.9G

IVB1.9G

CPU_ IVB 1.9 G@

CPU_ IVB 1.9 G@

SA00005K53L for i7-3517U-1.9G

DMI_ CRX _PT X_ N0[18]
DMI_ CRX _PT X_ N1[18]
DMI_ CRX _PT X_ N2[18]
DMI_ CRX _PT X_ N3[18]

DMI_ CRX _PT X_ P0[18 ]
DMI_ CRX _PT X_ P1[18 ]
DMI_ CRX _PT X_ P2[18 ]
DMI_ CRX _PT X_ P3[18 ]

DMI_ CT X_P RX_ N0[18]
DMI_ CT X_P RX_ N1[18]
DMI_ CT X_P RX_ N2[18]
DMI_ CT X_P RX_ N3[18]

DMI_ CT X_P RX_ P0[18 ]
DMI_ CT X_P RX_ P1[18 ]
DMI_ CT X_P RX_ P2[18 ]
DMI_ CT X_P RX_ P3[18 ]

FDI_C TX _PR X_N0[18]
FDI_C TX _PR X_N1[18]
FDI_C TX _PR X_N2[18]
FDI_C TX _PR X_N3[18]
FDI_C TX _PR X_N4[18]
FDI_C TX _PR X_N5[18]
FDI_C TX _PR X_N6[18]
FDI_C TX _PR X_N7[18]

FDI_C TX _PR X_P 0[ 18]
FDI_C TX _PR X_P 1[ 18]
FDI_C TX _PR X_P 2[ 18]
FDI_C TX _PR X_P 3[ 18]
FDI_C TX _PR X_P 4[ 18]
FDI_C TX _PR X_P 5[ 18]
FDI_C TX _PR X_P 6[ 18]
FDI_C TX _PR X_P 7[ 18]

FDI_F SYN C0[18]
FDI_F SYN C1[18]

FDI_I NT[18]

FDI_L SY NC0[18 ]
FDI_L SY NC1[18 ]

1 2

4

12

eDP_ AUX N[24]
eDP_ AUX P[24]

eDP_ TX N_P 0[24]
eDP_ TX N_P 1[24]

eDP_ TX P_ P0[24 ]
eDP_ TX P_ P1[24 ]

Ivy Bridge i7-2.0G

SA00005LA2L for i7-3667U-2.0G

3

PEG_ICOMPI and RCOMPO signals should be shor ted and routed
with - max leng th = 500 mils - typical imped ance = 43 mohm s
PEG_ICOMPO sign als should be routed with - m ax length = 50 0 mils

- typical imped ance = 14.5 mo hms

@

@

UCPU1 A

+EDP _CO M

CPU_ eDP _HPD #

UCPU1

UCPU1

IVB2.0G

IVB2.0G

CPU_ IVB 2.0 G@

CPU_ IVB 2.0 G@

UCPU1 A

M2
P6
P1

P10

N3
P7
P3

P11

K1
M8
N4
R2

K3
M7
P4
T3

U7

W11

W1

AA6

W6

V4
Y2

AC9

U6

W10

W3

AA7

W7

T4
AA3
AC8

AA11
AC12

U11

AA10

AG8

AF3
AD2

AG11

AG4
AF4

AC3
AC4

AE11

AE7

AC1
AA4

AE10

AE6

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

eDP_AUX#
eDP_AUX

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

eDP

eDP

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

X76 4G

X76 4G

X7641131L01

X7641131L01

X76 _4G @

X76 _4G @

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

X76 8G

X76 8G

X7641131L04

X7641131L04

X76 _8G @

X76 _8G @

PEG _CO MP

+VCC P

12

RC2

RC2

24.9 _0 402 _1 %

24.9 _0 402 _1 %

2

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P05-CPU(1/6) DMI,FDI ,PEG

P05-CPU(1/6) DMI,FDI ,PEG

P05-CPU(1/6) DMI,FDI ,PEG

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

5 54Frida y, S ep tem ber 28, 20 12

5 54Frida y, S ep tem ber 28, 20 12

5 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

4

3

2

1

PM, XDP, CLK, S3 Reduce, PLTRST

PU/PD for JTAG signals

@

@

UCPU1 B

RC34
0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

1 3

D

D

12

R1035

100K_0402_5%~D

R1035

100K_0402_5%~D

QC2

QC2

BSS 138 -G_ SOT 23 -3

BSS 138 -G_ SOT 23 -3

G

G

2

1

CC69

CC69

.047 U_0 40 2_1 6V7 K~D

.047 U_0 40 2_1 6V7 K~D

2

DRAM RST _C NTRL [ 15]

UCPU1 B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

4.99 K_ 040 2_ 1%

4.99 K_ 040 2_ 1%

RC77

RC77

H_DRA MR ST #

12

S

S

Deep S3 Support

Non Deep S3(De-pop R1035)

MISC THERMAL PWR MANAGEMENT

MISC THERMAL PWR MANAGEMENT

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#
PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

JTAG & BPM

JTAG & BPM

BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

3

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

J3
H2

AG3
AG1

AT30

H_DRA MR ST #

BF44

SM_ RCO MP 0

BE43

SM_ RCO MP 1

BG43

SM_ RCO MP 2

DDR3 Compensation Signals

N53

XDP_ PRD Y#

N55

XDP_ PRE Q#

L56

XDP_ TC K

L55

XDP_ TM S

J58

XDP_ TR ST #

M60

XDP_ TD I

L59

XDP_ TD O

K58

XDP_ DBR ESE T# _R

G58
E55
E59
G55
G59
H60
J59
J61

POWEROK

Issued Date

Issued Date

Issued Date

CLK_ CPU _DM I [17]
CLK_ CPU _DM I# [17 ]

CLK_ CPU _DPL L [17 ]
CLK_ CPU _DPL L# [1 7]

1 2

RC55 1 40_ 04 02_ 1%R C55 1 40_ 040 2_ 1%

1 2

RC58 2 5.5 _.4 02_ 1%R C58 2 5.5_ .40 2_ 1%

1 2

RC60 2 00_ 04 02_ 1%R C60 2 00_ 040 2_ 1%

RC56 0 _04 02 _5% ~D

RC56 0 _04 02 _5% ~D

T22 4@ T2 24@
T22 5@ T2 25@
T22 6@ T2 26@
T22 7@ T2 27@
T22 8@ T2 28@
T22 9@ T2 29@
T23 0@ T2 30@
T23 1@ T2 31@

PM_ DRA M_ PWRG D[1 8]

CPU1 .5V _S3 _GA TE[32,3 5,4 2,9 ]

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Width 20 mils, Spacing 13mils, Length < 500mil

T24 1@ T2 41@

SHORT

1 2

@

@

+3V _PCH

RC4

RC4
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

1 2

SHORT

1 2

RC11 0_04 02_ 5% ~D

RC11 0_04 02_ 5% ~D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

XDP_ DBR ESE T#

@

@

2

XDP_ DBR ESE T# [18]

+3V _PCH

1

2

CC65

CC65

.1U_0402_16V7K~D

.1U_0402_16V7K~D

5

UC1

UC1

1

P

B

4

Y

2

A

G

74A HC1G 09 GW_T SS OP 5

74A HC1G 09 GW_T SS OP 5

3

RUN_O N_C PU1. 5VS 3#[32]

Place close to PCH or EC

D D

+VCC P

RC43

RC43

62_ 040 2_ 5%

62_ 040 2_ 5%

H_T HERM T RIP#[20]

H_PM _S YNC[18]

H_CP UPWR GD[20]

1 2

H_CP UPWR GD_R

1

2

CC68

CC68

.1U_0402_16V7K~D

.1U_0402_16V7K~D

5

UC2

UC2

P

4

BUFO _CP U_RS T#

Y

G

3

SN74 LV C1G 07DC KR_ SC7 0-5~ D

SN74 LV C1G 07DC KR_ SC7 0-5~ D

1 2

1 2

H_PR OCHO T#[35, 38]

C C

RC44 1 0K_ 040 2_ 5%~ DRC4 4 10K _04 02 _5% ~D

Avoid stub in the PWRGD path
while placing resistors RC44 & RC53

+3V S

PLT _RS T#[19, 27, 28, 35]

B B

1

NC

2

A

RC13 0 0_040 2_5 %~D@ RC13 0 0_040 2_5 %~ D@

Place close to PCH reset Logic Gate

For CPU S3 Power Reduce

10

1 2

DDR3_ DRA MRS T#[11, 12, 13, 14]

Deep S3 Support

A A

Non Deep S3

DRAM RST _C NTRL _E C[35]

DRAM RST _C NTRL _P CH[17]

DDR3_ DRA MRS T# _R

RC76 1 K_0 40 2_5 %~DRC76 1K _04 02_ 5% ~D

SHORT

1 2

RC14 5 0_0 402 _5 %~D

RC14 5 0_0 402 _5 %~D

1 2

RC72 0 _04 02 _5% ~D@R C72 0 _04 02_ 5% ~D@

@

@

H_PR OCHO T#

+VCC P

12

RC32

RC32

T24 8@ T2 48@

T1@ T1@

H_PE CI[2 0,35 ]

1 2

RC41 56_ 040 2_ 5%RC41 56_ 040 2_ 5%

SHORT

1 2

RC49 0_0 402 _5 %~D

RC49 0_0 402 _5 %~D

@

@

SHORT

1 2

RC53 0_0 402 _5 %~D

RC53 0_0 402 _5 %~D

@

@

75_0402_5%

75_0402_5%

1 2

RC33 4 3_0 40 2_1 %RC33 43_ 04 02_ 1%

+1.3 5V

12

RC75

RC75
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

H_CA TE RR#

H_PR OCHO T# _R

H_T HERM T RIP# _R

H_CP UPWR GD_R

VDDP WRGO OD_ R

BUF_ CPU_ RST #

BUF_ CPU_ RST #

12

@ RC34

@

RC74 0 _04 02 _5% ~D@RC7 4 0_ 040 2_5 %~ D@

DRAM RST _C NTRL

CPU DRAMRST# Control Option for Deep S3

5

4

XDP_ TM S

XDP_ TD I

XDP_ PRE Q#

XDP_ TD O

XDP_ TC K

XDP_ TR ST #

12

RC8

RC8
200 _04 02 _1%

200 _04 02 _1%

VDDP WRGO OD

RC19

@ RC19

@

39_ 040 2_ 1%

39_ 040 2_ 1%

1 2

13

D

D

@

@

S

S

QC1

QC1
DII-DM N65 D8L W-7~ D

DII-DM N65 D8L W-7~ D

1 2

RC42 1 K_0 402 _5 %~DRC42 1 K_0 402 _5 %~D

Place close to CPU

1 2

RC57 1 30_ 04 02_ 1%~ DRC57 13 0_0 402 _1 %~D

XDP_ DBR ESE T#

+1.3 5V_ CPU _VD DQ

2

G

G

1/17, Change P/N to SB0000 0UO00

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

P06-CPU(2/6) PM,XDP,CLK,S3, PLT

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

1

1 2

1 2

1 2

1 2

1 2

1 2

VDDP WRGO OD_ R

+VCC P

RC4551_ 040 2_ 5% RC4551_ 040 2_ 5%

RC4651_ 040 2_ 5% RC4651_ 040 2_ 5%

RC4751_ 040 2_ 5% @RC4751_04 02_ 5% @

RC4851_ 040 2_ 5% RC4851_ 040 2_ 5%

RC5251_ 040 2_ 5% RC5251_ 040 2_ 5%

RC5451_ 040 2_ 5% RC5451_ 040 2_ 5%

+3V S

1.0

1.0

1.0

6 54Frida y, S ep tem ber 28, 20 12

6 54Frida y, S ep tem ber 28, 20 12

6 54Frida y, S ep tem ber 28, 20 12

5

4

3

2

1

D D

DDR_A _D[ 0..6 3][11,1 2]

C C

B B

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D1 0
DDR_A _D1 1
DDR_A _D1 2
DDR_A _D1 3
DDR_A _D1 4
DDR_A _D1 5
DDR_A _D1 6
DDR_A _D1 7
DDR_A _D1 8
DDR_A _D1 9
DDR_A _D2 0
DDR_A _D2 1
DDR_A _D2 2
DDR_A _D2 3
DDR_A _D2 4
DDR_A _D2 5
DDR_A _D2 6
DDR_A _D2 7
DDR_A _D2 8
DDR_A _D2 9
DDR_A _D3 0
DDR_A _D3 1
DDR_A _D3 2
DDR_A _D3 3
DDR_A _D3 4
DDR_A _D3 5
DDR_A _D3 6
DDR_A _D3 7
DDR_A _D3 8
DDR_A _D3 9
DDR_A _D4 0
DDR_A _D4 1
DDR_A _D4 2
DDR_A _D4 3
DDR_A _D4 4
DDR_A _D4 5
DDR_A _D4 6
DDR_A _D4 7
DDR_A _D4 8
DDR_A _D4 9
DDR_A _D5 0
DDR_A _D5 1
DDR_A _D5 2
DDR_A _D5 3
DDR_A _D5 4
DDR_A _D5 5
DDR_A _D5 6
DDR_A _D5 7
DDR_A _D5 8
DDR_A _D5 9
DDR_A _D6 0
DDR_A _D6 1
DDR_A _D6 2
DDR_A _D6 3

DDR_A _B S0[1 1,1 2,15 ]
DDR_A _B S1[1 1,1 2,15 ]
DDR_A _B S2[1 1,1 2,15 ]

DDR_A _CA S#[1 1,1 2,1 5]
DDR_A _RA S#[1 1,1 2,1 5]
DDR_A _WE #[11,1 2,15 ]

@

@

UCPU1 C

UCPU1 C

AG6

AJ6

AP11

AL6

AJ10

AJ8
AL8
AL7

AR11

AP6
AU6
AV9
AR6
AP8

AT13
AU13

BC7
BB7

BA13
BB11

BA7
BA9
BB9

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48

AY48

BA49

AV49

BB51

AY53

BB49
AU49
BA53
BB55
BA55

AV56

AP50
AP53

AV54

AT54
AP56
AP52
AN57

AN53
AG56
AG53

AN55

AN52
AG55

AK56

BD37

BF36

BA28

BE39

BD39

AT41

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11

DDR_A _DQ S#0

SA_DQS#[0]

AR8

DDR_A _DQ S#1

SA_DQS#[1]

AV11

DDR_A _DQ S#2

SA_DQS#[2]

AT17

DDR_A _DQ S#3

SA_DQS#[3]

AV45

DDR_A _DQ S#4

SA_DQS#[4]

AY51

DDR_A _DQ S#5

SA_DQS#[5]

AT55

DDR_A _DQ S#6

SA_DQS#[6]

AK55

DDR_A _DQ S#7

SA_DQS#[7]

AJ11

DDR_A _DQ S0

SA_DQS[0]

AR10

DDR_A _DQ S1

SA_DQS[1]

AY11

DDR_A _DQ S2

SA_DQS[2]

AU17

DDR_A _DQ S3

SA_DQS[3]

AW45

DDR_A _DQ S4

SA_DQS[4]

AV51

DDR_A _DQ S5

SA_DQS[5]

AT56

DDR_A _DQ S6

SA_DQS[6]

AK54

DDR_A _DQ S7

SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

BG35

DDR_A _M A0

BB34

DDR_A _M A1

BE35

DDR_A _M A2

BD35

DDR_A _M A3

AT34

DDR_A _M A4

AU34

DDR_A _M A5

BB32

DDR_A _M A6

AT32

DDR_A _M A7

AY32

DDR_A _M A8

AV32

DDR_A _M A9

BE37

DDR_A _M A1 0

BA30

DDR_A _M A1 1

BC30

DDR_A _M A1 2

AW41

DDR_A _M A1 3

AY28

DDR_A _M A1 4

AU26

DDR_A _M A1 5

M_C LK_ DDR0 [11 ,12 ,15 ]
M_C LK_ DDR# 0 [11,1 2,1 5]
DDR_A _CK E0 [1 1,1 2,1 5]

DDR_A _CS 0# [1 1,1 2,1 5]

M_O DT 0 [11, 12, 15]

DDR_A _DQ S#[ 0..7 ] [11,1 2]

DDR_A _DQ S[0 ..7] [11 ,12 ]

DDR_A _M A[0 ..15 ] [11 ,12 ,15 ]

DDR_B _D[ 0..6 3][13,1 4]

DDR_B _B S0[1 3,1 4,15 ]
DDR_B _B S1[1 3,1 4,15 ]
DDR_B _B S2[1 3,1 4,15 ]

DDR_B _CA S#[1 3,1 4,1 5]
DDR_B _RA S#[1 3,1 4,1 5]
DDR_B _WE #[13,1 4,15 ]

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D1 0
DDR_B _D1 1
DDR_B _D1 2
DDR_B _D1 3
DDR_B _D1 4
DDR_B _D1 5
DDR_B _D1 6
DDR_B _D1 7
DDR_B _D1 8
DDR_B _D1 9
DDR_B _D2 0
DDR_B _D2 1
DDR_B _D2 2
DDR_B _D2 3
DDR_B _D2 4
DDR_B _D2 5
DDR_B _D2 6
DDR_B _D2 7
DDR_B _D2 8
DDR_B _D2 9
DDR_B _D3 0
DDR_B _D3 1
DDR_B _D3 2
DDR_B _D3 3
DDR_B _D3 4
DDR_B _D3 5
DDR_B _D3 6
DDR_B _D3 7
DDR_B _D3 8
DDR_B _D3 9
DDR_B _D4 0
DDR_B _D4 1
DDR_B _D4 2
DDR_B _D4 3
DDR_B _D4 4
DDR_B _D4 5
DDR_B _D4 6
DDR_B _D4 7
DDR_B _D4 8
DDR_B _D4 9
DDR_B _D5 0
DDR_B _D5 1
DDR_B _D5 2
DDR_B _D5 3
DDR_B _D5 4
DDR_B _D5 5
DDR_B _D5 6
DDR_B _D5 7
DDR_B _D5 8
DDR_B _D5 9
DDR_B _D6 0
DDR_B _D6 1
DDR_B _D6 2
DDR_B _D6 3

DDR structure 1R X 8

DDR structure 1R X 8

@

@

UCPU1 D

UCPU1 D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43

BF40

BD45

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3

DDR_B _DQ S#0

AV3

DDR_B _DQ S#1

BG11

DDR_B _DQ S#2

BD17

DDR_B _DQ S#3

BG51

DDR_B _DQ S#4

BA59

DDR_B _DQ S#5

AT60

DDR_B _DQ S#6

AK59

DDR_B _DQ S#7

AM2

DDR_B _DQ S0

AV1

DDR_B _DQ S1

BE11

DDR_B _DQ S2

BD18

DDR_B _DQ S3

BE51

DDR_B _DQ S4

BA61

DDR_B _DQ S5

AR59

DDR_B _DQ S6

AK61

DDR_B _DQ S7

BF32

DDR_B _M A0

BE33

DDR_B _M A1

BD33

DDR_B _M A2

AU30

DDR_B _M A3

BD30

DDR_B _M A4

AV30

DDR_B _M A5

BG30

DDR_B _M A6

BD29

DDR_B _M A7

BE30

DDR_B _M A8

BE28

DDR_B _M A9

BD43

DDR_B _M A1 0

AT28

DDR_B _M A1 1

AV28

DDR_B _M A1 2

BD46

DDR_B _M A1 3

AT26

DDR_B _M A1 4

AU22

DDR_B _M A1 5

M_C LK_ DDR2 [13 ,14 ,15 ]
M_C LK_ DDR# 2 [13,1 4,1 5]
DDR_B _CK E0 [1 3,1 4,1 5]

DDR_B _CS 0# [1 3,1 4,1 5]

M_O DT 2 [13, 14, 15]

DDR_B _DQ S#[ 0..7 ] [13,1 4]

DDR_B _DQ S[0 ..7] [13 ,14 ]

DDR_B _M A[0 ..15 ] [13 ,14 ,15 ]

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P07-CPU(3/6) DDRIII

P07-CPU(3/6) DDRIII

P07-CPU(3/6) DDRIII

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

7 54Frida y, S ep tem ber 28, 20 12

7 54Frida y, S ep tem ber 28, 20 12

7 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

D D

CFG Straps for Processor

12

CFG2

RC781K_ 040 2_1 %~ D @RC781K_ 040 2_1 %~ D @

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation;
Lane # definition matches socket pin
map definition

CFG2

0:Lane Reversed

*

12

CFG4

RC811K_ 040 2_1 %~ D RC8 11K_04 02 _1% ~D

Display Port Presence Strap

C C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display

*

Port device is connected to the
Embedded Display Port

12

RC871K_ 040 2_1 %~ D @RC871K_ 040 2_1 %~ D @

12

RC861K_ 040 2_1 %~ D @RC861K_ 040 2_1 %~ D @

CFG5

CFG6

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions

*

1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled
;function 2 disabled

CFG[6:5]

01: Reserved - (Device 1 function 1
disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1

B B

and 2 enabled

12

RC891K_ 040 2_1 %~ D @RC891K_ 040 2_1 %~ D @

CFG7

4

VCC_ DIE_ SE NSE

RC14 2

@ RC14 2

@

0_0 402 _5 %~D

0_0 402 _5 %~D

1 2

12

RC14 3

RC14 3
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

3

@

@

UCPU1 E

UCPU1 E

B50

CFG0

T23 2@ T2 32@

CFG1

T20 8@ T2 08@

CFG2
CFG3

T20 9@ T2 09@

CFG4
CFG5
CFG6
CFG7
CFG8

T21 3@ T2 13@

CFG9

T21 0@ T2 10@

CFG1 0

T21 1@ T2 11@

CFG1 1

T21 2@ T2 12@

CFG1 2

T23 5@ T2 35@

CFG1 3

T23 6@ T2 36@

CFG1 4

T23 7@ T2 37@

CFG1 5

T23 8@ T2 38@

CFG1 6

T21 4@ T2 14@

CFG1 7

T21 5@ T2 15@

CPU_ RSV D6
CPU_ RSV D7

12

RC14 4

RC14 4
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53

F53

G53

L51
F51

D52

L53

H43
K43

H45
K45

F48

H48
K48

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22

BE22

BG26

BE26
BF23
BE24

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RSVD6
RSVD7

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

RESERVED

RESERVED

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BD61
DC_TEST_BE61

DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

BCLK_ITP

BCLK_ITP#

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

N59
N58

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

CLK_ RES _IT P
CLK_ RES _IT P#

DC_T ES T_ C4_D 3

DC_T ES T_ A59 _C5 9

DC_T ES T_ A61 _C6 1

DC_T ES T_ BE6 1_B E5 9

DC_T ES T_ BG3 _BE 3

DC_T ES T_ BG1 _BE 1

2

T23 3@ T2 33@
T23 4@ T2 34@

1

PEG DEFER TRAINING

1: (Default) PEG Train immediately

*

following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for training

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P08-CPU(4/6) RSVD,CFG

P08-CPU(4/6) RSVD,CFG

P08-CPU(4/6) RSVD,CFG

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

8 54Frida y, S ep tem ber 28, 20 12

8 54Frida y, S ep tem ber 28, 20 12

8 54Frida y, S ep tem ber 28, 20 12

1

1.0

1.0

1.0

5

ULV-DC Icc(max)=33A

D D

C C

B B

A A

+VCC _COR E

@

@

UCPU1 F

UCPU1 F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

POWER

POWER

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]

AB20

PEG IO AND DDR IO

PEG IO AND DDR IO

VCCIO[33]

AC13

CORE SUPPLY

CORE SUPPLY

5

VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50
VCCIO51

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

RAILS

RAILS

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

SENSE LINES SVID QUIET

+VCC _COR E

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
CC219

CC219

1

2

AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
CC220

CC220

H_VC CP_ SEL

VCCS ENS E_R

+VCC P

8.5A

+1.0 5VS _V CCPQ

1

CC22 4

CC22 4
1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

2

+VCC P

H_CP U_S VIDA LRT #
H_CP U_S VIDCL K
H_CP U_S VIDDA T

+VCC _COR E

RC97 1 00_ 04 02_ 1%~ DRC 97 10 0_ 040 2_1 %~D
RC98 0 _04 02 _5% ~D@RC9 8 0_ 040 2_5 %~ D@
RC99 0 _04 02 _5% ~D@RC9 9 0_ 040 2_5 %~ D@
RC10 0 100_0 402 _1 %~DRC100 100 _04 02 _1% ~D

+VCC P

1 2

RC12 6 10_ 040 2_ 5%~ DRC1 26 10 _04 02 _5% ~D

1 2

RC12 9 10_ 040 2_ 5%~ DRC1 29 10 _04 02 _5% ~D

Place the PU
resistors close to CPU

+VCC P

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

CC221

CC221

2

2

Close to JCPU1

4

+1.3 5V_ CPU _VD DQ

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC160

CC160

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC233

CC233

1

2

+1.8 VS

11

@

@

1 2

RC10 9 0_0 805 _5 %~D

RC10 9 0_0 805 _5 %~D

SHORT

@

T22 3@T22 3

+VCC P

RH28 0

@RH280

@

0_0 603 _5 %~D

0_0 603 _5 %~D

12

SHORT

1 2

RC93 7 5_0 40 2_5 %RC93 7 5_0 40 2_5 %

1 2

RC94 4 3_0 40 2_5 %~DRC9 4 43_ 04 02_ 5%~ D

1 2

RC92 0 _04 02 _5% ~D@RC9 2 0_ 040 2_5 %~ D@

1 2

RC96 0 _04 02 _5% ~D@RC9 6 0_ 040 2_5 %~ D@

1 2

RC95 1 30_ 04 02_ 5%~ DRC 95 13 0_ 040 2_5 %~D

RC95 close to CPU

1 2
1 2
1 2
1 2

+1.3 5V_ CPU _VD DQ

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CC222

CC222

CC223

CC223

2

4

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

+VCC SA

VIDALERT#
Connect one end of s eries-resistor 43±5% close t o
processor and pull-up to VCCI O through 75±5% on
the other end of the series-resist or towards Int el MVP 7.

1

2

1

1

1

CC164

CC164

CC162

CC162

CC163

CC163

CC161

CC161

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC238

CC238

1U_0402_6.3V6K~D

CC239

CC239

CC234

CC234

CC240

CC240

1

1

1

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

1

CC167

CC167

CC168

CC168

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC227

@

@ CC226

@

1

1

1

CC227

CC226

2

2

2

+1.8 VS_ VCC PLL

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC172

@

1

1

1

CC172

CC174

CC174

2

2

2

VR_S VID _AL RT# [4 4]
VR_S VID _CL K [44]
VR_S VID _DA T [44]

+VCC P

VIDSOUT:
Requires a pull-up t o VCCIO through a pull-up res istor of 130 ±5% c lose to t he processor, and a pull-up
to VCCIO through a pull-up res istor of 130 ±5% c lose to I ntel MVP 7.
VIDSCLK:
Required pull-up to VC CIO through 55 ±5% close to Intel IMVP 7.

VCCS ENS E [44]
VSS SEN SE [44]

VCCIO _S ENSE [ 41]
VSS IO_ SEN SE [41]

1

2

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CC169

CC169

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC228

@

CC228

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC175

CC175

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC165

CC165

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC235

CC235

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@ CC170

@

1

CC170

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC229

@

1

CC229

2

1

+

+

CC17 6

CC17 6
330 U_D2 _2 .5VM _R 6M ~D

330 U_D2 _2 .5VM _R 6M ~D

2

VCC_ AXG _S ENSE[44]
VSS _AX G_ SENS E[4 4]

CC231

CC231

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC241

CC241

1

2

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC232

CC232

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC236

CC236

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@ CC225

@

1

CC225

+

+

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@ CC230

@

CC230

+VCC _GFX COR E_A XG

1

+

+

2

1

2

CC17 1

CC17 1
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

3

330U_B2_2VM_R15M

330U_B2_2VM_R15M

CC166

CC166

ULV-DC GT2 29A
ULV-DC GT1 18A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC242

CC242

12

12

3

+VCC _GFX COR E_A XG

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC237

CC237

1

2

RC13 5

RC13 5
100 _04 02 _5% ~D

100 _04 02 _5% ~D

RC13 6

RC13 6
100 _04 02 _5% ~D

100 _04 02 _5% ~D

1.2A

+1.8 VS_ VCC PLL

+VCC SA

4A (ULV-DC)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

@

@

UCPU1 G

UCPU1 G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

POWER

POWER

GRAPHICS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

1.8V RAIL

SA RAIL

SA RAIL

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SA_DIMM_VREFDQ

VREF

VREF

SB_DIMM_VREFDQ

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

QUIET RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

SENSE LINES

VCCSA_VID[0]
VCCSA_VID[1]

VCCSA VID

lines

VCCSA VID

lines

2

+V_SM_VREF should
have 10 mil trace width

AY43

SM_VREF

BE7
BG7

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

VDDQ[4]

AL30

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36

VDDQ[10]

AM40

VDDQ[11]

AN30

VDDQ[12]

AN34

VDDQ[13]

AN38

VDDQ[14]

AR26

VDDQ[15]

AR28

VDDQ[16]

AR30

VDDQ[17]

AR32

VDDQ[18]

AR34

VDDQ[19]

AR36

VDDQ[20]

AR40

VDDQ[21]

AV41

VDDQ[22]

AW26

VDDQ[23]

BA40

VDDQ[24]

BB28

VDDQ[25]

BG33

VDDQ[26]

AM28

VCCDQ[1]

AN26

VCCDQ[2]

BC43
BA43

U10

D48
D49

1

0_0 402 _5 %~D

0_0 402 _5 %~D

+VRE FDQ_ A

QC6

@ QC 6

+V_ SM_ VRE F

V_DD R_RE FA_ R [15]
V_DD R_RE FB_ R [15]

+1.3 5V_ CPU _VD DQ

5A

+0.6 75V S

RC10 6 0_0 402 _5 %~D@ RC 106 0 _04 02_ 5% ~D@

+1.3 5V_ CPU _VD DQ +1.3 5V

+1.3 5V_ CPU _VD DQ

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CC218

CC218

2

Tit le

Tit le

Tit le

P09-CPU(5/6) PWR,BYPASS

P09-CPU(5/6) PWR,BYPASS

P09-CPU(5/6) PWR,BYPASS

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

@

AP2 302 GN-H F_SO T2 3-3

AP2 302 GN-H F_SO T2 3-3

CPU1 .5V _S3 _GA TE[32,3 5,4 2,6 ]

+V_ SM_ VRE F

1 2

12

CC18 2 0 .1U_ 04 02_ 10V 7K ~DCC182 0.1U_0 40 2_1 0V 7K~ D

12

CC18 4 0 .1U_ 04 02_ 10V 7K ~DCC184 0.1U_0 40 2_1 0V 7K~ D

12

CC18 1 0 .1U_ 04 02_ 10V 7K ~DCC181 0.1U_0 40 2_1 0V 7K~ D

12

CC18 3 0 .1U_ 04 02_ 10V 7K ~DCC183 0.1U_0 40 2_1 0V 7K~ D

VCCS A_S ENS E [43 ]

VCCS A_V ID0 [4 3]
VCCS A_V ID1 [4 3]

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

RCU1

@ RCU 1

@

1 2

123

+1.3 5V_ CPU _VD DQ

12

RC11 2

RC11 2
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

12

RC11 6

RC11 6
1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+V_ SM_ VRE F

12

RC14 1

@ RC1 41

@

100 K_0 40 2_5 %~D

100 K_0 40 2_5 %~D

9 54Frida y, S ep tem ber 28, 20 12

9 54Frida y, S ep tem ber 28, 20 12

9 54Frida y, S ep tem ber 28, 20 12

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

@

@

UCPU1 H

UCPU1 H

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

A9

AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

@

@

UCPU1 I

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

UCPU1 I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-B RIDG E_ BGA 102 3

IVY-B RIDG E_ BGA 102 3

VSS

VSS

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11

NCTF

NCTF

VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P10-CPU(6/6) PWR,VSS

P10-CPU(6/6) PWR,VSS

P10-CPU(6/6) PWR,VSS

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

10 54Fri da y, S epte mb er 2 8, 201 2

10 54Fri da y, S epte mb er 2 8, 201 2

10 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

DDR_A _DQ S#[ 0..7 ][1 2,7 ]

DDR_A _DQ S[0 ..7][12, 7]

DDR_A _D[ 0..6 3][12 ,7]

DDR_A _M A[0 ..15 ][12, 15,7 ]

All VREF traces should
have 10 mil trace width

UD3

UD3

UD4

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD3

UD3

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD3

UD3

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD3

UD3

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD3

UD3

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD3

UD3

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD4

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD4

UD4

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD4

UD4

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD4

UD4

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD4

UD4

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD4

UD4

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD2

UD2

UD1

UD1

C C

B B

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD1

UD1

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD1

UD1

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD1

UD1

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD1

UD1

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD1

UD1

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD2

UD2

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD2

UD2

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD2

UD2

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD2

UD2

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD2

UD2

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_A _DQ S0
DDR_A _DQ S#0

DDR_A _D2
DDR_A _D1
DDR_A _D7
DDR_A _D4
DDR_A _D3
DDR_A _D0
DDR_A _D6
DDR_A _D5

12

RD1 240 _0 402 _1 %RD1 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

DDR_A _DQ S2
DDR_A _DQ S#2

DDR_A _D1 8
DDR_A _D1 6
DDR_A _D1 9
DDR_A _D2 2
DDR_A _D1 7
DDR_A _D2 0
DDR_A _D2 3
DDR_A _D2 1

12

RD3 240 _0 402 _1 %RD3 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

@

@

UD1

UD1

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD3

UD3

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

DDR_A _DQ S1
DDR_A _DQ S#1

DDR_A _D1 0
DDR_A _D1 2
DDR_A _D1 4
DDR_A _D1 3
DDR_A _D1 1
DDR_A _D8
DDR_A _D1 5
DDR_A _D9

12

RD2 240 _0 402 _1 %RD2 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _DQ S3
DDR_A _DQ S#3

DDR_A _D3 0
DDR_A _D2 5
DDR_A _D3 1
DDR_A _D2 4
DDR_A _D2 6
DDR_A _D2 8
DDR_A _D2 7
DDR_A _D2 9

12

RD4 240 _0 402 _1 %RD4 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

2

@

@

UD2

UD2

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD4

UD4

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

+1.3 5V

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

M_C LK_ DDR0M_C LK_ DDR0

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

1

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

Memory Channel A SPD EEPROM

+1.3 5V +3V S

A A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD1

CD1

CD2

CD2

1

12

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD4

CD4

CD3

CD3

1

12

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD5

CD5

CD6

CD6

1

12

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD7

CD7

CD8

CD8

1

12

2

4

1

+

+

CD12 5

CD12 5
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

+3V S

PCH_ SM BCL K[1 3,1 7,3 4]
PCH_ SM BDA TA[13 ,17 ,34 ]

2

UD17

@ UD17

@

AT2 4C0 2C-X HM-T _T SS OP 8

AT2 4C0 2C-X HM-T _T SS OP 8

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND4SDA

Non-CIS part

@

@

1
2
3

12

RD39 1 K_ 040 2_5 %~ D

RD39 1 K_ 040 2_5 %~ D

12

RD40 1 K_ 040 2_5 %~ D

RD40 1 K_ 040 2_5 %~ D

@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P11-DDRIII C hannel_A Lower

P11-DDRIII C hannel_A Lower

P11-DDRIII C hannel_A Lower

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

@ CD127

@

1

1

CD12 7

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

11 54Fri da y, S epte mb er 2 8, 201 2

11 54Fri da y, S epte mb er 2 8, 201 2

11 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

D D

DDR_A _DQ S#[ 0..7 ][1 1,7 ]

DDR_A _DQ S[0 ..7][11, 7]

DDR_A _D[ 0..6 3][11 ,7]

DDR_A _M A[0 ..15 ][11, 15,7 ]

All VREF traces should
have 10 mil trace width

UD7

UD7

UD8

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD7

UD7

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD7

UD7

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD7

UD7

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD7

UD7

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD7

UD7

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD8

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD8

UD8

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD8

UD8

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD8

UD8

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD8

UD8

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD8

UD8

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD5

UD5

UD6

UD6

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD5

UD5

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD5

UD5

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD5

UD5

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD5

UD5

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD5

UD5

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5P R0L

UD6

UD6

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD6

UD6

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD6

UD6

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD6

UD6

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD6

UD6

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

C C

B B

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_A _DQ S4
DDR_A _DQ S#4

DDR_A _D3 5

DDR_A _D3 6
DDR_A _D3 9
DDR_A _D3 7
DDR_A _D3 8
DDR_A _D3 2
DDR_A _D3 4

12

RD5 240 _0 402 _1 %RD5 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

DDR_A _DQ S6
DDR_A _DQ S#6

DDR_A _D5 4
DDR_A _D4 9
DDR_A _D5 0
DDR_A _D5 1
DDR_A _D5 2
DDR_A _D4 8
DDR_A _D5 3
DDR_A _D5 5

12

RD7 240 _0 402 _1 %RD7 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _M A1 5 DDR_A _M A1 5

@

@

UD5

UD5

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD7

UD7

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0

ODT

F7

CK

G7

M_C LK_ DDR# 0

CK#

G9

DDR_A _CK E0

CKE

H2

DDR_A _CS 0#

CS#

F3

DDR_A _RA S#

RAS#

G3

DDR_A _CA S#

CAS#

H3

DDR_A _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+1.3 5V +1.3 5V

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

+VRE FDQ_ A
+VRE FCA_ A

DDR_A _B S2[11,12 ,15 ,7]
DDR_A _B S1[11,12 ,15 ,7]
DDR_A _B S0[11,12 ,15 ,7]

DDR_A _DQ S5
DDR_A _DQ S#5

DDR_A _D4 2
DDR_A _D4 1DDR_A _D3 3
DDR_A _D4 6
DDR_A _D4 4
DDR_A _D4 7
DDR_A _D4 5
DDR_A _D4 3
DDR_A _D4 0

12

RD6 240 _0 402 _1 %RD6 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

DDR_A _DQ S7
DDR_A _DQ S#7

DDR_A _D5 9
DDR_A _D5 7
DDR_A _D5 8
DDR_A _D6 0
DDR_A _D5 6
DDR_A _D6 1
DDR_A _D6 2
DDR_A _D6 3

12

RD8 240 _0 402 _1 %RD8 2 40_ 040 2_ 1%

DDR_A _B S2
DDR_A _B S1
DDR_A _B S0

DDR_A _M A0
DDR_A _M A1
DDR_A _M A2
DDR_A _M A3
DDR_A _M A4
DDR_A _M A5
DDR_A _M A6
DDR_A _M A7
DDR_A _M A8
DDR_A _M A9
DDR_A _M A1 0
DDR_A _M A1 1
DDR_A _M A1 2
DDR_A _M A1 3
DDR_A _M A1 4

2

@

@

UD6

UD6

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD8

UD8

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

1

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 0
M_C LK_ DDR0M_C LK_ DDR0
M_C LK_ DDR# 0
DDR_A _CK E0

DDR_A _CS 0#
DDR_A _RA S#
DDR_A _CA S#
DDR_A _WE #
DDR3_ DRA MRS T#

M_O DT 0
M_C LK_ DDR0M_C LK_ DDR0
M_C LK_ DDR# 0
DDR_A _CK E0

DDR_A _CS 0#
DDR_A _RA S#
DDR_A _CA S#
DDR_A _WE #
DDR3_ DRA MRS T#

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 0 [11, 12, 15, 7]
M_C LK_ DDR0 [11 ,12 ,15 ,7]
M_C LK_ DDR# 0 [11,1 2,1 5,7 ]
DDR_A _CK E0 [1 1,1 2,1 5,7 ]

DDR_A _CS 0# [1 1,1 2,1 5,7 ]
DDR_A _RA S# [1 1,1 2,1 5,7 ]
DDR_A _CA S# [1 1,1 2,1 5,7 ]
DDR_A _WE # [11 ,12 ,15 ,7]DDR_A _WE # [11 ,12 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

+1.3 5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD30

CD30

CD29

CD29

1

A A

12

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD33

CD34

CD34

1

12

2

5

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD38

CD38

CD37

CD37

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD41

CD41

CD42

CD42

1

12

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P12-DDRIII C hannel_A Upper

P12-DDRIII C hannel_A Upper

P12-DDRIII C hannel_A Upper

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

12 54Fri da y, S epte mb er 2 8, 201 2

12 54Fri da y, S epte mb er 2 8, 201 2

12 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0

5

D D

DDR_B _DQ S#[ 0..7 ][1 4,7 ]

DDR_B _DQ S[0 ..7][14, 7]

DDR_B _D[ 0..6 3][14 ,7]

DDR_B _M A[0 ..15 ][14, 15,7 ]

All VREF traces should
have 10 mil trace width

UD9

UD9

UD10

UD10

C C

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@

X76 _M IC_4 G@

X76 _M IC_4 G@

SA0 000 5S O0L

SA0 000 5S O0L

SA0 000 5S O0L

SA0 000 5S O0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@

X76 _HY N_2 G@

X76 _HY N_2 G@

SA0 000 4RG 0L

SA0 000 4RG 0L

SA0 000 4RG 0L

SA0 000 4RG 0L

UD9

UD9

UD10

UD10

DRAM

DRAM

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@

X76 _HY N_4 G@

X76 _HY N_4 G@

SA0 000 5JT 0L

SA0 000 5JT 0L

SA0 000 5JT 0L

UD9

UD9

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD9

UD9

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5JT 0L

UD10

UD10

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD10

UD10

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

B B

UD11

UD11

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD11

UD11

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD11

UD11

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD11

UD11

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD11

UD11

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD11

UD11

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

UD12

UD12

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD12

UD12

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD12

UD12

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD12

UD12

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD12

UD12

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD12

UD12

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_B _DQ S0
DDR_B _DQ S#0

DDR_B _D3
DDR_B _D4
DDR_B _D2
DDR_B _D7
DDR_B _D0
DDR_B _D5
DDR_B _D6
DDR_B _D1

12

RD9 240 _0 402 _1 %RD9 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

DDR_B _DQ S2
DDR_B _DQ S#2

DDR_B _D2 2
DDR_B _D1 8
DDR_B _D1 6
DDR_B _D2 3
DDR_B _D2 0
DDR_B _D1 7
DDR_B _D1 9
DDR_B _D2 1

12

RD11 2 40_ 04 02_ 1%R D11 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

@

@

UD9

UD9

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD11

UD11

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

DDR_B _DQ S1
DDR_B _DQ S#1

DDR_B _D1 5
DDR_B _D1 2
DDR_B _D1 0
DDR_B _D9
DDR_B _D1 4
DDR_B _D8
DDR_B _D1 1
DDR_B _D1 3

12

RD10 2 40_ 04 02_ 1%R D10 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _DQ S3
DDR_B _DQ S#3

DDR_B _D3 0
DDR_B _D2 4
DDR_B _D2 6
DDR_B _D2 8
DDR_B _D2 7
DDR_B _D2 5
DDR_B _D3 1
DDR_B _D2 9

12

RD12 2 40_ 04 02_ 1%R D12 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

2

@

@

UD10

UD10

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD12

UD12

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

+1.3 5V

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

M_C LK_ DDR2M_C LK_ DDR2

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

1

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

A A

1U_0402_6.3V6K~D

CD58

CD58

CD57

CD57

1

12

2

5

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD60

CD60

CD59

CD59

1

12

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD62

CD62

CD61

CD61

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD63

CD63

CD64

CD64

1

12

2

1

+

+

CD12 6

CD12 6
330 U_B 2_2 VM _R1 5M

330 U_B 2_2 VM _R1 5M

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Memory Channel B SPD EEPROM

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

+3V S

PCH_ SM BCL K[1 1,1 7,3 4]
PCH_ SM BDA TA[11 ,17 ,34 ]

2

UD18

@ UD18

@

AT2 4C0 2C-X HM-T _T SS OP 8

AT2 4C0 2C-X HM-T _T SS OP 8

8

A0

VCC

7

A1

WP

6

A2

SCL

5

GND4SDA

Non-CIS part

@

@

1

RD41 1 K_ 040 2_5 %~ D

RD41 1 K_ 040 2_5 %~ D

2

RD42 1 K_ 040 2_5 %~ D

RD42 1 K_ 040 2_5 %~ D

3

@

@

Tit le

Tit le

Tit le

P13-DDRIII C hannel_B Lower

P13-DDRIII C hannel_B Lower

P13-DDRIII C hannel_B Lower

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

+3V S

12
12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

+3V S

1

CD12 8

@ CD128

@

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

2

13 54Fri da y, S epte mb er 2 8, 201 2

13 54Fri da y, S epte mb er 2 8, 201 2

13 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

D D

DDR_B _DQ S#[ 0..7 ][1 3,7 ]

DDR_B _DQ S[0 ..7][13, 7]

DDR_B _D[ 0..6 3][13 ,7]

DDR_B _M A[0 ..15 ][13, 15,7 ]

All VREF traces should
have 10 mil trace width

UD13

UD13

UD14

UD14

UD15

UD15

UD16

UD16

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

X76 _M IC_2 G@

SA0 000 5P R0L

SA0 000 5P R0L

SA0 000 5P R0L

UD13

UD13

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD13

UD13

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD13

UD13

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD13

UD13

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD13

UD13

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

SA0 000 5P R0L

UD14

UD14

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD14

UD14

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD14

UD14

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD14

UD14

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD14

UD14

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

C C

B B

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD15

UD15

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD15

UD15

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD15

UD15

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD15

UD15

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD15

UD15

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

DRAM

X76 _M IC_2 G@

X76 _M IC_2 G@
SA0 000 5P R0L

SA0 000 5P R0L

UD16

UD16

DRAM

DRAM

X76 _M IC_4 G@

X76 _M IC_4 G@
SA0 000 5S O0L

SA0 000 5S O0L

UD16

UD16

DRAM

DRAM

X76 _HY N_2 G@

X76 _HY N_2 G@
SA0 000 4RG 0L

SA0 000 4RG 0L

UD16

UD16

DRAM

DRAM

X76 _HY N_4 G@

X76 _HY N_4 G@
SA0 000 5JT 0L

SA0 000 5JT 0L

UD16

UD16

DRAM

DRAM

X76 _SA M_ 2G@

X76 _SA M_ 2G@
SA0 000 5P 90L

SA0 000 5P 90L

UD16

UD16

DRAM

DRAM

X76 _SA M_ 4G@

X76 _SA M_ 4G@
SA0 000 5A T0 L

SA0 000 5A T0 L

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

For 4Gb Using For 4Gb Using

4

DDR_B _DQ S4
DDR_B _DQ S#4

DDR_B _D3 4

DDR_B _D3 5
DDR_B _D3 8
DDR_B _D3 2
DDR_B _D3 7
DDR_B _D3 9
DDR_B _D3 6

12

RD13 2 40_ 04 02_ 1%R D13 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

DDR_B _DQ S6
DDR_B _DQ S#6

DDR_B _D5 0
DDR_B _D4 9
DDR_B _D5 5
DDR_B _D5 1
DDR_B _D5 3
DDR_B _D4 8
DDR_B _D5 4
DDR_B _D5 2

12

RD15 2 40_ 04 02_ 1%R D15 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _M A1 5 DDR_B _M A1 5

@

@

UD13

UD13

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD15

UD15

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2

ODT

F7

CK

G7

M_C LK_ DDR# 2

CK#

G9

DDR_B _CK E0

CKE

H2

DDR_B _CS 0#

CS#

F3

DDR_B _RA S#

RAS#

G3

DDR_B _CA S#

CAS#

H3

DDR_B _WE #

WE#

N2

DDR3_ DRA MRS T#

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

3

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+1.3 5V +1.3 5V

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

+VRE FDQ_ B
+VRE FCA_ B

DDR_B _B S2[13,14 ,15 ,7]
DDR_B _B S1[13,14 ,15 ,7]
DDR_B _B S0[13,14 ,15 ,7]

DDR_B _DQ S5
DDR_B _DQ S#5

DDR_B _D4 2
DDR_B _D4 1DDR_B _D3 3
DDR_B _D4 7
DDR_B _D4 4
DDR_B _D4 5
DDR_B _D4 6
DDR_B _D4 3
DDR_B _D4 0

12

RD14 2 40_ 04 02_ 1%R D14 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

DDR_B _DQ S7
DDR_B _DQ S#7

DDR_B _D6 3
DDR_B _D5 6
DDR_B _D5 9
DDR_B _D5 7
DDR_B _D5 8
DDR_B _D6 1
DDR_B _D6 2
DDR_B _D6 0

12

RD16 2 40_ 04 02_ 1%R D16 2 40_ 040 2_ 1%

DDR_B _B S2
DDR_B _B S1
DDR_B _B S0

DDR_B _M A0
DDR_B _M A1
DDR_B _M A2
DDR_B _M A3
DDR_B _M A4
DDR_B _M A5
DDR_B _M A6
DDR_B _M A7
DDR_B _M A8
DDR_B _M A9
DDR_B _M A1 0
DDR_B _M A1 1
DDR_B _M A1 2
DDR_B _M A1 3
DDR_B _M A1 4

2

@

@

UD14

UD14

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

@

@

UD16

UD16

C3

DQS

D3

DQS#

B3

DQ0

C7

DQ1

C2

DQ2

C8

DQ3

E3

DQ4

E8

DQ5

D2

DQ6

E7

DQ7

A7

NF/TDQS#

B7

DM/TDQS

H8

ZQ

E1

VREFDQ

J8

VREFCA

J3

BA2

K8

BA1

J2

BA0

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC#

N3

A13

N7

A14

F1

NC

H1

NC

A3

NC

J7

NC

F9

NC

H9

NC

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

MT 41K 25 6M 8DA-1 5E -M_ FBGA 78

RESET#

RESET#

1

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

M_O DT 2
M_C LK_ DDR2M_C LK_ DDR2
M_C LK_ DDR# 2
DDR_B _CK E0

DDR_B _CS 0#
DDR_B _RA S#
DDR_B _CA S#
DDR_B _WE #
DDR3_ DRA MRS T#

M_O DT 2
M_C LK_ DDR2M_C LK_ DDR2
M_C LK_ DDR# 2
DDR_B _CK E0

DDR_B _CS 0#
DDR_B _RA S#
DDR_B _CA S#
DDR_B _WE #
DDR3_ DRA MRS T#

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

M_O DT 2 [13, 14, 15, 7]
M_C LK_ DDR2 [13 ,14 ,15 ,7]
M_C LK_ DDR# 2 [13,1 4,1 5,7 ]
DDR_B _CK E0 [1 3,1 4,1 5,7 ]

DDR_B _CS 0# [1 3,1 4,1 5,7 ]
DDR_B _RA S# [1 3,1 4,1 5,7 ]
DDR_B _CA S# [1 3,1 4,1 5,7 ]
DDR_B _WE # [13 ,14 ,15 ,7]
DDR3_ DRA MRS T# [11,1 2,1 3,1 4,6]

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

C1

VDDQ

E2

VDDQ

B9

VDDQ

E9

VDDQ

A2

VDD

A9

VDD

D7

VDD

G2

VDD

G8

VDD

K1

VDD

K9

VDD

M1

VDD

M9

VDD

G1

ODT

F7

CK

G7

CK#

G9

CKE

H2

CS#

F3

RAS#

G3

CAS#

H3

WE#

N2

B2

VSSQ

B8

VSSQ

C9

VSSQ

D1

VSSQ

D9

VSSQ

A1

VSS

A8

VSS

B1

VSS

D8

VSS

F2

VSS

F8

VSS

J1

VSS

J9

VSS

L1

VSS

L9

VSS

N1

VSS

N9

VSS

+1.3 5V +1.3 5V+1.3 5V +1.3 5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD85

CD85

CD86

CD86

1

A A

12

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD87

CD87

CD88

CD88

1

12

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD89

CD89

CD90

CD90

1

12

2

4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD91

CD91

CD92

CD92

1

12

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P14-DDRIII C hannel_B Upper

P14-DDRIII C hannel_B Upper

P14-DDRIII C hannel_B Upper

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et

Date : She et of

Date : She et of

1

of

14 54Fri da y, S epte mb er 2 8, 201 2

14 54Fri da y, S epte mb er 2 8, 201 2

14 54Fri da y, S epte mb er 2 8, 201 2

1.0

1.0

1.0

5

+1.3 5V

12

RD17

RD17
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD19
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

D D

1

CD113

CD113

2

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

12

RD19

+VRE FCA_ A

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

CD114

CD114

2

RD18

RD18
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD20

RD20
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

+1.3 5V

4

3

2

1

12

+VRE FCA_ B

.1U_0402_16V7K~D

.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

12

1

1

CD116

CD116

CD115

CD115

2

2

+1.3 5V

M1 M1

12

RD21

RD21
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

12

RD25

RD25
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

M3

C C

B B

A A

+VRE FDQ_ A

Deep S3 Support

+VRE FDQ_ B

Deep S3 Support

DRAM RST _C NTRL

DRAM RST _C NTRL

5

DRAM RST _C NTRL[6 ]

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

+VRE FDQ_ A

RD27 0 _04 02 _5% ~D@RD2 7 0_ 040 2_5 %~ D@

RD30 0 _04 02 _5% ~D@RD3 0 0_ 040 2_5 %~ D@

1 2

1 3

D

D

1 2

1 3

D

D

+VRE FDQ_ A

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

1

2

S

S

G

G

2

QD1

QD1

BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

S

S

G

G

2

QD2

QD2

BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

CD118

CD118

CD117

CD117

2

V_DD R_RE FA_ R [9]

12

RD29

@ RD29

@

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

V_DD R_RE FB_ R [9]

12

RD32

@ RD32

@

1K_ 040 2_ 5%~ D

1K_ 040 2_ 5%~ D

+1.3 5V

12

12

RD22

RD22
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

RD26

RD26
1K_ 040 2_ 1%~ D

1K_ 040 2_ 1%~ D

4

+VRE FDQ_ B

+VRE FDQ_ B

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

.1U_0402_16V7K~D

.1U_0402_16V7K~D

1

1

CD119

CD119

CD120

CD120

2

2

+0.675VS +0.675VS

DDR_A _M A1 2
DDR_A _M A1 5
DDR_A _M A0

DDR_A _M A[0 ..15 ][11, 12,7 ]

DDR_B _M A[0 ..15 ][13, 14,7 ]

+0.675VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD12 9

CD12 9

2

+0.675VS

1

CD13 6

CD13 6

2

CD13 3

CD13 3

CD13 2

CD13 2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD13 9

CD13 9

CD14 0

CD14 0

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD13 5

CD13 5

2

2

DDR_A _CK E0[11 ,12 ,7]
DDR_A _RA S#[11 ,12 ,7]
DDR_A _CS 0#[1 1,1 2,7 ]
DDR_A _CA S#[11 ,12 ,7]

DDR_A _WE #[11 ,12, 7]
DDR_A _B S0[11, 12, 7]
DDR_A _B S2[11, 12, 7]
DDR_A _B S1[11, 12, 7]

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD14 2

CD14 2

2

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

M_O DT 0[11,12, 7] M_O DT 2[13,14, 7]

M_C LK_ DDR0[11 ,12, 7]

M_C LK_ DDR# 0[11,1 2,7 ]

Issued Date

Issued Date

Issued Date

DDR_A _M A1 0

DDR_A _M A4
DDR_A _M A2
DDR_A _M A1
DDR_A _M A6

DDR_A _M A3
DDR_A _M A9
DDR_A _M A1 1
DDR_A _M A5

DDR_A _M A1 4
DDR_A _M A7
DDR_A _M A8
DDR_A _M A1 3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

1 2

R103 6 36 _0 402 _1 %~DR 103 6 36 _0 402 _1 %~D

1 2

R103 8 36 _0 402 _1 %~DR 103 8 36 _0 402 _1 %~D

1 2

R104 0 36 _0 402 _1 %~DR 104 0 36 _0 402 _1 %~D

1 2

R104 2 36 _0 402 _1 %~DR 104 2 36 _0 402 _1 %~D

1 2

R104 4 36 _0 402 _1 %~DR 104 4 36 _0 402 _1 %~D

1 2

R104 6 36 _0 402 _1 %~DR 104 6 36 _0 402 _1 %~D

1 2

R104 8 36 _0 402 _1 %~DR 104 8 36 _0 402 _1 %~D

1 2

R105 0 36 _0 402 _1 %~DR 105 0 36 _0 402 _1 %~D

1 2

R105 2 36 _0 402 _1 %~DR 105 2 36 _0 402 _1 %~D

1 2

R105 4 36 _0 402 _1 %~DR 105 4 36 _0 402 _1 %~D

1 2

R105 6 36 _0 402 _1 %~DR 105 6 36 _0 402 _1 %~D

1 2

R105 8 36 _0 402 _1 %~DR 105 8 36 _0 402 _1 %~D

1 2

R106 0 36 _0 402 _1 %~DR 106 0 36 _0 402 _1 %~D

1 2

R106 2 36 _0 402 _1 %~DR 106 2 36 _0 402 _1 %~D

1 2

R106 4 36 _0 402 _1 %~DR 106 4 36 _0 402 _1 %~D

1 2

R106 6 36 _0 402 _1 %~DR 106 6 36 _0 402 _1 %~D

1 2

R106 8 36 _0 402 _1 %~DR 106 8 36 _0 402 _1 %~D

1 2

R107 0 36 _0 402 _1 %~DR 107 0 36 _0 402 _1 %~D

1 2

R107 2 36 _0 402 _1 %~DR 107 2 36 _0 402 _1 %~D

1 2

R107 4 36 _0 402 _1 %~DR 107 4 36 _0 402 _1 %~D

1 2

R107 6 36 _0 402 _1 %~DR 107 6 36 _0 402 _1 %~D

1 2

R107 8 36 _0 402 _1 %~DR 107 8 36 _0 402 _1 %~D

1 2

R108 0 36 _0 402 _1 %~DR 108 0 36 _0 402 _1 %~D

1 2

R108 2 36 _0 402 _1 %~DR 108 2 36 _0 402 _1 %~D

RD33

RD33
36_ 040 2_ 1%~ D

36_ 040 2_ 1%~ D

1 2

1 2

RD35 3 0_0 40 2_1 %~DRD3 5 30_ 04 02_ 1%~ D

1

CD12 1

CD12 1

1.5P _0 402 _5 0V8 C~D

1.5P _0 402 _5 0V8 C~D

2

1 2

RD37 3 0_0 40 2_1 %~DRD3 7 30_ 04 02_ 1%~ D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CD12 3

CD12 3

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

DDR_B _M A1 2
DDR_B _M A1 5
DDR_B _M A0
DDR_B _M A1 0

DDR_B _M A1 4
DDR_B _M A6
DDR_B _M A4
DDR_B _M A2

DDR_B _M A8
DDR_B _M A1
DDR_B _M A1 3
DDR_B _M A7

DDR_B _M A3
DDR_B _M A9
DDR_B _M A1 1
DDR_B _M A5

DDR_B _CK E0[13 ,14 ,7]
DDR_B _CS 0#[1 3,1 4,7 ]
DDR_B _CA S#[13 ,14 ,7]
DDR_B _RA S#[13 ,14 ,7]

DDR_B _B S1[13, 14, 7]
DDR_B _B S2[13, 14, 7]
DDR_B _B S0[13, 14, 7]
DDR_B _WE #[13 ,14, 7]

M_C LK_ DDR2[13 ,14, 7]

M_C LK_ DDR# 2[13,1 4,7 ]

1

2

Tit le

Tit le

Tit le

P15-DDRIII Vref & Ter mination

P15-DDRIII Vref & Ter mination

P15-DDRIII Vref & Ter mination

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et

Date : She et of

Date : She et of

1 2

R103 7 36 _0 402 _1 %~DR 103 7 36 _0 402 _1 %~D

1 2

R103 9 36 _0 402 _1 %~DR 103 9 36 _0 402 _1 %~D

1 2

R104 1 36 _0 402 _1 %~DR 104 1 36 _0 402 _1 %~D

1 2

R104 3 36 _0 402 _1 %~DR 104 3 36 _0 402 _1 %~D

1 2

R104 5 36 _0 402 _1 %~DR 104 5 36 _0 402 _1 %~D

1 2

R104 7 36 _0 402 _1 %~DR 104 7 36 _0 402 _1 %~D

1 2

R104 9 36 _0 402 _1 %~DR 104 9 36 _0 402 _1 %~D

1 2

R105 1 36 _0 402 _1 %~DR 105 1 36 _0 402 _1 %~D

1 2

R105 3 36 _0 402 _1 %~DR 105 3 36 _0 402 _1 %~D

1 2

R105 5 36 _0 402 _1 %~DR 105 5 36 _0 402 _1 %~D

1 2

R105 7 36 _0 402 _1 %~DR 105 7 36 _0 402 _1 %~D

1 2

R105 9 36 _0 402 _1 %~DR 105 9 36 _0 402 _1 %~D

1 2

R106 1 36 _0 402 _1 %~DR 106 1 36 _0 402 _1 %~D

1 2

R106 3 36 _0 402 _1 %~DR 106 3 36 _0 402 _1 %~D

1 2

R106 5 36 _0 402 _1 %~DR 106 5 36 _0 402 _1 %~D

1 2

R106 7 36 _0 402 _1 %~DR 106 7 36 _0 402 _1 %~D

1 2

R106 9 36 _0 402 _1 %~DR 106 9 36 _0 402 _1 %~D

1 2

R107 1 36 _0 402 _1 %~DR 107 1 36 _0 402 _1 %~D

1 2

R107 3 36 _0 402 _1 %~DR 107 3 36 _0 402 _1 %~D

1 2

R107 5 36 _0 402 _1 %~DR 107 5 36 _0 402 _1 %~D

1 2

R107 7 36 _0 402 _1 %~DR 107 7 36 _0 402 _1 %~D

1 2

R107 9 36 _0 402 _1 %~DR 107 9 36 _0 402 _1 %~D

1 2

R108 1 36 _0 402 _1 %~DR 108 1 36 _0 402 _1 %~D

1 2

R108 3 36 _0 402 _1 %~DR 108 3 36 _0 402 _1 %~D

RD34

RD34
36_ 040 2_ 1%~ D

36_ 040 2_ 1%~ D

1 2

1 2

RD36 3 0_0 40 2_1 %~DRD3 6 30_ 04 02_ 1%~ D

1

CD12 2

CD12 2

1.5P _0 402 _5 0V8 C~D

1.5P _0 402 _5 0V8 C~D

2

1 2

RD38 3 0_0 40 2_1 %~DRD3 8 30_ 04 02_ 1%~ D

CD12 4

CD12 4

0.1U _04 02 _10 V7K ~D

0.1U _04 02 _10 V7K ~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

15 54Fri da y, S epte mb er 2 8, 201 2

15 54Fri da y, S epte mb er 2 8, 201 2

15 54Fri da y, S epte mb er 2 8, 201 2

1

1

2

1.0

1.0

1.0

of

5

D D

+RT CVCC

1 2

1 2

LOW=Default
HIGH=No Reboot

+3V _PCH+3V _PC H+ 3V_ PCH

12

RH40

RH40

RH39

RH39

@

@

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

12

RH46

RH46

RH45

RH45

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

12

HDA_ SDO UT

HDA_ SDO UT

12

PCH_ INT VRM EN

HDA_ SPK R

HDA_ SYN C

PCH_ JTA G_ TM S
PCH_ JTA G_ TDI
PCH_ JTA G_ TDO

PCH_ JTA G_ TCK

RH53

RH53
51_ 040 2_ 5%

51_ 040 2_ 5%

RH31 330K _04 02 _5% ~DRH31 330 K_0 402 _5 %~D

RH34 330K _04 02 _5% ~D@ RH 34 330K_ 04 02_ 5% ~D@

INTVRMEN

H：Integrated VRM enable

*

C C

+3V S

RH37 1 K_0 402 _5 %~D@ R H37 1K _0 402 _5% ~D@

L：Integrated VRM disa ble

1 2

*

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in ef fect (default)

H=>Flash Descriptor Security will be overridde n

+3V _PCH

1 2

RH42 1 K_0 402 _5 %~D@ R H42 1K _0 402 _5% ~D@

Low = Disabl ed

*

High = Enabled

B B

HDA_SYNC

This si gnal h as a weak i nternal pu ll-down

is s upplied by

apled hi gh
mpled low
ulled Hi gh for Huron River p latfrom

+3V _PCH

1 2

RH27 9 1K_ 040 2_ 5%~ DRH27 9 1K_ 040 2_ 5%~ D

PCH JTAG

12

12

RH38

RH38

@

@

@

@

200_0402_5%

200_0402_5%

12

12

RH44

RH44

A A

100_0402_1%~D

100_0402_1%~D

CH10 3 10P _04 02 _50 V8J ~D@ C H10 3 10P _04 02_ 50 V8J ~D@

+RT CVCC

RH25 20K_0 402 _5 %~DRH25 20K_0 402 _5 %~D

RH23 20K_0 402 _5 %~DRH23 20K_0 402 _5 %~D

HDA_ SYN C_AU DIO[ 25]

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1 2

1 2

CH5

CH5

1U_0 40 2_6 .3V 6K~ D

1U_0 40 2_6 .3V 6K~ D

1

CH4

CH4

2

1

2

Reserve for RF please close to UH1

5

4

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

32.7 68 KHZ_ 12. 5PF _CM 31 532 768 DZFT

CMOS

12

@

@

CLRP 1

CLRP 1
SHOR T P ADS

SHOR T P ADS

PCH_ RTC RST #

PCH_ SRT CRST #

12

@

@

CLRP 2

CLRP 2
SHOR T P ADS

SHOR T P ADS

ME CMOS

CLP1 & CLP2 place near DIMM

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

1 2

HDA_ SYN C_R HDA _S YNC

RH33 33_0 402 _5 %~DRH33 33_04 02 _5% ~D

1 2

4

CH2 1 8P _04 02 _50 V8J ~DCH 2 1 8P_ 04 02_ 50V 8J~ D

CH3 1 8P _04 02 _50 V8J ~DCH 3 1 8P_ 04 02_ 50V 8J~ D

far away hot spot

HDA_ BIT CLK _AU DIO

1

CH11 7

CH11 7

2

CH11 8

@ CH11 8

@

1 2

12P _04 02 _50 V8J ~D

12P _04 02 _50 V8J ~D

+5V S

G

G

2

S

S

1 2

RH36 0 _04 02 _5% ~D@R H36 0 _04 02_ 5% ~D@

RH27 5

RH27 5
1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

PCH_ SPI _CS #

PCH_ SPI _SO

2

8/20, Follow DFB suggest, modify YH1 footprint.

12

12

12

RH2

RH2

YH1

YH1

10M _0 402 _5 %

10M _0 402 _5 %

12

RH11

RH11

+RT CVCC

HDA_ SPK R[25]

HDA_ RST _A UDIO#[2 5]

HDA_ SDIN 0[25]

HDA_ SDO UT_ AUDI O[ 25]

HDA_ SDO[35]

From EC, for enable ME code progr aming

PCH_ SPI _CL K

QH1

QH1
BSS 138 _NL _SO T2 3-3

BSS 138 _NL _SO T2 3-3

13

D

D

RH54

RH54

3.3K_0402_5%~D

3.3K_0402_5%~D

+3V _PCH

1 2

PCH_ SPI _WP #

1 2

PCH_ SPI _CL K_R

RH57

RH57

3.3K_0402_5%~D

3.3K_0402_5%~D

RH28 33_ 040 2_ 5%~ DRH28 33_ 04 02_ 5% ~D

RH30 33_ 040 2_ 5%~ DRH30 33_ 04 02_ 5% ~D

RH24 1K_ 040 2_ 5%~ DRH24 1K_0 40 2_5 %~D

1

2

3

W25Q64

3

UH1A

UH1A

A19

PCH_ RTC X1

PCH_ RTC X2

PCH_ RTC RST #

PCH_ SRT CRST #

1 2

SM_ INT RUDE R#

1M_ 04 02_ 5% ~D

1M_ 04 02_ 5% ~D

PCH_ INT VRM EN

1 2

HDA_ BIT _CL K

HDA_ SYN C

RH27

RH27
47_ 040 2_ 5%~ D

47_ 040 2_ 5%~ D

HDA_ SPK R

1 2

HDA_ RST #

HDA_ SDIN 0

1 2

HDA_ SDO UT

1 2

PCH_ JTA G_ TCK

PCH_ JTA G_ TM S

PCH_ JTA G_ TDI

PCH_ JTA G_ TDO

@

@

1 2

PCH_ SPI _CL K

RH25 5 0_0 402 _5 %~D

RH25 5 0_0 402 _5 %~D

PCH_ SPI _CS #

SHORT

PCH_ SPI _SI

PCH_ SPI _SO

SPI ROM FOR ME ( 8MByte )
ROM is Dual Output IC

U48

U48

8

VCC

/CS

7

DO

/WP

GND4DIO

EN25 Q6 4-10 4HIP _S O8~ D

EN25 Q6 4-10 4HIP _S O8~ D

SPI BIOS Pinout

(1)CS# (5)I/O_ 0
(2)I/O_1(6)CLK
(3)WP# (7)HOLD #
(4)GND (8)VCC

PCH_ SPI _HO LD#

/HOLD

6

PCH_ SPI _CL K_R

CLK

5

PCH_ SPI _SI

3

RTCX1

C19

RTCX2

F19

RTCRST#

A23

SRTCRST#

K22

INTRUDER#

C21

INTVRMEN

H35

HDA_BCLK

H37

HDA_SYNC

N1

SPKR

F35

HDA_RST#

D36

HDA_SDIN0

B36

HDA_SDIN1

C35

HDA_SDIN2

A35

HDA_SDIN3

K37

HDA_SDO

K35

HDA_DOCK_EN# / GPIO33

M35

HDA_DOCK_RST# / GPIO13

M17

JTAG_TCK

M15

JTAG_TMS

U12

JTAG_TDI

M12

JTAG_TDO

AD12

SPI_CLK

AB8

SPI_CS0#

AB6

SPI_CS1#

W8

SPI_MOSI

Y2

SPI_MISO

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

1 2

RH56 3.3K_ 04 02_ 5% ~DRH56 3.3K_ 04 02_ 5% ~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

2

A37

FWH0 / LAD0

A39

FWH1 / LAD1

C39

FWH2 / LAD2

C37

FWH3 / LAD3

K40

FWH4 / LFRAME#

H40

LDRQ0#

F37

LDRQ1# / GPIO23

Y4

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATALED#

AN3
AN1
AU3
AU1

AN6
AN8
AR3
AR1

AD4
AD2
AL3
AL1

AD8
AD6
AG3
AG1

AE3
AE1
AH8
AH6

AC3
AC1
AJ3
AJ1

AB10

AB12

AF10

AF12

AH4

W10

M2

R1

SERI RQ

SAT A_ COM P

RH41 37.4 _04 02_ 1%RH41 37.4_0 402 _1 %

Width = 10 mil, Spac ing = 20 mil
Close PCH wi thin 500 mil

SAT A3 _CO MP

RH43 49.9 _04 02_ 1% ~DRH43 4 9.9 _04 02 _1% ~D

RBIA S_S AT A3

RH48 750_ 040 2_ 1%RH4 8 750_04 02 _1%

PCH_ SAT AL ED#

PCH_ GPI O21

BBS _BI T0 _R

1 2

1 2

1 2

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

LPC

LPC

SATA3

SATA3

SATA

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SATA1GP / GPIO19

Boot BIOS Strap

1 1

*

+3V _PCH

1

CH6

CH6
.1U_ 040 2_ 16V 7K~ D

.1U_ 040 2_ 16V 7K~ D

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

2

CH94

@ CH94

@

12

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

Reserve for EMI please close to U48

LPC_ AD0 [27,2 8,3 5]
LPC_ AD1 [27,2 8,3 5]
LPC_ AD2 [27,2 8,3 5]
LPC_ AD3 [27,2 8,3 5]

LPC_ FRA ME # [27,28 ,35 ]

SERI RQ [27,3 5]

+1.0 5VS _V CC_S AT A

12

RH35 10K_ 040 2_ 5%~ D@ RH3 5 10K_0 402 _5% ~D@

12

RH32 10K_ 040 2_ 5%~ DRH32 10K_0 402 _5 %~D

12

RH27 6 10K _04 02 _5% ~DRH27 6 10K _04 02 _5% ~D

Boot BIOS LocationBBS_BIT[0]B BS_BIT[1]

SPI

RH25 6

@ RH25 6

@

1 2

PCH_ SPI _CL K_R

33_ 040 2_ 5%~ D

33_ 040 2_ 5%~ D

1

SERI RQ

SAT A_ PRX _DT X_N 0 [2 9]
SAT A_ PRX _DT X_P 0 [29 ]HDA_ BIT CLK _AU DIO[ 25]
SAT A_ PT X_DR X_N 0 [2 9]
SAT A_ PT X_DR X_P 0 [29 ]

+VCC P

+3V S

Tit le

Tit le

Tit le

P16-PCH (1/8) SATA,HDA,SPI, LPC

P16-PCH (1/8) SATA,HDA,SPI, LPC

P16-PCH (1/8) SATA,HDA,SPI, LPC

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

12

RH29 10K _04 02 _5% ~DRH29 10K _04 02 _5% ~D

mSATA

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

+3V S

1.0

1.0

1.0

16 54Fri da y, S epte mb er 2 8, 201 2

16 54Fri da y, S epte mb er 2 8, 201 2

16 54Fri da y, S epte mb er 2 8, 201 2

5

MiniWLAN --->

PCIE _PR X_W LANT X_ N3[28]
PCIE _PR X_W LANT X_ P3[28 ]
PCIE _PT X_ WLA NRX_ N3[28]
PCIE _PT X_ WLA NRX_ P3[28 ]

CLK_ PCI E_M INI1 #[2 8]
CLK_ PCI E_M INI1[ 28]

MINI 1CL K_R EQ#[28]

1 2

CH11 0.1U _04 02 _10 V7K ~DC H11 0.1U _04 02_ 10 V7K ~D

1 2

CH16 0.1U _04 02 _10 V7K ~DC H16 0.1U _04 02_ 10 V7K ~D

RH91 1 0K_ 040 2_ 5%~ DRH9 1 10K _04 02 _5% ~D

+3V _PCH

RH95 10K _04 02 _5% ~DRH95 10K _04 02 _5% ~D

+3V S

RH10 0 10K _04 02 _5% ~DRH10 0 10K _04 02 _5% ~D

+3V S

RH10 3 10K _04 02 _5% ~DRH10 3 10K _04 02 _5% ~D

+3V _PCH

RH10 7 10K _04 02 _5% ~DRH10 7 10K _04 02 _5% ~D

+3V _PCH

RH11 0 10K_0 402 _5 %~DR H11 0 1 0K _04 02 _5% ~D

+3V _PCH

RH11 2 10K_0 402 _5 %~DR H11 2 1 0K _04 02 _5% ~D

+3V _PCH

RH11 6 10K_0 402 _5 %~DR H11 6 1 0K _04 02 _5% ~D

+3V _PCH

RH11 8 10K_0 402 _5 %~DR H11 8 1 0K _04 02 _5% ~D

+3V _PCH

D D

C C

B B

MiniWLAN --->

1 2

1 2

1 2

1 2

1 2

T23 9@ T2 39@
T24 0@ T2 40@

12

12

12

12

4

PCIE _PT X_ WLA NRX_ N3_ C
PCIE _PT X_ WLA NRX_ P3 _C

T81@ T8 1@
T82@ T8 2@

PCH_ GPI O73

PCH_ GPI O18

PCH_ GPI O20

MINI 1CL K_R EQ#

PCH_ GPI O26

PCH_ GPI O44

PEG _B_ CLK REQ #

PCH_ GPI O45

PCH_ GPI O46

CLK_ BCL K_ ITP #
CLK_ BCL K_ ITP

UH1B

UH1B

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0# / GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1# / GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2# / GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3# / GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4# / GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5# / GPIO44

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ# / GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6# / GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7# / GPIO46

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

BD82 QS 77-Q PRF-C 1_B GA 101 7~D

PCI-E*

PCI-E*

CLOCKS

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

H12

F17

F10

H22

K12

A9

C9

D12

C11

L3

J1

M8

R8

AF44
AF46

BB24
AY24

AN10
AN12

BD17
BF17

BB26
AY26

M24
K24

AK8
AK6

J49

E51

W49
W51

AC49

H50

D48

G49

J51

SMB AL ERT #

SMB CLK

SMB DAT A

DRAM RST _C NTRL _P CH

SML 0CL K

SML 0DA TA

NFC_I RQ

SML 1CL K

SML 1DA TA

Total device

No support iAMT

PEG _A_ CLK RQ#

CLKI N_DM I#
CLKI N_DM I

CLKI N_DM I2 #
CLKI N_DM I2

CLKI N_DO T9 6#
CLKI N_DO T9 6

CLKI N_S AT A#
CLKI N_S AT A

CLK_ PCH _14 M

CLK_ PCI _LP BAC K

XTA L2 5_I N
XTA L2 5_O UT

XCLK _RC OM P

CLKF LEX 0

RH29 6 2 2_0 40 2_5 %~DRH29 6 2 2_0 40 2_5 %~D

KB_ DET #

KB_ DET #

SMB CLK [28]

SMB DAT A [2 8]

DRAM RST _C NTRL _P CH [6]

+3V _PCH

RH14 1

RH14 1
10K _04 02 _5% ~D

10K _04 02 _5% ~D

1 2

CLK_ CPU _DM I# [6]
CLK_ CPU _DM I [6]

CLK_ CPU _DPL L# [6 ]
CLK_ CPU _DPL L [6]

CLK_ PCI _LP BAC K [19 ]

1 2

RH11 3 90 .9_ 040 2_ 1%RH113 9 0.9 _04 02 _1%

1 2

1 2

RH30 2 100 K_0 40 2_5 %~DRH30 2 100 K_0 40 2_5 %~D

2

+VCC P

CLK_ PCI _T PM [27]

KB_ DET # [3 3]

+3V S

1

+3V _PCH

SMB CLK

SMB DAT A

SML 0CL K

SML 0DA TA

SML 1CL K

SML 1DA TA

DRAM RST _C NTRL _P CH

NFC_I RQ

SMB AL ERT #

NFC_I RQ

CLKI N_DM I2 #
CLKI N_DM I2
CLKI N_DM I#
CLKI N_DM I
CLKI N_DO T9 6#
CLKI N_DO T9 6
CLKI N_S AT A#
CLKI N_S AT A
CLK_ PCH _14 M

If use e xtenal CLK ge n, please place clos e to CLK gen
else, please place close to PCH

CLK_ PCH _14 M

Reserve for EMI please close to UH1

CLK_ PCI _LP BAC K

Reserve for EMI please close to UH1

XTA L2 5_I N

XTA L2 5_O UT

+3V S

+3V S

1 2

RH67 2 .2K _04 02_ 5% ~DRH67 2 .2K _04 02_ 5% ~D

1 2

RH69 2.2K_ 04 02_ 5% ~DRH69 2.2K_ 04 02_ 5% ~D

1 2

RH70 2 .2K _04 02_ 5% ~DRH70 2 .2K _04 02_ 5% ~D

1 2

RH72 2 .2K _04 02_ 5% ~DRH72 2 .2K _04 02_ 5% ~D

1 2

RH73 2 .2K _04 02_ 5% ~DRH73 2 .2K _04 02_ 5% ~D

1 2

RH74 2 .2K _04 02_ 5% ~DRH74 2 .2K _04 02_ 5% ~D

1 2

RH75 1K_0 402 _5 %~DRH75 1K_ 040 2_ 5%~ D

1 2

@

@

R517 10 K_0 402 _5 %~D

R517 10 K_0 402 _5 %~D

1 2

R812 10 K_0 402 _5 %~DR81 2 10 K_ 040 2_5 %~D

R110 0 10 0K _04 02 _5% ~DR11 00 1 00K _0 402 _5% ~D

1 2

RH76 10K_0 402 _5% ~DRH76 10K_0 402 _5% ~D

1 2

RH78 10K_0 402 _5% ~DRH78 10K_0 402 _5% ~D

1 2

RH77 10K_0 402 _5% ~DRH77 10K_0 402 _5% ~D

1 2

RH79 10K_0 402 _5% ~DRH79 10K_0 402 _5% ~D

1 2

RH80 10K_0 402 _5% ~DRH80 10K_0 402 _5% ~D

1 2

RH81 10K_0 402 _5% ~DRH81 10K_0 402 _5% ~D

1 2

RH82 10K_0 402 _5% ~DRH82 10K_0 402 _5% ~D

1 2

RH83 10K_0 402 _5% ~DRH83 10K_0 402 _5% ~D

1 2

RH84 10K_0 402 _5% ~DRH84 10K_0 402 _5% ~D

12

CH21

@ CH21

@

RH86 3 3_0 40 2_5 %~D@R H86 3 3_0 402 _5 %~D@

12

CH22

@ CH22

@

RH89 33_0 40 2_5 %~D@ RH89 33_ 040 2_ 5%~ D@

1 2

RH11 7 1M_04 02 _5% ~DRH117 1M_04 02 _5% ~D

YH2

YH2

25M HZ_ 18P F_X 3G0 25 000 DI1H -H~D

25M HZ_ 18P F_X 3G0 25 000 DI1H -H~D

1

IN

OUT

2

GND

GND

1

2

CH24

CH24
15P _04 02 _50 V8J ~D

15P _04 02 _50 V8J ~D

1 2

1 2

12

3

4

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

22P _04 02 _50 V8J ~D

1

2

CH23

CH23
15P _04 02 _50 V8J ~D

15P _04 02 _50 V8J ~D

+3V S

QH3A

SML 1CL K

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

QH4A

QH4A

A A

5

4

SML 1DA TA

354

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

QH4B

QH4B

PCH_ SM LCL K [24,35 ]

PCH_ SM LDA TA [24,35 ]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGI NEERING D RAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC . AND CONTAINS CON FIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS

DEPARTMENTEXCEPT AS AUTHOR IZED BY COMPALELEC TRONICS, I NC. N EITHER THIS SH EET NOR THE IN FORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPALELECTRON ICS, IN C.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2

6 1

SMB CLK

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

RH10 5 0 _0 402 _5 %~D@ RH1 05 0_0 402 _5 %~D@

SMB DAT A

Compal Secret Data

Compal Secret Data

Compal Secret Data

QH3A

6 1

1 2

Deciphered Date

Deciphered Date

Deciphered Date

2.2K _0 402 _5 %~D

2.2K _0 402 _5 %~D

2

QH3B

QH3B

354

DMN6 6D0 LDW-7 _S OT 363 -6~D

DMN6 6D0 LDW-7 _S OT 363 -6~D

1 2

RH11 1 0_0 402 _5 %~D@ RH 111 0 _04 02_ 5% ~D@

2

RH98

RH98

RH99

RH99

2.2K _0 402 _5 %~D

2.2K _0 402 _5 %~D

1 2

1 2

PCH_ SM BCL K [11,13 ,34 ]

Connect DDR SPD, TP

PCH_ SM BDA TA [11,1 3,3 4]

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

P17-PCH (2/8) PCIE, SMB US, CLK

P17-PCH (2/8) PCIE, SMB US, CLK

P17-PCH (2/8) PCIE, SMB US, CLK

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

Size Docu me nt N umb er Rev

LA-8821P

LA-8821P

LA-8821P

Date : She et of

Date : She et of

Date : She et of

17 54Fri da y, S epte mb er 2 8, 201 2

17 54Fri da y, S epte mb er 2 8, 201 2

17 54Fri da y, S epte mb er 2 8, 201 2

1

1.0

1.0

1.0