Bosch TTCAN User Manual

User’s Manual

TTCAN

IP Module

User’s Manual

Revision 1.6TTCAN

manual_about.fm

Revision 1.6

11.11.02

BOSCH

Robert Bosch GmbH

Automotive Electronics

Semiconductors and Integrated Circuits

Digital CMOS Design Group

11.11.02

User’s Manual

Revision 1.6TTCAN

Copyright © 1998, 1999, 2002 Robert Bosch GmbH. All rights reserved. This software and manual are owned by Robert Bosch GmbH, and may be used only as authorized in the license agreement controlling such use. No part of this publication may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Robert Bosch GmbH, or as expressly provided by the license agreement.

Disclaimer

ROBERT BOSCH GMBH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

ROBERT BOSCH GMBH RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO THE PRODUCTS DESCRIBED HEREIN. ROBERT BOSCH GMBH DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN.

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TTCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1. About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1. Change Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1.1. Current Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1.2. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.2. Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.3. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.4. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.5. Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.3.1. Software Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.3.2. CAN Message Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.3.3. Disabled Automatic Retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.3.4. Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.3.4.1. Test Register (addresses 0x0B & 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.3.4.2. Disable Watchdog Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.3.4.3. Silent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.3.4.4. Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.3.4.5. Loop Back combined with Silent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.3.4.6. Software control of Pin CAN_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.3.4.7. No Message RAM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1. Hardware Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2. CAN Protocol Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.2.1. CAN Control Register (addresses 0x01 & 0x00) . . . . . . . . . . . . . . . . . . . . . .17

3.2.2. Status Register (addresses 0x03 & 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.2.2.1. Status Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.3. Error Counter (addresses 0x05 & 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.4. Bit Timing Register (addresses 0x07 & 0x06) . . . . . . . . . . . . . . . . . . . . . . . .19

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3.2.5. BRP Extension Register (addresses 0x0D & 0x0C) . . . . . . . . . . . . . . . . . . .20

3.3. Message Interface Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.3.1. IFx Command Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.3.1.1. Direction = Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.3.1.2. Direction = Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.3.2. IFx Command Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.3.3. IFx Message Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3.3.1. IFx Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3.3.2. IFx Arbitration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3.3.3. IFx Message Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.3.3.4. IFx Data A and Data B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.3.4. Message Object in the Message Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .24

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3.4. Message Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.4.1. Interrupt Register (addresses 0x09 & 0x08) . . . . . . . . . . . . . . . . . . . . . . . . .27

3.4.2. Transmission Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.4.3. New Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.4.4. Interrupt Pending Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.4.5. Message Valid 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5. Registers for Time Triggered Communication . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.5.1. Trigger Memory Access Register (addresses 0x0F & 0x0E) . . . . . . . . . . . .29

3.5.2. IF1 Data B1 and B2 Registers for Trigger Memory Access . . . . . . . . . . . . .29

3.5.3. TT Operation Mode Register (addresses 0x29 & 0x28) . . . . . . . . . . . . . . . .30

3.5.4. TT Matrix Limits1 Register (addresses 0x2B & 0x2A) . . . . . . . . . . . . . . . . .31

3.5.5. TT Matrix Limits2 Register (addresses 0x2D & 0x2C) . . . . . . . . . . . . . . . . .31

3.5.6. TT Application Watchdog Limit Register (addresses 0x2F & 0x2E) . . . . . . .32

3.5.7. TT Interrupt Enable Register (addresses 0x31 & 0x30) . . . . . . . . . . . . . . . .32

3.5.8. TT Interrupt Vector Register (addresses 0x33 & 0x32) . . . . . . . . . . . . . . . . .32

3.5.9. TT Global Time Register (addresses 0x35 & 0x34) . . . . . . . . . . . . . . . . . . .34

3.5.10. TT Cycle Time Register (addresses 0x37 & 0x36) . . . . . . . . . . . . . . . . . . . .34

3.5.11. TT Local Time Register (addresses 0x39 & 0x38) . . . . . . . . . . . . . . . . . . . .34

3.5.12. TT Master State Register (addresses 0x3B & 0x3A) . . . . . . . . . . . . . . . . . .34

3.5.13. TT Cycle Count Register (addresses 0x3D & 0x3C) . . . . . . . . . . . . . . . . . .35

3.5.14. TT Error Level Register (addresses 0x3F & 0x3E) . . . . . . . . . . . . . . . . . . . .35

3.5.15. TUR Numerator Configuration Low Register (addresses 0x57 & 0x56) . . . .35

3.5.16. TUR Denominator Configuration Register (addresses 0x59 & 0x58) . . . . . .36

3.5.17. TUR Numerator Actual Registers (addresses 0x5B & 0x5A) . . . . . . . . . . . .36

3.5.18. TT Stop_Watch Register (addresses 0x61 & 0x60) . . . . . . . . . . . . . . . . . . .36

3.5.19. TT Global Time Preset Register (addresses 0x65 & 0x64) . . . . . . . . . . . . .37

3.5.20. TT Clock Control Register (addresses 0x67 & 0x66) . . . . . . . . . . . . . . . . . .37

3.5.21. TT Sync_Mark Register (addresses 0x69 & 0x68) . . . . . . . . . . . . . . . . . . . .38

3.5.22. TT Time Mark Register (addresses 0x6D & 0x6C) . . . . . . . . . . . . . . . . . . . .39

3.5.23. TT Gap Control Register (addresses 0x6F & 0x6E) . . . . . . . . . . . . . . . . . . .39

4. CAN Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1. Internal CAN Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

4.1.1. Data Transfer Between IFx Registers and Message RAM . . . . . . . . . . . . . .41

4.1.2. Transmission of Messages in Event Driven CAN Communication . . . . . . . .42

4.1.3. Acceptance Filtering of Received Messages . . . . . . . . . . . . . . . . . . . . . . . .43

4.1.3.1. Reception of Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.1.3.2. Reception of Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

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4.1.4. Storing Received Messages in FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . .43

4.1.5. Receive / Transmit Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4.2. Configuration of the Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4.2.1. Configuration of the Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.2.1.1. Bit Time and Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.2.1.2. Propagation Time Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

4.2.1.3. Phase Buffer Segments and Synchronisation . . . . . . . . . . . . . . . . . . . . . . . .47

4.2.1.4. Oscillator Tolerance Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.2.1.5. Configuration of the CAN Protocol Controller . . . . . . . . . . . . . . . . . . . . . . .50

4.2.1.6. Calculation of the Bit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .51

4.2.1.7. Example for Bit Timing at high Baudrate . . . . . . . . . . . . . . . . . . . . . . . . . . .52

4.2.1.8. Example for Bit Timing at low Baudrate . . . . . . . . . . . . . . . . . . . . . . . . . . .53

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4.2.2. Configuration of the Message Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

4.2.2.1. Configuration of a Transmit Object for Data Frames . . . . . . . . . . . . . . . . . .54

4.2.2.2. Configuration of a Single Receive Object for Data Frames . . . . . . . . . . . . .54

4.2.2.3. Configuration of a FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4.2.2.4. Configuration of a Single Receive Object for Remote Frames . . . . . . . . . .55

4.3. CAN Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

4.3.1. Handling of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

4.3.2. Updating a Transmit Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.3.3. Changing a Transmit Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

4.3.4. Reading Received Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

4.3.5. Requesting New Data for a Receive Object . . . . . . . . . . . . . . . . . . . . . . . . .58

4.3.6. Reading from a FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

5. TTCAN Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.1. TTCAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

5.1.1. TTCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

5.1.2. Message Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

5.1.3. Trigger Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

5.1.4. Message Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.1.4.1. Reference Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.1.4.2. Periodic Transmit Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.1.4.3. Event Driven Transmit Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5.2. TTCAN Schedule Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5.2.1. Time Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5.2.2. Potential Time Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5.3. TTCAN Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.3.1. Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.3.2. Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.3.2.1. Periodic Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.3.2.2. Event Driven Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.4. TTCAN Gap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

5.5. Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

5.6. Local Time, Cycle Time, and Global Time and External Clock Synchronisation 67

5.7. TTCAN Interrupt and Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5.8. Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

6. CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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6.1. Customer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

6.2. Timing of the WAIT output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

6.3. Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

7. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.1. List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

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1. About this Document

1.1 Change Control

1.1.1 Current Status

Revision 1.6

1.1.2 Change History

Issue Date By Change Draft 0.0 30.06.00 F. Hartwich First Draft

Revision 0.1 12.01.01 F. Hartwich Gap Control Revision 0.2 21.10.00 F. Hartwich Trigger Memory Revision 1.0 29.11.00 F. Hartwich Cycle Count, Global Time Mark Revision 1.1 11.12.00 F. Hartwich TUR Conﬁguration, Enable Local Time Revision 1.2 13.12.00 F. Hartwich Time Mark Register, TMC Revision 1.3 17.01.01 F. Hartwich TUR Conﬁguration Registers Revision 1.4 30.04.01 F. Hartwich Clock Synch., Stop_Watch, External Events Revision 1.5 12.10.01 F. Hartwich Editorial changes Revision 1.6 11.11.02 F. Hartwich Watchdog, Gap Control, Global Time Preset

1.2 Conventions

The following conventions are used within this User’s Manual. Helvetica bold Names of bits and signals

Helvetica italic

States of bits and signals

1.3 Scope

This document describes the TTCAN IP module and its features from the application programmer’s point of view.

All information necessary to integrate the TTCAN IP module into an user-deﬁned ASIC is located in the ‘Module Integration Guide’.

1.4 References

This document refers to the following documents.

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Ref Author(s) Title

1 FV/SLN1 CAN Speciﬁcation Revision 2.0 2 K8/EIS1 Module Integration Guide 3 K8/EIS1 VHDL Reference CAN User’s Manual 4 ISO ISO 11898-1 “Controller Area Network (CAN) - Part 1:

Data link layer and physical signalling”

5 ISO ISO 11898-4 “Controller Area Network (CAN) - Part 4:

Time triggered communication”

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1.5 Terms and Abbreviations

This document uses the following terms and abbreviations.

Term Meaning

CAN Controller Area Network BSP Bit Stream Processor BTL Bit Timing Logic CRC Cyclic Redundancy Check Register DLC Data Length Code EML Error Management Logic FSE Frame Synchronisation Entity FSM Finite State Machine NTU Network Time Unit TTCAN Time Triggered CAN

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2. Functional Description

2.1 Functional Overview

The TTCAN is a CAN IP module that can be integrated as stand-alone device or as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis. It consists of the components (see ﬁgure 1) CAN_Core, Message RAM, Message Handler, Control Registers, Module Interface, and, for the time triggered function, Trigger Memory and Frame Synchronisation Entity.

The TTCAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch CAN protocol speciﬁcation 2.0 A, B) and according to ISO 11898-4 : “Time triggered communication on CAN”. The bit rate can be programmed to values up to 1MBit/s depending on the used technology. Additional transceiver hardware is required for the connection to the physical layer (the CAN bus line).

TTCAN provides all features of time triggered communication speciﬁed in ISO 11898-4, including event synchronised time triggered communication, global system time, and clock drift compensation. Optionally, it may be restricted to the functions of ISO 11898-1, with the same features as the Bosch C_CAN IP module.

For communication on a CAN network, individual Message Objects are conﬁgured. The Message Objects and Identiﬁer Masks are stored in the Message RAM. The time triggers deﬁning the transmission schedule are stored in the Trigger RAM.

All functions concerning the handling of messages are implemented in the Message Handler. Those functions are acceptance ﬁltering, transfer of messages between the CAN_Core and the Message RAM, and the handling of transmission requests as well as the generation of the module interrupt.

All functions concerning the time schedule and the global system time are implemented in the Frame Synchronisation Entity FSE.

The register set of the TTCAN can be accessed directly by an external CPU via the module interface. These registers are used to control/conﬁgure the CAN_Core and the Message Handler and to access the single-ported Message RAM.

The module interfaces delivered with the TTCAN IP module can easily be replaced by a customized module interface adapted to the needs of the user.

The TTCAN implements the following features:

•Supports CAN protocol version 2.0 part A, B and TTCAN (ISO 11898-4)

•Bit rates up to 1 MBit/s

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•32 Message Objects, each Message Object has its own Identiﬁer Mask

•Programmable FIFO mode for Message Objects

•TTCAN protocol level 1 and level 2 completely in hardware

•Event synchronised time triggered communication implemented

•Programmable loop-back mode for self-test operation

•two 16-bit module interfaces to the AMBA APB bus from ARM

•16-bit non-multiplex TI TMS470 compatible module interface

•8-bit non-multiplex Motorola HC08 compatible module interface

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2.2 Block Diagram

Clock Reset Control

Address

DataIN

User’s Manual

CAN_Core

CAN-Message

Message RAM

(single ported)

Revision 1.6TTCAN

CAN_TX

CAN_RX

Message Handler

Trigger Memory

DataOUT Wait

Interrupt

SWT, EVT

Module Interface

CPU IFC Register 2

CPU IFC Register 1

Trigger

TTCAN - Frame Synchronisation Entity

TMI

Figure 1: Block Diagram of the TTCAN

CAN_Core

CAN Protocol Controller and Rx/Tx Shift Register, handles all ISO 11898-1 protocol functions.

Message Handler

State Machine that controls the data transfer between the single ported Message RAM, the CAN_Core’s Rx/Tx Shift Register, and the CPU IFC Registers. It also handles acceptance ﬁltering and the interrupt setting as programmed in the Control and Conﬁguration Registers.

Message RAM / CPU IFC Registers

Single ported RAM, word-length = [CAN message & acceptance ﬁlter mask & control bits & status bits]. To ensure data consistency, all CPU accesses to the Message RAM are relayed through CPU IFC registers that have the same word-length as the Message RAM.

TTCAN

Frame Synchronisation Entity / Trigger Memory

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State machine that controls the ISO 11898-4 time triggered communication. It synchronises itself to the reference messages on the CAN bus, controls Cycle Time and Global Time, and handles transmissions according to the predeﬁned message schedule, the system matrix. StopWatch Trigger, EVent Trigger, and Time Mark Interrupt are synchronisation interfaces. The Trigger Memory stores the time marks of the system matrix that are linked to the messages in the Message RAM.

Module Interface

Up to now the TTCAN module is provided with three different interfaces. An 8-bit interface for the Motorola HC08 controller a 16-bit interface to the TI TMS470 controller, and two 16-bit interfaces to the AMBA APB bus from ARM. They can easily be replaced by a user-deﬁned module interface.

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2.3 Operating Modes

2.3.1 Software Initialisation

The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by a hardware reset, or by going

Bus_Off

While Init is set, all message transfer from and to the CAN bus is stopped, the status of the CAN bus output CAN_TX is

recessive

(HIGH). The counters of the EML are unchanged.

Setting Init does not change any conﬁguration register. To initialize the CAN Controller, the CPU has to set up the Bit Timing Register and each

Message Object. If a Message Object is not needed, it is sufﬁcient to set it’s MsgVal bit to not valid. Otherwise, the whole Message Object has to be initialized.

Access to the Bit Timing Register and to the BRP Extension Register for the conﬁguration of the bit timing and to the TT Operation Mode Register for the conﬁguration of the time triggered communication is enabled when both bits Init and CCE in the CAN Control Register are set.

Resetting Init (by CPU only) ﬁnishes the software initialisation. Afterwards the Bit Stream Processor BSP (see section 4.2.1 on page 45) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive

) before it can take part in bus activities and starts the message transfer.

Idle

recessive

bits (≡

Bus

The initialization of the Message Objects is independent of Init and can be done anytime, but the Message Objects should all be conﬁgured to particular identiﬁers or set to not valid before the BSP starts the message transfer.

To change the conﬁguration of a Message Object during normal operation, the CPU has to start by setting MsgVal to not valid. When the conﬁguration is completed, MsgVal is set to valid again.

To change the conﬁguration of the time triggered communication, the TTMode in the TT Operation Mode Register must be set to Conﬁguration Mode. Entering and leaving this Conﬁguration Mode requires that both bits Init and CCE are set.

2.3.2 CAN Message Transfer

Once the TTCAN is initialized and Init is reset to zero, the TTCAN’s CAN_Core synchronizes itself to the CAN bus and starts the message transfer in the conﬁgured TTMode.

Received messages are stored into their appropriate Message Objects if they pass the Message Handler’s acceptance ﬁltering. The whole message including all arbitration bits, DLC and eight data bytes is stored into the Message Object. If the Identiﬁer Mask is used, the arbitration bits which are masked to “don’t care” may be overwritten in the Message Object

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when a received message is stored. The CPU may read or write each message any time via the Interface Registers, the Message

Handler guarantees data consistency in case of concurrent accesses. Messages to be transmitted are updated by the CPU. If a permanent Message Object

(arbitration and control bits set up during conﬁguration) exists for the message, only the data bytes are updated. How the transmission is started depends on the conﬁgured TTMode.If several transmit messages are assigned to the same Message Object (when the number of Message Objects is not sufﬁcient), the whole Message Object has to be conﬁgured before the transmission of this message is requested.

The transmission of any number of Message Objects may be requested at the same time, they are transmitted subsequently according to their internal priority. Messages may be updated or

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set to not valid any time, even when their requested transmission is still pending. The old data will be discarded when a message is updated before its pending transmission has started.

Depending on the conﬁguration of the Message Object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identiﬁer.

2.3.3 Disabled Automatic Retransmission

According to the CAN Speciﬁcation (see ISO11898, 6.3.3 Recovery Management), the TTCAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission. The frame transmission service will not be conﬁrmed to the user before the transmission is successfully completed. By default, this means for automatic retransmission is enabled. It can be disabled to enable the TTCAN to work within a Time Triggered CAN (TTCAN, see ISO11898-1) environment.

The Disabled Automatic Retransmission mode is enabled by programming bit DAR in the CAN

one

Control Register to

. In this operation mode the programmer has to consider the different

behaviour of bits TxRqst and NewDat in the Control Registers of the Message Buffers:

•When a transmission starts bit TxRqst of the respective Message Buffer is reset, while bit

NewDat remains set.

•When the transmission completed successfully bit NewDat is reset.

When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission the CPU has to set TxRqst back to

Note :

It is not necessary to set DAR if the TTCAN is in time triggered operating mode.

2.3.4 Test Mode

The Test Mode is entered by setting bit Test in the CAN Control Register to the bits Tx1, Tx0, LBack, Silent, NoRAM, and WdOff in the Test Register are writable. Bit Rx monitors the state of pin CAN_RX and therefore is only readable. All Test Register functions are disabled when bit Test is reset to zero.

Loop Back Mode, No Message RAM Mode, and CAN_TX Control Mode are hardware test modes, not to be used by application programs.

Silent Mode and the Watchdog Disable Mode are software test modes.

2.3.4.1 Test Register (addresses 0x0B & 0x0A)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

StW EvT res res res res res res Rx Tx1 Tx0 LBack Silent NoRAM res WdOff

rrrrrrrrrrwrwrwrwrwrrw

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one

. In Test Mode

StW Monitors the actual value of the STOP_WATCH_TRIGGER pin EvT Monitors the actual value of the EVENT_TRIGGER pin Rx Monitors the actual value of the CAN_RX pin

one zero

The CAN bus is recessive (CAN_RX = ‘1’). The CAN bus is dominant (CAN_RX = ‘0’).

Tx1-0 Control of CAN_TX pin

00 01 10 11

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Reset value, CAN_TX is controlled by the CAN_Core. Sample Point can be monitored at CAN_TX pin.

CAN_TX pin drives a dominant (‘0’) value. CAN_TX pin drives a recessive (‘1’) value.

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LBack Loop Back Mode

one zero

Loop Back Mode is enabled. Loop Back Mode is disabled.

Silent Silent Mode

one zero

The module is in Silent Mode Normal operation.

NoRAM No Message RAM Mode

one zero

IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. No Message RAM Mode disabled, normal Message RAM usage.

WdOff Disable Watchdog

one zero

The Watchdog disabled. The Watchdog is enabled, after Initialization has ﬁnished (Init = 0).

Write access to the Test Register is enabled by setting bit Test in the CAN Control Register. The different test functions may be combined, but Tx1-0 ≠ “00” disturbs message transfer.

2.3.4.2 Disable Watchdog Mode

The TT Application Watchdog (see chapter 3.5.6) can be disabled by programming the Test Register bit WdOff to

one

and the Application_Watchdog_Limit AppWdL to 0x00. When bit Test in the CAN Control Register is reset, WdOff is also reset if the TTCAN is in time triggered operating mode; if the TTCAN is in event driven CAN mode, WdOff is remains set and the TT Application Watchdog remains disabled (emulating the C_CAN function).

The TT Application Watchdog should not be disabled in a TTCAN application program.

2.3.4.3 Silent Mode

The CAN_Core can be set in Silent Mode by programming the Test Register bit Silent to In Silent Mode, the TTCAN is able to receive valid data frames and valid remote frames, but it

sends only is required to send a internally so that the CAN_Core monitors this

recessive

in affecting it by the transmission of

recessive

bits on the CAN bus and it cannot start a transmission. If the CAN_Core

dominant

bit (ACK bit, overload ﬂag, active error ﬂag), the bit is rerouted

dominant

bit, although the CAN bus may remain

state. The Silent Mode can be used to analyse the trafﬁc on a CAN bus without

dominant

bits (Acknowledge Bits, Error Frames). Figure 2

shows the connection of signals CAN_TX and CAN_RX to the CAN_Core in Silent Mode.

CAN_TX CAN_RX

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TTCAN

•

Tx Rx

one

CAN_Core

Figure 2: CAN_Core in Silent Mode

In ISO 11898-1, the Silent Mode is called the Bus Monitoring Mode.

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2.3.4.4 Loop Back Mode

The CAN_Core can be set in Loop Back Mode by programming the Test Register bit LBack to

one

. In Loop Back Mode, the CAN_Core treats its own transmitted messages as received messages and stores them (if they pass acceptance ﬁltering) into a Receive Buffer. Figure 3 shows the connection of signals CAN_TX and CAN_RX to the CAN_Core in Loop Back Mode.

CAN_TX CAN_RX

TTCAN

•

Tx Rx

CAN_Core

Figure 3: CAN_Core in Loop Back Mode

This mode is provided for hardware self-test functions. To be independent from external stimulation, the CAN_Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back Mode. In this mode the CAN_Core performs an internal feedback from its Tx output to its Rx input. The actual value of the CAN_RX input pin is disregarded by the CAN_Core. The transmitted messages can be monitored at the CAN_TX pin.

2.3.4.5 Loop Back combined with Silent Mode

It is also possible to combine Loop Back Mode and Silent Mode by programming bits LBack

one

and Silent to

at the same time. This mode can be used for a “Hot Selftest”, meaning the TTCAN hardware can be tested without affecting a running CAN system connected to the pins CAN_TX and CAN_RX. In this mode the CAN_RX pin is disconnected from the CAN_Core and the CAN_TX pin is held

recessive

. Figure 4 shows the connection of signals CAN_TX and

CAN_RX to the CAN_Core in case of the combination of Loop Back Mode with Silent Mode.

CAN_TX CAN_RX

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TTCAN

•

Tx Rx

CAN_Core

Figure 4: CAN_Core in Loop Back combined with Silent Mode

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2.3.4.6 Software control of Pin CAN_TX

Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function – the serial data output – it can drive the CAN Sample Point signal to monitor the CAN_Core’sbit timing and it can drive constant dominant or recessive values.The last two functions, combined with the readable CAN receive pin CAN_RX, can be used to check the CAN bus’ physical layer.

The output mode of pin CAN_TX is selected by programming the Test Register bits Tx1 and Tx0 as described in section 2.3.4.1 on page 11.

The three test functions for pin CAN_TX interfere with all CAN protocol functions. CAN_TX must be left in its default function when CAN message transfer or any of the test modes Loop Back Mode, Silent Mode, or No Message RAM Mode are selected.

2.3.4.7 No Message RAM Mode

The CAN_Core can be set in No Message RAM Mode by programming the Test Register bit

one

NoRAM to

. In this mode the TTCAN module operates without the Message RAM.

The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the transmission is pending. The CPU-IFC’s output signal CAN_WAIT_B is disabled (always ‘1’) in this mode.

As soon the CAN bus is idle, the IF1 Registers are loaded into the CAN_Core’s shift register and the transmission is started. When the transmission has completed, the Busy bit is reset and the locked IF1 Registers are released.

A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request Register while the IF1 Registers are locked. If the CPU has reset the Busy bit, a possible retransmission in case of lost arbitration or in case of an error is disabled.

The IF2 Registers are used as Receive Buffer. After the reception of a message the contents of the shift register is stored into the IF2 Registers, without any acceptance ﬁltering.

Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time a read Message Object is initiated by writing the Busy bit of the IF2 Command Request Register to ‘1’, the contents of the shift register is stored into the IF2 Registers.

In No Message RAM Mode the evaluationof all Message Object related control and status bits and of the control bits of the IFx Command Mask Registers is turned off. The message number of the Command request registers is not evaluated. The NewDat and MsgLst bits of the IF2 Message Control Register retain their function, DLC3-0 will show the received DLC,

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the other control bits will be read as ‘0’. The No Message RAM Mode is a hardware test mode that allows to evaluate the TTCAN IP

RTL code in FPGA types that do not support the TTCAN’s Message RAM structure.

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3. Programmer’s Model

The TTCAN module allocates an address space of 256 bytes. The registers are organized as 16-bit registers, with the high byte at the odd address and the low byte at the even address.

The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conﬂicts between CPU accesses and message reception/transmission.

Address Name Reset Value Note

CAN Base+0x00 CAN Control Register 0x0001 CAN conﬁg register CAN Base+0x02 Status Register 0x0000 CAN status register CAN Base+0x04 Error Counter 0x0000 CAN status register CAN Base+0x06 Bit Timing Register 0x2301 CAN conﬁg reg., req. CCE CAN Base+0x08 Interrupt Register 0x0000 CAN status register CAN Base+0x0A Test Register 0x00& 0br0000000 CAN Base+0x0C BRP Extension Register 0x0000 CAN conﬁg reg., req. CCE CAN Base+0x0E Trigger Memory Access 0x0000 TTCAN conﬁg register CAN Base+0x10 IF1 Command Request 0x0001 CAN appl. IF1 Register Set CAN Base+0x12 IF1 Command Mask 0x0000 CAN Base+0x14 IF1 Mask 1 0xFFFF CAN Base+0x16 IF1 Mask 2 0xFFFF CAN Base+0x18 IF1 Arbitration 1 0x0000 CAN Base+0x1A IF1 Arbitration2 0x0000 CAN Base+0x1C IF1 Message Control 0x0000 CAN Base+0x1E IF1 Data A 1 0x0000 CAN Base+0x20 IF1 Data A 2 0x0000 CAN Base+0x22 IF1 Data B 1 0x0000 CAN Base+0x24 IF1 Data B 2 0x0000 CAN Base+0x26 — reserved — CAN Base+0x28 TT Operation Mode 0x0000 TTCAN conﬁg register CAN Base+0x2A TT Matrix Limits1 0x0000 TTCAN conﬁg register CAN Base+0x2C TT Matrix Limits2 0x0000 TTCAN conﬁg register CAN Base+0x2E TT Application Watchdog 0x0001 TTCAN conﬁg register CAN Base+0x30 TT Interrupt Enable 0x0000 TTCAN appl. register CAN Base+0x32 TT Interrupt Vector 0x0000 TTCAN status register CAN Base+0x34 TT Global Time 0x0000 TTCAN status register

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CAN Base+0x36 TT Cycle Time 0x0000 TTCAN status register CAN Base+0x38 TT Local Time 0x0000 TTCAN status register CAN Base+0x3A TT Master State 0x0000 TTCAN status register CAN Base+0x3C TT Cycle Count 0x003F TTCAN status register CAN Base+0x3E TT Error Level 0x0000 TTCAN status register CAN Base+0x40 IF2 Command Request 0x0001 CAN appl. IF2 Register Set CAN Base+0x42 IF2 Command Mask 0x0000 CAN Base+0x44 IF2 Mask 1 0xFFFF CAN Base+0x46 IF2 Mask 2 0xFFFF

r signiﬁes the actual value of the CAN_RX pin.

Reserved bits are read as ’0’ except for IFx Mask 2 Register where they are read as ’1’

CAN appl. reg., req. Test

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Address Name Reset Value Note

CAN Base+0x48 IF2 Arbitration 1 0x0000 CAN appl. IF2 Register Set CAN Base+0x4A IF2 Arbitration 2 0x0000 CAN Base+0x4C IF2 Message Control 0x0000 CAN Base+0x4E IF2 Data A 1 0x0000 CAN Base+0x50 IF2 Data A 2 0x0000 CAN Base+0x52 IF2 Data B 1 0x0000 CAN Base+0x54 IF2 Data B 2 0x0000 CAN Base+0x56 TUR-NumeratorCfg 0x0000 TTCAN conﬁg register CAN Base+0x58 TUR-DenominatorCfg 0x1000 TTCAN conﬁg register CAN Base+0x5A TUR-NumeratorActL 0x0000 TTCAN status register CAN Base+0x5C TUR-NumeratorActH 0x0001 TTCAN status register CAN Base+0x5E — reserved — CAN Base+0x60 Stop_Watch 0x0000 TTCAN status register CAN Base+0x62 — reserved — CAN Base+0x64 Global Time Preset 0x0000 TTCAN appl. register CAN Base+0x66 Clock Control 0x1000 TTCAN appl. register CAN Base+0x68 Sync_Mark 0x0000 TTCAN status register CAN Base+0x6A — reserved — CAN Base+0x6C Time Mark 0x0000 TTCAN appl. register CAN Base+0x6E Gap Control 0x0000 TTCAN appl. register CAN Base+0x70-0x7E — reserved — CAN Base+0x80 Transmission Request 1 0x0000 CAN status register CAN Base+0x82 Transmission Request 2 0x0000 CAN status register CAN Base+0x84-0x8E — reserved — CAN Base+0x90 New Data 1 0x0000 CAN status register CAN Base+0x92 New Data 2 0x0000 CAN status register CAN Base+0x94-0x9E — reserved — CAN Base+0xA0 Interrupt Pending 1 0x0000 CAN status register CAN Base+0xA2 Interrupt Pending 2 0x0000 CAN status register CAN Base+0xA4-0xAE — reserved — CAN Base+0xB0 Message Valid 1 0x0000 CAN status register CAN Base+0xB2 Message Valid 2 0x0000 CAN status register CAN Base+0xB4-0xBE — reserved —

r signiﬁes the actual value of the CAN_RX pin.

Reserved bits are read as ’0’ except for IFx Mask 2 Register where they are read as ’1’

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Revision 1.6TTCAN

Figure 5: TTCAN Register Summary

3.1 Hardware Reset Description

After hardware reset, the registers of the TTCAN hold the values described in ﬁgure 5. Additionally the

Bus_Off

state is reset and the output CAN_TX is set to

recessive

(HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation. The TTCAN does not inﬂuence the CAN bus until the CPU resets Init to ‘0’.

The data in the Message RAM is (apart from the MsgVal, NewDat, TxRqst, and IntPnd bits)

RAM

notaffectedbyahardwarereset.Afterpower-on,thecontentsofthe Message

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3.2 CAN Protocol Related Registers

These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the conﬁguration of the CAN bit timing and provide status information.

3.2.1 CAN Control Register (addresses 0x01 & 0x00)

1514131211109876543210

res res res res res res res res Test CCE DAR res EIE SIE IE Init

rrrrrrrrrwrwrwrrwrwrwrw

Test Test Mode Enable

one zero

Test Mode. Normal Operation.

CCE Conﬁguration Change Enable

one zero

The CPU has write access to the conﬁguration registers (while Init = The CPU has no write access to the conﬁguration registers.

one

DAR Disable Automatic Retransmission

one zero

Automatic Retransmission disabled. Automatic Retransmission of not successful messages enabled.

EIE Error Interrupt Enable

one

Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt.

zero

Disabled - No Error Status Interrupt will be generated.

SIE Status Change Interrupt Enable

one

Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.

zero

Disabled - No Status Change Interrupt will be generated.

IE Module Interrupt Enable

one

Enabled - Interrupts will set IRQ_B to LOW. IRQ_B remains LOW until all pending interrupts are processed.

zero

Disabled - Module Interrupt IRQ_B is always HIGH.

Init Initialization

one zero

Initialization is started. Normal Operation.

The conﬁguration registers controlled by CCE are the Bit Timing Register, the BRP Extension

manual_about.fm

Note :

The

Bus_Off

ting or resetting Init. If the device goes activities. Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of

Bus Idle

of the Bus_Off recovery sequence, the Error Management Counters will be reset.

recovery sequence (see CAN Speciﬁcation Rev. 2.0) cannot be shortened by set-

(129 * 11 consecutive

Bus_Off

recessive

, it will set Init of its own accord, stopping all bus

bits) before resuming normal operations. At the end

During the waiting time after the resetting of Init, each time a sequence of 11

recessive

bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at

dominant

or continuously disturbed and to

monitor the proceeding of the Bus_Off recovery sequence.

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3.2.2 Status Register (addresses 0x03 & 0x02)

1514131211109876543210

res res res res res res res res BOff

rrrrrrrrrrrrwrw rw

EWarn

EPass RxOk TxOk LEC

BOff Bus_Off Status

one zero

The CAN module is in Bus_Off state. The CAN module is not Bus_Off.

EWarn Warning Status

one

At least one of the error counters in the EML has reached the error warning limit of 96.

zero

Both error counters are below the error warning limit of 96.

EPass Error Passive

one zero

The CAN Core is in the The CAN Core is

error active

error passive

state as deﬁned in the CAN Speciﬁcation.

RxOk Received a Message Successfully

one

Since this bit was last reset (to zero) by the CPU, a message has been successfully received (independent of the result of acceptance ﬁltering).

zero

Since this bit was last reset by the CPU, no message has been successfully received. This bit is never reset by the CAN Core.

TxOk Transmitted a Message Successfully

one

Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.

zero

Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core.

LEC Last Error Code (Type of the last error to occur on the CAN bus)

0 No Error

Stuff Error : More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

2 3

Form Error : A ﬁxed format part of a received frame has the wrong format. AckError : The message this CAN Core transmitted was not acknowledged by

another node.

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Bit1Error : During the transmission of a message (with the exception of the arbitration ﬁeld), the device wanted to send a ‘1’), but the monitored bus value was

dominant

recessive

Bit0Error : During the transmission of a message (or acknowledge bit, or active error ﬂag, or overload ﬂag), the device wanted to send a (data or identiﬁer bit logical value ‘0’), but the monitored bus value was

. During

sive recessive

Bus_Off

recovery this status is set each time a sequence of 11

bits has been monitored. This enables the CPU to monitor the pro-

ceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at

dominant

CRCError : The CRC check sum was incorrect in the message received, the

or continuously disturbed).

CRC received for an incoming message does not match with the calculated CRC for the received data.

7 unused : When the LEC shows the value ‘7’, no CAN bus event was detected

since the CPU wrote this value to the LEC.

level(bit of logical value

dominant

level

reces-

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The LEC ﬁeld holds a code which indicates the type of the last error to occur on the CAN bus. This ﬁeld will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error. The unused code ‘7’ may be written by the CPU to check for updates.

3.2.2.1 Status Interrupts A Status Interrupt is generated by bits BOff and EWarn (Error Interrupt, EIE)orbyRxOk,

TxOk, and LEC (Status Change Interrupt, SIE) assumed that the corresponding enable bits in the CAN Control Register are set. A change of bit EPass or a CPU write to RxOk, TxOk,or LEC will never generate a Status Interrupt.

When SIE is set, a Status Interrupt will be generated at each CAN bus error and at each valid CAN message, independent of the Message RAM conﬁguration.

Reading the Status Register will clear the Status Interrupt value (8000h) in the Interrupt Register, if it is pending.

3.2.3 Error Counter (addresses 0x05 & 0x04)

1514131211109876543210

RP REC6-0 TEC7-0

rr r

RP Receive Error Passive

one

The Receive Error Counter has reached the

error passive

level as deﬁned

in the CAN Speciﬁcation.

zero

The Receive Error Counter is below the

error passive

level.

REC6-0 Receive Error Counter

Actual state of the Receive Error Counter. Values between 0 and 127.

TEC7-0 Transmit Error Counter

Actual state of the Transmit Error Counter. Values between 0 and 255.

3.2.4 Bit Timing Register (addresses 0x07 & 0x06)

1514131211109876543210

res TSeg2 TSeg1 SJW BRP

rrw rw rw rw

TSeg1 The time segment before the sample point

0x01-0x0F

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valid values for TSeg1 are [1 … 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

TSeg2 The time segment after the sample point

0x0-0x7

valid values for TSeg2 are [0 … 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

SJW (Re)Synchronisation Jump Width

0x0-0x3

Valid programmed values are 0-3. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

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BRP Baud Rate Prescaler

0x00-0x3F

The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0 … 63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

This register is only writable if bits CCE and Init in the CAN Control Register are set. The CAN bit time may be programed in the range of [4 … 25] time quanta. The CAN time quantum may be programmed in the range of [1 … 1024] CAN_CLK periods. For details see chapter 4.2.1.

Note :

With a module clock CAN_CLK of 8 MHz and BRPE = 0x00, the reset value of 0x2301 conﬁgures the TTCAN for a bit rate of 500 kBit/s.

3.2.5 BRP Extension Register (addresses 0x0D & 0x0C)

1514131211109876543210

res res res res res res res res res res res res BRPE

rrrrrrrrrrrr rw

BRPE Baud Rate Prescaler Extension

0x00-0x0F By programming BRPE the Baud Rate Prescaler can be

extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BRP (LSBs) is used.

This register is only writable if bits CCE and Init in the CAN Control Register are set.

Note :

The width of BRPE may be increased to more than its default width of 4 bits in particular implementations of the TTCAN IP module width a high module clock frequency.

3.3 Message Interface Register Sets

Address IF1 Register Set Address IF2 Register Set

CAN Base+0x10 IF1 Command Request CAN Base+0x40 IF2 Command Request CAN Base+0x12 IF1 Command Mask CAN Base+0x42 IF2 Command Mask CAN Base+0x14 IF1 Mask 1 CAN Base+0x44 IF2 Mask 1 CAN Base+0x16 IF1 Mask 2 CAN Base+0x46 IF2 Mask 2 CAN Base+0x18 IF1 Arbitration 1 CAN Base+0x48 IF2 Arbitration 1 CAN Base+0x1A IF1 Arbitration 2 CAN Base+0x4A IF2 Arbitration 2 CAN Base+0x1C IF1 Message Control CAN Base+0x4C IF2 Message Control

manual_about.fm

CAN Base+0x1E IF1 Data A 1 CAN Base+0x4E IF2 Data A 1 CAN Base+0x20 IF1 Data A 2 CAN Base+0x50 IF2 Data A 2 CAN Base+0x22 IF1 Data B 1 CAN Base+0x52 IF2 Data B 1 CAN Base+0x24 IF1 Data B 2 CAN Base+0x54 IF2 Data B 2

Figure 6: IF1 and IF2 Message Interface Register Sets

There are two sets of Interface Registers that control the CPU access to the Message RAM. The Interface Registers avoid (by buffering the data to be transferred) conﬂicts between CPU access to the Message RAM and CAN message reception and transmission. A complete Message Object (see chapter 3.3.4) or parts of the Message Object may be transferred between the Message RAM and the IFx Message Buffer registers (see chapter 3.3.3) in one

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single transfer. This transfer,performed in parallel on all selected parts of the Message Object, guarantees the data consistency of the CAN message. Figure 6 shows the structure of the two Interface Register sets.

The function of the two Interface Register sets is identical (except for test mode NoRAM). The second interface register set is provided to serve application programming. Two groups of software drivers may deﬁned, each group is restricted to the use of one of the Interface Register sets. The software drivers of one group may interrupt software drivers of the other group, but not of the same group.

In a simple example, there is one Read_Message task that uses IFC1 to get received messages from the Message RAM and there is one Write_Message task that uses IFC2 to write messages to be transmitted into the Message RAM. Both tasks may interrupt each other.

Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers. The Command Mask Register speciﬁes the direction of the data transfer and which parts of a Message Object will be transferred. The Command Request Register is used to select a Message Object in the Message RAM as target or source for the transfer and to start the action speciﬁed in the Command Mask Register.

3.3.1 IFx Command Mask Registers

The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx Message Buffer Registers are source or target of the data transfer.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IF1 CommandMask Register

(addresses 0x13 & 0x12)

IF2 CommandMask Register

(addresses 0x43 & 0x42)

res WR/RD Mask Arb Control

r r r r r r r r rw rw rw rw rw rw rw rw

ClrIntPnd

TxRqst/ NewDat

Data A Data B

WR/RD Write / Read

one

Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.

zero

Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.

The other bits of IFx Command Mask Register have different functions depending on the transfer direction :

3.3.1.1 Direction = Write Mask Access Mask Bits

manual_about.fm

one zero

transfer Identiﬁer Mask + MDir + MXtd to Message Object. Mask bits unchanged.

Arb Access Arbitration Bits

one zero

transfer Identiﬁer + Dir + Xtd + MsgVal to Message Object. Arbitration bits unchanged.

Control Access Control Bits

Note :

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one zero

MSC2-0 is read-only in time triggered operating mode.

transfer Control Bits to Message Object. Control Bits unchanged.

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ClrIntPnd Clear Interrupt Pending Bit

Note :

When writing to a Message Object, this bit is ignored.

TxRqst/NewDatAccess Transmission Request Bit

Note :

one zero

If a transmission is requested by setting TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored.

set TxRqst bit TxRqst bit unchanged

Data A Access Data Bytes 0-3

one zero

transfer Data Bytes 0-3 to Message Object. Data Bytes 0-3 unchanged.

Data B Access Data Bytes 4-7

one zero

transfer Data Bytes 4-7 to Message Object. Data Bytes 4-7 unchanged.

3.3.1.2 Direction = Read Mask Access Mask Bits

one zero

transfer Identiﬁer Mask + MDir + MXtd to IFx Message Buffer Register. Mask bits unchanged.

Revision 1.6TTCAN

Arb Access Arbitration Bits

one zero

transfer Identiﬁer + Dir + Xtd + MsgVal to IFx Message Buffer Register. Arbitration bits unchanged.

Control Access Control Bits

one zero

transfer Control Bits to IFx Message Buffer Register. Control Bits unchanged.

ClrIntPnd Clear Interrupt Pending Bit

one zero

clear IntPnd bit in the Message Object.

IntPnd bit remains unchanged.

TxRqst/NewDatAccess New Data Bit

Note :

one zero

A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFx Message Control Register always reﬂect the status before resetting them.

clear NewDat bit in the Message Object.

NewDat bit remains unchanged.

Data A Access Data Bytes 0-3

manual_about.fm

one zero

transfer Data Bytes 0-3 to IFx Message Buffer Register. Data Bytes 0-3 unchanged.

Data B Access Data Bytes 4-7

Note :

one zero

The speed of the message transfer does not depend on how many bytes are transferred.

transfer Data Bytes 4-7 to IFx Message Buffer Register. Data Bytes 4-7 unchanged.

3.3.2 IFx Command Request Registers

A message transfer is started as soon as the CPU has written the message number to low byte of the Command Request Register. With this write operation, the Busy bit is automatically set to ‘1’ to notify the CPU that a transfer is in progress. After a wait time of 3 to

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6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed and the Busy bit is cleared to ‘0’. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance ﬁltering, or message storage. If the CPU-IFC is implemented with the wait-function, the CPU is halted while the Busy bit is set. If the CPU writes to both Command Request Registers consecutively (requests a second transfer while another transfer is already in progress), the second transfer starts when the ﬁrst one is completed.

IF1 Command Request Register

(addresses 0x11 & 0x10)

IF2 Command Request Register

(addresses 0x41 & 0x40)

1514131211109876543210

Busy res res Message Number Busy res res Message Number

rr rrw

Busy Busy Flag

one zero

set to one when writing to the IFx Command Request Register reset to zero when read/write action has ﬁnished.

Message Number

0x01-0x20

Valid Message Number, the Message Object in the Message RAM is selected for data transfer.

Note :

0x00 0x21-0x3F

When an invalid Message Number is written to the Command Request Register, the Message Number will be transformed into a valid value and that Message Object will be transferred.

Not a valid Message Number, interpreted as Not a valid Message Number, interpreted as

0x20

0x01-0x1F

3.3.3 IFx Message Buffer Registers

The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. The function of the Message Objects bits is described in chapter 3.3.4.

3.3.3.1 IFx Mask Registers

IF1 Mask 1 Register

(addresses 0x15 & 0x14)

IF1 Mask 2 Register

(addresses 0x17 & 0x16)

IF2 Mask 1 Register

(addresses 0x45 & 0x44)

IF2 Mask 2 Register

(addresses 0x47 & 0x46)

manual_about.fm

3.3.3.2 IFx Arbitration Registers

IF1 Arbitration 1 Register

(addresses 0x19 & 0x18)

IF1 Arbitration 2 Register

(addresses 0x1B& 0x1A)

IF2 Arbitration 1 Register

(addresses 0x49 & 0x48)

IF2 Arbitration 2 Register (addresses 0x4B & 0x4A)

15 14 131211109876543210

Msk15-0

MXtd MDir res Msk28-16

Msk15-0

MXtd MDir res Msk28-16

rw rw r rw

15 14 131211109876543210

ID15-0

MsgVal Xtd Dir ID28-16

ID15-0

MsgVal Xtd Dir ID28-16

rw rw rw rw

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3.3.3.3 IFx Message Control Registers

Revision 1.6TTCAN

IF1MessageControl Register

(addresses 0x1D & 0x1C)

IF2MessageControl Register

(addresses 0x4D & 0x4C)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0 NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0

rw rw rw rw rw rw rw rw rw rw rw

3.3.3.4 IFx Data A and Data B Registers

The data bytes of CAN messages are stored in the IFx registers in the following order:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IF1 Message Data A1 (addresses 0x1F & 0x1E) Data(1) Data(0)

IF1 Message Data A2 (addresses 0x21 & 0x20) Data(3) Data(2) IF1 Message Data B1 (addresses 0x23 & 0x22) Data(5) Data(4) IF1 Message Data B2 (addresses 0x25 & 0x24) Data(7) Data(6)

IF2 Message Data A1 (addresses 0x4F & 0x4E) Data(1) Data(0)

IF2 Message Data A2 (addresses 0x51 & 0x50) Data(3) Data(2) IF2 Message Data B1 (addresses 0x53 & 0x52) Data(5) Data(4) IF2 Message Data B2 (addresses 0x55 & 0x54) Data(7) Data(6)

rw rw

In a CAN Data Frame, Data(0) is the ﬁrst, Data(7) is the last byte to be transmitted or received. In CAN’s serial bit stream, the MSB of each byte will be transmitted ﬁrst.

3.3.4 Message Object in the Message Memory

There are 32 Message Objects in the Message RAM. To avoid conﬂicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.

Figure 7 gives an overview of the two structure of a Message Object.

Message Object UMask Msk28-0 MXtd MDir EoB MSC2-0 NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst MsgVal ID28-0 Xtd Dir DLC3-0 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7

Figure 7: Structure of a Message Object in the Message Memory

MsgVal Message Valid

manual_about.fm

Note :

one zero

The CPU must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register. This bit must also be reset before the identiﬁer Id28-0, the control bits Xtd, Dir, or the Data Length Code DLC3-0 are modiﬁed, or if the Messages Object is no longer required.

The Message Object is conﬁgured and should be considered by the Message Handler.

The Message Object is ignored by the Message Handler.

UMask Use Acceptance Mask

Note :

one zero

If the UMask bit is set to initialization of the Message Object before MsgVal is set to

Use Mask (Msk28-0, MXtd, and MDir) for acceptance ﬁltering Mask ignored.

one

, the Message Object’s mask bits have to be programmed during

one

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