ATMEL ATmega325, ATmega325V, ATmega3250, ATmega3250V, ATmega645 User Manual

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BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powe rful Instructions – Most Single Clock Cy cle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– In-System Self-programmable Flash Program Memory

• 32K Bytes (ATmega325/ATmega3250)

• 64K Bytes (ATmega645/ATmega6450)

– EEPROM

• 1K bytes (ATmega325/ATmega3250)

• 2K bytes (ATmega645/ATmega6450)

– Internal SRAM

• 2K bytes (ATmega325/ATmega3250)

• 4K bytes (ATmega645/ATmega6450) – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation – Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator –Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Pac kages

– 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:

• 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega325/3250/645/6450:

• 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 350 µA 32 kHz, 1.8V: 20 µA (including Oscillator)

– Power-down Mode:

100 nA at 1.8V

8-Bit Microcontroller

(1)

8-bit

Microcontroller with In-System Programmable Flash

ATmega325/V ATmega3250/V ATmega645/V ATmega6450/V

Preliminary Summary

ATmega325/3250/645/6450

1. Pin Configurations

Figure 1-1. Pinout ATmega3250/6450

(RXD/PCINT0) PE0

DNC

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24) PJ0

(PCINT25) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

AVCC

AGND

AREF

PF0 (ADC0)

PF1(ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23)

PH6 (PCINT22)

PH5 (PCINT21)

PH4 (PCINT20)

DNC

GND

9998979695949392919089888786858483828180797877

100

26272829303132333435363738394041424344454647484950

INDEX CORNER

ATmega3250/6450

VCC

DNC

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PG2

PC7

PC6

DNC

PH3 (PCINT19)

PH2 (PCINT18)

PH1 (PCINT17)

PH0 (PCINT16)

DNC

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

DNC

(T1) PG3

(T0) PG4

RESET/PG5

(OC2A/PCINT15) PB7

VCC

GND

XTAL2 (TOSC2)

XTAL1 (TOSC1)

DNC

(PCINT26) PJ2

(PCINT27) PJ3

(PCINT28) PJ4

(PCINT29) PJ5

DNC

(ICP1) PD0

(PCINT30) PJ6

PD2

(INT0) PD1

PD3

PD4

PD5

PD6

PD7

2570LS–AVR–08/07

Figure 1-2. Pinout ATmega325/645

GND

AVCC

DNC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

(OC2A/PCINT15) PB7

INDEX CORNER

(T1) PG3

PF0 (ADC0)

AREF

(T0) PG4

RESET/PG5

ATmega325/3250/645/6450

VCC

GND

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

6018592058

ATmega325/645

VCC

GND

XTAL2 (TOSC2)

PF4 (ADC4/TCK)

57225623552454255326522751

XTAL1 (TOSC1)

PF7 (ADC7/TDI)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PD2

PD1 (INT0)

(ICP1) PD0

PD3

PD4

PA0

PD5

PA1

PD6

PA2

PD7

PA3

PA4

PA5

PA6

PA7

PG2

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

2. Disclaimer

3. Overview

2570LS–AVR–08/07

Note: The large center pad underneath the QFN/MLF packages is made of metal and inter nally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es will be available after the device is characterized.

The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325/3250/645/6450 achieves through puts approaching 1 MIPS per MHz a llowing the system designer to optimize power consumption versus processing speed.

ATmega325/3250/645/6450

3.1 Block Diagram

Figure 3-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

AVR CPU

PORTF DRIVERS

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

ALU

STATUS

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

XTAL1

XTAL2

RESET

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

COMPARATOR

DATA REGISTER

USART

PORTE

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

DATA REGISTER

PORTB

PORTB DRIVERS

DATA DIR.

REG. PORTB

PB0 - PB7PE0 - PE7

SPI

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

2570LS–AVR–08/07

ATmega325/3250/645/6450

The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging sup port an d pro gramming, three flexib le Timer /Co unters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer will continue to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchron ous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sle eping. This allows very fast start-up combined with lowpower consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Bo ot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solut ion to many embed ded control applications.

The ATmega325/3250/645/6450 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

3.2 Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450

The ATmega325, ATmega3250, ATmega645, and ATmega6450 differs only in memory sizes, pin count and pinout. Table 3-1 on page 5 summarizes the different configurations for the four devices.

Table 3-1. Configuration Summary

General Purpose

Device Flash EEPROM RAM

ATmega325 32K bytes 1K bytes 2K bytes 54 ATmega3250 32K bytes 1K bytes 2K bytes 69 ATmega645 64K bytes 2K bytes 4K bytes 54 ATmega6450 64K bytes 2K bytes 4K bytes 69

I/O Pins

3.3 Pin Descriptions

The following section describes the I/O-pin special funct ion s.

2570LS–AVR–08/07

ATmega325/3250/645/6450

3.3.1 V

3.3.2 GND

3.3.3 Port A (PA7..PA0)

3.3.4 Port B (PB7..PB0)

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports. Port B also serves the function s of various special features of the ATmega325/3250/645/6450

as listed on page 67.

3.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

3.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 70.

3.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port E also serves the function s of various special features of the ATmega325/3250/645/6450 as listed on page 71.

2570LS–AVR–08/07

3.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

3.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various specia l features of the ATmega3 25/3250/645/6450 as listed on page 71.

ATmega325/3250/645/6450

3.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250/6450 as listed on page 71.

3.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up re sistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250/64 50 as listed on

page 71.

3.3.12 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page

300. Shorter pulses are not guaranteed to gener at e a re se t.

3.3.13 XTAL1

2570LS–AVR–08/07

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

ATmega325/3250/645/6450

3.3.14 XTAL2

3.3.15 AVCC

3.3.16 AREF

4. Resources

5. Data Retention

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V through a low-pass filter.

This is the analog reference pin for the A/D Converter.

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

Note: 1.

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

, even if the ADC is not used. If the ADC is used, it should be connected to V

2570LS–AVR–08/07

ATmega325/3250/645/6450

6. Register Summary

Note: Registers with bold type only available in ATmega3250/6450.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4)

Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - -

PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 83

DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 83

PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 83

PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 83

DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 83

PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 83

Reserved Reserved Reserved Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved

UDR0 USART0 Data Register 178

UBRR0H

UBRR0L USART0 Baud Rate Register Low 183

- - - - - - - -

USART0 Baud Rate Register High 183

2570LS–AVR–08/07

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