Atmel ATmega16U4, ATmega32U4 Datasheet

ATmega16U4/ATmega32U4

8-bit Microcontroller with 16/32K bytes of ISP Flash and

USB Controller

DATASHEET SUMMARY

Features

• High Performance, Low Power AVR

8-Bit Microcontroller

• Advanced RISC Architecture

– 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Worki ng Re gisters – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16/32KB of In-System Self-Programmable Flash – 1.25/2.5KB Internal SRAM – 512Bytes/1KB Internal EEPROM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85C/ 100 years at 25C – Optional Boot Code Section with Independent Lo ck Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation Parts using external XTAL clock are pre -programed with a default USB bootloader

– Programming Lock for Software Security

• JTAG (IEEE

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

std. 1149.1 compliant) Interface

(1)

• USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification Rev 2.0 – Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s – Endpoint 0 for Control Transfers: up to 64-bytes – Six Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers – Configurable Endpoints size up to 256 bytes in double bank mode – Fully independent 832 bytes USB DPRAM for endpoint memory allocation – Suspend/Resume Interrupts – CPU Reset possible on USB Bus Reset detection – 48MHz from PLL for Full-speed Bus Operation – USB Bus Connection/Disconnection on Microcontroller Request – Crystal-less operation for Low Speed mode

• Peripheral Features

– On-chip PLL for USB and High Speed Timer: 32 up to 96MHz operation – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

– Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – One 10-bit High-Speed Timer/Counter with PLL (64MHz) and Compare Mode – Four 8-bit PWM Channels – Four PWM Channels with Programmable Resolution from 2 to 16 Bits – Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits – Output Compare Modulator – 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain) – Programmable Serial USART with Hardware Flow Control – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wa ke -u p on Pin Change – On-chip Temperature Sensor

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal 8MHz Calibrated Oscillator – Internal clock prescaler and On-the-fly Clock Switching (Int RC / Ext Osc) – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– All I/O combine CMOS outputs and LVTTL inputs – 26 Programmable I/O Lines – 44-lead TQFP Package, 10x10mm – 44-lead QFN Package, 7x7mm

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8MHz at 2.7V - Industrial range – 16MHz at 4.5V - Industrial range

Note: 1. See “Data Retention” on page 8 for details.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

1. Pin Configurations

(

)

Figure 1-1. Pinout

AVCC

D-

D+

1 2 3 4 5 6 7 8 9

(INT.6/AIN0) PE6

UVcc

UGnd UC ap

VBus

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

GND

VCC

PE2 (HWB)

PC7 (ICP3/CLK0/OC4A)

PC6 (OC3A/OC4A)

PB6 (PCINT6/OC1B/OC4B/AD

PB5 (PCINT5/OC1A/OC4B/AD

PB4 (PCINT4/ADC11)

PD7 (T0/OC4D/ADC10)

P F 4 (AD C 4/TCK

P F 5 (AD C 5/TMS)P F 6 (AD C 6/TDO)P F 7 (AD C 7/TD 38

GND

ARE F

P F 0 (AD C 0)

P F 1 (AD C 1)

INDEX CORNER

AT mega 32U4 AT mega 16U4

44-pin QFN/TQFP

PD6 (T1/OC4D/ADC9)

PD4 (ICP1/ADC8)

AVCC

(X C K1/CT S) P D5

24 23

GND

(PDI/PCINT2/MOSI) PB2

PDO/PCINT3/MISO) PB3

10 11

PCI NT7/OC0 A/OC1C/RT S) PB7

RESET

VCC

GND

XT AL2

XT AL1

(OC 0B /S C L/INT0) P D0

(S D A/INT1) P D 1

(R X D1/INT 2) P D2

(T X D 1 /INT3) PD3

2. Overview

The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

ATmega16U4/32U4 [DATASHEET ]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

2.1 Block Diagram

PROGRAM COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMERS/

COUNTERS

INSTRUCTION

DECODER

DATADIR.

REG. PORTB

DATADIR.

REG. PORTE

DATADIR.

REG. PORTD

DATAREGISTER

PORTB

DATAREGISTER

PORTE

DATAREGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPI

STATUS

SRAM

USART1

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0

PE6

PF7 - PF4

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

PC7

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB 2.0

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATADIR.

REG. PORTC

DATAREGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATADIR.

REG. PORTF

DATAREGISTER

PORTF

POR - BOD

RESET

PD7 - PD0

TWO-WIRE SERIAL

INTERFACE

PLL

HIGH SPEED

TIMER/PWM

PE2

PC6PF1

PF0

ON-CHIP

USB PAD 3V

REGULATOR

UVcc

UCap

1uF

ANALOG

COMPARATOR

VBUS

ADC

AGND

AREF

AVCC

TEMPERATURE

SENSOR

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The device provides the following features: 16/32K bytes of In-System Programmable Flash with Read-WhileWrite capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six softwa re selectable

ATmega16U4/32U4 [DATASHEET]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using the Atmel Flash allows the program memory to be reprogrammed in-system thr ough an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the applica tion Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the device is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

high-density nonvolatile memory technology. The On-chip ISP

2.2.2 GND

Ground.

2.2.3 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the cloc k is not ru nn in g.

Port B has better driving capabilities than the other ports. Port B also serves the functions of various special feat ur es of the device as listed on page 74.

2.2.4 Port C (PC7,PC6)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the cloc k is not ru nn in g.

Only bits 6 and 7 are present on the product pinout. Port C also serves the functions of special features of the device as listed on page 77.

2.2.5 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the cloc k is not ru nn in g.

ATmega16U4/32U4 [DATASHEET ]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 78.

2.2.6 Port E (PE6,PE2)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the cloc k is not ru nn in g.

Only bits 2 and 6 are present on the product pinout. Port E also serves the functions of various special feat ur es of the ATmega16U4/ATmega32U4 as listed on

page 81.

2.2.7 Port F (PF7..PF4, PF1,PF0)

Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels ar e not used. Port pins can

provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Bits 2 and 3 are not present on the product pinout . Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-up resistors on

pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

2.2.8 D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22 resistor.

2.2.9 D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 resistor.

2.2.10 UGND

USB Pads Ground.

2.2.11 UVCC

USB Pads Internal Regulator Input supply voltage.

2.2.12 UCAP

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

2.2.13 VBUS

USB VBUS monitor input.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

2.2.14 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Sho rter pulses are not guaranteed to generate a reset.

2.2.15 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.16 XTAL2

Output from the inverting Oscillator amplifier.

2.2.17 AVCC

AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to V

2.2.18 AREF

This is the analog reference pin (input) for the A/D Converter.

. If the ADC is used, it should be connected to VCC through a low-pass filter.

ATmega16U4/32U4 [DATASHEET ]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

3. About

3.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the device is characterized.

3.2 Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

3.3 Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit defini ti ons in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

3.4 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1PPM over 20 years at 85°C or 100 years at 25°C.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - - (0xFE) Reserved - - - - - - - (0xFD) Reserved - - - - - - - (0xFC) Reserved - - - - - - - (0xFB) Reserved - - - - - - - (0xFA) Reserved - - - - - - - (0xF9) Reserved - - - (0xF8) Reserved - - - - - - - (0xF7) Reserved - - - - - - - (0xF6) Reserved - - - - - - - (0xF5) Reserved - - - - - - - (0xF4) UEINT - EPINT6:0 (0xF3) UEBCHX - - - - -BYCT10:8 (0xF2) UEBCLX BYCT7:0 (0xF1) UEDATX DAT7:0 (0xF0) UEIENX FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE (0xEF) UESTA1X - - - - - CTRLDIR CURRBK1:0 (0xEE) UESTA0X CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK1:0 (0xED) UECFG1X EPSIZE2:0 EPBK1:0 ALLOC (0xEC) UECFG0X EPTYPE1:0 - - - - - EPDIR (0xEB) UECONX - - STALLRQ STALLRQC RSTDT - - EPEN (0xEA) UERST - EPRST6:0 (0xE9) UENUM - - - - - EPNUM2:0 (0xE8) UEINTX FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI (0xE7) Reserved - - - (0xE6) UDMFN - - - FNCERR - - - (0xE5) UDFNUMH - - - - - FNUM10:8 (0xE4) UDFNUML FNUM7:0 (0xE3) UDADDR ADDEN UADD6:0 (0xE2) UDIEN - UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE (0xE1) UDINT - UPRSMI EORSMI WAKEUPI EORSTI SOFI MSOFI SUSPI (0xE0) UDCON - - - - RSTCPU LSM RMWKUP DETACH (0xDF) Reserved (0xDE) Reserved (0xDD) Reserved (0xDC) Reserved (0xDB) Reserved (0xDA) USBINT - - - - - - - VBUSTI (0xD9) USBSTA - - - - - -IDVBUS (0xD8) USBCON USBE - FRZCLK OTGPADE - - -VBUSTE (0xD7) UHWCON - - - - - - - UVREGE (0xD6) Reserved (0xD5) Reserved (0xD4) DT4 DT4H3 DT4H2 DT4H1 DT4H0 DT4L3 DT4L2 DT4L1 DT4L0 (0xD3) Reserved (0xD2) OCR4D Timer/Counter4 - Output Compare Register D (0xD1) OCR4C Timer/Counter4 - Output Compare Register C (0xD0) OCR4B Timer/Counter4 - Output Compare Register B (0xCF) OCR4A Timer/Counter4 - Output Compare Register A (0xCE) UDR1 USART1 I/O Data Register (0xCD) UBRR1H - - - - USART1 Baud Rate Register High Byte (0xCC) UBRR1L USART1 Baud Rate Register Low Byte (0xCB) UCSR1D - - - - - - CTSEN RTSEN (0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 (0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 (0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 PE1 U2X1 MPCM1 (0xC7) CLKSTA - - - - - - RCON EXTON (0xC6) CLKSEL1 RCCKSEL3 RCCKSEL2 RCCKSEL1 RCCKSEL0 EXCKSEL3 EXCKSEL2 EXCKSEL1 EXCKSEL0 (0xC5) CLKSEL0 RCSUT1 RCSUT0 EXSUT1 EXSUT0 RCE EXTE -CLKS (0xC4) TCCR4E TLOCK4 ENHC4 OC4OE5 OC4OE4 OC4OE3 OC4OE2 OC4OE1 OC4OE0 (0xC3) TCCR4D FPIE4 FPEN4 FPNC4 FPES4 FPAC4 FPF4 WGM41 WGM40 (0xC2) TCCR4C COM4A1S COM4A0S COM4B1S COM4B0S COM4D1S COM4D0S FOC4D PWM4D (0xC1) TCCR4B PWM4X PSR4 DTPS41 DTPS40 CS43 CS42 CS41 CS40 (0xC0) TCCR4A COM4A1 COM4A0 COM4B1 COM4B0 FOC4A FOC4B PWM4A PWM4B (0xBF) TC4H - - - - - Timer/Counter4 High Byte

ATmega16U4/32U4 [DATASHEET SUMMARY]

Atmel-7766JS-USB-ATmega16U4/32U4-Datasheet_04/2016

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