Atmel ATmega8U2, ATmega16U2, ATmega32U2 Datasheet

Features

High Performance, Low Power AVR
Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
– 8K/16K/32K Bytes of In-System Self-Programmable Flash – 512/512/1024 EEPROM – 512/512/1024 Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by on-chip Boot Program hardware-activated after reset True Read-While-Write Operation
– Programming Lock for Software Security
USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification REV 2.0 – 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s – Fully independant 176 bytes USB DPRAM for endpoint memory allocation – Endpoint 0 for Control Transfers: from 8 up to 64-bytes – 4 Programmable Endpoints:
IN or Out Directions Bulk, Interrupt and IsochronousTransfers Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer – Suspend/Resume Interrupts – Microcontroller reset on USB Bus Reset without detach – USB Bus Disconnection on Microcontroller Request
Peripheral Features
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
PWM channels)
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
(three 8-bit PWM channels) – USART with SPI master only mode and hardware flow control (RTS/CTS) – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change
On Chip Debug Interface (debugWIRE)
Special Microcontroller Features
– Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
– 22 Programmable I/O Lines – QFN32 (5x5mm) / TQFP32 packages
Operating Voltages
– 2.7 - 5.5V
Operating temperature
– Industrial (-40°C to +85°C)
Maximum Frequency
– 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range
Note: 1. See “Data Retention” on page 6 for details.
®
8-Bit Microcontroller
(1)
8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller
ATmega8U2 ATmega16U2 ATmega32U2
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1. Pin Configurations

UVCC
QFN32
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
VCC
XTAL1
(INT5/ AIN3) PD4
(TXD1 / INT3) PD3
(XCK / AIN4 / PCINT12) PD5
PB3 (PDO / MISO / PCINT3)
GND
(PC0) XTAL2
UGND
PB4 (T1 / PCINT4)
282726 1 2 3 4 5
6 7
24 23 22 21 20 19 18
1211109131415
(AIN0 / INT1) PD1
8
16
17
PB6 (PCINT6)
D-
D+
2529303132
PB7 (PCINT7 / OC.0A / OC.1C)
PB5 (PCINT5)
PC7 (INT4 / ICP1 / CLKO)
PC6 (OC.1A / PCINT8)
Reset
(PC1 / dW)
PC5 ( PCINT9/ OC.1B)
PC4 (PCINT10)
UCAP
(RXD1 / AIN1 / INT2) PD2
(RTS / AIN5 / INT6) PD6
(CTS
/ HWB / AIN6 / T0 / INT7) PD7
(SS
/ PCINT0) PB0
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
AVCC
UVCC
VQFP32
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
VCC
XTAL1
(INT5/ AIN3) PD4
(TXD1 / INT3) PD3
(XCK AIN4 / PCINT12) PD5
PB3 (PDO / MISO / PCINT3)
GND
(PC0) XTAL2
UGND
PB4 (T1 / PCINT4)
282726 1 2 3 4 5
6 7
24 23 22 21 20 19 18
1211109131415
(AIN0 / INT1) PD1
8
16
17
PB6 (PCINT6)
D-
D+
2529303132
PB7 (PCINT7 / OC.0A / OC.1C)
PB5 (PCINT5)
PC7 (INT4 / ICP1 / CLKO)
PC6 (OC.1A / PCINT8)
Reset
(PC1 / dW)
PC5 ( PCINT9/ OC.1B)
PC4 (PCINT10)
UCAP
(RXD1 / AIN1 / INT2) PD2
(RTS / AIN5 / INT6) PD6
/ HWB
/ AIN6 / T0 / INT7) PD7
(SS
/ PCINT0) PB0
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
AVCC
Figure 1-1. Pinout
ATmega8U2/16U2/32U2

1.1 Disclaimer

Note: The large center pad underneath the QFN package should be soldered to ground on the board to
ensure good mechanical stability.
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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2
ATmega8U2/16U2/32U2
PROGRAM COUNTER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTC
DATA REGISTER
PORTC
INTERRUPT
UNIT
EEPROM
USART1
STATUS
REGISTER
Z
Y
X
ALU
PORTC DRIVERS
PORTD DRIVERS
PORTB DRIVERS
PC7 - PC0 PD7 - PD0
RESET
VCC
GND
XTAL1
XTAL2
CONTROL
LINES
ANALOG
COMPARATOR
PB7 - PB0
D+/SCK D-/SDATA
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
8-BIT DA TA BUS
USB
PS/2
TIMING AND
CONTROL
OSCILLATOR
CALIB. OSC
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
ON-CHIP DEBUG
Debug-Wire
PROGRAMMING
LOGIC
DATA DIR.
REG. PORTD
DATA REGISTER
PORTD
POR - BOD
RESET
PLL
+
-
SPI
ON-CHIP
3.3V
REGULATOR
UVcc
UCap
1uF

2. Overview

The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
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ATmega8U2/16U2/32U2
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.
The ATmega8U2/16U2/32U2 provides the following features: 8K/16K/32K Bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/512/1024 Bytes EEPROM, 512/512/1024 SRAM, 22 general purpose I/O lines , 32 general purpose work ing registers, two flexible Timer/Counters with compare modes and PWM, one USART, a prog rammable Watch­dog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system and programmi n g and five software selectable power sav­ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, the main Oscillator continues to run.
The device is manufactured using Atmel’s high -dens ity no nvola tile memo ry tec hnol ogy. The on­chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8U2/16U2/32U2 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega8U2/16U2/32U2 are supported with a full suite of program and system develop­ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 AVCC

AVCC is the supply voltage pin (input) for all analog features (Analog Comparator, PLL). It should be externally connected to VCC through a low-pass filter.

2.2.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.
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Port B also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on
page 74.
4

2.2.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on page 77.

2.2.6 Port D (PD7..PD0)

Port D serves as analog inputs to the analog comparator. Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-
cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.2.7 D-

USB Full Speed Negative Data Upstream Port
ATmega8U2/16U2/32U2

2.2.8 D+

2.2.9 UGND

2.2.10 UVCC

2.2.11 UCAP

2.2.12 RESET/PC1/dW

2.2.13 XTAL1

USB Full Speed Positive Data Upstream Port
USB Ground.
USB Pads Internal Regulator Input supply voltage.
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac­itor (1µF).
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System Control and
Reset” on page 47. Shorter pulses are not guaranteed to generate a reset. This pin alternatively
serves as debugWire channel or as generic I/O. The configuration depen ds on the fuses RST­DISBL and DWEN.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.14 XTAL2/PC0

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Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.
5

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

4. Code Examples

This documentation contains simple code examples that briefly sh ow how to use vari ous parts of the device. Be aware that not all C compiler vendors include bit def initions in the header files and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumen­tation for more details.
These code examples assume that the part spe cific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBI C", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega8U2/16U2/32U2
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6. AVR CPU Core

Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n

6.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

6.2 Architectural Overview

Figure 6-1. Block Diagram of the AVR Architecture
ATmega8U2/16U2/32U2
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipe lining. While one instruc tion is being executed, the next instruc­tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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7
ATmega8U2/16U2/32U2
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ­ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera­tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for­mat. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi­tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis­ters, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega8U2/16U2/32U2 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU opera tions are divided into three main categories – arithmetic, logical, and bit-functions. See the “Instruction Set” sec­tion for a detailed description.

6.4 Status Register

7799D–AVR–11/10
The Status Register contains information about the r esult of th e most recen tly executed arith me­tic instruction. This information can be used for altering program flow in order to perform
8
conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in man y case s re move th e need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be ha nd le d by software.

6.4.1 SREG – Status Register

Bit 76543210 0x3F (0x5F) ITHSVNZCSREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter­rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
ATmega8U2/16U2/32U2
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti­nation for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
7799D–AVR–11/10
9
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

6.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6-2. AVR CPU General Purpose Working Registers
General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11
ATmega8U2/16U2/32U2
70Addr. R0 0x00
R1 0x01 R2 0x02 … R13 0x0D
… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple­mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

6.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some a dded functions to their general purpose usage. These reg­isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.
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10

6.6 Stack Pointer

ATmega8U2/16U2/32U2
Figure 6-3. The X-, Y-, and Z-registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed d isplacem ent, automatic increment, and automatic decrement (see the instruction set reference fo r details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure
7-2 on page 18.
See Table 6-1 for Stack Pointer details.
Table 6-1. Stack Pointer instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL ICALL RCALL
POP Incremented by 1 Data is popped from the stack
RET RETI
Decremented by 2
Incremented by 2 Return address is popped from the stack with return from
Return address is pushed onto the stack with a subroutine call or interrupt
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa­tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
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11

6.6.1 SPH and SPL – Stack Pointer High and Low Register

clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
Bit 1514131211109 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 1 0 0 0 0 0
11111111

6.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast- access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the
CPU
ATmega8U2/16U2/32U2
Figure 6-4. The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycl e an ALU
operation using two register operands is executed, and the result is stored back to the destina­tion register.
Figure 6-5. Single Cycle ALU Operation
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6.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with th e Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 246 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 64. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 64 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 246.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis­abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
ATmega8U2/16U2/32U2
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec­tor in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap pears befo re the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
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ATmega8U2/16U2/32U2
CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..
Assembly Code Example
in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe­cuted before any pending interrupts, as shown in this example.
7799D–AVR–11/10
14
Assembly Code Example
sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending ; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

6.8.1 Interrupt Response Time

The interrupt execution response for all the enabl ed AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling ro utine is exe­cuted. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe­cution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
ATmega8U2/16U2/32U2
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre­mented by three, and the I-bit in SREG is set.
7799D–AVR–11/10
15

7. AVR Memories

This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi­tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

7.1 In-System Reprogrammable Flash Program Memory

The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable Flash memory for program storage . Since all AVR instructio ns are 16 or 32 bits wide, the Flas h is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 100,000 write/erase cycles. The ATmega8U2/16U2/32U2 Program Counter (PC) is 16 bits wide, thus addressing the 8K/16K/32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Memory Programming” on page
246. “Memory Programming” on page 246 contains a detailed description on Flash data serial
downloading using the SPI pins or the debugWIRE interface. Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description and ELPM - Ex tended Load Program Me mory instruction description).
ATmega8U2/16U2/32U2
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 12.
7799D–AVR–11/10
16
Figure 7-1. Program Memory Map
0x00000
0x1FFF (8KBytes)
0x3FFF (16KBytes)
Program Memory
Application Flash Section
Boot Flash Section
0x7FFF (32KBytes)
ATmega8U2/16U2/32U2

7.2 SRAM Data Memory

Figure 7-2 shows how the ATmega8U2/16U2/32U2 SRAM Memory is organized.
The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The first 768 Data Memory locations address the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory, and the 512 locations of internal data SRAM.The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post­increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base addres s given
by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
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17
The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter-
32 Registers
64 I/O Registers
Internal SRAM
(512/512/1024 x 8)
$0000 - $001F $0020 - $005F
$2FF/$2FF/$4FF (8U2/16U2/32U2)
$0060 - $00FF
Data Memory
160 Ext I/O Reg.
$0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.
Figure 7-2. Data Memory Map

7.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk
ATmega8U2/16U2/32U2
cycles as described in Figure 7-3.
CPU

7.3 EEPROM Data Memory

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Figure 7-3. On-chip Data SRAM Access Cycles
The ATmega8U2/16U2/32U2 contains 512/512/1024 bytes of data EEPROM memory. It is orga­nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/er ase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
18
For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 259, page 244, and page 250 respectively.

7.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con­tains instructions that write the EEPROM, some precautions must be take n. In heavily filtered power supplies, V some period of time to run at a voltage lower th an sp ecified as min imum for the clo ck freq uency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.3.2 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.
ATmega8U2/16U2/32U2
is likely to rise or fall slowly on power-up/down. This causes the device for
CC
the EEPROM data can be corrupted because the supply voltage is
CC,

7.4 I/O Memory

An EEPROM data corruption can be caused by two situ at ion s wh en the vo lt age is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec­ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-ou t Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V
reset Protection circuit can
CC
be used. If a reset occurs while a write operation is in progress, the write operation will be com­pleted provided that the power supply voltage is sufficient.
The I/O space definition of the ATmega8U2/16U2/32U2 is shown in “Register Summary” on
page 288.
All ATmega8U2/16U2/32U2 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis­ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Op code for the IN and OUT instructions. For the
7799D–AVR–11/10
19
Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with reg­isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.

7.4.1 General Purpose I/O Registers

The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global vari­ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.5 Register Description

ATmega8U2/16U2/32U2

7.5.1 EEARH and EEARL – The EEPROM Address Register

Bit 1514131211 10 9 8 0x22 (0x42) EEAR11 EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543 210
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 X X X X
XXXXX XXX
• Bits 15:12 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 11:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

7.5.2 EEDR – The EEPROM Data Register

Bit 76543210 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000
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• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
20

7.5.3 EECR – The EEPROM Control Register

Bit 76543210 0x1F (0x3F) EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig­gered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for th e differen t modes are shown in Table 7- 1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
ATmega8U2/16U2/32U2
Table 7-1. EEPROM Mode Bits
Programming
EEPM1 EEPM0
0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 Reserved for future use
Time Operation
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter­rupt when EEPE is cleared.
• Bit 2 – EEMPE: EEPROM Master Programming Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Programming Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other­wise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
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21
ATmega8U2/16U2/32U2
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Me mory Pr o-
gramming” on page 246 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft­ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a log ic one to trig ger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 7-2 lists the typic al pro­gramming time for EEPROM access from the CPU.
Table 7-2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time
EEPROM write (from CPU)
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob­ally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
26,368 3.3 ms
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22
ATmega8U2/16U2/32U2
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18 out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) {
/* Wait for completion of previous write */ while(EECR & (1<<EEPE))
; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
(1)
(1)
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Note: 1. See “Code Examples” on page 6.
23
ATmega8U2/16U2/32U2
The next code examples show assembly and C functions for reading the EEPROM. The exam­ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example
(1)
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18 out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR ret
C Code Example
(1)
unsigned char EEPROM_read(unsigned int uiAddress) {
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
Note: 1. See “Code Examples” on page 6.

7.5.4 GPIOR2 – General Purpose I/O Register 2

Bit 76543210 0x2B (0x4B) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

7.5.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210 0x2A (0x4A) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000
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24

7.5.6 GPIOR0 – General Purpose I/O Register 0

Bit 76543210 0x1E (0x3E) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000
ATmega8U2/16U2/32U2
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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 42. The clock systems are detailed below.
Figure 8-1. Clock Distribution
ATmega8U2/16U2/32U2
8.1.1 CPU Clock – clk
CPU
USB
clk
USB PLL
X6
clk
PLL Clock Prescaler
clk
USB (48MHz)
Pllin (8MHz)
XTAL (2-16 MHz)
Crystal
Oscillator
General I/O
Modules
clk
CPU Core RAM
I/O
AVR Clock
Control Unit
Source clock
System Clock
Prescaler
Clock
Multiplexer
External
Clock
clk
CPU
clk
FLASH
Watchdog TimerReset Logic
Watchdog clock
Watchdog Oscillator
Flash and EEPROM
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
8.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external inter­rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
8.1.3 Flash Clock – clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul­taneously with the CPU clock.
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FLASH
26
ATmega8U2/16U2/32U2
USB
CPU Clock
External Oscillator
RC oscillator
Ext RC Ext
non-Idle Idle
(Suspend)
non-Idle
3ms
resume
1
1
Resume from Host
Watchdog wake-up from power-down
8.1.4 USB Clock – clk

8.2 Clock Switch

8.2.1 Exemple of use

USB
The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48 MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8 MHz clock on the PLL input.
In the ATmega8U2/16U2/32U2 product, the Clock Multiplexer and the System Clock Presca ler can be modified by software.
The modification can occur when the device enters in USB Suspend mode. It th en switches from External Clock to Calibrated RC Oscillator in order to reduce consumption. In such a configura­tion, the External Clock is disabled.
The firmware can use the watchdog timer to be woken-up from power-down in order to check if there is an event on the application.
If an event occurs on the application or if the USB controller signals a non-idle state on the USB line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC Oscillator to the External Clock.
Figure 8-2. Example of clock switching with wake-up from USB Host
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27
Figure 8-3. Example of clock switching with wake-up from Device
USB
CPU Clock
External Oscillator
RC oscillator
Ext RC Ext
non-Idle Idle
(Suspend)
non-Idle
3ms
upstream-resume
2
2
Upstream Resume from device
Watchdog wake-up from power-down

8.2.2 Clock switch Algorythm

8.2.2.1 Swith from external clock to RC clock
if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1) { Usb_ack_suspend(); // UDINT.SUSPI = 0; Usb_freeze_clock(); // USBCON.FRZCLK = 1; Disable_pll(); // PLLCSR.PLLE = 0; Enable_RC_clock(); // CLKSEL0.RCE = 1; while (!RC_clock_ready()); // while (CLKSTA.RCON != 1); Select_RC_clock(); // CLKSEL0.CLKS = 0; Disable_external_clock(); // CLKSEL0.EXTE = 0; }
ATmega8U2/16U2/32U2
8.2.2.2 Switch from RC clock to external clock
if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1) { Usb_ack_wake_up(); // UDINT.WAKEUPI = 0; Enable_external_clock(); // CKSEL0.EXTE = 1; while (!External_clock_ready()); // while (CLKSTA.EXTON != 1); Select_external_clock(); // CLKSEL0.CLKS = 1; Enable_pll(); // PLLCSR.PLLE = 1; Disable_RC_clock(); // CLKSEL0.RCE = 0; while (!Pll_ready()); // while (PLLCSR.PLOCK != 1); Usb_unfreeze_clock(); // USBCON.FRZCLK = 0; }
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8.3 Clock Sources

ATmega8U2/16U2/32U2
The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 8-1. Device Clocking Options Select
Device Clocking Option CKSEL3:0
Low Power Crystal Oscillator 1111 - 1000 Full Swing Crystal Oscillator 0111 - 0110 Reserved 0101 - 0100 Reserved 0011 Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.3.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 pro­grammed, resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting u sing a ny available prog ramming inter face.

8.3.2 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.
(1)
to start oscillating and a minimum number of oscillating
CC
To ensure sufficient V
, the device issues an internal reset with a time-out delay (t
CC
TOUT
) after the device reset is released by all other reset sources. “On-chip Debug System” on page 45 describes the start conditions for the internal reset. The delay (t
) is timed from the Watchdog
TOUT
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics” on page 273.
Table 8-2. Number of Watchdog Oscillator Cycles
Ty p Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.
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29
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
XTAL2
XTAL1
GND
C2
C1
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.

8.4 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-4. Either a quartz crystal or a ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out­put. It gives the lowest power con sumption, bu t is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.
ATmega8U2/16U2/32U2
Figure 8-4. Crystal Oscillator Connections
The Low Power Oscillator can operate in three different modes, each optimized for a specific fre­quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.
Table 8-3. Low Power Crystal Oscillator Operating Modes
Recommended Range for Capacitors C1
Frequency Range
0.4 - 0.9 100
0.9 - 3.0 101 12 - 22
3.0 - 8.0 110 12 - 22
8.0 - 16.0 111 12 - 22
(1)
(MHz) CKSEL3..1
(2)
(3)
and C2 (pF)
7799D–AVR–11/10
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
30
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