Atmel ATmega162, ATmega162V Datasheet

Features

N

This i

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 131 Po we rful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Regi sters
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16K Bytes of In-System Self-programmab le Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles
– 1K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip De bug Support
– Programming of Flas h, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– T w o 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– T w o 16-bit Timer/Counters with Separate Prescaler s, Compare Modes, and

Capture Modes
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparat or

• Special Micro controller Features

– Powe r-on Reset and Programmable Brown-out Detection
– Internal Calibra ted RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

• Operating Voltages

– 1.8 - 5.5V for ATmega162V
– 2.7 - 5.5V for ATmega162

• Speed Grades

– 0 - 8 MHz for ATmega162V (see Figure 113)
– 0 - 16 MHz for ATmega162 (see Figure 114)

®

8-bit Microcontroller

8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash

ATmega162
ATmega162V

Advance
Information

Summary

2513DS–AVR–04/03

Rev. 2513DS–AVR–04/03

ote:

avai lable on our web site at

s a summary document. A complete document is

www.atmel.com

.

1

Pin Configurations Figure 1. Pinout ATmega162

(OC0/T0) PB0
(OC2/T1) PB1

(RXD1/AIN0) PB2

(TXD1/AIN1) PB3

(SS/OC3B) PB4

(MOSI) PB5
(MISO) PB6

(RXD0) PD0

(TXD0) PD1

(INT0/XCK1) PD2

(TOSC1/XCK0/OC3A) PD4

(INT0/XCK1) PD2

(TOSC1/XCK0/OC3A) PD4

(INT1/ICP3) PD3

(OC1A/TOSC2) PD5

(INT1/ICP3) PD3

(OC1A/TOSC2) PD5

(MOSI) PB5
(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

VCC

(TXD0) PD1

1
2
3
4
5
6

(SCK) PB7

RESET

(WR) PD6

(RD) PD7

XTAL2
XTAL1

1
2
3
4
5
6
7
8
9
10
11

7
8
9
10
11
12
13
14
15
16
17
18
19

GND

20

PB4 (SS/OC3B)

PB3 (TXD1/AIN1)

PB2 (RXD1/AIN0)

44 42 40 38 36 34

43 41 39 37 35

13 15 17 19 21

12 14 16 18 20 22

PDIP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TQFP/MLF

PB1 (OC2/T1)

PB0 (OC0/T0)

GND

VCC

PA0 (AD0/PCINT0)

VCC
PA0 (AD0/PCINT0)
PA1 (AD1/PCINT1)
PA2 (AD2/PCINT2)
PA3 (AD3/PCINT3)
PA4 (AD4/PCINT4)
PA5 (AD5/PCINT5)
PA6 (AD6/PCINT6)
PA7 (AD7/PCINT7)
PE0 (ICP1/INT2)
PE1 (ALE)
PE2 (OC1B)
PC7 (A15/TDI/PCINT15)
PC6 (A14/TDO/PCINT14)
PC5 (A13/TMS/PCINT13)
PC4 (A12/TCK/PCINT12)
PC3 (A11/PCINT11)
PC2 (A10/PCINT10)
PC1 (A9/PCINT9)
PC0 (A8/PCINT8)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PA4 (AD4/PCINT4)

33

PA5 (AD5/PCINT5)

32

PA6 (AD6/PCINT6)

31

PA7 (AD7/PCINT7)

30

PE0 (ICP1/INT2)

29

GND

28

PE1 (ALE)

27

PE2 (OC1B)

26

PC7 (A15/TDI/PCINT15)

25

PC6 (A14/TDO/PCINT14)

24

PC5 (A13/TMS/PCINT13)

23

VCC

GND

XTAL2

XTAL1

(RD) PD7

(WR) PD6

(A8/PCINT8) PC0

(A9/PCINT9) PC1

(A11/PCINT11) PC3

(A10/PCINT10) PC2

(TCK/A12/PCINT12) PC4

Disclaimer Typical values contained in thi s data sheet are based on s imulation s and cha racteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max va lu es w ill be av a ilable after the device is ch a r ac ter iz ed.

2

ATmega162/V

2513DS–AVR–04/03

ATmega162/V

Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys­tem designer to optimize power consumption versus processing speed.

Block Diagram Figure 2. Block Diagram

VCC

PA0 - PA7 PC0 - PC7

PORTA DRIVERS/BUFFERS

PE0 - PE2

PORTE
DRIVERS/
BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL
PURPOSE

REGISTERS

X
Y
Z

ALU

STATUS

REGISTER

SPI

PORTE

DIGITAL

INTERFACE

PORTC DIGITAL INTERFACE

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

TIMERS/

COUNTERS

EEPROM

USART0

OSCILLATOR

INTERNAL
CALIBRATED
OSCILLATOR

OSCILLATOR

XTAL1

XTAL2

RESET

2513DS–AVR–04/03

+

-

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

COMP.

INTERFACE

USART1

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7PB0 - PB7

3

The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 re gist ers ar e d irect ly co nnec ted t o t he Ari thme tic Logi c Un it (A LU), allow ing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.

The ATmega162 provides the following features: 16K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an
external memory interface, 35 general purpose I/O lines, 32 general purpose working
registers, a JTAG interface for Boundary-scan, On-chip Debugging support and pro­gramming, four flex ible Timer/Counters with com pare modes, internal and external
interrupts, two serial programmable USARTs, a programmable Watchdog Timer with
Internal Oscillator, an SPI serial port, and five software selectable power saving m odes.
The Idle mode stops the CPU whi le allowing the SRAM, Timer/Counters, SPI port, a nd
interrupt system to continue functioning. The Power-down mode saves the register con­tents but freezes t he Oscillat or, disabling all other chip funct ions until the n ext interrupt
or Hardware Reset. In Power-save m ode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the cr ystal/resonat or Oscillator is runnin g while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer con­tinue to run.

The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a convent ional non-volatil e memory progra mmer, or
by an On-chip Boot Program running on the AVR core. The Boot Program can use any
interface to download the Application Program in the Application Flash memory. Soft­ware in the Boot Flash s ection wil l continue to run while th e A pplication Flash sec tion is
updated, pro viding true Re ad-Whi le-Write operation . By co mbinin g an 8-bi t RISC CP U
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications .

ATmega161 and ATmega162 Compatibility

4

ATmega162/V

The ATmega162 AVR is supported with a full suite of program and system development
tools i nclud ing: C comp ile rs, m acro a sse mbl ers, progra m de bugg er /simu lators , In -Cir­cuit Emulators, and evaluation kits.

The ATmega162 is a hig hly complex m icrocontroller where t he number of I/O loca tions
supersedes the 64 I/O locations reserved in the AVR instruction set. To ensur e back­ward compatibility with the ATmega161, all I/O locations present in ATmega161 have
the sam e locat ions in A Tmega 162. So me addi tiona l I/O loca tions a re add ed in an
Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega1 62 internal RAM
space). Thes e locations can be reached by using LD/LDS/LDD and ST/STS/ STD
instructions only, not by using IN and OUT instructions. The relocation of the internal
RAM space may still be a problem for ATmega161 users. Also, the increased number of
Interrupt Vectors might be a problem if the code uses absolute addresses. To solve
these problems, an ATmega161 compatibility mode can be selected by programming
the fuse M161C. In this m ode, none o f the functions i n the Exte nded I/O sp ace are i n
use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec­tors are re moved . The ATm ega16 2 is 1 00% pin compa tible wi th ATme ga1 61, an d can
replace the ATmega161 on current Printed Circuit Boards. However, t he location of
Fuse bits and the electrical characteristics differs between the two devices.

2513DS–AVR–04/03

ATmega162/V

ATmega161 Compatibility Mode

Programming the M161C will change the following functionality:

• The extended I/O map will be configured as internal RAM once the M161C Fuse is
programmed.

• The timed sequence for changing the Watchdog Time-out period is disabled. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page
54 for details.

• The double buffering of the USART Receive Registers is disabled. See “AVR
USART vs. AVR UART – Compatibility” on page 166 for details.

• Pin change interrupts are not supported (Contol Registers are located in Extended
I/O).

• One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible .

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers
in ATmega 162, UBRR 0H and UB RR1H. The l ocation of th ese regist ers will not be
affected by the ATmega161 compatibility fuse.

Pin Descript i on s

VCC Digital supply voltage GND Ground Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull -up resistors (sele cted for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current if the internal pull-up resistors are activated. The Port
A pins are tri-stated when a reset condition becomes active, even if the clock is not
running.

Port A also serves the f unctions of v ario us spec ial f eat ures of the ATmega162 as listed
on page 70.

Port B (PB7..P B0) Port B is an 8-bit bi-directional I/O port with internal pull -up resistors (sele cted for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. A s inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a res et
condition becomes active, even if the clock is not running.

Port B also serves the f unctions of v ario us spec ial f eat ures of the ATmega162 as listed
on page 70.

Port C (PC7..P C0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected fo r each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability . As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes ac tive, even i f the clock is no t running . If the JTAG int erface is
enabled, the pul l-up resist ors on pins PC 7(TDI), PC 5(TMS) an d PC4(T CK) will be acti­vated even if a Reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the
ATmega162 as listed on page 73.

2513DS–AVR–04/03

5

Port D (PD7..P D0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected fo r each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability . As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port D also serves the f unc tions of various special features of t he A Tmega162 as listed
on page 76.

Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull -up resistors (sele cted for each

bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. A s inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a res et
condition becomes active, even if the clock is not running.

Port E also serves the f unctions of v ario us spec ial f eat ures of the ATmega162 as listed
on page 79.

RESET

XTAL1 Input to the Inverting Oscillator am plif ier and input to th e internal clock operating circuit. XTAL2 Output from the Inve rting Oscillat o r a mplifier.

Reset input. A low le ve l on this pin for l onger than the minimum pul se length will gener­ate a Reset, even if the clock is not running. The minimum pulse length is given in Table
18 on page 46. Shorter pulses are not guaranteed to generate a reset.

About Code Examples This documentation contains simple code examples that briefly show how to use various

parts of the device. These code examples assume that the part specific header file is
included before com pilation. Be aware t hat not all C com pile r vendors incl ude bi t defini­tions in the header files and inte rrupt hand ling in C is c ompiler de pendent . Please
confirm with the C compiler documentation for more details.

6

ATmega162/V

2513DS–AVR–04/03