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PCIE-8120
Installation and Use
P/N: 6806800R89C
July 2014
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©
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Industrial Computer Manufacturers Group.
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omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document
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It is possible that this publication may contain reference to or information about Artesyn products (machines and programs),
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Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in
Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and
Documentation clause at DFARS 252.227-7014 (Jun. 1995).
Contact Address
Artesyn Embedded Technologies Artesyn Embedded Technologies
Marketing Communications
2900 S. Diablo Way, Suite 190
Tempe, Arizona 85282
Lilienthalstr. 17-19
85579 Neubiberg/Munich
Germany
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Contents
Contents
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Ordering/Support Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Unpacking and Inspecting the Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Environmental, Thermal, and Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1 Environmental and Thermal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Card Installation and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 Installation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.2 Removal Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Installing Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 PCIE-8120 Software Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 Configuration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.1 Initialization of the Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.2 Setting up the Host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.3 Starting the DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 Demo Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5.1 Executing Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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5 Application Development Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1 Application Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Application Development Tool Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.1 Octasic Linux Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Octasic DSP Firmware image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1 Octasic DSP Firmware image creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.2 12xDSP Audio Transcode Demo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A PCIE-8120 External Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A.2 PCIE-8120 Card Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A.3 J1/J2 External Ethernet Connector s/w status LEDs (not available on -N versions) . . . . . . . . . . . 52
A.4 P2 External ATX 6-Pin Power Connector (only on
-N versions) 53
A.5 Debug Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
A.6 P3 Fan Unit Connector (Optional component) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
B PCIE-8120 Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
B.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
B.2 Block Diagrams for PCIE-8120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
B.3 Card Reset Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.4 Power Supply Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.5 Card Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.6 Ethernet NIC - i82580EB/DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B.6.1 NV-Memory-NIC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B.7 Ethernet Switch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B.7.1 Main Switch Unit (MSW) - BCM5396 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.7.2 Video Switch Unit (VSW) - BCM5396 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.7.3 Ethernet Port Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
B.8 Media Flow Aggregator (MFA) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
B.9 Glue Logic - CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
B.9.1 Card Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
B.9.2 Interfaces and S/W control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
B.9.2.1 MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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B.9.2.2 Card Variant MOD_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
B.9.2.3 Card BASE_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
B.9.2.4 Opus Debug Port Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
B.9.2.5 SMBus and PVT_I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
B.9.2.6 Debug LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
B.9.3 CPLD Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
B.10 DSP Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
B.10.1 DSP Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
B.10.2 DDR3 Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
B.10.3 Ethernet MAC Engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
B.10.4 Boot Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
B.10.5 DSP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
B.10.6 DSP 25MHz Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
B.10.7 OPUS Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
C.1 OctSetup Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
C.2 DSP Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
D Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
D.1 OctSetup: Internal Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
D.2 Identifying the Card at PCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
D.3 Serial Number of the card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
D.4 12xDSP Audio Transcode Voip Channel Demo Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
D.4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
D.4.2 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
D.4.3 Running Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
E Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
E.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . . . 91
E.2 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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List of Tables
Table 1-1 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-2 Available Board Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3-1 Environmental and Thermal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3-2 Wattage Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3-3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table A-1 PCIE-8120 Card Edge Connector Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table A-2 ATX PWR Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table A-3 Opt. fan unit connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table B-1 Card Variant MOD_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table B-2 Sensor alert default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table B-3 LED Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table B-4 LED Error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table B-5 Ethernet Physical Interface Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table B-6 DSP Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table E-1 Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . . 91
Table E-2 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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List of Figures
Figure 1-1 Software Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 1-2 Mechanical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5-1 Octasic Firmware Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 5-2 Files in firmware build . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure A-1 PCIE-8120 Primary and Secondary Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure B-1 Card Block Diagram PCIE-8120-A12/V12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure B-2 Card Block Diagram PCIE-8120-A04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure B-3 Card Block Diagram PCIE-8120-A12-N/V12-N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure B-4 Card Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure B-5 Board Power Supply Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure B-6 Card Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure B-7 Port Mapping PCIE-8120-A12/V12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure B-8 Port Mapping PCIE-8120-A04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure B-9 Port Mapping PCIE-8120-A12-N/V12-N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure B-10 SMBus and PVT_I2C bus connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure B-11 Temperature Sensor Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure D-1 Host Network Set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure D-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PCIE-8120 Installation and Use (6806800R89C)
9
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List of Figures
10
PCIE-8120 Installation and Use (6806800R89C)
Page 11
About this Manual
Overview of Contents
This manual is divided into the following chapters and appendices.
Introduction on page 17 gives a brief overview of the product features, standard safety
compliances and ordering information.
Functional Description on page 23 describes media processing functions of the component.
Hardware Preparation and Installation on page 25 includes a procedure for unpacking the
product, environmental and power requirements, additional required equipment,
installation, and removal instructions.
Software Installation on page 31 includes prerequisites, software packages, software
installation, and demo application.
Application Development Overview on page 39 includes application development kit,
octasic Digital Signal Processor (DSP) firmware image creation, and 12xDSP audio
transcode demo application.
Appendix A, PCIE-8120 External Connectors, on page 49 describes the board layout, board
LEDs, and connectors.
Appendix B, PCIE-8120 Hardware Description, on page 55 includes block diagrams and
functional description of major components.
Appendix C, Known Issues, on page 81 describes known issues of octSetup and DSP
connection.
Appendix D, Miscellaneous, on page 83 describes octSetup, card identification on PCI-Bus,
and Serial number of the card.
Related Documentation on page 91 provides a listing of related product documentation,
manufacturer’s documents and industry standard specifications.
Safety Notes on page 93 describes the safety information which has to be regarded.
Sicherheitshinweise on page 97 provides a German translation of the chapter “Safety
Notes”.
PCIE-8120 Installation and Use (6806800R89C)
11
Page 12
About this Manual
Abbreviations
This document uses the following abbreviations:
Abbreviation Definition
API Application Programmers Interface
ATX Advanced Technology Extended
BGA Ball Grid Array
CEM Card Electro Mechanical
CISPR Comité Internationale Spécial des Perturbations
Radioelectrotechnique
CPLD Complex Programmable Logic Device
DC Direct Current
DDR Double Data Rate
About this Manual
DHCP Dynamic Host Configuration Protocol
DRAM Dynamic Random Access Memory
DSP Digital Signal Processor
EMC Electromagnetic Compatibility
EMV Elektromagnetische Verträglichkeit
EN European Norm
ESD Electrostatic Discharge
ETH Ethernet
ETSI European Telecommunications Standards Institute
FCC Federal Communications Commission
FPGA Field Programmable Gate Array
Gbps Gigabit per second
I/O Input Output
ID Identifier
IEC International Electro technical Commission
IP Internet Protocol
12
PCIE-8120 Installation and Use (6806800R89C)
Page 13
Abbreviation Definition
JTAG Joint Test Action Group
LED Light Emitting Diode
LV Low Voltage
MAC Media Access Controller
MDIO Management Data I/O
MFA Media Flow Aggregator
MGW Media Gateway
MSW Main Switch
NEBS Network Equipment Building Standards
NIC Network Interface Controller
NVRAM Non-Volatile Random Access Memory
About this Manual
OCTVOC Internal code name for Octasic DSP 1010
OCTVOC2 Internal code name for Octasic DSP 2224M (equipped on PCIE-8120)
OCTVOC2_EB Internal code name for Octasic Evaluation Board equipped with DSP
2224M
OS Operating System
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
PCI-E Peripheral Component Interconnect Express
PHY Physical Layer Access Device
S/W Software
SELV Safety Extra Low Voltage
SerDes Serializer-Deserializer
SGMII Serialized Gigabit Media Independent Interface
SMBus System Management Bus
SPI Serial Protocol Interface
TPE Twisted-Pair Ethernet
PCIE-8120 Installation and Use (6806800R89C)
13
Page 14
About this Manual
Abbreviation Definition
TFTP Trivial File Transfer Protocol
UL Underwriters Laboratories Incorporated
VCCI Voluntary Control Council for Interference
VSW Video Switch
Conventions
The following table describes the conventions used throughout this manual.
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits are
0 through F), for example used for addresses and
offsets
About this Manual
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word
Screen Used for on-screen output and code related elements
or commands in body text
Courier + Bold Used to characterize user input and to separate it
from system output
Reference Used for references and for table and figure
descriptions
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys
[text] Notation for software buttons to click on the screen
and parameter description
... Repeated item for example node 1, node 2,..., node
12
.
.
.
.. Ranges, for example: 0..4 means one of the integers
Omission of information from example/command
that is not necessary at the time being
0,1,2,3, and 4 (used in registers)
14
PCIE-8120 Installation and Use (6806800R89C)
Page 15
Notation Description
| Logical OR
Indicates a hazardous situation which, if not avoided,
could result in death or serious injury
Indicates a hazardous situation which, if not avoided,
may result in minor or moderate injury
Indicates a property damage message
About this Manual
No danger encountered. Pay attention to important
information
Summary of Changes
This manual has been revised and replaces all prior editions.
Part Number Publication Date Description
6806800R89A March 2013 Initial version.
6806800R89B July 2013 Updated 6806800R89A.
6806800R89C July 2014 Re- branded to Artesyn template.
PCIE-8120 Installation and Use (6806800R89C)
15
Page 16
About this Manual
About this Manual
16
PCIE-8120 Installation and Use (6806800R89C)
Page 17
Introduction
1.1 Features Summary
The PCIE-8120 is Octasic Digital Signal Processor (DSP) based PCI Express card for rack mount
server based installations in a telecom network environment. The PCIE-8120 media processing
accelerator enables high density voice and video processing to be integrated into a rack mount
server or other network appliances that feature standard PCI Express slots.
The following are PCIE-8120 hardware components and its features:
Full height, full-length single slot PCIe add-in card with x4 PCIe interface.
High performance media processing core, based on power efficient DSPs.
Comprehensive voice and video processing firmware and programmers interface
included.
Assembly variants with 4, 8 or 12 DSP building blocks.
Chapter 1
Optional 2 x GbE ports (RJ45) with network address translation (NAT) function for direct
network attachment providing server off load.
Support for 720p and 1080p video conferencing (each DSP has 2 x 1Gb/s data path).
Card can operate either from slot power or from an external connector for NEBS variant,
which requires 3.3V if operated through the slot.
Power envelope of 75 Watts for > 4 DSP slot powered versions.
Designed for NEBS level 3 and ETSI telecom standards compliance when used in a suitable
carrier grade enclosure that provides sufficient airflow.
1.2 Software Components
Following are the software components used to configure the PCIE-8120 card:
The PCIE-8120 card support software.
The Octasic Vocallo Media Gateway (MGW) application software.
PCIE-8120 Installation and Use (6806800R89C)
17
Page 18
Introduction
The following figure provides an architectural overview of the PCIE-8120 software:
Figure 1-1 Software Diagram
18
The PCIE-8120 support software configures the PCIE-8120 card, sets up the switches to which
the DSPs are connected, and initializes the card.
The user application manages the Vocallo media processing services through a packet based
Application Programmers Interface (API). The portable transport API library allows user
application to interact with the packet interface.
PCIE-8120 Installation and Use (6806800R89C)
Page 19
1.3 Standard Compliances
This product is designed to meet the following standards when installed in an appropriate
system environment:
Table 1-1 Standard Compliances
Standard Description
Introduction
UL 60950-1
EN 60950-1
IEC 60950-1
CAN/CSA C22.2 No 60950-1
CISPR 22
CISPR 24
EN 55022
EN 55024
FCC Part 15
Industry Canada ICES-003
VCCI Japan
AS/NZS CISPR 22
EN 300 386
NEBS Standard GR-1089 CORE
NEBS Standard GR-63-CORE
ETSI EN 300019 series
PCI-SIG CEM Rev.2.0 PCI Express Card Electromechanical Specification
Legal safety requirements
EMC requirements (legal) on system level (predefined
Artesyn system)
Environmental requirements
Revision2.0
PCIE-8120 Installation and Use (6806800R89C)
19
Page 20
Introduction
1.4 Ordering/Support Information
When ordering card variants or requesting support information, use the order numbers given
in the following table:
Table 1-2 Available Board Variants
Est.Max
Number of
Order Number
PCIE-8120-A12 12 55W 65W Yes Slot No
PCIE-8120-V12 12 55W 65W Yes Slot Yes
PCIE-8120-A04 4 23W 27W Yes Slot No
PCIE-8120-V04 4 23W 27W Yes Slot Yes
PCIE-8120-A08 8 39W 46W Yes Slot No
PCIE-8120-V08 8 39W 46W Yes Slot Yes
PCIE-8120-A12-N 12 53W 63W No Ext No
PCIE-8120-V12-N 12 53W 63W No Ext Yes
DSPs
Power
@35C
Est.Max
Power
@NEBS
External
GbE ports
Slot or Ext
Power
Video SW
Support
20
PCIE-8120 Installation and Use (6806800R89C)
Page 21
1.5 Mechanical Data
The outline of the PCIE-8120 card and dimensions are shown in Figure 1-2.
Figure 1-2 Mechanical Layout
29.95
4.85
M13
C254
C28
C30
C18
C16
C20
U2
43
R137
C17
C22
C25
C37
P3
E31 R258
D5300
D5301
D5302
R300
D5303
R342
D5304
D5305
D5306
B1
D5307
R328
B11
C923
R845 R846
B12
R275
A16
P1
B32
C920
R817
C919
C6810
C6822
R6834
C6818
C6823
C6824
A22
AB1
C6953
C6951
R6931
R6939
R6938
C6914
C6920
C5527
C5526
C5525
C5519
C5521
C5520
C7010
C7021
R7034
C7018
C7024
C7025
A22
299.25
304.50
7.50
49.65
40.55
E3
29
C21
C19
C23
C24
R136
15
R135
Q3
R313
R327
R314
R315
R316
D1
K
K
K
K
K
K
K
T1
K
R277
R283
U452
R279
R1
C84
R844
U45
R819
R818
R260
C6815
R6835
R6832
C6826
U6800
C6803
R6960
R6961C6802
R6965
R6964
U6900
C6922
C6952
C6916
C6917
R6940
C6926
R6933
Q5500
5
C5530
C5529
C5528
C5523
C5524
C9
C5522
C8
Q5501
5
C7015
R7035
R7032
C7023
U7000
R154
C83
C80
R259
R348
R350
U1000
C907
C908
C963
C85
T1
C06201
R06201
C921
C922
R6833
C6825
R6840
R6841
C6817
C6816
C6855
C6821
R6860
R6862
R6864
R6865
R6863
R6861 C6902
R6963
R6962
C6903
C6923
R6941
R6932
R6935
C6915
L5500
L5501
R7033
C7026
R7040
R7041
C7017
C7012
C7052
C7022
85.40
J2
R152
C70
C76
DN7DN8
A16
U1001
R6421
R5102
C232
C258
R281
R282
R280
C926
R343
C932
U5006
U5004
11
U5005
11
C6820
C6814
R6838
R6839
R6831
C6854
C6851
AB1
M9
C82017
A22
C80017
A16
C6925
C6924
C6918
R6934
C6921
C6910
C80112 C80312
A16
M16
C7016
C7014
R7038
R7039
R7031
C7051
C7053
C7020
101.80
J1
C51
C46
C57
R144
U1
C64
15
R112
C81
C77
DN6
C5408
C6415
R6432
C6424
C64033
C64023
C64022
C64032
C64020
R6561
R6560
AB1
C6521
C6551
C6556
C6518
R6532
R6540
R6538
R6533
C82000
C82018
C82001
C80000
C80001
C80018
U8000
C80044
C80054
C80051
Y8000
C80053
C80043C80041
U9000
R90238
R90239
R9046
R9047
C6615
R6631
C6625
C73
C68
DN5
P99
P5001
C54070
C54071
R5403 C5405
U5400
L5400
C5401
R6433
C6425
R6435
R6440
R6441
C6418
C6416
C6456
C6426
C6421
U6400
C6400
R6462
R6463
C6401
R6461
R6460
C64021
C64031
C65020
C65030
C65022
C65032
C64030
C65021
C65031
C65023
C65033
R6563
R6562
C6501
C6500
U6500
C6523
C6510
R6541
R6531
R6535
C6515
C6526
C82002
C82003
C80220
C80221
C80002
C80003
C80320
C80321
C80231
C80230
R8000
R80238
R8046
R8047
R80239
T1
C80223 C80323
C80222
C80527
C80526
C8027
C8026
C5441
T1
Y9000
R6633
C6626
R6635
R6640
R6641
C6617
C6616
C6652
C6623
C6622
U6600
U4203 U10
C54072
C54073
C6420
C6414
R6438
R6439
R6431
C6455
C6451
AB1
M7
A22
C6525
C6524
C6517
R6534
C6522
C6516
Y8001
C80331
C260 R360
C80330
C261
C80322
C5448
U5440
L5440
U12
13
C6620
C6614
R6638
R6639
R6632
C6651
C6653
C5406
M15
U18
U19
R361
C233
R293
R292
R5443 C5440
C256
C257
M17
R151
U1002
U17
C6410
C6422
R6434
C6417
C6423
A22
C6552
R6539
C6514
C6512
C82019
C82016
C80016
C80019
C80113
C80313
C6610
C6621
R6634
C6618
C6624
A22 A22
43
C54
C59
C50
C250
C49
C45
E8
29
R113
C48
C53
C52
C47
U8
L5600 L5601
C10
C5622
C5623
5 5
Q5600
C5624
C5630
C5626
C5621
C5619
C5625
C6012
C6026
C6022
M*
C6014
R6034
R6035
R6031
R6041
C6017
C6024
C6016
C6023
C6051
U6000
C6000
R6062
R6063
C6001
C60021
C60031
C60041
C61030
C60050
C60020
C60030
C60040
C61021
C61031
R6161C60051
R6162
R6163
R6160
C6100
C6101
U6100
C6122
C6125
C6151
C6152
C6116
C6126
C6117
R6141
R6132
R6135
R6140
R6139
R6138
C6115
C6114
C6154
C6150
R6133
A16
N1
U4150
A9
C4151
C4150
C4152
C4153
C41152
C41153
C41151
C41150
R294
C5438
C5447
C5431
R5433
U5430
C5437
C5435
L5430
C5436
C5446
P2
C6210
C6224
C6222
C6215
R6234
R6235
R6231
R6241
C6218
C6226
C6216
C6225
C6223
U6200
M11
J3
C11
C5628
C5629
C5627
R6033
C6020
C6015
R6038
R6039
R6032
R6040
C6018
C6025
C6052
C6053
C6021
M5
R6061
R6060
C61020
C61022
C61032
C61023
C61033
C6156
C6153
C6118
R6131
R6134
C6121
C6120
U4200
C41110
C41111
C4110
C4111
C4112C41112
C4113C41113
U4100
N1
R6233
C6220
C6214
R6238
R6239
R6232
R6240
C6217
C6254
C6255
C6251
C6221
Introduction
AAA
Q5601
C5620
T16
T1
Y4200
A9
PCIE-8120 Installation and Use (6806800R89C)
M10
AB1 AB1 AB1
C70002
C70003
C70013
C70012
C7002
C7003
R7060
R7062
R7063
R7061
C70001
C70011
C7001
C7000
R7160
R7161
R7163
R7165
R7164
R7162
C7100
C7103
C7101
C7102
AB1AB1AB1
U7100
A22A22A22
C7126
C7122
C7153
C7124
C7152
C7120
C7125
C7151
R7131
R7139
R7138
C7114
C7150
AAA
M14
R226
C227
C7118
C7117
R7141
R7132
R7135
R7140
R228 R229
R7134
C7115
C7121
C7123
R227
R230
C7112
R7133
C5418
U5410
C5411
C54171
C54170
C54172
C54173
C5416
L5410
C6750
C6751
R6732
R6739
C6714
C6712
C6602
R6761
C6755
C6754
R6738
R6663
R6662
R6664
R6665
C6601
C6603
C6600
R6661
R6660
R6763
R6765
R6764
R6762
R6760
C6703
C6702
U6700
C6721
C6725
C6710
C6717
R6741
R6731
R6735
R6740
C6715
C6724
R6733
P4200
C6723
M8
C6726
C6718
R6734
C6722
C6716
94.55
M6
C6202
R6262
R6264
R6265
C6203
R6261
R6260
R6263
R6361
R6362
R6365
R6364
R6360
C6303
C6302
R6363
U6300
R5508
R5509
C6323
C6322
C6351
C6326
M*
C6355
C6316
C6325
C6352
C6317
C6318
R6341
R6332
R6335
R6331
R6340
R68
R67
R6339
R70
R69
R263
C6314
C6312
R72
R71
R255
C150
R256
E32
C5428
U5420
L5420
C5421
R6334
R6338
C6315
C6321
C6324
C6310
R6333
AAA
M12
C54270
C54271
C54272
C54273
C5426
5.02
21
Page 22
Introduction
The PCB size according to PCI-SIG CEM specifications is:
Height=101.80 mm.
Length=304.50 mm.
22
PCIE-8120 Installation and Use (6806800R89C)
Page 23
Functional Description
2.1 Overview
PCIE-8120 is based on the Octasic OCT2224M multi-core DSP running Vocallo MGW firmware.
The DSP array performs media processing acceleration for a host server, supporting both voice
and video conferencing and transcode applications.
Media acceleration performance depends on both the codecs required and the number of
DSPs available. A variety of board configurations allow differences in application needs and
server capabilities, and include a choice of 4, 8 and 12 DSPs, with maximum power
consumption between 25W and 65W.
NOTE: An external power connector option is available only for NEBS variant.
Media streams for transcoding are typically RTP/UDP/IP streams that go to the DSP array. The
functions that can be applied to each media stream are determined by the capabilities of the
Vocallo MGW firmware. For more information on the media processing functions, see PCIE-
8120 Data Sheet.
Chapter 2
Media streams can be routed to the DSPs either via the host CPU or optionally via two external
Gigabit Ethernet ports provided for direct traffic termination. In this configuration, packets for
transcode can bypass the host computer entirely, while a special Network Address Translation
(NAT) device makes the board appear as a single IP address to external networks.
2.2 Programming Model
The internal data flows of the board are all based on Gigabit Ethernet connections with all DSPs
accessible via a local Ethernet switching subsystem. Host access to all the DSPs is via a 2 x 1Gb/s
PCI Ethernet controller. The Ethernet switching subsystem also supports two 1Gb/s links to
each DSP to support special 1080p video conferencing modes. Based on the number of DSPs,
this is provided by either one or two on-board Ethernet switches. For more details, see the
block diagrams in PCIE-8120 Hardware Description on page 55. For most applications, this detail
is invisible to the application.
A comprehensive host-based Media Processing Application Programmers Interface is
provided. This is used to configure and execute voice and video stream processing functions on
the DSPs. The API commands communicate directly with the DSP array based on an endpoint
and stream resource model. A non-blocking command/response protocol supports multichannel programming efficiency.
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Functional Description
Additional board support utilities can set the board's internal switching infrastructure into
various modes, and provide diagnostic information.
24
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Hardware Preparation and Installation
3.1 Overview
In this chapter, you can find information on the following topics:
Unpacking and inspecting the card.
Environmental, thermal, and power requirements.
Card installation and removal.
3.2 Unpacking and Inspecting the Card
Chapter 3
Damage of Circuits
Electrostatic discharge and incorrect installation and removal of the card can damage
circuits or shorten their life.
Before touching the card or electronic components, make sure that your are working in an
ESD-safe environment.
Shipment Inspection
To inspect the shipment, perform the following steps:
1. Verify that you have received all items of your shipment:
PCIE-8120 card.
Any optional items ordered.
2. Check for damage and report any damage or differences to the customer service.
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Hardware Preparation and Installation
3. Remove the desiccant bag shipped with the card and dispose it according to your
country’s legislation.
The card is thoroughly inspected before shipment. If any damage has occurred during
transportation please contact our customer service immediately.
3.3 Environmental, Thermal, and Power Requirements
The following environmental, thermal, and power requirements are applicable to the card:
3.3.1 Environmental and Thermal Requirements
You must make sure that the card, when operated in your particular system configuration,
meets the environmental requirements specified below:
Operating temperatures refer to the temperature of the air circulating around the card and not to
the component temperature.
High humidity and condensation on the card surface causes short circuits.
Do not operate the card outside the specified environmental limits. Make sure that the card
is completely dry and there is no moisture on its surface before applying power.
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Hardware Preparation and Installation
Table 3-1 Environmental and Thermal Requirements
Requirement Operating Non-Operating
Temperature 0xC to +55xC -40xC to +70xC
Forced Air Flow recommended >0.5m/s
Temp. Change +/-0.25xC/min +/-0.25xC/min
Rel. Humidity 5% to 90% non-condensing 5% to 95% non-condensing
-
Vibration
5 to 200Hz
1g sinusoidal 1g sinusoidal
The PCIE-8120 temperature sensors provide alerts about absolute and delta temperature level
on the card. For more information on the default values to set up sensor alarms, see Sensor Alert
Default Values, Table B-2 on page 74.
3.3.2 Power Requirements
Before installing the card, make sure that the system is capable to safely deliver the required
power.Typical wattage status is given for the following operating conditions:
Table 3-2 Wattage Status
Wattage Status Description
Idle Card powered and is in the default reset state.
Active Power good status on all DSP operations.
Maxload Maximum load test condition (Not achieved during normal operation).
Table 3-3 Power Requirements
PCIE-8120-A12/V12 PCIE-8120-A04/V04 PCIE-8120-A12/V12-N
3.3V current <100mA <100mA <100mA
Typ.Wattage
Idle 20W 12W 20W
Active 35W 15W 32W
Maxload 65W 25W 70W
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Hardware Preparation and Installation
Table 3-3 Power Requirements
PCIE-8120-A12/V12 PCIE-8120-A04/V04 PCIE-8120-A12/V12-N
12V max. current 5.5A 2.1A 6A
3.4 Card Installation and Removal
3.4.1 Installation Procedure
Ensure that the rack mount server area can hold the full height/length PCIE-8120 card. The rack
mount server provides snap-in fixation or screw holes. Other servers provide additional card
retainer part.
The PCIE-8120 card requires PCIE x4 connector size. It should be installed in a minimum x4
wide slot, typically or x8 or x16 slot. Ensure that the I/O slot can supply a power envelope via
the 12V supply rail.The PCIE-8120 card can be powered-up in any slot with minimum power
supply of 25W (i.e., any x4, x8, or x16 I/O slot). However, the PCIE-8120 card must be
configured as a high power device to use the full 75W. For more power-up details on PCIE-8120
card, see Table 1-2 on page 20. For PCIE-8120, a reduced number of DSP can be taken into
operation if the full 75W supply is not available.
28
An external ATX power connector option is available only for NEBS variant. For this you need to
order PCIE-8120 card with an external power connector. Cards with external power connectors
cannot be recognized by the host without external power connection.
Use the following steps to install the PCIE-8120 card into the rack mount server:
1. Use anti-static pads and attach an ESD strap to your wrist. Attach the other end of the ESD
strap to an electrical ground (refer to Unpacking Guidelines). The ESD strap must be
secured to your wrist and to ground throughout the procedure.
2. Identify the rack mount server to be used for installation.
3. Remove any filler panel that might fill that slot.
4. Continue to gently push the card along the guide rails till the card is fully engaged with the
connector. Avoid excessive force during this operation.
5. Connect the cables appropriately.
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3.4.2 Removal Procedure
The following procedure describes how to remove the PCIE-8120 card from the rack mount
server:
1. Make sure you are in an ESD safe environment.
2. Remove any cable that is connected to the card.
3. Power off the system before removing the card.
4. Gently pull the PCIE-8120 card to disconnect from the connectors. Continue to slide the
card outward along the guide rails from the rack mount server.
5. Install the filler panel.
Hardware Preparation and Installation
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Software Installation
4.1 Prerequisites
Before installing the PCIE-8120 card, ensure that the following software packages are
installed on your host:
1. vconfig
2. xinetd
3. net-tools
4. dhcp
5. tftp-server
6. pciutils
7. ethtool
8. policycoreutils-python (needed if SELinux is installed and enabled)
Chapter 4
Download the following packages from the SWORDS portal or you can contact your local
Artesyn support personnel to get them installed on your host:
1. PCIE-8120 support package: PCIE8120-<version>.zip
2. Octasic software package: octasic-sdk-<version>.zip
3. Documentation package: PCIE8120-doc-<version>.zip
Follow the steps below for software installation:
1. Mount the card in your system. For more information on PCIE-8120 card installation,
see Card Installation and Removal on page 28.
2. Install the software. For software installation procedure, see Installing Software on
page 31.
3. Run the demo.
NOTE: Before starting the demo, refer to known issues section in C.1 on page 81.
4.2 Installing Software
You must be a super user to install the packages or to execute some tools from the support
package.
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Software Installation
Unpack and install the following rpm files:
1. The pcie8120-<version>.zip file contains an RPM with the support package. Install
the RPM with:
# rpm -ihv pcie8120-<version>.el6.x86_64.rpm.
The installed software will be in /opt/bladeservices.
2. The octasic-sdk-<version>.zip file contains two RPMs with the Octasic software
and a support library. Install them with:
# rpm -ihv sofia-sip-<version>.el6.x86_64.rpm
# rpm -ihv octasic-sdk-<version>.el6.x86_64.rpm.
The installed software will be in /opt/octasic.
After the installation, add /opt/bladeservices/bin to the PATH variable of the user.
export PATH = $PATH: /opt/bladeservices/bin
4.3 PCIE-8120 Software Package
LIBRARY
The library is a C-programming interface provided for software development that provides
access to the resources on the card.The components that can be accessed are:
1. Switches
The DSPs are connected to the ports of the switches. You can configure the switches.
2. CPLD
The CPLD provides access to functions and components of the card.
The CPLD controls the reset state of the DSPs and provide access to the onboard
voltage and temperature sensors.
Installing the RPM creates the following folders and files:
Folder Description
/opt/bladeservices/bin Contains tools.
/opt/bladeservices/share/doc/htmlContains documentation.
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Folder Description
/opt/bladeservices/include Includes PCIE-8120 header files.
/opt/bladeservices/lib Contains PCIE-8120 library.
/opt/bladeservices/modules Contains PCIE-8120 kernel module.
/opt/bladeservices/share/octasic Contains specific configuration files to create
4.4 Configuration Overview
When first initialized, the board infrastructure is initialized into a default condition and the
DSPs are held in reset waiting for the rest of the system to start up.
When the DSPs are taken out of reset, DSPs send out DHCP DISCOVER messages to get a
firmware image. Once the DSP retrieves its networking information from the DHCP-server, a
firmware image is loaded to the DSP. The DSP automatically loads a firmware image via TFTP
GET, in case a boot file provided in the DHCP response from the server. Otherwise, a firmware
image should be uploaded using TFTP PUT to the DSP.
Software Installation
firmware images for the DSPs.
The standard configuration assumes that DHCP and TFTP servers are already installed and
configured on the system. The octSetup tool from the support software serves for setting up a
standard configuration on both DHCP and TFTP servers locally on the system.
When the DSP has loaded the right firmware image and is running, it is ready to handle media
streams according to application control.
4.4.1 Initialization of the Card
Initialize the PCIE-8120 card before you start using it. Call
# pcie8120-init
PCIe-8120 Initialization
fdev00.00 ... ok.
fdev00.01 ... ok.
fdev00.02 ... ok.
NOTE: To perform the initialization of all installed cards in the system, execute the above step
once after every reboot.
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Software Installation
4.4.2 Setting up the Host
Follow the steps below to set up the host:
1. Before setting up the host assume the default IP-address of the cards and the DSPs as
192.168.100.1.
Execute the command below:
# octSetup
The following message displays when executing octSetup for the first time and can be
ignored:
SELINUX: labeling directory /var/lib/tftpboot with tftpdir _rw_t
…libsemanage.dbase_llist_query: could not query record value (No
such file or directory).
2. Execute the below command (If you want to setup a different IP-address):
# octSetup --ipaddr=dd.dd.dd.dd
34
Configuring the IP-address:
The default format of <IP-address> is aa.bb.cc.dd. In that 'cc' denotes subnet value. Every
card in the system gets its own subnet. The subnet of each card differs with the other
based on their sequence of insertion.
The subnet changes based on the formula aa.bb.[cc+Card#).dd and
Card # denotes number of the card. By default, the first card takes the value as zero and it
increments by 1 for each card.
For example, assume that 192.168.100.1 is a sample IP-address. For the first card, the IP
address will be 192.168.[100+0].1 which is equal to 192.168.100. 1 and for the second
card it changes to 192.168.[100+1].1 that is equal to 192.168.101.1 and it increments
respectively based on the number of cards inserted.
The following message displays when executing octSetup for the first time and can be
ignored:
SELINUX: labeling directory /var/lib/tftpboot with tftpdir _rw_t
…libsemanage.dbase_llist_query: could not query record value (No
such file or directory).
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NOTE: Execute the above step1 or step2 only once. The configuration is persistent and is
retained after system reboot.
4.4.3 Starting the DSPs
After setting up the host, start the DSPs to load the image by executing the following
command:
# octService start all
The Octasic firmware images are stored at /var/lib/tftpboot/pcie8120 directory.
Now, the DSPs are taken out of reset. The DSP starts loading and executing the image. You can
check the tftpboot directory given above, to evaluate whether DSPs have successfully loaded
its image or not. The tftp load process is successful, if every DSP has stored its MAC addressspecific boot status file in tftpboot directory.
Also, the boot status file’s binary content can be analyzed to check error status, version
register, and progress counter. For more information, see Boot user guide listed in Table "Related
Specifications" on page 91.
Software Installation
Once the DSP firmware is loaded, you can execute the demo application.
4.5 Demo Application
Artesyn provides a demo application for PCIE-8120, setting up 400 IP to IP channels (800 IP end
points) per DSP, to transfer voice data from one DSP to another. The demo application monitors
all DSPs (one after the other) and evaluates its status by providing statistical data.
For more information with basic examples on configuring the DSPs with various codecs, refer
to Octasic SDK folder /opt/octasic/application/sample/octvoc.
Note: The demo is used to configure 12DSPs.
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Software Installation
4.5.1 Executing Demo
The demo is used to configure the maximum number of VOIP connections on the PCIE-8120.
For more information, see 12dsp_audio_transcode_net_api.c file at
/opt/octasic/application/sample/octvoc/12dsp_audio_transcode_net_a
pi/source location.
To start the demo, execute the following:
# cd
/opt/octasic/application/sample/octvoc/12dsp_audio_transocde_net_a
pi.
To execute the demo, find MAC-address of your local interface to the card. Determine the
network interface with the tool pcie8120-listdev. Associate the interface with device
function MSW (example output):
# pcie8120-listdev
PCIE-8120-A12/V12#0
MSW0: 05:00.0 eth6
CPLD0: 05:00.1 eth7
VSW0: 05:00.2 eth5
36
The MAC address of this network interface (here eth6) can be retrieved by executing the
command ifconfig:
# ifconfig eth6
eth6 Link encap:Ethernet HWaddr 00:80:42:2C:7B:D8
inet addr:192.168.101.1 Bcast:192.168.101.255
Mask:255.255.255.0
inet6 addr: fe80::280:42ff:fe2c:7bd8/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:2401552 errors:0 dropped:0 overruns:0 frame:0
TX packets:36880 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:725995492 (692.3 MiB) TX bytes:54316690 (51.8 MiB)
Start the demo with the MAC address retrieved above:
# ./12_dsp_audio_transcode_net_api 00:80:42:2C:7B:D8 1
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Software Installation
The first argument defines the MAC of the MSW network interface. The second argument
defines the number of iterations. In the example above, just one loop is executed. To run
continuously use -1 for the number of iterations:
# ./12_dsp_audio_transcode_net_api 00:80:42:2C:7B:D8 -1
The test passes, if all of the “Err”, “Drop”, “Slip” counters are zero. In this case the following
output is provided:
*** Loop: 0 ***
+-- VOC TERM MC STATISTICS (DSP 00) ----------------------
| RxOutPktCnt : 2457645
| RxInSidPktCnt : 0
| RxNoPktCnt : 2448744
| RxBadPktTypeCnt : 0
| RxBadRtpPayloadTypeCnt : 0
| RxBadPktHdrFormatCnt : 0
| RxBadPktLengthCnt : 0
| RxMisorderedPktCnt : 0
| RxLostPktCnt : 0
| RxBadPktChecksumCnt : 0
| RxUnderrunSlipCnt : 0
| RxOverrunSlipCnt : 0
| RxLastVocoderType : 0
| RxVocoderChangeCnt : 0
| RxMaxDetectedPdv : 173 (in 125 us)
| RxDecdrRate : 0
| RxMaxJitterCurrentDelay : 165 (in 125 us)
| RxJitterEstimatedDelay : 0 (in 125 us)
| RxJitterEstimatedDelay : 0 (in 125 us)
| RxJitterClkDriftingCorrectionCnt : 0
| RxMaxJitterInitializationCnt : 1
| RxCircularBufferWriteErrCnt : 0
| RxApiEventCnt : 0
| TxCurrentVocoderType : 0
| TxInPktCnt : 2456643
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Software Installation
| TxInBadPktPayloadCnt : 0
| TxTimestampGapCnt : 0
| TxTdmWriteErrCnt : 0
| RxToneDetectedCnt : 0
| RxToneRelayEventPktCnt : 0
| RxToneRelayUnsupportedCnt : 0
| TxToneRelayEventPktCnt : 0
| TxApiEventCnt : 0
| TxNoRtpEntryPktDropCnt : 0
| ConnectionWaitAckFlag : 0
| RxMipsProtectionDropCnt : 0
| TxMipsProtectionDropCnt : 0
| CallTimerMsec : 61665
NOTE: The loop counter increments, each time the DSP 00 displayed.
To know what happens if all of the “Err”, “Drop”, “Slip” counters are non-zero, see Appendix D,
Running Software, on page 88.
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Application Development Overview
5.1 Application Development
Applications make use of both the board services tools and the media processing APIs.
The board support tools are required to manage the setup and operation of the board,
including bringing DSPs out of reset.
The media processing application development software environment is provided by the
Octasic Vocallo MGW SDK package.
But during normal operation, it is also important to monitor the board temperature sensors
using the board support tools in case of problems with the airflow.
5.2 Application Development Tool Kit
Chapter 5
Artesyn provides all the Octasic information to enable you to commence application
development. The following is the information included in the application development tool
kit:
Octasic Documentation
Octasic VOCALLO API source files
Octasic basic examples
Precompiled DSP firmware image file
Vocallo MGW SDK to match firmware image
Artesyn Demo application configuring all 12 DSPs at PCIE-8120
PCIE-8120 configuration files (csv and octvocfs.tar)
DSP firmware creation tool executable
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Application Development Overview
Audio license file
Debug tools
OCTVOC2 is the internal name for OCT2224M DSP devices that are equipped with the PCIE8120 card.
Be aware that other software packages (OCTVOC=OCT 1010 DSP,
OCTVOC2_EB=OCT2224M Evaluation Board) should not be used with PCIE-8120.
For detailed documentation about the Octasic VOCALLO software, see readme.html file at
the /opt/octasic/doc location.
5.2.1 Octasic Linux Tools
40
Octasic provides tools for development and debugging. This tool package is provided for linux:
File name: octconsole, ethloopback_test
File location: /opt/octasic
Documentation from octasic is provided inside the tool folders.
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Application Development Overview
5.3 Octasic DSP Firmware image
Every Octasic DSP on the PCIE-8120 card loads the firmware code and it executes directly from
external DRAM. The firmware image is loaded in the following way:
Figure 5-1 Octasic Firmware Image
A sample DSP firmware image is provided for quick-start only. It has been built from the Octasic
source code delivered with the package octasic-sdk.
To get the latest version of the source code, code fixes, new codecs and appropriate license
files, contact octasic.
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Application Development Overview
Boot status can be read by evaluating the stage1 and stage2 specific boot process progress
counter, version register, error status and info field. DSP writes its boot status into
boot_status.<MAC-address> file located in the TFTP root directory (defaults are
/var/lib/tftpboot or /tftproot). This write operation occurs when either the
Stage2 process completes successfully (just prior to entering the application), or when an error
is encountered (just before the Stage 2 process halts). These registers are valid only during the
boot process.
The firmware image provided cannot be used with other revisions of Octasic VOCALLO APIs.
It includes an audio license only. You need to create new firmware images with every new
release or when changing pre-compiled options.
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Application Development Overview
5.3.1 Octasic DSP Firmware image creation
Octasic provides an image creation tool, that allows the user to specify configuration options
and the application object file to be included when creating the bootfile. The DSP firmware
image creation application is provided with the package:
File Name: oct2200_boot_img_gen
File Location: /opt/octasic/bin
Syntax: oct2200_boot_img_gen <input file> <output file>
Input file: simplified CSV description file created for PCIE-8120.
Output file: firmware image file created
Example: # cd /opt/octasic/hardware/octvoc2/oct2200/bootfile
# /opt/octasic/bin/oct2200_boot_img_gen
octvocmgw.citadelle.csv oct2200citadelle.img
Always use the octvocmgw.citadelle.csv file provided with the RPM, for creating DSP
images for PCIE-8120. To set up the card with its board-specific hardware
octvocmgw.citadelle.csv file is required.
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Application Development Overview
The following figure shows the files included in a firmware build and the files that should be
configured with reference to the application:
Figure 5-2 Files in firmware build
44
The input file octvocmgw.citadelle.csv includes a TAR file called octvocfs.tar. The
tar file contains two files:
license file (audio license) octvc1.lic.asc
hardware/application configuration file octvc1_config.arg
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Application Development Overview
The file octvc1_config.arg located in folder octvocmgw specifies the hardware specifics
of the PCIE-8120:
<EthernetPort PortNum="0">
<PortInterface Value="EMAC2"/>
<EthernetPort PortNum="1">
<PortInterface Value="EMAC0"/>
<TdmModule>
<TdmDisabledFrameSrcValue="0"/>
<FramePolarity Value=""/>
<FrameSamplingMode Value=""/>
<DataSamplingMode Value=""/>
<FromTdmTsstBufferSizeMs Value=""/>
<ToTdmTsstBufferSizeMs Value=""/>
<FromTdmBitOffset Value=""/>
<ToTdmBitOffset Value=""/>
<NumStream Value=""/>
<StreamFrequency Value=""/>
<Loopback Value=""/>
<TdmDataResolution Value=""/>
</TdmModule>
<CoreAllocation>
<TdmDriverEnable Value="0"/>
<lineEchoCancellerEnable Value="0"/>
</CoreAllocation>
<MaxNumBuffer Value="32"/>
There are configuration parameters that should be customized with respect to their
application. An example is given below:
<MaxNumTerm Value="800"/>
<MaxNumEchoTerm Value="400"/>
<MaxNumConferenceParticipants Value="128"/>
<MaxNumVideoRxQcif Value="32"/>
<MaxNumVideoRxCif Value="4"/>
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Application Development Overview
<MaxNumVideoRxSd Value="1"/>
<MaxNumVideoRx720p Value="0"/>
<MaxNumVideoRx1080p Value="0"/>
<MaxNumVideoBufferQcif Value="224"/>
1. octvc1._config.arg file is provided as an example for 12dsp audio application.
Align the resources of the DSP based on your application.
2. Also, keep the hardware-specific configuration parameters (port interface,
TdmModule) as specified in the RPM (see the first set of configuration parameters
above).
For details about how to set the configuration parameters, see Octasic documentation Vocallo
Media Gateway API Configuration Guide, and the octvoctn5009-sys_config.pdf file at
/opt/octasic/software/octvoc location.
For details about how to use the firmware image generator, see Octasic documentation and
the oct2200m_boot_image_gen.html file at
/opt/octasic/application/oct2200/oct2200_boot_img_gen location.
Once you have created a new firmware image you should copy it to the tftpboot folder. For
details about how to copy firmware image to the tftpboot folder, see Executing Demo on
page 36.
To load the new firmware image into the DSPs, you should execute:
# octservice stop all
# octservice start all
5.3.2 12xDSP Audio Transcode Demo
An example application in source code and as an executable for the reference platform is
provided in12dsp_audio_transcode_net_api at the
/opt/octasic/application/sample/octvoc/12dsp_audio_transcode_net_a
pi location.
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Application Development Overview
For details about how to use the demo, see README_max_channel_tests.txt file at the
/opt/octasic/application/sample/octvoc/12dsp_audio_transcode_net_a
pi location.
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Application Development Overview
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A PCIE-8120 External Connectors
A.1 Overview
This appendix describes the pin assignments and signals for the connectors on the PCIE-8120
card.
PCIE-8120 Card Edge Connector
J1/J2 External Ethernet Connector s/w status LEDs (not available on -N versions)
P2 External ATX 6-Pin Power Connector (only on -N versions)
Debug Connectors
P3 Fan Unit Connector (Optional component)
Appendix A
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PCIE-8120 External Connectors
The following figure shows the top and bottom layout of the PCIE-8120:
Figure A-1 PCIE-8120 Primary and Secondary Layout
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PCIE-8120 External Connectors
A.2 PCIE-8120 Card Edge Connector
The following table provides pin assignment for the PCIE-8120 card edge connector:
Table A-1 PCIE-8120 Card Edge Connector Pin out
Pin
#
1 +12V 12V power PRSNT1# Hot-Plug presence detect
2 +12V 12V power +12V 12V power
3 +12V 12V power +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus (System management
6 SMDAT SMBus (System management
7 GND Ground JTAG4 TDO (Test Data Output)
8 +3.3V 3.3V power JTAG5 TMS (Test Mode Select)
9 JTAG1 TRST# (Test Reset) resets the JTAG
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# Signal for Link reactivation PERST# Fundamental reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ Reference clock
14 PETp0 Transmitter differential pair,
15 PETn0 GND Ground
Side B
Name Description
Bus) clock
Bus) data
interface
Lane 0
Side A
Name Description
JTAG2 TCK (Test Clock), clock input for JTAG
interface
JTAG3 TDI (Test Data Input)
+3.3V 3.3V power
REFCLK-
(differential pair)
16 GND Ground PERp0 Receiver differential pair,
17 PRSNT2# Hot-Plug presence detect PERn0
18 GND Ground GND Ground
End of the x1 connector
PCIE-8120 Installation and Use (6806800R89C)
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PCIE-8120 External Connectors
Table A-1 PCIE-8120 Card Edge Connector Pin out (continued)
Pin
#
19 PETp1 Transmitter differential pair,
20 PETn1 GND Ground
21 GND Ground PERp1 Receiver differential pair,
22 GND Ground PERn1
23 PETp2 Transmitter differential pair,
24 PETn2 GND Ground
25 GND Ground PERp2 Receiver differential pair,
26 GND Ground PERn2
27 PETp3 Transmitter differential pair,
28 PETn3 GND Ground
29 GND Ground PERp3 Receiver differential pair,
30 RSVD Reserved PERn3
31 PRSNT2# Hot-Plug presence detect GND Ground
32 GND Ground RSVD Reserved
End of the x4 connector
Side B
Name Description
Lane 1
Lane 2
Lane 3
Side A
Name Description
RSVD Reserved
Lane 1
GND Ground
Lane 2
GND Ground
Lane 3
A.3 J1/J2 External Ethernet Connector s/w status
LEDs (not available on -N versions)
Two 10/100/1000BASE-T IEEE802.3 compliant Ethernet ports are available on the PCIE-8120
via RJ45 style connectors (except -N versions). They are provided through two Transceiver
devices (PHY) connected to the MSW:
LED0 : YELLOW: LINK
LED1 : GREEN : ACTIVE
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PCIE-8120 External Connectors
A.4 P2 External ATX 6-Pin Power Connector (only on
-N versions)
An ATX 6pin power connector is available at the P2 location for the NEBS optimized (-N)
variants of the PCIE-8120 card. As under NEBS exceptional operation conditions, the current
drawing from the slot connector could exceed the maximum allowed per pin current. The -N
variants receive 12V supply power exclusively from the P2 connector.
For more details on the P2 connector, see PCI Express x16 Graphics 150W-ATX Specification
document listed in Table "Related Specifications" on page 91.
Table A-2 ATX PWR Pinout
Pin No. Description
1
2 +12V
3 +12V
4 Ground
5 Sense
6 Ground
+12V
A.5 Debug Connectors
The PCIE-8120card is equipped with several debug ports. The debug ports allow
DSP/MFA,CPLD/FPGA programming, and JTAG/BSCAN functionality.
P4201 serial port MFA: RS232 style debug port for the MFA application.
P5001 OCT-SDBI2 debug port: The Octasic Pod requires an adapter cable for the micro-
header.
The connector style is a 16-pin, 1.27 mm pitch micro-header.
For more information, contact Artesyn and refer to part number 30NL9302D24.
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PCIE-8120 External Connectors
A.6 P3 Fan Unit Connector (Optional component)
The PCIE-8120 card supports a heat sink assembly that is equipped with a fan or blower unit. A
three pin header provides 12V supply for this purpose. An additional buffer circuitry allows for
PWM fan speed control via the CPLD.
Molex 3 pin header 53398-0371 “pico-blade” series.
12V /200mA max. PWM drive capability for a 2.4W class fan/blower unit or hi-impedance
2k/20k PWM control input.
Table A-3 Opt. fan unit connector Pinout
Pin-No. Description
1 12V main supply (1A max.)
2 FAN_PWM_CTRL (3.3V logic level PWM control or 12V/200mA PWM
driver)
3 GND main supply
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B PCIE-8120 Hardware Description
B.1 Overview
This section describes:
Block Diagrams for PCIE-8120
Card Reset Architecture
Power Supply Architecture
Card Clock Architecture
The main components of the PCIE-8120 are:
Ethernet NIC - i82580EB/DB
Ethernet Switch Unit
Media Flow Aggregator (MFA) Unit
Appendix B
Glue Logic - CPLD
DSP Array
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PCIE-8120 Hardware Description
B.2 Block Diagrams for PCIE-8120
The following figures provide an overview of the main function blocks of the PCIE-8120 and
how they are interconnected:
Figure B-1 Card Block Diagram PCIE-8120-A12/V12
56
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Figure B-2 Card Block Diagram PCIE-8120-A04
PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C)
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PCIE-8120 Hardware Description
Figure B-3 Card Block Diagram PCIE-8120-A12-N/V12-N
58
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B.3 Card Reset Architecture
PHY
88E1512
PCIe x4 card-edge connector
PHY
88E1512
PHY
88E1111
PHY
88E1111
12x DSPx-RST_N
PERST_N
PERST-82580_N
MSW-RST_N
VSW-RST_N
Hard/Auto
_N
The following figure provides an overview of the Card Reset Architecture of PCIE-8120:
Figure B-4 Card Reset Diagram
-RST
PCIE-8120 Hardware Description
MFA1-RST_N
2x ETH1/2-RST_N
MFA2-RST_N
All devices on the card that provide a dedicated reset input are connected to the CPLD to allow
for individual reset control at start up or during runtime via host control. The PERST_N signal is
propagated to the ethernet network devices (NIC, Switch, PHY) to make the card behave like a
standard NIC card. All other functions are kept in reset state and released only on S/W driver
activity to allow for correct set up before going active (i.e., Switch/PHY configuration, MFA
startup, DSP boot loading).
For additional information on CPLD, refer to Logic Design Specification PCIE-
8120.2012.1206874M02A listed in Table "Related Specifications" on page 91.
For timing requirements on PERST# signal, refer to PCI Express Card Electromechanical
Specification Rev.2.0.2007.PCISIG CEM 2.04/11/2007 listed in Table "Related Specifications"
on page 91.
PCIE-8120 Installation and Use (6806800R89C)
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PCIE-8120 Hardware Description
V1P0_DSP_A @ 30 A
DC
DC
V1P0_DSP_B @ 30 A
DC
DC
V1P5
DC
DC
V1P5_DSP_B
DC
DC
V1P2_DSP
DC
DC
V2P5_DSP
DC
DC
V3P3_DSP
DC
DC
12V main supply
12V
LDO
V1P8_ETH @ 0.1 A
5
PWRENABLE
5
3.3V
150W-ATX connector
Assembly
option
12V UVLO
VP12_FAIL
U/I/P-
Monitor
PVT_I2C_bus, ALERT_N
B.4 Power Supply Architecture
The following figure provides an overview of the Power Supply Architecture of PCIE-8120:
Figure B-5 Board Power Supply Architecture
PCIe x4 cardedge
PWRGOOD
_DSP_A @ 4.0 A
@ 4.0 A
@ 5.0 A
@ 4.0 A
@ 3.0 A
The PCIE-8120 uses seven DC/DC building blocks to provide the necessary operating voltages
that are required by the devices on the board.
Main voltage supply comes from the 12V card edge or ATX 6-Pin connector via the
assembly option. For more information, see P2 External ATX 6-Pin Power Connector (only on
-N versions) on page 53.
3.3V from card edge supplies power-up control circuitry.
3.3V aux is not used (no wake capability).
Current/voltage/power monitor, see I/V/P Sensors on page 72.
Card power management control by CPLD, see Card Power Management on page 68.
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PCIE-8120 Installation and Use (6806800R89C)
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According to the PCI Express Card Electromechanical Specification Rev.2.0.2007.PCISIG CEM
PCIe_x4
25.000MHz
PCIe_ RefCLK
100MHz
25.000MHz
20MHz
PHY
88E1512
PHY
88E1111
PHY
88E1512
PHY
88E1111
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
LVC x12 buffer
12
2.04/11/2007, the PERST# signal indicates a system power good status combined with a card
reset function. Therefore, it cannot be used as a power good signal to the cards power-up
control for the local DC/DC units. To keep up with the timing requirements for the PERST#
signal, the local power control must enable the DC/DC units immediately after card edge
power appears. An undervoltage-lockout circuitry is used to provide a status signal that
indicates when the 12V main supply is within the allowed range:
DC/DC enable for VP12 > 11.08V (calculated)
DC/DC disable for VP12 < 8.5V (calculated)
B.5 Card Clock Architecture
The following figure provides an overview of the Card Clock Architecture of PCIE-8120:
Figure B-6 Card Clock Scheme
PCIE-8120 Hardware Description
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PCIE-8120 Hardware Description
A synchronous clocking scheme is used for the DSP building blocks to allow for task distribution
over several DSPs. All other components have individual clocking sources.
Oscillators are EPSON SG-210 or equivalent types, +/-50ppm tolerance.
Resonators are EPSON FA238 or equivalent types, +/-23ppm tolerance.
Clock buffer device is TI CDCLVC1112.
B.6 Ethernet NIC - i82580EB/DB
The PCIE-8120 uses an Intel 82580EB/DB Gigabit Ethernet Controller to implement PCI Express
connectivity and thereby provides access for the Host system towards the card's resources.
This device supports up to four Ethernet ports with integrated MAC units and SGMII/SerDes
interface. The ports are connected to the Ethernet switch unit on the card. Also, see Ethernet
Port Mappings on page 63.The host interface supports a PCI Express v2.0 x4, x2, x1 link with
5Gbps and 2.5Gbps operation.
B.6.1 NV-Memory-NIC Configuration
The PCIE-8120 card stores configuration data for the Intel i82580EB/DB device on a local
EEPROM device. The configuration data for individual variants is according to port mapping.
See, Ethernet Port Mappings on page 63.
MAC Addresses: factory programmed.
Subsystem Vendor ID set to 0X1223 for Artesyn.
Subsystem ID set to 0x0016.
B.7 Ethernet Switch Unit
Based on the variant, PCIE-8120 uses one or two 16-Port SerDes Gigabit Ethernet switch
devices to allow full bandwidth connectivity between all onboard resources.
Broadcom BCM5396 device, 256-Pin FBGA package.
16 port 10/100/1000Mbps integrated switch controller.
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PCIE-8120 Hardware Description
B.7.1 Main Switch Unit (MSW) - BCM5396
The main switch unit (MSW) is available on all versions of the PCIE-8120 card and provides the
basic connection between all DSP, NIC, MFA, and external Ethernet resources.
B.7.2 Video Switch Unit (VSW) - BCM5396
The Video Switch Unit (VSW) is available on variants that provide additional network
connection between DSP, NIC, MFA, and external Ethernet resources. The main task of the VSW
is to connect the second Ethernet port of the DSP units to the switch fabric.
B.7.3 Ethernet Port Mappings
The following figures show the port mappings of the Ethernet fabric on the individual variants
of the PCIE-8120 card:
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PCIE-8120 Hardware Description
MainSwitch
port
numbers
#1
#2
#0#1#2
#3
Figure B-7 Port Mapping PCIE-8120-A12/V12
DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP09 DSP10 DSP11
#2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3
DSPETHport numbers
64
#4 #12 #10 #11 #1 #14 #8 #13 #15 #16 #3 #5 #7#9 #2 #6
0189
0:PHYH/WAddress
RJ45
#1
RJ45
Frontpanel ETH
PHYs
#11 #10 #7 #6 #14 #12 #4 #5 #16 #1 #2 #3#8 #9 #15#13
MFA
#2
NIC
ETHcontroller port numbers
MFA/PHYports
PCIE-8120 Installation and Use (6806800R89C)
VideoSwitch port numbers
Page 65
Figure B-8 Port Mapping PCIE-8120-A04
#2#3#2#3#2#3#2#3#2#3#2#3#2#3#2#3#2#3#2
#3
#1#2#0
#1#2#3
MainSwitch
port
numbers
#
#
#0##
#3
DSPETHport numbers
PCIE-8120 Hardware Description
DSP0
#4 #12 #10 #11 #1 #14 #8 #13 #15 #16 #3 #5 #7#9 #2 #6
DSP1
DSP2
DSP3
DSP4
0157
0:PHYH/WAddress
RJ45
#1
RJ45
Frontpanel ETH
PHYs
DSP5
#2
DSP6
MFA
MFA/PHYports
DSP7
DSP8
NIC
DSP09
ETHcontroller port numbers
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PCIE-8120 Hardware Description
MainSwitch
port
numbers
#1
#0#1#2
#3
Figure B-9 Port Mapping PCIE-8120-A12-N/V12-N
DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP09 DSP10 DSP11
#2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3 #2 #3
DSPETHport numbers
#4 #12 #10 #11 #1 #14 #8 #13 #15 #16 #3 #5 #7#9 #2 #6
SGMII
SFF8087
RJ45
#1
#11 #10 #7 #6 #14 #12 #4 #5 #16 #1 #2 #3#8 #9 #15#13
VideoSwitch port numbers
MFA
RJ45
#2
NIC
ETHcontroller port numbers
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PCIE-8120 Hardware Description
B.8 Media Flow Aggregator (MFA) Unit
The PCIE-8120 is optionally equipped with an Octasic OCT1503 MFA FPGA. The purpose of the
device is to aggregate an array of Ethernet devices (i.e., the OCT2224 DSP array) to form a
single logical node. For more information on Octasic OCT1503 MFA FPGA, see OCT1503 MFA
FPGA Specifications. 2012. OCT1503DS9000 listed in
The MFA provides following features:
FPGA design based on Altera EP3C25F256 device (Cyclone III Family).
Field update programming through ethernet API.
Interfaces: 2x GMII via MFA PHY 1&2 connected to VSW (default) or MSW based on
assembly option
– Interface MFA#1 used as device port (DSP side).
– Interface MFA#2 used as aggregated port (Network & control processor).
Table "Related Specifications" on page 91.
Serial debug port option (RS232) via 3-Pin header P4201.
B.9 Glue Logic - CPLD
The PCIE-8120 card is equipped with a CPLD to support additional functionality that is required
by the design but not provided by the main components selected for the card. The functional
details are as follows:
Lattice MachXO2-1200U, -4 device, 256-Ball caBGA.
Single 3.3V supply from card edge connector.
Internal 20MHz clock and power-up watchdog.
Internal UFM stores H/W settings and product-specific information.
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PCIE-8120 Hardware Description
Optional external Flash for persistent storage of user configuration data
– AT25256 device, 256kbits density, 8S1 SOIC package.
B.9.1 Card Power Management
The CPLD on the PCIE-8120 fulfills the functionality of a power management controller for the
card. The power-up and power-down control is based on the input signals.
Internal power good status, that is, 3.3V from PCIE slot is present and the device has
started properly.
VP12_FAIL signal indicating when the 12V main supply is not within the allowed range.
PERST# signal from PCIE connector indicating the system preparing to go into operation
or leaving operational mode.
VPx_PWRGD status signals of the on board DC/DC units.
Based on the status of the input signals, the following control signals display output:
VPx_PWREN enables/disables the DC/DC units according to power-up/down timing
sequence requirements.
– Default power-up/down sequence is simultaneous.
PWRDN_VP discharges the residual voltage levels after powering off the DC/DC units.
B.9.2 Interfaces and S/W control
B.9.2.1 MDIO
The MDIO[1] channel from the second SerDes port of the NIC is connected to the CPLD for
basic S/W access via mapped pseudo-PHY registers. A card specific enhanced network card
driver is necessary to make use of the functionality that is provided through the CPLD. For more
information on interfaces and S/W control, see PCIE-8120 Software Package on page 32.
B.9.2.2 Card Variant MOD_ID
The card provides a 4-bit wide H/W strapped ID (MOD_ID<3..0>). It is used to identify the
variant of the card. Based on the variant, some settings in the CPLD are different or specific
registers are not available.
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The OS device driver or user mode S/W can make use of the MOD_ID to make user specific
settings or specific functions available for the respective card.
Table B-1 Card Variant MOD_ID
Order Number MOD_ID<3...0>
PCIE-8120-A12 0111
PCIE-8120-V12 0111
PCIE-8120-A04 0100
PCIE-8120-V04 0100
PCIE-8120-A12-N 1000
PCIE-8120-V12-N 1000
B.9.2.3 Card BASE_ID
PCIE-8120 Hardware Description
The Card provides a 4-bit address register for the DSP array (BASE_ID<3...0>). It is used to
differentiate multiple cards within a system from S/W point of view. It can be used to store the
IP address range of a card in the UFM or to reconfigure an exchanged card to respond to the
same IP address range than the original card.
The default value for BASE_ID<3..0> is 0b1111.
B.9.2.4 Opus Debug Port Multiplexer
The CPLD contains multiplex logic to select an individual DSP unit for debugging. The signals
from the OCT-SBDI2 Pod connection header are routed to the CPLD and the CPLD has a set of
SBDI output signals to every of the twelve DSP units. For more information on how to set up
OCT-SBDI2 debug connection, refer to OCT2200UG8002 user guide listed in Table "Related
Specifications" on page 91. Also, refer to OPUS Debug Port on page 79.
B.9.2.5 SMBus and PVT_I2C Bus
The PCIE-8120 card provides connectivity to the PCI Express connector SMBus. Additionally, a
private I2C bus (PVT_I2C) is available that accesses the onboard sensor devices. Both are
connected to the CPLD to allow access to the sensor information via SMBus or through the Host
system via MDIO.
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PCIE-8120 Hardware Description
PCIe_x4
I2c Temp
sensor#1
I2c I/V/P
sensor
ID PROM
ADT7461
SMBus
PVT_I2C_bus
PCIe
MDIO#1
0x90 : inlet temp
0x92: outlet temp
0x88
0xA0
Temp_INT
Alert_INT
I2c Temp
sensor#2
The CPLD is connected as a slave device on the PCI Express SMBus.
Figure B-10 SMBus and PVT_I2C bus connection diagram
70
ID PROM (Optional)
A serial EEPROM is available on the PVT_I2C bus for the purpose of storing manufacturer or user
data specific to the card. This ID PROM device is optional and may not be present on specific
variants of the card.
M24C04 Device
4 kbits density
I2C address: 0xA0
Temperature Sensors
There are two temperature sensors on the PVT_I2C bus for monitoring the temperature on the
card and the thermal behavior of the system. One sensor is placed on the mounting bracket
side which is considered as the air outlet side. The other sensor is placed on the card retainer
side which is considered as the air inlet side (see Figure "Temperature Sensor Location" on page
72.)
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PCIE-8120 Hardware Description
These sensors measure the PCB component temperature, which allows to determine the
absolute and the delta temperature level on the card. A possible sensor fault or a cooling
system degradation can also be indicated.
The PCB component temperature may not be very closely correlated to the system or card
ambient temperature as specified in Table 3-1 on page 27.
The PCB component temperature is largely dependent on specific mechanical and thermal
conditions in the respective server where the card is installed. See, Sensor Alert Default Values
on page 73.
Sensor type is a LM75 Device.
I2C address: 0x90 for air inlet temperature sensor.
I2C address: 0x92 for air outlet temperature sensor.
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PCIE-8120 Hardware Description
An additional temperature sensor is available at the SMBus in conjunction with the NIC device.
It allows monitoring the temperature of the device.
ADT7461 Device
SMB address 0x4C
Figure B-11 Temperature Sensor Location
72
I/V/P Sensors
A current and power monitor device is available on the PVT_I2C bus for surveillance purpose. It
allows to sense the 12V bus power and can be used to control the card’s power consumption
or provide alerts about over-current or under-voltage that can be handled via the CPLD
interface.
INA226 Device
I2C address: 0x88
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PCIE-8120 Hardware Description
Programmable alerts for
–Power
–Current
– Voltage
Alert_INT to CPLD
Check the power consumption of the card with the command. An example is given below:
# PCIE-8120-read-sensor
PCIE-8120#0:
t_inlet: 31°C
t_outlet: 32.5°C
ivp_volt: 11.9425V
ivp_curr: 1.84125A
ivp_powr: 17.575W
Sensor Alert Default Values
Until the card is fully characterized in a reference system environment, system integrators can
use values to set up sensor alarms.
It is proposed to use a smart sensor algorithm that collects data from the sensors, verifies
readings and calculates history, acts quickly on critical levels, and still does not overload the low
bandwidth of the interface. It should be noted that these types of sensors are not useful for
transient alarms. For example short voltage dips or current peaks. A three-level approach to
sensor alarms seems appropriate with the following strategy:
Minor: Readings in this range should be tracked (response time: minutes)
Major: Actions to reduce load should be taken/requested (response time: less than a
minute)
Critical: Emergency shutdown/store event to NVRAM (response time: few seconds)
Following are the values to set up sensor alarms:
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PCIE-8120 Hardware Description
Table B-2 Sensor alert default values
Sensor type Minor Major Critical
Inlet Temp >50°C >55°C >60°C
Outlet Temp >55°C >70°C >80°C ***
Delta Temp <5°C * >15°C > 0°C
Card Power 12 OCT 60W@12V 65W@12V 70W@12V
Supply Bus voltage < 11.5V < 10 V < 9V
Supply Bus current 4 OCT 1.8A ** 2.1A ** 2.5A **
Supply Bus current 12 OCT >5 Amp >6.5 Amp >7 Amp
Card Power 4 OCT 22W@12V 26W@12V 30W@12V
Card Power 12 OCT -N**** 60W@12V 78W@12V 84W@12V
* A low delta temperature reflects poor system cooling capability.
** It is not recommended to use current readings for alarms as they depend on varying
voltage. Use card power readings instead.
*** The PCIE-8120 temperature sensors are pre-configured to shutdown the card when
either sensors reach 80 °C. The system can restart when the temperature falls below 75 °C.
**** The higher sensor readings for -N version reflect exceptional operating conditions per
NEBS requirement.
B.9.2.6 Debug LED
The card provides 8 Debug LEDs to the CPLD to indicate the power-up status and generic fault
conditions. The LEDs 0-7 are located on the top component side of the card near the PCI
Express connector, oriented from left to right. In default run state, all LED are off. For LED error
codes see the table below:
Table B-3 LED Error Code
210
Off Off Off Enable state-12V stable
LED NUMBER
DESCRIPTION
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Table B-3 LED Error Code
PCIE-8120 Hardware Description
LED NUMBER
210
Off Off On Enable state-Onboard converters
enabled
Off On Off Wait state-Power good status
Off On On Wait state-Power-up sequencing
On Off Off Power good status and PERST_N
deasserted
On Off On N/A (shutdown)
DESCRIPTION
Table B-4 LED Error code
LED NUMBER
7654 3
Off Off Off Off Off No Error
Off Off Off Off On 12V Failed
Off Off Off On Off 3.3V Failed
Off Off Off On On 2.5V Failed
X X On Off Off 1.5V Failed (additional 1.2V
DESCRIPTION
or 1.0V)
X On X Off Off 1.2V Failed (additional 1.5V
On X X Off Off 1.0V Failed (additional 1.5V
Off Off On Off On PERST_N deasserted before
Off On Off Off On Not all power good status
PCIE-8120 Installation and Use (6806800R89C)
or 1.0V)
or 1.2V)
power good status
within time-out
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PCIE-8120 Hardware Description
B.9.3 CPLD Upgrade
The CPLD offers a functionality to reprogram its configuration data under host software
control. The procedure is not FAIL-SAFE status. This means if a reprogramming procedure fails,
the whole card becomes unusable and needs to be reprogrammed via H/W (download cable).
B.10 DSP Array
The PCIE-8120 DSP Array can be populated with up to 12 instances of Octasic's DSP OCT2224M
System-On-Chip device, which is specialized for media gateway applications. For more
information on the Octasic DSP OCT2224M, refer to the OCT2200M Hardware Specification listed
in Table "Related Specifications" on page 91.
The following sections describe specific aspects of the PCIE-8120 design:
B.10.1 DSP Overview
The Octasic OCT2224M DSP is part of the OCT2200 series of devices which is a family of Digital
Signal Processors (DSP) based on the Opus 2 architecture developed by Octasic. It is targeting
voice and video applications for telephony infrastructure applications.
The OCT2224M is composed of five major subsystems:
The Opus2 DSP subsystem
The DDR Memory Subsystem
The High-speed I/O Subsystem (Ethernet MAC Engines)
The Resources Subsystem (GPIO)
The Maintenance Subsystem (Boot Controller)
The main features of the OCT2224M are:
24 Opus2 cores with 144k bytes of L1 memory per core
C programmable DSP
484-Pin BGA 1.0mm pitch
4W typical power consumption
Secure custom booting capability
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Precision clock synchronization on external references
Various Peripheral Interfaces Ethernet, serial/parallel hi-speed interfaces, TDM, Flash, and
so on. For details, see document OCT2200MDS8000 listed in Table "Related Specifications"
on page 91.
B.10.2 DDR3 Memory Subsystem
The 32-bit DDR memory controller is used for interface to JEDEC DDR3 SDRAM devices. The
interface supports 4.32 GB/s at a 1080 MHz data rate (540 MHz clock rate).
The DSP memory on the PCIE-8120 is realized with two DDR3 x16 devices per DSP. The
memory access is 32-bits wide.
The default memory size is 512 MByte.
The DDR3 memory is not used until the DDR configuration is obtained from the boot image.
PCIE-8120 Hardware Description
B.10.3 Ethernet MAC Engines
The OCT2224M device on the PCIE-8120 card configures two Ethernet MAC engines,
supporting 10/100/1000-Mbps data transfer rates on the physical interfaces: SERDES2 and
SERDES3 in SGMII mode. See Table B-5 below.
EMAC0 and EMAC2 support jumbo packets (maximum size of 9,018 bytes or 9,022 bytes for
VLAN frames). EMAC2 is available for BOOTP.
Table B-5 Ethernet Physical Interface Mapping
Mode SERDES0 SERDES1 SERDES2 SERDES3 Eth0 Eth1
5 EMAC 1 (not used) EMAC 3 (not used) EMAC 2 EMAC 0 n/a n/a
B.10.4 Boot Controller
The boot controller is responsible for managing the boot process. The boot process loads a
boot image that is created by an Octasic software tool that allows the user to specify optional
device configuration and the application image to load.
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PCIE-8120 Hardware Description
The boot process uses a default device configuration determined by either a lowest common
capability and/or the BOOT_MODE to load a boot image. The final device configuration
information is obtained from the boot image and can override the one used for the boot
process.
The PCIE-8120 card is configured for BOOTP on EMAC 2 on SERDES 2 (SGMII, 1Gbps).
B.10.5 DSP Configuration
The following table lists the assignment of the DSP control and configuration pins:
Table B-6 DSP Control Signals
Signal Group Controlled by Description
DSPx_RST_N CPLD Reset input to each DSP
DSPx_INT_N CPLD Interrupt output from each DSP
DSPx_USER_HW_CONF[
3:0]
DSPx_USER_HW_CONF[
7:4]
DSPx_USER_HW_CONF[
13:8]
HW Strapping DSP position on Mezzanine set by strapping
resistors range 0 - 11
0000 = DSP0
0001 = DSP1
0010 = DSP2
0011 = DSP3
0100 = DSP4
0101 = DSP5
0110 = DSP6
0111 = DSP7
1000 = DSP8
1001 = DSP9
1010 = DSP10
1011 = DSP11
BASE_ID[3:0] A card specific 4bit Base ID can be
programmed via the CPLD
HW Strapping Strapped by resistor to 1
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PCIE-8120 Hardware Description
Table B-6 DSP Control Signals (continued)
Signal Group Controlled by Description
DSPx_USER_HW_CONF[
14]
CPLD 0 = Unique factory-burned per-chip MAC
address
1 = TFTP server with IP derived from
00:0C:90:02:<USER_HW_CONFIG>xx
DSPx_USER_HW_CONF[
15]
BOOT_MODE[3:0] HW Strapping Strapped by resistor to
CPLD 0 = TFTP server at 192.168.1.200
B.10.6 DSP 25MHz Clock Synchronization
The PCIE-8120 card provides clock synchronization for the entire DSP array to ensure equal
processing time on computing tasks that are shared between two or more DSP units. The
synchronized main DSP operating clock is 25.00 MHz.
B.10.7 OPUS Debug Port
A debug port is available for low level debugging of individual DSP units via the vendor specific
Opus Studio development suite.
Opus debug port via connector P5001
16-Pin 1,27mm pitch micro header
DSP debug port selection via CPLD.
1 = TFTP server with IP derived from
192.168.<USER_HW_CONFIG>xx
0100 = BOOTP on EMAC 2 on SERDES 2
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PCIE-8120 Hardware Description
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C Known Issues
C.1 OctSetup Known Issues
1. When starting octSetup for the first time you might observe the following message:
SELINUX: labeling directory /var/lib/tftpboot with tftpdir _rw_t
…libsemanage.dbase_llist_query: could not query record value (No
such file or directory)
This message can be ignored. It has no impact on the correct functionality of octSetup.
This is a known issue of the tool semanage, which is called by octSetup.
2. When executing octSetup the following messages are displayed:
Note: optional package xxx not installed
This message is a hint and can be ignored as long as you plan only to start the demo. If
you plan to do some development for the DSPs, you should consider to install the
optional package indicated by the message.
Appendix C
Error: mandatory package xxx not installed
If you get this message then you should install the missing package and execute
octSetup again. Install a missing package with:
# yum install xxx
C.2 DSP Known Issues
1. When there is no connection between host and DSP, the following error is displayed
instead of the error statistics.
Error:
cOCTVC1_VSPMP_VOC_MSG_MODULE_GET_CONFIG failed, rc = 0x0a0a0003
(cOCTVC1_PKT_API_RC_TIMEOUT)
ulNumConnections out of range : 0
2. If every DSP displays
ulNumConnections out of range : 0
Check that the Artesyn Licence file is included.
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Known Issues
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D Miscellaneous
D.1 OctSetup: Internal Behavior
OctSetup sets up the host for the demo. The following figure explains the network set-up of the
host:
Figure D-1 Host Network Set up
Appendix D
At boot time, the numbering of the network devices of the card is completed. This
numbering is arbitrary and differs from system to system. Use ethx, ethy and ethz as
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Miscellaneous
placeholders in the above example set up.
No network device is connected to ethy. The pseudo-device ethy is only to access the
CPLD. Avoid finding a link at this device and configuring an IP-address used to access.
It is not required to define IP-address for the network devices ethx and ethz. The DSPs
use a MAC-based protocol and not an IP-based protocol. However, you can identify the
MAC-address of the network device and configure the IP-address for these devices.
The default VLAN ID of the DSP ports at MSW is 999. It indicates that the switch adds the
VLAN tag with ID 999 for every untagged packet received at a port.
Be aware that when you develop an application running on the DSPs, either define your own
VLAN for your application packets or remove or disable VLAN 999 after the DSPs has loaded
its firmware image. You can select any other ID except zero to develop the application after
the DSPs have loaded their firmware images.
84
When the DSP requests an IP-address from the DHCP server, the server selects an arbitrary
IP-address from the range 192.168.100.[10-21]. There is no fixed relation between
IP-address and DSP number. Additionally, there is no need to prefer this particular subnet
192.168.100.0., you can select any subnet.
If a second card provided in the system, the subnet for that card is 192.168.101.0. The
system that octSetup uses is 192.168.[100 + card#].0. You can select any system
or subnet.
The configuration files for the DHCP server are in the /opt/bladeservices/etc
directory. The DHCP configuration file name is pdevn-dhcpd.conf.
The switch VSW is used for internal data/packet exchange between the DSPs.
Place the DSP firmware images in the root directory of the TFTP server (or a subdirectory
of TFTP server). The default is /var/lib/tftpboot directory.
OctSetup creates pcie1820/pdevn directories in the TFTP root directory. Where ‘n’ is
the PCI-bus number of the card. Therefore, find a pdevn directory for every card in the
host. For information on how to find PCI-bus number, see section Identifying the Card at PCI-
Bus on page 85.
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octSetup creates links for the boot files of the DSPs in the pdevn directories. The
identification is oct2200.0 for DSP0 of the card, oct2200.1 for DSP1 of the card and so
on. These boot files are links to firmware image that should be loaded to the respective
DSP. You can change the links to point to different boot files. Similarly, you can load an
individual firmware image into every DSP. The identification system is set up in the
configuration files of the DHCP server pdevn-dhcpd.conf in
/opt/bladeservices/etc.
If you have to reload firmware image, first put DSP in reset and then take it out of reset
again. The DSP starts to load a firmware image. Use the octmezz tool with --
dspctrl=[up|down] option to perform these steps.
D.2 Identifying the Card at PCI-Bus
Use pcie8120-listdev tool to identify all cards in the system at PCI-bus.
Below is the sample output:
Miscellaneous
# pcie8120-listdev
PCIE-8120-A12/V12#0
MSW0: 01:00.0 eth29
CPLD0: 01:00.1 eth31
VSW0: 01:00.2 eth30
PCIE-8120-A12/V12#1
MSW1: 05:00.0 eth6
CPLD1: 05:00.1 eth7
VSW1: 05:00.2 eth5
The second column shows the PCI-device of the function of a card. For example, MSW0 is at
01:00.0, which is bus 1, slot 0, function 0. You can identify this in the output of the tool lspci
# lspci
00:00.0 Host bridge: Intel Corporation 2nd Generation Core Processor
Family DRAM Controller (rev 09)
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Miscellaneous
…
01:00.0 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
01:00.1 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
01:00.2 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
…
05:00.0 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
05:00.1 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
05:00.2 Ethernet controller: Intel Corporation 82580 Gigabit
Backplane Connection (rev 01)
...
D.3 Serial Number of the card
Use the pcie8120-serialno tool to determine the serial number of all cards installed in the
system.
The sample output below shows that the serial number of the cards zero and one:
# pcie8120-serialno
PCIE-8120#0: 6010687046XX
PCIE-8120#1: 601068703YXX
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D.4 12xDSP Audio Transcode Voip Channel Demo
Application
The following is the additional information available in
README_max_channel_tests.txt file at
/opt/octasic/application/sample/octvoc/12dsp_audio_transcode_net_a
pi location.
D.4.1 Introduction
Figure D-2 Block Diagram
12dsp_audio_transcode_net_api - sets up to 400 IP to IP channels (800 IP end points)
per DSP. The main purpose of this software is to load the DSPs with maximum IP to IP channels
so that the test is set in pairs of physical DSPs.
This software code assumes that there are 12 DSPs available and that the code is running on
the Xeon server host with RHEL, though it should run on other hosts.
NOTE: Main change is to change the data structures to large arrays.
Some functions are copied from existing sample files and are named as MyXXXXXXX, whereas
XXXXXX is the original function name.
DSP IP Addresses are controlled by these #defines
#define DSP_IP_BASE 0xC0A84C00
#define DSP_IP_START 201
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#define DSP_IP_FINISH (DSP_IP_START+MAX_DSPS-1)
So, with current settings these IP addresses are used:
DSP0 IP : 192.168.76.201
DSP11 IP : 192.168.76.212
D.4.2 Requirements
The following requirements must be fulfilled to enable the demo application to run:
This demo application is compiled with Octasic SDK version 1.9.3.
The DSP image must have the Artesyn specific license file included. This means the DSPs must
be out of reset and the image downloaded via TFTP.
The IP address is not important, as the software uses raw sockets to communicate with the
DSPs.
Miscellaneous
D.4.3 Running Software
New features
If any of these counters are non-zero a warning will be displayed at the end of each out
DSPs statistics list.
ulRxBadPktTypeCnt
ulRxBadRtpPayloadTypeCnt
ulRxBadPktHdrFormatCnt
ulRxBadPktLengthCnt
ulRxMisorderedPktCnt
ulRxLostPktCnt
ulRxBadPktChecksumCnt
ulRxUnderrunSlipCnt
ulRxOverrunSlipCnt
ulRxVocoderChangeCnt
ulRxCircularBufferWriteErrCnt
ulRxApiEventCnt
ulTxInBadPktPayloadCnt
ulTxTimestampGapCnt
ulTxTdmWriteErrCnt
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Miscellaneous
ulRxToneDetectedCnt
ulRxToneRelayEventPktCnt
ulRxToneRelayUnsupportedCnt
ulTxToneRelayEventPktCnt
ulTxApiEventCnt
ulTxNoRtpEntryPktDropCnt
ulConnectionWaitAckFlag
ulRxMipsProtectionDropCnt
ulTxMipsProtectionDropCnt
The output below are the results when error detected:
+-- VOC TERM MC STATISTICS (DSP 03) ---------------------| RxOutPktCnt : 125190214
| RxInSidPktCnt : 0
| RxNoPktCnt : 1236800
| RxBadPktTypeCnt : 0
| RxBadRtpPayloadTypeCnt : 0
| RxBadPktHdrFormatCnt : 0
| RxBadPktLengthCnt : 0
| RxMisorderedPktCnt : 800
| RxLostPktCnt : 116800
| RxBadPktChecksumCnt : 0
| RxUnderrunSlipCnt : 0
| RxOverrunSlipCnt : 0
| RxLastVocoderType : 0
| RxVocoderChangeCnt : 0
| RxMaxDetectedPdv : 161 (in 125 us)
| RxDecdrRate : 0
| RxMaxJitterCurrentDelay : 162 (in 125 us)
| RxJitterEstimatedDelay : 0 (in 125 us)
| RxJitterEstimatedDelay : 0 (in 125 us)
| RxJitterClkDriftingCorrectionCnt : 0
| RxMaxJitterInitializationCnt : 1
| RxCircularBufferWriteErrCnt : 0
| RxApiEventCnt : 0
| TxCurrentVocoderType : 0
| TxInPktCnt : 125189952
| TxInBadPktPayloadCnt : 0
| TxTimestampGapCnt : 0
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| TxTdmWriteErrCnt : 0
| RxToneDetectedCnt : 0
| RxToneRelayEventPktCnt : 0
| RxToneRelayUnsupportedCnt : 0
| TxToneRelayEventPktCnt : 0
| TxApiEventCnt : 0
| TxNoRtpEntryPktDropCnt : 0
| ConnectionWaitAckFlag : 0
| RxMipsProtectionDropCnt : 0
| TxMipsProtectionDropCnt : 0
| CallTimerMsec : 3130006
Note: Above mentioned are DSP 03 observed Errors.
Miscellaneous
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Appendix E
E Related Documentation
E.1 Artesyn Embedded Technologies - Embedded
Computing Documentation
The publications listed below are referenced in this manual. You can obtain electronic copies of
Artesyn Embedded Technologies - Embedded Computing publications by contacting your
local Artesyn sales office. For released products, you can also visit our Web site for the latest
copies of our product documentation.
1. Go to www.artesyn.com/computing.
2. Under SUPPORT, click TECHNICAL DOCUMENTATION.
3. Under FILTER OPTIONS, click the Document types drop-down list box to select the type of
document you are looking for.
4. In the Search text box, type the product name and click GO.
Table E-1 Artesyn Embedded Technologies - Embedded Computing Publications
Organization Document Title
Artesyn Embedded Technologies PCIE-8120 Data Sheet
E.2 Related Specifications
For additional information, refer to the following table for related specifications. As an
additional help, a source for the listed document is provided. Please note that, while these
sources have been verified, the information is subject to change without notice.
Table E-2 Related Specifications
Organization Document Title
PCI Special Interest Group
(PCI SIG) Specifications
PCI Express Card Electromechanical Specification Rev.2.0.2007.PCISIG CEM
2.04/11/2007
PCI Express Base Specification Rev.2.0
PCI Express x16 Graphics 150W-ATX Specification
PCIE-8120 Software Package
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Related Documentation
Table E-2 Related Specifications (continued)
Organization Document Title
Octasic OCT1503 MFA FPGA Specifications. 2012. OCT1503DS9000
OCT2200M Hardware Specifications. 2012. OCT2200MDS8000
Octasic system BDI pod (OCT-SBDI2) OCT2200UG8002 User Guide
Vocallo Media Gateway API configuration Guide
Octasic Software Package document
Boot user guide
Vocallo Media Gateway Software Architecture Overview document
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Safety Notes
This section provides warnings that precede potentially dangerous procedures throughout
this manual. Instructions contained in the warnings must be followed during all phases of
operation, service, and repair of this equipment. You should also employ all other safety
precautions necessary for the operation of the equipment in your operating environment.
Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
Artesyn intends to provide all necessary information to install and handle the product in this
manual. Because of the complexity of this product and its various uses, we do not guarantee
that the given information is complete. If you need additional information, ask your Artesyn
representative.
The product has been designed to meet the standard industrial safety requirements. It must
not be used except in its specific area of office telecommunication industry and industrial
control.
Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering
are authorized to install, remove or maintain the product.
The information given in this manual is meant to complete the knowledge of a specialist and
must not be used as replacement for qualified personnel.
Keep away from live circuits inside the equipment. Operating personnel must not remove
equipment covers. Only factory authorized service personnel or other qualified service
personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment.
Do not install substitute parts or perform any unauthorized modification of the equipment or
the warranty may be voided. Contact your local Artesyn representative for service and repair
to make sure that all safety features are maintained.
EMC
This equipment has been tested and found to comply with the limits for a Class A digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if
not installed and used in accordance with the instruction manual, may cause harmful
interference to radio communications.
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Safety Notes
Operation of this equipment in a residential area is likely to cause harmful interference in which
case the user will be required to correct the interference at his own expense. Changes or
modifications not expressly approved by Artesyn Embedded Communications Computing
could void the user's authority to operate the equipment. Board products are tested in a
representative system to show compliance with the above mentioned requirements. A proper
installation in a compliant system will maintain the required performance. Use only shielded
cables when connecting peripherals to assure that appropriate radio frequency emissions
compliance is maintained.
Operation
Product Damage
Surface of the Product
High humidity and condensation on the product surface causes short circuits.
Do not operate the product outside the specified environmental limits. Make sure the product
is completely dry and there is no moisture on any surface before applying power.
Overheating and Product Damage
Operating the product without forced air cooling may lead to overheating and thus damage of
the product.
When operating the product, make sure that forced air cooling is available in the enclosure.
Data Corruption
If power to the unit is removed while a firmware update is in progress to the card flash memory,
the changes will not be saved, and worse, the flash memory may be corrupted. In such case the
card is likely to remain in non-operable state and will require reconditioning by qualified repair
services.
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Installation
Damage of Circuits
Electrostatic discharge and incorrect installation and removal of the product can damage
circuits or shorten their life.
Before touching the product or electronic components, make sure that your are working in an
ESD-safe environment.
Product Damage
Incorrect installation of the product can cause damage of the product.
Only use appropriate tools when installing/removing the product to avoid
damage/deformation to the card and/or PCB.
Safety Notes
Cabling and Connectors
Product Damage
The RJ-45 connector(s) on the card are twisted-pair Ethernet (TPE) or interfaces. Connecting
an E1/T1/J1 line to an Ethernet connector may damage the product.
Make sure that TPE connectors near your working area are clearly marked as network
connectors.
Verify that the length of an electric cable connected to a TPE bushing does not exceed 100
m.
Make sure the TPE bushing of the product is connected only to safety extra low voltage
circuits (SELV circuits).
If in doubt, ask your system administrator.
Environment
Always dispose equipment that is finally taken out of operation according to your country’s
legislation and manufacturer’s instructions.
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Safety Notes
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Sicherheitshinweise
Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses
Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der
Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten
sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des
Produktes innerhalb Ihrer Betriebsumgebung notwendig sind. Wenn Sie diese
Vorsichtsmaßnahmen oder Sicherheitshinweise, die an anderer Stelle diese Handbuchs
enthalten sind, nicht beachten, kann das Verletzungen oder Schäden am Produkt zur Folge
haben.
Artesyn ist darauf bedacht, alle notwendigen Informationen zum Einbau und zum Umgang mit
dem Produkt in diesem Handbuch bereit zu stellen. Da es sich jedoch um ein komplexes
Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die Vollständigkeit der im
Handbuch enthaltenen Informationen nicht garantieren. Falls Sie weitere Informationen
benötigen sollten, wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn.
Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf
ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang
mit Industriesteuerungen verwendet werden.
Einbau, Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich
Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden. Die in diesem
Handbuch enthaltenen Informationen dienen ausschließlich dazu, das Wissen von
Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.
Halten Sie sich von stromführenden Leitungen innerhalb des Produktes fern. Entfernen Sie auf
keinen Fall Abdeckungen am Produkt. Nur werksseitig zugelassenes Wartungspersonal oder
anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen, um Komponenten
zu ersetzen oder andere Anpassungen vorzunehmen.
Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt
durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für
Sie zuständige Geschäftsstelle von Artesyn. So stellen Sie sicher, dass alle
sicherheitsrelevanten Aspekte beachtet werden.
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Sicherheitshinweise
EMV
Das Produkt wurde in einem Artesyn Standardsystem getestet. Es erfüllt die für digitale Geräte
der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien
Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz
vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie Industriegebieten
gewährleisten.
Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei
unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können
Störungen im Hochfrequenzbereich auftreten.
Wird das Produkt in einem Wohngebiet betrieben, so kann dies mit grosser Wahrscheinlichkeit
zu starken Störungen führen, welche dann auf Kosten des Produktanwenders beseitigt werden
müssen. Änderungen oder Modifikationen am Produkt, welche ohne ausdrückliche
Genehmigung von Artesyn durchgeführt werden, können dazu führen, dass der Anwender die
Genehmigung zum Betrieb des Produktes verliert. Boardprodukte werden in einem
repräsentativen System getestet, um zu zeigen, dass das Board den oben aufgeführten EMVRichtlinien entspricht. Eine ordnungsgemässe Installation in einem System, welches die EMVRichtlinien erfüllt, stellt sicher, dass das Produkt gemäss den EMV-Richtlinien betrieben wird.
Verwenden Sie nur abgeschirmte Kabel zum Anschluss von Zusatzmodulen. So ist
sichergestellt, dass sich die Aussendung von Hochfrequenzstrahlung im Rahmen der erlaubten
Grenzwerte bewegt.
Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im Wohnbereich
Funkstörungen verursachen. In diesem Fall kann vom Betreiber verlangt werden,
angemessene Maßnahmen durchzuführen.
Betrieb
Beschädigung des Produktes
Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Produktes können zu
Kurzschlüssen führen.
Betreiben Sie das Produkt nur innerhalb der angegebenen Grenzwerte für die relative
Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich
auf dem Produkt kein Kondensat befindet.
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Überhitzung und Beschädigung des Produktes
Betreiben Sie das Produkt ohne Zwangsbelüftung, kann das Produkt überhitzt und schließlich
beschädigt werden.
Bevor Sie das Produkt betreiben, müssen Sie sicher stellen, dass das Gerät über eine
Zwangskühlung verfügt.
Fehlerhafter Datenbestand
Wenn sie die Spannungsversorgung des Produkts abschalten, während Programmdaten im
Flashspeicher aktualisiert, werden, können diese Daten nicht korrekt gespeichert werden. In
diesem Fall ist das Produkt mit hoher Wahrscheinlichkeit nicht mehr betriebsbereit und die
Funktionsfähigkeit muß durch einen qualifizierten Reparaturdienst wieder hergestellt werden.
Sicherheitshinweise
PCIE-8120 Installation and Use (6806800R89C)
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Sicherheitshinweise
Installation
Beschädigung von Schaltkreisen
Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau des Produktes
kannSchaltkreise beschädigen oder ihre Lebensdauer verkürzen.Bevor Sie das Produkt oder
elektronische Komponenten berühren, vergewissern Sie sich, daßSie in einem ESDgeschützten Bereich arbeiten.
Beschädigung des Produktes
Fehlerhafte Installation des Produktes kann zu einer Beschädigung des Produktes führen.
Verwenden Sie geeignetes Werkzeug, um das Produkt zu installieren/deinstallieren. Auf diese
Weise vermeiden Sie, dass das card oder die Platine deformiert oder zerstört wird
Kabel und Stecker
Beschädigung des Produktes
Bei den RJ-45 Steckern, die sich an dem Produkt befinden, handelt es sich um Twisted-PairEthernet (TPE). Beachten Sie, dass ein versehentliches Anschließen einer E1/T1/J1-Leitung an
einen TPE-Stecker das Produkt zerstören kann.
Kennzeichnen Sie deshalb TPE-Anschlüsse in der Nähe Ihres Arbeitsplatzes deutlich als
Netzwerkanschluss.
Stellen Sie sicher, dass die Länge eines mit Ihrem Produkt verbundenen TPE-Kabels 100 m
nicht überschreitet.
Das Produkt darf über die TPE-Stecker nur mit einem Sicherheits-Kleinspannungs-
Stromkreis (SELV) verbunden werden.
Umweltschutz
Entsorgen Sie alte elektronische Baugruppen stets gemäß der in Ihrem Land gültigen
Gesetzgebung und den Empfehlungen des Herstellers.
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PCIE-8120 Installation and Use (6806800R89C)
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