Artesyn ATCA-8310 Installation

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ATCA-8310

Installation and Use

P/N: 6806800M72E May 2014

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Trademarks

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Microsoft Corporation. PICMG®, CompactPCI®, AdvancedTCA™ and the PICMG, CompactPCI and AdvancedTCA logos are registered trademarks of the PCI

Industrial Computer Manufacturers Group. UNIX® is a registered trademark of The Open Group in the United States and other countries.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Artesyn assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to an Artesyn website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Artesyn.

It is possible that this publication may contain reference to or information about Artesyn products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Artesyn.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).

Contact Address

Artesyn Embedded Technologies Artesyn Embedded Technologies Marketing Communications 2900 S. Diablo Way, Suite 190 Tempe, Arizona 85282

Lilienthalstr. 17-19 85579 Neubiberg/Munich Germany

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Contents

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.2 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.4 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.1 Unpacking and Inspecting the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.2 Environmental and Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.2.1 Environmental Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.2.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.3 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.4 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.5 Installing and Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.5.1 Installing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.5.2 Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3 Controls, Indicators, and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.1 Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.1.1 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.1.2 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.1.3 Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.2 Onboard Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3 ATCA Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4 Connector Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.4.1 Zone 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.4.2 Zone 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.3 DMC Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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3.4.4 VGA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.4.5 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.4.6 Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.4.7 USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.2 Service and Packet Processor (SPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1.1 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1.2 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1.3 P4080 USB and Mass Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.1.4 P4080 Serdes Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.1.5 Freescale P4080 PCI-Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.1.6 Freescale P4080 Serial Rapid IO SRIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.1.7 Freescale P4080 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.2.1.8 Dual UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.2.1.9 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.3 General Purpose Processor (GPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.1 Intel x86 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.1.1 Thermal Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.1.2 Chipset Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.1.3 GPP System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.2 Mobile Intel 5 Series Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.2.1 PCI Express Interface of the Ibex-Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.2.2 Ibex-Peak Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.3 Ibex-Peak LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.4 Ibex-Peak SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.5 Ibex-Peak SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.6 Ibex-Peak USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.7 GPP System Management Bus (SMBus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2.8 Ibex-Peak RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3.3 GPP Ethernet Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3.3.1 Dual Gigabit Ethernet Controller Intel 82576 . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.3.3.2 Single Gigabit Ethernet Controller 82574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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4.4 DSP Farm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.4.1 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.4.1.1 DSP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.4.1.2 Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.4.1.3 EMAC Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.4.2 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.4.3 DSP TSIP Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.4.4 SRIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4.5 RGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4.6 DSP-FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4.7 Module IPMC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4.8 Configuration Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.4.8.1 Base Board and Module Slot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.4.8.2 Module Functional Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.4.8.3 DSP Mezzanine Card Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.5 Ethernet Network (ETH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.5.1 Ethernet Network Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5.2 ETH Switch Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5.2.1 Ethernet Switch Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5.2.2 Switch management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5.2.3 PHY connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5.3 ATCA Fabric Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.5.4 ATCA Base Interface and SOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.5.4.1 Serial over LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.6 Timing Synchronization (TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.6.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.7 Glue Logic FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.7.1 SPI System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.8 IPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.9 Reset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.9.1 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.9.1.1 GPP-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.9.1.2 SPP-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

4.9.1.3 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

4.9.1.4 RTM Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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5 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.1 BIOS Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.1.1 Shared Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.1.1.1 clid Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.1.1.2 btorder Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.1.1.3 bootwd Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.1.2 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.1.3 Redirection of Console I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.1.4 Board Information display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.2 BIOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.2.1 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.2.2 Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.2.3 Initiating Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

5.3 Setup Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.3.1 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.1.1 Platform Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.2 Advanced Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.3.2.1 PCI Subsystem Sub-menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3.2.2 ACPI Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.3.2.3 Trusted Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.3.2.4 S5 RTC Wake Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.3.2.5 CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.3.2.6 ME Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.3.2.7 Thermal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.3.2.8 Port 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.3.2.9 TDT Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

5.3.2.10 USB Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3.2.11 AMT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.3.2.12 Super IO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.3.2.13 Serial Port Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3.2.14 Network Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.3.3 Chipset Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.3.3.1 North Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

5.3.3.2 South Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.3.4 Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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5.3.5 Security Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.3.6 Save Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

5.4 Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.4.1 Status Code Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.4.2 SEC Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

5.4.3 SEC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

5.4.4 PEI Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

5.4.5 PEI Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.4.6 DXE Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

5.4.7 DXE Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.4.8 CPU Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

5.4.9 ACPI/ASL Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.4.10 OEM-Reserved Checkpoint Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6 U-Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.2 U-Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.2.1 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.2.1.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

6.2.1.2 Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.2.1.3 Network interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

6.2.1.4 GPP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

6.2.1.5 Firmware Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

6.2.1.6 FPGA/Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

6.2.1.7 IPMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.2.1.8 Application Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.2.1.9 Default Boot Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

6.2.1.10 Broadcom Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6.2.1.11 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.2.1.12 SRIO Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.2.1.13 Miscellaneous Commands and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

6.2.1.14 Power-on Self Test (POST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.2.1.15 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

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7 Intelligent Peripheral Management Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

7.1 IPMC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

7.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

7.3 Firmware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

7.4 HPM.1 Firmware Upgrade and Crisis Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.5 Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.5.1 Firmware Progress, OS Boot, and Boot Error Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.5.2 Boot Bank Supervision Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.5.3 POST Results Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.5.4 Power Good Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.5.5 SW Progress Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.5.6 Power Interface Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.5.7 Reset Cause Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.5.8 Presence Sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.5.9 Voltage and Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

7.6 Sensor Data Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.7 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

7.8 FRU Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

7.8.1 MAC Address FRU OEM Records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

7.9 Reset Domains and FRU Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

7.10 U-Boot Boot Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.11 Asynchronous Event Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

7.12 Serial Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.13 Built-in Terminal Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7.13.1 Evaluating the Version of the Telnet Server Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.13.2 Establishing a Telnet Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

7.14 Fail Safe Logic and Watchdog Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

7.14.1 SPP BMC Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

7.14.2 SPP FPGA Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.15 Payload Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.16 Payload Boot Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.17 Settable Graceful Shutdown Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

7.18 FPGA Health Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.19 GPP THERMTRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

7.20 Local System Event Log (SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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7.21 IPMI Hardware Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.22 Artesyn OEM Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

7.22.1 Set Serial Output Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

7.22.2 Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.22.3 Set Feature Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

7.22.4 Get Feature Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.22.5 Send SW Progress Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

8 CPLD and FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

8.1 Power-up CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

8.1.1 Power-up CPLD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

8.1.1.1 Unit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8.1.2 CPLD Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8.1.2.1 CPLD Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

8.1.2.2 CPLD Registers Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

8.1.3 Reset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

8.1.4 Clocking Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

8.1.5 Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

8.1.5.1 IPMC Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

8.1.5.2 IPMC IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

8.1.5.3 FPGA Configuration Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

8.1.5.4 CPLD Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

8.1.5.5 IPMC SPI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.1.5.6 FPGA SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.2 Glue Logic FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

8.2.1 Glue Logic FPGA Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

8.2.1.1 Unit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

8.2.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

8.2.2.1 Register Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

8.2.2.2 Glue Logic FPGA Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

8.2.2.3 Glue Logic FPGA Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8.2.3 Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.2.3.1 Telecom Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.2.3.2 Asynchronous Receiver Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

8.2.3.3 Super IO Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

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8.2.3.4 GPP Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

8.2.3.5 Watchdog Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

8.2.3.6 GPP Interrupt Mapping Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

8.2.3.7 SPP Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

8.2.3.8 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

8.2.3.9 Glue Logic FPGA Configuration Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . .357

8.2.3.10 Glue Logic FPGA Dual Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

8.2.3.11 Communication between SPP, GPP and IPMC . . . . . . . . . . . . . . . . . . . . . . . . . 360

8.2.3.12 SPP Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

8.2.3.13 SPP Persistent memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

8.2.3.14 SPI Interfaces DCM baseboard, DMC1, DMC2 and ARTM . . . . . . . . . . . . . . . .365

8.2.3.15 Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

8.2.3.16 Reset Domain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

8.2.3.17 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

8.3 DSP FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

8.3.1 DSP FPGA Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

8.4 DSP FPGA HW/SW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

8.4.1 DSP FPGA Address map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

8.4.2 DSP FPGA Registers Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

8.4.2.1 SerDes Client Interface (8bit each) (SerDesClientIf) . . . . . . . . . . . . . . . . . . . . 385

8.4.2.2 TSIP Interface Test Pattern Generator Block (TstPatGenBlk) . . . . . . . . . . . . . 386

8.4.2.3 TSIP Interface Test Pattern Comparator Block ( TstPatCmpBlk) . . . . . . . . . .389

8.4.2.4 TSIP to Serializer Converter Block (Tsip2SerBlk) . . . . . . . . . . . . . . . . . . . . . . . 393

8.4.2.5 Deserializer to TSIP Allocater Block (Des2TsipBlk) . . . . . . . . . . . . . . . . . . . . . . 396

8.4.2.6 DSP Reset and NMI Control Block (DspResNmiCtrlBlk) . . . . . . . . . . . . . . . . . 402

8.4.2.7 DSP Status and Interrupt Block (DspStaIntBlk) . . . . . . . . . . . . . . . . . . . . . . . . 406

8.4.2.8 DMC Power Supply Control Block (DmcPwrCtrlBlk) . . . . . . . . . . . . . . . . . . . . 415

8.4.2.9 General Registers (GnrlRegs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

8.4.2.10 Configuration Prom Update Registers (CfgPrmUpd) . . . . . . . . . . . . . . . . . . .424

8.4.2.11 General Test Registers (GenTestRegs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

8.4.2.12 I2C interface to Dsps (I2CIfToDsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

8.4.2.13 MDIO interface to Phy (MdioIfToPhy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431

8.4.3 Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

8.4.3.1 Logic blocks Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

8.4.3.2 Transmission principle between TSIP and SERDES . . . . . . . . . . . . . . . . . . . . . 434

8.4.3.3 Setting up SERDES links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

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8.4.3.4 Pseudo Random Generator and Comparator (PRGC) . . . . . . . . . . . . . . . . . . .436

8.4.3.5 DSP Status and Interrupt Interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436

8.4.3.6 Base ID and Sub module ID Register (BSID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

8.4.3.7 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

A.1 Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

B Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

B.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . .443

Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445

Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

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Table 1-1 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 1-2 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 1-3 Blade Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 1-4 Blade Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 2-1 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 2-2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 3-1 Face Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 3-2 Zone 2 P20 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 3-3 Zone 2 P23 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 3-4 Zone 3 P30 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 3-5 Zone 3 P31 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 3-6 Zone 3 P32 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 3-7 DMC Mezzanine Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 3-8 VGA Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 3-9 Ethernet Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 3-10 Serial Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 3-11 USB Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 4-1 SPI Chip Select Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 4-2 P4080 I2C Bus Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 4-3 PCI Express Interface of the Ibex-Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 4-4 SMBus Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 4-5 BASE_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 4-6 MOD_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 4-7 DMCx_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 4-8 ACS8520 Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 4-9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 5-1 Aptio Navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 5-2 Menu Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 5-3 Main Menu Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 5-4 Platform Information Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 5-5 Advanced Menu Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 5-6 PCI Subsystem Sub-menu Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 5-7 ACPI Settings Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 5-8 Trusted Computing Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 5-9 S5 RTC Wake Settings Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 5-10 CPU Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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Table 5-11 Power and Performance Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Table 5-12 ME Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 5-13 Thermal Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 5-14 CPU Thermal Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Table 5-15 Platform Thermal Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 5-16 Port 80h Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 5-17 TDT Configurations Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Table 5-18 USB Configurations Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Table 5-19 AMT Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Table 5-20 Super IO Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Table 5-21 Serial Port 0 Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 5-22 Serial Port 1 Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Table 5-23 Serial Port Console Redirection Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 5-24 Console Redirection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 5-25 Network Stack Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 5-26 Chipset Menu Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 5-27 North Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 5-28 Common North Bridge Control Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Table 5-29 PEG Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Table 5-30 South Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Table 5-31 Ibexpeak Options Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 5-32 USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Table 5-33 SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 5-34 PCI Express Configuration Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 5-35 PCI-to-PCI Bridge Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 5-36 Boot Menu Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 5-37 Security Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Table 5-38 Save Menu Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 5-39 Status Code Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 5-40 SEC Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Table 5-41 SEC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Table 5-42 PEI Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Table 5-43 PEI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Table 5-44 DXE Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Table 5-45 DXE Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 5-46 CPU Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

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Table 5-47 ACPI/ASL Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 5-48 OEM-Reserved Checkpoint Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 6-1 P4080 Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 6-2 Dynamic Variables Set During the Boot Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 6-3 Variables for Controlling the Boot Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 6-4 GPP Run Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 6-5 U-Boot Name/Value Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 6-6 Boot Process Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 6-7 Broadcom Switch Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 6-8 Marvell Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 6-9 Port and SRIO Target ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 6-10 POST Tests and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 7-1 Voltage and Temperature Sensor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 7-2 Sensor Data Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 7-3 FRU information EEPROM Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 7-4 Aryesyn ECC MAC Address Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 7-5 Artesyn ECC MAC Address Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 7-6 Interface Type Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 7-7 IPMC Boot Parameter Storage Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 7-8 TS Channel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 7-9 Artesyn OEM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 7-10 Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 7-11 Serial Output Selector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 7-12 Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 7-13 Set Feature Configuration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 7-14 Feature Selector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 7-15 Get Feature Configuration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 7-16 Send SW Progress Data Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 8-1 Register Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 8-2 Register Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 8-3 CPLD Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 8-4 CPLD Code Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 8-5 JTAG Update Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 8-6 Status Debug Switches, DMC Base ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 8-7 Status DMC 1 ID and DMC 2 ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 8-8 GPP Status Signals Part 1Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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Table 8-9 GPP Status Signals Part 2Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

Table 8-10 SPP and other Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Table 8-11 Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Table 8-12 Power-up Failure Codes Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Table 8-13 Power-up Failure Codes Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Table 8-14 Power-up Failure Codes Part 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Table 8-15 Power-up Failure Codes Part 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Table 8-16 Power-up Failure Codes Part 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

Table 8-17 Power-up Failure Codes Part 6 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

Table 8-18 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

Table 8-19 Glue FPGA Force Golden Image or Reload Image Register . . . . . . . . . . . . . . . . . . . . . . . . . .255

Table 8-20 DMC Base FPGA force golden image or reload image Register . . . . . . . . . . . . . . . . . . . . . . .256

Table 8-21 DMC 1 FPGA force golden image or reload image Register . . . . . . . . . . . . . . . . . . . . . . . . . .256

Table 8-22 DMC 2 FPGA force golden image or reload image Register . . . . . . . . . . . . . . . . . . . . . . . . . .256

Table 8-23 RTM FPGA device 0 force golden image or reload image Register . . . . . . . . . . . . . . . . . . . .257

Table 8-24 RTM FPGA device 1 force golden image or reload image Register . . . . . . . . . . . . . . . . . . . .257

Table 8-25 RTM FPGA device 2 force golden image or reload image Register . . . . . . . . . . . . . . . . . . . .257

Table 8-26 Register Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

Table 8-27 Register Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

Table 8-28 Byte Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

Table 8-29 Word Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

Table 8-30 LPC I/O Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

Table 8-31 POST Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

Table 8-32 Super IO Configuration Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

Table 8-33 Super IO Configuration Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

Table 8-34 Global Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

Table 8-35 Super IO Logical Device Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

Table 8-36 Super IO Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

Table 8-37 Super IO Device Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

Table 8-38 Super IO LPC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

Table 8-39 Global Super IO SERIRQ and Pre-divide Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

Table 8-40 Logical Device Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

Table 8-41 Logical Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

Table 8-44 Logical Device Common Decode Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Table 8-42 Logical Device Base IO Address MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Table 8-43 Logical Device Base IO Address LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

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Table 8-45 Logical Device Primary Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 8-46 Logical Device 0x74 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 8-47 Logical Device 0x75 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 8-48 Logical Device 0x75 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 8-49 GPP UART Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 8-50 Receiver Buffer Register (RBR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 8-51 Transmitter Holding Register (THR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 8-52 Interrupt Enable Register (IER), if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Table 8-53 UART Interrupt Priorities2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Table 8-54 Interrupt Identification Register (IIIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 8-55 Interrupt Identification Register Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Table 8-56 FIFO Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Table 8-57 Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Table 8-58 Modem Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Table 8-59 Line Status Register (LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 8-60 Modem Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Table 8-61 Scratch Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 8-62 Divisor Latch LSB Register (DLL), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Table 8-63 Divisor Latch MSB Register (DLM), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Table 8-64 Glue FPGA Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 8-65 Glue Logic FPGA Module Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table 8-66 Glue Logic FPGA Code Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 8-67 Serial Line Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 8-68 User LED Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table 8-69 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Table 8-70 SPP Boot Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Table 8-71 GPP Boot Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 8-72 CPLD SPI Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 8-73 CPLD SPI Access Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 8-74 SPP BIOS Reset Source Indication Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Table 8-75 BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 8-76 SPP OS Reset Source Indication Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Table 8-77 OS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Table 8-78 IPMC Reset Source Indication Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Table 8-79 IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Table 8-80 Reset Terminal Server Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

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Table 8-81 Reset Release GPP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 8-82 Reset SPP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

Table 8-83 Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

Table 8-84 Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

Table 8-85 SPP Watchdog Trigger Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Table 8-86 GPP Watchdog Trigger Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Table 8-87 SPP Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Table 8-88 GPP Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

Table 8-89 SPP Watchdog Time-out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

Table 8-90 GPP Watchdog Time-out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

Table 8-91 Real Time Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

Table 8-92 Real Time Clock Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

Table 8-93 GPP Remote Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

Table 8-94 GPP Other Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

Table 8-95 Address Map of GPP Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

Table 8-96 Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

Table 8-97 GPP Mailbox Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

Table 8-98 SPP Mailbox Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

Table 8-99 GPP Mailbox Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

Table 8-100 SPP Mailbox Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

Table 8-101 SPP Page Pointer 1 to Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

Table 8-102 GPP Page Pointer 1 to Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

Table 8-103 SPP Page Pointer 2 to Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

Table 8-104 GPP Page Pointer 2 to Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

Table 8-105 Semaphore Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Table 8-106 SPP Shared Memory 8 byte Area. Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

Table 8-107 GPP Shared Memory 8 byte Area. Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

Table 8-108 SPP Shared Memory 8 byte Area. Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

Table 8-109 GPP Shared Memory 8 byte Area. Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

Table 8-110 Telecom Clock Enable/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 8-112 Supervised Telecom Clocks Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

Table 8-111 Telecom Clock 166Hz Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Table 8-114 Telecom Clock Monitor Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

Table 8-115 Telecom Clock Monitor Out of Range Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

Table 8-113 Telecom Clock Monitor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

Table 8-117 Telecom Clock Monitor Time Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

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Table 8-116 Telecom Clock Monitor Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Table 8-118 Telecom Clock Monitor Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 8-119 Telecom Clock Monitor Lower Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 8-120 Telecom Clock Monitor Upper Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 8-121 Test Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 8-122 Force CRC Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Table 8-123 Glue Logic FPGA Code SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Table 8-124 Glue Logic FPGA Code SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 8-125 SPP Persistent Memory Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Table 8-126 SPP Persistent Memory Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Table 8-127 SPP Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Table 8-128 GPP Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table 8-129 IPMC Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table 8-130 SPP and IPMC access to GPP Port 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table 8-131 Failover Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Table 8-132 Failover Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Table 8-133 Fault Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Table 8-134 Fault Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table 8-135 Software Fault Event 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 8-136 Software Fault Event 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 8-137 Software Fault Event 3Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 8-138 Software Fault Event 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 8-139 SPP Interrupt Group Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 8-140 Cascade Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Table 8-141 Cascade Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Table 8-142 SPP Watchdog Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 8-143 SPP Watchdog Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 8-144 SPP Remote Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 8-145 SPP Remote Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Table 8-146 IPMC KCS Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Table 8-147 Telecom Clocking Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Table 8-148 Telecom Clocking Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 8-149 Failover Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Table 8-150 SPP Failover Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Table 8-151 SPP Miscellaneous Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Table 8-152 SPP Miscellaneous Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

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Table 8-153 ARTM Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

Table 8-154 ARTM Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

Table 8-155 KCS Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

Table 8-156 KCS Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

Table 8-157 DMC Base SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

Table 8-158 DMC Base SPI LS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

Table 8-159 DMC Base SPI MS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

Table 8-160 DMC 1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

Table 8-161 DMC 1 SPI LS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

Table 8-162 DMC 1 SPI MS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

Table 8-163 DMC 2 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

Table 8-164 DMC 2 SPI LS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

Table 8-165 DMC 2 SPI MS Word Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

Table 8-166 ARTM SPI Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

Table 8-167 ARTM SPI Access Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350

Table 8-168 GPP Boot SPI Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350

Table 8-169 GPP Boot SPI Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Table 8-170 Terminal Server SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

Table 8-171 BIOS Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

Table 8-172 SPP Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

Table 8-173 GPP Serial Redirection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

Table 8-174 Logic DSP FPGA Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

Table 8-175 SerDesPreselect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Table 8-176 Test Pattern Generator Link and Timeslot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

Table 8-177 Test Pattern Generator Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

Table 8-178 Test Pattern Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Table 8-179 Test Pattern Comparator Link and Timeslot Register Register . . . . . . . . . . . . . . . . . . . . . . .389

Table 8-180 Test Pattern Comparator Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

Table 8-181 Test Pattern Comparator Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

Table 8-182 Test Pattern Comparator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

Table 8-183 Test Pattern Synchronization Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392

Table 8-184 Test Pattern Comparator Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

Table 8-185 Serdes Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394

Table 8-186 Serdes Transmitter Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

Table 8-187 Supplemental Test Pattern Transmit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

Table 8-188 Supplemental Test Pattern, CRC and Disparity Generator Control Register . . . . . . . . . . . .396

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Table 8-189 Serdes Receiver Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Table 8-190 Serdes Receiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Table 8-191 Supplemental Test Pattern Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 8-192 Supplemental Test Pattern Compare Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 8-193 Test Pattern , CRC and Disparity Error Counter Control Register . . . . . . . . . . . . . . . . . . . . . 399

Table 8-194 Test Frame Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 8-195 Supplemental Test Pattern Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 8-196 CRC Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Table 8-197 Disparity Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Table 8-198 DSPand Phy Reset and Dsp NMI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Table 8-199 DSP Local Reset and NMI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Table 8-200 DSP Boot Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 8-201 DSP Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Table 8-202 DSP Watchdog Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Table 8-203 DSP Host Event Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Table 8-204 DSP Watchdog Interrupt Status Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Table 8-205 DSP Host Event Interrupt Status Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 8-206 DSP Watchdog Interrupt Status Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Table 8-207 DSP Host Event Interrupt Status Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Table 8-208 DMC Power Supply Monitor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Table 8-209 Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Table 8-210 Synchronization and Error Monitor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Table 8-211 Synchronization and Error Monitor Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 8-212 Synchronisation and Error Monitor Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Table 8-213 Debug LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 8-214 Base Board and Module Place Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 8-215 Module Functional Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Table 8-216 Component Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 8-217 Dsp Fpga Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 8-218 Unoccupied Address Access Monitor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 8-219 Unoccupied Address Access Monitor Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 8-220 Unoccupied Address Access Monitor Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Table 8-221 Configuration Prom Update Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Table 8-222 Configuration Prom Update Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Table 8-223 Fault Insertion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 8-224 ScratchPad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

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Table 8-225 Test Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428

Table 8-226 Test Read Val Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429

Table 8-227 I2C Bit Bang Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430

Table 8-228 MDIO Bit Bang Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Table 8-229 DSP FPGA debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

Table B-1 Artesyn Embedded Technologies- Embedded Computing Publications . . . . . . . . . . . . . .443

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List of Figures

Figure 1-1 Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 1-2 Serial Number Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 2-1 Location of Critical Temperature Spots (Blade Top Side) . . . . . . . . . . . . . . . . . . . . . . 44

Figure 2-2 ATCA-8310 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 3-1 Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 3-2 Location of Face Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 3-3 Location of Face Plate Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 3-4 Location of AdvancedTCA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 4-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 4-2 Service Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 4-3 Boot Flash Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 4-4 Block Diagram of the GPP Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 4-5 DSP Cluster Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 4-6 Ethernet Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 4-7 Telco Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 4-8 CLK1, CLK2, CLK3 Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 4-9 Telco Clock Structure Continued . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 4-10 Glue Logic FPGA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 4-11 SPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 4-12 IPMC/MMC block diagram of the ATCA-8310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 5-1 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 5-2 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 5-3 Platform Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 5-4 Advanced Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 5-5 PCI Subsystem Sub-menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 5-6 ACPI Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 5-7 Trusted Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 5-8 S5 RTC Wake Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 5-9 CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 5-10 Power and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 5-11 ME Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 5-12 Thermal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 5-13 CPU Thermal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 5-14 Platform Thermal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 5-15 Port 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 5-16 TDT Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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List of Figures

Figure 5-17 USB Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 5-18 AMT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 5-19 Super IO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 5-20 Serial Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 5-21 Serial Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 5-22 Serial Port Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 5-23 Console Redirection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 5-24 Network Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 5-25 Chipset Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 5-26 North Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 5-27 Common North Bridge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 5-28 PEG Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 5-29 South Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 5-30 Ibexpeak Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 5-31 USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 5-32 SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 5-33 PCI Express Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 5-34 PCI-to-PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 5-35 Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 5-36 Security Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 5-37 Save Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 7-1 IPMC/MMC block diagram of the ATCA-8310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 7-2 Firmware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 7-3 IPMC Boot Parameter Storage Configuration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 7-4 COM #0 and IPMC Serial Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 7-5 Com #1 Serial Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 7-6 Payload Boot Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 8-1 Power-up CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 8-2 CPLD Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 8-3 IPMC SPI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 8-4 Glue Logic FPGA Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 8-5 Telecom Clock Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Figure 8-6 GPP Interrupt Structure handled by Glue FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Figure 8-7 SPI Flash Configuration circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 8-8 Inter Processor Communication (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 8-9 Failover Logic Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

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List of Figures

Figure 8-10 FPGA GPP Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Figure 8-11 SPP COM1 Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 8-12 Dsp Fpga Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370

Figure 8-13 Logic blocks overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Figure 8-14 122,912μs SERDES frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Figure A-1 Location of Onboard Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439

ATCA-8310 Installation and Use (6806800M72E)

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List of Figures

ATCA-8310 Installation and Use (6806800M72E)

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About this Manual

Overview of Contents

This Reference Guide is intended for users qualified in electronics or electrical engineering. Users must have a working understanding of Peripheral Component Interconnect (PCI), AdvancedTCA®, and telecommunications.

The manual contains the following chapters and appendices:

 About this Manual on page 27 lists all conventions and abbreviations used in this manual

and outlines the revision history.

 Safety Notes on page 445 lists safety notes applicable to the blade.

 Sicherheitshinweise on page 449 provides the German translation of the safety notes

section.

 Introduction on page 35 describes the main features of the blade.

 Hardware Preparation and Installation on page 41 outlines the installation requirements,

hardware accessories, switch settings, installation and removal procedures.

 Controls, Indicators, and Connectors on page 55 describes external interfaces of the blade.

This includes connectors and LEDs.

 Functional Description on page 71 describes the functional blocks of the blade in detail.

This includes a block diagram, description of the main components used and so on.

 U-Boot on page 163 describes the features and setup of BIOS.

 Intelligent Peripheral Management Controller on page 201 lists all supported IPMI

commands.

 Replacing the Battery on page 439 provides the battery exchange procedures.

 Related Documentation on page 443 provides links to further blade-related

documentation.

ATCA-8310 Installation and Use (6806800M72E)

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Abbreviations

This document uses the following abbreviations:

Abbreviation Definition

ATCA Advanced Telecom Compute Architecture

BBS Basic Blade Services

BGA Ball Grid Array

BIOS Basic Input/Output System

BOM Bill of Material

CFM Cubic Feet per Minute

CG Carrier-grade

CPLD Complex Programmable Logic Device

CPM Critical Parameter Management

About this Manual

CPU Central Processing Unit

DDR Dual Data Rate (type of SDRAM)

DDR3 Double Data Rate 3 synchronous dynamic random access memory (SDRAM) is the

name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM.

DFM Design for Manufacturability

DFT Design for Test

DMA Direct Memory Access

DRAM Dynamic Random Access Memory

ECC Error Correction Code

EEPROM Electrically Erasable Programmable Read Only Memory

EMC Electro-magnetic Compatibility

EMI Electro-magnetic Interference

ESD Electro-static Discharge

FMECA Failure Mode, Effects and Criticality Analysis

FRU Field Replaceable Unit

FWH Firmware Hub

ATCA-8310 Installation and Use (6806800M72E)

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Abbreviation Definition

GA General Availability

Gb Gigabit(s)

GB Gigabyte(s)

Gbps Gigabits per second

GHz Gigahertz

GbE Gigabit Ethernet

GPIO General Purpose Input/Output

I2C Inter Integrated-Circuit Bus (2-wire serial bus and protocol)

I/O Input/Output

ICT In-circuit Test

IMC Integrated Memory Controller

About this Manual

IPMB Intelligent Platform Management Bus

IPMB-L The IPMB connecting the carrier IPMC to the AMC module

MMC Intelligent Platform Management Controller

IPMI Intelligent Platform Management Interface

ITP In-Target Probe

JTAG Joint Test Action Group (test interface for digital logic circuits)

L2 Level 2 (as in "L2 Cache")

LAN Local Area Network

LED Light-emitting Diode

LFM Linear Feet per Minute

LPC Low Pin Count

LVDS Low Voltage Differential Signaling

MAC Medium Access Controller

Mb(ps) Megabits (per second)

MB(ps) Megabytes (per second)

MHz Megahertz

MMC Module Management Controller

ATCA-8310 Installation and Use (6806800M72E)

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Abbreviation Definition

Module This term is used to refer to the Module card in this document

MP Management Power

MTBF Mean Time Between Failures

MTTR Mean Time To Repair

N/A Not Applicable

NEBS Network Equipment Building System

NMI Non-Maskable Interrupt

NT Non-transparent

NVRAM Non-volatile Random Access Memory

OEM Original Equipment Manufacturer

OOS Out-of-service

OS Operating System

About this Manual

PCB Printed Circuit Board

PCH Platform Controller Hub

PCI-E PCI-Express

PHY Physical layer device (for Ethernet)

PICMG PCI Industrial Computer Manufacturers Group

PLL Phase Locked Loop

POST Power-on Self Test

PP Payload Power

PRD Product Requirements Document

RC Root Complex

RoHS Restriction of Hazardous Substances

RS232 Recommended Standard 232C - interface standard for serial communication

RTC Real-Time Clock

Rx Receive line (of a duplex serial communication interface)

SATA Serial AT Attachment (high-speed serial interface standard for storage devices)

SDR Sensor Data Record

ATCA-8310 Installation and Use (6806800M72E)

Page 31

Abbreviation Definition

SDRAM Synchronous Dynamic Random Access Memory

SELV Safety Extra Low Voltage

SerDes Serializer-Deserializer

SIMD Single Instruction Multiple Data

SMBus System Management Bus

SMI System Management Interrupt

SODIMM Small Outline Dual-in-line Memory Module

SPD Serial Presence Detect

TBD To be decided

TCP Transmission Control Protocol

TDP Thermal Design Power

About this Manual

Tx Transmit line (of a duplex serial communication interface)

UART Universal Asynchronous Receiver-Transmitter

UDP User Datagram Protocol

USB Universal Serial Bus

ATCA-8310 Installation and Use (6806800M72E)

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Conventions

The following table describes the conventions used throughout this manual.

Notation Description

0x00000000 Typical notation for hexadecimal numbers (digits are

0b0000 Same for binary numbers (digits are 0 and 1)

bold Used to emphasize a word Screen Used for on-screen output and code related elements

Courier + Bold Used to characterize user input and to separate it

Reference Used for references and for table and figure

About this Manual

0 through F), for example used for addresses and offsets

or commands in body text

from system output

descriptions

File > Exit Notation for selecting a submenu

<text> Notation for variables and keys

[text] Notation for software buttons to click on the screen

and parameter description

... Repeated item for example node 1, node 2, ..., node

. . .

.. Ranges, for example: 0..4 means one of the integers

| Logical OR

Omission of information from example/command that is not necessary at the time being

0,1,2,3, and 4 (used in registers)

ATCA-8310 Installation and Use (6806800M72E)

Page 33

Notation Description

Summary of Changes

Indicates a hazardous situation which, if not avoided, could result in death or serious injury

Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury

Indicates a property damage message

No danger encountered. Pay attention to important information

Part Number Publication Date Description

6806800M72A October 2011 First version

6806800M72B October 2011 Updated Figure "Serial Number Location" on page 39 and

deleted Chapter 3.1 Mechanical Layout.

6806800M72C December 2011 Updated Table 4-8.

6806800M72D March 2012 Added Notice in Installation on page 446 and Installation on

page 450.

Updated EMC on page 445 and EMV on page 450.

6806800M72E May 2014 Re- branded to Artesyn template.

ATCA-8310 Installation and Use (6806800M72E)

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ATCA-8310 Installation and Use (6806800M72E)

Page 35

Introduction

1.1 Features

The ATCA-8310 is a Media Gateway on a blade architecture with on-board packet and controlplane processing options.

Main features:

 Single slot ATCA form factor (280mm x 322mm)

 Up to 30 TNETV3020 DSPs provide up to 16,000 ports of TDM -> IP conversion

 Build options for 0 or 5 TNETV 3020 DSP on baseboard

 Mezzanine sites supporting 5 or 10 TNETV3020 DSP per mezzanine

 Freescale P4080 for local setup, call control, and load balancing

 Build option for Intel Arrandale+ECC CPU with on-board mass storage for localized call

agent.

Chapter 1

 10G fabric interface with multiple non-blocking internal data paths

 Clock termination and sync

 Architecture-ready for next generation TNETV3030 DSP

 External Connectivity

– Wireline I/O RTM (different RTM)

– 8x OC/3 or 2 x OC/12 line terminations for voice traffic

– APS line and equipment protection

– 8x T1/E1 line terminations for local signaling

– BITS clock termination

– 4x GbE for direct VoIP connection also for Sigtran (signaling)

– 24x DS3

– 1x 10GigE SFP+

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1.2 Standard Compliances

The product is designed to meet the following standards.

Table 1-1 Standard Compliances

Standard Description

Introduction

UL 60950-1 EN 60950-1 IEC 60950-1 CAN/CSA C22.2 No 60950-1

CISPR 22 CISPR 24 EN 55022 EN 55024 FCC Part 15 Industry Canada ICES-003 VCCI Japan AS/NZS CISPR 22 EN 300 386 NEBS Standard GR-1089 CORE

NEBS Standard GR-63-CORE ETSI EN 300019 series

PICMG 3.0 Defines mechanics, blade dimensions, power distribution,

Legal safety requirements

EMC requirements (legal) on system level (predefined Artesyn system)

Environmental requirements

power and data connectors, and system management

ATCA-8310 Installation and Use (6806800M72E)

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Introduction

 To fulfill the requirements of Telcordia GR-1089,R4-14, use Shielded Twisted Pair (STP)

cables grounded at both ends to connect to the Ethernet ports.

 This blade contains an embedded power source rated >150W. To achieve NEBS

compliance on system level, Shelf Ground (chassis ground) and Logic Ground (logic signal return) have to be connected. The connection may be implemented inside the shelf, for example at the backplane, or the shelf has to provide a possibility to lead Logic Ground out of the shelf for external connection to Central Office Ground. For further information refer to Telcordia GR-1089-CORE, section 9.8.2, requirement R9-14.

 The product has been designed to meet the directive on the restriction of the use of

certain hazardous substances in electrical and electronic equipment (RoHS) Directive 2002/95/EC.

ATCA-8310 Installation and Use (6806800M72E)

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Figure 1-1 Declaration of Conformity

Introduction

ATCA-8310 Installation and Use (6806800M72E)

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1.3 Mechanical Data

The following table provides details about the blade's mechanical data, such as dimensions and weight.

Table 1-2 Mechanical Data

Feature Value

Dimensions (width x height x depth) 30 mm x 351 mm x 312 mm

Weight of blade 2.5kg

1.4 Product Identification

The following figure show the location of the serial number labels.

Introduction

8U form factor

Figure 1-2 Serial Number Location

ATCA-8310 Installation and Use (6806800M72E)

Serial Number

Page 40

1.5 Ordering Information

The following table lists the blade variants that are available upon release of this publication. Consult your local Artesyn Embedded Technologies sales representative for the availability of other variants.

Table 1-3 Blade Variants

Product Name Description

ATCA-8310-IA-T0 ATCA DSP blade with X86 processor, 0x TMS320TCI6486 DSP - BOM will

be created on customer request

ATCA-8310-IA-T5 ATCA DSP blade with X86 processor, 5x TMS320TCI6486 DSP installed,

and 2 free mezzanine sites

ATCA-8310-IA-T10 ATCA DSP blade with X86 processor, 10x TMS320TCI6486 DSP installed,

and 2 free mezzanine sites

ATC A-8310-IA-T20 ATC A DSP blade with X86 processor, 20x TMS320TCI6486 DSP - BOM will

be created on customer request

Introduction

ATC A-8310-IA-T30 ATC A DSP blade with X86 processor, 30x TMS320TCI6486 DSP - BOM will

be created on customer request

The following table lists the blade accessories that are available upon release of this publication. Consult your local sales representative for the availability of other accessories.

Table 1-4 Blade Accessories

Accessory Description

831X-MEZZ-T10 DSP mezzanine module for ATCA-8310 with 10x TMS320TCI6486

installed

ARTM-831X-IP ARTM-831X-2X10GE-4X1GBE

SM-BBS-WR-ATC A-8310 Basic Blade Services soft ware and SRstackware protocols based on MGEL

- CD media only

RJ45-DSUB-ATCA7140 RJ-45 DSUB cable for the ATCA-7140, 7150, 7350, 736X

ATCA-8310 Installation and Use (6806800M72E)

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Hardware Preparation and Installation

2.1 Unpacking and Inspecting the Blade

Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life. Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment.

Shipment Inspection

Chapter 2

To inspect the shipment, perform the following steps.

1. Verify that you have received all items of your shipment:

 Printed Quick Start Guide and Safety Notes Summary

 ATCA-8310 blade

 Any optional items ordered

2. Check for damage and report any damage or differences to the customer service.

3. Remove the desiccant bag shipped together with the blade and dispose of it according to your country’s legislation.

The blade is thoroughly inspected before shipment. If any damage occurred during transportation or any items are missing, please contact our customer's service immediately.

ATCA-8310 Installation and Use (6806800M72E)

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Hardware Preparation and Installation

2.2 Environmental and Power Requirements

In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed.

Before you power up the blade, calculate the power needed according to your combination of blade upgrades and accessories.

2.2.1 Environmental Requirements

The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment.

 The environmental requirements of the blade may be further limited down due to

installed accessories, such as hard disks or PMC modules, with more restrictive environmental requirements.

 Operating temperatures refer to the temperature of the air circulating around the

blade and not to the actual component temperature.

Blade Damage Blade Surface High humidity and condensation on the blade surface causes short circuits. Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power.

Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage. When operating the blade, make sure that forced air cooling is available in the shelf.

ATCA-8310 Installation and Use (6806800M72E)

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Hardware Preparation and Installation

Table 2-1 Environmental Requirements

Requirement Operating Non-operating

Temperature +5 ºC (+41 °F) to +40 ºC

(+104 °F) (normal operation) according to NEBS Standard GR- 63-CORE

-5 ºC (+23 °F) to +55 ºC (+131 °F) (exceptional operation) according to NEBS Standard GR-63-CORE

Airflow The blade is designed to

operate in a chassis that provides B4 cooling per CPTA

-40 ºC (-40 °F) to +70 ºC (+158 °F)

Temp. change +/- 0.25 ºC/min according to

NEBS Standard GR-63-CORE

Rel. humidity 5% to 90% non-condensing 5% to 95% non-condensing

Vibration 20 to 2000Hz

0.1 g from 5 to 100 Hz (Rack Level according to NEBS Standard GR-63-CORE)

+/- 0.25 ºC/min

5-20 Hz at 0.01 g2/Hz 20-200 Hz at -3.0 dB/octave Random 5-20 Hz at 1 m2/Sec3 Random 20-200 Hz at -3 m/Sec2

ATCA-8310 Installation and Use (6806800M72E)

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Hardware Preparation and Installation

During the safety qualification of this blade, the following on-board locations were identified as critical with regards to the maximum temperature during blade operation. To guarantee proper blade operation and to ensure safety, you have to make sure that the temperatures at the locations specified in the following are not exceeded. If not stated otherwise, the temperatures should be measured by placing a sensor exactly at the given locations. For your convenience all temperature spots are shown in the figure below that provides a detailed view of the blade.

Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)

R1307

R2106

R1812

R1813

R2104

C2134 R1127

R2105

DN1

C1829C1829

C1828C1828

D4D4

LED7LED7

P48P48

C2685

LED6LED6

R2140

C2457

5481R3842C

SW2SW2

R1844

P47P47

R1597

R1596

R1595

P39P39

P97

P18P18

U9001U9001

MH3

R3643 R3644

R3638R3637

R3639R3640

R1141 R1910

R1143

R1911

R1146

DISP1DISP1

R1280

R1274

R1265

D37D37

D36D36

D38D38

D35D35

R2154

R1618

R1617

R2153

R2152

C2462

R1754

R1755

C2460 C2461

D34D34

C2463

D33D33

U9015U9015

R384

A16

R1750

D32D32

D31D31

R1672R1815

R1671

U70U70U89U89U88U88

R1668 R1669

R1666

R1667 R1670

Y6Y6

C2409

C2413

R1615

R1589

R1590

R1586

R1612

R1582

R1614

R1584

R1585

R1583

U9019

R1599

C2414

C2408

U9021U9021

R1616

R1600

R279

R281

R282

R285

R286

J77

BJ1

R1292

R1268

R1269

R1245

R1894

R1118

R1275

R1294

R1288

R1277

R2056

R1115

R1184

R1116

R1119

R1266

R1248

R1267

R1912

R1909

R1283

C2683

R1289

R1290

R1276

R1286

R1279

R1281

R1282

R2024

J11

COO

J12

U63U63

J75

U9020U9020

ZSSD1

C2681

C2680

C2682

U57U57

R1295

R1285

R1291

R1270

R1287

R1293

R1328

R1329

C2248

C2250

7422C6422C R1315

C2254

R1325

R1324

Q73Q73

R1323

R1322

U39U39

R1762R1762

R1317

C2251 C2257

R1321

R1320

E122

R2016

R2019

R2017

R2020

U5005U5005

P46P46

U5004U5004

CMM

CE/C-TICK

ZSSD2

CE2

CE3

R2059 R2060

Temperature spot #2 Max: 100 °C (exact location: in the geometric middle of the heat spreader)

R1042

R1060

R1017

R1016

R1043

R1045

R1044

R1048

A71

R1049

R1051

R1050

3602C8302C R1158

R1056

C2039

C2050

R1053

C2030

C2062

6502C1102C

C2015

C2072

C2010

C2066

C2009

C2067

C2008

C2068

C2029

C2023

C2022

C2018

6302C7302C

R1058

C1994

C2002

R1018

R1019

R1006

R989

R990

R991 R358

R1000

R992

R1963

C2663

R1009

R1962

R1008

C1875

U54U54

S14 P1

P15

C2012C2012

R993

R994

R1024

R1025

R1007

C1923

C2337C2337 C2338C2338 C2336C2336

L29L29

L28L28

Q16Q16

Q70Q70

Q68Q68

Q69Q69

C2328C2328

C2320C2320

C2318C2318

C2321C2321

C2521

R1914

C1177

C2572

C2315

R468

R1412

R466

C2331

C2570

C1176

C2330

C2335

C2571

U64U64

U60U60

C2316

C2332

C1178

U19U19

R460

R1413

C2334

8032C3041R

ZF5

R1012

R1013

R1011

U35U35

R1031 R2018

BV1

R1027

R1026

R1028

R1014

R1021

R1015

R1020

R1956

R365

R371

R361

C1090

C2 C1085

R369

C1097

R373

U14U14

R374

C1093

C1092

C1195

C1196

C1194

C1187

C1192 C1189

C1099C1099 C1197C1197 C1198C1198

C1100C1100

C2401

C961C961

L10L10

L35L35

L34L34

Q19Q19

Q18Q18

C2511C2511 C2329C2329

C1190C1190

C1186C1186

Q76Q76

Q75Q75

R1836

Q74Q74

C1088C1088

Q17Q17 Q71Q71

Q30Q30

Q31Q31

C2510C2510

C1086C1086

C1087C1087

C1185C1185

C1089C1089

C1191C1191

P91P91 P93P93

Temperature spot #1 Max: 110 °C (exact location: on top of the transformer housing)

C1163

R444

C1164

C1165

C1160

C1162C1159

C2107C2107

C2081C2081

R442

R443

R440

188

J15

R441

C1158

R438

R436

18765187

R50

R1917

C2581

P41P41

P40P40

R72

R70

C753

U4U4

C2580

R64

C2549

R1863

U94U94

C2550

R336

R1864 R1852

L8L8

C1072

C1066

U12U12

123

L9L9

C1073

C1068

U13U13

R2058R2057

C775C775

C771

C774C774

C773

C772

C766

C769

C764

J72 J71

6436

U56U56U36U36

L2L2

C2579

Q3Q3

Q1Q1

C2525

C2516C2516

C763C763

C768C768

C767C767

R2134

R2135

R2136

R2133

R2138

R2137

C826

C825

C823

C824

R1850

R1851

108

109

C1074C1074

U5U5

C1076C1076

162

163

C1075C1075

C1077C1077

U77U77

U78U78

CD1

GH1

L38L38

C962C962

Q2Q2

Q4Q4

C2517C2517

C1C1

216

J38

C828 C827 C860 E47

MH1

F7 F6

C2359C2359

C2360C2360

F4F4

F3F3

F2F2

C2358C2358

C2357C2357

F1F1

P23

A10

CD10

GH10

C965C965

P10

R3633 R3634 R3641R3642

R3632 R3631

R3630 R3629

R3628R3627

Temperature spot #3 Max: 105 °C (exact location: on top of the hold-up cap)

If you integrate the blade in your own system please contact your local sales representative for further safety information.

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2.2.2 Power Requirements

Make sure that the blade is used in an AdvancedTCA shelf connected to -48 VDC up to -60 VDC according to Telecommunication Network Voltage (TNV-2). A TNV-2 circuit is a circuit whose normal operating voltages exceed the limits for a safety-extra-low-voltage (SELV) under normal operating conditions, and which is not subject to over voltages from telecommunication networks.

Table 2-2 Power Requirements

Characteristic Value

Rated Voltage -48 VDC to -60 VDC

Operating Voltage -40 VDC to -72 VDC

Max. power consumption ATCA-8310 base board: 200W

Hardware Preparation and Installation

US and Canada: -48 VDC

US and Canada: -40 VDC to -60 VDC

ATCA-8310 Mezzanines (up to two provided): 60W / total =120W; supplied by ATCA-8310 base board

ARTM-8310: up to 40W (depends on type); supplied by ATCA-8310 base board

TOTAL: up to 360W

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Hardware Preparation and Installation

The blade provides two independent power inputs according to the AdvancedTCA Specification. Each input has to be equipped with an additional fuse of max. 90 A located either in the shelf where the blade is installed or the power entry module (PEM).

The power consumption has been measured using specific boards in a configuration considered to represent the worst-case (with RTM and SAS HDD, maximum memory population, USB-Flash, SF-MEM persistent memory module) and with software simultaneously exercising as many functions and interfaces as possible. This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification.

Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation. Depending on the actual operating configuration and conditions, customers may see slightly higher power dissipation, or it may even be significantly lower. There is also a dependency on the batch variance of the major components like the processor and DIMMs used. Hence, Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards.

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2.3 Blade Layout

The following figure shows the location of components on the ATCA-8310:

Figure 2-2 ATCA-8310 Blade Layout

Hardware Preparation and Installation

ATCA-8310 Installation and Use (6806800M72E)

Page 48

2.4 Switch Settings

The blade provides several configuration switches. Their location is shown in Figure "ATCA-

8310 Blade Layout" on page 47.

Blade Malfunction Switches marked as "'Reserved" may carry production-related functions and may cause the blade to malfunction if their setting is changed. Therefore, do not change settings of switches marked as "'Reserved". The setting of switches which are not marked as "'Reserved" has to be checked and changed before blade installation.

Blade Damage Setting/resetting the switches during operation can cause blade damage. Therefore, check and change switch settings before you install the blade.

Hardware Preparation and Installation

All DIP-switches are for debugging purposes only. For normal operation they have to stay in the off position.

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Hardware Preparation and Installation

2.5 Installing and Removing the Blade

The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves.

The blade can be installed in any AdvancedTCA node slot. Do not install it in an AdvancedTCA hub slot.

Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the face plate but use the handles.

2.5.1 Installing the Blade

To install the blade into an AdvancedTCA shelf, proceed as follows.

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Hardware Preparation and Installation

Installation Procedure

The following procedure describes the installation of the blade. It assumes that your system is powered on. If your system is not powered on, you can disregard the blue LED and skip the respective step. In this case, it is purely a mechanical installation.

1. Ensure that the top and bottom ejector handles are in the outward position by squeezing the lever and the latch together.

2. Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf. Ensure that the guiding module of shelf and blade are aligned properly.

3. Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance. Continue to gently push the blade until the blade connectors engage.

4. Squeeze the lever and the latch together and hook the lower and the upper handle into the shelf rail recesses.

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Hardware Preparation and Installation

5. Fully insert the blade and lock it to the shelf by squeezing the lever and the latch together and turning the handles towards the face plate.

If your shelf is powered on, as soon as the blade is connected to the backplane power pins, the blue LED is illuminated. When the blade is completely installed, the blue LED starts to blink. This indicates that the blade announces its presence to the shelf management controller.

If an RTM is connected to the front blade, make sure that the handles of both the RTM and the front blade are closed in order to power up the blade’s payload.

6. Wait until the blue LED is switched off, then tighten the face plate screws which secure the blade to the shelf. The switched off blue LED indicates that the blade’s payload has been powered up and that the blade is active.

7. Connect cables to the face plate, if applicable.

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2.5.2 Removing the Blade

This section describes how to remove the blade from an AdvancedTCA system.

Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the face plate but use the handles.

Hardware Preparation and Installation

Removal Procedure

The following procedure describes how to remove the blade from a system. It assumes that the system is powered on. If the system is not powered on, you can disregard the blue LED and skip the respective step. In that case, it is purely a mechanical procedure.

1. Unlatch the lower handle by squeezing the lever and the latch together and turning the handle outward just enough to unlatch the handle from the face plate. Do not rotate the handle fully outward. The blue LED blinks indicating that the blade power-down process is ongoing.

2. Wait until the blue LED is illuminated permanently, then unlatch the upper handle and rotate both handles fully outward.

If the LED continues to blink, a possible reason may be that the upper layer software rejected the blade extraction request.

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Hardware Preparation and Installation

Data Loss Removing the blade with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated, before removing the blade.

3. Remove the face plate cables, if applicable.

4. Unfasten the screws of the face plate until the blade is detached from the shelf.

5. Remove the blade from the shelf.

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Hardware Preparation and Installation

ATCA-8310 Installation and Use (6806800M72E)

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Controls, Indicators, and Connectors

3.1 Face Plate

The following figure illustrates the connectors, keys and LEDs available at the face plate:

Figure 3-1 Face Plate

Chapter 3

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Controls, Indicators, and Connectors

3.1.1 LEDs

The following figure illustrates all LEDs available at the face plate.

Figure 3-2 Location of Face Plate LEDs

ink

vity

ATCA-8310 Installation and Use (6806800M72E)

Page 57

The LEDs are described in the following table.

Table 3-1 Face Plate LEDs

LED Description

OOS Out Of Service

Red/optional Amber (controllable by IPMC): This LED is controlled by higher layer software, such as middle ware or applications.

IS Payload Power Status

Green: The payload power has been enabled by the IPMC. Note that this LED indicates the payload power status both in the early power state and the normal blade operation. OFF: Payload power is disabled Note: This LED is multicolored (red/green/yellow) and is programmable by IPMC.

Controls, Indicators, and Connectors

ATN Amber: This LED is controlled by higher layer software, such as middle ware or

applications.

ETH Status LEDs The Ethernet connector provides two status LEDs

Link (upper) Green: Link is available Off: No link Activity (lower) Yellow: Activity Off: No activity

U1, U2 Base interface activity is visualized via FPGA LEDs U1 and U2

U3 User LED, selectable color via FPGA register.

Colors: red, green, orange

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Controls, Indicators, and Connectors

Table 3-1 Face Plate LEDs (continued)

LED Description

H/S FRU State Machine

During blade installation: Permanently blue: On-board IPMC powers up Blinking blue: Blade communicates with shelf manager OFF: Blade is active During blade removal: Blinking blue: Blade notifies shelf manager of its desire to deactivate Permanently blue: Blade is ready to be extracted

3.1.2 Keys

The blade provides one face plate reset key.

Figure 3-3 Location of Face Plate Reset Key

ATCA-8310 Installation and Use (6806800M72E)

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Controls, Indicators, and Connectors

On pressing it, a hard reset is triggered and all attached on-board devices are reset.

You cannot reset the IPMC via this key.

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Controls, Indicators, and Connectors

3.1.3 Connectors

The blade provides the following face plate interfaces and control elements:

 For GPP:

– Two USB 2.0 ports

– D-SUB15 VGA connector

– Serial console port to connect to either GPP or IPMC serial I/F

– One 1000Base-T Ethernet port

 For SPP:

– Serial console port to connect to SPP

– One USB 2.0 port

 For IPMI:

– Out of Service, In Service, Attention, and Hot Swap LED's (IPMC control)

– LED's connected to FPGA for BASE IF and Faceplate IF Link Control (FPGA control)

– Recessed reset button

3.2 Onboard Connectors

The blade provides the following on-board connectors:

 2x Module Connector for DSP-Mezzanine Card

3.3 ATCA Backplane Connectors

The ATCA specification defines Zone 3 for user input/output signals. On ATCA-8310 ATCA Zone 3 Type A connector (direct connect to RTM) are used. The same connectors are used for Zone 2 and Zone 3. Zone 3 connectors are assigned to reference designators P30 through P32.

Zone 3 Connector P30 is the top most connector. P31 is below P30. P32 is below P31. Zone 3 connectors carry the signals as described in the following tables.

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Controls, Indicators, and Connectors

Figure 3-4 Location of AdvancedTCA Connectors

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Controls, Indicators, and Connectors

3.4 Connector Pin Definitions

3.4.1 Zone 2

Table 3-2 Zone 2 P20 Pin Assignment

P20

Row # Interface Col AB Col CD Col EF Col GH

1 CLKs CLK1A+ CLK1A- CLK1B+ CLK1B- CLK2A+ CLK2A- CLK2B+ CLK2B-

3 UP-Tx2+ UP-Tx2- UP-Rx2+ UP-Rx2- UP-Tx3+ UP-Tx3- UP-Rx3+ UP-Rx3-

Update Channel

4 UP-Tx0+ UP-Tx0- UP-Rx0+ UP-Rx0- UP-Tx1+ UP-Tx1- UP-Rx1+ UP_Rx1-

6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

7 Reserved NC NC NC Reserved Reserved Reserved Reserved

8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

9 NC NCNCNCNC NC NC NC

Reser ved

10 NC NC NC NC NC NC NC NC

UP-Tx4+ UP-Tx4- UP-Rx4+ UP-Rx4- CLK3A+ CLK3A- CLK3B+ CLK3B-

Reserved NC Reserved NC NC NC NC NC

Table 3-3 Zone 2 P23 Pin Assignment

P23

Row # Interface Col AB Col CD Col EF Col GH

1 Fabric Ch1 FAB1_TX2+ FAB1_TX2- FAB1_RX2+ FAB1_RX2- FAB1_TX3+ FAB1_TX3- FAB1_RX3+ FAB1_RX3-

2 FAB1_TX0+ FAB1_TX0- FAB1_RX0+ FAB1_RX0- FAB1_TX1+ FAB1_TX1- FAB1_RX1+ FAB1_RX1-

3 Fabric Ch0 FAB0_TX2+ FAB0_TX2- FAB0_RX2+ FAB0_RX2- FAB0_TX3+ FAB0_TX3- FAB0_RX3+ FAB0_RX3-

4 FAB0_TX0+ FAB0_TX0- FAB0_RX0+ FAB0_RX0- FAB0_TX1+ FAB0_TX1- FAB0_RX1+ FAB0_RX1-

5 Base 1 B1_TRD1+ B1_TRD1- B1_TRD2+ B1_TRD2- B1_TRD3+ B1_TRD3- B1_TRD4+ B1_TRD4-

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Controls, Indicators, and Connectors

Table 3-3 Zone 2 P23 Pin Assignment

P23

Row # Interface Col AB Col CD Col EF Col GH

6 Base 2 B1_TRD1+ B1_TRD1- B1_TRD2+ B1_TRD2- B1_TRD3+ B1_TRD3- B1_TRD4+ B1_TRD4-

7 NCNCNCNCNCNCNCNC

8 NCNCNCNCNCNCNCNC

9 NCNCNCNCNCNCNCNC

10 NC NC NC NC NC NC NC NC

3.4.2 Zone 3

Table 3-4 Zone 3 P30 Pin Assignment

P30

Row # Col AB Col CD Col EF Col GH

1 SERIAL_RTM-

RXD

2 NC NC NC TRACKDWN_

3 SPI_MOSI NC SPI_MISO NC SPI_CLK SPI_CLK1 SPI_CS_N NC

4 CLK_T3-Bits NC HEALTHY-OUT CONF_CRC-

5NC NC NC NCNCNCNC NC

6 PCIE_RX0+ PCIE_RX0- PCIE_TX0+ PCIE_TX0- PCIE_RX1+ PCIE_RX1- PCIE_TX1+ PCIE_TX1-

7 100MHz_PCIE

-CLK+

8 T4_CLK-OUT NC RTM_RST_N NC CLK_OUT7+ CLK_OUT7- GPIO2 GPIO3

9 IPMB_SCL IPMB_SDA V3P3_MGMT NC BRD_PRESEN

10 VP12 VP12 NC NC VP5_MGMT RTM_ENABLE_NSPP_I2C2_SCL SPP_I2C2_SDA

SERIAL_RTMTXD

100MHz_PCIE

-CLK-

NC NC NC NC PS1_N RTM_PWRGD

NC RTM2-FORCE-

VP-RTM

RTM_ACTIVE

ERR

NC NC REFCLK1 NC REFCLK2 NC

-OUT

T_N

GOLDEN

FPGA_DONE FPGA_INTI_N FPGA_PROG_N

NC RST_KEY_N NC

RTM1-FORCEGOLDEN

RTM0-FORCEGOLDEN

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Controls, Indicators, and Connectors

Table 3-5 Zone 3 P31 Pin Assignment

P31

Row # Col AB Col CD Col EF Col GH

1 ESSI3_TX+ ESSI3_TX- ESSI3_RX+ ESSI3_RX- ESSI4_TX+ ESSI4_TX- ESSI4_RX+ ESSI4_RX-

2 ESSI1_TX+ ESSI1_TX- ESSI1_RX+ ESSI1_RX- ESSI2_TX+ ESSI2_TX- ESSI2_RX+ ESSI2_RX-

3 ETH_XG_MDIOETH_RST_N ETH_XG_MDC NC ETH_MDIO0 NC ETH_MDC0 NC

4 NC NC CLK_77MHz NC FRSYNC NC MFRSYNC NC

5 16MHz NC 25MHz NC DS3+ DS3- 32MHz NC

6 DMC_TSIP0-

RX+

7 DMC1_TSIP0-

RX+

8 DMC2_TSIP0-

RX+

9 RTM2_TSIP_C

LK+

10 VP12 NC NC NC NC NC VP12 VP12

DMC_TSIP0RX-

DMC1_TSIP0RX-

DMC2_TSIP0RX-

RTM2_TSIP_C LK-

DMC_TSIP0TX+

DMC1_TSIP0TX+

DMC2_TSIP0TX+

RTM1_TSIP_C LK+

DMC_TSIP0TX-

DMC1_TSIP0TX-

DMC2_TSIP0TX-

RTM1_TSIP_C LK-

DMC_TSIP1RX+

DMC1_TSIP1RX+

DMC2_TSIP1RX+

RTM_TSIP_CLK+RTM_TSIP_CLK-CLK_166Hz NC

DMC_TSIP1RX-

DMC1_TSIP1RX-

DMC2_TSIP1RX-

DMC_TSIP1TX+

DMC1_TSIP1TX+

DMC2_TSIP1TX+

DMC_TSIP1TX-

DMC1_TSIP1TX-

DMC2_TSIP1TX-

Table 3-6 Zone 3 P32 Pin Assignment

P32

Row # Col AB Col CD Col EF Col GH

1NCNCNCNCNCNCNCNC

2 SG0_TX+ SG0_TX- SG0_RX+ SG0_RX- SG1_TX+ SG1_TX- SG1_RX+ SG1_RX-

3 SG2_TX+ SG2_TX- SG2_RX+ SG2_RX- SG3_TX+ SG3_TX- SG3_RX+ SG3_RX-

4 SG4_TX+ SG4_TX- SG4_RX+ SG4_RX- SG5_TX+ SG5_TX- SG5_RX+ SG5_RX-

5NCNCNCNCNCNCNCNC

6NCNCNCNCNCNCNCNC

7 XG_TX2+ XG_TX2- XG_RX2+ XG_RX2- XG_TX3+ XG_TX3- XG_RX3+ XG_RX3-

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Controls, Indicators, and Connectors

Table 3-6 Zone 3 P32 Pin Assignment

P32

Row # Col AB Col CD Col EF Col GH

8 XG_TX0+ XG_TX0- XG_RX0+ XG_RX0- XG_TX1+ XG_TX1- XG_RX1+ XG_RX1-

9NCNCNCNCNCNCNCNC

10 VP12 NC NC VP12 VP12 PS0_N NC NC

3.4.3 DMC Connector

Table 3-7 DMC Mezzanine Connector Pinout

Signal Pin Pin Signal

SRIO0_TX+ 1 2 SRIO1_TX+

SRIO0_TX- 3 4 SRIO1_TX-

GND 5 6 GND

SRIO_CLK+ 7 8 SRIO1_RX+

SRIO_CLK- 9 10 SRIO1_RX-

GND 11 12 GND

SRIO0_RX+ 13 14 NC

SRIO0_RX- 15 16 NC

GND 17 18 NC

SG1_TX+ 19 20 SG12_TX+

SG1_TX- 21 22 SG12_TX-

SG1_RX+ 23 24 SG12_RX+

SG1_RX- 25 26 SG12_RX-

VP12 27 28 VP12

SG2_TX+ 29 30 SG11_TX+

SG2_TX- 31 32 SG11_TX-

SG2_RX+ 33 34 SG11_RX+

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Controls, Indicators, and Connectors

Table 3-7 DMC Mezzanine Connector Pinout (continued)

Signal Pin Pin Signal

SG2_RX- 35 36 SG11_RX-

VP12 37 38 VP12

SG3_TX+ 39 40 SG10_TX+

SG3_TX- 41 42 SG10_TX-

SG3_RX+ 43 44 SG10_RX+

SG3_RX- 45 46 SG10_RX-

VP12 47 48 VP12

SG4_TX+ 49 50 SG9_TX+

SG4_TX- 51 52 SG9_TX-

SG4_RX+ 53 54 SG9_RX+

SG4_RX- 55 56 SG9_RX-

VP12 57 58 VP12

SG5_TX+ 59 60 SG8_TX+

SG5_TX- 61 62 SG8_TX-

SG5_RX+ 63 64 SG8_RX+

SG5_RX- 65 66 SG8_RX-

VP12 67 68 VP12

SG6_TX+ 69 70 SG7_TX+

SG6_TX- 71 72 SG7_TX-

SG6_RX+ 73 74 SG7_RX+

SG6_RX- 75 76 SG7_RX-

GND 77 78 NC

SG13_TX+ 79 80 NC

SG13_TX- 81 82 NC

SG13_RX+ 83 84 NC

SG13_RX- 85 86 NC

GND 87 88 NC

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Controls, Indicators, and Connectors

Table 3-7 DMC Mezzanine Connector Pinout (continued)

Signal Pin Pin Signal

BASE_ID1_MGMT 89 90 NC

BASE_ID0_MGMT 91 92 NC

DMC_ID3 93 94 DMC_PRESENT

DMC_ID2 95 96 NC

DMC_ID1 97 98 DMC_RESET_N

DMC_ID0 99 100 FORCE_GOLDEN

DMC_RSV3 101 102 BASE_ID3

DMC_RSV2 103 104 BASE_ID2

DMC_RSV1 105 106 BASE_ID1

DMC_RSV0 107 108 BASE_ID0

DMC_PWREN 109 110 HOUT_DSP_N

DMC_PWRGD 111 112 CONF_CRC_ERR

DMC_FPGA_PROG_N 113 114 FPGA_INIT_N

JTAG_TRST_N 115 116 FPGA_DONE

JTAG_TDO 117 118 FPGA_JTAG_TDO

JTAG_TDI 119 120 FPGA_JTAG_TDI

JTAG_TCK 121 122 FPGA_JTAG_TCK

TAG_TMS 123 124 FPGA_JTAG_TMS

SOI_MOSI 125 126 V3P3_MGMT

SPI_MISO 127 128 I2C_SDA_BUF

SPI_CLK 129 130 I2C_SCL_BUF

SPI_CS_N 131 132 BRD_PWROK

V3P3 133 134 V3P3

TSIP_CLK+ 135 136 CLK_8K

TSIP_CLK- 137 138 CLK_32M768

V1P2 139 140 V1P2

TSIP1_RX+ 141 142 TSIP1_TX+

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Controls, Indicators, and Connectors

Table 3-7 DMC Mezzanine Connector Pinout (continued)

Signal Pin Pin Signal

TSIP1_RX- 143 144 TSIP1_TX-

V1P2 145 146 V1P2

TSIP0_RX+ 147 148 TSIP0_TX+

TSIP0_RX- 149 150 TSIP0_TX-

V1P2 151 152 V1P2

The pinouts on Table 3-7 on page 65 applies to both mezzanine connectors. The signal names are then named DMC1… DMC2…

3.4.4 VGA Connector

Table 3-8 VGA Connector Pinout

Pin Signal Pin Signal

1 CRT-RED 9 VP5

2 CRT-GREEN 10 GND

3 CRT-BLUE 11 NC

4 NC 12 DDC-DATA

5 GND 13 CRT-HSYNC

6 GND 14 CRT-VSYNC

7 GND 15 DDC-CLK

8GND

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3.4.5 Ethernet Connector

Table 3-9 Ethernet Connector Pinout

Pin Signal

1 TRD0+

2 TRD0-

3 TRD1+

4 TRD2+

5 TRD2-

6 TRD1-

7 TRD3+

Controls, Indicators, and Connectors

8 TRD3-

3.4.6 Serial Connector

Table 3-10 Serial Connector Pinout

Pin Signal

1NC

2NC

3 TXD

4GND

5GND

6 RXD

7NC

8NC

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Controls, Indicators, and Connectors

3.4.7 USB Connector

Table 3-11 USB Connector Pinout

Pin Signal

1 VP5

2 USB-

3 USB+

4GND

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Functional Description

4.1 Block Diagram

The block diagram shows how the devices work together and the data paths used.

Figure 4-1 Block Diagram

Chapter 4

TCI

6486

DSP farm

SGMII

PHY

Arendale

CPU (optional)

TCI

6486

IBEX Peak

1 GbE

XAUI

CLK

1 * SRIO

TSIP

PHY

store

QPI

SATA

82571

PCIe

PCIe * n

PCI-33

TSIP SPI/USB

1 * SRIO

4 * SRIO

2 * GbE

30 * TSIP

8kHz

OSC

SRIO * n

Local Bus

30 * GbE

Tsi

572

SRIO * 1

ACS

8520

MSSYNC

LREFCLK1/2

T3/T4/MFrSync/FrSync/8kHz/19.44MHz

GLUE FPGA

Local Bus

P4080

3 * GE

PCIe *2

BCM

56624

SOL

6161

SPI

USB

MS-CNTR

flash

store

4 * GbE

XAUI

CLK166

REFCLK[0:2]

PHY

PCIe * 1 rear

UC-CLK

CLK3AB

CLK1/2AB

2 * ESSI + 2 * RX

Zone 2Zone 3

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Functional Description

4.2 Service and Packet Processor (SPP)

The service and packet processor serves the following purposes:

 Setting up and controlling the DSP-Farm

 Setting up and controlling the switch

 Running certain applications as required e.g. IP-SEC

The Freescale P4080 processor is used for these purposes.

Figure 4-2 Service Processor Overview



Tsi

572

Local BUS

Glue

FPGA

LPC

COM1/2

IPMI

2*PCIe

Zone3

SPI

Flash

(boot)

ACS

8520

USB

Flash

BCM

56624

USB

1*SRIO

SPIͲInterface

USB

PHY

1*XAUI

2*SGMII 2*PCIe



P4080

I2C0

Zone2UC

DualChannel

DDR3

I2C1

RTC

COM

FPRL

USB

USB

PHY

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4.2.1 Memory Interface

The Freescale P4080 provides an on-chip DDR3 compliant memory controller with the following features:

 Programmable timing supporting DDR2 and DDR3 SDRAM

 Two channel 64-bit data interface, supporting interleaving

 Full ECC support

4.2.1.1 Local Bus

The Freescale P4080 provides an enhanced local bus controller (eLBC).

The Glue-Logic FPGA is connected to LCS3# and configured as a 8 Bit device. LCS0-2# are connected to the FPGA as spare signals. LCS4# - 7# are not used.

4.2.1.2 SPI Interface

Functional Description

The Freescale P4080 includes a full duplex four-wire SPI interface. The SPI interface can support up to four separate SPI devices. The P4080 SPI interface is routed to the ACS8520B linecard PLL, and to the SPI-boot Flashes. The following table shows the P4080 chip select assignments for the SPI devices.

Table 4-1 SPI Chip Select Assignment

SPI Chip Select Value

CS0 SPI-Boot Flash

CS1 SPI-backup Boot Flash

CS2 ACS8520B

CS3 Terminal Server

4.2.1.2.1 Boot Flash

On the ATCA-8310, two SPI Flash devices are used as boot devices for the service processor. The flash devices used will be Atmel AT25321 with a capacity of 32MBit.

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4.2.1.2.2 Boot Bank Selection and Reprogramming

By default, the payload processor boots from Boot Flash device #1. An IPMI OEM command can be used to send a message to the IPMC to change the boot device. The IPMC provides an IPMI sensor to control the signal BOOT_SELECT. Write protection is implemented through the FPGA.

The update mechanism is described in the software specification. The principal is to store the information which device was used to boot from and keep that device protected. The redundant device can then be upgraded as needed.

Figure 4-3 Boot Flash Switching

Functional Description



P4080

IPMC

CS0/1# SPIͲInterface

CS1#

P4080ͲRESET

BOOT_SELECT#

IPMC_BOOTSEL#

Manual

BOOTSEL#

ACS

8520

Boot1_CS0/1#

Boot2_CS1/0#

Glue

FPGA

SPI

Flash

#1

SPI

Flash

#2

In case of an IPMC firmware upgrade, the BOOT_SELECT signal stays unchanged. Besides others, this signal is latched by a latch buffer to ensure that its state doesn't change when the IPMC resets hard.

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4.2.1.3 P4080 USB and Mass Storage

The P4080 has two multiplexed USB-MAC integrated which have the pins multiplexed with the three speed Ethernet Controller 1/2.

To connect a mass storage device, USB Host port 1 is used. This USB port is then connected to a modular flash disk module with USB2.0 interface that provides up to 16GB of user flash. The device initially used is the SmartModulear (SG9ED52M4GGCNEMR) with 4GB of memory.

The second USB port is routed to the front panel and accessible for external USB-devices.

4.2.1.4 P4080 Serdes Configuration

The Freescale P4080 provides 18 Serdes lanes that can be mapped to different IO-Interfaces. The following interfaces are required:

 2x PCI-Express, one to the RTM, one to the switch

 1x SRIO

Functional Description

 1x XAUI to the switch

 2x SGMII to the switch

4.2.1.5 Freescale P4080 PCI-Express

The Freescale P4080 provides three PCI Express 2.0 controllers running up to 5 GHz. Two of them are used on the ATCA-8310. Both interfaces are run with 2.5GHz.

Two lanes are routed to the switch. One lane is routed to the RTM via Zone 3.

4.2.1.6 Freescale P4080 Serial Rapid IO SRIO

The Freescale P4080 provides two serial RapidIO 1.2 controllers running at up to 3.125 GHz. One of them is used to connect to the SRIO switch device. The configuration is x1 and the speed is 2.5GHz.

Both controllers are connected to the SRIO-switch.

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4.2.1.7 Freescale P4080 Ethernet

The Freescale P4080 provides two XAUI interfaces and eight 1Gbps Ethernet interfaces which can be used alternatively. On the ATCA-8310, one XAUI interface is used to connect to the switch. The two 1G interfaces are routed to the switch device Table 6: SERDES. .

4.2.1.8 Dual UART

The Freescale P4080 provides a dual UART compatible with 16450 and the PC16550D UARTs. Both interfaces consist of four wires each: RXD, TXD, RTS and CTS. Both serial ports of the Freescale P4080 are routed to the Glue Logic FPGA. Only the TXD and RXD signals are used for this interface.

The serial port parameters for this port are 9600 baud, 8 data bits, no parity, 1 stop bit.

4.2.1.9 I2C Interface

The Freescale P4080 includes a dual I2C controller. Both open-drain two-wire interfaces provide multiple-master and master-slave I2C mode support. I2C bus 0 is used to connect to a boot sequencer memory and the SPD PROMs of the DDR3. I2C bus 1 is connected to an onboard RTC (DS1337).

Functional Description

Table 4-2 P4080 I2C Bus Assignment

Address Bus Component

0x5C 0 ISL90727

0x7C 0 ISL9072x

0xA0 0 Parameter PROM

0xA2 / 0x62 / 0x32 0 DIMM1 Memory module SPD PROM / SPD-Fuse / Temp Sensor

0xA4 / 0x64 / 0x34 0 DIMM2 Memory module SPD PROM / SPD-Fuse / Temp sensor

0xB0 0 RTC

0xA0 1 SRIO EEPROM

0x60 1 SRIO Switch

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4.2.1.9.1 RTC

The DS1337 is an I2C-bus-compatible real-time clock (RTC). This device contains a real-time clock/calendar and 31 bytes of static random access memory (SRAM). The real-time clock / calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. The clock operates in either the 24hr or 12hr format with an AM/PM indicator. The timekeeping supply current for this device is max 0.63uA. Battery backup is provided with one battery, supplying the SPP RTC and the GPP RTC.

Functional Description

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4.3 General Purpose Processor (GPP)

On the ATCA-8310, the Intel processor is responsible for the call control. For this purpose an Intel Arrandale+ECC CPU is used with the Mobile Intel 5 Series Chipset.

Figure 4-4 Block Diagram of the GPP Part

Functional Description



IMVP6.5

XDP

CRTVGA

2xUSB

1xSATA

FRPLͲETH

1xRS232

Arrandale+

ECC

FDI DMIx4

IBEXPEAKMobile

QM57

SPILPC

Glue

Logic

FPGA

DualChannelDDR3 800/1066MT/s

PCIe(Port6)

SMBUS

PCIex4(Port1Ͳ4)

SPIFlash

82574

GbELAN

DualGbE

LAN82576

ToBCM Switch

4.3.1 Intel x86 CPU

The Arrandale+ECC consists of two dies. The CPU-core which is based on the Nehalem core and the Ironlake GMCH core which includes memory and graphic controller.

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4.3.1.1 Thermal Monitor

The Arrandale+ECC provides integrated "Adaptive Intel Thermal Monitor and Digital Thermal Sensor" - PECI.

4.3.1.2 Chipset Connection

The connection to the chipset is done with a DMI x4 interface which is a proprietary interface from Intel. Electrically, it is similar to PCIe.

Additionally, the graphic signals are transmitted over the Intel Flexible Display Interface to the chipset.

4.3.1.3 GPP System Memory

The system memory, which is directly connected to the Arrandale+ECC consists of two channels. Unbuffered DDR3 memory with one DIMM-slot per channel is supported. The speed grade is 800/1066.

Functional Description

The ATCA-8310 provides two very Low Profile (VLP) Mini-DIMM sockets to install off-the-shelf DIMM modules. Different DIMM types must not be used at the same time. DIMM module height is restricted.

4.3.2 Mobile Intel 5 Series Chipset

The Mobile Intel 5 Series Chipset is available in different flavours. Two of which are suitable for the Arrandale+ECC platform. The QM57 (Ibex Peak Mobile) is used.

4.3.2.1 PCI Express Interface of the Ibex-Peak

The Ibex-Peak provides eight PCIe lanes.

For the ATCA-8310, port 1-4 will be configured as a by 4 port to connect to the dual Gigabit Ethernet Controller.

Table 4-3 PCI Express Interface of the Ibex-Peak

PORT Destination

1-4 Dual Gigabit Ethernet Controller

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Table 4-3 PCI Express Interface of the Ibex-Peak

PORT Destination

5 Not used

6 Gigabit Controller 82574

7-8 Not used

4.3.2.2 Ibex-Peak Display

The Ibex-Peak provides a VGA interface at the front panel via DSUB-15.

4.3.2.3 Ibex-Peak LPC

The LPC interface is connected to the Glue-Logic FPGA. A Super I/O will not be used for the ATCA-8310.

Functional Description

4.3.2.4 Ibex-Peak SPI

The SPI interface will be connected to the Glue-Logic FPGA. Inside the FPGA the redundant BOOT-Flash choice and the BIOS update over IPMI will be implemented.

4.3.2.5 Ibex-Peak SATA

SATA port 1 is routed to the onboard 1.8'' SSD. All other SATA-Ports are not used on the ATCA-

8310.

4.3.2.6 Ibex-Peak USB

USB port 1 and 2 are routed to the front panel.

4.3.2.7 GPP System Management Bus (SMBus)

The Ibex-Peak contains a SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.

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Functional Description

The SMBus interface of the Ibex-Peak is connected to onboard devices like Clock PLL's, Temperatures sensors and the SPD PROM's. The BIOS reads memory configuration parameters from SPD PROM.

Table 4-4 SMBus Address Map

Device Name Device Type Location SM-BUS Address

SPD EEPROM 24C02 DIMMA 0xA0

SPD EEPROM 24C02 DIMMB 0xA4

Thermal Sensor DIMMA 0x30

SPD EEPROM DIMMB 0x34

DDR3 VREF_D margening ISL90728 Base Board 0x7C

DDR3 VREF_D margening ISL90727 Base Board 0x5C

Clock generator CK505 Base Board 0xD2

XDP Debug Connector Base Board - can be

separated by series resistors

Device Name Device Type Location SML0-BUS Address

IPMI Controller H8S Renesas H8S Base Board - SML1 BUS

4.3.2.8 Ibex-Peak RTC

The integrated RTC requires a 32kHz quartz and a backup battery. There is one battery that provides backup for the GPP-RTC as well as the SPP-RTC. A CR2030 battery is used to provide backup.

4.3.3 GPP Ethernet Connectivity

Two Ethernet connections are provided from the GPP to the switch. For other purposes, one Ethernet interface is available on the front panel.

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4.3.3.1 Dual Gigabit Ethernet Controller Intel 82576

One dual 1GbE Ethernet Controller of type Intel 82576 is connected to the x4 PCI express bus of the Ibex-Peak (lane 1-4). The two Ethernet interfaces operate in 1000Base-X mode and are routed to the BCM56624. A serial EEPROM is used for storage of configuration parameters such as the MAC addresses.

4.3.3.2 Single Gigabit Ethernet Controller 82574

The Intel 82574 Ethernet controller is connected to the PCIe lane 6 of the Ibex-Peak. The 1000B-T interface is routed to the front panel and accessible via an RJ45 plug. A low profile RJ45 connector is used.

4.4 DSP Farm

The ATCA-8310 contains up to 30 x TNETV3020 "Tomahawk" DSPs TNETV3020. The DSPs are distributed between three modules, each with 10 DSPs. Module 0 is assembled on baseboard. Module 1 and 2 are arranged on two mezzanine cards DSP-MC1 and DSP-MC2.

Functional Description

Factory assembly options allow baseboard module configurations with 0, 5 and 10 DSPs. In total this gives options for 5, 10, 15, 20, 25 and 30 DSPs. The DSP mezzanines are not hot swappable. However, they can be exchanged or assembled in the field.

The DSPs are connected to the infrastructure with two SRIO ports per module, two concentrated TSIP SERDES interfaces per module and one GbE link per DSP. The design is fault tolerant in a way that a single failure, specifically the loss of a single DSP, does not cut the SRIO connection to functional DSPs.

Three additional GbE connections are routed to mezzanine connectors to support a minimum of 13 GbE connections at each mezzanine site for future use.

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Functional Description

The module structure of the mezzanine cards is identical to the baseboard module structure but with the following differences:

 The baseboard cluster allows a factory assembly option with five DSPs for different product

variants.

 The mezzanine cards are connected to baseboard via module connector

Figure 4-5 DSP Cluster Block Diagram

DDR2



DSP4

PHY

45

DDR2 DDR2 DDR2 DDR2 DDR2

DDR2 DDR2 DDR2 DDR2

DSP3 DSP2

DSP

FPGA

DSP6DSP5

4.4.1 Digital Signal Processor

PHY

23

TSIPSERDES

PHY

57

DSP1 DSP0

PHY

01

10*SGMII

DSPͲMCConnector

PHY

DSP7 DSP8 DSP9

89

The TNETV3020 device is a Texas Instruments fixed-point, voice-over-packet, digital signal processor (DSP) targeting telephony infrastructure applications, including voice-over-packet high-density and medium-density gateways, wireless media gateways, and remote access servers.

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The peripheral set includes: three Telecom Serial Interface Port (TSIPs), an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the TCI6486 DSP core processor and the network a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system, a Serial RapidIO with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit generalpurpose timers; an inter-integrated circuit bus module (I2C), 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes and a 16-bit multiplexed host-port interface (HPI16).

4.4.1.1 DSP Configuration

Following interfaces are not used and disable by strapping option:

 UTOPIA Interface

 TSIP Interface 1 and 2

Functional Description

 EMAC Interface 1

The DSPs run with 500 MHz core clock.

4.4.1.2 Boot Mode Selection

The desired boot mode is selected by setting the four boot mode select pins BOOTMODE<3..0>, which are sampled during reset. The BOOTMODE can be set simultaneous for all DSP via DSP-FPGA register.

Following boot modes are supported:

 Slave I2C boot (BOOTMODE = 4)

 EMAC Port 0 (BOOTMODE =9) default

 SRIO Boot (BOOTMODE =11)

4.4.1.3 EMAC Boot Mode

The bootloader configures the EMAC peripheral if it is enabled in bit 5 of Options in the EMAC boot parameter table, opens a transmit and receive channel, configures Rx Communications Port Programming Interface (CPPI), and also routes EMAC Rx interrupt to 4, and Tx interrupt to

5. Then the bootloader transmits an Ethernet-ready frame out if it is enabled in bit 4 of Options.

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When an EMAC Rx interrupt happens, the bootloader processes the received packet and passes the boot tables into memory. As a result of Efusing, the MAC address is stored in registers 0x02A8 0700 and 0x02A8 0704. When the end of the boot table is reached, it clears the Rx Channel 0 head description pointer to disable reception and exit boots, and jumps to application.

The Ethernet peripheral is configured to accept a combination of a single MAC address and broadcast packets, as defined by the Ethernet boot parameter table. The peripheral rejects packets not matching the MAC addresses selected without a record of the drop.

4.4.2 DSP Memory

The TCI6486 DDR2 interface supports JEDEC DDR2 x16 devices. Supported densities are 256Mb, 512Mb, and 1Gb in the x16 device width. Any JEDEC DDR2-533 speed grade device at these densities in the x16 width will work with TCI6486's DDR2 controller at 266 MHz clock speed/533M data rate. The DSP memory on the ATCA-8310 is realized with two DDR2x16 devices per DSP and runs with 266 MHz. The memory access will be 32 bits wide.

Functional Description

4.4.3 DSP TSIP Interface

The TSIP is a multi-link serial interface consisting of a maximum of eight transmit data signals (or links), eight receive data signals (or links), two frame sync input signals, and two serial clock inputs. The TSIP module offers support for a maximum of 1024 timeslots for transmit and receive. Typically, 672 timeslots (DS3) for transmit and receive are utilized on these links. The TSIP module can be configured to use the frame sync signals and the serial clocks as redundant sources for all transmit and receive data signals or one frame sync and serial clock for transmit and the second frame sync and clock for receive. The standard serial data rate for each TSIP transmit and receive data signal is 8.192 Mbps. The standard frame sync is a one- (or more) bit wide pulse that occurs once every 125 ms or a minimum of one serial clock period every 1024 serial clocks. At the standard rate and default configuration there are 8 transmit and 8 receive links that are active. Each serial interface link supports up to 128 8-bit timeslots. This corresponds to an HMVIP or H.110 serial data rate interface.

The serial interface clock frequency may be either 16.384 MHz (default). Typical timeslot occupation is 96 timeslots (DS2) for each serial interface link. Seven transmit data links and seven receive data links are utilized to support the DS3 timeslot requirement. The eighth transmit and receive links are available to support common channel signaling (CCS).

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The data rate for the serial interface links is set to 32.768 Mbps and the number of active serial links is reduced to two.

4.4.4 SRIO Interface

The TNETV3020 has two x1 SRIO interfaces which are cascaded to one chain with two connections to the carrier board. The design is fault tolerant in a way that a single failure, specifically the loss of one single DSP, does not cut the SRIO connection to functional DSPs.

The SRIO interfaces run with 1.25 Gb during boot operation and 2.5 Gb at normal operation.

4.4.5 RGMII Interface

Each TNETV3020 has a RGMII Ethernet interface which is connected to a dual PHY device BCM5482S. The MDIO serial interface allows the DSP to configure the PHY devices and read back PHY link information.

Functional Description

The BCM5482 offers an interface converter mode that supports RGMII-to-SGMII slave data conversion. Each one of the PHY ports has a secondary SerDes that is used to perform conversion.

4.4.6 DSP-FPGA

The DSP-FPGA is the main control unit on the DSP cluster. It controls all DSP functionality including TSIP interface to the RTM and the power sequencing. The DSP-FPGA is connected to service processor via SPI interface.

The configuration data are stored one SPI flash device. For update and recovery the SPP has access to the configuration device.

Detailed functional informations are specified in detail within the FPGA Design Specification.

4.4.7 Module IPMC Interface

Each DSP module contains an EEPROM to storage FRU information. The interface is powered by management power and connected to the IPMC via I2C.

Sensors and FRU information are specified in detail within the IPMC Design Specification.

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4.4.8 Configuration Identifier

4.4.8.1 Base Board and Module Slot Identifier

The Base Board and Module Slot Identifier (BASE_ID) delivers information about the position and the address of a FPGA and is used for bit stream check and output buffer activation of the FPGA.

The BASE_ID is readable by the BaseIdReg (Address: 0xC5) of the DSP-FPGA

Table 4-5 BASE_ID

BASE_ID<3..0> Description

0b1100 DSP-FPGA on base board (DMC0)

0b1101 DSP-FPGA on mezzanine card 1 (DMC1)

0b1110 DSP-FPGA on mezzanine card 2 (DMC2)

Functional Description

0b1111 GLUE-FPGA on base board (for internal use only)

All others reserved

4.4.8.2 Module Functional Identifier

The Module Functional Identifier (MOD_ID) delivers information about the functionality of the DSP Mezzanine Card.

The MOD_ID is readable by the ModuleFunctionalIdReg (Address: 0xC6) of the DSP-FPGA.

Table 4-6 MOD_ID

MOD_ID<3..0> Description

0b0000 Reserved

0b0001 2 DSP available

0b0010 5 DSP available

0b0011 10 DSP available

All others reserved

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4.4.8.3 DSP Mezzanine Card Identifier

The DSP Mezzanine Card Identifiers (DMCx_ID) deliver information about the availability and type of DSP Mezzanine Cards and is used for power control requirements inside the CPLD.

The DMCx_ID of each module is readable by the status registers (Address: 0x02/0x03) of the Power-Up CPLD

Table 4-7 DMCx_ID

DMCx_ID<3..0> Description

0b1111 DSP Mezzanine Card not available

0b1110 DSP Mezzanine Card available

All others reserved

Functional Description

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4.5 Ethernet Network (ETH)

The Ethernet-part of the ATCA-8310 connects the DSP-Farm as well as the general purpose processor to Base and Fabric interface and the ARTM. For this purpose a suitable switch device is used. This switch is configured by the service processor.

Figure 4-6 Ethernet Overview



DSPfarm0(onboard)

5*DualͲPHY SGMIItoRGMII

BCM

5482

10*SGMII

6*SGMII

XAUIARTM

Functional Description

Zone3 Zone2

DSPfarm1module1

5*DualͲPHY SGMIItoRGMII

DSPfarm2module2

5*DualͲPHY SGMIItoRGMII

GPPCPU

SPPCPU

2*RS232 P4080

1*RS232 GPP

BCM

5482

BCM

5482

FPGA

13*SGMII

2*SGMII

XAUI

2*PCIe

SGMII

2*RS232

BCM

56624

2*SGMII

100BͲT

MCF

52232

2*XAUI

88E

6161

UC

BI

FPRL

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4.5.1 Ethernet Network Overview

The Ethernet Switching Unit on the ATCA-8310 provides following interfaces:

 One 1000Base-BX interfaces to the Update Channel 0

 Redundant connections to the PICMG 3.0 Base Interface

 Redundant connections to the PICMG 3.1, option 9 Fabric Interface.

 Redundant connections to a 10GBase-KX4 Fabric Interface

4.5.2 ETH Switch Unit

4.5.2.1 Ethernet Switch Device

The ATCA-8310 contains a BCM56624, which is a highly integrated Gigabit Ethernet switch with 10G uplink capability.

Functional Description

The interfaces to the host CPU via the PCI express bus of the Freescale P4080. High end switching systems use the PCI express interfaces for setup, configuration, maintenance, and management of the BCM56624 Switch. In high-end systems, requiring the host CPU running routing protocol stacks, PCI express bus is necessary for moving data packets to and from CPU.

For ATCA-8310, the BCM56624 provides switching between any on-board Ethernet port and the backplane interfaces (ATCA Base- and Fabric-interface).

4.5.2.2 Switch management

The switch device is managed by the SPP, Freescale P4080. Therefore the switch is connected to the SPP via a two line PCIe interface, running at 2.5Gb.

4.5.2.3 PHY connection

The MIIM_MDx_[1] interface is not connected.

The MIIM_MDx_[0] interface is routed to the Zone 3 as well as the MIIM_XG_MDx interface which is run at 2.5V (MIIM_XG_VDDO=2.5V). Both interfaces are 3.3V tolerant.

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4.5.3 ATCA Fabric Interface

The redundant (dual) Fabric Interface of the ATCA-8310 is provided by the Switching Unit. Two XAUI-Ports of the BCM56624 are directly connected to the Zone2, providing the ATCA Fabric Interface on connector P23 rows #4,#3 (Fabric Channel 1 Port 0-3) and rows #2,#1 (Fabric Channel 2 Port 0-3).

The two following options as described in the ATCA standards PICMG3.1 Rev.1.0 are supported:

 1x 1000Base-BX or 1000Base-KX (PICMG3.1 Option 1)

 1x 10GBase-BX4 or 10GBase-KX4 (PICMG3.1 Option 9)

4.5.4 ATCA Base Interface and SOL

The redundant Base Interface of the ATCA-8310 is also provided by the Switching Unit. Two SGMII lanes are connected to a MARVELL 88E6161 switch. This switch has 1000B-T ports to the Base interface. It is configured at power up via serial prom which allows for immediate SOL after power up.

Functional Description

4.5.4.1 Serial over LAN

The serial over LAN functionality is provided by a Freescale controller. This device transforms up to two RS232 ports to Ethernet and is connected to the Base-Switch via 100B-T.

4.6 Timing Synchronization (TS)

To support the timing synchronization on the ATCA-8310 the ACS8520 from Semtech is used.

The Microprocessor Interface Mode Selection connected to the SPI-bus of the Freescale P4080.

Table 4-8 ACS8520 Frequencies

Signal Frequency Connected to

CLK1A 8kHz From Backplane Zone2

CLK1B 8kHz From Backplane Zone2

CLK2A 19,44MHz From Backplane Zone2

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Table 4-8 ACS8520 Frequencies

Signal Frequency Connected to

CLK2B 19,44MHz From Backplane Zone2

CLK3A

CLK3B

MSSYNC_IN6.48MHz diff MasterSlaveSync

FPGA and Zone2 Update Channel

Functional Description

LREFCLK1 8kHz x N /

25MHz

LREFCLK2 8kHz x N /

25MHz

SYNC2K (2kHz)

1.544/2.04 8MHz

MFrSync 2kHz MultiFrameSync

FrSync 8kHz FrameSync

SBI_CLK 77.76MHz 1x Zone3

MVIP_CLK 16.384MHz 1x Zone3 RTM

TSIP_CLK 32.768MHz 3x DSP-FPGA

ETH_CLK_ OUT

25MHz Ethernet CLK output to

FPGA to 8520

ACS8520 to Zone3

ACS8520: 1x Zone3, 3x DSP-FPGA

1x GlueLogic FPGA

1x Zone3 RTM

Zone 3

T4 1.544/2.048

MHz

DS3_CLK 34/44/51

MHz

To RTM Zone 3

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Table 4-8 ACS8520 Frequencies

Signal Frequency Connected to

MSSYNC_ OUT

6.48MHz To FPGA

Functional Description

RTM_CLK_

To R TM

OUT7

ESFSync 166Hz (6ms) From FPGA to Backplane

Zone 3

Figure 4-7 Telco Clock Structure

Glue

I9 (Semtech)

FPGA

CMAC E2747

ACS

8520

CLK2A

BP (Zone2)ADM

166.7Hz

CLK1A

CLK2B

CLK1B

CLK3A

MSSYNC (diff)

6.48M

SYNC_2

SYNC2K (Semtech)

CLK1B

CLK1A

I5 (Semtech)

I7 (Semtech)

I6 (Semtech)

I8 (Semtech)

REFCLK1

REFCLK2CLK3B

I10 (Semtech)

166.7Hz (out)

T3 (BITS) I14 (Semtech)

TO1 (6.48MHz)

TO11 MFrSync (2kHz)

TO10 FrSync (8kHz)

TO5 (77.76MHz)

TO3 (32MHz)

TO4 (25.00MHz)

TO9 (1.544/2.048MHz) T4

TO6 DS3_CLK(12.283MHz)

TO2 (16MHz)

Zone 3

TO7

RXCLK[1] RXCLK[2] RXCLK[3]

RXCLK[N-2] RXCLK[N-1]

RXCLK[N]

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Figure 4-8 CLK1, CLK2, CLK3 Clock Structure



Zone2

CLK2A

8kHz

Functional Description

I12

CLK2B

CLK1A

CLK1B

CLK3A

CLK3B

EN_CLK3B

EN_CLK3A

SYNC_2

I13

Sync2K

I3 I4

I10

I14 (T3 BITS)

ACS

8520B

REFCLK1

REFCLK2

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Figure 4-9 Telco Clock Structure Continued

Functional Description



ADM

I11

ACS

8520B

TO1: (6.48MHz)

TO5: (77.76MHz)

TO2: (16.384MHz)

TO11: MFrSync (2kHz)

TO10: FrSync (8kHz)

TO3: (32.768MHz)

TO4: (25MHz)

TO9: T4 (1.544/2.048MHz)

TO6: DS3_CLK (34/44/51MHz)

TO2: (16,384MHz)

3x DSP-FPGA

TO7: RTM_CLK_TO7

166Hz

Zone3

166.7Hz

4.6.1 Oscillator

The ACS8520B is clocked by an external 12.80MHz oscillator. This means that the Free-run and Holdover stability is determined by the oscillator quality.

The following Oscillator is used:

CMACStratum 3, E2747, 3.3V

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4.7 Glue Logic FPGA

Figure 4-10 Glue Logic FPGA Overview



SPPLocalBus

GPP

LPCBus

GPP

SERIRQ

IPMC

LPCBus

Functional Description

IPMC

SERIRQ

SPPLocalBus

InternalLocalBus

IPMCSPIInterface

LPCBusInterface

SuperIO

CPLDSPIInterface

LPCHostInterface

COM1

COM2

PostCodeRegister

GPPWatchdogController

GPPResetController

GPPInterruptController

SPPWatchdogController

SPPResetController

SPPInterruptController

GPP/SPPSharedMemory

DMXBaseInterface

DMX1Interface

DMX2Interface

Miscellaneous

Functions

SerialSignals

7SegmentLEDDisplays

Watchdogsignals

GPPResetSignals

GPPInterruptSignals

SPPWatchdogSignals

SPPResetSignals

GPPInterruptSignals

DMCBaseSignals

DMC1Signals

DMC2Signals

OtherSignals

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Functional Description

The programmable logic required on ATCA-8310 (Windsor) resides in a Glue Logic FPGA. It implements special functions, like:

 LPC Bus Interface connected to GPP

 LPC Host Interface connected to IPMC. Local Bus to LPC Bridge. Includes SERIRQ. Emulates

KCS Interface

 Local Bus connected to SPP to access Glue Logic FPGA Register

 IPMC SPI interface connected through CPLD to access Glue Logic FPGA Register.

 GPP/SPP Shared Memory

 SPI Interface to update Glue FPGA Configuration Flash

 Two Serial Interfaces COM1 and COM2 usable via Super IO mapping for GPP

 Watchdog Controller for GPP and SPP

 Reset Controller for GPP and SPP

 Routing of internal and externals GPP Interrupts via SERIRQ protocol

 Routing of internal and externals SPP Interrupts to SPP interrupt input signals

 Interrupt masking of GPP and SPP interrupts

 GPP Post Code Register (For Debugging support)

 Telecom Clock Support

 DMC Module support

 GPP and SPP Boot SPI flash selection support

 Miscellaneous Registers (e. g. Version Register, User LED control)

4.7.1 SPI System Overview

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Figure 4-11 SPI Overview

Functional Description



LocalBus

GlueLogicFPGA

Config

SPI

RTM

PCIe

Bussedinternally

SPI

Flash

TSIͲFPGA

SPIͲBus

SPIͲBus

SPIͲBus

RTMͲ

FPGA

TSIͲXO

DSPͲ

FPGA

DSPͲ

FPGA

DSPͲ

FPGA

RTMͲ

FPGA

(base)

Config

SPI

Config

SPI

Config

SPI

Config

SPI

Config

SPI

Flash

SPI

Flash

SPI

Flash

SPI

Flash

SPI

Flash

RTMpiggypack

Config

SPI

Flash

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4.8 IPMC

ATCA-8310 (Windsor) is using the Renesas H8S IMPC building block from Pigeon Point Systems. For details on the implementation, refer to the Pigeon Point System documentation.

Figure 4-12 IPMC/MMC block diagram of the ATCA-8310

DSP Module

DMC Module

Temperature

Sensor

FRU Information

Presence Sensor

System Event Log

DMC Module

Sensor

Temperature

Sensor

FRU Information

Presence Sensor

Power Interface

Sensors

Temperature

Sensors

ATCA-8310 FRU

Information

Voltage Sensors

(SEL)

Glue Logic FPGA

I2C

P4080

Local Bus

KCS

Renesas H8S

2166 (IPMC)

WDT

IPMB-A

IPMB-B

IPMB-L

IPMB-0

SPI

Power

CPLD

ATMEGA 128

(MMC at RTM)

WDT

Functional Description

Mezzanine Card

Presence Sensor

Temperature Sensor

FRU Information

SFP Presence

Sensors

I2C

Temperature

Sensors

ATCA-8310 FRU

Information

Voltage Sensors

4.9 Reset Structure

The source of the reset is monitored by the Glue Logic FPGA and can be read after the ATCA8310 has booted. For a full description of the reset monitoring see the ATCA-8310 Glue Logic FPGA Design Specification.

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Functional Description

Similar to the power domains, the reset is also divided into domains. This means that the SPP and GPP can be reset independently. This is achieved by routing the Face plate Reset Key and the RTM Reset Key over the Glue Logic FPGA. The configuration of the FPGA determines the Reset that is asserted.

The default configuration is that SPP and GPP are reset simultaneously.

Table 4-9 Resets

Source Cold Reset Warm Reset

Power-Up Reset X X

Software Control Reset X X X

Watchdog Reset X X

Face plate Reset Key X X

RTM Reset Key X X

IPMI Reset X X

4.9.1 Reset Types

4.9.1.1 GPP-Reset

4.9.1.1.1 Cold Reset

During a Cold reset the CPU RESET#, PCI_RST# (legacy PCI bus) and PLT_RST# (downstream PCIe busses) signals are asserted. CPU RESET# is used to reset all internal registers, state machines and caches of the processor. The PCI_RST#/PLT_RST# is used to reset all onboard PCI/PCIe participants of all onboard PCI/PCIe busses. The P4080 is also reset by the PLT_RST# signal and generates CPU RESET# to the Nehalem-EP processors.

4.9.1.1.2 Warm Reset

During a Warm Reset the P4080 asserts the INIT# signal for 16 processor clock cycles. The INIT# signal is fed to the P4080 which resets the processors through QOI messaging without affecting its internal caches or bus state machines. Example for a Soft Reset is the Southbridge CF9h Warm Reset.

100

ATCA-8310 Installation and Use (6806800M72E)