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ATCA-7480
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Artesyn ATCA-7480 Installation

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ATCA-7480

Installation and Use
P/N: 6806800T17A February 2015
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©
Copyright 2015 Artesyn Embedded Technologies, Inc.
All rights reserved.
Trademarks
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Java™ and all other Java-based marks are trademarks or registered trademarks of Oracle America, Inc. in the U.S. and other countries. Microsoft®, Windows® and Windows Me® are registered trademarks of Microsoft Corporation; and Windows XP™ is a trademark of
Microsoft Corporation. PICMG®, CompactPCI®, AdvancedTCA™ and the PICMG, CompactPCI and AdvancedTCA logos are registered trademarks of the PCI
Industrial Computer Manufacturers Group. UNIX® is a registered trademark of The Open Group in the United States and other countries.
Notice
While reasonable efforts have been made to assure the accuracy of this document, Artesyn assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to an Artesyn website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Artesyn.
It is possible that this publication may contain reference to or information about Artesyn products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Artesyn.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).
Contact Address
Artesyn Embedded Technologies Artesyn Embedded Technologies Marketing Communications 2900 S. Diablo Way, Suite 190 Tempe, Arizona 85282
Lilienthalstr. 17-19 85579 Neubiberg/Munich Germany
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Contents
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.2 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1 Unpacking and Inspecting the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2 Environmental and Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2.1 Environmental Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.4 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.5 Installing the Blade Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.1 DIMM Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.2 SSD Carrier and MO297 SSD Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6 Installing and Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.6.1 Installing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.6.2 Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3 Controls, Indicators, and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.1 Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.1.1 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.1.2 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1.3 Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1.3.1 Serial COM#1 P17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.1.3.2 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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3.1.3.3 Serial Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1.3.4 USB 3.0 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2 On-board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2.1 MO297 SSD Module Carrier Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3 AdvancedTCA Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3 DDR4 Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.4 Platform Controller Hub (PCH) Intel C612 Wellsburg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4.1 PCH I/O Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4.2 Intel i350 Quad GB Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.4.3 Firmware Flashes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5 ATCA Fabric IF Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.6 Storage Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.7 MO297 SlimSATA Embedded Solid State Disc (SSD) Carrier/Riser Card . . . . . . . . . . . . . . . . . . . . 87
4.8 Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.9 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.10 IPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.10.1 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.10.2 FRU Data serial IDROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.10.3 System Event Log EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.11 Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.12 Serial Over LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.13 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.14 Front Board Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.15 Faceplate Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.15.1 IPMC Debug Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.16 USB 3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.17 LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.18 Trusted Platform Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.19 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.20 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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5 Maps and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.1 FPGA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.1.1 Register Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1.1.1 LPC Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
5.1.1.2 I2C Register Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.2 POST Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.1.3 Super IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.3.1 Entering the Configuration State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.3.2 Existing the Configuration State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.3.3 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.1.3.4 Super IO Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.1.4 UART1 and UART2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.4.1 UART Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.4.2 UART Registers DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1.4.3 Programmable Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.5 FPGA Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.5.1 LPC I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.5.2 IPMC I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.6 Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
5.1.7 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1.8 Serial Redirection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1.9 Serial over LAN (SOL) Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.10 Serial Line Routing Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.11 IPMC Power Failure Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.11.1 ME Power Failure Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.11.2 Payload Power Failure Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.11.3 Power Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.12 Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.12.1 BIOS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.12.2 Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
5.1.12.3 BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.1.12.4 BIOS Push Button Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.1.12.5 OS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
5.1.12.6 OS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.1.12.7 IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
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5.1.12.8 IPMC Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1.12.9 IPMC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.1.12.10DIMM ADR Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.1.12.11DIMM ADR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.13 CPU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.1.14 S-States Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.1.15 NMI Control Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
5.1.15.1 NMI Generation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.1.15.2 NMI Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.1.16 Interrupt Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.1.16.1 Internal Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
5.1.16.2 Telecom Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1.16.3 Telecom Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
5.1.16.4 RTM Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.1.16.5 External Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.1.16.6 Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.1.17 PCI Express Hot Plug I2C IO Expander Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1.17.1 CPU0 Hot Plug I2C IO Expander Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1.17.2 CPU1 Hot Plug I2C IO Expander Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1.17.3 Hot-Plug Virtual Pin Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1.17.4 PCA9555 Internal Register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
5.1.18 Flash Status and Selection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.1.19 PCH Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
5.1.20 RTM SPI Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.1.21 Update Channel Equalization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.1.22 RTM USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
5.1.23 LED Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.1.24 Spare Signals Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
5.1.25 CPU Presence Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.1.26 CPU Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.1.27 Telecom Clock Supervision Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.1.28 BIOS Version Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.1.29 IPMC BIOS Communication Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
5.1.30 Scratch Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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6 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.2 Accessing the Blade Using the Serial Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.2.1 Requirements for Serial Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.2.2 Default Access Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.2.3 Connecting to the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.3 Changing Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.4 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.4.1 Supported Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.4.2 Selecting the Boot Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.4.3 By Boot Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.5 IPMI Boot Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.6 BIOS Setup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.6.1 Main. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.6.2 Advanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.6.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.6.4 Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.6.5 Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
6.7 UEFI Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.8 Restoring BIOS Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.9 IPMI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
6.10 Watchdog Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
6.11 BIOS Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.11.1 Runtime Error Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.11.2 IPMI Error Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.12 LED Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.13 Upgrading the BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.14 BIOS POST Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
7 Serial Over LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.2 Installing the ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.3 Configuring SOL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.3.1 Using Standard IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
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7.3.2 Using ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
7.4 Establishing an SOL Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
8 Supported IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.1 Standard IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.1.1 Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.1.2 System Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.1.3 Watchdog Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.1.4 SEL Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.1.5 FRU Inventory Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
8.1.6 Sensor Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
8.1.7 Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.1.7.1 System Boot Options Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.1.8 LAN Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.2 PICMG 3.0 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.3 Artesyn Embedded Technologies Specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.3.1 Serial Output Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
8.3.1.1 Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
8.3.1.2 Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.3.2 OEM Command to configure IPMI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.3.2.1 Set Feature Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.2.2 Get Feature Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
8.4 Pigeon Point Specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
8.4.1 Get Status Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
8.4.2 Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.4.3 Set Serial Interface Properties Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.4.4 Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
8.4.5 Set Debug Level Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
8.4.6 Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
8.4.7 Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
8.4.8 Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
8.4.9 Set Handle Switch Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.4.10 Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.4.11 Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
8.4.12 Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
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8.4.13 Disable Payload Control Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
8.4.14 Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
8.4.15 Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
8.4.16 Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
8.4.17 Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
8.4.18 Set Payload Shutdown Time-Out Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
8.4.19 Get Module State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
8.4.20 Enable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
8.4.21 Disable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
8.4.22 Reset Carrier SDR Repository Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9 IPMI Feature Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
9.1 Firmware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
9.2 Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
9.2.1 HPM.1 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
9.2.1.1 IPMI Boot-loader and Firmware Component . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.2.1.2 IAP Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
9.2.1.3 FPGA Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
9.2.1.4 BIOS Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.2.2 Retrieving Versioning Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.2.3 Firmware Upgrade Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
9.2.3.1 Installing ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
9.2.3.2 Updating ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
9.2.3.3 Upgrading Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
9.2.4 HPM.2 Specific Firmware Updates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
9.3 Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
9.3.1 Payload Driven Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
9.3.2 Boot Bank Supervision Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
9.3.3 IPMC POST Results Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.3.4 Power Good Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.3.5 Power Interface Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.3.6 Reset Cause Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.3.7 Voltage and Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
9.3.8 ME Power Failure Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
9.3.9 Payload Power Failure State Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
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9.3.10 Payload Power Failure Cause Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.4 POST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.5 Ejector Handle De-Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
9.6 FRU Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
9.6.1 MAC Address FRU OEM Records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
9.7 Reset and Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
9.8 Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
9.9 BIOS Boot Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
9.10 Asynchronous Event Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.11 Serial Line Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.12 BIOS Boot Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
9.12.1 Boot Bank Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
9.12.2 Fail Safe Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
9.13 Glue Logic FPGA Flash Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
9.13.1 Boot Bank Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
9.13.2 Fail Protect Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
9.13.3 Remote Crisis Recover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
9.14 Settable Graceful Shutdown Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
9.15 Local System Event Log (SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1 Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
B Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
B.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . .327
B.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
B.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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Table 1-1 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 1-2 Blade Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 1-3 Blade Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-1 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 2-2 Critical Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 2-3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 2-4 Power Consumption of ATCA-7480 with and without RTM . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 2-5 Switch SW1 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 2-6 Switch SW2 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 2-7 Switch SW3 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 2-8 DIMM Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 3-1 Faceplate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 3-2 RJ45 female Serial Line Connector pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 3-3 Signal Segment Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 3-4 Power Segment Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 4-1 IPMI I2C Bus Address Map (private I2C bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 4-2 Faceplate Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 4-3 IPMC Debug Console Destination Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 4-4 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 4-5 SMBus Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 5-1 Register Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 5-2 Register Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 5-3 LPC I/O Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 5-4 IPMC SPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 5-5 POST Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 5-6 Super IO Configuration Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 5-7 Super IO Configuration Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 5-8 Global Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 5-9 Super IO Logical Device Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 5-10 Super IO Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 5-11 Super IO Device Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 5-12 Super IO LPC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 5-13 Global Super IO SERIRQ and Pre-divide Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 5-14 Logical Device Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 5-15 Logical Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 5-18 Logical Device Common Decode Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Table 5-16 Logical Device Base IO Address MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 5-17 Logical Device Base IO Address LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 5-19 Logical Device Primary Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table 5-20 Logical Device 0x74 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 5-21 Logical Device 0x75 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 5-22 Logical Device 0xF0 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 5-23 UART Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 5-24 Receiver Buffer Register (RBR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 5-25 Transmitter Holding Register (THR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 5-26 Interrupt Enable Register (IER), if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 5-27 UART Interrupt Priorities2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 5-28 Interrupt Identification Register (IIIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 5-29 Interrupt Identification Register Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 5-30 FIFO Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 5-31 Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 5-32 Modem Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 5-33 Line Status Register (LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 5-34 Modem Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table 5-35 Scratch Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table 5-36 Divisor Latch LSB Register (DLL), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 5-37 Divisor Latch MSB Register (DLM), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Table 5-38 FPGA Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Table 5-39 Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 5-40 FPGA Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 5-41 Serial Redirection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 5-42 Serial over LAN Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 5-43 Serial Line Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 5-44 ME Power Failure State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Table 5-45 ME Power Failure States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Table 5-46 ME Power Failure Cause Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 5-47 Payload Power Failure State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 5-48 Payload Power Failure States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 5-49 Payload Power Failure Cause Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Table 5-50 Payload Power Failure Cause Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Table 5-51 Payload Power Failure Cause Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Table 5-52 Power Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
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Table 5-53 BIOS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 5-54 Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 5-55 BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 5-56 BIOS Push Button Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 5-57 OS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 5-58 OS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 5-59 IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 5-60 IPMC Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 5-61 IPMC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 5-62 DIMM ADR Feature Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 5-63 DIMM ADR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 5-64 CPU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 5-65 S-States Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 5-66 NMI Generation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 5-67 NMI Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 5-68 Internal Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 5-69 Telecom Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 5-70 Telecom Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 5-71 External Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 5-72 Address Map of Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 5-73 Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 5-74 Hot-Plug Virtual Pin Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 5-75 Address Control for PCA9555 Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 5-76 Content of PCA9555 Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 5-77 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 5-78 PCH Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 5-79 RTM SPI Address/Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 5-80 RTM SPI Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 5-81 RTM SPI Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 5-82 Update Channel Equalization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 5-83 RTM USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 5-84 RTM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 5-85 RTM Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 5-86 LED Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 5-87 Spare Signal Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 5-88 CPU Presence Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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Table 5-89 CPU Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Table 5-90 Supervised Telecom Clocks Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Table 5-91 Telecom Clock Monitor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Table 5-92 Telecom Clock Monitor Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Table 5-93 Telecom Clock Monitor Out of Range Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Table 5-94 Telecom Clock Monitor Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Table 5-95 Telecom Clock Monitor Time Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Table 5-96 Telecom Clock Monitor Frequency/Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Table 5-97 Telecom Clock Monitor Lower Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Table 5-98 Telecom Clock Monitor Upper Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Table 5-99 BIOS Version Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Table 5-100 BIOS Version Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Table 5-101 BIOS Version Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Table 5-102 IPMC BIOS Communication Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Table 5-103 IPMC BIOS Communication Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Table 5-104 IPMC BIOS Communication Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Table 5-105 LPC Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Table 5-106 IPMC Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Table 6-1 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Table 6-2 Advanced >> RTM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
Table 6-3 Advanced >> Peripheral Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Table 6-4 Advanced >> Peripheral Configuration >> Intel VT for Directed I/O (VT-d) . . . . . . . . . . . . .188
Table 6-5 Advanced >> SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Table 6-6 Advanced >> USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Table 6-7 Advanced >> Processor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Table 6-8 Advanced >> Processor Configuration >> Processor Power Management Configuration 193
Table 6-9 Advanced >> Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Table 6-10 Advanced >> Memory Configuration >> Memory RAS Configuration . . . . . . . . . . . . . . . . .196
Table 6-11 Advanced >> Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Table 6-12 Advanced >> APEI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Table 6-13 Advanced >> BIOS Event Log Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 6-14 Advanced >> IPMI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Table 6-15 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Table 6-16 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Table 6-17 Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Table 6-18 Logged Error Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
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Table 6-19 BIOS Supported IPMI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 6-20 BIOS POST Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 7-1 SOL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 8-1 Supported Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 8-2 Supported System Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 8-3 Supported Watchdog Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 8-4 Supported SEL Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 8-5 Supported FRU Inventory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 8-6 Supported Sensor Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 8-7 Supported Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 8-8 Configurable System Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 8-9 System Boot Options Parameter #96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 8-10 System Boot Options Parameter #98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 8-11 System Boot Options - Parameter #100 - Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 8-12 System Boot Options Parameter #100 - SET Command Usage . . . . . . . . . . . . . . . . . . . . . . 237
Table 8-13 System Boot Options Parameter #100 - GET Command Usage . . . . . . . . . . . . . . . . . . . . . . 238
Table 8-14 System Boot Options Parameter #100 - Supported Parameters . . . . . . . . . . . . . . . . . . . . . 239
Table 8-15 boot_order Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 8-16 Supported LAN Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 8-17 Supported PICMG 3.0 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 8-18 Serial Output Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 8-19 Request Data of Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 8-20 Response Data of Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 8-21 Request Data of Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 8-22 Response Data of Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 8-23 Feature Configuration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 8-24 Set Feature Configuration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 8-25 Feature Selector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 8-26 Get Feature Configuration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 8-27 Pigeon Point Extension Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 8-28 IPMC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 8-29 Get Status Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 8-30 Get Serial Interface Properties Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 8-31 Set Serial Interface Properties Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 8-32 Get Debug Level Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 8-33 Set Debug Level Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
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Table 8-34 Get Hardware Address Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Table 8-35 Set Hardware Address Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Table 8-36 Get Handle Switch Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Table 8-37 Set Handle Switch Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 8-38 Get Payload Communication Time-Out Command Description . . . . . . . . . . . . . . . . . . . . .269
Table 8-39 Set Payload Communication Time-Out Command Description . . . . . . . . . . . . . . . . . . . . . . 270
Table 8-40 Enable Payload Control Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Table 8-41 Disable Payload Control Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Table 8-42 Reset IPMC Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Table 8-43 Hang IPMC Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Table 8-44 Graceful Reset Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Table 8-45 Get Payload Shutdown Time-Out Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . .274
Table 8-46 Set Payload Shutdown Time-Out Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Table 8-47 Get Module State Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Table 8-48 Enable Module Site Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
Table 8-49 Disable Module Site Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
Table 8-50 Reset Carrier SDR Repository Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
Table 9-1 HPM.1 components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Table 9-2 ATCA-7480 Specific Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Table 9-3 Event Data of Boot Bank Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Table 9-4 Status Sensor's Sensor Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Table 9-5 Voltage and Temperature Sensor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
Table 9-6 FRU information and SEL at EEPROM storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Table 9-7 Artesyn MAC Address Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Table 9-8 Artesyn MAC Address Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Table 9-9 Interface Type Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Table 9-10 Power Consumption Depending on the Product Version . . . . . . . . . . . . . . . . . . . . . . . . . . .312
Table 9-11 IPMC Boot Parameter storage format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . .327
Table B-2 Manufacturer’s Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
Table B-3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
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Figure 1-1 Serial Number Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 1-2 Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side) . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-2 ATCA-7480 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 2-3 Switch Location (Bottom Side of the Blade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 3-1 Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 3-2 Ethernet Interface Connectors Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 3-3 Serial Interface Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 3-4 USB Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 3-5 Location of MO297 SSD Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 3-6 MO297 SSD Module Carrier Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 3-7 Location of AdvancedTCA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 3-8 P10 Backplane Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 3-9 P20 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 3-10 P20 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 3-11 P23 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 3-12 P23 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 3-13 P30 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 3-14 P30 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 3-15 P31 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 3-16 P31 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 3-17 P32 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 3-18 P32 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 4-1 Block Diagram ATCA-7480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 4-2 Master Only I2C Bus Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 4-3 SMBus Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 6-1 Main menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 6-2 Boot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 6-3 IPMI Boot Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 6-4 Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 6-5 Platform Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 6-6 RTM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 6-7 Peripheral Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 6-8 Peripheral Intel VT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 6-9 SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 6-10 USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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List of Figures
Figure 6-11 CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 6-12 Processor Power Management Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 6-13 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 6-14 Memory RAS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 6-15 Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 6-16 APEI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 6-17 IPMI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 6-18 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 6-19 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 6-20 EFI Boot Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 6-21 Legacy Boot Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 6-22 Exit menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 7-1 SOL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview . . . . . . . . . . 236
Figure 9-1 IPMC block diagram of ATCA-7480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 9-2 Firmware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 9-3 FailSafe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 9-4 Fail Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure A-1 Location of On-board Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
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About this Manual

Overview of Contents

This guide is intended for users qualified in electronics or electrical engineering. Users must have a working understanding of Peripheral Component Interconnect (PCI), AdvancedTCA®, and telecommunications.
The manual contains the following chapters and appendices:
About this Manual on page 19, lists all conventions and abbreviations used in this manual
and outlines the revision history.
Safety Notes on page 25, lists safety notes applicable to the blade.
Sicherheitshinweise on page 31, provides the German translation of the safety notes
section.
Introduction on page 37, describes the main features of the blade.
Hardware Preparation and Installation on page 43, outlines the installation requirements,
hardware accessories, switch settings, installation and removal procedures.
Controls, Indicators, and Connectors on page 65, describes external interfaces of the blade.
This includes connectors and LEDs.
BIOS on page 173, describes the features and setup of BIOS.
Functional Description on page 83, describes the functional blocks of the blade in detail.
This includes a block diagram, description of the main components used and so on.
Maps and Registers on page 99, provides information on the maps and registers of the
blade.
Serial Over LAN on page 223, provides information on how to establish a serial-over LAN
session on your blade.
Supported IPMI Commands on page 229, lists all supported IPMI commands.
IPMI Feature Set on page 279, provides information about controlling via IPMI.
Replacing the Battery on page 323, provides the battery exchange procedures.
Related Documentation on page 327, provides links to further blade-related
documentation.
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About this Manual

Abbreviations

This document uses the following abbreviations:
Abbreviation Definition
APIC Advanced Programmable Interrupt Controller
ATA Advanced Technology Attachment
ATCA Advanced Telecommunications Computing Architecture
BIOS Basic Input/Output System
DDR Double Data Rate
DIMM Dual Inline Memory Module
ECC Error-Correction Code
EMC Electromagnetic Compatibility
EMV Elektromagnetische Vertraeglichkeit
About this Manual
20
EN European Norm
ESD Electrostatic Sensitive Device
FPGA Field-Programmable Gate Array
IPMB Intelligent Platform Management Bus
IPMC Intelligent Platform Management Controller
IPMI Intelligent Platform Management Interface
ISA Industry Standard Architecture
MAC Media Access Control
NEBS Network Equipment Building System
NVRAM Nonvolatile Random Access Memory
OEM Original Equipment Manufacturer
OOS Out-Of-Service
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
PEM Power Entry Module
PICMG PCI Industrial Computer Manufacturers Group
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About this Manual
Abbreviation Definition
PIM Power Input Module
PMC PCI Mezzanine Card
POST Power-On Self-Test
PROM Programmable Read-Only Memory
RTC Real Time Clock
RTM Rear Transition Module
RoHS Restriction of the use of Certain Hazardous Substances
SAS Serial Attached SCSI
SATA Serial ATA
SCSI Small Computer System Interface
SDR Sensor Data Record
SMI Serial Management Interface
SOL Serial-over-LAN
SPD Serial Presence Detect
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SSC Spread Spectrum Clocking

Conventions

The following table describes the conventions used throughout this manual.
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits are
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word Screen Used for on-screen output and code related elements
0 through F), for example used for addresses and offsets
or commands in body text
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About this Manual
Notation Description Courier + Bold Used to characterize user input and to separate it
Reference Used for references and for table and figure
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys
[text] Notation for software buttons to click on the screen
... Repeated item for example node 1, node 2, ..., node
About this Manual
from system output
descriptions
and parameter description
12
. . .
.. Ranges, for example: 0..4 means one of the integers
| Logical OR
Omission of information from example/command that is not necessary at the time being
0,1,2,3, and 4 (used in registers)
Indicates a hazardous situation which, if not avoided, could result in death or serious injury
Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury
Indicates a property damage message
No danger encountered. Pay attention to important information
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Summary of Changes

Part Number Publication Date Description
6806800T17A February 2015 Initial Version
About this Manual
ATCA-7480 Installation and Use (6806800T17A)
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About this Manual
About this Manual
24
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Safety Notes

This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.
Artesyn Embedded Technologies intends to provide all necessary information to install and handle the product in this manual. Because of the complexity of this product and its various uses, we do not guarantee that the given information is complete. If you need additional information, ask your Artesyn Embedded Technologies representative.
The product has been designed to meet the standard industrial safety requirements. It must not be used except in its specific area of office telecommunication industry and industrial control.
Only personnel trained by Artesyn Embedded Technologies or persons qualified in electronics or electrical engineering are authorized to install, remove or maintain the product.
The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel.
Keep away from live circuits inside the equipment. Operating personnel must not remove equipment covers. Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment.
Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided. Contact your local Artesyn Embedded Technologies representative for service and repair to make sure that all safety features are maintained.
EMC
The blade has been tested in a standard Artesyn Embedded Technologies system and found to comply with the limits for a Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class A respectively. These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment.
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Safety Notes
This is a Class A product based on the standard of the Voluntary Control Council for Interference by Information Technology Interference (VCCI). If this equipment is used in a domestic environment, radio disturbance may arise. When such trouble occurs, the user may be required to take corrective actions.
The blade generates and uses radio frequency energy and, if not installed properly and used in accordance with this guide, may cause harmful interference to radio communications. Operating the system in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.
The COM, ETH1, ETH2, USB1 and USB2 interfaces are considered as debug/maintenance ports. During normal operation no cables must be connected to these ports. Cables attached to these ports during maintenance must not exceed a length of 3m.

Installation

Damage of Circuits
Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life. Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment.
Data Loss
Removing the blade with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated, before removing the blade.
Restricted access area - This board is only to be installed in a restricted access area.
Damage of Blade and Additional Devices and Modules
Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation
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Safety Notes
System Damage
The intra building port(s) of the equipment or subassembly is suitable for connection to intra building wiring or cabling only (Type 2 or Type 4 ports as described in Telcordia GR-1089­CORE, Issue 6) and require isolation from the exposed OSP (Outside Plant) cabling.The addition of primary protectors is not sufficient protection in order to connect these interfaces metallically to OSP wiring. The intra building port(s) of the equipment or subassembly must not be metallically connected to interfaces that connect to the OSP or its wiring.

Operation

Ensure that the display devices that are permanently connected to the VGA interface provide
a fire enclosure according to the IEC/EN/UL/CSA 60950-1 requirements. All other devices that are connected only for service purposes to the VGA interface needs supervision during operation and must be disconnected after maintenance.
Blade Damage
Blade surface High humidity and condensation on the blade surface causes short circuits. Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power.
Blade Overheating and Blade Damage
Operating the blade without forced air cooling may lead to blade overheating and thus blade damage. When operating the blade, make sure that forced air cooling is available in the shelf.
When operating the blade in areas of electromagnetic radiation ensure that the blade is bolted on the system and the system is shielded by enclosure.
Injuries or Short Circuits
Blade or power supply
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Safety Notes
In case the O-Ring diodes of the blade fail, the blade may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit (and vice versa). To avoid damage or injuries, always check that there is no more voltage on the line that has been disconnected before continuing your work.
The EMI radiation compliancy of the product has been qualified in a reference system with 10
ATCA-7480 boards installed each with the Spread Spectrum feature enabled. Please note that the integrator needs to verify the EMI radiation compliancy of other configurations/settings (for example, Spread Spectrum disabled).

Switch Settings

Blade Malfunction
Switches marked as 'reserved' might carry production-related functions and can cause the blade to malfunction if their setting is changed. Therefore, do not change settings of switches marked as 'reserved'. The setting of switches which are not marked as 'reserved' has to be checked and changed before blade installation.
Blade Damage
Setting/resetting the switches during operation can cause blade damage. Therefore, check and change switch settings before you install the blade.

Battery

Blade Damage
Wrong battery installation may result in hazardous explosion and blade damage. Therefore, always use the same type of Lithium battery as is installed and make sure the battery is installed as described in this manual.
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Environment

Always dispose of used blades, system components and RTMs according to your country’s legislation and manufacturer’s instructions.
Safety Notes
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Safety Notes
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Sicherheitshinweise

Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind. Wenn Sie diese Vorsichtsmaßnahmen oder Sicherheitshinweise, die an anderer Stelle diese Handbuchs enthalten sind, nicht beachten, kann das Verletzungen oder Schäden am Produkt zur Folge haben.
Artesyn Embedded Technologies ist darauf bedacht, alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handbuch bereit zu stellen. Da es sich jedoch um ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren. Falls Sie weitere Informationen benötigen sollten, wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn Embedded Technologies.
Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden.
Einbau, Wartung und Betrieb dürfen nur von durch Artesyn Embedded Technologies ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden. Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu, das Wissen von Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.
Halten Sie sich von stromführenden Leitungen innerhalb des Produktes fern. Entfernen Sie auf keinen Fall Abdeckungen am Produkt. Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen, um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen.
Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für Sie zuständige Geschäftsstelle von Artesyn Embedded Technologies. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.
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Sicherheitshinweise
EMV
Das Blade wurde in einem Artesyn Embedded Technologies Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Blades in Gewerbe- sowie Industriegebieten gewährleisten.
Das Blade arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im Hochfrequenzbereich auftreten.
Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen. In diesem Fall kann vom Betreiber verlangt werden, angemessene Maßnahmen durchzuführen.
Die nachfolgend aufgeführten Schnittstellen sind Wartungsschnittstellen: COM, ETH1, ETH2, USB1, USB2. Während des Normalbetriebs darf an diesen Schnittstellen kein Kabel angeschlossen sein. Im Wartungsfall angeschlossene Kabel dürfen eine Länge von 3m nicht überschreiten.

Installation

Beschädigung von Schaltkreisen
Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau von Blades kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen. Bevor Sie Blades oder elektronische Komponenten berühren, vergewissern Sie sich, daß Sie in einem ESD-geschützten Bereich arbeiten.
Bereich mit eingeschränktem Zugang - Installieren Sie das Board in ein System nur in Bereichen
mit eingeschränktem Zugang.
Datenverlust
Wenn Sie das Blade aus dem Shelf herausziehen, und die blaue LED blinkt noch, gehen Daten verloren. Warten Sie bis die blaue LED durchgehend leuchtet, bevor Sie das Blade herausziehen.
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Beschädigung des Blades und von Zusatzmodulen
Fehlerhafte Installation von Zusatzmodulen, kann zur Beschädigung des Blades und der Zusatzmodule führen. Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation.
Beschädigung des Systems
Die Gebäude-internen Schnittstellen ("intra-building ports" per Telcordia GR-1089-CORE 6 Issue 6) der Geräte oder Baugruppen sind nur für gebäudeinterne Verkabelung vorgesehen. Die Schnittstellen sind als Typ 2 oder Typ 4 definiert (wie in GR-1089-Core beschrieben) und erfordern eine Isolation zu Leitungen außerhalb des Gebäudes. Die Gebäude-internen Schnittstellen dürfen keine elektrisch leitende Verbindung zu Leitungen außerhalb des Gebäudes haben. Ein "Primary Protector" (wie in GR-1089-CORE beschrieben) ist keine ausreichende Absicherung, um die Gebäude-internen Schnittstellen mit Leitungen außerhalb des Gebäudes zu verbinden.
Sicherheitshinweise

Betrieb

Stellen Sie sicher, daß Geräte, die dauerhaft mit der VGA Schnittstelle verbunden, sind über ein
Brandschutzgehäuse verfügen, die die Anforderungen der IEC/EN/UL/CSA 60950-1 Norm erfüllen. Alle anderen Geräte, die nur zeitweise für Wartungsarbeiten an die VGA Schnittstelle angeschlossen werden, müssen während dem Betrieb überwacht und nach der Beendigung der Wartungsarbeiten entfernt werden.
Beschädigung des Blades
Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen. Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Blade kein Kondensat befindet.
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Sicherheitshinweise
Überhitzung und Beschädigung des Blades
Betreiben Sie das Blade ohne Zwangsbelüftung, kann das Blade überhitzt und schließlich beschädigt werden. Bevor Sie das Blade betreiben, müssen Sie sicher stellen, dass das Shelf über eine Zwangskühlung verfügt.
Wenn Sie das Blade in Gebieten mit starker elektromagnetischer Strahlung betreiben, stellen Sie sicher, dass das Blade mit dem System verschraubt ist und das System durch ein Gehäuse abgeschirmt wird.
Verletzungen oder Kurzschlüsse
Blade oder Stromversorgung Falls die ORing Dioden des Blades durchbrennen, kann das Blade einen Kurzschluss zwischen den Eingangsleitungen A und B verursachen. In diesem Fall ist Leitung A immer noch unter Spannung, auch wenn sie vom Versorgungskreislauf getrennt ist (und umgekehrt). Prüfen Sie deshalb immer, ob die Leitung spannungsfrei ist, bevor Sie Ihre Arbeit fortsetzen, um Schäden oder Verletzungen zu vermeiden.
Die Messung der EMV Abstrahlung wurde in einem Referenzsystem mit 10 ATCA-7480 Boards
ermittelt, bei denen die "Spread Spectrum" Funktion eingeschalten war. Der Integrator ist dafür verantwortlich, daß seine Konfiguration die EMV Anforderungen erfüllt (z.B. mit einer abweichenden Anzahl von ATCA-7480 Boards oder mit ausgeschalteter "Spread Spectrum" Funktion).

Schaltereinstellungen

Fehlfunktion des Blades
Schalter, die mit 'Reserved' gekennzeichnet sind, können mit produktionsrelevanten Funktionen belegt sein. Das Ändern dieser Schalter kann im normalen Betrieb Störungen auslösen. Verstellen Sie nur solche Schalter, die nicht mit 'Reserved' gekennzeichnet sind. Prüfen und ändern Sie die Einstellungen der nicht mit 'Reserved' gekennzeichneten Schalter, bevor Sie das Blade installieren.
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Beschädigung des Blades
Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des Blades führen. Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Blade installieren.

Batterie

Beschädigung des Blades
Ein unsachgemäßer Einbau der Batterie kann gefährliche Explosionen und Beschädigungen des Blades zur Folge haben. Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung.

Umweltschutz

Sicherheitshinweise
Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers.
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Sicherheitshinweise
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Introduction

1.1 Features

The ATCA-7480 is a high-performance ATCA compliant single board computer designed for demanding storage and processing applications.
The main features of the ATCA-7480 board are as follows:
Designed for NEBS level 3
Dual socket Intel Xeon E5-2600 V3 (Haswell-EP socket LGA2011-3)
Standard ATCA-7480 configuration:
– Intel Xeon E5-2648L V3 12-cores 1.8GHz 75W
– Intel Xeon E5-2618L V3 8-cores 2.3GHz 75W (optional)
– Intel Xeon E5-2658 V3 12-cores 2.2GHz 105W (optional)
Chapter 1
– DDR4 memory support up to 2133MT/s
– Four independent DDR4 memory channels per CPU with two DIMM slots per channel
(2 DPC) resulting in a total of 16 DIMM slots
– 8GB and 16GB DDR4 modules in VLP available
Single slot ATCA form factor (280mm x 322mm)
Direct CPU to PCIe interface providing 40 PCIe Gen3 lanes (8 Gbps)
Next Generation Communications Platform from Intel, codename Grantley with on-board
Intel C612 Wellsburg Platform controller Hub (PCH)
Intel QuickAssist Technology support for advanced Datapacket processing on RTM Coleto
Creek Devices
Dual Gb Ethernet AdvancedTCA Base Interfaces according to PICMG 3.0 based on Intel
i350 Powerville
Quad 40GBASE-KR4,10GBASE-KR,10GBASE-KX4,1000Base-KX: Option1, 1-K,1-KR,9,9-
K,9-KR Ethernet AdvancedTCA Fabric Interfaces according to PICMG 3.1 based on Intel XL710 Forteville
Dual Gb Ethernet ports on Faceplate (Intel i350 Powerville)
Serial over LAN via AdvancedTCA base Interface
CPU and I/O virtualization support
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Introduction
Power management support
Crisis recovery for BIOS, IPMC Firmware, and FPGA code
MO-297/SlimSATA module Carrier slot to carry up to three MO297 type SSD module
drives

1.2 Mechanical Data

The following table provides details about the mechanical data of the blade.
Table 1-1 Mechanical Data
Feature Value
Height 322.25 mm +0/-0.3mm
Length 280 mm +0/-0.3 mm
Thickness 2.4 mm + 0.2mm
Mounting height top side (component side 1)
Mounting height bottom side (component side 2)
Weight ATCA-7480-0GB(-L): 3.5kg
21.33 mm
1.61 mm
ATCA-7480-0GB-H: 3.6kg
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1.3 Product Identification

The following figure shows the location of the serial number label.
Figure 1-1 Serial Number Location
Introduction
P30
J11 DIMM 1

1.4 Ordering Information

P30
P20
ZONE 1
P31
P32
P22
P23
Serial Number
The ATCA-7480 is a high performance ATCA compliant single board computer designed for demanding storage and processing applications.
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Introduction
The following table lists the blade variants that are available upon release of this publication. Consult your local Artesyn Embedded Technologies sales representative for the availability of other variants.
Table 1-2 Blade Variants
Product Name Description
ATCA-7480-0GB ATCA-7480 Blade with Dual Intel Xeon E5-2648L V3 12-Core @1.8GHz
ATCA-7480-0GB-L ATCA-7480 Blade with Dual Intel Xeon E5-2618L V3 8-Core @2.3GHz
ATCA-7480-0GB-H ATCA-7480 Blade with Dual Intel Xeon E5-2658 V3 12-Core @2.2GHz
processors (Haswell-EP 75W TDP), 2.5MB per Core Last Level Cache, 256KB L2 Cache per core, 32Kb+32KB L1 Cache per core; 16 DIMM sockets; no memory preinstalled.
processors (Haswell-EP 75W TDP), 2.5MB per Core Last Level Cache, 256KB L2 Cache per core, 32Kb+32KB L1 Cache per core; 16 DIMM sockets; no memory preinstalled.
processors (Haswell-EP 105W TDP), 2.5MB per Core Last Level Cache, 256KB L2 Cache per core, 32Kb+32KB L1 Cache per core; 8 DIMM sockets; no memory preinstalled.
40
The following table lists the blade accessories that are available upon release of this publication. Consult your local sales representative for the availability of other accessories.
Table 1-3 Blade Accessories
Accessory Description
ATCA-7480MEM-2133-8G 8GB DDR4-2133 (PC4-2133) VLP memory module
ATCA-7480MEM-2133-16G 16GB DDR4-2133 (PC4-2133) VLP memory module
ATCA-748XMMOD-KIT ATCA-7480 carrier module
ATCA-7XMMOD-SATA3 MO-297 solid state drive 128 GB
ATCA-7XMMOD-SATA4 MO-297 solid state drive 256GB (3Gb/s)
ATCA-7XMMOD-SATA5 MO-297 solid state drive 256GB (6Gb/s)
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The following figure is a copy of Declaration of Conformity for ATCA-7480.
Figure 1-2 Declaration of Conformity
Introduction
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Introduction
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Hardware Preparation and Installation

2.1 Unpacking and Inspecting the Blade

Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life. Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment.
Shipment Inspection
Chapter 2
To inspect the shipment, perform the following steps.
1. Verify that you have received all items of your shipment:
ATCA-7480 blade
Any optional items ordered
2. Check for damage and report any damage or differences to the customer service.
3. Remove the desiccant bag shipped together with the blade and dispose of it according to your country’s legislation.
The blade is thoroughly inspected before shipment. If any damage has occurred during transportation or any items are missing, contact our customer's service immediately.

2.2 Environmental and Power Requirements

In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed.
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Hardware Preparation and Installation
Before you power up the blade, calculate the power needed according to your combination of blade upgrades and accessories.

2.2.1 Environmental Requirements

The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment.
The environmental requirements of the blade may be further limited down due to
installed accessories, such as hard disks or PMC modules, with more restrictive environmental requirements.
Operating temperatures refer to the temperature of the air circulating around the
blade and not to the actual component temperature.
44
Blade Damage Blade Surface High humidity and condensation on the blade surface causes short circuits. Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power.
Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage. When operating the blade, make sure that forced air cooling is available in the shelf.
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Hardware Preparation and Installation
Table 2-1 Environmental Requirements
Requirement Operating Non-Operating
Temperature Normal Operation: +5 °C (41 °F) to +40
°C (104 °F) according to Telcordia GR­63-CORE (NEBS) and ETSI EN 300 019­1-3, Class 3.1
Exceptional Operation: -5 °C (23 °F) to +55 °C (131 °F) according to Telcordia GR-63-CORE (NEBS)
Note: This exceeds ETSI EN 300 019-1­3, Class 3.1E requirements (-5°C to +45°C)
Temp. Change +/- 0.25 °C/min according to Telcordia
GR-63-CORE
Rel. Humidity Normal Operation: 5%rH to 85%rh non-
condensing Exceptional Operation: 5%rH to 90%rh
non-condensing According to Telcordia GR-63-CORE
(NEBS) and EN 300 019-1-3, Classes 3.1 and 3.1E
Vibration 1g from 5 to 200Hz and back to 5Hz at
a rate of 0.25 octave/minute (according to Telcordia GR-63-core)
Shock Half-sine, 11 ms, 30 m/s
2
Free Fall - 1.2 m/ packaged (according to ETSI 300
-40 °C (-40 °F) to +70 °C (158 °F) according to Telcordia GR-63-CORE (NEBS) and ETSI EN 300 019-1-2, Class 2.3
Note: This exceeds ETSI EN 300 019-1-1, Class 1.2 requirements (storage from ­25 °C (-13 °F) to +55 °C (131 °F) Note: This may be further limited by installed accessories.
+/- 0.25 °C/min
5% to 95% non-condensing according to Telcordia GR-63-CORE (NEBS) and EN 300 019-1-1, Classes 1.2 and 2.3
5-20 Hz at 0.01 g
2
/Hz (according to Telcordia GR-63-core and ETSI EN 300 019-2-2) 20-200 Hz at -3 dB/octave Hz (according to Telcordia GR-63-core and ETSI EN 300 019-2-2)
Random 5-20Hz at 1 m Random 20-200Hz at 3 m2/s
2/s3
3
Blade level packaging Half-sine, 6 ms at 180 m/s
2
019-2-2) 100 mm unpackaged (according to
Telcordia GR-63-core)
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Hardware Preparation and Installation
During the safety qualification of this blade, the following on-board locations were identified as critical with regards to the maximum temperature during blade operation. To guarantee proper blade operation and to ensure safety, you have to make sure that the temperatures at the locations specified in the Figure 2-1 are not exceeded. If not stated otherwise, the temperatures should be measured by placing a sensor exactly at the given locations.
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)
46
Temperature Spot 2 (48 V to 12 V DC DC)
Temperature Spot 1 PIM
Exact locations of critical temperature spots:
1. On the PIM (U34) (On top of the transformer). Maximum up to 90oC.
2. On the 48V/12V DC/DC (U35) (on the PCB, next to the transformer). Maximum up to 125oC.
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Table 2-2 Critical Temperature Limits
Thermal Design
Component
All product variants using the following processor:
Intel Xeon E5-2648L V3
All product variants using the following processor:
Intel Xeon E5-2618L V3
All product variants using the following processor:
Intel Xeon E5-2658 V3
Power Max Case or Junction Temperature
75W Tj.max ~87
75W Tj.max ~87
105W Tj.max ~87
Hardware Preparation and Installation
o
C (CPU specific and readable in
TEMPERATURE_TARGET register)
o
C (CPU specific and readable in
TEMPERATURE_TARGET register)
o
C (CPU specific and readable in
TEMPERATURE_TARGET register)
If you integrate the blade in your own system, contact your local sales representative for further safety information.

2.2.2 Power Requirements

The blade's power requirements depend on the installed hardware accessories. If you want to install accessories on the blade, the load of the respective accessory has to be added to that of the blade. In the following table you will find typical examples of power requirements with and without accessories installed. For information on the accessories' power requirements, refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details.
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Hardware Preparation and Installation
The blade must be connected to a TNV-2 or a safety-extra-low-voltage (SELV) circuit. A TNV-2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions, and which is not subject to over voltages from telecommunication networks.
Table 2-3 Power Requirements
Characteristic Value
Rated Voltage Exception in the US and Canada
Operating Voltage Exception in the US and Canada
-48 VDC to -60 VDC
-48 VDC
-39 VDC to -72 VDC
-39 VDC to -60 VDC
The following table provides information about the maximum power consumption of ATCA­7480 all variants equipped with DIMIs, SSDs, and RTM-ATCA-748x-40G including 4x QSFP. The table also contains power consumption details of blade without any RTM.
Table 2-4 Power Consumption of ATCA-7480 with and without RTM
Blade Variant Configuration
ATCA-7480 variant with 75W 12-cores processors and 16 DIMM sockets (ATCA-7480­xGB)
ATCA-7480 variant with 75W 8-cores processors and 16 DIMM sockets (ATCA-7480­xGB-L)
ATC A-7480 variant with 105W 12-cores processors and 8 DIMM sockets (ATCA-7480­xGB-H)
With RTM-ATCA-748x-40G 289W 258W
Without any RTM 273W 241W
With RTM-ATCA-748x-40G 255W 229W
Without any RTM 238W 196W
With RTM-ATCA-748x-40G 337W 289W
Without any RTM 332W 268W
Max. Power Consumption
Typ. Power Consumption
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Hardware Preparation and Installation
The blade provides two independent power inputs according to the AdvancedTCA Specification. Each input has to be equipped with an additional fuse of maximum 90 A located either in the shelf where the blade is installed or the power entry module (PEM).
The power consumption has been measured using specific boards in a configuration considered to represent the worst-case (maximum memory population, 3x MO297 SSD modules, with RTM-ATCA-748X-40G and QSFPs) and with software simultaneously exercising as many functions and interfaces as possible. This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification.
Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation. Depending on the actual operating configuration and conditions, customers may see slightly higher power dissipation, or it may even be significantly lower. There is also a dependency on the batch variance of the major components like the processor and DIMMs used. Hence, Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards.
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Hardware Preparation and Installation

2.3 Blade Layout

The following figure shows the location of components on the ATCA-7480:
Figure 2-2 ATCA-7480 Blade Layout
J28 DIMM 8 J27 DIMM 7 J26 DIMM 6
J25 DIMM 5
J21 DIMM 1
J22 DIMM 2 J23 DIMM 3 J24 DIMM 4
FPGA
Intel C612 PCH (Wellsburg)
Intel i350 Powerville
MO-297 Carrier
J15 DIMM 5
J16 DIMM 6
J17 DIMM 7
J18 DIMM 8
48V to 12V DCDC
J11 DIMM 1
P30
P20
ZONE 1
P30
P31
ZONE 3
P32
Zone 2 (Update Channel)
P22
Zone 2 (Base- and Fabric-IF)
P23
RTM 12V Power
PCIe Gen3 Retimer
Intel XL710 #2 (Forteville)
Intel XL710 #1 (Forteville)
ATCA PIM
J11 DIMM 1
J12 DIMM 2
J13 DIMM 3
J14 DIMM 4
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2.4 Switch Settings

All mechanical switches are OFF in their default configuration. Switch selection used only for debugging are grouped in separate devices, which are not assembled in volume production. Switches reside on the component side 1 and are not covered by any other component. Their location is shown in the following figure:
Figure 2-3 Switch Location (Bottom Side of the Blade)
Hardware Preparation and Installation
Table 2-5 Switch SW1 settings
Switch Function Default
SW1.1 A2F200 JTAG_SEL strap
OFF= JTAG to Fabric (Default) ON= JTAG to CPU-Core
SW1.2 BIOS Image Swap OFF Default Image
SW1.3 TSOP or Debug-Socket SPI Boot
select OFF= Boot from TSOP SPI Flash (either
Default/Recovery) ON = Boot from Debug Socket SPI
Flash
ATCA-7480 Installation and Use (6806800T17A)
OFF A2F200 JTAGSEL
ON=secondary Image in 16MB device
OFF Boot from BIOS
Socket
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Table 2-5 Switch SW1 settings (continued)
Switch Function Default
SW1.4 Reserved. Connected to FPGA OFF Reserved
Table 2-6 Switch SW2 Settings
Switch Function Default
SW2.1 Serial Line #1 and #2 Routing
OFF=FPGA-COM#1 to Faceplate FPGA-COM#2 to RTM ON= FPGA-COM#1 to RTM FPGA-COM#2 to Faceplate
SW2.2 SW2.2IPMC Debug Console Routing
OFF= IPMC Debug Console at 3-pin Header ON= IPMC Debug Console at Faceplate instead of
FPGA COM
SW2.3 FPGA_PROM_SEL
OFF = 0 (default PROM) ON = 1 (Backup/Recovery PROM)
SW2.4 OFF = Reset push button enabled
ON = Reset push button disabled
OFF OFF: COM1 routing to
OFF IPMC Debug Console
OFF Use standard download
ON Disable faceplate reset
Table 2-7 Switch SW3 Settings
Switch Function Default
SW3.1 manual "Default SPI Boot Flash" / "Recovery SPI
Boot Flash" select enable. ON: SW3.2 selects Boot Flash
OFF IPMI selects Boot Flash
Fac epl ate IPMC setting wins
always
(TTL-level) routing
OFF: IPMC Debug Console at 3-pin Header
PROM or redundant download PROM for FPGA configuration
push button
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SW3.2 SW3.2 controls Boot flash select if SW3.1 is ON
OFF = Boot from "Default SPI Boot Flash" device ON= Boot from "Recovery SPI Boot Flash" device
ATCA-7480 Installation and Use (6806800T17A)
OFF OFF = Boot from "Default
SPI Boot Flash" device
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Hardware Preparation and Installation
Table 2-7 Switch SW3 Settings (continued)
Switch Function Default
SW3.3 Debug Output to Serial Console OFF [SW3.4, SW3.3]
SW3.4 Load BIOS defaults OFF

2.5 Installing the Blade Accessories

The following additional components are available for the blade:
Dual Inline Memory Module (DIMM)
MO297 SSD Module
00 - Normal operation, 01- Load Bios Defaults, 10 - Crisis recovery, 11 - Pot80 to COM1
Rear transition modules
They are described in detail in the following sections. For order numbers, refer to section
Ordering Information on page 39.

2.5.1 DIMM Memory Modules

The blade provides 16 memory slots for main memory DIMM modules of type DDR4 VLP. You may install and/or remove DIMM memory modules in order to match the main memory size to your needs. The corresponding installation/removal procedures are described in this section.
For the location of the DIMM Memory modules, see Figure "ATCA-7480 Blade Layout" on page
50.
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Hardware Preparation and Installation
Each processor provides four memory channels with two DIMM sockets each. When installing DIMM memory modules, the DIMM sockets, which are farthest away on each memory channel from the CPU device, need to be populated first:
Table 2-8 DIMM Sockets
Memory
CPU
CPU#0 A J11 J12
CPU#1 E J21 J22
channel
B J13 J14
C J15 J16
D J17 J18
F J23 J24
G J25 J26
H J27 J28
Primary Secondary
DIMM socket
For optimal performance, all memory channels A through H should be populated and also a balanced DIMM configuration is recommended; that is, every memory channel using the same type and amount of DIMMs. In case of using only one DIMM per channel, make sure that you use only primary sockets and leave the secondary sockets empty.
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Only qualified DDR4 DIMMs (Single Ranked or Dual Ranked RDIMM) are allowed; because of the thermal limit/budget of the blade and the high variation of the power consumptions of different DIMM types. For thermal reasons, no 4-rank DIMMs and no dual-Die DIMM are allowed.
Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.
Installation Procedure
To install a DIMM module, proceed as follows:
1. Remove blade from system as described in Installing and Removing the Blade on
page 58.
2. Open locks of memory module socket.
3. Press module carefully into socket. As soon as the memory module has been fully inserted, the locks automatically close.
4. If applicable, repeat steps 2 to 3 to install further modules.
Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.
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Hardware Preparation and Installation
Removal Procedure
To remove a DIMM module, proceed as follows:
1. Remove blade from system as described in Installing and Removing the Blade on
page 58.
2. Open locks of socket at both sides. The memory module is automatically lifted up.
3. Remove module from socket.
4. Repeat steps 2 to 3 in order to remove further memory modules.

2.5.2 SSD Carrier and MO297 SSD Modules

ATCA-7480 provides a modular solution for up to three MO297-A compliant SSDs. Each SSD is connected to the Intel Wellsburg PCH via a SATA interface. The modular approach consists of a riser card, which provide up to three sockets for SSDs and the MO297-A compliant SSDs.
56
The SD module is an accessory kit and is not part of the default ATCA-7480. The following procedure describes the steps to install/remove the MO297-A compliant SSD module.
Before mounting the storage on ATCA-7480, the riser card and SSDs should be pre­mounted.
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Hardware Preparation and Installation
Installation Procedure
To install an MO297-A SSD module, proceed as follows:
Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.
1. Remove the blade from the system as described in Installing and Removing the Blade
on page 58.
2. Plug the SSD module into the MO297-A connector. When inserting the MO297-A module to the on-board connector, hold the on-board connector with two fingers to prevent damage to the connector.
3. Fasten the SSD module to the blade using the screws supplied with the ACC kit.
4. Reinstall the blade into the system as described in Installing and Removing the Blade
on page 58.
The additional resource (either memory or SATA SSD) will be detected automatically during the boot-up sequence.
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Hardware Preparation and Installation
Removal Procedure
To remove an MO297-A SSD module, proceed as follows:
Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.
1. Remove the blade from the system as described in Installing and Removing the Blade
on page 58.
2. Remove the two screws holding the
3. Remove the
SSD module from the blade.
SSD module.
4. Reinstall the blade into the system as described in Installing and Removing the Blade
on page 58.

2.6 Installing and Removing the Blade

The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves.
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The blade can be installed in any AdvancedTCA node slot. Do not install it in an AdvancedTCA hub slot.
Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life. Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment.
Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the faceplate but use the handles.

2.6.1 Installing the Blade

The following procedure describes the installation of the blade. It assumes that your system is powered on. If your system is not powered on, you can disregard the blue LED and skip the respective step. In this case, it is purely a mechanical installation.
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Hardware Preparation and Installation
Installation Procedure
To install the blade into an ATCA shelf:
1. Visually inspect the blade and backplane connectors for damage or bent pins before attempting to insert a blade. If any connector damage or pin damage is observed, stop inserting the blade and send the damaged item to proper repair channels.
Latch
Handle
60
2. Slide the latch into the release position and pull out the handle outward to unlatch the handle from the faceplate. Do not rotate the handle fully outward.
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3. Insert the blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf. Make sure that the guiding module of shelf and blade are aligned properly.
4. Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance. Continue to push the blade gently until the blade connectors engage.
5. Fully insert the blade and turn the handle towards the faceplate. The latch automatically slides inwards and locks the handle.
If you feel that you need an abnormal amount of force during blade insertion into the slot, please extract the blade, then carefully inspect the blade and slot for problems to prevent damage.
If your shelf is powered, as soon as the blade is connected to the backplane power pins, the blue LED is illuminated.
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Hardware Preparation and Installation
When the blade is completely installed, the blue LED starts to blink. This indicates that the blade has signified its presence to the shelf management controller.
If an RTM is connected to the front blade, make sure that the handles of both the RTM and the front blade are closed in order to power up the blade’s payload.
6. Wait until the blue LED is switched off, then fasten the faceplate screws, which secure the blade to the shelf. When the blue LED is switched OFF and the green LED (IS) is switched ON, this indicates that the payload has been powered up and the blade is active.
7. Connect cables to the faceplate, if applicable.

2.6.2 Removing the Blade

This section describes how to remove the blade from an AdvancedTCA system.
Damage of Circuits Electrostatic discharge, incorrect blade installation and removal can damage circuits or shorten their life. Before touching the blade or electronic components, make sure that you are working in an ESD-safe environment.
Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the faceplate, instead use the handles.
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Hardware Preparation and Installation
Removal Procedure
The following procedure describes how to remove the blade from a shelf. It assumes that the system is powered on. If the system is not powered on, you can disregard the blue LED and skip the respective steps. In that case, it is purely a mechanical procedure.
1. Unlatch the handle from the faceplate by sliding the latch into the release position and pull out the handle outward. Do not rotate the handle fully outward. The blue LED starts blinking indicates that the blade power-down process is ongoing.
2. Wait until the blue LED is illuminated permanently. Loosen the screws of the faceplate, then unlatch the handle and rotate the handle fully outward until the blade is detached from the shelf.
If the LED continues to blink, a possible reason may be that the upper layer software has rejected the blade extraction request.
Data Loss Removing the blade with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated before removing the blade.
3. Remove the faceplate cables, if applicable.
4. Loosen the screws of the faceplate until the blade is detached from the shelf.
5. Remove the blade from the shelf.
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Controls, Indicators, and Connectors

3.1 Faceplate

The following figure illustrates the connectors, keys, and LEDs available on the faceplate:
Figure 3-1 Faceplate
Chapter 3
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Controls, Indicators, and Connectors

3.1.1 LEDs

The LEDs on the faceplate are described in the following table:
Table 3-1 Faceplate LEDs
LED Description
OOS Out Of Service
Red/optional Amber (controllable by IPMC): This LED is controlled by higher layer software, such as middle ware or applications.
IS Payload Power Status
Green: The payload power has been enabled by the IPMC. Note that this LED indicates the payload power status both in the early power state and the normal blade operation.
OFF: Payload power is disabled Note: This LED is multicolored (red/green/yellow) and is programmable by
IPMC.
66
ATN Amber: This LED is controlled by higher layer software, such as middle ware or
applications.
ETH Status LEDs The Ethernet connector provides two status LEDs
Link (upper) Green: Link is available Off: No link Activity (lower) Yellow: Activity Off: No activity
U1, U2 Base interface activity is visualized via FPGA LEDs U1 and U2
U3 User LED, selectable color via FPGA register.
Colors: Red, Green, Amber
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Table 3-1 Faceplate LEDs (continued)
LED Description
H/S FRU State Machine

3.1.2 Keys

The blade provides one faceplate reset key.
Controls, Indicators, and Connectors
During blade installation:
Permanently blue: On-board IPMC powers up Blinking blue: Blade communicates with shelf manager OFF: Blade is active
During blade removal:
Blinking blue: Blade notifies shelf manager of its desire to deactivate Permanently blue: Blade is ready to be extracted
On pressing it, a hard reset is triggered and all attached on-board devices are reset.
You cannot reset the IPMC via this key.

3.1.3 Connectors

The blade provides the following connectors at its faceplate:
2x Ethernet
1x Serial
2x USB 3.0/USB 2.0
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Controls, Indicators, and Connectors
3.1.3.1 Serial COM#1 P17
Serial line interface #1 of Glue Logic FPGA is available at the faceplate of ATCA-7480. A female RJ45 connector is used for serial line connection. The pinout in the following table is used according to the Cisco-like Pinout. Additionally, Hardware Handshake support signals are available.
Table 3-2 RJ45 female Serial Line Connector pinout
Pin Signal
1 COM1_CTS
2 COM1_DTR
3 COM1_RS232_TXD
4GND
5GND
6 COM1_RS232_RXD
7 COM1_DSR
8 COM1_RTS
3.1.3.2 Ethernet Connector
There are two Ethernet connectors:
ETH1 connector P70
ETH2 connector P71
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The pinout of the connector is shown in the following figure.
Figure 3-2 Ethernet Interface Connectors Pinout
3.1.3.3 Serial Interface Connector
Controls, Indicators, and Connectors
The blade provides one RS-232 serial interface connector at its faceplate. It is of type RJ-45 and corresponds to the physical serial interface port 1. By default, the BIOS maps this interface to the serial interface COM1. The on-board switch 2-1 allows to swap COM1 with COM2, making COM2 accessible through the faceplate connector instead. Note that the BIOS serial redirection feature uses COM1 as access interface. Therefore, swapping the serial interfaces via SW2-1 also changes the serial connector that you need to access to make use of the serial redirection feature.
The pinout of the serial interface connector is shown below.
Figure 3-3 Serial Interface Connector Pinout
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Controls, Indicators, and Connectors
3.1.3.4 USB 3.0 Connectors
The blade provides two USB 3.0 connectors at its faceplate and one USB at RTM (zone 3) interface. The USB connectors at faceplate are compliant to the USB 3.0 standard and correspond to the blade's USB interfaces 3 and 4. The USB at RTM interface is compliant to USB
2.0.
The pinout of each USB connector is shown in the following figure.
Figure 3-4 USB Connector Pinout
Attaching a device to the front panel USB ports that exceeds the maximum USB current rating of 500mA per port will result in the ATCA-7480 protecting itself through a controlled board shutdown.

3.2 On-board Connectors

The blade provides the following on-board connectors:
MO297 SSD module carrier connector

3.2.1 MO297 SSD Module Carrier Connector

The MO297 SSD module Carrier (Riser card) connects three SATA interfaces of the Wellsburg PCH to three slots of standard MO297 type SSD flash discs. This carries the following types of signals:
3 SATA port (from PCH)
Power supply 5V and 3.3V
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The location of the MO297 SSD module carrier/riser is illustrated in the following figure.
Figure 3-5 Location of MO297 SSD Module Connector
P30
P31
MO-297 Carrier
J11 DIMM 1
P30
P32
P20
P22
P23
ZONE 1
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The pinout of this connector is illustrated in the following figure.
Figure 3-6 MO297 SSD Module Carrier Connector Pinout
Table 3-3 Signal Segment Pinout
Pin Number Function Description
S1 GND 2
S2 A+ Differential singal Pair A
nd
mate
72
S3 A-
nd
nd
mate
mate
S4 GND 2
S5 B- Differential signal Pair B
S6 B+
S7 GND 2
Table 3-4 Power Segment Pinout
Pin Number Function
P1 Not used (3.3V)
P2 Not used (3.3V)
P3 Not used (3.3V Pre-
Charge)
P4 GND
P5 GND
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Table 3-4 Power Segment Pinout (continued)
Pin Number Function
P6 GND
P7 5V Pre-Charge
P8 5V
P9 5V
P10 GND
P11 RESERVED
P12 GND
P13 Not used (12V Pre-
Charge)
P14 Not used (12V)
P15 Not used (12V)
Controls, Indicators, and Connectors
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3.3 AdvancedTCA Backplane Connectors

The AdvancedTCA backplane connectors reside in three zones 1 to 3 as specified by the AdvancedTCA standard, and are called P10, P20 and P23, P30, P31 and P32. The pinouts of all these connectors are given in this section.
Figure 3-7 Location of AdvancedTCA Connectors
P30
P31
P30
P32
74
P20
P22
P23
J11 DIMM 1
ZONE 1
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The connector residing in zone 1 is called P10 and it carries the following signals:
Power feed for the blade (VM48_x_CON and RTN_x_CON)
Power enable (ENABLE_x)
IPMB bus signals (IPMB0_x_yyy)
Geographic address signals (HAx)
Ground signals (SHELF_GND and GND)
Reserved signals
Figure 3-8 P10 Backplane Connector Pinout
Zone 2 contains the two connectors P20 and P23. They carry the following types of signals:
Telecom clock signals (CLKx_)
Base interface signals (BASE_)
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SAS update channel
100Base-BX update channel
Some of the pins provided by P20 and P23 are defined as optional in the AdvancedTCA specification and are unused on the blade. If the AdvancedTCA specification defines these signals as input signals, they are terminated on the blade and marked as “TERM_” in the following pinouts. In all other cases the pins are unconnected and consequently marked as "n.c.".
The pinouts of P20 and P23 are as follows.
Figure 3-9 P20 Backplane Connector Pinout - Rows A to D
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Figure 3-10 P20 Backplane Connector Pinout - Rows E to H
Figure 3-11 P23 Backplane Connector Pinout - Rows A to D
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Figure 3-12 P23 Backplane Connector Pinout - Rows E to H
Zone 3 contains the three connectors P30, P31, and P32. They are used to connect an RTM to the blade and carry the following signals:
78
Serial (RS232_x_yyyy)
Serial ATA (SATAx_yyy)
USB (USBxy)
PCI Express (PCIEx_yyy)
IPMI (IPMB1_xxx, ISMB_xxx)
Power (VP12_RTM, V3P3_RTM, VP5_RTM)
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SAS Update channels
General control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY-, RTM_RST-)
Figure 3-13 P30 Backplane Connector Pinout - Rows A to D
Figure 3-14 P30 Backplane Connector Pinout - Rows E to H
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Figure 3-15 P31 Backplane Connector Pinout - Rows A to D
a
PCIE_CPU1_P3_RX_P<0>
1
PCIE_CPU1_P3_RX_P<2>
2
PCIE_CPU1_P3_RX_P<4>
3
PCIE_CPU1_P3_RX_P<6>
4
PCIE_CPU1_P3_RX_P<8>
5
PCIE_CPU1_P3_RX_P<10>
6
PCIE_CPU1_P3_RX_P<12>
7
PCIE_CPU1_P3_RX_P<14>
8
CLK100_RTM CPU1PORT3AB DP
9
n.c
10
b
PCIE_CPU1_P3_RX_N<0>
PCIE_CPU1_P3_RX_N<2>
PCIE_CPU1_P3_RX_N<4>
PCIE_CPU1_P3_RX_N<6>
PCIE_CPU1_P3_RX_N<8>
PCIE_CPU1_P3_RX_N<10>
PCIE_CPU1_P3_RX_N<12>
PCIE_CPU1_P3_RX_N<14>
CLK100_RTM CPU1PORT3AB DN
a b c d e f g h
n.c
PCIE_CPU1_P3_TX_P<0>
PCIE_CPU1_P3_TX_P<2>
PCIE_CPU1_P3_TX_P<4>
PCIE_CPU1_P3_TX_P<6>
PCIE_CPU1_P3_TX_P<8>
PCIE_CPU1_P3_TX_P<10>
PCIE_CPU1_P3_TX_P<12>
PCIE_CPU1_P3_TX_P<14>
CLK100_RTM CPU1PORT3CD DP
n.c.
Figure 3-16 P31 Backplane Connector Pinout - Rows E to H
e
PCIE_CPU1_P3_RX_P<1>
1
PCIE_CPU1_P3_RX_P<3>
2
PCIE_CPU1_P3_RX_P<5>
3
PCIE_CPU1_P3_RX_P<7>
4
PCIE_CPU1_P3_RX_P<9>
5
PCIE_CPU1_P3_RX_P<11>
6
PCIE_CPU1_P3_RX_P<13>
7
PCIE_CPU1_P3_RX_P<15>
8
n.c
9
n.c.
10
f
PCIE_CPU1_P3_RX_N<1>
PCIE_CPU1_P3_RX_N<3>
PCIE_CPU1_P3_RX_N<5>
PCIE_CPU1_P3_RX_N<7>
PCIE_CPU1_P3_RX_N<9>
PCIE_CPU1_P3_RX_N<11>
PCIE_CPU1_P3_RX_N<13>
PCIE_CPU1_P3_RX_N<15>
a b c d e f g h
c
g
PCIE_CPU1_P3_TX_P<1>
PCIE_CPU1_P3_TX_P<3>
PCIE_CPU1_P3_TX_P<5>
PCIE_CPU1_P3_TX_P<7>
PCIE_CPU1_P3_TX_P<9>
PCIE_CPU1_P3_TX_P<11>
PCIE_CPU1_P3_TX_P<13>
PCIE_CPU1_P3_TX_P<15>
n.c
n.c
d
PCIE_CPU1_P3_TX_N<0>
PCIE_CPU1_P3_TX_N<2>
PCIE_CPU1_P3_TX_N<4>
PCIE_CPU1_P3_TX_N<6>
PCIE_CPU1_P3_TX_N<8>
PCIE_CPU1_P3_TX_N<10>
PCIE_CPU1_P3_TX_N<12>
PCIE_CPU1_P3_TX_N<14>
CLK100 RTM CPU1PORT3CD DN
h
PCIE_CPU1_P3_TX_N<1>
PCIE_CPU1_P3_TX_N<3>
PCIE_CPU1_P3_TX_N<5>
PCIE_CPU1_P3_TX_N<7>
PCIE_CPU1_P3_TX_N<9>
PCIE_CPU1_P3_TX_N<11>
PCIE_CPU1_P3_TX_N<13>
PCIE_CPU1_P3_TX_N<15>
n.c
n.c
n.c
10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
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Figure 3-17 P32 Backplane Connector Pinout - Rows A to D
Figure 3-18 P32 Backplane Connector Pinout - Rows E to H
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Functional Description

4.1 Block Diagram

The block diagram shows how the devices work together and the data paths used.
Figure 4-1 Block Diagram ATCA-7480
Chapter 4

4.2 Processor

ATCA-7480 provides two Intel Xeon E5-26xxL V3 (Haswell-EP) server processors as the central processing unit (CPU). Each processor provides 40 PCIe lanes up to Gen3 speeds (8GT/s). The processors are connected with each other through 2 Intel QuickPath Interconnect point-to­point links capable of up to 9.8 GT/s. Each processor provides an integrated 4-channel DDR4 Memory Controller (IMC) supporting up to DDR4-2133.
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Functional Description

4.3 DDR4 Main Memory

The blade provides 2 CPUs which has 4 channels of independent DDR4 memory on each CPU. On each of the eight DDR4 channels the blade provides 2 DIMMs. The latest JEDEC specification defines a DDR4 socket with 288 pins. Registered DDR4 DIMMs are used for best performance.
Following are the DDR4 module specifications:
DDR4-2133
Very Low Profile
Max 2 ranks per DIMM
8 and 16 GByte capacity
Standard Voltage (1.2V)
Speed up to DDR4-2133 (PC4-2133) for 1DPC
Speed up to DDR4-1866 (PC4-1866) for 2DPC
84
When mixing DIMMs of different speed selections, BIOS setups the lowest speed for all memory channels/DIMM slots on per CPU level basis.
Supported memory features:
RAS features supported with ECC (mirroring, x8/x4 SDDC, Sparing, Scrubbing)
Memory Error signaling for uncorrectable errors
Memory Error signaling for correctable memory errors
ADR feature to support persistent memory structures in DDR3 (asynchronous DRAM
refresh)
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Functional Description

4.4 Platform Controller Hub (PCH) Intel C612 Wellsburg

The Next Generation Communications Platform Controller hub (codename Wellsburg) Intel C612 PCH provides access between processors and the I/O subsystem. The PCH connects to CPU#0 through Intel DMI2.0, PCH I/O-controller connected to DMI2 interface of CPU#0.
ATCA-7480 supports Intel Hybrid Clocking Mode through the Intel C612 PCH controller. By default, Spread Spectrum Clocking (SSC) feature is enabled for the 100MHz CPU and the PCIe clocks, which are provided by the Intel C612 and buffered through DB1900 buffer. If SSC is enabled in BIOS settings, all PCIe devices that are connected on-board or via RTM module will receive SSC clock. SSC can be disabled using BIOS settings.
The SSC tolerance is +/-0.25% from nominal frequency (100 MHz).

4.4.1 PCH I/O Controller Features

PCH I/O Controller features:
X4 PCIe Gen1 (2.5GT/s) connected to VGA module slot
8237 DMA controller
8254 based Counter Timer/timers
8259 Interrupt Controllers PIC (D31:F0)
I/O APIC controller (D31:F0)
Serial Interrupt (D31:F0)
RTC with 256-byte battery-backed SRAM (D31:F0) (D31:F7)
Processor Interface (D31:F0) including Thermtrip input and A20GATE, INIT3_3V,
CPUPWRGD, PMSYNC#, PECI
Two stage Watchdog timer (WDT) (D31:F7)
SPI Interface (Boot Flash)
LPC/KCS Interface
Up to 10 serial ATA (SATA) controllers 6Gb/s of which four are used on ATCA-7480
Six USB 3.0 and 8 PCIe 2.0 interfaces of which 2+2 are used on ATCA-7480
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Functional Description
Power management support (D31:F0) including ACPI S3 state support (suspend to RAM)
and Management Engine Power Management support
High Precision Event Timers (HPET)
System TCO (total cost of ownership) Reduction circuits
SMBus Host controller (D31:F3) and SMLINK0,1 interface for communication with external
IPMC controller
General purpose I/O pins (D31:F0)

4.4.2 Intel i350 Quad GB Ethernet Controller

The i350 four 1Gb Ethernet MACs are used on ATCA-7480 to provide:
Dual AdvancedTCA Base Interface 10/100/1000Base-T
Two Faceplate 10/100/1000Base-T interfaces

4.4.3 Firmware Flashes

The Blade has two physically separate 16 MB flash devices hosting the BIOS firmware.
Primary (or Default BIOS) Flash (SPI 0)
Recovery BIOS Flash (SPI 1)
The flash is allocated for storing the binary code of the BIOS. The ATCA-7480 boots from the primary flash SPI 0 under normal circumstances. If booting BIOS from primary flash SPI 0 fails, a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI 1. The image that the processor will boot from after next reset is determined by the IPMC. It can be selected via dedicated IPMI OEM command.

4.5 ATCA Fabric IF Ethernet

The ATCA-7480 blade utilizes two Intel XL710 Dual 40GB Ethernet controllers to provide four 40GB Ethernet IFs to the ATCA zone 2. They operate at 40GBASE-KR4,10GBASE-KR,10GBASE­KX4,1000Base-KX: Option1, 1-K,1-KR,9,9-K,9-KR. The redundant fabric I/F is fully operable in 40G, 10G, or 1G mode without the presence of an RTM.
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4.6 Storage Controller

Using an optional RTM, the blade provides a Serial Attached SCSI (SAS) controller. One on­board hard disk drive located on the RTM is connected to the controller. A minimum of two (2) ports are available on the RTM faceplate. They can be used to attach an external storage RAID (JBOD). Another SAS port of the controller is routed to ATCA Zone 3 for the purposes of synchronizing with an RTM based disk located in a logically paired ATCA slot.

4.7 MO297 SlimSATA Embedded Solid State Disc (SSD) Carrier/Riser Card

ATCA-7480 provides a modular solution for up to three MO297-A compliant SSDs. Each SSD is connected to the Intel Wellsburg PCH via a SATA interface. The modular approach consists of a riser card, which provide up to three sockets for SSDs and the MO297-A compliant SSDs. Before the storage solution can be mounted on ATCA-7480, the riser card and the SSDs have to be pre­mounted.

4.8 Heat Sink

Passive heat sinks are mounted on top of the Intel Haswell-EP LGA2011-R3 socket assembly. The maximum thermal design power used by Intel Haswell-EP is 75 W. The thermal resistance of the processor heat sink (including interface material) guarantees a proper cooling in the system. The heat sink fixture withstands shock and vibration tests.

4.9 BIOS

ATCA-7480 provides a BIOS firmware that is stored in flash memory. It can be updated remotely via Ethernet or locally via operating system. Along with the BIOS and BIOS Setup program, the flash memory contains POST and Plug and Play support.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. A BIOS extension is provided for the RTM based SAS controller to support RAID configuration.
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Functional Description

4.10 IPMC

ATCA-7480 contains the IPMC building block from Pigeon Point Systems (PPS). It is based on Microsemi Smartfusion cSOC (customizable System-on-Chip). The PPS IPMC controller is based on 32-bit Cortex M3 microcontroller operating at 50 MHz. The PPS implementation is the BMR-A2F200-AMCc-CM288R utilizing Microsemi Smartfusion A2F200M3F-CSG288I device.
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4.10.1 I2C Bus

ATCA-7480 contains the IPMC controller Master-Only I2C Bus. It is also called as Private I2C Bus, which is connected to a FRU EEPROM, temperature sensors, and monitoring logic of the PIM.
Figure 4-2 Master Only I2C Bus Architecture
Functional Description
Fab#1
ADT7461
98h (4C)
I350
PowerVille
SOL-I2C MO-I2C
ADT7461-2
9Ah (4D)
PCA9555 48h
PCA9555 4Ah
PCA9557 38h
SEL A2h
FRU A0h
FPGA 5Eh
A2F200
Fab#2
IPMB-L1
IPMB-L2
AMC#1=RTM
IPMB-L3
AMC#1
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Table 4-1 IPMI I2C Bus Address Map (private I2C bus)
Device Name Device Type Location I2C Controller
IPMC Sensor #12 Inlet Temp LM75 ATCA-7480 IPMB-L1 90
IPMC Sensor #13 Outlet Temp LM75 ATCA-7480 IPMB-L1 94
48V Power Interface Sensor PIM4328 ATCA-7480 IPMB-L1 50
SMB Address hex
FRU EEPROM 24C512 ATCA-7480 Atmel A2F200
SEL EEPROM 24C512 ATCA-7480 Atmel A2F200
GLUE FPGA Lattice LFE2-6EATCA-7480 Atmel A2F200
IPMC GPI I/O Expander#1 PCA9555 ATCA-7480 Atmel A2F200
IPMC GPI I/O Expander#2 PCA9555 ATCA-7480 Atmel A2F200
IPMC GPI I/O Expander#1 PCA9557 ATCA-7480 Atmel A2F200
IntelXL710#1 Temp Sensor ADT7461 ATCA-7480 Atmel A2F200
IntelXL710#1 Temp Sensor ADT7461-2 ATCA-7480 Atmel A2F200

4.10.2 FRU Data serial IDROM

ATCA-7480 contains a 64KByte IDROM. It contains the FRU data, and board specific information. For example, serial number of the board, MAC addresses of network interfaces, and some additional information. The EEPROM has an I2C interface and is connected to the on­board Private I2C interface of IPMC building block. The IDROM is assigned to I2C address 0xA0.
A0
Maste-Only I2C
A2
Maste-Only I2C
FE
Maste-Only I2C
48
Maste-Only I2C
4A
Maste-Only I2C
38
Maste-Only I2C
98
Maste-Only I2C
9A
Maste-Only I2C
90
Characteristic Value I2C Address
Device Type 24C512 A0
H
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4.10.3 System Event Log EEPROM

ATCA-7480 contains a 64KByte System Event Log (SEL) PROM. The EEPROM has an I2C interface and is connected to the on-board Private I2C interface of IPMC building block. The IDROM is assigned to I2C address 0xA2.

4.11 Serial Redirection

The CPU serial redirection reroutes the console input and output; that is the text output to the text screen and input from the standard keyboard. The console is used by the BIOS setup menus, BIOS initialization and boot routines, OS boot loaders, and the loaded OSs.
The serial console of the payload CPU is available via SOL. In addition to the SOL capability, the serial console is also available on the blade faceplate using an RJ45 connector with Cisco pin­out.
If an SOL session is established, only the output is available on the faceplate. Input is not possible during this time via the faceplate. Alternatively to the CPU serial console, the IPMC serial console is also available on the faceplate serial connector. It can be selected via specific IPMI OEM command.
Functional Description

4.12 Serial Over LAN

Serial over LAN (SOL) enables suitably designed blades and servers to transparently redirect a serial character stream of a baseboard UART to/from a remote client via LAN over RMCP+ sessions. This enables users at remote consoles to access the serial port of a blade/server and interact with a text-based BIOS console, operating system, command line interfaces, and serial text-based applications.
The IPMC provides a dedicated sideband connection to the Base Interface Ethernet controller. This connectivity is not shared with IPMB-0 or any other I2C/SMBus/IPMB connections that the IPMC may use on the blade for hardware management. Data from the payload serial redirection is routed through the sideband connection to the Base I/F and vice versa. The Ethernet controller filters packets based on either MAC address, RMCP port number, or IP address and forwards them to the serial redirection over the sideband interface.
Client software like openIPMI is required to enable SOL and to communicate with the SOL based serial console.
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Functional Description

4.13 Control Logic

The blade provides control logic for specific functions, which includes:
Payload power supervision and sequencing
Payload resets
Multiple HW interfaces between payload and IPMC
Support for sensors as required
Any control circuitry based on programmable logic whether intended for payload supervision or as part of the payload is remotely upgradeable. Crisis recovery circuitry is provided to prevent board lock-ups as the result of a failed remote upgrade of the board control logic.

4.14 Front Board Faceplate

The blade's faceplate provides the following interfaces and control elements:
Two USB 2.0 ports
Two 10/1000/1000Base-T Ethernet ports
Serial console port to connect to either payload or IPMC serial I/F
Recessed reset button
Out of Service, In Service, Attention, and Hot Swap LEDs
The blade design provides the possibility to cover unused faceplate elements like LEDs or push button behind a custom overlay foil.

4.15 Faceplate Serial Interfaces

The ATCA-7480 has two serial interfaces. They are fully compliant to industry standard 16550 asynchronous communication controllers. The two Serial line interfaces #1 and #2 are integrated in the Intel DH8900CC PCH and routed to the on-board FPGA, which distributes them to either Faceplate, RTM, or IPMC for SOL. The serial line interfaces support baud rates up to 115200 kbps through a programmable baud rate generator.
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Functional Description
Serial Line Interface #1 (COM #1) and #2 (COM#2) destination
The serial line interface #1/ #2 can be routed either to the zone 3 connector or to the Faceplate. Destination selection is through IPMC or SW2-1.
The serial line interface #1 provides two different routing options:
Glue Logic FPGA <=> RTM
Glue Logic FPGA <=> Faceplate
Table 4-2 Faceplate Serial Interfaces
SW2.1 Connection
HIGH Switch 2.1 OFF Default
LOW or Switch 2.1 ON Glue Logic FPGA COM1 to RTM

4.15.1 IPMC Debug Console

The IPMC Debug Console IF connection is normally routed to a 3-pin on-board header (RS232) The IPMC Debug monitor terminal output can also be routed to the Faceplate. The IPMC Debug Console is also available when the ATCA-7480 Payload is powered off.
Table 4-3 IPMC Debug Console Destination Selection
SW2.2 Connection
SW2.2 OFF Default Faceplate connected to Payload COM1/2
IPMC Debug Console at three Pin Header
SW2.2 ON IPMC Debug Console to Faceplate
Glue Logic FPGA COM1 to Faceplate Glue Logic FPGA COM2 to RTM
Glue Logic FPGA COM2 to Faceplate
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Functional Description

4.16 USB 3.0 Interfaces

The PCH Intel C612 (Wellsburg) provides internal USB 3.0/ USB 2.0 host controllers with up to six USB 3.0 ports (480Mb/s) and eight USB 2.0 ports. Two USB 2.0 ports are routed to the faceplate and one USB 2.0 port is routed to the RTM. The ports available at the faceplate are routed to a dual stacked connector. The ports are USB 3.0 compliant.

4.17 LPC Interface

The PCH provides a 4-bit-wide low pin count (LPC) interface running at 33MHz, which is connected to following on-board I/O devices:
Glue Logic FPGA register map
IPMC Controller
TPM Extension Module Header

4.18 Trusted Platform Module

The Trusted Platform Module (TPM) is a specific protected and encapsulated microcontroller security chip used to defend the internal data structures against real intelligent attacks.
The nature of this security chip ensures that the information like keys, password, and digital certificates stored within are made more secure from external software attacks and physical theft. With the handful of keys it stores, all cryptographic functions are performed on the chip.
TPM provides the ability for a computing system to run applications more secured, allows secured remote access, performs electronic transactions and communication more safely.
The ATCA-7480 provides an on-board Infineon SLB9635TT1.2 FW3.16 TPM Controller connected to the LPC bus of PCH. This advanced Infineon controller guarantees that ATCA­7480 is fully compliant to TPM 1.2 specification. ATCA-7480 is ready to migrate to TPM 2.0.
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4.19 Real Time Clock

An external 32.768 kHz clock sources the internal real time clock inside Intel DH8900CC PCH with a frequency tolerance of 20 PPM. The RTC is fully DS1287, MC14618, PC87911, and Y2K compliant and provides 256 bytes of backed up CMOS RAM (of which 14 bytes contain the RTC time and date information and RTC configuration). During power down, the RTC consumes
0.9uA/hr.
Default power-down backup solution is an external +3V lithium battery with a capacity of
200mAh, which provides 3 years of backup.
Optional power-down backup method uses a Super CAP with a 1 Farad capacity. This
provides 300 hours of RTC/SRAM backup.

4.20 SMBus

Intel C612 PCH (Wellsburg) provides six SMBus interfaces. Only four interfaces are used on ATCA-7480 as described in the following table:
Functional Description
Table 4-4 SMBus Interface
Device / SMBus Description
Intel C612 B0:D31:F3
SMLINK0 Connection to external IPMC to report thermal information via PCH
SMLink1 Reserved
ME SMBus Optional connection
The Master SMBus interface of the Intel C612 PCH is connected to on-board devices like Clock PLLs, temperature sensors and so on. An I2C Bus Repeater of type PCA9515 is used for load distribution and buffering.
Additionally, both CPUs provide 2x SMBus to connect to the SPD PROMs of the DDR4 memory system.
ATCA-7480 Installation and Use (6806800T17A)
Host SMBus (Master/Slave)
internal PECI bridge to CPU
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Functional Description
The following figure shows the ATCA-7480 SMBus architecture.
Figure 4-3 SMBus Architecture
PIM 50h
LM75 Upper
94h
LM75 Lower
90h
XDP CPU
LTC
4300
LTC 4300
RTM
IPMB-L
isol isol
DB 1900
D8h
PCH SMBUS
(MGMT Domain)
SMLINK1
SMLINK0
Ret#1
E0h
Ret#2
E2h
PCH
Wellsburg
Fab#1 Fab#2
96
The following table provides SMBus mapping address details.
Table 4-5 SMBus Address Map
Device Name DeviceType Location SMBus Controller SMB Address hex
SPD EEPROM NA DDR4 module CPU#0 memory
controller AB
SPD EEPROM NA DDR4 module CPU#0 memory
controller AB
ATCA-7480 Installation and Use (6806800T17A)
A0
A8
Page 97
Functional Description
Table 4-5 SMBus Address Map (continued)
Device Name DeviceType Location SMBus Controller SMB Address hex
SPD EEPROM NA DDR4 module CPU#0 memory
controller CD
A0
SPD EEPROM NA DDR4 module CPU#0 memory
controller CD
SPD EEPROM NA DDR4 module CPU#0 memory
controller EF
SPD EEPROM NA DDR4 module CPU#0 memory
controller EF
SPD EEPROM NA DDR4 module CPU#0 memory
controller GH
SPD EEPROM NA DDR4 module CPU#0 memory
controller GH
IPMC Sensor #12 Inlet Temp
IPMC Sensor #13 Outlet Tem p
48V Power Interface Sensor
CB1900Z clock buffer
Retimer #1 IDT 89HT0816 ATCA-7480 Intel
Retimer #2 IDT 89HT0816 ATCA-7480 Intel
LM75 ATCA-7480 Intel
Wellsburg PCH
LM75 ATCA-7480 Intel
Wellsburg PCH
PIM4328 ATCA-7480 Intel
Wellsburg PCH
IDT 9ZX21901BKLF
ATCA-7480 Intel
Wellsburg PCH
Wellsburg PCH
Wellsburg PCH
A8
A0
A8
A0
A8
90
94
50
D8
E0
E2
ATCA-7480 Installation and Use (6806800T17A)
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Functional Description
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Maps and Registers

5.1 FPGA Registers

For register description, the convention shown in Table 5-1 and Table 5-2 are used.
Table 5-1 Register Default
Default Description
- Not applicable or undefined
0 or 1 Default value after PWR_GOOD is valid or after PCH_PLTRST_
deassertion.
Undef. Undefined value
<reset>: 0 or 1 Default value after deassertion of the reset signal <reset>
Ext. External Reset Source. Default depends on external logic level.
Chapter 5
Table 5-2 Register Access Type
Access Description
r Read only
w Write only
r/w Read and write
w1c Write-1-to-clear, ignore bit while reading
r/w1c Read and write-1-to-clear, write 0 has no effect
r/w1s Read and write-1-to-set, write 0 has no effect
r/w1t Read and write-1-to-toggle, write 0 has no effect
LPC: The prefix “LPC:” signals that the access is restricted to the LPC interface.
For example, LPC: r/w means that the register bit is readable/writable from the LPC interface
IPMC: The prefix “IPMC:” signals that the access is restricted to the IPMC I2C interface.
For example, IPMC: r/w means that the register bit is readable/writable from IPMC I2C interface
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Maps and Registers

5.1.1 Register Decoding

The FPGA registers can be accessed from the host or the IPMC. For the host access, LPC bus interface is used. The IPMC uses an I2C interface.
5.1.1.1 LPC Decoding
The LPC bus supports different protocols.
5.1.1.1.1 LPC I/O Decoding
The LPC interface responds to LPC I/O accesses listed in the following table. All other LPC I/O accesses are ignored.
Table 5-3 LPC I/O Register Map Overview
Base Address Address Size Address Range Name Description
0x4E 2 SIW Super IO Configuration Registers
0x80 1 POSTCODE POST Code Register
BASE1 8 COM1 UART1. Serial Port 1 (Logical Device
BASE2 8 COM2 UART2. Serial Port 2. (Logical
0x600 128 REGISTERS FPGA Registers
All LPC I/O accesses to address POSTCODE and the address range REGISTERS and within the address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are decoded by the LPC core.
5.1.1.1.2 LPC Memory Decoding
The LPC interface never responds to LPC memory accesses.
for Index and Date
4). BASE1 address is set up during Super IO Configuration.
Device 4). BASE2 address is set up during Super IO Configuration.
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ATCA-7480 Installation and Use (6806800T17A)
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