Apple X502 Schematics

639-03266 PCBA,MLB_CATZ,XXXXX,X502

DESIGN: X502/MLB_CATZ

DOCUMENTS / BOARDS / ASSEMBLIES

LAST CHANGE: Tue Aug 9 17:02:57 2016

1 OF 73

LAST_MODIFICATION=Tue Aug 9 17:03:06 2016

Power Sensors Extended56

55

54

53

52

45

44

43

42

41

Power Sensors High Side

SMBus Connections

SMC Project Support

PAULM

06/15/2015

PAULM

Power Sensors Load Side

71

70

69

66

55

53

52

51

CPU IMVP VCC & VCCSA

VReg CPU VCC Cntl

PBUS Supply & Battery Charger

DC-IN & BATTERY CONNECTORS

JACK TRANSLATORS

54

72

84

80

79

65

64

63

62

61

PMIC 1.2V 1.0V 0.6V 81 82 Power FETs

LCD Backlight Driver

RAIL DESENSE CAPS

PMIC VCCPCH VCCIO 1.8V

Chipset Support 1

22

20

18

19

18

17

16

LPDDR3 VREF Margining20

CPU/PCH Merged XDP

19

PCH SPI/UART/GPIO

Chipset Support 2

16

6

8 9 10

6 7 8 9 10

PAULM

CPU & PCH Grounds CPU Core Decoupling

CPU & PCH Power

7

06/15/2015

CPU LPDDR3 Interface

CPU MISC/JTAG/CFG/RSVD

SPI ROM & SWD Debug

HDA BRIDGE

JACK CODEC

SPEAKER AMP

46 47 48

50

58 61 62 63 64

AHAAGE

03/23/2016

09/22/2015

03/23/2016

PAULM

06/15/2015

Thermal Sensors

49

51

50

48

40

39

40

38

37

P1:KEYBOARD & TRACKPAD CONN

CAMERA 2 OF 2

SMC Shared Support

39 SMC

CAMERA 1 OF 236

32 34

USB-C SUPPORT 2

38

37

35

33

35

34

33

31

USB-C CONNECTOR B

USB-C CONNECTOR A

WIFI/BT MODULE WIFI/BT Module Support

32

31

29

28

30

29

28

27

26

USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B

USB-C HIGH SPEED 1

30 USB-C SUPPORT

USB-C HIGH SPEED 2

LAST_MODIFICATION=Tue Aug 9 17:03:06 2016

1 2 3 4 5

PAULM

PAULM 06/15/2015

06/15/2015

CPU GFX

PD Parts

BOM Configuration

Table of Contents

06/15/2015

27

26

25

24

23

25

24

23

22

LPDDR3 DRAM Channel B (32-63)

LPDDR3 DRAM Channel A (00-31)

LPDDR3 DRAM Termination

21

LPDDR3 DRAM Channel B (00-31)

LPDDR3 DRAM Channel A (32-63)

MICHKLEE500

104

103

73

72

=LAST SCHEMATIC PAGE=

FCT, ICT PROPERTIES

X502-EXP

PAULM

12/03/2015

06/15/2015

06/23/2015

Memory Signal Swaps71

Power Aliases 102

100

99

86

85

70

69

68

67

66

SSD MODULE

eDP Display Connector

PAULM

X502-EXP

X362

PAULM

06/23/2015

06/15/2015

12/03/2015

06/15/2015

NC_ AND NO_TEST SIGNALS

DEVELOPMENT ONLY

78

76

74

59

58

57

56

VR - 5V S4, 3.3V S5

IMVP VCCSA

PMIC IC & Power Control

GT IMVP VCCGT

60

77 VR - OPC (EDRAM)

73

15

14

13

12

11

15

14

13

12

11

PCH Power Management

PCH Decoupling

CPU GT Decoupling

PCH Audio/LPC/SPI/SMBus

PCH PCIE/USB/CLKS

SCHEM,MLB-CATZ,X502

051-02265

2016-08-1000067823291 ENGINEERING RELEASED

1 OF 500

1.0.0

PCBF,MLB_CATZ,X502 MLB1 CRITICAL820-00875

CBOM1 CMN_PARTS_BOM685-00125 COMMON PARTS,MLB_CATZ,X502

SCH1051-02265 SCHEM,MLB_CATZ,X502

DEV11 DEVELOPMENT_LIST985-00239 DEV PARTS,MLB_CATZ,X502

Table of Contents

BOM_COST_GROUP=NO COST ITEMS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CK APPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

D

SIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

DATESYNCCONTENTSCSAPAGE DATESYNCCONTENTSCSAPAGE

www.vinaﬁx.com

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TBT ROM

EFI ROM

MICRON

Programmables (All Builds)

(BOOT CODE: 0002.08.07)

(BOOT CODE: 0002.08.08)

(BOOT CODE: 0002.08.07)

WIFI ROM

DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016

CPU

Major ICs

TBT ALPINE RIDGE

BT ROM

ACE

WIRELESS MODULE

SMC

2 OF 73

2 OF 500

1.0.0

051-02265

BT_ROM:PVTCRITICAL341S00397 1 U3770IC,BT ROM (V53) PROTO0,X502

IC,BT ROM (V53) PROTO0,X502

U37701341S00397 CRITICAL BT_ROM:PROTO0

SMC:PVTCRITICAL341S00662 1 U5000

IC,SMC-B1,EXT (V2.36F58) PVT,X502

ALT_CMN MACRONIXALL335S0959335S00006

BOOTROM:PROTO1CRITICAL341S00452 1 U6100IC,EFI (V0093) PROTO 0,X502

CRITICAL1 U6100341S00673 IC,EFI (V0173) PVT,X502 BOOTROM:PVT

ALTERNATE

335S00024 ALT_CMN ALL335S0837

1 BT_ROM:BLANKCRITICAL335S00024 U3770IC,FLASH,USON8,512KBIT,75MHZ

BOM Configuration

BOM_COST_GROUP=NO COST ITEMS

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

338S1231 SMC:BLANKCRITICAL1 U5000IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA

1 U5000IC,SMC-B1,EXT (V2.35A4) PROTO 1,X502 SMC:PROTO1CRITICAL341S00429

IC,EFI (V0143) EVT,X502 U61001341S00573 CRITICAL BOOTROM:EVT

SMC:PROTO2CRITICAL341S00517 1 U5000

IC,SMC-B1,EXT (V2.35A51) PROTO 2,X502

SMC:EVTCRITICAL341S00562 1 U5000IC,SMC-B1,EXT (V2.36A2) EVT,X502

SMC:PREDVTCRITICAL341S00611 1 U5000IC,SMC-B1,EXT (V2.36A33) PRE-DVT,X502

BOOTROM:BLANKCRITICAL335S0959 1 U6100IC,SPI SERIAL FLASH,64M BITS,3V,CSP,QE=1

TBT_AR:C1_PRQCRITICAL338S00254 1 U2800IC,TBT,ALPINE RIDGE,SLLSM,PRQ,C1,CSP337

TBT_AR:C1_QSCRITICAL338S00249 1 U2800IC,TBT,ALPINE RIDGE,QT5S,QS,C1,CSP337

ACE:B0CRITICAL353S00807 2 U3100,U3200IC,CD3215,ACE,B0,USB PWR SWITCH,BGA96

ACE:B0_BCRITICAL353S00887 2 U3100,U3200IC,CD3215,ACE,B0,USB PWR SW,BLNK,BGA96

WIRELESS:USICRITICAL339S0251 1 U3700MODULE,WIFI/BT,STELLA CIDRE,USI,LGA80

WIRELESS:MURATACRITICAL339S0250 1 U3700MODULE,WIFI/BT,STELLA CIDRE,MUR,LGA80

CPU_SKL:2_2_QS_2.3CRITICAL337S00168 1 U0500CPU,SKYU,QJ8N,D0,QS,2/2,2.3,15W,BGA1356

CPU_SKL:2_3_SQS_1G8CRITICAL337S00219 1 U0500CPU,SKYU,QK2T,K1,SQS,1.8,15W,.95,BGA1356

ACE:B0_2CRITICAL353S00888 2 U3100,U3200IC,CD3215,ACE,B0,USB PWR SW,OTP=2,BGA96

CPU_SKL:2_3_ES0_BTCRITICAL337S00150 1 U0500CPU,SKYU,QJ58,J0,ES0,2/3,1.6,28W,BGA1356

BT_ROM:X261CRITICAL341S00196 1 U3770IC,BT ROM (V53) DVT,X261

CPU_SKL:VTT_INTERPOSERCRITICAL998-04195 1 U0500INTERPOSER,VTT ADAPTER,SKL-U,BGA1356

ALT_CMN ALTERNATEALL335S0956335S00145

WIFI-ROM:MURATA-ETSICRITICAL341S00608 1 U3780WIFI ROM (P175) PRE-DVT,WW2,X502

WIFI-ROM:USI-ETSICRITICAL341S00637 1 U3780WIFI ROM (P177) USI-WW2,X502

WIFI-ROM:MURATA-INDCRITICAL341S00610 1 U3780WIFI ROM (P175) PRE-DVT,IND,X502

WIFI-ROM:MURATA-FCCCRITICAL341S00607 1 U3780WIFI ROM (P175) PRE-DVT,WW1,X502

WIFI-ROM:BLANKCRITICAL335S0956 1 U3780IC,MEMORY,EEPROM,4K,1.7V-5.5V,UDFN8

WIFI-ROM:MURATA-APACCRITICAL341S00609 1 U3780WIFI ROM (P175) PRE-DVT,WW3,X502

TBT_AR:B1_PRQ_TRAYCRITICAL998-04160 1 U2800IC,TBT,ALP-RIDGE DP,SLL44-TRAY,B1,CSP337

TBT_AR:C0_QSCRITICAL338S00229 1 U2800IC,TBT,ALPINE RIDGE,QSTY,QS,C0,CSP337

WIFI-ROM:USI-INDCRITICAL341S00639 1 U3780WIFI ROM (P177) USI-IND,X502

WIFI-ROM:USI-APACCRITICAL341S00638 1 U3780WIFI ROM (P177) USI-WW3,X502

WIFI-ROM:USI-FCCCRITICAL341S00636 1 U3780WIFI ROM (P177) USI-WW1,X502

TBT_AR:B1_PRQCRITICAL338S00176 1 U2800IC,TBT,ALPN-RIDGE DP,SLL43-T&R,B1,CSP337

TBT_AR:B1_QSCRITICAL338S00160 1 U2800IC,TBT,ALPINE RIDGE DP,QSJV,B1,6X6MM,BGA96

ACE:A1CRITICAL353S00660 2 U3100,U3200IC,CD3215,ACE,A1,USB PWR SWITCH,BGA96

ACE:A0CRITICAL353S00422 2 U3100,U3200IC,CD3215,USB PWR SWITCH,A0,6X6MM,BGA96

CPU_SKL:2_3_PRQ_2G0CRITICAL337S00239 1 U0500CPU,SKY,SR2JM,K1,PRQ,2.0,15W,BGA1356

ACE:B0_3CRITICAL353S00926 2 U3100,U3200IC,CD3215,ACE,B03,USB PWR SW,BLNK,BGA96

ACE:C0CRITICAL353S00961 2 U3100,U3200IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96

CRITICAL337S00220 1 U0500 CPU_SKL:2_3_SQS_2G2CPU,SKYU,QKBY,K1,SQS,2.2,15W,1.05,BG1356

CPU_SKL:2_3_SQS_2G0CRITICAL337S00222 1 U0500CPU,SKYU,QK33,K1,SQS,2.0,15W,1.0,BG1356

CRITICAL337S00149 1 U0500 CPU_SKL:2_3_ES0_GDCPU,SKYU,QJ57,J0,ES0,2/3,1.6,15W,BGA1356

CPU_SKL:2_2_QS_2.6CRITICAL337S00170 1 U0500CPU,SKYU,QJ8K,D0,QS,2/2,2.6,15W,BGA1356

CPU_SKL:BASECRITICAL998-00235 1 U0500IC,CPU,SKL-ULT,2+3E,42X24MM,BGA1356

CPU_SKL:2_3_SQS_2G4CRITICAL337S00233 1 U0500CPU,SKYU,QK32,K1,SQS,2.4,15W,BGA1356

CPU_SKL:2_3_PRQ_1G8CRITICAL337S00232 1 U0500CPU,SKY,SR2JC,K1,PRQ,1.8,15W,BGA1356

CPU_SKL:2_3_PRQ_2G4337S00234 1 U0500 CRITICALCPU,SKYU,SR2JL,K1,PRQ,2.4,15W,BGA1356

341S00334 SMC:POCCRITICAL1 U5000IC,SMC-B1,EXT (V2.31A18) POC,X502

SMC:DVTCRITICAL341S00633 1 U5000IC,SMC-B1,EXT (V2.36A48) DVT,X502

BOOTROM:PROTO0CRITICAL341S00389 1 U6100IC,EFI (V0072) PROTO 0,X502

AR_ROM:EVTCRITICAL341S00559 1 U2890IC,NVM (V16.8) EVT,X502

AR_ROM:PROTO2CRITICAL341S00512 1 U2890IC,NVM (VB1-10.11-E2.6.3) PROTO 2,X502

AR_ROM:PROTO1CRITICAL341S00451 1 U2890IC,NVM / AR (V0.8.15.E1) PROTO 1,X502

AR_ROM:PREDVTCRITICAL341S00606 1 U2890IC,NVM (V1.5) PRE-DVT,X502

AR_ROM:DVTCRITICAL341S00628 1 U2890IC, NVM (V3.8), DVT, X502

AR_ROM:PVTCRITICAL341S00661 1 U2890IC, NVM (VTBD), PVT, X502

BOOTROM:PROTO2CRITICAL341S00513 1 U6100IC,EFI (V0114) PROTO 2,X502

IC,EFI (V0130) PROTO 2.2,X502

BOOTROM:PROTO2_2CRITICAL341S00543 1 U6100

AR_ROM:BLANKCRITICAL335S00133 1 U2890

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8

TABLE_ALT_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_ITEM

合肥怡飞苹果维修qq：82669515 qq群： 241000

<10100> <01011>

<01010><10101>

INVERT TO VALUE

MLB VERSION ID STRAPS

Main DRAM SPD Straps

RAMCFG0

<11110>

<11011>

<11001>

<00100>

0 (STUFF R)

Main DRAM Parts

DIE B

RAMCFG2

1 (OPEN)

0 (STUFF R)

1 (OPEN)1 (OPEN)0 (STUFF R)

-RESERVED-

MICRON

SAMSUNG

HYNIX 0 (STUFF R)

1 (OPEN)

0 (STUFF R)

0 (STUFF R) 8GB 0 (STUFF R) 2133

RAMCFG3

DIE A

1 (OPEN)

LAST CHANGE: Fri Aug 5 13:34:33 2016

DESIGN: X502/MLB_CATZ

RAMCFG4

1 (OPEN)

PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.

RAMCFG1

<11010>

<11111>

<11101>

CODE

<11100>

<00000>

<00001>

<00010>

<00101>

More Alternate Parts

<11000> <00111>

<01000><10111>

16GB 1867

<00110>

<00011>

Alternate Parts

<10110> <01001>

3 OF 73

3 OF 500

1.0.0

051-02265

ALT_CMN197S00036 KYOCERA197S00047 ALL

ALLALT_CMN

197S00050 KYOCERA197S00053

ALT_CMN ALL197S00050197S00054 NDK

311S00060 ALLALT_CMN DIODES INC311S0273

ALT_CMN ALL311S00004 311S0370 ON SEMI

ALT_CMN TFTALL

107S00033 107S00034

TFTALL107S00011 ALT_CMN107S00015

107S00053

ALT_CMN ALL107S00071 YAGEO

ALT_CMN DIODES INC

311S0271311S00008 ALL

IC,SDRAM,LPDDR3-1866,32GBIT,20NM,BGA1784 U2300,U2400,U2500,U2600 CRITICAL DRAM:SAMSUNG_16GB_1866333S00049

155S00115 155S00114 MURATAALLALT_CMN

ALT_CMN ALL

138S0777 MULTIPLE138S00015

ALT_CMN ALL138S0846 138S0811 SAMSUNG

ALT_CMN

138S0831138S00049 ALL KYOCERA

SAMSUNGALT_CMN

138S0775 ALL138S0860

152S00266

ALL NECALT_CMN152S00367

152S00322

ALT_CMN CHILISIN152S00403 ALL

740S00028 740S0118 ALT_CMN ALL BUSSMANN

ALL

377S00011 ON SEMIALT_CMN377S0155

376S00074 376S0855

ALLALT_CMN TOSHIBA

376S0820 ALLALT_CMN DIODES INC376S1080

R16921117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO2

RES,MF,1/20W/1K OHM,5,0201,SMD2117S0006 R1692,R1691 BOARD_ID:EVT

117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD1 R1691 BOARD_ID:PRE_PROTO1

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO1117S0006 2 R1691,R1690

128S00070 128S00015 PANASONICALLALT_CMN

128S00010 PANASONICALLALT_CMN128S00011

TAIYO YUDEN155S00203 155S0894 ALT_CMN ALL

MURATA

155S00034 155S0706 ALT_CMN ALL

TAIYO YUDENALL

155S00007 155S0667 ALT_CMN

MURATA

155S0660 155S0513 ALLALT_CMN

TDK

155S00155 155S0441 ALLALT_CMN

ALT_CMN

152S00361 ALL MURATA152S1872

155S0694 155S0387

ALL MURATAALT_CMN

155S0659 MURATAALLALT_CMN155S0382

152S00208

ALT_CMN152S00358 ALL CHILISIN

ALT_CMN

152S00048152S00363 ALL NEC

ALT_CMN

152S00381 152S1129 CHILISINALL

SAMSUNG

138S1101138S0738 ALLALT_CMN

138S00086 ALL TAIYO YUDEN138S0884 ALT_CMN

ALL

138S0831138S00032 ALT_CMN TAIYO YUDEN

ALLALT_CMN

138S00106 KYOCERA138S0754

ALLALT_CMN138S0719138S1103 TAIYO YUDEN

ALT_CMN MULTIPLEALL

138S0709138S0864

128S00058 128S00018

ALT_CMN ROHMALL

128S00011 ALL ROHM128S00031 ALT_CMN

ALL

128S00011 NEC128S00026 ALT_CMN

107S00087 YAGEOALL107S00029 ALT_CMN

ALT_CMN ALL CYNTEC

107S00076107S00044

ALT_CMN ALL TFT107S0248 107S0250

107S0251107S0249

ALL TFTALT_CMN

197S00055 197S00050 MURATAALLALT_CMN

DIODES INCALT_CMN ALL

311S0543311S00122

311S0508311S00013

ALLALT_CMN DIODES INC

ALLALT_CMN

740S00002740S00033 THINKING

740S00019 BOURNSALT_CMN ALL740S00007

BOURNSALL740S0159740S00027 ALT_CMN

AEM, INC.

740S00003 ALLALT_CMN740S0135

LITTELFUSE740S0144 740S0118 ALT_CMN ALL

ALT_CMN ALL

377S00017377S00048 ST MICRO

NXP

376S1128376S1089 ALT_CMN ALL

377S00031 377S0178 ON SEMIALT_CMN ALL

ALL ROHMALT_CMN

376S00146 376S1061

376S0604

DIODES INC376S1053 ALT_CMN ALL

376S0678376S1106 FAIRCHILDALLALT_CMN

DIODES INC

372S00016 ALLALT_CMN372S00015

372S0186

NXPALLALT_CMN372S0185

DIODES INC371S00089 371S00085 ALLALT_CMN

ALT_CMN

371S00077371S0704 NXPALL

VISHAYALT_CMN ALL

353S4471353S00525

DIODES INCALT_CMN371S0558371S0713 ALL

371S0602 INFINEONALT_CMN ALL371S00074

ALT_CMN353S4398353S00769 DIODES INCALL

ALT_CMN

353S4342 ST MICRO353S00854 ALL

353S2216 ALT_CMN353S00712 ALL ON SEMI

353S00711 ALT_CMN353S2073 ALL ON SEMI

311S00097 DIODES INC311S00036 ALT_CMN ALL

ALT_CMN

311S0593 TIALL311S0596

ALT_CMN TDKALL107S0085107S00070

ALT_CMN KEMETALL128S00009 128S00015

RES,MF,1/20W/1K OHM,5,0201,SMD117S0006 3 BOARD_ID:PREDVTR1692,R1691,R1690

RES,MF,1/20W/1K OHM,5,0201,SMD2 R1692,R1690 BOARD_ID:PROTO2_2117S0006

IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178 U2300,U2400,U2500,U2600

4 DRAM:SAMSUNG_8GB_1866333S00099 CRITICAL

U2300,U2400,U2500,U2600 DRAM:MICRON_16GB_1866IC,LPDDR3-1866,32GB,1GX32,20NM,BGA178333S00098 4 CRITICAL

4

333S00097 CRITICALU2300,U2400,U2500,U2600 DRAM:MICRON_8GB_1866IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178

CRITICAL4 IC,LPDDR3-1866,32GBIT,25NM,BGA178 U2300,U2400,U2500,U2600333S0784 DRAM:HYNIX_16GB_1866

RES,MF,1/20W/1K OHM,5,0201,SMD0117S0006 BOARD_ID:POC

DRAM:HYNIX_8GB_18664 CRITICAL333S00101 IC,LPDDR3-1866,16GB,512MX32,25NM,BGA178 U2300,U2400,U2500,U2600

MURATAALL197S00036 ALT_CMN197S00048

ALL197S00046 197S00036 ALT_CMN EPSON

ALT_CMN

353S3239353S00107 ON SEMIALL

3117S0006

R1331,R1332,R1334 DRAM:MICRON_8GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD

R1331,R13342 RES,MF,1/20W,1K OHM,5,0201,SMD117S0006 DRAM:MICRON_16GB_1866

R1330,R1331,R1332,R1334RES,MF,1/20W,1K OHM,5,0201,SMD4117S0006 DRAM:HYNIX_8GB_1866

117S0006 2 R1330,R1334 DRAM:SAMSUNG_16GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD

NECALT_CMN ALL128S00062 128S00067

128S00067

ALT_CMN ALL ROHM128S00069

ALT_CMN ALL128S0364 SANYO 2ND FACTORY128S0264

128S0311 128S0329

NEC ALT TO SANYOALT_CMN ALL

ALL PANASONIC

128S0325 128S0397 ALT_CMN

ALT_CMN ALL TAIYO YUDEN

131S00134 131S00041

ALT_CMN132S0409 ALL MURATA132S00064

TAIYO YUDENALT_CMN ALL138S00035138S00077

TAIYO YUDENALLALT_CMN138S00084 138S00060

138S0641

ALT_CMN ALL MURATA138S0700

ALT_CMN ALL138S0701 MURATA138S0689

ALLALT_CMN152S1682 MURATA152S00343

ALT_CMN MURATA138S0648 ALL138S0703

ALL KYOCERAALT_CMN138S00093 138S00035

376S0761376S00086

DIODES INC.ALLALT_CMN

376S00014 TOSHIBA376S0761 ALT_CMN ALLMURATA138S0739 ALT_CMN138S0706 ALL

1 BOARD_ID:DVTRES,MF,1/20W/1K OHM,5,0201,SMD117S0006 R1693

3117S0006 R1330,R1332,R1334 DRAM:SAMSUNG_8GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD

DRAM:HYNIX_16GB_1866

3 RES,MF,1/20W,1K OHM,5,0201,SMD R1330,R1331,R1334117S0006

RES,MF,1/20W/1K OHM,5,0201,SMD117S0006 R1693,R16902 BOARD_ID:DVT3

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO0R16901117S0006

BOM Configuration

SYNC_DATE=06/15/2015SYNC_MASTER=PAULM

BOM_COST_GROUP=NO COST ITEMS

2117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PVTR1693,R1691

2117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PRQ1R1693,R1691,R1690

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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D

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PAGE TITLE

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A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_5_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

PART NUMBER

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

合肥怡飞苹果维修qq：82669515 qq群： 241000

870-01680

FAN MOUNTING HOLE

MOUNTING HOLES

998-03850

BOTTOM STANDOFFS

SHIELD CANS

MEMORY CAN - TOP

WIRELESS CAN

MEMORY CAN - BOTTOM

LAST CHANGE: Thu Aug 4 21:00:42 2016

DESIGN: X502/MLB_CATZ

TOP STANDOFFS

POGO PINS

860-00468

PLATED HOLES

870-02068

998-03823

998-03850

998-03823

860-00385

USB-C CAN

LARGER SLOT, NEAR ANTENNA

998-06494

4 OF 73

4 OF 500

1.0.0

051-02265

SHIELD CAN,AR,USB-C,THRU,X520 SHLD31806-07885 CRITICAL SHIELD_CAN_USBC

SHIELD FENCE,BOT DRAM,SUS,PRE-MN,X520 SHLD11806-08894 CRITICAL SHIELD_CAN_MEMORY_BOT

SHIELD CAN FENCE,DRAM,MN,X520 SHLD41806-07887 CRITICAL SHIELD_CAN_MEMORY_TOP

SHIELD CAN,EMI,WIFI,SYM,MN,TALL,X520 SHLD21806-07886 CRITICAL SHIELD_CAN_WIFI

BOM_COST_GROUP=MECHANICALS

PD Parts

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

SM

POGO-2.3OD-4.1H-SM

1

SH0436

POGO-2.3OD-4.1H-SM

SM

1

SH0437

SM

POGO-2.0OD-2.95H-SM-1

1

SH0433

SM

POGO-2.0OD-2.95H-SM-1

1

SH0432

POGO-2.3OD-4.1H-SM

SM

1

SH0431

SM

POGO-2.3OD-4.1H-SM

1

SH0430

TH-NSP

SL-3.36X2.1-5.86X4.6

1

SH0426

TH-NSP

SL-3.36X2.1-5.86X4.6

1

SH0425

TH-NSP

SL-3.36X2.1-5.86X4.6

1

SH0421

TH-NSP

SL-3.38X2.1-5.88X4.6

1

SH0420

2.8OD1.2ID-3.0H-SM

2

1

SH0460

2.8OD1.2ID-3.0H-SM

2

1

SH0461

SL-2.6X2.0-4.7X4.1

TH-NSP

1

SH0410

4.0R3.6-NSP

1

SH0401

4.0R3.6-NSP

1

SH0400

2.8OD1.2ID-1.44H-SM

2

1

SH0457

2.8OD1.2ID-1.44H-SM

2

1

SH0455

2.8OD1.2ID-1.44H-SM

2

1

SH0453

2.8OD1.2ID-1.44H-SM

2

1

SH0452

2.8OD1.2ID-1.44H-SM

2

1

SH0451

2.8OD1.2ID-1.44H-SM

2

1

SH0450

SM

POGO-2.3OD-4.1H-SM

1

SH0434

SM

POGO-2.3OD-4.1H-SM

1

SH0435

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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C

345678

D

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8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

合肥怡飞苹果维修qq：82669515 qq群： 241000

FOR FUTURE PRODUCT PER PDG

DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016

5 OF 73

5 OF 500

1.0.0

051-02265

=PP0V95_S0_CPU_VCCIO

=PP3V3_SUS_PCH_VCCPRIM

XDP_USB_EXTD_OC_L

XDP_USB_EXTA_OC_L

JTAG_ISP_TDO

=PP1V8_SUS_PCH_VCC1P8_U12 =PP1V8_SUS_PCH_VCC1P8_U11

DP_DDPB_HPD

DP_DDI1_ML_C_N<0>

DP_DDI1_ML_C_N<2> DP_DDI1_ML_C_P<2>

DP_DDI1_ML_C_P<0>

DP_DDI2_ML_C_N<2>

DP_DDI2_ML_C_P<0>

DP_DDI2_ML_C_P<3>

DP_DDI2_ML_C_N<0>

DP_DDI1_ML_C_P<3>

DP_DDI2_ML_C_N<1> DP_DDI2_ML_C_P<1>

DP_DDI2_ML_C_P<2> DP_DDI2_ML_C_N<3>

DP_INT_HPD

JTAG_ISP_TDO

TP_PCH_GPP_E15

DP_DDPC_HPD

XDP_USB_EXTD_OC_L

EDP_COMP

DP_DDI1_ML_C_N<1> DP_DDI1_ML_C_P<1>

EDP_ML_C_N<0> EDP_ML_C_P<0> EDP_ML_C_N<1> EDP_ML_C_P<1> EDP_ML_C_N<2> EDP_ML_C_P<2> EDP_ML_C_N<3>

EDP_AUXCH_C_P

EDP_AUXCH_C_N

DP_DDI1_AUXCH_C_N

DP_DDI2_AUXCH_C_P

DP_DDI2_AUXCH_C_N

DP_DDI1_AUXCH_C_P

XDP_PCH_OBSDATA_B0

XDP_PCH_OBSDATA_A3

XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

EDP_BKLT_EN

EDP_PANEL_PWR_EN

XDP_USB_EXTC_OC_L

=PP3V3_S0_PCH

XDP_USB_EXTB_OC_L

DP_DDI1_ML_C_N<3>

EDP_BKLT_PWM

XDP_USB_EXTA_OC_L

EDP_ML_C_P<3>

BOM_COST_GROUP=CPU & CHIPSET

CPU GFX

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

72 66

201MF1/20W5%

100K

21

R0553

201MF1/20W5%

100K

21

R0552

201MF1/20W5%

100K

21

R0551

68 65

201MF1/20W5%

100K

21

R0550

201MF1/20W5%

10K

21

R0554

28 5

17 5

17

72 66

28

66

72 66

28

72 66

28

201

MF

1/20W

1%

PLACE_NEAR=U0500.E52:15.24MM

24.9

2

1

R0530

28

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

U12

U11

H11

G46

F52

F46

F6

E3

D12

C12

C11

C7

B11

AW69

AW68

AW48

AU56

A11

U0500

BGA

TBD

SKL-ULT-2+3E

CRITICAL

OMIT_TABLE

L10

N9

L6

L7

L9

B9

D9

C9

A9

H1

A7

U13

B47

B45

C45

C46

A47

A45

D46

C47

E52

B52

R12

R11

F45

E45

C51

B50

D52

D50

D51

A50

C52

C50

F48

E48

G56

G53

F58

F55

F56

F53

E58

E55

F50

G50

U0500

69 10 8

69 12 8

17 5

28 5

12

70

17 5

69 60 19 16 14 13

17 5

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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SHEET

PAGE TITLE

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A

D

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A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

IN

OUT

NC NC NC NC NC NC NC NC

SYM 20 OF 20

SPARE

RSVDRSVD

RSVD

NC

NC NC NC

NC NC

NC

DISPLAY SIDEBANDS

SYM 1 OF 20

EDP

DDI

EDP_VDDEN

EDP_BKLTEN

EDP_BKLTCTL

GPP_E11/USB2_OC2*

GPP_E10/USB2_OC1*

GPP_E9/USB2_OC0*

GPP_E7/CPU_GP1

GPP_E8/SATALED*

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI1_AUXN

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXN[3]

EDP_TXP[3]

EDP_TXP[2]

EDP_TXN[2]

EDP_TXP[1]

EDP_TXN[1]

EDP_TXP[0]

EDP_TXN[0]

DDI1_TXP[1]

DDI1_TXN[1]

EDP_RCOMP

GPP_E12/USB2_OC3*

GPP_E14/DDPC_HPD1

GPP_E15/DDPD_HPD2

GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

DDI2_TXN[3]

DDI2_TXP[2]

DDI2_TXP[1]

DDI2_TXN[1]

DDI1_TXP[3]

DDI2_TXN[0]

DDI2_TXP[3]

DDI2_TXP[0]

DDI2_TXN[2]

DDI1_TXN[3]

DDI1_TXP[0]

DDI1_TXP[2]

DDI1_TXN[2]

DDI1_TXN[0]

GPP_E13/DDPB_HPD0

合肥怡飞苹果维修qq：82669515 qq群： 241000

(IPU)

DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016

CONNECT TO OPC VRS

(IPU)

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

6 OF 73

6 OF 500

1.0.0

051-02265

PROC_POPIRCOMP PCH_OPIRCOMP

MLB_RAMCFG4 XDP_PCH_OBSDATA_D2

=PP1V_S0SW_CPU_VCCSTG

TP_CPU_AY4

TP_CPU_BB5

PCH_JTAGX

XDP_PCH_TRST_L

XDP_BPM_L<0>

XDP_BPM_L<3>

TP_CPU_RSVD_BA70 TP_CPU_RSVD_BA68

OPC_RCOMP

XDP_BPM_L<1>

XDP_PCH_TCK

=PP1V_S3_CPU_VCCST

CPU_CFG<10>

CPU_CFG<15>

CPU_CFG_RCOMP

CPU_CFG<3> CPU_CFG<4>

CPU_CFG<6> CPU_CFG<7>

ITP_PMODE

TP_CPU_RSVD_BB69

TP_CPU_RSVD_AK12

TP_CPU_AU5 TP_CPU_AT5

BT_TIMESTAMP

BT_PWRRST_L

CPU_PECI

CPU_PROCHOT_R_L

XDP_BPM_L<2>

CPU_CFG<11> CPU_CFG<12> CPU_CFG<13>

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2>

CPU_CFG<9>

CPU_CFG<14>

CPU_CFG<8>

OPCE_RCOMP

CPU_CFG<16> CPU_CFG<17>

TP_CPU_BB3

XDP_CPU_TMS XDP_CPU_TRST_L

XDP_PCH_TDI XDP_PCH_TDO

CPU_MSM_L

CPU_ZVM_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_CPU_TCK

TP_CPU_RSVD_AW70

TP_CPU_RSVD_AW71

XDP_PCH_TMS

TP_CPU_RSVD_AK13

CPU_CFG<19>

CPU_CFG<18>

CPU_CFG<5>

CPU_CATERR_L

PM_THRMTRIP_L

CPU_PROCHOT_L

CPU_CFG<4>

TP_CPU_RSVD_BB68

CPU MISC/JTAG/CFG/RSVD

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

201

MF

1/20W

5%

1K

EDP_ENABLE

2

1

R0634

201

MF

1/20W

1%

49.9

2

1

R0680

68

39 19

40

68 54 40 39

13

201

MF

1/20W

1%

PLACE_NEAR=U0500.H65:12.7MM

49.9

2

1

R0684

201

MF

1/20W

1%

PLACE_NEAR=U0500.H66:12.7MM

49.9

2

1

R0683

13

17

59

201

MF

1/20W

1%

PLACE_NEAR=U0500.AU16:12.7MM

49.9

2

1

R0682

201

MF

1/20W

1%

PLACE_NEAR=U0500.AT16:12.7MM

49.9

2

1

R0681

201

MF

1/20W

5%

PLACE_NEAR=U0500.C63:254MM

1K

2

1

R0612

40 39

201

MF

1/20W

5%

PLACE_NEAR=R0611:1MM

1K

2

1

R0610

201

MF

1/20W

1%

PLACE_NEAR=U0500.C65:25.4MM

499

2 1

R0611

19

72 17

17

72 17

19

72 17

17

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AR56

G65

F65

AY71

AT5

AU5

BB5

BB3

AY4

BB69

BB68

BA70

BA68

AW71

AW70

AK13

AK12

K46

K45

J71

J68

F61

F60

E61

E2

E1

D71

D54

D5

D4

D3

D1

C71

C70

C54

C4

C2

BB4

BB2

BA4

BA3

B70

B69

B3

B2

AY3

AY2

AY1

AW1

AL27

AL25

A69

A52

A4

A3

C64

AP56

E8

E60

F66

E66

F63

E63

G70

H69

G71

H70

G68

F70

G69

F71

C67

D68

C68

E70

D67

D65

B67

E68

U0500

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

C63

A65

C65

B59

C60

A61

D60

B61

AT16

A54

C61

AU16

C59

A56

D59

B56

H66

H65

A59

H3

V1

AY5

BA5

D63

C56

B54

D55

C55

U0500

17

17 6

17

72 17

17

69 17 10 8

70

69 59 54 19 14 10 8

70

19

17 6

70

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

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D

R

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PAGE TITLE

C

A

D

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

BI

IN

NC

OUT

NC

NC NC

NC

NC NC

OUT

NCNC

NC

NC NC

NC

OUT

BI

IN

OUT

IN

OUT

BI

IN

BI

IN

OUT

BI

RESERVED

SYM 19 OF 20

RSVD

RSVD_TP

RSVD

VSS

RSVD

CFG_RCOMP

ITP_PMODE

RSVD

CFG[16]

CFG[17]

CFG[19]

CFG[18]

CFG[15]

CFG[12]

CFG[11]

CFG[9]

CFG[7]

CFG[10]

CFG[6]

CFG[5]

CFG[4]

CFG[3]

CFG[2]

CFG[1]

CFG[0]

MSM*

TP2

TP1

VSS

RSVD_TP

PROC_SELECT*

RSVD

TP4

RSVD

TP6

TP5

RSVD

RSVD_TP

ZVM*

CFG[14]

CFG[13]

CFG[8]

JTAG

CPU MISC

SYM 4 OF 20

PROC_TDI

PROC_TCK

PROC_TDO

PROC_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TCK

PROC_TRST*

PCH_TRST*

JTAGX

PECI

CATERR*

BPM[0]*

SKTOCC*

THERMTRIP*

PROCHOT*

BPM[1]*

BPM[3]*

BPM[2]*

GPP_B4/CPU_GP3

PROC_POPIRCOMP

PCH_OPIRCOMP

GPP_D21/SPI1_IO2

GPP_B3/CPU_GP2

GPP_E1/SATAXPCIE1/SATAGP1

OPCE_RCOMP

OPC_RCOMP

BI

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7 OF 73

7 OF 500

1.0.0

051-02265

MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQS_P<5>

MEM_B_DQ<55>

MEM_B_DQ<52>

MEM_A_DQ<49> MEM_A_DQS_P<3>

MEM_B_DQ<40>

MEM_B_DQ<36>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<6>

MEM_B_DQ<10>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_A_DQS_P<7>

MEM_A_DQS_P<4>

MEM_A_DQ<15>

MEM_A_DQ<47>

MEM_A_DQ<51> MEM_A_DQ<52>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<10>

MEM_A_DQ<5>

MEM_A_DQ<42>

MEM_A_DQ<17>

MEM_A_DQ<54>

MEM_A_CKE<0>

MEM_A_DQ<23>

MEM_A_DQ<8>

MEM_A_DQ<31>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<21>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<22>

MEM_A_DQ<3>

MEM_A_DQ<20>

MEM_A_DQ<40>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<16>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<37>

MEM_A_CAB<0>

MEM_A_DQ<58>

MEM_A_DQ<50>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<57>

MEM_A_DQ<53>

MEM_A_DQ<45>

MEM_A_DQ<43>

MEM_A_DQS_N<0>

MEM_A_CAB<7>

MEM_A_CAB<1>

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_CAA<7>

MEM_A_CAA<6>

MEM_A_CAA<2>

MEM_A_CAB<2>

MEM_A_CAB<4>

MEM_A_CAB<9>

MEM_A_CAA<1>

MEM_A_CAA<5>

MEM_A_CAA<4>

MEM_A_CAB<6>

MEM_A_CAB<5>

MEM_A_CKE<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_N<3>

MEM_A_DQS_P<1>

MEM_A_DQS_N<4>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<0>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3>

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_DQS_P<4>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_CAB<9>

MEM_B_CAB<8>

MEM_B_CAB<7>

MEM_B_CAB<6>

MEM_B_CAB<5>

MEM_B_CAB<4>

MEM_B_CAB<3>

MEM_B_CAB<2>

MEM_B_CAB<1>

MEM_B_CAB<0>

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<5>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_ODT<0>

MEM_B_DQ<29>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<3>

MEM_B_CKE<2>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<23>

MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22>

MEM_B_DQ<24>

MEM_B_DQ<27> MEM_B_DQ<28>

MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<35>

MEM_B_DQ<37>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<60>

MEM_B_DQ<56>

MEM_B_DQ<59>

MEM_B_DQ<62>

MEM_A_DQ<0>

MEM_A_DQS_N<5>

MEM_A_DQS_P<2>

MEM_B_DQ<58>

MEM_B_DQ<51>

MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_CAA<3>

MEM_B_DQ<7> MEM_B_DQ<8>

MEM_A_CAB<3>

MEM_A_DQ<26>

MEM_A_DQ<6>

MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<48>

MEM_B_DQ<57>

MEM_B_DQ<38>

MEM_A_CAB<8>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_CAA<0>

MEM_B_DQ<11>

MEM_B_DQ<9>

MEM_B_DQ<14> MEM_B_DQ<15>

MEM_A_CLK_N<0> MEM_B_CLK_N<0>

CPU_DDR_RCOMP<2>

CPU_DDR_RCOMP<1>

CPU_DDR_RCOMP<0>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<39>

CPU_DIMM_VREFCA

MEM_A_DQ<7>

MEM_A_DQ<4>

PM_MEMVTT_EN

BOM_COST_GROUP=CPU & CHIPSET

CPU LPDDR3 Interface

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

201

MF

1/20W

1%

PLACE_NEAR=U0500.AR18:6MM

200

2

1

R0702

201

MF

1/20W

1%

PLACE_NEAR=U0500.AT18:6MM

80.6

2

1

R0701

201

MF

1/20W

1%

PLACE_NEAR=U0500.AU18:6MM

162

2

1

R0700

62

72 25 23

72 25 24

72 25 21

72 25 22

72 25 22 21

72 25 21

72 25 22

72 25 22 21

72 71

72

71

72 71

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AT13

AU18

AT18

AR18

AP43

AW42

BA42

BA47

BB46

AR21

AR27

BA26

AY30

AR32

AR38

BA34

AY38

AR22

AR25

AY26

BA30

AT32

AT38

AY34

BA38

AN21

AP21

AP22

AN22

AT21

AU21

AU22

AT22

AP25

AN25

AN27

AP27

AU25

AT25

AT27

AU27

BB25

BA25

BA27

BB27

AW25

AY25

AW27

AY27

BB29

BA29

BA31

BB31

AW29

AY29

AW31

AY31

AP30

AR30

AP33

AR33

AT30

AU30

AU33

AT33

AR37

AP37

AP40

AR40

AU37

AT37

AT40

AU40

BB33

BA33

BA35

BB35

AW33

AY33

AW35

AY35

BB37

BA37

BA39

BB39

AW37

AY37

AW39

AY39

AY42

BB42

AP46

AP45

AN46

AN45

AP53

AN55

AP55

AN56

BA46

AY46

AW46

BA44

AY47

BB44

AW44

AY44

AY43

BA43

AN52

AN53

AN48

AN50

AP52

AP48

BB48

BA48

AP50

AY48

AN43

U0500

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AW67

AY67

BA67

AY68

AT52

AT43

AT45

BB52

BA50

AR60

AR65

BA60

AY64

AG70

AH65

AT70

AM69

AR61

AR66

AY60

BA64

AG69

AH66

AT69

AM70

AU60

AT60

AP61

AN61

AN60

AP60

AU61

AT61

AU65

AT65

AP66

AN66

AN65

AP65

AU66

AT66

AY59

BA59

AY61

BB61

AW59

BB59

AW61

BA61

BB63

BA63

AY65

BA65

AY63

AW63

AW65

BB65

AH69

AH70

AF69

AF71

AH68

AH71

AF68

AF70

AK66

AK67

AF67

AF66

AK64

AK65

AF64

AF65

AU69

AU70

AR69

AR71

AU68

AU71

AR68

AR70

AN71

AN70

AL69

AL70

AN69

AN68

AL68

AL71

AU43

AU45

AT55

AT53

AU55

AU53

AY56

AW56

BB56

BA56

AY50

BB50

AT50

AT48

AY51

AU52

AU50

AT46

AU48

AU46

AY54

BA55

BA54

AW54

AY55

AW52

AY52

BA52

BB54

BA51

AW50

U0500

72 25 24

72 25 23

72 25 24

72 25 23

72 71

72 25 22

72 25

22

72 25 22

72 25 21

72 71

72 25 24 23

72 25 24

72 25 23

20

72 71

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

NC

NCNC

OUT

NCNC

OUT

BI

LPDDR3 NON-INTERLEAVED

SYM 3 OF 20

DDR1_DQ[0]

DDR1_DQ[1]

DDR1_DQ[2]

DDR1_DQ[3]

DDR1_MA[3]

DDR1_MA[4]

DRAM_RESET*

DDR_RCOMP[2]

DDR_RCOMP[0]

DDR_RCOMP[1]

DDR1_PAR

DDR1_ALERT*

DDR1_DQSP[6]

DDR1_DQSP[7]

DDR1_DQSP[5]

DDR1_DQSP[4]

DDR1_DQSP[3]

DDR1_DQSP[2]

DDR1_DQSP[1]

DDR1_DQSP[0]

DDR1_DQSN[7]

DDR1_DQSN[6]

DDR1_DQSN[5]

DDR1_DQSN[4]

DDR1_DQSN[3]

DDR1_DQSN[2]

DDR1_DQSN[1]

DDR1_DQSN[0]

DDR1_CAB[9]

DDR1_CAB[8]

DDR1_CAB[7]

DDR1_CAB[6]

DDR1_CAB[5]

DDR1_CAB[4]

DDR1_CAB[3]

DDR1_CAB[2]

DDR1_CAB[1]

DDR1_CAB[0]

DDR1_CAA[9]

DDR1_CAA[8]

DDR1_CAA[7]

DDR1_CAA[6]

DDR1_CAA[5]

DDR1_CAA[4]

DDR1_CAA[3]

DDR1_CAA[2]

DDR1_CAA[1]

DDR1_CAA[0]

DDR1_ODT[1]

DDR1_ODT[0]

DDR1_DQ[33]

DDR1_DQ[29]

DDR1_CS[1]*

DDR1_CS[0]*

DDR1_CKE[3]

DDR1_CKE[2]

DDR1_CKE[1]

DDR1_CKE[0]

DDR1_CKN[0]

DDR1_CKP[0]

DDR1_CKP[1]

DDR1_CKN[1]

DDR1_DQ[8]

DDR1_DQ[6]

DDR1_DQ[5]

DDR1_DQ[4]

DDR1_DQ[7]

DDR1_DQ[9]

DDR1_DQ[19]

DDR1_DQ[18]

DDR1_DQ[17]

DDR1_DQ[16]

DDR1_DQ[15]

DDR1_DQ[14]

DDR1_DQ[10]

DDR1_DQ[13]

DDR1_DQ[12]

DDR1_DQ[11]

DDR1_DQ[23]

DDR1_DQ[20]

DDR1_DQ[21]

DDR1_DQ[22]

DDR1_DQ[24]

DDR1_DQ[25]

DDR1_DQ[26]

DDR1_DQ[27]

DDR1_DQ[28]

DDR1_DQ[30]

DDR1_DQ[31]

DDR1_DQ[32]

DDR1_DQ[34]

DDR1_DQ[35]

DDR1_DQ[36]

DDR1_DQ[37]

DDR1_DQ[38]

DDR1_DQ[39]

DDR1_DQ[40]

DDR1_DQ[46]

DDR1_DQ[47]

DDR1_DQ[48]

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[42]

DDR1_DQ[41]

DDR1_DQ[45]

DDR1_DQ[44]

DDR1_DQ[43]

DDR1_DQ[60]

DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

SYM 2 OF 20

LPDDR3 NON-INTERLEAVED0

DDR0_PAR

DDR0_ALERT*

DDR0_DQSP[7]

DDR0_DQSP[4]

DDR0_DQSP[1]

DDR0_DQSP[0]

DDR0_DQSN[7]

DDR0_DQSN[6]

DDR0_DQSN[5]

DDR0_DQSN[4]

DDR0_DQSN[3]

DDR0_DQSN[2]

DDR0_DQSN[1]

DDR0_DQSN[0]

DDR0_MA[3]

DDR0_DQ[49]

DDR_VTT_CNTL

DDR1_VREF_DQ

DDR0_VREF_DQ

DDR_VREF_CA

DDR0_MA[4]

DDR0_DQSP[6]

DDR0_DQSP[5]

DDR0_DQSP[3]

DDR0_DQSP[2]

DDR0_CAB[9]

DDR0_CAB[8]

DDR0_CAB[7]

DDR0_CAB[6]

DDR0_CAB[4]

DDR0_CAB[5]

DDR0_CAB[3]

DDR0_CAB[2]

DDR0_CAB[1]

DDR0_CAB[0]

DDR0_DQ[24]

DDR0_CAA[9]

DDR0_CAA[8]

DDR0_CAA[7]

DDR0_CAA[6]

DDR0_CAA[5]

DDR0_CAA[4]

DDR0_CAA[3]

DDR0_CAA[2]

DDR0_CAA[1]

DDR0_CAA[0]

DDR0_ODT[1]

DDR0_ODT[0]

DDR0_CKN[1]

DDR0_CKP[0]

DDR0_CKE[3]

DDR0_DQ[4]

DDR0_DQ[5]

DDR0_CS[0]*

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKN[0]

DDR0_DQ[3]

DDR0_DQ[61]

DDR0_DQ[62]

DDR0_DQ[60]

DDR0_DQ[59]

DDR0_DQ[58]

DDR0_DQ[57]

DDR0_DQ[56]

DDR0_DQ[53]

DDR0_DQ[54]

DDR0_DQ[55]

DDR0_DQ[51]

DDR0_DQ[52]

DDR0_DQ[48]

DDR0_DQ[50]

DDR0_DQ[47]

DDR0_DQ[46]

DDR0_DQ[45]

DDR0_DQ[43]

DDR0_DQ[44]

DDR0_DQ[41]

DDR0_DQ[42]

DDR0_DQ[40]

DDR0_DQ[39]

DDR0_DQ[38]

DDR0_DQ[36]

DDR0_DQ[37]

DDR0_DQ[35]

DDR0_DQ[34]

DDR0_DQ[33]

DDR0_DQ[32]

DDR0_DQ[31]

DDR0_DQ[30]

DDR0_DQ[28]

DDR0_DQ[29]

DDR0_DQ[25]

DDR0_DQ[26]

DDR0_DQ[27]

DDR0_DQ[21]

DDR0_DQ[20]

DDR0_DQ[19]

DDR0_DQ[18]

DDR0_DQ[17]

DDR0_DQ[16]

DDR0_DQ[15]

DDR0_DQ[14]

DDR0_DQ[13]

DDR0_DQ[12]

DDR0_DQ[11]

DDR0_DQ[10]

DDR0_DQ[9]

DDR0_DQ[8]

DDR0_DQ[7]

DDR0_DQ[6]

DDR0_DQ[2]

DDR0_DQ[1]

DDR0_DQ[0]

DDR0_CS[1]*

DDR0_CKE[0]

DDR0_CKP[1]

DDR0_DQ[63]

DDR0_DQ[23]

DDR0_DQ[22]

OUT

BI

OUT

BI

OUT

BI

合肥怡飞苹果维修qq：82669515 qq群： 241000

R0829:

R0831:

R0830:

8 OF 73

1.0.0

8 OF 500

051-02265

CPU_VCCGTSENSE_N

CPU_VCCSASENSE_N

CPU_VCCEOPIOSENSE_N

CPU_VCCIOSENSE_N

CPU_VCCGTXSENSE_P

CPU_VIDSOUT_R

CPU_VIDSOUT

CPU_VIDSCLK_R

CPU_VIDSCLK

CPU_VIDALERT_R_L CPU_VIDALERT_L

=PP1V_S3_CPU_VCCST

CPU_VCCIOSENSE_P

CPU_VCCSASENSE_P

=PPVCCGT_S0_CPU CPU_VCCGTSENSE_P

CPU_VCCGTXSENSE_P

=PP1V_S0_CPU_VCCOPC_AB62 CPU_VCCOPCSENSE_P

=PP1V_S0_CPU_VCCEOPIO_AE62 CPU_VCCEOPIOSENSE_P

CPU_VCCGTXSENSE_N

CPU_VCCSENSE_N

CPU_VCCEOPIOSENSE_N

=PP1V_S0_CPU_VCCEOPIO_AG62

=PP1V_S0_CPU_VCCEOPIO_AE62

=PP1V_S0_CPU_VCCOPC_V62

=PP1V2_S0SW_CPU_VCCPLLOC

CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N

CPU_VCCEOPIOSENSE_P

=PP0V95_S0_CPU_VCCIO

=PPVCCGTX_S0_CPU

=PP1V_S0SW_CPU_VCCSTG

=PP1V8_SUS_CPU_VCCOPC_H63

CPU_VCCOPCSENSE_P

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VCCGTXSENSE_N

=PP1V_SUSSW_PCH_VCCAPLLEBB

=PP1V_SUSSW_PCH_VCCAMPHYPLL

=PP1V_SUSSW_PCH_VCCSRAM

=PP3V3_SUS_PCH_VCCSPI

=PP1V8_S0_PCH_VCCHDA_F

=PP3V3_S5_PCH_VCCDSW

=PP1V_SUSSW_PCH_VCCMPHYGT

=PPVCCPRIMECORE_SUS_PCH

=PP1V8_SUS_PCH_VCCATS

=PP3V_G3H_PCH_VCCRTC

=PP1V_SUS_PCH_VCCCLK1

=PP1V_SUS_PCH_VCCCLK2

=PP1V_SUS_PCH_VCCAPLL_F

=PP1V_S0_CPU_VCCOPC_AB62 =PP1V_S0_CPU_VCCOPC_P62

=PP1V_SUS_PCH_VCCCLK6

=PP1V_SUS_PCH_VCCCLK3

=PP3V3_SUS_PCH_VCCPRIM

=PP3V3_SUS_PCH_VCCPGPPC

=PP3V3_SUS_PCH_VCCRTCPRIM

PPDCPRTC_PCH

CPU_VCCOPCSENSE_N

=PP1V8_SUS_CPU_VCCOPC_G61

=PP1V_SUS_PCH_VCCPRIM

=PP1V_S0SW_CPU_VCCSTG

=PP1V_S3_CPU_VCCPLL

=PP3V3_SUS_PCH_VCCPGPPD

=PP1V8_SUS_PCH_VCCPGPPF

=PP1V_SUS_PCH_VCCPRIM

=PP3V3_SUS_PCH_VCCPRIM

CPU_VCCOPCSENSE_N

=PP1V2_S3_CPU_VDDQC

=PP1V_S3_CPU_VCCST

=PP1V_SUS_PCH_VCCMPHYAON

PP1V_S5_PCH_DCPDSW

=PP3V3_SUS_PCH_VCCPGPPB

=PP3V3_SUS_PCH_VCCPGPPA

=PP3V3_SUS_PCH_VCCPGPPE

=PP3V3_SUS_PCH_VCCPGPPG

=PPVCCSA_S0_CPU

=PP1V2_S3_CPU_VDDQ

=PPVCC_S0_CPU

CPU_VCCIOSENSE_P

CPU_VCCSASENSE_N CPU_VCCSASENSE_P

=PP1V_SUS_PCH_VCCCLK4

VCCPRIM_CORE_VID0 VCCPRIM_CORE_VID1

=PP1V_SUS_PCH_VCCCLK5

=PPVCC_S0_CPU

=PPVCCGT_S0_CPU

CPU_VCCSENSE_P

=PP1V_SUS_PCH_FUSE

=PPVCCGTX_S0_CPU

=PPVCCSA_S0_CPU

=PP0V95_S0_CPU_VCCIO

CPU_VCCIOSENSE_N

SYNC_DATE=06/15/2015SYNC_MASTER=PAULM

CPU & PCH Power

BOM_COST_GROUP=CPU & CHIPSET

54

201

MF

1/20W

1%

100

2

1

R0828

201

MF

1/20W

1%

56

2

1

R0827

201

MF

1/20W

1%

PLACE_NEAR=U0500.B63:12.7MM

220

21

R0829

201MF1/20W5%

PLACE_NEAR=U0500.E33:50.8MM

100

2 1

R0826

201MF1/20W5%

PLACE_NEAR=U0500.AJ62:50.8MM

100

2 1

R0824

201MF1/20W5%

PLACE_NEAR=U0500.AE63:50.8MM

100

2 1

R0822

201MF1/20W5%

PLACE_NEAR=U0500.AL61:50.8MM

100

2 1

R0814

201MF1/20W5%

PLACE_NEAR=U0500.J69:50.8MM

100

2 1

R0812

201MF1/20W5%

PLACE_NEAR=U0500.H21:50.8MM

100

2 1

R0803

201MF1/20W5%

PLACE_NEAR=U0500.AM22:50.8MM

100

2 1

R0802

0201

MF

1/20W

5%

PLACE_NEAR=U0500.D64:12.7MM

0

21

R0831

0201

MF

1/20W

5%

PLACE_NEAR=U0500.A63:12.7MM

0

21

R0830

201MF1/20W5%

PLACE_NEAR=U0500.E32:50.8MM

100

21

R0825

201MF1/20W5%

PLACE_NEAR=U0500.AL63:50.8MM

100

21

R0823

201MF1/20W5%

PLACE_NEAR=U0500.AC63:50.8MM

100

21

R0821

201MF1/20W5%

PLACE_NEAR=U0500.AK62:50.8MM

100

21

R0813

201MF1/20W5%

PLACE_NEAR=U0500.J70:50.8MM

100

21

R0811

201MF1/20W5%

PLACE_NEAR=U0500.H20:50.8MM

100

21

R0804

201MF1/20W5%

PLACE_NEAR=U0500.AM23:50.8MM

100

21

R0801

70

59 8

54 8

61 8

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

T20

T19

AF21

AF20

AJ16

AK17

BB14

AK19

V21

V20

AF19

AF18

V19

AJ21

Y18

T1

P18

AK20

AB20

AB19

AB17

AD15

AF16

T16

Y15

Y16

AG15

AK15

P16

P15

N17

N16

N15

L1

K17

AJ19

AJ17

AD18

AD17

A10

L19

N20

L21

K19

A14

AA1

N18

V15

L15

K15

AN13

AN11

BB10

AL1

U0500

72 54 8

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AL61J69

AK62

BB66

BB57

AU63

AU58

AM58

AM56

AM53

AM52

AM50

AM48

AL60

AL56

AL53

AL50

AL46

AL43

AK70

AK60

AK58

AK56

AK55

AK53

AK52

AK50

AK48

AK46

AK45

AK43

AK42

Y62

W71

W70

W69

W68

W67

W66

W65

W64

W63

U71

U68

U65

T62

J70

R71

R70

R69

R68

R67

R66

R65

R64

R63

N71

N70

N69

N67

N66

N64

N63

M62

L71

L70

L69

L68

L67

L66

L65

L64

L63

L62

K60

K58

K56

K55

K53

K52

K50

K48

J60

J58

J56

J55

J53

J52

J50

J48

J46

J45

J43

AC71

AC70

AC69

AC68

AC67

AC66

AC65

AC64

AA71

AA70

AA69

AA67

AA66

AA64

AA63

A66

A62

A58

A53

A48

U0500

54 8

69 8

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AE63

AJ62

E33

D64

A63

B63

G20

V62

AC63

P62

AB62

AL63

AG62

AE62

E32

H63

G61

K43

K42

K40

K38

K37

K35

K33

J40

J37

J33

J30

G42

G40

G38

G37

G35

G33

G32

G30

AM38

AM37

AM35

AM33

AM32

AL40

AL37

AL33

AK40

AK38

AK37

AK35

AK33

A44

A39

A34

A30

K32

AK32

U0500

54 8

54

8

54

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

H21

AM22

AM40

BB51

BB47

BB41

BB32

BB23

AU42

AU35

AU28

AU23

A22

A18

H20

K30

K28

K27

K25

K23

J27

J23

J22

G28

G27

G25

G23

AK25

AK23

AL23

K21

K20

AM23

AM42

AM30

AM28

AL42

AL30

AK30

AK28

U0500

72 54 8

54 8

59 8

61 8

69 59 54 19 14 10 8 6

61 8

54 8

69 11 8 54 8

69 8

59 8 59 8

69 8

54 8

59

59 8

59

69 10

69 10 8 5

69 11 8

69 17

10 8 6

59

69 12

12

69 12

69 47 13

12

69 14

69 12

69 15 14 12

69

12

59 8

59

69 12

69

69 12 8 5

69 12

12

59

69 12 8

69 17 10 8 6

69 10

69

69 14

69 12 8

69 12 8 5

59 8

69 10

69 59 54 19 14 10 8 6

69 12

12

69 19 12

69 16 15 14 13

69 12

69

69 10 8

69 10

69 10 8

12

69 10 8

69 11 8

54 8

64 12

69 11 8

69 10 8

69 10 8 5

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

NC

OUT

NC

OUT

CPU POWER 4

SYM 15 OF 20

VCCSRAM_1P0

VCCPRIM_3P3

VCCPRIM_1P0

VCCAPLLEBB_1P0

VCCAMPHYPLL_1P0

VCCSRAM_1P0

VCCSPI

VCCHDA

VCCDSW_3P3

VCCPRIM_1P0

VCCAPLL_1P0

VCCMPHYGT_1P0

VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0

VCCMPHYGT_1P0

VCCPRIM_CORE

VCCPRIM_1P0

VCCPRIM_CORE

VCCPGPPA

VCCPGPPB

VCCPGPPC

VCCPGPPD

VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0

GPP_B1/CORE_VID1

OUT

SYM 13 OF 20

CPU POWER 2

VCCGT

VCCGTX

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT

VCCGT_SENSE

VSSGT_SENSE

OUT

SYM 12 OF 20

CPU POWER 1

VCCSTG

VCC

VIDSOUT

VIDSCK

VIDALERT*

VSS_SENSE

VCC_SENSE

VCC

RSVD

VCCOPC

VCC_OPC_1P8

VSSOPC_SENSE

VCCEOPIO

VCC_OPC_1P8

VCCOPC_SENSE

VCCEOPIO

VCCEOPIO_SENSE

VSSEOPIO_SENSE

OUT

BI

OUT

SYM 14 OF 20

CPU POWER 3

VCCSA_SENSE

VSSSA_SENSE

VSSIO_SENSE

VCCIO

VCCSA

VCCIO_SENSE

VDDQ

VDDQC

VCCST

VDDQ

VCCSTG

VCCPLL_OC

VCCPLL

合肥怡飞苹果维修qq：82669515 qq群： 241000

9 OF 500

051-02265

1.0.0

9 OF 73

TP_CPU_NCTFVSS_BB70 TP_CPU_NCTFVSS_C1

TP_CPU_NCTFVSS_BA71

TP_CPU_NCTFVSS_B71 TP_CPU_NCTFVSS_BA1

TP_CPU_NCTFVSS_AV1

TP_CPU_NCTFVSS_A5

TP_CPU_NCTFVSS_A70

CPU & PCH Grounds

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

Y21

Y20

Y19

Y17

W13

W9

W6

V18

V17

V16

U70

U69

U67

U66

U64

U63

U10

T21

T18

T17

T15

T4

T2

R13

R6

P21

P20

P19

P17

N68

N65

N21

N19

N13

N10

N6

L20

L18

L17

L16

L11

L8

L4

L2

K71

K70

K68

K67

K66

K65

K64

K63

K61

K22

K18

K16

J42

J38

J35

J32

J28

J25

J13

J11

J8

H71

H18

H15

G66

G63

G60

G58

G55

G52

G48

G45

G43

G22

G10

G6

G5

F8

U0500

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

F68

F42

F40

F38

F37

F35

F33

F32

F28

F27

F23

F22

F13

F4

F2

F1

E71

E65

E56

E53

E50

E46

E21

E18

E15

E11

E6

D69

D66

D62

D58

D53

D48

D47

D45

D44

D39

D34

D30

D26

D25

D22

D18

D14

D11

D10

D6

C25

C5

C1

BB70

BB67

BB64

BB60

BB55

BB43

BB38

BB34

BB30

BB26

BB18

BB6

BA71

BA66

BA62

BA57

BA53

BA49

BA45

BA41

BA36

BA32

BA28

BA23

BA18

BA14

BA10

BA6

BA2

BA1

B71

B66

B62

B58

B53

B48

B44

B39

B34

B30

B22

B18

B14

B10

AY66

AW66

AW64

AW62

AW60

AW57

AW55

AW53

AW51

AW49

AW47

AW45

AW43

AW41

AW38

AW36

AW34

AW32

AW30

AW28

AW26

AW23

AW21

AW18

AW16

AW14

AW12

AW10

AW8

AW6

AV71

AV70

AV69

AV68

AV1

AU38

AU32

AU20

AU15

AU10

AT71

AT68

AT63

U0500

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AT58

AT56

AT42

AT35

AT28

AT23

AT20

AT4

AT2

AR63

AR58

AR55

AR53

AR52

AR50

AR48

AR46

AR45

AR43

AR42

AR35

AR28

AR23

AR20

AR16

AR15

AR11

AR8

AR5

AP70

AP68

AP63

AP58

AP42

AP38

AP35

AP32

AP28

AP23

AP20

AP18

AP10

AN63

AN58

AN42

AN40

AN38

AN37

AN35

AN33

AN32

AN30

AN28

AN23

AN20

AM71

AM68

AM61

AM60

AM55

AM46

AM45

AM43

AM27

AM25

AM21

AM13

AM8

AL66

AL65

AL64

AL58

AL55

AL52

AL48

AL45

AL38

AL35

AL32

AL28

AL4

AL2

AK69

AK68

AK63

AK27

AK22

AK21

AK18

AK16

AK11

AK8

AJ20

AJ18

AJ15

AJ4

AH67

AH64

AH63

AH13

AH6

AG71

AG21

AG20

AG19

AG18

AG17

AG16

AF63

AF17

AF15

AF10

AF4

AF2

AF1

AE69

AE68

AE67

AE66

AE65

AE64

AD62

AD21

AD20

AD19

AD16

AD13

AD8

AB21

AB18

AB16

AB15

AB8

AA68

AA65

AA4

AA2

A70

A67

A5

U0500

70

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND 3

SYM 18 OF 20

VSS

VSSVSS

VSS

GND2

SYM 17 OF 20

VSS

SYM 16 OF 20

GND1

VSS

VSSVSS

VSS

合肥怡飞苹果维修qq：82669515 qq群： 241000

051-02265

1.0.0

10 OF 500

10 OF 73

=PPVCCSA_S0_CPU

=PP1V2_S3_CPU_VDDQ

=PP1V_S3_CPU_VCCPLL

=PP1V_S0_CPU_VCCEOPIO

=PP1V2_S0SW_CPU_VCCPLLOC =PP1V_S3_CPU_VCCST =PP1V_S0SW_CPU_VCCSTG

=PP1V_S0_CPU_VCCOPC

=PP0V95_S0_CPU_VCCIO

=PP1V2_S3_CPU_VDDQC

=PPVCC_S0_CPU

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

CPU Core Decoupling

BOM_COST_GROUP=CPU & CHIPSET

0402

X6S

4V

20%

10UF

CRITICAL NOSTUFF

2

1

C1094

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10F3

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10F2

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10F1

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10F0

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C10E1

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C10E0

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D1

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D2

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D3

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C10D0

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D4

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D5

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10D6

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1091

0402

X6S

4V

20%

10UF

CRITICAL NOSTUFF

2

1

C1092

0402

X6S

4V

20%

10UF

CRITICAL NOSTUFF

2

1

C1093

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1090

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1080

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1081

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1082

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1083

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1084

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1085

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1070

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1071

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1066

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1065

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1064

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1055

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1054

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1063

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1062

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1060

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1061

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1053

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1052

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1051

0402

X6S

4V

20%

10UF

CRITICAL

2

1

C1050

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C10G1

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C10G0

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1010

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100I

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100J

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100K

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100L

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100M

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100N

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100O

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100P

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100Q

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100R

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100S

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100T

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100U

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100V

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100W

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100X

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100Y

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100C

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100D

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100E

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100F

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100G

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100H

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1006

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1007

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1008

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1009

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100A

0201

X6S-CERM

6.3V

20%

1UF

2

1

C100B

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1005

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1004

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1003

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1002

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1001

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1000

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10CA

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10BA

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C6

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B6

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C7

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B7

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C8

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B8

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C9

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B9

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101K

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101L

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C101A

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C101B

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101C

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101D

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101E

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101F

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101G

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101H

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101I

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C101J

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C10G4

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL NOSTUFF

3 2

1

C10H1

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C10H0

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C10C0

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C1

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C2

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C10C3

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10C4

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C10C5

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B5

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C10B4

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B3

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B2

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B1

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A0

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A1

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A2

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A3

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A4

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A5

0201

X6S-CERM

6.3V

20%

1UF

2

1

C10A6

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C10B0

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1020

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1021

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1022

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1023

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1024

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1029

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1028

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1027

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1026

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1025

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1015

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1016

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1017

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1018

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1019

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1014

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1013

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1012

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1011

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C10G3

0402

X6S

4V

20%

10UF

CRITICAL NOSTUFF

2

1

C1095

69 8

59

69 8

69

59 54 19 14 8 6 69 17 8 6

59

69 8 5

69 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

合肥怡飞苹果维修qq：82669515 qq群： 241000

051-02265

1.0.0

11 OF 500

11 OF 73

=PPVCCGTX_S0_CPU

=PPVCCGT_S0_CPU

CPU GT Decoupling

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110L

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110K

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1105

X6S-CERM 0201

6.3V

20%

1UF

2

1

C110J

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1104

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110I

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1103

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110H

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1102

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110G

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1101

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110F

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1100

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110E

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C1161

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1157

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1156

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1150

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1194

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1195

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1151

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1196

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1152

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1197

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1153

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1198

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1154

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1199

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1155

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1140

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1130

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1141

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1131

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1142

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1132

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1143

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1133

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1144

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1134

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1145

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1135

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1146

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1147

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1136

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1137

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1148

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1138

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1149

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1139

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL NOSTUFF

3 2

1

C1164

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C1191

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1180

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1181

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1182

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1183

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1184

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1185

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1186

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1187

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1177

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1176

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1175

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1174

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1173

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1172

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1171

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1170

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1120

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1121

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1122

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1123

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1124

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1129

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1128

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1127

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1126

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1125

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1115

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL

2

1

C1116

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1117

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1118

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1119

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1114

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1113

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1112

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1111

0402

X6S-CERM

2.5V

20%

20UF

CRITICAL NOSTUFF

2

1

C1110

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL NOSTUFF

3 2

1

C1190

CRITICAL

SM-COMBO

ELEC

2V

20%

220UF

3 2

1

C1163

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C1162

SM-COMBO

ELEC

2V

20%

220UF

CRITICAL

3 2

1

C1160

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110V

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110W

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110X

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110U

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110T

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110S

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110D

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110C

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110R

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110Q

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110B

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110A

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110P

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110O

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1109

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1108

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110N

0201

X6S-CERM

6.3V

20%

1UF

2

1

C110M

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1107

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1106

69 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

合肥怡飞苹果维修qq：82669515 qq群： 241000

FILTER PLACEHOLDERS ONLY

PCH SIDERAIL SIDE

FOR FUTURE PRODUCT PER PDG

CPU CIRCUITS GENERATE NOISE AT WIFI BAND FREQUENCIES.

USE SPECIFIC 3PF CAPS FOR BEST FILTERING OF THOSE FREQUNCIES.

12 OF 73

12 OF 500

1.0.0

051-02265

=PP1V_SUS_PCH_VCCCLK5_SRC

=PP1V_SUSSW_PCH_VCCAPLLEBB

=PP3V3_SUS_PCH_VCCPRIM

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCCLK5_F=PP3V3_SUS_PCH_VCCPGPPC

=PP1V_SUS_PCH_VCCCLK4_SRC

MAKE_BASE=TRUE

PP1V8_SUS_PCH_VCC1P8

=PP1V8_SUS_PCH_VCC1P8_SRC

=PP3V3_SUS_PCH_VCCRTCPRIM

=PP1V_SUS_PCH_VCCCLK2=PP1V_SUS_PCH_VCCCLK2_SRC

=PP1V8_SUS_PCH_VCCATS

MAKE_BASE=TRUE

PP1V8_S0_PCH_VCCHDA_F

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCAPLL_F

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCCLK4_F

=PP1V_SUS_PCH_VCCCLK4

=PP3V3_SUS_PCH_VCCPGPPE

=PP1V8_SUS_PCH_VCC1P8_U12

=PP1V_SUSSW_PCH_VCCAMPHYPLL_SRC

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCCLK2_F

=PP1V_SUS_PCH_VCCCLK5

=PP1V_SUS_PCH_VCCCLK6

=PP1V_SUSSW_PCH_VCCSRAM

=PP3V3_SUS_PCH_VCCPGPPB

MAKE_BASE=TRUE

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

=PP1V_SUSSW_PCH_VCCAMPHYPLL

=PP1V8_SUS_PCH_VCC1P8_U11

=PP1V8_S0_PCH_VCCHDA_F

PP1V_S5_PCH_DCPDSW

=PP1V8_S0_PCH_VCCHDA

=PPVCCPRIMECORE_SUS_PCH

=PP1V_SUS_PCH_VCCAPLL

=PP1V_SUS_PCH_VCCMPHYAON

=PP3V_G3H_PCH_VCCRTC

=PP1V_SUS_PCH_VCCAPLL_F

PPDCPRTC_PCH

=PP1V_SUS_PCH_VCCPRIM

=PP1V_SUS_PCH_FUSE

=PP1V_SUSSW_PCH_VCCMPHYGT

L1250,L1252,L1253,L1254RES,MF,1A MAX,0OHM,5%,06034113S0022

SYNC_DATE=06/15/2015SYNC_MASTER=PAULM

PCH Decoupling

BOM_COST_GROUP=CPU & CHIPSET

0201

X7R

25V

10%

BYPASS=U0500.AK20::10MM

1000PF

2

1

C1208

0201

C0G-CERM

25V

+/-0.05PF

2.9PF

CRITICAL

2

1

C1267

0201

CERM

25V

5%

12PF

2

1

C1264

0201

C0G-CERM

25V

+/-0.05PF

2.9PF

CRITICAL

2

1

C1265

0201

MF

1/20W

5%

0

21

R1261

0201

X7R

25V

10%

BYPASS=U0500.V15::10MM

1000PF

2

1

C1261

0201

C0G-CERM

25V

+/-0.05PF

BYPASS=U0500.V15::10MM

2.9PF

CRITICAL

2

1

C1262

0201

MF

1/20W

5%

0

21

R1260

0201

X7R

25V

10%

BYPASS=U0500.AJ19::10MM

1000PF

2

1

C1226

0201

MF

1/20W

5%

0

NOSTUFF

21

R1251

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.U11::10MM

1UF

NOSTUFF

2

1

C1251

0603

2.2UH-240MA-0.221OHM

OMIT_TABLE

21

L1254

0805

POLY-TANT

6.3V

20%

47UF

CRITICAL NOSTUFF

2

1

C1254

0603

2.2UH-240MA-0.221OHM

OMIT_TABLE

21

L1253

0805

POLY-TANT

6.3V

20%

47UF

CRITICAL NOSTUFF

2

1

C1253

0603

2.2UH-240MA-0.221OHM

OMIT_TABLE

21

L1252

0805

POLY-TANT

6.3V

20%

47UF

CRITICAL NOSTUFF

2

1

C1252

0805

POLY-TANT

6.3V

20%

BYPASS=U0500.K15::3MM

47UF

CRITICAL NOSTUFF

2

1

C1250

0603

2.2UH-240MA-0.221OHM

OMIT_TABLE

21

L1250

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.AL1::3MM

1UF

2

1

C1232

0201

X5R-CERM

10V

10%

BYPASS=U0500.BB10::3MM

0.1UF

2

1

C1231

0201

X5R-CERM

10V

10%

BYPASS=U0500.AK19::3MM

0.1UF

2

1

C1228

0201

X5R-CERM

10V

10%

BYPASS=U0500.AK17::3MM

0.1UF

2

1

C1222

0805

POLY-TANT

6.3V

20%

BYPASS=U0500.N15::10MM

47UF

CRITICAL NOSTUFF

2

1

C1203

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.AA1::10MM

1UF

2

1

C1230

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.AK19::3MM

1UF

2

1

C1227

0201

C0G-CERM

25V

+/-0.05PF

BYPASS=U0500.AJ19::10MM

2.9PF

CRITICAL

2

1

C1260

0201

X7R

25V

10%

BYPASS=U0500.Y16::10MM

1000PF

2

1

C1225

0201

X7R

25V

10%

BYPASS=U0500.V19::10MM

1000PF

2

1

C1224

0201

X7R

25V

10%

BYPASS=U0500.AG15::3MM

1000PF

2

1

C1223

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.AK17::3MM

1UF

2

1

C1221

0201

X7R

25V

10%

BYPASS=U0500.T16::3MM

1000PF

2

1

C1220

0201

X7R

25V

10%

BYPASS=U0500.AF18::10MM

1000PF

2

1

C1210

0201

X7R

25V

10%

BYPASS=U0500.A10::3MM

1000PF

2

1

C1207

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.N18::3MM

1UF

2

1

C1206

0201

X7R

25V

10%

BYPASS=U0500.AF20::10MM

1000PF

2

1

C1205

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1204

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.N15::3MM

1UF

2

1

C1202

0201

X6S-CERM

6.3V

20%

BYPASS=U0500.K17::3MM

1UF

2

1

C1201

0201

X7R

25V

10%

BYPASS=U0500.AB19::10MM

1000PF

2

1

C1200

69

69 8

69 8 5

69 8

69

69 8

8 69

69 8

72

8

69 8

5

69

8

69 8

69 19 8

8

5

8

69

69 8

69 15

69 8

69 15 14 8

8

69 8

64 8

69 8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

合肥怡飞苹果维修qq：82669515 qq群： 241000

(STRAP)

PCH INTERNAL PULL-UPS ARE TO 3.3V.

IO1

IO0

(STRAP)

DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016

(1.8V)

(STRAP)

(BSSB_DATA_IN)

(BSSB_CLK)

(1.8V)

MEMORY CONFIGURATION STRAPS.

ALL GPP_F* PINS ARE 1.8V ONLY!

13 OF 73

13 OF 500

1.0.0

051-02265

=PP3V3_SUS_PCH_VCCPGPPA

=PP3V3_S0_PCH

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

XDP_PCH_OBSDATA_C0

SML_PCH_1_DATA

HDA_BIT_CLK_R

HDA_SDIN0

LPC_AD_R<1>

=USBC_TMS_X_SWD_CLK_X

MLB_RAMCFG1

SPI_IO<2>

MLB_RAMCFG2

BT_PWRRST_L

SPI_CS0_R_L

LPC_SERIRQ

SOC_ALS_UART_D2R

PCH_BSSB_CLK

MLB_RAMCFG3

PCH_UART2_CTS_L

LCD_PSR_EN

TBT_X_CIO_PWR_EN

HDA_SDOUT

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

LPC_SERIRQ

TP_SPI_CS2_L

SPI_IO<3>

SPI_CLK_R

PU_PCH_RCIN_L

=USBC_TMS_T_SWD_DATA_X

TP_SPI_CS1_L

SPI_CS0_R_L

SPI_MISO

PCH_DDPC_CTRLDATA

MLB_RAMCFG0

PCH_BSSB_DATA

MLB_RAMCFG3

MLB_RAMCFG2

MLB_RAMCFG1

LPC_AD_R<0>

LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L

LPC_CLK24M_SMC_R

SSD_PWR_EN_L

LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

LPC_CLK24M_SMC

LPC_AD<0>

PCH_DDPB_CTRLDATA

PCH_STRP_TOPBLK_SWP_L

CAMERA_PWR_EN_PCH

CAMERA_RESET_L

SOC_ALS_UART_D2R

SOC_ALS_UART_R2D

SOC_ALS_UART_R2D PCH_UART2_CTS_L

PCH_SOC_WDOG

SD_RCOMP

PCH_STRP_BSSB_SEL_GPIO

TP_PCH_STRP_TLSCONF

TP_PCH_STRP_ESPI

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

LPC_PWRDWN_L

TP_PCH_CLKOUT_LPC1 LPC_CLKRUN_L

LCD_PSR_EN

MLB_RAMCFG4

MLB_RAMCFG0

SPI_MOSI_R

=USBC_TMS_T_SWD_DATA_X

TBT_X_CIO_PWR_EN

SOC_S2R_ACK_L

PCH_SOC_DFU_STATUS

TBT_X_USB_PWR_EN

SOC_PANIC_L

=USBC_TMS_X_SWD_CLK_X

SML_PCH_1_CLK

DEBUGUART_SEL_SOC

SOC_SLEEP_L

TBT_X_USB_PWR_EN

CAMERA_PWR_EN

BT_TIMESTAMP

=PP3V3_SUS_PCH_VCCSPI

LPC_CLKRUN_L

PU_PCH_RCIN_L

RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_LRAMCFG_SLOT

SYNC_DATE=06/15/2015

PCH Audio/LPC/SPI/SMBus

SYNC_MASTER=PAULM

BOM_COST_GROUP=CPU & CHIPSET

201MF1/20W5%

10K

21

R1344

201MF1/20W5%

1K

21

R1343

70

67

201MF1/20W5%

PLACE_NEAR=U0500.AW9:38MM

22

21

R1327 39

201MF1/20W5%

10K

21

R1342

201MF1/20W5%

100K

21

R1359

201MF1/20W5%

100K

21

R1340

201MF1/20W5%

100K

21

R1341

39 13

201

MF

1/20W

5%

1K

RAMCFG4_L

2

1

R1334

201

MF

1/20W

5%

1K

RAMCFG3_L

2

1

R1333

201

MF

1/20W

5%

1K

RAMCFG2_L

2

1

R1332

201

MF

1/20W

5%

1K

RAMCFG1_L

2

1

R1331

201

MF

1/20W

5%

1K

RAMCFG0_L

2

1

R1330

201MF1/20W5%

100K

21

R1358

201MF1/20W5%

10K

21

R1356

201MF1/20W5%

100K

21

R1357

201MF1/20W5%

10K

21

R1355

201MF1/20W5%

47K

21

R1354

201MF1/20W5%

47K

21

R1353

201MF1/20W5%

47K

21

R1352

201MF1/20W5%

100K

CAMERA_PWR_EN:S0

21

R1351

201MF1/20W5%

10K

21

R1350

42

19 13

19

36 19

28 13

40

17

201

MF

1/20W

1%

PLACE_NEAR=U0500.AB7:12.7MM

200

2

1

R1370

70

47 13

47

47 17

47

39

201MF1/20W5%

33

21

R1325

42

201MF1/20W5%

33

21

R1320

201MF1/20W5%

33

21

R1322

201MF1/20W5%

33

21

R1321

201MF1/20W5%

33

21

R1323

39

39 13

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AV3

AW3

AU4

AW2

AU1

AU2

AU3

AV2

U4

U3

AD4

AD3

AD2

AD1

V3

W3

W1

W2

R9

R10

R8

R7

AM7

BA11

AY9

AW9

AW11AY11

BA12

AY12

BB13

BA13

AY13

AW13

G1

G2

G3

U0500

19

28 13

19

48

201MF1/20W5%

PLACE_NEAR=U0500.AY22:14MM

33

21

R1301

201MF1/20W5%

PLACE_NEAR=U0500.BA22:14MM

33

21

R1300

48

201MF1/20W5%

PLACE_NEAR=U0500.AW22:14MM

33

21

R1303

201MF1/20W5%

PLACE_NEAR=U0500.BB22:14MM

33

21

R1302

48

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AB7

AW20

AY20

BA22

BB22

AY21

BA21

AW22

AY22

AB13

AB11

AF13

AM3

AM2

AM1

AM4

AN2

AN1

N8

N7

L12

L13

D8

U2

U1

P1

P4

AW5

BA9

BB9

U0500

69 16 15 14 8

69 60 19 16 14 5

18

13

6

47 13

39 13

13

28 13

70

13

70

13

19 13

19

70

19 13

6

13

28 13

70

28 13

70

28 13

36 19

6

69 47 8

39 13

13

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

NC

IN

OUT

BI

OUT

BI

OUT

BI

OUT

BI

LPC

SPI-TOUCH

SPI-FLASH

SMBUS,SMLINK

SYM 5 OF 20

C LINK

SML0BALERT*

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_B23/SML1ALERT*/PCHHOT*

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME*/ESPI_CS*

GPP_A3/LAD2/ESPI_IO2

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_C5/SML0ALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_A8/CLKRUN*

GPP_A10/CLKOUT_LPC1

SPI0_CS0*

SPI0_MISO

SPI0_CLK

SPI0_MOSI

SPI0_IO2

SPI0_IO3

SPI0_CS1*

CL_CLK

SPI0_CS2*

GPP_C21/UART2_TXD

GPP_C20/UART2_RXD

GPP_D16/ISH_UART0_CTS*/

GPP_C22/UART2_RTS*

GPP_C23/UART2_CTS*

GPP_D15/ISH_UART0_RTS*

CL_DATA

CL_RST*

GPP_A0/RCIN*

GPP_A6/SERIRQ

IN

BI

OUT

IN

NC

OUT

NC

IN

OUT

AUDIO

SML0BDATA/I2C4B_SDA

SML0BCLK/I2C4B_SCL

SDIO/SDXC

SYM 7 OF 20

SD_RCOMP

GPP_F17/EMMC_DATA4

GPP_A16/SD_1P8_SEL

GPP_A17/SD_PWR_EN*/ISH_GP7

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_F22/EMMC_CLK

GPP_F23

GPP_F19/EMMC_DATA6

GPP_F21/EMMC_RCLK

GPP_F20/EMMC_DATA7

GPP_F18/EMMC_DATA5HDA_SDI1/I2S1_RXD

HDA_SDI0/I2S0_RXD

HDA_SDO/I2S0_TXD

HDA_BLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

I2S1_TXD

I2S1_SFRM

GPP_D17/DMIC_CLK1

GPP_E21/DDPC_CTRLDATA

GPP_E18/DDPB_CTRLCLK

HDA_RST*/I2S1_SCLK

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_D11

GPP_D12

GPP_B14/SPKR

GPP_D13/ISH_UART0_RXD/

GPP_D14/ISH_UART0_TXD/

合肥怡飞苹果维修qq：82669515 qq群： 241000

NOTE: PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED.

THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.

PCH Reset Button

R1400 kept for debug purposes.

VCCST_PWRGD 1V TOLERANT

(1.8V)

LAST CHANGE: Thu Aug 4 21:00:42 2016

DESIGN: X502/MLB_CATZ

ALL GPP_F* PINS ARE 1.8V ONLY!

(1V ONLY)

THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE.

14 OF 73

14 OF 500

1.0.0

051-02265

PCH_SWD_CLK

SSD_SR_EN_L

PCIE_WAKE_L

PCH_PWRBTN_L

SMC_WAKE_SCI_L

PM_SLP_S4_L

PM_SLP_SUS_L

PCIE_WAKE_L

PCH_SOC_FORCE_DFU

TP_PCH_GPP_F8

TP_PCH_PME_L

TP_PCH_SLP_WLAN_L

PCH_SUSWARN_L

PCH_INTRUDER_L

BT_LOW_PWR_L

PCH_SWD_MUX_SEL

PM_SLP_S4_L PM_SLP_S5_L

PM_PCH_SYS_PWROK =PP3V_G3H_PCH_VCCRTC

PM_SLP_SUS_L

=PP1V_S3_CPU_VCCST

TP_PCH_GPP_F9

TP_PCH_GPP_D0

SMC_WAKE_SCI_L

SSD_BOOT_L

EMMC_RCOMP

SSD_SR_EN_L

TP_PCH_SLP_A_L

PM_SLP_S3_L

PM_SLP_S0_L

PCH_PWRBTN_L

PM_BATLOW_L

TP_CPU_PWRGD

PM_SLP_S0_L

TP_PCH_GPD7

PCH_HSIO_PWR_ENTP_PCH_LANPHYPC

UPC_I2C_INT_L

SOC_S2R_L

CSI2_COMP

TP_PCH_GPP_F10

PCH_SWD_CLK

PCH_SWD_IO

PCH_BT_ROM_BOOT

CPU_VCCST_PWRGD

=PP3V3_S0_PCH

PCH_SUSACK_L

=PP3V3_SUS_PCH_VCCPGPPA

PCH_SWD_IO

BT_LOW_PWR_L

=PP1V8_SUS_PCH_VCCPGPPF

PM_SLP_S3_L

=PP3V3_S4_PCH

SOC_S2R_L

=PP3V3_S0_PCH

=PP3V3_S5_PCH_VCCDSW

CPU_VCCST_PWRGD_R

PM_PCH_PWROK

PM_DSW_PWRGD

PM_RSMRST_L

PM_SYSRST_L

PLT_RST_L

PM_SLP_S5_L

PM_BATLOW_L

SSD_BOOT_L

PCH_SWD_MUX_SEL

BOM_COST_GROUP=CPU & CHIPSET

SYNC_DATE=06/15/2015SYNC_MASTER=PAULM

PCH Power Management

41

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AN3

AP3

AP1

AP2

AP4

AD12

AD11

AF12

AF11

AH12

AH11

M1

AT1D27

B27

D28

B29

B33

B31

D33

D31

B38

D36

D38

B36

C27

A27

C28

A29

A33

A31

C33

C31

A38

C36

C38

A36

E13

A26

D29

D32

D37

B26

C29

C32

C37

U0500

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

BB15

B65

B5

B6

AN15

AW15

AY17

A68

BA20

AP16

AN10

AT11

AM10

AM11

AP11

AR13

AU11

AW17

AY16

BB17

AT15

AN16

BA16

AP15

BA15

AM15

AY15

AU13

BB20

U0500

201

MF

1/20W

5%

2.2K

2

1

R1408

201MF1/20W5%

10K

21

R1441

70

60

72 60 39 14

201MF1/20W5%

100K

21

R1446

100K

201MF1/20W5%

21

R1445

100K

5% 1/20W MF 201

21

R1444

NOSTUFF

100K

2015% MF1/20W

21

R1443

201MF1/20W5%

100K

21

R1442

MF 2011/20W5%

100K

21

R1440

19 14

NOSTUFF

201

MF

1/20W

5%

2.2K

2

1

R1407

201 MF 1/20W

1%

PLACE_NEAR=U0500.B65:38mm

60.4

21

R1406

201

MF

1/20W

5%

1K

2

1

R1405

MF 2011/20W5%

100K

21

R1458

MF 2011/20W5%

100K

21

R1456

201MF1/20W5%

220K

21

R1457

MF 2011/20W5%

100K

21

R1454

201MF1/20W5%

100K

21

R1455

201MF1/20W5%

10K

21

R1452

10K

201MF1/20W5%

21

R1451

201MF1/20W5%

1K

21

R1450

5% 201MF1/20W

100K

21

R1453

70

67 14

35 34 14

39 14

201

MF

1/20W

1%

PLACE_NEAR=U0500.AT1:12.7MM

200

2

1

R1481

201

MF

1/20W

1%

PLACE_NEAR=U0500.E13:12.7MM

100

2

1

R1480

201

MF

1/20W

5%

1M

2

1

R1401

39 28 14

67 14

72 60 14

72 60 39 14

72 68 60 39 14

72 66

60 59 39 26 14

18 14

68 39

201

MF

1/20W

5%

100K

2

1

R1403

60

68 35 19

68 39 17

41 14

68 60 39 17

60 19

60 59 39

41

0201

MF

1/20W

5%

0

NO STUFF

1

2

R1400

19 14

67 14

18 14

41 14

39 14

72 68 60 39 14

72 60 14

70

69 15 12 8

69 59 54 19 10 8 6

70

72

72 60 39 14

70

19 14

70

69 60 19 16 14 13 5

69 16 15 13 8

19 14

35 34 14

69 8

72 66 60 59 39 26 14

69

19 14

69 60 19 16 14 13 5

69 8

72

72 60 39 14

39 28 14

67 14

19 14

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

EMMC

CSI-2

SYM 9 OF 20

CSI2_COMP

GPP_D0/SPI1_CS*

GPP_F7/I2C3_SCL

CSI2_DN8

CSI2_DP11

CSI2_DN11

CSI2_DP10

CSI2_DN10

CSI2_DP9

CSI2_DN9

CSI2_DP8

CSI2_DP7

CSI2_DN7

CSI2_DP6

CSI2_DN6

CSI2_DP5

CSI2_DN5

CSI2_DP4

CSI2_DN4

CSI2_DP3

CSI2_DN3

CSI2_DP2

CSI2_DN0

CSI2_DP0

CSI2_DN1

CSI2_DP1

CSI2_DN2

EMMC_RCOMP

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_F12/EMMC_CMD

GPP_F13/EMMC_DATA0

GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2

GPP_F16/EMMC_DATA3

GPP_F6/I2C3_SDA

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

CSI2_CLKN3

CSI2_CLKP3

CSI2_CLKP2

CSI2_CLKN2

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKP1

CSI2_CLKN1

GPP_F8/I2C4_SDA

GPP_F9/I2C4_SCL

SYSTEM POWER MANAGEMENT

SYM 11 OF 20

GPP_B12/SLP_S0*

GPD5/SLP_S4*

GPD4/SLP_S3*

GPD10/SLP_S5*

SLP_SUS*

GPD9/SLP_WLAN*

GPD6/SLP_A*

SLP_LAN*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD0/BATLOW*

GPP_A11/PME*

INTRUDER*

GPP_B11/EXT_PWR_GATE*

GPP_B2/VRALERT*

GPP_B13/PLTRST*

SYS_RESET*

RSMRST*

PROCPWRGD

SYS_PWROK

VCCST_PWRGD

DSW_PWROK

PCH_PWROK

GPP_A15/SUSACK*

GPP_A13/SUSWARN*/SUSPWRDNACK

WAKE*

GPD2/LAN_WAKE*

GPD11/LANPHYPC

GPD7/RSVD

OUT

BI

OUT

IN

OUT

NC

OUT

IN

NC

NC NC

NC

NC NC

NC

NC NC NC NC NC NC NC

NC

IN

OUT

IN

OUT

IN

OUT

合肥怡飞苹果维修qq：82669515 qq群： 241000

EXT B (LS/FS/HS)

ANY CLKREQ CAN MAP TO ANY CLK. ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT. UNUSED CLKREQS AND CLKS SHOULD BE DISABLED.

PCIe Port Assignments:

PER SKYLAKE PDG, SKYLAKE PCH EDS.

EXT A (LS/FS/HS)

EXT B (SS)

SSD LANE 3

SSD LANE 1

LAST CHANGE: Thu Aug 4 21:00:42 2016

DESIGN: X502/MLB_CATZ

EXT A (SS,DCI)

GROUNDED PER SKYLAKE MOW 2015WW10.

Thunderbolt X lane 0

Thunderbolt X lane 1

Thunderbolt X lane 3

Thunderbolt T lane 1

Thunderbolt T lane 0

AirPort

CAMERA

SSD LANE 2

SSD LANE 0

Thunderbolt X lane 2

15 OF 73

15 OF 500

1.0.0

051-02265

USB_EXTA_N USB_EXTA_P

USB3_EXTB_R2D_C_P

TP_USB3_03_R2DP

TP_USB3_04_D2RN TP_USB3_04_D2RP

NC_USB2_07P

NC_USB2_09P

NC_USB2_06P

NC_USB2_06N

PCH_USB2_COMP

TP_USB3_04_R2DP

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<3>

PCIE_TBT_X_R2D_C_P<1>

TP_USB3_04_R2DN

PCIE_SSD_D2R_P<0>

XDP_PCH_OBSFN_C1

USB3_EXTB_D2R_P

NC_USB2_10P

USB3_EXTB_D2R_N

TP_USB_TESTERN

PCH_USB2_VBUSSENSE

NC_USB2_09N

NC_USB2_08N

=PP3V_G3H_PCH_VCCRTC

PCIE_TBT_X_D2R_N<1>

PCIE_TBT_X_R2D_C_P<3>

PCIE_AP_R2D_C_P

PCH_PCIE_RCOMP_P

PCIE_AP_R2D_C_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_C_N

PCH_DIFFCLK_BIASREF

PCH_SRTCRST_L RTC_RESET_L=PP3V3_SUS_PCH_VCCPGPPA

PCH_CLK24M_XTALOUT

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2>

PCIE_SSD_D2R_P<3>

PCIE_TBT_X_D2R_N<2>

PCIE_TBT_X_R2D_C_N<3>

PCIE_SSD_R2D_C_P<3>

NC_USB2_08P

NC_USB2_07N

USB_CAMERA_DFR_N

NC_USB2_05N

TP_USB3_03_D2RN TP_USB3_03_D2RP

SMC_RUNTIME_SCI_L

PCIE_SSD_R2D_C_P<0>

SPKR_ID0

PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_R2D_C_N<1>

PCIE_SSD_R2D_C_P<1>

PCIE_TBT_X_D2R_P<0>

PCIE_TBT_X_D2R_P<2>

XDP_CPU_PRDY_L

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_C1

NC_USB2_10N

PCH_PCIE_RCOMP_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

=PP1V_SUS_PCH_VCCAPLL

PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_P<0>

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_TBT_X_D2R_P<3>

PCIE_TBT_X_D2R_N<3>

PCIE_TBT_X_R2D_C_P<2>

XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_C3

XDP_PCH_OBSDATA_D3

PCIE_TBT_X_D2R_N<0>

USB_EXTB_N

PCIE_TBT_X_R2D_C_N<1>

PCIE_TBT_X_D2R_P<1>

PCIE_SSD_D2R_N<3>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<0>

PCIE_CLK100M_TBT_X_N

=TBT_X_CLKREQ_L

TP_PCH_CLKREQ5_L

TP_PCIE_CLK100M5P

TP_PCIE_CLK100M5N

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_AP_N

PCIE_CLK100M_TBT_T_N

=CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_P

XDP_PCH_OBSDATA_C2

USB_CAMERA_DFR_P

TP_USB_TESTERP

NC_USB2_05P

USB_EXTB_P

USB3_EXTA_D2R_N USB3_EXTA_D2R_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_C_N

TP_USB3_03_R2DN

PCIE_TBT_X_R2D_C_N<2>

=AP_CLKREQ_L

PCIE_CLK100M_AP_P

=TBT_T_CLKREQ_L

PCIE_CLK100M_TBT_T_P

=SSD_CLKREQ_L

PCIE_CLK100M_TBT_X_P

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_C_P

PCH_CLK24M_XTALIN

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

XDP_CPU_PREQ_L

SMC_RUNTIME_SCI_L

PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_P<0>

PCIE_TBT_T_R2D_C_P<1>

TP_ITPXDP_CLK100MN

PM_CLK32K_SUSCLK_R

TP_ITPXDP_CLK100MP

BOM_COST_GROUP=CPU & CHIPSET

PCH PCIE/USB/CLKS

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

19

201MF1/20W5%

100K

21

R1550

70

28

28 19

28

70

26

19

26

19

67

19

35

37

19

37

17

72 67

37

72 35

39 15

70

201

MF

1/20W

1%

PLACE_NEAR=U0500.F5:12.7mm

100

2

1

R1504

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

E35

E37

E42

AN18

AM20

AM18

AM16

AU7

AU8

AT10

AT8

AT7

AR10

BA17

E38

A40

C40

C41

A42

C42

E40

B40

D40

D41

B42

D42

E43

F43

U0500

201

MF

1/20W

1%

20K

2

1

R1531

201

MF

1/20W

1%

20K

2

1

R1530

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1531

0201

X6S-CERM

6.3V

20%

1UF

2

1

C1530

201

MF

1/20W

1%

PLACE_NEAR=U0500.E42:2.54mm

2.7K

2

1

R1520

19

40

201

MF

1/20W

5%

PLACE_NEAR=U0500.AG4:12.7MM

1K

2

1

R1503

28

201

MF

1/20W

1%

PLACE_NEAR=U0500.AB6:12.7MM

113

2

1

R1501

70

28

70

72 17

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

D15

C15

F10

E10

A15

B15

H10

J10

A13

B13

H6

J6

D13

C13

G8

H8

AH8

AG2

AF9

AH2

AF7

AJ2

AD10

AJ3

AD7

AB10

AH7

AG1

AF8

AH1

AF6

AJ1

AD9

AH3

AD6

AB9

AG4

AG3

AB6

D61

D56

E5

F5

B25

A25

F30

E30

C24

D24

E27

E28

C23

D23

E25

F25

A23

B23

E23

E22

C21

D21

F21

G21

A21

B21

E20

F20

C20

D20

F18

G18

D19

C19

E16

F16

A19

B19

F15

G15

C17

D17

G16

H16

C16

D16

F11

G11

A17

B17

G13

H13

J3

J2

J1

A6

G4

H2

J5

V2

D7

H5

C8

BB11

U0500

70

72

70

28

69 14 12 8

69 16 14 13 8

28

70

39 15

70

69 12

70

72

70

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

SYM 10 OF 20

CLOCK SIGNALS

CLKOUT_PCIE_P5

GPP_B10/SRCCLKREQ5*

CLKOUT_PCIE_N5

CLKOUT_PCIE_P4

GPP_B9/SRCCLKREQ4*

GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_N4

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

CLKOUT_PCIE_P2

GPP_B7/SRCCLKREQ2*

GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_N2

CLKOUT_PCIE_N1

CLKOUT_PCIE_P1

CLKOUT_PCIE_N0

GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_P0

CLKOUT_ITPXDP_N

GPD8/SUSCLK

CLKOUT_ITPXDP_P

XTAL24_OUT

XTAL24_IN

RTCX2

XCLK_BIASREF

RTCX1

SRTCRST*

RTCRST*

IN

OUT

BI

OUT

IN

OUT

IN

OUT

SYM 8 OF 20

USB2

PCIE/USB3/SATA

SSIC/USB3

PCIE6_TXP

PCIE6_RXP

PCIE6_TXN

PCIE6_RXN

PCIE1_RXP/USB3_5_RXP

PCIE1_TXN/USB3_5_TXN

PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN

USB2N_2

USB2P_2

PCIE5_RXN

GPP_E2/SATAXPCIE2/SATAGP2

GPP_D20/DMIC_DATA0

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_E0/SATAXPCIE0/SATAGP0

GPP_D23/I2S_MCLK

GPP_E6/DEVSLP2

GPP_D22/SPI1_IO3

GPP_E4/DEVSLP0

GPP_E3/CPU_GP0

GPP_E5/DEVSLP1

USB2_ID

USB2_VBUSSENSE

USB2_COMP

USB2P_10

USB2P_9

USB2N_10

USB2N_9

USB2P_8

USB2P_7

USB2N_8

USB2N_7

USB2P_6

USB2P_5

USB2N_6

USB2N_5

USB2P_4

USB2P_3

USB2N_4

USB2N_3

USB2P_1

USB2N_1

USB3_4_TXP

USB3_4_TXN

USB3_4_RXN

USB3_4_RXP

USB3_1_TXP

USB3_1_TXN

USB3_1_RXP

USB3_1_RXNPCIE1_RXN/USB3_5_RXN

PCIE3_RXP

PCIE3_RXN

PCIE4_RXP

PCIE4_RXN

PCIE3_TXN

PCIE3_TXP

PCIE2_TXP/USB3_6_TXP

PCIE2_TXN/USB3_6_TXN

PCIE2_RXP/USB3_6_RXP

PCIE4_TXN

PCIE5_RXP

PCIE4_TXP

PCIE7_RXN/SATA0_RXN

PCIE7_RXP/SATA0_RXP

PCIE7_TXN/SATA0_TXN

PCIE7_TXP/SATA0_TXP

PCIE8_RXN/SATA1A_RXN

PCIE8_RXP/SATA1A_RXP

PCIE8_TXN/SATA1A_TXN

PCIE8_TXP/SATA1A_TXP

PCIE9_RXN

PCIE9_RXP

PCIE9_TXN

PCIE9_TXP

PCIE10_RXN

PCIE10_RXP

PCIE10_TXN

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

PROC_PRDY*

PROC_PREQ*

GPP_A7/PIRQA*

PCIE12_RXP/SATA2_RXP

PCIE12_RXN/SATA2_RXN

PCIE11_TXP/SATA1B_TXP

PCIE11_RXN/SATA1B_RXN

PCIE11_RXP/SATA1B_RXP

PCIE11_TXN/SATA1B_TXN

PCIE12_TXP/SATA2_TXP

PCIE12_TXN/SATA2_TXN

PCIE5_TXP

PCIE5_TXN

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP

USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB3_3_RXN

USB3_3_RXP

USB3_3_TXN

USB3_3_TXP

合肥怡飞苹果维修qq：82669515 qq群： 241000

<11011>

<10110>

<11010>

<11001>

<11000>

MLB ID STRAPS.

<10101>

LAST CHANGE: Thu Aug 4 21:00:42 2016

<10111>

<11111>

<11110>

<11100>

CODE

ALL GPP_F* PINS ARE 1.8V ONLY!

(STRAP)

(1.8V)

(STRAP)

DESIGN: X502/MLB_CATZ

<11101>

PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.

<10100>

<01111>

DRIVEN PUSH PULL FROM SWITCHED RAIL.

16 OF 73

16 OF 500

1.0.0

051-02265

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

AUD_SPI_MISO

AUD_SPI_CS_L

I2C_UPC_SDA

MLB_DEV_L

AUD_SPI_CLK

MLB_BOARD_ID3

TBT_X_PCI_RESET_L

I2C_UPC_SCL

TP_PCH_GPP_D1

SPKR_ID1

TP_PCH_GPP_D3 TP_PCH_GPP_D4

TBT_T_CIO_PWR_EN

AP_RESET_L

SPIROM_USE_MLB

TBT_T_USB_PWR_EN

AP_DEV_WAKE

AP_S0IX_WAKE_SEL

MLB_BOARD_ID2

MLB_BOARD_ID1

MLB_BOARD_ID4

LCD_IRQ_L

PCH_BT_UART_CTS_L

SPIROM_USE_MLB

SOC_UART_CTS_L

TP_BT_I2S_SYNC

TBT_T_PLUG_EVENT_L

TBT_POC_RESET

SOC_UART_R2D

SOC_UART_D2R

TBT_T_PLUG_EVENT_L

TBT_X_PLUG_EVENT_L

PCH_BT_UART_D2R

AUD_SPI_MOSI

AUD_SPI_CS_L

AUD_SPI_MOSI

TPAD_SPI_MOSI

TPAD_SPI_INT_L

TBT_X_PLUG_EVENT_L

LCD_IRQ_L

SOC_UART_RTS_L

TP_BT_I2S_R2D

TP_BT_I2S_CLK

SSD_RESET_L

MLB_BOARD_ID4

MLB_BOARD_ID0

MLB_BOARD_ID3

MLB_BOARD_ID2

MLB_BOARD_ID1

MLB_BOARD_ID0

TPAD_SPI_IF_EN TPAD_SPI_INT_L

AUD_PWR_EN

TPAD_SPI_IF_EN

PCH_BT_UART_RTS_L

PCH_BT_UART_R2D

TBT_POC_RESET

PCH_BT_UART_CTS_L

TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL

PCH_BT_UART_D2R

TP_BT_I2S_D2R

=PP3V3_SUS_PCH_VCCPGPPA

AUD_SPI_CLK AUD_SPI_MISO

TPAD_SPI_MISO

AP_S0IX_WAKE_L

AP_S0IX_WAKE_SEL

SOC_UART_CTS_L

SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L

=PP3V3_S0_PCH

TPAD_SPI_CS_L TPAD_SPI_CLK

PCH_BT_UART_R2D PCH_BT_UART_RTS_L

AP_S0IX_WAKE_L AP_DEV_WAKE

TBT_T_PCI_RESET_L

BOM_COST_GROUP=CPU & CHIPSET

PCH SPI/UART/GPIO

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

0117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:0

2117S0006 R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:3

3117S0006 R1693,R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:11

1117S0006 R1694RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:16

2117S0006 R1693,R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:10

1117S0006 R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:1

1117S0006 R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:2

2117S0006 R1693,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:9

1117S0006 R1692RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:4

1117S0006 R1693RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:8

3117S0006 R1692,R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:7

2117S0006 R1692,R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:6

2117S0006 R1692,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:5

201MF1/20W5%

100K

21

R1674

201MF1/20W5%

100K

21

R1673

201MF1/20W5%

100K

21

R1669

201

MF

1/20W

5%

1K

OMIT_TABLE

2

1

R1694

201

MF

1/20W

5%

1K

OMIT_TABLE

2

1

R1693

201

MF

1/20W

5%

1K

OMIT_TABLE

2

1

R1692

201

MF

1/20W

5%

1K

OMIT_TABLE

2

1

R1691

201

MF

1/20W

5%

1K

OMIT_TABLE

2

1

R1690

201MF1/20W5%

100K

21

R1672

201MF1/20W5%

47K

21

R1642

201MF1/20W5%

47K

21

R1641

201MF1/20W5%

47K

21

R1640

201MF1/20W5%

47K

21

R1643

70

72 38 16

201MF1/20W5%

100K

21

R1671

201MF1/20W5%

100K

21

R1668

201MF1/20W5%

100K

21

R1667

201MF1/20W5%

100K

21

R1666

201MF1/20W5%

100K

21

R1665

201MF1/20W5%

47K

21

R1664

201MF1/20W5%

47K

21

R1663

201MF1/20W5%

47K

21

R1662

201MF1/20W5%

47K

21

R1661

201MF1/20W5%

150K

21

R1660

201MF1/20W5%

47K

21

R1659

201MF1/20W5%

47K

21

R1658

201MF1/20W5%

47K

21

R1657

201MF1/20W5%

47K

21

R1655

201MF1/20W5%

1K

21

R1656

201MF1/20W5%

47K

21

R1654

201MF1/20W5%

47K

21

R1653

201MF1/20W5%

100K

AUD_PWR_EN:S0

21

R1652

201MF1/20W5%

100K

21

R1650

70

49 19 16

72 38 16

70

72 47 16

72 66 16

28 19

70

35 34 16

35 34 19

28 16

67 19

19 16

28 16

18 16

35 16

72 38 16

38 16

19 16

BGA

TBD

SKL-ULT-2+3E

OMIT_TABLE

AP13

W7

W8

W10

W11

W12

AB12

AH10

AH9

AK10

AK9

AK7

AK6

N12

N11

P3

P2

N2

N1

N3

M4

B7

J4

M3

M2

U9

U8

U6

U7

AB4

AC3

AC2

AC1

AB3

W4

AB2

AB1

AN5

AP5

AN7

AM5

AR7

AP8

AP7

AN8

AW7

AY7

BA7

BB7

BA8

AY8

U0500

16

70

19

70

18 16

16

35 16

72 47 16

70

19 16

28 16

19 16

72 38 16

28 16

72 66 16

70

16

49 19 16

72 38 16

35 16

70

69 15 14 13 8

19 16

72 38 16

19 16

69 60 19 14 13 5

38 16

72 38 16

35 16

18 16

35 34 16

TABLE_5_ITEM

PART# DESCRIPTIONQTY

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

SYM 6 OF 20

LPSS ISH

BM_BUSY*/ISH_GP6

GPP_A18/ISH_GP0

GPP_C19/I2C1_SCL

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_D3/SPI1_MOSI

GPP_D4/FLASHTRIG

GPP_F2/I2S2_TXD

GPP_F0/I2S2_SCLK

GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_C14/UART1_RTS*/ISH_UART1_RTS*

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_F3/I2S2_RXD

GPP_F1/I2S2_SFRM

GPP_C11/UART0_CTS*

GPP_C10/UART0_RTS*

GPP_B21/GSPI1_MISO

GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD

GPP_C18/I2C1_SDA

GPP_C17/I2C0_SCL

GPP_C16/I2C0_SDA

GPP_C9/UART0_TXD

GPP_B19/GSPI1_CS*

GPP_B20/GSPI1_CLK

GPP_B15/GSPI0_CS*

GPP_B16/GSPI0_CLK

GPP_B17/GSPI0_MISO

GPP_B18/GSPI0_MOSI

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_F4/I2C2_SDA

GPP_F5/I2C2_SCL

GPP_G6/SD_CLK

GPP_D9

GPP_G7/SD_WP

GPP_D10

GPP_G2/SD_DATA1

GPP_G3/SD_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD*

GPP_A19/ISH_GP1

GPP_A20/ISH_GP2

GPP_A21/ISH_GP3

GPP_A22/ISH_GP4

GPP_A23/ISH_GP5

SX_EXIT_HOLDOFF*/GPP_A12/

GPP_E22

GPP_E23

合肥怡飞苹果维修qq：82669515 qq群： 241000

OBSDATA_D1

OBSDATA_B0

PULL CFG<3> LOW

They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

(UNDOCUMENTED STRAP FUNCTION)

PULL STRAP LOW WHEN XDP IS PLUGGED IN.

TDO

XDP_PRESENT#

(OD)

OBSDATA_D2

OBSDATA_D3

(STRAP TO PCH)

RESET#/HOOK6

TDI

These signals do not connect to the Primary (Merged) XDP connector in this architecture.

OBSDATA_D0

WHEN XDP PRESENT

OBSFN_D0

OBSDATA_A0

OBSFN_A1

OBSFN_A0

OBSDATA_B3

support chipset debug.

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_A2

SCL

Unused GPIOs have TPs.

Non-XDP Signals

SDA

DBR#/HOOK7

TMS

ITPCLK/HOOK4

DESIGN: X502/MLB_CATZ

PCH/XDP Signals

PCH XDP Signals

OBSFN_C0

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

HOOK2

VCC_OBS_CD

ITPCLK#/HOOK5

TCK0

TCK1

XDP_PIN_1

NOTE: This is not the standard XDP pinout.

518S0847

OBSDATA_B2

OBSDATA_B1

OBSFN_C1

OBSFN_D1

HOOK1

HOOK3

HOOK0

The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.

OBSDATA_C3

OBSDATA_C2

OBSDATA_C1

OBSDATA_C0

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

Use with 921-0133 Adapter Flex to

OBSDATA_A1

Primary / Merged (CPU/PCH) Micro2-XDP

LAST CHANGE: Thu Aug 4 21:00:42 2016

TRSTn

VCC_OBS_AB

17 OF 73

18 OF 500

1.0.0

051-02265

SPI_IO<2>SPI_IO2_STRAP_L

CPU_CFG<12> CPU_CFG<13>

XDP_PM_RSMRST_L

XDP_PRESENT_CPU

XDP_CPU_PRDY_L

XDP_PCH_TCK

CPU_CFG<4>

USB_EXTA_OC_L

CPU_CFG<3>

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_CPU_TDI

XDP_CPU_TRST_L

JTAG_ISP_TDI

XDP_PCH_OBSFN_C1

XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_D0

XDP_PCH_OBSDATA_C1

XDP_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_PCH_OBSDATA_B0

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_PCH_TDI

XDP_PCH_TMS

XDP_CPU_TDO

USB_EXTC_OC_L

JTAG_ISP_TCK

XDP_PCH_OBSDATA_C3

PM_PWRBTN_L

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_A3

PM_SYSRST_L

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

XDP_PCH_OBSDATA_D2

XDP_PCH_OBSDATA_C0

USB_EXTD_OC_L

XDP_PCH_OBSDATA_D3

XDP_PCH_OBSDATA_C2

CPU_CFG<2>

CPU_CFG<8>

=PP1V_S0SW_CPU_VCCSTG

XDP_PCH_TDO

CPU_CFG<11>

XDP_CPU_TMS

XDP_CPU_TDO

CPU_CFG<9>

CPU_CFG<18>

CPU_CFG<19>

CPU_CFG<10>

XDP_PCH_TCK

XDP_CPU_TCK

XDP_DBRESET_L

XDP_PCH_TDO

CPU_CFG<15>

XDP_PCH_TRST_L

ITP_PMODE

CPU_CFG<14>

=PP3V3_SUS_XDP

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<1>

PCH_JTAGX

CPU_CFG<6>

XDP_PRESENT_L

XDP_PCH_TMS

PM_RSMRST_L

XDP_CPU_PREQ_L

CPU_CFG<0>

XDP_CPU_TCK

USB_EXTB_OC_L

XDP_CPU_PWRBTN_L

CPU_CFG<7>

XDP_PCH_TDI

=PP1V_SUS_XDP

CPU_CFG<5>

SYNC_DATE=06/15/2015SYNC_MASTER=PAULM

BOM_COST_GROUP=DEBUG

CPU/PCH Merged XDP

6

72 17 6

6

0.1UF

10% 10V X5R-CERM 0201

XDP_STRAP

2

1

C1830

74AUP1G07GF

SOT891

XDP_STRAP

4

6

5

1

3

2

U1830

47 13

72 6

XDP:YES

0

5%

1/20W

MF

0201

21

R1806

68 39 14

5

15

6

15

13

TP-P6

1

TP1880

TP-P6

1

TP1879

TP-P6

1

TP1878

TP-P6

1

TP1877

TP-P6

1

TP1881

TP-P6

1

TP1876

TP-P6

1

TP1875

TP-P6

1

TP1874

TP-P6

1

TP1873

TP-P6

1

TP1872

TP-P6

1

TP1871

28 19

TP-P6

1

TP1870

19

28

72 60

XDP:YES

100K

5%

1/20W

MF

201

2

1

R1850

XDP:YES

10

PLACE_NEAR=U0500.BA15:2.54MM

5% 1/20W MF 201

21

R1802

1K

PLACE_NEAR=U0500.E8:2.54MM

5% 1/20W MF 201

2

1

R1830

72 6

1.5K

NO_XNET_CONNECTION=1

PLACE_NEAR=U0500.AW2:10MM

5%

1/20W

MF

201

XDP_STRAP

21

R1831

XDP:YES

0

PLACE_NEAR=J1800.57:2.54MM

5% 1/20W MF 0201

21

R1824

XDP:YES

0

PLACE_NEAR=J1800.55:2.54MM

5% 1/20W MF 0201

21

R1823

XDP:YES

0

PLACE_NEAR=J1800.53:2.54MM

5% 1/20W MF 0201

21

R1822

XDP:YES

0

PLACE_NEAR=J1800.51:2.54MM

5% 1/20W MF 0201

21

R1821

68 60 39 14

XDP:YES

1K

NO_XNET_CONNECTION

PLACE_NEAR=U0500.D67:2.54MM

5%

1/20W

MF

201

2

1

R1801

6

XDP_CONN:YES

DF40RC-60DP-0.4V

M-ST-SM1

64 63

62

61

60 59

58 57

56 55

54 53

52 51

50 49

48 47

46 45

44 43

42 41

40 39

38 37

36 35

34 33

32 31

30

29

28 27

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

8 7

6 5

4 3

2 1

J1800

NOSTUFF

51

PLACE_NEAR=U0500.C61:28MM 5% 1/20W MF 201

12

R1897

XDP:YES

0.1UF

PLACE_NEAR=J1800.47:28MM

10% 10V X5R-CERM 0201

2

1

C1806

XDP:YES

0.1UF

PLACE_NEAR=J1800.42:28MM

10% 10V

X5R-CERM

0201

2

1

C1804

5

72 15

XDP:YES

0.1UF

PLACE_NEAR=J1800.44:28MM

10% 10V

X5R-CERM

0201

2

1

C1800

5

15

6

15

5

XDP:YES

0.1UF

PLACE_NEAR=J1800.43:28MM

10% 10V X5R-CERM 0201

2

1

C1801

72 17 6

72 6

6

XDP:YES

0

PLACE_NEAR=J1800.58:28MM

5% 1/20W MF 0201

21

R1835

XDP:YES

51

PLACE_NEAR=U0500.A56:28MM 5% 1/20W MF 201

12

R1890

XDP:YES

51

PLACE_NEAR=U0500.D59:28MM 5% 1/20W MF 201

12

R1891

XDP:YES

51

PLACE_NEAR=U0500.C59:28MM 5% 1/20W MF 201

12

R1892

XDP:YES

51

PLACE_NEAR=U0500.A61:28MM 5% 1/20W MF 201

12

R1810

72 17 6

6

XDP:YES

1K

PLACE_NEAR=U0500.AY17:19MM

5% 1/20W MF 201

21

R1800

XDP:YES

51

PLACE_NEAR=U0500.B61:28MM 5% 1/20W MF 201

12

R1813

72 17 6

6

72 17 6

72 41 39

6

72 6

6

72

72 17 6

69 10 8 6

72 17 6

72

69 60 17

72

69

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

IN

GND

VCC

NCNC

YA

NC NC

NC

NC NC

NC

OUT

IN

BI

OUT

BI

TP

OUT

TP

IN

OUT

IN

OUT

IN

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

合肥怡飞苹果维修qq：82669515 qq群： 241000

System 32kHz / 12MHz / 24MHz Clock Generator

359S00006

NOTE: 30 PPM or better required for SKL PCH

H AP_S0IX_WAKE_L (B1)

PCH ME Disable Strap

SEL OUTPUT

PCH IPD = 9-50k

L PCIE_WAKE_L (B0)

PCIe Wake Muxing

If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting.

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

***** Circuit does not support HDA voltage >3.3V.

18 OF 73

VOLTAGE=2.9V

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500

19 OF 500

1.0.0

051-02265

PP2V9_SYSCLK

=PPVIO_CAMERA_BT_AP_32CLK =PPVIOE_PCHCLK

SYSCLK_CLK24M_X1

SYSCLK_CLK24M_X2

SPI_DESCRIPTOR_OVERRIDE

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S5_WIRELESS

AP_S0IX_WAKE_L

AP_PCIE_WAKE_L PCIE_WAKE_L

AP_S0IX_WAKE_SEL

=PPVIOE_CAMCLK

SYSCLK_CLK24M_X2_R

=PPVIOE_SSDCLK

SYSCLK_CLK24M_PCH

SYSCLK_CLK32K_CAMERA_BT_AP

SYSCLK_CLK32K_PCH

SYSCLK_CLK24M_SSD

SYSCLK_CLK24M_CAMERA

SYSCLK_CLK12M_SMC

=PP1V8R1V5_S0_PCH_VCCHDA

=PP3V3_G3H_SYSCLK

SMC_CLK12M_EN

SYNC_DATE=06/17/2015SYNC_MASTER=X362

BOM_COST_GROUP=CPU & CHIPSET

Chipset Support 1

19

2.5X2.0MM-SM

24MHZ-10PPM-8PF-40OHM

CRITICAL

31

42

Y1900

DFN

PI5A3157B

1

6

5

2

43

U1910

16

14

0201

X5R-CERM

10V

10%

0.1UF

2

1

C1910

201

MF

1/20W

5%

100K

2

1

R1910

35 34

DFN1006H4-3

DMP31D0UFB4

2

1

3

Q1930

69

0201

X5R-CERM

6.3V

20%

BYPASS=U1900.17:18:5MM

2.2UF

2

1

C1900

STQFN

SLG3AP3444

CRITICAL

19

20

11

17

15

5

2

12

1

8

18

14

9

4

13

10

16

6

3

7

U1900

0201-1

X5R

6.3V

20%

BYPASS=U1900.11:18:5MM

1.0UF

2

1

C1901

39

201

MF

1/20W

5%

1M

NOSTUFF

2

1

R1901

0201

MF

1/20W

5%

0

21

R1900

0201

C0G

50V

5%

10PF

2 1

C1907

0201

C0G

50V

5%

10PF

2 1

C1908

39

13

201

MF

1/20W

5%

1K

2

1

R1930

69

19

39 19

19

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

SEL

0

VER 1

A

VCC

1

B1

GND

B0

IN

OUT

OUTIN

D

S

G

IN

VIO_32K_B

VIOE_24M_A

VIOE_24M_B

X2

X1

VDD

VIOE_24M_C

VRTC

12M

VOUT

GND

OE_12M

32.768K_A

24M_A

24M_B

24M_C

32.768K_B

IN

OUT

合肥怡飞苹果维修qq：82669515 qq群： 241000

PROBE POINTS

GREENCLK CLOCK CONNECTIONS.

SERIES R FOR VOLTAGE DIVIDER WHEN PCH IS DRIVING IN L1 SUB-STATE.

LAST CHANGE: Thu Aug 4 21:00:42 2016

DESIGN: X502/MLB_CATZ

NOSTUFF / DELETE TO ALLOW INTERNAL PULL-DOWN FOR BSSB ON USB-SS.

UNUSED GPIO SIGNALS

IFDIM TRIGGERS USING R2055 & R2056 PADS

STUFF PULL-UP TO ENABLE BSSB (DCI) CLK/DI ON GPP_D11, _D12.

(STRAP-OPTION)

NOSTUFF / DELETE TO ALLOW INTERNAL PULL-DOWNS TO DISABLE.

UNUSED PCH XDP SIGNALS NEED TEST POINTS.

S3X SSD CONTROL

S3X SSD DOWN

(STRAP-OPTION)

PCH

PROJECT DEPENDANT

UNUSED GPIO SIGNALS

ASK DC/DC GROUP FOR DETAILS.

(STRAP-OPTION)

RESETS

STUFF PULL-UPS TO ENABLE INTERNAL GPU DP PORTS.

OPTION STRAPS

PCH 24MHz VIOE Options

EXTRA BPM TESTPOINTS

19 OF 73

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800

VOLTAGE=1V

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800

VOLTAGE=1V

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800

VOLTAGE=1V

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800

20 OF 500

1.0.0

051-02265

SOC_ALS_UART_D2R

=TBT_X_CLKREQ_L

SOC_UART_D2R

PCH_SWD_IO PCH_SWD_MUX_SEL

USB_EXTD_OC_L

XDP_BPM_L<2>

=PP3V3_S0_PCH

=SSD_CLKREQ_L

AUD_SPI_CS_L AUD_SPI_CLK

MAKE_BASE=TRUE

TP_SPKR_ID0

MAKE_BASE=TRUE

TP_SPKR_ID1

CAMERA_PWR_EN

AUD_PWR_EN

SOC_UART_RTS_L SOC_UART_CTS_L

MAKE_BASE=TRUE

PD_LCD_PSR_EN

CAMERA_PWR_EN_PCH

SPKR_ID1

SPKR_ID0

AUD_SPI_MISO

LCD_PSR_EN

PM_PCH_PWROK_BUF

=PP3V3_S0_PCH

MAKE_BASE=TRUE

PD_AUD_SPI_CLK

SOC_UART_R2D

AUD_SPI_MOSI

CAMERA_PWR_EN

DP_X_SNK1_ML_C_P<0> DP_X_SNK1_ML_C_N<0>

SOC_S2R_L

MAKE_BASE=TRUE

SOC_WAKE_L

CPU_CATERR_L

=PP1V_S3_CPU_VCCST

MAKE_BASE=TRUE

CPU_RSVD_AK13

PCH_DDPC_CTRLDATA

PCH_STRP_BSSB_SEL_GPIO

PCH_SWD_CLK

CAMERA_CLKREQ_L

MAKE_BASE=TRUE

PU_PCH_SWD_CLK

XDP_BPM_L<1>

XDP_BPM_L<0>

MAKE_BASE=TRUE

PD_SOC_UART_CTS_L

MAKE_BASE=TRUE

PD_PCH_SWD_MUX_SEL

MAKE_BASE=TRUE

PU_SOC_UART_D2R

MAKE_BASE=TRUE

PU_SOC_UART_R2D

MAKE_BASE=TRUE

PU_SOC_UART_RTS_L

MAKE_BASE=TRUE

PU_TBT_T_PLUG_EVENT_LTBT_T_PLUG_EVENT_L

MAKE_BASE=TRUE

TP_XDP_BPM_L<2>

JTAG_ISP_TCK

TP_CPU_RSVD_AK13

=PP3V3_S0_PCH

SYSCLK_CLK12M_SMC

MAKE_BASE=TRUE

PD_AUD_SPI_MISO

MAKE_BASE=TRUE

PU_AUD_SPI_CS_L

USB_EXTC_OC_L

MAKE_BASE=TRUE

PD_SSD_UART_CTS_L

MAKE_BASE=TRUE

PU_SSD_UART_D2R

MAKE_BASE=TRUE

PU_SSD_UART_R2D

PCIE_TBT_X_R2D_C_P<0> PCIE_TBT_X_R2D_C_N<0>

TBTXR2DP0

DPX1P0

MAKE_BASE=TRUE

TBT_X_PCI_RESET_LPM_PLT_RST_TBT_X_L

MAKE_BASE=TRUE

TBT_X_CLKREQ_R_L

SMC_LRESET_L

TBT_X_PCI_RESET_L

SSD_RESET_L

AP_RESET_L

=PP3V3_SUS_PCH_VCCPGPPB

JTAG_ISP_TDI

PCH_CLK24M_XTALIN

MAKE_BASE=TRUE

TP_SYSCLK_CLK24M_SSD

MAKE_BASE=TRUE

SSD_PWR_REQ STORAGE_LATCH

SSD_CLKREQ_L

MAKE_BASE=TRUE

AP_CLKREQ_R_L=AP_CLKREQ_L

=CAMERA_CLKREQ_L

MAKE_BASE=TRUE

CAMERA_CLKREQ_R_L

TBT_X_CLKREQ_L

MAKE_BASE=TRUE

TP_XDP_BPM_L<3>

MAKE_BASE=TRUE

TP_XDP_BPM_L<1>

AP_CLKREQ_L

MAKE_BASE=TRUE

SSD_CLKREQ_R_L

CAMERA_RESET_LCAMERA_CLKREQ_L

SOC_ALS_UART_R2D

XDP_BPM_L<3>

MAKE_BASE=TRUE

PU_PCH_SWD_IO

MAKE_BASE=TRUE

PU_AUD_SPI_MOSI

PCH_DDPB_CTRLDATA

MAKE_BASE=TRUE

SYSCLK_CLK24M_PCH

MAKE_BASE=TRUE

SYSCLK_CLK24M_CAMERA

SYSCLK_CLK24M_SSD

AP_CLKREQ_L

TBT_X_CLKREQ_L

PLT_RST_L

=PP3V3_G3H_SYSCLK PP3V3_G3H

=PPVIO_CAMERA_BT_AP_32CLK

CLK25M_CAM_CLKP

PCH_CLK24M_XTALOUT

MAKE_BASE=TRUE

TP_PCH_CLK24M_XTALOUT

=PP3V3_S4_WLAN

MAKE_BASE=TRUE

PPVIO_BT_AP_32CLK

=PPVIOE_CAMCLK

=PPVIOE_PCHCLK

=PPVIOE_SSDCLK

MAKE_BASE=TRUE

PD_PPVIOE_SSDCLK

=PPVDDIO_S0_CAMCLK

MAKE_BASE=TRUE

PPVIOE_CAMCLK

PM_SLP_S0S3_L

PP1V_S5G

MAKE_BASE=TRUE

TP_PCH_CLK32K_RTCX2 PCH_CLK32K_RTCX2

MAKE_BASE=TRUE

SYSCLK_CLK32K_PCH PCH_CLK32K_RTCX1

=PPVIOE_PCHCLK

=PPVIOE_CAMCLK

SYSCLK_CLK32K_BT_AP

MAKE_BASE=TRUE

SYSCLK_CLK32K_BT_AP_R

SYSCLK_CLK32K_CAMERA_BT_AP

=PPVIO_CAMERA_BT_AP_32CLK

PM_PCH_PWROK

PCH_UART2_CTS_L

MAKE_BASE=TRUE

PP1V_SUSRS0SW_PCHCLK

PP1V_S5G_PCHCLK

PP1V_S0SW_PCHCLK

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=PAULM SYNC_DATE=06/15/2015

Chipset Support 2

201

MF

1/20W

5%

100K

2

1

R2041

201

MF

1/20W

5%

100K

2

1

R2040

60 14

SOT891

74LVC1G08

CRITICAL

4

6

5 3

1

2

U2040

0201

X5R-CERM

10V

10%

0.1UF

2

1

C2040

0201

MF

1/20W

5%

0

BT_CLK32K:YES

21

R2032

34

201

MF

1/20W

5%

100K

BT_CLK32K:NO

2

1

R2031

0201

MF

1/20W

5%

0

BT_CLK32K:YES

21

R2030

201

MF

1/20W

5%

470K

2

1

R2014

14

16

28 26

28 15

0201

X5R-CERM

16V

10%

PLACE_NEAR=C3040.1:1MM

NO_XNET_CONNECTION=1

0.1UF

NOSTUFF

2

1

C2093

0201

X5R-CERM

16V

10%

PLACE_NEAR=C3040.1:1MM

NO_XNET_CONNECTION=1

0.1UF

NOSTUFF

2

1

C2092

0201

X5R

6.3V

20%

PLACE_NEAR=C3040.1:1MM

NO_XNET_CONNECTION=1

0.22UF

NOSTUFF

2

1

C2091

0201

X5R

6.3V

20%

PLACE_NEAR=C3040.1:1MM

NO_XNET_CONNECTION=1

0.22UF

NOSTUFF

2

1

C2090

201

MF

1/20W

5%

PLACE_NEAR=C2090.2:5MM

51

DPX1N0

NOSTUFF

2

1

R2093

201

MF

1/20W

5%

PLACE_NEAR=C2090.2:6MM

51

NOSTUFF

2

1

R2092

201

MF

1/20W

5%

PLACE_NEAR=C3040.1:1MM

51

TBTXR2DN0

NOSTUFF

2

1

R2091

201

MF

1/20W

5%

PLACE_NEAR=C2090.2:1MM

51

NOSTUFF

2

1

R2090

6

15

201 MF

1/20W 5%

1K

21

R2004

26 19

201MF1/20W5%

47K

21

R2072

201MF1/20W5%

100K

21

R2013

201MF1/20W5%

33

21

R2015

39

SM

21

XW2002

SM

2 1

XW2065

0201

X5R-CERM

10V

10%

BYPASS=U1900.05:18:5MM

0.1UF

2

1

C2004

0201

X5R-CERM

10V

10%

BYPASS=U1900.02:18:5MM

0.1UF

2

1

C2005

0201

X5R-CERM

10V

10%

BYPASS=U1900.12:18:5MM

0.1UF

2

1

C2006

13

DFN1006H4-3

DMN32D2LFB4

CRITICAL

PCH24M:S0SW

2

1

3

Q2065

72 68 60

0201

MF

1/20W

5%

0

PCH24M:S0SW

21

R2066

0201

MF

1/20W

5%

0

PCH24M:SUS

21

R2065

16

SM

21

XW2000

15

201 MF

1/20W 5%

1K

21

R2003

36 19

15

201 MF

1/20W 5%

1K

21

R2002

35 34 19

201 MF

1/20W 5%

1K

21

R2001

15 67 19

36 13

35 34 16

67 16

28 19 16

201MF1/20W5%

47K

21

R2075

201MF1/20W5%

47K

21

R2074

201MF1/20W5%

47K

21

R2071

17

TP-P6

1

TP2073

68 39 6

201

MF

1/20W

5%

51

2

1

R2061

6

402

MF-LF

1/16W

5%

100K

NOSTUFF

21

R2056

402

MF-LF

1/16W

5%

100K

NOSTUFF

21

R2055

14

15

16

13

TP-P6

1

TP2072

TP-P6

1

TP2071

17

28 17

TP-P6

1

TP2070

13

0201

MF

1/20W

5%

0

21

R2060

36 19 13

13

16

60 67

39 18 39 18

18 36

18

15

68 35 14

201MF1/20W5%

1K

BSSB_ON_GPIOS

21

R2022

201MF1/20W5%

2.2K

IG_DDI2_EN

21

R2021

201MF1/20W5%

2.2K

IG_DDI1_EN

21

R2020

201MF1/20W5%

100K

21

R2012

201MF1/20W5%

100K

21

R2010

201MF1/20W5%

100K

21

R2011

69 60 19 16 14 13 5

70

36 19 13

49 16

69 60 19 16 14 13 5

69 59 54 14 10 8 6

13

70

69 60 19 16 14 13 5

28 19 16

26

69 12 8

70

67 19

70

35 34 19

36 19

13

26 19

18

72

69 68 60 53 52 51 47 42 41 28

19 18

70

69 34

19 18

18

36

72 69 64 63 62

70

19 18

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

NC

08

NC

OUT

IN

OUT

IN

OUT IN

OUT

IN

G S

SYM_VER_3

D

IN

OUT

IN

OUT IN

OUT

IN

TP

OUT

IN

BI

IN

OUT

IN

TP

IN

TP

IN OUT

OUT

IN

OUT

OUT IN

IN OUT

IN

OUT

IN

OUT

IN

合肥怡飞苹果维修qq：82669515 qq群： 241000

CPU-Based Margining

VREFCA. Connected to 4 DRAMs.

VRef Dividers

NOTE: CPU has single output for VREFCA.

051-02265

1.0.0

20 OF 73

22 OF 500

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1800

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

PPVREF_S3_MEM_VREFDQ_A

PPVREF_S3_MEM_VREFDQ_B

PPVREF_S3_MEM_VREFCACPU_DIMM_VREFCA

=PPDDR_S3_MEMVREF

MEM_VREFDQ_B_RC

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

MEM_VREFCA_RC

MEM_VREFDQ_A_RC

SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP

BOM_COST_GROUP=CPU & CHIPSET

LPDDR3 VREF Margining

201

MF

1/20W

1%

8.2K

2

1

R2221

201

MF

1/20W

1%

8.2K

2

1

R2241

201

MF

1/20W

1%

PLACE_NEAR=R2221.2:1mm

8.2K

2

1

R2222

201

MF

1/20W

1%

24.9

21

R2220

201

MF

1/20W

1%

8.2K

2

1

R2261

201

MF

1/20W

1%

PLACE_NEAR=R2241.2:1mm

8.2K

2

1

R2242

201

MF

1/20W

1%

24.9

21

R2240

201

MF

1/20W

1%

PLACE_NEAR=R2261.2:1mm

8.2K

2

1

R2262

201

MF

1/20W

1%

24.9

21

R2260

201

MF

1/20W

1%

10

21

R2223

0201

X5R-CERM

6.3V

10%

0.022UF

2

1

C2220

201

MF

1/20W

1%

10

21

R2243

0201

X5R-CERM

6.3V

10%

0.022UF

2

1

C2240

0201

MF

1/20W

1%

5.1

21

R2263

0201

X5R-CERM

6.3V

10%

0.022UF

2

1

C2260

7

69

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

合肥怡飞苹果维修qq：82669515 qq群： 241000

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

23 OF 500

051-02265

1.0.0

21 OF 73

=PP1V2_S3_MEM_VDDQ

=MEM_A_DQ<26>

=MEM_A_DQ<30> =MEM_A_DQ<31>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_CKE<0>

=MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQ<21>

=MEM_A_DQS_P<0>

MEM_A_CAA<2>

MEM_A_ODT<0>

=MEM_A_DQS_N<0> =MEM_A_DQS_N<1>

=MEM_A_DQ<25>

MEM_A_CLK_N<0>

MEM_A_CAA<6>

MEM_A_CAA<0> MEM_A_CAA<1>

MEM_A_CAA<5>

=MEM_A_DQ<0>

=MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<12>

=MEM_A_DQ<15> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23> =MEM_A_DQ<24>

=MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQ<3>

=MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

PP0V6_S3_MEM_VREFDQ_A

MEM_A_CAA<7>

=MEM_A_DQ<22>

=MEM_A_DQ<1>

MEM_A_ZQ<0> MEM_A_ZQ<1>

=MEM_A_DQ<14>

MEM_A_CAA<4>

MEM_A_CAA<3>

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<6>

=PP1V8_S3_MEM

MEM_A_CAA<9>

MEM_A_CAA<8>

=PP1V2_S3_MEM_VDDQ

=MEM_A_DQ<13>

PP0V6_S3_MEM_VREFCA_A

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDCA

=MEM_A_DQS_P<1> =MEM_A_DQS_P<2> =MEM_A_DQS_P<3>

MEM_A_CLK_P<0>

MEM_A_CKE<1>

SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP

LPDDR3 DRAM Channel A (00-31)

BOM_COST_GROUP=DRAM

71

243

1%

1/20W

MF

201

2

1

R2301

243

1%

1/20W

MF

201

2

1

R2300

71

72 25 22 7

72 25 7

71

72 25 7

71

3PF

+/-0.1PF 25V C0G 0201

2

1

C2380

12PF

5% 25V CERM 0201

2

1

C2381

3PF

+/-0.1PF 25V C0G 0201

2

1

C2382

71

12PF

5% 25V CERM 0201

2

1

C2383

1.0UF

20%

6.3V X5R 0201-1

2

1

C2313

OMIT_TABLE

CRITICAL

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

B4

B3

J11

H4

J8

U13

U12

U2

U1

T13

T1

B13

B1

A13

A12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

B8

B9

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

F10

F11

M11

M10

M9

M8

N11

N10

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300

OMIT_TABLE

CRITICAL

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

T12

T6

R6

P12

N6

M12

M6

L9

K10

H10

G9

G6

F12

F6

E6

D12

C6

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

H2

T5

T4

T3

T2

R5

R4

N5

N4

M5

L6

K2

J12

F5

E5

E4

C5

B5

B2

U11

R12

N12

N8

L12

K11

K8

J10

J9

H11

H9

H8

G12

E12

E8

C12

A11

M2

L2

H3

G2

F2

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

J5

H12

H6

H5

G5

D6

D5

D4

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

0.047UF

10%

6.3V X5R 201

2

1

C2340

0.047UF

10%

6.3V X5R 201

2

1

C2341

71

1.0UF

20%

6.3V X5R 0201-1

2

1

C2330

1.0UF

20%

6.3V X5R 0201-1

2

1

C2331

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2332

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2333

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2323

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2324

71

1.0UF

20%

6.3V X5R 0201-1

2

1

C2322

1.0UF

20%

6.3V X5R 0201-1

2

1

C2321

1.0UF

20%

6.3V X5R 0201-1

2

1

C2320

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2312

1.0UF

20%

6.3V X5R 0201-1

2

1

C2311

1.0UF

20%

6.3V X5R 0201-1

2

1

C2310

71

1.0UF

20%

6.3V X5R 0201-1

2

1

C2305

0.1UF

10% 16V X5R-CERM 0201

2

1

C2301

1.0UF

20%

6.3V X5R 0201-1

2

1

C2304

1.0UF

20%

6.3V X5R 0201-1

2

1

C2303

0.1UF

10% 16V X5R-CERM 0201

2

1

C2300

71

1.0UF

20%

6.3V X5R 0201-1

2

1

C2302

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2307

CRITICAL

10UF

20%

6.3V CERM 0402

2

1

C2306

71

69 24 23 22 21

69 22

69 24 23 22 21

69 22

69 24 23 22 21

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

IN

BI

IN

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

BI

SYM 1 OF 2

DQ13

CS0*

DM2

DM1

DM0

CS1*

DM3

CA8

CKE0

CK_T

DQS2_C

DQS3_C

DQ21

CA9

DQS0_T

DQS2_T

CA2

ODT

DQS0_C

DQS1_C

DQ25

CK_C

CA6

CA0

CA1

CA3

CA4

CA5

CKE1

DQ0

DQ10

DQ11

DQ12

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ2

DQ20

DQ23

DQ24

DQ26

DQ27

DQ28

DQ29

DQ3

DQ30

DQ31

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQS1_T

DQS3_T

VREFCA

VREFDQ

CA7

NU

DQ22

DQ1

NC

ZQ0

ZQ1

SYM 2 OF 2

VSSCA

VDD1

VDD2

VDDCA

VDDQ

VSS

VSSQ

BI

合肥怡飞苹果维修qq：82669515 qq群： 241000

LPDDR3 CHANNEL A (32-63)

Distribute evenly.

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

24 OF 500

22 OF 73

051-02265

1.0.0

MEM_A_CAB<6>

MEM_A_CKE<3>

=PP1V2_S3_MEM_VDDQ

=MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQ<36>

=MEM_A_DQ<56>

=MEM_A_DQ<32>

MEM_A_CS_L<0>

MEM_A_CLK_N<1>

MEM_A_CS_L<1>

MEM_A_ZQ<2>

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_A_DQ<39>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<46>

=MEM_A_DQS_P<7>

=MEM_A_DQ<45>

=MEM_A_DQ<50>

=MEM_A_DQ<38>

=MEM_A_DQ<41>

=MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQ<61>

=MEM_A_DQ<59> =MEM_A_DQ<60>

=MEM_A_DQ<57> =MEM_A_DQ<58>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DQ<51>

=MEM_A_DQ<47> =MEM_A_DQ<48>

=MEM_A_DQ<44>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<40>

MEM_A_CAB<7>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_CAB<5>

MEM_A_CAB<4>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_ODT<0>

MEM_A_CAB<2>

MEM_A_CAB<9>

MEM_A_CLK_P<1>

MEM_A_CKE<2>

MEM_A_CAB<8>

MEM_A_ZQ<3>

=PP1V2_S3_MEM_VDDQ

=MEM_A_DQS_P<6>

=PP1V2_S3_MEM_VDDCA

=MEM_A_DQ<49>

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

=MEM_A_DQ<37>

SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP

BOM_COST_GROUP=DRAM

LPDDR3 DRAM Channel A (32-63)

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2402

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2422

0201

X5R-CERM

16V

10%

0.1UF

2

1

C2401

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2421

0201

X5R-CERM

16V

10%

0.1UF

2

1

C2400

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2420

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2432

71

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2411

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2410

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2431

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2430

71

72 25 21 7

72 25 7

71

72 25 7

71

0201

C0G

25V

+/-0.1PF

3PF

2

1

C2480

0201

CERM

25V

5%

12PF

2

1

C2481

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2413

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2412

0201

C0G

25V

+/-0.1PF

3PF

2

1

C2482

0201

CERM

25V

5%

12PF

2

1

C2483

71

FBGA

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

T12

T6

R6

P12

N6

M12

M6

L9

K10

H10

G9

G6

F12

F6

E6

D12

C6

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

H2

T5

T4

T3

T2

R5

R4

N5

N4

M5

L6

K2

J12

F5

E5

E4

C5

B5

B2

U11

R12

N12

N8

L12

K11

K8

J10

J9

H11

H9

H8

G12

E12

E8

C12

A11

M2

L2

H3

G2

F2

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

J5

H12

H6

H5

G5

D6

D5

D4

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

B4

B3

J11

H4

J8

U13

U12

U2

U1

T13

T1

B13

B1

A13

A12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

B8

B9

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

F10

F11

M11

M10

M9

M8

N11

N10

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2424

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2407

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2433

201

X5R

6.3V

10%

0.047UF

2

1

C2441

71

201

X5R

6.3V

10%

0.047UF

2

1

C2440

201

MF

1/20W

1%

243

2

1

R2401

201

MF

1/20W

1%

243

2

1

R2400

72 25 21 7

71

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2406

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2405

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2404

0201-1

X5R

6.3V

20%

1.0UF

2

1

C2403

0402

CERM

6.3V

20%

10UF

CRITICAL

2

1

C2423

71

69 24 23 22 21

69 21

69 24 23 22 21

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

IN

BI

IN

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

BI

SYM 2 OF 2

VSSCA

VDD1

VDD2

VDDCA

VDDQ

VSS

VSSQ

SYM 1 OF 2

DQ13

CS0*

DM2

DM1

DM0

CS1*

DM3

CA8

CKE0

CK_T

DQS2_C

DQS3_C

DQ21

CA9

DQS0_T

DQS2_T

CA2

ODT

DQS0_C

DQS1_C

DQ25

CK_C

CA6

CA0

CA1

CA3

CA4

CA5

CKE1

DQ0

DQ10

DQ11

DQ12

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ2

DQ20

DQ23

DQ24

DQ26

DQ27

DQ28

DQ29

DQ3

DQ30

DQ31

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQS1_T

DQS3_T

VREFCA

VREFDQ

CA7

NU

DQ22

DQ1

NC

ZQ0

ZQ1

BI

IN

BI

Apple X502 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual