Apple X425G Schematics

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

Page

TABLE_TABLEOFCONTENTS_ITEM

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

<ECO_DESCRIPTION>

SCHEM,MLB,VENUS,X425G

EVT 01/12/2015

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

(.csa)

61

SPI Debug Connector

62

AUDIO:CODEC, ANALOG

63

AUDIO:CODEC, DIGITAL

64

AUDIO: SPEAKER AMP

65

AUDIO: JACK

66

AUDIO: JACK TRANSLATORS

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.5 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

1.35V DDR3L SUPPLY

75

5V / 3.3V Power Supply

76

1V05V POWER SUPPLY

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

79

X249 POWER SUPPLY

80

Power FETs

81

Power Control 1/ENABLE

82

Power Sequencing EG/PGOOD

83

eDP Display Connector

84

Venus PCI-E

85

Venus CORE/FB POWER

86

Venus FRAME BUFFER I/F

87

0V95 GPU / 1V35 FB Power Supply

88

GDDR5 Frame Buffer A

89

GDDR5 Frame Buffer B

90

Venus HDMI/DP/GPIO

91

Venus GPIOs & STRAPs

92

Venus DP PWR/GNDs

93

GFX IMVP VCore Regulator

94

VREG GPU VDDCI

95

RIO Connectors

96

eDP Mux

97

eDP Muxed Graphics Support

100

Power Aliases

102

Signal Aliases

104

Functional Test Points

105

NC & No Test

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

GPU (AMD VENUS) Constraints

Contents

CLEAN_X425

JOE_J45

CLEAN_X305

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X305_PEG

CLEAN_X425

CLEAN_X305

CLEAN_MAXWELL

J45_IG

MARY_X425G

J45G_AMD

ADITYA_X425G

MARY_X425G

ADITYA_X425G

CLEAN_MAXWELL

MARY_X425G

CLEAN_X305

J15_MLB

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

J45G_AMD

(.csa)

1

1 2 3 4 5 6 7 8 9

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU DMI/PEG/FDI/RSVD

6

CPU Clock/Misc/JTAG/CFG

7

CPU DDR3 Interfaces

8

CPU Power

9

CPU Ground

10

CPU Decoupling

11

PCH RTC/HDA/JTAG/SATA/CLK

12

PCH DMI/FDI/PM/GFX/PCI

13

PCH PCI-E/USB

14

PCH GPIO/MISC/NCTF

15

PCH Power

16

PCH Grounds

17

PCH DECOUPLING

18

CPU & PCH XDP

19

Chipset Support

20

Project Chipset Support

21

CPU Memory S3 Support

22

DDR3 VREF MARGINING

23

DDR3 SDRAM Bank A (1 OF 2)

24

DDR3 SDRAM Bank A (2 OF 2)

25

DDR3 SDRAM Bank B (1 OF 2)

26

DDR3 SDRAM Bank B (2 OF 2)

27

DDR3 Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

35

X87 CONNECTOR

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

46

USB 3.0 CONNECTORS

48

KEYBOARD/TRACKPAD (1 OF 2)

49

KEYBOARD/TRACKPAD (2 OF 2)

50

SMC

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Voltage and Current Sensing

55

Load Side Voltage and Current Sensing

56

Debug Sensors

57

GPU V/I Sensors

58

Thermal Sensors

60

Fan Connectors

Contents

MASTER

CLEAN_X305

J15_MLB

CLEAN_X305G

CLEAN_X305_PEG

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

CLEAN_X305G

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

CLEAN_X425

J15_MLB

CLEAN_X425

J15_REFERENCE

CLEAN_MAXWELL

CLEAN_X425

J15_MLB

CLEAN_X425

T29_RR

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X425G

CLEAN_MAXWELL

CLEAN_X305

CLEAN_X305G

CLEAN_X305_PEG

CLEAN_X425G

CLEAN_X305

J45G_AMD

CHANG_J45

J15_MLB

Sync

Date

MASTER

05/30/2014

10/31/2012

08/08/2014

02/18/2014

12/18/2012

10/31/2014

12/18/2012

08/11/2014

12/18/2012

10/31/2014

12/18/2012

10/30/2014

10/31/2012

10/31/2014

01/14/2013

07/02/2014

08/11/2014

10/31/2012

10/30/2014

01/14/2013

10/30/2014

06/24/2014

10/30/2014

08/15/2014

10/30/2014

09/10/2014

07/02/2014

01/15/2014

06/24/2014

08/11/2014

02/18/2014

09/10/2014

01/14/2014

07/01/2014

11/26/2012

10/31/2012

Page

TABLE_TABLEOFCONTENTS_ITEM

Sync

Date

08/15/2014

07/30/2013

06/24/2014

11/04/2014

01/15/2014

01/09/2015

01/15/2014

11/04/2014

02/18/2014

10/30/2014

01/15/2014

07/02/2014

07/01/2014

09/11/2014

12/11/2014

08/22/2014

09/22/2014

06/30/2014

09/16/2014

09/22/2014

11/07/2014

09/22/2014

09/15/2014

09/16/2014

07/01/2014

09/22/2014

10/15/2014

05/30/2014

10/31/2012

12/10/2012

02/18/2014

12/10/2012

02/18/2014

12/10/2012

07/01/2014

Schematic / PCB #’s

TITLE=MLB ABBREV=ABBREV

LAST_MODIFIED=Mon Jan 12 16:34:40 2015

ALIASES RESOLVED

051-00383

820-00163

1 SCH

1 PCB

SCHEM,MLB,VENUS,X425G

PCBF,MLB,VENUS,X425G

CRITICAL

<PART_DESCRIPTION>

<SCH_NUM>

<BRANCH> 1 OF 119

1 OF 97

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

X425 BOM Groups

COMMON/DEVEL BOM

DRAM SPD Straps

BOM Variants

Module Parts

SYNC_DATE=05/30/2014

SYNC_MASTER=CLEAN_X305

BOM Configuration

X425_COMMON

685-00042

COMMON PARTS,MLB,VENUS,X425G

X425_DEVEL:ENG

985-00050

DEV BOM,MLB,VENUS,X425G

639-00682

PCBA,MLB,VENUS,CTO,16GHYN,VR-4GHYN,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_HYNIX

639-00798

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,BEST,16GHYN,VR-4GHYN,X425G

639-00799

PCBA,MLB,VENUS,BEST,16GMIC,VR-4GMIC,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_MICRON

PCBA,MLB,VENUS,NOCPU,16GMIC,VR-4GHYN,X425G

639-00803

BASE_BOM,DEVEL_BOM,GFX_BOM,RAM:MICRON_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,CTO,16GMIC,VR-4GMIC,X425G

639-00703

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_MICRON

639-00739

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_MICRON

PCBA,MLB,VENUS,CTO,16GHYN,VR-4GMIC,X425G

639-00740

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,CTO,16GMIC,VR-4GHYN,X425G

PCBA,MLB,VENUS,BEST,16GMIC,VR-4GHYN,X425G

639-00801

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_HYNIX

CRW,SR1ZX,PRQ,C0,2.5,47W,4+3E,1.2,6M,BGA

U0500

CPU_CRW:BEST

CRITICAL

1

337S00058

CRITICAL

1

CPU_CRW:CTO

U0500

CRW,SR1ZY,PRQ,C0,2.8,47W,4+3E,1.2,6M,BGA

337S00059

CRITICAL

U1100

337S4542

1

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

CRITICAL

U2800

1

338S1247

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

1

CRITICAL

U3900

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

338S1264

CRITICAL

1

U4000

333S0700

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

32

MICRON_1600

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

333S0660 CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

U8400

1

IC,GPU,VENUS XTAA1,QS,29X29MM,FCBGA962

337S00116

VENUS:XTA

CRITICAL

RAM:HYNIX_1600

HYNIX_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM:MICRON_1600

MICRON_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

IC,SDRAM,DDR3L-1600,4GBIT,78B FBGA

32

HYNIX_1600

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S00032

FB_4G_HYNIX

4

U8800,U8850,U8900,U8950

IC,GDDR5,4GBIT,6GBPS,1.5V,25NM,BGA170

333S00027

CRITICAL

XDP_DEBUG

XDP_CONN,XDP_PCH

GFX_BOM

VENUS:XTA

X425_DEVEL:ENG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,DPMUX_DEBUG,GPU_ROM:YES,SENSOR_GPU_NONPROD:Y

SMC_PROG:BASE,BOOTROM_PROG:EVT,TBTROM:PROG,DPMUXMCU:PROG

X425_PROGPARTS

BKLT:PROD,SENSOR_NONPROD:N

X425_PVT

EDP:YES,XDP,SSD_PWR_EN:GPIO,CAM_WAKE:NO,SAMCONN,APCLKRQ:ISOL,CRW_SPRT,WLAN_SW:SIL

X425_COMMON2

X425_COMMON1

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CPUPEG:X8X4X4,S2_PWR:S0,SMC_SUSACK:YES

ALTERNATE,COMMON,X425_COMMON1,X425_COMMON2,X425_PROGPARTS,ACAPS:A2

X425_COMMON

PCBA,MLB,NOGPU,CTO,16GMIC,VR-4GHYN,X425G

639-00974

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

X425_DEVEL:PVT

XDP_DEBUG

639-00800

PCBA,MLB,VENUS,BEST,16GHYN,VR-4GMIC,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_MICRON

BASE

1

CRITICAL

BASE_BOM

COMMON PARTS,MLB,VENUS,X425G

685-00042

DEVEL

CRITICAL

DEVEL_BOM

1

DEV,MLB,VENUS,X425G

985-00050

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED

X425_DEVEL:DVT

333S0766

FB_4G_MICRON

4

U8800,U8850,U8900,U8950

IC,GDDR5,4GBIT,6GBPS,128MX32,25NM,170BGA

CRITICAL

<SCH_NUM>

2 OF 119

2 OF 97

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC

EFI ROM

Alternate Parts

Programmables - All builds

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

BOM Configuration

U5000

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

338S1214

SMC_PROG:BLANK

CRITICAL

1

U9600

1

DPMUXMCU:BLANK

CRITICAL

IC,MCU,H8S/2113,9X9MM,TLP-145V

337S4313

U9600

CRITICAL

DPMUXMCU:PROG

1

IC,EDP MUX-95C,(RENESAS) V3.2.8,DVB,D2

341S3565

U9101

335S0724

1MBIT SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

GPUROM:BLANK

1

CRITICAL

U2890

T29,FALCON RIDGE(V27.1)PROTO0,X425G

CRITICAL

TBTROM:PROG

1

341S00166

U2890

TBTROM:BLANK

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

335S0915 CRITICAL

1

BOOTROM_BLANK:WIN

335S00007

1

U6100

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

CRITICAL

BOOTROM_BLANK:MAC

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

CRITICAL

335S00006

1

U6100

BOOTROM_PROG:EVT

IC,EFI ROM (V0145) EVT,X425

341S00239

1

U6100

CRITICAL

IC,SMC-B1,EXT (V2.25A9) PROTO 0,X425G

U5000

SMC_PROG:BASE

1

CRITICAL

341S00157

Diodes alt to Vishay

376S00086

376S0761

ALL

128S0264

ALL

Kemet alt to Sanyo

128S0364

138S0843

ALL

Samsung alt to Murata

138S0674

740S0135

ALL

AEM alt to Tyco

740S00003

128S0311

ALL

NEC alt to Sanyo

128S0329

155S00008

155S0667

Panasonic alt to TDK

ALL

376S0604376S1053

Diodes alt to Fairchild

ALL

128S0376

Kemet alt to Sanyo

ALL

128S0371

Cyntec alt to Vishay

152S0461

ALL

152S1645

138S0846 138S0811

Samsung alt to Murata

ALL

371S0713 371S0558

DDS alt to ST

Rohm alt to Vishay

138S0715

ALL

138S0732

ALL

ELPIDA to HYNIX U4000

333S0700333S0704

197S0478 197S0479

NDK Alt to Epson

ALL

197S0480

ALL

197S0481

Epson Alt to NDK

138S0739

Samsung alt to Murata

138S0706

ALL

138S0639

Samsung alt to Murata

ALL

138S0803

127S0164 127S0162

Rohm alt to Vishay

ALL

Toshiba alt to Vishay

376S00014

376S0761

376S1089 376S1128

NXP alt to Diodes

ALL

NXP alt to Diodes

376S0855376S1129

376S00074

376S0855

Toshiba alt to Diodes

ALL

376S1080 376S0820

Diodes alt to On Semi

ALL

353S2162

ON Semi alt to TI

353S00394 ALL

353S00133 ALL

ON Semi alt to TI

353S2741

Diodes alt to NXP

311S00060 ALL

311S0273

NEC alt to Sanyo

128S00008 ALL

128S0380

ON alt to Toshiba

311S0649

ALL

311S0541

740S00004

740S0134

AEM alt to Littlefuse

ALL

107S00029 107S00030 ALL

TFT alt to Cyntec

128S0220

Kemet alt to Sanyo

128S0398

ALL

128S0284128S0386

Kemet alt to Sanyo

ALL

311S0271

311S00008 ALL

Diodes alt to NXP

Kemet alt to Sanyo

128S0334128S0393

ALL

107S00033

TFT alt to Cyntec

ALL107S00034

107S0255

ALL

TFT alt to Cyntec

107S0240

ALL

TFT alt to Cyntec

107S00032107S00031

TFT alt to Cyntec

ALL107S00011107S00015

ALL

TFT alt to Cyntec

107S00038107S00037

ALL

TFT alt to Cyntec

107S0251107S0249

ALL

TFT alt to Cyntec

107S0250107S0248

371S00017

Diodes alt to Onsemi

ALL

371S0749

311S0426

Diodes alt to NXP

ALL311S00007

Kemet alt to Sanyo

128S0325128S0397

ALL

311S00004

ON Semi alt to NXP

311S0370

ALL

Pericom alt to TI

353S00095

353S3328

ALL

Yageo alt to Cyntec

112S00001

112S0254

ALL

<SCH_NUM>

3 OF 119

3 OF 97

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FAN BOSS APN 860-3428

Thermal Module gaskets APN 875-9290

Frame Holes

APN 860-1448

APN 806-9391

806-00452

APN 870-2451

X305G STANDOFF

APN 806-2247

X305G POGO PINS

IPD FLEX BRACKET BOSS (860-00166)

RIO FLEX BRACKET BOSS (860-00166)

APN 817-0688

APN 817-0741

SMT GND TEST PONTS

X305G THERMAL MODULE STANDOFF

PD parts

--------------------------------------------------------

CPU BOSS APN 860-2931

APN 860-3690

--------------------------------------------------------

GPU BOSS APN 860-4772

GPU BOSS APN 817-4517

1

ZT0415

2.8R2.3

1

SH0431

POGO-2.3OD-5.5H-X304

SM

1

ZT0470

TH-NSP

SL-1.1X0.45-1.4x0.75

1

SH0450

SHLD-MLB-USB-J45

SM

1

SH0432

SM

POGO-2.3OD-5.5H-X304

1

SH0433

POGO-2.3OD-5.5H-X304

SM

1

SH0435

SM

POGO-2.3OD-5.5H-X304

1

SH0434

SM

POGO-2.3OD-5.5H-X304

1

ZT0471

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0472

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0473

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0450

SL-2.3X3.9-2.9X4.5

TH-NSP

2

1

SH0442

2.9OD1.2ID-1.35H-SM

2

1

SH0441

2.9OD1.2ID-1.35H-SM

2

1

SH0443

2.9OD1.2ID-1.35H-SM

2

1

SH0444

2.9OD1.2ID-1.35H-SM

1

ZT0490

SMT-PAD-NSP

2.1SM2.0MM-CIR

1

ZT0491

SMT-PAD-NSP

2.1SM2.0MM-CIR

1

ZT0492

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

BR0401

TH

MLB-MTG-BRKT-J5

1

SH0437

SM

POGO-2.3OD-5.5H-X304

2

1

SH0460

2.9OD1.2ID-1.35H-SM

2

1

SH0461

2.9OD1.2ID-1.35H-SM

2

1

SH0462

2.9OD1.2ID-1.35H-SM

2

1

SH0467

2.9OD1.2ID-1.35H-SM

2

1

SH0466

2.9OD1.2ID-1.35H-SM

2

1

SH0465

2.9OD1.2ID-1.35H-SM

1

SH0428

4.5OD1.85ID-1.95H

1

SH0427

4.5OD1.85ID-1.95H

1

SH0430

4.5OD1.85ID-1.95H

2

1

SH0440

2.9OD1.2ID-1.35H-SM

1

SH0420

5.0OD1.85ID-2.35H

1

SH0422

5.0OD1.85ID-2.35H

1

SH0426

5.0OD1.85ID-2.35H

1

SH0429

5.0OD1.85ID-2.35H

1

CG0400

6.0OD3.9H-SM

OMIT

1

CG0401

OMIT

6.0OD3.9H-SM

1

CG0402

OMIT

6.0OD3.9H-SM

1

CG0403

OMIT

6.0OD3.9H-SM

1

SH0421

4.5OD1.85ID-1.95H-1

1

SH0480

3.5OD1.85ID-2.0H

1

SH0481

3.5OD1.85ID-2.0H

1

SH0451

SM

SHLD-FENCE-MLB-T29-X305

2

1

SH0464

2.9OD1.2ID-1.35H-SM

2

1

SH0463

2.9OD1.2ID-1.35H-SM

1

SH0483

3.5OD1.85ID-2.0H

1

SH0482

3.5OD1.85ID-2.0H

1

SH0445

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

1

SH0446

STDOFF-4.9OD2.38H-SM-2

1

SH0424

STDOFF-4.5OD1.9H-SM-1

1

SH0425

STDOFF-4.5OD1.8H-SM-1

1

SH0423

STDOFF-4.5OD1.8H-SM-1

SYNC_DATE=08/08/2014

SYNC_MASTER=CLEAN_X305G

PD Parts

1

CRITICAL946-3819

EDGE_BOND

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

GND

<SCH_NUM>

4 OF 119

4 OF 97

IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

DDIB_TXP3

DDIB_TXN2

DDIB_TXP1

DDIB_TXN1

DDIB_TXP0

DDIC_TXP3

DDIC_TXN3

DDIC_TXN2

DDIC_TXP1

DDID_TXN2 DDID_TXP2 DDID_TXN3 DDID_TXP3

DDID_TXN0 DDID_TXP0 DDID_TXN1 DDID_TXP1

EDP_AUXN

EDP_HPD

EDP_AUXP

EDP_TXN1

EDP_TXP0 EDP_TXP1

DDIB_TXP2 DDIB_TXN3

DDIC_TXN0 DDIC_TXP0 DDIC_TXN1

DDIB_TXN0

EDP_RCOMP

EDP_DISP_UTIL

FDI_TXN0 FDI_TXP0 FDI_TXN1 FDI_TXP1

DDIC_TXP2

EDP_TXN0

SYM 10 OF 12

FDI

DIGITAL DISPLAY INTERFACES

EDP

DAISY_CHAIN_NCTF

RSVD139

RSVD138

RSVD137

RSVD136

RSVD135

RSVD134

RSVD133

RSVD132

DAISY_CHAIN_NCTF

SYM 12 OF 12

RESERVED

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

DMI_RX1

DMI_TX3

DMI_TX2

DMI_TX1

DMI_TX0

DMI_TX3*

DMI_TX2*

DMI_TX1*

DMI_TX0*

DMI_RX3

DMI_RX2

DMI_RX0

DMI_RX3*

DMI_RX2*

DMI_RX1*

DMI_RX0*

PEG_RX15

PEG_RX14

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

FDI_CSYNC

DISP_INT

PEG_RCOMP

PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*

PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

PEG_RX0*

PEG_RX1*

PEG_RX2*

PEG_RX3*

PEG_RX4*

PEG_RX5*

PEG_RX6*

PEG_RX7*

PEG_RX8*

PEG_RX9* PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15*

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

DMI

PCI EXPRESS BASED INTERFACE SIGNALS

FDI

SYM 1 OF 12

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Each corner of CPU has two testpoints. Other corner test signals connected in

Port D pins out of order

CPU Daisy-Chain Strategy:

NO_TESTNO_TEST

to match Intel symbol.

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

85

28 85 89

85

28 85 89

34 85 89

85

28 85 89

34 85 89

85

28 85 89

34 85 89

B14

D12 A14

C12

B12

D14

A12

C14

AG6

E14

E12

F14

F15

B16

D16

B17

D17

A16

C16

A17

C17

B20

D20

B21

D21

A20

C20

A21

C21

B24

D24

B25

D25

A24

C24

A25

C25

U0500

HASWELL

OMIT_TABLE

BGA

2

1

R0530

1% 1/16W MF-LF 402

24.9

2

1

R0531

10k

5% 1/16W MF-LF 402

G17

G14

AN37

AN35

AG45

AF9 AE9

AD45

D54

D1

C54

C3

C2

C1

BF53

BF52

BF51

BF4

BF3

BF2

BE54

BE53

BE52

BE3

BE2

BE1

BD54

BD1

BC54

BC1

B54

B53

B52

B3

B2

A53

A52

A51

A4

A3

U0500

HASWELL

OMIT_TABLE

BGA

1

TP0500

TP-P6

1

TP0501

TP-P6

1

TP0511

TP-P6

1

TP0531

TP-P6

1

TP0510

TP-P6

1

TP0520

TP-P6

1

TP0530

TP-P6

1

TP0521

TP-P6

12 89

12 87 89

12 89

12 87 89

12 89

12 87 89

2

1

R0510

402

1/16W MF-LF

1%

24.9

12 89

J1

J4

G2

J6

E2

G5

E4

D6

T2

T3

R3

R1

R5

T5

B5

C6

J2

J3

G3

J5

E3

G4

D4

E6

T1

T4

R4

R2

R6

T6

C5

B6

L3

M3

L1

M5

A9

C9

F9

A10

Y1

Y4

V2

V3

Y5

M1

D10

F10

L4

M4

L2

L5

B9

D9

E9

B10

Y2

Y3

V1

V4

V5

M2

C10

E10

AH6

F11

AG1

AG3

AF3

AF1

AG2

AG4

AF4

AF2

AC2

AC4

AB4

AB1

AC1

AC3

AB3

AB2

F12

U0500

OMIT_TABLE

HASWELL

BGA

85

28 85 89

34 85 89

28 85 89

34 85 89

85

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=CLEAN_X305_PEG

SYNC_DATE=02/18/2014

=PEG_D2R_P<1>

=PEG_D2R_N<0>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_P<0>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_P<1> PCIE_TBT_D2R_P<2>

=PEG_D2R_P<6> =PEG_D2R_P<7> PCIE_TBT_D2R_P<0>

=PEG_D2R_P<5>

=PEG_D2R_P<4>

=PEG_D2R_P<3>

=PEG_D2R_P<2>

=PEG_D2R_P<0>

PCIE_SSD_D2R_N<3>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_N<2>

PCIE_TBT_D2R_N<3> PCIE_SSD_D2R_N<0>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_N<1>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<5>

=PEG_D2R_N<3> =PEG_D2R_N<4>

=PEG_D2R_N<1> =PEG_D2R_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_P<1> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<0>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<0>

=PEG_R2D_C_P<6> =PEG_R2D_C_P<7>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_N<0>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_N<3>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<0>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<6>

CPU_PEG_RCOMP

DMI_S2N_N<2>

DP_INT_IG_ML_P<3>

DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<2>

DP_INT_IG_ML_N<2>

CPU_DC_BE53_BF53

TRUE

CPU_DC_A3_B3 CPU_DC_A4

TP_DP_IG_B_MLP<0>

PPVCOMP_S0_CPU

DP_INT_IG_ML_P<1>

CPU_DC_BC54

CPU_DC_A3_B3

TRUE

CPU_DC_BF51

TRUE

CPU_DC_B54_C54

DMI_S2N_N<0>

CPU_EDP_RCOMP

TP_DP_IG_D_MLP<3>

PPVCCIO_S0_CPU

DP_INT_IG_AUX_N

PPVCOMP_S0_CPU

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_P<3>

DMI_S2N_P<2>

FDI_INT

FDI_CSYNC

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DP_INT_IG_ML_N<0>

TP_DP_IG_C_MLP<2>

TP_EDP_DISP_UTIL

TP_DP_IG_B_MLN<0>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLN<0>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<2>

DP_INT_IG_ML_P<0>

DP_INT_IG_ML_N<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<2>

TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<3>

DP_INT_IG_AUX_P

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

DP_IG_A_HPD_L

TRUE

CPU_DC_A53_B53

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_D1

CPU_DC_BF4

CPU_DC_BC1

CPU_DC_BE53_BF53

TRUE

CPU_DC_A51

CPU_DC_D54

5 OF 97

5 OF 119

<SCH_NUM>

89

82 85 97

5

5 8

82 85 97

5 5

89

6 8

10 18 58

82 85 97

5 8

82 85 97

20

5

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SSC_DPLL_REF_CLKP

BCLKP

BCLKN

DPLL_REF_CLKP

DPLL_REF_CLKN

CATERR*

PROCHOT*

PROC_DETECT*

PECI

BPM7*

BPM6*

BPM5*

BPM4*

BPM2* BPM3*

BPM1*

BPM0*

DBR*

TDO

TDI

TRST*

TMS

TCK

PREQ*

PRDY*

SM_DRAMRST*

SM_RCOMP2

SM_RCOMP1

SM_RCOMP0

PLTRSTIN*

PWRGOOD

THERMTRIP*

PM_SYNC

SM_DRAMPWROK

SSC_DPLL_REF_CLKN

THERMAL

DDR3

PWR

JTAG

CLOCK

SYM 2 OF 12

OUT

IN IN

RSVD_TP24

RSVD_TP25 RSVD_TP26

RSVD49

RSVD48

RSVD47

RSVD_TP4

RSVD_TP23

RSVD_TP35 RSVD_TP36

RSVD_TP37

RSVD_TP18

RSVD_TP17

CFG15

CFG13 CFG14

CFG12

CFG7 CFG8 CFG9 CFG10 CFG11

TESTLO_F20

CFG4

CFG3

CFG2

CFG5 CFG6

CFG1

CFG0

TESTLO_F21

VSS_F51 VSS_F52

VSS_G19

VCC_F22

VSS_H53

VSS_H51 VSS_H52

VSS_H54

CFG17

CFG18

CFG19

CFG16

CFG_RCOMP

RSVD92 RSVD93 RSVD94 RSVD95

RSVD9

RSVD10

RSVD41 RSVD42

RSVD16

RSVD50

RSVD52

RSVD51

RSVD_TP1

RSVD11

RSVD_TP38 RSVD_TP39

RSVD_TP27 RSVD_TP28

RSVD_TP2 RSVD_TP3

RESERVED

SYM 11 OF 12

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

J1800 and only for debug access

(IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU)

(IPU) (IPU) (IPU) (IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

These can be placed close to

(IPU) (IPU)

18 89

2

1

R0611

10K

5% 1/16W MF-LF

402

PLACE_NEAR=U0500.F50:157mm

12 21 89

14 18 89

14 41 89

2

1

R0614

402

MF-LF

1/16W

1%

100

PLACE_NEAR=U0500.BB52:12.7mm

2

1

R0613

PLACE_NEAR=U0500.BB53:12.7mm

402

MF-LF

1/16W

1%

75

2

1

R0612

PLACE_NEAR=U0500.BB51:12.7mm

402

MF-LF

1/16W

1%

100

40 89

2

1

R0601

MF-LF

62

402

1/16W

5%

2 1

R0603

1/16W

56

5%

MF-LF

402

40 41 58 89

M53

M51

D53

M49

N49

N54

Y6

V6

BB52

BB53

BB51

BE51

AP48

F50

E50

C51

N52

N53

D52

L54

G51

AE6

AC6

F53

G50

P51

U51

P53

R49

N50

P49

R50

R51

AA6

AB6

U0500

OMIT_TABLE

HASWELL

BGA

21

11 89

H54 H53

H52

H51

G19

F52

F51

F22

F21

F20

L53

L52

L51

G6

G24

G21

G12 G10

F6

F25

F24

F1 E1

BE4 BD3

A6

A5

N51L50

L49

H50

G53

F8

F16

E5

BD4 BC4

B50

AU27

AU26

AM48

AL6

AH49

R54

Y54

Y49

W51

V51

AB49

Y50

AE49

AC49

V52

V53 Y51

Y52

R52

R53

V54

U53

W53

Y53

AD49

AG49

U0500

BGA

OMIT_TABLE

HASWELL

2

1

R0690

49.9

1% 1/16W

402

MF-LF

2

1

R0680

402

MF-LF

1/16W

1%

49.9

2

1

R0685

402

MF-LF

1/16W

1%

49.9

2

1

R0649

NOSTUFF

1/16W

1K

5%

MF-LF

402

2

1

R0643

1K

NOSTUFF

5% 1/16W

402

MF-LF

2

1

R0641

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0640

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0647

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0646

CPUCFG6_PD

402

MF-LF

1/16W

5%

1K

2

1

R0645

CPUCFG5_PD

402

MF-LF

1/16W

5%

1K

2

1

R0644

1K

EDP:YES

5% 1/16W MF-LF

402

2

1

R0642

NOSTUFF

1K

5% 1/16W MF-LF 402

2

1

R0621

PLACE_NEAR=U0500.AP48:51.562mm

1% 1/16W MF-LF

402

3.32K

2

1

R0648

NOSTUFF

1K

5% 1/16W MF-LF

402

18 86 89

2

1

R0620

1/16W MF-LF

402

1%

PLACE_NEAR=R0621.2:1mm

1.82K

12 89

14

18 19 89

18 89

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

CPUPEG:X8X8

CPUCFG5_PD

CPU Clock/Misc/JTAG/CFG

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

XDP_BPM_L<7>

CPU_SM_RCOMP<2> CPU_MEM_RESET_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

CPU_PROCHOT_R_L

CPU_CATERR_L

TP_CPU_RSVD_TP2

CPU_PECI

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

PM_SYNC

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

PPVCC_S0_CPU

TP_CPU_RSVD_TP37

TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP48

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP36

CPU_CFG<15>

CPU_CFG<13> CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<4>

TP_CPU_RSVD_TP35

TP_CPU_RSVD_TP24

XDP_CPUPCH_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

CPU_CFG<3>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG_RCOMP

TP_CPU_RSVD_TP3

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP47

CPU_TESTLO_F21

TP_CPU_RSVD_TP18

CPU_CFG<0>

CPU_TESTLO_F20

CPU_CFG<19>

TP_CPU_RSVD_TP27 TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP25

TP_CPU_RSVD_TP38 TP_CPU_RSVD_TP39

CPU_CFG<18>

TP_CPU_RSVD_TP17

PM_THRMTRIP_L

CPU_CLK135M_DPLLREF_N

CPU_PWRGD

CPU_RESET_L

CPU_CFG<6>

CPU_CFG<7>

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<16>

CPU_CFG<3>

CPU_CFG<9>

CPU_PROCHOT_L

PPVCCIO_S0_CPU

CPU_CFG<2>

PM_MEM_PWRGD

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

6 OF 119

6 OF 97

89

8

10 45 59 84 86

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 86 89

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 86 89

6

18 89

5 8

10 18 58

6

18 89

8

10 21 66 67 84 96

OUT

NC

NC NC

NC

NC NC NC

NC

NCNC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

RSVD160

RSVD161

SA_DQ60

SA_DQ59

RSVD163 RSVD164

RSVD166 RSVD167

RSVD169 RSVD170

SA_MA15

SA_MA14

SA_MA10

SA_CKN2

RSVD168

RSVD165

RSVD162

RSVD25

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

SA_DQ45 SA_DQ46 SA_DQ47

SA_DQ6

SA_DQ5

SA_DQ7

SA_DQ10

SA_DQ3 SA_DQ4

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ35

SA_DQ34

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ14

SA_DQ13

SA_DQ9

SA_DQ2

SA_DQ1

SA_DQ0

SA_DQ30

SA_CKE0

SA_CKE2

SA_CKE3

SA_CS0*

SA_CS2* SA_CS3*

SA_ODT0 SA_ODT1 SA_ODT2

SA_BS0

SA_ODT3

SA_BS2

SA_BS1

SA_RAS*

VSS_BC21

SA_WE*

SA_CAS*

SA_MA1

SA_MA0

SA_MA3

SA_MA2

SA_MA4

SA_MA6

SA_MA5

SA_MA7 SA_MA8 SA_MA9

SA_MA11 SA_MA12 SA_MA13

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SM_VREF

SA_DQ20

SA_CS1*

SA_CKE1

SA_CKN0 SA_CKP0

SA_CKN1 SA_CKP1

SA_CKP2

SA_CKN3 SA_CKP3

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ8

SA_DQ11 SA_DQ12

MEMORY CHANNEL A

SYM 3 OF 12

VSS_AU30

SB_BS2

SB_CKP3

SB_CKN3

SB_CKP2

SB_CKN2

SB_CKP1

SB_CKN1

SB_CKP0

SB_DQS7

SB_DQS6

SB_DQS2

SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59

SB_DQSN7

SB_DQ58

SB_DQ57

SB_DQSN5

SB_DQ56

SB_DQSN4

SB_DQ55

SB_DQ54

SB_DQSN2

SB_DQ53

SB_DQSN1

SB_DQ52

SB_DQSN0

SB_DQ51

SB_DQ50

SB_MA15

SB_DQ49

SB_MA14

SB_DQ48

SB_MA13

SB_DQ47

SB_MA12

SB_DQ46

SB_MA11

SB_DQ45

SB_MA10

SB_DQ44

SB_MA9

SB_DQ43

SB_MA8

SB_DQ42

SB_MA7

SB_DQ41

SB_MA6

SB_DQ40

SB_MA5

SB_DQ39

SB_MA4

SB_DQ38

SB_MA3

SB_DQ37

SB_MA2

SB_DQ36

SB_MA1

SB_MA0

SB_CAS*

SB_WE*

SB_RAS*

SB_DQ30

SB_DQ27

SB_BS1

SB_DQ26

SB_BS0

SB_DQ25

SB_DQ24

SB_ODT3

SB_DQ23

SB_ODT2

SB_DQ22

SB_ODT1

SB_DQ21

SB_ODT0

SB_DQ20

SB_CS3*SB_DQ19

SB_CS2*SB_DQ18

SB_CS1*SB_DQ17

SB_CS0*SB_DQ16

SB_DQ15

SB_CKE3SB_DQ14

SB_DQ13

SB_DQ12

SB_DQ11

SB_CKE2

SB_DQ10

SB_DQ9

SB_DQ8

SB_CKE1

SB_DQ7

SB_DQ6

SB_DQ5

SB_DQ4

SB_DQ3

SB_DQ2

SB_DQ1

SB_DQ0

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQS4

SB_DQS3

SB_DQS5

SB_DQS1

SB_DQS0

SB_DQSN6

SB_DQSN3

RSVD172

RSVD173

RSVD174 RSVD175 RSVD176 RSVD177 RSVD178 RSVD179 RSVD180 RSVD181

SB_CKE0

SB_CKN0

RSVD171

SB_DQ28 SB_DQ29

MEMORY CHANNEL B

SYM 4 OF 12

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22 89

22

23 24 92

25 26 92

23 27 92

24 27 92

23 24 27 92

BC21

AM6

AN6

BF21

BF20

BD17

BF17

BF16

BC16

BC32

BE27

BC28

BF27

BC27

BF32

BE28

BF28

BE31

BE32

BE20

BC31

BF31

BD20

BD27

BD28

AT2

BA3

BE7

BD12

AY46

AW52

AP53

AJ52

AT3

BA2

BD7

BE12

BA46

AW53

AP52

AJ53

AN52

AN54

AK53

AR3

AR2

AU4

AU2

AK52

AR4

AR1

AU1

AU3

AW1

AW4

BB2

BB3

AW2

AW3

AH51

BC2

BB4

BD6

BE5

BF9

BD9

BC6

BE6

BE9

BC9

AH53

BE11

BD11

BD14

BE14

BF11

BC11

BC14

BF14

BA43

BA49

AK54

AY43

AY45

BA45

BA47

AY49

AY47

AY53

AY54

AV54

AV51

AK51

AY51

AY52

AV53

AV52

AR54

AR52

AN51

AN53

AR53

AR51

AH52

AH54

AR6

BD16

BE17

BC17

BE16

BC23

BF23

BC25

BF25

BD23

BE23

BD25

BE25

BD34

BC34

BF34

BE34

BE21

BD32

BD21

BC20

BD31

BC53

BA40

BA39

AY40

AY39

AW40

AW39

AV40

AV39

AU40

AU39

U0500

OMIT_TABLE

HASWELL

BGA

AU30

AW23

AV23

AW19

AV19

BA19

AY20

AU32

BA32

AV32

AT30

AY32

AW32

AV30

AY30

BA35

AW36

AU20

AW35

AY35

AU23

AW30

BA30

AL2

AW8

AW10

AW16

BD43

BD48

AU46

AD52

AL3

AW6

AW12

AW15

BE43

BE48

AV46

AD53

AU49

AU47

AE53

AK3

AK2

AM4

AM1

AE52

AK4

AK1

AM3

AM2

AY6

AU6

AY8

AV8

BA6

AV6

AC51

BA8

AU8

AV10

AY10

BA12

AV12

AU10

BA10

AY12

AU12

AC53

AU15

AY15

AV16

AY16

AV15

BA15

AU16

BA16

BE42

BD42

AE54

BC44

BF44

BF42

BC42

BD44

BE44

BF47

BE47

BD50

BD49

AE51

BC47

BD47

BE49

BC49

AV49

AV47

AU45

AU43

AV45

AV43

AC52

AC54

AW20

AU19

AY19

BA20

AY27

AY26

AV26

AV27

BA27

BA26

AW26

AW27

AV36

AV35

AU35

AU36

AV20

BA36

BA23

AY23

BF39

BF37

BE39

BE38

BE37 BD39

BD38

BD37

BC39 BC37

AY36

U0500

OMIT_TABLE

HASWELL

BGA

23 24 92

24 27 92

23 27 92

24 27 92

23 27 92

23 24 27 92

25 27 92

26 27 92

25 27 92

25 26 27 92

26 27 92

25 27 92

26 27 92

25 26 27 92

25 26 92

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU DDR3 Interfaces

MEM_A_DQ<2> MEM_A_DQ<3>

MEM_A_CS_L<1>

MEM_A_DQ<45>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQ<53>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13>

MEM_A_DQ<15> MEM_A_DQ<16>

MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50>

MEM_A_DQ<52>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<15>

MEM_B_DQ<20>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<61>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_A_DQ<60>

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>

MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<17>

MEM_A_DQ<14>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_B_DQ<52>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

CPU_DIMM_VREFCA

MEM_B_DQ<16>

MEM_B_DQ<18>

<SCH_NUM>

7 OF 119

7 OF 977 OF 97

7 OF 119

<SCH_NUM>

BI

OUT

IN

PWR_DEBUG*

RSVD64

RSVD76

VCCIO_OUT

VCC

VDDQ

FC_D3

FC_D5

VSS_B51

VCC_SENSE

VCOMP_OUT

VCC_M6

VCC_L6

RSVD70

RSVD72 RSVD73

RSVD74

RSVD66 RSVD67

RSVD69

RSVD65

FC_F17

VSS_AB50(RSVD)

VSS_AD50(RSVD)

VSS_AJ50(RSVD)

VSS_AK49(RSVD)

VSS_AM50(RSVD)

VSS_AN49(RSVD)

VSS_AP49(RSVD)

VSS_AP50(RSVD)

VSS_V50(RSVD)

RSVD79(VSS)

VIDALERT* VIDSCLK VIDSOUT

RSVD68

RSVD71

VSS_E52

IVR_ERROR IST_TRIGGER

RSVD75

VSS_AG50(RSVD)

VSS_AJ49(RSVD)

SYM 5 OF 12

VCCVCC

POWER

SYM 6 OF 12

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

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C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

to avoid any extraneous connections.

Max load: 300mA

R0810.2: R0800.2:

R0802.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs

for BDW CPU support.

Connections are required

21

R0812

0

5% 1/16W MF-LF

402

58 89

2

1

R0802

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1% MF-LF

21

R0811

0

402

5%

MF-LF

1/16W

58 89

21

R0810

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

58 89

2

1

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

V50

E52

B51

AP50

AP49

AN49

AM50

AK49 AJ50

AJ49 AG50

AD50

AB50

J50

J52

J53

BE33

BE30

BE26

BE22

BE18

BD33

BD30

BD26

BD22

BB36

BB34

BB31

BB30

BB27

BB26

BB22

BB21

AY18

AW33

AW29

AW25

AW22

AV37

AT36

AT32

AT27

AT23

AT19

AT13

AR33

AR31

AR29

AK6

D51

C50

M6

L6

H29

H27

H26

H25

H24

H23

H21

H20

H19

H18

H17

H16

H14

H13

H12

H11

G48

G46

G45

G43

G42

G39

G38

G36

G34

G32

G31

G29

G27

F48

F46

F45

F43

F42

F39

F38

F36

F34

F32

F31

F28

F27

E48

E46

E45

E43

E42

E39

E38

E36

E34

E32

E31

E28

E27

D48

D46

D45

D43

D42

D39

D38

D36

D34

D32

D31

D28

D27

C48

C46

C45

C43

C42

C39

C38

C36

C34

C32

C31

C28

C27

B48

B46

B45

B43

AA9

AA8

AA47

AA46

A48

A46

A45

A43

A42

A39

A38

A36

W9

V49 U49

J31

J26

J21

J17

J12

AR49

AN33

AN31

AN22 AN18

AH9

F19

AM49

W49

F17

D5 D3

U0500

OMIT_TABLE

HASWELL

BGA

Y8

Y46

Y45

W8

W47

W46

V8

V46

V45

U9U8U47

U46

T46

T45

R9R8R47

R46

P8

P46

P45

N9N8N47

N46

N44

N43

N42

N40

N39

N38

N37

M9M8M46

M45

M44

M43

M42

M40

M39

M38

M37

L8

L47

L46

L44

L43

L42

L40

L39

L38

L37

K9K8K48

K46

K45

K44

K43

K40

K38

J9J8J48

J46

J45

J43

J42

J40

J39

J38

J37

J36

J33

J29

J24

J19

J14

J10

H9H8H48

H46

H45

H43

H42

H40

H39

H38

H37

H36

H34

H33

H32

H31

H30

B42

B39

B38

B36

B34

B32

B31

B28

B27

AR46

AR45

AR43

AR41

AR39

AR37

AR35

AP9

AP8

AP47

AP46

AP44

AP43

AP42

AP41

AP40

AP39

AP38

AP37

AP36

AP35

AP34

AP33

AP32

AP31

AP30

AP29

AP27

AP26

AP25

AP24

AP23

AP22

AP21

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

AP12

AP10

AN9

AN8

AN46

AN45

AN44

AN43

AN42

AN41

AN40

AN39

AN38

AN36

AN34

AN32

AN30

AN29

AN27

AN26

AN25

AN24

AN23

AN21

AN20

AN19

AN17

AN16

AN15

AN14

AN13

AN12

AN10

AM9

AM8

AM47

AM46

AL9

AL8

AL46

AL45

AK8

AK47

AK46

AJ46

AJ45

AH8

AH47

AH46

AG8

AG46

AF8

AE8

AE47

AE46

AD8

AD46

AC9

AC8

AC47

AC46

AB8

AB46

AB45

A34

A32

A31

A28

A27

U0500

OMIT_TABLE

HASWELL

BGA

18

2

1

R0860

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

58 89

19

SYNC_DATE=10/31/2014

SYNC_MASTER=CLEAN_X425

CPU Power

PP1V05_S0_CPU_VCCST CPU_VCCST_PWRGD

PPVCC_S0_CPU

CPU_VIDSOUT_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm

TP_CPU_RSVD_TP78

PP1V35_S3RS0_CPUDDR

CPU_VIDALERT_R_L

TP_CPU_IVR_ERROR

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

MIN_NECK_WIDTH=0.2 mm

CPU_VIDALERT_L

CPU_VIDSOUT

CPU_PWR_DEBUG

TP_CPU_RSVD_TP75 TP_CPU_RSVD_TP76

CPU_VCCSENSE_P

CPU_VIDSCLK_R

CPU_VIDSCLK

<SCH_NUM>

<BRANCH> 8 OF 119

8 OF 97

10 19

6 8

10 45 59 84 86

6 8

10 45 59 84 86

5 6

10 18 58

6

10 21 66 67 84 96

5

VSSVSS

GROUND

SYM 7 OF 12

VSS VSS

SYM 8 OF 12

GROUND

VSS

VSS_SENSE

VSS_NCTF

VSS_AB48(RSVD)

VSS_AR22(RSVD)

VSS_G18(RSVD)

VSS_P9(RSVD)

SYM 9 OF 12

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AT4

AT39

AT37

AT35

AT33

AT29

AT26

AT25

AT22

AT20

AT18

AT16

AT15

AT12

AT10

AT1

AR9

AR8

AR7

AR50

AR5

AR48

AR26

AR24

AR20

AR18

AR16

AR14

AR12

AP7

AP54

AP51

AN7

AN50

AN5

AN48

AN4

AN3

AN2

AN1

AM7

AM54

AM53

AM52

AM51

AM5

AL7

AL5

AL48

AL4

AL1

AK9

AK7

AK50

AK5

AK48

AJ54

AJ51

AJ48

AH7

AH50

AH5

AH48

AH4

AH3

AH2

AH1

AG9

AG7

AG54

AG53

AG52

AG51

AG5

AG48

AF7

AF6

AF5

AE7

AE50

AE5

AE48

AE4

AE3

AE2

AE1

AD9

AD7

AD54

AD51

AD48

AC7

AC50

AC5

AC48

AB9

AB7

AB54

AB53

AB52

AB51

AB5

AA7

AA5

AA48

AA4

AA3

AA2

AA1

A44

A40

A37

A33

A30

A26

A22

A19

A15

A11

U0500

HASWELL

OMIT_TABLE

BGA

BB9

BB7

BB6

BB5

BB49

BB48

BB47

BB46

BB44

BB43

BB42

BB41

BB39

BB38

BB37

BB33

BB32

BB28

BB25

BB23

BB20

BB18

BB17

BB16

BB15

BB14

BB12

BB11

BB10

BA9

BA53

BA52

BA51

BA50

BA5

BA42

BA4

BA37

BA33

BA29

BA25

BA22

BA18

BA13

B8

B49

B44

B40

B37

B33

B30

B26

B22

B19

B15

B11

AY9

AY50

AY42

AY37

AY33

AY29

AY25

AY22

AY13

AW9

AW54

AW51

AW50

AW5

AW49

AW47

AW46

AW45

AW43

AW42

AW37

AW18

AW13

AV9

AV50

AV5

AV42

AV4

AV33

AV3

AV29

AV25

AV22

AV2

AV18

AV13

AV1

AU9

AU5

AU42

AU37

AU33

AU29

AU25

AU22

AU18

AU13

AT9

AT8

AT6

AT54

AT53

AT52

AT51

AT50

AT5

AT49

AT47

AT46

AT45

AT43

AT42

AT40

U0500

HASWELL

OMIT_TABLE

BGA

Y9Y7Y48

W7

W54

W52

W50

W48

V9V7V48

U7U6U54

U52

U50

U5

U48

U4U3U2U1T48

D50

R7

R48P9P7P6P54

P52

P50

P5

P48

P4P3P2

P1

G1

F54

E54

D2

C53

BF6

BF50

BF5

BF49

BD53

BD2

BB54

BB1

BA54

BA1

B4A8A50

A49

N7

N48

M7

M54

M52

M50

M48

L9L7L48

K7K6K5K4K3K2K1J7J54

J51

J49

J44

H7

H49

H44

G9G8G7

G54

G52

G49

G44

G40

G37

G33

G30

G26

G25

G23

G20

G18

G16

G13

G11

F5

F49

F44

F40

F4

F37

F33

F30

F3

F26

F2

E8

E53

E51

E49

E44

E40

E37

E33

E30

E26

E25

E24

E22

E21

E20

E19

E17

E16

E15

E11

D8

D49

D44

D40

D37

D33

D30

D26

D22

D19

D15

D11

C8

C52

C49

C44

C40

C4

C37

C33

C30

C26

C22

C19

C15

C11

BF7

BF48

BF46

BF43

BF41

BF38

BF36

BF33

BF30

BF26

BF22

BF18

BF15

BF12

BF10

BE46

BE41

BE36

BE15

BE10

BD51

BD5

BD46

BD41

BD36

BD18

BD15

BD10

BC7

BC52

BC50

BC5

BC48

BC46

BC43

BC41

BC38

BC36

BC33

BC30

BC3

BC26

BC22

BC18

BC15

BC12

BC10

AR22

AB48

U0500

HASWELL

OMIT_TABLE

BGA

58 89

2

1

R0960

PLACE_NEAR=U0500.D50:50.8mm PLACE_SIDE=BOTTOM

402

MF-LF

1/16W

5%

100

CPU Ground

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU_VCCSENSE_N

<SCH_NUM>

9 OF 119

9 OF 97

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LOCATION DEPENDS ON DESENSE TEAM

FOR DESENSE IMPROVEMENT

Intel recommendation: 1x 0.1uF 0402, 1x 4.7uF 0805 Apple Implementation: 1x 0.1uF 0201, 1x 4.7uF 0402

CAPS for Acoustic Control (C102E to C103F)

LOCATION DEPENDS ON DESENSE TEAM

FOR DESENSE IMPROVEMENT

CPU VCCST Decoupling

PLACEMENT_NOTE (C1068-C1076:

CPU VDDQ Decoupling

Apple Implementation: 3x 270uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1080-C1089):

PLACEMENT_NOTE (C1090-C1097):

PLACEMENT_NOTE (C1020-C1023):

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)

(Z = 2mm, place on tall side next to CPU & under heat pipe)

CAPS for Acoustic Control (C109A to C102D)

CPU VCCIO Decoupling

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1000-C1019):

Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

CPU VCORE Decoupling

PLACEMENT_NOTE (C1098-C1099):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)

PLACEMENT_NOTE (C1024-C1045):

PLACEMENT_NOTE (C1046-C1067):

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

C1098, C1099 and C108A use B size caps due to EG board placement constraints.

2

1

C1009

X6S-CERM 0402

1UF

10V

10%

Place on bottom side of U0500

2

1

C1008

X6S-CERM

10V

0402

Place on bottom side of U0500

10%

1UF

2

1

C1007

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1031

CRITICAL

NO STUFF

2.5V X6S-CERM

20UF

20%

Place near inductors on bottom side.

0402

2

1

C1006

X6S-CERM

10% 10V

0402

Place on bottom side of U0500

1UF

2

1

C1005

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1004

X6S-CERM

10%

1UF

10V

0402

Place on bottom side of U0500

2

1

C1003

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1002

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1001

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

1UF

2

1

C1000

X6S-CERM

Place on bottom side of U0500

10V

10%

0402

1UF

2

1

C1030

Place near inductors on bottom side.

CRITICAL

NO STUFF

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1029

NO STUFF

Place near inductors on bottom side.

CRITICAL

X6S-CERM 0402

20UF

20%

2.5V

2

1

C1027

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1026

Place near inductors on bottom side.

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

CRITICAL

2

1

C1020

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1021

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1022

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1023

Place near U0500 on bottom side

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1025

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1024

CRITICAL

NO STUFF

0402

20%

X6S-CERM

2.5V

20UF

2

1

C1028

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1032

NO STUFF

Place near inductors on bottom side.

CRITICAL

X6S-CERM 0402

20UF

20%

2.5V 2

1

C1033

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM

20UF

20%

0402

2

1

C1039

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1038

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1037

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1036

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1035

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1034

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1079

0.01UF

10%

X7R-CERM

16V

0402

2

1

C1089

Place on bottom side of U0500

0402

10% 10V X6S-CERM

1UF

2

1

C1088

X6S-CERM

1UF

0402

10V

Place on bottom side of U0500

10%

2

1

C1087

X6S-CERM

10%

Place on bottom side of U0500

10V

1UF

0402

2

1

C1086

0402

X6S-CERM

1UF

10V

Place on bottom side of U0500

10%

2

1

C1085

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1084

X6S-CERM 0402

Place on bottom side of U0500

10V

1UF

10%

2

1

C1083

X6S-CERM 0402

Place on bottom side of U0500

1UF

10% 10V

2

1

C1082

X6S-CERM

1UF

0402

Place on bottom side of U0500

10V

10%

2

1

C1081

X6S-CERM

10V

1UF

0402

Place on bottom side of U100.

10%

2

1

C1080

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1093

Place near U0500 on bottom side

10UF

0402

X6S

4V

20%

2

1

C1092

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1091

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1090

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1097

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1096

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1095

10UF

X6S

Place near U0500 on bottom side

0402

4V

20%

2

1

C1094

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1043

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1042

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1041

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1040

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1019

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1018

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1017

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1016

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1015

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1014

X6S-CERM

Place on bottom side of U0500

1UF

10V

10%

0402

2

1

C1013

X6S-CERM

Place on bottom side of U0500

10% 10V

1UF

0402

2

1

C1012

X6S-CERM

1UF

10% 10V

Place on bottom side of U0500

0402

2

1

C1011

X6S-CERM

Place on bottom side of U0500

10% 10V

1UF

0402

2

1

C1010

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1065

X6S-CERM

2.5V

CRITICAL

0402

20UF

20%

Place near inductors on bottom side.

2

1

C1064

X6S-CERM

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

2

1

C1063

X6S-CERM

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

2

1

C1062

20%

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

2

1

C1061

20UF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20%

2

1

C1060

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1059

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1058

2.5V

CRITICAL

Place near inductors on bottom side.

X6S-CERM 0402

20UF

20%

2

1

C1057

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1056

CRITICAL

ACAPS:A2

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1055

CRITICAL

ACAPS:A1

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1054

ACAPS:A2

Place near inductors on bottom side.

CRITICAL

2.5V

X6S-CERM 0402

20UF

20%

2

1

C1053

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1052

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1051

ACAPS:A1

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1050

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1049

X6S-CERM

ACAPS:A1

Place near inductors on bottom side.

CRITICAL

2.5V

0402

20UF

20%

2

1

C1048

CRITICAL

Place near inductors on bottom side.

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1047

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

CRITICAL

2

1

C1046

CRITICAL

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1045

ACAPS:A2

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1044

Place near inductors on bottom side.

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1067

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1066

0402

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM

20UF

20%

2

1

C1068

CRITICAL

CASE-B2S

2.5V

210UF

POLY-TANT

20%

2

1

C1069

POLY-TANT

2.5V

210UF

CASE-B2S

CRITICAL

20%

2

1

C1070

POLY-TANT CASE-B2S

210UF

CRITICAL

2.5V

20%

2

1

C1071

POLY-TANT

2.5V

CASE-B2S

210UF

CRITICAL

20%

2

1

C1072

CRITICAL

POLY-TANT

2.5V

CASE-B2S

210UF

20%

2

1

C1073

POLY-TANT

2.5V

210UF

CASE-B2S

CRITICAL

20%

2

1

C1074

CASE-B2S

POLY-TANT

2.5V

210UF

CRITICAL

20%

2

1

C1075

POLY-TANT

210UF

2.5V

CASE-B2S

CRITICAL

20%

2

1

C1076

CRITICAL

CASE-B2S

POLY-TANT

2.5V

NO STUFF

210UF

20%

2

1

C103F

0402

2.5V

CRITICAL

Place near inductors on bottom side.

X6S-CERM

20UF

20%

2

1

C103E

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103D

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103C

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103B

NO STUFF

20UF

20%

0402

CRITICAL

2.5V X6S-CERM

2

1

C103A

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102F

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102E

CRITICAL

ACAPS:A2

2.5V X6S-CERM 0402

20UF

20%

2

1

C101B

CRITICAL

ACAPS:A1

2.5V X6S-CERM 0402

20UF

20%

2

1

C101A

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109F

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109E

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109D

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109C

CRITICAL

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C109B

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109A

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102D

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102C

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102B

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102A

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101E

CRITICAL

ACAPS:A1

2.5V X6S-CERM 0402

20UF

20%

2

1

C101D

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101C

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101F

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

3 2

1

C1077

CRITICAL

330UF-9MOHM

D15T-1

2.5V POLY-TANT

NO STUFF

20%

2

1

C1098

CRITICAL

270UF

CASE-B2-SM

TANT

2V

20%

2

1

C1099

CRITICAL

CASE-B2-SM

TANT

270UF

2V

20%

2

1

C108A

270UF

2V CASE-B2-SM

CRITICAL

TANT

20%

2

1

C108B

0201

12PF

5% NP0-C0G

25V

CRITICAL

2

1

C108D

CRITICAL

0201

12PF

5% NP0-C0G

25V

2

1

C108C

CRITICAL

25V

NP0-C0G

5%

12PF

0201

2

1

C108E

5% NP0-C0G

25V

12PF

0201

CRITICAL

2

1

C107A

CRITICAL

NP0-C0G 0201

25V

+/-0.1PF

3.0PF

2

1

C107B

CRITICAL

0201

3.0PF

NP0-C0G

25V

+/-0.1PF

21

R1080

BDW_SPRT

1/10W

0

603

5%

MF-LF

2

1

C106A

BDW_SPRT

0.1UF

10%

6.3V CERM-X5R 0201

PLACE_NEAR=U0500.D5:12.7mm

2

1

C106B

BDW_SPRT

402

6.3V X5R

4.7UF

PLACE_NEAR=U0500.D5:25.4mm

20%

CPU Decoupling

SYNC_MASTER=CLEAN_X305G

SYNC_DATE=08/11/2014

PP1V05_S0_CPU_VCCST

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

PPVCC_S0_CPU

10 OF 97

<SCH_NUM>

10 OF 119

8

19

14 15 17 18 41 62 67 84 86

6 8

21 66 67

84 96

5 6 8

18 58

6 8

45 59 84 86

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

OUT OUT

IN

OUT OUT

OUT

NC

HDA_SDI0

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_TXP3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_RXN0

INTVRMEN

RTCRST*

SATA_RXP1

SATA_RXN1

SATA_TXP0

SATA1GP/GPIO19

SATA_IREF

TP9

SATA_TXN3

SATA_RXP3

SATA_RXN3

SATA_TXP2

SATA_TXN2

SATA_RXN2 SATA_RXP2

HDA_SDO

HDA_SDI3

INTRUDER*

JTAG_TCK

TP20

JTAG_TMS

JTAG_TDO

JTAG_TDI

SATALED*

SATA0GP/GPIO21

SATA_TXN1

SATA_TXN4/PETN1

SATA_TXP1

SATA_TXP4/PETP1

SATA_TXN0

SATA_RCOMP

DOCKEN*/GPIO33

RTCX2

RTCX1

SRTCRST*

TP8

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_RXP0

HDA_DOCK_RST*/GPIO13

TP22

TP25

HDA_SDI2

HDA_SDI1

HDA_RST*

SPKR

HDA_SYNC

HDA_BCLK

SATA

AZALIA

RTC

(1 OF 11)

JTAG

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_DP_P

PEG_A_CLKRQ*/GPIO47

(2 OF 11)

CLOCKS

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-RSMRST#)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

If HDA = S0, must also ensure that signal cannot be high in S3.

(IPD)

(IPD-PLTRST#)

(IPU)

1.5V -> 1.1V

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK)

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPU-PLTRST#)

(IPD)

Unused clock terminations for FCIM Mode

(IPD-boot)

(IPU)

(IPD)

Unused

(if not combo w/SD Card)

Reserved: Ethernet

SATA Port assignments:

PCIe:

Unused

Reserved: ODD

Primary HDD/SSD (SATA only)

Secondary HDD/SSD (SATA only)

NOTE: ENET pair only used if SD Card Reader is USB3.

(IPD)

(IPD-DOCKEN#?)

CLKOUT_PEG outputs can be used for those devices.

If 2 or less devices are attached to PEG the

while PCH-attached PCIe devices use the other set.

PEG-attached (CPU) PCIe devices must use one set,

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.

19 90

52 91

2

1

R1100

330K

1/20W

5%

201

MF

2

1

R1101

1/20W

5%

201

MF

1M

2

1

R1102

1/20W

5%

201

MF

20K

2

1

R1103

1/20W

5%

201

MF

20K

2

1

C1103

10V

10% 402

X5R

1UF

2

1

C1102

10V

10% 402

X5R

1UF

2

1

R1130

1/20W

1%

201

MF

7.5K

PLACE_NEAR=U1100.AY5:2.54mm

11 85

18 86

21

R1172

340

MF-LF

402

1%

1/16W

2

1

R1173

1K

1/20W

1%

201

MF

19 90

18

11 18

33 91

36 91

18

36 91

11 34

11 35

11 28

6

89

6

89

6

89

6

89

19 91

11 82 85

28 91

21

R1177

MF

1/20W

5% 201

4.7K

21

R1178

4.7K

201

1/20W

5% MF

21

R1134

10K

MF 2015%

1/20W

21

R1142

10K

MF 2015%

1/20W

21

R1169

10K

MF 2015%

1/20W

21

R1144

10K

MF 2015%

1/20W

21

R1145

10K

MF 2015%

1/20W

21

R1147

10K

MF 2015%

1/20W

12

R1114

10K

MF 2015%

1/20W

21

R1115

10K

MF 201

1/20W

5%

21

R1143

1/20W

5% 201MF

10K

21

R1133

1/20W

5% 201MF

10K

21

R1179

1/20W

10K

MF 2015%

21

R1146

1/20W

5% 201MF

10K

21

R1148

1/20W

5% 201MF

10K

52 91

21

R1191

10K

MF 2015%

1/20W

21

R1192

10K

MF 2015%

1/20W

21

R1193

10K

MF5%

1/20W

201

21

R1194

10K

MF 2015%

1/20W

21

R1195

10K

MF 2015%

1/20W

21

R1196

10K

MF 2015%

1/20W

21

R1197

10K

MF 2015%

1/20W

21

R1170

5% 201MF

10K

1/20W

21

R1171

10K

MF 2015%

1/20W

BA2 BB2

F8 C26 AB6

B9

AL10

AP3

AR15

AW15

AT13

AW13

AW10

AY8

AP15

AV15

AR13

AY13

AV10

AW8

BE14

BB13

BE12

BD9

BE10

BE8

BC14

BD13

BC12

BB9

BC10

BC8

AY5

BD4

AU2

AT1

B4

B5

D9

AD1

AD3

AE2

AB3

G10

A8

A22

A24

F22

G22

K22

L22

C24

C22

B25

B17

U1100

OMIT_TABLE

LYNXPOINT

MOBILE

FCBGA

AL44

AM43

AD39 AD38

F45

U4

AF6

Y3

AE4

AA2

V3

T3

AF3

AF1

AB1

AM45

AN44

F39

F36

F38

C40

Y38

Y39

AB36

AB35

AJ42

AB39

AE42

AF45

AD45

AB45

AA42

Y45

AJ44

AB40

AE44

AF43

AD43

AB43

AA44

Y43

AH45

AH43

AF36

AF35

AJ39

AJ40

AF40

AF39

A40

F41

B42

E44

D44

BC6

BE6

AT24

AR24

G33

H33

AW24

AY24

D17

U1100

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

6

89

6

89

87 89

21

R1110

PLACE_NEAR=U1100.B25:1.27mm

MF 2015%

1/20W

33

21

R1113

PLACE_NEAR=U1100.A24:1.27mm

2015%

1/20W33MF

21

R1111

1/20W

5% 201MF

33

PLACE_NEAR=U1100.A22:1.27mm

21

R1112

PLACE_NEAR=U1100.C24:1.27mm

33

MF 2015%

1/20W

19 91

87 91

19 91

87 90

87

11 18

12

R1190

1/20W

MF

1%

PLACE_NEAR=U1100.AN44:2.54mm

201

7.5K

11 85

21

R1176

10K

MF 2015%

1/20W

34 91

11 85

87 90

70 85 91

PCH RTC/HDA/JTAG/SATA/CLK

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PP3V3_S0

PP3V3_SUS

NC_PCIE_CLK100M_ENETSDP

NC_PCIE_CLK100M_ENETSDN

SSD_CLKREQ_L

PCH_SATA_RCOMP

PCH_SATALED_L

NC_SATA_B_R2D_CP

NC_SATA_B_R2D_CN

NC_SATA_B_D2RP

NC_SATA_B_D2RN

NC_SATA_A_D2RN NC_SATA_A_D2RP NC_SATA_A_R2D_CN NC_SATA_A_R2D_CP

NC_SATA_ODD_D2RN NC_SATA_ODD_D2RP NC_SATA_ODD_R2D_CN NC_SATA_ODD_R2D_CP

XDP_DC1_SATARDRVR_EN

XDP_DC0_DP_AUXCH_ISOL_L

NC_SATA_F_R2D_CN

NC_SATA_F_D2RP

NC_SATA_F_R2D_CP

NC_SATA_D_R2D_CN

NC_SATA_D_D2RP

NC_SATA_D_R2D_CP

NC_SATA_D_D2RN

TP_PCIE_ENET_D2RN TP_PCIE_ENET_D2RP

NC_SATA_F_D2RN

TP_PCIE_ENET_R2D_CP

TP_PCIE_ENET_R2D_CN

HDA_SDOUT_R

NC_HDA_SDIN2

TBT_CLKREQ_L

CAMERA_CLKREQ_L

NC_PCIE_CLK100M_ENETP

PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_PEGBP

DMI_CLK100M_CPU_P

CPU_CLK135M_DPLLSS_N CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLREF_N CPU_CLK135M_DPLLREF_P

PCH_CLK100M_SATA_N

PP1V5_S0

DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

PCH_CLK33M_PCIOUT

NC_LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

NC_ITPXDP_CLK100MP

NC_ITPXDP_CLK100MN

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PEG_CLKREQ_L

TBT_CLKREQ_L

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

XDP_DD3_AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

LPC_CLK33M_DPMUX_UC_R

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_SWP

NC_PCIE_CLK100M_SWN

PCH_CLKRQ7_L_GPIO46

NC_PCI_CLK33M_OUT3

NC_PCIE_CLK100M_PE5N

PCH_CLKRQ5_L_GPIO44

PCH_CLK96M_DOT_P

SYSCLK_CLK25M_SB_R

PCH_CLK33M_PCIIN

NC_PCH_GPIO65_CLKOUTFLEX1

XDP_PCH_TDI

PCH_SPKR

RTC_RESET_L

PCH_INTVRMEN_L

HDA_RST_L

HDA_SYNC

ENET_CLKREQ_L

PCH_CLKRQ7_L_GPIO46

PEG_CLKREQ_L

PCH_CLKRQ5_L_GPIO44

AP_CLKREQ_L

XDP_DD2_ENETSD_CLKREQ_L

PCH_SATALED_L

NC_PCH_GPIO64_CLKOUTFLEX0

SSD_CLKREQ_L

PP1V5_S0

XDP_PCH_TDO

XDP_PCH_TMS

HDA_BIT_CLK

HDA_RST_R_L

HDA_BIT_CLK_R

SYSCLK_CLK32K_RTC

NC_PCIE_CLK100M_ENETN

DMI_CLK100M_CPU_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

NC_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_GPIO66_CLKOUTFLEX2

PCH_CLK100M_SATA_P

PCH_CLKIN_GNDP

PCH_CLKIN_GNDN

PCH_CLK14P3M_REFCLK

PCH_DIFFCLK_BIASREF

NC_HDA_SDIN1

NC_HDA_SDIN3

SYSCLK_CLK25M_SB

PPVRTC_G3H

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTVRMEN_L

PCH_INTRUDER_L

PP1V5_S0

HDA_SYNC_R

PCH_INTRUDER_L

PCH_SRTCRST_L

DP_TBT_SEL

PCH_SPKR

PCH_CLK96M_DOT_N

HDA_SDIN0

HDA_SDOUT

DP_TBT_SEL ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

ENET_MEDIA_SENSE_RDIV

PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_PEGBN

ENET_CLKREQ_L

PEG_CLK100M_N PEG_CLK100M_P

XDP_DD2_ENETSD_CLKREQ_L

<SCH_NUM>

11 OF 119

11 OF 97

12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

12 13 14 15 17 50 64 66 67 84

90

11

87

19 91

87

11 28

11 35

87

11

87

91

11 12 13 15 17 19 52 64 67 81 84 86

18 85

11 18

20

87

11

87

11

91

90

87

11

11 91

11 85

11

11 82 85

11

18 33

11 18

11

87

11 34

11 12 13 15 17 19 52 64 67 81 84 86

91

87

91

87

91

87

12 15 19 84

11

11 91

11 12 13 15 17 19 52 64 67 81 84 86

91

11 91

11 85

11

91

11 85

11

87

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

VGA_DDC_CLK

DDPD_AUXN

DDPB_AUXP

VGA_GREEN

DDPB_AUXN

PLTRST*

PME*

PIRQB* PIRQC* PIRQD*

GPIO50 GPIO52

PIRQA*

DDPD_CTRLCLK

DDPD_CTRLDATA

PIRQE*/GPIO2

DDPD_HPD

DDPB_HPD

DDPD_AUXP

DDPC_AUXP

DDPC_HPD

PIRQF*/GPIO3

EDP_BKLTCTL

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

GPIO53 GPIO55

GPIO51

GPIO54

EDP_BKLTEN

DDPC_AUXN

PIRQG*/GPIO4 PIRQH*/GPIO5

VGA_VSYNC

VGA_IRTN

VGA_BLUE

VGA_RED

VGA_DDC_DATA

VGA_HSYNC

DAC_IREF

EDP_VDDEN

EDP

(5 OF 11)

DISPLAY

PCI

CRT

OUT

IN

OUT

IN

BI

OUT

IN

DMI_RXN3

FDI_CSYNC

FDI_INT

FDI_IREF

DMI_RXN2

SYS_PWROK

CLKRUN*

SLP_S3*

TP10

DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_RXP0

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

WAKE*

TP7

DMI_RCOMP

TP12

DMI_IREF

DMI_TXP3

DMI_TXP2

FDI_RCOMP

DMI_TXN0

SUSWARN*/SUSPWRNACK/GPIO30

TP21

APWROK

FDI_RXN0

FDI_RXP0

FDI_RXN1

FDI_RXP1

SYS_RESET*

DMI_RXN1

TP17 TP13

TP16

TP15

DMI_RXN0

PMSYNCH

TP5

DMI_TXP0 DMI_TXP1

DMI_TXN2 DMI_TXN3

DMI_TXN1

SLP_S4*

DSWVRMEN

SLP_WLAN*/GPIO29

ACPRESENT/GPIO31

SLP_SUS*

PWROK

SLP_A*

SLP_LAN*

DRAMPWROK

RSMRST*

PWRBTN*

BATLOW*/GPIO72

DPWROK

RI*

SUSACK*

FDI

DMI

(4 OF 11)

MANAGEMENT

SYSTEM POWER

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VGA DAC Disabled per SB

Redundant to pull-up on audio page

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPU-PWROK&PCIRST#)

(IPU)

(OD)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

DG v1.0 (Table 12-18).

(IPD-DeepSx)

5

89

5

89

2

1

R1200

201

1/20W

MF

1%

7.5K

PLACE_NEAR=U1100.AY17:12.7mm

5

89

5

89

5

89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

N44

V45

U39

N42

U44

M45

M43

T45

AD10

Y11

M15

L15

F17

G17

M20

K17

L20

H20

AL6

C12

A10

B13

C10

A12

G36

K36

N36

H39

N38

N40

J44

J42

K38

R36

R35

K45

K43

K40

R39

R40

H43

H45

U40

U1100

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

2

1

R1215

5%

201

1/20W MF

330K

12 44 66 67

2

1

R1209

5%

201

1/20W MF

100K

19 40 86 91

18 19 40 86 91

6

21 89

12 19 86 91

67 86 91

12 18 40 91

40 41

12 30 40 42

12 33 35 86 91

12 40

20 40

41

12 40 67

12 21 33 37 40 67 81 86

12 21 40 67 86

6

89

40 86 91

12

R1223

5%

201

1/20W

MF

100K

21

R1225

5%

201

1/20W

MF

1K

21

R1291

5%

201

1/20W

MF

10K

12

R1222

5%

201

1/20W

MF

100K

12

R1221

5%

201

1/20W

MF

100K

12

R1224

5%

201

1/20W

MF

100K

12

R1284

5%

201

1/20W

MF

100K

12

R1281

5%

201

1/20W

MF

100K

K3

AV17

AY45

AB10

AU42

AV43

AV45

AU44

AW17

AW44

AM1

AD7

J4

Y6

R6

U7

D2

F1

Y7

C6

H1

G5

F3

J2

N4

F10

K1

AY3

AL36

AJ36

AL35

AJ35

AR44

AT45

AL40

AL39

C8

H3

L13

BC18

BB17

BC20

BB21

BE18

BD17

BE20

BD21

AW20

AR17

AP20

AY22

AV20

AP17

AR20

AW22

AY17

BE16

AN7

K7

AB7

E6

U1100

OMIT_TABLE

FCBGA

LYNXPOINT

MOBILE

12 82 85

87

5

89

2

1

R1210

201

1/20W

MF

PLACE_NEAR=U1100.AR44:12.7mm

7.5K

1%

21

R1261

5% 201

1/20W

MF

10K

21

R1263

5% 201

1/20W

MF

10K

21

R1262

5% 201

1/20W

MF

10K

21

R1260

5% 201

1/20W

MF

10K

21

R1233

5% 201

1/20W

MF

NO STUFF

10K

21

R1231

5% 201

1/20W

MF

10K

21

R1214

5% 201

1/20W

MF

100K

NO STUFF

21

R1230

5% 201

1/20W

MF

10K

21

R1217

5% 201

1/20W

MF

100K

21

R1218

5% 201

1/20W

MF

10K

12 85

21

R1216

5% 201

1/20W

MF

10K

12 85

12 29

12 85

18 20 21 86

12 85

12

R1240

5%

201

1/20W

MF

10K

21

R1239

5%

201

1/20W

MF

3.0K

42

12 85

2

1

R1205

5%

1/20W

MF

10K

201

2

1

R1287

201

MF

1/20W

5%

10K

NO STUFF

42

2

1

R1286

SMC_SUSACK:NO

0201

1/20W

5%

0

MF

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PP1V5_S0

SDCONN_OC_L

AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

PM_PCH_PWROK

BT_PWRRST_L

ENET_LOW_PWR_PCH

PCI_INTA_L

PCI_INTD_L

AUD_IPHS_SWITCH_EN_PCH

TP_PCH_STRP_ESI_L

TP_PM_SLP_A_L

PM_SLP_S3_L

TP_PCH_SLP_WLAN_L

PM_CLKRUN_L

PCIE_WAKE_L

TP_PCH_SLP_LAN_L

PCI_INTC_L

PCI_INTB_L

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

NC_EDP_IG_BKL_PWM

PM_BATLOW_L

PM_PCH_SYS_PWROK

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1> DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

AUD_IP_PERIPHERAL_DET

DP_TBTSNK0_HPD_IG

NC_DP_IG_D_AUXCHP

DPA_IG_AUX_CH_P

NC_DP_IG_D_AUXCHN

DPB_IG_AUX_CH_N

TP_DP_IG_D_DDC_CLK TP_DP_IG_D_DDC_DATA

DPB_IG_DDC_CLK

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

TP_PCH_STRP_BBS1

PM_SLP_S4_L

FDI_INT

FDI_CSYNC

TP_PCH_SLP_S0_L

PM_DSW_PWRGD

PCH_DSWVRMEN

PPVRTC_G3H

DPA_IG_AUX_CH_N

PP1V5_S0

PM_MEM_PWRGD PM_RSMRST_L

PM_SYSRST_L

DPB_IG_DDC_DATA

TBT_PWR_REQ_L

TP_DP_IG_D_HPD

DP_TBTSNK1_HPD_IG

DPB_IG_AUX_CH_P

PP3V3_S0

SMC_ADAPTER_EN

PCH_STRP_TOPBLK_SWP_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCH_FDI_RCOMP

PM_PWRBTN_L PM_BATLOW_L PM_CLKRUN_L ENET_LOW_PWR_PCH

BT_PWRRST_L SDCONN_OC_L

AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L

AUD_I2C_INT_L PCIE_WAKE_L

PM_SLP_S4_L

PM_SLP_SUS_L EDP_IG_BKL_ON

EDP_IG_PANEL_PWR

PP3V3_S5

PM_SYNC

PM_SLP_SUS_L

PM_SLP_S5_L

PM_SLP_S3_L

PP3V3_S0

PCH_DMI_RCOMP

AUD_IPHS_SWITCH_EN_PCH

PM_PWRBTN_L

PM_PCH_PWROK

PP3V3_SUS

PCH_SUSACK_L

PCH_RI_L

PCH_SUSWARN_L

12 OF 97

12 OF 119

<SCH_NUM>

11 12 13 15 17 19 52 64 67 81 84 86

87

82 85

87

83 85 89

87

83 85 89

83 85

91

11 15 19 84

83 85 89

11 12 13 15 17 19 52 64 67 81 84 86

83 85

82 85

83 85 89

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

12 18 40 91

12 30 40 42

12 40

12 85

12 29

12 85

12 33 35 86 91

12 21 33 37 40 67 81 86

12 44 66 67

12 82 85

14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 40 67

12 21 40 67 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67

68 69 82 83 84 86 96

12 85

11 13 14 15 17 50 64 66 67 84

BI

BI BI

IN IN

OUT

IN

OUT

IN

BI

IN

USBRBIAS

USBRBIAS*

TP24 TP23

USB2P12

USB2N12

PETP3

PETP2_USB3TP4

USB2P11

USB2P1

USB2P13

USB2N11

USB2P7

USB2N8

USB2P9

USB2N9

USB2N3

USB2N2

USB2N1

PERN8 PERP8

USB3RP1

USB3RP6

USB3RN1

USB3RN6

PERP2_USB3RP4

PERP4

PERN4

PERP7

PERN7

USB3RP2

USB3RP5

PERP5

USB3RN2

USB3RN5

PERN1_USB3RN3

PERN3

PERP6

PERP3

PERN6

USB2N10

USB2N4

USB2N0

TP6

PETP5

USB3TP2

USB3TP5

TP11

PETN6

PETP7

USB3TP1

USB3TN2

USB3TN6

PCIE_RCOMP

PETN5

PETP8

PETN8

USB3TN1

USB3TN5

USB3TP6

PCIE_IREF

PETN1_USB3TN3

PETN3

PETP6

PETN7

USB2P8

USB2P3

USB2P2

USB2P10

USB2P4

USB2P0

USB2N13

USB2N5

USB2N7

USB2P5

USB2N6 USB2P6

OC7*/GPIO14

OC4*/GPIO43

OC6*/GPIO10

OC3*/GPIO42

OC0*/GPIO59

OC5*/GPIO9

OC2*/GPIO41

OC1*/GPIO40

PERP1_USB3RP3

PETP1_USB3TP3

PERN2_USB3RN4

PETN2_USB3TN4

PETN4 PETP4

PERN5

PCI-E

USB

(9 OF 11)

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

LAD3

LFRAME*

SML0DATA

LAD0

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

CL_DATA

CL_CLK

TD_IREF

LDRQ0*

SML1CLK/GPIO58

CL_RST*

SML1DATA/GPIO75

LAD2

SPI_MOSI

SPI_MISO

SPI_CS2*

SPI_CLK

SPI_IO3

SPI_IO2

SPI_CS0*

SERIRQ

SPI_CS1*

TP1 TP2 TP4 TP3

LAD1

LDRQ1*/GPIO23

SML1ALERT*/PCHHOT*/GPIO74

SML0CLK

C-LINK

SPI

(3 OF 11)

LPC

SMBUS

IN BI

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

NC

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext B (LS/FS/HS)

Ext C (SS)

(IPD)

Trackpad

BT

IR

Ext D (SS)

USB3 Port Assignments:

Ext B (SS)

Ext A (SS)

Reserved: Camera

Ext D (LS/FS/HS)

Unused

Reserved: PSOC (Legacy Trackpad)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Reserved: WiFi (HS)

Reserved: SD (HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

AirPort

Camera

Lane 3 (PCIe-only)

Lane 2 (PCIe-only)

SSD (Gumstick)

Or PCIe switch if TBT/SSD

SSD (Gumstick)

(PCIe-only)

Lane 0

Lane 1

Or PCIe switch if TBT/SSD

(PCIe-only)

USB3 Port Assignments:

PCIe/USB3 Port Assignments:

SD Card Reader (& Ethernet if combo)

PCIe Port Assignments:

Unused

SSD (Gumstick)

87 90

12

R1367

1/20W

5% 201MF

10K

21

R1368

10K

MF 2015%

1/20W

21

R1361

10K

1/20W

MF 2015%

21

R1362

10K

MF 2015%

1/20W

21

R1360

10K

MF 201

1/20W

5%

21

R1369

10K

MF 2015%

1/20W

13 18

18

13 18

18

13 18

37 90

13 18

K24 K26

BE28

BC26

BC24

BD23

BD27

BE26

BD25

BE24

AP29

AV29

AV26

AP26

AR29

AW29

AW26

AR26

C30

C32

H29

L31

G31

D33

C34

C36

G24

F26

C28

D29

C38

D37

A30

A32

G29

K31

F31

B33

A34

A36

F24

G26

A28

B29

A38

B37

BB29

M33 L33

BC30

BD41

BC40

BE38

BB37

BC36

BC34

BB33

BC32

BD42

BE40

BC38

BD37

BE36

BE34

BD33

BE32

AN39

AT39

AW38

AV36

AR33

AY33

AR31

AY31

AN38

AT40

AY38

AW36

AT33

AW33

AT31

AW31

BD29

BE30

M1

N2

T1

M3

P1

U2

V1

P3

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

37 90

81 86 90

81 90

87 90

50 91

BE43 BE44

BC45

BA45

AY43

AH1

AH3

AJ2

AJ4

AJ10

AL7

AJ7

AJ11

N11

K6

H6

R7

U8

N8

U11

R10

N7

AL11

B21

G20

D21

C18

A18

C20

A20

AF7

AF10

AF11

U1100

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

43 91

18 43 81 85 86 91

2

1

R1300

PLACE_NEAR=U1100.BD29:12.7mm

1/20W 201

MF

1%

7.5K

21

R1340

201MF5%

1/20W

33

21

R1341

MF 2015%

1/20W

33

21

R1343

2015%331/20W

MF

21

R1342

MF 201

33

5%

1/20W

21

R1344

5% 201MF

1/20W

33

13 20

13 40

21

R1350

1/20W

5% 201MF

10K

40 82 91

2

1

R1380

8.2K

MF

1/20W 201

1%

33 90

87 90

38 86 90

21

R1355

1/20W

5% 201MF

10K

21

R1354

1/20W

5% 201MF

10K

21

R1353

1/20W

5% 201MF

10K

21

R1320

1/20W

5% 201MF

10K

21

R1321

1/20W

5% 201MF

10K

50 91

13 50 91

18

21

R1351

10K

MF 2015%

1/20W

21

R1393

1/20W

5% 201MF

1K

21

R1392

1/20W

5% 201MF

1K

81 86 90

20 81 86 91

81 86 90

85

20 33 91

33 91

20 36 91

36 91

2

1

R1370

1% 1/20W

201

MF

22.6

PLACE_NEAR=U1100.K24:11.4mm

PCH PCI-E/USB

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CAMERA_PWR_EN_PCH

XDP_DB1_USB_EXTD_OC_L

SPI_IO<2>

XDP_DB3_SDCONN_STATE_CHANGE_L

SD_PWR_EN

SSD_PWR_EN

XDP_DA1_USB_EXTC_OC_L

TBT_PWR_EN_PCH XDP_DA0_USB_EXTA_OC_L

XDP_DB0_USB_EXTB_OC_L

PCH_SMBALERT_L PCH_SML0ALERT_L PCH_SML1ALERT_L

NC_PCIE_SSD_D2RN<0> NC_PCIE_SSD_D2RP<0>

NC_PCIE_SSD_D2RP<1>

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_P

USB3_SD_D2R_N

NC_USB3_SPARE_R2D_CN NC_USB3_SPARE_R2D_CP

NC_USB3_SPARE_D2RN NC_USB3_SPARE_D2RP

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_P PCIE_CAMERA_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

NC_PCIE_SSD_R2D_CP<0>

NC_PCIE_SSD_D2RN<1>

NC_PCIE_SSD_R2D_CP<1>

NC_PCIE_SSD_R2D_CN<1>

NC_PCIE_SSD_R2D_CN<0>

NC_PCIE_SSD_D2RN<2>

NC_PCIE_SSD_R2D_CN<2>

NC_PCIE_SSD_D2RP<2>

NC_PCIE_SSD_R2D_CN<3> NC_PCIE_SSD_R2D_CP<3>

NC_PCIE_SSD_D2RP<3>

NC_PCIE_SSD_D2RN<3>

NC_PCIE_SSD_R2D_CP<2>

PCH_USB_RBIAS

LPC_AD_R<0>

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

NC_CLINK_DATA

NC_CLINK_CLK

PCH_TD_IREF

NC_CLINK_RESET_L

SPI_MOSI_R SPI_MISO

TP_SPI_CS2_L

SPI_CLK_R

SPI_IO<3>

SPI_IO<2>

SPI_CS0_R_L

LPC_SERIRQ

TP_SPI_CS1_L

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTA_N USB_EXTA_P

NC_USB_EXTCN NC_USB_EXTCP

USB_EXTB_N USB_EXTB_P

NC_USB_EXTDN NC_USB_EXTDP

USB_BT_N

NC_USB_IRN

USB_BT_P

USB_TPAD_N

NC_USB_IRP

USB_TPAD_P

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_P USB3_EXTB_R2D_C_N

NC_USB3_EXTC_D2RP

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_R2D_CN

XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTC_OC_L

XDP_DA3_CAMERA_PWR_EN XDP_DB0_USB_EXTB_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

NC_USB_7P

NC_USB_WLANN

NC_USB_SDN

TP_USB_CAMERAN

NC_USB_4N

NC_USB_WLANP

NC_USB_SDP

NC_USB_4P NC_USB_PSOCN

NC_USB_7N

NC_USB_PSOCP NC_USB_6N

PP1V5_S0

NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RP

NC_USB3_EXTD_R2D_CP

XDP_DB2_SD_PWR_EN

PCH_PCIE_RCOMP

NC_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

NC_USB3_EXTC_R2D_CN

TP_USB_CAMERAP

NC_USB_6P

XDP_DA2_SSD_PWR_EN

USB3_EXTB_R2D_C_P NC_USB3_EXTC_D2RN

SPI_IO<3>

LPC_SERIRQ

PP3V3_SUS PP3V3_SUS

PP3V3_S0

PP3V3_S3RS0_CAMERA

PP3V3_S3

13 OF 119

<SCH_NUM>

13 OF 97

18 20

13 18

13 50 91

13 18

18 81 86

18 66

13 18

13 20

13 18

13

87

90

13

87

13

87 90

87

87 90

87

87 90

87

87 90

87

87 90

11 12 15 17 19 52 64 67 81 84 86

87

87 90

13 50 91

13 40

11 12 13 14 15 17 50 64 66 67 84

11 12 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

20 35 46 84

20 21 43 45 46 66 81 82 84 86

OUT

BI

IN

OUT

IN

BI

ININ

OUT

IN

OUT

SATA2GP/GPIO36

VSS

RCIN*

PROCPWRGD

PECI

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

VSS

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

LAN_PHY_PWR_CTRL/GPIO12

TP14

PLTRST_PROC*

GPIO8

VSS

TACH0/GPIO17

SATA4GP/GPIO16

GPIO15

GPIO28

SATA3GP/GPIO37

SATA5GP/GPIO49

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

GPIO34

GPIO35/NMI*

SLOAD/GPIO38

THRMTRIP*

SCLOCK/GPIO22

TACH4/GPIO68

GPIO27

GPIO57

GPIO24

BMBUSY*/GPIO0

(6 OF 11)

GPIO

CPU/MISC

OUT

BI

OUT

IN

OUT

BI

OUT

IN

IN IN

OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

Pull-up/down on chipset support page (depends on TBT controller)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high. Systems with chip-down memory should add pull-downs on another page and set straps per software.

Falcon Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.

(IPU-Boot/SATA5GP?)

NOTE: GPIO0 pull-up/down on project-specific page

(IPD-PLTRST#)

(IPD)

(IPU-RSMRST#)

(IPU-DeepSx)

(IPU-Boot/SATA4GP?)

(IPU-Boot?)

NOTE: GPIO70 pull-up/down on project-specific page

6

18 89

14 85

14 20

18

14 20

14 50 86

6

41 89

2

1

R1472

5%

201

1/20W MF

10K

RAMCFG3:H

2

1

R1473

5%

201

1/20W

MF

10K

RAMCFG2:H

2

1

R1474

5%

201

1/20W MF

10K

RAMCFG1:H

2

1

R1475

5%

201

1/20W

MF

10K

RAMCFG0:H

14 40

14 20

14 40

14 85

N10

A4

E45

E1

D1

BE3

BE2

BD45

BD44

BD2

BD1

BC1

BA1

B45

B44

B2

B1

A44

A43

A41

A2

A5

C45

BE5

BE41

AN10

AV1

H15

G13

D13

C16

G15

A14

F13

C14

AT7

AN4

AM3

BB4

AK3

AN2

AK1

AT3

AT6

AV3

AU4

AY1

K13

Y1

U12

AP1

AN6

AD11

R11

Y10

AB11

AT8

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

12

R1411

5% 201

1/20W

MF

20K

12

R1495

5% 201

1/20W

MF

100K

21

R1491

5% 201

1/20W

MF

10K

21

R1492

5% 201

1/20W

MF

10K

21

R1493

5% 201

1/20W

MF

100K

21

R1494

5% 201

1/20W

MF

10K

21

R1484

5% 201

1/20W

MF

10K

21

R1490

5% 201

1/20W

MF

100K

21

R1496

5% 201

1/20W

MF

10K

21

R1485

5% 201

1/20W

MF

10K

12

R1412

5% 201

1/20W

MF

10K

29

14 18

12

R1498

5% 201

1/20W

MF

10K

21

R1450

5% 201

1/20W

MF

10K

21

R1455

5% 201

1/20W

MF

10K

21

R1470

5%

1/20W

MF43201

NO STUFF

21

R1440

MF

1/20W

0201

5%

0

21

R1456

390

201

1/20W

MF

5%

CRW_SPRT

6

41 89

14 85

20 28

18

14 85

6

21

R1486

5% 201

1/20W

MF

10K

21

R1499

5% 201

1/20W

MF

10K

12

R1413

5% 201

1/20W

MF

10K

14 85

21

R1489

5% 201

1/20W

MF

10K

18

14 82 85

14 18

2

1

R1457

MF-LF 402

1/16W

1K

5%

BDW_SPRT

18 20 20

21

PCH GPIO/MISC/NCTF

SYNC_MASTER=CLEAN_X425

SYNC_DATE=10/31/2014

R1456

BDW_SPRT

1

117S0201

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

ISOLATE_CPU_MEM_L

SMC_WAKE_SCI_L

XDP_DD0_SSD_PCIE_SEL_L

WOL_EN

SMC_RUNTIME_SCI_L

FW_PME_L

TBT_CIO_PLUG_EVENT_L

PM_THRMTRIP_L_R

PCH_PROCPWRGD

PM_THRMTRIP_L

PCH_PECI

PCH_A20GATE

PCH_RCIN_L

PP1V05_S0

CPU_PECI

SD_SEL_PCIE_L_USB_H

JTAG_ISP_TDO

PP3V3_SUS

XDP_DD0_SSD_PCIE_SEL_L

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO JTAG_TBT_TMS_PCH

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK

JTAG_ISP_TDI

PCH_RCIN_L

PP3V3_S5

PP3V3_S0

SPIROM_USE_MLB

CPU_RESET_L

CPU_PWRGD

PCH_A20GATE

SMC_RUNTIME_SCI_L WOL_EN

TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

FW_PWR_EN_PCH

MLB_RAMCFG0

SPIROM_USE_MLB

JTAG_ISP_TDO JTAG_ISP_TDI

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

XDP_FC1_GPU_GOOD

DPMUX_UC_IRQ

FW_PME_L DPMUX_UC_IRQ

MLB_RAMCFG2

MLB_RAMCFG3

FW_PWR_EN_PCH

XDP_FC0_HDD_PWR_EN

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO

TBT_GO2SX_BIDIR

TBT_POC_RESET_L

XDP_DD1_MLB_RAMCFG1

PP3V3_S0

JTAG_TBT_TMS_PCH

14 OF 97

14 OF 119

<SCH_NUM>

41 42

91

14

14 91

10 15 17 18 41 62 67 84 86

14 20

11 12 13 15 17 50 64 66 67 84

14 18

14 85

14 20

14 18

18 20

14 20

14 91

12 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

14 50 86

14

14 40

14 85

14 40

14 85

20

14 85

14 82 85

20

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

VCCCLK

VCCIO

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCSUSHDA

DCPRTC

V_PROC_IO

VCC

VCC3_3

VCCASW

VCCCLK

VCCCLK3_3

VCCIO

VCCVRM

VSS

VCCRTC

DCPSST

VCCSPI

VCCUSBPLL

DCPSUS2

VCCSUS3_3

CLK/MISC

SPI CPU RTC HDA

USB

GPIO/LPC

(8 OF 11)

THERMAL

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCC3_3: 133mA Max, 3mA Idle

6uA Max (3.0V, room temperature)

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

15 mA Max, 1mA Idle

2

1

C1532

20% 10V

0.1UF

BYPASS=U1100.A6::6.35mm

402

CERM

2

1

C1531

10%

6.3V CERM

1UF

BYPASS=U1100.A6::6.35mm

402

2

1

C1533

20% 10V

402

0.1UF

BYPASS=U1100.A6::6.35mm

CERM

P43

BE22

BB44

AN11

AK28

AK26

AJ32

AJ30

AM20

AM18

AK22

AK20

AK18

AT22

AR22

AP22

AN35

AN34

AM22

V24

V22

V20

V18

U24

U22

U20

U18

AA18

Y22

Y20

Y18

M31

P45

AD28

AD26

AD24

AD22

AD20

AA26

R32

R30

AA24

Y26

AG24

AG22

AG20

AG18

AE26

AE24

AE22

AE20

AE18

U14

AJ28

AJ26

Y12

U1100

OMIT_TABLE

LYNXPOINT

MOBILE

CKPLUS_WAIVE=PwrTerm2Gnd

FCBGA

M24

AW40

AF34

U35

A26

U26

R28

R26

R24

R22

R20

K8

AD12

A6

Y30

V30

V28

U36U30

A16

AG32

AG30

AE32

AE30

AD36

AD35

V32

U32

M29

M26

L29

L26

AD34

AA32

AA30

Y32

R18

L17

AK32

AK30

AG14

AF12

AE14

L24

AP45

P20

P18

AJ14

AJ12

Y35

AA14

P16

P14

U1100

MOBILE

FCBGA

LYNXPOINT

OMIT_TABLE

2

1

C1550

402

CERM

PLACE_NEAR=R1550.1:2.54mm

1UF

6.3V

10%

21

R1550

PLACE_NEAR=U1100.U14:2.54mm

201

5.11

1/20W MF-LF

1%

2

1

C1590

0.1UF

20% 10V CERM 402

BYPASS=U1100.P14::6.35mm

2

1

C1580

10V

20% CERM

402

0.1UF

BYPASS=U1100.AA14::6.35mm

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PCH Power

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

PP3V3_SUS

PP1V05_S0

PP3V3_S5

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_CLK_F

PP1V5_S0

PP1V05_S0

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PPVRTC_G3H

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP1V05_S0

<SCH_NUM>

15 OF 119

15 OF 97

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 50 64 66 67

84

10 14 15 17 18 41 62 67 84

86

12 14 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

17

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 50 64 66 67 84

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67

84

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 14 15 17 50 64 66 67

84

11 12 19 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

VSS

(10 OF 11)

VSS VSS

VSS

(11 OF 11)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Y8

Y40

AM16

Y36

Y34

Y28

Y24

Y16

Y14

W44

W2

V43

V26

AM32

V16

V14

U6

U42

U38

U34

U28

U16

U10

T43

AM30

R8

R44

R38

R34

R2

R16

R14

R12

P32

P30

AM28

P28

P26

P24

P22

N6

N39

N35

N12

M22

M17

AM26

L44

L2

K39

B15

B11

AY7

AY29

AY26

AY20

AY15

AM24

AY10

F43

AW2

AV6

AV40

BB25

AV33

AV31

AV24

AV22

AM14

AV13

D42

AT38

AT36

AT29

AT26

AT20

AT17

AT15

AT10

AL8

AK16

AR2

AP43

AP31

AP24

AP13

AN8

AN42

AN40

AN36

AL38

AL34

U1100

FCBGA

LYNXPOINT

OMIT_TABLE

MOBILE

AB38

AB34

AB12

AA4

AA28

AA22

AA20

AA16

BC28

K33

K29

K20

K15

K10

H7

H40

H36

H31

H26

H24

H22

H17

H13

H10

G8

G44

G38

G2

D4

BC16

F33

F29

F20

F15

AV7

D25

BD7

BD39

BD35

BD31

AT43

AY36

BD19

BD15

BD11

BA40

B7

B39

B35

B31

B27

B23

B19

BB42

BC22

AL2

AL12

AK45

AK43

AK24

AK14

AJ8

AJ6

AJ38

AJ34

AJ24

AJ22

AJ20

AJ18

AJ16

AG44

AG28

AG26

AG2

AG16

AF8

AF38

AE28

AE16

AD8

AD6

AD40

AD32

AD30

AD18

AD16

AD14

AC44

AC2

AB8

U1100

FCBGA

OMIT_TABLE

MOBILE

LYNXPOINT

PCH Grounds

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

16 OF 97

16 OF 119

<SCH_NUM>

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

183mA Max, 68mA Idle

PCH VCCVRM BYPASS

(PCH 3.3V USB2 PWR)

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR)

PCH VCCSPI BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR)

PCH VCCCLK BYPASS (PCH 1.05V DIFFCLK135 PWR)

(PCH 3.3V FUSE PWR)

670mA Max, 34mA Idle

(PCH 3.3V/1.5V HDA PWR)

PCH VCCIO BYPASS

PCH VCCSUSHDA BYPASS

(PCH 1.5V VCCVRM PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V CLK PWR)

PCH VCCCLK3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCCIO BYPASS (PCH 1.05V FDI PWR)

PCH VCCUSBPLL BYPASS

(PCH 1.05V CORE PWR)

PCH VCC BYPASS

Not documented in EDS!

(PCH 1.05V USB2 PLL PWR)

(PCH 1.05V SSC PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH VCCCLK BYPASS (PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V CLK PLL PWR)

PCH CLK VCC BYPASS

(PCH 3.3V THERMAL PWR)

PCH VCCIO BYPASS (PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCASW BYPASS

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

PCH VCC BYPASS

PCH V_PROC_IO BYPASS (PCH 1.05V CPU I/F PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND USB PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

(PCH 3.3V SPI PWR)

(PCH 1.05V USB2 PWR)

(PCH 1.05V ME CORE PWR)

2

1

C1777

1.0UF

0402

X6S

BYPASS=U1100.AG30::6.35mm

6.3V

10%

2

1

C1778

1.0UF

0402

X6S

BYPASS=U1100.AD35::6.35mm

6.3V

10%

2

1

C1780

1.0UF

0402

X6S

BYPASS=U1100.AD34::6.35mm

6.3V

10%

2

1

C1782

1.0UF

0402

X6S

BYPASS=U1100.AA30::6.35mm

6.3V

10%

2

1

C1764

1.0UF

0402

X6S

BYPASS=U1100.AM18::6.35mm

6.3V

10%

2

1

C1752

1.0UF

0402

X6S

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

2

1

C1751

1.0UF

0402

X6S

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

2

1

C1750

PLACE_NEAR=U1100.V20:2.54mm

X5R-CERM-1

22UF

6.3V 603

20%

2

1

C1758

1.0UF

0402

X6S

BYPASS=U1100.AE18::6.35mm

6.3V

10%

2

1

C1763

1.0UF

0402

X6S

BYPASS=U1100.AK20::6.35mm

6.3V

10%

2

1

C1757

1.0UF

0402

X6S

BYPASS=U1100.AD20::6.35mm

6.3V

10%

2

1

C1755

BYPASS=U1100.AG18::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1756

1.0UF

0402

X6S

BYPASS=U1100.AA24::6.35mm

6.3V

10%

2

1

C1762

1.0UF

0402

X6S

BYPASS=U1100.AK22::6.35mm

6.3V

10%

2

1

C1761

1.0UF

0402

X6S

BYPASS=U1100.AK18::6.35mm

6.3V

10%

2

1

C1760

BYPASS=U1100.AK18::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1776

1.0UF

0402

X6S

BYPASS=U1100.AE30::6.35mm

6.3V

10%

2

1

C1770

1.0UF

0402

X6S

BYPASS=U1100.U35::6.35mm

6.3V

10%

2

1

C1772

1.0UF

0402

X6S

BYPASS=U1100.AN34::6.35mm

6.3V

10%

2

1

C1774

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.U30::6.35mm

10%

2

1

C1787

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AJ12::6.35mm

10%

2

1

C1785

1.0UF

0402

X6S

BYPASS=U1100.AJ12::12.7mm

6.3V

10%

2

1

C1786

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AJ12::6.35mm

10%

2

1

C1723

1.0UF

0402

X6S

BYPASS=U1100.U32::6.35mm

6.3V

10%

2

1

C1726

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.R30::6.35mm

10%

2

1

C1728

BYPASS=U1100.AE14::6.35mm

16V

X7R-CERM

0402

0.01UF

10%

2

1

C1730

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.L24::6.35mm

10%

2

1

C1732

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AK30::6.35mm

10%

2

1

C1734

1.0UF

0402

X6S

BYPASS=U1100.P18::6.35mm

6.3V

10%

2

1

C1791

BYPASS=U1100.AP45::6.35mm

10V X6S-CERM 0402

1UF

10%

2

1

C1790

BYPASS=U1100.AP45::12.7mm

NO STUFF

16V

X6S-CERM

0603

10UF

20%

21

L1790

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

21

R1790

1

1/16W

5%

MF-LF

402

2

1

C1740

BYPASS=U1100.AF34::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1722

1.0UF

0402

X6S

BYPASS=U1100.M29::6.35mm

6.3V

10%

2

1

C1721

1.0UF

0402

X6S

BYPASS=U1100.L29::6.35mm

6.3V

10%

2

1

C1720

1.0UF

0402

X6S

BYPASS=U1100.L26::6.35mm

6.3V

10%

2

1

C1700

0.1UF

25V

X7R-CERM

0402

BYPASS=U1100.A16::6.35mm

10%

2

1

C1704

0402

X7R-CERM

25V

BYPASS=U1100.R20::6.35mm

0.1UF

10%

2

1

C1702

1.0UF

0402

X6S

BYPASS=U1100.AD12::6.35mm

6.3V

10%

2

1

C1708

1.0UF

0402

X6S

BYPASS=U1100.K8::6.35mm

6.3V

10%

2

1

C1706

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.R26::6.35mm

10%

2

1

C1710

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.A26::6.35mm

10%

2

1

C1775

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1765

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1759

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1753

25V

0201

5%

CRITICAL

NP0-C0G

12PF

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1113S0022

PCH DECOUPLING

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

PP1V05_S0

PP3V3_SUS

PP3V3_S0

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

PP1V5_S0

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

PP3V3_SUS

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V5_S0

PP1V05_S0

PP3V3_SUS

PP3V3_S5

PP3V3_S0

PP1V5_S0

<SCH_NUM>

17 OF 119

17 OF 97

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

15

11 12 13 15 17 19 52 64 67 81 84 86

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67 84

12 14 15 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 15 17 19 52 64 67 81 84 86

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

OUT

IN

BI

TP

IN

OUT

NCNC

Y

NC NC

VCC

GND

A

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT

NC NC

BI

IN

IN IN

IN

TP

IN

IN IN

OUT

BI IN

OUT

IN

OUT

IN

OUT

G

VER 5

SD

G

VER 5

SD

G

VER 5

SD

G

VER 5

SD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OBSDATA_A3

OBSDATA_B0 OBSDATA_B1

OBSDATA_B3

Unused PCH/XDP Signals

signal destination (to minimize stub).

Merged (CPU/PCH) Micro2-XDP

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

OBSFN_D0

OBSDATA_C2

OBSFN_C1

TCK0

TDI and TMS are terminated in CPU.

PCH/XDP Signals

(All 10 R’s)

Non-XDP Signals

PCH/XDP Signal Isolation Notes: ’Output’ non-XDP signals require pulls.

signal path needs to split between route

’Output’ PCH/XDP signals require pulls.

OBSFN_B1

OBSFN_B0

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

VCC_OBS_AB

Extra BPM Testpoints

CPU JTAG Isolation

SDA

TCK1

SCL

HOOK2

HOOK1

HOOK3

OBSDATA_B2

PWRGD/HOOK0

518S0847

TDO TRSTn TDI TMS

VCC_OBS_CD RESET#/HOOK6

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

OBSDATA_D2

OBSFN_A0 OBSFN_A1

OBSFN_C0

OBSDATA_C1

OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSFN_D1

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

from PCH to J1850 and path to non-XDP

R187x and R189x should be placed where

20

11 85

21

R1897

201

SHORT

OMIT

NONE NONENONE

21

R1896

201

SHORT

NONE NONENONE

OMIT

21

R1872

201

NONE

OMIT

NONE NONE

SHORT

13

21

R1875

201

NONE

SHORT

NONE NONE

OMIT

11 18

11

11 18

21

R1890

NONE

201

OMIT

SHORT

NONENONE

13 37

13 81 86

13

14 20

21

R1893

201

SHORT

NONENONE NONE

OMIT

13 20 13

81 86

21

R1894

201

NONE NONE NONE

SHORT

OMIT

13

21

R1879

201

SHORT

OMIT

NONE NONE NONE

11

11 18

14

11 18

11 33

13 66 13

14 18 14 18

21

R1895

201

SHORT

NONENONENONE

OMIT

14 34

13

14

1

TP1810

TP-P6

1

TP1811

TP-P6

1

TP1812

TP-P6

1

TP1813

TP-P6

6

18 86 89

6

18 86 89

6

86 89

12

R1861

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U1100.AE2:28mm

12

R1860

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AD3:28mm

12

R1862

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AD1:28mm

12

R1866

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AB3:28mm

6

86 89

2

1

R1845

5%

201

1/20W MF

330K

4

6

5

1

3

2

U1845

74LVC1G07GF

SOT891

2

1

C1845

16V

0201

X5R-CERM

0.1UF

10%

19 40 58 67 86

21

R1820

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.M49:28mm

12

R1823

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.N54:28mm

6

89

6

89

6

89

6

89

6

89

6

89

6

89

6

89

6

89

2

1

R1830

5%

150

402

MF-LF

1/16W

12 20 21 86

11 18 86

21

R1805

5% 201

1/20W

MF

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

6

89

6

89

6

89

6

19 89

2

1

C1806

CERM-X5R

0.1UF

10%

6.3V 0201

XDP

2

1

C1801

XDP

6.3V CERM-X5R 0201

0.1UF

10%

9

8 7

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J1800

CRITICAL XDP_CONN

DF40RC-60DP-0.4V

M-ST-SM1

2

1

C1800

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

6

86 89

6

86 89

6

89

6

89

6

89

6

86 89

6

89

6

89

6

89

1

TP1802

TP-P6

1

TP1803

TP-P6

1

TP1804

TP-P6

1

TP1805

TP-P6

1

TP1806

TP-P6

1

TP1807

TP-P6

6

89

6

89

6

89

6

89

6

89

6

89

2

1

C1804

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

R1831

5%

1K

XDP

MF-LF 402

1/16W

6

89

6

89

6

89

8

13 43 81 85 86 91

11 18 86

21

R1800

5% 201

1/20W

MF

PLACE_NEAR=U0500.F50:2.54mm

1K

XDP

21

R1802

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

21

R1804

5%

0

XDP

402

MF-LF1/16W

6

14 89

12 40 91

12 19 40 86 91

6

18 86 89

12

R1824

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.M53:28mm

21

R1876

201

OMIT

NONENONENONE

SHORT

14 18 20 14 18 20

1

2

6

Q1840

CRITICAL

DMN5L06VK-7

SOT563

PLACE_NEAR=J1800.53:28mm

XDP

4

5

3

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.51:28mm

SOT563

XDP

CRITICAL

4

5

3

Q1842

CRITICAL

XDP

SOT563

DMN5L06VK-7

PLACE_NEAR=J1800.55:28mm

1

2

6

Q1842

XDP

PLACE_NEAR=J1800.57:28mm

SOT563

CRITICAL

DMN5L06VK-7

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

CPU & PCH XDP

XDP_DD1_MLB_RAMCFG1

SD_PWR_EN

SSD_PWR_EN CAMERA_PWR_EN_PCH

SDCONN_STATE_CHANGE_L

XDP_DC1_SATARDRVR_EN

XDP_DD2_ENETSD_CLKREQ_L

XDP_PCH_TDI

XDP_CPU_TDI

XDP_CPU_TMS

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_CPU_PRESENT_L

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

XDP_SYS_PWROK

SMBUS_PCH_DATA

XDP_CPU_TCK

PP5V_S0

CPU_PWRGD

PP1V05_S0

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

ALL_SYS_PWRGD

CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<19>

CPU_PWR_DEBUG

PLT_RESET_L

CPU_CFG<14> CPU_CFG<15>

XDP_DBRESET_L

CPU_CFG<1>

XDP_CPU_PREQ_L

CPU_CFG<0>

XDP_BPM_L<1>

XDP_BPM_L<0>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

CPU_CFG<3>

XDP_BPM_L<2>

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

XDP_CPU_TCK

AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_DA1_USB_EXTC_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_FC1_GPU_GOOD

SMBUS_PCH_CLK

XDP_CPU_PRDY_L

USB_EXTA_OC_L

USB_EXTB_OC_L

DP_AUXCH_ISOL_L

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK SSD_PCIE_SEL_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_CAMERA_PWR_EN

XDP_DA2_SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_L XDP_DB2_SD_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DC1_SATARDRVR_EN

MAKE_BASE=TRUE

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

MAKE_BASE=TRUE

XDP_DD0_SSD_PCIE_SEL_L

XDP_DD3_AP_CLKREQ_L

XDP_DD1_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_DD2_ENETSD_CLKREQ_L

MAKE_BASE=TRUE

XDP_DC0_DP_AUXCH_ISOL_L

PP1V05_SUS

XDP_PCH_TDI

XDP_CPURST_L

PPVCCIO_S0_CPU

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<11>

PP3V3_S5

XDP_PCH_TCK

PP1V05_S0

XDP_PCH_TDO

XDP_JTAG_CPU_ISOL_L

XDP_TRST_L

XDP_PCH_TMS

18 OF 119

<SCH_NUM>

18 OF 97

6

18 86 89

19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

10 14 15 17 18 41 62 67 84 86

6

18 86 89

6

18 86 89

11 18 86

6

18 86 89

64 84

11 18 86

5 6 8

10 58

12 14 15 17 19 21 31 32 33 61 64 66 67 82 84 85 86

96

10 14 15 17 18 41 62 67 84 86

IN

OUT

IN

OUT

NC NC

IN

OUT

OUT OUT

OUT

IN

Y

A

B

08

Y

A

B

08

IN

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

VER 3

D

SG

G

VER 5

SD

NC

YA

B

NC

GND

VCC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

WF: Do we need this?

VCCST (1.05V S0) PWRGD

PCH ME Disable Strap

PCH PWROK Generation

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

SMC controls strap enable to allow in-field control of strap setting.

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

SB XTAL Power Camera XTAL Power

GreenClk 25MHz Power

Coin-Cell: VBAT (300-ohm & 10uF RC)

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

VDDIO_25M_B: Camera power rail for XTAL circuit.

available ~3.3V power

create VDD_RTC_OUT. +V3.3A should be first

internally ORed to

VBAT and +V3.3A are

to reduce VBAT draw.

For SB RTC Power

No Coin-Cell: 3.42V G3Hot (no RC)

least 5ms after all rails are valid.

NOTE: ALL_SYS_PWRGD must remain low until at

NOTE: 30 PPM crystal required

IPD = 9-50k

TBT XTAL Power

VDDIO_25M_A: SB power rail for XTAL circuit.

PCH Reset Button

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH 33MHz Clocks

System RTC Power Source & 32kHz / 25MHz Clock Generator

No bypass necessary

NOTE: SLG3NB148A provides slow rising edge on 25MHZ_B when powered from

1.2V VDDIO. Falcon Ridge also complicates VDD_25M power, forcing at least S4. Both issues to be addressed in upcoming part (SLG3NB148C).

6

18 89

21

R1996

5%

0

MF-LF

1/16W

402

XDP

21

R1955

5%

201

22

MF

PLACE_NEAR=U1100.D44:6.35mm

1/20W

11 91 40 91

11 91

21

R1959

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.A40:6.35mm

11 91

2

1

R1997

0

5%

OMIT

1/16W MF-LF 402

SILK_PART=SYS RESET

2

1

R1995

1K

MF-LF 402

1/16W

5%

12 40 86 91

11 90

28 90

2

1

C1910

1UF

6.3V

10% CERM

402

2

1

C1902

X5R

10% 10V

402-1

1UF

2

1

C1920

0.1UF

20%

CERM

402

10V

2

1

C1922

20% 10V

CERM

402

0.1UF

2

1

R1906

5%

NO STUFF

1M

MF-LF

1/16W 402

2

1

C1924

20%

402

CERM

10V

0.1UF

21

R1905

5%

0

402

MF-LF

1/16W

2 1

C1905

12PF

C0G

50V

0402

5%

21

C1906

C0G

50V

12PF

0402

5%

40 41

2

1

R1921

5%

201

1/20W MF

1K

2

1

R1920

5%

201

1/20W MF

100K

11 91

36 90

1

2

R1948

NO STUFF

0201

0

5% 1/20W MF

12 19 86 91

21

R1949

MF-LF

5%

402

1/16W

1K

12 18 40 86 91 58

18 40 58 67 86

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

PLACE_NEAR=U1100.AD7:7MM

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

7

8

4

2

1

U1950

74LVC2G08GT/S505

SOT833

2

1

R1950

5%

402

MF-LF

2.0K

1/16W

2

1

C1950

0.1UF

CERM

BYPASS=U1950::5MM

402

10V

20%

29 30 40 41

2

1

R1947

5%

0

0201

1/20W

MF

3 4

1

14

6

11

13

5

17216107

12

15

8

9

U1900

SLG3NB148CV

TQFN

CRITICAL

31

42

Y1905

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

CRITICAL

1

2

6

Q1920

SOT563

DMN5L06VK-7

4

5

3

Q1920

SOT563

DMN5L06VK-7

4

6

5

3

1

2

U1930

BDW_SPRT

74AUP1G09

CRITICAL

SOT891

2

1

C1930

BDW_SPRT

0201

X5R-CERM

16V

10%

0.1UF

2

1

R1930

BDW_SPRT

MF

1/20W 201

5%

10K

8

Chipset Support

SYNC_DATE=10/31/2014

SYNC_MASTER=CLEAN_X425

PP3V3_TBTLC

LPC_CLK33M_SMC

PP3V42_G3H

SYS_PWROK_R

PM_PCH_SYS_PWROK

SMC_DELAYED_PWRGD

PM_PCH_PWROK

PM_S0_PGOOD

CPUVR_PGOOD

PP3V3_S0

PP5V_S0

HDA_SDOUT_R

PM_SYSRST_L

XDP_DBRESET_L

LPC_CLK33M_SMC_R

ALL_SYS_PWRGD

PP3V3_S0

SYSCLK_CLK32K_RTC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

PP1V5_S0

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2

PCH_CLK33M_PCIOUT

PCH_CLK33M_PCIIN

PP3V3_S5

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_LS5V

CPU_VCCST_PWRGD

PP1V05_S0_CPU_VCCST

PM_PCH_PWROK

PP3V3_S5

MAKE_BASE=TRUE

PM_PCH_PWROK

<SCH_NUM>

19 OF 119

19 OF 97

20 28 29 84

19 34 37 38 40 41 42 43 50 56 57 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

18 36 49 58 59 62 63 66 67 73 79 80 84 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51

52 55 66 67 68 69 82 83 84

86 96

11 12 15 84

11 12 13 15 17 19 52 64 67 81 84 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

35

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84

85 86 96

11 12 13 15 17 19 52 64 67 81 84 86

8

10

12 19 86 91

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

GND

1Y

VCC

1A

3Y 3A

2A 2Y

Y

B

A

IN

G

VER 5

SD

G

VER 5

SD

OUT

IN

OUT

IN

OUT

IN

OUT

IN

G

SYM_VER_1

D

S

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Buffered

Unbuffered

Platform Reset Connections

AP PCIE D2R test points

PCH 33MHz Clock for DPMUX

GS3 Connector Support

Flexible I/O Configuration Strap

Camera power-up sequencing Support

DEVSLP not supported on LPT-H

Must pull signal correctly even if always USB or PCIe

(Pull-ups on PCH page)

To/From PCH

To/From RR

U2060 supports I/O’s powered when VCC=0V

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

Falcon Ridge Support

RR output is open-drain, no isolation necessary

Pull-up values TBD

Falcon Ridge JTAG Isolation

GPIO Glitch Prevention

From RIO Connector

HDMI HPD pull-down

Camera PCIE D2R test points

LCD HPD Inverter

(Pull-Up on CPU Page)

To/From PCH

TBT_PWR_EN must be high for JTAG Programming

RAM Configuration Straps

RIO SD Card Reader Support

SD Card Reader is always USB3 in this implementaton.

Flexible I/O Aliases

18

14

14 18

14

2

1

R2002

201

MF

1/20W

5%

1K

RAMCFG0:L

2

1

R2011

201

RAMCFG1:L

1K

5% MF

1/20W

2

1

R2012

201

RAMCFG2:L

MF

1/20W

5%

1K

2

1

R2013

201

1/20W MF

5%

1K

RAMCFG3:L

2

1

R2070

MF

1/20W

201

5%

10K

34

2

1

R2040

470K

5%

1/20W

MF

201

20 28 13

12 40

2

1

R2075

10K

5% MF

201

1/20W

14 20 28 14 20 28

14

2

1

R2030

5% MF

100K

201

1/20W

13 20 81 86 91

13 20 81 86 91 13 20 81 86 91

13 20 81 86 91

14

28

2

1

R2063

10K

5% 1/20W MF 201

28

2

1

R2062

MF

1/20W

5%

201

10K

2

1

R2061

1/20W

10K

5% MF

201

81 86

2

1

C2060

X5R-CERM

0201

16V

0.1UF

10%

2

1

R2010

MF

1/20W

5%

100K

201

81 82 86

2

5

7

8

4

6

3

1

U2060

SN74AUP3G07DQER

X2SON

CRITICAL

4

5

3

1

2

U2030

CRITICAL

SOT665

TC7SZ08FEAPE

2

1

C2080

0.1UF

CERM

10V

20%

402

28

4

5

3

Q2040

SOT563

DMN5L06VK-7

1

2

6

Q2040

DMN5L06VK-7

SOT563

82

21

R2057

PLACE_NEAR=U1100.B42:6.35MM

201

5%

MF

22

1/20W

11 20

21

R2072

402

5%

MF-LF

1/16W

0

82

13 18

2

1

C2054

10% 10V

0201

X5R-CERM

0.1UF

PLACE_NEAR=U2050.1:3mm

2

1

R2052

5%

1/20W

10K

MF

201

PLACE_NEAR=U2050.1:3mm

5

4

1

2

3

U2050

MC74VHC1G08

CRITICAL

SC70-HF

21

R2050

NOSTUFF

0

5% MF

1/20W

0201

2

1

C2050

0201

X5R-CERM

0.1UF

10V

10%

BYPASS=U2050::3mm

21

R2051

33

5%

MF

1/20W

201

35

2

1

R2080

MF-LF 402

5% 1/16W

100K

13 36 91

2

1

R2020

MF

1/20W

84.5

1%

NOSTUFF

201

PLACE_NEAR=U1100.AT33:1mm

13 33 91

2

1

R2021

MF

84.5

1%

NOSTUFF

201

1/20W

PLACE_NEAR=U1100.AW33:1mm

5

4

1

2

3

U2080

CRITICAL

MC74VHC1G08

SC70-HF

21

R2091

402

5%

0

MF-LF

1/16W

21

R2087

0

1/16W MF-LF

5%

402

21

R2088

MF-LF

1/16W

0

5%

402

21

R2085

5%

402

1/16W MF-LF

0

2

1

C2030

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

R2041

201

470K

5% 1/20W MF

12 18 21 86

21

R2083

402

33

1/16W MF-LF

5%

35

28

33

34

40

82

2

1

3

Q2010

DMN32D2LFB4

DFN1006H4-3

5

14 18

20 28

3

7

8

4

6

2 5

1

U2000

74LVC2G08GT/S505

CRITICAL

SOT833

2

1

C2013

10%

0.1UF

X5R-CERM 0201

16V

28

28 40 41 42

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=01/14/2013

Project Chipset Support

PP3V3_S3RS0_CAMERA

PP3V3_S4

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

CAMERA_PWR_EN_RC

USB3_SD_D2R_N

USB3_SD_R2D_C_P

CAMERA_PWR_EN_R

CAMERA_PWR_EN

CAMERA_PWR_EN_PCH

USB3_SD_D2R_P

PP3V3_S3

SSD_DEVSLP

MLB_RAMCFG2

SDCONN_STATE_CHANGE_L

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

PP3V3_S0

LPC_PWRDWN_L

TBT_PWR_EN_PCH

JTAG_TBT_TCK

TBT_PWR_EN

MLB_RAMCFG0

XDP_DD1_MLB_RAMCFG1

MLB_RAMCFG3

MAKE_BASE=TRUE

USB3_SD_D2R_N

USB3_SD_D2R_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

DP_INT_IG_HPD

DP_IG_A_HPD_L

PP3V3_S0

PP3V3_S4

JTAG_ISP_TCK

TBT_PWR_EN

SMC_PME_S4_DARK_L

SMC_PME_SDCONN

HDMI_HPD

RIO_SDCONN_STATE_CHANGE_L

SD_SEL_PCIE_L_USB_H

PP3V3_S0

PP3V3_TBTLC

JTAG_TBT_TMS

PP3V3_S0

MAKE_BASE=TRUE

TBT_CIO_PLUG_EVENT_L TBT_CIO_PLUG_EVENT_L

JTAG_TBT_TDO

JTAG_TBT_TDIJTAG_ISP_TDI

JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

LPC_CLK33M_DPMUX_UC_R

PCIE_AP_D2R_P

PCIE_AP_D2R_N

LPC_CLK33M_DPMUX_UC_R

MAKE_BASE=TRUE

LPC_CLK33M_DPMUX_UC

PLT_RESET_L

MAKE_BASE=TRUE

SMC_LRESET_L

SSD_RESET_L

AP_RESET_L

TBT_PCIE_RESET_L

DPMUX_LRESET_L

CAM_PCIE_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

<SCH_NUM>

20 OF 119

20 OF 97

13 35 46 84

20 33 38 41 42 45 46 65 66 67 81 84 85 86

13 21 43 45 46 66 81 82 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51

52 55 66 67 68 69 82 83 84

86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

20 33 38 41 42 45 46 65 66 67 81 84 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

19 28 29 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83

84 86 96

11 20

69

IN IN

IN

OUT

IN

G

D

S

OUT

VER 3

D

SG

VER 3

D

SG

G

VER 5

SD

G

VER 5

S D

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1 3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

75mA max load @ 0.75V

S0

to

S3

to

60mW max power

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

S0

MEMVTT Clamp

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MEM S0 "PGOOD" for CPU

14 12 40 67 86

12 18 20 86

2

1

R2102

MF-LF

5%

CPUMEM:S0

100K

1/16W

402

21 60 85

2

1

R2110

CPUMEM:S0

5% 1/16W MF-LF

10K

402

2

1

R2115

CPUMEM:S0

402

MF-LF

1/16W

5%

100K

23 24 25 26

2

1

R2116

1K

MF-LF 402

1/16W

5%

CPUMEM:S0

66

2

1

R2105

402

MF-LF

5%

CPUMEM:S0

1/16W

10K

12 33 37 40 67 81 86

2

1

R2101

100K

402

1/16W MF-LF

CPUMEM:S0

5%

21 60 85

2

1

R2151

MF-LF

1/16W

100K

402

5%

CPUMEM:S0

2

1

C2151

402

CERM

20% 50V

NO STUFF

0.001UF

2

1

R2150

1/10W

603

MF-LF

5%

10

CPUMEM:S0

21

R2117

CPUMEM:S3

1/16W

5%

0

402

MF-LF

6

21

2

1

R2121

MF-LF

1%

1/16W

43.2K

402

2

1

R2120

402

27.4K

1/16W MF-LF

1%

4

3

5

Q2120

CRITICAL

DMB53D0UV

SOT-563

2

1

R2122

402

1/16W MF-LF

10K

5%

1

2

6

Q2120

DMB53D0UV

SOT-563

CRITICAL

6

12 89

2

1

C2120

0402

X5R-CERM

10%

0.047UF

10V

2

1

C2116

20%

402

CERM

10V

0.1UF

CPUMEM:S0

2

1

C2117

NO STUFF

10%

X5R

6.3V

201

0.047UF

1

2

6

Q2100

CRITICAL

SOT563

DMN5L06VK-7

CPUMEM:S0

1

2

6

Q2110

CRITICAL CPUMEM:S0

SOT563

DMN5L06VK-7

1

2

6

Q2115

SOT563

DMN5L06VK-7

CRITICAL

CPUMEM:S0

4

5

3

Q2115

SOT563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

4

5

3

Q2100

CPUMEM:S0

SOT563

DMN5L06VK-7

CRITICAL

4

5

3

Q2110

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT563

1

2

6

Q2105

SOT563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

4

5

3

Q2105

CPUMEM:S0

CRITICAL

SOT563

DMN5L06VK-7

1

2

6

Q2150

CRITICAL

SOT563

DMN5L06VK-7

CPUMEM:S0

4

5

3

Q2150

CRITICAL

CPUMEM:S0

DMN5L06VK-7

SOT563

SYNC_DATE=07/02/2014

SYNC_MASTER=CLEAN_MAXWELL

CPU Memory S3 Support

PP3V3_S3

MEMPWR_DIV

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PP3V3_S5

CPU_MEM_RESET_L

PPVTT_S0_DDR

PP5V_S3

MEM_RESET_L

CPU_MEM_RESET_L

MAKE_BASE=TRUE

MEMRESET_ISOL_LS5V_L

PLT_RESET_L

MEMVTT_EN

MEMVTT_EN_L

CPUVDDQ_EN

CPUVDDQ_EN_L

PM_SLP_S3_L

PM_SLP_S4_L

PP5V_S3

MEMVTT_EN

VTTCLAMP_L

VTTCLAMP_EN

ISOLATE_CPU_MEM_L

PP1V35_S3

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

21 OF 119

21 OF 97

13 20 43 45 46 66 81 82 84 86

12 14 15 17 18 19 31 32 33 61 64 66 67 82 84 85 86 96

27 60 84 86

21 36 60 66 67 84 86

22

21 36 60 66 67 84 86

45 60 66 84 86

6 8

10 66 67 84 96

IN

G

VER 5

S D

G

VER 5

S D

G

VER 5

S D

G

VER 5

S D

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Always used, regardless

VRef Dividers

CPU-Based Margining

Connected to 4 DRAMs.

NOTE: CPU has single output for VREFCA.

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

of margining option.

2

1

R2221

1/20W

1% MF

201

1K

2

1

R2241

1% 1/20W

201

MF

1K

2

1

R2222

1/20W

1%

201

MF

PLACE_NEAR=R2221.2:1mm

1K

21

R2220

MF

1%

1/20W

24.9

201

2

1

R2261

1/20W 201

MF

1%

1K

2

1

R2242

1/20W

1%

201

MF

PLACE_NEAR=R2241.2:1mm

1K

21

R2240

MF

1%

1/20W

24.9

201

2

1

R2262

PLACE_NEAR=R2261.2:1mm

1%

1/20W

201

MF

1K

21

R2260

24.9

MF

201

1%

1/20W

21

R2223

0201

1% MF

1/20W

2

1

C2220

X5R-CERM 0201

0.022UF

10%

6.3V

21

R2243

0201

MF

1%

2

1/20W

2

1

C2240

X5R-CERM

10%

0.022UF

6.3V 0201

21

R2263

1/20W

1% MF

2

0201

2

1

C2260

0201

10%

6.3V X5R-CERM

0.022UF

7

89

7

89

7

1

2

6

Q2220

SOT563

DMN5L06VK-7

CRITICAL

4

5

3

Q2220

DMN5L06VK-7

CRITICAL

SOT563

1

2

6

Q2260

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2260

DMN5L06VK-7

SOT563

CRITICAL

21

SYNC_DATE=08/11/2014

DDR3 VREF MARGINING

SYNC_MASTER=CLEAN_X425

MEMRESET_ISOL_LS5V_L

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFDQ_A_ISOL

MEM_VREFDQ_B_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_MEM_VREFDQ_B_ISOL

CPU_DIMMA_VREFDQ

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_MEM_VREFCA_ISOL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MEM_VREFCA_RC

MEM_VREFDQ_A_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

22 OF 97

22 OF 119

<SCH_NUM>

23 24 25 26 85 89 92

23 24 85 89 92

23 24 25 26 27 45 84 92

25 26 85 89

NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2

1

C2340

20% 10V

402

2.2UF

X5R-CERM

2

1

C2341

20% 10V

402

2.2UF

X5R-CERM

2

1

C2343

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2344

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2345

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2353

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2354

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2355

0201

CERM-X5R

6.3V

10%

0.1UF

2

1

C2363

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2364

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2365

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2373

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2374

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2375

6.3V CERM-X5R 0201

0.1UF

10%

1

2

R2300

MF

1/20W

1%

240

201

1

2

R2310

MF

240

1% 1/20W

201

1

2

R2320

MF

1/20W

1%

240

201

1

2

R2330

1%

240

1/20W MF 201

2

1

C2307

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2309

0.047UF

6.3V X5R 201

10%

2

1

C2308

0.047UF

6.3V X5R 201

10%

2

1

C2319

0.047UF

6.3V X5R 201

10%

2

1

C2318

0.047UF

6.3V X5R 201

10%

2

1

C2317

0.47UF

20%

4V

CERM-X5R-1

201

2

1

C2329

0.047UF

6.3V X5R 201

10%

2

1

C2328

0.047UF

6.3V X5R 201

10%

2

1

C2327

CERM-X5R-1

20%

4V

0.47UF

201

2

1

C2339

0.047UF

6.3V X5R 201

10%

2

1

C2338

0.047UF

6.3V X5R 201

10%

2

1

C2337

20%

4V

CERM-X5R-1

0.47UF

201

2

1

C2379

0.047UF

6.3V X5R 201

10%

2

1

C2378

0.047UF

6.3V X5R 201

10%

2

1

C2377

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2369

0.047UF

6.3V X5R 201

10%

2

1

C2368

0.047UF

6.3V X5R 201

10%

2

1

C2367

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2359

0.047UF

6.3V X5R 201

10%

2

1

C2358

0.047UF

6.3V X5R 201

10%

1

2

R2370

MF

1/20W

1%

240

201

1

2

R2360

240

1% 1/20W MF 201

2

1

C2357

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2349

0.047UF

6.3V X5R 201

10%

2

1

C2348

0.047UF

6.3V X5R 201

10%

2

1

C2347

CERM-X5R-1

4V

20%

0.47UF

201

1

2

R2350

MF

1/20W

1%

240

201

1

2

R2340

240

1% 1/20W MF 201

2

1

C2335

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2334

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2333

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2325

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2324

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2323

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2315

6.3V

0.1UF

10%

0201

CERM-X5R

2

1

C2314

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2313

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2305

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2304

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2303

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2301

20% 10V

402

2.2UF

X5R-CERM

2

1

C2300

402

10V

20%

2.2UF

X5R-CERM

2

1

C2311

X5R-CERM

2.2UF

402

10V

20%

2

1

C2351

X5R-CERM

2.2UF

402

10V

20%

2

1

C2310

2.2UF

20% 10V

402

X5R-CERM

2

1

C2350

X5R-CERM

2.2UF

402

10V

20%

2

1

C2321

X5R-CERM

2.2UF

402

10V

20%

2

1

C2361

2.2UF

X5R-CERM

402

10V

20%

2

1

C2320

X5R-CERM

2.2UF

20% 10V

402

2

1

C2360

20%

X5R-CERM

2.2UF

402

10V

2

1

C2331

X5R-CERM

2.2UF

402

10V

20%

2

1

C2330

X5R-CERM

2.2UF

20% 10V

402

2

1

C2371

2.2UF

X5R-CERM

402

10V

20%

2

1

C2370

2.2UF

10V

20%

402

X5R-CERM

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2300

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2310

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2320

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2330

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2340

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2350

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2360

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2370

OMIT_TABLE

DDR3-1333

FBGA

DDR3 SDRAM Bank A (1 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

MEM_A_ZQ<5>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA

MEM_A_DQ<6>

MEM_A_A<11>

MEM_A_DQS_N<5>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<50> MEM_A_DQ<51>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<7>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<62>

MEM_A_DQS_N<7>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<6>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<6>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<54>

MEM_A_DQS_N<6>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<46>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<5>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_A<2>

MEM_A_DQ<32>

MEM_A_CAS_L

MEM_A_DQ<37>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<4>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<38>

MEM_A_DQS_N<4>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<4>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<3>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CS_L<0>

MEM_A_DQS_P<3>

MEM_A_DQ<29>

MEM_A_DQ<25>

MEM_A_DQ<30>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_A<2>

MEM_A_A<3>

PP1V35_S3_MEM

MEM_A_A<2>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<2>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<20>

MEM_A_DQS_N<2>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<2>

MEM_A_DQ<19>

MEM_A_DQ<23>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQ<14>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_DQ<9>

MEM_A_A<0>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<1>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

PP0V75_S3_MEM_VREFCA

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<1>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_A<2>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_DQS_N<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<2>

MEM_A_DQ<0>

MEM_A_DQ<5> MEM_A_DQ<3> MEM_A_DQ<1>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_DQ<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3> MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<8> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<0>

MEM_A_RAS_L

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

<SCH_NUM>

23 OF 119

23 OF 97

22 23 24 85 89 92

22 23 24 25 26 85 89 92

22 23 24 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

22 23 24 85 89 92

22 23 24 25 26 85 89 92

7

24 92

7

23

24 27

92

7

23

24 27

92

7

24 92

22 23 24 25 26 85 89 92

22 23 24 85 89 92

7

24 92

7

24 92

22 23 24 85 89 92

7

23 27

92

7

23 27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 92

7

24 92

7

23 27

92

7

23 27

92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

23 24 27 92

7

23 24 27 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7 24 92

7

23 24 27 92

7

23 24

27 92

7

23 27 92

7

23

27

92

7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 27

92

22 23 24 85 89 92

7

23 27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 92

7

24 92

7

23 27

92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23 24

27 92

22 23 24 85 89 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7 23 27

92

7

23 24 27

92

7

23 24 27 92

7

24 92

22 23 24 85 89 92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 24

27 92

7

23 24

27 92

7 23 27

92

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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8 7 6 5 4 3

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2440

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2450

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2460

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2470

OMIT_TABLE

FBGA

DDR3-1333

1

2

R2400

240

1% MF

1/20W 201

1

2

R2410

MF

1/20W

1%

240

201

1

2

R2420

1% MF

240

1/20W 201

1

2

R2430

MF

1/20W

1%

240

201

2

1

C2407

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2409

0.047UF

6.3V X5R 201

10%

2

1

C2408

0.047UF

6.3V X5R 201

10%

2

1

C2419

0.047UF

6.3V X5R 201

10%

2

1

C2418

0.047UF

6.3V X5R 201

10%

2

1

C2417

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2429

0.047UF

6.3V X5R 201

10%

2

1

C2428

0.047UF

6.3V X5R 201

10%

2

1

C2427

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2439

0.047UF

6.3V X5R 201

10%

2

1

C2438

0.047UF

6.3V X5R 201

10%

2

1

C2437

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2479

0.047UF

6.3V X5R 201

10%

2

1

C2478

0.047UF

6.3V X5R 201

10%

2

1

C2477

20%

4V

CERM-X5R-1

0.47UF

201

2

1

C2469

0.047UF

6.3V X5R 201

10%

2

1

C2468

0.047UF

6.3V X5R 201

10%

2

1

C2467

CERM-X5R-1

0.47UF

20%

4V

201

2

1

C2459

0.047UF

6.3V X5R 201

10%

2

1

C2458

0.047UF

6.3V X5R 201

10%

1

2

R2470

240

1% 1/20W MF 201

1

2

R2460

MF

1/20W

1%

240

201

2

1

C2457

20%

4V

0.47UF

CERM-X5R-1

201

2

1

C2449

0.047UF

6.3V X5R 201

10%

2

1

C2448

0.047UF

6.3V X5R 201

10%

2

1

C2447

20%

4V

CERM-X5R-1

0.47UF

201

1

2

R2450

240

1% 1/20W MF 201

1

2

R2440

MF

1/20W

1%

240

201

2

1

C2440

20%

402

2.2UF

X5R-CERM

10V

2

1

C2400

402

10V

20%

2.2UF

X5R-CERM

2

1

C2441

20% 10V

402

2.2UF

X5R-CERM

2

1

C2401

20% 10V

402

2.2UF

X5R-CERM

2

1

C2450

2.2UF

402

10V

20%

X5R-CERM

2

1

C2410

X5R-CERM

2.2UF

20% 10V

402

2

1

C2451

X5R-CERM

402

10V

20%

2.2UF

2

1

C2411

X5R-CERM

2.2UF

402

10V

20%

2

1

C2460

X5R-CERM

2.2UF

402

10V

20%

2

1

C2461

X5R-CERM

2.2UF

402

10V

20%

2

1

C2420

X5R-CERM

2.2UF

20% 10V

402

2

1

C2421

X5R-CERM

2.2UF

402

10V

20%

2

1

C2470

2.2UF

X5R-CERM

402

10V

20%

2

1

C2471

X5R-CERM

2.2UF

402

10V

20%

2

1

C2430

X5R-CERM

2.2UF

20% 10V

402

2

1

C2431

X5R-CERM

2.2UF

402

10V

20%

2

1

C2443

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2444

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2403

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2404

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2445

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2453

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2405

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2413

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2454

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2414

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2455

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2463

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2415

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2423

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2464

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2465

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2424

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2425

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2473

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2433

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2474

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2434

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2475

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2435

6.3V CERM-X5R 0201

0.1UF

10%

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2400

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2410

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2420

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2430

FBGA

DDR3-1333

OMIT_TABLE

DDR3 SDRAM Bank A (2 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MEM_A_A<10>

MEM_A_A<14>

PP0V75_S3_MEM_VREFCA

MEM_A_A<5>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<15>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<15>

MEM_A_DQ<61>

MEM_A_DQS_N<7>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_A<2>

MEM_A_DQ<43>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_DQS_N<5>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<14>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<6>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<53>

MEM_A_DQS_N<6>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_A<2>

MEM_A_CLK_N<1>

MEM_A_DQS_N<4>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_ODT<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<45>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<5>

MEM_A_DQ<44>

MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<12>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<4>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<11>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<25>

MEM_A_DQS_N<3>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<3>

MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_A<2>MEM_A_A<2>

MEM_A_A<6>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18> MEM_A_DQS_P<2>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4> MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_A_A<1>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<10>

MEM_A_RAS_L

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA

MEM_A_DQ<13>

PP1V35_S3_MEM

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_A<15>

MEM_A_DQS_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L

MEM_A_ZQ<9>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQS_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<9>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_A<15>

MEM_A_A<13>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<8>

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQ<1>

MEM_A_CKE<1>

MEM_A_DQS_P<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<41>

MEM_A_A<4>

MEM_A_A<1>

MEM_A_A<8> MEM_A_A<7>

MEM_A_DQ<46>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_ZQ<13>

PP1V35_S3_MEM

<SCH_NUM>

24 OF 119

24 OF 97

7

23 24

27 92

7

23 24 27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

22 23 24 85 89 92

7

24 27

92

7

24 27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27 92

7

23

24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 92

7

23 92

7

24 27

92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 24 27 92

7

23 92

7

23

24 27

92

7

23 24

27 92

7

23 24

27 92

7 23 92

7

24 27 92

7

24

27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

24 27 92

7

24 27 92

7

24

27

92

7

23 24 27 92

7

23 24

27 92

21 23 24

25 26

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 92

7

23 24 27 92

22 23 24 85 89 92

7 24 27 92

7

23 24

27 92

7

23 24

27 92

7

24 27

92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

24 27

92

7 23 92

7

23 92

7

23 24

27 92

7

23 24

27 92

7

23 24 27 92

7

24 27

92

22 23 24 85 89 92

7

24 27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 92

7

23 92

7

24 27

92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

7

23 24 27 92

7

23

24 27

92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27 92

7

23

24 27

92

22 23 24 25 26 27 45 84 92

22 23 24 25 26 85 89 92

7

23 24 27

92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23

24 27 92

7 24 27

92

22 23 24 85 89 92 22 23 24 85 89 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

24 27

92

7

24 27

92

7

23 24 27 92

7

23 92

7

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23

92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

7

23 24

27 92

22 23 24 85 89 92

7 24 27

92

7

23 24

27 92

7

24 27

92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7 23 92

7

23 24

27 92

22 23 24 85 89 92 22 23 24 85 89 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2550

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2560

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2570

OMIT_TABLE

FBGA

DDR3-1333

1

2

R2500

240

1% 1/20W MF 201

1

2

R2510

MF

1/20W

1%

240

201

1

2

R2520

1%

240

1/20W MF 201

1

2

R2530

1/20W

1%

240

MF 201

2

1

C2507

0.47UF

4V

20%

CERM-X5R-1

201

2

1

C2509

0.047UF

6.3V X5R 201

10%

2

1

C2508

0.047UF

6.3V X5R 201

10%

2

1

C2519

0.047UF

6.3V X5R 201

10%

2

1

C2518

0.047UF

6.3V X5R 201

10%

2

1

C2517

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2529

0.047UF

6.3V X5R 201

10%

2

1

C2528

0.047UF

6.3V X5R 201

10%

2

1

C2527

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2539

0.047UF

6.3V X5R 201

10%

2

1

C2538

0.047UF

6.3V X5R 201

10%

2

1

C2537

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2579

0.047UF

6.3V X5R 201

10%

2

1

C2578

0.047UF

6.3V X5R 201

10%

2

1

C2577

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2569

0.047UF

6.3V X5R 201

10%

2

1

C2568

0.047UF

6.3V X5R 201

10%

2

1

C2567

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2559

0.047UF

6.3V X5R 201

10%

2

1

C2558

0.047UF

6.3V X5R 201

10%

1

2

R2570

MF

1/20W

1%

240

201

1

2

R2560

1% 1/20W

240

MF 201

2

1

C2557

0.47UF

4V

20%

CERM-X5R-1

201

2

1

C2549

0.047UF

6.3V X5R 201

10%

2

1

C2548

0.047UF

6.3V X5R 201

10%

2

1

C2547

20%

4V

0.47UF

CERM-X5R-1

201

1

2

R2550

MF

1/20W

1%

240

201

1

2

R2540

240

1% 1/20W MF 201

2

1

C2540

20% 10V

402

2.2UF

X5R-CERM

2

1

C2500

402

10V

20%

X5R-CERM

2.2UF

2

1

C2541

20% 10V

402

2.2UF

X5R-CERM

2

1

C2550

X5R-CERM

2.2UF

402

10V

20%

2

1

C2501

20% 10V

402

2.2UF

X5R-CERM

2

1

C2510

X5R-CERM

2.2UF

20% 10V

402

2

1

C2551

X5R-CERM

2.2UF

402

10V

20%

2

1

C2511

X5R-CERM

2.2UF

402

10V

20%

2

1

C2560

X5R-CERM

2.2UF

402

10V

20%

2

1

C2561

X5R-CERM

2.2UF

402

10V

20%

2

1

C2520

X5R-CERM

2.2UF

20% 10V

402

2

1

C2521

X5R-CERM

2.2UF

402

10V

20%

2

1

C2570

X5R-CERM

2.2UF

402

10V

20%

2

1

C2571

2.2UF

X5R-CERM

402

10V

20%

2

1

C2530

2.2UF

10V

X5R-CERM

20%

402

2

1

C2531

X5R-CERM

2.2UF

402

10V

20%

2

1

C2543

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2544

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2503

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2504

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2545

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2553

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2505

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2513

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2554

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2514

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2555

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2563

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2515

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2523

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2564

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2565

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2524

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2525

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2573

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2533

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2534

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2574

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2575

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2535

6.3V CERM-X5R 0201

0.1UF

10%

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2500

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2510

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2520

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2530

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2540

OMIT_TABLE

FBGA

DDR3-1333

DDR3 SDRAM Bank B (1 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<54>

MEM_B_DQS_N<6>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

PP0V75_S3_MEM_VREFCA

MEM_B_A<5>

MEM_B_DQ<32>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<38>

MEM_B_DQS_N<4>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<22>

MEM_B_DQS_N<2>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<2>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_A<2>

MEM_B_DQ<11>

MEM_B_DQ<3>

MEM_B_A<12>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<1>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_A<2>

PP1V35_S3_MEM

MEM_B_DQ<2> MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<6>

MEM_B_A<2>

PP1V35_S3_MEM

<SCH_NUM>

25 OF 119

25 OF 97

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

22 25 26 85 89

7

25 27

92

7

25 27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

21 23 24 25 26

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

26 92

7

25 27

92

7

25 27

92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

25 26 27 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

22 23 24 25 26 85 89 92

7

25 26

27 92

7

26 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25 26

27 92

7

25 26

27 92

7

25 27

92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 27 45 84 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 27

92

7

25 27 92

7

25 27 92

7

25 26 27 92

7

26 92

22 25 26 85 89

7

25 27

92

7

25 27

92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

21 23 24 25 26

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

26 92

7

25 27

92

7

25 27

92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 25 26 85 89

7

25

26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

25

26 27

92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25 26

27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

22 23 24 25 26 27 45 84 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25 26

27 92

7

25 27

92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 85 89 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 27 45 84 92

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2650

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2660

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2670

FBGA

DDR3-1333

OMIT_TABLE

1

2

R2600

201

MF

1%

240

1/20W

1

2

R2610

201

240

1% 1/20W MF

1

2

R2620

201

MF

1/20W

1%

240

1

2

R2630

201

240

1% 1/20W MF

2

1

C2607

201

CERM-X5R-1

20%

4V

0.47UF

2

1

C2609

10%

201

X5R

6.3V

0.047UF

2

1

C2608

10%

201

X5R

6.3V

0.047UF

2

1

C2619

10%

201

X5R

6.3V

0.047UF

2

1

C2618

10%

201

X5R

6.3V

0.047UF

2

1

C2617

201

CERM-X5R-1

20%

4V

0.47UF

2

1

C2629

10%

201

X5R

6.3V

0.047UF

2

1

C2628

10%

201

X5R

6.3V

0.047UF

2

1

C2627

201

0.47UF

20%

4V

CERM-X5R-1

2

1

C2639

10%

201

X5R

6.3V

0.047UF

2

1

C2638

10%

201

X5R

6.3V

0.047UF

2

1

C2637

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2679

10%

201

X5R

6.3V

0.047UF

2

1

C2678

10%

201

X5R

6.3V

0.047UF

2

1

C2677

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2669

10%

201

X5R

6.3V

0.047UF

2

1

C2668

10%

201

X5R

6.3V

0.047UF

2

1

C2667

201

0.47UF

20%

CERM-X5R-1

4V

2

1

C2659

10%

201

X5R

6.3V

0.047UF

2

1

C2658

10%

201

X5R

6.3V

0.047UF

1

2

R2670

201

240

1% 1/20W MF

1

2

R2660

201

MF

1/20W

1%

240

2

1

C2657

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2649

10%

201

X5R

6.3V

0.047UF

2

1

C2648

10%

201

X5R

6.3V

0.047UF

2

1

C2647

201

0.47UF

20%

4V

CERM-X5R-1

1

2

R2650

201

240

1% 1/20W MF

1

2

R2640

201

MF

1/20W

1%

240

2

1

C2640

20% 10V

402

2.2UF

X5R-CERM

2

1

C2600

10V

20%

2.2UF

X5R-CERM

402

2

1

C2641

20% 10V

402

2.2UF

X5R-CERM

2

1

C2650

X5R-CERM

2.2UF

402

10V

20%

2

1

C2601

20% 10V

402

2.2UF

X5R-CERM

2

1

C2610

X5R-CERM

2.2UF

20% 10V

402

2

1

C2651

X5R-CERM

2.2UF

402

10V

20%

2

1

C2611

X5R-CERM

2.2UF

402

10V

20%

2

1

C2660

X5R-CERM

2.2UF

402

10V

20%

2

1

C2661

X5R-CERM

2.2UF

402

10V

20%

2

1

C2620

X5R-CERM

2.2UF

20% 10V

402

2

1

C2621

X5R-CERM

2.2UF

402

10V

20%

2

1

C2670

X5R-CERM

2.2UF

402

10V

20%

2

1

C2671

X5R-CERM

2.2UF

402

10V

20%

2

1

C2630

2.2UF

10V

X5R-CERM

20%

402

2

1

C2631

X5R-CERM

2.2UF

402

10V

20%

2

1

C2643

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2644

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2603

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2604

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2645

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2653

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2605

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2613

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2654

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2614

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2655

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2663

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2615

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2623

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2664

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2665

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2624

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2625

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2673

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2633

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2634

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2674

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2675

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2635

10%

0.1UF

0201

CERM-X5R

6.3V

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2600

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2610

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2620

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2630

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2640

DDR3-1333

FBGA

OMIT_TABLE

DDR3 SDRAM Bank B (2 OF 2)

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

PP1V35_S3_MEM

MEM_B_A<2>

MEM_B_DQ<1>

MEM_B_DQ<5>

MEM_B_DQ<0> MEM_B_DQ<7>

MEM_B_DQS_P<0>

MEM_B_CKE<1>

MEM_B_DQS_N<0>

MEM_B_DQ<4>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<0>

PP1V35_S3_MEM

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_ZQ<8>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_A<11>

MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<11> MEM_B_DQ<8> MEM_B_DQ<15>

MEM_B_DQ<10> MEM_B_DQS_P<1>

MEM_B_CS_L<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

PP0V75_S3_MEM_VREFCA

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<9>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<9>

MEM_B_DQ<12>

MEM_B_DQS_N<1>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<20> MEM_B_DQ<18> MEM_B_DQ<16>

MEM_B_DQ<17> MEM_B_DQ<22>

MEM_B_DQ<23> MEM_B_DQS_P<2>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<2>

MEM_B_DQ<21>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<6> MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<10>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

PP1V35_S3_MEM

MEM_B_DQ<19>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_DQ<25> MEM_B_DQ<27> MEM_B_DQ<29> MEM_B_DQ<26> MEM_B_DQ<24> MEM_B_DQ<31>

MEM_B_DQ<30> MEM_B_DQS_P<3>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<11>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_WE_L

MEM_B_A<2>

MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<38>

MEM_B_DQ<36> MEM_B_DQS_P<4>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<4>

MEM_B_DQ<37>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<8> MEM_B_A<7> MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<12>

MEM_B_RAS_L

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_P<1>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<2>

MEM_B_DQ<40> MEM_B_DQ<43> MEM_B_DQ<42>

MEM_B_DQ<46>

MEM_B_DQ<44> MEM_B_DQS_P<5>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8> MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<13>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

PP1V35_S3_MEM

MEM_B_DQ<41>

MEM_B_A<5>

MEM_RESET_L

MEM_B_DQ<49> MEM_B_DQ<48>

MEM_B_DQ<50> MEM_B_DQ<55> MEM_B_DQ<54>

MEM_B_DQ<52> MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<53>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<14>

MEM_B_RAS_L

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_DQ<47>

MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<63> MEM_B_DQ<62>

MEM_B_DQ<60> MEM_B_DQS_P<7>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<7>

MEM_B_DQ<61>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<15>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<3>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_BA<2>

MEM_B_DQ<51>

PP1V35_S3_MEM

MEM_B_DQ<2>

PP0V75_S3_MEM_VREFCA

<SCH_NUM>

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IN

IN IN

IN

IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FOR DESENSE IMPROVEMENT

C2701,C2721 FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

Place Source Cterm at neckdown at first DRAM

MEM Clock Termination

Place RC end termination after last DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

PLACE ONE AT EACH DDR3L MEMORY MODULE.

7

25 26 92

81

RP2730

1/32W

4X0201

5%

36

81

RP2703

5%361/32W

4X0201

81

RP2702

1/32W

4X0201

5%

36

72

RP2701

4X0201

1/32W

36

5%

54

RP2701

4X0201

1/32W

5%

36

72

RP2702

4X0201

1/32W

36

5%

72

RP2706

1/32W

4X0201

36

5%

2

1

C2704

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2702

CERM-X5R-1

20% 4V

0.47UF

201

2

1

C2700

CERM-X5R-1

0.47UF

20% 4V

201

2

1

C2723

20% 4V CERM-X5R-1

0.47UF

201

72

RP2728

5%

4X0201

1/32W

36

2

1

C2727

20% 4V

0.47UF

CERM-X5R-1 201

2

1

C2725

20% 4V CERM-X5R-1

0.47UF

201

2

1

C2707

20% CERM-X5R-1

0.47UF

4V 201

2

1

C2703

201

20%

0.47UF

CERM-X5R-1

4V

2

1

C2705

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2765

PLACE_NEAR=U2600.F8:3.2mm

25V

3.3PF

C0G

0201

+/-0.25PF

21

R2766

30

1/20W

MF

5%

201

2

1

C2755

PLACE_NEAR=U2470.F8:3.2mm

C0G

0201

25V

+/-0.25PF

3.3PF

72

RP2730

1/32W

36

4X0201

5%

21

R2765

30

1/20W

MF

5%

201

21

R2756

5% MF

1/20W

30

201

21

R2755

5%

30

MF

201

1/20W

21

C2766

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2756

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2751

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2761

6.3V

CERM-X5R

0201

0.1UF

10%

21

R2750

30

1/20W

MF

5%

201

72

RP2724

36

4X0201

1/32W

5%

21

R2751

5% MF

1/20W

30

201

2

1

C2750

PLACE_NEAR=U2370.F8:3.2mm

25V

3.3PF

C0G

0201

+/-0.25PF

21

R2760

30

MF

1/20W

5%

201

21

R2761

30

MF

5%

201

1/20W

2

1

C2760

25V

3.3PF

C0G

0201

+/-0.25PF

PLACE_NEAR=U2500.F8:3.2mm

7

23 92

7

23 92

7

25 92

7

25 92

7

24 92

2

1

C2730

20% 4V CERM-X5R-1

0.47UF

201

7

24 92

7

26 92

7

26 92

81

RP2705

4X0201

1/32W

5%

36

7

24 92

72

RP2705

4X0201

5%361/32W

7

23 24 92

72

RP2725

36

4X0201

1/32W

5%

7

25 26 92

63

RP2725

1/32W

5%

4X0201

36

2

1

C2728

0.47UF

CERM-X5R-1

4V

20%

201

7

25 26 92

81

RP2725

5%

1/32W

4X0201

36

7

25 26 92

63

RP2705

4X0201

36

5%

1/32W

7

23 24 92

54

RP2705

36

5%

1/32W

4X0201

7

23 24 92

54

RP2725

4X0201

36

5%

1/32W

7

25 26 92

2

1

C2726

20% 4V CERM-X5R-1

0.47UF

201

2

1

C2701

12PF

25V

5% 0201

NP0-C0G

2

1

C2721

5% NP0-C0G 0201 25V

12PF

2

1

C2770

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2740

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2771

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2741

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2772

5%

12PF

NP0-C0G

25V

CRITICAL

0201

2

1

C2742

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2773

5%

CRITICAL

25V

12PF

NP0-C0G

0201

2

1

C2743

5%

12PF

0201

NP0-C0G

25V

CRITICAL

81

RP2720

5%

1/32W

4X0201

36

2

1

C2774

5%

12PF

25V

CRITICAL

NP0-C0G

0201

2

1

C2775

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2744

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2745

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2776

5%

0201

NP0-C0G

25V

CRITICAL

12PF

2

1

C2777

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2746

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2747

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

26 92

7

25 26 92

7

25 26 92

7

25 26 92

2

1

C2787

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2797

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2796

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2786

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2785

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2795

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

25 92

2

1

C2784

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2794

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2783

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2793

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2782

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2792

5%

12PF

NP0-C0G

25V

CRITICAL

0201

2

1

C2781

5%

12PF

0201

CRITICAL

25V

NP0-C0G

2

1

C2791

5%

0201

NP0-C0G

25V

CRITICAL

12PF

2

1

C2790

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2780

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

25 92

7

25 26 92

7

25 26 92

7

25 26 92

7

26 92

7

26 92

7

25 26 92

7

25 26 92

7

25 26 92

7

25 92

7

25 26 92

7

25 26 92

7

25 26 92

7

25 26 92

7

23 24 92

7

23 24 92

7

23 92

7

23 92

7

23 24 92

7

25 26 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

54

RP2724

1/32W

4X0201

5%

36

54

RP2730

4X0201

5%361/32W

63

RP2720

1/32W

36

4X0201

5%

72

RP2720

4X0201

1/32W

36

5%

72

RP2722

36

1/32W

4X0201

5%

7

25 26 92

54

RP2722

4X0201

1/32W

36

5%

63

RP2726

5%361/32W

4X0201

63

RP2728

4X0201

1/32W

36

5%

54

RP2728

5%361/32W

4X0201

72

RP2726

36

5%

1/32W

4X0201

63

RP2724

1/32W

4X0201

36

5%

63

RP2722

36

5%

4X0201

1/32W

54

RP2720

5%361/32W

4X0201

81

RP2728

36

5%

1/32W

4X0201

81

RP2724

4X0201

5%

1/32W

36

7

25 26 92

81

RP2722

5%

36

4X0201

1/32W

54

RP2726

36

4X0201

1/32W

5%

2

1

C2724

20% 4V

0.47UF

CERM-X5R-1 201

2

1

C2722

CERM-X5R-1

0.47UF

4V

20%

201

2

1

C2720

CERM-X5R-1

0.47UF

20% 4V

201

63

RP2706

5%

1/32W

4X0201

36

81

RP2701

5%

1/32W

36

4X0201

63

RP2701

4X0201

1/32W

5%

36

54

RP2704

1/32W

5%

36

4X0201

72

RP2704

1/32W

5%

4X0201

36

7

25 26 92

54

RP2707

4X0201

1/32W

5%

36

54

RP2702

36

5%

4X0201

1/32W

63

RP2703

1/32W

4X0201

5%

36

81

RP2707

1/32W

5%

36

4X0201

2

1

C2710

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2708

20%

0.47UF

CERM-X5R-1

4V 201

2

1

C2706

0.47UF

CERM-X5R-1

4V

20%

201

72

RP2707

4X0201

5%

1/32W

36

7

23 24 92

7

23 24 92

63

RP2730

1/32W

4X0201

5%

36

7

23 24 92

7

24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 92

7

23 24 92

7

23 24 92

7

23 24 92

81

RP2726

4X0201

1/32W

36

5%

7

24 92

7

23 24 92

54

RP2703

36

1/32W

5%

4X0201

81

RP2704

4X0201

36

1/32W

5%

54

RP2706

36

1/32W

5%

4X0201

63

RP2702

4X0201

5%

1/32W

36

63

RP2704

4X0201

1/32W

5%

36

72

RP2703

5%

1/32W

4X0201

36

63

RP2707

4X0201

1/32W

5%

36

81

RP2706

4X0201

36

1/32W

5%

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

DDR3 Termination

PP1V35_S3_MEM

PPVTT_S0_DDR

MEM_A_BA<2>

PP1V35_S3_MEM

MEM_B_CLK0_TERM_R

MEM_A_CLK1_TERM_R

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK0_TERM_R

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2> MEM_A_A<1>

MEM_A_A<11> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<12>

MEM_A_CS_L<1> MEM_A_A<15>

MEM_A_ODT<1> MEM_A_A<10>

MEM_A_RAS_L MEM_A_CKE<0>

MEM_A_A<4>

MEM_A_A<5> MEM_A_BA<1>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_BA<0>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_BA<1> MEM_B_A<0>

MEM_B_CKE<1> MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_A<15>

MEM_B_A<9> MEM_B_A<14>

MEM_B_A<7> MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_A_CAS_L MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_B_A<12>

MEM_B_CS_L<1>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_WE_L

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_RAS_L MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_A<10>

MEM_A_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CLK1_TERM_R

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_CLK_P<1>

MEM_B_BA<2>

MEM_A_ODT<0>

PPVTT_S0_DDR

MEM_A_A<3>

MEM_A_A<6>

<SCH_NUM>

27 OF 119

27 OF 97

22 23 24 25 26 27 45 84 92

21 27 60 84 86

22 23 24 25 26 27 45 84 92

21 27 60 84 86

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

IN

IN IN

IN

OUT

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1 PETN_1

PETP_2

RSENSE

PETN_2

PETP_3 PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1 PERN_1

PERP_2 PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK TDO TEST_EN TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI TMS

PERN_0

PERP_3

IN IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(TBT_SPI_CLK) (TBT_SPI_CS_L)

(TBT_SPI_MISO)

SNK0 AC Coupling

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

SNK1 AC Coupling

(TBT_SPI_MOSI)

Used for straps in host mode

depends on the code in the flash.

Security strap setting is XORed with

If strap != bit then security is enabled?

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15 9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14 11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

DEBUG: For monitoring current/voltage

bit in the flash, so the active-level

2

1

R2890

MF

1/20W

201

3.3K

5%

82

2

1

R2825

100

5% MF

1/20W 201

31

31 93

31 87 93

31 93

31 87 93

32 93

32

32 93

2

1

R2830

MF

201

100K

5%

1/20W

2

1

R2831

MF

1/20W

201

100K

5%

31 93

2

1

R2893

201

MF

5%

3.3K

1/20W

21

C2829

0201

0.1UF

X5R-CERM

16V10%

83 89 97

76 89 97

21

C2828

0201

0.1UF

X5R-CERM

10% 16V

21

C2827

0201

0.1UF

X5R-CERM

16V10%

21

C2826

0201

0.1UF

X5R-CERM

10% 16V

21

C2825

0201

0.1UF

X5R-CERM

16V10%

21

C2824

0201

X5R-CERM

0.1UF

10% 16V

21

C2823

0201

0.1UF

X5R-CERM

16V10%

21

C2822

0201

0.1UF

X5R-CERM

10% 16V

2

1

R2855

1%

1K

201

1/20W MF

21

C2821

0201

0.1UF

X5R-CERM

16V10%

21

C2820

0201

0.1UF

X5R-CERM

16V10%

21

C2830

0201

0.1UF

X5R-CERM

16V10%

21

C2831

0201

0.1UF

X5R-CERM

16V10%

21

C2832

0201

0.1UF

X5R-CERM

16V10%

21

C2833

0201

0.1UF

X5R-CERM

16V10%

21

C2834

0201

X5R-CERM

0.1UF

16V10%

21

C2835

0201

0.1UF

X5R-CERM

16V10%

21

C2836

0201

0.1UF

X5R-CERM

16V10%

21

C2837

0201

0.1UF

X5R-CERM

16V10%

21

C2838

0201

0.1UF

X5R-CERM

16V10%

21

C2839

0201

X5R-CERM

0.1UF

16V10%

76 89 97

2

1

C2890

BYPASS=U2890::2mm

1UF

10%

6.3V CERM

402

83 89 97

31

32

20

32 93

32

20

31 93

31

28 30 31

31

28 31

28 30 32

32

28 32

28 29

20 40 41 42

11

19 90

21

R2895

201

MF

1/20W

1%

806

2

1

R2896

1/20W MF 201

1K

5%

2

1

R2899

MF

5%

1/20W

10K

201

NO STUFF

11 91

29

2

1

R2815

NOSTUFF

NONE NONE 0201

NONE

OMIT

2

1

R2888

5%

10K

201

1/20W

MF

2

1

R2887

10K

201

MF

1/20W

5%

2

1

R2886

NO STUFF

5%

201

1/20W MF

10K

2

1

R2885

NO STUFF

5%

10K

201

1/20W

MF

2

1

R2880

100K

MF

1/20W

201

5%

20

28 82

14 20

2

1

R2883

5%

201

1/20W MF

100K

3

8

9

7

4

25

1

6

U2890

4MBIT

USON

W25X40CLXIG

OMIT_TABLE

CRITICAL

28 30

28 31 32

2

1

R2861

5%

10K

201

1/20W MF

2

1

R2863

MF

1/20W 201

10K

5%

2

1

R2867

MF

1/20W 201

10K

5%

NO STUFF

2

1

R2862

MF

1/20W 201

10K

5%

2

1

R2881

MF

1/20W

201

5%

100K

2

1

R2829

10K

201

1/20W

MF

5%

2

1

R2884

100K

MF

1/20W

201

5%

2

1

R2882

MF

1/20W 201

5%

100K

28 85

2

1

R2878

100K

MF

1/20W

201

5%

2

1

R2879

5%

201

1/20W MF

100K

2

1

R2832

5%

201

1/20W

MF

100K

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

L8

AD1

U20

AB21 AD21

W20

R4

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5 P7

N6

A22 B23

A20 B21

M1

D3

W24 U24

W22 U22

R24 N24

R22 N22

K3 K1

N8 J6

M3

A18 B19

A16 B17

K5

P1

L24 J24

L22 J22

G24 E24

G22 E22

L4 L2

W18 W16

AC24

AD23

M7

V7

T7

Y1

Y7

H5

L6

U2

F1

V1

AD3

AB3

W6

T3

T1

F3P3

R2N2

R8

Y3

AA2

T5 U8

AC2

J4 J2

A14 B15

A12 B13

A10 B11

A8 B9

U4

H3 H1

E6 D5

E8 D7

E10

D9

E12 D11

AB5

G4 G2

E14 D13

E16 D15

E18 D17

E20 D19

U2800

CRITICAL

OMIT_TABLE

FCBGA

FALCON RIDGE

31 82 32 82

21

C2801

X5R-CERM

10%

16V

0201

0.1UF

21

C2800

16V

0201

10%

0.1UF

X5R-CERM

21

C2802

0.1UF

0201

10%

16V X5R-CERM

21

C2803

0.1UF

0201

10%

16V X5R-CERM

2

1

R2892

201

5% MF

1/20W

3.3K

21

C2804

0.1UF

10%

X5R-CERM

0201

16V

21

C2805

0201

10%

16V X5R-CERM

0.1UF

21

C2806

0201

10%

16V X5R-CERM

0.1UF

21

C2807

0201

10%

16V X5R-CERM

0.1UF

21

C2840

16V

X5R-CERM

0.1UF

0201

10%

21

C2841

16V10%

X5R-CERM

0.1UF

0201

21

C2842

16V10%

X5R-CERM

0.1UF

0201

2

1

R2891

MF

1/20W 201

3.3K

5%

21

C2843

16V10%

X5R-CERM

0.1UF

0201

21

C2845

16V10%

X5R-CERM

0.1UF

0201

21

C2844

16V10%

0.1UF

X5R-CERM

0201

21

C2846

10% 16V

0.1UF

X5R-CERM

0201

21

C2847

10% 16V

0.1UF

0201

X5R-CERM

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

SYNC_DATE=01/14/2013

SYNC_MASTER=T29_RR

Thunderbolt Host (1 of 2)

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_N<0>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

PP3V3_TBTLC

DP_TBTSRC_HPD

PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

PP3V3_S4_TBT

TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L TBTROM_HOLD_L

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_C_P<3>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<3>

DP_TBTSNK0_ML_C_P<0>

PP3V3_TBTLC

SYSCLK_CLK25M_TBT

TBT_A_HV_EN

TBT_B_DP_PWRDN

PP3V3_TBTLC

PCIE_TBT_R2D_P<3>

JTAG_TBT_TMS

JTAG_TBT_TDI

TBT_PCIE_RESET_L

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

TBT_A_R2D_C_P<0>

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

JTAG_TBT_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP TBT_MONOBSN

TBT_THERMDP

TBT_SPI_MOSI

TP_TBT_MONDC0 TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

DP_TBTPB_AUXCH_C_P

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_P<1>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

TBTDP_AUXIO_EN TBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RC

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_BATLOW_L

TBT_GPIO7

HDMITBTMUX_SEL_TBT

SMC_PME_S4_DARK_L

TBT_PWR_EN

NC_DP_TBTSRC_ML_CP<0>

NC_DP_TBTSRC_ML_CP<1>

NC_DP_TBTSRC_ML_CP<3>

NC_DP_TBTSRC_ML_CP<2>

DP_TBTSRC_HPD

TBT_GPIO2

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT_R

TBT_DFT_STRAP_1 TBT_ROM_SECURITY_XOR TBT_DFT_STRAP_3

TP_TBT_PCIE_RESET0_L

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_RBIAS

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0>

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_ML_CN<1>

NC_DP_TBTSRC_ML_CN<2>

NC_DP_TBTSRC_ML_CN<3>

TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<1>

TBT_B_R2D_C_N<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_R2D_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_B_CONFIG1_BUF

TBT_B_D2R_P<0>

28 OF 97

28 OF 119

<SCH_NUM>

19 20 28 29 84

28

28 29 30 45 84

28 29

28 85

28 82

28 31 32

28 29 30 45 84

28 30

28 30 32

28 31

28 89 97

19 20 28 29 84

28 30 31

28 32

19 20 28 29 84

87

89

28 89 97

93

48 96

93

87 89

87

89

87 89

87

89

87

89

87

28

90

87

89

87

89

87

89

87

89

87

89

87 89

28 89 97

87

28 89 97

87 89

NC

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

S G

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VER 3

D

S G

G

VER 5

S D

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Isolated to reduce noise from SVR

Pull-up (S0) on PCH page

SVR input to FR - 1100 mA EDP

EDP: 1.25 A

2.4 W (Single-Port)

3.1 W (Dual-Port)

700 mA EDP

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

TBT "POC" Power-up Reset

Delay = 4.04ms nominal

1200 mA EDP

8 mOhm Typ

@ 1.05V

R(on)

Type

Part

Push-pull output

U2950

Max Current = 4A (85C)

11.5 mOhm Max

100 mA EDP

J45 Implementation: 4 X 10uF

25 mA EDP

1900 mA EDP

Load Switch

TPS22920

1.05V TBT "CIO" Switch

Internal switch not functional on FR.

X425 Implementation: 3 X 20uF

POC input to FR - 150 mA EDP

2

1

C2906

6.3V X5R

1.0UF

20%

0201-1

2

1

C2911

6.3V

1.0UF

20%

0201-1

X5R

2

1

C2910

0201-1

1.0UF

20%

6.3V X5R

21

L2920

680NH-30%-3.6A-35MOHM

CRITICAL

SM

2

1

C2922

0402-2

X5R-CERM

4V

20%

20UF

K

A

D2920

CRITICAL

SOD-323

NSR1020MW2T1G

2

1

R2945

MF 201

100K

5% 1/20W

C1

B1

A1

C2

B2

A2

D2

D1

U2940

CRITICAL

CSP

TPS22920

2

1

C2940

0201-1

X5R

20%

6.3V

1.0UF

2

1

C2981

0201-1

6.3V X5R

1.0UF

20%

2

1

C2980

0201-1

6.3V X5R

1.0UF

20%

2

1

C2970

20% X5R

0201-1

6.3V

1.0UF

28

2

1

C2960

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2961

0201-1

6.3V X5R

1.0UF

20%

2

1

C2953

CERM-X5R

0402-1

10UF

20%

6.3V

2

1

C2952

CERM-X5R

20%

10UF

0402-1

6.3V

2

1

C2951

20%

10UF

CERM-X5R

6.3V

0402-1

2

1

C2950

10UF

20%

0402-1

CERM-X5R

6.3V

2

1

XW2960

PLACE_NEAR=C2953.1:1mm

SM

28

2

1

C2995

X7R

16V

0201

10%

330PF

2

1

R2991

24.9K

1%

201

MF

1/20W

2

1

C2990

402

0.1UF

10% X5R

25V

14

2

1

R2995

1/20W

100K

201

MF

5%

19 30 40 41

2

1

R2990

201

MF

1/20W

100K

5%

2

1

3

Q2995

DMN32D2LFB4

DFN1006H4-3

2

1

C2991

0402

0.001UF

50V

10%

X7R-CERM

12

6

4

3

2

1

5

U2990

CRITICAL

USON

TPS3895ADRY

2

1

R2992

5% MF

201

100K

1/20W

1

2

6

Q2945

DMN5L06VK-7

SOT563

4

5

3

Q2945

SOT563

DMN5L06VK-7

2

1

C2923

4V

0402-2

X5R-CERM

20%

20UF

NOSTUFF

Y9

AC12

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V9

V23

V21

AC10

V13

U16

U12

T9

T23

T21

T17

T13

R20

R16

AB17

R12

P9

P23

P21

P13

N20

N16

N12

M9

M23

AB11

M21

M13

L20

L12

K23

K21

K13

J20

J16

J14AA8

H23

H21

G8

G6

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C2

C18

C16

C14

C12

C10

AA14

B7

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

A24

A2

W10

R18

N18

L18

H7

H17

H15

H13

Y5

W4

V5

N4

H11

E2

D1

K17

K15

J18

H9

H19

G18

G16

W14

G14

W12

V17

V15

U18

T19

P19

M19

L16

K7

K19

G12

G10

R10

P15

P11

N14

N10

M11

L10

K11

V11

U14

U10

T15

T11

R14

J12

J10

V19

P17

M17

M15

L14

K9

J8

B3

A6

A4

B5

U2800

CRITICAL

FALCON RIDGE

OMIT_TABLE

FCBGA

2

1

C2907

12PF

5% 0201

CRITICAL

25V

NP0-C0G

2

1

C2908

25V 0201

NP0-C0G

+/-0.1PF

3.0PF

CRITICAL

2

1

C2913

CRITICAL

3.0PF

+/-0.1PF NP0-C0G

0201

25V

2

1

C2912

CRITICAL

NP0-C0G 25V

12PF

0201

5%

2

1

C2934

3.0PF

+/-0.1PF 25V

0201

CRITICAL

NP0-C0G

2

1

C2933

5% 0201

CRITICAL

12PF

25V

NP0-C0G

2

1

C2954

CRITICAL

NP0-C0G 25V

12PF

0201

5%

2

1

C2955

3.0PF

+/-0.1PF

0201

NP0-C0G

CRITICAL

25V

2

1

C2903

6.3V

1.0UF

0201-1

20% X5R

2

1

C2920

20%

4V

X5R-CERM

0402-2

20UF

2

1

C2921

X5R-CERM

20UF

0402-2

4V

20%

2

1

C2904

0201-1

1.0UF

X5R

6.3V

20%

2

1

C2905

0201-1

6.3V X5R

1.0UF

20%

2

1

C2900

X5R

0201-1

6.3V

1.0UF

20%

2

1

C2901

0201-1

6.3V

20% X5R

1.0UF

2

1

C2902

0201-1

6.3V

1.0UF

X5R

20%

2

1

C2932

1.0UF

0201-1

6.3V X5R

20%

2

1

C2931

0201-1

6.3V X5R

20%

1.0UF

2

1

C2930

0201-1

6.3V X5R

1.0UF

20%

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

Thunderbolt Host (2 of 2)

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3_TBTRDV

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15 MM

PP3V3_TBTLC

PP3V3_S0

TBT_PWR_REQ_L

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

PP1V05_TBT

TBT_PWR_ON_POC_RST_L TBTPOCRST_CT

TBTPOCRST_SENSE

PP3V3_S4_TBT

SMC_DELAYED_PWRGD

TBTPOCRST_MR_L

TBT_POC_RESET_L

PP3V3_TBTLC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

PP1V05_TBT

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.50 MM

MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.38 MM

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_TBTCIO

VOLTAGE=1.05V

PP3V3_S0

PP3V3_S4_TBT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_S4_TBT_F

MIN_NECK_WIDTH=0.20 MM

<SCH_NUM>

29 OF 119

29 OF 97

19 20 28 29 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

29

28 29 30 45 84

19 20 28 29 84

29

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

28 29 30 45 84

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

IN

OUT

D

SYM_VER_3

S G

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

SG

IN

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

C3080 USING 0603 PAKAGE IS FOR DFM TO PROTECT Q3080 (CSP)

8-13V Input Changes required for 2S.

Vds(max): -30V

Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

Thunderbolt 15V Boost Regulator

add property on another page.

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

NOTE: Change R3097 to XW3095 at PVT

Max Vgs: 10V

Vout = 1.6V * (1 + Ra / Rb)

Freq = 480KHz

NOTE: MIRROR C3096 and C3098

BATLOW# Isolation

(NONE)

- =PP15V_TBT_REG (15V Boost Output)

Pull-up on RR page

Voltage not specified here,

BOM options provided by this page:

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

<R2>

UVLO = 4.55V (falling), 4.95 (rising)

GND inside package,

<Rb>

Vgs(th): -1.4V

Vgs(max): +/-12V

SI8409DB:

<R1>

- =PPVIN_SW_TBTBST (8-13V Boost Input)

no XW necessary.

Max Current = 2A?

SGND shorted to

Vout = 15.47V

<Ra>

2

1

R3081

402

MF-LF

5%

1/16W

330K

2

1

R3080

402

MF-LF

5%

1/16W

470K

2

1

C3080

603-1

X7R

0.1UF

10% 50V

2

1

R3092

402

73.2K

1/16W MF-LF

1%

2

1

R3087

402

5%

330K

MF-LF

1/16W

2

1

R3094

402

1/16W

1%

26.7K

MF-LF

2

1

C3094

10%

0.33UF

X6S-CERM 0402

6.3V

2

1

R3088

402

5% 1/16W MF-LF

330K

19 29 40 41

2

1

C3089

402

NO STUFF

5% 50V CERM

100PF

2

1

R3096

402

1/16W

15.8K

MF-LF

1%

2

1

C3095

20%

33UF-0.06OHM

POLY-TANT

25V CASE-D3L

2

1

C3096

20%

X5R-CERM

PLACE_SIDE=BOTTOM

10UF

0603

25V

2

1

C3097

NO STUFF

X7R-CERM 1206

10UF

25V

10%

2

1

C3087

CERM 0402

68PF

50V

5%

2

1

C3085

20%

2.2UF

0402

CER-X6S

10V

4

1

32

Q3080

BGA

CRITICAL

SI8409DB

2

1

R3093

402

1%

49.9K

1/16W MF-LF

2

1

R3091

402

1/16W MF-LF

200K

1%

2

1

C3090

20%

X5R-CERM

10UF

25V

0603

2

1

C3091

20%

X5R-CERM

0603

25V

10UF

21

L3095

CRITICAL

3.3UH-6.5A

PIMB063T-SM

2

1

C3088

CERM

10PF

0402

50V

5%

27

30

34

382120

9

8

32

37

24234

3

6

33

36

35

10

2

1

28

1716151413

12

31

25

U3090

CRITICAL

LT3957

QFN

2

1

R3095

402

137K

1/16W MF-LF

1%

2

1

R3089

1/20W

MF

5%

0

0201

2

1

C3099

0402

50V

10% X7R-CERM

0.001UF

2

1

C3093

0.0033UF

50V

10% X7R-CERM

0402

2

1

C3092

20%

2.2UF

0402

CER-X6S

10V

2

1

C3086

20%

2.2UF

0402

CER-X6S

10V

3

2

1

D3095

CRITICAL

PWRDI5

PDS540XF

28 32

28 30

2

1

3

Q3000

DFN1006H4-3

DMN32D2LFB4

12 40 42

2

1

C3098

20%

X5R-CERM

PLACE_SIDE=TOP

0603

25V

10UF

21

R3097

402

5%

10

MF-LF

1/16W

4

5

3

Q3088

SOT563

DMN5L06VK-7

1

2

6

Q3088

SOT563

DMN5L06VK-7

1

2

6

Q3005

DMN5L06VK-7

SOT563

28 31

4

5

3

Q3005

DMN5L06VK-7

SOT563

Thunderbolt Mobile Support

SYNC_DATE=06/24/2014

SYNC_MASTER=CLEAN_X305

TBTBST_PWREN_DIV_L

TBTBST_PWREN_L

TBT_B_HV_ENTBT_A_HV_EN

TBTBST_SNS2

PM_BATLOW_L

MAKE_BASE=TRUE

TBT_BATLOW_L

TBTBST_SS

TBT_BATLOW_L

PP3V3_S4_TBT

TBTBST_SNS1

TBTBST_FBX

PP15V_TBT

SMC_DELAYED_PWRGD

TBTBST_SHDN_DIV

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

TBTBST_BOOST

MIN_NECK_WIDTH=0.25 mm

TBTBST_VSNS

TBTBST_RT

TBTBST_VC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

TBTBST_VC_RC

TBTBST_EN_UVLO

TBTBST_INTVCC

30 OF 97

30 OF 119

<SCH_NUM>

28 30

28 29 45 84

31 32 84

84

44 47 56 57 63 65 84 86

IN IN

OUT

IN IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

OUT

BI

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN IN

IN

ML_LANE1P

GND1

ML_LANE0N

GND0

ML_LANE0P

ML_LANE1N

ML_LANE2N

RETURN

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4

DP_PWR

AUX_CHP AUX_CHN

ML_LANE2P

GND3

SHIELD PINS

PORT B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Thunderbolt Connector A

Single-fault protection

ISET_Sx with CD3210.

ILIM = 40000 / RISET

12V: See

(0-18.9V)

For 12V systems:

wake from Thunderbolt devices.

DP Dir

514-0876

down HPD input with

to 100K (DPv1.1a).

greater than or equal

TBT: Unused

<RV3P3>

V3P3 must be S4 to support

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Low: 0 - 0.8V

Sink HPD range:

(Both C’s)

TBT Dir

(0-18.9V)

TBT: TX_0

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

DP Source must pull

High: 2.0 - 5.0V

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU) (IPD)

(IPD)

(IPU)

below

requires two R’s per HV

Single R on ISET_V3P3 OK.

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

TBT: TX_1

TBT: RX_0

TBT: RX_1

IV3P3 1100mA 1030mA 1200mA

3.3V/HV Power MUX

15.75V Max

Nominal Min Max

TBT Dir

470k R’s for ESD protection on AC-coupled signals.

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

2

1

C3200

50V

10%

0402

X7R-CERM

0.01UF

28 93

2

1

C3202

0201

16V

10% X5R-CERM

0.01UF

21

R3201

1/20W

MF

201

5%

12

2

1

C3201

0402

50V

10% X7R-CERM

0.01UF

2

1

R3294

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20W

5%

201

MF

1K

2

1

R3295

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20W

5%

201

MF

1K

2

1

R3241

5%

100K

1/20W 201

MF

2

1

C3286

6.3V

20%

0402

CERM-X5R

10UF

2

1

C3285

X5R-CERM

16V

10%

0201

0.1UF

2

1

C3281

16V

10%

0201

X5R-CERM

0.1UF

2

1

C3280

20%

6.3V 603

X5R-CERM-1

22UF

2

1

C3287

100UF

6.3V

20%

CASE-B2-SM

POLY-TANT

CRITICAL

2

1

R3252

1/20W

MF

5%

201

1M

2

1

R3251

201

1/20W

5% MF

1M

2

1

C3294

X7R

330PF

0201

10% 16V

2

1

C3295

X7R

330PF

0201

10% 16V

21

L3200

CRITICAL

FERR-120-OHM-3A

0603

28

2

1

C3210

0.1UF

25V

10%

402

X5R

2

1

R3270

470K

MF 201

5% 1/20W

GND_VOID=TRUE

2

1

R3271

GND_VOID=TRUE

470K

MF 201

5% 1/20W

21

C3271

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

21

C3270

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

28 93

21

C3272

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

21

C3273

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

2

1

R3273

470K

MF 201

5% 1/20W

GND_VOID=TRUE

2

1

R3272

470K

MF 201

5% 1/20W

GND_VOID=TRUE

7

6

18

20

19

21

17

14

12

8

9

1011

15

13

321

416

5

U3210

QFN

CRITICAL

CD3211A1RGP

28 30

32 66 67

32 44 67

2

1

R3212

1/20W

1%

201

MF

36.5K

2

1

C3211

25V

10%

402

X5R

0.1UF

2

1

C3220

0.1UF

0201

10% 16V

X5R-CERM

28

83

28

28 82

28 87 93

28 93

21

C3232

0201

0.22UF

6.3V

20% X5R

21

C3233

0.22UF

6.3V

20%

0201

X5R

28 93

21

C3230

0.1UF

10% 16V X5R-CERM

0201

21

C3231

X5R-CERM

0201

0.1UF

10% 16V

28 93

21

C3278

0.22UF

6.3V

20%

0201

X5R 21

C3279

0.22UF

6.3V

20%

0201

X5R

28 93

2

1

R3211

1/20W

1%

201

MF

22.6K

TBTHV:P15V

2

1

R3210

MF

1/20W

1%

201

22.6K

TBTHV:P15V

2

1

R3214

22.6K

MF 201

1% 1/20W

TBTHV:P15V

2

1

R3213

TBTHV:P15V

22.6K

MF

201

1%

1/20W

2

1

C3215

25V

10%

0603

X5R-CERM

4.7UF

2

1

C3205

GND_VOID=TRUE

0.01UF

X5R-CERM

0201

10% 25V

2

1

C3206

0.01UF

GND_VOID=TRUE

25V

0201

X5R-CERM

10%

28

21

C3274

4V

GND_VOID=TRUE

201

CERM-X5R-1

0.47UF

20% 21

C3275

2014V

GND_VOID=TRUE

CERM-X5R-1

0.47UF

20%

3

25

8

7 15

14 13

12 17

21

9

19 20

6

11 10

4 5

16 18

22

23

24

2

1

U3220

SIGNAL_MODEL=TBT_MUX

CBTL05024

HVQFN24-COMBO

CRITICAL

28 32

28

2

1

R3279

1/20W

5%

201

MF

470K

2

1

R3278

470K

1/20W

5%

201

MF

21

C3277

2014V

0.47UF

20% CERM-X5R-1

GND_VOID=TRUE

21

C3276

2014V

0.47UF

20%

GND_VOID=TRUE

CERM-X5R-1

S24

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

B19

B10 B12

B15 B17

B9 B11

B3 B5

B2

B14 B13

B8 B7

B1

B20

B6

B4

B16 B18

J3200

MDP-J44

F-RT-TH

CRITICAL

2

1

C3204

NP0-C0G

CRITICAL

0201

25V

+/-0.1PF

3.0PF

2

1

C3203

NP0-C0G 25V

12PF

CRITICAL

0201

5%

TBTHV:P12V

118S0145

R3211,R3214

2

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

TBTHV:P12V

R3210,R3213

2

118S0145

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Thunderbolt Connector A

SYNC_MASTER=CLEAN_X425

SYNC_DATE=10/30/2014

TBT_A_D2R_C_N<1>

TBT_A_CIO_SEL

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_S4_TBTAPWR

TBTAPWRSW_ISET_V3P3

TBT_A_HV_EN

S4_PWR_EN

TBTAPWRSW_ISET_S0 TBTAPWRSW_ISET_S3

PP15V_TBT

TBT_A_D2R_P<1>

TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_P

TBTAPWRSW_ISET_S3_R

DP_TBTPA_HPD

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_DDC_DATA

TBT_A_CONFIG1_BUF

TBT_A_D2R1_AUXDDC_N TBT_A_D2R1_AUXDDC_P

TBTDP_AUXIO_EN TBT_A_DP_PWRDN

DP_TBTPA_AUXCH_N

DP_TBTPA_ML_N<1>

DP_TBTPA_ML_P<1>

TBT_A_HPD

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_CONFIG1_RC

PP3V3_S4_TBTAPWR

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_DDC_CLK

PP3V3_S4_TBTAPWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V

TBTAPWRSW_ISET_S0_R

TBT_A_R2D_N<1>

DP_A_LSX_ML_N<1>

TBT_A_R2D_P<0> TBT_A_R2D_N<0>

TBTACONN_7_C

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=18.9V

TBT_A_D2R1_AUXDDC_N

PP3V3_S5

PM_SLP_S3_R_L

DP_A_LSX_ML_P<1>

TBT_A_R2D_P<1>

TBT_A_D2R1_AUXDDC_P

TBT_A_CONFIG2_RC

TBT_A_HPD

MIN_LINE_WIDTH=0.38 MM

TBTACONN_20_RC

MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM

TBTACONN_1_C

MIN_NECK_WIDTH=0.20 MM

TBT_A_CONFIG1_RC

TBT_A_D2R_C_N<0>

TBT_A_D2R_C_P<0>

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_P<3>

PP3V3RHV_S4_TBTAPWR_F

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

<SCH_NUM>

32 OF 119

31 OF 97

93

30 32 84

93

31 93

93

31

31 93

31

93

31 93

93

31 93

12 14 15 17 18 19 21 32 33 61 64 66

67 82 84 85 86 96

31 93

93

31 93

31

93

IN IN

OUT

IN IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

OUT

BI

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN IN

IN

ML_LANE1P

GND3

GND4

HPD

CONFIG2 GND2

RETURN

AUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

GND0

DP_PWR

ML_LANE0P

GND1

ML_LANE0N

ML_LANE1N

ML_LANE2N

ML_LANE2P

PORT A

SHIELD PINS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

12V: See

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IV3P3 1100mA 1030mA 1200mA

TBT: TX_1

514-0876

<RV3P3>

Nominal Min Max

wake from Thunderbolt devices.

15.75V Max

(Both C’s)

DP Dir

TBT Dir

(Both C’s)

on AC-coupled signals.

470k R’s for ESD protection

(Both C’s)

TBT Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

greater than or equal

Low: 0 - 0.8V

High: 2.0 - 5.0V

Sink HPD range:

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU) (IPD)

(IPD)

(IPU)

3.3V/HV Power MUX

Single-fault protection

below

ILIM = 40000 / RISET

ISET_Sx with CD3210.

requires two R’s per HV

Single R on ISET_V3P3 OK.

<RHVS0>

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

TBT: RX_0

TBT: Unused

down HPD input with

TBT: RX_1

DP Source must pull

V3P3 must be S4 to support

For 12V systems:

to 100K (DPv1.1a).

<RHVS3>

Thunderbolt Connector B

2

1

C3300

0.01UF

X7R-CERM

0402

10% 50V

28 93

2

1

C3302

0.01UF

X5R-CERM 0201

10% 16V

21

R3301

1/20W

201

12

MF

5%

2

1

C3301

0.01UF

X7R-CERM 0402

10% 50V

2

1

R3394

1K

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

2

1

R3395

1K

MF 201

5% 1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

2

1

R3341

MF 201

5% 1/20W

100K

2

1

C3386

10UF

CERM-X5R 0402

20%

6.3V

2

1

C3385

0.1UF

X5R-CERM

0201

10% 16V

2

1

C3381

X5R-CERM

0.1UF

0201

10% 16V

2

1

C3380

X5R-CERM-1

6.3V 603

22UF

20%

2

1

C3387

POLY-TANT

CASE-B2-SM

20%

6.3V

CRITICAL

100UF

2

1

R3352

1M

MF

201

5%

1/20W

2

1

R3351

1M

MF 201

5% 1/20W

2

1

C3394

16V

10%

0201

330PF

X7R

2

1

C3395

16V

10% 0201

330PF

X7R

21

L3300

CRITICAL

0603

FERR-120-OHM-3A

28

2

1

C3310

0.1UF

X5R 402

10% 25V

2

1

R3370

GND_VOID=TRUE

1/20W

5%

201

MF

470K

2

1

R3371

GND_VOID=TRUE

1/20W

5%

201

MF

470K

21

C3371

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

21

C3370

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

28 93

21

C3372

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

21

C3373

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

2

1

R3373

GND_VOID=TRUE

1/20W

5%

201

MF

470K

2

1

R3372

GND_VOID=TRUE

1/20W

5%

201

MF

470K

7

6

18

20

19

21

17

14

12

8

9

1011

15

13

321

416

5

U3310

CD3211A1RGP

QFN

CRITICAL

28 30

31 66 67

31 44 67

2

1

R3312

201

MF

1/20W

1%

36.5K

2

1

C3311

0.1UF

X5R 402

10% 25V

2

1

C3320

X5R-CERM

16V

10%

0201

0.1UF

28

83

28

28 82

28 93

21

C3332

0.22UF

6.3V

20%

0201

X5R 21

C3333

0.22UF

6.3V

20%

0201

X5R

28 93

21

C3330

0.1UF

10% 16V X5R-CERM

0201

21

C3331

0201

0.1UF

X5R-CERM

10% 16V

28 93

21

C3378

X5R

0201

20%

6.3V

0.22UF

21

C3379

X5R

0201

20%

6.3V

0.22UF

28 93

2

1

R3311

1%

22.6K

MF 201

1/20W

TBTHV:P15V

2

1

R3310

22.6K

TBTHV:P15V

MF

201

1%

1/20W

2

1

R3314

1/20W

1%

201

MF

22.6K

TBTHV:P15V

2

1

R3313

1/20W

1%

201

MF

22.6K

TBTHV:P15V

2

1

C3315

4.7UF

X5R-CERM

0603

10% 25V

2

1

C3305

GND_VOID=TRUE

25V

10%

0201

X5R-CERM

0.01UF

2

1

C3306

0.01UF

X5R-CERM

0201

10% 25V

GND_VOID=TRUE

28

21

C3374

20%

0.47UF

CERM-X5R-1

201

GND_VOID=TRUE

4V

21

C3375

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

4V 201

3

25

8

7 15

14 13

12 17

21

9

19 20

6

11 10

4 5

16 18

22

23

24

2

1

U3320

HVQFN24-COMBO

CRITICAL

CBTL05024

SIGNAL_MODEL=TBT_MUX

28 31

28

2

1

R3379

470K

MF

201

5%

1/20W

2

1

R3378

470K

MF 201

5% 1/20W

21

C3376

CERM-X5R-1

20%

0.47UF

4V 201

GND_VOID=TRUE

21

C3377

CERM-X5R-1

20%

0.47UF

4V 201

GND_VOID=TRUE

S9S8S7

S6

S5S4S3

S23S2S11

S10

S1

A19

A10 A12

A15 A17

A9 A11

A3 A5

A2

A14 A13

A8 A7

A1

A20

A6

A4

A16 A18

J3200

F-RT-TH

CRITICAL

MDP-J44

2

1

C3303

NP0-C0G 25V

12PF

CRITICAL

0201

5%

2

1

C3304

NP0-C0G

CRITICAL

0201

25V

+/-0.1PF

3.0PF

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

2

R3311,R3314

TBTHV:P12V

118S0145

Thunderbolt Connector B

SYNC_MASTER=CLEAN_X425

SYNC_DATE=10/30/2014

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

2

R3310,R3313

TBTHV:P12V

MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_S4_TBTBPWR_F

TBT_B_HPD TBT_B_CONFIG1_RC

PM_SLP_S3_R_L

PP15V_TBT

TBTBPWRSW_ISET_S3

TBT_B_HV_EN

PP3V3_S5

TBTBPWRSW_ISET_V3P3

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_S4_TBTBPWR

VOLTAGE=15V

S4_PWR_EN

MIN_NECK_WIDTH=0.20 MM

PP3V3_S4_TBTBPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

DP_TBTPB_HPD

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_D2R1_AUXDDC_N TBT_B_D2R1_AUXDDC_P

TBT_B_CIO_SEL TBTDP_AUXIO_EN TBT_B_DP_PWRDN

DP_TBTPB_ML_N<1>

DP_TBTPB_ML_P<1>

TBT_B_HPD

DP_B_LSX_ML_N<1>

DP_B_LSX_ML_P<1>

TBT_B_CONFIG1_RC

DP_TBTPB_AUXCH_P

PP3V3_S4_TBTBPWR

TBT_B_CONFIG2_RC

TBT_B_R2D_C_N<0>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<3>

TBT_B_D2R_N<0>

TBT_B_D2R_P<0>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_N<1> TBT_B_D2R_P<1>

TBT_B_D2R_C_P<1>

TBT_B_D2R_C_N<1>

TBT_B_R2D_P<1> TBT_B_R2D_N<1>

DP_B_LSX_ML_N<1>

TBT_B_R2D_N<0>

TBTBCONN_7_C

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBT_B_R2D_P<0>

VOLTAGE=18.9V

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBT_B_D2R1_AUXDDC_P

DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

TBT_B_D2R_C_P<0>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R_C_N<0>

DP_B_LSX_ML_P<1>

TBTBPWRSW_ISET_S0

<SCH_NUM>

33 OF 119

32 OF 97

32

30 31 84

12 14 15 17 18 19 21 31 33 61 64 66

67 82 84 85 86 96

32

93

32 93

93

32

32 93

32

93

32

93

32 93

93

32 93

93

32 93

93

32 93

IN

OUT

IN

OUT

IN

OUT

IN

OUT

SYM_VER_2

G S

D

BI BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

NC

OUT

GND

VOUTONVIN

IN

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

GND

VDD

D

SON

CAP

SYM_VER-1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LOCATION DEPENDS ON DESENSE TEAM

AIRPORT

3.3V SIL WLAN Switch

18.5 mOhm Typ

SLG5AP1443V

17 mOhm Typ 19 mOhm Max

Load Switch

Part Type R(on)

Max Current = 2A (85C)

R(on)

Load Switch

TPS22924C

@ 2.5V

1A PEAK

155S0367

BLUETOOTH

L USB_BT_WAKE

SEL OUTPUT

Delay = 130 ms +/- 20%

Supervisor & CLKREQ # Isolation

516S1016

H USB_BT

NOTE: Stuff non-zero value for R3557 to see which end is driving low

Type

CURRENT SENSE

25.8 mOhm Max

FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

LOCATION DEPENDS ON DESENSE TEAM

FOR DESENSE IMPROVEMENT

FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

Part

3.3V TI WLAN Switch

FOR DESENSE IMPROVEMENT

21

L3504

0603

FERR-120-OHM-3A

2

1

C3521

CERM

0.1uF

10V

20%

402

PLACE_NEAR=J3501.1:2.54MM

2

1

C3522

20% 10V

402

PLACE_NEAR=J3501.1:2.54MM

CERM

0.1uF

13 91

11 91

21

C3531

0402

0.1UF

10%

X7R-CERM

PLACE_NEAR=J3501.5:2.54MM

16V

21

C3530

PLACE_NEAR=J3501.4:2.54MM

X7R-CERM0402

0.1UF

16V10%

12 35 86 91

2

1

C3532

X7R-CERM 0402

16V

0.01UF

10%

20

11 18

2

1

C3540

CERM 402

20% 10V

0.1uF

2

1

R3554

402

MF-LF

1/16W

1%

232K

2

1

R3555

1/16W 402

1%

100K

MF-LF

2

1

R3553

1/16W

1%

402

MF-LF

100K

40 41 86

2

1

C3570

5%

12PF

NP0-C0G

25V

NOSTUFF

0201

2

1

C3571

X5R-CERM

0.1UF

10% 16V

0201

NOSTUFF

2

1

C3573

0.1UF

16V 0201

10% X5R-CERM

NOSTUFF

2

1

C3572

5%

12PF

NP0-C0G

25V

NOSTUFF

0201

2

1

C3575

0201

10% 16V X5R-CERM

0.1UF

NOSTUFF

2

1

C3574

5%

12PF

NP0-C0G

25V 0201

NOSTUFF

2

1

C3577

0.1UF

X5R-CERM

10% 16V

0201

NOSTUFF

2

1

C3576

5%

12PF

NP0-C0G

25V

NOSTUFF

0201

13 20 91

33 46

2 1

L3505

PLACE_NEAR=J3501.18:2.54MM

FERR-120-OHM-1.5A

0402-LF

2

1

3

Q3510

DFN1006H4-3

DMN32D2LFB4

NO_XNET_CONNECTION=TRUE

13 90

2

1

R3512

15K

201

MF

1% 1/20W

1 2

9

10

8

5 4

3

7 6

U3510

CRITICAL

SIGNAL_MODEL=MOJO_MUX_USBONLY

TQFN

PI3USB102EZLE

12 21 37 40 67 81 86

2

1

C3510

CERM-X5R

0.1UF

0201

10%

6.3V

38 40 42 86

B1

A1

B2

A2

C2

C1

U3550

WLAN_SW:TI

CSP

CRITICAL

TPS22924

33 40 67

1

9

2

4

8

3

7

5

6

U3540

SLG4AP041V

TDFN

CRITICAL

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J3501

CRITICAL

F-RT-SM

SSD-X29-D1

2

1

R3556

0

APCLKRQ:ISOL

0201

1/20W

MF

5%

21

R3557

APCLKRQ:BIDIR

201

5% MF

1/20W

1K

2

1

C3555

4700PF

201

10V X7R

10%

WLAN_SW:SIL

1

52

8

37

U3551

WLAN_SW:SIL

TDFN

SLG5AP1443V

CRITICAL

4

32

1

L3501

90-OHM-0.1A-0.7-2GHZ

PLACE_NEAR=J3501.7:2.54MM

CRITICAL

TAM0605

2

1

C3524

0201

5%

25V

12PF

NP0-C0G

CRITICAL

2

1

C3523

5% NP0-C0G

CRITICAL

25V

0201

12PF

2

1

C3550

0201

12PF

5% NP0-C0G

25V

CRITICAL

2

1

C3551

0201

12PF

5% NP0-C0G

25V

CRITICAL

2

1

C3533

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C3534

3.0PF

+/-0.1PF 25V

0201

CRITICAL

NP0-C0G

2

1

C3525

0201

CRITICAL

25V NP0-C0G

+/-0.1PF

3.0PF

SYNC_MASTER=CLEAN_X425

SYNC_DATE=10/30/2014

X87 CONNECTOR

PCIE_AP_R2D_P

PCIE_AP_R2D_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_R

MIN_NECK_WIDTH=0.25 mm

PCIE_AP_R2D_C_N

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

PP3V3_WLAN_R

PP3V3_S5

PM_WLAN_EN

PM_WLAN_CAP

PP3V3_S5

PP3V3_S4

PCIE_AP_R2D_C_P

AP_CLKREQ_L

USB_BT_N

SMC_PME_S4_WAKE_L

USB_BT_P

PP3V3_S5

AP_RESET_L

P3V3WLAN_VMON

PP3V3_WLAN_F

AP_CLKREQ_R_L

PM_WLAN_EN

PM_SLP_S4_L

USB_BT_WAKEN

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PP3V3_S4

USB_BT_CONN_P

USB_BT_CONN_N

MIN_LINE_WIDTH=1 mm

PP3V3_WLAN

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

WIFI_EVENT_L

AP_RESET_CONN_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S3RS4_BT_F

AP_CLKREQ_Q_L

PCIE_CLK100M_AP_CONN_P

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PCIE_CLK100M_AP_CONN_N

PCIE_WAKE_L

<SCH_NUM>

35 OF 119

33 OF 97

86 91

33 46

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

33 40 67

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

20 33 38 41 42 45 46 65 66 67 81 84 85 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

33 46

33 40 67

20 33 38 41 42 45 46 65 66 67 81 84 85 86

86 90

41 86

86

86 91

OUT

IN

NC

08

NC

IN

IN IN

OUT

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FOR DESENSE IMPROVEMENT

Delay = ~55ms

Supervisor & CLKREQ# Isolation

GND_VOID

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

Gumstick3 Connector

APN 343S0511

OOB Isolation

GND_VOID

514S0449

40

2

1

C3702

PLACE_NEAR=L3700.1:1mm

10V X5R-CERM 0201

0.1UF

10%

21

L3700

PLACE_NEAR=J3700.1:3mm

CRITICAL

FERR-26-OHM-6A

0603

2

1

C3701

PLACE_NEAR=L3700.1:1mm

10V X5R-CERM 0201

0.1UF

10%

2

1

R3742

MF

1%

100K

1/20W 201

2

1

R3740

201

100K

1/20W

MF

5%

2

1

R3741

1% MF

1/20W

232K

201

11

2

1

C3740

CERM-X5R

10%

0.1UF

6.3V 0201

20

34 66

4

6

5 3

1

2

U3711

SOT891

74LVC1G08

CRITICAL

2

1

C3719

BYPASS=U3711::5 mm

X5R-CERM

0.1UF

10V

10%

0201

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

21

C3711

0.22UF

6.3V

20%

GND_VOID=TRUE

X6S-CERM 0201

21

C3710

20%

0.22UF

6.3V 0201

GND_VOID=TRUE

X6S-CERM

11 91

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

34 66

40

20

18

9

8

7

63

62

61

60

6

59

58

57

56

55

54

53 52 51

50

5

49 48 47

46 45 44 43 42 41 40

4

39 38 37 36 35 34 33

32 31 30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3700

F-RT-SM

TRUE

TRUE TRUE

TRUE

SSD-GS3

TRUE

CRITICAL

TRUE

TRUE TRUE

2

1

R3700

MF

201

1/20W

1%

100K

NOSTUFF

4

6

53

1

2

U3710

74LVC1G08

CRITICAL

SOT891

40

2

1

C3718

BYPASS=U3710::5 mm

0.1UF

10V 0201

X5R-CERM

10%

1

9

2

4

8

3

7

5

6

U3740

SLG4AP016V

TDFN

CRITICAL

21

C3712

0.22UF

6.3V

20%

0201X6S-CERM

GND_VOID=TRUE

21

C3713

20%

6.3V X6S-CERM 0201

0.22UF

GND_VOID=TRUE

21

C3714

0.22UF

X6S-CERM6.3V

20%

0201

GND_VOID=TRUE

21

C3715

X6S-CERM

20%

0201

0.22UF

6.3V

GND_VOID=TRUE

21

C3716

6.3V X6S-CERM

20%

0201

0.22UF

GND_VOID=TRUE

21

C3717

0.22UF

0201

GND_VOID=TRUE

20%

X6S-CERM6.3V

2

1

R3701

1/20W

201

MF

1%

100K

2

1

C3722

PLACE_NEAR=J3700.3:2mm

0201

12PF

5% NP0-C0G

25V

2

1

C3723

12PF

PLACE_NEAR=J3700.4:2mm

0201

5% NP0-C0G

25V

2

1

C3724

PLACE_NEAR=J3700.5:2mm

25V

NP0-C0G

5%

12PF

0201

SYNC_DATE=08/15/2014

SYNC_MASTER=CLEAN_X425

SSD Connector

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<0>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_N<3>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_N

PCIE_SSD_D2R_N<1>

SMC_OOB1_D2R_L

PP3V3_S0SW_SSD

PP3V3_S0

SMC_OOB1_R2D_L

SSD_DEVSLP

P3V3SSD_VMON

SSD_CLKREQ_L

SSD_PWR_FET_EN

PP3V3_S0SW_SSD

PP3V42_G3H

MAKE_BASE=TRUE

SSD_PWR_FET_EN

PCIE_SSD_D2R_P<2>

SSD_RESET_L

PP3V3_S0SW_SSD

NO_TEST=TRUE

NC_SSD_MFG_RSVD

PP3V3_S0

PCIE_SSD_R2D_N<0>

PCIE_CLK100M_SSD_P

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

SMC_PWRFAIL_WARN_L

PCIE_SSD_R2D_C_P<1>

SSD_PWR_FET_EN

SMC_OOB1_R2D_CONN_L

SSD_PCIE_SEL_L

SMC_OOB1_D2R_CONN_L

SSD_CLKREQ_CONN_L

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<0>

SSD_RESET_CONN_L

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_C_N<1>

VOLTAGE=3.3V

PP3V3_S0SW_SSD_FLT

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.15mm

<SCH_NUM>

37 OF 119

34 OF 97

89

34 45 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

34 45 84 86

19 37 38 40 41 42 43 50 56 57 67 84 86

34 66 34 66

34 45 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

89

NC NC

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03 DEBUG_04 DEBUG_05

DEBUG_09

PCIE_RDP0

DEBUG_06

DEBUG_00 DEBUG_01 DEBUG_02

DEBUG_07 DEBUG_08

DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13

DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

JTAG_TCK JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS UARTRTS

UARTRXD UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1 MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS*

DDR_DM0 DDR_DM1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI BI BI

BI BI

OUT OUT OUT

IN

OUT

IN

OUT

NC NC NC NC

NC

NC NC NC

NC NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PU = 25MHz

PD = 1.35V

L3901:1 L3902:1

(=PP3V3_S3RS0_CAMERA)

PU on PCH page

11

36

35 36 86

2

1

R3930

NOSTUFF

100K

MF

1/20W 201

5%

2

1

R3932

NOSTUFF

100K

1/20W MF 201

5%

20

2

1

C3900

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3924

0.1UF

10% CERM-X5R

6.3V 0201

2

1

C3923

X5R

6.3V 0201-1

1.0UF

20%

2

1

C3922

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3921

X5R

6.3V

20%

0201-1

1.0UF

2

1

C3910

0.1UF

0201

10% CERM-X5R

6.3V

BYPASS=U3900.D6::2.54MM

2

1

C3951

BYPASS=U3900.D6::2.54MM

0201

0.1UF

10% CERM-X5R

6.3V

2

1

R3901

100K

MF

1/20W 201

5%

36

36 91

2

1

R3906

NO STUFF

100K

MF

1/20W

5%

201

2

1

R3907

100K

MF 201

5% 1/20W

2

1

R3904

1/20W

5%

100K

MF 201

21

L3901

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

1008

21

L3902

1.0UH-1.6A-55MOHM

PLACE_NEAR=U3900.K13:4MM

1008

2

1

C3912

BYPASS=U3900.K13::2.54MM

4.7UF

6.3V

20% X5R

402

2

1

C3915

X5R

6.3V

PLACE_NEAR=U3900.M13:2.54MM

4.7UF

20%

402

21

L3906

22NH

0402

2

1

C3916

BYPASS=U3900.L7::2.54MM

0.1UF

CERM-X5R

10%

0201

6.3V

2

1

C3928

X5R

6.3V 402

20%

4.7UF

2

1

C3926

PLACE_NEAR=U3900.M14:2.54MM

4.7UF

X5R

6.3V 402

20%

2

1

C3919

0.1UF

10%

6.3V CERM-X5R 0201

BYPASS=U3900.J1::2.54MM

2

1

C3937

10%

0201

6.3V

BYPASS=U3900::5mm

CERM-X5R

0.1UF

2

1

C3935

10%

BYPASS=U3900::5mm

CERM-X5R

6.3V 0201

0.1UF

2

1

C3940

BYPASS=U3900::5mm

CERM-X5R

10%

0.1UF

6.3V 0201

2

1

C3942

402

BYPASS=U3900::7mm

4.7UF

X5R

6.3V

20%

2

1

C3941

BYPASS=U3900.F15::2.54MM

CERM

2.2UF

20%

402-LF

6.3V

2

1

C3939

1UF

BYPASS=U3900.G15::2.54MM

10% 10V

402

X5R

2

1

C3960

10%

0.1UF

0201

CERM-X5R

6.3V

A13 A12

E14

E13

D14

D13

J12 M10

C12

C13

H12

R13

E15

G12

N12

B9 C9

A8 B8

R14

B10 A10

B7 A7

P13

P6

P8

R6

R8

P7 R7

D11

D12

F12

E12

F13

C11

R9

C15

R10

D15

N9

N10

N11

P9

P10

P11

P12

R12

L10

L11

K10

K11

J10

H10

H11

G10

G11

F10

F11

E10

E11

A15

B14

C14

B11

U3900

OMIT_TABLE

FBGA

BCM15700

CRITICAL

G3

J2

R3

H3

A2

E2

A3

D2

B3

B2

C5

A5

B4

B1

C3

B5

F2

F4

F1

F3

D3

E4

E3

C2

C4

C1

L4

J3

H2 G2

H4

K2

L2

K3

R4

P1

L1

R2

J4

P2

P3

N2

P4

M2

M1

M3

N3

M4

L3

U3900

BCM15700

OMIT_TABLE

CRITICAL

FBGA

B12

B13

G8

G7

G6

G1

E5

D5

E9

R5

R1

P5

D1

N1

M9

A14

K9

K8

K7

K6

K5

K1

J9

B6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

A6

A1

K12

M11

R11

B15

L9

L8

L5

L6

F9

F8

F7

F6

J11

F14

G15

F15

K14

K13

N14

M13

J15

J14

J13

H15

H14

N15

M15

M14

L15

L14

L13

L12

K15

R15

P15

P14

N13

M12

G14

D6

C8

D9

C7

C10

D7

L7

N6

N8

N7

N5

G5

N4

K4

G4

D4

A4

J1

U3900

CRITICAL

BCM15700

FBGA

OMIT_TABLE

2

1

C3918

BYPASS=U3900.J1::2.54MM

X7R-1

10%

0201

16V

1000PF

2

1

C3934

X7R-1

BYPASS=U3900::3mm

0201

16V

1000PF

10%

2

1

C3917

BYPASS=U3900.L7::2.54MM

0201

1000PF

X7R-1

16V

10%

2

1

C3936

X7R-1

BYPASS=U3900::3mm

1000PF

16V 0201

10%

2

1

C3938

X7R-1 0201

BYPASS=U3900.D7::2.54MM

1000PF

16V

10%

36 94

36

2

1

R3910

NO STUFF

5%

201

1/20W MF

100K

2

1

R3911

5%

201

1/20W MF

100K

21

R3912

1%

240

MF

1/20W

201

2

1

R3913

1K

MF

1/20W

201

5%

2

1

R3914

1K

MF

1/20W

201

5%

36 94

21

XW3900

SM

21

XW3901

SM

2

1

R3990

100K

1/20W MF 201

5%

2

1

C3990

NO STUFF

0201

6.3V CERM-X5R

0.1UF

10%

2

1

C3927

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3930

X5R

6.3V

1.0UF

20%

0201-1

36 94

2

1

C3932

1.0UF

6.3V X5R

20%

0201-1

2

1

C3931

X5R 402

4V

10UF

20%

2

1

C3933

X5R

4V

20%

10UF

402

2

1

C3914

X5R

6.3V 402

20%

4.7UF

2

1

C3913

4.7UF

X5R

6.3V

20%

402

21

L3903

220-OHM-1.4A

0603

21

L3904

220-OHM-1.4A

0603

21

R3991

MF

1/20W

0201

0

5%

NO STUFF

12 33 86 91

2

1

C3975

BYPASS=U3900.L9::2.54MM

0201

10%

0.1UF

CERM-X5R

6.3V

2

1

C3974

CERM-X5R

0.1UF

BYPASS=U3900.L9::2.54MM

10% 0201

6.3V

2

1

C3973

0201

X7R-1

16V

BYPASS=U3900.F9::2.54MM

1000PF

10%

2

1

C3972

BYPASS=U3900.F9::2.54MM

CERM-X5R 0201

10%

0.1UF

6.3V

2

1

C3971

X7R-1

BYPASS=U3900.F6::2.54MM

0201

16V

10%

1000PF

2

1

C3970

BYPASS=U3900.F6::2.54MM

10% 0201

CERM-X5R

6.3V

0.1UF

2

1

R3975

1/20W MF 201

51K

5%

2

1

R3976

201

MF

1/20W

51K

5%

2

1

R3920

201

100K

MF

1/20W

5%

2

1

R3921

100K

MF

1/20W 201

5%

2

1

R3934

NOSTUFF

100K

MF

1/20W 201

5%

2

1

R3931

5%

201

1/20W MF

330K

2

1

R3933

5%

201

1/20W MF

330K

2

1

R3935

5%

201

1/20W MF

330K

2

1

R3936

100K

NOSTUFF

MF

1/20W

201

5%

2

1

R3937

NOSTUFF

100K

MF

1/20W

201

5%

36 94

2

1

C3976

5% 0201

CRITICAL

12PF

25V

NP0-C0G

2

1

C3979

NP0-C0G 25V

12PF

CRITICAL

0201

5%

2

1

C3978

NP0-C0G 0201 25V

5%

CRITICAL

12PF

2

1

C3980

NP0-C0G 25V

12PF

CRITICAL

0201

5%

2

1

C3977

NP0-C0G 25V

12PF

CRITICAL

0201

5%

2

1

C3981

3.0PF

CRITICAL

NP0-C0G 0201

25V

+/-0.1PF

2

1

C3983

NP0-C0G 0201 25V

5%

CRITICAL 12PF

2

1

C3982

12PF

CRITICAL

NP0-C0G 25V

0201

5%

SYNC_MASTER=CLEAN_X425

Camera 1 of 2

SYNC_DATE=10/30/2014

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSD

PP1V8_CAM

CAM_XTAL_SEL

CAMERA_CLKREQ_L

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_PCIE_PVDD_FLT

CAM_RAMCFG0

CAM_RAMCFG1

PCIE_CAMERA_R2D_N

TP_CAM_LV_JTAG_TMS

TP_CAM_LV_JTAG_TDI

TP_CAM_LV_JTAG_TCK

TP_CAM_TEST_MODE2

TP_CAM_TEST_MODE1

TP_CAM_TEST_MODE0

TP_CAM_LV_JTAG_TRSTN

GND_CAM_PVSSC

MEM_CAM_A<14>

MEM_CAM_A<13>

MEM_CAM_A<12>

MEM_CAM_BA<0>

PCIE_CLK100M_CAMERA_C_P

PP1V8_CAM

CAM_GPIO3

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

CAM_RAMCFG2

CAM_RAMCFG0

CAM_XTAL_SEL

CAM_XTAL_FREQ

CAM_TEST_MODE

CAM_TEST_OUT

CAM_UARTCTS TP_CAM_UARTRTS

CAM_UARTRXD TP_CAM_UARTTXD

CAM_RAMCFG1

I2C_CAM_SMBDBG_CLK

MIPI_CLK_N

MIPI_CLK_P

GND_CAM_PVSSC

PP1V35_CAM

PP1V2_CAM

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP0V675_CAM_VREF

PP1V35_DDR_CLK

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.35V

P1V2_CAM_SRVLXC_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

P1V35_CAM_SRVLXD_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MEM_CAM_ZQ_S2

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3>

MEM_CAM_A<5>

MEM_CAM_A<4>

MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8>

MEM_CAM_A<10>

MEM_CAM_A<9>

MEM_CAM_A<11>

MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_CKE MEM_CAM_CS_L

MEM_CAM_DQ<15>

MEM_CAM_DQ<14>

MEM_CAM_DQ<13>

MEM_CAM_DQ<12>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<9>

MEM_CAM_DQ<8>

MEM_CAM_DQ<7>

MEM_CAM_DQ<6>

MEM_CAM_DQ<4>

MEM_CAM_DQ<3>

MEM_CAM_DQ<2>

MEM_CAM_DQ<1>

MEM_CAM_DQ<0>

MIPI_DATA_N

MIPI_DATA_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_C_N

PP1V8_CAM

CAM_XTAL_FREQ

CAM_UARTCTS CAM_UARTRXD

CLK25M_CAM_CLKP CLK25M_CAM_CLKN

PCIE_CLK100M_CAMERA_C_N

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L MEM_CAM_RESET_L

GND_CAM_PVSSD

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PCIE_WAKE_L

PP1V2_CAM_XTALPCIEVDD

CAM_RAMCFG2

GND_CAM_PVSSD

CAM_DEBUG_RESET_L

CAM_PCIE_RESET_L

CAM_PWR_SEL

PP1V8_CAM

P1V35_CAM_SRVLXD_PHASE

I2C_CAM_SMBDBG_DAT

PP1V2_CAM

VOLTAGE=1.35V

PP1V35_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_XTALPCIEVDD

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V8_CAM

GND_CAM_PVSSC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

PP1V2_CAM_XTALPCIEVDD

PP1V8_CAM

VOLTAGE=1.2V

PP1V2_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

PP1V2_CAM_XTALPCIEVDD

MIN_NECK_WIDTH=0.2MM

MEM_CAM_DQ<5>

TP_CAM_JTAG_TMS

CAMERA_PWR_EN

CAM_SENSOR_WAKE_L

CAM_TEST_OUT

CAM_TEST_MODE

TP_CAM_JTAG_TDO

TP_CAM_JTAG_TRST_L

TP_CAM_JTAG_TDI

TP_CAM_JTAG_TCK

I2C_CAM_SMBDBG_CLK I2C_CAM_SCK

I2C_CAM_SCK

I2C_CAM_SDA

TP_CAM_JTAG_SRST_L

CAM_PCIE_WAKE_L

I2C_CAM_SDA

I2C_CAM_SMBDBG_DAT

PCIE_CAMERA_D2R_C_P

TP_CAM_LV_JTAG_TDO

PP3V3_S3RS0_CAMERA

<SCH_NUM>

39 OF 119

35 OF 97

35

35 36

35

35 36

35

35 36 94

35

36 94

35

35 36

35

35 36

35

35 36 94

19 35

35

19 35

35

35 36 86

35

13 20 46 84

OUT

IN

BI

IN

BI

BI IN

A4

A14

DQSL*

DQL1

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML DMU

DQL5 DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NC NC NC NC NC

BI BI BI BI BI BI BI BI

BI BI

IN IN

BI BI BI BI BI BI BI BI

IN

IN IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

SYM_VER-1

NC NC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: TBD PPM crystal required

B

518S0892

ALS

77.2 mA nominal max

96.2 mA peak

DRAM CFG Chart

DIE REV

ELPIDA

A

CFG 2

1

0

1

VENDOR HYNIX SAMSUNG MICRON

CFG 110CFG 0

0 0

0 1

remove DRAM SPD Straps

CAMERA SENSOR

35 91

13 20 91

21

C4033

X5R-CERM 0201

16V

0.1UF

10% 21

C4032

X5R-CERM 0201

16V

0.1UF

10%

21

C4031

16V

0201X5R-CERM

0.1UF

10% 21

C4030

16V

0201X5R-CERM

0.1UF

10%

13 91

35 91

21

R4009

NO STUFF

MF

1/20W

0201

0

5%

21

R4010

NO STUFF

MF

1/20W

0201

0

5%

21

R4008

MF

1/20W

020105%

21

R4007

NO STUFF

MF

1/20W

020105%

21

R4000

5%

0

0201

1/20W

MF

2

1

C4004

CERM-X5R-1

BYPASS=U4000.H9::4mm

201

0.47UF

4V

20%

2

1

C4008

BYPASS=U4000.K2::4mm

10V

2.2UF

20% X5R-CERM

402

2

1

C4006

X5R-CERM

20%

2.2UF

10V

BYPASS=U4000.D2::4mm

402

2

1

R4012

NO STUFF

1M

1% MF

1/20W 201

21

C4015

CERM

5%

0201

12PF

25V

NO STUFF

21

C4014

CERM

5%

12PF

25V

0201

NO STUFF

2

1

C4009

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C4007

BYPASS=U4000.R9::4mm

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C4013

0.1uF

20% 10V

402

CERM

35 86

2

1

C4005

10%

0.1UF

0201

CERM-X5R

6.3V

35 94

2 1

L4010

0402-LF

FERR-120-OHM-1.5A

2

1

C4003

BYPASS=U4000.B2::4mm

10UF

X5R

4V

20%

402

2

1

C4002

BYPASS=U4000.A1::4mm

X5R

10UF

402

20% 4V

40 43 48 69 76 85 86 95

2

1

R4022

MF

1/20W

201

1K

1%

2

1

R4023

201

1/20W

MF

1K

1%

L8

L3

G9G1F9E8E2D8D1B9B1

P9P1M9M1J8J2G8

E1

T9

T1

B3

A9

H1

M8

H9H2F1E9D2C9C1A8A1

R9R1N9N1K8K2G7

D9

B2

T2

J3

K1

M7

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

T7

T3

N7

R7

L7

P7

N3

U4000

4GB-DDR3-256MX16

K4B4G1646B-HYK0

CRITICAL

OMIT_TABLE

FBGA

35 94

2

1

C4011

10%

0.1UF

0201

CERM-X5R

6.3V

35 94

2

1

C4010

CERM-X5R

10%

0.1UF

0201

6.3V

35 94

35

35 94

2

1

R4020

201

1/20W MF

84.5

1%

35 94

2

1

R4021

201

NO STUFF

1/20W MF

82

1%

35 94

2

1

R4002

5%

201

1/20W

MF

1K

2

1

R4003

5%

201

1/20W

MF

NOSTUFF

1K

2

1

R4004

MF 201

1/20W

240

1%

21

R4030

5%

0

0201

1/20W

MF

CAM_WAKE:YES

2

1

C4016

C0G

5%

0201

100PF

25V

2

1

R4031

5%

0

0201

1/20W

MF

CAM_WAKE:NO

9

8

7

6

5

4

3

2

12

11

10

1

13

14

J4002

F-RT-SM

CRITICAL

CCR20-AK7100-1

21

C4061

X5R-CERM 0201

16V

0.1UF

10%

21

C4062

X5R-CERM 0201

16V

0.1UF

10%

2 1

L4011

NOSTUFF

0402-LF

FERR-120-OHM-1.5A

2

1

C4026

NO STUFF

C0G

25V 0201

100PF

5%

35 94

4

32

1

L4007

TAM0605

90-OHM-0.1A-0.7-2GHZ

CRITICAL

PLACE_NEAR=J4002.5:2.54MM

4

32

1

L4009

CRITICAL

TAM0605

90-OHM-0.1A-0.7-2GHZ

PLACE_NEAR=J4002.2:2.54MM

2

1

C4012

12PF

0201

5%

PLACE_NEAR=J4002.12:2mm

NP0-C0G 25V

2

1

C4018

0201

NP0-C0G

12PF

CRITICAL

25V

5%

2

1

C4017

12PF

CRITICAL

0201

NP0-C0G 25V

5%

3 1

4 2

Y4000

NO STUFF

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

CRITICAL

35

35 91

11 91

2

1

R4005

5%

201

1/20W MF

100K

19 90

SYNC_MASTER=CLEAN_X425

Camera 2 of 2

SYNC_DATE=10/30/2014

I2C_CAM_SCK

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL

I2C_CAM_SDA

MIPI_DATA_CONN_N

MIPI_CLK_CONN_P

MIPI_CLK_CONN_N

MEM_CAM_CKE

MEM_CAM_CLK_N

MEM_CAM_CLK_P

PP0V675_CAM_VREF

MEM_CAM_A<5>

MEM_CAM_A<4>

MEM_CAM_A<2>

MEM_CAM_A<1>

MEM_CAM_A<0>

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP0V675_MEM_CAM_VREFDQ

MEM_CAM_DQ<1>

MEM_CAM_DQ<6>

SYSCLK_CLK25M_CAMERA

CLK25M_CAM_CLKN

CAM_SENSOR_WAKE_L

CAM_SENSOR_WAKE_L_CONN

PP1V8_CAM

PCIE_CLK100M_CAMERA_N

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_P

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_C_P

PCIE_CLK100M_CAMERA_C_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_R2D_P

CLK25M_CAM_XTALP

CLK25M_CAM_XTALP_R

CLK25M_CAM_CLKP

MEM_CAM_A<14>

MEM_CAM_A<13>

MEM_CAM_BA<2>

CAM_SENSOR_WAKE_L_CONN

PP5V_S0

MEM_CAM_DQ<8>

MEM_CAM_BA<1>

MEM_CAM_A<11>

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

MEM_CAM_A<3>

MEM_CAM_A<6>

MEM_CAM_DM<0>

MEM_CAM_DQS_N<0>

MEM_CAM_DQ<7>

MEM_CAM_DQ<4>

MEM_CAM_DQ<3>

MEM_CAM_DQ<2>

MEM_CAM_DQ<0>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<12>

MEM_CAM_DQ<15>

MEM_CAM_DQ<14>

MEM_CAM_DQS_N<1>

MEM_CAM_DQS_P<0>

MEM_CAM_DM<1>

MEM_CAM_DQ<5>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<9>

MEM_CAM_DQ<13>

MEM_CAM_A<7> MEM_CAM_A<8>

MEM_CAM_A<10>

MEM_CAM_A<9>

MEM_CAM_A<12>

MEM_CAM_BA<0>

MEM_CAM_RAS_L MEM_CAM_CAS_L

MEM_CAM_CS_L

MEM_CAM_WE_L

MEM_CAM_CKE_R

PP5V_S3

CLK25M_CAM_XTALN

MIPI_CLK_P

MIPI_CLK_N

MIPI_DATA_P

MIPI_DATA_N

MIPI_DATA_CONN_P

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3RS0_ALSCAM_F

VOLTAGE=5V

MEM_CAM_ODT

PP1V35_CAM

VOLTAGE=0.675V

PP0V675_MEM_CAM_VREFCA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

<SCH_NUM>

40 OF 119

36 OF 97

86 94

35 94

94

35

36 86

35

36 86

18 19 49 58 59 62 63 66 67 73 79 80 84 85 86

21 60 66 67 84 86

86 94

86

94

35 94

94

OUT

IN

GND

VBUS

SSTX+

SSRXGND

SSTX-

D+

D-

GND SXRX+

SYM_VER-1

BI

IN

OUT

IN

OUT

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GND

THRM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

USB Port Power Switch

USB/SMC Debug Mux

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

SEL=1 Choose USB

SEL=0 Choose SMC

514-0934

Left USB Port A

13 90

21

L4605

PLACE_NEAR=J4600.1:5MM

CRITICAL

FERR-26-OHM-6A

0603

21

C4611

GND_VOID=TRUE

10%

X5R-CERM

16V

0.1UF

0201

21

C4610

GND_VOID=TRUE

0.1UF

10%

X5R-CERM

0201

16V

2

1

C4696

CRITICAL

220UF-35MOHM

POLY-TANT

6.3V

CASE-B2-SM1

20%

2

1

R4600

1%

22.1K

MF-LF

402

1/16W

2

1

R4601

MF

1%

22.1K

201

1/20W

21

R4651

5%

0

0201

1/20W

MF

NOSTUFF

21

R4652

5%

0

0201

1/20W

MF

NOSTUFF

1

8

2 3

9

19

18

17

16

15

14

13

12

23

22

21

20

11

10

7

4

6

5

J4600

USB3.0-J44-ALT

F-RT-TH

CRITICAL

4

32

1

L4600

TAM0605

90-OHM-0.1A-0.7-2GHZ

CRITICAL

2

1

D4601

CRITICAL

ESD112-B1-02ELS

0201-THICKSTNCL

2

1

D4600

0201-THICKSTNCL

CRITICAL

ESD112-B1-02ELS

2

1

D4610

ESD112-B1-02ELS

0201-THICKSTNCL

CRITICAL

GND_VOID=TRUE

2

1

D4611

0201-THICKSTNCL

ESD112-B1-02ELS

CRITICAL

GND_VOID=TRUE

2

1

D4612

ESD112-B1-02ELS

CRITICAL

GND_VOID=TRUE

0201-THICKSTNCL

2

1

D4613

GND_VOID=TRUE

ESD112-B1-02ELS

CRITICAL

0201-THICKSTNCL

2

1

C4607

25V

3.0PF

0201

NP0-C0G

+/-0.1PF

CRITICAL

2

1

C4606

5% 0201

CRITICAL

12PF

25V

NP0-C0G

2

1

C4695

603

10UF

X5R

20%

6.3V

2

1

C4691

402

10V

0.1UF

CERM

20%

13 90

2

1

C4650

402

10V

20%

CERM

0.1UF

2

1

R4650

5%

402

MF-LF

1/16W

100K

40 41 90

40

2

1

C4605

0402

16V

20%

0.01UF

X7R-CERM

18

2

1

C4690

603

6.3V

20%

10UF

X5R

2

1

R4690

0

5%

1/16W

402

MF-LF

2

1

C4692

10%

0402

X5R

10V

0.47UF

NOSTUFF

1 2

9

10

8

5 4

3

7 6

U4650

TQFN

PI3USB102EZLE

SIGNAL_MODEL=MOJO_MUX_USBONLY

CRITICAL

9

7

6

3

2

5

1

8

4

U4600

TPS2557DRB

CRITICAL

SON

SYNC_DATE=10/30/2014

USB 3.0 CONNECTORS

SYNC_MASTER=CLEAN_X425

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_LTUSB_A_F

VOLTAGE=5V

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

USB_LT1_N USB_LT1_P

USB3_EXTA_D2R_N

PP5V_S4

USB_EXTA_N

SMC_DEBUGPRT_EN_L

USB_EXTA_P

PP3V42_G3H

PM_SLP_S4_L

USB_ILIM

USB_EXTA_OC_L

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

USB_EXTA_MUXED_P

USB_ILIM_R

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_P USB3_EXTA_R2D_N

USB_EXTA_MUXED_N

USB3_EXTA_D2R_P

USB_PWR_EN

<SCH_NUM>

46 OF 119

37 OF 97

90

38 51 61 66 67 69 81 84 86

19 34 38 40 41 42 43 50 56 57 67 84 86

12 21 33 40 67 81 86

90

OUT

SYM_VER_2

G S

D

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7

INT*

ADDR

SCL SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4 P1_5 P1_6 P1_7

GND

OUT

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7

INT*

ADDR

SCL SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4 P1_5 P1_6 P1_7

GND

VDD

OUT_1

GND

THRM

OE

OUT_ALL#

OUT_3

OUT_2

IN_1

IN_3

IN_2

(IPD)

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IPD CONNECTOR

SMC Manual Reset & Isolation

PART WILL NOT WORK WITH BOOST.

LEFT SHIFT, OPTION & CONTROL KEYS COMBINED WITH POWER BUTTON CAUSE SMC RESET# ASSERTION.

Keys ANDed with PSoC power to isolate when PSoC is not powered.

(Write: 0x42 Read: 0x43)

311S0597

IO EXPANDER / KEYBOARD INTERFACE

311S0597

(Write: 0x40 Read: 0x41)

Pull-up in U5110.

No IPD on OE input pin PP3V3_S4 (symbol error).

APN 516S1035

CONNECT WITH 516S1037

Keyboard Connector

518S0752

2

1

C4821

BYPASS=U4820.B3:E2:2MM

10%

0201

CERM-X5R

6.3V

0.1UF

2

1

R4855

10K

MF

1/20W

201

5%

2

1

R4856

1/20W

201

10K

MF

5%

2

1

R4857

1/20W

10K

MF

201

5%

2

1

R4859

10K

MF

1/20W

201

5%

2

1

R4860

10K

MF

1/20W

201

5%

2

1

R4861

10K

MF

1/20W

201

5%

2

1

R4862

10K

MF

1/20W

201

5%

2

1

R4858

1/20W

10K

MF

201

5%

2

1

C4822

BYPASS=U4820.B4:E2:2MM

10%

0.1UF

CERM-X5R

6.3V 0201

2

1

C4801

C0G

25V

5%

100PF

0201

2

1

XW4801

SM

PLACE_NEAR=J4801:3MM

2

1

R4890

1/16W

0

5% MF-LF

402

NOSTUFF

2

1

R4891

MF-LF

5%

0

402

NOSTUFF

1/16W

2

1

C4803

CERM

10V

0.1uF

402

20%

2 1

L4803

0402-LF

FERR-120-OHM-1.5A

2

1

R4893

201

MF

1/20W

5%

100K

NOSTUFF

40 86

21

R4808

1/20W

5% MF 0201

0

9

87

6

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3231

30

3

29

2827

2625

2423

2221

20

2

19

1615

1413

1211

10

1

J4801

CRITICAL

F-ST-SM

DF40CG1.5-48DS-0.4V

2

1

C4808

10%

1.0UF

0402

CERM-X5R

PLACE_NEAR=J4801.7:5mm

35V

2

1

C4807

PLACE_NEAR=J4801.7:5mm

0.1UF

10% 35V CER-X5R 0201

2

1

C4806

PLACE_NEAR=J4801.7:5mm

0.1UF

10% 35V CER-X5R 0201

21

F4809

1812

2.5A-16V-0.1OHM

CRITICAL

2

1

C4805

2%

12PF

0402

CERM

100V

CRITICAL

2

1

C4804

12PF

5% NP0-C0G

25V

0201

CRITICAL

2

1

C4833

25V

12PF

CRITICAL

0201

NP0-C0G

5%

2

1

C4812

12PF

25V

0201

CRITICAL

5% NP0-C0G

2

1

C4811

0201 25V

NP0-C0G

5%

12PF

CRITICAL

41

2

1

C4850

0402

0.1UF

10%

X7R-CERM

16V

BYPASS=U4850.10:5:5 mm

2

1

C4824

10%

NOSTUFF

0.01UF

0201

10V

X5R-CERM

2

1

R4821

MF

1/20W

201

5%

10K

2 1

R4824

MF

1/20W

0201

5%

0

NOSTUFF

2

1

R4840

100K

1%

1/16W

402

MF-LF

2

1

3

Q4840

DFN1006H4-3

DMN32D2LFB4

2

1

R4820

201

5% 1/20W MF

100K

2

1

C4834

X5R-CERM

0.01UF

NOSTUFF

10% 10V

0201

2

1

R4831

1/20W

10K

5% MF

201

2

1

R4830

MF

5% 1/20W

100K

201

2

1

C4830

1UF

6.3V 402

CERM

10%

BYPASS=U4830.B4:E2:5MM

B4

B3

A4

A5

A2

C4

C5

D5

D4

E5

D3

E4

E3

D2

E1

D1

C2

C1

B1

C3

A1A3

E2

B5

U4830

VFBGA

PCAL6416A

2

1

C4831

10%

0.1UF

0201

BYPASS=U4830.B3:E2:2MM

6.3V CERM-X5R

2

1

C4832

10%

6.3V 0201

CERM-X5R

0.1UF

BYPASS=U4830.B4:E2:2MM

38 40 41 86

2

1

C4820

10%

6.3V

BYPASS=U4820.B4:E2:5MM

1UF

402

CERM

2

1

C4810

0.1UF

20% 402

CERM

10V

PLACE_NEAR=J4813.5:5MM

21

R4810

5%

MF-LF

402

1/16W

1K

21

R4815

0

MF-LF

1/16W

402

5%

21

R4814

402

1%

113

MF-LF

1/16W

9 8 7 6 5 4

30

3

29 28 27 26 25 24 23 22 21 20

2

19 18 17 16 15 14 13 12 11 10

1

32

31

J4813

CRITICAL

FF14A-30C-R11DL-B-3H

F-RT-SM

B4

B3

A4

A5

A2

C4

C5

D5

D4

E5

D3

E4

E3

D2

E1

D1

C2

C1

B1

C3

A1A3

E2

B5

U4820

VFBGA

PCAL6416A

10

11

6

7

8

9

4

3

2

1

5

U4850

SLG4AP4103

TQFN

2

1

R4822

5%

201

1/20W

MF

2.0K

2

1

R4823

2.0K

MF

1/20W

201

5%

2

1

R4802

1/20W

10K

5% MF

201

2

1

R4801

201

MF

5%

10K

1/20W

2

1

R4852

10K

MF

201

5%

1/20W

2

1

R4853

10K

MF

1/20W

201

5%

2

1

R4854

10K

201

5%

1/20W

MF

SYNC_MASTER=CLEAN_X425G

SYNC_DATE=09/10/2014

KEYBOARD/TRACKPAD (1 OF 2)

SMC_ACTUATOR_EN_L

PP3V42_G3H

PP3V3_S4

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_S4_TPAD_F

VOLTAGE=28V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

PPVIN_S4_TPAD_FUSE

TPAD_ACTUATOR_THRMTRIP_L

GND_ACTUATOR

I2C_IOXP_SCL

TPAD_SPI_BUS_EN

PP3V3_S4

TPAD_SPI_SCLK

IOXP2_INT_L

WS_CONTROL_KBD

TPAD_SPI_CS_L

SMC_ACTUATOR_EN_R_L SMBUS_SMC_2_S3_SCL TPAD_NC3

PP3V3_S4

IOXP1_LED_DRV

USB_TPAD_N

I2C_IOXP_SDA

TPAD_NC4

SMC_PME_S4_WAKE_L

TPAD_SPI_INT_L

PP3V3_S4

SMC_LID

WS_LEFT_SHIFT_KEY

I2C_IOXP_SCL

WS_LEFT_OPTION_KEY

WS_KBD14

WS_KBD11

WS_KBD18

WS_KBD7

WS_KBD6

IOXP1_RESET_L

I2C_IOXP_SDA

SMC_ONOFF_L

WS_KBD16N

WS_KBD2

WS_KBD_ONOFF_L

WS_KBD15_C

WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD13

WS_KBD11 WS_KBD12

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD19

WS_KBD22 WS_KBD23

WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

WS_KBD7 WS_KBD8

WS_KBD16_NUM

WS_KBD15_CAP

IOXP1_INT_L

SMC_TPAD_RST_L

WS_CONTROL_KEY

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KEY

PP3V3_S4

IOXP1_DEBUG SMC_ONOFF_L WS_KBD16N

TP_IOXP1_4

TP_IOXP1_2 TP_IOXP1_3

TP_IOXP1_0 TP_IOXP1_1

I2C_IOXP_SDA

I2C_IOXP_SCL

WS_KBD21

WS_KBD22

WS_KBD20

WS_KBD4

WS_KBD1

WS_KBD2

WS_KBD23

WS_KBD15_C

PP3V3_S4

WS_KBD5

WS_KBD1

WS_KBD20

WS_KBD3

WS_KBD10

IOXP2_RESET_L

WS_KBD19

PP3V3_S4

WS_KBD17

WS_KBD8

WS_KBD9

PP3V3_S4

WS_KBD12

WS_CONTROL_KEY

WS_LEFT_SHIFT_KEY

WS_KBD13

TPAD_SPI_MISO

TPAD_SPI_MOSI

PP5V_S4

USB_TPAD_P

PP3V42_G3H

IOXP2_INT_L

SMBUS_SMC_2_S3_SDA

PPVIN_S4_TPAD

TPAD_VBUS_EN

GND_ACTUATOR

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

<SCH_NUM>

38 OF 97

48 OF 119

19 34 37 38 40 41 42 43 50 56 57 67 84 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

65 86

38 86

85

20 33 38 41 42 45 46 65 66 67 81 84 85 86

85 91

38 86

85 91

40 43 86 95

20 33 38 41 42 45 46 65 66 67 81 84 85 86

13 86 90

38 86

33 40 42

86

85

20 33 38 41 42 45 46 65 66 67 81 84 85 86

38

38 86

38

38 86

38

38 86

86

38

38 86

86

38

38 86

38

20 33 38 41 42 45 46 65 66 67 81 84 85 86

38 40 41 86

38

38 86

38

20 33 38 41 42 45 46 65 66 67 81 84 85 86

38 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

38 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

38 86

38

38 86

85 91

37 51 61 66 67 69 81 84 86

13 86 90

19 34 37 38 40 41 42 43 50 56 57 67 84 86

38 86

40 43 86 95

45 84 86

67 86

38 86

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

516S0899

.

Keyboard Backlight Connector

9

8 7

6 5

4 3

2

10

1

14

13

12

11

J4915

CRITICAL

AA07A-S010-VA1

F-ST-SM

SYNC_MASTER=CLEAN_MAXWELL

KEYBOARD/TRACKPAD (2 OF 2)

SYNC_DATE=07/02/2014

KBDBKLT_RETURN1

KBDBKLT_RETURN2

PPVOUT_S0_KBDBKLT

<SCH_NUM>

49 OF 119

39 OF 97

63 86

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI BI BI BI

IN IN

IN BI OUT

IN OUT

BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT OUT OUT OUT

OUT

IN

OUT

OUT OUT OUT

IN

OUT

IN

OUT

OUT OUT

NC

OUT

BI OUT

IN OUT

OUT

IN

OUT

IN

OUT

IN

IN OUT

OUT

BI

IN

NC

OUT

IN

OUT

BI

IN

BI

OUT

BI

NC

OUT

IN

BI

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OD)

H10

G4

H3

H4

J3

K4

K3

L7

K7

E12

E13

E11

F11

M1

L3

C5 D5

C8

A9

B9

C9

F3

F4

N9

M9

K10

L10

N1

L4

M3

M2

L6

M6

K5

N6

N5

F5

E4

D4

K6

D8

L5

J13

J12

M5

L12

M13

M11

N11

N12

L11

D10

G3

L13

H11

A12

C11

B12

J2

J4

K9

L9

C6

C4

L1

H13

F12

C13

F13

D12

G11

H12

D11

C12

A13

B13

N3

N4

M7

N7

K8

L8

M8

N8

N2

M4

D13

E10

L2

K1

K2

A8

B8

A7

B7

H2

H1

G1

G2

B2

B1

C2

C1

A6

B6

A5

B5

A4

B4

A3

B3

F1

F2

E1

E2

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

N10

M10

N13

D2 D1

D6

K13

J6

J1

D3

J10

J9

J7

F10

E9

E8

E6

D7

K12

B10

A11

A10

C10G10

B11

G13

G12

A2

M12

E3

C3

J11

J8

J5

H9

H5

F9

E5

D9

K11

C7

A1

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

2 1

XW5000

SM

PLACE_NEAR=U5000.A1:4MM

41 50 57 86

2

1

C5014

6.3V

10%

0201

CERM-X5R

0.1UF

2

1

C5015

6.3V

10%

0201

CERM-X5R

0.1UF

2

1

C5016

6.3V

10%

0201

CERM-X5R

0.1UF

2

1

C5017

6.3V

10%

0201

CERM-X5R

0.1UF

2

1

C5013

6.3V

10%

0201

CERM-X5R

0.1UF

41

2

1

R5002

1/20W

5%

201

MF

1M

2

1

C5006

16V

10% 0201

X5R-CERM

0.1UF

2

1

C5005

16V

10% 0201

X5R-CERM

0.1UF

2

1

C5009

16V

10%

0201

X5R-CERM

0.1UF

2

1

C5008

16V

10%

0201

X5R-CERM

0.1UF

2

1

C5004

16V

10% 0201

X5R-CERM

0.1UF

2

1

C5003

16V

10% 0201

X5R-CERM

0.1UF

2

1

C5007

16V

10%

0201

X5R-CERM

0.1UF

13 82 91

19 91

13 82 91

20

13

12

12 20

14

36 43 48 69 76 85 86 95

43 48 95

38 43 86 95

42 95

42

43 56 57 86 95

42 45

42 44

42 45

42 44

42 45

42 44

42 46

42 44

42 46

42 47

42 45

42 47

42 46

42 47

42 45

41 61 67

12 86 91

19 29 30 41

41

37 41 90

42

50 91

37

42 82

18 19 58 67 86

41

12 18 91

12 19 86 91

2

1

C5001

6.3V

10%

0201

CERM-X5R

0.1UF

14

41

49

63

49

42

33 38 42 86

38 41 42 86

41

41 42 56 57

41

12 21 67 86

12 21 33 37 67 81 86

12 67

38 41 86

20 28 41 42

41 67

12 30 42

33 41 86

42

41

61 67

19 41

21

L5001

0402

30-OHM-1.7A

6

41 58 89

34

42

34

2

1

C5011

25V

10% 402

X5R

1UF

2

1

C5010

25V

10% 402

X5R

1UF

2

1

C5012

25V

10% 402

X5R

1UF

56

12 18 19 86 91

41

6

89

42

12 41

42 82

2

1

C5020

10V

10% 0201

X5R-CERM

0.01UF

2

1

C5021

6.3V

10% 402

CERM

1UF

2

1

C5002

6.3V

10% 402

CERM

1UF

42

33 67

34

38 86

65

42

SYNC_MASTER=CLEAN_X305

SYNC_DATE=01/15/2014

SMC

SMC_X87_ISENSE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SDA

SMC_GPUCORE_ISENSE

ALL_SYS_PWRGD

SMC_GFX_OVERTEMP

SMC_DEBUGPRT_EN_L

SMC_ACTUATOR_DISABLE_L SMC_GFX_SELF_THROTTLE SYS_ONEWIRE

LPC_CLK33M_SMC

LPC_AD<1> LPC_AD<2> LPC_AD<3>

LPC_AD<0>

SMC_LID

SMC_ACTUATOR_EN_L

SMC_S4_WAKESRC_EN

SMC_PME_S4_DARK_L

SMC_PME_S4_WAKE_L

SMC_TOPBLK_SWP_L

SMC_DP_HPD_L

SMC_GPU_HI_ISENSE

NC_SMBUS_SMC_3_SCL

SMS_INT_L

SMC_PM_G2_EN

CPU_THRMTRIP_3V3

G3_POWERON_L

SMC_BC_ACOK

SMC_FAN_1_CTL

SMC_THRMTRIP

SMC_DCIN_ISENSE

SMC_OOB1_R2D_L NC_IR_RX_OUT_RC NC_SMC_TPAD_BOOST_DISABLE_L

PM_BATLOW_L

PM_PWRBTN_L

NC_MEM_EVENT_L SMC_ADAPTER_EN

PM_SLP_S3_L

PM_SLP_S5_L

SMC_TX_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_2_S3_SCL

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA

SMC_CPU_HI_ISENSE

SMC_LCDPANEL_ISENSE

SPI_DESCRIPTOR_OVERRIDE_L

SMC_CPUDDR_ISENSE

SMC_XTAL

SMC_TDI

SMC_GPU0V95_ISENSE

SMC_GPUCORE_VSENSE

SMC_PCH_CORE_ISENSE

SMC_DEBUGPRT_TX_L

SMC_TBT_ISENSE

SMC_TPAD_ISENSE

SMC_CPUPKG_VSENSE

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

SMC_RESET_L

SMC_OTHER5V_HI_ISENSE

SMC_PBUS_VSENSE

SMC_TDO

SMC_WAKE_L

SMC_CPUPKG_ISENSE

SMC_OOB1_D2R_L

SMC_EXTAL

SMC_CLK32K

WIFI_EVENT_L

PM_SYSRST_L

CPU_CATERR_L

CPU_PROCHOT_L

SMC_GPU_FB_VSENSE

SMC_GPU_VDDCI_ISENSE

SMC_DCIN_VSENSE

SMBUS_SMC_5_G3_SDA

PM_CLKRUN_L

SMBUS_SMC_0_S0_SDA

SMC_TCK

SMBUS_SMC_5_G3_SCL

SMC_TMS

SMC_OTHER3V3_HI_ISENSE

SMC_CHGR_BMON_ISENSE

SMC_SSD_ISENSE

SMC_P1V35MEM_ISENSE

PP3V42_G3H

PM_WLAN_EN

PM_SLP_S4_L

SMC_ONOFF_L

SMC_RX_L

SMC_PWRFAIL_WARN_L

SMC_BIL_BUTTON_L

SMC_PECI_L

NC_HISIDE_ISENSE_OC

SMC_FAN_0_TACH

CPU_PECI_R

TP_SMC_MPM5_LED_CHG

SMC_FAN_1_TACH

SMC_SYS_KBDLED

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.2V

PP1V2_S5_SMC_VDDC

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S5_SMC_VDDA

NC_SMBUS_SMC_3_SDA

LPC_PWRDWN_L

LPC_SERIRQ

SMC_LRESET_L

SMC_PCH_SUSACK_L

SMC_PCH_SUSWARN_L

LPC_FRAME_L

SMC_GPU_FB_ISENSE

SMC_S5_PWRGD_VIN

SMC_VCCIO_CPU_DIV2

SMC_FAN_0_CTL

SMC_WAKE_SCI_L

SMC_RUNTIME_SCI_L

SMC_DEBUGPRT_RX_L

SMC_PROCHOT

PM_DSW_PWRGD SMC_DELAYED_PWRGD

PM_PCH_SYS_PWROK

S5_PWRGD

SPI_SMC_CS_L

SPI_SMC_CLK

SPI_SMC_MOSI

NC_SMC_SYS_LED

SPI_SMC_MISO

SMC_GFX_PWR_LEVEL_L

<SCH_NUM>

50 OF 119

40 OF 97

41

41 44 45 46 47

41 86

41

41 50 86

19 34 37 38 41 42 43 50 56 57 67 84 86

41

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

BI

OUT

SYM_VER_2

G S

D

SN0903049

PAD

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

VER 3

D

S G

VER 3

D

S G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Mac Mini: 5V

NOTE: Internal pull-ups are to VIN, not V+.

From/To CPU/PCH

SMC12 PECI SUPPORT

From SMC

To SMC

(IPU) (IPU)

Mobiles: 3.42V

SMC Crystal Circuit

MR1* and MR2* must both be low to cause manual reset.

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

SMC Reset "Button", Supervisor & AVREF Supply

Used on mobiles to support SMC reset via keyboard.

Debug Power "Buttons"

21

R5170

5%

201

1/20W

MF

10K

21

R5171

5%

201

1/20W

MF

100K

21

R5173

5%

201

1/20W

MF

10K

21

R5174

5%

201

1/20W

MF

100K

21

R5177

5%

201

1/20W

MF

10K

21

R5178

5%

201

1/20W

MF

10K

21

R5179

5%

201

1/20W

MF

10K

21

R5180

5%

201

1/20W

MF

10K

21

R5185

5%

201

1/20W

MF

10K

40 41

14 42 91

2

1

R5115

5%

0

OMIT

1/10W MF-LF 603

SILK_PART=PWR_BTN

PLACE_SIDE=BOTTOM

6

40 58 89

40

21

R5189

5%

201

1/20W

MF

10K

21

R5181

5%

201

1/20W

MF

10K

21

R5187

5%

201

1/20W

MF

470K

21

R5193

5%

201

1/20W

MF

10K

21

R5172

5%

201

1/20W

MF

10K

2

1

R5116

5%

0

PLACE_SIDE=TOP

MF-LF

SILK_PART=PWR_BTN

603

OMIT

1/10W

2

1

R5101

5%

0

PLACE_SIDE=BOTTOM

1/10W MF-LF 603

SILK_PART=SMC_RST

OMIT

38 40 41 86

38

2

1

C5101

0201

X5R-CERM

10%

0.01UF

10V

2

1

C5125

20%

10uF

X5R 603

6.3V 2

1

C5126

0201

10V

10%

0.01UF

X5R-CERM

40 50 57 86

12

21

R5112

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.Y6:5.1mm

40

21

R5190

5%

201

1/20W

MF

100K

21

R5175

5%

201

1/20W

MF

20K

21

R5176

5%

201

1/20W

MF

20K

21

R5186

5%

201

1/20W

MF

10K

21

R5169

5%

201

1/20W

MF

100K

2

1

R5131

5%

201

1/20W MF

330

2

1

R5133

NONE

NOSTUFF

OMIT

0201

21

R5132

5%

0

0201

1/20W

MF

40

2

1

R5197

201

1/20W MF

100K

1%

2

1

R5196

201

1/20W MF

100K

1%

21

R5192

5%

201

1/20W

MF

100K

40 41

6

14 89

21

R5194

5%

201

1/20W

MF

100K

21

R5195

5%

201

1/20W

MF

10K

NOSTUFF

2

3

1

Q5158

CRITICAL

MMBT3904LP-7

DFN1006-3

21

R5134

5%

201

1/20W

MF

43

40

6

14 89

38 40 41 86

21

R5158

5%

201

1/20W

MF

3.3K

21

R5198

5%

201

1/20W

MF

100K

21

R5191

5%

201

1/20W

MF

100K

2

1

C5111

12PF

25V 0201

5% CERM

2

1

C5110

12PF

25V

5% CERM

0201

21

R5110

201

MF

2.49K

1/20W

1%

31

42

Y5110

12.000MHZ-30PPM-10PF-85C

CRITICAL

3.2X2.5MM-SM-1

2

1

C5120

0.47UF

CERM-X5R

402

10%

6.3V

2

1

C5127

X5R 402

4.7UF

6.3V

20%

NO STUFF

2

1

R5100

5%

201

1/20W MF

100K

21

R5127

402

MF-LF

1/16W

5%

0

2

1

3

Q5130

DMN32D2LFB4

DFN1006H4-3

CRITICAL

3

1

9

5

8

7

6

2

4

U5110

CRITICAL

DFN

VREF-3.3V-VDET-3.0V

4

5

3

Q5159

DMN5L06VK-7

SOT563

1

2

6

Q5159

DMN5L06VK-7

SOT563

SMC Shared Support

SYNC_DATE=06/24/2014

SYNC_MASTER=CLEAN_X305

SMC_XTAL_R

SMC_EXTAL

SPI_DESCRIPTOR_OVERRIDE_L

SMC_THRMTRIP

CPU_THRMTRIP_3V3

SMC_LID

PP3V42_G3H

MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

SMC_TPAD_RST_L

SMC_RESET_L

SMC_MANUAL_RST_L

SMC_ONOFF_L

SMC_XTAL

PP1V05_S0

PM_THRMTRIP_B_L

PM_THRMTRIP_L

SMC_CLK32K

SMC_PECI_L

SMC_PECI_L_R

SMC_RX_L

G3_POWERON_L

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_PME_S4_DARK_L

SMC_TDO

SMC_S5_PWRGD_VIN

SMC_DELAYED_PWRGD

SMC_S4_WAKESRC_EN

SMC_PM_G2_EN

WIFI_EVENT_L

SMC_DEBUGPRT_RX_L

SMC_ONOFF_L

SMC_TCK

SMC_TX_L

SMC_BIL_BUTTON_L

SMC_TDI

SMC_BC_ACOK

SMS_INT_L

PP1V05_S0

PP3V3_WLAN

PP3V42_G3H

PP3V3_S4

CPU_PECI

CPU_PECI_R

SMC_VCCIO_CPU_DIV2

CPU_THRMTRIP_3V3

SMC_ADAPTER_EN

PM_CLK32K_SUSCLK_R

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

PP3V42_G3H_SMC_SPVSRPP3V42_G3H

SMC_ONOFF_L

PM_THRMTRIP_L_R

SMC_THRMTRIP

CPU_PROCHOT_L

SMC_PROCHOT

<SCH_NUM>

51 OF 119

41 OF 97

40

19 40

40 41

38 40 42 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

40 44 45 46 47

40 86

40

10 14 15 17 18 41 62 67 84 86

40

37 40 90

40 50 86

20 28 40 42

40

19 29 30 40

40 67

40 61 67

33 40 86

37 40 90

38 40 41 86

40 50 86

40

40 42 56 57

40

10 14 15 17 18 41 62 67 84 86

33 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

20 33 38 42 45 46 65 66 67 81 84 85 86

40

12 40

19 34 37 38

40 41

42 43

50 56

57 67

84 86

IN

OUT

SYM_VER_2

GS

D

IN

NC

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APN: 998-3029

Hall Effect pads

Spare S4 IRQ

GPU HI ISENSE

40 42 47

40 42 44

40 42 46

40 42 45

40 42 44

40 42 45

40 42 44

40 42 45

40 41 42 56 57

40 42 47

40 42 45

40 42 47

40 42 46

40 42 45

40 42 47

40 42 82

14 41 91

2

1

3

Q5260

CRITICAL

DMN32D2LFB4

DFN1006H4-3

40 82

8 7 6 54

3

2

1

J5250

SM

HALL-SENSOR-MLB-PADS-K99

OMIT_TABLE

2

1

C5250

50V

10% 0402

X7R-CERM

0.001UF

21

R5250

1/20W

5%

0201

MF

0

40

12 30 40 42

21

R5283

1/20W

5%

201

MF

1K

33 38 40 42 86

12 30 40 42

12

2

1

R5282

1/20W

5%

201

MF

100K

33 38 40 42 86

2

1

R5259

5% 1/20W

201

MF

100K

40

21

R5230

0

SMC_SUSACK:YES

1/20W

5%

201

MF

12

21

R5231

1/20W

5%

201

MF

0

SMC_SUSACK:YES

40

40 12

40 42 47

J5250

1

607-6811

SUBASSY,PCBA HALL EFFECT,K99

CRITICAL

SMC Project Support

PM_THRMTRIP_L_R

SMC_GFX_OVERTEMP

SMC_DCIN_VSENSE

SMC_PBUS_VSENSE

SMC_P1V35MEM_ISENSE

MAKE_BASE=TRUE

SMC_LCDPANEL_ISENSE

SMC_SSD_ISENSE

SMC_TBT_ISENSE

NC_SMBUS_SMC_4_ASF_SDA

NC_SMC_TPAD_BOOST_DISABLE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_PME_S4_DARK_L SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_EVENT_L

PCH_SUSWARN_L

NC_SMBUS_SMC_3_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_3_SCL

SMC_PCH_SUSWARN_L

SMC_DP_HPD_L

SMC_PCH_SUSACK_L

SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L

PCH_SUSACK_L

PCH_STRP_TOPBLK_SWP_L

SMC_TOPBLK_SWP_L

MAKE_BASE=TRUE

NC_SMC_SYS_LED

NO_TEST=TRUE

PP3V42_G3H

SMC_LID_R

PP3V3_S4

SMC_GPU_VDDCI_ISENSE

SMC_LID

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

PP3V3_S4

PM_BATLOW_L

NC_SMC_TPAD_BOOST_DISABLE_L

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

NO_TEST=TRUE

NC_SMBUS_SMC_3_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

NC_SMBUS_SMC_4_ASF_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

SMC_CHGR_BMON_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

SMC_CPUPKG_VSENSE

MAKE_BASE=TRUE

SMC_GPU_VDDCI_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

SMC_OTHER5V_HI_ISENSE

SMC_CPU_HI_ISENSE

SMC_CHGR_BMON_ISENSE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSE

SMC_CPUPKG_ISENSE

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

SMC_GFX_SELF_THROTTLE SMC_GFX_PWR_LEVEL_L

MAKE_BASE=TRUE

SMC_P1V35MEM_ISENSE

SMC_OTHER3V3_HI_ISENSE

SMC_CPUPKG_VSENSE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_BC_ACOK

NC_MEM_EVENT_L

NC_SMC_SYS_LED

SMC_GFX_PWR_LEVEL_L

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

SMC_TPAD_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OCNC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_CPUPKG_ISENSE

NC_IR_RX_OUT_RC SMC_GFX_SELF_THROTTLE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

MAKE_BASE=TRUE

SMC_GPUCORE_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

SMC_GPU0V95_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE SMC_GPUCORE_ISENSE

SMC_GPUCORE_VSENSE

MAKE_BASE=TRUE

SMC_GPU_FB_ISENSE SMC_GPU_FB_VSENSE SMC_X87_ISENSE

MAKE_BASE=TRUE

SMC_X87_ISENSE

SMC_GPUCORE_VSENSE

MAKE_BASE=TRUE

SMC_GPU_FB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_FB_VSENSE

SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUE

SMC_PCH_CORE_ISENSE

SMC_GPU0V95_ISENSE

<SCH_NUM>

52 OF 119

42 OF 97

40 42 44

40 42 45

40 42

20 28 40 41 42

40 42

40 42 95

40 42

40 42 95

40 42

19 34 37 38 40 41 43

50 56 57 67 84

86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

40 42 47

38 40 41 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

40 42

40 42 95

20 28 40 41 42

40 42

40 42 44

40 42 45

40 42 46

40 42 82

40 42 45

40 42 44

40 42 45

40 41 42 56 57

40 42

40 42 82

40 42 46

40 42 45

40 42 40 42

40 42

40 42 82

40 42 47

40 42 46

40 42 47

40 42 45

40 42 47

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Trackpad

(Write: 0x98 Read: 0x99)

J4801

SMC "1" SMBUS CONNECTIONS

CPU/DDR3/PCH/AIRFLOW TEMP

EMC1414-A: U5870

(Write: 0x98 Read: 0x99)

(MASTER)

U5000

eDP Connector

(Write: 0x86 Read: 0x87)

PCH "SMLink 0" Connections

XDP Connectors

J1800 & J1850

(MASTER)

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "2" SMBUS CONNECTIONS

(WRITE: 0xCC READ: 0xCD)

(MASTER)

HDMI Redriver (on RIO)

Need to check with SMC team

L&R Fin Stack Temp

(MASTER)

SMC "0" SMBus Connections

GPU

J9510 -> U9700

(Write: 0x72 Read: 0x73)

Lynx Point

(MASTER)

U9100

Unused

U5000

(MASTER)

DPMUX IC

Lynx Point

SMLink 1 is slave port to

U1100

(MASTER)

U1100

(MASTER)

SMC

(MASTER)

U5000

SMC

SMC "5" SMBUS CONNECTIONS

J7050

(Write: 0x16 Read: 0x17)

Battery

Battery Charger

U5000

(MASTER)

SMC

U5000

Unused

SMC "3" SMBUS CONNECTIONS

PCH "SMLink 1" Connections

access PCH & CPU via PECI.

(Write: 0x88 Read: 0x89)

U1100

Lynx Point

(Write: 0x12 Read: 0x13)

ISL6258 - U7100

U5000

SMC

PCH SMBus "0" Connections

EMC1414-A: U5850

DPMUX IC

U9100

(MASTER)

(WRITE: 0X92 READ: 0X93)

TMP105: U5823

X87 TEMP

J8300

SMC "4" SMBUS CONNECTIONS

(Write: 0x98 Read: 0x99)

J4002

ALS

U8400

NEED CONFIRM FROM AMD

(Write: 0x?? Read: 0x??)

SMC

2

1

R5380

2.0K

MF

1/20W

201

5%

2

1

R5381

5%

201

1/20W MF

2.0K

2

1

R5370

1K

5%

MF

1/20W

201

2

1

R5371

1K

MF

1/20W

201

5%

2

1

R5351

201

1/20W MF

2.0K

5%

2

1

R5350

201

1/20W

MF

5%

2.0K

2

1

R5310

5%

8.2K

MF-LF

402

1/16W

2

1

R5311

5%

8.2K

MF-LF 402

1/16W

2

1

R5321

NO STUFF

5%

201

1/20W MF

8.2K

2

1

R5320

NO STUFF

5%

201

1/20W

MF

8.2K

21

R5323

MF

1/20W

0201

0

5%

21

R5322

MF

1/20W

0201

0

5%

2

1

R5301

1/16W

402

MF-LF

1K

5%

2

1

R5300

1/16W

402

MF-LF

1K

5%

2

1

R5361

5%

1K

201

MF

1/20W

2

1

R5360

5%

201

1/20W

MF

1K

2

1

R5335

1/20W

5%

201

MF

2.0K

2

1

R5334

5%

MF

1/20W

201

2.0K

SYNC_DATE=08/11/2014

SYNC_MASTER=CLEAN_X305G

SMBus Connections

PP3V3_S3

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

PP3V3_S0

I2C_DPMUX_UC_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SDA

I2C_DPMUX_UC_SCL

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SML_PCH_1_DATA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SML_PCH_1_CLK

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V42_G3H

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V3_S0

I2C_DPMUX_UC_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

PP3V3_S0

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_0_CLK

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_PCH_CLK

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK

NC_I2C_DPMUX_A_SCL

NC_I2C_DPMUX_A_SDA

MAKE_BASE=TRUE

NC_I2C_DPMUX_A_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_I2C_DPMUX_A_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

PP3V3_S0

SMBUS_SMC_1_S0_SCL

<SCH_NUM>

53 OF 119

43 OF 97

13 20 21 45 46 66 81 82 84 86

36 40 43 48 69 76

85 86 95

36 40 43 48 69 76

85 86 95

36 40 43 48 69 76

85 86 95

36 40 43 48 69 76

85 86 95

36 40 43 48 69 76

85 86 95

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

43 82

38 40 43 86 95

13 91

40

43 56 57 86 95

13 91

38 40 43 86 95

40 43 56 57 86 95

40 43 48 95

40 43 56 57 86 95

19 34 37 38 40 41 42 50 56 57 67 84 86

40 43 48 95

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

36 40 43 48 69 76

85 86 95

40 43 56 57 86 95

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

43 82

36 40 43 48 69 76 85 86

95

40 43 48 95

38 40 43 86 95

36 40 43 48 69 76 85 86

95

36 40 43 48 69 76 85 86

95

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

13 91

13 18 43 81 85 86

91

13 18 43 81 85 86 91

13 18 43 81 85 86

91

13 18 43 81 85 86 91

43 82

43 82 43 82

43 82

36

40 43 48 69 76

85 86 95

36

40 43 48 69 76

85

86 95

36 40 43 48 69 76 85 86

95

40

43 56 57 86 95

38

40 43 86 95

38

40 43 86 95

40 43 48

95

40 43 48

95

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 43 48 95

IN

OUT

IN

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

IN-

IN+ REF

V+

GND

D

S

G

S

D

P-CH

N-CH

OUT

IN-

IN+ REF

V+

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OTHERS (5V) High Side Current Sense / Filter

Gain:100x

Power Drop across R5400 at EDP becomes 1.21W

EDP Current:21.6A

COMPUTING High Side Current Sense / Filter

Enables DC-In VSense

Divider set for Vin max of 22.32V

SMC_ADC5

RTHEVENIN = 4567 Ohms

SMC KEY VD0R

SMC Key VP0R

Enables PBUS VSense

divider when SUS present.

SMC_ADC3

EDP Current:5A

Gain:100x

OTHERS (3.3V) High Side Current Sense / Filter

SMC Key IC0R

PBUS Voltage Sense Enable & Filter

divider when in S0.

RTHEVENIN = 4508 Ohms

Divider set for Vin max of 13.98V

SMC_ADC4

SMC Key ID0R

EDP Current:4.6A

IPBR

SMC_ADC7

SMC_ADC8

SMC_ADC9

SMC Key IO3R

Gain:100x

EDP Current:5A

DC-IN (AMON) Current Sense Filter

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER

From charger

DC-In Voltage Sense Enable & Filter

SMC Key IO5R SMC_ADC13

57

40 42 57

2

1

C5403

0.22UF

PLACE_NEAR=U5000.B5:5MM

0201

20%

6.3V X5R

21

R5403

4.53K

PLACE_NEAR=U5000.B5:5MM

201

1/20W

MF

1%

40 42

21

R5433

PLACE_NEAR=U5000.A5:5MM

4.53K

1/20W

201

MF

1%

2

1

C5433

PLACE_NEAR=U5000.A5:5MM

0201

6.3V X5R

0.22UF

20%

40 42

2

1

C5401

20%

0.1UF

402

10V CERM

2

1

C5431

402

0.1UF

20%

CERM

10V

432

1

R5430

CRITICAL

MF 1W

0612-6

0.005

1%

40 42

2

1

C5421

0.022UF

10%

6.3V

PLACE_NEAR=U5000.A4:5MM

X5R-CERM 0201

21

R5423

1/20W

45.3K

PLACE_NEAR=U5000.A4:5MM

201

MF

1%

21

R5441

PLACE_NEAR=U5000.B3:5MM

201

1/20W

45.3K

MF

1%

2

1

C5441

PLACE_NEAR=U5000.B3:5MM

0201

2200PF

X7R-CERM

10V

10%

2

1

R5402

100K

1/16W MF-LF

402

1%

31 32 67

40 42

2

1

R5401

19.1K

1/20W

201

PLACE_NEAR=U5000.A3:5MM

MF

1%

2

1

C5404

6.3V

20%

0.22UF

X5R 0201

PLACE_NEAR=U5000.A3:5MM

2

1

R5404

1/20W

201

PLACE_NEAR=U5000.A3:5MM

5.90K

MF

1%

4

1

5

2

3

6

Q5400

SOT-963

CRITICAL

NTUD3169CZ

2

1

R5405

1/16W MF-LF

402

100K

1%

40 42

2

1

R5412

1/16W

402

MF-LF

100K

1%

12 66 67

2

1

R5413

201

30.9K

1/20W

PLACE_NEAR=U5000.F1:5MM

MF

1%

2

1

C5414

X5R 0201

PLACE_NEAR=U5000.F1:5MM

0.22UF

20%

6.3V

2

1

R5414

201

PLACE_NEAR=U5000.F1:5MM

1/20W

5.36K

MF

1%

2

1

R5411

1/16W

402

MF-LF

100K

1%

2

1

R5409

402

20K

1/16W MF-LF

5%

PLACE_NEAR=U5400.6:5MM

2

1

R5439

402

20K

PLACE_NEAR=U5430.6:5MM

5% 1/16W MF-LF

40 42

2

1

C5426

20% X5R

0201

6.3V

0.22UF

PLACE_NEAR=U5000.C2:5MM

21

R5426

201

4.53K

1/20W

PLACE_NEAR=U5000.C2:5MM

MF

1%

2

1

R5429

402

20K

PLACE_NEAR=U5420.6:5MM

MF-LF

1/16W

5%

2

1

C5422

10V CERM

20%

0.1UF

402

432

1

R5420

CRITICAL

MF 1W

0612-6

0.005

1%

3

1

6

4

5

2

U5430

INA214

CRITICAL

SC70

3

1

6

4

5

2

U5420

SC70

CRITICAL

INA214

4

1

5

2

3

6

Q5410

SOT963

DMC31D5UDJ

432

1

R5400

0.001

CRITICAL

MF-3

0612

1W 1%

3

1

6

4

5

2

U5400

INA214

CRITICAL

SC70

High Side Voltage and Current Sensing

SYNC_DATE=02/18/2014

SYNC_MASTER=CLEAN_X305_PEG

PPBUS_G3H

SMC_OTHER5V_HI_ISENSE

GND_SMC_AVSS

DCIN_S5_VSENSE

PPDCIN_G3H_ISOL

PDCINVSENS_EN_L_DIV

PM_SLP_SUS_L

DCINVSENS_EN_L

HS_OTHER5V_IOUT

SMC_OTHER3V3_HI_ISENSE

PPBUS_G3H

PPVIN_S5_HS_OTHER3V3_ISNS

GND_SMC_AVSS

PPBUS_G3H

PPVIN_S5_HS_OTHER5V_ISNS

GND_SMC_AVSS

CHGR_BMON

SMC_CHGR_BMON_ISENSE

GND_SMC_AVSS

CHGR_AMON

SMC_DCIN_ISENSE

GND_SMC_AVSS

PBUSVSENS_EN_L_DIV

PBUSVSENS_EN_L

GND_SMC_AVSS

PPBUS_G3H

PBUS_S0_VSENSE

SMC_CPU_HI_ISENSE

PP3V3_S0

ISNS_HS_OTHER3V3_P

ISNS_HS_OTHER3V3_N

HS_OTHER3V3_IOUT

ISNS_HS_OTHER5V_P

ISNS_HS_OTHER5V_N

SMC_PBUS_VSENSE

PM_SLP_S3_R_L

GND_SMC_AVSS

SMC_DCIN_VSENSE

PPVIN_S5_HS_COMPUTING_ISNS

PP3V3_S0

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

HS_COMPUTING_IOUT

PP3V3_S0

<SCH_NUM>

54 OF 119

44 OF 97

30 44 47 56 57 63 65 84 86

40 41 44 45 46 47

56 57 84

30 44 47 56 57 63 65 84 86

61 84

40 41 44 45 46 47

30 44 47 56 57 63 65 84 86

61 84

40 41 44 45 46 47

30 44 47 56 57 63 65 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 41 44 45 46 47

58 59 60 62 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

OUT

V-

V+

+

-

V-

V+

+

-

OUT

V-

V+

+

-

IN

V-

V+

+

-

IN

OUT

GND

OUT

VIN+ VIN-

V+

IN

V-

V+

+

-

OUT

V-

V+

+

-

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Vsense: 52.2 mV, Range: 5 A

Rsense: 0.02 (R5510)

TBT Router CURRENT SENSE

CPU PKG Load Side Current Sense / Filter

Gain: 1000uA/V * 24.9kOhm = 24.9x

Total Gain: 24.9 x 2 = 49.8x

TRACKPAD CURRENT SENSE

DDR3L 1.35V DRAM ONLY CURRENT SENSE / FILTER

EDP: 95A TDP :45A

SMC_ADC1

Max VOut: 3.3V at 95.8A

Scale: 29.03A / V

Gain:137.77x

GAIN:136.6X

IM0C

SMC_ADC10

SMC_ADC0

SENSE RESISTOR 0.010 OHM

VC0C

SMC_AD2

ITPC

IHSC

EDP CURRENT: 0.94 A

SMC_ADC6

IHDC

SSD CURRENT SENSE

GAIN: 274X

IC0C

SMC_ADC23

GAIN: 165.56X

EDP CURRENT:8A

CPU Vcore Voltage Sense / Filter

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

Individual Sense R is 0.75mOhm

EDP CURRENT: 5A

Sense Resistor 0.005 Ohm

Gain: 24.9x, EDP: 2.61 A (Transient)

PCH CORE CURRENT SENSE

SMC_ADC19

IC1C

GAIN: 333X

Sense Resistor R7640 0.001 Ohm on PCH regulator page

EDP CURRENT: 5A

40 42

21

R5577

PLACE_NEAR=U5000.B6:7mm

201

1/20W

4.53K

MF

1%

2

1

C5577

PLACE_NEAR=U5000.B6:5mm

X5R

6.3V

20%

0.22UF

0201

21

R5573

402

1/16W MF-LF

7.32K

1%

21

R5576

NO_XNET_CONNECTION=TRUE

1M

1/16W

402

MF-LF

1%

2

1

R5575

402

MF-LF

1/16W

1M

1%

21

R5574

402

MF-LF

1/16W

7.32K

1%

5

2

4

3

1

U5560

SC70-5

OPA333DCKG4

2

1

C5560

0.1UF

0402

20%

X7R-CERM

10V

2

1

C5540

20%

6.3V

0201

0.22UF

PLACE_NEAR=U5000.B4:5MM

X5R

21

R5564

PLACE_NEAR=U5000.B4:7MM

201

1/20W

4.53K

MF

1%

2

1

C5558

0.1UF

402

20%

CERM

10V

5

2

4

3

1

U5540 OPA333DCKG4

SC70-5

OMIT_TABLE

21

R5563

1M

MF-LF

1/16W

402

NO_XNET_CONNECTION=TRUE

1%

2

1

R5562

1M

1/16W

402

MF-LF

1%

NO_XNET_CONNECTION=TRUE

21

R5504

402

MF-LF

1/16W

6.04K

1%

21

R5561

402

MF-LF

6.04K

1%

1/16W

40 42

2

1

C5501

X5R 0201

6.3V

20%

0.22UF

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.E1:5MM

21

R5506

PLACE_NEAR=U5000.E1:5MM

SENSOR_NONPROD:Y

4.53K

1/20W

201

MF

1%

2

1

C5550

0402

SENSOR_NONPROD:Y

20%

0.1UF

PLACE_NEAR=U5550.5:3MM

10V X7R-CERM

5

2

4

3

1

U5550

SC70-5

OPA333DCKG4

CRITICAL

SENSOR_NONPROD:Y

21

R5555

402

MF-LF

732K

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

1/16W

1%

21

R5503

SENSOR_NONPROD:Y

1/16W

3.57K

402

MF-LF

1%

2

1

R5554

402

1/16W

732K

MF-LF

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

1%

21

R5507

MF-LF

SENSOR_NONPROD:Y

1/16W

3.57K

402

1%

21

R5505

0.5%

1/16W

402

5.23K

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

PLACE_NEAR=R7310.3:5MM

MF

59 96

21

R5500

SENSOR_NONPROD:Y

PLACE_NEAR=R7330.3:5MM

NO_XNET_CONNECTION=TRUE

5.23K

1/16W

402

0.5% MF

21

R5508

5.23K

0.5%

402

1/16W

PLACE_NEAR=R7320.3:5MM

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

MF

21

R5570

1/16W

0.5%

402

5.23K

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

PLACE_NEAR=R7310.4:5MM

MF

21

R5571

1/16W

402

0.5%

5.23K

PLACE_NEAR=R7320.4:5MM

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

MF

59 96

21

R5572

402

5.23K

0.5%

1/16W

PLACE_NEAR=R7330.4:5MM

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

MF

59 96

2

1

C5500

0.22UF

0201

20%

6.3V X5R

PLACE_NEAR=U5000.A8:5MM

21

R5502

1/20W

4.53K

201

MF

1%

PLACE_NEAR=U5000.A8:5MM

2

1

C5551

402

CERM

10V

20%

0.1UF

5

2

4

3

1

U5500

SC70-5

OPA333DCKG4

OMIT_TABLE

21

R5501

1/20W

1M

201

NO_XNET_CONNECTION=TRUE

MF

1%

2

1

R5553

201

1/20W

1M

MF

1%

21

R5551

1/20W

3.65K

MF

1%

201

21

R5552

201

1/20W

MF

1%

3.65K

432

1

R5559

1206-1

1/2W

0.010

CRITICAL

MF

1%

21

R5530

0

NOSTUFF

0201

5%

PLACE_NEAR=U7200.3:5MM

1/20W

MF

58

432

1

R5560

CRITICAL

CYN

0612

0.003

1W

1%

43

21

R5549

1% 1W MF

0.005

CRITICAL

0612-6

40 42

2

1

C5510

BYPASS=U5510.5::5MM

20%

0.1UF

CERM

10V 402

43

5 1

2

U5510

INA139

SOT23-5

CRITICAL

65 84

2

1

R5511

24.9K

MF-LF

1/16W

402

1%

2

1

C5511

CERM

BYPASS=U5511.5::5MM

0.1UF

20%

402

10V

5

2

1

4

3

U5511

CRITICAL

SOT-23

OPA340NA

38 84 86

2

1

C5514

PLACE_NEAR=U5000.F2:5MM

0201

X5R

6.3V

0.22UF

20%

40 42

21

R5514

1/20W

4.53K

201

MF

1%

PLACE_NEAR=U5000.F2:5MM

5

2

4

3

1

U5590 OPA333DCKG4

SC70-5

OMIT_TABLE

2

1

C5591

20%

6.3V X5R 0201

0.22UF

PLACE_NEAR=U5000.H2:5MM

21

R5595

PLACE_NEAR=U5000.H2:7MM

201

MF

1/20W

1%

4.53K

2

1

C5590

0.1UF

402

20%

CERM

10V

21

R5594

1%

1/16W

402

1M

MF-LF

NO_XNET_CONNECTION=TRUE

2

1

R5593

1%

MF-LF

1M

402

1/16W

NO_XNET_CONNECTION=TRUE

21

R5591

MF

0.1%

1/20W

0201

3.0K

21

R5592

MF

1/20W

0.1%

0201

3.0K

62 96

21

R5518

10K

201

1/20W

MF

1%

2

1

R5519

1/20W

10K

201

MF

1%

43

21

R5510

1% 1W

0.02

CRITICAL

PLACE_NEAR=U5510.4:3MM

MF

PLACE_NEAR=U5510.3:3MM

0612-2

40 42

21

R5520

201

4.53K

1/20W

MF

1%

PLACE_NEAR=U5000.E2:7MM

2

1

C5520

0.22UF

20%

X5R

6.3V

0201

PLACE_NEAR=U5000.E2:5MM

21

XW5520

SM

PLACE_NEAR=R7310.2:5 MM

U5500,U5540,U5590

IC,OPAMP,NCS333QS3,SC70-5

353S00107

CRITICAL

3

SYNC_MASTER=CLEAN_X425G

SYNC_DATE=09/10/2014

Load Side Voltage and Current Sensing

PP3V3_S0

P1V05S0_CS_P

GND_SMC_AVSS

P1V05S0_CS_N

ISNS_PCH_R_P

ISNS_PCH_R_N

ISNS_PCH_IOUT

SMC_PCH_CORE_ISENSE

PPVIN_S4_TPAD

CPUVSENSE_IN

ISNS_SSD_N

ISNS_SSD_P

PP3V3_S0SW_SSD_R

CPUVR_ISNS2_P

PP1V35_S3

CPUVR_ISUM_IOUT

GND_SMC_AVSS

PP3V3_S4

GND_SMC_AVSS

PP3V3_S4_TBT

CPUVR_ISNS3_P

ISNS_SSD_R_P

ISNS_TBT_P

CPUVR_ISNS1_P

PP3V3_S0SW_SSD

ISNS_SSD_R_N

PP3V3_S0

SMC_SSD_ISENSE

CPUVR_ISNS3_N

GND_SMC_AVSS

PP3V3_S4

ISNS_SSD_IOUT

ISNS_TBT_R_P

CPUVR_ISNS2_N

SMC_TBT_ISENSE

CPUVR_ISNS1_N

CPUVR_ISNS_P

CPUVR_ISUM_R_N

ISNS_TBT_R_N

GND_SMC_AVSS

ISNS_TPAD_IOUT_FDBK

SMC_TPAD_ISENSE

GND_SMC_AVSS

SMC_CPUPKG_VSENSE

PPVCC_S0_CPU

ISNS_TBT_N

GND_SMC_AVSS

ISENSE_P1V35MEM_IOUT

PP3V3_S3

ISNS_1V35_MEM_R_N

ISNS_1V35_MEM_R_P

SMC_P1V35MEM_ISENSE

PP3V3_S0

CPUVR_IMON

SMC_CPUPKG_ISENSE

CPUVR_ISUM_R_P

CPUVR_ISNS_N

ISNS_1V35_MEM_N

ISNS_TBT_IOUT

ISNS_TPAD_P ISNS_TPAD_N

PP3V3_S4

SMC_TPAD_ISENSE_R

PP3V3_S4

ISNS_TPAD_IOUT_BUF

PP1V35_S3_MEM

ISNS_1V35_MEM_P

PPBUS_S4_TPAD

<SCH_NUM>

55 OF 119

45 OF 97

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 41 44 45 46 47

96

40 42

96

66 84

21 60 66 84 86

40 41 44 45 46 47

20 33 38 41 42 45 46 65

66 67 81 84 85 86

40 41 44 45 46 47

28 29 30 84

96

34 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 41 44 45 46 47

20 33 38 41 42 45 46 65 66 67 81 84 85 86

96

40 41 44 45 46 47

6 8

10 59 84 86

96

40 41 44 45 46 47

13 20 21 43 46 66 81 82 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

96 96

20 33 38 41 42 45 46 65 66 67 81 84 85 86

22 23 24 25 26 27 84 92

96

OUT

IN-

IN+ REF

V+

GND

IN

V-

V+

+

-

IN

V-

V+

+

-

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

ICMC removed due to lack of channel on SMC

S2 CAMERA CONTROLLER CURRENT SENSE

Use 1206 package

EDP CURRENT: 5A

SENSE RESISTOR 0.003 OHM

EDP CURRENT: 1.0A

EDP Current: 1.06A

Sense Resistor 0.005 Ohm

CPU DDR CURRENT SENSE

EDP CURRENT: 4.2A

LCD PANEL CURRENT SENSE

ILDC

SMC_ADC12

IC3C

Gain: 316x

.

GAIN: 100X

SMC_ADC22

IAPC

X87 AIRPORT CURRENT SENSE

GAIN: 822X

SMC_ADC11

2

1

C5682

SENSOR_NONPROD:Y

10V

CERM

20%

402

0.1UF

21

R5684

SENSOR_NONPROD:Y

1M

1/20W

201

NO_XNET_CONNECTION=TRUE

MF

1%

21

R5681

1/20W

201

3.16K

SENSOR_NONPROD:Y

MF

1%

21

R5682

3.16K

1/20W

201

SENSOR_NONPROD:Y

MF

1%

2

1

R5683

1M

1/20W

201

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

MF

1%

3

1

6

4

5

2

U5670

SC70

INA214

SENSOR_NONPROD:Y

2

1

C5670

SENSOR_NONPROD:Y

0.1UF

CERM 402

20%

10V

69 96

5

2

4

3

1

U5682

SC70-5

OPA333DCKG4

SENSOR_NONPROD:Y

69 96

2

1

C5631

SENSOR_NONPROD:Y

20%

6.3V

X5R 0201

0.22UF

PLACE_NEAR=U5000.B8:7MM

21

R5634

4.53K

201

SENSOR_NONPROD:Y

1/20W

PLACE_NEAR=U5000.B8:7MM

MF

1%

2

1

C5630

SENSOR_NONPROD:Y

10%

0201

CERM-X5R

6.3V

0.1UF

5

2

4

3

1

U5630

SC70-5

OPA333DCKG4

SENSOR_NONPROD:Y

21

R5633

SENSOR_NONPROD:Y

1/20W

201

NO_XNET_CONNECTION=TRUE

510K

MF

1%

21

R5630

SENSOR_NONPROD:Y

1/20W

620

201

MF

1%

21

R5631

1/20W

201

SENSOR_NONPROD:Y

620

MF

1%

2

1

R5632

NO_XNET_CONNECTION=TRUE

1/20W

201

510K

SENSOR_NONPROD:Y

MF

1%

2

1

C5681

PLACE_NEAR=U5000.A6:5MM

0.22UF

20%

0201

6.3V

X5R

SENSOR_NONPROD:Y

2

1

C5671

0201

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.C1:7MM

0.22UF

20%

6.3V

X5R

21

R5671

PLACE_NEAR=U5000.C1:7MM

SENSOR_NONPROD:Y

4.53K

1/20W

201

MF

1%

21

R5685

PLACE_NEAR=U5000.A6:7MM

1/20W

4.53K

201

SENSOR_NONPROD:Y

MF

1%

40 42

4 3

2 1

R5635

CRITICAL

MF

1W

0.005

1%

0612-6

66 96

2

1

XW5675

SM

21

R5677

MF-LF 1/16W

402

5%

0

S2_PWR:S0

21

R5676

S2_PWR:S3

402

0

1/16W

5%

MF-LF

2

1

R5678

201

5%

PLACE_NEAR=U5670.6:5MM

SENSOR_NONPROD:Y

1/20W

20K

MF

5

C5601,C5631,C5600,C5681,C5671

RES,MTL FILM,100K,5,1/20W,0201,SMD,LF

117S0008

SENSOR_NONPROD:N

SYNC_DATE=01/14/2014

SYNC_MASTER=CLEAN_X305

Debug Sensors

PP3V3_S3

SMC_CPUDDR_ISENSE

LCD_PANEL_IOUT

ISNS_AIRPORT_IOUT

PP3V3_S4

ISNS_AIRPORT_R_N

ISNS_LCD_PANEL_P

GND_SMC_AVSS

SMC_LCDPANEL_ISENSE

SMC_X87_ISENSE

GND_SMC_AVSS

PP3V3_S0

GND_SMC_AVSS

ISNS_AIRPORT_R_P

ISNS_CPUDDR_N

ISNS_CPUDDR_P

ISNS_CPU_DDR_IOUT

ISNS_CPU_DDR_R_N

ISNS_CPU_DDR_R_P

ISNS_LCD_PANEL_N

PP3V3_S3RS0_CAMERA

PP3V3_S0

PP3V3_S3

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

PP3V3_S3RS0_CAMERA_R

PP3V3_WLAN_R

PP3V3_WLAN_F

ISNS_AIRPORTP

ISNS_AIRPORTN

46 OF 97

<SCH_NUM>

56 OF 119

13 20 21 43 45 46 66 81 82 84 86

20 33 38 41 42 45 65 66 67 81 84 85 86

96

40 41 44 45 46 47

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 41 44 45 46 47

96

13 20 35 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

13 20 21 43 45 46 66 81 82 84 86

33

V-

V+

+

-

OUT

V-

V+

+

-

IN

OUT

IN-

IN+ REF

V+

GND

OUT

V-

V+

+

-

V-

V+

+

-

OUT

V+

GND

OUT

GND

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP Current: 13.5A

Gain: 3.004x

GPU VCORE Voltage Sense

VG0C

VDDCI Current Sense

GPU FB Voltage Sense

EDP Current: 13.5A

IG0R

GRAPHICS High Side Current Sense

EDP Current: 13.9A

Gain:100x

Gain: 100x

GPU FB Current Sense

IGMC

SMC_ADC20

SMC_ADC14

SMC_ADC17

SMC_ADC21

IG3C

SMC_ADC18

SMC_ADC16

IG2C

VG1C

Gain: 139.86x

EDP Current: 7.317A

.

Vimon=3xIo*(0.2/R8915)*R8912

EDP Current:49.5A

SMC_ADC15

IG0C

GPU 0V95 Current Sense

Gain: 124.07x

GPU VR OCP

GPU VCORE Current Sense

TRIP POINT: 61A

2

1

C5742

SENSOR_GPU_NONPROD:Y

0.22UF

PLACE_NEAR=U5000.G2:5MM

6.3V

20%

0201

X5R

21

R5744

SENSOR_GPU_NONPROD:Y

1/20W

4.53K

201

PLACE_NEAR=U5000.G2:5MM

MF

1%

2

1

C5743

0.1UF

20% 10V X7R-CERM 0402

SENSOR_GPU_NONPROD:Y

5

2

4

3

1

U5740

OPA333DCKG4

SC70-5

SENSOR_GPU_NONPROD:Y

21

R5740

7.15K

1/20W

201

SENSOR_GPU_NONPROD:Y

MF

1%

21

R5741

1/20W

201

7.15K

SENSOR_GPU_NONPROD:Y

MF

1%

21

R5743

1/16W

1M

MF-LF

402

SENSOR_GPU_NONPROD:Y

NO_XNET_CONNECTION=TRUE

1%

2

1

R5742

NO_XNET_CONNECTION=TRUE

1/16W MF-LF

1M

402

SENSOR_GPU_NONPROD:Y

1%

40 42

21

R5710

NOSTUFF

PLACE_NEAR=U5700.1:5mm

0

5%

1/20W

0201

NO_XNET_CONNECTION=TRUE

MF

2

1

C5718

SENSOR_NONPROD:Y

6.3V

PLACE_NEAR=U5000.B2:5mm

X5R

20%

0.22UF

0201

2

1

C5710

0.1UF

SENSOR_NONPROD:Y

CERM 402

20%

CRITICAL

10V

21

R5718

1/20W

201

4.53K

PLACE_NEAR=U5000.B2:5mm

SENSOR_NONPROD:Y

MF

1%

5

2

4

3

1

U5700

OPAMP_OPA333_NONINV

SENSOR_NONPROD:Y

OPA333DCKG4

SC70-5

21

R5717

NO_XNET_CONNECTION=TRUE

MF-LF

1M

402

1/16W

SENSOR_NONPROD:Y

1%

2

1

R5700

1/16W MF-LF 402

499K

SENSOR_NONPROD:Y

1%

79

30 44 56 57 63 65 84 86

73 79 80 84

432

1

R5701

CRITICAL

CYN

1W

0612

0.002

1%

3

1

6

4

5

2

U5710

INA214

CRITICAL

SC70

2

1

C5711

402

10V

20%

0.1UF

CERM

21

R5719

PLACE_NEAR=U5000.F2:5mm

4.53K

1/20W

201

MF

1%

2

1

C5719

20%

6.3V X5R 0201

0.22UF

PLACE_NEAR=U5000.F2:5mm

40 42

21

XW5735

SM

21

R5735

PLACE_NEAR=U5000.B3:5mm

1/20W

4.53K

201

MF

1%

2

1

C5735

PLACE_NEAR=U5000.B3:5mm

20%

6.3V

0.22UF

X5R 0201

40 42

21

XW5790

SM

21

R5790

PLACE_NEAR=U5000.H1:5mm

201

1/20W

4.53K

MF

1%

2

1

C5790

PLACE_NEAR=U5000.H1:5mm

0.22UF

20%

6.3V X5R 0201

40 42

2

1

C5791

SENSOR_GPU_NONPROD:Y

PLACE_NEAR=U5000.A7:5mm

0201

X5R

6.3V

20%

0.22UF

2

1

C5792

10V CERM

0.1UF

402

20%

SENSOR_GPU_NONPROD:Y

21

R5791

PLACE_NEAR=U5000.A7:5mm

201

4.53K

1/20W

SENSOR_GPU_NONPROD:Y

MF

1%

5

2

4

3

1

U5790

OPA333DCKG4

SC70-5

SENSOR_GPU_NONPROD:Y

21

R5794

SENSOR_GPU_NONPROD:Y

402

1M

1/16W MF-LF

NO_XNET_CONNECTION=TRUE

1%

21

R5795

SENSOR_GPU_NONPROD:Y

201

1/20W

8.06K

MF

1%

21

R5796

SENSOR_GPU_NONPROD:Y

201

1/20W

8.06K

MF

1%

2

1

R5793

NO_XNET_CONNECTION=TRUE

SENSOR_GPU_NONPROD:Y

1/16W

1M

MF-LF 402

1%

21

R5771

201

1/20W

10K

MF

1%

21

R5770

1/20W

201

10K

MF

1%

2

1

R5772

402

1M

MF-LF

NO_XNET_CONNECTION=TRUE

1/16W

1%

21

R5773

NO_XNET_CONNECTION=TRUE

402

1/16W MF-LF

1M

1%

5

2

4

3

1

U5770

OPA333DCKG4

SC70-5

2

1

C5770

0.1UF

CERM 402

20% 10V

2

1

C5771

6.3V

X5R

PLACE_NEAR=U5000.H2:5mm

0201

0.22UF

20%

21

R5774

PLACE_NEAR=U5000.H2:5mm

201

4.53K

1/20W

MF

1%

40 42

2

1

R5709

5% MF-LF

1/16W 402

20K

2

1

C5750

1UF

0402-1

X5R

25V

10%

2

1

C5751

0.1UF

10%

6.3V

CERM-X5R

0201

21

R5752

40.2K

201

1/20W

MF

1%

2

1

R5753

324K

201

1/20W MF

1%

21

R5761

1/20W

1M

201

MF

1%

4

5

1

3

2

U5760

LMV7275MG/NOPB

CRITICAL

SC70-5

2

1

C5760

10%

CERM-X5R

0.1UF

6.3V 0201

21

R5762

1/20W

201

0

5% MF

2

1

R5763

5%

201

2.2K

1/20W

NO STUFF

MF

77

2

1

C5761

6.3V 0201

10%

CERM-X5R

0.1UF

NO STUFF

2

1

3

U5750

REF3030

SOT23-3

CRITICAL

SYNC_MASTER=J45G_AMD

GPU V/I Sensors

SYNC_DATE=07/01/2014

PP3V3_S0

GFXIMVP6_IMON

PP3V3_S0GPU

GPUCORE_VR_ICCWARN_BUF_L

P3V0_GPU_VREF

PP3V3_S0GPU

GPU_VCORE_OC_L

VDDCIS0_CS_N

GPUVCORE_IOUT

GPUVCORE_INV

SMC_GPUCORE_ISENSE

PP3V3_S0

GND_SMC_AVSS

PPBUS_G3H

ISNS_HS_GPU_N

GND_SMC_AVSS

PP3V3_S0

0V95_GPU_IOUT

PPVCORE_GPU

ISNS_PP0V95_S0GPU_P

ISNS_PP0V95_S0GPU_N

ISNS_PP0V95_S0GPU_R_N

ISNS_PP0V95_S0GPU_R_P

SMC_GPUCORE_VSENSE

GND_SMC_AVSS

SMC_GPU_FB_VSENSE

GPU_FB_VSENSE_IN

SMC_GPU_VDDCI_ISENSE

VDDCIS0_CS_P

SMC_GPU_HI_ISENSE

VDDCIS0_CS_R_N

VDDCIS0_CS_R_P

GND_SMC_AVSS

SMC_GPU0V95_ISENSE

GND_SMC_AVSS

SMC_GPU_FB_ISENSE

PP3V3_S0

HS_GPU_IOUT

SMC_GPU_FB_R

GPUFB_CS_R_P

GPUFB_CS_N

GPUFB_CS_P

GPUFB_CS_R_N

PP1V35_GPU_REG

PP3V3_S0

VDDCI_GPU_IOUT

GPUVCORE_IOUT

IWARN_FB

GPUVSENSE_IN

PPVIN_S5_HS_GPU_ISNS

ISNS_HS_GPU_P

57 OF 119

47 OF 97

<SCH_NUM>

11 12 13 14 15 17

19 20 29

34 43 44

45 46 47

48 49 51

52 55 66

67 68 69

82 83 84

86 96

47 66 68 71 72 76 77 79 80 84

80 96

47

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

40 41 44 45 46 47

96

40 41 44 45 46 47

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

71 79 84

73 96

96

40 41 44 45 46 47

40 42

80 96

96

40 41 44 45 46 47

40 42

40 41 44 45 46 47

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

73 96

96

71 72 73 74 75 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

47

96

BI

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

BI

NC

GND

V+

ADD0

ALERT

SCL

SDA

BI

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE U5850 ON TOP SIDE UNDER THE GPU

Write Address: 0x98 Read Address: 0x99

Placement note:

CLOSE TO THE LEFT FIN STACK

AIRFLOW PROXIMITY TEMPERATURE

R5851 10K gives:

PLACE Q5801 ON TOP SIDE

Placement note:

PLACE Q5803 ON TOP SIDE NEAR DDR3

Use GND pin B1 on U2800 for N leg

THSP

TBT DIE

Th2H

Placement note:

RIGHT FIN STACK TEMPERATURE

PCH PROXIMITY TEMPERATURE

TW0P

TC0P

Placement note:

TP0P

Ta0P

TM0P

CLOSE TO BOARD EDGE

Placement note:

PLACE Q5802 ON TOP SIDE

PLACE U5870 ON TOP SIDE UNDER CPU

PLACE Q5804 ON TOP SIDE UNDER PCH

Placement note:

DDR3 PROXIMITY TEMPERATURE

CPU PROXIMITY TEMPERATURE

PLACE U5823 ON BOTTOM NEAR X87 CONN

READ ADDRESS: 0X93

WRITE ADDRESS: 0X92

Placement note:

X87 PROXIMITY

Write Address: 0x98

R5871 10K gives:

GPU DIE TEMPERATURE

GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK

Placement note:

Th1H

Read Address: 0x99

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

PLACE Q5803 ON BOTTOM SIDE NEAR RIGHT FIN STACK

LEFT FIN STACK TEMPERATURE

TG0D

2

1

R5872

10K

MF-LF 402

5% 1/16W

2

1

R5871

10K

MF-LF

402

5%

1/16W

2

3

1

Q5804

SOT732-3

BC846BMXXH

CRITICAL

2

3

1

Q5802

SOT732-3

BC846BMXXH

CRITICAL

2

1

C5871

0.0022uF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5870.2:5mm

PLACE_NEAR=U5870.3:5mm

50V

10%

402

CERM

28 48 96

21

XW5820

SM

PLACE_NEAR=U2800.AC6:2mm

2

1

R5820

10K

402

5% 1/16W

NOSTUFF

PLACE_SIDE=TOP

MF-LF

2

3

1

Q5806

SOT732-3

BC846BMXXH

CRITICAL

1

11

7

9

10

6

4

2

5

3 8

U5870

DFN

EMC1414-A-AIA

40 43 48 95

2

1

C5823

402

CERM

10V

20%

0.1uF

2

1

R5822

MF-LF

5% 1/16W

402

10K

5

6

1

2

3

4

U5823

CRITICAL

PLACE_NEAR=J3501:5MM

SOT563

PLACE_SIDE=BOTTOM

HPA00330AI

2

1

R5852

10K

5% MF

1/20W 201

36 40 43 69 76 85 86 95

2

1

R5851

10K

5% MF

1/20W

201

2

1

C5850

X7R-CERM

20% 10V

0402

0.1UF

1

11

7

9

10

6

4

2

5

3 8

U5850

EMC1414-A-AIA

DFN

2

1

C5851

PLACE_NEAR=U5850.2:5mm

50V

CERM

402

0.0022uF

PLACE_NEAR=U5850.3:5mm

NO_XNET_CONNECTION=TRUE

10%

2

1

C5852

PLACE_NEAR=U5850.4:5mm

NO_XNET_CONNECTION=TRUE

0.0022uF

402

10%

PLACE_NEAR=U5850.5:5mm

CERM

50V

21

R5850

1/16W

402

47

5%

MF-LF

76 96

2

3

1

Q5803

BC846BMXXH

CRITICAL

SOT732-3

2

3

1

Q5801

CRITICAL

BC846BMXXH

SOT732-3

40 43 48 95

36 40 43 69 76 85 86 95

2

1

C5803

NOSTUFF

PLACE_NEAR=Q5803.3:2mm

C0G

47PF

0201

5%

25V

40 43 48 95

2

1

C5870

0.1UF

20% 0402

X7R-CERM

10V

21

R5870

1/16W

5%

402

MF-LF

47

2

1

C5890

PLACE_NEAR=U5870.5:5mm

PLACE_NEAR=U5870.4:5mm

50V

10%

402

CERM

0.0022uF

NO_XNET_CONNECTION=TRUE

Thermal Sensors

SYNC_DATE=11/26/2012

SYNC_MASTER=CHANG_J45

GPUTHMSNS_D_P

CPUTHMSNS_D2_N

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

GPUTHMSNS_D_N

SMBUS_SMC_1_S0_SDA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

PP3V3_S0_GPUTHMSNS_R

GPUTHMSNS_ALERT_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0

X87THMSNS_A0

DDR3THMSNS_D1_P

CPUTHMSNS_THM_L

DDR3THMSNS_D1_N

PP3V3_S0

GPUTHMSNS_THM_L

TBT_THERMDP

MAKE_BASE=TRUE

TBT_THERMDN

TBT_THERMDP

PP3V3_S0

CPUTHMSNS_D2_P

CPUTHMSNS_ALERT_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_0_S0_SCL

GPU_TDIODE_N

GPU_TDIODE_P

SMBUS_SMC_0_S0_SDA

<SCH_NUM>

58 OF 119

48 OF 97

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

28 48 96

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

IN

OUT

IN

NC

NC NC

OUT

VER 1

S

D

G

VER 1

S

D

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0769

Right Fan

Left Fan

518S0769

2

1

R6050

47K

5%

1/16W

402

MF-LF

21

R6055

5%

1/16W

47K

402

MF-LF

2

1

R6060

MF-LF

402

5%

1/16W

47K

21

R6065

1/16W

5%

402

MF-LF

47K

2

1

R6051

100K

201

MF

1/20W

5%

2

1

R6061

201

MF

100K

5%

1/20W

40

5

4

3

2

1

6

7

J6050

FF14A-5C-R11DL-B-3H

CRITICAL

F-RT-SM

5

4

3

2

1

6

7

J6060

FF14A-5C-R11DL-B-3H

F-RT-SM

CRITICAL

40

21

R6071

0

NOSTUFF

402

1/16W MF-LF

5%

21

R6072

MF-LF

1/16W

NOSTUFF

0

5%

402

4

5

3

Q6060

DMN5L06VK-7

SOT563

1

2

6

Q6060

DMN5L06VK-7

SOT563

SYNC_DATE=10/31/2012

Fan Connectors

SYNC_MASTER=J15_MLB

FAN_LT_PWM

PP5V_S0

PP3V3_S0

FAN_RT_TACH

PP3V3_S0

SMC_FAN_1_TACH

PP3V3_S0

SMC_FAN_1_CTL

PP3V3_S3_FAN_CTL

FAN_RT_PWM

SMC_FAN_0_CTL

PP5V_S0

FAN_LT_TACH

PP3V3_S3_FAN_CTL

SMC_FAN_0_TACH

<SCH_NUM>

60 OF 119

49 OF 97

86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

49 85

86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

86

49 85

BI

IN

OUT

BI

OUTOUT

VCC

D

B

A Y

OE*

C

GND

CS*

DI(IO0)

THRM_PAD

CLK

WP*(IO2) HOLD*(IO3)

DO(IO1)

VCC

GND

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IO3

SMC12 Master

SPI ROM Slave

IO1

IO0

SPI ROM

Sam Card ROM Slave

NOTE: If HOLD* is asserted

in normal and Dual-IO modes.

SPI Frequency: 50MHz for CPU, 20MHz for SMC.

Quad-IO Mode (Mode 0 & 3) supported.

IO2

516S00024

(SPI_IO<1>)

0HOM WERE ADDED FOR R6118&R6119 AS PLACEHOLDER.

OVER/UNDER-SHOOT WAS OBSERVED ON IO2 AND IO3.

ROM will ignore SPI cycles

FINAL VALUE NEEDS TO BE TUNED.

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

SPI Bus Series Termination

(SWDIO) (SWCLK)

SPI+SWD SAM Connector

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

PCH Master

(SPI_IO<0>)

21

R6122

PLACE_NEAR=U6100.5:12MM

1/20W

MF

1%

33

201

21

R6112

201

5%

11

1/20W

MF

PLACE_NEAR=U1100.AH1:50MM

13 91

40 91

21

R6117

0201

0

MF

1/20W

5%

NOSTUFF

PLACE_NEAR=U5000.K10:12MM

21

R6115

0201

PLACE_NEAR=U5000.N9:12MM

0

MF

1/20W

5%

NOSTUFF

21

R6116

0201

0

MF

1/20W

5%

NOSTUFF

PLACE_NEAR=U5000.L10:12MM

21

R6114

0201

0

MF

1/20W

5%

PLACE_NEAR=U5000.M9:12MM

NOSTUFF

21

R6113

5%

11

201

1/20W

MF

PLACE_NEAR=U1100.AH3:50MM

21

R6130

1/20W

MF

33

201

1%

PLACE_NEAR=U6100.3:12MM

21

R6131

1/20W

MF

201

1%

33

PLACE_NEAR=U6100.7:12MM

13 91

40 41 86

14 50 86

40 41 86

9

8 7

6 5

4 3

2

16

15

14 13

12 11

10

1

J6100

SAMCONN

M-ST-SM

DF40PC-12DP-0.4V-51

CRITICAL

40 41 57 86

2

1

C6100

0201

X5R-CERM

16V

10%

0.1UF

BYPASS=U6100::3mm

2

1

C6101

0201

BYPASS=U6101::3mm

10% 16V X5R-CERM

0.1UF

7

8

1

4

6

5

3

2

U6101

74LVC1G99

SOT833

CRITICAL

PLACE_NEAR=U6100.1:12MM

3

8

9

7

4

2

5

1

6

U6100

WSON

OMIT_TABLE

W25Q64FVZPIG

64MBIT

CRITICAL

50 91

21

R6118

5%

11

201

1/20W

MF

PLACE_NEAR=U1100.AJ4:50MM

21

R6119

5%

11

201

1/20W

MF

PLACE_NEAR=U1100.AJ2:50MM

21

R6110

201

5%

1/20W

MF

11

PLACE_NEAR=U1100.AJ7:50MM

13 91

21

R6111

5%

11

201

1/20W

MF

PLACE_NEAR=U1100.AJ11:50MM

13 91

21

R6123

1/20W

MF

1%

PLACE_NEAR=U6100.2:12MM

201

33

13 91

21

R6120

1/20W

MF

PLACE_NEAR=U6100.1:12MM

201

1%

33

21

R6121

33

1/20W

MF

1%

PLACE_NEAR=U6100.6:12MM

201

SYNC_MASTER=CLEAN_X425

SYNC_DATE=08/15/2014

SPI Debug Connector

MAKE_BASE=TRUE

SPI_MLB_IO0_MOSI

MAKE_BASE=TRUE

SPI_MLB_CLK

MAKE_BASE=TRUE

SPI_MLB_CS_L

MAKE_BASE=TRUE

SPI_MLB_IO2_WP_L

SPI_CLK_R

MAKE_BASE=TRUE

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

PP3V42_G3H

SPI_MLB_IO2_WP_L

SMC_TMS

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_MLB_IO0_MOSI

SPI_MLB_CLK

SPI_MLB_IO3_HOLD_L

MAKE_BASE=TRUE

SPI_MLB_IO3_HOLD_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_IO0_MOSI

SPI_CLK

SPI_CS0_R_L

SPI_MOSI

SPI_CS0_L

SPI_IO2_R

SPI_IO3_R

SPI_MISO_R

SPI_IO<3>

SPI_MLB_IO1_MISO

SPI_IO<2>

SPI_MISO

SPI_MLB_CLK

PP3V3_SUS

SPI_MLBROM_CS_L

SPI_MOSI_R

SPI_SMC_CS_L

SPI_SMC_MISO

SPI_SMC_CLK

SPI_SMC_MOSI

SMC_TCK

SPI_MLB_IO3_HOLD_L

SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

SPI_MLB_IO1_MISO

SPIROM_USE_MLB

SPI_MLB_CS_L

SMC_RESET_L

<SCH_NUM>

61 OF 119

50 OF 97

50 91

19 34 37 38 40 41 42 43 56 57 67 84 86

50 91

50 91 50 91

50 91

91

50 91

11 12 13 14 15 17 64 66 67 84

50 91

14 50 86

50 91

ANALOG

SYM 1 OF 2

AGND

HPGND

HSGND

PLLGND

VA_PLL

VA

VA_REF

VA_HP

SENSE_A1 SENSE_A2

HPOUT_L HPOUT_R

HS3 HS4

HS4_REF

SENSE_B2

SENSE_B1

SENSE_D

SENSE_C

HS3_REF

HSIN+ HSIN-

LINEOUT1_L-

LINEOUT1_L+

LINEOUT1_R+ LINEOUT1_R-

LINEOUT2_L-

LINEOUT2_L+

LINEOUT2_R-

LINEOUT2_R+

LINEOUT3_R+

LINEOUT3_L+

LINEOUT3_R-

LINEOUT4_L+ LINEOUT4_L-

LINEOUT4_R+ LINEOUT4_R-

LINEOUT3_L-

VREF_ADC

VCOM

FLYN

FLYP

VHP_FILT-

VREF_DAC

LINEIN_L+

LINEIN_R-

LINEIN_R+

LINEIN_L-

MICBIAS2_R

MICBIAS2_L

MICBIAS1_R

MICBIAS1_L

MICIN1_L+

MICIN2_L-

MICIN1_L-

MICIN1_R+

MICIN2_L+

MICIN2_R+ MICIN2_R-

HSBIAS_IN HSBIAS HSBIAS_REF HSBIAS_FILT

MICIN1_R-

OUT

NR/FB

NC

IN

EN

GND

OUT

IN IN

IN IN IN IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APPLE P/N 353S4080

AUDIO CODEC, ANALOG BLOCKS

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SUBWOOFER AMP. SIG. SOURCE

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC

PLACE XW6201 NEAR 5V SOURCE

H13

N12

A11

M12

H12A1A9

N13

L3

M3

D11

E11

D12

C11

A2

N4 M4

N5 M5

N7 M7

N8 M8

L4

L5

L7

L8

K13 L11

K11 K12

J12 J13

H11 J11

G12 G13

F13 G11

F11 F12

E12 E13

N9 M9

N10 M10

N6 M6

D13

M13

L12

N11

L13

B12

C12 B13

C13

A13

A12

C10

C8

A10

A8

B11

B10

L10

L9

L6

M11

U6201

CS4208-CRZR

VFBGA

2

1

C6212

16V

X7R-CERM

10%

0402

0.1UF

BYPASS=U6201.A1:A2:5 MM

2

1

C6216

X7R-CERM

10%

0.1UF

16V

0402

BYPASS=U6201.N13:M11:5 mm

2

1

C6215

0805-LLP-1

TANT-POLY

16V

CRITICAL

BYPASS=U6201.H12:H13:5 mm

10UF

20%

21

C6219

0402

15UF

X5R

4V

CRITICAL

20%

53 96

2

1

C6210

TANT

25V

1UF-10OHM

0603-LLP

CRITICAL

20%

2

1

C6211

0805-LLP-1

CRITICAL

16V TANT-POLY

10UF

20%

2

1

C6222

BYPASS=U6201.A8:B10:5 mm

15UF

X5R

4V

0402

CRITICAL

20%

2

1

C6221

4.7UF

0402

10V X5R-CERM

20%

21

C6220

1UF

10% 25V

402

X5R

21

R6206

201

1/20W

1% MF

2.21K

21

C6224

1UF

25V X5R

10%

402

21

C6225

1UF

402

X5R

25V

10%

21

XW6201

SM

21

R6200

MF

201

5%

NOSTUFF

1/20W

2.2K

21

L6200

0201

FERR-22-OHM-1A-0.055OHM

2

1

C6201

1UF

10%

402

X5R

10V

1

3

5

6

2

4

U6200

TPS71745

CRITICAL

SON

21

XW6200

SM

2

1

C6203

CRITICAL

1.0UF

0201-1

10V X5R-CERM

20%

2

1

C6218

10%

BYPASS=U6201.H12:L10:5 mm

X7R-CERM

16V

0.1UF

0402

55

54 96

2

1

C6217

0805-LLP-1

16V TANT-POLY

10UF

20%

55

2

1

C6202

10%

CRITICAL

0201

0.01UF

25V

X5R-CERM

2

1

C6214

0402

X7R-CERM

16V

0.1UF

10%

2

1

C6213

CRITICAL

6.3V CERM-X6S 0402

10UF

20%

21

L6201

120-OHM-25%-1.3A

CRITICAL

0402

21

C6226

10%

0.1UF

0201

16V X5R-CERM

2

1

C6200

10%

X7R-CERM

0.1UF

16V

0402

21

R6207

201

1/20W

MF

22K

5%

SYNC_DATE=07/30/2013

SYNC_MASTER=JOE_J45

AUDIO:CODEC, ANALOG

GND_AUDIO_CODEC

AUD_HSBIAS_FILT

AUD_HSBIAS_REF

AUD_HSBIAS

AUD_HSBIAS_IN

CODEC_MICIN2

TP_AUD_CODEC_MICBIAS1_L

TP_AUD_CODEC_MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

TP_AUD_CODEC_MICBIAS2_R

GND_AUDIO_CODEC

VREF_DAC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

VHP_FILTN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

CODEC_FLYP

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.20MM

CODEC_FLYN

CODEC_VCOM CODEC_VREF_ADC

AUD_LO3_L_N

NO_TEST=TRUE

NC_AUD_LO4_RN

NO_TEST=TRUE

NC_AUD_LO4_RP

NO_TEST=TRUE

NC_AUD_LO4_LN

NO_TEST=TRUE

NC_AUD_LO4_LP

AUD_LO3_R_N

AUD_LO3_L_P

AUD_LO3_R_P

AUD_LO2_R_P

AUD_LO2_R_N

AUD_LO2_L_P AUD_LO2_L_N

NO_TEST=TRUE

NC_AUD_LO1_RN

NO_TEST=TRUE

NC_AUD_LO1_RP

NO_TEST=TRUE

NC_AUD_LO1_LP

NO_TEST=TRUE

NC_AUD_LO1_LN

MIN_NECK_WIDTH=0.06MM

CODEC_HS_MIC_N

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.3MM

CODEC_HS_MIC_P

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFUS

MIN_NECK_WIDTH=0.07MM

AUD_TYPEDET

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFCH

MIN_NECK_WIDTH=0.07MM

AUD_CH_HS_GND

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.07MM

AUD_US_HS_GND

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

AUD_TIPDET_2

AUD_TIPDET_1

PP3V3_S0_AUDIO_ANALOG

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 mm

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

PP5V_S4_AUDIO_XW

MIN_LINE_WIDTH=0.60MM

PP3V3_S0

PM_SLP_S3_BUF_L

4V5_REG_EN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM VOLTAGE=5V

4V5_REG_IN

PP3V3_S0

GND_AUDIO_CODEC

VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

4V5_NR

GND_AUDIO_CODEC

PP5V_S4

MIN_NECK_WIDTH=0.15MM VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.20MM

HS_MIC_N

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.3MM

HS_MIC_P

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.07MM

<SCH_NUM>

62 OF 119

51 OF 97

51 55

96

51 55

51

51 55

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

66 67 81 82 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

51 55

37 38 61 66 67 69 81 84 86 51

DIGITAL

SYM 2 OF 2

VD

VL_HD

VL_IF

VL_SP

VL_DM

NC

DMIC_SCL3

DMIC_SDA3

DMIC_SCL2

DMIC_SDA2

DMIC_SCL1

DMIC_SDA1

DMIC_SCL0

DMIC_SDA0

SPDIF_OUT

SPDIF_IN

SCL

SDA

SDIN_B

SDOUT_B

LRCK_B

SCLK_B

MCLK_B

RST*

SDO3

SDO2

SDO1

SDO0

GPIO0 GPIO1

GPIO5

GPIO4

GPIO3

GPO0

SYNC

BCLK

SDI0

GPO1

SDI1

SCLK_A

MCLK_A

LRCK_A SDOUT_A SDIN_A

GPIO2

DGND

LGND

PP

OUT

IN

OUT

IN

OUT

IN

OUT

PP

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APPLE P/N 353S4080

AUDIO CODEC, DIGITAL BLOCKS

A7G1E1K1J2

E2

G2

G3

B8

A3

B1

C3

C2

D2

A4

B3

C1

D1

C6

B6

B2

B7

D3

H8

H7

H6

G8

G7

G6

F8

F7

F6

A6

A5

B5

B4

K3J3F3E3F1

B9

C9

C7

C5

C4

H1

H2

H3

K2

M2

N1

N3

L2

L1

M1

N2

J1

F2

U6201

CS4208-CRZR

VFBGA

21

R6302

SHORT

402

OMIT

21

R6323

100K

201

5%

MF

1/20W

2

1

R6325

201

MF

5%

100K

1/20W

1

PP6305

P3MM

SM

PLACE_NEAR=U6201.D1:5 mm

54

21

L6300

FERR-22-OHM-1A-0.055OHM

0201

11 91

11 52 91

21

R6331

201

MF

5%

22

1/20W

2

1

C6305

6.3V CERM-X6S 0402

10UF

20%

2

1

C6302

10%

0.1UF

0402

16V X7R-CERM

BYPASS=U6201.E1:F1:5 mm

2

1

C6306

6.3V CERM-X6S 0402

10UF

20%

2

1

C6307

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.A7:E3:5 mm

2

1

C6303

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.G1:F1:5 mm

2

1

C6300

4.7UF

4V

402

X5R-1

20%

2

1

C6304

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.K1:K3:5 mm

11 52 91

21

R6330

1/16W

402

5%

33

MF-LF

55

21

R6332

75

402

MF-LF

1/16W

1%

55 86

52 55 86

2

1

C6301

10%

0.1UF

BYPASS=U6201.J2:J1:5 mm

X7R-CERM 0402

16V

53

2

1

R6324

201

MF

5%

100K

1/20W

21

R6322

NOSTUFF

MF

201

1/20W

5%

100K

1

PP6302

PLACE_NEAR=U6201.F2:5 mm

P3MM

SM

1

PP6301

P3MM

SM

PLACE_NEAR=U6201.N3:5 mm

1

PP6303

P3MM

SM

PLACE_NEAR=U6201.E2:5 mm

1

PP6304

P3MM

SM

PLACE_NEAR=U6201.D2:5 mm

54

55 86

AUDIO:CODEC, DIGITAL

SYNC_MASTER=JOE_J45

SYNC_DATE=07/30/2013

PP3V3_S0

PD_CS4208_GPIO1

SPKRCONN_L_ID

CS4208_HDA_SDOUT0_R

MIN_NECK_WIDTH=0.07MM

VOLTAGE=1.5V

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM

GPIO0_SPKR_SHUTDOWN

NO_TEST=TRUE

NC_CS4208_LRCLKA

NO_TEST=TRUE

NC_CS4208_SDOUTA

NO_TEST=TRUE

NC_CS4208_LRCLKB

DMIC_SDA3

DMIC_CLK3

NO_TEST=TRUE

NC_CS4208_SCLKB

DMIC_CLK3_R

PP3V3_S0

HDA_SYNC

HDA_SDOUT

CS4208_HDA_SDOUT0_R

HDA_BIT_CLK

CS4208_SPDIF_IN

PP1V5_S0

DMIC_SDA3

TP_CS4208_HDA_SDOUT1

NO_TEST=TRUE

NC_CS4208_MCLKB

NO_TEST=TRUE

NC_CS4208_SCLKA

NO_TEST=TRUE

NC_CS4208_SDOUTB

NO_TEST=TRUE

NC_DMIC_CLK1

NO_TEST=TRUE

NC_DMIC_CLK2

SPDIF_OUT_JACK

CS4208_SPDIF_OUT

NO_TEST=TRUE

NC_DMIC_CLK0

HDA_RST_L

NO_TEST=TRUE

NC_CS4208_MCLKA

HDA_SDIN0

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

NO_TEST=TRUE

NC_CS4208_GPO1

DFET_OPENCH

DFET_OPENUS

SPKRCONN_R_ID

NO_TEST=TRUE

NC_CS4208_GPO0

<SCH_NUM>

63 OF 119

52 OF 97

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

52 91

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 52 91

52 91

11 52 91

11 12 13 15 17 19 64 67 81 84 86

52 55 86

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

IN

OUT

IN

OUT

IN

OUT

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

C6411 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6410 (CSP)

C6441 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6440 (CSP)

1ST ORDER FC (SUB) = NOM 9 HZ

1ST ORDER FC (L&R) = NOM 569 HZ

GAIN = +3 DB

APN: 353S2888 & 353S2958

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

21

L6430

FERR-1000-OHM

0402

CRITICAL

21

C6443

10%

402

CERM

CRITICAL

0.22UF

16V

21

C6444

CRITICAL

0.22UF

10%

402

CERM

16V

21

C6434

16V

CRITICAL

CERM

402

10%

0.22UF

21

C6433

16V

CRITICAL

CERM

402

10%

0.22UF

C2

A2

C3

B3

B1

A1

C1

A3

B2

U6430

SSM2375

WLCSP

CRITICAL

55 86 96

2

1

C6431

BYPASS=U6430.C2:C1:5 mm

0.1UF

10% 16V X5R-CERM 0201

C2

A2

C3

B3

B1

A1

C1

A3

B2

U6440

CRITICAL

WLCSP

SSM2375

55 86 96

2

1

C6422

CRITICAL

47UF

TANT-POLY

CASE-A4

20%

6.3V

2

1

C6432

CRITICAL

100UF

CASE-AL1

6.3V TANT

20%

2

1

C6442

CRITICAL

100UF

20%

6.3V TANT

CASE-AL1

2

1

C6436

10% X7R-CERM

0402

50V

4700PF

2

1

C6446

4700PF

10%

0402

50V X7R-CERM

2

1

C6411

0.1UF

10% 50V

BYPASS=U6410.A1:A2:5 mm

X7R 603-1

2

1

C6441

BYPASS=U6440.C2:C1:5 mm

0.1UF

10% 50V X7R 603-1

2

1

R6400

1/16W

402

MF-LF

5%

100K

21

L6401

CRITICAL

0402

FERR-1000-OHM

51 96

52

21

L6411

FERR-1000-OHM

CRITICAL

0402

55 86 96

2

1

C6421

BYPASS=U6420.A1:A2:5 mm

0201

0.1UF

10% 16V X5R-CERM

21

L6421

0402

FERR-1000-OHM

CRITICAL

51 96

55 86 96

2

1

C6412

CASE-A4

CRITICAL

6.3V

20%

TANT-POLY

47UF

21

L6410

FERR-1000-OHM

CRITICAL

0402

51 96

21

L6420

FERR-1000-OHM

CRITICAL

0402

51 96

21

C6423

0.01UF

50V

X7R-CERM

0402

10%

CRITICAL

21

C6424

0402

CRITICAL

50V

10%

X7R-CERM

0.01UF

21

C6414

CRITICAL

X7R-CERM

50V

10%

0.01UF

0402

21

C6413

10% 50V

X7R-CERM

CRITICAL

0402

0.01UF

55 86 96

C2

A1

A2

B1 C1

B2

A3 B3

C3

U6410

MAX98300

WLP

CRITICAL

2

1

R6410

100K

5%

MF-LF

402

1/16W

C2

A1

A2

B1 C1

B2

A3 B3

C3

U6420

WLP

CRITICAL

MAX98300

2

1

R6420

MF-LF

402

5%

1/16W

100K

51 96

21

L6441

0402

FERR-1000-OHM

CRITICAL

21

L6440

0402

CRITICAL

FERR-1000-OHM

51 96

21

L6431

FERR-1000-OHM

CRITICAL

0402

51 96

AUDIO: SPEAKER AMP

SYNC_MASTER=JOE_J45

SYNC_DATE=07/30/2013

LSUB_GAIN

RSUB_GAIN

PP5V_S0_AUDIO_AMP_R

SPKR_L_GAIN

SPKR_SHUTDOWN

AUD_LO2_L_P

SPKR_SHUTDOWN

AUD_LO3_L_N

AUD_LO3_L_P

AUD_LO3_R_N

AUD_LO3_R_P

AUD_LO2_R_N

SPKR_R_GAIN

AUD_LO2_R_P

AUD_LO2_L_N

LSUBIN_P

NO_TEST=TRUE

LSUBIN_N

NO_TEST=TRUE

RSUBIN_N

NO_TEST=TRUE

SPKRAMP_RIN_P

AUD_SPKRAMP_RSUBIN_P

AUD_SPKRAMP_LIN_N

NO_TEST=TRUE

SPKRAMP_LIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

SPKRCONN_SL_OUT_N

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRAMP_RIN_N

NO_TEST=TRUE

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_L_OUT_N

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_N

MIN_LINE_WIDTH=0.40 MM

NO_TEST=TRUE

RSUBIN_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_SR_OUT_N

SPKRCONN_SL_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

PP5V_S0_AUDIO_AMP_R

AUD_SPKRAMP_RSUBIN_N

GPIO0_SPKR_SHUTDOWN

SPKR_SHUTDOWN

NO_TEST=TRUE

SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LSUBIN_N

AUD_SPKRAMP_LSUBIN_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_L_OUT_P

SPKRCONN_SR_OUT_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

PP5V_S0_AUDIO_AMP_L

<SCH_NUM>

64 OF 119

53 OF 97

53 85

53

96

53 85

96

53

96

53 85

OUT

IN

OUT

IN

PSEL

CP

GND

OUT2

OUT1

VDD

PSEL

CP

GND

OUT2

OUT1

VDD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(SEE RADAR # 6210118)

R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS

51 96

2

1

R6556

5% MF

1/20W

100K

201

21

R6550

5%

2.2K

1/16W MF-LF

402

2

1

C6558

27PF

CRITICAL

25V 0201

5% C0G

21

R6559

402

2.2K

5%

MF-LF

1/16W

55 96

2

1

C6501

NP0-C0G 0402

5% 25V

1000PF

52

54 55

52

2

1

C6502

0402

5%

1000PF

NP0-C0G

25V

2

1

R6520

5%

10K

MF-LF

1/16W

402

2

1

C6542

0201

16V X5R-CERM

10%

0.1UF

BYPASS=U6501.B2::3MM

2

1

C6530

35V

10%

0402

CERM-X5R

1.0UF

2

1

C6550

3300PF

0201

10V

10% X7R-CERM

CRITICAL

2

1

C6543

10%

0201

X5R-CERM

10V

BYPASS=U6501.B2::3MM

0.01UF

B2

C2

A2

A1

B1

C1

U6500

WCSP

TAIC3027A0YFFR

B2

C2

A2

A1

B1

C1

U6501

TAIC3027A0YFFR

WCSP

2

1

C6563

0.01UF

10V X5R-CERM 0201

10%

BYPASS=U6500.B2::3MM

2

1

C6562

X5R-CERM

10%

0.1UF

16V 0201

BYPASS=U6500.B2::3MM

2

1

C6560

1.0UF

CERM-X5R 0402

10% 35V

2

1

R6521

402

1/16W MF-LF

10K

5%

SYNC_MASTER=CLEAN_X305

SYNC_DATE=06/24/2014

AUDIO: JACK

DFET_OPENCH

DFET_OPENUS

DFET_CPO1

AUD_HS_MIC_P

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.2MM

AUD_HS_MIC_N

MIN_NECK_WIDTH=0.06MM

HS_MIC_P

HS_MIC_N

AUD_CONN_SLEEVE_XW AUD_CONN_SLEEVE_XW

AUD_CONN_RING2_XW AUD_CONN_RING2_XW

DFET_CPO2

<SCH_NUM>

65 OF 119

54 OF 97

IN

IN IN

OUT

IN

OUT

IN

OUT

IN

NC

GND

VDD

AUDIO GND

SHELL

VIN

MIC

DET2 DET1 1RTN

2RTN

R.AUDIO

AUDIO GND

PINS

POF

OPERATING VOLTAGE 3.3

AUDIO

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DFET CONTROL

APN: 514-0875

SUB

DMIC 1

HEADSET MIC

LEFT SPEAKER ID RIGHT SPEAKER ID

OUTPUT

GPIO4

2-MIC CONNECTOR

APN: 518S0769

0X0E (14)

0X1C (28)

3.3V

0X09 (9)

GPIO2 INPUT GPIO3

0X21 (33)

0X13 (19)

0X12 (18)

N/A

CONVERTER

SPDIF OUT

FUNCTION

0X10 (16)

CONVERTER

MUTE CONTROL

FUNCTION

N/A

N/AHP/HS OUT

CODEC INPUT SIGNAL PATHS

HP=80HZ

INPUT

SPEAKER CONNECTOR

APN: 518S0672

0X03 (3)

0X02 (2)

PIN COMPLEX

0X07 (7)

0X18 (24)

2.7V

DMIC 2 0X1C (28)

CODEC GPIO0 CODEC GPIO0

3.3V

VREF

CODEC OUTPUT SIGNAL PATHS

PIN COMPLEX

TWEETERS

VOLUME

0X04 (4)

0X02 (2) 0X03 (3) 0X04 (4)

0X09 (9)

HIGH = DFETs OPEN

OTHER CODEC GPIO LINES

HIGH = FG, LOW = MERRY HIGH = FG, LOW = MERRY

6

5

4

3

2

1

8

7

J6602

M-RT-SM

78171-6006

CRITICAL

6

5

4

3

2

1

8

7

J6603

M-RT-SM

CRITICAL

78171-6006

53 86 96

52 86

53 86 96

52 86

53 86 96

52 86

21

R6680

402

OMIT

SHORT

51

54 96

51

21

L6606

0201

FERR-470-OHM

CRITICAL

21

L6605

CRITICAL

120-OHM-25%-1.3A

0402

21

L6607

FERR-470-OHM

CRITICAL

0201

21

L6604

0402

CRITICAL

120-OHM-25%-1.3A

51

21

L6608

0201

CRITICAL

FERR-470-OHM

2

1

C6600

10V

1UF

402-1

X5R

10%

2

1

C6601

6.3V CERM-X5R 0201

0.1UF

10%

2

1

R6601

5%

402

10K

1/16W MF-LF

21

XW6600

PLACE_NEAR=J6600.3:2.54mm

SM

21

XW6602

SM

PLACE_NEAR=J6600.5:2.54mm

21

XW6601

SM

21

XW6603

SM

5

4

3

2

1

6

7

J6601

F-RT-SM

FF14A-5C-R11DL-B-3H

2

1

DZ6607

CRITICAL

SOD882

ESDALC5-1BM2

2

1

DZ6602

SOD882

CRITICAL

ESDALC5-1BM2

2

1

DZ6606

CRITICAL

SOD882

ESDALC5-1BM2

2

1

DZ6604

CRITICAL

ESDALC5-1BM2

SOD882

2

1

DZ6601

ESDALC5-1BM2

SOD882

CRITICAL

2

1

DZ6603

SOD882

CRITICAL

ESDALC5-1BM2

2

1

DZ6605

ESDALC5-1BM2

CRITICAL

SOD882

52

2

1

C6608

25V

100PF

5%

0201

C0G

21

L6611

0402

CRITICAL

120-OHM-25%-1.3A

21

L6612

0402

CRITICAL

120-OHM-25%-1.3A

21

L6613

0402

CRITICAL

120-OHM-25%-1.3A

21

L6614

CRITICAL

0402

120-OHM-25%-1.3A

2

1

C6607

0201

25V

100PF

5% C0G

2

1

C6602

25V

0201

5%

100PF

C0G

2

1

C6605

100PF

5%

0201

25V C0G

2

1

C6606

25V

100PF

5%

0201

C0G

2

1

C6604

5%

25V

0201

100PF

C0G

2

1

C6603

25V

100PF

5%

0201

C0G

9

8 7

6

5

4

3

2

15

14

13

12

11

10

1

J6600

F-RT-TH

AUDIO-SPDIF-J44

2

1

R6603

2.2K

5%

201

1/20W MF

2

1

R6602

201

MF

1/20W

5%

2.2K

SYNC_MASTER=CLEAN_X305

SYNC_DATE=06/24/2014

AUDIO: JACK TRANSLATORS

AUD_CONN_TIPDET_2

PP3V3_S0

AUD_CONN_TYPEDET

AUD_CONN_TIPDET_1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

AUD_CONN_HP_RIGHT

MIN_NECK_WIDTH=0.06MM

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.5MM

AUD_CONN_RING2_XW

MIN_NECK_WIDTH=0.1MM

AUD_HS_MIC_P

AUD_HP_PORT_REFUS

AUD_HP_PORT_L

AUD_HP_PORT_R

GND_AUDIO_CODEC

AUD_TIPDET_2

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

AUD_CONN_RING2

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.4MM

AUD_CONN_SLEEVE

DMIC_CLK3

DMIC_SDA2

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.5MM

AUD_CONN_SLEEVE_XW

AUD_CH_HS_GND

SPKRCONN_SR_OUT_N

SPKRCONN_R_OUT_N

SPKRCONN_R_OUT_P

DMIC_SDA3

PP3V3_S0

AUD_TYPEDET

SPKRCONN_L_ID

SPKRCONN_L_OUT_P

SPKRCONN_SR_OUT_P

SPKRCONN_R_ID

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

SPKRCONN_L_OUT_N

AUD_HP_PORT_REFCH

AUD_US_HS_GND

AUD_HS_MIC_N

SPDIF_OUT_JACK

AUD_TIPDET_1

<SCH_NUM>

66 OF 119

55 OF 97

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

54

51

86

54

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

VCC

EXT INT

NC

GND

NC

POS

NEG

SYS_DETECT

SDA

POS

POS SCL

NEG NEG NEG

VER 1

NC NC

BI

NC

G

D

S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

IN

Y

B

A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Switcher limit)

NOTE: MIRROR C7093 and C7097

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

APN:353S3733

conduct and power charger and 3.42V reg

NOTE: R7097 can be replaced

by SHORT at PVT

Vout = 3.425V

send transients onto ADAPTER_SENSE when AC is

1-Wire OverVoltage Protection

6.8V Zener

The chassis ground will otherwise float and can

<Ra>

Input impedance of 22.1K meets sparkitecture requirements

518S0508

connected.

for D2 design only

518-0376

MagSafe DC Power Jack

blocking the leakage path and 22.1K can be

BATTERY CONNECTOR

When input voltage is 2V the FET will be off

Vout = 1.25V * (1 + Ra / Rb)

NOTE: MIRROR C7092 and C7096

properly detected.

When input voltage is at 16V+, FET will

300MA MAX OUTPUT

<Rb>

21

F7005

CRITICAL

0603

6AMP-32V-0.0095OHM

2

1

C7005

CERM

NOSTUFF

0.01UF

50V

0603

20%

1

3

4

2

5

U7000

CRITICAL

SC70-5

MAX9940

2

1

C7050

10%

0.1UF

25V

X7R-CERM

0402

2

1

C7060

10%

1UF

0402

CER-X6S

16V

2

1

3

D7050

CRITICAL

RCLAMP2402B

SC-75

2

1

R7050

402

5% MF-LF

10K

1/16W

2

1

C7095

C0G

22PF

50V

0201

5%

2

1

R7096

201

1/20W

MF

200K

1%

2

1

C7099

6.3V CERM-X6S 0402

10UF

20%

2

1

R7095

201

MF

1%

348K

1/20W

21

R7005

805

1/8W

10

MF-LF

5%

21

R7020

805

1%

47

1/3W

MF

3

2

1

D7005

BAT30CWFILM

SOT-323

CRITICAL

2

1

C7094

10%

402

16V

0.22UF

CERM

20 9

19 8

18 7

17 6

16 5

15 4

14 3

13 2

12 1

22 11

21 10

J7050

BAT-J5

F-ST-TH

CRITICAL

6

5

4

3

2

1

J7000

M-RT-SM

WTB-PWR-M82

CRITICAL

40

2

1

R7029

402

1/16W

2.0K

MF-LF

5%

5A

5

4

1

Q7010

POWERPAK

SI5419DU

2

1

R7010

100K

MF 201

1/20W

5%

2

1

R7012

22.1K

1% MF

1/20W 201

K

A

D7010

CDZ6.8B

SM

2

1

C7091

10%

NOSTUFF

0603

35V

4.7UF

X5R-CERM

2

1

C7090

10%

NOSTUFF

4.7UF

35V

0603

X5R-CERM

2

1

C7092

10%

0603

35V

4.7UF

X5R-CERM

2

1

C7093

10%

0603

4.7UF

35V

X5R-CERM

2

1

C7096

10%

0603

4.7UF

35V

X5R-CERM

2

1

C7097

10%

4.7UF

35V

0603

X5R-CERM

2

1

C7012

10%

0402

0.047UF

X7R

25V

21

R7011

10K

MF

1/20W

201

5%

6

9

48

7

5

1

3

2

U7090

CRITICAL

DFN

LT3470AED

2

1

C7008

402

CERM

PLACEMENT_NOTE=PLACE NEAR U7100 and U7001

0.1UF

10V

20%

40 41 42 57

4

5

3

1

2

U7001

CRITICAL

TC7SZ08FEAPE

SOT665

2

1

C7000

402

CERM

0.1UF

10V

20%

21

R7001

MF

1/20W

0201

0

5%

2

1

C7001

402

NOSTUFF

NONE NONE

NONE

OMIT

2

1

R7002

49.9K

NOSTUFF

1% MF

1/20W 201

2

1

C7098

6.3V CERM-X6S 0402

10UF

20%

2

1

R7097

402

0

5%

MF-LF

1/16W

21

L7095

2520

10UH-20%-0.85A-0.46OHM

CRITICAL

DC-In & Battery Connectors

SYNC_DATE=11/04/2014

SYNC_MASTER=CLEAN_X425

SMBUS_SMC_5_G3_SCL

SYS_DETECT_L

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

P3V42G3H_SW

P3V42G3H_BIAS

DIDT=TRUE

P3V42G3H_BOOST

PPDCIN_G3H_ISOL

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=20V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=20V

PP20V_DCIN_CONN_R

DCIN_ISOL_GATE

PPBUS_G3H

P3V42G3H_SHDN_L

PPVBAT_G3H_CONN

SMBUS_SMC_5_G3_SDA

SMC_BC_ACOK_VCC

DCIN_ISOL_GATE_R

TP_TDM_ONEWIRE_MPM

PP3V42_G3H

SYS_ONEWIRE

SMC_BC_ACOK

ADAPTER_SENSE

PP20V_DCIN_FUSE

VOLTAGE=20V

MIN_LINE_WIDTH=1MM MIN_NECK_WIDTH=0.20MM

PPDCIN_G3H

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

PP3V42_G3H

P3V42G3H_FB

<SCH_NUM>

70 OF 119

56 OF 97

40 43 57 86 95

86

44 57 84

30 44 47 57 63 65 84 86

57 86

40 43 57 86 95

19 34 37 38 40 41

42 43 50

56 57 67

84 86

86

57 84 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

OUT

IN BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

S

G

IN

NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

NCNCNC

G

S

D

S

D

S

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

f = 400 kHz

(L7130 limit)

Inrush Limiter

Reverse-Current Protection

(CHGR_CSO_P)

(PPVBAT_G3H_CHGR_R)

(GND)

20V/V

TO/FROM BATTERY

36V/V

(AGND)

(CHGR_BGATE)

(PPVBAT_G3H_CHGR_R)

353S2392

(OD)

FROM ADAPTER

30mA max load

(CHGR_CSO_N)

Divider sets ACIN threshold at 13.55V

ACIN pin threshold is 3.2V, +/- 50mV

<Rb>

AND C7199

NOTE: MIRROR C7198

AND C7191

<Ra>

100MA MAX OUTPUT

(Switcher limit)

Vout = 5.50V

For Erp Lot6 spec

NOTE: MIRROR C7190

(CHGR_SGATE)(CHGR_AGATE)

(CHGR_DCIN)

Sparkitecture impedance is set by R7112 in D2

152S1466

Vout = 1.25V * (1 + Ra / Rb)

TO SYSTEM

MIRROR C7135 AND C7136

Max Current = 8A

2

1

C7142

50V CER-X7R 0402

0.1UF

10%

2

1

C7116

470PF

CERM

50V 0402

10%

2

1

R7116

1%

MF-LF

3.01K

1/16W

402

2

1

C7115

X7R-CERM

220PF

50V

0402

10%

2

1

R7115

1/16W

5% MF-LF

330K

402

2

1

C7102

X6S-CERM

0402

1UF

10% 10V

2

1

C7100

X6S-CERM 0402

1UF

10% 10V

21

R7101

5% 1/16W MF-LF

4.7

402

2

1

C7157

0.01UF

X7R-CERM

0402

16V

10%

2

1

C7156

X7R-CERM

0402

0.1UF

16V

10%

21

XW7100

SM

PLACE_NEAR=U7100.29:1mm

PLACE_NEAR=U7100.22:1mm

2

1

C7101

X6S-CERM

0402

1UF

10% 10V

2

1

C7121

50V CER-X7R 0402

0.1UF

10%

2

1

C7122

50V

CER-X7R

0402

0.1UF

10%

2

1

C7120

X7R-CERM

0.047UF

0402

16V

10%

2

1

C7125

PLACE_NEAR=U7100.25:2mm

CERM

0.22UF

16V 402

10%

21

R7122

10

1/16W

5%

MF-LF

402

21

R7121

1/16W

10

5%

MF-LF

402

21

R7151

1/16W5%MF-LF

2.2

402

21

R7152

1/16W5%MF-LF0402

44

40 43 56 86 95

2

1

C7111

X7R-CERM

0.01UF

0402

16V

10%

2

1

C7150

16V CER-X6S 0402

1UF

10%

2

1

C7126

X7R-CERM

0.001UF

50V

0402

10%

40 41 42 56

341

2

R7120

0612-6

CRITICAL

1W

0.5%

0.02

MF

2

1

C7137

X7R-CERM

0.001UF

50V 0402

10%

2

1

C7145

0.001UF

X7R-CERM

50V 0402

10%

8

12

4

20

19

7

24

29

13

26

10

11

23

22

21

5

2

18 17

28 27

6

25

15

16 9

1

14

3

U7100

TQFN

ISL6259

CRITICAL

2

1

R7102

5% MF-LF

100K

1/16W

NO STUFF

402

67

321

4

5

Q7155

SO-8

SI7137DP

CRITICAL

3

2

1

D7105

CRITICAL

BAT30CWFILM

SOT-323

2

1

R7112

1% 1/16W MF-LF

1K

402

321

4

5

Q7130

NTMFS4C06N

CRITICAL

DFN

2

1

C7140

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

16V

20%

21

R7105

5%

1/16W

20

MF-LF

402

2

1

C7135

PLACE_NEAR=Q7130.5:2mm

CRITICAL

35V

1.0UF

CERM-X6S 0402

10%

2

1

C7136

PLACE_NEAR=Q7130.5:2mm

CRITICAL

35V CERM-X6S

1.0UF

0402

10%

2

1

C7155

25V X7R

0603

1UF

10%

21

R7100

1/16W

5%

MF-LF

0

402

40 41

50

86

2

1

C7185

X7R-CERM 0402

0.1UF

25V

10%

2

1

R7185

1% 1/16W MF-LF

470K

402

2

1

R7186

1% 1/16W MF-LF

332K

402

2

1

R7181

5% MF-LF

1/16W

62K

402

2

1

R7180

1/16W

5% MF-LF

100K

402

21

F7141

8AMP-32V-0.006OHM

CRITICAL

0603

21

F7140

0603

CRITICAL

8AMP-32V-0.006OHM

4 3

2 1

R7150

MF

1W

0612-6

0.005

1%

CRITICAL

21

L7130

CRITICAL

PIME173T-SM

4.7UH-20%-14.5A-9MOHM

2

1

C7130

35V CASE-D2-SM

TANT-POLY

CRITICAL 10UF

20%

2

1

C7131

TANT-POLY

35V CASE-D2-SM

CRITICAL

10UF

20%

2

1

C7132

CRITICAL

CASE-D2-SM

TANT-POLY

35V

10UF

20%

2

1

C7133

CASE-D2-SM

TANT-POLY

35V

CRITICAL

10UF

20%

2

1

C7134

CRITICAL

35V TANT-POLY CASE-D2-SM

10UF

20%

2

1

R7142

1/16W MF-LF

5%

1K

402

2

1

R7195

1% MF

201

1/20W

681K

2

1

C7198

PLACE_SIDE=TOP

CRITICAL

6.3V CERM-X6S 0402

10UF

20%

2

1

R7196

1% MF

201

200K

1/20W

2

1

C7194

CERM

0.22UF

16V 402

10%

21

L7195

DP418C-SM

CRITICAL

33UH-20%-0.39A-0.435OHM

2

1

C7195

5%

22PF

0201

C0G

50V

2

1

C7190

0603

PLACE_SIDE=TOP

35V

4.7UF

10%

X5R-CERM

6

9

48

7

5

1

3

2

U7190

DFN

CRITICAL

LT3470A

21

R7190

0

MF-LF

5%

1/16W

NOSTUFF

402

2

1

C7199

PLACE_SIDE=BOTTOM

CRITICAL

6.3V CERM-X6S 0402

10UF

20%

2

1

C7105

CER-X7R

0603

0.22UF

50V

10%

2

1

R7110

1/16W

1% MF-LF

130K

402

2

1

R7111

1% 1/16W MF-LF

40.2K

402

2

1

C7180

NONE

OMIT

603

NONE NONE

NOSTUFF

251

4

3

6

1097

8

Q7180

CRITICAL

IRF9395TRPBF

DIRECTFET-MC

2

1

C7191

0603

35V

PLACE_SIDE=BOTTOM

4.7UF

10%

X5R-CERM

321

4

5

Q7135

NTMFS4C10N

CRITICAL

DFN

SYNC_DATE=01/15/2014

SYNC_MASTER=CLEAN_X305

PBus Supply & Battery Charger

MIN_NECK_WIDTH=0.25 mm VOLTAGE=20V

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm

CHGR_CSI_N

CHGR_CSI_P

CHGR_CSO_R_N

VOLTAGE=12.6V

PPVBAT_G3H_CHGR_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PP5V1_CHGR_VDDP

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P5V1_SW

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

PP3V42_G3H

CHGR_DCIN_D_R

VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CHGR_LGATE

CHGR_AGATE

P5V1_FB

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

P5V1_BOOST

CHGR_DCIN

CHGR_DCIN_D_R

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

GND_CHGR_AGND

CHGR_CSO_R_P

CHGR_AGATE_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_CELL

CHGR_VNEG_R

SMBUS_SMC_5_G3_SDA

CHGR_ICOMP_RC

CHGR_VNEG

CHGR_RST_L

SMBUS_SMC_5_G3_SCL

CHGR_AMON

SMC_RESET_L

CHGR_ICOMP

CHGR_VCOMP_R

CHGR_BMON SMC_BC_ACOK

CHGR_CSO_N

PPVBAT_G3H_CONN

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

CHGR_CSI_R_N

CHGR_CSI_R_P

MIN_NECK_WIDTH=0.25 mm

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm VOLTAGE=20V

PPDCIN_G3H

PPDCIN_G3H_ISOL

CHGR_SGATE

CHGR_DCIN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=0V

GND_CHGR_AGND

DIDT=TRUE

CHGR_PHASE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

CHGR_UGATE

DIDT=TRUE

CHGR_BOOT

CHGR_VFRQ

CHGR_VCOMP

CHGR_ACIN

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_R

VOLTAGE=12.6V

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

CHGR_BGATECHGR_CSO_P

<SCH_NUM>

71 OF 119

57 OF 97

95

96

57

19 34 37 38 40 41 42 43 50 56 67 84 86

57

30 44 47 56 63 65 84 86

57

96

95

56 86

96

56 84 86

44 56 84

57

95

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

NC

NC NC

OUT OUT OUT

NC

IN IN IN

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(CPUVR_ISUMP)

(GND)

(CPU_VCCSENSE_N)

8

89

8

89

8

89

18 19 40 67 86

6

40 41 89

2

1

R7279

PLACE_NEAR=U7200.32:2mm

54.9

1% MF

1/20W

201

2

1

R7280

1%

110

MF

1/20W 201

PLACE_NEAR=U7200.30:2mm

1

4

17

16

33

29

30

32

13

23 22 2026

27

28

2

5

24

21

19

9

15 14

10

11

12

3

18

8

7

25

6

31

U7200

ISL95826AHRZ-_S2378

LLP

CRITICAL

19

59

21

R7224

1%

1/16W

0402

2.49M

MF

21

R7202

1/16W MF-LF

10

402

5%

2

1

C7202

0.22UF

PLACE_NEAR=U7200.17:2mm

X7R

25V

0402

10%

21

R7201

1/16W MF-LF

402

1

5%

2

1

C7201

PLACE_NEAR=U7200.16:2mm

10V X6S-CERM 0402

1UF

10%

59

2

1

C7210

20% X6S-CERM

0.22UF

6.3V 0201

2

1

C7211

0.22UF

X6S-CERM

20%

6.3V 0201

2

1

C7212

0.22UF

X6S-CERM

20%

6.3V 0201

59

2

1

C7213

6.3V X6S

0201

0.1UF

10%

2

1

R7220

4.02K

1% MF

1/20W 201

2

1

R7221

201

1%

154K

MF

1/20W

45

2

1

R7230

93.1K

201

1/20W MF

1%

2

1

C7230

1500PF

X7R

10V

0201

10%

59

2

1

C7214

X7R-CERM

201

25V

220PF

NO_XNET_CONNECTION=TRUE

10%

21

R7215

201

845

1%

1/20W

MF

21

C7215

X7R-CERM

2700PF

201

10V

10%

21

C7216

5%

25V

NP0-C0G

39PF

0201

8

89

9

89

2

1

C7260

X7R

16V

330PF

0201

10%

2

1

C7261

X7R

16V

330PF

0201

10%

2

1

C7240

X7R-CERM

1800PF

25V

0201

10%

2 1

C7242

C0G

5%

25V

100PF

NO_XNET_CONNECTION=TRUE

0201

2

1

C7241

C0G

5%

25V

18PF

NO_XNET_CONNECTION=TRUE

0201

2

1

R7240

365K

1% MF

1/20W

201

NO_XNET_CONNECTION=TRUE

2 1

R7242

1K

1%

201

MF

1/20W

NO_XNET_CONNECTION=TRUE

21

R7243

MF

1/20W

0

5%

0201

21

R7235

201

MF

9.31K

1%

1/20W

2

1

R7236

201

95.3K

1% MF

1/20W

2

1

R7237

100KOHM

0201

21

R7250

NO_XNET_CONNECTION=TRUE

NO STUFF

201

2K

1/20W

MF

1%

2

1

C7250

X7R

16V

330PF

NO STUFF

0201

10%

21

R7241

201

1/20W

MF

1%

2.94K

21

R7210

1/20W

1%

487

MF

201

2

1

R7223

102K

MF

1% 1/20W

201

2

1

R7222

9.31K

201

1% MF

1/20W

2

1

C7231

C0G

5%

47PF

25V

0201

2

1

C7279

0402

16V X7R-CERM

0.01UF

10%

CPU VR12.5 VCC Regulator IC

SYNC_MASTER=CLEAN_X425

SYNC_DATE=01/09/2015

CPU_VIDSOUT

CPU_VIDSCLK

CPUVR_ISUMN

CPU_VIDALERT_L

CPUVR_NTC_R

CPUVR_PROG1

CPU_PROCHOT_L

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.3 mm

PP5V_S0_CPUVR_VDD

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=12.9V

MIN_NECK_WIDTH=0.2 mm

CPUVR_FB_RC

PP5V_S0

CPUVR_DRSEL

CPUVR_FCCM

CPUVR_PWM2

CPUVR_PWM3

CPUVR_PGOOD

PPVIN_S5_HS_COMPUTING_ISNS

CPUVR_PWM1

CPU_VCCSENSE_P

ALL_SYS_PWRGD

CPUVR_PROG3

CPUVR_SLOPE

CPUVR_ISUMN_RC

CPUVR_ISUMN_R

CPUVR_COMP_RC

CPUVR_ISEN1

CPUVR_PROG2

CPUVR_NTC

PPVCCIO_S0_CPU

CPUVR_IMON

CPUVR_FB2

CPUVR_COMP

CPUVR_ISUMP

CPUVR_ISEN3

CPU_VCCSENSE_N

CPU_VCCSENSE_P_RC

CPU_VCCSENSE_P_R

CPUVR_ISEN2

CPUVR_FB

<SCH_NUM>

72 OF 119

58 OF 97

18 19 36 49 59 62 63 66 67 73 79 80 84 85 86

44 59 60 62 84

5 6 8

10 18

IN

OUT

IN

OUT

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

IN

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

IN

OUTOUT

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

f = 450 kHz

THESE TWO CAPS ARE FOR EMC

152S1538

353S3836

PHASE 2

PHASE 3

PHASE 1

353S3836

152S1538

THESE TWO CAPS ARE FOR EMC

95A max output

Vout = 1.85V max

THESE TWO CAPS ARE FOR EMC

Additonal Input Bulk Caps

152S1538

2

1

C7372

CRITICAL

68UF

POLY-TANT CASE-D2E-SM

16V

20%

2

1

C7371

CRITICAL

68UF

CASE-D2E-SM

POLY-TANT

16V

20%

2

1

C7370

16V

20%

POLY-TANT CASE-D2E-SM

CRITICAL

68UF

2

1

C7319

0.001UF

10% 50V X7R-CERM 0402

2

1

C7318

0.001UF

10%

0402

50V X7R-CERM

2

1

C7317

1UF

10%

0402

X6S-CERM

16V

2

1

C7316

10UF

20% X6S-CERM

16V

CRITICAL

NOSTUFF

0603

2

1

C7315

X6S-CERM

NOSTUFF

CRITICAL

10UF

16V

20%

0603

43

21

R7310

0.00075

0612-1

MF

1W

1%

CRITICAL

2

1

R7314

3.9

1%

201

MF

1/20W

NO_XNET_CONNECTION=TRUE

2

1

C7314

CRITICAL

68UF

16V

20%

CASE-D2E-SM

POLY-TANT

2

1

C7313

68UF

16V

20%

POLY-TANT CASE-D2E-SM

CRITICAL

21

L7310

PIMS103T-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

2

1

R7312

NOSTUFF

5%

2.2

1/10W MF-LF

603

2

1

C7312

0402

X7R-CERM

10% 50V

NOSTUFF

0.001UF

58

58 59

2

1

C7373

CRITICAL

68UF

POLY-TANT CASE-D2E-SM

16V

20%

2

1

R7316

NO_XNET_CONNECTION=TRUE

1%

201

MF

1/20W

10K

2

1

R7315

NO_XNET_CONNECTION=TRUE

1/20W

1K

MF

1%

201

58

58 59

21

R7317

10K

1/20W

1% MF

201

NO_XNET_CONNECTION=TRUE

2

1

C7329

X7R-CERM 0402

50V

10%

0.001UF

58 59

2

1

C7328

0402

X7R-CERM

0.001UF

50V

10%

2

1

C7327

10% X6S-CERM

0402

1UF

16V

2

1

R7324

3.9

1%

201

MF

1/20W

NO_XNET_CONNECTION=TRUE

2

1

C7326

10UF

NOSTUFF

CRITICAL

X6S-CERM

16V

0603

20%

2

1

C7325

0603

16V

10UF

NOSTUFF

CRITICAL

20% X6S-CERM

2

1

C7324

CASE-D2E-SM

POLY-TANT

20% 16V

68UF

CRITICAL

2

1

C7323

CRITICAL

20%

CASE-D2E-SM

68UF

16V POLY-TANT

21

L7320

PIMS103T-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

2

1

C7322

X7R-CERM

0.001UF

NOSTUFF

10% 50V

0402

2

1

R7326

NO_XNET_CONNECTION=TRUE

10K

1/20W 201

MF

1%

2

1

R7325

NO_XNET_CONNECTION=TRUE

1%

1K

201

MF

1/20W

2

1

R7322

NOSTUFF

5%

603

1/10W MF-LF

2.2

58

2

1

C7339

0402

50V

0.001UF

10% X7R-CERM

58 59

2

1

C7338

0.001UF

10% 50V X7R-CERM 0402

2

1

C7337

10% 16V

0402

1UF

X6S-CERM

2

1

R7334

1/20W MF 201

1%

3.9

NO_XNET_CONNECTION=TRUE

2

1

C7336

X6S-CERM 0603

10UF

CRITICAL

NOSTUFF

20% 16V

2

1

C7335

20%

0603

CRITICAL

NOSTUFF

16V X6S-CERM

10UF

2

1

C7334

20% 16V

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

2

1

C7333

20%

68UF

16V

CASE-D2E-SM

POLY-TANT

CRITICAL

21

L7330

0.36UH-20%-36A-0.00108OHM

CRITICAL

PIMS103T-SM

2

1

C7332

NOSTUFF

0402

X7R-CERM

10% 50V

0.001UF

2

1

R7336

NO_XNET_CONNECTION=TRUE

1/20W

10K

MF

1%

201

2

1

R7335

NO_XNET_CONNECTION=TRUE

1K

201

1% MF

1/20W

2

1

R7332

NOSTUFF

2.2

5%

MF-LF

603

1/10W

58

58 59

58

58 59

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25

2423222120

19

18

282726

17

16

8

36

6

39

41

37

5

4

U7310

FDMF6808N

CRITICAL

PQFN

1 2

R7311

5%

MF-LF

0

402

1/16W

21

C7311

10% 16V

CERM

402

0.22UF

2

1

C7310

1UF

16V

10%

X6S-CERM

0402

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25242322212019

18

282726

17

16

8

36

6

39

41

37

5

4

U7320

CRITICAL

PQFN

FDMF6808N

2

1

C7320

1UF

16V

10%

X6S-CERM

0402

1 2

R7321

5%

MF-LF

1/16W

0

402

21

C7321

10% 16V

CERM

0.22UF

402

58 59

2

1

C7330

0402

X6S-CERM

10% 16V

1UF

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25242322212019

18

282726

17

16

8

36

6

39

41

37

5

4

U7330

FDMF6808N

PQFN

CRITICAL

1 2

R7331

0

1/16W MF-LF

5%

402

21

C7331

402

0.22UF

CERM

16V

10%

58

58 59

4 3

2 1

R7320

0612-1

MF

1% 1W

0.00075

CRITICAL

43

21

R7330

1%

0.00075

CRITICAL

1W MF

0612-1

2

1

C7376

20% 16V

CASE-D2E-SM

POLY-TANT

CRITICAL

68UF

2

1

C7375

20% 16V POLY-TANT CASE-D2E-SM

68UF

CRITICAL

2

1

C7374

16V

20%

68UF

POLY-TANT CASE-D2E-SM

CRITICAL

2

1

C7377

20%

15UF

TANT SM

16V

CRITICAL

2

1

C7378

CRITICAL

16V

20%

15UF

TANT SM

2

1

C7379

CRITICAL

16V

20%

15UF

TANT SM

2

1

C7380

CRITICAL

16V

20%

15UF

TANT SM

21

R7318

10K

NO_XNET_CONNECTION=TRUE

1/20W

1% MF

201

21

R7327

MF

1/20W

201

10K

1%

NO_XNET_CONNECTION=TRUE

21

R7328

MF

1/20W

201

10K

1%

NO_XNET_CONNECTION=TRUE

21

R7337

MF

1/20W

201

10K

1%

NO_XNET_CONNECTION=TRUE

21

R7338

NO_XNET_CONNECTION=TRUE

1%

10K

201

1/20W

MF

45 59 96 45 96

45 96 45 59 96

2

1

C7340

CRITICAL

NP0-C0G

12PF

25V

5% 0201

2

1

C7341

CRITICAL

NP0-C0G

25V

3.0PF

+/-0.1PF

0201

SYNC_DATE=01/09/2015

CPU VR12.5 VCC Power Stage

SYNC_MASTER=CLEAN_X425

MIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE2

MIN_LINE_WIDTH=1.5 MM

SWITCH_NODE=TRUE

DIDT=TRUE

CPUVR_ISNS3_N

CPUVR_ISEN2 CPUVR_ISUMP

CPUVR_ISUMN

CPUVR_ISNS1_N

CPUVR_ISNS3_N

CPUVR_PHASE3_K

CPUVR_PHASE2_K

CPUVR_PHASE1_K

PP5V_S0

CPUVR_PWM1

CPUVR_ISNS2_N

PP5V_S0

CPUVR_PWM3

CPUVR_FCCM

CPUVR_PWM2

CPUVR_ISUMP

CPUVR_FCCM

CPUVR_ISNS1_N

CPUVR_ISNS3_N

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISEN3

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT2

CPUVR_PH3_SNUB

DIDT=TRUE

CPUVR_BOOT1_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT3_RC

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUVR_BOOT1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT3

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

SWITCH_NODE=TRUE

CPUVR_PHASE3

MIN_NECK_WIDTH=0.2 MM

CPUVR_PH2_SNUB

DIDT=TRUE

SWITCH_NODE=TRUE

CPUVR_PHASE1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU_PH1

CPUVR_ISUMN

CPUVR_ISEN1

CPUVR_ISNS2_N

PPVCC_S0_CPU_PH2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V

PPVCC_S0_CPU_PH3

CPUVR_ISNS3_P

CPUVR_ISUMN

PP5V_S0

PPVCC_S0_CPU

CPUVR_ISNS2_P

CPUVR_ISUMP

PPVIN_S5_HS_COMPUTING_ISNS

CPUVR_PH1_SNUB

DIDT=TRUE

CPUVR_ISNS1_P

<SCH_NUM>

73 OF 119

59 OF 97

45 59 96

18 19 36 49 58 59 62 63 66 67

73 79 80 84 85

86

45 59 96

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

45 59 96

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

6 8

10 45 84 86

44 58 60 62 84

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

f = 400 kHz

(Q7335 limit)

Vout = 1.35V 18A max output

DDR3L (1V35 S3) REGULATOR

10mA max load

(DDRREG_DRVL)

(DDRREG_LL)

152S0905

NOTE: MIRROR C7432 and C7434

(DDRREG_VDDQSNS)

C7460, C7461, C7462, C7463 close to memory NOTE:MIRROR C7460, C7462 and C7461, C7463

(DDRREG_DRVH)

(VDDQ/VTTREF Enable)

(VTT Enable)

2

1

C7400

BYPASS=U7400.12:10:5MM

6.3V

CERM-X6S

0402

10UF

20%

2

1

C7430

16V

CASE-D2E-SM

POLY-TANT

CRITICAL

68UF

20%

2

1

C7431

16V

CASE-D2E-SM

POLY-TANT

CRITICAL

68UF

20%

21

C7425

10%

0402

25V

0.1UF

X7R-CERM

2

1

C7433

10%

0402

50V X7R-CERM

0.001UF

2

1

C7440

270UF

2V CASE-B4-SM

TANT

CRITICAL

20%

21

L7430

0.68UH-18A-3.3MOHM

CRITICAL

PCMB103T

2

1

C7441

2V

TANT

CRITICAL

CASE-B4-SM

270UF

20%

2

1

C7445

0402

X6S

4V

10UF

20%

2

1

C7446

10%

0402

X7R-CERM

50V

0.001UF

67

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

U7400

CRITICAL

QFN

TPS51916

67

21

XW7460

PLACE_NEAR=C7461.1:3mm

SM

2

1

XW7400

SM

2

1

C7450

10%

0.22UF

402

CERM

16V

BYPASS=U7400.5:7:5mm

2

1

C7460

0402

4V

PLACE_NEAR=C2730.1:1mm

PLACE_SIDE=TOP

X6S

10UF

20%

21 85

2

1

C7415

10%

0402

X7R-CERM

0.1UF

16V

2

1

C7461

0402

PLACE_SIDE=TOP

PLACE_NEAR=C2724.1:3mm

4V X6S

10UF

20%

2

1

R7417

402

200K

MF-LF

1% 1/16W

2

1

R7415

402

1% 1/16W MF-LF

19.6K

2

1

R7416

402

MF-LF

1/16W

1%

60.4K

2

1

C7416

10% 0402

16V

0.01UF

X7R-CERM

2

1

C7401

BYPASS=U7400.2:10:5MM

6.3V

CERM-X6S

0402

10UF

20%

8

7

6

1

4

3

9

5

Q7430

CRITICAL

CSD58872Q5D

SON5X6

2

1

R7418

402

1/16W

1% MF-LF

52.3K

2

1

C7435

16V

TANT

SM

15UF

CRITICAL

20%

2

1

C7462

0402

PLACE_SIDE=BOTTOM

4V

X6S

10UF

20%

2

1

C7463

0402

4V

PLACE_SIDE=BOTTOM

X6S

10UF

20%

2

1

C7447

0402

4V X6S

10UF

20%

21

R7401

201

MF

1/20W

1%

10

2

1

C7432

10%

1.0UF

0402

X6S

25V

2

1

C7434

10%

1.0UF

0402

X6S

25V

21

R7425

402

MF-LF

1/16W

5%

0

2

1

C7464

0402

PLACE_NEAR=U7400.3:3mm

4V X6S

10UF

20%

2

1

C7465

0402

PLACE_NEAR=U7400.3:3mm

X6S

4V

10UF

20%

SYNC_DATE=01/15/2014

1.35V DDR3L SUPPLY

SYNC_MASTER=CLEAN_X305

PP5V_S3

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVH

DIDT=TRUE

DDRREG_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

SWITCH_NODE=TRUE

PPVTT_S0_DDR

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V

PPVTTDDR_S3

DDRREG_VDDQSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VTTSNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVL

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_1V8_VREF

DDRREG_FB

PPVIN_S5_HS_COMPUTING_ISNS

PP1V35_S3

MEMVTT_EN

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VSW

DDRREG_PGOOD

DDRREG_MODE

DDRREG_EN

DDRREG_TRIP

PP1V35_S3

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST_R

MIN_NECK_WIDTH=0.17 mm

<SCH_NUM>

74 OF 119

60 OF 97

21 36 66 67 84 86

84

86

44 58 59 62 84

21 45 60 66 84 86

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

G2

S2

D1

S1/D2

G1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: MIRROR C7540 and C7541

NOTE: MIRROR C7581 and C7586

NOTE: Change R7562 to XW7562 at PVT

NOTE: Change R7522 to XW7522 at PVT

11A MAX OUTPUT

152S0754

F = 400 KHZ

VOUT = 3.3V

F = 400 KHZ

VOUT = 5.0V

(P5VP3V3_VREF2) (P5VP3V3_VREF2)

VOUT = 5V

10A MAX OUTPUT

100MA MAX OUTPUT

2

1

C7500

10%

1UF

25V

0603

X7R

2 1

L7560

CRITICAL

1.0UH-22A

PCMC063T-SM

2

1

C7564

10%

0402

25V

X7R-CERM

0.1UF

2

1

C7590

6.3V CERM-X6S 0402

10UF

20%

2

1

C7524

10%

0402

25V X7R-CERM

0.1UF

2

1

C7552

POLY-TANT

6.3V

330UF

CRITICAL

CASE-D3L-SM

20%

2

1

C7550

CRITICAL

6.3V

CERM-X6S

0402

10UF

20%

2

1

C7581

10%

1.0UF

0402

X6S

25V

2

1

C7503

0402

2.2UF

CER-X6S

10V

20%

2

1

C7505

6.3V CERM-X6S 0402

10UF

20%

2

1

R7506

402

1%

249K

1/16W MF-LF

67

2

1

XW7561

PLACE_NEAR=L7560.2:3MM

SM

2

1

C7501

10%

0.22UF

402

CERM

16V

2

1

R7560

402

MF-LF

1/16W

1%

23.2K

2

1

R7561

402

1/16W

1%

MF-LF

10K

2

1

R7520

0.1%

0402

MF

40.2K

1/16W

2

1

R7521

0.1%

0402

MF

10K

1/16W

2

1

C7580

POLY-TANT

CASE-D2E-SM

16V

68UF

CRITICAL

20%

21

C7588

10% X5R

402

0.15UF

10V

2

1

XW7560

SM

PLACE_NEAR=L7560.1:3MM

21

C7518

10% X5R

402

0.15UF

10V

21

R7547

402

3.24K

MF-LF

1%

1/16W

2

1

R7556

402

1/16W

1%

MF-LF

4.75K

2

1

XW7520

SM

PLACE_NEAR=L7520.1:3MM

2

1

XW7521

PLACE_NEAR=L7520.2:3MM

SM

2

1

R7536

402

12.1K

1% 1/16W MF-LF

2

1

R7537

402

10K

MF-LF

1% 1/16W

2

1

C7537

0402

CERM

15PF

5%

50V

2

1

C7592

330UF

POLY-TANT CASE-D3L-SM

6.3V

CRITICAL

20%

2

1

R7539

402

20.0K

1/16W

1%

MF-LF

2

1

C7539

0402

CER

47PF

5% 50V

2

1

R7538

402

12.1K

MF-LF

1% 1/16W

67

2

1

C7599

10%

0402

50V

X7R-CERM

NO STUFF

0.0033UF

2

1

R7599

1/10W

5%

1

MF-LF 603

NO STUFF

2

1

R7598

5%

NO STUFF

1/10W

603

MF-LF

10

2

1

C7572

10%

0402

50V

X7R-CERM

0.001UF

2

1

C7583

10% 0402

0.001UF

X7R-CERM

50V

2

1

C7570

10% 0402

0.001UF

50V X7R-CERM

2

1

C7571

10% 0402

X7R-CERM

50V

0.001UF

29

22

13

23

16

9

26

31

2

33

25

32

19

6

3

20

5

14

11

28

21

4

12

27

30

24

1

18

7

17

8

15

10

U7501

QFN

TPS51980

CRITICAL

2

1

C7542

POLY-TANT

CASE-D2E-SM

CRITICAL

16V

68UF

20%

2

1

C7582

CASE-D2E-SM

16V

POLY-TANT

68UF

CRITICAL

20%

40 41 67

21

R7546

402

1K

1%

MF-LF

1/16W

2

1

R7516

402

1% MF-LF

1/16W

4.02K

2

1

C7541

10%

1.0UF

0402

X6S

25V

67

40 67

2

1

C7598

10%

0402

X7R-CERM

NO STUFF

0.001UF

50V

2

1

XW7500

PLACE_NEAR=U7501.28:1MM

SM

8

7

6

1

4

3

9

5

Q7520

CRITICAL

SON5X6

CSD58872Q5D

2

1

R7500

0201

MF

0

5%

1/20W

SKIP_5V3V3:AUDIBLE

2

1

R7501

MF

1/20W

0201

5%

0

SKIP_5V3V3:INAUDIBLE

2

1

C7553

POLY-TANT

6.3V CASE-B2-SM

150UF-0.035OHM

CRITICAL

20%

2

1

C7554

150UF-0.035OHM

6.3V

POLY-TANT

CASE-B2-SM

CRITICAL

20%

2

1

C7593

6.3V

CRITICAL

POLY-TANT

150UF-0.035OHM

CASE-B2-SM

20%

2

1

L7520

PCMB103T-SM

CRITICAL

2.2UH-20%-13A-9MOHM

2

1

C7536

10% 402

CERM

100V

4700PF

2

1

C7538

10% 402

CERM

100V

4700PF

2

1

C7594

POLY-TANT

CASE-B2-SM

CRITICAL

6.3V

150UF-0.035OHM

20%

2

1

C7555

NO STUFF

150UF-0.035OHM

6.3V POLY-TANT CASE-B2-SM

CRITICAL

20%

2

1

C7585

CRITICAL

SM

15UF

16V

TANT

20%

2

1

C7584

SM

16V

TANT

15UF

CRITICAL

20%

2

1

C7543

CRITICAL

16V

SM

TANT

15UF

20%

2

1

C7544

CASE-D2E-SM

POLY-TANT

16V

68UF

CRITICAL

20%

2

1

C7551

CRITICAL

6.3V

CERM-X6S

0402

10UF

20%

2

1

C7591

6.3V CERM-X6S 0402

10UF

20%

2

1

R7522

402

10

MF-LF

5% 1/16W

PLACE_NEAR=L7520.1:3MM

2

1

R7562

402

10

MF-LF

1/16W

5%

PLACE_NEAR=L7560.2:3MM

21

R7564

402

1

1/16W MF-LF

5%

21

R7545

402

MF-LF

1/16W

5%

1

2

1

C7540

10%

1.0UF

0402

X6S

25V

2

1

C7586

10%

1.0UF

0402

X6S

25V

7

6

5

10

8

1

9

4

3

2

Q7560

NTMFD4951NF

DFN8

CRITICAL

SYNC_DATE=11/04/2014

SYNC_MASTER=CLEAN_X425

5V / 3.3V Power Supply

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS4_VSW

PP5V_S5

SWITCH_NODE=TRUE

P3V3S5_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P3V3S5_VBST_R

PPVIN_S5_HS_OTHER3V3_ISNS

P5VP3V3_VREF2

GND_5V3V3_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

P3V3S5_DRVL

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PP3V3_S5

DIDT=TRUE

P3V3S5_CSP2_R

P3V3S5_CSN2

SMC_PM_G2_EN

DIDT=TRUE

SWITCH_NODE=TRUE

P5VS4_LL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS4_VBST_R

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

P5VS4_COMP1

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

P5VS4_DRVH

P5VP3V3_SKIPSEL

P5VS4_PGOOD

GATE_NODE=TRUE

DIDT=TRUE

P5VS4_DRVL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

P5VS4_EN

P3V3S5_VFB2_R

S5_PWRGD

PP5V_S4

P5VS4_COMP1_R

P3V3S5_EN

P5VS4_VFB1_R

P5VS4_CSP1_R

DIDT=TRUE

P3V3S5_COMP2_R

P3V3S5_CSP2

P5VP3V3_VREG3

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS4_VBST

PPVIN_S5_HS_OTHER5V_ISNS

P5VS4_CSP1

P3V3S5_VFB2 P3V3S5_COMP2

P3V3S5_RF

P5VS4_CSN1

P5VS4_VFB1

PP5V_S4

<SCH_NUM>

61 OF 97

75 OF 119

66 84 86

44 84

12 14 15 17 18 19 21 31 32 33

64 66 67 82 84

85 86 96

37 38 51 61 66 67 69 81 84 86

44 84

37 38 51 61 66 67 69 81 84 86

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

OUT

G2

S2

D1

S1/D2

G1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Vout = 1.05V 12A MAX OUTPUT f = 500 kHz

NOTE: MIRROR C7624 and C7625

(P1V05S0_LL)

376S00043

152S0955

OCP = R7641 x 8.5uA / R7640 OCP = 14.4A

(PCHVCCIOS0_OCSET)

(PCHVCCIOS0_VO)

1V05 S0 REGULATOR

Vout = 0.5V * (1 + Ra / Rb)

2

1

R7644

402

1/16W

1%

3.01K

MF-LF

NO_XNET_CONNECTION=TRUE

67

2

1

C7602

2.2UF

CER-X6S

0402

BYPASS=U7600.13:1:5mm

10V

20%

2

1

R7603

1/16W 402

5% MF-LF

0

NO STUFF

21

XW7600

SM

PLACE_NEAR=U7600.1:1mm

8

13

11

4

2

14

10

9

16

7

15

1

5

6

3 12

U7600

UTQFN

CRITICAL

ISL95870

2

1

R7601

402

5% 1/16W MF-LF

2.2

2

1

C7601

BYPASS=U7600.14:16:5mm

6.3V CERM-X6S 0402

10UF

20%

2

1

C7630

10%

1UF

0402

CER-X6S

16V

2 1

C7640

10%

0402

0.0018UF

50V

X7R-CERM

2

1

C7623

0402

25V

PLACE_NEAR=L7630.2:1.5mm

CERM

1000PF

5%

2

1

C7620

16V

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20%

2

1

C7621

16V

POLY-TANT

CASE-D2E-SM

CRITICAL

68UF

20%

2

1

C7622

0402

25V

1000PF

CERM

BYPASS=Q7630.2:5:6mm

5%

2

1

C7648

CASE-B4-SM

TANT

CRITICAL

2V

270UF

20%

34

12

R7640

CRITICAL

0.001

0612

1% 1W

MF-3

2

1

C7649

2V

CASE-B4-SM

TANT

270UF

CRITICAL

20%

2

1

R7630

1/10W

5%

603

0

MF-LF

2

1

C7604

0402

10PF

5%

50V

CERM

21

XW7601

SM

PLACE_NEAR=U1100.AJ12:1MM

21

XW7602

PLACE_NEAR=U1100.AK14:1MM

SM

2

1

R7642

1.37K

1/20W

1% MF

201

2

1

R7641

1.37K

1% MF

1/20W

201

2

1

C7605

0402

10PF

5% 50V CERM

21

L7630

CRITICAL

PCMC063T-SM

0.68UH-25A-5.5MOHM

45 62 96

2

1

C7624

10%

1.0UF

0402

X6S

25V

BYPASS=Q7630.2:5:6mm

2

1

C7625

10%

1.0UF

0402

X6S

25V

BYPASS=Q7630.2:5:6mm

7

6

5

10

8

1

9

4

3

2

Q7630

CRITICAL

DFN8

NTMFD4951NF

2

1

C7603

10% 0402

16V X7R-CERM

0.047UF

2

1

R7645

402

1/16W

1% MF-LF

2.74K

2

1

R7605

402

1%

MF-LF

2.74K

1/16W

2

1

R7604

402

MF-LF

1/16W

1%

3.01K

NO_XNET_CONNECTION=TRUE

1V05V POWER SUPPLY

SYNC_MASTER=CLEAN_X305_PEG

SYNC_DATE=02/18/2014

P1V05S0_FB P1V05S0_SREF P1V05S0_VO P1V05S0_OCSET

P1V05S0_RTN

P1V05S0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

PP5V_S0_P1V05S0_VCC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

P1V05S0_BOOT_RC

DIDT=TRUE

P1V05S0_CS_P

VOLTAGE=1.05V

PP1V05_S0_REG_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_EN

MAKE_BASE=TRUE

P1V05S0_CS_P

P1V05S0_CS_N

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

DIDT=TRUE

P1V05S0_DRVL

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

P1V05S0_VBST

PP1V05_S0

MAKE_BASE=TRUE

P1V05S0_CS_N

MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVH

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

P1V05S0_FSEL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_LL

DIDT=TRUE

PPVIN_S5_HS_COMPUTING_ISNS PP5V_S0

P1V05S0_SENSE_P

P1V05S0_PGOOD

P1V05S0_SENSE_N

<SCH_NUM>

76 OF 119

62 OF 97

10 14 15 17 18 41 62 67 84 86

45 62 96

10 14 15 17 18 41

62 67 84

86

45 62 96

44 58 59 60 84

18 19 36 49 58 59 63 66 67 73 79 80 84 85 86

96

SW

VDDD

VDDA

GD

SW

VSENSE_N

SD

GND_SW2

GNDD

GNDA

THRM

FB

SENSE_OUT

PWM_KEYB

SCL SDA

KEYB2

KEYB1

FB2

SW2

GND_SW

ISET_KEYB

EN

VSENSE_P

PAD

IN

OUT

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BKLT:PROD - Stuffs 0 ohm series R for production

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds

152S1701

371S0572

- =PPVIN_S0_LCDBKLT (9-12.6V LCD Backlight Input)

- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)

(IPU)

Power aliases required by this page:

- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)

BOM options provided by this page:

C7720, C7721 SHOULD BE PLACED MIRRORED C7723, C7724 SHOULD BE PLACED MIRRORED

Page Notes

152S1527

353S4159

(PPBUS_S0_BKLT_PWR_F)

(PPBUS_S0_BKLT_PWR_R)

(IPU)

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

10

9

5

18

25

2 1

6

19

16

11

15

12

14

13

20

3

22

24

23

7

4

8

21

17

U7701

CRITICAL

LP8548B1SQ_-03

QFN

21

F7700

0603

3AMP-32V

CRITICAL

21

L7710

CRITICAL

22UH-20%-2.4A-0.105OHM

DEM8030C-SM

21

L7720

CRITICAL

10UH-20%-1.4A-0.17OHM

PST041H-CDH46D14-SM

2

1

R7701

1/20W MF

1%

201

80.6K

2

1

C7700

0201

1000PF

10% 16V X7R-1

2

1

R7702

63.4K

1%

402

MF-LF

1/16W

4

3

6 5 2 1

Q7706

SSOT6-HF

FDC638APZ_SBMS001

CRITICAL

2

1

C7722

16V

10%

0201

X5R-CERM

0.1UF

2

1

C7721

25V X5R-CERM

10%

603

2.2UF

2

1

C7725

50V

10%

0402

X7R-CERM

0.001UF

21

R7747

1/20W

5% MF

0

0201

2

1

C7747

NO STUFF

25V

5% 0201

NPO-C0G

33PF

21

R7742

1/20W

5%

0201

MF

0

2

1

C7740

10V

10%

402-2

X5R

1UF

2

1

C7741

10V

10% 402-2

X5R

1UF

2

1

R7740

5%

201

MF

1/20W

1M

21

R7723

1/16W

0.1%

402

TF

10.2

BKLT:ENG

21

XW7700

SM

2

1

C7712

25V

10% 402

X5R

0.1UF

82 86

40

2

1

C7701

10% 50V

0.001UF

NOSTUFF

CERM 402

2

1

C7710

X6S-CERM

4.7UF

10% 25V

0603

2

1

C7711

4.7UF

25V

10% 0603

X6S-CERM

2

1

R7741

1/20W

1%

201

MF

31.6K

KA

D7720

SOD-123

CRITICAL

RB160M-60G

2

1

C7723

50V

10%

0805

X7R

1.0UF

2

1

C7724

50V

10%

0805

X7R

1.0UF

2

1

C7720

X5R-CERM

25V

10%

603

2.2UF

2

1

C7742

25V

5%

0201

NPO-C0G

33PF

NO STUFF

2

1

XW7720

SM

PLACE_NEAR=D7720.K:2MM

96

21

R7724

1/16W

0.1%

402

TF

BKLT:ENG

10.2

2

1

R7709

1/16W

1%

402

MF-LF

150K

2

1

R7708

1/16W

1%

18.2K

402

MF-LF

KA

D7701

PLACE_NEAR=L7710.2:3MM

CRITICAL

POWERDI-123

DFLS2100

321

4

5

Q7701

SI7812DN

PWRPK-1212-8

PLACE_NEAR=L7710.2:3MM

CRITICAL

2

1

R7703

1/16W

5%

402

MF-LF

0

21

R7758

1/20W

5%

0201

MF

0

2

1

R7761

MF

5% 1/20W

1.8K

201

2

1

R7760

MF

5%

1.8K

1/20W

201

21

R7780

1/20W

5%

0201

MF

0

82

21

R7783

1/16W

5%

402

MF-LF

0

2

1

R7744

1/16W

5%

402

MF-LF

0

2

1

R7743

MF-LF

1/16W

5%

402

0

2

1

C7726

50V

10% 0805

X7R

1.0UF

2

1

C7727

50V

10% X7R

1.0UF

0805

69 85 86

69 86

21

R7757

1/20W

5%

0201

MF

0

69 85 86

2

1

C7717

0603

X7R-CERM

10%

1000PF

100V

PLACE_NEAR=D7701.K:5MM

2

1

C7715

2.2UF

X7R

100V

10%

1210-1

PLACE_NEAR=D7701.K:3MM

CRITICAL

2

1

C7716

X7R

10%

1210-1

100V

CRITICAL

2.2UF

PLACE_NEAR=D7701.K:5MM

2

1

C7718

100V

10%

1210-1

X7R

2.2UF

PLACE_NEAR=D7701.K:3MM

CRITICAL

2

1

C7719

100V

10% X7R

PLACE_NEAR=D7701.K:5MM

CRITICAL

1210-1

2.2UF

43

21

R7700

1W

1%

0.025

MF

CRITICAL

0612-1

2

1

C7730

100V 0402

CERM

12PF

2%

2

1

C7731

100V 0402

CERM

12PF

2%

2

1

C7728

CERM 0402

100V

2%

12PF

2

1

C7729

2%

12PF

0402

CERM

100V

SYNC_DATE=10/30/2014

LCD/KBD Backlight Driver

SYNC_MASTER=CLEAN_X425

116S0004

R7723,R7724

BKLT:PROD

2

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=55V

MIN_NECK_WIDTH=0.25 mm

BKL_SW

DIDT=TRUE

MIN_LINE_WIDTH=2 mm

BKL_FB

BKL_FET_CNTL

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM

PPBUS_SW_LCDBKLT_PWR

VOLTAGE=12.6V

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_FUSED

LCDBKLT_EN_L

KBDBKLT_RETURN2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

BKLT_PWM_KEYB

GND_BKLT_SGND

BKLT_SD

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

PP5V_S0_BKLT_VDDD

GND_BKLT_SGND

PP5V_S0_BKLT_VDDA

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

PP5V_S0

BKLT_EN_R

BKLT_SDA

I2C_BKLT_SDA

LCD_BKLT_PWM_R

LCD_BKLT_PWM

PP5V_S0_KBDLED_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0

SMC_SYS_KBDLED

BKLT_KEYB1

PPBUS_G3H

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

BKL_FET_CNTL_R

PP5V_S0

GND_BKLT_SGND

BKLT_SENSE_OUT

LCD_BKLT_EN

PPBUS_SW_BKL

VOLTAGE=12.6V

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM

I2C_BKLT_SCL

ISNS_LCDBKLT_P

BKLT_KEYB2

PPBUS_S0_LCDBKLT_PWR_SW

MIN_NECK_WIDTH=0.25 MM VOLTAGE=45V

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=2 MM

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM

PPVOUT_BKLT_FB2

VOLTAGE=40V

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

BKLT_SCL

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

KBDBKLT_SW

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

KBDBKLT_RETURN1

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=40V

PPVOUT_S0_KBDBKLT

BKLT_ISET_KEYB

ISNS_LCDBKLT_N

<SCH_NUM>

77 OF 119

63 OF 97

69 86

39 86

63

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

30 44 47 56 57 65 84 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

63

84

63

39 86

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Ra>

Freq = 1.6MHZ

Max Current = 1.5A

C7872, C7873 FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

Vout = 1.508V

1.5V S0 Regulator

1.05V SUS LDO

Max Current = 0.35A

Vout = 1.05V

<Rb>

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

dividers (200/100) to 3.3V SUS, which burns 100mW in all S-states.

70mA is required to support pull-ups. Alternative is strong voltage

Lynx Point-H requires JTAG pull-ups to be powered at 1.05V in SUS.

Vout = 0.8V * (1 + Ra / Rb)

66 67

1

6

9

4 5

3

8

7

2

U7810

DFN

ISL8009B

CRITICAL

2

1

C7850

CRITICAL

6.3V CERM-X6S 0402

10UF

20%

21

L7870

CRITICAL

2.2UH-3A

PCMB042T-IHLP1616BZ

2

1

R7881

113K

1/16W

1%

402

MF-LF

2

1

C7876

50V

CERM

5%

27PF

0402-1

2

1

R7880

100K

1/16W

1%

402

MF-LF

2

1

C7871

0805-1

6.3V

CRITICAL

47UF

X5R-CERM

20%

67

2

1

C7841

6.3V

10%

402

X5R

2.2UF

XDP_PCH

7

1

2

6

5

3

4

U7840

CRITICAL

XDP_PCH

SON

TPS720105

2

1

C7840

6.3V

10%

402

CERM

1UF

XDP_PCH

2

1

C7851

CRITICAL

6.3V CERM-X6S 0402

10UF

20%

2

1

C7872

0201

12PF

5% NP0-C0G

25V

CRITICAL

2

1

C7873

CRITICAL

12PF

NP0-C0G 25V

5% 0201

SYNC_MASTER=CLEAN_X305

Misc Power Supplies

SYNC_DATE=01/15/2014

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

P1V5S0_SW

PP3V3_S5

PP3V3_SUS

PP1V05_SUS

P3V3S0_P1V5_S0_EN P1V5S0_PGOOD

P1V5S0_FB

PP1V5_S0

<SCH_NUM>

78 OF 119

64 OF 97

12 14 15 17 18 19 21 31 32 33 61 66 67 82 84 85 86 96

11 12 13 14 15 17 50 66 67 84

18 84

11 12 13 15 17 19 52 67 81 84 86

IN

BI

SYM_VER_2

G S

D

S

G

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RC Value not Final

X

0 V

Hi-Z

X

PBUS ONLY CONTROL INPUTS

SYSTEM STATE

G3H, S5

S4, S3, S0

0 V

PBUS

X

0 V

Hi-Z

TPAD_ACTUATOR_THRMTRIP_L

SMC_ACTUATOR_DISABLE_L

0 V

T101 POWER

(Open-Drain)

2 1

R7970

402

5%

MF-LF

1/16W

33K

2

1

C7971

10%

0.033UF

402

X5R

16V

2

1

C7970

0.01UF

0402

10% 16V

X7R-CERM

2

1

C7979

CRITICAL

16V X6S-CERM 0603

NOSTUFF

20%

10UF

38 86

40

2

1

3

Q7972

DFN1006H4-3

DMN32D2LFB4

CRITICAL

2

1

R7972

47K

5%

402

1/16W MF-LF

321

4

5

Q7979

PWRPK-1212-8

SI7121DN

CRITICAL

2

1

R7976

100K

5%

201

1/20W MF

2

1

R7926

402

MF-LF

1/16W

5%

0

2

1

R7922

5%

MF-LF

0

402

1/16W

X249 POWER SUPPLY

SYNC_DATE=07/02/2014

SYNC_MASTER=CLEAN_MAXWELL

SMC_ACTUATOR_DISABLE_L

PPBUS_S4_TPAD

PVIN_S4_TPAD_EN_L

PPBUS_G3H

PVIN_S4_TPAD_SS

TPAD_ACTUATOR_THRMTRIP_L

PVIN_S4_TPAD_EN

PP3V3_S4

<SCH_NUM>

79 OF 119

65 OF 97

45 84

30 44 47 56 57 63 84 86

20 33 38 41 42 45 46 66 67 81 84 85

86

IN

D

S

G

IN

D

S

G

D

S

G

IN

S

G

D

OUT

D

S

G

IN

GND

VDD

D

SON

CAP

S

G

D

GND

VOUT

ON

VIN

IN

SYM_VER_2

G S

D

SYM_VER_2

G S

D

VER 1

S

D

G

VER 1

S

D

G

VER 1

S

D

G

VER 1

S

D

G

VIN

ON

GND

VOUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LOADING

3.3V S3 FET

FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

MOSFET

3.3V S3 FET

26 mOhm @1.8V

P-TYPE 8V/5V

LOADING

1.1 A (EDP)

RDS(ON)

CHANNEL

SiA427

1.35V S3/S0 FET

0.8V/ms = 19.75nF

Slew rate :

1.3 A (EDP)

2.8 A (EDP)

0.3 A (EDP)

26 mOhm @1.8V

P-TYPE 8V/5V

SiA427

EDP is per J45 Power Budget rev5

3.3V S4 FET

CHANNEL

LOADING

MOSFET

5 A (EDP)

SI7615DN

5.0V S0 FET

3.3V S0 SSD FET

LOADING

5.5 mOhm @4.5V

5.5 MOHM @4.5V

P-TYPE 20V/12V

P-TYPE 8V/5V

SiA427

MOSFET

Type R(on)

Part

TPS22924C

U8030

25.8 mOhm Max

18.5 mOhm Typ

Load Switch

LOADING

RDS(ON)

CHANNEL

SI7615DN

RDS(ON)

26 mOhm @1.8V

P-TYPE 8V/5V

CHANNEL

SiA427MOSFET

4.8 A (EDP)

9.6 mOhm

N-TYPE

LOADING

26 mOhm @1.8V

RDS(ON)

CHANNEL

RDS(ON)

3.3V SUS FET

1.35V S3/S0 FET

5V S3 FET

3.3V SUS FET

3.3V S4 FET

CHANNEL

5.0V S0 FET

RDS(ON)

MOSFET

P-TYPE 20V/12V

3.3V S0 SSD FET

MOSFET

LOADING

RDS(ON)

376S0945

0.5 A (EDP)

APN 353S2741

Integ. MOSFET

GPU_3.3V S0 Switch

3.3V S0 Switch

@ 2.5V

Max Current = 0.11A

APN 353S3979

5V S3 FET

Max Current = 2A

66 mOhm Typ 90 mOhm Max

Load Switch

U8090

TPS22904

0.5A Max

Current

R(on) @ 3.6V

Part

Type

SLG5AP1438V

C8030 USING 0603 PAKAGE IS FOR DFM TO PROTECT U8030 (CSP)

21

C8010

0.01UF

0402

X7R-CERM

16V

10%

2

1

C8011

10%

16V

402

X5R

0.033UF

21

R8010

MF-LF

1/16W

39K

5%

402

2

1

R8012

402

MF-LF

1/16W

47K

5%

67

74

3

1

Q8010

CRITICAL

SIA413DJ

SC70-6L

2

1

C8001

0.1UF

402

CERM

10V

20%

31 32 67

2

1

R8002

220K

MF-LF

1/16W

402

5%

2

1

R8000

402

1/16W

47K

5%

MF-LF

2

1

C8009

0.033UF

402

X5R

16V

10%

74

3

1

Q8000

SC70-6L

CRITICAL

SIA413DJ

21

C8000

0402

0.01UF

X7R-CERM

16V

10%

2

1

C8021

0.033UF

X5R

16V

402

10%

74

3

1

Q8020

SC70-6L

CRITICAL

SIA413DJ

21

C8020

X7R-CERM

16V

0.01UF

10%

0402

2

1

R8022

1/16W

100K

MF-LF

402

5%

21

R8020

12K

402

MF-LF

1/16W

5%

12 44 67

67

2

1

R8062

402

MF-LF

1/16W

270K

5%

21

R8060

MF-LF

1/16W

6.2K

5%

402

2

1

C8061

CERM-X5R

10.0V

10%

402

0.12UF

21

C8060

X5R

10% 10V

0402

0.47UF

321

4

5

Q8060

SI7615DN

PWRPK-1212-8

CRITICAL

2

1

C8002

0.018UF

10%

402

X7R

16V

46 96

74

3

1

Q8050

CRITICAL

SIA427DJ

SC70-6L

2

1

C8051

10%

402

X5R

16V

0.033UF

21

R8050

402

1/16W

5%

5.1K

MF-LF

2

1

R8052

402

MF-LF

1/16W

200K

5%

21

C8050

0.01UF

0402

X7R-CERM

16V

10%

67

1

52

8

37

U8001

SLG5AP1438V

TDFN

CRITICAL

21

C8070

10% 16V

0402

0.01UF

X7R-CERM

321

4

5

Q8070

PWRPK-1212-8

SI7615DN

PLACE_NEAR=R5549.2:6mm

CRITICAL

2

1

C8071

0.033UF

16V

402

X5R

10%

21

R8070

1/16W

402

33K

MF-LF

5%

2

1

R8072

402

MF-LF

1/16W

47K

5%

B1

A1

B2

A2

C2

C1

U8030

CSP

CRITICAL

TPS22924

2

1

C8030

603

16V

1UF

X5R

10%

64 67

2

1

3

Q8012

DFN1006H4-3

DMN32D2LFB4

2

1

3

Q8072

DMN32D2LFB4

DFN1006H4-3

21

R8073

SSD_PWR_EN:GPIO

1/20W

0201

0

5% MF

21

R8074

SSD_PWR_EN:S0

1/20W

0201

0

5% MF

1

2

6

Q8052

DMN5L06VK-7

SOT563

4

5

3

Q8052

SOT563

DMN5L06VK-7

4

5

3

Q8002

SOT563

DMN5L06VK-7

1

2

6

Q8002

DMN5L06VK-7

SOT563

43

21

R8005

SENSOR_NONPROD_R

CYN

1W

0612

0.002

1%

A2

A1

B1

B2

U8090

TPS22904

CRITICAL

CSP

2

1

C8090

10%

402

X5R

1UF

6.3V

68

2

1

C8091

10% X5R

402

16V

0.1UF

NOSTUFF

2

1

C8012

CRITICAL

12PF

25V

NP0-C0G

5% 0201

Power FETs

SYNC_MASTER=J45_IG

SYNC_DATE=07/01/2014

P3V3S0_P1V5_S0_EN

PP5V_S4

P5VS0_EN

PP3V3_S5

PP3V3_S0

P3V3S4_EN_L

PP3V3_S0GPU

P3V3_S0GPU_EN

PP3V3_S5

PP5V_S0

P3V3_SSD_SS

P3V3_SSD_EN_L

P3V3S3_SS

P5V0S0_SS

PP5V_S3

PP3V3_S4

P1V35CPU_SLEW_CTL

PP3V3_SUS

P3V3SUS_SS

PP5V_S4

P3V3S3_EN

PP3V3_S5

PP3V3_S0SW_SSD_R

SSD_PWR_EN

P5VS3_SS

CPUVDDQ_EN

P5VS3_EN

P5V0S0_EN_L

P3V3SUS_EN_L

PM_SLP_SUS_L

S4_PWR_EN

ISNS_CPUDDR_N

PP1V35_S3RS0_FET

PP1V35_S3RS0_CPUDDR

PP1V35_S3

PP5V_S5

P5VS3_EN_L

PM_SLP_S3_BUF_L

PP3V3_S5

P3V3S3_S4

PP3V3_S5

SSD_PWR_FET_EN

P3V3S3_EN_L

PP3V3_S3

ISNS_CPUDDR_P

<SCH_NUM>

80 OF 119

66 OF 97

37 38 51 61 66 67 69 81 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

67 68 69 82 83 84 86 96

47 68 71 72 76 77 79 80 84

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85

86 96

12 14 15 17 18 19 21 31 32 33 61 64

66 67 82 84 85 86

96

18 19 36 49 58 59 62 63 67 73 79 80 84 85 86

21 36 60 67 84 86

20 33 38 41 42 45 46 65 67 81 84 85 86

11 12 13 14 15 17 50 64 67 84

37 38 51 61 66 67 69 81 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

45 84

13 18

84

6 8

10 21 67 84 96

21 45 60 84

86

61 84 86

51 67 81 82 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

34

13 20 21 43 45 46 81 82 84 86

OUT

IN

OUT

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

OUT

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

IN

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

IN

NC

OUT

IN

OUT

SYM_VER_2

G S

D

SYM_VER_2

G S

D

OUT

G

D

S

OUT

IN

OUT

VER 1

S

D

G

VER 1

S

D

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

S3 ENABLE

Min delay time

keep R8171 DDRCPU 1.35V only

V2MON: 2.815V-3.099V

Vbe 0.7V max @2mA

(ISL Version in development)

P1V5S0_PGOOD from U7810

1V05_VMON divider

0.716V @1.02V

S0 Rail PGOOD Circuitry

P5V_VMON divider

353S2310

(IPU)

0.717V @1.31V

3.16V @4.5V

Q1 Vth 0.7~1V @Id 250uA

V4MON: 0.572V-0.630V

V3MON: 0.572V-0.630V

Thresholds: VDD: 2.734V-3.010V

(For development only)

Deep Sleep (dS4AC)

0

S0 ENABLE

3V3 Divider:1.07V

CHGR VFRQ Generation

Vce(sat) 0.1V max @1mA

1V5 S0 "PGOOD" Delay

S5 Rail Enables & PGOOD

Power State Debug LEDs

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

VBEon: 0.58~0.7V

1V5 Divider:0.75~0.85V

Vgs:0.7V~1.0V

Unused PGOOD signals

SMC-->PM_DSW_PWRGD

S5_PWRGD-->SMC

PM_RSMRST_L goes to U1100.C21

Battery Off (G3HotAC)

SMC_ADAPTER_EN

State

0

1

Mobile System Power State Table

0 00

0

1

0

353S2809

(PM_SLP_S3_BUF_L)

5.0V Divider:1.07V

1V35_VMON divider

Deep Sleep (dS5AC)

0

PM_SLP_S3_L

0

1

0

PM_SLP_S4_LPM_SLP_S5_L

1

11

1

PM_SLP_SUS_L

1

SMC_S4_WAKESRC_EN

1 0 0

0

00

0

0 0

0

1

10

X

SMC_PM_G2_ENABLE

Sleep (S3)

Sleep (S3AC)

Run (S0)

1 1

1

0 1

10

0

1

toggle 3Hz

Deep Sleep (dS4)

Deep Sleep (dS5)

Battery Off (G3Hot)

PM_SLP_S4_L:100K pull down in PCH page

threhold is 3.07V

0

U8130 Sense input

No stuff C8131, 12ms

S0 Rail PGOOD (BJT Version)

PM_SLP_S3_L:100K pull down in PCH page

PM_SLP_S5_L:100K pull down on PCH page

S4 Power Enable

CPUVCORE ENABLE

PM_SLP_SUS_L: 100K pull down on PCH page

3.3V SUS Detect

3.3V SUS Enable

NOTE: S4 term is guaranteed by S4 pull-up on open-drain AP_PWR_EN signal.

"WLAN" = ("S4" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

60 67

66 67

2

1

R8112

0

MF-LF

5%

402

1/16W

PLACE_NEAR=Q8012.1:6mm

2

1

C8112

NO STUFF

10% CERM-X5R

402

6.3V

PLACE_NEAR=Q8012.1:6mm

0.47UF

18 19 40 58 67 86

31 32 44 67

62 67

2

1

R8111

5%

402

1/16W MF-LF

5.1K

PLACE_NEAR=U7400.16:6mm

2

1

C8110

0.47UF

CERM-X5R 402

10%

6.3V

PLACE_NEAR=U7400.16:6mm

12 21 33 37 40 67 81 86

2

1

R8185

PLACE_NEAR=U7600.3:6mm

5% 1/16W MF-LF 402

130K

2

1

C8185

402

6.3V

10%

0.82UF

X5R

PLACE_NEAR=U7600.3:6mm

2

1

R8131

1/16W MF-LF 402

5%

100K

57

12 21 40 86

31 32 66 67

2

1

R8167

10K

5% 1/16W MF-LF

402

18 19 40 58 67 86

2

1

R8157

5%

1/16W

402

MF-LF

100

21

R8169

100

402

5%

MF-LF

1/16W

2

1

R8165

5% MF-LF

402

1/16W

470K

61

21

R8162

330

402

5%

S0PGOOD_ISL

MF-LF

1/16W

62

2

1

R8156

150K

1/16W MF-LF

402

1%

21

R8153

5%

MF-LF

1/16W

1K

402

2

1

R8151

1% 1/16W MF-LF

402

54.9K

2

1

R8152

15.0K

402

1%

MF-LF

1/16W

3

2

8

4

6

1

7

5

Q8150

ASMCC0179

CRITICAL

DFN2015H4-8

21

R8154

1K

MF-LF

1/16W

5%

402

21

R8155

5%

1K

402

MF-LF

1/16W

31 32 66 67

12 40

6

5 1

3

2

4

U8130

TPS3808G33DBVRG4

CRITICAL

SOT23-6

2

1

C8131

0.001UF

20%

402

50V CERM

NO STUFF

2

1

R8133

5%

402

1/16W MF-LF

100K

2

1

C8130

20%

CERM

402

10V

0.1uF

BYPASS=U8130.6::2.3mm

21

R8168

MF-LF

5%

100

402

1/16W

64

21

R8178

MF-LF

5%

402

100

1/16W

64 66 67

12 86 91

40 41 61 67

2

1

C8142

0.0033UF

10% 50V X7R-CERM

PLACE_NEAR=U7501.21:7mm

NO STUFF

0402

21

R8140

402

MF-LF

1/16W

5%

PLACE_NEAR=U7501.21:7mm

100

61 67

40 61

67

2

1

R8141

MF-LF

5%

402

100K

1/16W

PLACE_NEAR=U7501.20:7mm

7

2

6

5

3

9

8

1

4

U8160

S0PGOOD_ISL

TDFN

ISL88042IRTEZ

CRITICAL

2

1

R8172

1/16W

402

6.04K

S0PGOOD_ISL

MF-LF

1%

2

1

R8173

1/16W

S0PGOOD_ISL

MF-LF

1%

402

15.0K

2

1

R8170

S0PGOOD_ISL

10K

1%

MF-LF

402

1/16W

2

1

R8171

S0PGOOD_ISL

12.4K

1%

1/16W

402

MF-LF

2

1

R8160

1%

S0PGOOD_ISL

1/16W MF-LF

402

6.04K

2

1

R8161

1/16W

MF-LF

1%

402

15.0K

S0PGOOD_ISL

12 44 66 67 12 44 66 67

31 32 66 67

2

1

C8113

402

CERM-X5R

10%

6.3V

0.47UF

PLACE_NEAR=Q8052.2:6MM

NO STUFF

2

1

R8113

402

MF-LF

5%

PLACE_NEAR=Q8052.2:6MM

1/16W

0

66 67

31 32 44 67

40 41

4

6

5 3

1

2

U8170

SOT891

74LVC1G32

2

1

C8170

BYPASS=U8170.6:3:2.3mm

0.1uF

20% 10V

CERM

402

2

1

C8114

NO STUFF

0.47UF

10%

6.3V CERM-X5R 402

PLACE_NEAR=J4801.22:10MM

2

1

R8114

1/20W MF

3.3K

201

5%

PLACE_NEAR=J4801.22:10MM

38 86

2

1

C8160

PLACE_NEAR=U8160.2:4mm

0402

10V

20%

X7R-CERM

S0PGOOD_ISL

0.1UF

K

A

D8190

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

DBGLED

SILK_PART=S5_ON

K

A

D8191

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM SILK_PART=S4_ON

DBGLED

LTQH9G-SM

K

A

D8193

SILK_PART=S0_ON

PLACE_SIDE=BOTTOM

DBGLED

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

A

D8192

DBGLED

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V LTQH9G-SM

2

1

R8190

DBGLED

20K

5%

201

1/20W MF

2

1

R8191

20K

1/20W MF 201

5%

DBGLED

2

1

R8192

20K

5% 1/20W

201

DBGLED

MF

2

1

R8193

20K

DBGLED

1/20W 201

MF

5%

2 1

R8194

PLACE_SIDE=BOTTOM

MF-LF

0

5%

402

1/16W

DBGLED

2

1

R8120

470K

201

5% 1/20W MF

60

2

1

R8158

1%

15.0K

402

1/16W MF-LF

2

1

R8159

7.15K

402

1%

1/16W MF-LF

2

1

R8186

5%

20K

1/16W MF-LF 402

64 66 67

2

1

C8186

CERM

10%

6.3V 402

0.68UF

2

1

C8187

CERM

10%

6.3V 402

PLACE_NEAR=Q8052.5:6mm

0.68UF

NO STUFF

2

1

R8187

0

402

5% MF-LF

1/16W

PLACE_NEAR=Q8052.5:6mm

66 67

2

1

C8174

X5R 402

6.3V

10%

2.2UF

PLACE_NEAR=U7501.4:6mm

2

1

R8174

402

1/16W MF-LF

43K

5%

PLACE_NEAR=U7501.4:6mm

61 67

2

1

3

Q8131

DFN1006H4-3

DMN32D2LFB4

2

1

3

Q8191

DMN32D2LFB4

DFN1006H4-3

DBGLED

21

R8175

MF-LF

5%

1/16W

240

402

21

R8138

820

402

MF-LF

1/16W

5%

PLACE_NEAR=R8185.2:6mm

5

4

1

2

3

U8180

SC70-HF

MC74VHC1G08

12 44 66 67

40 41

61

67

2

1

R8180

100K

NO STUFF

402

MF-LF

1/16W

5%

K

A

D8185

SOD-523

BAT54XV2T1

PLACE_NEAR=R8138.1:6mm

K

A

D8174

PLACE_NEAR=R8174.1:6mm

SOD-523

BAT54XV2T1

2

1

C8180

20% 10V

CERM

402

0.1uF

BYPASS=U8180.5:3:2.3mm

18 19 40 58 67 86

1

2

6

Q8151

DMB53D0UV

SOT-563

CRITICAL

2

1

R8136

MF-LF

1/16W

402

23.7K

1%

4

3

5

Q8151

SOT-563

DMB53D0UV

CRITICAL

2

1

C8134

X5R 402

6.3V

2.2UF

10%

2

1

R8135

1/16W

402

1%

MF-LF

54.9K

2

1

R8134

MF-LF

1%

1/16W

61.9K

402

21

R8137

1/16W

5%

402

MF-LF

100

2

1

R8139

402

MF-LF

1/16W

2.0K

1%

33 40 67

2

1

R8125

MF

1/20W 201

330K

5%

33 40 67

51 66 67 81 82 86

2

1

C8161

PLACE_NEAR=U8160.2:4mm

10V

0402

S0PGOOD_ISL

0.1UF

20%

X7R-CERM

21

R8195

PLACE_NEAR=U8160.2:4mm

402

1/16W

5%

10

MF-LF

S0PGOOD_ISL

21

R8196

1/16W

5%

402

MF-LF

10

S0PGOOD_ISL

PLACE_NEAR=U8160.7:4mm

2

1

C8162

PLACE_NEAR=U8160.2:7mm

0.1UF

10V

0402

NOSTUFF

20%

X7R-CERM

2

1

C8163

PLACE_NEAR=U8160.2:7mm

20%

X7R-CERM

0402

10V

NOSTUFF

0.1UF

2

1

R8197

PLACE_NEAR=U8160.7:4mm

5%

100K

402

1/16W MF-LF

NOSTUFF

1

2

6

Q8190

DBGLED

SOT563

DMN5L06VK-7

4

5

3

Q8190

SOT563

DMN5L06VK-7

DBGLED

SYNC_MASTER=J45_IG

SYNC_DATE=07/01/2014

Power Control 1/ENABLE

PP3V3_S5

PP1V5_S0

PP3V3_S5

PP3V3_S0_VMON_P7

PM_SLP_S3_BUF_L

P5VS0_EN

PM_SLP_SUS_L

PM_SLP_S3_L

P5VS4_EN_D

PP3V3_S5

P5VS4_EN

MAKE_BASE=TRUE

P3V3S0_P1V5_S0_EN

MAKE_BASE=TRUE

P1V05S0_EN

PM_SLP_S3_R_L

PP3V3_S5

P3V3S0_P1V5_S0_EN

P1V05S0_EN

SMC_S4_WAKESRC_EN

PM_SLP_SUS_L

P3V3S0_P1V5_S0_EN

P5VS3_EN

DDRREG_EN

VMON_5V_DIV

PP5V_S0

PP3V3_SUS

DBGLED_S0

PP3V3_SUS

P1V05_EN_D

S4_PWR_EN S4_PWR_EN

VMON_Q4_BASE

PM_SLP_S5_L

P3V3S3_EN

DBGLED_S3

S4_PWR_EN

ALL_SYS_PWRGD

PP3V42_G3H

S5_PWRGD

PP3V3_S0

PP1V35_S3RS0_CPUDDR

VMON_3V3_DIV

CHGR_VFRQ

PP5V_S4

PP5V_S3

DDRREG_PGOOD

P5VS4_PGOOD

TP_SUS_PGOOD_MR_L

SMC_PM_G2_EN

P3V3S5_EN

SUS_PGOOD_CT

TPAD_VBUS_EN

PM_SLP_S3_R_L

ALL_SYS_PWRGD

PP3V42_G3H

DELAY_1V5S0_PGD

PM_P1V5_PGD_DIV

PM_1V5_PGD_L_R

PM_1V5_PGD_L

DBGLED_S0_D

PM_SLP_S3_R_L

MAKE_BASE=TRUE

PM_SLP_S3_R_L

MAKE_BASE=TRUE

P3V3S5_EN

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

MAKE_BASE=TRUE

S5_PWRGD

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

P5VS0_EN

MAKE_BASE=TRUE

VMON_Q2_BASE

S0PGD_C

ALL_SYS_PWRGD

PP3V3_S5

PM_WLAN_EN

MAKE_BASE=TRUE

PP3V3_S4

PM_WLAN_EN

MAKE_BASE=TRUE

DDRREG_EN

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

P5VS4_EN

MAKE_BASE=TRUE

S4_PWR_EN

P1V5S0_PGOOD

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 MM

P1V05_VID_VMON

ALL_SYS_PWRGD

PP3V3_S0 PP3V3_S0

PP1V05_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_VMON_P7

MIN_LINE_WIDTH=0.5 MM

ALL_SYS_PWRGD_R

PP1V35_S3RS0_CPUDDR

VMON_MR

S0PGD_BJT_GND_R

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S0_VMON_P2

MIN_NECK_WIDTH=0.2 MM

P1V05S0_PGOOD

VMON_MR

P1V5_DIV_VMON

PP5V_S0

DBGLED_S5

P5V_DIV_VMON

VMON_Q3_BASE

DBGLED_S4

PM_SLP_S3_BUF_L

PP3V3_S5

S4_PWR_EN

DBGLED_S3_D

PM_SLP_S4_L

DBGLED_S4_D

PM_RSMRST_L

PM_SLP_S4_L

<SCH_NUM>

81 OF 119

67 OF 97

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 15 17 19 52 64

81 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

51 66 67 81 82 86

12 14 15 17 18 19 21 31 32 33 61 64 66

67 82 84 85 86 96

64 66 67

62 67

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

11 12 13 14 15 17 50 64 66 67 84

19 34 37 38 40 41 42 43 50 56 57 67 84 86

40 61 67

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83

84 86 96

6 8

10 21 66

67 84

96

37 38 51 61 66 69 81 84 86

21 36 60 66 84 86

31 32 44 67

19 34 37 38 40 41 42 43 50 56 57 67 84 86

61 67

18 19 40 58 67 86

66 67

18 19 40 58 67 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

20 33 38 41 42 45 46 65 66 81 84 85 86

60 67

66 67

61 67

11 12

13

14

15

17

19

20

29

34

43

44

45

46

47

48

49

51

52

55

66

67

68

69

82

83

84

86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46

47 48 49

51 52 55 66

67 68 69 82

83 84 86 96

10 14 15 17 18 41 62 84 86

67

6 8

10 21 66 67 84

96

67

18 19 36 49

58 59

62

63

66

67

73

79

80

84

85

86

51 66 67 81 82 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

31 32 66 67

12 21 33 37 40 67 81 86

OUT

IN

OUT

IN

OUT

IN

OUT

G

SYM_VER_1

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCIE TEST STRUCTURES (FOR LAB USE)

4) VDDCI

5. VDDCI GPU_PGOOD4

(For development only)

Power State Debug LEDs

Pending Layout. Can add more.

5) FB VRAM MVDD

3) GPUVCore

1) GPU_3.3V

PGOOD ON SEQUENCE

1. GPU 3V3 GPU_PGOOD1

3. 1V8_GPU GPU_PGOOD2

6. FB MVDD GPU_PGOOD5

up in the following order:

GPU Rails Power UP Sequencing

2) GPU_0V95 (BIF_VDDC) & GPU_1V8 (VDD_CT)

Venus GPU requires rails to come

2. 0.95_S0GPU GPU_PGOOD6_2

EXT GPU PWRGD Pullup

4. GPUVCORE GPU_PGOOD3

(GPU_PGOOD6_2 is up before 1V8GPU_PGOOD after 3V3GPU_PGOOD)

68 80

66 68

68 73

68 79

68 73

68 80

2

1

C8231

0.47UF

CERM-X5R-1

NO STUFF

201

20% 4V

2

1

C8232

0.47UF

20%

201

4V CERM-X5R-1

NO STUFF

68 79 82

68 73 82

2

1

R8293

100K

5% MF

1/20W

201

2

1

R8292

MF

5%

100K

1/20W

201

2

1

R8291

MF

1/20W

5%

100K

201

2

1

R8290

1/20W

201

5% MF

100K

68 79 82

68 73

68 73 82

68 80 82

68 80 82 68 80 82

2

1

R8294

1/20W

100K

5%

201

MF

21

R8295

1/20W

0

MF

201

5%

68 82

21

R8234

0

PLACE_NEAR=U8090.B1:7mm

402

1/16W MF-LF

5%

21

R8235

0

5%

1/16W MF-LF

402

PLACE_NEAR=U9450.15:7mm

21

R8233

0

1/16W MF-LF

402

5%

PLACE_NEAR=U8700.15:7mm

21

R8236

0

402

5%

MF-LF1/16W

PLACE_NEAR=U9300.38:7mm

21

R8231

MF-LF

402

1/16W

0

5%

PLACE_NEAR=U8750.3:7mm

21

R8232

402

MF-LF1/16W

5%

0

PLACE_NEAR=U9400.13:7mm

2

1

R8220

NOSTUFF

1/20W MF

1%

49.9

201

PLACE_NEAR=C8420.1:3mm

21

C8220

20%

0.22UF

X5R

6.3V 201

NOSTUFF

GND_VOID=TRUE

PLACE_NEAR=C8420.1:3mm

2

1

R8221

NOSTUFF

PLACE_NEAR=C8421.1:3mm

1/20W MF

1%

49.9

201

21

C8221

0.22UF

PLACE_NEAR=C8421.1:3mm

GND_VOID=TRUE

NOSTUFF

201

6.3V X5R

20%

2

1

R8240

PLACE_NEAR=C8434.1:3mm

49.9

1/20W MF 201

NOSTUFF

1%

21

C8240

0.22UF

GND_VOID=TRUE

PLACE_NEAR=C8434.1:3mm

201

20% X5R

6.3V

NOSTUFF

2

1

R8241

PLACE_NEAR=C8435.1:3mm

NOSTUFF

1/20W MF

1%

49.9

201

21

C8241

NOSTUFF

201

PLACE_NEAR=C8435.1:3mm

20% X5R

6.3V

GND_VOID=TRUE

0.22UF

70 89

70 85 89

68 80 82

2

1

R8212

DBGLED

5% MF

20K

201

1/20W

K

A

D8211

SILK_PART=ALL_GPU_PGOOD

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

DBGLED

2

1

R8296

5% MF

1/20W

201

10K

68 82

2

1

3

Q8210

DFN1006H4-3

DMN32D2LFB4

DBGLED

SYNC_MASTER=MARY_X425G

SYNC_DATE=09/11/2014

Power Sequencing EG/PGOOD

GPUVCORE_PGOOD

P0V95_S0GPU_PGOOD PVDDCI_PGOOD

P3V3_S0GPU_PGOOD

P1V35R1V5FB_PGOOD

P1V8GPU_PGOOD

MAKE_BASE=TRUE

GPUVCORE_PGOOD

PP3V3_S0GPU

MAKE_BASE=TRUE

P3V3_S0GPU_PGOOD

P1V8GPU_PGOOD

MAKE_BASE=TRUE

EG_RAIL5_EN

EG_RAIL1_EN

MAKE_BASE=TRUE

P3V3_S0GPU_EN P3V3_S0GPU_EN

P0V95_S0GPU_EN

MAKE_BASE=TRUE

P0V95_S0GPU_EN

P1V35R1V5FB_EN

P1V8_S0GPU_EN

MAKE_BASE=TRUE

PVDDCI_GPU_EN

MAKE_BASE=TRUE

PVDDCI_GPU_EN

GPUVCORE_EN

MAKE_BASE=TRUE

GPUVCORE_ENEG_RAIL3_EN

PEG_D2R_C_P<0> GAP_PEG_D2R_P0

GAP_PEG_D2R_N0

PEG_R2D_C_N<0>

GAP_PEG_R2D_P0

EG_RAIL4_EN

MAKE_BASE=TRUE

P1V35R1V5FB_EN

P1V8_S0GPU_EN

DBG_RAIL_5

P1V35R1V5FB_PGOOD

PM_ALL_GPU_PGOOD

PEG_R2D_C_P<0>

GAP_PEG_R2D_N0

PEG_D2R_C_N<0>

MAKE_BASE=TRUE

P0V95R1V8GPU_R_EN

PVDDCI_PGOOD

MAKE_BASE=TRUE

P0V95_S0GPU_PGOOD

MAKE_BASE=TRUE

P1V35R1V5FB_PGOOD

PP3V3_S0

PM_ALL_GPU_PGOOD

DBG_RAIL5_D

<SCH_NUM>

82 OF 119

68 OF 97

68 73

47 66 71 72 76 77 79 80 84

68 82

82

66 68

68 73

68 80

68 79

82

68 73

68

82

68 82

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 69 82 83 84 86 96

68 82

IN

BI

NC

OUT

VIN

ON

GND

VOUT

IN

BI

IN

BI

IN

SYM_VER-1

GND

VDD

D

SON

CAP

IN

G

D

S

SYM_VER_2

G S

D

G

VER 5

SD

G

VER 5

SD

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

NC

08

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Type

3.3V_EDP ON/OFF CONTROL

Current

5V_eDP ON delay:9.4ms ~13.7ms

APN 376S0764

VBEon: 0.58~0.7V

66 mOhm Typ

delay time

680uF 2% APN 131S00033

APN 132S0332

Load Switch

5V_EDP_DIV min 0.5057V

U8330 Sense input threhold is 0.505V

C8331 (680pF) 2.7ms

U8300

R(on)

Type

Load Switch

Current

90 mOhm Max

GND_VOID

R(on)

Part

GND_VOID

LCD PANEL INTERFACE (eDP)

GND_VOID

Part

@ 3.6V

@100mA

0.5A Max

LCD Panel HPD & AUX strapping

APN 353S3999

Vgs:0.7V~1.0V

3V3_EDP_DIV min(V) 1.14

U8310

TPS22904(353S3979)

GND_VOID

518S0829

C8305 is placeholder for 3pF cap

GND_VOID

APN 353S3920

SLG5AP1443V

17 mOhm Typ 19 mOhm Max

2.5 A Max

3.3V TCON Switch

TCON 3V3 <30mA

TCON 5V 2A

5V TCON Switch

2

1

C8301

10% 16V

0.1UF

X7R-CERM

0402

21

L8300

CRITICAL

0805

FERR-220-OHM

2

1

C8302

0.001UF

0402

X7R-CERM

50V

10%

2

1

C8311

X7R-CERM

16V

10%

0.1UF

0402

2

1

C8312

0603

X6S-CERM

10UF

20% 10V

21

C8321

TRUE

16V

X5R-CERM 0201

10%

0.1UF

21

C8320

0201

16V

TRUE

X5R-CERM

10%

TRUE

0.1UF

82 97

21

C8323

16V

TRUE

10% X5R-CERM

0.1UF

0201

21

C8322

0.1UF

TRUE

16V

0201X5R-CERM

10%

TRUE

82 97

21

C8325

16V

TRUE

10% X5R-CERM

TRUE

0.1UF

0201

21

C8324

TRUE

16V

X5R-CERM

10%

0.1UF

TRUE

0201

82 97

21

C8327

X5R-CERM 0201

16V10%

0.1UF

TRUE

21

C8326

TRUE

10%

0.1UF

16V

X5R-CERM 0201

82 97

21

C8329

0.1UF

10% X5R-CERM 0201

16V

21

C8328

10% X5R-CERM

16V

0201

0.1UF

82 97

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8300

TRUE

F-RT-SM

20525-130E-01

CRITICAL

2

1

C8300

X7R

100V

10%

1000PF

0603

69 82 85 86

21

R8300

5%

1/20WMF0201

0

82

2

1

R8302

NOSTUFF

1/20W

5%

201

MF

1M

2

1

R8303

NOSTUFF

1/20W

5%

201

MF

1M

2

1

R8301

1/20W

5%

201

MF

1M

21

R8313

TRUE

5%

201

MF

1M

1/20W

21

R8314

TRUE

1/20W

5%

201

MF

1M

21

R8315

TRUE

1/20W

5%

201

MF

1M

21

R8316

TRUE

1/20W

5%

201

MF

1M

21

R8312

TRUE

5%

1/20W

MF

1M

201

21

R8317

1/20W

5%

201

MF

1M

TRUE

21

R8318

TRUE

5% MF

1M

1/20W

201

21

R8311

1M

TRUE

1/20W

5%

201

MF

46 96

2

1

C8350

0201

NP0-C0G

12PF

5%

25V

2

1

C8351

25V

0201

5% NP0-C0G

12PF

2

1

C8352

5%

12PF

25V

0201

NP0-C0G

2

1

C8353

0201

5%

25V

NP0-C0G

12PF

2

1

C8354

0201

12PF

5%

25V

NP0-C0G

2

1

C8355

0201 25V

5%

12PF

NP0-C0G

43

21

R8320

1%

0.025

MF

0612-1

1W

CRITICAL

SENSOR_NONPROD_R

2

1

C8308

20% X5R

1.0UF

6.3V

0201-1

2

1

C8304

0.1UF

6.3V

10% 0201

CERM-X5R

NOSTUFF

BYPASS=J8300.5::5MM

A2

A1

B1

B2

U8310

TPS22904

CSP

CRITICAL

2

1

R8380

201

MF

5%

1/20W

2.0K

2

1

R8381

2.0K

5%

201

MF

1/20W

36 40 43 48 76 85 86 95

2

1

C8309

0.1UF

10V

10% 0201

X5R-CERM

2

1

C8313

10V 201

X7R

10%

4700PF

63 85 86

63 86

2

1

R8350

NOSTUFF

5% MF

100K

201

1/20W

2

1

R8351

5%

201

100K

1/20W MF

4

32

1

FL8300

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

TRUETRUETRUETRUE

CRITICAL

4

32

1

FL8301

TRUETRUE

3.25-OHM-0.1A-2.4GHZ

TRUE

TAM0605-4SM

TRUE

CRITICAL

4

32

1

FL8302

TRUETRUETRUETRUE

TAM0605-4SM

CRITICAL

3.25-OHM-0.1A-2.4GHZ

4

32

1

FL8303

CRITICAL

TAM0605-4SM

TRUETRUETRUETRUE

3.25-OHM-0.1A-2.4GHZ

1

52

8

37

U8300

TDFN

CRITICAL

SLG5AP1443V

2

1

C8356

25V

5%

12PF

NP0-C0G 0201

2

1

C8357

5%

25V

12PF

0201

NP0-C0G

2

1

C8358

5%

12PF

NP0-C0G 25V

0201

2

1

C8303

PLACE_NEAR=J8300.28:2mm

0201

NP0-C0G

12PF

5%

25V

2

1

C8306

2% CERM

0402

12PF

100V

2

1

C8330

BYPASS=U8330.6::2.3mm

16V

20%

0201

X6S-CERM

0.1UF

2

1

R8333

NOSTUFF

201

1/20W

470K

MF

5%

2

1

C8331

25V

680PF

PLACE_NEAR=U8330.5:3.5mm

CRITICAL

10%

CERM 201

21

R8330

MF

201

0

1/20W

5%

69 82 86

2

1

R8331

201

MF

1%

680K

1/20W

PLACE_NEAR=U8330.3:2.5mm

2

1

R8332

88.7K

201

1% 1/20W MF

PLACE_NEAR=U8330.3:2.5mm

2

1

C8332

NOSTUFF

X7R-CERM 0201

16V

1000PF

10%

4

3

5

Q8300

SOT-563

DMB53D0UV

CRITICAL

2

1

R8339

MF

201

75K

1/20W

1%

2

1

R8334

1/20W

MF

201

5%

24K

2

1

R8335

510

1%

201

MF

1/20W

1

2

6

Q8300

CRITICAL

SOT-563

DMB53D0UV

2

1

C8334

0.68UF

5%

X6S

0402

6.3V

CRITICAL

2

1

3

Q8301

DMN32D2LFB4

DFN1006H4-3

1

2

6

Q8302

DMN5L06VK-7

SOT563

4

5

3

Q8302

SOT563

DMN5L06VK-7

2

1

R8336

201

MF

1/20W

1%

100K

PLACE_NEAR=Q8300.2:3.5mm

2

1

C8336

0201

25V C0G

390PF

2%

NOSTUFF

2

1

R8337

66.5K

PLACE_NEAR=Q8300.2:3.5mm

1/20W MF

1%

201

6

4

3

2

1

5

U8330

USON

CRITICAL

TPS3895ADRY

4

6

5 3

1

2

U8305

SOT891

CRITICAL

74LVC1G08

21

R8305

5%

1/20W

MF

201

0

21

R8338

0

201

5% MF

1/20W

20

2

1

C8307

10% 10V

0201

X5R-CERM

0.1UF

2

1

C8305

0402

2%

12PF

100V CERM

2

1

C8315

+/-0.1PF

3.0PF

PLACE_NEAR=J8300.28:2mm

NP0-C0G

25V 0201

2

1

C8314

PLACE_NEAR=J8300.5:2mm

3.0PF

+/-0.1PF

0201

25V NP0-C0G

SYNC_MASTER=MARY_X425G

eDP Display Connector

SYNC_DATE=12/11/2014

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm

PP3V3_S0_EDP_SW

DP_INT_ML_P<1>

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5VR3V3_SW_LCD

DP_INT_ML_N<3>

DP_INT_ML_P<3>

DP_INT_ML_P<2>

DP_INT_ML_N<1>

I2C_TCON_SDA_R

PP3V3_S0_EDP_SW

LCD_HPD_CONN

LCD_FSS

DP_INT_AUX_P

DP_INT_ML_P<0>

DP_INT_ML_N<0>

DP_INT_AUX_N

DP_INT_ML_N<2>

PP5V_S4

DP_INT_ML_C_P<2>

DP_INT_ML_C_P<1>

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5VR3V3_SW_LCD_UF

DP_INT_ML_F_P<3>

ISNS_LCD_PANEL_N ISNS_LCD_PANEL_P

DP_INT_ML_F_N<3>

I2C_TCON_SCL_R

I2C_BKLT_SDA

DP_INT_ML_F_N<0>

LCD_BKLT_PWM_R

LCD_HPD

DP_INT_AUXCH_C_P

DP_INT_ML_F_P<2>

PPVOUT_S0_LCDBKLT

DP_INT_ML_C_N<1>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<0>

DP_INT_ML_C_P<3>

DP_INT_ML_F_N<1>

DP_INT_ML_F_P<1>

DP_INT_ML_P<1>

DP_INT_ML_F_N<2>

LCD_5V_PLT_RST_BUF_L

PP3V3_S0_EDP_SW

SNS_3V3EDP_DIV

SNS_5VEDP_DIV

MAKE_BASE=TRUE

SNS_5VEDP_DIV

PP3V3_S0_EDP_SW

EDP5V_PGD_CT

I2C_BKLT_SCL

LCD_3V3_EN_R

MAKE_BASE=TRUE

LCD_3V3_EN_R

LCD_5V_EN_RLCD_5V_EN_R

MAKE_BASE=TRUE

DP_INT_ML_F_P<0>

DP_INT_ML_N<0>

DP_INT_ML_N<1>

DP_INT_ML_C_N<0>

DP_INT_ML_P<2>

DP_INT_ML_P<3>

PP3V3_S0_EDP_SW

DP_INT_AUX_N DP_INT_AUX_P LCD_HPD_CONN

DP_INT_AUXCH_C_N

DP_INT_ML_P<0>

DP_INT_ML_N<3>

DP_INT_ML_N<2>

LCD_3V3_EN

LCD_3V3_EN_R

DP_INT_ML_C_N<3>

PP3V3_S0

VOLTAGE=0.5V MIN_LINE_WIDTH=0.25 mm

SNS_5VEDP_DIV

MIN_NECK_WIDTH=0.1 mm

LCD_PWR_EN

SNS_3V3EDP_DIV

MAKE_BASE=TRUE

PP3V3_S0

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.19V

SNS_3V3EDP_DIV

LCD_5V_EN_L

BUF_5V_EN

LCD_PWR_EN

PP5VR3V3_SW_LCD_ISNS

PP3V3_S0_EDP_SW

LCD_FSS

LCD_5V_EN_R_L

PP3V3_S0

LCD_5V_EN_R

LCD_5V_EN

I2C_TCON_SDA_R

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

PLT_RST_BUF_L

BUF_5V_EN

PP3V3_S0_EDP_SW

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_FETCAP_LCD

MIN_NECK_WIDTH=0.1 mm

PP3V3_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5VR3V3_SW_LCD_ISNS

I2C_TCON_SCL_R

PP3V3_S0

<SCH_NUM>

83 OF 119

69 OF 97

69

69 86 97

86

69 86 97

69

69 86

69 86 97

37 38 51 61 66 67 81 84 86

97

69

97

63 86

97

97 69 86 97

97

69

69 69

69

69 69

97

69 86 97

69

69 86 97

69 86 97 69 86

69 86 97

69

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

69

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

69

69 82 86

69

69 82 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

69

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

69

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51

52 55 66 67 68 69 82 83 84

86 96

NC NC

NC

NC NC

IN

OUT

(1 OF 9)

PCIE_RX6N

PCIE_RX5N

PCIE_RX6P

PCIE_RX3N

PCIE_RX3P

PCIE_RX2N

PCIE_RX2P

PCIE_RX1N

PCIE_RX1P

PCIE_RX0N

PCIE_RX0P

PCIE_RX7N

PCIE_RX8P

TEST_PG

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_RX15N

PCIE_RX15P

PCIE_RX14P PCIE_RX14N

PCIE_RX8N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P

PCIE_RX13P

PCIE_CALR_RX

PCIE_CALR_TX

PCIE_RX4N

PCIE_RX4P

PCIE_RX5P

PCIE_RX7P

PCIE_RX9N

PCIE_RX9P

PCIE_RX10N

PCIE_RX10P

PCIE_RX12N

PCIE_RX13N

PCIE_TX0N

PCIE_TX0P

PCIE_TX1N

PCIE_TX1P

PCIE_TX2N

PCIE_TX2P

PCIE_TX3N

PCIE_TX3P

PCIE_TX4N

PCIE_TX4P

PCIE_TX5N

PCIE_TX5P

PCIE_TX6N

PCIE_TX6P

PCIE_TX7N

PCIE_TX7P

PCIE_TX8N

PCIE_TX8P

PCIE_TX9N

PCIE_TX9P

PCIE_TX10N

PCIE_TX10P

PCIE_TX11N

PCIE_TX11P

PCIE_TX12N

PCIE_TX12P

PCIE_TX13N

PCIE_TX13P

PCIE_TX14N

PCIE_TX14P

PCIE_TX15N

PCIE_TX15P

PERST*

IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(NONE)

Power aliases required by this page:

BOM options provided by this page:

- =PPV95_GPU_PCIE

Page Notes

Signal aliases required by this page:

(NONE)

21

R8400

201

1/20W

MF

5%

0

2

1

R8405

PLACE_NEAR=U8400.Y30:2.54MM

201

1/20W

1.69K

1%

MF

2

1

R8401

PLACE_NEAR=U8400.Y29:2.54MM

MF

201

1K

1%

1/20W

2

1

R8404

201

1K

5%

MF

1/20W

21

C8420

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.AA38:7mm

21

C8421

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.Y37:7mm

21

C8422

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.Y35:7mm

21

C8423

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.W36:7mm

21

C8424

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.W38:7mm

21

C8425

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.V37:7mm

21

C8426

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.V35:7mm

21

C8427

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.U36:7mm

21

C8428

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.U38:7mm

21

C8429

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.T37:7mm

21

C8430

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.T35:7mm

21

C8431

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.R36:7mm

21

C8432

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.R38:7mm

21

C8433

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.P37:7mm

21

C8434

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.P35:7mm

21

C8435

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U8400.N36:7mm

68 85 89

85 89

68 85 89

85 89

21

C8456

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.E10:7mm

21

C8455

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.F10:7mm

21

C8457

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.D10:7mm

21

C8459

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.A10:7mm

21

C8458

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.C10:7mm

21

C8460

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.B10:7mm

21

C8461

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.F9:7mm

21

C8462

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.E9:7mm

21

C8463

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.C9:7mm

21

C8464

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.D9:7mm

21

C8466

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.B9:7mm

21

C8465

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.A9:7mm

85 89

21

C8468

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.L5:7mm

21

C8467

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.M5:7mm

21

C8470

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.L2:7mm

21

C8469

20%

0.22UF

0201X6S-CERM6.3V

GND_VOID=TRUE

PLACE_NEAR=U0500.L1:7mm

AH16

AA30

N30 N29

N33 N32

P30 P29

P33 P32

T30 T29

T33 T32

U30 U29

U33 U32

W33 W32

H33 H32

K30 K29

J33 J32

K33 K32

L30 L29

L33 L32

Y33 Y32

M35 L36

N38 M37

P35 N36

R38 P37

T35 R36

U38 T37

V35 U36

W38 V37

Y35 W36

F35 E37

G38 F37

H35 G36

J38 H37

K35 J36

L38 K37

AA38

Y37

AB35 AA36

Y30 Y29

U8400

OMIT_TABLE

VENUS-XT

FCBGA

11 85 91

82 85

Venus PCI-E

SYNC_MASTER=MARY_X425G

SYNC_DATE=08/22/2014

GPU

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_C_N<5>

PEG_D2R_N<7>

PEG_D2R_C_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_C_P<4>

PEG_D2R_P<6>

PEG_D2R_N<5>

PEG_D2R_N<3>

PEG_D2R_P<5>

PEG_D2R_N<2>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_N<0>

PEG_R2D_P<7>

PEG_R2D_N<7>

GPU_TEST_PG

PEG_R2D_N<1>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_P<7>

PEG_D2R_C_P<5>

PEG_D2R_C_N<4>

PEG_D2R_P<3>

PEG_D2R_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_P<2>

PEG_D2R_C_P<2>

PEG_D2R_C_N<1>

PEG_D2R_C_N<2>

PEG_D2R_C_P<1>

PEG_D2R_P<0>

PEG_D2R_C_P<0>

PEG_D2R_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<1>

PEG_R2D_N<2>

PEG_R2D_P<3>

PEG_R2D_C_P<4>

PEG_R2D_P<6>

PEG_R2D_N<6>

PEG_R2D_N<3>

PEG_R2D_N<4>

PEG_R2D_N<5>

PEG_R2D_P<4>

PEG_R2D_C_N<2>

PEG_R2D_C_N<0>

PEG_R2D_N<0>

PEG_R2D_C_P<0>

PEG_R2D_P<0>

PEG_R2D_P<5>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3>

PEG_R2D_C_N<4>

PEG_R2D_C_N<5>

PEG_R2D_C_N<7>

PEG_CALRP

PP0V95_S0GPU

PEG_R2D_C_P<2>

EG_RESET_L

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_P<1>

PEG_CLK100M_N

PEG_CLK100M_P

GPU_RESET_R_L

PEG_CALRN

PEG_R2D_P<2>

PEG_R2D_C_P<5>

<SCH_NUM>

84 OF 119

70 OF 97

89

68 89

89

71 73 78 84

89

PCIE_PVDD

VDDR3

VDD_CT

VDDR4

VDDR1

VDDC

SPLL_PVSS

PCIE_VDDC

NC_PCIE_VDDR

NC_BIF_VDDC

MPLL_PVDD

FB_VDDCI

FB_GND

BIF_VDDC

VDDCI

VDDC

BIF_VDDC

FB_VDDC

SPLL_VDDC

SPLL_PVDD

(7 OF 9)

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

for GPU VR measurement

- =PP1V5R1V35_GPU_FB_VDDR1

- =PP3V3_GPU_VDDR4

- =PP1V0_GPU_PLL

- =PP1V8_GPU_PLL

- =PP1V8_GPU_PCIE_VDDC

Signal aliases required by this page:

Power aliases required by this page:

- =PPVCORE_GPU

BOM options provided by this page:

(NONE)

Page Notes

- =PP1V8_GPU_PCIE_VDDR

- =PP1V8_GPU_MEM_PLL

- =PP3V3_GPU_VDDR3

- =PP1V8_GPU_VDD_CT

75mA

250mA

150mA

200mA

2500mA

2000mA

52A (63A?)

1200mA

150mohm DCR

60mA

150mA

300mA

R8510/1/2 only stuffed

7A@0.9V

2

1

C85B0

10UF

0402

CERM-X6S

6.3V

20%

2

1

C85A0

0.1UF

X7R

10%

0201

6.3V 2

1

C85A1

0.1UF

X7R

10%

0201

6.3V 2

1

C85A2

0.1UF

X7R

10%

0201

6.3V

2

1

C8500

CERM-X6S 0402

10UF

6.3V

20%

2

1

C8501

CERM-X6S

10UF

0402

6.3V

20%

2

1

C8502

CERM-X6S

10UF

0402

6.3V

20%

2

1

C8505

4V X6S-CERM 0201

2.2UF

20%

2

1

C8506

4V X6S-CERM 0201

2.2UF

20%

2

1

C8507

4V X6S-CERM 0201

2.2UF

20%

2

1

C8508

4V X6S-CERM 0201

2.2UF

20%

2

1

C8509

4V X6S-CERM 0201

2.2UF

20%

2

1

C8510

X7R-CERM

10V

10%

0.01UF

0201

2

1

C8511

10V X7R-CERM

0.01UF

10%

0201

2

1

C8512

10V X7R-CERM

0.01UF

10%

0201

2

1

C8513

10V X7R-CERM

0.01UF

10%

0201

2

1

C8514

10V X7R-CERM

10%

0201

0.01UF

2

1

C8525

10UF

CERM-X6S 0402

6.3V

20%

2

1

C8551

10UF

CERM-X6S 0402

6.3V

20%

2

1

C8545

0402

10UF

CERM-X6S

6.3V

20%

2

1

C8542

0402

CERM-X6S

10UF

6.3V

20%

2

1

C8530

CERM-X6S 0402

10UF

6.3V

20%

2

1

C8537

0402

10UF

CERM-X6S

6.3V

20%

21

L8531

CRITICAL

0402

220-OHM-1A

2

1

C85C0

10UF

0402

CERM-X6S

6.3V

20%

2

1

C85C2

PLACE_NEAR=U8400.AF12:2.54MM

0.1UF

X7R

10%

0201

6.3V

2

1

C8535

PLACE_NEAR=U8400.AF23:2.54MM

0.1UF

10%

0201

X7R

6.3V

2

1

C8515

0.1UF

X7R

10%

0201

PLACE_NEAR=L8520.1:2.54MM

6.3V

2

1

C8516

0.1UF

PLACE_NEAR=L8551.1:2.54MM

X7R

10%

0201

6.3V

2

1

C8518

10%

PLACE_NEAR=L8531.1:2.54MM

0.1UF

X7R 0201

6.3V

2

1

C8519

0.1UF

X7R

10%

0201

PLACE_NEAR=L8532.1:2.54MM

6.3V

2

1

C8503

PLACE_NEAR=L8530.1:2.54MM

X7R

0.1UF

10%

0201

6.3V

2

1

C85A7

X6S

4V

0201

1.0UF

20%

2

1

C85A8

4V X6S 0201

1.0UF

20%

2

1

C85A9

4V X6S 0201

1.0UF

20%

2

1

C8528

4V X6S

PLACE_NEAR=U8400.AG26:2.54MM

0201

1.0UF

20%

2

1

C8534

PLACE_NEAR=U8400.AG23:2.54MM

6.3V X6S-CERM 0201

1UF

20%

2

1

C8533

6.3V X6S-CERM 0201

1UF

20%

2

1

C85C1

PLACE_NEAR=U8400.AG13:2.54MM

4V X6S 0201

1.0UF

20%

2

1

C8538

4V X6S

PLACE_NEAR=U8400.H8:2.54MM

0201

1.0UF

20%

2

1

C8543

4V X6S

PLACE_NEAR=U8400.AM10:2.54MM

0201

1.0UF

20%

2

1

C8531

PLACE_NEAR=U8400.AN9:2.54MM

4V

0201

X6S

1.0UF

20%

2

1

C8547

X6S

4V

PLACE_NEAR=U8400.AB37:2.54MM

0201

1.0UF

20%

2

1

C8548

X6S

4V

PLACE_NEAR=U8400.AB37:2.54MM

0201

1.0UF

20%

2

1

C8552

4V X6S 0201

1.0UF

20%

2

1

C8553

X6S

4V

0201

1.0UF

20%

2

1

C8554

4V X6S 0201

1.0UF

20%

2

1

C8555

4V X6S 0201

1.0UF

20%

2

1

C8556

4V X6S 0201

1.0UF

20%

2

1

C8557

4V X6S 0201

1.0UF

20%

2

1

C8558

X6S

4V

0201

1.0UF

20%

21

L8520

CRITICAL

0402

120OHM-25%-1.8A-0.06DCR

21

L8551

120OHM-25%-1.8A-0.06DCR

CRITICAL

0402

21

L8532

0402

CRITICAL

120OHM-25%-1.8A-0.06DCR

21

L8530

CRITICAL

120OHM-25%-1.8A-0.06DCR

0402

2

1

C8540

X7R

10%

0.1UF

PLACE_NEAR=U8400.H7:2.54MM

0201

6.3V

AG15

AG13

AG11

AF15

AF13

AF12

AF11

AD12

AG24

AG23

AF24

AF23

G17

G14

G11

AL9

AK8

AJ7

Y7

Y11

U7

U11

AG10

R11

P7

N11

M11

L7

L26

L23

L21

L16

L12

AF7

K8

K13

K11

J9

J7

H10

G29

G26

G23

G20

AD11

AC7

M23

M18

M16

M15

AD16

AD13

AC15

Y13

V15

AC12

T15

T12

R16

R13

R12

N22

N20

N17

N15

N13

AB13

AA13

AB23

AB21

AB18

AB16

Y28

Y26

Y23

Y21

Y18

AA27

Y16

V27

V24

V22

V20

V17

U26

U23

U21

U18

AA24

U16

T24

T22

T20

T17

R26

R23

R21

R18

N24

AA22

M26

AH28

AH27

AH22

AG18

AG16

AF22

AF20

AF17

AD26

AA20

AD23

AD21

AD18

AC27

AC24

AC22

AC20

AC17

AB28

AB26

AA17

AA15

AG27

AG26

AF27

AF26

AN9

AN10

AM10

R28

N28

M28

L28

J30

J29

H30

H29

U28

T28

G31

G30

AB37

Y31

W30

AA34

AA33

AA32

AA31

W29

V28

H8

H7

AG28

AF28

AH29

T27

N27

U8400

VENUS-XT

FCBGA

OMIT_TABLE

2

1

C8550

10UF

0402

CERM-X6S

6.3V

20%

2

1

C8567

4V X6S-CERM 0201

2.2UF

20%

2

1

C8577

4V X6S-CERM 0201

2.2UF

20%

2

1

R8510

100

NOSTUFF

MF

1/20W

1%

PLACE_NEAR=U8400.AF28:2.54MM

201

2

1

R8511

PLACE_NEAR=U8400.AH29:2.54MM

1/20W

1%

100

MF

NOSTUFF

201

2

1

R8512

1/20W

1% MF

100

PLACE_NEAR=U8400.AG28:2.54MM

NOSTUFF

201

21

XW8510

SM

NO_XNET_CONNECTION=TRUE

21

XW8512

SM

NO_XNET_CONNECTION=TRUE

79 96

80 96

21

XW8542

SM

2

1

C8517

3.0PF

CRITICAL

+/-0.1PF NP0-C0G

25V 0201

2

1

C8504

CRITICAL

NP0-C0G

12PF

25V

5% 0201

2

1

C855A

CRITICAL

3.0PF

+/-0.1PF NP0-C0G

25V 0201

2

1

C8559

12PF

NP0-C0G

CRITICAL

5%

25V

0201

2

1

C8597

12PF

5%

CRITICAL

NP0-C0G 25V

0201

2

1

C8598

3.0PF

+/-0.1PF NP0-C0G

25V

CRITICAL

0201

2

1

C85A3

CRITICAL

NP0-C0G

12PF

25V

5% 0201

2

1

C85A4

CRITICAL

3.0PF

+/-0.1PF NP0-C0G

25V 0201

2

1

C8520

0.1UF

X7R

10%

0201

6.3V 2

1

C8521

0.1UF

X7R

10%

0201

6.3V 2

1

C8522

0.1UF

X7R

10%

0201

6.3V 2

1

C8523

0.1UF

X7R

10%

0201

6.3V 2

1

C8524

0.1UF

X7R

10%

0201

6.3V

2

1

C8529

0.1UF

PLACE_NEAR=U8400.AF26:2.54MM

X7R

10%

0201

6.3V

2

1

C8544

0.1UF

X7R

10%

0201

PLACE_NEAR=U8400.AM10:2.54MM

6.3V

2

1

C8532

10%

PLACE_NEAR=U8400.AN9:2.54MM

0.1UF

X7R 0201

6.3V

2

1

C8590

0402

10UF

CERM-X6S

6.3V

20%

2

1

C8591

0402

10UF

CERM-X6S

6.3V

20%

2

1

C8592

CERM-X6S 0402

10UF

6.3V

20%

2

1

C8593

10UF

0402

CERM-X6S

6.3V

20%

2

1

C8594

CERM-X6S 0402

10UF

6.3V

20%

2

1

C8595

10UF

0402

CERM-X6S

6.3V

20%

2

1

C8596

CERM-X6S

10UF

0402

6.3V

20%

2

1

C8560

4V X6S-CERM 0201

2.2UF

20%

2

1

C8561

4V

0201

2.2UF

X6S-CERM

20%

2

1

C8562

4V X6S-CERM 0201

2.2UF

20%

2

1

C8563

4V X6S-CERM 0201

2.2UF

20%

2

1

C8564

4V X6S-CERM 0201

2.2UF

20%

2

1

C8565

4V X6S-CERM 0201

2.2UF

20%

2

1

C8566

4V X6S-CERM 0201

2.2UF

20%

2

1

C8576

4V X6S-CERM 0201

2.2UF

20%

2

1

C8575

4V X6S-CERM 0201

2.2UF

20%

2

1

C8574

4V X6S-CERM 0201

2.2UF

20%

2

1

C8573

4V X6S-CERM 0201

2.2UF

20%

2

1

C8572

4V X6S-CERM 0201

2.2UF

20%

2

1

C8571

4V X6S-CERM 0201

2.2UF

20%

2

1

C8570

4V X6S-CERM 0201

2.2UF

20%

Venus CORE/FB POWER

SYNC_DATE=09/22/2014

GPU

SYNC_MASTER=MARY_X425G

PP0V95_GPU_PLL

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.95V

GND_SPLL_PVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PP0V95_S0GPU

PP1V8_GPUIFPX

PPVCORE_GPU

PP1V35_GPU_REG

PPVDDCI_S0_ISENSE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_GPU_VDDR3

PP0V95_S0GPU

VSNS_GPU_VDDI_P

PP1V8_GPU_PLL

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPUIFPX

PP0V95_S0GPU

PP1V8_GPUIFPX

PP3V3_S0GPU

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_VDD_CT

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.8V

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_MEM_PLL

GPU_GND_SENSE

VOLTAGE=0.0V MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

VSNS_GPU_VDDC_P

VSNS_GPU_VDDI_P

PPVDDCI_S0_ISENSE

PPVCORE_GPU

VSNS_GPU_VDDI_N

VSNS_GPU_VDDC_N

<SCH_NUM>

85 OF 119

71 OF 97

70 71

73

78

84

71 76 78 80 84

47 71 79 84

47 72 73 74 75 84

71 80 84

70 71 73 78 84

71 80 85 96

71 76 78 80 84

70 71 73 78 84

71 76 78 80 84

47 66 68 72 76 77 79 80

84

71 76 78 80 84

71

71 79

85 96

71 79 85 96

71 80 85 96

71 80 84

47 71 79 84

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI

BI BI BI BI

BI BI

NC

OUT OUT

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT

BI

OUT OUT OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

OUT OUT

OUT

OUT OUT

OUT

NC

OUT

NC NC NC

NC NC

OUT

DQA0_4

WCKA1_0

DQA0_10

DQA0_0 DQA0_1 DQA0_2

DQA1_31

MAA0_8

MAA0_7

MAA0_6

DQA0_16

CLKA0*

CLKA1*

RASA1*

CASA1*

CASA0*

CSA0_1*

CSA0_0*

CSA1_1*

CSA1_0*

WEA0*

DQA0_7

DQA0_5

CLKA1

WCKA0_1*

MAA1_7

MAA1_5

MAA0_2

MAA1_0

MAA1_6

DQA1_16 DQA1_17 DQA1_18

DQA0_13

DQA0_11

ADBIA0 ADBIA1

CKEA0 CKEA1

CLKA0

DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3

DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

DQA0_6

DQA0_8 DQA0_9

DQA0_14 DQA0_15

DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31

DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15

DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30

EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3

EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

MAA0_0 MAA0_1

MAA0_3 MAA0_4 MAA0_5

MAA0_9

MAA1_1 MAA1_2 MAA1_3 MAA1_4

MAA1_8 MAA1_9

MEM_CALRP0

MVREFDA MVREFSA

NC_MEM_CALRN0 NC_MEM_CALRN1 NC_MEM_CALRN2

NC_MEM_CALRP1 NC_MEM_CALRP2

WCKA0_0

WCKA0_0*

WCKA0_1

WCKA1_0*

WCKA1_1

WCKA1_1*

DQA0_3

RASA0*

WEA1*

DQA0_12

(4 OF 9) (5 OF 9)

CSB1_0* CSB1_1*

MAB0_9

MAB0_8

RASB1*

CASB0*

DQB0_31

DQB0_29

DQB0_16

DQB0_15

DQB0_14

DQB0_13

DQB0_12

DQB0_11

WEB0*

TESTEN

RASB0*

MVREFSB

MVREFDB

MAB1_9

MAB1_8

MAB1_6

MAB1_4

MAB1_3

MAB1_1

MAB0_7

MAB0_6

MAB0_5

MAB0_4

MAB0_3

MAB0_2

MAB0_1

MAB0_0

EDCB1_3

EDCB1_2

EDCB1_1

EDCB1_0

EDCB0_3

EDCB0_2

EDCB0_1

EDCB0_0

DQB1_31

DQB1_30

DQB1_29

DQB1_28

DQB1_27

DQB1_26

DQB1_25

DQB1_24

DQB1_23

DQB1_22

DQB1_21

DQB1_20

DQB1_19

DQB1_18

DQB1_17

DQB1_16

DQB1_15

DQB1_14

DQB1_13

DQB1_12

DQB1_11

DQB1_10

DQB1_9

DQB1_8

DQB1_6

DQB1_5

DQB1_4

DQB1_3

DQB1_2

DQB1_1

DQB1_0

DQB0_30

DQB0_28

DQB0_25

DQB0_24

DQB0_23

DQB0_22

DQB0_21

DQB0_20

DQB0_19

DQB0_17

DQB0_8

DQB0_7

DQB0_6

DQB0_5

DDBIB1_3

DDBIB1_2

DDBIB1_1

DDBIB1_0

DDBIB0_3

DDBIB0_2

DDBIB0_1

DDBIB0_0

CSB0_1*

CSB0_0*

CLKTESTB

CLKTESTA

CLKB1*

CLKB1

CLKB0

CKEB1

CKEB0

CASB1*

ADBIB1

ADBIB0

DQB0_18

DQB0_27

DQB0_26

DQB0_10

DQB0_9

CLKB0*

WCKB0_0*

WCKB0_0

WCKB1_1*

WCKB1_1

WCKB1_0*

WCKB1_0

WCKB0_1*

MAB1_0

MAB1_2

MAB1_5

MAB1_7

WCKB0_1

WEB1*

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4

DQB1_7

DRAM_RST

IN IN IN IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Signal aliases required by this page:

(NONE)

- =PP1V5R1V35_FB_REF

- =PP1V5R1V35_FB_CAL

Page Notes

BOM options provided by this page:

Power aliases required by this page:

74 97

75 97

74 97

75 97

2

1

R8650

10K

MF

5% 1/20W

201

2

1

C8651

X5R

6.3V

201

10%

NOSTUFF

0.1UF

2

1

C8652

NOSTUFF

X5R

6.3V

201

10%

0.1UF

2

1

C8660

50V C0G-CERM

PLACE_NEAR=R8661.2:5MM

0402

5%

120PF

2

1

R8651

51.1

201

1/20W

MF

1%

NOSTUFF

2

1

R8652

51.1

201

1/20W MF

1%

NOSTUFF

74 75

21

R8613

1% MF

201

1/20W

PLACE_NEAR=U8400.M27:2.54MM

120

NOSTUFF

2

1

R8660

4.99K

1%

1/20W

201

MF

PLACE_NEAR=U8400.AH11:5MM

21

R8661

10

1%

MF

201

PLACE_NEAR=U8400.AH11:5MM

1/20W

21

R8662

51

MF

1/20W

5%

PLACE_NEAR=R8661.2:5MM

201

2

1

R8600

1/20W MF 201

1%

40.2

PLACE_NEAR=U8400.L18:2.54MM

NOSTUFF

2

1

R8601

PLACE_NEAR=U8400.L18:2.54MM

201

MF

1/20W

1%

100

NOSTUFF

2

1

R8602

PLACE_NEAR=U8400.L20:2.54MM

201

MF

1/20W

1%

40.2

NOSTUFF

2

1

R8603

PLACE_NEAR=U8400.L20:2.54MM

201

MF

1/20W

1%

100

NOSTUFF

2

1

R8604

MF

40.2

1% 1/20W

201

PLACE_NEAR=U8400.Y12:2.54MM

NOSTUFF

2

1

R8605

PLACE_NEAR=U8400.Y12:2.54MM

100

1% 1/20W MF 201

NOSTUFF

2

1

R8606

PLACE_NEAR=U8400.AA12:2.54MM

201

MF

1/20W

1%

40.2

NOSTUFF

2

1

R8607

PLACE_NEAR=U8400.AA12:2.54MM

100

201

MF

1/20W

1%

NOSTUFF

74 97

75 97

L15

K26

D9

E10

A14

C14

E22

D23

C32

A32

K19

K23

AH12

M12

AG12

N12

L27

L20

L18

M27

M20

J19

H17

J17

H16

J16

G16

L13

H20

H19

M21

H23

G21

H21

J26

H26

J24

H24

J23

G24

D7

J10

E12

E16

E20

D25

D29

C34

D13

F14

E14

D15

F16

A16

A5

E6

D17

C6

A6

E8

C8

A8

G9

K10

K9

G8

G10

F18

H11

J13

H13

G13

C10

A10

F10

D11

A12

F12

A18

C18

F30

D31

E32

F32

D33

G32

E18

D19

E34

F20

A20

D21

F22

A22

C22

E24

A24

C24

F24

A35

A26

C26

F26

D27

E28

A28

C28

F28

A30

C30

C35

C37

F8

J11

C12

C16

C20

E26

E30

A34

K16

M13

K27

K24

H14

J14

G27

H27

J20

K21

K17

K20

G19

J21

U8400

OMIT_TABLE

VENUS-XT

FCBGA

AB11

N10

AK5

AK6

AF5

AE4

T5

T3

H1

H3

AD28

Y10

T10

AA12

Y12

V12

W8

AA9

Y8

AA8

AA7

AC9

AC8

W9

Y9

U12

T8

U8

U9

N9

N8

N7

P9

T9

P8

AM5

AJ9

AH1

AB5

V5

P3

K3

F6

AH11

AF3

AF1

AD5

AD3

AD1

AD6

AP5

AP1

AB3

AP3

AN4

AM1

AM6

AL4

AK1

AM7

AM8

AL7

AK9

AB1

AG7

AG8

AF9

AF8

AK3

AJ4

AH6

AH5

AG4

AF6

AB6

AA4

H6

H5

G4

F5

F3

F1

Y5

Y3

E1

Y1

Y6

V3

V1

V6

U4

T1

T6

R4

P5

E3

P6

N4

M5

M3

M1

M6

L4

K5

K6

J4

C3

C5

AM3

AJ8

AH3

AC4

W4

P1

K1

G7

AC10

AD10

L10

P10

AL10

AK10

AD7

AD8

L8

L9

AA11

U10

AA10

W10

W7

T7

U8400

OMIT_TABLE

VENUS-XT

FCBGA

2

1

C8600

20%

X5R

6.3V

1.0UF

0201

PLACE_NEAR=U8400.L18:2.54MM

NOSTUFF

2

1

C8601

20%

X5R

6.3V

PLACE_NEAR=U8400.L20:2.54MM

1.0UF

0201

NOSTUFF

2

1

C8602

20%

X5R

6.3V

PLACE_NEAR=U8400.Y12:2.54MM

1.0UF

0201

NOSTUFF

2

1

C8603

20%

X5R

6.3V

0201

1.0UF

PLACE_NEAR=U8400.AA12:2.54MM

NOSTUFF

21

R8665

5%

MF

NOSTUFF

10K

1/20W

201

74 97

75 97

Venus FRAME BUFFER I/F

SYNC_MASTER=J45G_AMD SYNC_DATE=06/30/2014

GPU

FB_B1_DQ<8> FB_B1_DQ<9>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<0>

FB_B1_A<7>

FB_B1_WCLK_N<0>

FB_B1_EDC<3>

FB_B1_EDC<2>

FB_B1_EDC<1>

FB_B1_EDC<0>

FB_B0_EDC<3>

FB_B0_EDC<2>

FB_B0_EDC<1>

FB_B0_EDC<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

FB_A0_WCLK_P<0>

FB_A1_A<7>

FB_A1_A<6>

FB_A1_A<1>

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

FB_A1_EDC<3>

FB_A1_EDC<2>

FB_A1_EDC<1>

FB_A1_EDC<0>

FB_A0_EDC<3>

FB_A1_WCLK_P<1>

FB_A0_EDC<1>

FB_A0_EDC<0>

FB_A0_EDC<2>

FB_A1_WCLK_N<1>

FB_A0_DBI_L<0>

PP3V3_S0GPU

FB_A0_DQ<0> FB_A0_DQ<1>

FB_A0_DQ<3> FB_A0_DQ<4>

NC_FB_B0_A<9>

FB_B1_A<8>

GPU_FB_RESET_L

FB_A1_WE_L

FB_A1_DQ<24>

NC_FB_A0_A<9>

FB_A1_A<8> NC_FB_A1_A<9>

FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8>

FB_A0_DQ<22>

FB_A0_DQ<20>

FB_A1_DQ<0>

FB_A1_DQ<10>

FB_RESET_RC_L

FB_B1_DQ<13>

FB_B0_DQ<18>

FB_B0_DQ<17>

FB_B0_WE_L FB_B1_WE_L

FB_A0_CS_L

GPU_TEST_EN

GPU_CLK_TEST_P

FB_B1_DQ<29>

FB_B1_DQ<25> FB_B1_DQ<26> FB_B1_DQ<27>

GPU_CLK_TEST_RC_P

FB_B1_DQ<30>

FB_A1_CLK_P

GPU_CLK_TEST_N

FB_B_VREFS

FB_A1_DQ<23>

FB_A1_DQ<26>

FB_A1_DQ<28>

FB_A1_CKE_L

FB_A0_CKE_L

FB_A1_RAS_L

FB_A1_CLK_N

FB_A0_CAS_L

FB_B1_DQ<24>

FB_B1_DQ<23>

FB_B1_DQ<22>

FB_A_VREFS

PP1V35_GPU_REG

FB_A1_DQ<29>

FB_A1_DQ<27>

PP1V35_GPU_REG

FB_B_VREFD

FB_A_VREFS

FB_A_VREFD

FB_B0_DQ<8> FB_B0_DQ<9>

FB_RESET_L

PP1V35_GPU_REG

FB_A0_DQ<12>

FB_A0_RAS_L

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<0>

FB_A0_WCLK_N<0>

FB_CALRP0

FB_A1_A<4>

FB_A1_A<3>

FB_A1_A<2>

FB_A0_A<7>

FB_A0_A<6>

FB_A0_A<5>

FB_A0_A<4>

FB_A0_A<3>

FB_A0_A<1>

FB_A0_A<0>

FB_A1_DQ<31>

FB_A1_DQ<30>

FB_A1_DQ<25>

FB_A1_DQ<22>

FB_A1_DQ<21>

FB_A1_DQ<20>

FB_A1_DQ<19>

FB_A1_DQ<15>

FB_A1_DQ<14>

FB_A1_DQ<13>

FB_A1_DQ<12>

FB_A1_DQ<11>

FB_A1_DQ<9>

FB_A1_DQ<7>

FB_A1_DQ<6>

FB_A1_DQ<5>

FB_A1_DQ<4>

FB_A1_DQ<3>

FB_A1_DQ<2>

FB_A1_DQ<1>

FB_A0_DQ<31>

FB_A0_DQ<30>

FB_A0_DQ<29>

FB_A0_DQ<28>

FB_A0_DQ<27>

FB_A0_DQ<26>

FB_A0_DQ<25>

FB_A0_DQ<23>

FB_A0_DQ<21>

FB_A0_DQ<19>

FB_A0_DQ<18>

FB_A0_DQ<17>

FB_A0_DQ<16>

FB_A0_DQ<15>

FB_A0_DQ<14>

FB_A0_DQ<9>

FB_A1_DBI_L<3>

FB_A1_DBI_L<2>

FB_A1_DBI_L<1>

FB_A0_DBI_L<3>

FB_A0_DBI_L<1>

FB_A0_CLK_P

FB_A1_ABI_L

FB_A0_ABI_L

FB_A0_DQ<11>

FB_A0_DQ<13>

FB_A1_DQ<18>

FB_A1_DQ<17>

FB_A1_DQ<16>

FB_A1_A<0>

FB_A0_A<8>

FB_A0_A<2>

FB_A1_A<5>

FB_A0_DQ<10>

FB_A0_WE_L

FB_A1_CS_L

FB_A1_CAS_L

FB_A0_CLK_N

FB_B1_CS_L

FB_B0_A<8>

FB_B1_RAS_L

FB_B0_DQ<31>

FB_B0_DQ<29>

FB_B0_DQ<16>

FB_B0_DQ<15>

FB_B0_DQ<14>

FB_B0_DQ<13>

FB_B0_DQ<12>

FB_B0_DQ<11>

FB_B0_RAS_L

FB_B_VREFS

FB_B_VREFD

FB_B1_A<6>

FB_B1_A<4>

FB_B1_A<3>

FB_B1_A<1>

FB_B0_A<7>

FB_B0_A<6>

FB_B0_A<5>

FB_B0_A<4>

FB_B0_A<3>

FB_B0_A<2>

FB_B0_A<1>

FB_B0_A<0>

FB_B1_DQ<31>

FB_B1_DQ<28>

FB_B1_DQ<21>

FB_B1_DQ<20>

FB_B1_DQ<19>

FB_B1_DQ<18>

FB_B1_DQ<17>

FB_B1_DQ<16>

FB_B1_DQ<15>

FB_B1_DQ<14>

FB_B1_DQ<12>

FB_B1_DQ<11>

FB_B1_DQ<10>

FB_B1_DQ<6>

FB_B1_DQ<5>

FB_B1_DQ<4>

FB_B1_DQ<3>

FB_B1_DQ<2>

FB_B1_DQ<1>

FB_B1_DQ<0>

FB_B0_DQ<30>

FB_B0_DQ<28>

FB_B0_DQ<25>

FB_B0_DQ<24>

FB_B0_DQ<23>

FB_B0_DQ<22>

FB_B0_DQ<21>

FB_B0_DQ<20>

FB_B0_DQ<19>

FB_B0_DQ<7>

FB_B0_DQ<6>

FB_B1_DBI_L<3>

FB_B1_DBI_L<2>

FB_B1_DBI_L<1>

FB_B1_DBI_L<0>

FB_B0_DBI_L<3>

FB_B0_DBI_L<2>

FB_B0_DBI_L<1>

FB_B0_DBI_L<0>

FB_B0_CS_L

FB_B1_CLK_N

FB_B1_CLK_P

FB_B0_CLK_P

FB_B1_CKE_L

FB_B0_CKE_L

FB_B1_CAS_L

FB_B1_ABI_L

FB_B0_ABI_L

FB_B0_DQ<27>

FB_B0_DQ<26>

FB_B0_DQ<10>

FB_B0_CLK_N

FB_B1_WCLK_P<0>

FB_B1_A<0>

FB_B1_A<2>

FB_B1_A<5>

FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2>

FB_B0_DQ<4>

FB_B1_DQ<7>

FB_B0_DQ<5>

FB_B0_DQ<3>

PP1V35_GPU_REG

FB_B0_CAS_L

FB_A0_DQ<5>

FB_A0_DQ<2>

FB_A1_DQ<8>

FB_A1_DBI_L<0>

FB_A0_DBI_L<2>

FB_A_VREFD

FB_A0_DQ<24>

GPU_CLK_TEST_RC_N

NC_FB_B1_A<9>

<SCH_NUM>

86 OF 119

72 OF 97

47 66 68 71 76 77 79 80 84

87

97

72

47 71 72 73 74 75 84 47 71 72 73 74 75

84

72

47 71 72 73 74 75 84

72

47 71 72 73 74 75 84

72

97

87

IN

VID1

SET1

PGOOD

OCSET

FB

VO

EN

GND

PGND

PHASE

LGATE

UGATE

BOOT

VCC

PVCC

SET0

FSEL

RTN

VID0

SREF

OUT

IN

BG

TGR

TG

PGND

VIN

VSW

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Rb>

GPIO 21 --> VID1

0 0 1.5V

5.2A MAX OUTPUT

F = 500 KHZ

12A MAX OUTPUT

VOUT = 1.5V / 1.35V

<Ra>

376S0959

<Rb>

VOUT = 0.95V

F = 500 KHZ

Vout = 0.5V * (1 + Ra / Rb)

VID1 VID0 FBVDD

1 0 1.35V

APN 152S00140

152S00139

376S1038

<Ra>

GPU FB SUPPLY

MIRROR C8702 AND C8708

MIRROR C8750 AND C8758

GPU 0.95V/BIF_VDDC SUPPLY

2

1

C8710

TANT

PLACE_NEAR=L8710.2:3MM

CASE-B2-SM

2V

270UF

CRITICAL

20%

2

1

C8702

25V X6S-CERM 0402

2.2UF

20%

2

1

C8708

PLACE_NEAR=Q8710.1:1.5MM

25V X6S-CERM 0402

2.2UF

20%

2

1

C8707

68UF

16V

POLY-TANT

CRITICAL

CASE-D2E-SM

20%

2

1

C8705

0.1UF

X7R-CERM

16V

10%

0402

2 1

R8739

5%

402

1/16W MF-LF

1

2

1

R8709

5%

402

0

1/16W MF-LF

2

1

C8721

6.3V CERM-X6S 0402

10UF

20%

2

1

R8701

5%

201

2.2

1/20W

MF

2

1

C8711

5%

1000PF

CERM

PLACE_NEAR=L8760.2:1.5MM

0402

25V

43

21

R8730

CRITICAL

CYN

1W

0612

0.002

1%

2

1

R8721

201

1/20W

4.64K

MF

1%

2 1

C8770

0201

X7R

2200PF

10% 25V

2

1

R8772

1/20W 201

4.64K

MF

1%

21

XW8700

SM

PLACE_NEAR=U8700.1:1mm

68

12

5

6

19

17

7

9

8

4

20

16

14

2

11

1

3

13

10

15 18

U8700

CRITICAL

UTQFN

ISL95870AH

68

2

1

R8713

5%

201

1/20W

0

NOSTUFF

MF

2

1

C8722

X6S-CERM 0402

10% 10V

2.2UF

76 77

2

1

R8717

191K

1/20W

0.1% MF

0201

2

1

R8718

MF

95.3K

0.1%

0201

1/20W

2

1

C8723

X7R-CERM

16V

0.01UF

0402

10%

21

R8700

5%

201

1/20W

0

MF

2

1

R8734

MF

16.9K

1/20W

0.1%

0201

2

1

C8715

5%

0201

C0G

50V

10PF

2

1

R8702

1/20W 201

4.64K

NOSTUFF

MF

1%

21

R8731

201

1/20W

1.62K

MF

1%

NO_XNET_CONNECTION=TRUE

21

R8703

1/20W

201

1.62K

MF

1%

NO_XNET_CONNECTION=TRUE

2

1

R8704

201

1/20W MF

1%

4.64K

NOSTUFF

2

1

C8726

5%

0201

C0G

50V

10PF

2

1

C8706

68UF

CASE-D2E-SM

POLY-TANT

CRITICAL

16V

20%

2

1

C8712

270UF

CASE-B2-SM

TANT

2V

PLACE_NEAR=L8710.2:3MM

CRITICAL

20%

2 1

C8700

0201

2200PF

X7R

10% 25V

2

1

R8705

3.01K

1/20W 201

MF

1%

2

1

C8750

25V X6S-CERM 0402

2.2UF

20%

2

1

C8758

PLACE_NEAR=Q8760.1:1.5MM

25V X6S-CERM 0402

2.2UF

20%

2

1

R8771

3.01K

1/20W

201

MF

1%

2

1

C8795

16V X7R-CERM

0.1UF

0402

10%

2

1

R8775

5%

1/16W

2.2

402

MF-LF

2 1

R8796

5%

402

MF-LF

1

1/16W

8

7

6

1

4

3

9

5

Q8760

CSD58873Q3D

Q3D

CRITICAL

2

1

C8751

6.3V CERM-X6S 0402

10UF

20%

2

1

R8751

5%

2.2

201

1/20W

MF

8

13

11

4

2

14

10

9

16

7

15

1

5

6

3

12

U8750

CRITICAL

UTQFN

ISL95870

21

XW8750

SM

PLACE_NEAR=U8750.1:1mm

68

2

1

R8753

5%

0

1/20W

NOSTUFF

201

MF

2

1

C8752

X6S-CERM

0402

10% 10V

2.2UF

68 82

2

1

C8755

5%

C0G

50V

10PF

0201

2

1

C8753

16V X7R-CERM

0.047UF

0402

10%

2

1

R8755

MF

1/20W

3.01K

NO_XNET_CONNECTION=TRUE

0.1%

0201

2

1

R8754

MF

1/20W

3.01K

NO_XNET_CONNECTION=TRUE

0.1%

0201

2

1

R8757

MF

1/20W

3.32K

0.1%

0201

2

1

C8754

5%

0201

10PF

50V C0G

2

1

R8756

MF

3.32K

1/20W

0.1%

0201

2

1

C8760

270UF

CRITICAL

TANT

PLACE_NEAR=L8760.2:3MM

2V

CASE-B2-SM

20%

43

21

R8795

CRITICAL

CYN

0.003

1W

0612

1%

2

1

C8759

5%

1000PF

CERM

PLACE_NEAR=L8760.2:1.5MM

0402

25V

2

1

C8756

CRITICAL

16V

POLY-TANT

68UF

CASE-D2E-SM

20%

21

L8760

CRITICAL

PIME053T-SM

1.0UH-20%-8.6A

21

XW8755

NO_XNET_CONNECTION=TRUE

SM

21

XW8754

SM

NO_XNET_CONNECTION=TRUE

21

XW8731

SM

NO_XNET_CONNECTION=TRUE

21

XW8703

SM

NO_XNET_CONNECTION=TRUE

8

732

54

6

1

Q8710

SIZ710DT

CRITICAL

POWERPAK-6X3.7

21

L8710

CRITICAL

PILE063T-SM

0.68UH-20%-14A

2

1

C8713

CASE-B2-SM

TANT

270UF

2V

CRITICAL

PLACE_NEAR=L8710.2:3MM

20%

2

1

C8761

CRITICAL

PLACE_NEAR=L8760.2:3MM

CASE-B2-SM

TANT

2V

270UF

20%

2

1

C8762

CASE-B2-SM

2V

CRITICAL

TANT

270UF

PLACE_NEAR=L8760.2:3MM

20%

2

1

C8714

PLACE_NEAR=L8710.2:3MM

CRITICAL

CASE-B2-SM

2V

270UF

TANT

20%

2

1

R8706

5%

201

2.2

1/20W MF

2

1

C8709

CRITICAL

33UF

16V POLY-TANT CASED12-SM

20%

2

1

C8703

5%

CERM

1000PF

0402

25V

2

1

C8757

5%

CERM

1000PF

0402

25V

2

1

C8701

0201

5%

12PF

NP0-C0G

CRITICAL

25V

2

1

C8704

0201

CRITICAL

NP0-C0G

+/-0.1PF

3.0PF

25V

2

1

C8771

NP0-C0G

12PF

5% 0201

CRITICAL

25V

2

1

C8772

3.0PF

+/-0.1PF NP0-C0G

CRITICAL

0201

25V

SYNC_MASTER=ADITYA_X425G

0V95 GPU / 1V35 FB Power Supply

SYNC_DATE=09/16/2014

GPU

GPUFB_LL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

GPUFB_VBST

P1V35R1V5FB_EN

PP5V_S0GPU_P1V35_GPU

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

PP1V35_GPU_REG

GPUFB_SREF

P0V95_GPU_FB

P0V95_GPU_VO

PP0V95_S0GPU

GPUFB_SET0

ISNS_PP0V95_S0GPU_N

ISNS_PP0V95_S0GPU_P

PP0V95_S0GPU

MIN_LINE_WIDTH=0.6 mm

P0V95_S0GPU_REG_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVIN_S5_HS_GPU_ISNS

P0V95_GPU_LL

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P0V95_GPU_LL_FET

SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GPUFB_OCSET

PPVIN_S5_HS_GPU_ISNS

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

GPUFB_BOOT_RC

P0V95_GPU_RTN

P0V95_GPU_OCSET

VSNS_GPU_0V95_XW_P

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P0V95_GPU_AGND

P1V35R1V5FB_PGOOD

PP1V35_GPU_REG

GPUFB_CS_P

P0V95_GPU_BOOT_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm DIDT=TRUE

PP5V_S0

GPUFB_DRVH_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

P0V95_GPU_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VSNS_GPU_FB_XW_P

GPUFB_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P0V95_GPU_DRVH_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

P0V95_S0GPU_PGOOD

P0V95_GPU_VBST

MIN_LINE_WIDTH=0.3 mm DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

P0V95_GPU_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

VSNS_GPU_FB_XW_N

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP5V_S0GPU_P1V05_GPU

MIN_LINE_WIDTH=0.6 mm

P0V95_GPU_SREF

P0V95_GPU_FSEL

P0V95_S0GPU_EN

PP5V_S0

PP5V_S0_GPUFB_PVCC

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

FBVDD_ALTVO

GPUFB_FSEL

PP1V5R1V35_GPU_REG_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

GPUFB_CS_N

GPUFB_SET1

VSNS_GPU_0V95_XW_N

GPUFB_SET_R

DIDT=TRUE

GATE_NODE=TRUE

GPUFB_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GPUFB_SENSE_DIV

GPUFB_RTN_DIV

GPUFB_VO

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GPUFB_AGND

<SCH_NUM>

87 OF 119

73 OF 97

47 71 72 73 74 75 84

70 71 73 78 84

47 96

70 71 73 78 84

47 73 79 80 84

96

47 71 72 73 74 75 84

47 96

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

96

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

47 96

96

A12/A13

A10/A0

DBI0* DBI1* DBI2* DBI3*

DQ1

DQ0

VPP/NC

DQ30

DQ24

DQ31

WCK01

DQ14

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

CS*

CK

ABI*

CK*

A8/A7 A9/A1

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

DQ28

RESET*

WCK23*

WCK23

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

DQ8

VPP/NC

WCK01*

EDC2

EDC1

(MF=0)

SYM 1 OF 2

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

SYM 2 OF 2

A12/A13

A10/A0

DBI0* DBI1* DBI2* DBI3*

DQ1

DQ0

VPP/NC

DQ30

DQ24

DQ31

WCK01

DQ14

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

CS*

CK

ABI*

CK*

A8/A7 A9/A1

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

DQ28

RESET*

WCK23*

WCK23

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

DQ8

VPP/NC

WCK01*

EDC2

EDC1

(MF=0)

SYM 1 OF 2

OUT OUT OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

NC

BI BI BI BI

IN IN IN IN

IN

IN IN

IN IN IN IN

IN

IN IN

IN

IN IN

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

SYM 2 OF 2

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

- =PP1V5R1V35_S0_FB_VDD

(NONE)

Power aliases required by this page:

2

1

C8884

X6S

4V

NOSTUFF

0201

1.0UF

20%

2

1

R8884

MF

1/20W

201

2.37K

NOSTUFF

1%

2

1

C8885

X6S

4V

1.0UF

NOSTUFF

0201

20%

2

1

R8885

NOSTUFF

MF

1/20W

201

5.49K

1%

2

1

C8800

20%

4.7UF

0402

X6S

6.3V 2

1

C8801

0402

X6S

20%

6.3V

4.7UF

2

1

C8802

6.3V X6S

20%

0402

4.7UF

2

1

C8803

4.7UF

X6S

6.3V

20%

0402

2

1

C8804

6.3V

0402

X6S

4.7UF

20%

2

1

C8805

0402

20%

X6S

6.3V

4.7UF

2

1

C8850

0402

6.3V X6S

4.7UF

20%

2

1

C8851

0402

6.3V

20%

4.7UF

X6S

2

1

C8852

0402

6.3V X6S

20%

4.7UF

2

1

C8853

X6S

6.3V

20%

4.7UF

0402

2

1

C8854

6.3V

4.7UF

20%

X6S 0402

2

1

C8855

0402

X6S

4.7UF

6.3V

20%

2

1

R8800

1/20W

120

MF

1%

201

2

1

R8850

201

1%

MF

1/20W

120

J13

L12

P5

P4

D5

D4

U5

A5

J10

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

M2

M4

B2

N2

N4

T2

T4

U2

U4

M13

M11

N13

N11

B4

T13

T11

U13

U11

F13

F11

E13

E11

B13

B11

A2

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

H10

K11

K10

H11

J4

H5

K4

J5

K5

H4

U8850

OMIT_TABLE

GDDR5-128MX32-4GB-38NM-MFL

H5GC4H24MFR-T2C

BGA

2

1

R8804

201

5%

1K

1/20W MF

2

1

R8803

1/20W

1K

5% MF

201

2

1

R8854

1K

5%

MF

1/20W 201

2

1

R8853

201

1/20W MF

5%

1K

C14

C12

C11

C4

C3

C1

U14

U12

U3

U1

R14

R12

A14

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

A12

K13

K2

H13

H2

F10

F5

E14

E12

E3

E1

A3

A1

L5

K14

K1

H14

H1

G10

G5

D10

T10

T5

P10

L10

B10

B5

U10

A10

J14

E10

E5

D14

D12

D3

D1

T14

T12

T3

T1

P14

P12

B14

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

B12

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

B3

B1

L11

L4

L1

G14

G11

G4

G1

D11

R10

R5

P11

L14

C10

C5

U8800

BGA

H5GC4H24MFR-T2C

OMIT_TABLE

GDDR5-128MX32-4GB-38NM-MFL

J13

L12

P5

P4

D5

D4

U5

A5

J10

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

M2

M4

B2

N2

N4

T2

T4

U2

U4

M13

M11

N13

N11

B4

T13

T11

U13

U11

F13

F11

E13

E11

B13

B11

A2

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

H10

K11

K10

H11

J4

H5

K4

J5

K5

H4

U8800

GDDR5-128MX32-4GB-38NM-MFL

H5GC4H24MFR-T2C

OMIT_TABLE

BGA

72 97

2

1

C8826

0201

5% 25V

12PF

NP0-C0G

CRITICAL

2

1

C8827

0201

CRITICAL

25V NP0-C0G

+/-0.1PF

3.0PF

2

1

C8877

3.0PF

+/-0.1PF 25V

0201

NP0-C0G

CRITICAL

2

1

C8876

NP0-C0G

12PF

25V

5%

CRITICAL

0201

72 97

72 74 75

72 97

2

1

R8801

MF-LF

1/16W

402

60.4

1%

2

1

R8802

402

60.4

1% 1/16W MF-LF

2

1

C8806

0201

1.0UF

4V X6S

20%

2

1

C8807

4V

0201

X6S

20%

1.0UF

2

1

C8808

20%

1.0UF

0201

4V X6S

2

1

C8809

20%

0201

4V X6S

1.0UF

2

1

C8810

20%

0201

1.0UF

4V X6S

2

1

C8811

20%

1.0UF

0201

4V X6S

2

1

C8812

0201

4V X6S

20%

1.0UF

2

1

C8813

20%

0201

4V X6S

1.0UF

2

1

C8814

0201

20%

1.0UF

4V X6S

2

1

C8815

20% 4V X6S 0201

1.0UF

2

1

C8816

0.1UF

10%

6.3V X7R 0201

2

1

C8817

6.3V

0.1UF

10%

X7R 0201

2

1

C8818

6.3V

0.1UF

10%

X7R 0201

2

1

C8819

0.1UF

X7R 0201

6.3V

10%

2

1

C8820

6.3V

0.1UF

10%

X7R 0201

2

1

C8821

6.3V

10%

X7R

0.1UF

0201

2

1

C8822

6.3V

X7R

0.1UF

10%

0201

2

1

C8823

X7R

0.1UF

6.3V

10%

0201

2

1

C8824

6.3V

0.1UF

X7R 0201

10%

2

1

C8825

6.3V

10%

0.1UF

X7R 0201

2

1

C8830

X6S

4V

1.0UF

NOSTUFF

0201

20%

2

1

C8831

X6S

4V

0201

1.0UF

20%

2

1

R8830

1/20W MF 201

2.37K

1%

2

1

R8831

1/20W MF 201

5.49K

1%

2

1

C8832

X6S

4V

NOSTUFF

0201

1.0UF

20%

2

1

C8833

X6S

4V

0201

1.0UF

20%

NOSTUFF

2

1

R8832

NOSTUFF

MF

1/20W

201

2.37K

1%

2

1

R8833

NOSTUFF

MF

1/20W

201

5.49K

1%

2

1

C8834

X6S

4V

0201

NOSTUFF

1.0UF

20%

2

1

C8835

1.0UF

X6S 0201

20%

NOSTUFF

4V

2

1

R8834

NOSTUFF

MF

1/20W

201

2.37K

1%

2

1

R8835

NOSTUFF

MF

1/20W

201

5.49K

1%

72 97

2

1

R8852

60.4

MF-LF

1/16W

402

1%

2

1

R8851

402

60.4

MF-LF

1/16W

1%

72 97

72 74 75

72 97

C14

C12

C11

C4

C3

C1

U14

U12

U3

U1

R14

R12

A14

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

A12

K13

K2

H13

H2

F10

F5

E14

E12

E3

E1

A3

A1

L5

K14

K1

H14

H1

G10

G5

D10

T10

T5

P10

L10

B10

B5

U10

A10

J14

E10

E5

D14

D12

D3

D1

T14

T12

T3

T1

P14

P12

B14

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

B12

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

B3

B1

L11

L4

L1

G14

G11

G4

G1

D11

R10

R5

P11

L14

C10

C5

U8850

OMIT_TABLE

H5GC4H24MFR-T2C

BGA

GDDR5-128MX32-4GB-38NM-MFL

2

1

C8859

X6S

4V

0201

1.0UF

20%

2

1

C8863

X6S

4V

0201

1.0UF

20%

2

1

C8858

X6S

4V

0201

1.0UF

20%

2

1

C8862

X6S

4V

0201

1.0UF

20%

2

1

C8867

6.3V

0.1UF

10%

X7R 0201

2

1

C8866

6.3V

0.1UF

10%

X7R 0201

2

1

C8857

1.0UF

20%

0201

4V X6S

2

1

C8861

X6S

4V

0201

1.0UF

20%

2

1

C8856

20%

1.0UF

0201

4V X6S

2

1

C8860

X6S

4V

0201

1.0UF

20%

2

1

C8865

X6S

4V

0201

1.0UF

20%

2

1

C8864

X6S

4V

1.0UF

20%

0201

2

1

C8871

10%

X7R

6.3V

0.1UF

0201

2

1

C8875

6.3V

0.1UF

10%

X7R 0201

2

1

C8870

6.3V

0.1UF

10%

X7R 0201

2

1

C8874

6.3V

10%

X7R 0201

0.1UF

2

1

C8869

6.3V

0.1UF

10%

0201

X7R

2

1

C8873

0.1UF

X7R

10%

0201

6.3V

2

1

C8868

0.1UF

10%

X7R

6.3V

0201

2

1

C8872

6.3V

10%

X7R

0.1UF

0201

72 97

2

1

C8880

X6S

4V

NOSTUFF

1.0UF

20%

0201

2

1

R8880

1/20W

2.37K

1%

201

MF

2

1

C8881

X6S

4V

1.0UF

20%

0201

2

1

R8881

MF

1/20W

201

5.49K

1%

2

1

C8882

X6S

4V

NOSTUFF

0201

1.0UF

20%

2

1

R8882

NOSTUFF

MF

1/20W

201

2.37K

1%

2

1

C8883

20%

1.0UF

0201

X6S

4V

NOSTUFF

2

1

R8883

NOSTUFF

MF

1/20W

201

5.49K

1%

SYNC_MASTER=MARY_X425G

GDDR5 Frame Buffer A

SYNC_DATE=09/22/2014

GPU

PP1V35_GPU_REG

FB_A1_DQ<16> FB_A1_DQ<20> FB_A1_DQ<19>

FB_A1_VREFC

FB_A1_DQ<25>

FB_A1_DQ<28>

PP1V35_GPU_REG

FB_A0_VREFC

FB_A1_DQ<5>

FB_A1_VREFD2

PP1V35_GPU_REG

FB_A1_VREFD1

PP1V35_GPU_REG

FB_A0_CLK_P

FB_A1_DQ<18> FB_A1_DQ<22>

FB_A1_DQ<13>

PP1V35_GPU_REG

FB_A0_EDC<2>

FB_A0_EDC<3>

FB_A0_EDC<1>

FB_A0_EDC<0>

FB_A1_DQ<27>

FB_A1_ABI_L

FB_A1_MF

FB_A1_ZQ

FB_A1_CLK_N

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A1_EDC<1>

FB_A1_EDC<0>

FB_A1_SEN

FB_A1_DQ<0>

FB_A1_DQ<10>

FB_A1_DQ<12>

FB_A1_DQ<15>

FB_A1_DQ<31>

FB_A1_DQ<30>

FB_A1_DQ<24>

FB_A1_DQ<2>

FB_A1_DQ<4>

FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<3> FB_A1_DBI_L<2>

PP1V35_GPU_REG

FB_A0_VREFD2

PP1V35_GPU_REG PP1V35_GPU_REG

FB_A0_WCLK_N<0>

FB_A0_SEN

FB_A0_CAS_L

FB_A0_A<6>

FB_A0_A<5>

FB_A0_DQ<23>

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

FB_A0_DQ<22>

FB_A0_CKE_L

FB_A0_A<2>

FB_A0_DQ<0>

FB_A0_DQ<2>

FB_A0_A<3>

FB_A0_A<4>

FB_A0_A<1>

FB_A0_A<7>

FB_A0_CLK_N

FB_A0_ABI_L

FB_A0_CS_L

FB_A0_DQ<26> FB_A0_DQ<30>

FB_A0_DQ<28> FB_A0_DQ<27> FB_A0_DQ<31>

FB_A0_DQ<17> FB_A0_DQ<18>

FB_A0_RAS_L

FB_A0_DQ<16>

FB_A0_WCLK_P<0>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<4>

FB_A0_DBI_L<2>

FB_A0_DBI_L<0>

FB_A0_A<8>

FB_A0_DQ<7>

FB_A0_MF

FB_RESET_L

FB_A1_WCLK_N<0>

FB_A1_CAS_L

FB_A1_A<6>

FB_A1_A<5>

FB_A1_DQ<23>

FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>

FB_RESET_L

FB_A1_DQ<17>

FB_A1_CKE_L

FB_A1_A<2>

FB_A1_A<3>

FB_A1_A<4>

FB_A1_WE_L

FB_A1_A<1>

FB_A1_A<7>

FB_A1_CS_L

FB_A1_RAS_L

FB_A1_WCLK_P<0>

FB_A1_A<8>

PP1V35_GPU_REG

FB_A0_VREFD2

FB_A0_VREFD1

FB_A0_VREFC

FB_A0_DBI_L<1> FB_A0_DBI_L<3>

FB_A0_DQ<24>

FB_A0_DQ<14>

FB_A0_DQ<13>

FB_A0_DQ<12>

FB_A0_DQ<15>

FB_A0_DQ<29>

FB_A0_DQ<6>

FB_A0_DQ<3>

FB_A0_DQ<5>

FB_A0_A<0>

FB_A0_ZQ

FB_A0_DQ<11>

FB_A0_DQ<25>

FB_A1_CLK_P

FB_A1_DQ<8>

FB_A1_DQ<14>

FB_A1_A<0>

FB_A1_DQ<6> FB_A1_DQ<1> FB_A1_DQ<7>

FB_A1_DQ<3>

FB_A1_DQ<11>

FB_A1_DQ<21>

FB_A1_DQ<26>

FB_A1_DQ<29>

FB_A1_DQ<9>

FB_A0_WE_L

FB_A0_DQ<9>

FB_A0_DQ<10>

FB_A0_DQ<8>

FB_A0_DQ<1>

FB_A0_DQ<19>

FB_A0_VREFD1

FB_A1_VREFD2

FB_A1_VREFD1

FB_A1_VREFC

<SCH_NUM>

88 OF 119

74 OF 97

47 71 72 73 74 75 84

74

47 71 72 73

74 75

84

74

47 71 72 73 74 75

84

47 71 72 73 74 75

84

74

47 71 72 73 74 75 84

47 71 72 73 74 75

84

74

47 71 72 73 74 75

84

47 71 72 73 74 75 84 47 71 72 73 74 75

84

74

IN

BI

A12/A13

A10/A0

DBI0* DBI1* DBI2* DBI3*

DQ1

DQ0

VPP/NC

DQ30

DQ24

DQ31

WCK01

DQ14

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

CS*

CK

ABI*

CK*

A8/A7 A9/A1

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

DQ28

RESET*

WCK23*

WCK23

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

DQ8

VPP/NC

WCK01*

EDC2

EDC1

(MF=0)

SYM 1 OF 2

A12/A13

A10/A0

DBI0* DBI1* DBI2* DBI3*

DQ1

DQ0

VPP/NC

DQ30

DQ24

DQ31

WCK01

DQ14

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

CS*

CK

ABI*

CK*

A8/A7 A9/A1

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

DQ28

RESET*

WCK23*

WCK23

DQ29

BA1/A5

A11/A6

CAS*

SEN

MF

ZQ

DQ8

VPP/NC

WCK01*

EDC2

EDC1

(MF=0)

SYM 1 OF 2

OUT OUT OUT OUT

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

SYM 2 OF 2

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

NC

BI BI BI BI

IN IN IN IN

IN

IN IN

IN IN IN IN

IN

IN IN

IN

IN IN

VDD

VDDQ

VREFC

VREFD

VSS

VSSQ

SYM 2 OF 2

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

IN IN

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page:

BOM options provided by this page:

(NONE)

Page Notes

(NONE)

2

1

C8984

X6S

4V

NOSTUFF

0201

1.0UF

20%

2

1

R8984

NOSTUFF

MF

1/20W

201

2.37K

1%

2

1

C8985

X6S

4V

NOSTUFF

0201

1.0UF

20%

2

1

R8985

NOSTUFF

MF

1/20W

201

5.49K

1%

72 97

2

1

C8933

20%

NOSTUFF

1.0UF

0201

4V X6S

2

1

C8907

X6S

4V

0201

1.0UF

20%

2

1

C8906

4V

1.0UF

20%

0201

X6S

2

1

C8900

0402

20%

X6S

6.3V

4.7UF

2

1

C8901

0402

X6S

4.7UF

6.3V

20%

2

1

C8902

0402

20%

X6S

6.3V

4.7UF

2

1

C8905

0402

20%

6.3V X6S

4.7UF

2

1

C8904

0402

4.7UF

X6S

6.3V

20%

2

1

C8903

0402

4.7UF

X6S

6.3V

20%

2

1

C8950

X6S

6.3V

4.7UF

20%

0402

2

1

C8951

20%

6.3V

4.7UF

X6S 0402

2

1

C8952

20%

6.3V

4.7UF

X6S 0402

2

1

C8953

6.3V X6S

4.7UF

20%

0402

2

1

C8954

20%

X6S 0402

6.3V

4.7UF

2

1

C8955

6.3V

4.7UF

20%

0402

X6S

2

1

R8950

MF

1%

120

1/20W

201

2

1

R8904

1/20W MF

5%

1K

201

2

1

R8903

201

1/20W MF

5%

1K

2

1

R8953

MF

1K

5%

201

1/20W

2

1

R8954

1K

5%

MF

1/20W 201

J13

L12

P5

P4

D5

D4

U5

A5

J10

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

M2

M4

B2

N2

N4

T2

T4

U2

U4

M13

M11

N13

N11

B4

T13

T11

U13

U11

F13

F11

E13

E11

B13

B11

A2

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

H10

K11

K10

H11

J4

H5

K4

J5

K5

H4

U8900

GDDR5-128MX32-4GB-38NM-MFL

H5GC4H24MFR-T2C

OMIT_TABLE

BGA

J13

L12

P5

P4

D5

D4

U5

A5

J10

J2

G3

J1

R2

R13

C13

C2

A13

A11

F2

F4

E2

E4

M2

M4

B2

N2

N4

T2

T4

U2

U4

M13

M11

N13

N11

B4

T13

T11

U13

U11

F13

F11

E13

E11

B13

B11

A2

A4

P2

P13

D13

D2

G12

J3

J11

J12

L3

H10

K11

K10

H11

J4

H5

K4

J5

K5

H4

U8950

GDDR5-128MX32-4GB-38NM-MFL

H5GC4H24MFR-T2C

OMIT_TABLE

BGA

72 97

2

1

C8926

0201

5% 25V

12PF

NP0-C0G

CRITICAL

2

1

C8927

0201

25V NP0-C0G

+/-0.1PF

3.0PF

CRITICAL

2

1

C8976

0201

5% 25V

NP0-C0G

CRITICAL

12PF

2

1

C8977

0201

25V NP0-C0G

+/-0.1PF

3.0PF

CRITICAL

C14

C12

C11

C4

C3

C1

U14

U12

U3

U1

R14

R12

A14

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

A12

K13

K2

H13

H2

F10

F5

E14

E12

E3

E1

A3

A1

L5

K14

K1

H14

H1

G10

G5

D10

T10

T5

P10

L10

B10

B5

U10

A10

J14

E10

E5

D14

D12

D3

D1

T14

T12

T3

T1

P14

P12

B14

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

B12

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

B3

B1

L11

L4

L1

G14

G11

G4

G1

D11

R10

R5

P11

L14

C10

C5

U8900

OMIT_TABLE

GDDR5-128MX32-4GB-38NM-MFL

BGA

H5GC4H24MFR-T2C

72 97

72 74 75

2

1

R8900

201

120

MF

1/20W

1%

72 97

2

1

R8901

402

60.4

MF-LF

1/16W

1%

2

1

R8902

1/16W

60.4

MF-LF 402

1%

2

1

C8908

X6S

4V

0201

1.0UF

20%

2

1

C8909

X6S

4V

0201

1.0UF

20%

2

1

C8910

X6S

4V

0201

1.0UF

20%

2

1

C8911

X6S

4V

0201

1.0UF

20%

2

1

C8912

X6S

4V

0201

1.0UF

20%

2

1

C8913

1.0UF

X6S

4V

0201

20%

2

1

C8914

X6S

4V

0201

20%

1.0UF

2

1

C8915

X6S

4V

0201

1.0UF

20%

2

1

C8916

0.1UF

10%

X7R

6.3V

0201

2

1

C8917

0.1UF

X7R

6.3V

10%

0201

2

1

C8918

6.3V

10%

X7R

0.1UF

0201

2

1

C8919

0.1UF

10%

6.3V

0201

X7R

2

1

C8920

0.1UF

X7R

6.3V

10%

0201

2

1

C8921

6.3V

10%

X7R

0.1UF

0201

2

1

C8922

0.1UF

X7R

6.3V

10%

0201

2

1

C8923

6.3V

10%

X7R

0.1UF

0201

2

1

C8924

10%

X7R

6.3V

0201

0.1UF

2

1

C8925

10%

0.1UF

X7R

6.3V

0201

2

1

C8930

20%

NOSTUFF

1.0UF

0201

4V X6S

2

1

C8931

20%

0201

4V X6S

1.0UF

2

1

R8930

MF

1/20W

201

2.37K

1%

2

1

R8931

MF 201

5.49K

1% 1/20W

2

1

C8932

0201

1.0UF

20% 4V

NOSTUFF

X6S

2

1

R8932

2.37K

NOSTUFF

MF

1/20W

201

1%

2

1

R8933

NOSTUFF

MF

1/20W

201

1%

5.49K

2

1

C8934

20%

0201

NOSTUFF

1.0UF

4V X6S

2

1

C8935

20%

1.0UF

0201

NOSTUFF

4V X6S

2

1

R8934

NOSTUFF

MF

1/20W

201

2.37K

1%

2

1

R8935

NOSTUFF

MF

1/20W

201

5.49K

1%

72 97

2

1

R8952

402

60.4

MF-LF

1/16W

1%

2

1

R8951

60.4

MF-LF

1/16W

402

1%

72 97

72 74 75

72 97

C14

C12

C11

C4

C3

C1

U14

U12

U3

U1

R14

R12

A14

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

A12

K13

K2

H13

H2

F10

F5

E14

E12

E3

E1

A3

A1

L5

K14

K1

H14

H1

G10

G5

D10

T10

T5

P10

L10

B10

B5

U10

A10

J14

E10

E5

D14

D12

D3

D1

T14

T12

T3

T1

P14

P12

B14

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

B12

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

B3

B1

L11

L4

L1

G14

G11

G4

G1

D11

R10

R5

P11

L14

C10

C5

U8950

GDDR5-128MX32-4GB-38NM-MFL

BGA

H5GC4H24MFR-T2C

OMIT_TABLE

2

1

C8959

20%

1.0UF

0201

4V X6S

2

1

C8963

20%

1.0UF

0201

4V X6S

2

1

C8958

20%

1.0UF

0201

4V X6S

2

1

C8962

20%

1.0UF

0201

4V X6S

2

1

C8967

0.1UF

10%

X7R

6.3V

0201

2

1

C8966

6.3V

0.1UF

10%

X7R 0201

2

1

C8957

20%

0201

4V X6S

1.0UF

2

1

C8961

20%

1.0UF

0201

4V X6S

2

1

C8956

20%

1.0UF

0201

4V X6S

2

1

C8960

20%

1.0UF

0201

4V X6S

2

1

C8965

1.0UF

0201

X6S

20% 4V

2

1

C8964

20%

1.0UF

0201

4V X6S

2

1

C8971

10%

X7R

6.3V

0.1UF

0201

2

1

C8975

6.3V

10%

X7R

0.1UF

0201

2

1

C8970

6.3V

0.1UF

10%

X7R 0201

2

1

C8974

6.3V

0.1UF

X7R

10%

0201

2

1

C8969

10%

0.1UF

X7R

6.3V

0201

2

1

C8973

X7R

6.3V

10%

0.1UF

0201

2

1

C8968

6.3V X7R

0.1UF

10%

0201

2

1

C8972

6.3V X7R

0.1UF

10%

0201

72 97

2

1

C8980

X6S

4V

0201

1.0UF

NOSTUFF

20%

2

1

R8980

2.37K

MF

1/20W

201

1%

2

1

C8981

X6S

4V

0201

1.0UF

20%

2

1

R8981

MF

1/20W

201

5.49K

1%

2

1

C8982

X6S

4V

0201

1.0UF

NOSTUFF

20%

2

1

R8982

201

NOSTUFF

MF

1/20W

2.37K

1%

2

1

C8983

X6S

4V

0201

1.0UF

20%

2

1

R8983

NOSTUFF

MF

1/20W

201

5.49K

1%

SYNC_MASTER=MARY_X425G

GDDR5 Frame Buffer B

SYNC_DATE=09/22/2014

GPU

PP1V35_GPU_REG

FB_B1_DQ<22>

FB_B1_DQ<31>

FB_B1_DQ<20>

PP1V35_GPU_REG

FB_B0_DQ<29>

FB_B0_DQ<31>

FB_B0_A<2> FB_B0_A<5>

FB_B0_A<0>

FB_B1_DBI_L<2>

FB_B1_DQ<1>

FB_B1_DQ<15> FB_B1_DQ<12>

FB_B1_DQ<5>

FB_B1_DQ<10> FB_B1_DQ<9>

FB_B1_DQ<7>

FB_B1_DBI_L<0>

FB_B0_DBI_L<2>

FB_B0_DQ<13> FB_B0_DQ<15>

FB_B0_DQ<0>

FB_B0_CLK_P

FB_B0_A<6>

FB_B0_DQ<12>

FB_B0_DQ<18> FB_B0_DQ<22> FB_B0_DQ<20> FB_B0_DQ<16> FB_B0_DQ<17> FB_B0_DQ<19>

FB_B0_DQ<21>

FB_B0_DQ<30>

FB_B0_DQ<7> FB_B0_DQ<2> FB_B0_DQ<3>

FB_B0_DQ<23>

FB_B0_DQ<6>

FB_B0_DQ<5>

FB_B1_DQ<2>

FB_B1_DQ<30>

FB_B1_DQ<8>

FB_B1_CLK_P

FB_B1_A<5> FB_B1_A<4>

FB_B1_DQ<27>

FB_B1_DQ<26>

FB_B1_DQ<29>

FB_B1_DQ<3> FB_B1_DQ<4>

FB_B1_SEN

FB_B1_CS_L

FB_B1_CLK_N

FB_B1_WE_L FB_B1_CAS_L FB_B1_RAS_L

FB_B0_A<4>

FB_B1_DQ<28>

FB_B1_DQ<24>

FB_B0_A<8>

FB_B0_DBI_L<1> FB_B0_DBI_L<0>

FB_B0_DBI_L<3>

FB_B0_DQ<9>

FB_B0_DQ<8>

FB_B0_DQ<28> FB_B0_DQ<25>

FB_B0_WCLK_P<0>

FB_B0_DQ<26>

FB_B0_DQ<10>

FB_B0_CS_L

FB_B0_ABI_L

FB_B0_A<7> FB_B0_A<1>

FB_B0_WE_L

FB_B0_A<3>

FB_B0_DQ<4>

FB_B0_DQ<1>

FB_B0_DQ<14>

FB_B0_DQ<11>

FB_B0_CKE_L

FB_B0_DQ<27>

FB_RESET_L

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<1>

FB_B0_DQ<24>

FB_B0_CAS_L

FB_B0_WCLK_N<0>

FB_B1_DQ<19>

FB_B1_DQ<17> FB_B1_DQ<16>

FB_B1_A<0>

FB_B1_DBI_L<1> FB_B1_DBI_L<3>

FB_B1_DQ<23>

FB_B1_WCLK_P<0>

FB_B1_DQ<21>

FB_B1_DQ<14>

FB_B1_DQ<25>

FB_B1_DQ<6>

FB_B1_ABI_L

FB_B1_DQ<0>

FB_B1_CKE_L

FB_RESET_L

FB_B1_WCLK_N<1>

FB_B1_WCLK_P<1>

FB_B1_DQ<18>

PP1V35_GPU_REG

FB_B0_VREFC

PP1V35_GPU_REG PP1V35_GPU_REG

PP1V35_GPU_REG

FB_B1_VREFD2

FB_B0_VREFD1

FB_B0_VREFD2

FB_B1_A<6>

FB_B1_A<2>

FB_B1_A<7>

FB_B0_VREFD2

FB_B0_VREFD1

FB_B0_VREFC

FB_B1_ZQ FB_B1_MF

FB_B0_CLK_N

FB_B1_A<3>

FB_B1_EDC<1> FB_B1_EDC<3> FB_B1_EDC<2>

FB_B0_EDC<1> FB_B0_EDC<0> FB_B0_EDC<2> FB_B0_EDC<3>

FB_B0_SEN

FB_B0_MF

FB_B0_ZQ

FB_B0_RAS_L

FB_B1_DQ<13>

FB_B1_A<1>

FB_B1_DQ<11>

FB_B1_EDC<0>

FB_B1_WCLK_N<0>

FB_B1_VREFD2

FB_B1_VREFD1

FB_B1_VREFC

FB_B1_A<8>

FB_B1_VREFD1

<SCH_NUM>

89 OF 119

75 OF 97

47 71 72 73 74 75 84 47 71 72 73

74 75

84

47 71 72 73 74 75

84

47 71 72 73 74 75

84

47 71 72 73 74 75 84

47 71 72 73 74 75

84

75

47 71 72 73 74 75

84

47 71 72 73 74 75 84

47 71 72 73 74 75

84

75

NC

NC NC

OUT

NC NC

IN

OUT

NC NC

NC

OUT OUT

NC

BI

OUT

NC

VARY_BL

TXOUT_U3N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_L3P TXOUT_L3N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

DIGON

TXOUT_U3P

TXOUT_U2N_DPF0N

TXOUT_U2P_DPF0P

(3 OF 9)

(2 OF 9)

GENLK_VSYNC

GENLK_CLK

CEC_1

CLKREQ*

NC_TSVSSQ

NC_XTAL_PVSS NC_XTAL_PVDD

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCVGACLK

DDCVGADATA

DDCCLK_AUX6P

DDCDATA_AUX6N

TSVSS

XO_IN2

DMINUS

TS_A

SWAPLOCKB

DVPDATA_22

DVPDATA_21

DVPDATA_19

DVPDATA_18

DVPDATA_16

DVPDATA_15

DVPDATA_14

XTALOUT

XTALIN

XO_IN

VSYNC

VSS1DI

VREFG

VDD1DI

TXCDP_DPD3P TXCDM_DPD3N

TXCCP_DPC3P TXCCM_DPC3N

TXCBP_DPB3P TXCBM_DPB3N

TXCAP_DPA3P TXCAM_DPA3N

TX5P_DPD0P

TX5P_DPB0P

TX5M_DPD0N

TX5M_DPB0N

TX4P_DPD1P

TX4P_DPB1P

TX4M_DPD1N

TX4M_DPB1N

TX3P_DPB2P

TX3M_DPD2N

TX3M_DPB2N

TX2P_DPC0P

TX2P_DPA0P

TX2M_DPC0N

TX2M_DPA0N

TX1P_DPC1P

TX1P_DPA1P

TX1M_DPC1N

TX1M_DPA1N

TX0P_DPC2P

TX0P_DPA2P TX0M_DPA2N

TSVDD

SWAPLOCKA

SCL

RSET

R

JTAG_TRST* JTAG_TDI

HSYNC

HPD1

GPIO_30

GPIO_29

GPIO_28_FDO

GPIO_22_ROMCS*

GPIO_21

GPIO_20_PWRCNTL_1

GPIO_19_CTF

GPIO_18_HPD3

GPIO_17_THERMAL_INT

GPIO_16

GPIO_15_PWRCNTL_0

GPIO_14_HPD2

GPIO_13

GPIO_12

GPIO_11

GPIO_10_ROMSCK

GPIO_9_ROMSI

GPIO_8_ROMSO

GPIO_7_BLON

GPIO_6

GENERICG_HPD6

GENERICF_HPD5

GENERICE_HPD4

GENERICD

GENERICC

GENERICB

GENERICA

DVPDATA_23

DVPDATA_20

DVPDATA_17

DVPDATA_13

DVPDATA_12

DVPDATA_11

DVPDATA_10

DVPDATA_9

DVPDATA_8

DVPDATA_6

DVPDATA_2

DVPDATA_1

DVPDATA_0

DVPCNTL_MVP_1

DVPCNTL_MVP_0

DVPCNTL_2

DVPCNTL_1

DVPCNTL_0

DVPCLK

DPLUS

B

AVSSQ

AVSSN2

AVSSN1

AVSSN0

AVDD

GPIO_5_AC_BATT

SMBCLK

SDA

GPIO_0 GPIO_1 GPIO_2

JTAG_TDO

JTAG_TMS

JTAG_TCK

TX3P_DPD2P

TX0M_DPC2N

G

SMBDATA

DVPDATA_7

DVPDATA_5

DVPDATA_4

DVPDATA_3

OUT

BI

BI BI

OUT

BI

BI BI

NC

NC NC

OUT OUT

NC

NC NC

NC

NC NC

NC

BI BI

NC

OUT

BI

G

VER 5

S D

G

VER 5

S D

G

VER 5

SD

G

VER 5

SD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMBUS "0"

8mA

(GND_GPU_TSVSS)

Page Notes

- =PP1V0_GPU_TS

- =PP1V0_GPU_DPLL

- =PP1V8_GPU_VREFG

Signal aliases required by this page:

BOM options provided by this page:

Power aliases required by this page:

- =PP3V3_GPU_I2C

(NONE)

- =PP1V8_GPU_DPLL

Straps for audio on DP and HDMI

DDC 3.3V level isolation

GPU Int Temp Sense can not be read through SMBUS

77 82

48 96

21

XW9001

SM

2

1

C9008

0201

4V X6S

1.0UF

20%

PLACE_NEAR=U8400.AJ32:2.54MM

2

1

C9009

0201

6.3V

0.1UF

10%

PLACE_NEAR=U8400.AJ32:2.54MM

X7R

2

1

C9000

6.3V

0201

PLACE_NEAR=U8400.AH13:2.54MM

10%

0.1UF

X7R

2

1

R9005

5%

201

MF

10K

1/20W

2

1

R9004

5%

MF

1/20W

201

10K

28 89 97

81

2

1

R9025

1/20W

1%

4.7K

201

MF

2

1

R9026

201

1/20W MF

1%

4.7K

2

1

R9002

PLACE_NEAR=U8400.AH13:2.54MM

1%

1/20W

MF

201

499

2

1

R9003

201

MF

1/20W

249

1%

PLACE_NEAR=U8400.AH13:2.54MM

2

1

C9007

20%

10UF

6.3V

0402

CERM-X6S

2

1

R9035

5% 1/20W

201

MF

10K

2

1

C9015

0201

6.3V

0.1UF

10%

PLACE_NEAR=L9002.1:2.54MM

X7R

AK27

AF35 AG36

AG38 AH37

AH35 AJ36

AJ38 AK37

AN36 AP37

AP35 AR35

AR37 AU39

AW37 AU35

AK35 AL36

AP34 AR34

AJ27

U8400

VENUS-XT

FCBGA

OMIT_TABLE

21

R9050

1%

201

1/20W

499

MF

31

42

Y9000

27MHZ-30PPM-12PF-40OHM

2.50X2.00MM-SM

CRITICAL

2

1

C9081

5% C0G

50V

15PF

0201

2

1

C9080

5%

C0G

50V

15PF

0201

21

R9082

201

1M

MF

1/20W

5%

AU34

AV33

AW35

AW34

AC38

AC34

AH13

AC33

AU20 AT19

AU14 AV13

AR30 AT29

AU24 AV23

AT23

AT33

AR22

AU32

AU22

AR32

AV21

AT31

AT21

AV31

AR20

AU30

AT17

AT27

AR16

AR26

AU16

AU26

AV15

AV25

AT15

AT25

AR14

AR24

AJ33

AJ32

AL31

AK21

AJ21

AH23

AJ23

AJ26

AK26

AB34

AD39

AF31 AF30

AF33

AM23

AL24 AM24

AN23 AK23

AC36

AK24

AH15

AJ13

AK17

AJ17

AH17

AG33

AG32

AK32

AK13

AJ14

AL13

AN16

AM17

AN14

AG30

AK14

AM13

AM14

AM16

AL16

AK16

AJ16

AH18

AH20

AC29

AD29

AH24

AH26

AJ24

AK20

AJ20

AK19

AJ19

AE36

AT7

AU6

AW6

AR6

AU5

AW5

AP6

AP12

AU12

AW12

AR12

AW3

AT11

AV11

AP10

AU10

AW10

AR10

AT9

AV9

AN7

AV7

AU3

AU1

AU8

AR8

AR3

AW8

AP8

AR1

AF29 AG29

AJ31

AJ30

AK29

AM21

AM29

AM30

AK30

AN21

AL29

AL30

AL19

AM19

AN26

AM26

AN13

AC30

AF37

AE34

AD37

AD35

AE38

AD34

AN20 AM20

AM27 AL27

U8400

OMIT_TABLE

FCBGA

VENUS-XT

21

L9002

0402

CRITICAL

120OHM-25%-1.8A-0.06DCR

77 83

77 83 97

77 83

77 83 97

2

1

R9023

5%

1K

201

MF

1/20W

NOSTUFF

2

1

R9024

5%

NOSTUFF

1K

1/20W MF 201

2

1

R9021

5% 1/20W MF 201

4.7K

2

1

R9020

5%

201

1/20W

MF

4.7K

82 97

2

1

R9006

5%

201

10K

1/20W MF

81 86 97

28 89 97

77 82 97

36 40 43 48 69 85 86 95

4

5

3

Q9000

CRITICAL

DMN5L06VK-7

SOT563

1

2

6

Q9000

SOT563

DMN5L06VK-7

CRITICAL

1

2

6

Q9010

DMN5L06VK-7

SOT563

CRITICAL

4

5

3

Q9010

CRITICAL

SOT563

DMN5L06VK-7

SYNC_MASTER=MARY_X425G

Venus HDMI/DP/GPIO

SYNC_DATE=09/22/2014

GPU_SMB_DAT

PP3V3_S0GPU

SMBUS_SMC_0_S0_SDA

GPU_SMB_CLK

SMBUS_SMC_0_S0_SCL

HDMI_EG_DATA_N<2>

GPU_VCORE_VID4

GPU_VCORE_VID2

HDMI_EG_HPD

FBVDD_ALTVO

DP_TBTSNK1_HPD_EG GPU_VCORE_VID1

PP3V3_S0GPU

HDMI_EG_DDC_DATA_Q

HDMI_EG_DDC_DATA

HDMI_EG_DDC_CLK_Q

HDMI_EG_DDC_CLK

GPU_GFX_PWR_LEVEL_R_L GFXIMVP_VR_ICCMAX_WARN_L

NC_GPU_GPIO_2

DP_TBTSNK0_EG_AUXCH_N

DPB_EG_DDC_CLK

TP_CLKREQ_L

DP_TBTSNK1_EG_AUXCH_N

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

DPB_EG_DDC_DATA

TP_DVPDATA<1>

TP_DVPDATA<5>

DP_TBTSNK0_ML_C_N<3>

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>

HDMI_EG_DATA_P<2>

HDMI_EG_DATA_N<1>

HDMI_EG_DATA_P<0>

DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>

HDMI_EG_CLK_P HDMI_EG_CLK_N

EG_LCD_PWR_EN

GPU_LCD_BLK_PWM

TP_DVPDATA<0>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<3>

GFX_VDDCI_ALTV

NC_DVPDATA<14>

PP3V3_S0GPU

NC_DVPDATA<19>

DP_TBTSNK0_ML_C_P<2>

NC_DP_EXTA_CA_DET_EG NC_GPU_GPIO_33 DP_INT_EG_HPD

DP_TBTSNK0_HPD_EG

TP_DVPDATA<2> TP_DVPDATA<3> TP_DVPDATA<4>

NC_DVPDATA<16>

NC_DVPDATA<18>

NC_DVPDATA<20>

NC_DVPDATA<22>

NC_DVPCNTL_M<0> NC_DVPCNTL_M<1>

NC_DVPCLK

NC_DVPCNTL<0> NC_DVPCNTL<1>

NC_DVPDATA<8>

NC_DVPDATA<23>

GFXIMVP_DPSLP_EN_R

PD_GPU_CLK27M

NC_GPU_GENERICB

GPU_VCORE_PSI_L

PP1V8_GPUIFPX

NC_GPU_GPIO_35

NC_DP_EXTB_CA_DET_EG

GPU_JTAG_TCK

GPU_VCORE_VID3

GPU_VCORE_VID0

GPU_VCORE_VID5

NC_GPU_GENERICA

NC_DVPDATA<21>

NC_DVPDATA<10> NC_DVPDATA<11>

GPU_ROM_SCLK

GPU_JTAG_TRST_L GPU_JTAG_TDI

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<1>

GPU_TDIODE_P

PP1V8_GPUIFPX

NC_DVPDATA<15>

GPU_RSET

NC_DVPDATA<13>

NC_DVPDATA<12>

NC_DVPDATA<9>

NC_DVPDATA<7>

NC_DVPDATA<6>

GPU_ROM_SI

GPU_ROM_CS_L

NC_DVPDATA<17>

GPU_AUD_1 GPU_AUD_0

GPU_MLPS_EN_L

NC_GPU_GPIO_1

PD_GPU_CLK100M

GPU_TDIODE_N

GPU_JTAG_TMS GPU_JTAG_TDO

GFX_SELF_THROTTLE_R

PP1V8_GPUIFPX

GPU_ROM_SO

EG_BKLT_EN

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DPA_EG_DDC_CLK

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK0_EG_AUXCH_P

DPA_EG_DDC_DATA

NC_DVPCNTL<2>

HDMI_EG_DATA_P<1>

HDMI_EG_DATA_N<0>

GPU_GFX_OVERTEMP_R

GPU_VREFG

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

GND_GPU_TSVSS

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_GPU_TSVDD

GPU_27M_XTAL_OUT

GPU_27M_XTAL_IN

<SCH_NUM>

90 OF 119

76 OF 97

47 66 68 71 72 76 77 79 80 84

77 79

77 82

73 77

77 82

77 79

47 66 68 71 72 76 77 79 80 84

77

77 79

77

77 80

87

47 66 68 71 72 76 77 79 80 84

87

77

77 82

87

77 79

77

71 76 78 80 84

77

77 86

77 79

77

87

77

77 86

71 76 78 80

84

87

77

87

77

77 86

77

71 76 78 80 84

77

77 82

87

77

IN

BI

OUT

HOLD*

S*

D

C

Q

THRM

W*

VCC

PAD

VSS

OUT

IN

OUT

BI BI

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PU on VR page)

(PD on GMUX page)

(GPIO17)

(GPIO5)

GP

GPIOs

GP

Native Func

GP

Native Func

GP

PU on U5760 and VR page

GPUCORE_VR_ICCMAX_WARN_L logic low if GPUCORE VR ICCMAX above 61A logic high if GPUCORE VR ICCMAX not more than 61A

(PD on GUMX page)

GPIOs

GP

GPU GPIO PU/PD

GPU GPIO TABLE

GPU ROM

JTAG signals

AMD AUX PD

DDC PULL UP

76 83

21

R9199

MF-LF

402

1/16W

0

5%

76 82

76 77 82

73 76 77

2

1

R9192

201

10K

1/20W

5%

MF

2

1

R9193

1/20W

10K

5%

201

MF

2

1

R9194

MF

1/20W

201

5%

10K

2

1

R9150

NOSTUFF

PLACE_NEAR=U8400.AM26:2.54MM

MF-LF

1/16W

5%

402

470K

2

1

R9151

NOSTUFF

5%

PLACE_NEAR=U8400.AN26:2.54MM

MF-LF

1/16W

402

470K

3

489

1

2

7

5

6

U9101

CRITICAL

OMIT_TABLE

UFDFPN8

M25P10A

21

R9126

GPU_ROM:YES

33

5%

MF

1/20W

201

21

R9123

GPU_ROM:YES

33

5%

MF

1/20W

201

21

R9124

GPU_ROM:YES

33

5%

MF

1/20W

201

21

R9125

33

5%

1/20W

GPU_ROM:YES

MF

201

2

1

C9121

0201

10%

GPU_ROM:YES

0.1UF

6.3V X7R

2

1

R9121

GPU_ROM:YES

201

5%

1/20W

MF

10K

2

1

R9122

100K

5% 1/20W

201

MF

NO STUFF

2

1

R9120

201

1/20W

5%

10K

MF

GPU_ROM:YES

2

1

R9155

5%

PLACE_NEAR=U8400.AL19:2.54MM

NOSTUFF

402

1/16W MF-LF

470K

2

1

R9154

PLACE_NEAR=U8400.AM19:2.54MM

402

1/16W MF-LF

5%

NOSTUFF

470K

82

21

R9158

0

5%

1/20W

MF

201

2

1

R9198

5%

10K

1/20W

201

MF

2

1

R9160

10K

5%

1/20W

MF

201

2

1

R9161

10K

MF

1/20W

5%

201

NOSTUFF

2

1

R9162

MF

1/20W

5%

201

10K

2

1

R9163

201

5%

1/20W

MF

10K

2

1

R9164

201

5%

1/20W

MF

10K

82

21

R9181

5%

1/16W MF-LF

402

0

79

21

R9182

402

MF-LF1/16W

5%

0

82

2

1

R9172

MF

100K

PLACE_NEAR=U8400.AL27:2.54MM

201

NOSTUFF

1/20W

5%

76 83 97

2

1

R9173

PLACE_NEAR=U8400.AM27:2.54MM

100K

5%

MF

201

1/20W

NOSTUFF

2

1

R9171

1/20W

MF

5%

201

100K

NOSTUFF

PLACE_NEAR=U8400.AN20:2.54MM

76 83 97

76 77 79

2

1

R9197

MF

201

1/20W

5%

10K

21

R9128

1/20W

0

201

MF

5%

47

2

1

R9170

1/20W

5%

MF

100K

201

NOSTUFF

PLACE_NEAR=U8400.AM20:2.54MM

2

1

R9174

201

5% MF

1/20W

100K

NOSTUFF

PLACE_NEAR=U8400.AK30:2.54MM

2

1

R9175

PLACE_NEAR=U8400.AK29:2.54MM

201

5% MF

1/20W

100K

NOSTUFF

76 82 97

SYNC_DATE=11/07/2014

GPU

SYNC_MASTER=MARY_X425G

Venus GPIOs & STRAPs

DP_TBTSNK1_HPD_EG

DP_INT_EG_AUX_N

GPU_ROM_SO

MAKE_BASE=TRUE

NC_GPU_GENERICB

NO_TEST=TRUE

GPU_VCORE_VID1

GPU_VCORE_VID2

HDMI_EG_HPD

GPU_VCORE_VID3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_EXTA_CA_DET_EG

DP_INT_EG_HPD

MAKE_BASE=TRUE

GPU_VCORE_VID3

NO_TEST=TRUE

NC_GPU_GENERICA

MAKE_BASE=TRUE

TP_CLKREQ_L

GFXIMVP_VR_ICCMAX_WARN_L

GPU_JTAG_TCK

PP3V3_S0GPU

GPU_JTAG_TRST_L

GPU_JTAG_TMS

GPU_JTAG_TDO

GPU_JTAG_TDI

GPU_VCORE_VID4

MAKE_BASE=TRUE

DP_INT_EG_AUX_P

DP_TBTSNK0_EG_AUXCH_N DP_TBTSNK0_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_N

DPA_EG_DDC_CLK

DPA_EG_DDC_DATA

DPB_EG_DDC_CLK

DPB_EG_DDC_DATA

PP3V3_S0GPU

GPU_GFX_PWR_LEVEL_R_L

MAKE_BASE=TRUE

GFXIMVP_VR_ICCMAX_WARN_L

GPU_VCORE_VID4

GPU_VCORE_VID0

GPU_ROM_SCLK

MAKE_BASE=TRUE

GPU_ROM_SCLK

MAKE_BASE=TRUE

GPU_VCORE_VID0

GPU_GFX_PWR_LEVEL_R_L

GPU_GFX_OVERTEMP_R

GPU_GFX_PWR_LEVEL_L

GPU_GFX_OVERTEMP

GFXIMVP_VR_ICCMAX_WARN_L

GFXIMVP_PSI_L

GFX_SELF_THROTTLE

EG_LCD_PWR_EN

EG_BKLT_EN

GPUCORE_VR_ICCWARN_BUF_L

GFXIMVP_VR_ICCMAX_WARN_L

MAKE_BASE=TRUE

PP3V3_S0GPU

FBVDD_ALTVO

MAKE_BASE=TRUE

GFX_VDDCI_ALTV

GPU_VCORE_PSI_L

GFX_SELF_THROTTLE_R

GFX_VDDCI_ALTV

GPU_ROM_SI

NC_GPU_GPIO_2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_EXTB_CA_DET_EG

NC_GPU_GPIO_35

GPU_VCORE_VID5

GPU_ROM_SI_R

PP3V3_S0GPU

NC_GPU_GPIO_1

DP_TBTSNK1_HPD_EG

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

GFX_SELF_THROTTLE_R

MAKE_BASE=TRUE

HDMI_EG_HPD

MAKE_BASE=TRUE

GPU_GFX_OVERTEMP_R

NC_GPU_GPIO_33

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_35

MAKE_BASE=TRUE

NO_TEST=TRUE

EG_BKLT_EN

GFXIMVP_DPSLP_EN_R

NC_GPU_GPIO_2

GPU_ROM_SCLK

GPU_ROM_CS_L

NC_GPU_GPIO_33

GPU_ROM_SI

MAKE_BASE=TRUE

FBVDD_ALTVO

GPU_VCORE_PSI_L

MAKE_BASE=TRUE

GPU_ROM_SCLK_R

TP_CLKREQ_L

GPU_ROM_SO

GPU_ROM_SO_R

GFX_SELF_THROTTLE_R

DP_INT_EG_HPD

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_EG

NC_DP_EXTA_CA_DET_EG

GPU_ROM_CS_L

NC_GPU_GENERICA

GPU_GFX_OVERTEMP_R

MAKE_BASE=TRUE

GPU_VCORE_VID5

FBVDD_ALTVO

MAKE_BASE=TRUE

NC_GPU_GPIO_1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_EXTB_CA_DET_EG

GFXIMVP_DPSLP_EN_R

MAKE_BASE=TRUE

HDMI_EG_HPD

GPU_ROM_SI

DP_TBTSNK0_HPD_EG

GPU_ROM_CS_L

MAKE_BASE=TRUE

GPU_VCORE_PSI_L

NC_GPU_GENERICB

GPU_ROM_SO

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

GPU_ROM_WP_L

GPU_ROM_CS_L_R

<SCH_NUM>

91 OF 119

77 OF 97

76 77 82

76 77

76 77 79

76 77 82

76 77 79

76 77

76 77 82

76 77 79

76 77

76 77 79

76 86

47 66 68 71 72 76 77 79 80 84

76 86

76 77 79

47 66 68 71 72 76 77 79 80 84

76 77

76 77 79

76 77 76 77

76 77 79

76 77

76 77 79

47 66 68 71 72 76 77 79 80 84

76 77 80

76 77

76 77 80

76 77

76 77 79

47 66 68 71 72 76 77 79 80 84

76 77

76 77 82

76 77 79

76 77

76 77 82

76 77

76 77 82

76 77 79

76 77

73 76 77

76 77

76 77 82

76 77

76 77 79

73 76 77

76 77

76 77 79

76 77 82

76 77

76 77 82

76 77

76 77 82

NC NC NC NC NC

NC

NC NC NC NC NC

NC NC NC NC NC NC NC NC NC

NC8

NC6 NC7

NC5

NC4

NC3

NC0 NC1 NC2

DP_VDDR

DPAB_CALR

DPCD_CALR

DPEF_CALR

DP_VDDC

NC_DP_VDDC

DP_VSSR

PS_1

PS_0

PS_2

PS_3

(6 OF 9)

GND

VSS_MECH

(8 OF 9)

GND GND

PX_EN

(9 OF 9)

NC NC NC

NC

NC NC NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPIO_28 pull low at power up

ROM BOOT NC 4.75K 0.68

ROM BOOT 4.53K 4.99K 0.68

-------------------------

PCIe Gen3 Enabled, Full-Swing, TX De-Emp Enabled

All Ports Audio-Capable Display Output

EFI BOOT (NO ROM) NC 4.75K 0.68

PU(ohm) PD(OHM) C(uF)

CONFIG STRAPS - MLPS

EFI BOOT (NO ROM)

PS_0: R9120=8.45K,R9211=2K,C9210=0.082uF PS_1: R9122=8.45K,R9213=2K,C9211NOSTUFF PS_2: R9214 NOSTUFF,R9215=4.75K,C9213=0.68uF

PS_2: R9216 NOSTUFF,R9217=4.75K,C9213=0.68uF

PS_2

PS_3

PS_0

PS_1

PU(ohm) PD(OHM) C(uF)

256MB FB Aperture Size

VGA Enabled

VBIOS Disabled, Boot from EFI

(NONE)

- =PP1V8_GPU_DP_AB

(NONE)

BOM options provided by this page:

- =PP1V0_GPU_DP_EF

- =PP1V8_GPU_DP_CD

- =PP1V8_GPU_DP_EF

- =PP1V0_GPU_DP_AB

- =PP1V0_GPU_DP_CD

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

EFI BOOT (NO ROM) NC 4.75K 0.68

-----------------------------

PU(ohm) PD(OHM) C(uF)

ROM BOOT 8.45K 2K NC

EFI BOOT (NO ROM) 8.45K 2K NC

-----------------------------

ROM BOOT 3.24K 5.62K 0.082

EFI BOOT (NO ROM) 8.45K 2K 0.082

-----------------------------

2

1

C9201

X6S 0201

4V

20%

PLACE_NEAR=U8400.AM37:2.54MM

1.0UF

AD33

AG31

AD31

AM34

AP23

AP22

AP21

AP20

AV29

AU28

AP26

AP25

AV19

AU18

AP24

AN24

AT13

AP15

AP14

AP13

AD32

AG21

AA29

AC31

V13

U13

AD30

AF32

AC32

AM39

AW18

AW28

AN34

AN29

AN27

AN19

AN17

AM35

AN32

AW32

AW30

AW26

AW24

AL34

AW22

AW20

AW16

AW14

AV27

AV17

AU37

AR39

AR28

AR18

AK39

AP39

AP30

AP29

AP28

AP27

AP19

AP18

AP17

AP16

AN38

AH39

AF39

AM32

AM37 AL38

AJ34

AH34

AG34

AF34

AN31

AM33

AL33

AK34

AK33

AP33

AP32

AP31

AN33

U8400

OMIT_TABLE

VENUS-XT

FCBGA

AW39

AW1

A39

AA6

AA28

AA26

AA23

AA21

AA2

AF18

AF16

AF10

AE6

AE2

AD9

AD27

AD24

AD22

AA18

AD20

AD17

AD15

AC6

AC28

AC26

AC23

AC21

AC2

Y39

Y34

W34

W31

V39

V34

AC18

AA16

U34

U31

T39

T34

T31

R34

P39

P34

P31

N34

AC16

N31

M39

M34

L34

L31

K39

K34

K31

J34

J31

AC13

H39

H34

H31

G34

G33

F39

F34

E39

AB39

AC11

AB27

AB24

AB22

AB20

AB17

AB15

AB12

A37

A3

U8400

OMIT_TABLE

VENUS-XT

FCBGA

AL21

F19

F17

F15

F13

F11

E5

E35

C39

C1

B9

B7

B33

B31

B29

B27

B25

B23

B21

B19

B17

B15

B13

B11

AR5

AP9

AP7

AP11

AN8

AN6

AN30

AN2

AN11

AM9

AM31

AM11

AL8

AL6

AL32

AL26

AL23

AL20

AL2

AL17

AL14

AL11

AK7

AK31

AK11

AJ6

AJ28

AJ2

AJ11

AJ10

AH21

AG9

AG6

AG22

AG20

AG2

AG17

AF21

Y27

Y24

Y22

Y20

Y17

Y15

W6

W2

V26

V23

V21

V18

V16

V11

U6

U27

U24

U22

U20

U2

U17

U15

T26

T23

T21

T18

T16

T13

T11

R6

R27

R24

R22

R20

R2

R17

R15

N6

N26

N23

N21

N2

N18

N16

M24

M22

M17

L6

L24

L22

L2

L17

L11

K7

K14

J8

J6

J27

J2

H9

G6

G2

F9

F7

F33

F31

F29

F27

F25

F23

F21

U8400

OMIT_TABLE

VENUS-XT

FCBGA

2

1

C9202

10%

0.1UF

6.3V X7R 0201

PLACE_NEAR=U8400.AF34:2.54MM

2

1

C9205

0201

X7R

6.3V

PLACE_NEAR=U8400.AP32:2.54MM

0.1UF

10%

2

1

C9204

PLACE_NEAR=U8400.AM33:2.54MM

X6S

4V

20%

1.0UF

0201

2

1

C9200

CERM-X6S

20%

10UF

6.3V

0402

2

1

C9203

CERM-X6S

20%

10UF

6.3V

0402

21

R9210

8.45K

1/20W

201

MF

1%

PLACE_NEAR=U8400.AM34:5.08MM

2

1

R9211

PLACE_NEAR=U8400.AM34:5.08MM

201

1/20W

1%

2K

MF

2

1

C9210

10%

PLACE_NEAR=U8400.AM34:5.08MM

0.082UF

CERM-X7R

16V 402

2

1

C9211

PLACE_NEAR=U8400.AD31:5.08MM

0402

X6S

NOSTUFF

5%

0.68UF

6.3V

2

1

R9213

1/20W 201

PLACE_NEAR=U8400.AD31:5.08MM

MF

1%

2K

21

R9212

PLACE_NEAR=U8400.AD31:5.08MM

8.45K

1/20W

MF

201

1%

2

1

C9212

PLACE_NEAR=U8400.AG31:5.08MM

X6S

5%

0402

0.68UF

6.3V

2

1

C9213

0.68UF

5% X6S

0402

PLACE_NEAR=U8400.AD33:5.08MM

6.3V

2

1

R9215

4.75K

1% 1/20W

PLACE_NEAR=U8400.AG31:5.08MM

MF 201

21

R9214

4.53K

PLACE_NEAR=U8400.AG31:5.08MM

MF

1%

1/20W

201

NOSTUFF

21

R9216

PLACE_NEAR=U8400.AD33:5.08MM

1%

1/20W

MF

201

NOSTUFF

4.53K

2

1

R9217

PLACE_NEAR=U8400.AD33:5.08MM

1%

4.75K

1/20W MF 201

21

R9200

PLACE_NEAR=U8400.AW28:2.54MM

150

MF

1%

1/20W

201

21

R9201

PLACE_NEAR=U8400.AW18:2.54MM

GPU_DP_CD_CALR

MF

150

201

1/20W

1%

21

R9202

150

201

1/20W

PLACE_NEAR=U8400.AM39:2.54MM

MF

1%

GPU

Venus DP PWR/GNDs

SYNC_DATE=09/22/2014

SYNC_MASTER=MARY_X425G

PP1V8_GPUIFPX

PP0V95_S0GPU

GPU_DP_EF_CALR

PP1V8_GPUIFPX

GPU_PS_1

GPU_PS_3

GPU_PS_2

GPU_PS_0

GPU_DP_AB_CALR

<SCH_NUM>

92 OF 119

78 OF 97

71 76 78 80 84

70 71 73 84

71 76 78 80 84

S

D

G

D

S

G

S

D

G

D

S

G

NC

IN

IMON

THRM

ISUM-

ISUM+

ISEN1

VSSP1

LGATE1A

UGATE1

BOOT1

PHASE1

ISEN2

LGATE1B

VSSP2

LGATE2

PHASE2

UGATE2

BOOT2

RTN

VSEN

FB

FB2

COMP

VW

VR_ON

DPRSLPVR

VID6

VID5

VID4

VID1 VID2

VID0

CLK_EN*

VR_TT*

PGOOD

VINVDD

NTC

RBIAS

VCCP

PSI*

VID3

PAD

NCNC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PSI_L = HIGH & DPSLP_EN = HIGH

Do not config

~30.5A max per phase

VIMON = Imon* R9312

0.85V is set by setting VID0-VID5

376S1011

NO_XNET_CONNECTION

1A will generate 14.6104mV and 891.23mV for 61A

VIMON = 1.46104uA/A * Io * 14.6104mV/A*Io

Imon = 3* Idroop. Idroop = 2*Rsns*Io/(N*Ri)

R9377 = DPSLP Control GPIO 30

R9375 = GFXIMVP_VR_TT_L GPIO13

NO_XNET_CONNECTION

376S1011

353S3679

Stuff option for GPIO control

as 001011

Default Vcore set to 0.85V.

(GND_GFXIMVP_AGND)

Line Width & DIDT on all DIDT nets

2

1

C9361

CRITICAL

270UF

TANT

2V CASE-B2-SM

20%

3

2

8

7

Q9330

IRF6802SDTRPBF

DIRECTFET-SA

653

4

782

1

Q9331

CRITICAL

DIRECTFET_S3C

649135PBF

4

1

6

5

Q9330

DIRECTFET-SA

IRF6802SDTRPBF

653

4

782

1

Q9361

CRITICAL

649135PBF

DIRECTFET_S3C

2 1

XW9300

PLACE_NEAR=U9300.41:1mm

SM

68

6

27

22

12

4

38

17

37

36

35

34

33

32

31

16

25

29

20

41

13

3

2

28

21

1

5

26

24

23

15

14

10

11

18

9 8

39

7

40

30

19

U9300

TQFN

CKPLUS_WAIVE=PdifPr_badTerm

ISL62882C

2 1

XW9330

PLACE_NEAR=Q9331.3:1mm

SM

2

1

R9330

MF-LF 603

0

1/10W

5%

2

1

C9330

10%

402

CERM

16V

0.22UF

2

1

R9360

603

0

1/10W MF-LF

5%

2

1

C9365

0.22UF

10%

402

CERM

16V

2 1

XW9331

SM

PLACE_NEAR=Q9361.3:1mm

2

1

R9364

1%

TRUE

MF-LF

1/20W 0201

1.00

2

1

R9363

1% MF

1K

1/20W

201

TRUE

2

1

R9361

1% MF

201

1/20W

10K

TRUE

2

1

R9362

1% MF

TRUE

201

1/20W

10K

2

1

R9331

201

1% MF

1/20W

TRUE

10K

2

1

R9334

1% 1/20W

TRUE

1.00

MF-LF 0201

2

1

R9333

1% MF

1/20W

1K

TRUE

201

2

1

R9332

1% MF

TRUE

10K

1/20W

201

21

R9311

1% MF

1/20W

201

1.15K

NOSTUFF

2

1

C9312

0201

X6S

6.3V

10%

0.1UF

NOSTUFF

2

1

C9311

6.3V

0.1UF

X6S

10%

0201

2

1

C9310

CERM 201

10V

5600PF

10%

21

C9366

6.3V

0.22UF

0201

X6S-CERM

20%

21

C9331

0201

X6S-CERM

6.3V

0.22UF

20%

2

1

C9302

10%

X6S-CERM

0402

1UF

PLACE_NEAR=U9300.25:1mm

25V

21

R9301

MF

201

1

5%

1/20W

2

1

C9313

6.3V

10%

0201

X6S

0.1UF

NO_XNET_CONNECTION=TRUE

47

71 85 96

2

1

C9314

NO_XNET_CONNECTION=TRUE

1000PF

10% 16V X7R-1 0201

2

1

C9315

10%

NO_XNET_CONNECTION=TRUE

16V

1000PF

X7R-1

0201

2

1

C9319

10% 16V X7R-1 0201

1000PF

2

1

R9317

1% MF

49.9

201

NOSTUFF

1/20W

2

1

C9341

10%

NOSTUFF

10V 201

CERM

5600PF

2

1

R9315

1% MF

1/20W

201

NO_XNET_CONNECTION=TRUE

3.09K

2

1

R9316

1% MF

301

201

1/20W

2

1

C9317

5%

100PF

C0G 0201

25V

2

1

C9318

50V

5%

0201

22PF

NOSTUFF

NP0-C0G-CERM

68 82

21

R9340

1% MF

1/20W

147K

201

43

21

R9399

1%

0.00075

0612-1

1W MF

4 3

2 1

R9398

1%

0.00075

0612-1

1W MF

2

1

C9340

X5R-X7R-CERM

470PF

0201

10%

NO_XNET_CONNECTION=TRUE

16V

2

1

R9313

1% MF

249K

201

1/20W

2

1

R9314

1% MF

201

5.11K

1/20W

2

1

R9312

1% MF

201

10K

NO_XNET_CONNECTION=TRUE

1/20W

2

1

C9316

X7R-CERM

560PF

10%

0201

50V

21

R9318

1% MF

201

1/20W

30.1K

2

1

C9301

PLACE_NEAR=U9300.16:1mm

0402

1UF

X6S-CERM

10% 25V

2

1

C9300

0402

X7R

PLACE_NEAR=U9300.17:1mm

10%

0.22UF

25V

21

R9310

1% MF

201

1/20W

1.54K

2

1

C9328

25V

X6S-CERM

0402

2.2UF

20%

2

1

R9300

MF

10

1/20W

5%

201

2

1

R9391

MF

5%

1/20W

2.2K

201

2

1

R9395

MF

201

1/20W

5%

NOSTUFF

2.2K

2

1

R9382

MF

1/20W

5%

2.2K

201

2

1

R9392

MF

2.2K

1/20W

5%

201

NOSTUFF

2

1

R9396

MF

5%

2.2K

1/20W

201

2

1

R9383

MF

5%

2.2K

1/20W

201

NOSTUFF

2

1

R9384

MF

1/20W

201

2.2K

5%

NOSTUFF

2

1

R9387

MF

201

2.2K

5%

1/20W

NOSTUFF

2

1

R9385

MF

5%

1/20W

2.2K

201

2

1

R9388

MF

5%

2.2K

1/20W

201

76 77 79

21

R9375

MF

1/20W

5%

201

0

21

R9377

MF

NOSTUFF

201

0

1/20W

5%

76 77

2

1

R9374

MF 201

NOSTUFF

1/20W

5%

100K

2

1

R9371

201

1/20W

5% MF

10K

2

1

R9373

MF

5% 1/20W

100K

201

2

1

R9372

MF

100K

NOSTUFF

5% 1/20W

201

2

1

R9370

1% MF

1/20W 201

10K

71 96

2 1

XW9315

SM

2 1

XW9314

SM

76 77

2

1

R9319

MF 201

PLACE_NEAR=U9300.37:5mm

10K

5% 1/20W

2

1

R9378

MF

201

2.2K

5%

1/20W

2

1

R9379

MF

2.2K

5%

201

1/20W

NOSTUFF

76 77 79

21

L9330

PILA63T-SM

0.2UH-20%-28A-0.0011OHM

CRITICAL

2

1

C9362

CRITICAL

270UF

CASE-B2-SM

2V TANT

20%

2

1

C9363

CASE-B2-SM

TANT

270UF

2V

CRITICAL

20%

2

1

C9327

25V

X6S-CERM

0402

2.2UF

20%

2

1

C9323

25V

X6S-CERM

0402

2.2UF

20%

2

1

C9324

25V

X6S-CERM

0402

2.2UF

20%

2

1

C9320

CRITICAL

68UF

16V

POLY-TANT

CASE-D2E-SM

20%

2

1

C9321

68UF

CASE-D2E-SM

16V

CRITICAL

POLY-TANT

20%

2

1

C9322

POLY-TANT

16V

68UF

CRITICAL

CASE-D2E-SM

20%

2

1

C9326

16V

POLY-TANT

68UF

CASE-D2E-SM

CRITICAL

20%

21

L9360

PILA63T-SM

CRITICAL

0.2UH-20%-28A-0.0011OHM

2

1

C9329

16V

33UF

CASED12-SM

POLY-TANT

CRITICAL

20%

2

1

C9325

33UF

POLY-TANT

16V CASED12-SM

CRITICAL

20%

3 2

1

C9364

D15T-ECGLT-COMBO

CRITICAL

POLY-TANT

330UF-6MOHM

2.0V

20%

2

1

C9332

5% 0201

NP0-C0G

CRITICAL

12PF

25V

2

1

C9333

3.0PF

+/-0.1PF NP0-C0G

0201

CRITICAL

25V

GFX IMVP VCore Regulator

SYNC_DATE=09/15/2014

GPU

SYNC_MASTER=ADITYA_X425G

SWITCH_NODE=TRUE

GFXIMVP_PHASE2

GFXIMVP_UGATE2

GATE_NODE=TRUE

GFXIMVP_ISNS2_P

PPVCORE_GPU

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP5V_S0_GFXIMVP_VDD

VOLTAGE=5V

GFXIMVP_ISEN2

GFXIMVP_COMP

GFXIMVP_FB

GPUVCORE_SENSE_N

GFXIMVP_FB2

GFXIMVP_VW

GPU_VCORE_VID2

SWITCH_NODE=TRUE

GFXIMVP_PHASE1

GPUVCORE_PGOOD

GFXIMVP_NTC

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

GPU_VCORE_VID4

GPU_VCORE_VID4 GPU_VCORE_VID5

GPU_VCORE_VID5

MAKE_BASE=TRUE

GPU_VCORE_VID0 GPU_VCORE_VID1

GPUVCORE_SENSE_P

PP5V_S0

GPU_VCORE_VID0

GFXIMVP_BOOT2

MIN_NECK_WIDTH=0.2MM DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

PPVIN_S5_HS_GPU_ISNS

GFXIMVP_ISNS1_N

GFXIMVP_ISUMN

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

PPVCORE_S0_GFX_PH2

GFXIMVP_ISUMP

GFXIMVP_ISNS1_N

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6MM

PPVCORE_S0_GFX_PH1

MIN_NECK_WIDTH=0.2MM

GFXIMVP_VR_TT_L

MIN_LINE_WIDTH=0.6MM

GFXIMVP_BOOT2_R

MIN_NECK_WIDTH=0.2MM DIDT=TRUE

GPUVCORE_EN

GFXIMVP_VR_TT_L

GFXIMVP_VR_ICCMAX_WARN_L

GFXIMVP_DPSLP_EN

GFXIMVP_DPSLP_EN_R

VSNS_GPU_VDDC_P

GFXIMVP_FB_SNS_R

GFXIMVP_COMP_R

GFXIMVP_VR_TT_L

GFXIMVP_FB_GND_R

GFXIMVP_PSI_L

GFXIMVP_ISNS1_P

GFXIMVP_ISNS2_N

GFXIMVP_ISUMP_C

GPU_VCORE_VID1

DIDT=TRUE

GFXIMVP_BOOT1_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GFXIMVP_VSSP1

GFXIMVP6_IMON

GPU_VCORE_VID4

GFXIMVP_ISUMP

GFXIMVP_ISUMN

GFXIMVP_DPSLP_EN

GFXIMVP_PSI_L

MIN_LINE_WIDTH=0.6MM

GFXIMVP_VSSP2

MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

PP3V3_S0GPU

GFXIMVP_ISNS2_N

GFXIMVP_ISUMP

PP3V3_S0GPU

GPU_VCORE_VID3

GPU_VCORE_VID2 GPU_VCORE_VID3

GFXIMVP_ISUMN_R

GFXIMVP_ISEN1

GFXIMVP_LGATE1

GATE_NODE=TRUE

GFXIMVP_BOOT1 GFXIMVP_UGATE1

GATE_NODE=TRUE

GPU_VCORE_VID5 GFXIMVP6_VID6

GATE_NODE=TRUE

GFXIMVP_LGATE2

VOLTAGE=12.8V

PPVIN_S0_GFXIMVP_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GFXIMVP_RBIAS

PPVIN_S5_HS_GPU_ISNS

VSNS_GPU_VDDC_N

GFXIMVP_DPSLP_EN

VOLTAGE=0V

GND_GFXIMVP_AGND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

<SCH_NUM>

93 OF 119

79 OF 97

96

47 71 84

96

76 77 79

96

18 19 36 49 58 59 62 63 66 67 73 80 84 85 86

76 77 79

47 73 79 80 84

79 96

79

79 96

79

77 79

96

79 96

76 77 79

79

77 79

47 66 68 71 72 76 77 79 80 84

79 96

79

47 66 68 71 72 76 77 79 80 84

76 77 79

47 73 79 80 84

79

BG

TGR

TG

PGND

VIN

VSW

IN

OUT

PAD

PVIN

VOS

FB

PG

THRM

AGND

PGND

AVIN

DEF

SS/TR

SW SW SW

EN

FSW

VID1

SET1

PGOOD

OCSET

FB

VO

EN

GND

PGND

PHASE

LGATE

UGATE

BOOT

VCC

PVCC

SET0

FSEL

RTN

VID0

SREF

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APN152S1822

GPU VDDCI REGULATOR

1 1 0.85V

--> DEFAULT

Output voltage:

VID1 VID0 GPU VDDCI

VOUT = 0.9V

1 0 0.9V

353S4283

<Rb>

<Ra>

7A MAX OUTPUT F = 500 KHZ

1.818 V

1.5A 1250 kHz

Vout = 0.8V * (Ra + Rb) / Rb

Switching freq:

Max peak current:

audio frequencies

prevent noise in the

a minimum load to

Regulator requires

Note:

APN376S1005

<Ra>

1.8V S0 GPU Regulator

<Ra>

Vout = 0.5 * (1 + Ra / Rb)

APN152S00137

2

1

C9405

16V X7R-CERM

0.1UF

0402

10%

2

1

R9407

2.2

1/16W

402

MF-LF

5%

21

L9410

1.0UH-20%-15A-0.0066OHM

PIME063T-SM

CRITICAL

8

7

6

1

4

3

9

5

Q9410

CSD58873Q3D

Q3D

CRITICAL

2

1

C9414

2V TANT

CRITICAL

270UF

CASE-B2-SM

20%

2

1

C9415

TANT CASE-B2-SM

CRITICAL

2V

270UF

20%

2

1

C9410

EMC

PLACE_NEAR=Q9410.1:4mm

25V

X6S-CERM

0402

2.2UF

20%

2

1

C9409

EMC

PLACE_NEAR=Q9410.1:4mm

25V

X6S-CERM

0402

2.2UF

20%

2

1

C9402

68UF

POLY-TANT

CASE-D2E-SM

16V

CRITICAL

20%

2

1

C9417

CRITICAL

X6S-CERM 0603

10UF

10V

20%

2

1

C9421

CRITICAL

25V X6S-CERM 0402

2.2UF

20%

2

1

C9422

CRITICAL

25V X6S-CERM 0402

2.2UF

20%

2

1

C9423

X6S

0.1UF

0402

10% 25V

21

R9420

1/20W

5%

201

MF

10

68

2

1

R9412

1/16W

5%

402

200

MF-LF

68 82

21

XW9420

SM

14

17

3

2

1

9

12

11

16

15

4

7

5

13

8

10

6

U9400

TPS62130ARGT

CRITICAL

QFN

2

1

C9424

201

X7R

4700PF

10V

10%

2

1

R9423

MF

82.5K

1/20W

0.1%

0201-1

2

1

R9422

MF

1/20W

105K

0.1%

0201-1

2

1

R9421

5%

201

10

1/20W

MF

2

1

C9420

16V CASED12-SM

33UF

CRITICAL

POLY-TANT

20%

2

1

C9426

CRITICAL

0805

POLY-TANT

47UF

6.3V

20%

2

1

C9427

CRITICAL

0805

POLY-TANT

47UF

6.3V

20%

2

1

C9428

CRITICAL

POLY-TANT

47UF

0805

6.3V

20%

2

1

C9429

CRITICAL

POLY-TANT

47UF

0805

6.3V

20%

2

1

C9413

5%

1000PF

CERM 0402

25V

2

1

C9430

CRITICAL

47UF

POLY-TANT 0805

6.3V

20%

2

1

C9425

0805

POLY-TANT

47UF

CRITICAL

6.3V

20%

21

R9408

402

1

5%

MF-LF

1/16W

12

5

6

19

17

7

9

8

4

20

16

14

2

11

1

3

13

10

15 18

U9450

CRITICAL

ISL95870AH

UTQFN

2

1

R9474

MF

17.4K

1/20W

0.1%

0201

2

1

R9475

MF

1/20W

0.1%

34.8K

0201-1

2

1

R9478

MF

249K

1/20W

0.1%

0201

21

R9477

0201

0

5%

1/20W

MF

2

1

R9481

1/20W

5%

10K

201

MF

2

1

R9483

10K

5% 1/20W MF 201

21

R9485

1/20W

5%

0201

0

MF

NOSTUFF

21

R9484

0

1/20W

5%

0201

MF

76 77

2

1

C9416

CASE-B2-SM

270UF

CRITICAL

2V TANT

20%

2

1

C9419

2V

270UF

TANT CASE-B2-SM

CRITICAL

20%

2

1

C9431

CRITICAL

TANT

2V

270UF

CASE-B2-SM

20%

21

L9400

CRITICAL

1.5UH-20%-2.61A-0.068OHM

PIFE32251B-SM

2

1

C9408

5%

1000PF

CERM 0402

25V

2

1

C9406

5% NP0-C0G

12PF

0201

CRITICAL

25V

2

1

C9407

0201

+/-0.1PF

3.0PF

NP0-C0G

CRITICAL

25V

2

1

C9433

+/-0.1PF NP0-C0G

3.0PF

CRITICAL

0201

25V

2

1

C9432

0201

5% NP0-C0G

12PF

CRITICAL

25V

2

1

C9418

CRITICAL

X6S-CERM 0603

10UF

10V

20%

2

1

R9411

3.92K

201

1/20W MF

1%

4 3

2 1

R9400

CRITICAL

0.003

1%

0612

CYN

1W

21

C9412

CERM

402

0.0022UF

50V

PLACE_NEAR=R9410.2:3mm

10%

2

1

R9410

3.92K

1/20W

201

MF

1%

2

1

C9411

NOSTUFF

0.001UF

X7R-CERM

50V 0402

10%

2

1

R9409

1/10W

2.2

NOSTUFF

5% MF-LF

603

2

1

C9404

10V X6S-CERM 0402

10%

2.2UF

2

1

R9406

201

1/20W

5%

2.2

MF

2

1

R9405

10

5%

1/20W

201

MF

2

1

XW9471

SM

PLACE_NEAR=U8400.AG28:5mm

2

1

XW9470

SM

PLACE_NEAR=U8400.AH28:5mm

71 85 96

71 96

2 1

XW9473

SM

PLACE_NEAR=U9450.3:1mm

68

2

1

C9490

0.033UF

402

16V X5R

10%

2

1

R9476

5%

0201

1/20W MF

0

NOSTUFF

2

1

R9471

0.1% MF

NO_XNET_CONNECTION=TRUE

2.8K

1/20W 0201

2

1

R9470

1/20W

NO_XNET_CONNECTION=TRUE

2.8K

0.1% MF

0201

2

1

C9485

0201

10PF

5% C0G

50V

2

1

R9473

MF

4.02K

1/20W

0.1%

0201

2

1

R9472

MF

4.02K

1/20W

0.1%

0201

2

1

C9470

10PF

50V C0G

5%

0201

2

1

C9403

16V

1UF

CER-X6S

0402

10%

2 1

XW9480

SM

2 1

XW9481

SM

47 96

68 82

SYNC_MASTER=ADITYA_X425G

VREG GPU VDDCI

GPU

SYNC_DATE=09/16/2014

PPVIN_S5_HS_GPU_ISNS

VRVDDCI_R

AGND_GPU_VDDCI

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

GFX_VDDCI_ALTV1

REG_GPU_VDDCI_RTN

GPU_VDDCI_SENSE_XW_N

REG_VOS_PVDDR REG_FB_PVDDR

VSNS_GPU_VDDI_N

VSNS_GPU_VDDI_P

REG_GPU_VDDCI_SET0

REG_GPU_VDDCI_FSEL

PVDDCI_PGOOD

GFX_VDDCI_ALTV0

GFX_VDDCI_ALTV

REG_GPU_VDDCI_FB

PPVIN_S5_HS_GPU_ISNS

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PPVIN_S0GPU_1V8_RC

AGND_PVDDR

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

PPVDDCI_S0_ISENSE

PP1V8_GPUIFPX

PP5V_VDDCI_VCC

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=5V

PP5V_VDDCI_PVCC

MIN_NECK_WIDTH=0.2 MM

REG_GPU_VDDCI_SET1

VDDCIS0_CS_P

REG_SNUBBER_GPU_VDDCI

REG_GPU_VDDCI_OCSET REG_GPU_VDDCI_VO

P1V8_S0GPU_EN

GPU_VDDCI_SENSE_XW_P

REG_GPU_VDDCI_VO

REG_GPU_VDDCI_OCSET

PP5V_S0

P1V8GPU_PGOOD

AGND_GPU_VDDCI

REG_GPU_VDDCI_OCSET_R

REG_BOOT_GPU_VDDCI_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

REG_BOOT_GPU_VDDCI

MIN_NECK_WIDTH=0.2 mm

REG_UGATE_VDDCI_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

VDDCIS0_CS_N

REG_SSTR_PVDDR

SWITCH_NODE=TRUE DIDT=TRUE

REG_PHASE_PVDDR

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

REG_GPU_VDDCI_SET1_R

PVDDCI_GPU_EN

REG_GPU_VDDCI_SREF

PP3V3_S0GPU

REG_GPU_VDDCI_VO_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

REG_LGATE_GPU_VDDCI

MIN_LINE_WIDTH=0.6 mm

REG_UGATE_VDDCI

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

VR_PHASE_GPU_VDDCI

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

REG_PHASE_GPU_VDDCI

<SCH_NUM>

94 OF 119

80 OF 97

47 73 79 80 84

80

96

47 73 79 80 84

71 84

71 76 78 84

80

96

80

18 19 36 49 58 59 62 63 66 67 73 79 84 85 86

80

47 66 68 71 72 76 77 79 84

IN IN

BI BI

IN

OUT OUT

IN

IN IN

OUT OUT

IN IN

IN

TP

IN

BI

OUT

IN

OUT

IN IN

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

516S00052

518S0829

Wire-to-Board (Micro-coax) Connector

LOCATION DEPENDS ON DESENSE TEAM

C9512&C9513 FOR DESENSE IMPROVEMENT

Board-to-Board (Flex) Connector

76 86 97

13 86 90

13 90

13 86 90

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9500

GND_VOID=TRUE

CRITICAL

20525-130E-01

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

F-RT-SM

GND_VOID=TRUE

76 86 97

13 20 86 91

76 86 97

1

BP9501

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

SM

1

BP9502

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

1

BP9505

SM

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

1

BP9506

SM

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

1

BP9503

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

1

BP9504

SM

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

21

C9501

0.1UF

GND_VOID=TRUE

10%

X5R-CERM

16V

0201

21

C9502

0.1UF

GND_VOID=TRUE

0201

16V

X5R-CERM

10%

2

1

C9510

0.1uF

402

10V

20%

CERM

2

1

C9511

CERM

0.1uF

402

20% 10V

9

8 7

6 5

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J9510

CRITICAL

DF40HC-3.0-40DS-0.4V-51

F-ST-SM

76

18 86

13 18 86

20 86

20 82 86

12 21 33 37 40 67 86

51 66 67 82 86

13 18 43 85 86 91

2

1

C9512

PLACE_NEAR=J9510.1:3mm

0201

NP0-C0G

5%

12PF

25V

2

1

C9513

5%

PLACE_NEAR=J9510.21:3mm

NP0-C0G

12PF

0201 25V

RIO Connectors

SYNC_DATE=07/01/2014

SYNC_MASTER=CLEAN_MAXWELL

PP5V_S4 PP5V_S4

PP3V3_S3

SMBUS_PCH_DATA

PP3V3_S4

SMBUS_PCH_CLK

USB3_EXTB_D2R_N

HDMI_EG_CLK_P HDMI_EG_CLK_N

HDMI_EG_DATA_P<0> HDMI_EG_DATA_N<0>

HDMI_EG_DATA_P<1> HDMI_EG_DATA_N<1>

USB3_EXTB_D2R_P

USB_EXTB_N

USB3_EXTB_R2D_P

USB3_SD_D2R_P USB3_SD_D2R_N

USB3_SD_R2D_C_P

HDMI_HPD

USB_EXTB_OC_L

SD_PWR_EN

RIO_SDCONN_STATE_CHANGE_L

PP3V3_S3

PM_SLP_S3_BUF_L

PM_SLP_S4_L

PP1V5_S0

PP3V3_S3

HDMI_EG_DDC_CLK

USB_EXTB_P

USB3_SD_R2D_C_N

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_EXTB_R2D_N

HDMI_EG_DATA_N<2>

HDMI_EG_DATA_P<2>

HDMI_EG_DDC_DATA

<SCH_NUM>

95 OF 119

81 OF 97

37 38 51 61 66 67 69 81 84 86 37 38 51 61 66 67 69 81 84 86

13 20 21 43 45 46 66 81 82 84 86

20 33 38 41 42 45 46 65 66 67 84 85 86

86 90

13 20 21 43 45 46 66 81 82 84 86

11 12 13 15 17 19 52 64 67 84 86

13 20 21 43 45 46 66 81 82 84 86

86 90

OUT

OUT OUT OUT OUT OUT

OUT

IN

OUT

OUT IN

OUT

IN

OUT

BI OUT OUT

OUT

P45/PWMU3B/TCMCKI2/TCMMCI2

P44/TMO1/PWMU2B/TCMCYI2

P43/TMI1/TCMCKI1/TCMMCI1

P41/TMO0/TCMCKI0/TCMMCI0

P52/SCL0

P51/FRXD

P50/FTXD

P47/PWMU5B

P46/PWMU4B

P42/TCMCYI1

P40/TMI0/TCMCYI0

P37/SERIRQ

P36/LCLK

P35/LRESET*

P34/LFRAM*

P33/LAD3

P32/LAD2

P31/LAD1

P30/LAD0

P26 P27

P25

P22

P21

P23 P24

P20

P10/WUE0* P11/WUE1* P12/WUE2* P13/WUE3* P14/WUE4* P15/WUE5* P16/WUE6* P17/WUE7*

P96/EXCL

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P83/LPCPD*

P82/CLKRUN*

P90/IRQ2* P91/IRQ1*

P85/IRQ4*/RXD1

P84/IRQ3*/TXD1

P86/IRQ5*/SCK1

P97/SDA0/IRQ15*

P77/AN7

P76/AN6

P75/AN5

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P80/PME* P81/GA20

P70/AN0

P66/KIN6*

P65/KIN5*

P64/KIN4*

P63/KIN3*

P62/KIN2*

P61/KIN1*

P60/KIN0*

P67/IRQ7*/KIN7*

SYM 1 OF 3

IN

NC

IN

OUT OUT

OUT

OUT OUT

IN IN

OUT

PC2/TIOCC0/TCLKA/WUE10* PC3/TIOCD0/TCLKB/WUE11*

PC5/TIOCB1/TCLKC/WUE13*

PC7/TIOCB2/TCLKD/WUE15*

PD6/SSCK PD7/SCS

PD5/SSI

PD4/SSO

PD3/AN11

PD2/AN10

PC4/TIOCA1/WUE12*

PC6/TIOCA2/WUE14*

PD1/AN9

PD0/AN8

PB6/CTS*/FSICK PB7/RTS*/FSISS

PC0/TIOCA0/WUE8*

PB5/DTR*/FSIDI

PB4/DSR*/FSIDO

PB3/DCD*/PWMU1B

PC1/TIOCB0/WUE9*

PB1/LSCI

PB0/LSMI*

PA5/KIN13*/PS2BD

PA0/KIN8*/SDA1 PA1/KIN9*/SCL1 PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD PA4/KIN12*/PS2BC

PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD

PEVREF

PECI

PH1/EXIRQ7*

PH0/IRQ6*

PG7/EXIRQ15*/SCLD

PG6/EXIRQ14*/SDAD

PG5/EXIRQ13*/SCLC

PG4/EXIRQ12*/SDAC

PF3/IRQ11*/TMOX PF4/PWMU2A/EXDSR PF5/PWMU3A/EXDTR PF6/PWMU4A/EXCTS PF7/PWMU5A/EXRTS

PG2/EXIRQ10*/SDAB PG3/EXIRQ11*/SCLB

PF2/IRQ10*/TMOY

PE4/ETMS

PE1/ETCK PE2/ETDI PE3/ETDO

PE0/EXEXCL

PE5/ETRST*

PF0/IRQ8*/PWMU0A PF1/IRQ9*/PWMU1A

PG1/EXIRQ9*/TMIY/SCLA

PG0/EXIRQ8*/TMIX/SDAA

PB2/RI*/PWMU0B

SYM 2 OF 3

IN IN

OUT

IN

IN IN IN IN

IN

BI

OUT

IN

OUT OUT

DIN1_1-

DIN1_1+

VDD

GND

DIN1_0-

DIN1_3-

DOUT_0+

DOUT_1-

DAUX1-

DIN2_0+ DIN2_0-

DAUX2+

DIN2_3-

DIN2_3+

DIN2_2-

DIN2_2+

HPDIN

AUX+

DIN2_1-

DDC_AUX_SEL

DIN2_1+

DOUT_3-

DOUT_3+

DOUT_2-

DOUT_2+

DDC_DAT1

DDC_CLK1

DOUT_1+

DIN1_2+

GPU_SEL

HPD_2

DDC_CLK2

DAUX2-

DDC_DAT2

DIN1_3+

DAUX1+

DIN1_2-

HPD_1

XSD*

DIN1_0+

GND

AUX-

DOUT_0-

IN

SYM_VER_2

G S

D

IN

Y

NC NC

VCC

GND

A

NC NC

G

VER 5

SD

G

VER 5

SD

IN

OUT

IN

VSS

AVSS

EXTAL

VBAT

AVREF

VCL

AVCC

VCC

RES*

XTAL

VSS

MD2

MD1

NMI

NC

MDCKN

SYM 3 OF 3

IN IN

NC NC NC NC NC NC NC NC

NC NC NC

NC

BI BI

NC

BI

IN IN

OUT

IN

BI

OUT

IN

BI

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CA_DET ISOLATION-Will delete

DPMUX UC PULL-UPS

PU on PCH Page

DPMUX UC PULL-DOWNS

CONNECT I2C TO LCD BKLT IC

PU OFFPAGE

DPMUX UC DEBUG HEADER

DP 2:1 ANALOG MUX

69 97

21

R9620

201

MF

1/20W

10K

5%

NOSTUFF

69 97

21

R9610

10K

1/20W

5%

201

MF

68 82

69 97

68 82

21

R9621

MF

1/20W

201

5%

10K

21

R9622

5%

201

1/20W

MF

10K

21

R9623

1/20W

MF

201

5%

10K

21

R9624

5%

201

MF

1/20W

10K

21

R9625

201

10K

1/20W

5% MF

11 82 85

69 97

70 82 85

21

R9626

10K

1/20W

5%

201

MF

21

R9627

MF

1/20W

201

5%

10K

69 85 86

69 97

82 85

83

82 85

43

14 85

63 82

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12

U9600

R4F2113NLG

TLP-145V

OMIT_TABLE

21

R9628

10K

5%

201

1/20W

MF

21

R9611

MF

1/20W

201

10K

5%

76 77

68 73

68

12 85

21

R9629

10K

201

MF

NOSTUFF

5%

1/20W

21

R9612

MF

201

1/20W

10K

5%

21

R9613

5%

10K

MF

201

1/20W

21

R9631

10K

5%

201

MF

NOSTUFF

1/20W

21

R9630

10K

MF

1/20W

201

5%

NOSTUFF

21

R9632

5%

201

MF

1/20W

10K

21

R9633

10K

MF

1/20W

201

5%

21

R9614

5%

201

MF

10K

1/20W

12 85

69

6

5

4

3

2

1

8

7

J9600

DPMUX_DEBUG

M-RT-SM

1909782

21

R9600

402

MF-LF

1/16W

5%

0

21

R9601

1/16W MF-LF

5%

0

402

21

R9615

10K

5%

1/20W

201

MF

21

R9616

10K

5% MF

201

1/20W

21

R9617

10K

5%

1/20W

MF

201

21

R9618

1/20W

5% MF

201

10K

69 82 86

63 82 86

40 42 82

76 77 82

20 82

21

R9602

402

MF-LF

0

5%

1/16W

NOSTUFF

76 77 82

28

83

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

B3

A4

H3

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3

U9600

R4F2113NLG

TLP-145V

OMIT_TABLE

21

R9635

5%

1/20W

MF

201

100K

21

R9619

201

100K

1/20W

MF5%

NOSTUFF

21

R9640

NOSTUFF

1/20W

MF

100K

5%

201

76 97

2

1

R9650

201

5% MF

1/20W

10K

21

R9636

5%

1/20W

MF

201

100K

21

R9637

5% MF

201

100K

1/20W

76 97

21

R9638

5%

1/20W

MF

201

100K

21

R9639

5%

100K

1/20W

MF

201

21

R9645

5%

201

MF

100K

1/20W

21

R9646

201

5%

1/20W

MF

100K

76 77

21

R9662

100K

1%

201

MF

1/20W

76 97

28 31

21

R9660

1/20W

201

MF

5%

100K

76 97

21

R9661

100K

MF 201

5%

1/20W

28 32

76 97

68 80

68 79

68 80

68

76 97

43

28

76 97

12 82 85

B7

J4

A2

J1

H3

J2

A1

G2H7H4G8C8

B3

F2 F1

E2 E1

D2 D1

B2 B1

F8 F9

E8 E9

D8 D9

B8 B9

A8 A9

B6 A6

B5 A5

B4 A4

J5

J8

H5

H8

C2

H6 J6

H9 J9

H2 H1

U9650

CBTL06142EEE

TFBGA

CRITICAL

21

R9647

1/20W

100K

MF

201

5%

21

R9648

100K

MF

1/20W

5%

201

76 97

2

1

3

Q9690

DFN1006H4-3

DMN32D2LFB4

20 81 86

4

6

5

1

3

2

U9670

74LVC1G07GF

SOT891

2

1

R9670

5%

201

MF

1/20W

4.7K

2

1

R9671

NOSTUFF

470K

201

5% MF

1/20W

2

1

C9670

0.1UF

10% X7R

6.3V 0201

1

2

6

Q9610

SOT563

DMN5L06VK-7

NOSTUFF

4

5

3

Q9610

SOT563

DMN5L06VK-7

NOSTUFF

20 82

21

R9641

0

1/20W

MF5%

201

40 42 82

77

77 82

A3

B11

C5

F10

L3

D2

E1

H10

M1

B1

J2

D3

E3

E5

C4

H1

D1

A2

L9

L11

M12

U9600

R4F2113NLG

OMIT_TABLE

TLP-145V

77 82

40 42 82

21

R9642

MF

100K

1/20W

5%

201

21

R9649

1/20W

100K

MF

201

5%

21

R9652

100K

MF

1/20W

5%

201

21

R9653

201

100K

MF

1/20W

5%

21

R9654

5%

1/20W

MF

100K

201

NOSTUFF

21

R9655

201

10K

1/20W

MF5%

21

R9656

10K

1/20W

MF5%

NOSTUFF

201

69 97

76 77 97

5

85 97

5

85 97

5

85 97

5

85 97

69 97

5

85 97

5

85 97

5

85 97

5

85 97

5

85 97

5

85 97

2

1

C9650

10V X7R-CERM 0402

0.1UF

20%

69 97

2

1

C9651

10V X7R-CERM 0402

0.1UF

20%

20

13 40 91

69 97

2

1

C9600

20%

0.1UF

0402

X7R-CERM

10V

2

1

C9601

20%

0.1UF

0402

X7R-CERM

10V

2

1

C9602

20%

0.1UF

0402

X7R-CERM

10V

2

1

C9603

0.1UF

0402

X7R-CERM

10V

20%

2

1

C9605

10%

0.47UF

6.3V 0402

X6S-CERM

2

1

C9604

0402

20% 10V X7R-CERM

0.1UF

eDP Mux

SYNC_MASTER=MARY_X425G

SYNC_DATE=09/22/2014

TP_DPMUX_UC_P45

DP_TBTSNK1_HPD GFX_SELF_THROTTLE

LPC_AD<3>

DP_INT_IG_AUX_P

TP_DPMUX_UC_P52

I2C_DPMUX_UC_SCL DPMUX_UC_IRQ

TP_DPB_EG_HPD DP_TBTSNK0_HPD_EG

TP_DPMUX_UC_P42

TP_DPMUX_UC_P47

DPMUX_UC_RX

TP_DPA_EG_HPD

DP_TBTSNK1_HPD_EG

GPU_GFX_PWR_LEVEL_L HDMI_EG_HPD

SMC_GFX_PWR_LEVEL_L

DP_TBTSNK0_HPD

GPU_GFX_OVERTEMP TP_DP_TBTPB_HPD_BUF

LCD_HPD

TP_DP_B_CA_DET_BUFTP_DP_A_CA_DET_BUF

EDP_IG_PANEL_PWR

DPMUX_LRESET_L

DPMUX_UC_TRST_L

TP_LCD_IRQ

GMUX_SLP_S3_BUF_L

MAKE_BASE=TRUE

PP3V3_S5

PM_SLP_S3_BUF_L

TBT_A_CONFIG1_BUF TBT_B_CONFIG1_BUF

PP3V3_S0

DPMUX_UC_TCK

DPMUX_UC_CLK32K

DPMUX_UC_TDI

TP_DPMUX_UC_P12 TP_DPMUX_UC_P13

TP_DPMUX_UC_P15

EG_RESET_L TP_FB_CLAMP

DP_EXTA_MUX_SEL_EG TP_DPMUX_UC_P62

TP_DPMUX_UC_P14

DP_INT_EG_HPD

LCD_BKLT_EN

TP_DPB_IG_HPD DP_TBTSNK0_HPD_IG DP_TBTSNK1_HPD_IG

TP_LCD_MUX_REQ LCD_BKLT_PWM DP_DDC_MUX_CROSSBAR_L

DPMUX_UC_PEVREF

LCD_FSS LCD_MUX_SEL

TP_DPMUX_UC_P46

DP_EXTB_MUX_EN

TP_DPMUX_UC_P67

TP_DPMUX_UC_P16

TP_DPMUX_UC_P41

LPC_CLK33M_DPMUX_UC

TP_DPMUX_UC_P10

DPMUX_UC_MD2

DPMUX_UC_MD1

DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<1>

DP_INT_IG_ML_N<0>

DP_INT_IG_ML_N<3>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>

DP_INT_IG_AUX_N

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<2>

DPMUX_HPD_PD

DP_INT_AUXCH_C_P

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<1>

DP_INT_ML_C_N<3>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<2>

DP_INT_ML_C_P<1>

DP_INT_IG_ML_P<2>

DP_INT_IG_ML_P<3>

DP_INT_IG_ML_N<2>

DP_INT_IG_ML_P<0>

DP_INT_AUXCH_C_N

DP_INT_ML_C_N<0>

TP_DP_EXTB_CA_DET_IG

TP_DPMUX_UC_PC2

P0V95R1V8GPU_R_EN

TP_DP_EXTA_CA_DET_IG

TP_DPA_IG_HPD

TP_HDMI_IG_HPD

EG_RAIL3_EN

DPMUX_UC_MD1

DPMUX_UC_RX

GMUX_SLP_S3_BUF_L

PP3V3_S0_DPMUX_UC_R

PEG_CLKREQ_L

EG_RAIL1_EN

DPMUX_UC_RESET_L

LPC_AD<1>

DP_INT_IG_HPD

EG_RAIL5_EN

I2C_DPMUX_UC_SDA

LPC_AD<2>

DPMUX_UC_TX

TP_DPMUX_UC_P37

EG_RAIL4_EN

LCD_MUX_EN

EDP_IG_BKL_ON

HDMI_HPD

LPC_FRAME_L

DP_EXTA_MUX_EN

DPMUX_LRESET_L

DPMUX_UC_TX

DPMUX_UC_PECI

DPMUX_UC_TMS

LPC_AD<0>

DP_INT_ML_C_P<3>

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

LCD_MUX_SEL

LCD_MUX_EN

EG_LCD_PWR_EN

DPMUX_UC_RX

TP_DPMUX_UC_P66

DP_EXTB_MUX_SEL_EG

TP_DPMUX_UC_PC3

LCD_PWR_EN

SMC_GFX_SELF_THROTTLE

TP_FB_CLAMP_TOGGLE_REQ_L

SMC_GFX_OVERTEMP

TP_DPMUX_UC_P11

TP_DPMUX_UC_P40

P3V3_S0GPU_PGOOD

EG_BKLT_EN

PM_ALL_GPU_PGOOD

P0V95_S0GPU_PGOOD PVDDCI_PGOOD

DPMUX_UC_TX

TP_DPMUX_UC_P83

TP_DPMUX_UC_P82

TP_DPMUX_UC_P81

GPUVCORE_PGOOD

NC_I2C_DPMUX_A_SDA

TP_DPMUX_UC_P17

DPMUX_UC_RESET_L

EG_RAIL1_EN

LCD_PWR_EN

EG_RAIL5_EN

EG_RAIL4_EN

DPMUX_UC_NMI

LCD_BKLT_PWM

LCD_BKLT_EN

DPMUX_UC_PEVREF

DPMUX_UC_PECI

DPMUX_UC_MD1

DPMUX_UC_MD2

DP_TBTSNK0_HPD_IG

EG_RESET_L

DP_INT_IG_HPD

DP_TBTSNK1_HPD_EG

SMC_GFX_SELF_THROTTLE

DP_TBTSNK1_HPD_IG

DP_TBTSNK0_HPD_EG

SMC_GFX_OVERTEMP

GFX_SELF_THROTTLE

DP_INT_EG_HPD

EG_RAIL3_EN

P0V95R1V8GPU_R_EN

GMUX_SLP_S3_BUF_L

LCD_MUX_SEL

PP3V3_S0

TBT_DDC_XBAR_EN_L

TP_DPMUX_UC_P96

DPMUX_UC_TDO

GMUX_SLP_S3_BUF_L

P1V8GPU_PGOOD

LCD_MUX_EN

DPMUX_UC_VCL

PP3V3_S3_DPMUX_UC_R MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3MM

DPMUX_UC_RESET_L

PP3V3_S0

DPMUX_LRESET_L

TP_DPMUX_UC_XTAL

DPMUX_UC_MD2

DPMUX_UC_MD1

DPMUX_UC_NMI

TP_DPMUX_UC_P80

DPMUX_UC_NMI

DPMUX_UC_TRST_L

DPMUX_UC_MD1

DPMUX_UC_TCK

PEG_CLKREQ_L

DPMUX_UC_CLK32K

DPMUX_UC_MD2

PP3V3_S0

DPMUX_UC_TDI

DPMUX_UC_TDO

LCD_MUX_SEL

DPMUX_UC_RESET_L

GPU_GFX_OVERTEMP

DPMUX_UC_TMS

LCD_MUX_EN

SMC_GFX_PWR_LEVEL_L

NC_I2C_DPMUX_A_SCL

MIN_LINE_WIDTH=0.3MM

PP3V3_S0_DPMUX_UC_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP3V3_S3

PP3V3_S0

DPMUX_UC_EXTAL

<SCH_NUM>

96 OF 119

82 OF 97

82

12 14 15 17 18 19 21 31 32 33 61 64 66 67 84 85 86 96

51 66 67 81 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

82

82 85

82

20 82

82 85

82

68 82

69 82 86

68 82

82

63 82

63 82 86

82

12 82 85

70 82 85

20 82

76 77 82

40 42 82

12 82 85

76 77 82

40 42 82

77 82

76 77 82

68 82

82

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

82

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

20 82

82

11 82 85

82

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48

49 51 52 55 66 67 68

69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

82

77 82

82

40 42 82

82

13 20 21 43 45 46 66 81 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

BI

IN

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

BI

IN

BI

IN

BI

IN

BI

IN

OUT BI

BI

OUT

IN

BI BI

IN

BI BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DP A & DP B AUX MUX

MUX TRUTH TABLE

SAI/SBI SAO SBO | INA INB

DP A & DP B DDC MUX

0 0 1 OUTB1 OUTA0 0 1 0 OUTB0 OUTA1

1 1 1 OUTA1 OUTB1

1 1 0 OUTA1 OUTB0

1 0 1 OUTA0 OUTB1

1 0 0 OUTA0 OUTB0

0 1 1 OUTB1 OUTA1

0 0 0 OUTB0 OUTA0

13

21

1112

15

14

6 7

8 9

20 19

18 17

3 4

1 2

5

10

16

U9700

TS3DS10224

QFN

28 89 97

82 83

13

21

1112

15

14

6 7

8 9

20 19

18 17

3 4

1 2

5

10

16

U9710

QFN

TS3DS10224

DDC_XBAR_MUX

28 89 97

82 83

12 85

76 77

12 85

76 77

12 85

82 83

82

2

1

R9710

5% 1/16W MF-LF

10K

402

2

1

R9740

NOSTUFF

MF

1/20W

1%

201

470K

2

1

R9750

1/20W

1%

470K

MF 201

NOSTUFF

2

1

R9720

470K

201

MF

1% 1/20W

NOSTUFF

2

1

R9730

470K

201

MF

1/20W

1%

NOSTUFF

31

32

2

1

R9753

470K

MF

1% 1/20W

201

2

1

R9754

470K

1% MF

1/20W 201

2

1

R9752

470K

1% 1/20W MF 201

2

1

R9751

470K

1% MF

201

1/20W

82 83

76 77 97

12 85 89

76 77 97

82 83

2

1

C9700

10V X7R-CERM 0402

0.1UF

20%

12 85 89

28 89 97

82 83

2

1

C9710

10V X7R-CERM 0402

0.1UF

20%

eDP Muxed Graphics Support

SYNC_DATE=10/15/2014

SYNC_MASTER=MARY_X425G

DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N

DP_EXTA_MUX_EN

DP_EXTB_MUX_SEL_EG

DPB_IG_AUX_CH_P DPB_IG_AUX_CH_N

DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P

DPA_IG_AUX_CH_P

DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK0_EG_AUXCH_P

DPB_EG_DDC_CLK

DP_EXTB_MUX_SEL_EG

DPB_EG_DDC_DATA

DP_EXTA_MUX_SEL_EG

DP_EXTB_MUX_EN

DP_TBTPB_DDC_DATA

DPA_EG_DDC_CLK

DP_EXTA_MUX_EN

DPA_IG_DDC_DATA

DPB_IG_DDC_CLK

DPA_EG_DDC_DATA

DPB_IG_DDC_DATA

DPA_IG_DDC_CLK

DP_TBTPA_DDC_CLK DP_TBTPA_DDC_DATA

DP_TBTPB_DDC_CLK

DP_EXTB_MUX_EN

DP_DDC_MUX_CROSSBAR_L

PP3V3_S0

DP_EXTA_MUX_SEL_EG

DPA_IG_AUX_CH_N

<SCH_NUM>

97 OF 119

83 OF 97

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 84 86 96

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

G3H/5V Rails TBT RAILS

"GPU" Rails

3.3V Rails

1.5V/1.35V/1.05V/VCORE/BKLT Rails

SYNC_DATE=05/30/2014

SYNC_MASTER=CLEAN_X305

Power Aliases

PP3V3_S4_TBT

PPVIN_S5_HS_GPU_ISNS

PPDCIN_G3H

PP3V42_G3H

PP0V95_S0GPU

PP1V35_GPU_REG

PP3V3_S0GPU

PP1V8_GPUIFPX

PP1V5_S0

PP3V3_S0GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM

PP1V8_GPUIFPX

MAKE_BASE=TRUE

VOLTAGE=1.8V

PPVTTDDR_S3

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=5V

PP1V35_S3RS0_CPUDDR

PP1V5_S0 PP1V5_S0

PP1V05_S0

PPBUS_SW_BKL

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU

MIN_NECK_WIDTH=0.25 MM

PP5V_S0

PP5V_S3

PPVRTC_G3H

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

PP5V_S3

MAKE_BASE=TRUE

PP5V_S0

PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H

PP3V3_S5

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

MIN_LINE_WIDTH=0.6 MM

PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

VOLTAGE=13.05V

MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_COMPUTING_ISNS

PP1V35_S3

PP1V8_GPUIFPX

PP3V3_S0GPU

PP1V5_S0

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=13.05V

PPVIN_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

VOLTAGE=13.05V

PPVIN_S5_HS_OTHER5V_ISNS

MIN_LINE_WIDTH=0.6 MM

PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_GPU_ISNS

PPVIN_S5_HS_OTHER5V_ISNS

PPBUS_S4_TPAD

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S4_TBT

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S5

PPVRTC_G3H

PP3V42_G3H

MAKE_BASE=TRUE

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

PPDCIN_G3H_ISOL

PPDCIN_G3H_ISOL PPDCIN_G3H_ISOL

PPDCIN_G3H

VOLTAGE=20V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H_ISOL

VOLTAGE=20V MAKE_BASE=TRUE

PPDCIN_G3H

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

PP5V_S4

MAKE_BASE=TRUE

PP1V05_SUS

PP5V_S4

PP5V_S3

PP5V_S0

PP5V_S3

PP5V_S4

PP3V3_S5

PP1V05_S0

PPVTT_S0_DDR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_OTHER3V3_ISNS

VOLTAGE=13.05V MAKE_BASE=TRUE

PPVIN_S5_HS_OTHER3V3_ISNS

PPVIN_S5_HS_OTHER5V_ISNS

PPVDDCI_S0_ISENSE

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.0V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVDDCI_S0_ISENSE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.12V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP0V95_S0GPU

PP1V35_GPU_REG

PP3V3_S0GPU

PPVIN_SW_TBTBST

VOLTAGE=12.8V

PP15V_TBT

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP15V_TBT

VOLTAGE=15V

PP3V3_S5

PPVTT_S0_DDR

PP1V05_S0

MIN_NECK_WIDTH=0.17 MM

PP1V35_S3_MEM

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.35V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_TBTLC

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_TBTLC

PP1V5_S0

PP1V35_S3_MEM

PP1V05_S0 PP1V05_S0

PP1V05_SUS

PPVCC_S0_CPU

MIN_LINE_WIDTH=2 MM

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

PPBUS_SW_BKL

PPVCC_S0_CPU

PP3V3_S0SW_SSD_R

PP3V3_S0SW_SSD

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.675V

PPVTTDDR_S3

PP1V5_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PPVTT_S0_DDR

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0SW_SSD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0SW_SSD_R

PPVCC_S0_CPU

PP1V05_S0

PP3V3_S5

PP1V35_S3

PP15V_TBT

PP1V35_S3

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.35V

PP1V35_S3RS0_CPUDDR

MIN_NECK_WIDTH=0.2 MM

PP1V35_S3

PP3V3_S5

MAKE_BASE=TRUE

VOLTAGE=1.35V

PP1V35_S3RS0_FET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V35_S3RS0_FET

MIN_NECK_WIDTH=0.17 MM

MIN_LINE_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V35_S3

VOLTAGE=1.35V

PP3V3_S5

PP1V35_S3_MEM

PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_OTHER3V3_ISNS

PPVIN_S4_TPAD

PPVIN_S5_HS_GPU_ISNS

PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H

PPBUS_G3H

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=13.05V

MIN_NECK_WIDTH=0.25 MM

PPVCORE_GPU

PP0V95_S0GPU

PPBUS_G3H

PP3V3_TBTLC

PP1V35_S3_MEM PP1V35_S3_MEM

PP1V35_S3RS0_CPUDDR

PP0V95_S0GPU

PP1V35_GPU_REG

PP1V5_S0

PP1V35_S3RS0_CPUDDR

PP1V35_GPU_REG

MAKE_BASE=TRUE

VOLTAGE=1.35V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V35_GPU_REG

PPVTT_S0_DDR

MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.4 mm

PPVTT_S0_DDR

PP1V05_S0

PPBUS_S4_TPAD

VOLTAGE=13.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPBUS_S4_TPAD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVIN_S4_TPAD

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=13.05V

PPVIN_S4_TPAD

PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS

PP3V3_S0GPU

PP1V5_S0

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PP0V95_S0GPU

MAKE_BASE=TRUE

VOLTAGE=0.95V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=3.3V

PP1V8_GPUIFPX

VOLTAGE=1.05V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0

PP3V3_S5

PP3V3_S4

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_SUS

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.075 MM

PP3V3_S3RS0_CAMERA

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S4 PP3V3_S4 PP3V3_S4

PP3V3_S4

PP3V3_S4 PP3V3_S4

PP3V3_S4

PP3V3_S4 PP3V3_S4

PP3V3_SUS PP3V3_SUS PP3V3_SUS

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S3RS0_CAMERA

PP3V3_S3

PP3V3_SUS

PP3V3_S5

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

GND

VOLTAGE=0V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.085 MM

<SCH_NUM>

100 OF 119

84 OF 97

28 29 30 45 84

47 73 79 80 84

56 57 84 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

70 71 73 78 84

47 71 72 73 74 75 84

47 66 68 71 72 76 77 79 80 84

71 76 78 80 84

11 12 13 15 17 19 52 64 67 81 84 86

47 66 68 71 72 76 77 79 80 84

71 76 78 80 84

60 84 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

6 8

10 21 66 67 84 96

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

63 84

6 8

10 45 59 84 86

18 19 36 49 58 59 62 63 66 67 73 79

80 84 85 86

21 36 60 66 67 84

86

11 12 15 19 84

61 66 84 86

21 36 60 66 67 84 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

19 34 37 38 40 41 42 43

50 56 57 67 84 86 19 34 37 38

40 41

42 43

50 56

57 67

84 86

12 14 15 17 18 19 21 31

32 33 61

64 66 67 82

84 85 86 96

30 44 47 56 57 63 65 84 86

44 58 59 60 62 84 44 58 59 60

62 84

21 45 60 66 84 86

71 76 78 80 84

47 66 68 71 72 76 77 79 80 84

11 12 13 15 17 19 52 64 67 81 84 86

47 73 79 80 84

44 58 59 60 62 84

44 61 84

44 58 59 60 62 84

47 73 79 80

84

44 61 84

45 65 84

28 29 30 45 84

61 66 84 86

11 12 15 19

84

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37

38 40 41 42 43 50 56 57 67 84

86

19 34 37 38 40 41 42 43 50 56

57 67 84

86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

11 12 15 19 84

44 56 57 84

56 57 84 86

44 56 57 84

56 57 84 86

37 38 51 61 66 67 69 81 84 86

18 64 84

37 38 51 61 66 67 69 81 84 86

21 36 60 66 67 84 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67 73 79

80 84

85 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67

73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67

73 79 80 84

85 86

18 19 36 49 58 59 62 63 66 67

73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

21 36 60 66 67 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67

69 81 84

86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82

84 85 86 96

10 14 15 17 18 41 62 67 84 86

21 27 60 84 86

44 61 84

71 80 84

47 71 79 84

71 80 84

70 71 73 78 84

47 71 72 73 74 75 84

47 66 68 71 72 76 77 79 80 84

30

30 31 32 84

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

21 27 60 84 86

10 14 15 17 18 41 62 67 84 86

22 23 24 25 26 27 45 84 92

19 20 28 29 84

11 12 13 15 17 19 52 64 67 81 84 86

22 23 24 25 26 27 45 84 92

10 14 15 17 18 41 62 67 84 86

18 64 84

6 8

10 45 59

84 86

63 84

6 8

10 45 59 84 86

45 66 84

34 45 84 86

60 84 86

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

21 27 60 84 86

34 45 84 86

45 66 84

6 8

10 45 59 84 86

10 14 15 17 18 41 62 67 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

21 45 60 66 84 86

30 31 32 84

21 45 60 66 84 86

6 8

10 21 66 67 84 96

21 45 60 66 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

66 84 66 84

21 45 60 66 84 86

22 23 24 25 26 27 45 84 92

44 58 59 60 62 84

44 61 84

38 45 84 86

47 73 79 80 84

30 44 47 56 57 63 65 84 86

47 71 79 84

70 71 73 78 84

30 44 47 56

57 63

65 84

86

22 23 24 25 26 27 45 84 92

6 8

10 21 66 67 84 96

47 71 72 73 74 75 84

11 12 13 15 17 19 52 64 67 81 84 86

6 8

10 21 66 67 84 96

47 71 72 73 74 75 84

21 27 60 84 86

10 14 15 17 18 41 62 67 84 86

45 65 84

38 45 84 86

47 73 79 80 84

47 66 68 71 72 76 77 79 80 84

11 12 13 15 17 19 52 64 67 81 84 86

70 71 73 78 84

47 66 68 71 72 76 77 79 80 84

71 76 78 80 84

18 64 84

10 14 15 17 18 41 62 67 84 86

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 14 15 17 18

19 21 31 32 33 61 64 66 67 82

84 85 86 96

12 14 15 17 18 19 21

31

32 33 61 64 66 67

82 84 85 86 96

12 14 15 17 18 19 21 31

32 33 61 64 66 67 82 84 85 86

96

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

20 33 38 41 42 45 46 65 66 67 81 84 85 86

11 12 13 14 15 17 50 64 66 67 84

13 20 21 43 45 46 66 81 82 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

13 20 35 46 84

20 33 38 41 42 45 46 65 66 67 81 84 85 86

20 33 38 41 42 45 46 65 66 67

81 84 85 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

20 33 38 41 42 45

46 65 66 67 81 84

85 86

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 50 64 66 67

84

11 12 13 14 15 17 50 64 66 67 84

13 20 21 43 45 46 66 81 82 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34

43

44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34

43

44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47

48 49 51 52 55 66 67 68 69 82

83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68

69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67

68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66 67 68 69 82 83 84 86 96

13 20 35 46 84

13 20 21 43 45 46 66 81 82 84 86

11 12 13 14 15 17 50 64 66 67 84

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Display Aliases

J9510 RIO FLEX CONN

MAKE_BASE

Unused PCH PCIE Lanes

NO_TEST

Thunderbolt Signals Through PEG

Unused signals

EDP CABLE

Unused TPAD SPI

MAKE_BASE

VOLTAGE

GUP PEG Lanes

CPU signals

SSD Signals Through PEG

21

XWA202

SM

21

XWA203

SM

5

28 89

5

28 89

5

28 89

5

28 89

21

RA201

1/20W

0

MF

5%

0201

21

RA202

NOSTUFF

0

5%

1/20W

MF

0201

2 1

RA298

100K

1/20W

201

1% MF

2 1

RA296

1%

1/20W

100K

MF

201

2 1

RA299

1%

201

100K

1/20W

MF

2 1

RA297

201

100K

1/20W

MF

1%

2 1

RA294

100K

MF

1%

1/20W

201

2 1

RA295

100K

1/20W

1% MF

201

5

34 89

5

34 89

5

34 89

5

34 89

I1490

Signal Aliases

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MEMVTT_EN

DPA_IG_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_IG

MAKE_BASE=TRUE

DPB_IG_AUX_CH_P

EG_RESET_L

MAKE_BASE=TRUE

TP_DP_IG_A_MLP<3..0>

MAKE_BASE=TRUE

DP_INT_IG_AUX_P

DPB_IG_AUX_CH_P

PEG_CLK100M_P

EDP_IG_PANEL_PWR

MAKE_BASE=TRUE

DPA_IG_AUX_CH_P

MAKE_BASE=TRUE

DP_INT_IG_AUX_N

PEG_CLK100M_N

LCD_FSS

MAKE_BASE=TRUE

LCD_FSS

DP_AUXCH_ISOL_L

MAKE_BASE=TRUE

DP_AUXCH_ISOL_L

PEG_CLKREQ_LPEG_CLKREQ_L

MAKE_BASE=TRUE

DPMUX_UC_TX

MAKE_BASE=TRUE

DPB_IG_AUX_CH_N

DPA_IG_AUX_CH_N

MAKE_BASE=TRUE

DP_INT_IG_ML_N<3..0>

MAKE_BASE=TRUE

DP_INT_IG_ML_P<3..0>

MAKE_BASE=TRUE

EDP_IG_BKL_ON

MAKE_BASE=TRUE

DPA_IG_DDC_CLK

MAKE_BASE=TRUE

=PEG_D2R_P<7..0>

TP_DP_IG_A_MLN<3..0>

PP0V75_S3_MEM_VREFCA

0.675V

TRUE

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

0.675V

TRUE

0.675V

TRUE

PP0V75_S3_MEM_VREFDQ_B

PP5V_S0

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.4MM

PP5V_S0_AUDIO_AMP_L

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

TPAD_SPI_MOSI

TPAD_SPI_INT_L TPAD_SPI_MISO

TPAD_SPI_CS_L

TPAD_SPI_SCLK

TPAD_SPI_BUS_EN TPAD_SPI_BUS_EN

TRUE

TPAD_SPI_MISO

TRUE

TPAD_SPI_SCLK

TPAD_SPI_MOSI

TRUE

TPAD_SPI_CS_L TPAD_SPI_INT_L

TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

I2C_BKLT_SCL

I2C_BKLT_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

I2C_BKLT_SDA

MAKE_BASE=TRUE

I2C_BKLT_SCL

MAKE_BASE=TRUE

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_B

TBT_GO2SX_BIDIR

BT_PWRRST_L MEM_VDD_SEL_1V5_L FW_PWR_EN_PCH WOL_EN FW_PME_L DP_TBT_SEL ENET_MEDIA_SENSE_RDIV AUD_IPHS_SWITCH_EN_PCH AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L

ENET_CLKREQ_L ENET_LOW_PWR_PCH HDMITBTMUX_SEL_TBT

PP3V3_S3_FAN_CTL

PP3V3_S4

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3_FAN_CTL

PP3V3_S5

LPCPLUS_GPIO

SDCONN_OC_L

PEG_CLKREQ_L

DPMUX_UC_IRQ

MEMVTT_EN

MAKE_BASE=TRUE

=PEG_R2D_C_P<15..12>

=PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

MAKE_BASE=TRUE

PCIE_SSD_D2R_P<3..0>

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<3..0> PCIE_SSD_R2D_C_P<3..0>

MAKE_BASE=TRUE

=PEG_R2D_C_N<15..12>

=PEG_D2R_P<11..8> =PEG_D2R_N<11..8> =PEG_R2D_C_P<11..8> =PEG_R2D_C_N<11..8>

MAKE_BASE=TRUE

PEG_D2R_P<7..0> PEG_D2R_N<7..0>

MAKE_BASE=TRUE

=PEG_D2R_N<7..0>

PEG_R2D_C_N<7..0>

MAKE_BASE=TRUE

=PEG_R2D_C_N<7..0>

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

=PEG_R2D_C_P<7..0>

PCIE_SSD_R2D_C_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0> PCIE_TBT_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

MAKE_BASE=TRUE

=PCIE_SSD_D2R_P<3..0>

TRUE TRUE

NC_PCIE_SSD_D2RN<3..0>

=PCIE_SSD_D2R_N<3..0>

TRUE TRUE

NC_PCIE_SSD_R2D_CN<3..0>

=PCIE_SSD_R2D_C_N<3..0>

TRUE TRUE

NC_PCIE_SSD_R2D_CP<3..0>

=PCIE_SSD_R2D_C_P<3..0>

TRUETRUE

NC_PCIE_SSD_D2RP<3..0>

PEG_CLK100M_N

MAKE_BASE=TRUE

DPB_IG_DDC_CLK

DP_INT_IG_AUX_P

MAKE_BASE=TRUE

PEG_CLK100M_P

DPMUX_UC_RX

DP_TBTSNK1_HPD_IG

DP_TBTSNK0_HPD_IG

MAKE_BASE=TRUE

DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N

DP_INT_IG_AUX_N

MAKE_BASE=TRUE

VSNS_GPU_VDDI_P

EDP_IG_BKL_ON

DPA_IG_AUX_CH_P

MAKE_BASE=TRUE

DPA_IG_DDC_DATA

MAKE_BASE=TRUE

DPB_IG_DDC_CLK

MAKE_BASE=TRUE

DPB_IG_DDC_DATA

DPMUX_UC_TX

EG_RESET_L

DPB_IG_AUX_CH_N

MAKE_BASE=TRUE

DPMUX_UC_RX

SMBUS_PCH_CLK

SMBUS_PCH_DATA SMBUS_PCH_DATA

SMBUS_PCH_CLK

DPB_IG_DDC_DATA

VSNS_GPU_VDDI_P

VSNS_GPU_VDDC_P

MAKE_BASE=TRUE

VSNS_GPU_VDDC_P

EDP_IG_PANEL_PWR

DP_TBTSNK0_HPD_IG

PP3V3_S4

<SCH_NUM>

102 OF 119

85 OF 97

21 60 85

12 83 85

12 82 85

12 83 85 89

70 82 85

5

82 85 97

12 83 85 89

11 70 85 91

12 82 85

12 83 85 89

5

82 85 97

11 70 85 91

69 82 85 86 69 82 85 86

11 18 85 11 18 85

11 82 85 11 82 85

82 85

12 83 85 89

5

82 97

5

82 97

12 82 85

12 83 85

5

22 23 24 25 26 85 89 92

22 23 24 85 89 92 22 23 24 85 89 92

22 25 26 85 89

18 19 36 49 58 59 62 63 66 67 73 79 80 84 86

53

38 85 91

38 85

38 85 91

38 85

38 85 91

38 85

36 40 43 48 69 76 85 86 95

63 69 85 86

36 40 43 48 69 76 85 86 95

63 69 85 86

22 23 24 25 26 85 89 92

22 25 26 85 89

14

12

14

11

12

11

12

28

49 85

20 33 38 41 42 45 46 65 66 67 81 84 85 86

49 85

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 86 96

14

12

11 82 85

14 82

21 60 85

70 89

5

68 70 89

5

68 70 89

5

13

11 70 85 91

12 83 85

5

82 85 97

11 70 85 91

82 85

12 82 85

12 83 85

12 83 85 89

5

82 85 97

71 80 85 96

12 82 85

12 83 85 89

12 83 85

82 85

70 82 85

12 83 85 89

82 85

13 18 43 81 85 86 91

13 18 43 81 85 86 91 13 18 43 81 85 86 91

13 18 43 81 85 86 91

12 83 85

71 80 85 96

71 79 85 96 71 79 85 96

12 82 85

20 33 38 41 42 45 46 65 66 67 81 84 85 86

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2X

4X 4X

2X

J9500 - rio coax

J4002 - Camera

J6602 - L speaker

J6603 - R speaker

XDP

FUNC_TEST

J4801 - ipd flex

J6100 - spi

FUNC_TEST

J4813 - keyboard

J8300 - eDP

3X

16X

J9510 - rio flex

5X

3X

10X

J6050 - left fan

J5150 - hall effect

J3501 - airport

J6601 - mic

2X

J4915 - kbd bklt

J6060 - right fan

5X

3X

3X 5X

19X

2X GND

J7000 - DC PWR

J7050 - battery

8X

2X 2X

2X

FUNC_TEST

4X

Power Rails

FUNC_TEST

Power Sequence

Functional Test Points

GPU_VENUS JTAG

FUNC_TEST

I1929

I1930

I1931 I1932

I1934

I1935

I1936

I1938 I1939

I1940

I1941

I1942

I1943

I1944

I1948 I1949

I1950

I1951 I1952

I1953

I1954

I1955

I1956

I1957 I1958

I1959 I1960

I1961

I1962 I1963

I1965

I1966

I1967

I1968

I1969

I1970 I1971

I1972

I1973 I1974

I2004

I2005

I2006

I2007

I2008

I2009

I2010

I2011

I2012

I2013

I2014

I2015

I2016

I2017

I2018

I2019

I2020

I2021

I2022

I2023

I2024

I2025

I2026

I2027

I2028

I2029

I2030

I2032

I2033

I2034

I2035

I2036

I2037

I2038

I2039

I2040

I2041

I2042

I2043

I2044

I2045

I2047

I2048

I2049 I2050

I2051

I2052

I2053

I2067

I2068

I2069

I2070

I2071

I2072 I2073

I2074

I2075 I2076

I2077

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

Functional Test Points

HDMI_EG_DATA_N<1>

TRUE

HDMI_EG_CLK_N

TRUE

HDMI_EG_CLK_P

TRUE

LCD_BKLT_EN

TRUE

GPU_JTAG_TCK GPU_JTAG_TDI

TRUE

GPU_JTAG_TDO

TRUE

GPU_JTAG_TMS

TRUE

GPU_JTAG_TRST_L

TRUE

GPU_PWRGOOD

TRUE

DP_INT_AUX_N

TRUE

DP_INT_AUX_P

TRUE

USB3_EXTB_R2D_P

CAM_SENSOR_WAKE_L_CONN

TRUE

MIPI_DATA_CONN_N

TRUE

CPU_CFG<3>

TRUE

PM_SYSRST_L

TRUE

PM_RSMRST_L

TRUE

PM_PCH_PWROK

PP3V3_S5_AVREF_SMC

TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

TRUE

PP20V_DCIN_FUSE

TRUE

ADAPTER_SENSE

SPKRCONN_SR_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_SL_OUT_P

TRUE

DMIC_SDA2

WS_LEFT_OPTION_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD7

WS_KBD3

TRUE

WS_KBD23

TRUE

WS_KBD22

TRUE

WS_KBD20

TRUE

WS_KBD19

TRUE

WS_KBD17 WS_KBD18

TRUE

WS_KBD16_NUM

TRUE

WS_KBD15_CAP

WS_KBD14

TRUE

WS_KBD12

TRUE

WS_KBD11

TRUE

WS_KBD10

USB_BT_CONN_P

TRUE

PCIE_AP_D2R_PI_N

TRUE

PPVOUT_S0_KBDBKLT

TRUE

KBDBKLT_RETURN2

TRUE

WS_LEFT_SHIFT_KBD

PPVTT_S0_DDR

TRUE

PP1V35_S3

TRUE

PP1V5_S0

XDP_PCH_TMS

TRUE

PM_DSW_PWRGD

TRUE

ALL_SYS_PWRGD

TRUE

PM_PCH_SYS_PWROK

TRUE

PLT_RESET_L

TRUE

LCD_PWR_EN

TRUE

SMC_ONOFF_L

TRUE

PCIE_AP_R2D_P

MIPI_DATA_CONN_P

TRUE

SMC_LID_R

TRUE

FAN_LT_PWM

TRUE

PP5V_S0

PP5V_S3RS0_ALSCAM_F

TRUE

HDMI_EG_DATA_N<2>

USB3_EXTB_D2R_P

TRUE

USB3_EXTB_D2R_N

USB_EXTB_N

TRUE TRUE

USB_EXTB_P

HDMI_EG_DATA_P<0>

TRUE

KBDBKLT_RETURN1

TRUE

DMIC_SDA3

TRUE

DMIC_CLK3

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_L_OUT_N

TRUE

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

TRUE

PPVBAT_G3H_CONN

TRUE

PP1V05_S0

TRUE

PP3V42_G3H

FAN_RT_PWM

TRUE

FAN_LT_TACH

TRUE

SYS_DETECT_L

TRUE

AP_CLKREQ_Q_L

TRUE

PP5V_S3

TRUE

PP3V42_G3H

TRUE

WS_KBD6

TRUE

WS_KBD5

WS_KBD4

TRUE

PP3V3_S0SW_SSD

TRUE

PPVTTDDR_S3

PPVCC_S0_CPU

TRUE

PPDCIN_G3H

TRUE

PPBUS_G3H

TRUE

PP5V_S5

TRUE

PP3V3_S5

PM_SLP_S3_L

TRUE

FAN_RT_TACH

WS_KBD2

TRUE

WS_KBD21

USB3_SD_R2D_C_P

TRUE

PP5V_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S4

TRUE

USB_EXTB_OC_L

SMBUS_PCH_DATA

TRUE

PM_SLP_S3_BUF_L

TRUE

RIO_SDCONN_STATE_CHANGE_L

TRUE

PP5V_S4

TRUE

PM_SLP_S4_L

TRUE

SMBUS_PCH_CLK

TRUE

HDMI_HPD

TRUE

HDMI_DDC_DATA

TRUE

HDMI_DDC_CLK

TRUE

SD_PWR_EN

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP5V_S0

DP_INT_ML_P<3>

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PP5VR3V3_SW_LCD

TRUE

I2C_BKLT_SCL

I2C_BKLT_SDA

TRUE

LCD_BKLT_PWM_R SMBUS_SMC_0_S0_SDA

TRUE TRUE

SMBUS_SMC_0_S0_SCL

TRUE

LCD_HPD_CONN

DP_INT_ML_P<2>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_N<3>

DP_INT_ML_N<1>

TRUE TRUE

DP_INT_ML_N<2>

DP_INT_ML_N<0>

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

USB_BT_CONN_N

TRUE

PCIE_AP_D2R_PI_P

TRUE

SMC_RESET_L

PP3V42_G3H

TRUE

AP_RESET_CONN_L

TRUE

LCD_FSS

TRUE

USB3_EXTB_R2D_N

USB3_SD_R2D_C_N

TRUE

XDP_PCH_TDO

XDP_PCH_TDI

TRUE

XDP_CPU_TMS

TRUE

XDP_CPUPCH_TRST_L

TRUE

XDP_CPU_TDI

XDP_CPU_TCK

TRUE

SPKRCONN_R_ID

MIPI_CLK_CONN_N

TRUE

XDP_PCH_TCK

TRUE

XDP_CPU_TDO

TRUE

PCIE_AP_R2D_N

SPKRCONN_L_ID

TRUE

PP3V3_S0

TRUE

PP3V3_WLAN

PCIE_WAKE_L

TRUE

WIFI_EVENT_L

TRUE

MIPI_CLK_CONN_P

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

HDMI_EG_DATA_N<0>

TRUE

HDMI_EG_DATA_P<2>

TRUE

USB3_SD_D2R_N

TRUE

USB3_SD_D2R_P

TRUE

HDMI_EG_DATA_P<1>

TRUE

PP3V3_S4

TRUE TRUE

PP3V42_G3H WS_CONTROL_KBD

TRUE

WS_KBD13

TRUE

WS_KBD1

TRUE

USB_TPAD_P

TRUE

USB_TPAD_N

TRUE

IOXP2_INT_L

TRUE

I2C_IOXP_SCL

TRUE

I2C_IOXP_SDA

TRUE

SMC_PME_S4_WAKE_L

TRUE

TPAD_ACTUATOR_THRMTRIP_L TPAD_VBUS_EN

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

SMC_LID

TRUE TRUE

SMC_ACTUATOR_EN_L PPVIN_S4_TPAD

TRUE TRUE

GND_ACTUATOR PP3V3_S4

TRUE

PP5V_S4

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PP3V3_S3RS4_BT_F

TRUE

SMC_TCK

TRUE

SMC_TMS

TRUE

SPIROM_USE_MLB

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

<SCH_NUM>

104 OF 119

86 OF 97

76 81 97

63 82

76 77

69 97

81 90

36

36 94

6

18 89

12 19 40 91

12 67 91

12 19 91

40 41

40 43 56 57 95

56

53 55 96

55

38

33 90

91

39 63

38

21 27 60 84

21 45 60 66 84

11 12 13 15 17 19 52 64 67 81 84

11 18

12 40 91

18 19 40 58 67

12 18 19 40 91

12 18 20 21

69 82

38 40 41

33 91

36 94

42

49

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

36

76 81 97

13 81 90

76 81 97

39 63

52 55

53 55 96

6

18 89

6

18 89

56 57

10 14 15 17 18 41 62 67 84

19 34 37 38 40 41 42 43 50 56 57 67 84 86

49

56

33

21 36 60 66 67 84

19 34 37 38 40 41 42 43 50 56 57 67 84 86

38

34 45 84

60 84

6 8

10 45 59 84

56 57 84

30 44 47 56 57 63 65 84

61 66 84

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 96

12 21 40 67

49

38

13 20 81 91

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

13 20 21 43 45 46 66 81 82 84 86

20 33 38 41 42 45 46 65 66 67 81 84 85 86

18 81

13 18 43 81 85 91

51 66 67 81 82

20 81

37 38 51 61 66 67 69 81 84 86

12 21 33 37 40 67 81

13 18 43 81 85 91

20 81 82

13 18 81

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

13 20 21 43 45 46 66 81 82 84 86

18 19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

69 97

63 69

69

63 69 85

63 69

36 40 43 48 69 76 85 86 95

69

69 97

33 91

33 90

91

40 41 50 57

19 34 37 38 40 41 42 43 50 56 57 67 84 86

33

69 82 85

81 90

13 20 81 91

11 18

6

18 89

6

18 89

6

18 89

6

18 89

52 55

36 94

11 18

6

18 89

33 91

52 55

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

33 41

12 33 35 91

33 40 41

36 94

36 40 43 48 69 76 85 86 95

35 36

76 81 97

13 20 81 91

76 81 97

20 33 38 41 42 45 46 65 66 67 81 84 85 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

38

13 38 90

38

33 38 40 42

38 65

38 67

38 40 43 95

38 40 41 42

38 40

38 45 84

38

20 33 38 41 42 45 46 65 66 67 81 84 85 86

37 38 51 61 66 67 69 81 84 86

33 91

33

40 41 50

14 50

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH

NO_TEST NO_TEST

Thunderbolt

PLACEABLE BEAD-PROBES FOR TBT

MAKE_BASE

NC NO_TESTs

MAKE_BASE

1

BPA532

SM

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

1

BPA531

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

I1975

I1976

I1977

I1978

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

NC & No Test

NC_PCIE_CLK100M_SWP

NC_USB_4N

TRUE TRUE

NC_DVPCNTL_M<1..0>

TRUETRUE

NC_FB_A0_A<9>NC_FB_A0_A<9>

NC_FB_A1_A<9>

TRUE TRUE

NC_FB_A1_A<9>

TRUE TRUE

NC_FB_B1_A<9>

TRUE TRUE

NC_FB_B0_A<9>

NC_FB_B1_A<9>

NC_FB_B0_A<9>

NC_SATA_B_D2RP

TRUE TRUE

NC_SATA_B_R2D_CN

TRUETRUE

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO67_CLKOUTFLEX3

NC_USB_4P

TRUETRUE

NC_PCIE_CLK100M_PEGBP

NC_PCH_GPIO66_CLKOUTFLEX2

NC_USB_4P

NC_PCH_GPIO67_CLKOUTFLEX3

TRUETRUE

TRUE

NC_SATA_ODD_D2RN

TRUE

NC_SATA_ODD_D2RP

TRUE TRUE TRUE TRUE

NC_SATA_ODD_R2D_CN

NC_PCIE_CLK100M_ENETSDN

NC_PCIE_CLK100M_PEGBN

NC_PCIE_CLK100M_SWN

NC_USB_4N

TRUETRUE

TRUE TRUE

NC_DVPCNTL<2..0> NC_DVPCLK

TRUETRUE

TRUE TRUE

NC_DVPDATA<23..6>

TP_NC_DVPDATA<23..6>

NC_USB3_SPARE_D2RN

TRUE TRUE

NC_USB3_SPARE_D2RP

TRUE TRUE

TRUE

NC_USB3_SPARE_R2D_CN

TRUE

NC_USB3_SPARE_R2D_CN NC_USB3_SPARE_R2D_CP

TRUE TRUE

NC_SATA_D_R2D_CP

TP_DVPCNTL_M<1..0> TP_DVPCNTL<2..0> NC_DVPCLK

TRUE TRUE

NC_USB3_EXTC_R2D_CP NC_USB3_EXTD_D2RN

TRUE TRUE

TRUETRUE

NC_USB3_EXTD_D2RP

NC_PCIE_CLK100M_ENETSDN

TRUE TRUE

NC_TBT_XTAL25OUT

TRUETRUE

NC_DP_IG_D_AUXCHN NC_DP_IG_D_AUXCHP

NC_PCIE_CLK100M_PE5P

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

NC_DP_TBTSRC_AUXCH_CP

NC_TBT_XTAL25OUT

TP_DP_TBTSRC_ML_CP<3..0> TP_DP_TBTSRC_ML_CN<3..0>

NC_PCIE_CLK100M_PE5N

TRUE TRUE TRUE TRUE

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_ENETSDP

TRUE TRUE

NC_PCIE_CLK100M_ENETN

TRUETRUE

NC_SATA_F_D2RP

TRUETRUE

NC_DP_TBTSRC_AUXCH_CN

NC_USB3_EXTC_D2RP

TRUE TRUE

NC_CLINK_DATA

TRUE

NC_CLINK_RESET_L

TRUE

TRUE TRUE

NC_LPC_CLK33M_LPCPLUS_RNC_LPC_CLK33M_LPCPLUS_R

NC_CLINK_RESET_L

NC_PCI_PME_L

NC_ITPXDP_CLK100MP

NC_ITPXDP_CLK100MN

TRUE TRUE

NC_USB_PSOCP

TRUE TRUE

NC_USB_7N

TRUE

NC_USB_WLANP

TRUE

PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0>

TRUE

PCIE_TBT_D2R_C_P<3..0>

TRUE

NC_SATA_ODD_R2D_CP

TRUETRUE

NC_PCIE_ENET_R2D_CP

TRUE

NC_PCIE_ENET_D2RN

TRUE

TRUETRUE

NC_DP_TBTSRC_ML_CN<3..0>

NC_SATA_A_D2RN

NC_SATA_A_R2D_CN NC_SATA_A_R2D_CP NC_SATA_B_D2RN NC_SATA_B_D2RP

NC_SATA_B_R2D_CP

NC_SATA_B_R2D_CN

NC_SATA_F_D2RN

NC_USB3_SPARE_D2RP

NC_USB3_EXTC_D2RN

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_D2RP

NC_USB3_EXTD_D2RN

NC_USB3_EXTD_R2D_CN NC_USB3_EXTD_R2D_CP

NC_PCIE_ENET_D2RN NC_PCIE_ENET_D2RP

NC_PCIE_ENET_R2D_CP

NC_SMC_INTERFACE_2

NC_SATA_D_R2D_CN

TRUE TRUE

NC_PCIE_CLK100M_SWN

TRUE

DMI_N2S_N<3..1>

TRUE

DMI_S2N_N<3..1>

TRUE

DMI_S2N_P<3..1>

PCIE_TBT_D2R_C_N<3..0>

TRUE

NC_DP_TBTSRC_ML_CP<3..0>

TRUETRUE

TRUE TRUE

NC_DP_TBTSRC_AUXCH_CP

TRUETRUE

NC_USB3_EXTD_R2D_CN

NC_PCH_GPIO64_CLKOUTFLEX0

TRUETRUE

NC_USB3_EXTC_D2RN

TRUE TRUE

NC_DP_TBTSRC_AUXCH_CN

NC_SATA_D_D2RN

TRUE TRUE

NC_SATA_F_R2D_CN

TRUETRUE

TRUE

NC_USB_SDP

TRUE

NC_LPC_DREQ0_L

TRUE TRUE TRUE TRUE

NC_CLINK_CLK

NC_USB_SMCP

TRUETRUE

NC_USB_SMCN

TRUE TRUE

TRUETRUE

NC_SATA_B_R2D_CP

TRUETRUE

NC_SATA_B_D2RN

NC_SATA_A_R2D_CP

TRUETRUE

NC_USB3_EXTD_R2D_CP

TRUETRUE

NC_USB3_EXTC_R2D_CN

TRUETRUE

NC_SATA_A_R2D_CN

TRUETRUE

NC_SATA_A_D2RN

TRUETRUE

NC_SMC_INTERFACE_2

TRUE TRUE

NC_ITPXDP_CLK100MP

TRUETRUE

NC_USB_SMCN

NC_USB_SMCP

NC_PCIE_CLK100M_SWP

TRUETRUE

NC_PCIE_CLK100M_PEGBP

TRUE TRUE

NC_PCIE_CLK100M_ENETP

TRUE TRUE

NC_SATA_D_D2RP

NC_SATA_F_R2D_CP

TRUETRUE

NC_HDA_SDIN3

TRUE TRUE

NC_SATA_D_D2RN

TRUETRUE

NC_PCIE_ENET_D2RP

NC_USB_SDN

NC_USB_EXTCN

NC_SATA_F_R2D_CP

NC_SATA_F_R2D_CN

TRUETRUE

NC_SATA_D_D2RP

NC_PCIE_ENET_R2D_CN

TRUETRUE

NC_SATA_A_D2RP

NC_SATA_ODD_D2RN

NC_USB3_SPARE_D2RN

NC_SATA_A_D2RP

TRUETRUE

TRUE TRUE

NC_SATA_ODD_R2D_CP

NC_SATA_D_R2D_CN

TRUE TRUE

NC_SATA_F_D2RN

NC_USB3_SPARE_R2D_CP

TRUE TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUETRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE TRUE

TRUE

NC_USB_EXTCN

TRUE TRUE TRUE

NC_USB_EXTCP

TRUETRUE

NC_USB_SDN

TRUE

NC_USB_6N

TRUE

NC_USB_IRN NC_USB_IRP

NC_USB_PSOCN

NC_USB_EXTDP

NC_USB_EXTDN

NC_PCIE_CLK100M_ENETN NC_PCIE_CLK100M_ENETP

NC_PCIE_CLK100M_ENETSDP

TRUE

NC_DP_IG_D_AUXCHN

TRUE

NC_PCIE_CLK100M_PE5N

TRUE TRUE

NC_USB_6P

NC_DP_IG_D_AUXCHP

TRUE TRUE

NC_USB_EXTCP

NC_SATA_D_R2D_CP

NC_SATA_ODD_R2D_CN

NC_SATA_ODD_D2RP

TRUETRUE

NC_PCIE_CLK100M_PEGBN

TRUE

DMI_N2S_P<3..1>

NC_PCIE_ENET_R2D_CN

NC_USB3_EXTC_R2D_CN

TRUE TRUE

NC_USB3_EXTC_D2RP

NC_EDP_IG_BKL_PWM

TRUE TRUE

NC_HDA_SDIN2

NC_PCI_PME_L

TRUETRUE

NC_USB_IRP

TRUETRUE

TRUE TRUE

NC_USB_7P

NC_SATA_F_D2RP

NC_USB_7P

TRUE

NC_EDP_IG_BKL_PWM

TRUE

NC_CLINK_DATA

NC_CLINK_CLK

NC_LPC_DREQ0_L

NC_HDA_SDIN3

NC_HDA_SDIN1 NC_HDA_SDIN2

TRUE TRUE

NC_HDA_SDIN1

TRUE TRUE

NC_PCI_CLK33M_OUT3NC_PCI_CLK33M_OUT3

NC_USB_EXTDP

TRUETRUE

TRUE

NC_USB_IRN

TRUE

NC_USB_EXTDN

TRUE TRUE

NC_ITPXDP_CLK100MN

NC_USB_SDP NC_USB_WLANN

TRUETRUE

NC_USB_WLANN NC_USB_WLANP NC_USB_6N NC_USB_6P NC_USB_7N

TRUE

NC_USB_PSOCP

TRUE

NC_USB_PSOCN

TRUE TRUE

<SCH_NUM>

105 OF 119

87 OF 97

11 87

13 87

76

72 87 72 87

72 87

11 87 90

11 87

13 87

11 87

13 87

11 87

13 87

76

76 87

76

13 87

13 87 13 87

13 87

11 87

76 87

13 87 90

11 87

28 87

12 87

11 87

28 31 93

28 87

11 87

28 87

13 87 90

13 87

11 87 91 11 87 91

13 87

12 87

11 87 89

13 87

13 87 90

13 87

28 89

11 87

87

28

11 87 90

11 87

13 87

13 87 90

87

11 87

5

12 89

5

12 89

5

12 89

28 89

28

28 87

13 87 90

11 87

13 87 90

28 87

11 87

13 87 90

13 87

87 90

11 87 90

13 87 90

11 87 90

87

11 87 89

87 90

11 87

87

13 87 90

11 87

87

11 87 90

11 87

13 87

11 87 90

11 87

13 87

11 87

13 87 90

13 87

13 87 90

11 87

12 87

11 87

13 87 90

12 87

13 87 90

11 87

11 87 11 87

5

12 89

87

13 87 90

12 87

11 87

12 87

13 87 90

11 87

13 87 90

12 87

13 87

11 87

11 87 11 87

13 87 90

11 87 89

13 87 90

13 87 13 87

13 87

13 87 90

13 87

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

X425G BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.

Stackup-Defined Spacing Rules

?

DEFAULT

*

0.1 MM

?

STANDARD

*

=DEFAULT

=STANDARD

0.1 MM 0.1 MM

=STANDARD

* Y

1:1_DIFFPAIR

=STANDARD

BGA

* *

P072_SPACE

0.058 MM

?

TOP,BOTTOM

1x_DIELECTRIC

*

?

0.075 MM

P075_SPACE

*

P65BGA

P65_BGA

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

?

0.101 MM

1X_DIELECTRIC

P075_SPACE

**

P65BGA

*

?

0.1 MM

BGA_P1MM

?

0.2 MM

*

BGA_P2MM

?

*

0.071 MM

P072_SPACE

*

0.1 MM

1:1_SPACING

?

0.092 MM0.092 MM

0.120 MM

ISL2,ISL11

Y

80_OHM_DIFF

0.120 MM

=STANDARD=STANDARD

=STANDARD

85_OHM_DIFF

=STANDARD

N =STANDARD*

0.200 MM

0.078 MM0.078 MM

ISL2,ISL11

90_OHM_DIFF

Y

0.200 MM

0.200 MM 0.200 MM

0.078 MM 0.078 MM

90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

=STANDARD=STANDARD =STANDARD

=STANDARD=STANDARD* N

90_OHM_DIFF

0.080 MM0.080 MM

85_OHM_DIFF

0.120 MM0.120 MM

ISL2,ISL11

Y

0.080 MM0.080 MM

Y

85_OHM_DIFF

0.120 MM 0.120 MM

ISL3,ISL4,ISL9,ISL10

1x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10

?

0.053 MM

P65_BGA

0.126MM0.075MM

* Y

0.071MM0.071MM

0.180 MM 0.180 MM

0.101 MM0.101 MM

Y

90_OHM_DIFF

TOP,BOTTOM

0.105 MM0.105 MM

Y

0.125 MM

85_OHM_DIFF

TOP,BOTTOM

0.125 MM

0.155 MM

0.125 MM

TOP,BOTTOM

80_OHM_DIFF

Y

0.155 MM

0.092 MM

ISL3,ISL4,ISL9,ISL10

0.092 MM

80_OHM_DIFF

Y

0.120 MM0.120 MM

=STANDARD

80_OHM_DIFF

N* =STANDARD

=STANDARD =STANDARD

0.146 MM

72_OHM_DIFF

TOP,BOTTOM

0.120 MM 0.120 MM

0.146 MM

Y

ISL2,ISL11

0.120 MM

Y

72_OHM_DIFF

0.120 MM

0.105 MM 0.105 MM

0.105 MM0.105 MM

0.120 MM

72_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.120 MM

=STANDARD

72_OHM_DIFF

=STANDARD* N =STANDARD

=STANDARD=STANDARD

0.186 MM

27P4_OHM_SE

=STANDARD

0.1 MM

Y* =STANDARD

=STANDARD

0.265 MM

27P4_OHM_SE

TOP,BOTTOM

0.095 MM

Y

0.095 MM 0.095 MM

50_OHM_SE

TOP,BOTTOM

Y

0.066 MM

50_OHM_SE

*

=STANDARD

=STANDARD =STANDARDY

0.066 MM

=STANDARD* Y =STANDARD

=STANDARD45_OHM_SE

0.083 MM0.083 MM

0.090 MM0.102 MM

40_OHM_SE

Y* =STANDARD=STANDARD

=STANDARD

0.090 MM0.118 MM

* Y

37_OHM_SE =STANDARD

=STANDARD =STANDARD

0.095 MM

Y

37_OHM_SE

TOP,BOTTOM

0.165 MM

0 MM0 MM

Y

DEFAULT

*

=45_OHM_SE 10 MM=45_OHM_SE

TOP,BOTTOM

45_OHM_SE

Y

0.116 MM 0.116 MM

0.145 MM 0.095 MM

Y

TOP,BOTTOM

40_OHM_SE

=DEFAULT

*

=DEFAULT

Y

=DEFAULTSTANDARD =DEFAULT

10 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

16.2

NO_TYPE,BGA,P65BGA

MM

PCB Rule Definitions

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

<SCH_NUM>

110 OF 119

88 OF 97

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DP / HDMI NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

Most CPU signals with impedance requirements are 50-ohm single-ended.

NET_TYPE

SPACING

Spacing Rule Sets

SOURCE: IVB PLATFORM DG , Tables 205-207

Some signals require 27.4-ohm single-ended impedance.

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

CPU Net Properties

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04. MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

DIGITAL VIDEO SIGNAL CONSTRAINTS

CPU Signal Constraints

PEG - SSD & TBT

ELECTRICAL_CONSTRAINT_SET

SPACING

DP AUX NET PROPERTIES

NET_TYPE

PHYSICAL

I125

I126

I130

I132

I133

I134

I135

I136

I140

I141

I150

I151

I152

I153

I154

I155

I156

I157

I158

I159

I223

I224

I225

I226

I227

I228

I229

I230

I235 I236

I237 I238

I239

I240 I241

I242

I247

I248

I249

I250

I251

I252

I253

I254

I255 I256

I257 I258

I259

I260

I261

I262

I263

I264

I265

I266 I267

I268

SYNC_DATE=02/18/2014

CPU Constraints

SYNC_MASTER=CLEAN_X305_PEG

* ?

=6X_DIELECTRIC

DMICLK2N2S

TOP,BOTTOM

?

PEG3_2OTHER

=8X_DIELECTRIC

*

PEG3_D2RPEG3_R2D

PEG3_TXRX

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

DP_85D

=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF

DP_2OTHER

?

=6x_DIELECTRIC

TOP,BOTTOM

PEG3_2SAME

PEG3_*

=SAME

*

=10X_DIELECTRIC

PEG_2CLK

?

TOP,BOTTOM

?

TOP,BOTTOM

=10X_DIELECTRIC

PEG_TXRX

TOP,BOTTOM

?

PEG_2SAME

=4X_DIELECTRIC

CLK_DMI

DMICLK2S2N

DMI_S2N

*

DMICLK2N2S

CLK_DMI

*

DMI_N2S

DMI_S2N DMI_N2S

DMI_TXRX

*

DMI_N2S

DMI_TXRX

*

DMI_S2N

*

DMICLK2OTHER

CLK_DMI

DMI_2SAME

?

TOP,BOTTOM

=4X_DIELECTRIC

TOP,BOTTOM

DMICLK2OTHER

?

=6X_DIELECTRIC

?

DMICLK2S2N

TOP,BOTTOM

*

DMI_2SAME

=SAMEDMI_*

=3X_DIELECTRIC

?

PEG_2SAME

*

PEG_TXRX

=6X_DIELECTRIC

? ?

PEG_2OTHER

*

=4X_DIELECTRIC

=50_OHM_SE

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD

*

=STANDARD

=45_OHM_SE=45_OHM_SE

=STANDARD

*

=45_OHM_SE =45_OHM_SE

=STANDARD

CPU_45S

TOP,BOTTOM

?

PEG3_2SAME

=6X_DIELECTRIC

*

?

PEG_2CLK

=7X_DIELECTRIC

PEG_80D

=80_OHM_DIFF =80_OHM_DIFF

*

=80_OHM_DIFF

=6X_DIELECTRIC

?

PEG_2OTHER TOP,BOTTOM

PEG_2CLK

*

PEG_* CLK_*

*

PEG3_*

PEG3_2OTHER

*

PEG3_TXRX

TOP,BOTTOM

?

=12X_DIELECTRIC

*

PEG3_*

PEG3_2CLK

CLK_*

*

PEG3_TXRX

=8X_DIELECTRIC

?

*

PEG_* =SAME

PEG_2SAME

PEG3_2CLK

*

=8X_DIELECTRIC

?

*

PEG_* PEG_2OTHER

*

PEG_D2R

*

PEG_TXRX

PEG_R2D

*

?

PEG3_2OTHER

=5X_DIELECTRIC

*

?

PEG3_2SAME

=4X_DIELECTRIC

CPU_VREF

12 MIL

* ?

CPU_VID

0.457 MM

?*

CPU_AGTL

TOP,BOTTOM

?

=2x_DIELECTRIC

=3x_DIELECTRIC

?*

DP_2SAME

=4x_DIELECTRIC

?

DP_2OTHER

*

=4x_DIELECTRIC

HDMICLK_2DP

?*

HDMICLK_2OTHER

=10x_DIELECTRIC

TOP,BOTTOM

?

*

CLK_*

HDMI_CLK

HDMICLK_2CLK

HDMI_CLK

HDMICLK_2DP

*

DISPLAYPORT

HDMI_CLK

* *

HDMICLK_2OTHER

*

DISPLAYPORT

DP_2OTHER

*

DISPLAYPORT

DP_2SAME

*

=SAME

=7x_DIELECTRIC

*

HDMICLK_2OTHER

?

=4x_DIELECTRIC

TOP,BOTTOM

?

DP_2SAME

HDMICLK_2DP

TOP,BOTTOM

?

=6x_DIELECTRIC

HDMICLK_2CLK

?

=10x_DIELECTRIC

TOP,BOTTOM

=7x_DIELECTRIC

?*

HDMICLK_2CLK

DMICLK2OTHER

* ?

=4X_DIELECTRIC

* ?

DMI_2SAME

=3X_DIELECTRIC

DMICLK2S2N

* ?

=3X_DIELECTRIC

?

=6X_DIELECTRIC

*

DMI_TXRX

=10X_DIELECTRIC

?

TOP,BOTTOM

DMI_TXRX

*

CPU_AGTL

=STANDARD

?

=2:1_SPACING

?*

CPU_ITP

25 MIL

CPU_VCCSENSE

* ?

=10X_DIELECTRIC

?

DMICLK2N2S TOP,BOTTOM

CPU_COMP

20 MIL

* ?

CPU_8MIL

?*

8 MIL

CPU_85D

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

=85_OHM_DIFF

=27P4_OHM_SE=27P4_OHM_SE

CPU_27P4S

=27P4_OHM_SE

*

7 MIL

=27P4_OHM_SE

7 MIL

?

=12X_DIELECTRIC

PEG3_2CLK

TOP,BOTTOM

DP_85D

DP_TBTSNK0_AUXCH_N

TBTSNK_AUXCH

DP_TBTSNK0_AUXCH_P

DP_85D

TBTSNK_AUXCH

DP_TBTSNK1_AUXCH_N

DP_85D

TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_P

TBTSNK_AUXCH

DISPLAYPORT

DP_85D

DPA_IG_AUX_CH_P

DP_IG_AUX

CPU_CFG CPU_45S

CPU_CFG<19..0>

CPU_ITP

XDP_CLK_PCH

CLK_PCIE

NC_ITPXDP_CLK100MN

CLK_PCIE_85D

CPU_CLK135_PLL CPU_85D

CPU_CLK135M_DPLLREF_P

CLK_PCIE

XDP_TRST_L

CPU_45S

XDP_CPUPCH_TRST_L

CPU_ITP

DPB_IG_AUX_CH_N

DP_85D

DISPLAYPORT

DP_IG_AUX

DISPLAYPORT

DPB_IG_AUX_CH_P

DP_85D

DP_IG_AUX

DISPLAYPORT

DPA_IG_AUX_CH_N

DP_85D

DP_IG_AUX

XDP_CPU_TDO

XDP_TDO CPU_ITPCPU_45S

XDP_CPU_TDI

CPU_ITPXDP_TDI CPU_45S

PEG_80D

PCIE_D2R_GPU PEG3_D2R

PEG_D2R_C_P<7..0>

PEG_80D

PCIE_D2R_GPU

PEG_D2R_C_N<7..0>

PEG3_D2R

PEG_80D

PEG3_R2DPCIE_R2D_GPU

PEG_R2D_C_N<7..0>

PEG_80D

PEG_D2R_P<7..0>

PEG3_D2RPCIE_D2R_GPU

PEG_80D

PEG3_R2DPCIE_R2D_GPU

PEG_R2D_C_P<7..0>

PEG_80D

PEG3_D2R

PEG_D2R_N<7..0>

PCIE_D2R_GPU

PEG_80D

PEG3_R2DPCIE_R2D_GPU

PEG_R2D_N<7..0>

PCIE_SSD_D2R_P<3..0>

PEG3_D2R

CPU_85D

PCIE_D2R_SSD

CPU_85D

PEG3_D2RPCIE_D2R_SSD

PCIE_SSD_D2R_N<3..0>

PCIE_R2D_SSD PEG3_R2D

CPU_85D

PCIE_SSD_R2D_C_P<3..0>

PEG3_R2D

CPU_85D

PCIE_SSD_R2D_N<3..0> PCIE_TBT_D2R_P<3..0>

CPU_85D

PEG_D2R_TBT

PEG_D2R

PCIE_TBT_R2D_P<3..0>

CPU_85D

PEG_R2D_TBT

PEG_R2D

PCIE_TBT_R2D_N<3..0>

PEG_R2DCPU_85D

PEG_R2D_TBT

PCIE_TBT_R2D_C_P<3..0>

CPU_85D PEG_R2D

PCIE_TBT_R2D_C_N<3..0>

CPU_85D PEG_R2D

CPU_45S

PM_SYNC

CPU_AGTL

PM_SYNC

XDP_BPM_L<7..4>

CPU_ITPCPU_45S

XDP_BPM_L

CPU_ITP

XDP_BPM_L<3..0>

CPU_45SXDP_BPM

PCIE_SSD_R2D_P<3..0>

PEG3_R2D

CPU_85D

CPU_VIDALERT_L

CPU_VID CPU_45S CPU_VID

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

PP0V75_S3_MEM_VREFCA

MEM_PWR

CPU_MEM_VREF

PP0V75_S3_MEM_VREFDQ_B

CPU_VREF

CPU_DIMMB_VREFDQ

MEM_12MIL

CPU_MEM_VREF

CPU_85D DMI_S2NDMI_S2N

DMI_S2N_P<3:0>

DMI_N2S CPU_85D

DMI_N2S_P<3:0>

DMI_N2S

FDI_INT CPU_50S

FDI_INT

CPU_AGTL

CPU_CATERR_L

CPU_CATERR_L CPU_AGTL

CPU_45S

XDP_PRDY_L

CPU_45S CPU_ITP

XDP_CPU_PRDY_L

DP_TBTSNK0_ML_C_N<3..0>

DP_TBT_ML0

DP_85D

DISPLAYPORT

DP_TBT_ML1

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_AUXCH_C_N

DP_85D

DP_TBTSNK0_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_AUXCH_C_P

DP_85D

PCIE_TBT_D2R_N<3..0>

PEG_D2R_TBT

CPU_85D PEG_D2R

CLK_PCIE

CPU_85DCPU_CLK135_PLL

CPU_CLK135M_DPLLSS_N

CPU_85D CLK_DMI

DMI_CLK100M_CPU_N

DMI_CLK

DMI_N2S CPU_85D

DMI_N2S_N<3:0>

DMI_N2S

CPU_27P4S

CPU_PEG_COMP CPU_COMP

CPU_PEG_RCOMP

CPU_85DCPU_CLK135_PLL

CLK_PCIE

CPU_CLK135M_DPLLREF_N

NC_ITPXDP_CLK100MP

CLK_PCIECLK_PCIE_85D

XDP_CLK_PCH

DMI_S2N_N<3:0>

DMI_S2N CPU_85D DMI_S2N

CPU_COMP

CPU_27P4S

CPU_EDP_COMP

CPU_EDP_RCOMP

CPU_PWRGD

CPU_AGTL

CPU_45S

CPU_PWRGD

FDI_CSYNC

CPU_50S

FDI_CSYNC

CPU_AGTL

DMI_CLK100M_CPU_P

DMI_CLK CPU_85D CLK_DMI

CLK_PCIE

CPU_CLK135M_DPLLSS_P

CPU_85DCPU_CLK135_PLL

DP_TBT_ML1

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_P<3..0>

DP_TBTSNK0_AUXCH_C_N

DP_85D

DP_TBTSNK0_AUXCH_C_P

DP_85D

DP_TBTSNK1_ML_N<3..0>

DISPLAYPORT

PM_THRMTRIP_L

CPU_45S

PM_THRMTRIP_L

CPU_8MIL

XDP_TCK CPU_ITPCPU_45S

XDP_CPU_TCK

XDP_CPU_TMS

XDP_TMS CPU_ITPCPU_45S

XDP_BDRESET_L

XDP_DBRESET_L

CPU_ITPCPU_45S

CPU_PROCHOT_L

CPU_AGTL

CPU_45S

CPU_PROCHOT_L

CPU_45S

CPU_VIDSCLK

CPU_VID CPU_VID

CPU_VIDSOUT

CPU_VID CPU_VIDCPU_45S

CPU_27P4S

CPU_COMPCPU_SM_RCOMP

CPU_SM_RCOMP<2..0>

CPU_VCCSENSE_N

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_AGTL

PM_MEM_PWRGD

CPU_45S

CPU_DIMMA_VREFDQ

CPU_MEM_VREF

MEM_12MIL

PCIE_TBT_D2R_C_N<3..0>

CPU_85D PEG_D2R

PCIE_TBT_D2R_C_P<3..0>

CPU_85D PEG_D2R

PCIE_SSD_R2D_C_N<3..0>

PCIE_R2D_SSD PEG3_R2D

CPU_85D

CPU_MEM_VREF

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

PP0V75_S3_MEM_VREFCA

MEM_PWR

CPU_MEM_VREF

PEG_80D

PEG3_R2DPCIE_R2D_GPU

PEG_R2D_P<7..0>

DP_TBTSNK0_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_C_P<3..0>

DP_TBT_ML0

DP_85D

DISPLAYPORT

XDP_CPU_PREQ_L

XDP_PREQ_L

CPU_ITPCPU_45S

CPU_PECI

CPU_VIDCPU_45S

<SCH_NUM>

111 OF 119

89 OF 97

28 97

12 83 85

6

18 86

11 87

6

11

6

18 86

12 83 85

6

18 86

6

18 86

68 70

68 70 85

70 85

68 70 85

70 85

70

5

34 85

5

34 85

5

34 85

34

5

28 85

28 87

5

28 85

5

28 85

6

12

6

18

6

18

34

8

58

8

58

22 23 24 25 26 85 89 92

22 25 26 85

7

22

5

12 87

5

12 87

5

12

6

40

6

18 86

28 76 97

28 83 97

28 97

28 83 97

5

28 85

6

11

6

11

5

12 87

5

6

11

11 87

5

12 87

5

6

14 18

5

12

6

11

6

11

28 76 97

28 97

28 83 97

28 97

6

14 41

6

18 86

6

18 86

6

18 19

6

40 41 58

8

58

8

58

6

9

58

6

12 21

7

22

28 87

5

34 85

22 23 24 85 92

22 23 24 25 26 85 89 92

70

28 97

28 76 97

6

18 86

6

14 41

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SATA Interface Constraints

PCH Net Properties

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

NOTE: Latest Intel DG calls out 50ohms SE for sys clocks

SPACING

PHYSICAL

NET_TYPE

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

NOTE: 25MHz system clocks very sensitive to noise.

System Clock Signal Constraints

USB 2.0 Interface Constraints

USB 3.0 INTERFACE CONSTRAINTS

I213

I220

I221

I222 I223

I228

I229

I230

I231

I238

I239

I244

I245

I248

I249

I250

I251

I253

I254

I255

I256

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I271

I272

I273

I274

I281 I282

I283 I284

I285

I286

I287

I288

I290

I291

I292

I293

I294

I295

I296 I297

I298

I299

I300 I301

I302 I303

*

BT_WAKE

?

=4X_DIELECTRIC

USB *

?

=6X_DIELECTRIC

USB_RBIAS

* ?

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

USB3_85D

*

SATA_TXRX

?

TOP,BOTTOM

=10X_DIELECTRIC

TOP,BOTTOM

SATA_2OTHER

?

=6X_DIELECTRIC

TOP,BOTTOM

?

USB

=6X_DIELECTRIC

USB_RBIAS

=10X_DIELECTRIC

?

TOP,BOTTOM

=6X_DIELECTRICBT_WAKE

?

TOP,BOTTOM

?

*

=3X_DIELECTRIC

USB3_2SAME

?

*

USB3_TXRX

=6X_DIELECTRIC

USB3_2OTHER

TOP,BOTTOM

=6X_DIELECTRIC

?

=10X_DIELECTRIC

USB3_TXRX

?

TOP,BOTTOM

=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE

CLK_SLOW_45S

=STANDARD =STANDARD*

=45_OHM_SE

=STANDARD

=45_OHM_SE=45_OHM_SE=45_OHM_SE

CLK_25M_45S

=STANDARD*

USB3_*

*

=SAME USB3_2SAME

USB3_TXRX

*

USB3_D2RUSB3_R2D

USB3_2OTHER

USB3_*

**

USB3_2SAME

=4x_DIELECTRIC

?

TOP,BOTTOM

?

*

CLK_25M =5x_DIELECTRIC

?

*

CLK_SLOW

=4x_DIELECTRIC

=37_OHM_SE =37_OHM_SE

SATA_37SE

=37_OHM_SE

=37_OHM_SE=37_OHM_SE

*

?

TOP,BOTTOM

=10X_DIELECTRIC

SATA_RCOMP

SATA_*

*

SATA_2OTHER

*

=3X_DIELECTRIC

SATA_2SAME

* ?

*

SATA_2SAME

SATA_*

=SAME

* ?

SATA_RCOMP

=6X_DIELECTRIC

=4X_DIELECTRIC

* ?

SATA_2OTHER

=85_OHM_DIFF

*

USB_85D

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

PCH_USB_RBIAS

=STANDARD

=STANDARD=STANDARD

=STANDARD

*

=STANDARD=STANDARD

=6X_DIELECTRIC

SATA_TXRX

* ?

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

SATA_85D

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

*

SATA_D2R

*

SATA_R2D

SATA_TXRX

=45_OHM_SE

=45_OHM_SE=45_OHM_SE

=45_OHM_SE

SATA_45SE

*

?

SATA_2SAME TOP,BOTTOM

=4x_DIELECTRIC

USB3_2OTHER

=4X_DIELECTRIC

?

*

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

PCH Constraints 1

USB_85D

USB3_R2D

USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N

USB3_R2D

USB_85D

USB3_EXTB_D2R_P

USB3_EXTB_RX USB3_D2R

USB_85D

USB3_EXTB_D2R_N

USB_85D

USB3_D2RUSB3_EXTB_RX

USB_85D

USB3_R2D

NC_USB3_EXTD_R2D_CN

USB3_EXTA_R2D_P

USB3_EXTA_TX USB3_R2D

USB_85D

USB

USB_NC

NC_USB_SDP

CLK_SLOW_45S CLK_SLOW

SYSCLK_CLK32K_RTC

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_SB

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_SB_R

CLK_25M_45S

SYSCLK_CLK25M_CAM

SYSCLK_CLK25M_CAMERA

CLK_25M

USB_85D

NC_USB3_EXTD_D2RN

USB3_D2R

NC_USB3

NC_USB_6P

USB

USB_NC

USB_85D

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_TBT_R

USB_85D

USB3_R2D

USB3_EXTB_R2D_N

USB3_EXTB_TX

USB3_EXTA_D2R_N

USB3_D2R

USB_85D

USB3_EXTA_RX

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M

SYSCLK_CLK25M_TBT

USB3_D2R

USB3_EXTA_D2R_C_P

USB_85D

USB3_EXTB_R2D_C_N

USB3_R2D

USB_85D

USB3_R2D

USB3_EXTA_R2D_N

USB3_EXTA_TX

USB_85D

USB3_EXTA_D2R_C_N

USB3_D2R

USB_85D

NC_USB3_EXTD_R2D_CP

USB3_R2D

NC_USB3_EXTD_D2RP

USB3_D2R

NC_USB3 USB_85D

NC_USB3_EXTC_R2D_CN

USB3_R2D

USB_85D

NC_USB3_EXTC_R2D_CP

USB3_R2D

NC_USB3

USB3_D2R

NC_USB3_EXTC_D2RN

USB_85D

NC_USB3_EXTC_D2RP

USB3_D2R

NC_USB3 USB_85D

USB3_EXTB_R2D_C_P

USB3_R2D

USB_85D

USB3_EXTB_D2R_C_P

USB3_D2R

USB_85D

USB3_EXTA_RX

USB_85D

USB3_D2R

USB3_EXTA_D2R_P

USB_85D

USB_BT_P

USB

USB_BT

NC_USB_EXTDN

USB_NC

USB_85D

USB

USB_NC

NC_USB_7N

USB

USB_85D

PCH_USB_RBIAS

USB_RBIAS

PCH_USB_RBIASPCH_USB_RBIAS

NC_USB_IRP

USB

USB_NC

USB_85D

NC_USB_EXTDP

USB

USB_NC

USB_85D

USB3_EXTB_R2D_P

USB3_R2DUSB3_EXTB_TX

USB_85D

USB3_EXTB_D2R_C_N

USB3_D2R

USB_BT_CONN_N

USB_85D

USB

USB_85D

USB_BT_CONN_P

USB

USB_BT_N

USB_BT

USB

USB_85D

NC_USB_SMCN

USB_SMC

USB

USB_85D

USB_NC

USB_85D

USB

NC_USB_EXTCN

USB_85DUSB_SMC

USB

NC_USB_SMCP

USB_85D

NC_USB_SDN

USB_NC

USB

SATA_D2RSATA_85D

NC_SATA_A_D2RP

SATA_R2DSATA_85D

NC_SATA_A_R2D_CP

SATA_85D SATA_D2R

NC_SATA_B_D2RP

SATA_85D SATA_R2D

NC_SATA_B_R2D_CN

SATA_D2RSATA_85D

NC_SATA_A_D2RN

SATA_R2DSATA_85D

NC_SATA_A_R2D_CN

USB

USB_EXTA_P

USB_85D

USB_EXTA

USB_85D

USB_EXTA

USB

USB_EXTA_N

CPU_ITP

SMC_DEBUGPRT_RX_L

CPU_45S

CPU_ITPCPU_45S

SMC_DEBUGPRT_TX_L

USB

USB_EXTA_MUXED_N

USB_85D

USB_EXTA

SATA_85D SATA_R2D

NC_SATA_B_R2D_CP

USB_85D

USB

USB_LT1_N

USB_EXTA

SATA_85D SATA_D2R

NC_SATA_B_D2RN

PCH_SATA_RCOMP

SATA_45SE

PCH_SATA_RCOMP

SATA_RCOMP

USB

USB_EXTA_MUXED_P

USB_85D

USB_EXTA

USB_85D

USB

USB_LT1_P

USB_EXTA

USB_85D

NC_USB_EXTCP

USB_NC

USB

NC_USB_IRN

USB_NC

USB_85D

USB

USB_EXTB

USB_85D

USB

USB_EXTB_P USB_EXTB_N

USB

USB_85D

USB_EXTB

NC_USB_7P

USB

USB_NC

USB_85D

USB_NC

USB

USB_85D

NC_USB_6N

USB_TPAD

USB_TPAD_N

USB

USB_85D

USB

USB_TPAD

USB_TPAD_P

USB_TPAD_R_N

USB_85D

USB

USB_TPAD_R_P

USB

USB_85D

<SCH_NUM>

112 OF 119

90 OF 97

13 37

13 81 86

13 87

37

13 87

11 19

11

19 36

13 87

28

81 86

13 37

19 28

13 81

37

13 87

13 81

13 37

13 33

13 87

13

13 87

81 86

33 86

13 33

87

13 87

87

13 87

11 87

13 37

37 40 41

37

11 87

37

11 87

11

37

13 87

13 81 86

13 87

13 38 86

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

NET_TYPE

PHYSICAL

NET_TYPE

SPACING

SMBus Interface Constraints

ELECTRICAL_CONSTRAINT_SET

PCH Net Properties

LPC Bus Constraints

PCH Net Properties

PCI-Express

PCH Single Net Constraints

SPI Interface Constraints

HD Audio Interface Constraints

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I275

I276

I281

I282

I293 I298

I299

I300

I303

I304

I307

I308

I313

I314 I315

I316

I317

I318

I319

I320

I321 I322

I323 I324

I325

I326

I327 I328

I329

I330 I331

I332

I333

I334

I341

I342

I343

I344

I353

I354

I358

I359

I363

I364

I368

I369

I370

I371

I372

I373

I374

I375

I376

I377

I380

I381

I382

I383

I386

I387

I390

I391

I392

I395

I396

I397

PCH Constraints 2

SYNC_DATE=02/18/2014

SYNC_MASTER=CLEAN_X305_PEG

=45_OHM_SE=45_OHM_SE=45_OHM_SE

LPC_45S

=STANDARD

*

=STANDARD

=45_OHM_SE

=45_OHM_SE =45_OHM_SE

=STANDARD=STANDARD

*

=45_OHM_SE =45_OHM_SE

CLK_LPC_45S

HDA_45S

*

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE=45_OHM_SE=45_OHM_SE

?

SPI

*

8 MIL

=STANDARD

*

=STANDARD

=45_OHM_SE=45_OHM_SE

SPI_45S

=45_OHM_SE=45_OHM_SE

HDA

?

*

=2x_DIELECTRIC

*

SPI3X

?

=3x_DIELECTRIC

PCIE_2OTHER

PCIE_*

**

CLK_*

*

PCIE_*

PCIE_2CLK

* *

CLK_PCIE

PCIECLK_2OTHER

PCIE_TXRX

PCIE_R2D

*

PCIE_D2R

PCIE_2SAME

PCIE_*

*

=SAME

=4X_DIELECTRIC

PCIE_2OTHER

?

*

?

=7X_DIELECTRIC

*

PCIE_2CLK

PCIECLK_2OTHER

?

*

=7X_DIELECTRIC

=6X_DIELECTRIC

?

*

PCIE_TXRX

=85_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

*

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFFCLK_PCIE_85D =85_OHM_DIFF

*

=85_OHM_DIFF

=2X_DIELECTRIC

* ?

PCIE_2SAME

=2x_DIELECTRIC

?*

PCH_SE

=45_OHM_SE

*

=STANDARD =STANDARD

PCH_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE

TOP,BOTTOM

?

PCIE_2CLK

=10X_DIELECTRIC

PCIECLK_2OTHER

?

TOP,BOTTOM

=10X_DIELECTRIC

TOP,BOTTOM

?

PCIE_2OTHER

=6X_DIELECTRIC

PCIE_2SAME

?

=4X_DIELECTRIC

TOP,BOTTOM

=3x_DIELECTRIC

PCH_SE

?

PCIE_TXRX

TOP,BOTTOM?=10X_DIELECTRIC

6 MIL

* ?

LPC

SMB

*

=2x_DIELECTRIC

?

SMB_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=STANDARD

*

=45_OHM_SE

=STANDARD

?

CLK_LPC

*

8 MIL

CLK_PCIECLK_PCIE_85D

PEG_CLK100M_P

PCIE_CLK100M_GPU

CLK_PCIE_85D CLK_PCIE

PEG_CLK100M_N

CLK_PCIE_85D

PCIE_CLK100M_PCH_P

CLK_PCIE

PCIE_CLK100M_PCH

CLK_PCIE_85D

PCIE_CLK100M_TBT_N

CLK_PCIE

PCIE_CLK100M_TBT

PCIE_85D

PCIE_CLK100M_SATA

PCH_CLK100M_SATA_N

CLK_PCIE

PCIE_CLK100M_AP_P

CLK_PCIE

PCIE_CLK100M_AP

PCIE_85D

PCIE_CLK100M_AP_N

CLK_PCIE

PCIE_CLK100M_AP

PCIE_85D

CLK_PCIE

PCIE_CLK100M_AP_CONN_P

PCIE_85D

PCIE_CLK100M_S2

PCIE_CLK100M_CAMERA_P

CLK_PCIECLK_PCIE_85D

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_SSD_N

CLK_PCIE_85D

PCIE_CLK100M_FW

PCIE_CLK100M_SSD_P

CLK_PCIE

CLK_PCIE_85D

PCIE_CLK100M_PCH_N

CLK_PCIE

PCIE_CLK100M_PCH

PCIE_CLK100M_TBT_P

CLK_PCIE

PCIE_CLK100M_TBT

CLK_PCIE_85D

PCH_CLK96M_DOT_P

PCIE_CLK100M_DOT

CLK_PCIE

CLK_PCIE_85D

PCH_CLK96M_DOT_N

PCIE_CLK100M_DOT

CLK_PCIE

PCH_CLK100M_SATA_P

PCIE_85D

PCIE_CLK100M_SATA

CLK_PCIE

PCIE_85D

PCIE_CLK100M_SD_P

CLK_PCIE

PCIE_CLK100M_ENET

PCIE_CLK100M_SD_N

PCIE_CLK100M_ENET

CLK_PCIEPCIE_85D

PCIE_85D CLK_PCIE

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_CAMERA_N

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_S2

PCIE_CLK100M_CAMERA_C_P

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_CAMERA_C_N

CLK_PCIE_85D CLK_PCIE

HDA_SDOUT

HDA

HDA_45S

HDA_SDOUT

CS4208_HDA_SDOUT0_R

HDA_SDIN0_R

HDA_45S

HDA

LPC_FRAME_L

LPC_45S

LPC

LPC_FRAME_L

SMBUS_PCH_DATA SMB_45S

SMBUS_PCH_DATA

SMB

SMBUS_PCH_0_CLK

SML_PCH_0_CLK

SMB_45S

SMB SMB

SMB_45S

SMBUS_PCH_0_DATA

SML_PCH_0_DATA SML_PCH_1_CLK

SMBUS_PCH_1_CLK

SMB_45S

SMB

SPI_CLK

SPI

SPI_45SSPI_MLB

SPI_45S

SPI_SMC_CLK

SPI3X

SPI_MLB

SPI_ALT_CS_L

SPI3X

SPI_45SSPI_MLB

SPI_MLB

SPI_CS0_L

SPI

SPI_45S

SPI_MLB

SPI_CS0_R_L

SPI

SPI_45S

SPI_MLB_CS_L

SPI_MLB

SPI3X

SPI_45S

SPI_MLB_CLK

SPI3X

SPI_MLB

SPI_45SSPI_MLB

SPI_ALT_CLK

SPI3X

PCIE_WAKE_L

PCH_45S

PCH_SE

PCH_PCIE_WAKE

PCH_45S

PCH_SE

PM_THRMTRIP_L_R

PCH_PM_NET

SPI_CLK_R

SPI

SPI_45SSPI_MLB

SPI_45S

SPI_ALT_IO3_HOLD_L

SPI_MLB_IO3

SPI3X

SPI_MLB_IO3_HOLD_L

SPI_45S

SPI_MLB_IO3

SPI3X

SPI_45S

SPI_MLB_IO3

SPI_IO<3>

SPI3X

SPI_45S

SPI_MLB_IO2

SPI_ALT_IO2_WP_L

SPI3X

SPI_45S

SPI_MLB_IO2_WP_L

SPI_MLB_IO2

SPI3X

SPI_MLB_IO2

SPI_45S

SPI_IO<2>

SPI3X

SPI_45S

SPI_SMC_MOSI

SPI_MLB

SPI3X

SPI_MLB SPI_45S

SPI_MLB_IO0_MOSI

SPI3X

SPI_45SSPI_MLB

SPI_ALT_IO0_MOSI

SPI3X

SPI_45SSPI_MLB

SPI_SMC_MISO

SPI3X

SPI_MLB SPI_45S

SPI_MLB_IO1_MISO

SPI3X

SPI_45SSPI_MLB

SPI_ALT_IO1_MISO

SPI3X

SPI_MLB

SPI_SMC_CS_L

SPI3X

SPI_45S

PCIE_AP_R2D_P

PCIE_R2DPCIE_85D

PCIE_AP_R2D

PCIE_AP_R2D_N

PCIE_85D PCIE_R2D

PCIE_AP_R2D

SPI

SPI_TPAD

SPI_45S

TPAD_SPI_SCLK

SPI

TPAD_SPI_CS_L

SPI_TPAD_CS

SPI_45S

TPAD_SPI_MISO

SPI_TPAD

SPI

SPI_45S

SPI_MISO

SPI

SPI_45SSPI_MLB

PCH_PM_NET

PCH_SE

PCH_45S

PM_PCH_PWROK

PCH_PM_NET

PCH_45S

PM_PCH_SYS_PWROK

PCH_SE

PCH_PM_NET

PM_DSW_PWRGD

PCH_SE

PCH_45S

SPI_MISO_R

SPI

SPI_45SSPI_MLB

HDA_SDOUT_R

HDA

HDA_45S

USB3_SD_R2D_C_P

USB3_R2DUSB3_85D

USB3_SD_R2D

HDA_SYNC

HDA_45S

HDA

HDA_SYNC

SPI_MLB

SPI_MOSI

SPI_45S

SPI

SPI_MLB

SPI_MOSI_R

SPI_45S

SPI

LPC_AD<3..0>

LPC_45S

LPC_AD

LPC

PCIE_CAMERA_R2D_P

PCIE_85D PCIE_R2D

PCIE_CAMERA_R2D

PCIE_CAMERA_R2D_C_N

PCIE_85D PCIE_R2D

PCIE_D2R

PCIE_CAMERA_D2R

PCIE_85D

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_C_N

PCIE_85D PCIE_D2R

CLK_LPC_45S

LPC_CLK33M_SMC_R

CLK_LPC

CLK_LPC_45S

LPC_CLK33M_SMC

PCH_LPC_CLK0

CLK_LPC

CLK_LPC_45S

NC_LPC_CLK33M_LPCPLUS_R

CLK_LPC

CPU_45S

PCH_CLK33M_PCIOUT

PCIE_CLK100M CLK_PCIE

CPU_45S

PCH_CLK14P3M_REFCLK

PCIE_CLK100M CLK_PCIE

CPU_45S

PCH_CLK33M_PCIIN

PCIE_CLK100M CLK_PCIE

PCIE_D2R

PCIE_CAMERA_D2R

PCIE_85D

PCIE_CAMERA_D2R_P

PCIE_85D PCIE_D2R

PCIE_AP_D2R_PI_N

PCIE_AP_D2R_PI_P

PCIE_85D PCIE_D2R

PCIE_85D PCIE_R2D

PCIE_CAMERA_R2D_N

PCIE_CAMERA_R2D

PCIE_CAMERA_R2D_C_P

PCIE_85D PCIE_R2D

PCIE_85D PCIE_D2R

PCIE_CAMERA_D2R_C_P

SMB_45S

SMBUS_PCH_1_DATA

SML_PCH_1_DATA

SMB

HDA_SYNC_R

HDA

HDA_45S

PCIE_AP_R2D_C_P

PCIE_R2DPCIE_85D

PCIE_AP_D2R_P

PCIE_85D

PCIE_AP_D2R

PCIE_D2R

PCH_SRTCRST_L

PCH_SE

PCH_45S

PCH_PM_NET PCH_PM_NET

PCH_45S

PM_RSMRST_L

PCH_SE

PCH_PM_NET

PCH_45S

PM_SYSRST_L

PCH_SE

PCIE_AP_R2D_C_N

PCIE_R2DPCIE_85D

PCIE_AP_R2D_PI_N

PCIE_R2DPCIE_85D

HDA_RST_L

HDA_45S

HDA_RST_L

HDA

HDA_RST_R_L

HDA_45S

HDA

PCH_45S

PCH_PM_NET

PCH_DSWVRMEN

PCH_SE

PCH_PM_NET

PCH_45S

PCH_INTVRMEN_L

PCH_SE

PCH_PM_NET

PCH_45S

PCH_INTRUDER_L

PCH_SE

HDA_BIT_CLK

HDA_45S

HDA

PCIE_AP_R2D_PI_P

PCIE_85D PCIE_R2D

PCH_PM_NET

PM_PCH_PWROK

PCH_SE

PCH_45S

PCIE_AP_D2R_N

PCIE_85D

PCIE_AP_D2R

PCIE_D2R

USB3_SD_D2R

USB3_85D USB3_D2R

USB3_SD_D2R_N

USB3_SD_D2R_P

USB3_SD_D2R

USB3_85D USB3_D2R

USB3_SD_R2D

USB3_R2DUSB3_85D

USB3_SD_R2D_C_N

HDA_BIT_CLK_R

HDA_45S

HDA

PCH_RCIN_L

PCH_45S

PCH_SE

PCH_PM_NET

HDA_SDIN0

HDA_45S

HDA_SDIN0

HDA

PCH_PM_NET

PM_PWRBTN_L

PCH_45S

PCH_SE

SPI_TPAD

SPI

SPI_45S

TPAD_SPI_MOSI

SMB_45S

SMBUS_PCH_CLK

SMB

SMBUS_PCH_CLK

<SCH_NUM>

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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PAGE TITLE

SHEET

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Memory to GND Spacing

Memory to Power Spacing

DDR3 (Memory Down):

SOURCE: Double checked with Doc#486985 Chief River SFF Platform DG: Memory Down

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

NET_TYPE

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs. A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.

SOURCE: Need to re-confirm CRW DG for memory down (Intel not yet provided)

Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

Spacing Rule Sets

PHYSICAL

SPACING

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

Memory Bus Constraints

Memory Bus Spacing Group Assignments

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].

DQ signals should be matched within 0.508mm of associated DQS pair

I101

I103

I105

I106

I108

I109

I110

I111

I112

I113

I114

I115

I116

I117

I118

I119

I120 I121

I122

I123

I124

I125

I126

I127

I128

I129

I130

MEM_*_DATA_*

**

MEM_2OTHER

MEM_*_DQS_*

MEM_2OTHER

**

MEM_CMD

*

MEM_2OTHER

*

MEM_A_DATA_7

MEM_A_DQS_7

MEM_DQS2OWNDATA

*

MEM_B_DATA_1

*

MEM_DQS2OWNDATA

MEM_B_DQS_1

MEM_B_DATA_3

MEM_B_DQS_3

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_B_DATA_5

MEM_B_DQS_5

*

MEM_B_DATA_7

MEM_B_DQS_7

MEM_DQS2OWNDATA

*

MEM_CLK2CLK

MEM_CLKMEM_CLK

*

MEM_CMD

MEM_CMD2CTRL

MEM_CTRL

*

=10x_DIELECTRIC

?

MEM_2OTHER

TOP,BOTTOM

=4x_DIELECTRIC

?

TOP,BOTTOM

MEM_2GND

=4x_DIELECTRIC

?

MEM_2PWR

TOP,BOTTOM

=5x_DIELECTRIC

?

TOP,BOTTOM

MEM_CMD2CTRL

=5x_DIELECTRIC

?

TOP,BOTTOM

MEM_DQS2OWNDATA

MEM_37S

=37_OHM_SE=37_OHM_SE

=STANDARD* =STANDARD

=37_OHM_SE =37_OHM_SE

=72_OHM_DIFF

=72_OHM_DIFF*

MEM_72D

=72_OHM_DIFF =72_OHM_DIFF

=STANDARD=STANDARD*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MEM_45S

=45_OHM_SE

=85_OHM_DIFF

MEM_85D

*

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

* =STANDARD

MEM_40S

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

=40_OHM_SE

MEM_2GND

*

=2x_DIELECTRIC

?

* ?

=6x_DIELECTRIC

MEM_2OTHER

*

MEM_CLK

*

MEM_A_DQS_3

MEM_A_DATA_3

*

MEM_DQS2OWNDATA

MEM_CLK2CLK

TOP,BOTTOM

=8x_DIELECTRIC

?

MEM_CTRL2CTRL

?

TOP,BOTTOM

=5x_DIELECTRIC

MEM_DATA2SELF

?

TOP,BOTTOM

=5x_DIELECTRIC

=4x_DIELECTRIC

?*

MEM_CLK2CLK

MEM_A_DQS_0*MEM_A_DATA_0

MEM_DQS2OWNDATA

=5x_DIELECTRIC

?

MEM_CMD2CMD

TOP,BOTTOM

MEM_2OTHER

*

MEM_CTRL

*

MEM_A_DQS_1

MEM_A_DATA_1

*

MEM_DQS2OWNDATA

MEM_A_DQS_2

MEM_A_DATA_2

*

MEM_DQS2OWNDATA

MEM_A_DATA_5

MEM_A_DQS_5

*

MEM_A_DATA_4

MEM_A_DQS_4

MEM_DQS2OWNDATA

*

MEM_A_DATA_6

MEM_DQS2OWNDATA

*

MEM_A_DQS_6

MEM_B_DATA_0

MEM_B_DQS_0

*

MEM_DQS2OWNDATA

MEM_B_DQS_2

MEM_DQS2OWNDATA

*

MEM_B_DATA_2

MEM_DQS2OWNDATA

MEM_B_DATA_4

MEM_B_DQS_4

*

MEM_B_DATA_6

MEM_B_DQS_6

MEM_DQS2OWNDATA

*

MEM_CMD2CMD

MEM_CMD MEM_CMD

*

MEM_*_DATA_*

=SAME

MEM_DATA2SELF

MEM_* MEM_*

*

MEM_2OTHERMEM

MEM_2PWR

*

MEM_*

MEM_PWR

DEFAULTMEM_PWR

**

MEM_2GND

MEM_*

*

GND

* ?

MEM_CMD2CTRL

=2x_DIELECTRIC

?*

MEM_CMD2CMD

MEM_CTRL2CTRL

* ?

=2x_DIELECTRIC

*

MEM_2OTHERMEM

?

=4x_DIELECTRIC

*

MEM_DQS2OWNDATA

=2x_DIELECTRIC

?

?*

=2x_DIELECTRIC

MEM_DATA2SELF

MEM_2PWR

?*

=2x_DIELECTRIC

MEM_CTRL MEM_CTRL

*

MEM_CTRL2CTRL

MEM_2OTHERMEM

TOP,BOTTOM

=8x_DIELECTRIC

?

SYNC_DATE=12/10/2012

SYNC_MASTER=SIDLE_J45

Memory Constraints

MEM_85D

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_A_DQS_2

MEM_85D

MEM_A_DQS_N<4>

MEM_A_DQS_4

MEM_A_DQS4

MEM_85D

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_A_DQS_7

MEM_45S

MEM_B_DATA_1

MEM_B_DQ<15..8>

MEM_B_DATA_1

MEM_45S

MEM_B_DQ<23..16>

MEM_B_DATA_2MEM_B_DATA_2

MEM_B_DQ<39..32>

MEM_B_DATA_4 MEM_B_DATA_4

MEM_45S MEM_45S

MEM_B_DQ<47..40>

MEM_B_DATA_5 MEM_B_DATA_5

MEM_85D

MEM_A_DQS0

MEM_A_DQS_P<0>

MEM_A_DQS_0

MEM_85D

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_A_DQS_0

MEM_B_CMD

MEM_B_A<15..0>

MEM_40S MEM_CMD

MEM_B_BA<2..0>

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_B_DATA_0 MEM_B_DATA_0

MEM_B_DQ<7..0>

MEM_45S

MEM_A_CLK0

MEM_A_CLK_P<0>

MEM_CLKMEM_72D

MEM_A_CLK0

MEM_A_CLK_N<0>

MEM_CLKMEM_72D

MEM_A_CLK1

MEM_A_CLK_P<1>

MEM_CLKMEM_72D

MEM_A_CNTL0

MEM_A_CKE<0>

MEM_CTRL

MEM_40S

MEM_A_CNTL0

MEM_A_CS_L<0>

MEM_40S

MEM_CTRL

MEM_A_CMD

MEM_A_A<15..0>

MEM_40S MEM_CMD

MEM_40S

MEM_A_CNTL1

MEM_A_ODT<1>

MEM_CTRL

MEM_A_CNTL0

MEM_A_ODT<0>

MEM_40S

MEM_CTRL

MEM_A_CMD

MEM_CMDMEM_40S

MEM_A_BA<2..0>

MEM_A_CS_L<1>

MEM_40S

MEM_CTRL

MEM_A_CNTL1

MEM_85D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_B_DQS_2

MEM_85D

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_B_DQS_4

MEM_85D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_B_DQS_5

MEM_85D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_B_DQS_7

MEM_85D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_A_DQS_5

MEM_A_DQS_N<3>

MEM_85D

MEM_A_DQS3

MEM_A_DQS_3

MEM_A_CKE<1>

MEM_40S

MEM_CTRL

MEM_A_CNTL1

MEM_B_CLK0

MEM_B_CLK_P<0>

MEM_72D MEM_CLK

MEM_85D

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_B_DQS_7

MEM_85D

MEM_B_DQS_N<6>

MEM_B_DQS_6

MEM_B_DQS6

MEM_85D

MEM_B_DQS_P<6>

MEM_B_DQS_6

MEM_B_DQS6

MEM_85D

MEM_B_DQS_3

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_85D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_B_DQS_3

MEM_85D

MEM_B_DQS_P<2>

MEM_B_DQS_2

MEM_B_DQS2

MEM_85D

MEM_B_DQS_P<1>

MEM_B_DQS_1

MEM_B_DQS1

MEM_85D

MEM_B_DQS_N<0>

MEM_B_DQS_0

MEM_B_DQS0

MEM_85D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_B_DQS_1

MEM_85D

MEM_B_DQS_P<0>

MEM_B_DQS_0

MEM_B_DQS0

MEM_B_CS_L<0>

MEM_40S

MEM_B_CNTL0

MEM_CTRL

MEM_B_CNTL0

MEM_B_ODT<0>

MEM_40S

MEM_CTRL

MEM_B_CLK_P<1>

MEM_72D MEM_CLK

MEM_B_CLK1

MEM_CLK

MEM_B_CLK_N<0>

MEM_B_CLK0

MEM_72D

MEM_A_CLK1

MEM_A_CLK_N<1>

MEM_CLKMEM_72D

MEM_85D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_A_DQS_7

MEM_85D

MEM_A_DQS4

MEM_A_DQS_4

MEM_A_DQS_P<4>

MEM_45S

MEM_A_DQ<39..32>

MEM_A_DATA_4 MEM_A_DATA_4

MEM_85D

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_A_DQS_1

MEM_45S

MEM_A_DATA_7

MEM_A_DQ<63..56>

MEM_A_DATA_7

MEM_45S

MEM_A_DQ<47..40>

MEM_A_DATA_5 MEM_A_DATA_5

MEM_A_DQS3

MEM_85D

MEM_A_DQS_P<3>

MEM_A_DQS_3

MEM_85D

MEM_A_DQS_N<5>

MEM_A_DQS_5

MEM_A_DQS5

MEM_85D

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_A_DQS_6

MEM_45S

MEM_B_DATA_6MEM_B_DATA_6

MEM_B_DQ<55..48>

MEM_45S

MEM_B_DQ<63..56>

MEM_B_DATA_7MEM_B_DATA_7

MEM_85D

MEM_B_DQS_N<4>

MEM_B_DQS4

MEM_B_DQS_4

MEM_85D

MEM_B_DQS_P<5>

MEM_B_DQS_5

MEM_B_DQS5

PP1V35_S3_MEM

MEM_PWR

PP0V75_S3_MEM_VREFDQ_A

MEM_85D

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_A_DQS_1

MEM_40S

MEM_A_CMD

MEM_A_CAS_L

MEM_CMD

MEM_40S

MEM_A_CMD

MEM_CMD

MEM_A_RAS_L

MEM_40S

MEM_A_WE_L

MEM_A_CMD

MEM_CMD

MEM_45S

MEM_A_DQ<7..0>

MEM_A_DATA_0 MEM_A_DATA_0

MEM_45S

MEM_A_DQ<15..8>

MEM_A_DATA_1 MEM_A_DATA_1

MEM_45S

MEM_A_DQ<23..16>

MEM_A_DATA_2 MEM_A_DATA_2

MEM_45S

MEM_A_DQ<31..24>

MEM_A_DATA_3 MEM_A_DATA_3

MEM_45S

MEM_A_DQ<55..48>

MEM_A_DATA_6 MEM_A_DATA_6

MEM_85D

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_A_DQS_2

MEM_85D

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_A_DQS_6

MEM_B_CS_L<1>

MEM_40S

MEM_B_CNTL1

MEM_CTRL

MEM_B_RAS_L

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_B_CAS_L

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_B_WE_L

MEM_B_CMD

MEM_CMDMEM_40S

MEM_B_DATA_3

MEM_B_DQ<31..24>

MEM_B_DATA_3

MEM_45S

MEM_B_ODT<1>

MEM_40S

MEM_B_CNTL1

MEM_CTRL

MEM_B_CKE<1>

MEM_40S

MEM_B_CNTL1

MEM_CTRL

MEM_B_CKE<0>

MEM_CTRL

MEM_40S

MEM_B_CNTL0

MEM_B_CLK_N<1>

MEM_CLKMEM_72D

MEM_B_CLK1

PP0V75_S3_MEM_VREFCA

MEM_PWR

<SCH_NUM>

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23 24 27

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24 27

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25 27

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25 26

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25 26

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25 26

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22 23 24 25 26 85 89

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

Thunderbolt IC Net Properties

Only used on hosts supporting Thunderbolt video-in

SPACING

Thunderbolt SPI Signal Constraints

TBT_DP Interface Constraints

NET_TYPE

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

Thunderbolt/DP Connector Signal Constraints

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Thunderbolt/DP Net Properties

I308

I309

I310

I311

I312

I313 I314

I315

I316 I317

I318 I319

I320

I321

I322

I323

I324

I325

I326

I327

I328 I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

Thunderbolt Constraints

SYNC_DATE=12/10/2012

SYNC_MASTER=SIDLE_J45

TBTDP_2OTHER

?*

=4X_DIELECTRIC

=6X_DIELECTRIC

* ?

TBTDP_TXRX

=3X_DIELECTRIC

*

TBTDP_2SAME

?

TBT_SPI =2x_DIELECTRIC

*

?

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

TBTDP_85D

*

TBTDP_R2D TBTDP_D2R

TBTDP_TXRX

* *

TBTDP_*

TBTDP_2OTHER

TOP,BOTTOM

?

=6X_DIELECTRIC

TBTDP_85D

=85_OHM_DIFF=85_OHM_DIFF*

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

=4x_DIELECTRIC

?

TBTDP_2SAME

TOP,BOTTOM

TBTDP_2SAME

*

=SAME

TBTDP_*

?

TOP,BOTTOMTBTDP_TXRX

=10X_DIELECTRIC

=STANDARD =STANDARD*

TBT_SPI_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE

TBTDP_85DTBT_A_R2D

TBT_A_R2D_N<1..0>

TBTDP_R2D

TBTDP_85D TBTDP_R2D

TBT_A_R2D_P<1..0>

TBT_A_R2D

TBT_A_AUXCH

DP_TBTPA_AUXCH_P

DP_85D

TBT_A_AUXCH

DP_TBTPA_AUXCH_C_N

DP_85D

TBT_A_D2R0

TBT_A_D2R_P<0>

TBTDP_D2RTBTDP_85D

TBTDP_D2R

TBT_A_D2R0

TBT_A_D2R_C_N<0>

TBTDP_85D

DP_TBTPA_ML

DP_85D

DISPLAYPORT

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML DISPLAYPORT

DP_85D

DP_A_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPA_ML_C_N<1>

TBTDP_85DTBT_A_R2D

TBT_A_R2D_C_N<1..0>

TBTDP_R2D

DP_A_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPA_ML_P<1>

DP_A_LSX_ML DISPLAYPORT

DP_85D

DP_TBTPA_ML_N<1>

DP_A_LSX_ML DISPLAYPORT

DP_85D

DP_A_LSX_ML_P<1>

DP_A_LSX_ML DISPLAYPORT

DP_85D

DP_TBTPA_ML_C_P<1>

TBTDP_85DTBT_A_R2D

TBT_A_R2D_C_P<1..0>

TBTDP_R2D

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML DISPLAYPORT

DP_85D

TBT_A_D2R1

TBT_A_D2R_C_P<1>

TBTDP_85D TBTDP_D2R

TBT_A_AUXCH

DP_TBTPA_AUXCH_C_P

DP_85D

TBT_A_D2R1

TBTDP_85D

TBT_A_D2R1_AUXDDC_N

TBTDP_D2R

TBTDP_85D

TBT_A_D2R1

TBT_A_D2R1_AUXDDC_P

TBTDP_D2R

TBTDP_85D

TBT_A_D2R1

TBT_A_D2R_N<1>

TBTDP_D2R

TBT_A_D2R1

TBT_A_D2R_C_N<1>

TBTDP_85D TBTDP_D2R

DP_85D

DP_TBTSRC_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTSRC_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_TBTSRC_AUXCH_C_P

DP_85D

DP_TBTSRC_AUXCH_C_N

DISPLAYPORT

TBT_SPI_45STBT_SPI_CLK

TBT_SPI_CLK

TBT_SPI

TBT_SPI_45S

TBT_SPI

TBT_SPI_MOSI

TBT_SPI_45S

TBT_SPI_CS_L

TBT_SPI

TBT_SPI_45S

TBT_SPI

TBT_SPI_MISO

TBT_A_D2R1

TBTDP_85D TBTDP_D2R

TBT_A_D2R_P<1>

TBT_A_D2R0

TBT_A_D2R_N<0>

TBTDP_D2RTBTDP_85D

TBT_A_D2R0

TBTDP_85D TBTDP_D2R

TBT_A_D2R_C_P<0>

DP_A_LSX_ML

DP_A_LSX_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_N<1>

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_P<1>

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_N<1>

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_B_LSX_ML_P<1>

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_B_LSX_ML_N<1>

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_P<3>

DP_TBTPB_ML

TBTDP_D2RTBTDP_85D

TBT_B_D2R_C_P<0>

TBT_B_D2R0

DP_85D

DISPLAYPORT

DP_TBTPB_ML_N<3>

DP_TBTPB_ML

TBTDP_85D TBTDP_D2R

TBT_B_D2R_P<0>

TBT_B_D2R0

TBTDP_85D TBTDP_D2R

TBT_B_D2R_N<0>

TBT_B_D2R0

TBTDP_D2RTBTDP_85D

TBT_B_D2R_C_N<1>

TBT_B_D2R1

TBTDP_D2RTBTDP_85D

TBT_B_D2R_C_P<1>

TBT_B_D2R1

TBTDP_85D TBTDP_R2D

TBT_B_R2D_C_N<1..0>

TBT_B_R2D

TBTDP_85D TBTDP_D2R

TBT_B_D2R_P<1>

TBT_B_D2R1

TBTDP_85D TBTDP_D2R

TBT_B_D2R_N<1>

TBT_B_D2R1

TBTDP_D2RTBTDP_85D

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R1

TBTDP_D2RTBTDP_85D

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R1

DP_85D

DP_TBTPB_AUXCH_C_P

TBT_B_AUXCH

DP_85D

DP_TBTPB_AUXCH_C_N

TBT_B_AUXCH

DP_85D

DP_TBTPB_AUXCH_P

TBT_B_AUXCH

DP_85D

DP_TBTPB_AUXCH_N

TBT_B_AUXCH

DP_B_LSX_ML

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_P<1>

TBTDP_85D TBTDP_R2D

TBT_B_R2D_P<1..0>

TBT_B_R2D

TBTDP_D2RTBTDP_85D

TBT_B_D2R_C_N<0>

TBT_B_D2R0

TBTDP_85D TBTDP_R2D

TBT_B_R2D_N<1..0>

TBT_B_R2D

TBTDP_85D TBTDP_R2D

TBT_B_R2D_C_P<1..0>

TBT_B_R2D

TBT_A_AUXCH

DP_TBTPA_AUXCH_N

DP_85D

DP_TBTPA_ML_P<3>

DP_TBTPA_ML

DP_85D

DISPLAYPORT

<SCH_NUM>

115 OF 119

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28 31

31

28 31

31

28 31

31

28 31

31

28 31 87

31

28

28 31 87

28 31

31

28 32

32

28 32

32

28 32

32

28 32

32

28 32

32

28 32

32

28 32

31

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Camera Net Properties

Memory Bus Spacing Group Assignments

MIPI Interface Constraints

ELECTRICAL_CONSTRAINT_SET

Spacing Rule Sets

Memory to Power Spacing

Memory to GND Spacing

SPACING

PHYSICAL

NET_TYPE

Memory Bus Constraints

I101

I102

I103 I104

I106

I107

I108

I109

I110

I127

I128

I129 I130

I131

I132

I133

I134

I145 I146

I147

I148

I149

S2MEM_2OTHER

?

=10x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

S2MEM_2PWR?TOP,BOTTOM

TOP,BOTTOM

?

S2_CMD2CTRL

=4x_DIELECTRIC

?

TOP,BOTTOM

=10X_DIELECTRIC

MIPICLK_2OTHER

TOP,BOTTOM

?

=8X_DIELECTRIC

MIPI_2CLK

MIPI_2OTHER

TOP,BOTTOM

?

=6X_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

?

S2_DATA2SELF

TOP,BOTTOM

?

S2_DQS2OWNDATA =4x_DIELECTRIC

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CMD2CMD

S2_2OTHERMEM

?

=6x_DIELECTRIC

TOP,BOTTOM

S2MEM_2GND TOP,BOTTOM

=4x_DIELECTRIC

?

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CTRL2CTRL

=2x_DIELECTRIC

?*

S2_CMD2CMD

?*

S2_CTRL2CTRL

=2x_DIELECTRIC

* ?

S2_CMD2CTRL

=2x_DIELECTRIC

S2_2OTHERMEM

=4x_DIELECTRIC

* ?

=2x_DIELECTRIC

?*

S2_DQS2OWNDATA

?*

=2x_DIELECTRIC

S2MEM_2PWR

=2x_DIELECTRIC

S2_DATA2SELF

?*

S2_MEM_CMD

S2_MEM_CTRL

S2_CMD2CTRL

*

S2_MEM_DQS*

**

S2MEM_2OTHER

S2MEM_2OTHERS2_MEM_DATA*

* *

=SAME

*

S2_DATA2SELF

S2_MEM_DATA*

S2MEM_2PWR

S2_MEM_*

S2_MEM_PWR

*

S2_MEM_PWR

**

DEFAULT

S2_MEM_DQS0

S2_DQS2OWNDATA

S2_MEM_DATA0

*

S2MEM_2OTHER

**

S2_MEM_CMD

S2MEM_2OTHER

S2_MEM_CTRL

* *

S2_MEM_CLK

*

S2MEM_2OTHER

*

S2_MEM_CMD

S2_CMD2CMD

S2_MEM_CMD

*

S2_MEM_CTRL S2_MEM_CTRL

S2_CTRL2CTRL

*

S2_2OTHERMEM

*

S2_MEM_*S2_MEM_*

GND

S2MEM_2GND

S2_MEM_*

*

MIPI_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

* =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

S2_MEM_85D

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE

*

S2_MEM_45S =45_OHM_SE

*

CLK_MIPI

*

MIPICLK_2OTHER

*

MIPI_2CLK

CLK_MIPI

MIPI_DATA

* *

MIPI_2OTHER

MIPI_DATA

MIPICLK_2OTHER

*

=7X_DIELECTRIC

?

MIPI_2CLK

*

=6X_DIELECTRIC

?

MIPI_2OTHER

?

*

=4X_DIELECTRIC

?*

S2MEM_2GND

=2x_DIELECTRIC

S2MEM_2OTHER

* ?

=6x_DIELECTRIC

S2_MEM_DQS1

S2_DQS2OWNDATA

S2_MEM_DATA1

*

Camera Constraints

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

S2_MEM_45S

S2_MEM_DATA_1

S2_MEM_DATA1

MEM_CAM_DM<1>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DQS0

MEM_CAM_DQS_N<0>

S2_MEM_DATA0

S2_MEM_DATA_0

S2_MEM_45S

MEM_CAM_DM<0>

S2_MEM_CMDS2_MEM_45S

MEM_CAM_WE_L

S2_MEM_CMD

S2_MEM_85D

S2_MEM_DQS1S2_MEM_DQS1

MEM_CAM_DQS_N<1>

S2_MEM_DATA0

S2_MEM_45S

S2_MEM_DATA_0

MEM_CAM_DQ<7..0>

S2_MEM_PWR

PP1V35_CAM

PP0V675_MEM_CAM_VREFDQ

S2_MEM_PWR

CLK_MIPI

MIPI_CLK_CONN_P

MIPI_85D

MEM_CAM_DQS_P<0>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DQS0

S2_MEM_CMD

S2_MEM_A

S2_MEM_45S

MEM_CAM_A<14..0>

PP0V675_CAM_VREF

S2_MEM_PWR

S2_MEM_CMD

MEM_CAM_BA<1>

S2_MEM_CMD S2_MEM_45S

MIPI_CLK_CONN_N

MIPI_85D CLK_MIPI

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

MEM_CAM_CLK_P

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_ODT

S2_MEM_45S

S2_MEM_CTRL

S2_MEM_CMD

MEM_CAM_CAS_L

S2_MEM_CTRL

MEM_CAM_CKE

S2_MEM_45S

S2_MEM_CNTL

S2_MEM_CTRL

S2_MEM_45SS2_MEM_CMD

MEM_CAM_RAS_L

MIPI_CLK_P

CLK_MIPI

MIPI_CLK_S2

MIPI_85D

S2_MEM_CLK S2_MEM_85D S2_MEM_CLK

MEM_CAM_CLK_N

S2_MEM_45S

S2_MEM_CTRLS2_MEM_CNTL

MEM_CAM_CS_L

S2_MEM_CMDS2_MEM_CMD S2_MEM_45S

MEM_CAM_BA<0>

MEM_CAM_BA<2>

S2_MEM_45SS2_MEM_CMD S2_MEM_CMD

CLK_MIPI

MIPI_CLK_N

MIPI_CLK_S2

MIPI_85D

PP0V675_MEM_CAM_VREFCA

S2_MEM_PWR

S2_MEM_DATA1

S2_MEM_45S

S2_MEM_DATA_1

MEM_CAM_DQ<15..8>

S2_MEM_85D

S2_MEM_DQS1S2_MEM_DQS1

MEM_CAM_DQS_P<1>

MIPI_DATA_CONN_N

MIPI_DATA

MIPI_85D

MIPI_DATA_CONN_P

MIPI_DATA

MIPI_85D

MIPI_DATA_N

MIPI_DATA

MIPI_DATA_S2 MIPI_85D

MIPI_DATA_S2

MIPI_DATA

MIPI_DATA_P

MIPI_85D

<SCH_NUM>

116 OF 119

94 OF 97

35 36

36

36 86

35 36

36 86

35 36

36

35 36

36

35 36

36 86

35 36

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC SMBus Net Properties

SMBus Charger Net Properties

PHYSICAL

NET_TYPE

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

SYNC_DATE=12/10/2012

SYNC_MASTER=SIDLE_J45

SMC Constraints

SMBUS_SMC_2_S3_SCL

SMB

SMBUS_SMC_2_S3_SCL

SMB_45S

SMBUS_SMC_1_S0_SCL

SMB

SMB_45S

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1_S0_SDA

SMB_45S

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_SDA

SMB

SMB_45S

NC_SMBUS_SMC_3_SCL

SMBUS_SMC_3_SCL

SMB

SMB_45S

SMB

SMBUS_SMC_0_S0_SCL

SMB_45S

SMBUS_SMC_2_S3_SDA

SMB

SMBUS_SMC_2_S3_SDA

SMB_45S

SMBUS_SMC_0_S0_SDA

SMB

SMB_45S

SMBUS_SMC_5_g3_SCL

SMBUS_SMC_5_SCL

SMB

SMB_45S

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

NC_SMBUS_SMC_3_SDA

SMB

SMB_45S

SMBUS_SMC_3_SDA

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

<SCH_NUM>

117 OF 119

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38 40 43 86

40 43 48

40 43 56 57 86

40 42

36 40 43 48 69 76 85 86

38 40 43 86

36 40 43 48 69 76 85 86

40 43 56 57 86

57

40 42

57

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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PAGE TITLE

SHEET

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

X425G Specific Net Properties X425G Specific Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

SPACING

NET_TYPE

PHYSICAL

NET_TYPE

DIFFERENTIAL_PAIR

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

AMD Net Properties

PHYSICAL

I357

I358

I359

I360

I361 I362

I405

I406

I407 I408

I419

I420

I421

I422

I423

I424

I425

I426

I432

I436

I440

I441 I442

I445

I446

I447

I448 I449

I450

I451

I452 I453

I454

I455

I456 I457

I458

I459

I460

I461

I462

I463

I480 I481

I482 I483

I484

I485 I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I498

I499

I502

I503

I510

I511

I514 I515

I520

I521

I522

I523

I526

I527

I528

I529

I530

I531

I532

I533

I534 I535

I536

I537

I538

I539

I540

I541

I542

I543

I544

I545

I546 I547

I548

I549

I550

I551

I552 I553

I554 I555

I556

I557 I558

I559

I560 I561

I562

I563 I564

I565

I566

I567

I568 I569

I570

I571

SYNC_DATE=12/10/2012

Project Specific Constraints

SYNC_MASTER=SIDLE_J45

SENSE_GPUVR

Y

0.300 MM 0.200 MM 3.000 MM

0.400 MM 0.200 MM

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

=1:1_DIFFPAIR

SENSE_1TO1_45S

=1:1_DIFFPAIR

CLK_PCIE

GND

*

GND_P2MM

500 MIL

TOP

0.1 MM

USB3_85D

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

*

THERM_1TO1_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE

PCIE_*

*

GND

GND_P2MM

SATA_*

GND

GND_P2MM

*

GND_P2MM

*

0.20 MM

1000

0.20 MM

1000

*

PWR_P2MM

GND

?

*

=STANDARD

GNDUSB

GND_P2MM

*

?

=2X_DIELECTRIC

AUDIO

1:1_DIFFPAIR

*

1TO1_DIFFPAIR

?

*

=2X_DIELECTRIC

THERM

SENSE

?

*

=2X_DIELECTRIC

MEM_72D

*

100 MIL0.09 MM

SENSE_1TO1_50S

=1:1_DIFFPAIR

=50_OHM_SE

=1:1_DIFFPAIR

=50_OHM_SE

*

=1:1_DIFFPAIR

=50_OHM_SE

0.075 MM

DP_85D

0.090 MM

ISL9

0.075 MM

ISL10

USB3_85D

0.090 MM

*

100 MILMEM_85D 0.09 MM

*

100 MILMEM_37S 0.09 MM

PCIE_85D

0.090 MM

ISL10

0.075 MM

=1:1_DIFFPAIR

=50_OHM_SE=50_OHM_SE

THERM_1TO1_50S

*

=1:1_DIFFPAIR

=50_OHM_SE

10 MM

0.09 MM

PCIE_85D

*

USB_85D

TOP

500 MIL

0.1 MM

CPU_27P4S

BOTTOM

0.23 MM 100 MIL

GND

*

CPU_COMP GND_P2MM

GND

CPU_VCCSENSE

GND_P2MM

*

PWR_P2MM

*

SB_POWERCLK_PCIE

SB_POWER

*

PWR_P2MM

SATA_*

PWR_P2MMSB_POWER

USB

*

MEM_40S 0.09 MM 100 MIL

*

0.2 MM

=1:1_DIFFPAIR

=45_OHM_SE =45_OHM_SETHERM_45S_CPUVRISNS1

0.2 MM

=45_OHM_SE

0.1 MM

AUDIODIFF

*

0.1 MM

0.1 MM0.1 MM

=1:1_DIFFPAIR

10 MM

=1:1_DIFFPAIR =1:1_DIFFPAIR

DIFFPAIR

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR

TBT_THERMDN

THERM

THERM_1TO1_45S

AUDIO

AUDIODIFF

CHGR_CSO_R_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

CHGR_CSO_R_P

AUDIO_DIFFPAIR

CHGR_CSI_R_P

AUDIO

AUDIODIFF

THERM

P1V05S0_SENSE

THERM_1TO1_45S

P1V05S0_SENSE_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_LCDBKLT_N

SENSE

SENSE_1TO1_45S

ISNS_AIRPORT_R_N

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

ISNS_LCDBKLT_P

ISNS_AIRPORT_R_P

SENSE_1TO1_45S

SENSE

SENSE_1TO1_45S

ISNS_AIRPORT_N

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_LCD_PANEL_P

AUDIODIFF

AUD_SPKRAMP_LIN_N

AUDIO

SENSE

ISNS_1V35_MEM_R_P

SENSE_1TO1_45S

FINTHMSNS_D_N

THERM

THERM_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

ISNS_1V35_MEM_N

SENSE

SENSE_DIFFPAIR

ISNS_1V35_MEM_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR THERM_1TO1_45S

GFXIMVP_ISNS1_P

THERM

THERM_1TO1_45S

GFXIMVP_ISNS1_N

THERM

SENSE_DIFFPAIR

AUDIO

AUDIODIFF

CHGR_CSI_R_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

GFXIMVP_ISNS2_N

SENSE

ISNS_HS_GPU_P

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S

SENSE

VDDCIS0_CS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_PP0V95_S0GPU_N

SENSE_DIFFPAIR

TBT_THERMDP

THERM

SENSE_DIFFPAIR THERM_1TO1_45S

SENSE

SENSE_1TO1_45S

ISNS_PP0V95_S0GPU_P

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S

VDDCIS0_CS_N

SENSE

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

GPUTHMSNS_D_N

SENSE_1TO1_45S

GPU_VDDCISENSE_P

SENSE

SENSE_DIFFPAIR

ISNS_PP0V95_S0GPU_R_N

SENSE

SENSE_1TO1_45S

THERM_1TO1_45S

SENSE

VSNS_GPU_0V95_XW_N

SENSE_1TO1_45S

VDDCIS0_CS_R_P

SENSE

SENSE_DIFFPAIR

GPUFB_CS_R_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

GPUFB_CS_R_N

SENSE

SENSE_1TO1_45S

SENSE

VSNS_GPU_VDDC_N

SENSE_DIFFPAIR

VSNS_GPU_VDDI_N

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

VSNS_GPU_VDDI_P

SENSE_DIFFPAIR

VSNS_GPU_VDDC_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

THERM

THERM_1TO1_45S

GPUFB_CS_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

GPUVCORE_SENSE_N

GPU_TDIODE_N

THERM_1TO1_45S

THERM

SENSE

SENSE_1TO1_45S

VDDCIS0_CS_R_N

GPUVCORE_SENSE_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_PP0V95_S0GPU_R_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE

VSNS_GPU_0V95_XW_P

THERM_1TO1_45S

THERM

P1V05S0_CS_N

THERM_1TO1_45S

THERM

ISNS_SSD_N

THERM

ISNS_SSD_R_P

THERM_1TO1_45SSENSE_DIFFPAIR

AUDIODIFF

ISNS_TBT_R_N

AUDIO

ISNS_TBT_R_P

AUDIO

AUDIODIFF

ISNS_SSD_P

THERM

THERM_1TO1_45SSENSE_DIFFPAIR

THERM_1TO1_45S

THERM

CPUTHMSNS_D2_N

SENSE_DIFFPAIR

ISNS_LCD_PANEL_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR

ISNS_LCD_PANEL_N

SENSE

SENSE_1TO1_45S

SENSE_DIFFPAIR

THERM

DDR3THMSNS_D1_P

THERM_1TO1_45S

ISNS_SSD_R_N

THERM

THERM_1TO1_45S

AUDIO_DIFFPAIR

DIFFPAIR

SPKRCONN_SR_OUT_N

AUDIO AUDIO

SPKRCONN_L_OUT_P

DIFFPAIR

AUDIO_DIFFPAIR

SPKRCONN_R_OUT_P

AUDIO

AUDIO_DIFFPAIR

DIFFPAIR DIFFPAIR

SPKRCONN_R_OUT_N

AUDIO_DIFFPAIR

AUDIO AUDIO

AUD_MIC_IN1_R_P

AUDIO_DIFFPAIR

DIFFPAIR

PP1V35_S3RS0_CPUDDR

SB_POWER

AUDIO

AUD_SPKRAMP_LIN_P

AUDIODIFF

ISNS_AIRPORT_P

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_1V35_MEM_R_N

CPUVR_ISNS1

CPUVR_ISNS1_N

SENSE_DIFFPAIR

THERM

THERM_45S_CPUVRISNS1

THERM_1TO1_45S

GFXIMVP_ISNS1_P

THERM

SENSE_DIFFPAIR

AUDIODIFF

AUDIO

ISNS_TBT_P

AUDIO_DIFFPAIR

AUDIODIFF

ISNS_TBT_N

AUDIO

AUDIO_DIFFPAIR

SENSE_DIFFPAIR

THERM

THERM_45S_CPUVRISNS1

CPUVR_ISNS2

CPUVR_ISNS2_P

CPUVR_ISNS3_N

THERM

CPUVR_ISNS3

SENSE_DIFFPAIR

THERM_45S_CPUVRISNS1

THERM

SENSE_DIFFPAIR

CPUVR_ISUM_R_N

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR THERM_1TO1_45S

CPUVR_ISUM_R_P

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

GFXIMVP_ISNS1_N

THERM

THERM_1TO1_45S

ISNS_CPU_DDR_R_P ISNS_CPU_DDR_R_N

THERM

THERM_1TO1_45S

AUDIO_DIFFPAIR

AUDIO

SPKRCONN_L_OUT_N

DIFFPAIR

AUDIO

AUD_HS_MIC_P

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

DIFFPAIR

CODEC_HS_MIC_P

DIFFPAIR

SPKRCONN_SR_OUT_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO

AUD_SPKRAMP_RSUBIN_P

AUDIO

SPKRAMP_RIN_N

AUDIODIFF

AUD_SPKRAMP_LSUBIN_N

AUDIODIFF

AUDIO

SB_POWER

PP3V3_S0

PP3V3_S5

SB_POWER

AUDIO

AUD_LO2_L_N

AUDIO_DIFFPAIR

AUDIODIFF

AUD_SPKRAMP_RIN_P

AUDIO

AUDIODIFF

AUDIO

RSUBIN_P

AUD_SPKRAMP_LSUBIN_P

AUDIODIFF

AUDIO

AUDIODIFF

AUDIO

AUD_SPKRAMP_RSUBIN_N

SPKRCONN_SL_OUT_N

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

AUD_LO3_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO3_R_N

AUDIO

AUDIODIFF

SPKRAMP_RIN_P

AUDIO

AUDIODIFF

AUDIO

DIFFPAIR

AUD_HS_MIC_N

AUDIO

HS_MIC_P

DIFFPAIR

AUDIO

AUD_LO3_L_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO3_R_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

DIFFPAIR

AUD_MIC_IN1_L_P

AUD_MIC_IN1_R_N

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_TPAD_N

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

CPUTHMSNS_D2_P

THERM

DDR3THMSNS_D1_N

THERM_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR

THERM

FINTHMSNS_D_P

THERM_1TO1_45S

SENSE_DIFFPAIR

GPUTHMSNS_D_P

THERM_1TO1_45S

THERM

SENSE

SENSE_1TO1_45S

ISNS_HS_GPU_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

GFXIMVP_ISNS2_P

P1V05S0_CS_P

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

P1V05S0_SENSE

P1V05S0_SENSE_P

SENSE

ISNS_HS_COMPUTING_P

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

GPU_VDDCISENSE_N

SENSE_DIFFPAIR

SENSE

ISNS_1V8_GPU_P

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

THERM_1TO1_45S

VSNS_GPU_FB_XW_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_1V8_GPU_N

SENSE_DIFFPAIR

SENSE

GPU_VDDCI_SENSE_XW_N

SENSE_1TO1_45S

GPU_VDDCI_SENSE_XW_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

GPU_TDIODE_P

THERM

THERM_1TO1_45SSENSE_DIFFPAIR

THERM

THERM_1TO1_45S

GPUFB_CS_P

SENSE_DIFFPAIR

SENSE

SENSE_DIFFPAIR THERM_1TO1_45S

VSNS_GPU_FB_XW_P

ISNS_1V8_GPU_R_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_1V8_GPU_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

CPUVR_ISNS3_P

SENSE_DIFFPAIR

THERM

CPUVR_ISNS3

THERM_45S_CPUVRISNS1

CPUVR_ISNS2_N

SENSE_DIFFPAIR

THERM

THERM_45S_CPUVRISNS1

CPUVR_ISNS2

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_TPAD_P

AUDIO

AUD_CONN_HS_MIC_N

DIFFPAIR

AUDIO

AUD_CONN_HS_MIC_P

DIFFPAIR

HS_MIC_N

AUDIO

DIFFPAIR

AUDIO

DIFFPAIR

AUD_MIC_IN1_L_N

AUDIO

DIFFPAIR

CODEC_HS_MIC_N

AUDIO_DIFFPAIR

SPKRCONN_SL_OUT_P

AUDIO_DIFFPAIR

DIFFPAIR

AUDIO

AUDIODIFF

AUDIO

SPKRAMP_LIN_N

AUDIODIFF

AUDIO

SPKRAMP_LIN_P

AUD_SPKRAMP_RIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO2_L_P

AUDIODIFF

AUDIO

AUD_LO2_R_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUDIODIFF

AUD_LO2_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

LSUBIN_N

AUDIODIFF

AUDIO

LSUBIN_P

AUDIODIFF

RSUBIN_N

AUDIO

SENSE_DIFFPAIR

ISNS_CPUDDR_N

THERM

THERM_1TO1_45S

ISNS_CPUDDR_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

SENSE_DIFFPAIR

SENSE

ISNS_LCD_PANEL_N

SENSE_1TO1_45S

ISNS_PCH_R_N

SENSE

SENSE_1TO1_45S

ISNS_PCH_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_HS_OTHER5V_P

SENSE

ISNS_HS_OTHER5V_N

SENSE_DIFFPAIR SENSE_1TO1_45S

CPUVR_ISNS_N

SENSE

SENSE_1TO1_45S

P1V05_GPU_PEX_IOVDD_SNS_N

THERM

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

CPUVR_ISNS1_P

SENSE_DIFFPAIR

THERM_45S_CPUVRISNS1

CPUVR_ISNS1

P1V05_GPU_PEX_IOVDD_SNS_P

THERM

SENSE_DIFFPAIR THERM_1TO1_45S

SENSE

CPUVR_ISNS_P

SENSE_1TO1_45S

SENSE

ISNS_HS_OTHER3V3_N

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_OTHER3V3_P

SENSE_DIFFPAIR SENSE_1TO1_45S

GND

<SCH_NUM>

118 OF 119

96 OF 97

48

57

62

63

46

63

46

46 69 96

53

45

79 96

57

79

47

47 80

47 73

28 48

47 73

47 80

48

47

73

47

71 79

71 80

71 80 85

71 79 85

47 73

79

48 76

47

79

47

73

45 62

45

48

46 69 96

48

45

53 55 86

6 8

10 21 66 67 84

53

45

45 59

79 96

45

45 59

45

79 96

46

53 55 86

54 55

51

53 55 86

53

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86

12 14 15 17 18 19 21 31 32 33

61 64

66 67 82 84 85 86

51 53

53

53 55 86

51 53

53

54 55

51 54

51 53

45

48

47

79

45 62

62

44

73

80

48 76

47 73

73

45 59

45

51 54

51

53 55 86

53

51 53

53

46 66

46 69 96

45

44

45

45 59

45

44

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NET_TYPE

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

PHYSICAL

GDDR5 FB B Net Properties

SPACING

NET_TYPE

GDDR5 FB A Net Properties

PHYSICAL

Kepler Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

GDDR5 Frame Buffer Signal Constraints

Breakout Spacing

GDDR5_CMD spacing can be relaxed to 2x per AMD recommendation for x32_4.5G config.

MUXGFX & DP AUX MUX NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

I337

I338

I339 I340

I345 I346

I349 I350

I371

I372

I373

I374

I375

I376

I377

I378

I379

I380 I381

I382

I383

I384

I385

I386

I387

I388

I389

I390

I391

I392

I393

I394

I395

I396

I397

I398

I399

I400

I401

I402

I403

I404 I405

I406

I407

I408

I409

I410

I411

I412 I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423

I424

I425

I426

I427

I428

I429

I430

I431

I432

I433

I434

I435

I436

I437 I438

I439

I440 I441

I442 I443

I444

I445

I446

I447

I448 I449

I450

I451

I452

I453 I454

I455

I456

I457 I458

I459

I460 I461

I462

I463

I464

I465

I466

I467

I468 I469

I470

I471

I472

I473 I474

I477

I478

I479

I480

I481

I482

I483

I484

I485

I486

I487

I488

I489

I490

I491

I492

I493

I494 I495

I496

I497

I498

I499

I500

I501

I502

I513

I514

I515

I516

I517

I518 I519

I520

SYNC_MASTER=J45G_AMD SYNC_DATE=07/01/2014

GPU (AMD VENUS) Constraints

*

?

GDDR5_DATA

=3x_DIELECTRIC

*

GDDR5_EDC

?

=7x_DIELECTRIC

GDDR5_BGA

BGA

*

GDDR5_*

*

?

GDDR5_BGA

=1.3x_DIELECTRIC

?

*

=5x_DIELECTRIC

GDDR5_CLK

=80_OHM_DIFF

*

=80_OHM_DIFF

GDDR5_80D

?

*

=3x_DIELECTRIC

GDDR5_CMD

=45_OHM_SEGDDR5_45SE =45_OHM_SE=45_OHM_SE

* =STANDARD=STANDARD

=45_OHM_SE

?

TOP,BOTTOM

GDDR5_EDC

=7x_DIELECTRIC

GDDR5_DATA?TOP,BOTTOM

=5x_DIELECTRIC

TOP,BOTTOM

=5x_DIELECTRIC

?

GDDR5_CLK

=4x_DIELECTRIC

?

GDDR5_CMD

TOP,BOTTOM

=50_OHM_SE

GDDR5_45R50SE

*

=50_OHM_SE

=STANDARD

12.7 MM

=STANDARD

GDDR5_CMD

FB_A0_A<8..0>

FB_A0_CMD

GDDR5_45SE

FB_A1_ABI_L

FB_A1_CMD GDDR5_CMD

GDDR5_45SE

FB_B0_DBI_L3

GDDR5_45SE GDDR5_DATA

FB_B0_DBI_L<3>

GDDR5_DATA

FB_B1_DBI_L<0>

GDDR5_45SE

FB_B1_DBI_L0

FB_A1_DBI_L2

FB_A1_DBI_L<2>

GDDR5_DATAGDDR5_45SE

GDDR5_CLKGDDR5_80D

FB_B1_WCLK_N<1>

FB_B1_WCLK1

GDDR5_CLK

FB_B0_WCLK_P<1>

GDDR5_80D

FB_B0_WCLK1

FB_B0_DBI_L<2>

GDDR5_DATAGDDR5_45SE

FB_B0_DBI_L2

FB_B1_EDC0

GDDR5_EDC

GDDR5_45SE

FB_B1_EDC<0>

FB_B0_EDC<1>

FB_B0_EDC1

GDDR5_EDC

GDDR5_45SE

FB_B1_CS_L

FB_B1_CMD

GDDR5_45SE

GDDR5_CMD

FB_B0_CS_L

GDDR5_CMDFB_B0_CMD

GDDR5_45SE

GDDR5_CMD

GDDR5_45SE

FB_B1_CKE_L

FB_B1_CMD

FB_B0_CKE_L

GDDR5_CMD

GDDR5_45SE

FB_B0_CMD

FB_B0_WE_L

GDDR5_CMD

GDDR5_45SE

FB_B0_CMD

FB_B1_WE_L

GDDR5_CMD

GDDR5_45SE

FB_B1_CMD

GDDR5_CMD

FB_A1_CKE_L

FB_A1_CMD

GDDR5_45SE

GDDR5_CMD

GDDR5_45SE

FB_A0_WE_L

FB_A0_CMD

GDDR5_CMD

GDDR5_45SE

FB_A1_WE_L

FB_A1_CMD

FB_A0_CKE_L

GDDR5_45SE

GDDR5_CMDFB_A0_CMD

GDDR5_CMDFB_A1_CMD

GDDR5_45SE

FB_A1_CAS_L

FB_A0_CMD GDDR5_CMD

FB_A0_CAS_L

GDDR5_45SE

FB_A0_RAS_L

FB_A0_CMD GDDR5_CMD

GDDR5_45SE

GDDR5_CLKGDDR5_80D

FB_A1_CLK_N

FB_A1_CLK

FB_A1_CLK_P

GDDR5_80D GDDR5_CLKFB_A1_CLK

FB_A0_CMD GDDR5_CMD

GDDR5_45SE

FB_A0_ABI_L

FB_A1_CMD

FB_A1_RAS_L

GDDR5_CMD

GDDR5_45SE

FB_A1_CMD

GDDR5_45SE

FB_A1_A<8..0>

GDDR5_CMD

FB_A0_CLK

FB_A0_CLK_N

GDDR5_80D GDDR5_CLK

FB_A0_CLK

FB_A0_CLK_P

GDDR5_CLKGDDR5_80D

GDDR5_45SE

FB_A0_DBI_L<3>

FB_A0_DBI_L3

GDDR5_DATA

TBTSNK_AUXCH

DP_85D

DP_TBTSNK0_AUXCH_N

DISPLAYPORT

TBTSNK_AUXCH

DP_85D

DP_TBTSNK0_AUXCH_P

DISPLAYPORT

TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_N

DISPLAYPORT

TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_P

DISPLAYPORT

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_ML_N<3..0>

DP_85D

DP_INT_ML

DISPLAYPORT

DP_INT_ML_P<3..0>

GDDR5_45SE

FB_A1_CMD_R

FB_A1_RESET_L

GDDR5_CMD

GDDR5_DATA

FB_A1_DQ<31..24>

FB_A1_DQ_BYTE3

GDDR5_45SE

GDDR5_DATA

FB_A0_DQ_BYTE2

GDDR5_45SE

FB_A0_DQ<23..16>

GDDR5_DATA

FB_A0_DQ_BYTE0

GDDR5_45SE

FB_A0_DQ<7..0>

FB_A1_WCLK_N<1>

GDDR5_CLKGDDR5_80D

FB_A1_WCLK1

GDDR5_CLK

FB_A1_WCLK1

GDDR5_80D

FB_A1_WCLK_P<1>

DP_INT_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_85D

DP_INT_ML_C_N<3..0>

DISPLAYPORT

DP_INT_ML_F_P<3..0>

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_AUX_P

DP_INT_AUXCH

DP_85D

DP_INT_ML_F_N<3..0>

DISPLAYPORT

GDDR5_45SE

FB_A1_DQ_BYTE2

FB_A1_DQ<23..16>

GDDR5_DATA

GDDR5_45SE

FB_A1_DQ<15..8>

GDDR5_DATA

FB_A1_DQ_BYTE1

DP_85D

DISPLAYPORT

DP_INT_AUXCH_C_N

FB_A0_DBI_L1

GDDR5_45SE

FB_A0_DBI_L<1>

GDDR5_DATA

FB_A0_DBI_L<0>

FB_A0_DBI_L0

GDDR5_45SE GDDR5_DATA

FB_A1_EDC<3>

GDDR5_45SE

GDDR5_EDC

FB_A1_EDC3

FB_A1_EDC<2>

GDDR5_EDC

GDDR5_45SEFB_A1_EDC2

FB_A1_EDC<1>

GDDR5_EDC

GDDR5_45SEFB_A1_EDC1

FB_A0_EDC<1>

GDDR5_EDC

GDDR5_45SEFB_A0_EDC1

FB_A0_DBI_L2

FB_A0_DBI_L<2>

GDDR5_45SE GDDR5_DATA

GDDR5_DATAGDDR5_45SE

FB_A1_DBI_L<1>

FB_A1_DBI_L1

GDDR5_80D

FB_A0_WCLK0

FB_A0_WCLK_P<0>

GDDR5_CLK GDDR5_CLKGDDR5_80D

FB_A0_WCLK0

FB_A0_WCLK_N<0>

FB_A1_EDC0

FB_A1_EDC<0>

GDDR5_EDC

GDDR5_45SE

FB_A0_DQ<15..8>

FB_A0_DQ_BYTE1

GDDR5_DATA

DISPLAYPORT

DP_85D

HDMI_DATA

HDMI_EG_DATA_N<2..0>

GDDR5_CLK

FB_B1_WCLK_P<1>

GDDR5_80D

FB_B1_WCLK1

GDDR5_CLKGDDR5_80D

FB_B1_WCLK_N<0>

FB_B1_WCLK0

GDDR5_CLK

FB_B1_WCLK0

GDDR5_80D

FB_B1_WCLK_P<0>

GDDR5_CLK

FB_B0_WCLK_N<0>

GDDR5_80D

FB_B0_WCLK0

GDDR5_CLK

FB_B0_WCLK_P<0>

GDDR5_80D

FB_B0_WCLK0

GDDR5_CLK

FB_A0_WCLK_N<1>

FB_A0_WCLK1

GDDR5_80D

GDDR5_CLK

FB_A1_WCLK_P<0>

FB_A1_WCLK0

GDDR5_80D

GDDR5_CLKGDDR5_80D

FB_A1_WCLK0

FB_A1_WCLK_N<0>

GDDR5_CLK

FB_A0_WCLK1

GDDR5_80D

FB_A0_WCLK_P<1>

FB_A1_DBI_L3

FB_A1_DBI_L<3>

GDDR5_45SE GDDR5_DATA

FB_B0_DBI_L<1>

GDDR5_DATA

FB_B0_DBI_L1

GDDR5_45SE

FB_B1_DBI_L<3>

GDDR5_DATA

FB_B1_DBI_L3

GDDR5_45SE

FB_A1_DQ<7..0>

GDDR5_DATA

FB_A1_DQ_BYTE0

FB_B0_DBI_L<0>

GDDR5_DATAGDDR5_45SE

FB_B0_DBI_L0

FB_B0_EDC<0>

FB_B0_EDC0

GDDR5_EDC

GDDR5_45SE

FB_B0_EDC<3>

FB_B0_EDC3

GDDR5_EDC

GDDR5_45SE

FB_B1_DBI_L<2>

GDDR5_DATA

FB_B1_DBI_L2

FB_B1_EDC<1>

FB_B1_EDC1

GDDR5_EDC

GDDR5_45SE

FB_B1_ABI_L

GDDR5_CMD

GDDR5_45SE

FB_B1_CMD

FB_B0_ABI_L

FB_B0_CMD GDDR5_CMD

GDDR5_45SE

FB_B0_CLK_P

FB_B0_CLK GDDR5_CLKGDDR5_80D

FB_B0_CLK_N

FB_B0_CLK GDDR5_CLKGDDR5_80D

FB_B1_CLK_P

FB_B1_CLK GDDR5_CLKGDDR5_80D

FB_B1_CLK_N

FB_B1_CLK GDDR5_CLKGDDR5_80D

FB_B1_A<8..0>

FB_B1_CMD GDDR5_CMD

GDDR5_45SE

FB_B0_A<8..0>

FB_B0_CMD GDDR5_CMD

GDDR5_45SE

FB_B1_EDC2

FB_B1_EDC<2>

GDDR5_EDC

GDDR5_45SE

FB_B0_EDC2

GDDR5_EDC

GDDR5_45SE

FB_B0_EDC<2>

FB_A0_DQ<31..24>

GDDR5_DATAGDDR5_45SE

FB_A0_DQ_BYTE3

FB_B1_DQ<31..24>

GDDR5_45SE GDDR5_DATA

FB_B1_DQ_BYTE3

GDDR5_EDC

FB_B1_EDC<3>

FB_B1_EDC3 GDDR5_45SE

GDDR5_45SE

GDDR5_EDC

FB_A0_EDC<3>

FB_A0_EDC3

FB_A0_EDC<2>

GDDR5_45SEFB_A0_EDC2

GDDR5_EDC

FB_B0_DQ<31..24>

GDDR5_DATAGDDR5_45SE

FB_B0_DQ_BYTE3

GDDR5_DATAGDDR5_45SE

FB_B0_DQ<23..16>

FB_B0_DQ_BYTE2

FB_B0_DQ<15..8>

GDDR5_DATAGDDR5_45SE

FB_B0_DQ_BYTE1

FB_B0_DQ<7..0>

GDDR5_DATAGDDR5_45SE

FB_B0_DQ_BYTE0

DP_TBT_ML1

DP_85D

DISPLAYPORT

DP_TBTSNK1_ML_N<3..0>

FB_A1_DBI_L0

GDDR5_DATA

FB_A1_DBI_L<0>

GDDR5_45SE

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_C_N<3..0>

DISPLAYPORT

DP_TBTSNK1_ML_P<3..0>

DP_TBT_ML1

DP_85D

FB_B0_RESET_L

FB_B0_CMD_R

GDDR5_45SE

GDDR5_CMD

FB_B1_DQ_BYTE2

GDDR5_45SE GDDR5_DATA

FB_B1_DQ<23..16>

GDDR5_DATAGDDR5_45SE

FB_B1_DQ<7..0>

FB_B1_DQ_BYTE0

GDDR5_45SE

FB_A0_CMD_R

GDDR5_CMD

FB_A0_RESET_L

FB_B1_CMD_R

FB_B1_RESET_L

GDDR5_CMD

GDDR5_45SE

FB_B1_DQ_BYTE1

FB_B1_DQ<15..8>

GDDR5_45SE GDDR5_DATA

GDDR5_CLK

FB_B0_WCLK1

FB_B0_WCLK_N<1>

GDDR5_80D

FB_B1_DBI_L<1>

GDDR5_DATAGDDR5_45SE

FB_B1_DBI_L1

FB_A0_EDC0

GDDR5_EDC

GDDR5_45SE

FB_A0_EDC<0>

FB_A1_CS_L

FB_A1_CMD GDDR5_CMD

GDDR5_45SE

FB_A0_CS_L

GDDR5_CMD

GDDR5_45SE

FB_A0_CMD

FB_B1_CMD GDDR5_CMD

GDDR5_45SE

FB_B1_CAS_L

FB_B0_CAS_L

FB_B0_CMD

GDDR5_45SE

GDDR5_CMD

FB_B1_RAS_L

FB_B1_CMD GDDR5_CMD

GDDR5_45SE

FB_B0_RAS_L

FB_B0_CMD GDDR5_CMD

GDDR5_45SE

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_P<3..0>

DP_85D

DP_TBT_ML

DISPLAYPORT

DP_TBTSNK0_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_TBTSNK1_AUXCH_C_N

DP_85D

DP_TBTSNK0_ML_N<3..0>

DISPLAYPORT

DP_TBT_ML

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_C_P<3..0>

DP_85D

HDMI_CLKHDMI_CLK

HDMI_EG_CLK_P

DP_85D

DP_INT_AUXCH_C_P

DISPLAYPORT

DP_INT_AUXCH

DP_85D

DISPLAYPORT

DP_INT_AUX_N

DP_85D

DP_INT_EG_AUX_P

DISPLAYPORT

1:1_DIFFPAIR

GPU_CLK_TEST_RC_P

1:1_DIFFPAIR

GPU_CLK_TEST_RC_N

1:1_DIFFPAIR

GPU_CLK_TEST

GPU_CLK_TEST_P

1:1_DIFFPAIR

GPU_CLK_TEST

GPU_CLK_TEST_N

DP_85D

DP_TBTSNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

HDMI_DATA

HDMI_EG_DATA_P<2..0>

DP_85D

HDMI_CLK HDMI_CLK

HDMI_EG_CLK_N

DP_85D

DP_TBTSNK0_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_TBTSNK0_AUXCH_C_N

DISPLAYPORT

DP_INT_ML

DP_85D

DP_INT_IG_ML_P<3..0>

DISPLAYPORT

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_EG_ML_P<3..0>

DP_85D

DP_INT_IG_AUX_N

DISPLAYPORT

DP_85D

DP_INT_IG_AUX_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_EG_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_INT_EG_AUX_N

DP_85D

DISPLAYPORT

DP_INT_IG_ML_N<3..0>

DP_EG_AUX

DP_TBTSNK1_EG_AUXCH_N

DP_85D

DISPLAYPORT

DP_EG_AUX

DP_85D

DP_TBTSNK1_EG_AUXCH_P

DISPLAYPORT

DP_EG_AUX

DP_85D

DISPLAYPORT

DP_TBTSNK0_EG_AUXCH_N

DP_EG_AUX

DP_TBTSNK0_EG_AUXCH_P

DISPLAYPORT

DP_85D

<SCH_NUM>

119 OF 119

97 OF 97

72 74

72 75

72 74

72 75

72 74

28 89

69 86

72 74

69 82

69

69 86

69

72 74

69 82

72 74

76 81 86

72 75

72 74

72 75

72 74

72 75

72 74

72 75

72 74

72 75

28 89

72 74

28 76 89

28 89

72 75

72 74

72 75

28 76 89

28 89

28 83 89

28 89

28 76 89

76 81 86

69 82

69 86

76 77 82

72

28 83 89

76 81 86

28 83 89

5

82 85

76 82

5

82 85

5

82 85

76 82

76 77 82

5

82 85

76 77 83

Apple X425G Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual