Apple X425G Schematics

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

Page

TABLE_TABLEOFCONTENTS_ITEM

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

<ECO_DESCRIPTION>

SCHEM,MLB,VENUS,X425G

EVT 01/12/2015

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

(.csa)

61

SPI Debug Connector

62

AUDIO:CODEC, ANALOG

63

AUDIO:CODEC, DIGITAL

64

AUDIO: SPEAKER AMP

65

AUDIO: JACK

66

AUDIO: JACK TRANSLATORS

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.5 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

1.35V DDR3L SUPPLY

75

5V / 3.3V Power Supply

76

1V05V POWER SUPPLY

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

79

X249 POWER SUPPLY

80

Power FETs

81

Power Control 1/ENABLE

82

Power Sequencing EG/PGOOD

83

eDP Display Connector

84

Venus PCI-E

85

Venus CORE/FB POWER

86

Venus FRAME BUFFER I/F

87

0V95 GPU / 1V35 FB Power Supply

88

GDDR5 Frame Buffer A

89

GDDR5 Frame Buffer B

90

Venus HDMI/DP/GPIO

91

Venus GPIOs & STRAPs

92

Venus DP PWR/GNDs

93

GFX IMVP VCore Regulator

94

VREG GPU VDDCI

95

RIO Connectors

96

eDP Mux

97

eDP Muxed Graphics Support

100

Power Aliases

102

Signal Aliases

104

Functional Test Points

105

NC & No Test

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

GPU (AMD VENUS) Constraints

Contents

CLEAN_X425

JOE_J45

CLEAN_X305

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X305_PEG

CLEAN_X425

CLEAN_X305

CLEAN_MAXWELL

J45_IG

MARY_X425G

J45G_AMD

ADITYA_X425G

MARY_X425G

ADITYA_X425G

CLEAN_MAXWELL

MARY_X425G

CLEAN_X305

J15_MLB

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

J45G_AMD

(.csa)

1

1 2 3 4 5 6 7 8 9

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU DMI/PEG/FDI/RSVD

6

CPU Clock/Misc/JTAG/CFG

7

CPU DDR3 Interfaces

8

CPU Power

9

CPU Ground

10

CPU Decoupling

11

PCH RTC/HDA/JTAG/SATA/CLK

12

PCH DMI/FDI/PM/GFX/PCI

13

PCH PCI-E/USB

14

PCH GPIO/MISC/NCTF

15

PCH Power

16

PCH Grounds

17

PCH DECOUPLING

18

CPU & PCH XDP

19

Chipset Support

20

Project Chipset Support

21

CPU Memory S3 Support

22

DDR3 VREF MARGINING

23

DDR3 SDRAM Bank A (1 OF 2)

24

DDR3 SDRAM Bank A (2 OF 2)

25

DDR3 SDRAM Bank B (1 OF 2)

26

DDR3 SDRAM Bank B (2 OF 2)

27

DDR3 Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

35

X87 CONNECTOR

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

46

USB 3.0 CONNECTORS

48

KEYBOARD/TRACKPAD (1 OF 2)

49

KEYBOARD/TRACKPAD (2 OF 2)

50

SMC

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Voltage and Current Sensing

55

Load Side Voltage and Current Sensing

56

Debug Sensors

57

GPU V/I Sensors

58

Thermal Sensors

60

Fan Connectors

Contents

MASTER

CLEAN_X305

J15_MLB

CLEAN_X305G

CLEAN_X305_PEG

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

CLEAN_X305G

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

CLEAN_X425

J15_MLB

CLEAN_X425

J15_REFERENCE

CLEAN_MAXWELL

CLEAN_X425

J15_MLB

CLEAN_X425

T29_RR

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X425G

CLEAN_MAXWELL

CLEAN_X305

CLEAN_X305G

CLEAN_X305_PEG

CLEAN_X425G

CLEAN_X305

J45G_AMD

CHANG_J45

J15_MLB

Sync

Date

MASTER

05/30/2014

10/31/2012

08/08/2014

02/18/2014

12/18/2012

10/31/2014

12/18/2012

08/11/2014

12/18/2012

10/31/2014

12/18/2012

10/30/2014

10/31/2012

10/31/2014

01/14/2013

07/02/2014

08/11/2014

10/31/2012

10/30/2014

01/14/2013

10/30/2014

06/24/2014

10/30/2014

08/15/2014

10/30/2014

09/10/2014

07/02/2014

01/15/2014

06/24/2014

08/11/2014

02/18/2014

09/10/2014

01/14/2014

07/01/2014

11/26/2012

10/31/2012

Page

TABLE_TABLEOFCONTENTS_ITEM

Sync

Date

08/15/2014

07/30/2013

06/24/2014

11/04/2014

01/15/2014

01/09/2015

01/15/2014

11/04/2014

02/18/2014

10/30/2014

01/15/2014

07/02/2014

07/01/2014

09/11/2014

12/11/2014

08/22/2014

09/22/2014

06/30/2014

09/16/2014

09/22/2014

11/07/2014

09/22/2014

09/15/2014

09/16/2014

07/01/2014

09/22/2014

10/15/2014

05/30/2014

10/31/2012

12/10/2012

02/18/2014

12/10/2012

02/18/2014

12/10/2012

07/01/2014

Schematic / PCB #’s

TITLE=MLB ABBREV=ABBREV

LAST_MODIFIED=Mon Jan 12 16:34:40 2015

ALIASES RESOLVED

051-00383

820-00163

1 SCH

1 PCB

SCHEM,MLB,VENUS,X425G

PCBF,MLB,VENUS,X425G

CRITICAL

<PART_DESCRIPTION>

<SCH_NUM>

<BRANCH> 1 OF 119

1 OF 97

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

X425 BOM Groups

COMMON/DEVEL BOM

DRAM SPD Straps

BOM Variants

Module Parts

SYNC_DATE=05/30/2014

SYNC_MASTER=CLEAN_X305

BOM Configuration

X425_COMMON

685-00042

COMMON PARTS,MLB,VENUS,X425G

X425_DEVEL:ENG

985-00050

DEV BOM,MLB,VENUS,X425G

639-00682

PCBA,MLB,VENUS,CTO,16GHYN,VR-4GHYN,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_HYNIX

639-00798

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,BEST,16GHYN,VR-4GHYN,X425G

639-00799

PCBA,MLB,VENUS,BEST,16GMIC,VR-4GMIC,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_MICRON

PCBA,MLB,VENUS,NOCPU,16GMIC,VR-4GHYN,X425G

639-00803

BASE_BOM,DEVEL_BOM,GFX_BOM,RAM:MICRON_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,CTO,16GMIC,VR-4GMIC,X425G

639-00703

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_MICRON

639-00739

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_MICRON

PCBA,MLB,VENUS,CTO,16GHYN,VR-4GMIC,X425G

639-00740

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

PCBA,MLB,VENUS,CTO,16GMIC,VR-4GHYN,X425G

PCBA,MLB,VENUS,BEST,16GMIC,VR-4GHYN,X425G

639-00801

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_HYNIX

CRW,SR1ZX,PRQ,C0,2.5,47W,4+3E,1.2,6M,BGA

U0500

CPU_CRW:BEST

CRITICAL

1

337S00058

CRITICAL

1

CPU_CRW:CTO

U0500

CRW,SR1ZY,PRQ,C0,2.8,47W,4+3E,1.2,6M,BGA

337S00059

CRITICAL

U1100

337S4542

1

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

CRITICAL

U2800

1

338S1247

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

1

CRITICAL

U3900

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

338S1264

CRITICAL

1

U4000

333S0700

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

32

MICRON_1600

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

333S0660 CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

U8400

1

IC,GPU,VENUS XTAA1,QS,29X29MM,FCBGA962

337S00116

VENUS:XTA

CRITICAL

RAM:HYNIX_1600

HYNIX_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM:MICRON_1600

MICRON_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

IC,SDRAM,DDR3L-1600,4GBIT,78B FBGA

32

HYNIX_1600

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S00032

FB_4G_HYNIX

4

U8800,U8850,U8900,U8950

IC,GDDR5,4GBIT,6GBPS,1.5V,25NM,BGA170

333S00027

CRITICAL

XDP_DEBUG

XDP_CONN,XDP_PCH

GFX_BOM

VENUS:XTA

X425_DEVEL:ENG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,DPMUX_DEBUG,GPU_ROM:YES,SENSOR_GPU_NONPROD:Y

SMC_PROG:BASE,BOOTROM_PROG:EVT,TBTROM:PROG,DPMUXMCU:PROG

X425_PROGPARTS

BKLT:PROD,SENSOR_NONPROD:N

X425_PVT

EDP:YES,XDP,SSD_PWR_EN:GPIO,CAM_WAKE:NO,SAMCONN,APCLKRQ:ISOL,CRW_SPRT,WLAN_SW:SIL

X425_COMMON2

X425_COMMON1

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CPUPEG:X8X4X4,S2_PWR:S0,SMC_SUSACK:YES

ALTERNATE,COMMON,X425_COMMON1,X425_COMMON2,X425_PROGPARTS,ACAPS:A2

X425_COMMON

PCBA,MLB,NOGPU,CTO,16GMIC,VR-4GHYN,X425G

639-00974

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

X425_DEVEL:PVT

XDP_DEBUG

639-00800

PCBA,MLB,VENUS,BEST,16GHYN,VR-4GMIC,X425G

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_MICRON

BASE

1

CRITICAL

BASE_BOM

COMMON PARTS,MLB,VENUS,X425G

685-00042

DEVEL

CRITICAL

DEVEL_BOM

1

DEV,MLB,VENUS,X425G

985-00050

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED

X425_DEVEL:DVT

333S0766

FB_4G_MICRON

4

U8800,U8850,U8900,U8950

IC,GDDR5,4GBIT,6GBPS,128MX32,25NM,170BGA

CRITICAL

<SCH_NUM>

2 OF 119

2 OF 97

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC

EFI ROM

Alternate Parts

Programmables - All builds

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

BOM Configuration

U5000

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

338S1214

SMC_PROG:BLANK

CRITICAL

1

U9600

1

DPMUXMCU:BLANK

CRITICAL

IC,MCU,H8S/2113,9X9MM,TLP-145V

337S4313

U9600

CRITICAL

DPMUXMCU:PROG

1

IC,EDP MUX-95C,(RENESAS) V3.2.8,DVB,D2

341S3565

U9101

335S0724

1MBIT SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

GPUROM:BLANK

1

CRITICAL

U2890

T29,FALCON RIDGE(V27.1)PROTO0,X425G

CRITICAL

TBTROM:PROG

1

341S00166

U2890

TBTROM:BLANK

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

335S0915 CRITICAL

1

BOOTROM_BLANK:WIN

335S00007

1

U6100

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

CRITICAL

BOOTROM_BLANK:MAC

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

CRITICAL

335S00006

1

U6100

BOOTROM_PROG:EVT

IC,EFI ROM (V0145) EVT,X425

341S00239

1

U6100

CRITICAL

IC,SMC-B1,EXT (V2.25A9) PROTO 0,X425G

U5000

SMC_PROG:BASE

1

CRITICAL

341S00157

Diodes alt to Vishay

376S00086

376S0761

ALL

128S0264

ALL

Kemet alt to Sanyo

128S0364

138S0843

ALL

Samsung alt to Murata

138S0674

740S0135

ALL

AEM alt to Tyco

740S00003

128S0311

ALL

NEC alt to Sanyo

128S0329

155S00008

155S0667

Panasonic alt to TDK

ALL

376S0604376S1053

Diodes alt to Fairchild

ALL

128S0376

Kemet alt to Sanyo

ALL

128S0371

Cyntec alt to Vishay

152S0461

ALL

152S1645

138S0846 138S0811

Samsung alt to Murata

ALL

371S0713 371S0558

DDS alt to ST

Rohm alt to Vishay

138S0715

ALL

138S0732

ALL

ELPIDA to HYNIX U4000

333S0700333S0704

197S0478 197S0479

NDK Alt to Epson

ALL

197S0480

ALL

197S0481

Epson Alt to NDK

138S0739

Samsung alt to Murata

138S0706

ALL

138S0639

Samsung alt to Murata

ALL

138S0803

127S0164 127S0162

Rohm alt to Vishay

ALL

Toshiba alt to Vishay

376S00014

376S0761

376S1089 376S1128

NXP alt to Diodes

ALL

NXP alt to Diodes

376S0855376S1129

376S00074

376S0855

Toshiba alt to Diodes

ALL

376S1080 376S0820

Diodes alt to On Semi

ALL

353S2162

ON Semi alt to TI

353S00394 ALL

353S00133 ALL

ON Semi alt to TI

353S2741

Diodes alt to NXP

311S00060 ALL

311S0273

NEC alt to Sanyo

128S00008 ALL

128S0380

ON alt to Toshiba

311S0649

ALL

311S0541

740S00004

740S0134

AEM alt to Littlefuse

ALL

107S00029 107S00030 ALL

TFT alt to Cyntec

128S0220

Kemet alt to Sanyo

128S0398

ALL

128S0284128S0386

Kemet alt to Sanyo

ALL

311S0271

311S00008 ALL

Diodes alt to NXP

Kemet alt to Sanyo

128S0334128S0393

ALL

107S00033

TFT alt to Cyntec

ALL107S00034

107S0255

ALL

TFT alt to Cyntec

107S0240

ALL

TFT alt to Cyntec

107S00032107S00031

TFT alt to Cyntec

ALL107S00011107S00015

ALL

TFT alt to Cyntec

107S00038107S00037

ALL

TFT alt to Cyntec

107S0251107S0249

ALL

TFT alt to Cyntec

107S0250107S0248

371S00017

Diodes alt to Onsemi

ALL

371S0749

311S0426

Diodes alt to NXP

ALL311S00007

Kemet alt to Sanyo

128S0325128S0397

ALL

311S00004

ON Semi alt to NXP

311S0370

ALL

Pericom alt to TI

353S00095

353S3328

ALL

Yageo alt to Cyntec

112S00001

112S0254

ALL

<SCH_NUM>

3 OF 119

3 OF 97

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FAN BOSS APN 860-3428

Thermal Module gaskets APN 875-9290

Frame Holes

APN 860-1448

APN 806-9391

806-00452

APN 870-2451

X305G STANDOFF

APN 806-2247

X305G POGO PINS

IPD FLEX BRACKET BOSS (860-00166)

RIO FLEX BRACKET BOSS (860-00166)

APN 817-0688

APN 817-0741

SMT GND TEST PONTS

X305G THERMAL MODULE STANDOFF

PD parts

--------------------------------------------------------

CPU BOSS APN 860-2931

APN 860-3690

--------------------------------------------------------

GPU BOSS APN 860-4772

GPU BOSS APN 817-4517

1

ZT0415

2.8R2.3

1

SH0431

POGO-2.3OD-5.5H-X304

SM

1

ZT0470

TH-NSP

SL-1.1X0.45-1.4x0.75

1

SH0450

SHLD-MLB-USB-J45

SM

1

SH0432

SM

POGO-2.3OD-5.5H-X304

1

SH0433

POGO-2.3OD-5.5H-X304

SM

1

SH0435

SM

POGO-2.3OD-5.5H-X304

1

SH0434

SM

POGO-2.3OD-5.5H-X304

1

ZT0471

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0472

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0473

TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0450

SL-2.3X3.9-2.9X4.5

TH-NSP

2

1

SH0442

2.9OD1.2ID-1.35H-SM

2

1

SH0441

2.9OD1.2ID-1.35H-SM

2

1

SH0443

2.9OD1.2ID-1.35H-SM

2

1

SH0444

2.9OD1.2ID-1.35H-SM

1

ZT0490

SMT-PAD-NSP

2.1SM2.0MM-CIR

1

ZT0491

SMT-PAD-NSP

2.1SM2.0MM-CIR

1

ZT0492

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

BR0401

TH

MLB-MTG-BRKT-J5

1

SH0437

SM

POGO-2.3OD-5.5H-X304

2

1

SH0460

2.9OD1.2ID-1.35H-SM

2

1

SH0461

2.9OD1.2ID-1.35H-SM

2

1

SH0462

2.9OD1.2ID-1.35H-SM

2

1

SH0467

2.9OD1.2ID-1.35H-SM

2

1

SH0466

2.9OD1.2ID-1.35H-SM

2

1

SH0465

2.9OD1.2ID-1.35H-SM

1

SH0428

4.5OD1.85ID-1.95H

1

SH0427

4.5OD1.85ID-1.95H

1

SH0430

4.5OD1.85ID-1.95H

2

1

SH0440

2.9OD1.2ID-1.35H-SM

1

SH0420

5.0OD1.85ID-2.35H

1

SH0422

5.0OD1.85ID-2.35H

1

SH0426

5.0OD1.85ID-2.35H

1

SH0429

5.0OD1.85ID-2.35H

1

CG0400

6.0OD3.9H-SM

OMIT

1

CG0401

OMIT

6.0OD3.9H-SM

1

CG0402

OMIT

6.0OD3.9H-SM

1

CG0403

OMIT

6.0OD3.9H-SM

1

SH0421

4.5OD1.85ID-1.95H-1

1

SH0480

3.5OD1.85ID-2.0H

1

SH0481

3.5OD1.85ID-2.0H

1

SH0451

SM

SHLD-FENCE-MLB-T29-X305

2

1

SH0464

2.9OD1.2ID-1.35H-SM

2

1

SH0463

2.9OD1.2ID-1.35H-SM

1

SH0483

3.5OD1.85ID-2.0H

1

SH0482

3.5OD1.85ID-2.0H

1

SH0445

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

1

SH0446

STDOFF-4.9OD2.38H-SM-2

1

SH0424

STDOFF-4.5OD1.9H-SM-1

1

SH0425

STDOFF-4.5OD1.8H-SM-1

1

SH0423

STDOFF-4.5OD1.8H-SM-1

SYNC_DATE=08/08/2014

SYNC_MASTER=CLEAN_X305G

PD Parts

1

CRITICAL946-3819

EDGE_BOND

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

GND

<SCH_NUM>

4 OF 119

4 OF 97

IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

DDIB_TXP3

DDIB_TXN2

DDIB_TXP1

DDIB_TXN1

DDIB_TXP0

DDIC_TXP3

DDIC_TXN3

DDIC_TXN2

DDIC_TXP1

DDID_TXN2 DDID_TXP2 DDID_TXN3 DDID_TXP3

DDID_TXN0 DDID_TXP0 DDID_TXN1 DDID_TXP1

EDP_AUXN

EDP_HPD

EDP_AUXP

EDP_TXN1

EDP_TXP0 EDP_TXP1

DDIB_TXP2 DDIB_TXN3

DDIC_TXN0 DDIC_TXP0 DDIC_TXN1

DDIB_TXN0

EDP_RCOMP

EDP_DISP_UTIL

FDI_TXN0 FDI_TXP0 FDI_TXN1 FDI_TXP1

DDIC_TXP2

EDP_TXN0

SYM 10 OF 12

FDI

DIGITAL DISPLAY INTERFACES

EDP

DAISY_CHAIN_NCTF

RSVD139

RSVD138

RSVD137

RSVD136

RSVD135

RSVD134

RSVD133

RSVD132

DAISY_CHAIN_NCTF

SYM 12 OF 12

RESERVED

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

DMI_RX1

DMI_TX3

DMI_TX2

DMI_TX1

DMI_TX0

DMI_TX3*

DMI_TX2*

DMI_TX1*

DMI_TX0*

DMI_RX3

DMI_RX2

DMI_RX0

DMI_RX3*

DMI_RX2*

DMI_RX1*

DMI_RX0*

PEG_RX15

PEG_RX14

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

FDI_CSYNC

DISP_INT

PEG_RCOMP

PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*

PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

PEG_RX0*

PEG_RX1*

PEG_RX2*

PEG_RX3*

PEG_RX4*

PEG_RX5*

PEG_RX6*

PEG_RX7*

PEG_RX8*

PEG_RX9* PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15*

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

DMI

PCI EXPRESS BASED INTERFACE SIGNALS

FDI

SYM 1 OF 12

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Each corner of CPU has two testpoints. Other corner test signals connected in

Port D pins out of order

CPU Daisy-Chain Strategy:

NO_TESTNO_TEST

to match Intel symbol.

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

85

28 85 89

85

28 85 89

34 85 89

85

28 85 89

34 85 89

85

28 85 89

34 85 89

B14

D12 A14

C12

B12

D14

A12

C14

AG6

E14

E12

F14

F15

B16

D16

B17

D17

A16

C16

A17

C17

B20

D20

B21

D21

A20

C20

A21

C21

B24

D24

B25

D25

A24

C24

A25

C25

U0500

HASWELL

OMIT_TABLE

BGA

2

1

R0530

1% 1/16W MF-LF 402

24.9

2

1

R0531

10k

5% 1/16W MF-LF 402

G17

G14

AN37

AN35

AG45

AF9 AE9

AD45

D54

D1

C54

C3

C2

C1

BF53

BF52

BF51

BF4

BF3

BF2

BE54

BE53

BE52

BE3

BE2

BE1

BD54

BD1

BC54

BC1

B54

B53

B52

B3

B2

A53

A52

A51

A4

A3

U0500

HASWELL

OMIT_TABLE

BGA

1

TP0500

TP-P6

1

TP0501

TP-P6

1

TP0511

TP-P6

1

TP0531

TP-P6

1

TP0510

TP-P6

1

TP0520

TP-P6

1

TP0530

TP-P6

1

TP0521

TP-P6

12 89

12 87 89

12 89

12 87 89

12 89

12 87 89

2

1

R0510

402

1/16W MF-LF

1%

24.9

12 89

J1

J4

G2

J6

E2

G5

E4

D6

T2

T3

R3

R1

R5

T5

B5

C6

J2

J3

G3

J5

E3

G4

D4

E6

T1

T4

R4

R2

R6

T6

C5

B6

L3

M3

L1

M5

A9

C9

F9

A10

Y1

Y4

V2

V3

Y5

M1

D10

F10

L4

M4

L2

L5

B9

D9

E9

B10

Y2

Y3

V1

V4

V5

M2

C10

E10

AH6

F11

AG1

AG3

AF3

AF1

AG2

AG4

AF4

AF2

AC2

AC4

AB4

AB1

AC1

AC3

AB3

AB2

F12

U0500

OMIT_TABLE

HASWELL

BGA

85

28 85 89

34 85 89

28 85 89

34 85 89

85

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=CLEAN_X305_PEG

SYNC_DATE=02/18/2014

=PEG_D2R_P<1>

=PEG_D2R_N<0>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_P<0>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_P<1> PCIE_TBT_D2R_P<2>

=PEG_D2R_P<6> =PEG_D2R_P<7> PCIE_TBT_D2R_P<0>

=PEG_D2R_P<5>

=PEG_D2R_P<4>

=PEG_D2R_P<3>

=PEG_D2R_P<2>

=PEG_D2R_P<0>

PCIE_SSD_D2R_N<3>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_N<2>

PCIE_TBT_D2R_N<3> PCIE_SSD_D2R_N<0>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_N<1>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<5>

=PEG_D2R_N<3> =PEG_D2R_N<4>

=PEG_D2R_N<1> =PEG_D2R_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_P<1> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<0>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<0>

=PEG_R2D_C_P<6> =PEG_R2D_C_P<7>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_N<0>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_N<3>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<0>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<6>

CPU_PEG_RCOMP

DMI_S2N_N<2>

DP_INT_IG_ML_P<3>

DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<2>

DP_INT_IG_ML_N<2>

CPU_DC_BE53_BF53

TRUE

CPU_DC_A3_B3 CPU_DC_A4

TP_DP_IG_B_MLP<0>

PPVCOMP_S0_CPU

DP_INT_IG_ML_P<1>

CPU_DC_BC54

CPU_DC_A3_B3

TRUE

CPU_DC_BF51

TRUE

CPU_DC_B54_C54

DMI_S2N_N<0>

CPU_EDP_RCOMP

TP_DP_IG_D_MLP<3>

PPVCCIO_S0_CPU

DP_INT_IG_AUX_N

PPVCOMP_S0_CPU

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_P<3>

DMI_S2N_P<2>

FDI_INT

FDI_CSYNC

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DP_INT_IG_ML_N<0>

TP_DP_IG_C_MLP<2>

TP_EDP_DISP_UTIL

TP_DP_IG_B_MLN<0>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLN<0>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<2>

DP_INT_IG_ML_P<0>

DP_INT_IG_ML_N<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<2>

TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<3>

DP_INT_IG_AUX_P

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

DP_IG_A_HPD_L

TRUE

CPU_DC_A53_B53

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_D1

CPU_DC_BF4

CPU_DC_BC1

CPU_DC_BE53_BF53

TRUE

CPU_DC_A51

CPU_DC_D54

5 OF 97

5 OF 119

<SCH_NUM>

89

82 85 97

5

5 8

82 85 97

5 5

89

6 8

10 18 58

82 85 97

5 8

82 85 97

20

5

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SSC_DPLL_REF_CLKP

BCLKP

BCLKN

DPLL_REF_CLKP

DPLL_REF_CLKN

CATERR*

PROCHOT*

PROC_DETECT*

PECI

BPM7*

BPM6*

BPM5*

BPM4*

BPM2* BPM3*

BPM1*

BPM0*

DBR*

TDO

TDI

TRST*

TMS

TCK

PREQ*

PRDY*

SM_DRAMRST*

SM_RCOMP2

SM_RCOMP1

SM_RCOMP0

PLTRSTIN*

PWRGOOD

THERMTRIP*

PM_SYNC

SM_DRAMPWROK

SSC_DPLL_REF_CLKN

THERMAL

DDR3

PWR

JTAG

CLOCK

SYM 2 OF 12

OUT

IN IN

RSVD_TP24

RSVD_TP25 RSVD_TP26

RSVD49

RSVD48

RSVD47

RSVD_TP4

RSVD_TP23

RSVD_TP35 RSVD_TP36

RSVD_TP37

RSVD_TP18

RSVD_TP17

CFG15

CFG13 CFG14

CFG12

CFG7 CFG8 CFG9 CFG10 CFG11

TESTLO_F20

CFG4

CFG3

CFG2

CFG5 CFG6

CFG1

CFG0

TESTLO_F21

VSS_F51 VSS_F52

VSS_G19

VCC_F22

VSS_H53

VSS_H51 VSS_H52

VSS_H54

CFG17

CFG18

CFG19

CFG16

CFG_RCOMP

RSVD92 RSVD93 RSVD94 RSVD95

RSVD9

RSVD10

RSVD41 RSVD42

RSVD16

RSVD50

RSVD52

RSVD51

RSVD_TP1

RSVD11

RSVD_TP38 RSVD_TP39

RSVD_TP27 RSVD_TP28

RSVD_TP2 RSVD_TP3

RESERVED

SYM 11 OF 12

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

J1800 and only for debug access

(IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU)

(IPU) (IPU) (IPU) (IPU)

(IPU)

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

These can be placed close to

(IPU) (IPU)

18 89

2

1

R0611

10K

5% 1/16W MF-LF

402

PLACE_NEAR=U0500.F50:157mm

12 21 89

14 18 89

14 41 89

2

1

R0614

402

MF-LF

1/16W

1%

100

PLACE_NEAR=U0500.BB52:12.7mm

2

1

R0613

PLACE_NEAR=U0500.BB53:12.7mm

402

MF-LF

1/16W

1%

75

2

1

R0612

PLACE_NEAR=U0500.BB51:12.7mm

402

MF-LF

1/16W

1%

100

40 89

2

1

R0601

MF-LF

62

402

1/16W

5%

2 1

R0603

1/16W

56

5%

MF-LF

402

40 41 58 89

M53

M51

D53

M49

N49

N54

Y6

V6

BB52

BB53

BB51

BE51

AP48

F50

E50

C51

N52

N53

D52

L54

G51

AE6

AC6

F53

G50

P51

U51

P53

R49

N50

P49

R50

R51

AA6

AB6

U0500

OMIT_TABLE

HASWELL

BGA

21

11 89

H54 H53

H52

H51

G19

F52

F51

F22

F21

F20

L53

L52

L51

G6

G24

G21

G12 G10

F6

F25

F24

F1 E1

BE4 BD3

A6

A5

N51L50

L49

H50

G53

F8

F16

E5

BD4 BC4

B50

AU27

AU26

AM48

AL6

AH49

R54

Y54

Y49

W51

V51

AB49

Y50

AE49

AC49

V52

V53 Y51

Y52

R52

R53

V54

U53

W53

Y53

AD49

AG49

U0500

BGA

OMIT_TABLE

HASWELL

2

1

R0690

49.9

1% 1/16W

402

MF-LF

2

1

R0680

402

MF-LF

1/16W

1%

49.9

2

1

R0685

402

MF-LF

1/16W

1%

49.9

2

1

R0649

NOSTUFF

1/16W

1K

5%

MF-LF

402

2

1

R0643

1K

NOSTUFF

5% 1/16W

402

MF-LF

2

1

R0641

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0640

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0647

402

MF-LF

1/16W

5%

1K

NOSTUFF

2

1

R0646

CPUCFG6_PD

402

MF-LF

1/16W

5%

1K

2

1

R0645

CPUCFG5_PD

402

MF-LF

1/16W

5%

1K

2

1

R0644

1K

EDP:YES

5% 1/16W MF-LF

402

2

1

R0642

NOSTUFF

1K

5% 1/16W MF-LF 402

2

1

R0621

PLACE_NEAR=U0500.AP48:51.562mm

1% 1/16W MF-LF

402

3.32K

2

1

R0648

NOSTUFF

1K

5% 1/16W MF-LF

402

18 86 89

2

1

R0620

1/16W MF-LF

402

1%

PLACE_NEAR=R0621.2:1mm

1.82K

12 89

14

18 19 89

18 89

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

CPUPEG:X8X8

CPUCFG5_PD

CPU Clock/Misc/JTAG/CFG

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

XDP_BPM_L<7>

CPU_SM_RCOMP<2> CPU_MEM_RESET_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

CPU_PROCHOT_R_L

CPU_CATERR_L

TP_CPU_RSVD_TP2

CPU_PECI

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

CPU_CLK135M_DPLLREF_P

PM_SYNC

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

PPVCC_S0_CPU

TP_CPU_RSVD_TP37

TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP48

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP36

CPU_CFG<15>

CPU_CFG<13> CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<4>

TP_CPU_RSVD_TP35

TP_CPU_RSVD_TP24

XDP_CPUPCH_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TMS

XDP_CPU_PRDY_L

CPU_CFG<3>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG_RCOMP

TP_CPU_RSVD_TP3

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP47

CPU_TESTLO_F21

TP_CPU_RSVD_TP18

CPU_CFG<0>

CPU_TESTLO_F20

CPU_CFG<19>

TP_CPU_RSVD_TP27 TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP25

TP_CPU_RSVD_TP38 TP_CPU_RSVD_TP39

CPU_CFG<18>

TP_CPU_RSVD_TP17

PM_THRMTRIP_L

CPU_CLK135M_DPLLREF_N

CPU_PWRGD

CPU_RESET_L

CPU_CFG<6>

CPU_CFG<7>

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<16>

CPU_CFG<3>

CPU_CFG<9>

CPU_PROCHOT_L

PPVCCIO_S0_CPU

CPU_CFG<2>

PM_MEM_PWRGD

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

6 OF 119

6 OF 97

89

8

10 45 59 84 86

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 86 89

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 86 89

6

18 89

5 8

10 18 58

6

18 89

8

10 21 66 67 84 96

OUT

NC

NC NC

NC

NC NC NC

NC

NCNC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

RSVD160

RSVD161

SA_DQ60

SA_DQ59

RSVD163 RSVD164

RSVD166 RSVD167

RSVD169 RSVD170

SA_MA15

SA_MA14

SA_MA10

SA_CKN2

RSVD168

RSVD165

RSVD162

RSVD25

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

SA_DQ45 SA_DQ46 SA_DQ47

SA_DQ6

SA_DQ5

SA_DQ7

SA_DQ10

SA_DQ3 SA_DQ4

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ35

SA_DQ34

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ14

SA_DQ13

SA_DQ9

SA_DQ2

SA_DQ1

SA_DQ0

SA_DQ30

SA_CKE0

SA_CKE2

SA_CKE3

SA_CS0*

SA_CS2* SA_CS3*

SA_ODT0 SA_ODT1 SA_ODT2

SA_BS0

SA_ODT3

SA_BS2

SA_BS1

SA_RAS*

VSS_BC21

SA_WE*

SA_CAS*

SA_MA1

SA_MA0

SA_MA3

SA_MA2

SA_MA4

SA_MA6

SA_MA5

SA_MA7 SA_MA8 SA_MA9

SA_MA11 SA_MA12 SA_MA13

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SM_VREF

SA_DQ20

SA_CS1*

SA_CKE1

SA_CKN0 SA_CKP0

SA_CKN1 SA_CKP1

SA_CKP2

SA_CKN3 SA_CKP3

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ8

SA_DQ11 SA_DQ12

MEMORY CHANNEL A

SYM 3 OF 12

VSS_AU30

SB_BS2

SB_CKP3

SB_CKN3

SB_CKP2

SB_CKN2

SB_CKP1

SB_CKN1

SB_CKP0

SB_DQS7

SB_DQS6

SB_DQS2

SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59

SB_DQSN7

SB_DQ58

SB_DQ57

SB_DQSN5

SB_DQ56

SB_DQSN4

SB_DQ55

SB_DQ54

SB_DQSN2

SB_DQ53

SB_DQSN1

SB_DQ52

SB_DQSN0

SB_DQ51

SB_DQ50

SB_MA15

SB_DQ49

SB_MA14

SB_DQ48

SB_MA13

SB_DQ47

SB_MA12

SB_DQ46

SB_MA11

SB_DQ45

SB_MA10

SB_DQ44

SB_MA9

SB_DQ43

SB_MA8

SB_DQ42

SB_MA7

SB_DQ41

SB_MA6

SB_DQ40

SB_MA5

SB_DQ39

SB_MA4

SB_DQ38

SB_MA3

SB_DQ37

SB_MA2

SB_DQ36

SB_MA1

SB_MA0

SB_CAS*

SB_WE*

SB_RAS*

SB_DQ30

SB_DQ27

SB_BS1

SB_DQ26

SB_BS0

SB_DQ25

SB_DQ24

SB_ODT3

SB_DQ23

SB_ODT2

SB_DQ22

SB_ODT1

SB_DQ21

SB_ODT0

SB_DQ20

SB_CS3*SB_DQ19

SB_CS2*SB_DQ18

SB_CS1*SB_DQ17

SB_CS0*SB_DQ16

SB_DQ15

SB_CKE3SB_DQ14

SB_DQ13

SB_DQ12

SB_DQ11

SB_CKE2

SB_DQ10

SB_DQ9

SB_DQ8

SB_CKE1

SB_DQ7

SB_DQ6

SB_DQ5

SB_DQ4

SB_DQ3

SB_DQ2

SB_DQ1

SB_DQ0

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQS4

SB_DQS3

SB_DQS5

SB_DQS1

SB_DQS0

SB_DQSN6

SB_DQSN3

RSVD172

RSVD173

RSVD174 RSVD175 RSVD176 RSVD177 RSVD178 RSVD179 RSVD180 RSVD181

SB_CKE0

SB_CKN0

RSVD171

SB_DQ28 SB_DQ29

MEMORY CHANNEL B

SYM 4 OF 12

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22 89

22

23 24 92

25 26 92

23 27 92

24 27 92

23 24 27 92

BC21

AM6

AN6

BF21

BF20

BD17

BF17

BF16

BC16

BC32

BE27

BC28

BF27

BC27

BF32

BE28

BF28

BE31

BE32

BE20

BC31

BF31

BD20

BD27

BD28

AT2

BA3

BE7

BD12

AY46

AW52

AP53

AJ52

AT3

BA2

BD7

BE12

BA46

AW53

AP52

AJ53

AN52

AN54

AK53

AR3

AR2

AU4

AU2

AK52

AR4

AR1

AU1

AU3

AW1

AW4

BB2

BB3

AW2

AW3

AH51

BC2

BB4

BD6

BE5

BF9

BD9

BC6

BE6

BE9

BC9

AH53

BE11

BD11

BD14

BE14

BF11

BC11

BC14

BF14

BA43

BA49

AK54

AY43

AY45

BA45

BA47

AY49

AY47

AY53

AY54

AV54

AV51

AK51

AY51

AY52

AV53

AV52

AR54

AR52

AN51

AN53

AR53

AR51

AH52

AH54

AR6

BD16

BE17

BC17

BE16

BC23

BF23

BC25

BF25

BD23

BE23

BD25

BE25

BD34

BC34

BF34

BE34

BE21

BD32

BD21

BC20

BD31

BC53

BA40

BA39

AY40

AY39

AW40

AW39

AV40

AV39

AU40

AU39

U0500

OMIT_TABLE

HASWELL

BGA

AU30

AW23

AV23

AW19

AV19

BA19

AY20

AU32

BA32

AV32

AT30

AY32

AW32

AV30

AY30

BA35

AW36

AU20

AW35

AY35

AU23

AW30

BA30

AL2

AW8

AW10

AW16

BD43

BD48

AU46

AD52

AL3

AW6

AW12

AW15

BE43

BE48

AV46

AD53

AU49

AU47

AE53

AK3

AK2

AM4

AM1

AE52

AK4

AK1

AM3

AM2

AY6

AU6

AY8

AV8

BA6

AV6

AC51

BA8

AU8

AV10

AY10

BA12

AV12

AU10

BA10

AY12

AU12

AC53

AU15

AY15

AV16

AY16

AV15

BA15

AU16

BA16

BE42

BD42

AE54

BC44

BF44

BF42

BC42

BD44

BE44

BF47

BE47

BD50

BD49

AE51

BC47

BD47

BE49

BC49

AV49

AV47

AU45

AU43

AV45

AV43

AC52

AC54

AW20

AU19

AY19

BA20

AY27

AY26

AV26

AV27

BA27

BA26

AW26

AW27

AV36

AV35

AU35

AU36

AV20

BA36

BA23

AY23

BF39

BF37

BE39

BE38

BE37 BD39

BD38

BD37

BC39 BC37

AY36

U0500

OMIT_TABLE

HASWELL

BGA

23 24 92

24 27 92

23 27 92

24 27 92

23 27 92

23 24 27 92

25 27 92

26 27 92

25 27 92

25 26 27 92

26 27 92

25 27 92

26 27 92

25 26 27 92

25 26 92

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU DDR3 Interfaces

MEM_A_DQ<2> MEM_A_DQ<3>

MEM_A_CS_L<1>

MEM_A_DQ<45>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQ<53>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13>

MEM_A_DQ<15> MEM_A_DQ<16>

MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50>

MEM_A_DQ<52>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<15>

MEM_B_DQ<20>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<61>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_A_DQ<60>

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>

MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<17>

MEM_A_DQ<14>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_B_DQ<52>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

CPU_DIMM_VREFCA

MEM_B_DQ<16>

MEM_B_DQ<18>

<SCH_NUM>

7 OF 119

7 OF 977 OF 97

7 OF 119

<SCH_NUM>

BI

OUT

IN

PWR_DEBUG*

RSVD64

RSVD76

VCCIO_OUT

VCC

VDDQ

FC_D3

FC_D5

VSS_B51

VCC_SENSE

VCOMP_OUT

VCC_M6

VCC_L6

RSVD70

RSVD72 RSVD73

RSVD74

RSVD66 RSVD67

RSVD69

RSVD65

FC_F17

VSS_AB50(RSVD)

VSS_AD50(RSVD)

VSS_AJ50(RSVD)

VSS_AK49(RSVD)

VSS_AM50(RSVD)

VSS_AN49(RSVD)

VSS_AP49(RSVD)

VSS_AP50(RSVD)

VSS_V50(RSVD)

RSVD79(VSS)

VIDALERT* VIDSCLK VIDSOUT

RSVD68

RSVD71

VSS_E52

IVR_ERROR IST_TRIGGER

RSVD75

VSS_AG50(RSVD)

VSS_AJ49(RSVD)

SYM 5 OF 12

VCCVCC

POWER

SYM 6 OF 12

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

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C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

to avoid any extraneous connections.

Max load: 300mA

R0810.2: R0800.2:

R0802.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs

for BDW CPU support.

Connections are required

21

R0812

0

5% 1/16W MF-LF

402

58 89

2

1

R0802

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1% MF-LF

21

R0811

0

402

5%

MF-LF

1/16W

58 89

21

R0810

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

58 89

2

1

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

V50

E52

B51

AP50

AP49

AN49

AM50

AK49 AJ50

AJ49 AG50

AD50

AB50

J50

J52

J53

BE33

BE30

BE26

BE22

BE18

BD33

BD30

BD26

BD22

BB36

BB34

BB31

BB30

BB27

BB26

BB22

BB21

AY18

AW33

AW29

AW25

AW22

AV37

AT36

AT32

AT27

AT23

AT19

AT13

AR33

AR31

AR29

AK6

D51

C50

M6

L6

H29

H27

H26

H25

H24

H23

H21

H20

H19

H18

H17

H16

H14

H13

H12

H11

G48

G46

G45

G43

G42

G39

G38

G36

G34

G32

G31

G29

G27

F48

F46

F45

F43

F42

F39

F38

F36

F34

F32

F31

F28

F27

E48

E46

E45

E43

E42

E39

E38

E36

E34

E32

E31

E28

E27

D48

D46

D45

D43

D42

D39

D38

D36

D34

D32

D31

D28

D27

C48

C46

C45

C43

C42

C39

C38

C36

C34

C32

C31

C28

C27

B48

B46

B45

B43

AA9

AA8

AA47

AA46

A48

A46

A45

A43

A42

A39

A38

A36

W9

V49 U49

J31

J26

J21

J17

J12

AR49

AN33

AN31

AN22 AN18

AH9

F19

AM49

W49

F17

D5 D3

U0500

OMIT_TABLE

HASWELL

BGA

Y8

Y46

Y45

W8

W47

W46

V8

V46

V45

U9U8U47

U46

T46

T45

R9R8R47

R46

P8

P46

P45

N9N8N47

N46

N44

N43

N42

N40

N39

N38

N37

M9M8M46

M45

M44

M43

M42

M40

M39

M38

M37

L8

L47

L46

L44

L43

L42

L40

L39

L38

L37

K9K8K48

K46

K45

K44

K43

K40

K38

J9J8J48

J46

J45

J43

J42

J40

J39

J38

J37

J36

J33

J29

J24

J19

J14

J10

H9H8H48

H46

H45

H43

H42

H40

H39

H38

H37

H36

H34

H33

H32

H31

H30

B42

B39

B38

B36

B34

B32

B31

B28

B27

AR46

AR45

AR43

AR41

AR39

AR37

AR35

AP9

AP8

AP47

AP46

AP44

AP43

AP42

AP41

AP40

AP39

AP38

AP37

AP36

AP35

AP34

AP33

AP32

AP31

AP30

AP29

AP27

AP26

AP25

AP24

AP23

AP22

AP21

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

AP12

AP10

AN9

AN8

AN46

AN45

AN44

AN43

AN42

AN41

AN40

AN39

AN38

AN36

AN34

AN32

AN30

AN29

AN27

AN26

AN25

AN24

AN23

AN21

AN20

AN19

AN17

AN16

AN15

AN14

AN13

AN12

AN10

AM9

AM8

AM47

AM46

AL9

AL8

AL46

AL45

AK8

AK47

AK46

AJ46

AJ45

AH8

AH47

AH46

AG8

AG46

AF8

AE8

AE47

AE46

AD8

AD46

AC9

AC8

AC47

AC46

AB8

AB46

AB45

A34

A32

A31

A28

A27

U0500

OMIT_TABLE

HASWELL

BGA

18

2

1

R0860

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

58 89

19

SYNC_DATE=10/31/2014

SYNC_MASTER=CLEAN_X425

CPU Power

PP1V05_S0_CPU_VCCST CPU_VCCST_PWRGD

PPVCC_S0_CPU

CPU_VIDSOUT_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm

TP_CPU_RSVD_TP78

PP1V35_S3RS0_CPUDDR

CPU_VIDALERT_R_L

TP_CPU_IVR_ERROR

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

MIN_NECK_WIDTH=0.2 mm

CPU_VIDALERT_L

CPU_VIDSOUT

CPU_PWR_DEBUG

TP_CPU_RSVD_TP75 TP_CPU_RSVD_TP76

CPU_VCCSENSE_P

CPU_VIDSCLK_R

CPU_VIDSCLK

<SCH_NUM>

<BRANCH> 8 OF 119

8 OF 97

10 19

6 8

10 45 59 84 86

6 8

10 45 59 84 86

5 6

10 18 58

6

10 21 66 67 84 96

5

VSSVSS

GROUND

SYM 7 OF 12

VSS VSS

SYM 8 OF 12

GROUND

VSS

VSS_SENSE

VSS_NCTF

VSS_AB48(RSVD)

VSS_AR22(RSVD)

VSS_G18(RSVD)

VSS_P9(RSVD)

SYM 9 OF 12

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AT4

AT39

AT37

AT35

AT33

AT29

AT26

AT25

AT22

AT20

AT18

AT16

AT15

AT12

AT10

AT1

AR9

AR8

AR7

AR50

AR5

AR48

AR26

AR24

AR20

AR18

AR16

AR14

AR12

AP7

AP54

AP51

AN7

AN50

AN5

AN48

AN4

AN3

AN2

AN1

AM7

AM54

AM53

AM52

AM51

AM5

AL7

AL5

AL48

AL4

AL1

AK9

AK7

AK50

AK5

AK48

AJ54

AJ51

AJ48

AH7

AH50

AH5

AH48

AH4

AH3

AH2

AH1

AG9

AG7

AG54

AG53

AG52

AG51

AG5

AG48

AF7

AF6

AF5

AE7

AE50

AE5

AE48

AE4

AE3

AE2

AE1

AD9

AD7

AD54

AD51

AD48

AC7

AC50

AC5

AC48

AB9

AB7

AB54

AB53

AB52

AB51

AB5

AA7

AA5

AA48

AA4

AA3

AA2

AA1

A44

A40

A37

A33

A30

A26

A22

A19

A15

A11

U0500

HASWELL

OMIT_TABLE

BGA

BB9

BB7

BB6

BB5

BB49

BB48

BB47

BB46

BB44

BB43

BB42

BB41

BB39

BB38

BB37

BB33

BB32

BB28

BB25

BB23

BB20

BB18

BB17

BB16

BB15

BB14

BB12

BB11

BB10

BA9

BA53

BA52

BA51

BA50

BA5

BA42

BA4

BA37

BA33

BA29

BA25

BA22

BA18

BA13

B8

B49

B44

B40

B37

B33

B30

B26

B22

B19

B15

B11

AY9

AY50

AY42

AY37

AY33

AY29

AY25

AY22

AY13

AW9

AW54

AW51

AW50

AW5

AW49

AW47

AW46

AW45

AW43

AW42

AW37

AW18

AW13

AV9

AV50

AV5

AV42

AV4

AV33

AV3

AV29

AV25

AV22

AV2

AV18

AV13

AV1

AU9

AU5

AU42

AU37

AU33

AU29

AU25

AU22

AU18

AU13

AT9

AT8

AT6

AT54

AT53

AT52

AT51

AT50

AT5

AT49

AT47

AT46

AT45

AT43

AT42

AT40

U0500

HASWELL

OMIT_TABLE

BGA

Y9Y7Y48

W7

W54

W52

W50

W48

V9V7V48

U7U6U54

U52

U50

U5

U48

U4U3U2U1T48

D50

R7

R48P9P7P6P54

P52

P50

P5

P48

P4P3P2

P1

G1

F54

E54

D2

C53

BF6

BF50

BF5

BF49

BD53

BD2

BB54

BB1

BA54

BA1

B4A8A50

A49

N7

N48

M7

M54

M52

M50

M48

L9L7L48

K7K6K5K4K3K2K1J7J54

J51

J49

J44

H7

H49

H44

G9G8G7

G54

G52

G49

G44

G40

G37

G33

G30

G26

G25

G23

G20

G18

G16

G13

G11

F5

F49

F44

F40

F4

F37

F33

F30

F3

F26

F2

E8

E53

E51

E49

E44

E40

E37

E33

E30

E26

E25

E24

E22

E21

E20

E19

E17

E16

E15

E11

D8

D49

D44

D40

D37

D33

D30

D26

D22

D19

D15

D11

C8

C52

C49

C44

C40

C4

C37

C33

C30

C26

C22

C19

C15

C11

BF7

BF48

BF46

BF43

BF41

BF38

BF36

BF33

BF30

BF26

BF22

BF18

BF15

BF12

BF10

BE46

BE41

BE36

BE15

BE10

BD51

BD5

BD46

BD41

BD36

BD18

BD15

BD10

BC7

BC52

BC50

BC5

BC48

BC46

BC43

BC41

BC38

BC36

BC33

BC30

BC3

BC26

BC22

BC18

BC15

BC12

BC10

AR22

AB48

U0500

HASWELL

OMIT_TABLE

BGA

58 89

2

1

R0960

PLACE_NEAR=U0500.D50:50.8mm PLACE_SIDE=BOTTOM

402

MF-LF

1/16W

5%

100

CPU Ground

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU_VCCSENSE_N

<SCH_NUM>

9 OF 119

9 OF 97

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LOCATION DEPENDS ON DESENSE TEAM

FOR DESENSE IMPROVEMENT

Intel recommendation: 1x 0.1uF 0402, 1x 4.7uF 0805 Apple Implementation: 1x 0.1uF 0201, 1x 4.7uF 0402

CAPS for Acoustic Control (C102E to C103F)

LOCATION DEPENDS ON DESENSE TEAM

FOR DESENSE IMPROVEMENT

CPU VCCST Decoupling

PLACEMENT_NOTE (C1068-C1076:

CPU VDDQ Decoupling

Apple Implementation: 3x 270uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1080-C1089):

PLACEMENT_NOTE (C1090-C1097):

PLACEMENT_NOTE (C1020-C1023):

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)

(Z = 2mm, place on tall side next to CPU & under heat pipe)

CAPS for Acoustic Control (C109A to C102D)

CPU VCCIO Decoupling

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1000-C1019):

Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

CPU VCORE Decoupling

PLACEMENT_NOTE (C1098-C1099):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)

PLACEMENT_NOTE (C1024-C1045):

PLACEMENT_NOTE (C1046-C1067):

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

C1098, C1099 and C108A use B size caps due to EG board placement constraints.

2

1

C1009

X6S-CERM 0402

1UF

10V

10%

Place on bottom side of U0500

2

1

C1008

X6S-CERM

10V

0402

Place on bottom side of U0500

10%

1UF

2

1

C1007

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1031

CRITICAL

NO STUFF

2.5V X6S-CERM

20UF

20%

Place near inductors on bottom side.

0402

2

1

C1006

X6S-CERM

10% 10V

0402

Place on bottom side of U0500

1UF

2

1

C1005

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1004

X6S-CERM

10%

1UF

10V

0402

Place on bottom side of U0500

2

1

C1003

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1002

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1001

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

1UF

2

1

C1000

X6S-CERM

Place on bottom side of U0500

10V

10%

0402

1UF

2

1

C1030

Place near inductors on bottom side.

CRITICAL

NO STUFF

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1029

NO STUFF

Place near inductors on bottom side.

CRITICAL

X6S-CERM 0402

20UF

20%

2.5V

2

1

C1027

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1026

Place near inductors on bottom side.

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

CRITICAL

2

1

C1020

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1021

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1022

NO STUFF

Place near U0500 on bottom side

2.5V X6S-CERM 0402

20UF

20%

2

1

C1023

Place near U0500 on bottom side

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1025

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1024

CRITICAL

NO STUFF

0402

20%

X6S-CERM

2.5V

20UF

2

1

C1028

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1032

NO STUFF

Place near inductors on bottom side.

CRITICAL

X6S-CERM 0402

20UF

20%

2.5V 2

1

C1033

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM

20UF

20%

0402

2

1

C1039

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1038

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1037

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1036

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1035

NO STUFF

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1034

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

X6S-CERM

2

1

C1079

0.01UF

10%

X7R-CERM

16V

0402

2

1

C1089

Place on bottom side of U0500

0402

10% 10V X6S-CERM

1UF

2

1

C1088

X6S-CERM

1UF

0402

10V

Place on bottom side of U0500

10%

2

1

C1087

X6S-CERM

10%

Place on bottom side of U0500

10V

1UF

0402

2

1

C1086

0402

X6S-CERM

1UF

10V

Place on bottom side of U0500

10%

2

1

C1085

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1084

X6S-CERM 0402

Place on bottom side of U0500

10V

1UF

10%

2

1

C1083

X6S-CERM 0402

Place on bottom side of U0500

1UF

10% 10V

2

1

C1082

X6S-CERM

1UF

0402

Place on bottom side of U0500

10V

10%

2

1

C1081

X6S-CERM

10V

1UF

0402

Place on bottom side of U100.

10%

2

1

C1080

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1093

Place near U0500 on bottom side

10UF

0402

X6S

4V

20%

2

1

C1092

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1091

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1090

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1097

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1096

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1095

10UF

X6S

Place near U0500 on bottom side

0402

4V

20%

2

1

C1094

10UF

0402

X6S

Place near U0500 on bottom side

4V

20%

2

1

C1043

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1042

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1041

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1040

NO STUFF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1019

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1018

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1017

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

2

1

C1016

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1015

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

2

1

C1014

X6S-CERM

Place on bottom side of U0500

1UF

10V

10%

0402

2

1

C1013

X6S-CERM

Place on bottom side of U0500

10% 10V

1UF

0402

2

1

C1012

X6S-CERM

1UF

10% 10V

Place on bottom side of U0500

0402

2

1

C1011

X6S-CERM

Place on bottom side of U0500

10% 10V

1UF

0402

2

1

C1010

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

2

1

C1065

X6S-CERM

2.5V

CRITICAL

0402

20UF

20%

Place near inductors on bottom side.

2

1

C1064

X6S-CERM

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

2

1

C1063

X6S-CERM

CRITICAL

Place near inductors on bottom side.

2.5V

0402

20UF

20%

2

1

C1062

20%

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

2

1

C1061

20UF

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20%

2

1

C1060

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1059

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1058

2.5V

CRITICAL

Place near inductors on bottom side.

X6S-CERM 0402

20UF

20%

2

1

C1057

CRITICAL

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1056

CRITICAL

ACAPS:A2

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1055

CRITICAL

ACAPS:A1

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1054

ACAPS:A2

Place near inductors on bottom side.

CRITICAL

2.5V

X6S-CERM 0402

20UF

20%

2

1

C1053

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1052

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1051

ACAPS:A1

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1050

ACAPS:A2

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1049

X6S-CERM

ACAPS:A1

Place near inductors on bottom side.

CRITICAL

2.5V

0402

20UF

20%

2

1

C1048

CRITICAL

Place near inductors on bottom side.

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1047

NO STUFF

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

CRITICAL

2

1

C1046

CRITICAL

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C1045

ACAPS:A2

Place near inductors on bottom side.

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1044

Place near inductors on bottom side.

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C1067

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM 0402

20UF

20%

2

1

C1066

0402

ACAPS:A1

CRITICAL

Place near inductors on bottom side.

2.5V X6S-CERM

20UF

20%

2

1

C1068

CRITICAL

CASE-B2S

2.5V

210UF

POLY-TANT

20%

2

1

C1069

POLY-TANT

2.5V

210UF

CASE-B2S

CRITICAL

20%

2

1

C1070

POLY-TANT CASE-B2S

210UF

CRITICAL

2.5V

20%

2

1

C1071

POLY-TANT

2.5V

CASE-B2S

210UF

CRITICAL

20%

2

1

C1072

CRITICAL

POLY-TANT

2.5V

CASE-B2S

210UF

20%

2

1

C1073

POLY-TANT

2.5V

210UF

CASE-B2S

CRITICAL

20%

2

1

C1074

CASE-B2S

POLY-TANT

2.5V

210UF

CRITICAL

20%

2

1

C1075

POLY-TANT

210UF

2.5V

CASE-B2S

CRITICAL

20%

2

1

C1076

CRITICAL

CASE-B2S

POLY-TANT

2.5V

NO STUFF

210UF

20%

2

1

C103F

0402

2.5V

CRITICAL

Place near inductors on bottom side.

X6S-CERM

20UF

20%

2

1

C103E

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103D

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103C

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C103B

NO STUFF

20UF

20%

0402

CRITICAL

2.5V X6S-CERM

2

1

C103A

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102F

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102E

CRITICAL

ACAPS:A2

2.5V X6S-CERM 0402

20UF

20%

2

1

C101B

CRITICAL

ACAPS:A1

2.5V X6S-CERM 0402

20UF

20%

2

1

C101A

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109F

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109E

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109D

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109C

CRITICAL

NO STUFF

2.5V X6S-CERM 0402

20UF

20%

2

1

C109B

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C109A

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102D

ACAPS:A2

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102C

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102B

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C102A

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101E

CRITICAL

ACAPS:A1

2.5V X6S-CERM 0402

20UF

20%

2

1

C101D

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101C

ACAPS:A1

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

2

1

C101F

NO STUFF

CRITICAL

2.5V X6S-CERM 0402

20UF

20%

3 2

1

C1077

CRITICAL

330UF-9MOHM

D15T-1

2.5V POLY-TANT

NO STUFF

20%

2

1

C1098

CRITICAL

270UF

CASE-B2-SM

TANT

2V

20%

2

1

C1099

CRITICAL

CASE-B2-SM

TANT

270UF

2V

20%

2

1

C108A

270UF

2V CASE-B2-SM

CRITICAL

TANT

20%

2

1

C108B

0201

12PF

5% NP0-C0G

25V

CRITICAL

2

1

C108D

CRITICAL

0201

12PF

5% NP0-C0G

25V

2

1

C108C

CRITICAL

25V

NP0-C0G

5%

12PF

0201

2

1

C108E

5% NP0-C0G

25V

12PF

0201

CRITICAL

2

1

C107A

CRITICAL

NP0-C0G 0201

25V

+/-0.1PF

3.0PF

2

1

C107B

CRITICAL

0201

3.0PF

NP0-C0G

25V

+/-0.1PF

21

R1080

BDW_SPRT

1/10W

0

603

5%

MF-LF

2

1

C106A

BDW_SPRT

0.1UF

10%

6.3V CERM-X5R 0201

PLACE_NEAR=U0500.D5:12.7mm

2

1

C106B

BDW_SPRT

402

6.3V X5R

4.7UF

PLACE_NEAR=U0500.D5:25.4mm

20%

CPU Decoupling

SYNC_MASTER=CLEAN_X305G

SYNC_DATE=08/11/2014

PP1V05_S0_CPU_VCCST

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

PPVCC_S0_CPU

10 OF 97

<SCH_NUM>

10 OF 119

8

19

14 15 17 18 41 62 67 84 86

6 8

21 66 67

84 96

5 6 8

18 58

6 8

45 59 84 86

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

OUT OUT

IN

OUT OUT

OUT

NC

HDA_SDI0

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_TXP3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_RXN0

INTVRMEN

RTCRST*

SATA_RXP1

SATA_RXN1

SATA_TXP0

SATA1GP/GPIO19

SATA_IREF

TP9

SATA_TXN3

SATA_RXP3

SATA_RXN3

SATA_TXP2

SATA_TXN2

SATA_RXN2 SATA_RXP2

HDA_SDO

HDA_SDI3

INTRUDER*

JTAG_TCK

TP20

JTAG_TMS

JTAG_TDO

JTAG_TDI

SATALED*

SATA0GP/GPIO21

SATA_TXN1

SATA_TXN4/PETN1

SATA_TXP1

SATA_TXP4/PETP1

SATA_TXN0

SATA_RCOMP

DOCKEN*/GPIO33

RTCX2

RTCX1

SRTCRST*

TP8

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_RXP0

HDA_DOCK_RST*/GPIO13

TP22

TP25

HDA_SDI2

HDA_SDI1

HDA_RST*

SPKR

HDA_SYNC

HDA_BCLK

SATA

AZALIA

RTC

(1 OF 11)

JTAG

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_DP_P

PEG_A_CLKRQ*/GPIO47

(2 OF 11)

CLOCKS

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU-RSMRST#)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

If HDA = S0, must also ensure that signal cannot be high in S3.

(IPD)

(IPD-PLTRST#)

(IPU)

1.5V -> 1.1V

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK)

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPU-PLTRST#)

(IPD)

Unused clock terminations for FCIM Mode

(IPD-boot)

(IPU)

(IPD)

Unused

(if not combo w/SD Card)

Reserved: Ethernet

SATA Port assignments:

PCIe:

Unused

Reserved: ODD

Primary HDD/SSD (SATA only)

Secondary HDD/SSD (SATA only)

NOTE: ENET pair only used if SD Card Reader is USB3.

(IPD)

(IPD-DOCKEN#?)

CLKOUT_PEG outputs can be used for those devices.

If 2 or less devices are attached to PEG the

while PCH-attached PCIe devices use the other set.

PEG-attached (CPU) PCIe devices must use one set,

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.

19 90

52 91

2

1

R1100

330K

1/20W

5%

201

MF

2

1

R1101

1/20W

5%

201

MF

1M

2

1

R1102

1/20W

5%

201

MF

20K

2

1

R1103

1/20W

5%

201

MF

20K

2

1

C1103

10V

10% 402

X5R

1UF

2

1

C1102

10V

10% 402

X5R

1UF

2

1

R1130

1/20W

1%

201

MF

7.5K

PLACE_NEAR=U1100.AY5:2.54mm

11 85

18 86

21

R1172

340

MF-LF

402

1%

1/16W

2

1

R1173

1K

1/20W

1%

201

MF

19 90

18

11 18

33 91

36 91

18

36 91

11 34

11 35

11 28

6

89

6

89

6

89

6

89

19 91

11 82 85

28 91

21

R1177

MF

1/20W

5% 201

4.7K

21

R1178

4.7K

201

1/20W

5% MF

21

R1134

10K

MF 2015%

1/20W

21

R1142

10K

MF 2015%

1/20W

21

R1169

10K

MF 2015%

1/20W

21

R1144

10K

MF 2015%

1/20W

21

R1145

10K

MF 2015%

1/20W

21

R1147

10K

MF 2015%

1/20W

12

R1114

10K

MF 2015%

1/20W

21

R1115

10K

MF 201

1/20W

5%

21

R1143

1/20W

5% 201MF

10K

21

R1133

1/20W

5% 201MF

10K

21

R1179

1/20W

10K

MF 2015%

21

R1146

1/20W

5% 201MF

10K

21

R1148

1/20W

5% 201MF

10K

52 91

21

R1191

10K

MF 2015%

1/20W

21

R1192

10K

MF 2015%

1/20W

21

R1193

10K

MF5%

1/20W

201

21

R1194

10K

MF 2015%

1/20W

21

R1195

10K

MF 2015%

1/20W

21

R1196

10K

MF 2015%

1/20W

21

R1197

10K

MF 2015%

1/20W

21

R1170

5% 201MF

10K

1/20W

21

R1171

10K

MF 2015%

1/20W

BA2 BB2

F8 C26 AB6

B9

AL10

AP3

AR15

AW15

AT13

AW13

AW10

AY8

AP15

AV15

AR13

AY13

AV10

AW8

BE14

BB13

BE12

BD9

BE10

BE8

BC14

BD13

BC12

BB9

BC10

BC8

AY5

BD4

AU2

AT1

B4

B5

D9

AD1

AD3

AE2

AB3

G10

A8

A22

A24

F22

G22

K22

L22

C24

C22

B25

B17

U1100

OMIT_TABLE

LYNXPOINT

MOBILE

FCBGA

AL44

AM43

AD39 AD38

F45

U4

AF6

Y3

AE4

AA2

V3

T3

AF3

AF1

AB1

AM45

AN44

F39

F36

F38

C40

Y38

Y39

AB36

AB35

AJ42

AB39

AE42

AF45

AD45

AB45

AA42

Y45

AJ44

AB40

AE44

AF43

AD43

AB43

AA44

Y43

AH45

AH43

AF36

AF35

AJ39

AJ40

AF40

AF39

A40

F41

B42

E44

D44

BC6

BE6

AT24

AR24

G33

H33

AW24

AY24

D17

U1100

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

6

89

6

89

87 89

21

R1110

PLACE_NEAR=U1100.B25:1.27mm

MF 2015%

1/20W

33

21

R1113

PLACE_NEAR=U1100.A24:1.27mm

2015%

1/20W33MF

21

R1111

1/20W

5% 201MF

33

PLACE_NEAR=U1100.A22:1.27mm

21

R1112

PLACE_NEAR=U1100.C24:1.27mm

33

MF 2015%

1/20W

19 91

87 91

19 91

87 90

87

11 18

12

R1190

1/20W

MF

1%

PLACE_NEAR=U1100.AN44:2.54mm

201

7.5K

11 85

21

R1176

10K

MF 2015%

1/20W

34 91

11 85

87 90

70 85 91

PCH RTC/HDA/JTAG/SATA/CLK

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PP3V3_S0

PP3V3_SUS

NC_PCIE_CLK100M_ENETSDP

NC_PCIE_CLK100M_ENETSDN

SSD_CLKREQ_L

PCH_SATA_RCOMP

PCH_SATALED_L

NC_SATA_B_R2D_CP

NC_SATA_B_R2D_CN

NC_SATA_B_D2RP

NC_SATA_B_D2RN

NC_SATA_A_D2RN NC_SATA_A_D2RP NC_SATA_A_R2D_CN NC_SATA_A_R2D_CP

NC_SATA_ODD_D2RN NC_SATA_ODD_D2RP NC_SATA_ODD_R2D_CN NC_SATA_ODD_R2D_CP

XDP_DC1_SATARDRVR_EN

XDP_DC0_DP_AUXCH_ISOL_L

NC_SATA_F_R2D_CN

NC_SATA_F_D2RP

NC_SATA_F_R2D_CP

NC_SATA_D_R2D_CN

NC_SATA_D_D2RP

NC_SATA_D_R2D_CP

NC_SATA_D_D2RN

TP_PCIE_ENET_D2RN TP_PCIE_ENET_D2RP

NC_SATA_F_D2RN

TP_PCIE_ENET_R2D_CP

TP_PCIE_ENET_R2D_CN

HDA_SDOUT_R

NC_HDA_SDIN2

TBT_CLKREQ_L

CAMERA_CLKREQ_L

NC_PCIE_CLK100M_ENETP

PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_PEGBP

DMI_CLK100M_CPU_P

CPU_CLK135M_DPLLSS_N CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLREF_N CPU_CLK135M_DPLLREF_P

PCH_CLK100M_SATA_N

PP1V5_S0

DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

PCH_CLK33M_PCIOUT

NC_LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

NC_ITPXDP_CLK100MP

NC_ITPXDP_CLK100MN

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PEG_CLKREQ_L

TBT_CLKREQ_L

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

XDP_DD3_AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

LPC_CLK33M_DPMUX_UC_R

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_SWP

NC_PCIE_CLK100M_SWN

PCH_CLKRQ7_L_GPIO46

NC_PCI_CLK33M_OUT3

NC_PCIE_CLK100M_PE5N

PCH_CLKRQ5_L_GPIO44

PCH_CLK96M_DOT_P

SYSCLK_CLK25M_SB_R

PCH_CLK33M_PCIIN

NC_PCH_GPIO65_CLKOUTFLEX1

XDP_PCH_TDI

PCH_SPKR

RTC_RESET_L

PCH_INTVRMEN_L

HDA_RST_L

HDA_SYNC

ENET_CLKREQ_L

PCH_CLKRQ7_L_GPIO46

PEG_CLKREQ_L

PCH_CLKRQ5_L_GPIO44

AP_CLKREQ_L

XDP_DD2_ENETSD_CLKREQ_L

PCH_SATALED_L

NC_PCH_GPIO64_CLKOUTFLEX0

SSD_CLKREQ_L

PP1V5_S0

XDP_PCH_TDO

XDP_PCH_TMS

HDA_BIT_CLK

HDA_RST_R_L

HDA_BIT_CLK_R

SYSCLK_CLK32K_RTC

NC_PCIE_CLK100M_ENETN

DMI_CLK100M_CPU_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

NC_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_GPIO66_CLKOUTFLEX2

PCH_CLK100M_SATA_P

PCH_CLKIN_GNDP

PCH_CLKIN_GNDN

PCH_CLK14P3M_REFCLK

PCH_DIFFCLK_BIASREF

NC_HDA_SDIN1

NC_HDA_SDIN3

SYSCLK_CLK25M_SB

PPVRTC_G3H

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTVRMEN_L

PCH_INTRUDER_L

PP1V5_S0

HDA_SYNC_R

PCH_INTRUDER_L

PCH_SRTCRST_L

DP_TBT_SEL

PCH_SPKR

PCH_CLK96M_DOT_N

HDA_SDIN0

HDA_SDOUT

DP_TBT_SEL ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

ENET_MEDIA_SENSE_RDIV

PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_PEGBN

ENET_CLKREQ_L

PEG_CLK100M_N PEG_CLK100M_P

XDP_DD2_ENETSD_CLKREQ_L

<SCH_NUM>

11 OF 119

11 OF 97

12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

12 13 14 15 17 50 64 66 67 84

90

11

87

19 91

87

11 28

11 35

87

11

87

91

11 12 13 15 17 19 52 64 67 81 84 86

18 85

11 18

20

87

11

87

11

91

90

87

11

11 91

11 85

11

11 82 85

11

18 33

11 18

11

87

11 34

11 12 13 15 17 19 52 64 67 81 84 86

91

87

91

87

91

87

12 15 19 84

11

11 91

11 12 13 15 17 19 52 64 67 81 84 86

91

11 91

11 85

11

91

11 85

11

87

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

VGA_DDC_CLK

DDPD_AUXN

DDPB_AUXP

VGA_GREEN

DDPB_AUXN

PLTRST*

PME*

PIRQB* PIRQC* PIRQD*

GPIO50 GPIO52

PIRQA*

DDPD_CTRLCLK

DDPD_CTRLDATA

PIRQE*/GPIO2

DDPD_HPD

DDPB_HPD

DDPD_AUXP

DDPC_AUXP

DDPC_HPD

PIRQF*/GPIO3

EDP_BKLTCTL

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

GPIO53 GPIO55

GPIO51

GPIO54

EDP_BKLTEN

DDPC_AUXN

PIRQG*/GPIO4 PIRQH*/GPIO5

VGA_VSYNC

VGA_IRTN

VGA_BLUE

VGA_RED

VGA_DDC_DATA

VGA_HSYNC

DAC_IREF

EDP_VDDEN

EDP

(5 OF 11)

DISPLAY

PCI

CRT

OUT

IN

OUT

IN

BI

OUT

IN

DMI_RXN3

FDI_CSYNC

FDI_INT

FDI_IREF

DMI_RXN2

SYS_PWROK

CLKRUN*

SLP_S3*

TP10

DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_RXP0

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

WAKE*

TP7

DMI_RCOMP

TP12

DMI_IREF

DMI_TXP3

DMI_TXP2

FDI_RCOMP

DMI_TXN0

SUSWARN*/SUSPWRNACK/GPIO30

TP21

APWROK

FDI_RXN0

FDI_RXP0

FDI_RXN1

FDI_RXP1

SYS_RESET*

DMI_RXN1

TP17 TP13

TP16

TP15

DMI_RXN0

PMSYNCH

TP5

DMI_TXP0 DMI_TXP1

DMI_TXN2 DMI_TXN3

DMI_TXN1

SLP_S4*

DSWVRMEN

SLP_WLAN*/GPIO29

ACPRESENT/GPIO31

SLP_SUS*

PWROK

SLP_A*

SLP_LAN*

DRAMPWROK

RSMRST*

PWRBTN*

BATLOW*/GPIO72

DPWROK

RI*

SUSACK*

FDI

DMI

(4 OF 11)

MANAGEMENT

SYSTEM POWER

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VGA DAC Disabled per SB

Redundant to pull-up on audio page

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPU-PWROK&PCIRST#)

(IPU)

(OD)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

DG v1.0 (Table 12-18).

(IPD-DeepSx)

5

89

5

89

2

1

R1200

201

1/20W

MF

1%

7.5K

PLACE_NEAR=U1100.AY17:12.7mm

5

89

5

89

5

89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

5

87 89

N44

V45

U39

N42

U44

M45

M43

T45

AD10

Y11

M15

L15

F17

G17

M20

K17

L20

H20

AL6

C12

A10

B13

C10

A12

G36

K36

N36

H39

N38

N40

J44

J42

K38

R36

R35

K45

K43

K40

R39

R40

H43

H45

U40

U1100

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

2

1

R1215

5%

201

1/20W MF

330K

12 44 66 67

2

1

R1209

5%

201

1/20W MF

100K

19 40 86 91

18 19 40 86 91

6

21 89

12 19 86 91

67 86 91

12 18 40 91

40 41

12 30 40 42

12 33 35 86 91

12 40

20 40

41

12 40 67

12 21 33 37 40 67 81 86

12 21 40 67 86

6

89

40 86 91

12

R1223

5%

201

1/20W

MF

100K

21

R1225

5%

201

1/20W

MF

1K

21

R1291

5%

201

1/20W

MF

10K

12

R1222

5%

201

1/20W

MF

100K

12

R1221

5%

201

1/20W

MF

100K

12

R1224

5%

201

1/20W

MF

100K

12

R1284

5%

201

1/20W

MF

100K

12

R1281

5%

201

1/20W

MF

100K

K3

AV17

AY45

AB10

AU42

AV43

AV45

AU44

AW17

AW44

AM1

AD7

J4

Y6

R6

U7

D2

F1

Y7

C6

H1

G5

F3

J2

N4

F10

K1

AY3

AL36

AJ36

AL35

AJ35

AR44

AT45

AL40

AL39

C8

H3

L13

BC18

BB17

BC20

BB21

BE18

BD17

BE20

BD21

AW20

AR17

AP20

AY22

AV20

AP17

AR20

AW22

AY17

BE16

AN7

K7

AB7

E6

U1100

OMIT_TABLE

FCBGA

LYNXPOINT

MOBILE

12 82 85

87

5

89

2

1

R1210

201

1/20W

MF

PLACE_NEAR=U1100.AR44:12.7mm

7.5K

1%

21

R1261

5% 201

1/20W

MF

10K

21

R1263

5% 201

1/20W

MF

10K

21

R1262

5% 201

1/20W

MF

10K

21

R1260

5% 201

1/20W

MF

10K

21

R1233

5% 201

1/20W

MF

NO STUFF

10K

21

R1231

5% 201

1/20W

MF

10K

21

R1214

5% 201

1/20W

MF

100K

NO STUFF

21

R1230

5% 201

1/20W

MF

10K

21

R1217

5% 201

1/20W

MF

100K

21

R1218

5% 201

1/20W

MF

10K

12 85

21

R1216

5% 201

1/20W

MF

10K

12 85

12 29

12 85

18 20 21 86

12 85

12

R1240

5%

201

1/20W

MF

10K

21

R1239

5%

201

1/20W

MF

3.0K

42

12 85

2

1

R1205

5%

1/20W

MF

10K

201

2

1

R1287

201

MF

1/20W

5%

10K

NO STUFF

42

2

1

R1286

SMC_SUSACK:NO

0201

1/20W

5%

0

MF

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PP1V5_S0

SDCONN_OC_L

AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

PM_PCH_PWROK

BT_PWRRST_L

ENET_LOW_PWR_PCH

PCI_INTA_L

PCI_INTD_L

AUD_IPHS_SWITCH_EN_PCH

TP_PCH_STRP_ESI_L

TP_PM_SLP_A_L

PM_SLP_S3_L

TP_PCH_SLP_WLAN_L

PM_CLKRUN_L

PCIE_WAKE_L

TP_PCH_SLP_LAN_L

PCI_INTC_L

PCI_INTB_L

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

NC_EDP_IG_BKL_PWM

PM_BATLOW_L

PM_PCH_SYS_PWROK

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1> DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

AUD_IP_PERIPHERAL_DET

DP_TBTSNK0_HPD_IG

NC_DP_IG_D_AUXCHP

DPA_IG_AUX_CH_P

NC_DP_IG_D_AUXCHN

DPB_IG_AUX_CH_N

TP_DP_IG_D_DDC_CLK TP_DP_IG_D_DDC_DATA

DPB_IG_DDC_CLK

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

TP_PCH_STRP_BBS1

PM_SLP_S4_L

FDI_INT

FDI_CSYNC

TP_PCH_SLP_S0_L

PM_DSW_PWRGD

PCH_DSWVRMEN

PPVRTC_G3H

DPA_IG_AUX_CH_N

PP1V5_S0

PM_MEM_PWRGD PM_RSMRST_L

PM_SYSRST_L

DPB_IG_DDC_DATA

TBT_PWR_REQ_L

TP_DP_IG_D_HPD

DP_TBTSNK1_HPD_IG

DPB_IG_AUX_CH_P

PP3V3_S0

SMC_ADAPTER_EN

PCH_STRP_TOPBLK_SWP_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCH_FDI_RCOMP

PM_PWRBTN_L PM_BATLOW_L PM_CLKRUN_L ENET_LOW_PWR_PCH

BT_PWRRST_L SDCONN_OC_L

AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L

AUD_I2C_INT_L PCIE_WAKE_L

PM_SLP_S4_L

PM_SLP_SUS_L EDP_IG_BKL_ON

EDP_IG_PANEL_PWR

PP3V3_S5

PM_SYNC

PM_SLP_SUS_L

PM_SLP_S5_L

PM_SLP_S3_L

PP3V3_S0

PCH_DMI_RCOMP

AUD_IPHS_SWITCH_EN_PCH

PM_PWRBTN_L

PM_PCH_PWROK

PP3V3_SUS

PCH_SUSACK_L

PCH_RI_L

PCH_SUSWARN_L

12 OF 97

12 OF 119

<SCH_NUM>

11 12 13 15 17 19 52 64 67 81 84 86

87

82 85

87

83 85 89

87

83 85 89

83 85

91

11 15 19 84

83 85 89

11 12 13 15 17 19 52 64 67 81 84 86

83 85

82 85

83 85 89

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

12 18 40 91

12 30 40 42

12 40

12 85

12 29

12 85

12 33 35 86 91

12 21 33 37 40 67 81 86

12 44 66 67

12 82 85

14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 40 67

12 21 40 67 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67

68 69 82 83 84 86 96

12 85

11 13 14 15 17 50 64 66 67 84

BI

BI BI

IN IN

OUT

IN

OUT

IN

BI

IN

USBRBIAS

USBRBIAS*

TP24 TP23

USB2P12

USB2N12

PETP3

PETP2_USB3TP4

USB2P11

USB2P1

USB2P13

USB2N11

USB2P7

USB2N8

USB2P9

USB2N9

USB2N3

USB2N2

USB2N1

PERN8 PERP8

USB3RP1

USB3RP6

USB3RN1

USB3RN6

PERP2_USB3RP4

PERP4

PERN4

PERP7

PERN7

USB3RP2

USB3RP5

PERP5

USB3RN2

USB3RN5

PERN1_USB3RN3

PERN3

PERP6

PERP3

PERN6

USB2N10

USB2N4

USB2N0

TP6

PETP5

USB3TP2

USB3TP5

TP11

PETN6

PETP7

USB3TP1

USB3TN2

USB3TN6

PCIE_RCOMP

PETN5

PETP8

PETN8

USB3TN1

USB3TN5

USB3TP6

PCIE_IREF

PETN1_USB3TN3

PETN3

PETP6

PETN7

USB2P8

USB2P3

USB2P2

USB2P10

USB2P4

USB2P0

USB2N13

USB2N5

USB2N7

USB2P5

USB2N6 USB2P6

OC7*/GPIO14

OC4*/GPIO43

OC6*/GPIO10

OC3*/GPIO42

OC0*/GPIO59

OC5*/GPIO9

OC2*/GPIO41

OC1*/GPIO40

PERP1_USB3RP3

PETP1_USB3TP3

PERN2_USB3RN4

PETN2_USB3TN4

PETN4 PETP4

PERN5

PCI-E

USB

(9 OF 11)

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

LAD3

LFRAME*

SML0DATA

LAD0

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

CL_DATA

CL_CLK

TD_IREF

LDRQ0*

SML1CLK/GPIO58

CL_RST*

SML1DATA/GPIO75

LAD2

SPI_MOSI

SPI_MISO

SPI_CS2*

SPI_CLK

SPI_IO3

SPI_IO2

SPI_CS0*

SERIRQ

SPI_CS1*

TP1 TP2 TP4 TP3

LAD1

LDRQ1*/GPIO23

SML1ALERT*/PCHHOT*/GPIO74

SML0CLK

C-LINK

SPI

(3 OF 11)

LPC

SMBUS

IN BI

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

NC

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext B (LS/FS/HS)

Ext C (SS)

(IPD)

Trackpad

BT

IR

Ext D (SS)

USB3 Port Assignments:

Ext B (SS)

Ext A (SS)

Reserved: Camera

Ext D (LS/FS/HS)

Unused

Reserved: PSOC (Legacy Trackpad)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Reserved: WiFi (HS)

Reserved: SD (HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

AirPort

Camera

Lane 3 (PCIe-only)

Lane 2 (PCIe-only)

SSD (Gumstick)

Or PCIe switch if TBT/SSD

SSD (Gumstick)

(PCIe-only)

Lane 0

Lane 1

Or PCIe switch if TBT/SSD

(PCIe-only)

USB3 Port Assignments:

PCIe/USB3 Port Assignments:

SD Card Reader (& Ethernet if combo)

PCIe Port Assignments:

Unused

SSD (Gumstick)

87 90

12

R1367

1/20W

5% 201MF

10K

21

R1368

10K

MF 2015%

1/20W

21

R1361

10K

1/20W

MF 2015%

21

R1362

10K

MF 2015%

1/20W

21

R1360

10K

MF 201

1/20W

5%

21

R1369

10K

MF 2015%

1/20W

13 18

18

13 18

18

13 18

37 90

13 18

K24 K26

BE28

BC26

BC24

BD23

BD27

BE26

BD25

BE24

AP29

AV29

AV26

AP26

AR29

AW29

AW26

AR26

C30

C32

H29

L31

G31

D33

C34

C36

G24

F26

C28

D29

C38

D37

A30

A32

G29

K31

F31

B33

A34

A36

F24

G26

A28

B29

A38

B37

BB29

M33 L33

BC30

BD41

BC40

BE38

BB37

BC36

BC34

BB33

BC32

BD42

BE40

BC38

BD37

BE36

BE34

BD33

BE32

AN39

AT39

AW38

AV36

AR33

AY33

AR31

AY31

AN38

AT40

AY38

AW36

AT33

AW33

AT31

AW31

BD29

BE30

M1

N2

T1

M3

P1

U2

V1

P3

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

37 90

81 86 90

81 90

87 90

50 91

BE43 BE44

BC45

BA45

AY43

AH1

AH3

AJ2

AJ4

AJ10

AL7

AJ7

AJ11

N11

K6

H6

R7

U8

N8

U11

R10

N7

AL11

B21

G20

D21

C18

A18

C20

A20

AF7

AF10

AF11

U1100

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

43 91

18 43 81 85 86 91

2

1

R1300

PLACE_NEAR=U1100.BD29:12.7mm

1/20W 201

MF

1%

7.5K

21

R1340

201MF5%

1/20W

33

21

R1341

MF 2015%

1/20W

33

21

R1343

2015%331/20W

MF

21

R1342

MF 201

33

5%

1/20W

21

R1344

5% 201MF

1/20W

33

13 20

13 40

21

R1350

1/20W

5% 201MF

10K

40 82 91

2

1

R1380

8.2K

MF

1/20W 201

1%

33 90

87 90

38 86 90

21

R1355

1/20W

5% 201MF

10K

21

R1354

1/20W

5% 201MF

10K

21

R1353

1/20W

5% 201MF

10K

21

R1320

1/20W

5% 201MF

10K

21

R1321

1/20W

5% 201MF

10K

50 91

13 50 91

18

21

R1351

10K

MF 2015%

1/20W

21

R1393

1/20W

5% 201MF

1K

21

R1392

1/20W

5% 201MF

1K

81 86 90

20 81 86 91

81 86 90

85

20 33 91

33 91

20 36 91

36 91

2

1

R1370

1% 1/20W

201

MF

22.6

PLACE_NEAR=U1100.K24:11.4mm

PCH PCI-E/USB

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CAMERA_PWR_EN_PCH

XDP_DB1_USB_EXTD_OC_L

SPI_IO<2>

XDP_DB3_SDCONN_STATE_CHANGE_L

SD_PWR_EN

SSD_PWR_EN

XDP_DA1_USB_EXTC_OC_L

TBT_PWR_EN_PCH XDP_DA0_USB_EXTA_OC_L

XDP_DB0_USB_EXTB_OC_L

PCH_SMBALERT_L PCH_SML0ALERT_L PCH_SML1ALERT_L

NC_PCIE_SSD_D2RN<0> NC_PCIE_SSD_D2RP<0>

NC_PCIE_SSD_D2RP<1>

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_P

USB3_SD_D2R_N

NC_USB3_SPARE_R2D_CN NC_USB3_SPARE_R2D_CP

NC_USB3_SPARE_D2RN NC_USB3_SPARE_D2RP

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_P PCIE_CAMERA_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

NC_PCIE_SSD_R2D_CP<0>

NC_PCIE_SSD_D2RN<1>

NC_PCIE_SSD_R2D_CP<1>

NC_PCIE_SSD_R2D_CN<1>

NC_PCIE_SSD_R2D_CN<0>

NC_PCIE_SSD_D2RN<2>

NC_PCIE_SSD_R2D_CN<2>

NC_PCIE_SSD_D2RP<2>

NC_PCIE_SSD_R2D_CN<3> NC_PCIE_SSD_R2D_CP<3>

NC_PCIE_SSD_D2RP<3>

NC_PCIE_SSD_D2RN<3>

NC_PCIE_SSD_R2D_CP<2>

PCH_USB_RBIAS

LPC_AD_R<0>

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

NC_CLINK_DATA

NC_CLINK_CLK

PCH_TD_IREF

NC_CLINK_RESET_L

SPI_MOSI_R SPI_MISO

TP_SPI_CS2_L

SPI_CLK_R

SPI_IO<3>

SPI_IO<2>

SPI_CS0_R_L

LPC_SERIRQ

TP_SPI_CS1_L

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTA_N USB_EXTA_P

NC_USB_EXTCN NC_USB_EXTCP

USB_EXTB_N USB_EXTB_P

NC_USB_EXTDN NC_USB_EXTDP

USB_BT_N

NC_USB_IRN

USB_BT_P

USB_TPAD_N

NC_USB_IRP

USB_TPAD_P

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_P USB3_EXTB_R2D_C_N

NC_USB3_EXTC_D2RP

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_R2D_CN

XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTC_OC_L

XDP_DA3_CAMERA_PWR_EN XDP_DB0_USB_EXTB_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

NC_USB_7P

NC_USB_WLANN

NC_USB_SDN

TP_USB_CAMERAN

NC_USB_4N

NC_USB_WLANP

NC_USB_SDP

NC_USB_4P NC_USB_PSOCN

NC_USB_7N

NC_USB_PSOCP NC_USB_6N

PP1V5_S0

NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RP

NC_USB3_EXTD_R2D_CP

XDP_DB2_SD_PWR_EN

PCH_PCIE_RCOMP

NC_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

NC_USB3_EXTC_R2D_CN

TP_USB_CAMERAP

NC_USB_6P

XDP_DA2_SSD_PWR_EN

USB3_EXTB_R2D_C_P NC_USB3_EXTC_D2RN

SPI_IO<3>

LPC_SERIRQ

PP3V3_SUS PP3V3_SUS

PP3V3_S0

PP3V3_S3RS0_CAMERA

PP3V3_S3

13 OF 119

<SCH_NUM>

13 OF 97

18 20

13 18

13 50 91

13 18

18 81 86

18 66

13 18

13 20

13 18

13

87

90

13

87

13

87 90

87

87 90

87

87 90

87

87 90

87

87 90

11 12 15 17 19 52 64 67 81 84 86

87

87 90

13 50 91

13 40

11 12 13 14 15 17 50 64 66 67 84

11 12 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55 66

67 68 69 82 83 84 86 96

20 35 46 84

20 21 43 45 46 66 81 82 84 86

OUT

BI

IN

OUT

IN

BI

ININ

OUT

IN

OUT

SATA2GP/GPIO36

VSS

RCIN*

PROCPWRGD

PECI

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

VSS

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

LAN_PHY_PWR_CTRL/GPIO12

TP14

PLTRST_PROC*

GPIO8

VSS

TACH0/GPIO17

SATA4GP/GPIO16

GPIO15

GPIO28

SATA3GP/GPIO37

SATA5GP/GPIO49

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

GPIO34

GPIO35/NMI*

SLOAD/GPIO38

THRMTRIP*

SCLOCK/GPIO22

TACH4/GPIO68

GPIO27

GPIO57

GPIO24

BMBUSY*/GPIO0

(6 OF 11)

GPIO

CPU/MISC

OUT

BI

OUT

IN

OUT

BI

OUT

IN

IN IN

OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

Pull-up/down on chipset support page (depends on TBT controller)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high. Systems with chip-down memory should add pull-downs on another page and set straps per software.

Falcon Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.

(IPU-Boot/SATA5GP?)

NOTE: GPIO0 pull-up/down on project-specific page

(IPD-PLTRST#)

(IPD)

(IPU-RSMRST#)

(IPU-DeepSx)

(IPU-Boot/SATA4GP?)

(IPU-Boot?)

NOTE: GPIO70 pull-up/down on project-specific page

6

18 89

14 85

14 20

18

14 20

14 50 86

6

41 89

2

1

R1472

5%

201

1/20W MF

10K

RAMCFG3:H

2

1

R1473

5%

201

1/20W

MF

10K

RAMCFG2:H

2

1

R1474

5%

201

1/20W MF

10K

RAMCFG1:H

2

1

R1475

5%

201

1/20W

MF

10K

RAMCFG0:H

14 40

14 20

14 40

14 85

N10

A4

E45

E1

D1

BE3

BE2

BD45

BD44

BD2

BD1

BC1

BA1

B45

B44

B2

B1

A44

A43

A41

A2

A5

C45

BE5

BE41

AN10

AV1

H15

G13

D13

C16

G15

A14

F13

C14

AT7

AN4

AM3

BB4

AK3

AN2

AK1

AT3

AT6

AV3

AU4

AY1

K13

Y1

U12

AP1

AN6

AD11

R11

Y10

AB11

AT8

U1100

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

12

R1411

5% 201

1/20W

MF

20K

12

R1495

5% 201

1/20W

MF

100K

21

R1491

5% 201

1/20W

MF

10K

21

R1492

5% 201

1/20W

MF

10K

21

R1493

5% 201

1/20W

MF

100K

21

R1494

5% 201

1/20W

MF

10K

21

R1484

5% 201

1/20W

MF

10K

21

R1490

5% 201

1/20W

MF

100K

21

R1496

5% 201

1/20W

MF

10K

21

R1485

5% 201

1/20W

MF

10K

12

R1412

5% 201

1/20W

MF

10K

29

14 18

12

R1498

5% 201

1/20W

MF

10K

21

R1450

5% 201

1/20W

MF

10K

21

R1455

5% 201

1/20W

MF

10K

21

R1470

5%

1/20W

MF43201

NO STUFF

21

R1440

MF

1/20W

0201

5%

0

21

R1456

390

201

1/20W

MF

5%

CRW_SPRT

6

41 89

14 85

20 28

18

14 85

6

21

R1486

5% 201

1/20W

MF

10K

21

R1499

5% 201

1/20W

MF

10K

12

R1413

5% 201

1/20W

MF

10K

14 85

21

R1489

5% 201

1/20W

MF

10K

18

14 82 85

14 18

2

1

R1457

MF-LF 402

1/16W

1K

5%

BDW_SPRT

18 20 20

21

PCH GPIO/MISC/NCTF

SYNC_MASTER=CLEAN_X425

SYNC_DATE=10/31/2014

R1456

BDW_SPRT

1

117S0201

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

ISOLATE_CPU_MEM_L

SMC_WAKE_SCI_L

XDP_DD0_SSD_PCIE_SEL_L

WOL_EN

SMC_RUNTIME_SCI_L

FW_PME_L

TBT_CIO_PLUG_EVENT_L

PM_THRMTRIP_L_R

PCH_PROCPWRGD

PM_THRMTRIP_L

PCH_PECI

PCH_A20GATE

PCH_RCIN_L

PP1V05_S0

CPU_PECI

SD_SEL_PCIE_L_USB_H

JTAG_ISP_TDO

PP3V3_SUS

XDP_DD0_SSD_PCIE_SEL_L

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO JTAG_TBT_TMS_PCH

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK

JTAG_ISP_TDI

PCH_RCIN_L

PP3V3_S5

PP3V3_S0

SPIROM_USE_MLB

CPU_RESET_L

CPU_PWRGD

PCH_A20GATE

SMC_RUNTIME_SCI_L WOL_EN

TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

FW_PWR_EN_PCH

MLB_RAMCFG0

SPIROM_USE_MLB

JTAG_ISP_TDO JTAG_ISP_TDI

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

XDP_FC1_GPU_GOOD

DPMUX_UC_IRQ

FW_PME_L DPMUX_UC_IRQ

MLB_RAMCFG2

MLB_RAMCFG3

FW_PWR_EN_PCH

XDP_FC0_HDD_PWR_EN

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO

TBT_GO2SX_BIDIR

TBT_POC_RESET_L

XDP_DD1_MLB_RAMCFG1

PP3V3_S0

JTAG_TBT_TMS_PCH

14 OF 97

14 OF 119

<SCH_NUM>

41 42

91

14

14 91

10 15 17 18 41 62 67 84 86

14 20

11 12 13 15 17 50 64 66 67 84

14 18

14 85

14 20

14 18

18 20

14 20

14 91

12 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

14 50 86

14

14 40

14 85

14 40

14 85

20

14 85

14 82 85

20

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

VCCCLK

VCCIO

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCSUSHDA

DCPRTC

V_PROC_IO

VCC

VCC3_3

VCCASW

VCCCLK

VCCCLK3_3

VCCIO

VCCVRM

VSS

VCCRTC

DCPSST

VCCSPI

VCCUSBPLL

DCPSUS2

VCCSUS3_3

CLK/MISC

SPI CPU RTC HDA

USB

GPIO/LPC

(8 OF 11)

THERMAL

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCC3_3: 133mA Max, 3mA Idle

6uA Max (3.0V, room temperature)

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

15 mA Max, 1mA Idle

2

1

C1532

20% 10V

0.1UF

BYPASS=U1100.A6::6.35mm

402

CERM

2

1

C1531

10%

6.3V CERM

1UF

BYPASS=U1100.A6::6.35mm

402

2

1

C1533

20% 10V

402

0.1UF

BYPASS=U1100.A6::6.35mm

CERM

P43

BE22

BB44

AN11

AK28

AK26

AJ32

AJ30

AM20

AM18

AK22

AK20

AK18

AT22

AR22

AP22

AN35

AN34

AM22

V24

V22

V20

V18

U24

U22

U20

U18

AA18

Y22

Y20

Y18

M31

P45

AD28

AD26

AD24

AD22

AD20

AA26

R32

R30

AA24

Y26

AG24

AG22

AG20

AG18

AE26

AE24

AE22

AE20

AE18

U14

AJ28

AJ26

Y12

U1100

OMIT_TABLE

LYNXPOINT

MOBILE

CKPLUS_WAIVE=PwrTerm2Gnd

FCBGA

M24

AW40

AF34

U35

A26

U26

R28

R26

R24

R22

R20

K8

AD12

A6

Y30

V30

V28

U36U30

A16

AG32

AG30

AE32

AE30

AD36

AD35

V32

U32

M29

M26

L29

L26

AD34

AA32

AA30

Y32

R18

L17

AK32

AK30

AG14

AF12

AE14

L24

AP45

P20

P18

AJ14

AJ12

Y35

AA14

P16

P14

U1100

MOBILE

FCBGA

LYNXPOINT

OMIT_TABLE

2

1

C1550

402

CERM

PLACE_NEAR=R1550.1:2.54mm

1UF

6.3V

10%

21

R1550

PLACE_NEAR=U1100.U14:2.54mm

201

5.11

1/20W MF-LF

1%

2

1

C1590

0.1UF

20% 10V CERM 402

BYPASS=U1100.P14::6.35mm

2

1

C1580

10V

20% CERM

402

0.1UF

BYPASS=U1100.AA14::6.35mm

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PCH Power

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

PP3V3_SUS

PP1V05_S0

PP3V3_S5

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_CLK_F

PP1V5_S0

PP1V05_S0

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PPVRTC_G3H

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP1V05_S0

<SCH_NUM>

15 OF 119

15 OF 97

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 50 64 66 67

84

10 14 15 17 18 41 62 67 84

86

12 14 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

17

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 50 64 66 67 84

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67

84

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 14 15 17 50 64 66 67

84

11 12 19 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

VSS

(10 OF 11)

VSS VSS

VSS

(11 OF 11)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Y8

Y40

AM16

Y36

Y34

Y28

Y24

Y16

Y14

W44

W2

V43

V26

AM32

V16

V14

U6

U42

U38

U34

U28

U16

U10

T43

AM30

R8

R44

R38

R34

R2

R16

R14

R12

P32

P30

AM28

P28

P26

P24

P22

N6

N39

N35

N12

M22

M17

AM26

L44

L2

K39

B15

B11

AY7

AY29

AY26

AY20

AY15

AM24

AY10

F43

AW2

AV6

AV40

BB25

AV33

AV31

AV24

AV22

AM14

AV13

D42

AT38

AT36

AT29

AT26

AT20

AT17

AT15

AT10

AL8

AK16

AR2

AP43

AP31

AP24

AP13

AN8

AN42

AN40

AN36

AL38

AL34

U1100

FCBGA

LYNXPOINT

OMIT_TABLE

MOBILE

AB38

AB34

AB12

AA4

AA28

AA22

AA20

AA16

BC28

K33

K29

K20

K15

K10

H7

H40

H36

H31

H26

H24

H22

H17

H13

H10

G8

G44

G38

G2

D4

BC16

F33

F29

F20

F15

AV7

D25

BD7

BD39

BD35

BD31

AT43

AY36

BD19

BD15

BD11

BA40

B7

B39

B35

B31

B27

B23

B19

BB42

BC22

AL2

AL12

AK45

AK43

AK24

AK14

AJ8

AJ6

AJ38

AJ34

AJ24

AJ22

AJ20

AJ18

AJ16

AG44

AG28

AG26

AG2

AG16

AF8

AF38

AE28

AE16

AD8

AD6

AD40

AD32

AD30

AD18

AD16

AD14

AC44

AC2

AB8

U1100

FCBGA

OMIT_TABLE

MOBILE

LYNXPOINT

PCH Grounds

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

16 OF 97

16 OF 119

<SCH_NUM>

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

183mA Max, 68mA Idle

PCH VCCVRM BYPASS

(PCH 3.3V USB2 PWR)

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR)

PCH VCCSPI BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR)

PCH VCCCLK BYPASS (PCH 1.05V DIFFCLK135 PWR)

(PCH 3.3V FUSE PWR)

670mA Max, 34mA Idle

(PCH 3.3V/1.5V HDA PWR)

PCH VCCIO BYPASS

PCH VCCSUSHDA BYPASS

(PCH 1.5V VCCVRM PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V CLK PWR)

PCH VCCCLK3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCCIO BYPASS (PCH 1.05V FDI PWR)

PCH VCCUSBPLL BYPASS

(PCH 1.05V CORE PWR)

PCH VCC BYPASS

Not documented in EDS!

(PCH 1.05V USB2 PLL PWR)

(PCH 1.05V SSC PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH VCCCLK BYPASS (PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V CLK PLL PWR)

PCH CLK VCC BYPASS

(PCH 3.3V THERMAL PWR)

PCH VCCIO BYPASS (PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCASW BYPASS

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

PCH VCC BYPASS

PCH V_PROC_IO BYPASS (PCH 1.05V CPU I/F PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND USB PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

(PCH 3.3V SPI PWR)

(PCH 1.05V USB2 PWR)

(PCH 1.05V ME CORE PWR)

2

1

C1777

1.0UF

0402

X6S

BYPASS=U1100.AG30::6.35mm

6.3V

10%

2

1

C1778

1.0UF

0402

X6S

BYPASS=U1100.AD35::6.35mm

6.3V

10%

2

1

C1780

1.0UF

0402

X6S

BYPASS=U1100.AD34::6.35mm

6.3V

10%

2

1

C1782

1.0UF

0402

X6S

BYPASS=U1100.AA30::6.35mm

6.3V

10%

2

1

C1764

1.0UF

0402

X6S

BYPASS=U1100.AM18::6.35mm

6.3V

10%

2

1

C1752

1.0UF

0402

X6S

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

2

1

C1751

1.0UF

0402

X6S

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

2

1

C1750

PLACE_NEAR=U1100.V20:2.54mm

X5R-CERM-1

22UF

6.3V 603

20%

2

1

C1758

1.0UF

0402

X6S

BYPASS=U1100.AE18::6.35mm

6.3V

10%

2

1

C1763

1.0UF

0402

X6S

BYPASS=U1100.AK20::6.35mm

6.3V

10%

2

1

C1757

1.0UF

0402

X6S

BYPASS=U1100.AD20::6.35mm

6.3V

10%

2

1

C1755

BYPASS=U1100.AG18::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1756

1.0UF

0402

X6S

BYPASS=U1100.AA24::6.35mm

6.3V

10%

2

1

C1762

1.0UF

0402

X6S

BYPASS=U1100.AK22::6.35mm

6.3V

10%

2

1

C1761

1.0UF

0402

X6S

BYPASS=U1100.AK18::6.35mm

6.3V

10%

2

1

C1760

BYPASS=U1100.AK18::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1776

1.0UF

0402

X6S

BYPASS=U1100.AE30::6.35mm

6.3V

10%

2

1

C1770

1.0UF

0402

X6S

BYPASS=U1100.U35::6.35mm

6.3V

10%

2

1

C1772

1.0UF

0402

X6S

BYPASS=U1100.AN34::6.35mm

6.3V

10%

2

1

C1774

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.U30::6.35mm

10%

2

1

C1787

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AJ12::6.35mm

10%

2

1

C1785

1.0UF

0402

X6S

BYPASS=U1100.AJ12::12.7mm

6.3V

10%

2

1

C1786

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AJ12::6.35mm

10%

2

1

C1723

1.0UF

0402

X6S

BYPASS=U1100.U32::6.35mm

6.3V

10%

2

1

C1726

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.R30::6.35mm

10%

2

1

C1728

BYPASS=U1100.AE14::6.35mm

16V

X7R-CERM

0402

0.01UF

10%

2

1

C1730

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.L24::6.35mm

10%

2

1

C1732

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.AK30::6.35mm

10%

2

1

C1734

1.0UF

0402

X6S

BYPASS=U1100.P18::6.35mm

6.3V

10%

2

1

C1791

BYPASS=U1100.AP45::6.35mm

10V X6S-CERM 0402

1UF

10%

2

1

C1790

BYPASS=U1100.AP45::12.7mm

NO STUFF

16V

X6S-CERM

0603

10UF

20%

21

L1790

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

21

R1790

1

1/16W

5%

MF-LF

402

2

1

C1740

BYPASS=U1100.AF34::12.7mm

16V

X6S-CERM

0603

10UF

20%

2

1

C1722

1.0UF

0402

X6S

BYPASS=U1100.M29::6.35mm

6.3V

10%

2

1

C1721

1.0UF

0402

X6S

BYPASS=U1100.L29::6.35mm

6.3V

10%

2

1

C1720

1.0UF

0402

X6S

BYPASS=U1100.L26::6.35mm

6.3V

10%

2

1

C1700

0.1UF

25V

X7R-CERM

0402

BYPASS=U1100.A16::6.35mm

10%

2

1

C1704

0402

X7R-CERM

25V

BYPASS=U1100.R20::6.35mm

0.1UF

10%

2

1

C1702

1.0UF

0402

X6S

BYPASS=U1100.AD12::6.35mm

6.3V

10%

2

1

C1708

1.0UF

0402

X6S

BYPASS=U1100.K8::6.35mm

6.3V

10%

2

1

C1706

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.R26::6.35mm

10%

2

1

C1710

0.1UF

0402

X7R-CERM

25V

BYPASS=U1100.A26::6.35mm

10%

2

1

C1775

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1765

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1759

CRITICAL

25V

0201

NP0-C0G

5%

12PF

2

1

C1753

25V

0201

5%

CRITICAL

NP0-C0G

12PF

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1113S0022

PCH DECOUPLING

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

PP1V05_S0

PP3V3_SUS

PP3V3_S0

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

PP1V5_S0

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

PP3V3_SUS

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V5_S0

PP1V05_S0

PP3V3_SUS

PP3V3_S5

PP3V3_S0

PP1V5_S0

<SCH_NUM>

17 OF 119

17 OF 97

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

15

11 12 13 15 17 19 52 64 67 81 84 86

11 12 13 14 15 17 50 64 66 67 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 15 17 19 52 64 67 81 84 86

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67 84

12 14 15 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 15 17 19 52 64 67 81 84 86

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

OUT

IN

BI

TP

IN

OUT

NCNC

Y

NC NC

VCC

GND

A

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT

NC NC

BI

IN

IN IN

IN

TP

IN

IN IN

OUT

BI IN

OUT

IN

OUT

IN

OUT

G

VER 5

SD

G

VER 5

SD

G

VER 5

SD

G

VER 5

SD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OBSDATA_A3

OBSDATA_B0 OBSDATA_B1

OBSDATA_B3

Unused PCH/XDP Signals

signal destination (to minimize stub).

Merged (CPU/PCH) Micro2-XDP

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

OBSFN_D0

OBSDATA_C2

OBSFN_C1

TCK0

TDI and TMS are terminated in CPU.

PCH/XDP Signals

(All 10 R’s)

Non-XDP Signals

PCH/XDP Signal Isolation Notes: ’Output’ non-XDP signals require pulls.

signal path needs to split between route

’Output’ PCH/XDP signals require pulls.

OBSFN_B1

OBSFN_B0

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

VCC_OBS_AB

Extra BPM Testpoints

CPU JTAG Isolation

SDA

TCK1

SCL

HOOK2

HOOK1

HOOK3

OBSDATA_B2

PWRGD/HOOK0

518S0847

TDO TRSTn TDI TMS

VCC_OBS_CD RESET#/HOOK6

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

OBSDATA_D2

OBSFN_A0 OBSFN_A1

OBSFN_C0

OBSDATA_C1

OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSFN_D1

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

from PCH to J1850 and path to non-XDP

R187x and R189x should be placed where

20

11 85

21

R1897

201

SHORT

OMIT

NONE NONENONE

21

R1896

201

SHORT

NONE NONENONE

OMIT

21

R1872

201

NONE

OMIT

NONE NONE

SHORT

13

21

R1875

201

NONE

SHORT

NONE NONE

OMIT

11 18

11

11 18

21

R1890

NONE

201

OMIT

SHORT

NONENONE

13 37

13 81 86

13

14 20

21

R1893

201

SHORT

NONENONE NONE

OMIT

13 20 13

81 86

21

R1894

201

NONE NONE NONE

SHORT

OMIT

13

21

R1879

201

SHORT

OMIT

NONE NONE NONE

11

11 18

14

11 18

11 33

13 66 13

14 18 14 18

21

R1895

201

SHORT

NONENONENONE

OMIT

14 34

13

14

1

TP1810

TP-P6

1

TP1811

TP-P6

1

TP1812

TP-P6

1

TP1813

TP-P6

6

18 86 89

6

18 86 89

6

86 89

12

R1861

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U1100.AE2:28mm

12

R1860

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AD3:28mm

12

R1862

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AD1:28mm

12

R1866

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U1100.AB3:28mm

6

86 89

2

1

R1845

5%

201

1/20W MF

330K

4

6

5

1

3

2

U1845

74LVC1G07GF

SOT891

2

1

C1845

16V

0201

X5R-CERM

0.1UF

10%

19 40 58 67 86

21

R1820

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.M49:28mm

12

R1823

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.N54:28mm

6

89

6

89

6

89

6

89

6

89

6

89

6

89

6

89

6

89

2

1

R1830

5%

150

402

MF-LF

1/16W

12 20 21 86

11 18 86

21

R1805

5% 201

1/20W

MF

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

6

89

6

89

6

89

6

19 89

2

1

C1806

CERM-X5R

0.1UF

10%

6.3V 0201

XDP

2

1

C1801

XDP

6.3V CERM-X5R 0201

0.1UF

10%

9

8 7

64 63

62

61

60659

58 57

56 55

54 53

52 51

50549

48 47

46 45

44 43

42 41

40439

38 37

36 35

34 33

32 31

30329

28 27

26 25

24 23

22 21

20219

18 17

16 15

14 13

12 11

10

1

J1800

CRITICAL XDP_CONN

DF40RC-60DP-0.4V

M-ST-SM1

2

1

C1800

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

6

86 89

6

86 89

6

89

6

89

6

89

6

86 89

6

89

6

89

6

89

1

TP1802

TP-P6

1

TP1803

TP-P6

1

TP1804

TP-P6

1

TP1805

TP-P6

1

TP1806

TP-P6

1

TP1807

TP-P6

6

89

6

89

6

89

6

89

6

89

6

89

2

1

C1804

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

R1831

5%

1K

XDP

MF-LF 402

1/16W

6

89

6

89

6

89

8

13 43 81 85 86 91

11 18 86

21

R1800

5% 201

1/20W

MF

PLACE_NEAR=U0500.F50:2.54mm

1K

XDP

21

R1802

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

21

R1804

5%

0

XDP

402

MF-LF1/16W

6

14 89

12 40 91

12 19 40 86 91

6

18 86 89

12

R1824

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.M53:28mm

21

R1876

201

OMIT

NONENONENONE

SHORT

14 18 20 14 18 20

1

2

6

Q1840

CRITICAL

DMN5L06VK-7

SOT563

PLACE_NEAR=J1800.53:28mm

XDP

4

5

3

Q1840

DMN5L06VK-7

PLACE_NEAR=J1800.51:28mm

SOT563

XDP

CRITICAL

4

5

3

Q1842

CRITICAL

XDP

SOT563

DMN5L06VK-7

PLACE_NEAR=J1800.55:28mm

1

2

6

Q1842

XDP

PLACE_NEAR=J1800.57:28mm

SOT563

CRITICAL

DMN5L06VK-7

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

CPU & PCH XDP

XDP_DD1_MLB_RAMCFG1

SD_PWR_EN

SSD_PWR_EN CAMERA_PWR_EN_PCH

SDCONN_STATE_CHANGE_L

XDP_DC1_SATARDRVR_EN

XDP_DD2_ENETSD_CLKREQ_L

XDP_PCH_TDI

XDP_CPU_TDI

XDP_CPU_TMS

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_CPU_PRESENT_L

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

XDP_SYS_PWROK

SMBUS_PCH_DATA

XDP_CPU_TCK

PP5V_S0

CPU_PWRGD

PP1V05_S0

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

ALL_SYS_PWRGD

CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<19>

CPU_PWR_DEBUG

PLT_RESET_L

CPU_CFG<14> CPU_CFG<15>

XDP_DBRESET_L

CPU_CFG<1>

XDP_CPU_PREQ_L

CPU_CFG<0>

XDP_BPM_L<1>

XDP_BPM_L<0>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

CPU_CFG<3>

XDP_BPM_L<2>

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

XDP_CPU_TCK

AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_DA1_USB_EXTC_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_FC1_GPU_GOOD

SMBUS_PCH_CLK

XDP_CPU_PRDY_L

USB_EXTA_OC_L

USB_EXTB_OC_L

DP_AUXCH_ISOL_L

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK SSD_PCIE_SEL_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_CAMERA_PWR_EN

XDP_DA2_SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_L XDP_DB2_SD_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DC1_SATARDRVR_EN

MAKE_BASE=TRUE

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

MAKE_BASE=TRUE

XDP_DD0_SSD_PCIE_SEL_L

XDP_DD3_AP_CLKREQ_L

XDP_DD1_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_DD2_ENETSD_CLKREQ_L

MAKE_BASE=TRUE

XDP_DC0_DP_AUXCH_ISOL_L

PP1V05_SUS

XDP_PCH_TDI

XDP_CPURST_L

PPVCCIO_S0_CPU

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<11>

PP3V3_S5

XDP_PCH_TCK

PP1V05_S0

XDP_PCH_TDO

XDP_JTAG_CPU_ISOL_L

XDP_TRST_L

XDP_PCH_TMS

18 OF 119

<SCH_NUM>

18 OF 97

6

18 86 89

19 36 49 58 59 62 63 66 67 73 79 80 84 85 86

10 14 15 17 18 41 62 67 84 86

6

18 86 89

6

18 86 89

11 18 86

6

18 86 89

64 84

11 18 86

5 6 8

10 58

12 14 15 17 19 21 31 32 33 61 64 66 67 82 84 85 86

96

10 14 15 17 18 41 62 67 84 86

IN

OUT

IN

OUT

NC NC

IN

OUT

OUT OUT

OUT

IN

Y

A

B

08

Y

A

B

08

IN

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

VER 3

D

SG

G

VER 5

SD

NC

YA

B

NC

GND

VCC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

WF: Do we need this?

VCCST (1.05V S0) PWRGD

PCH ME Disable Strap

PCH PWROK Generation

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

SMC controls strap enable to allow in-field control of strap setting.

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

SB XTAL Power Camera XTAL Power

GreenClk 25MHz Power

Coin-Cell: VBAT (300-ohm & 10uF RC)

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

VDDIO_25M_B: Camera power rail for XTAL circuit.

available ~3.3V power

create VDD_RTC_OUT. +V3.3A should be first

internally ORed to

VBAT and +V3.3A are

to reduce VBAT draw.

For SB RTC Power

No Coin-Cell: 3.42V G3Hot (no RC)

least 5ms after all rails are valid.

NOTE: ALL_SYS_PWRGD must remain low until at

NOTE: 30 PPM crystal required

IPD = 9-50k

TBT XTAL Power

VDDIO_25M_A: SB power rail for XTAL circuit.

PCH Reset Button

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH 33MHz Clocks

System RTC Power Source & 32kHz / 25MHz Clock Generator

No bypass necessary

NOTE: SLG3NB148A provides slow rising edge on 25MHZ_B when powered from

1.2V VDDIO. Falcon Ridge also complicates VDD_25M power, forcing at least S4. Both issues to be addressed in upcoming part (SLG3NB148C).

6

18 89

21

R1996

5%

0

MF-LF

1/16W

402

XDP

21

R1955

5%

201

22

MF

PLACE_NEAR=U1100.D44:6.35mm

1/20W

11 91 40 91

11 91

21

R1959

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.A40:6.35mm

11 91

2

1

R1997

0

5%

OMIT

1/16W MF-LF 402

SILK_PART=SYS RESET

2

1

R1995

1K

MF-LF 402

1/16W

5%

12 40 86 91

11 90

28 90

2

1

C1910

1UF

6.3V

10% CERM

402

2

1

C1902

X5R

10% 10V

402-1

1UF

2

1

C1920

0.1UF

20%

CERM

402

10V

2

1

C1922

20% 10V

CERM

402

0.1UF

2

1

R1906

5%

NO STUFF

1M

MF-LF

1/16W 402

2

1

C1924

20%

402

CERM

10V

0.1UF

21

R1905

5%

0

402

MF-LF

1/16W

2 1

C1905

12PF

C0G

50V

0402

5%

21

C1906

C0G

50V

12PF

0402

5%

40 41

2

1

R1921

5%

201

1/20W MF

1K

2

1

R1920

5%

201

1/20W MF

100K

11 91

36 90

1

2

R1948

NO STUFF

0201

0

5% 1/20W MF

12 19 86 91

21

R1949

MF-LF

5%

402

1/16W

1K

12 18 40 86 91 58

18 40 58 67 86

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

PLACE_NEAR=U1100.AD7:7MM

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

7

8

4

2

1

U1950

74LVC2G08GT/S505

SOT833

2

1

R1950

5%

402

MF-LF

2.0K

1/16W

2

1

C1950

0.1UF

CERM

BYPASS=U1950::5MM

402

10V

20%

29 30 40 41

2

1

R1947

5%

0

0201

1/20W

MF

3 4

1

14

6

11

13

5

17216107

12

15

8

9

U1900

SLG3NB148CV

TQFN

CRITICAL

31

42

Y1905

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

CRITICAL

1

2

6

Q1920

SOT563

DMN5L06VK-7

4

5

3

Q1920

SOT563

DMN5L06VK-7

4

6

5

3

1

2

U1930

BDW_SPRT

74AUP1G09

CRITICAL

SOT891

2

1

C1930

BDW_SPRT

0201

X5R-CERM

16V

10%

0.1UF

2

1

R1930

BDW_SPRT

MF

1/20W 201

5%

10K

8

Chipset Support

SYNC_DATE=10/31/2014

SYNC_MASTER=CLEAN_X425

PP3V3_TBTLC

LPC_CLK33M_SMC

PP3V42_G3H

SYS_PWROK_R

PM_PCH_SYS_PWROK

SMC_DELAYED_PWRGD

PM_PCH_PWROK

PM_S0_PGOOD

CPUVR_PGOOD

PP3V3_S0

PP5V_S0

HDA_SDOUT_R

PM_SYSRST_L

XDP_DBRESET_L

LPC_CLK33M_SMC_R

ALL_SYS_PWRGD

PP3V3_S0

SYSCLK_CLK32K_RTC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

PP1V5_S0

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2

PCH_CLK33M_PCIOUT

PCH_CLK33M_PCIIN

PP3V3_S5

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_LS5V

CPU_VCCST_PWRGD

PP1V05_S0_CPU_VCCST

PM_PCH_PWROK

PP3V3_S5

MAKE_BASE=TRUE

PM_PCH_PWROK

<SCH_NUM>

19 OF 119

19 OF 97

20 28 29 84

19 34 37 38 40 41 42 43 50 56 57 67 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

18 36 49 58 59 62 63 66 67 73 79 80 84 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51

52 55 66 67 68 69 82 83 84

86 96

11 12 15 84

11 12 13 15 17 19 52 64 67 81 84 86

19 34 37 38 40 41 42 43 50 56 57 67 84 86

35

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84

85 86 96

11 12 13 15 17 19 52 64 67 81 84 86

8

10

12 19 86 91

12 14 15 17 18 19 21 31 32 33 61 64 66 67 82 84 85 86 96

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

GND

1Y

VCC

1A

3Y 3A

2A 2Y

Y

B

A

IN

G

VER 5

SD

G

VER 5

SD

OUT

IN

OUT

IN

OUT

IN

OUT

IN

G

SYM_VER_1

D

S

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Buffered

Unbuffered

Platform Reset Connections

AP PCIE D2R test points

PCH 33MHz Clock for DPMUX

GS3 Connector Support

Flexible I/O Configuration Strap

Camera power-up sequencing Support

DEVSLP not supported on LPT-H

Must pull signal correctly even if always USB or PCIe

(Pull-ups on PCH page)

To/From PCH

To/From RR

U2060 supports I/O’s powered when VCC=0V

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

Falcon Ridge Support

RR output is open-drain, no isolation necessary

Pull-up values TBD

Falcon Ridge JTAG Isolation

GPIO Glitch Prevention

From RIO Connector

HDMI HPD pull-down

Camera PCIE D2R test points

LCD HPD Inverter

(Pull-Up on CPU Page)

To/From PCH

TBT_PWR_EN must be high for JTAG Programming

RAM Configuration Straps

RIO SD Card Reader Support

SD Card Reader is always USB3 in this implementaton.

Flexible I/O Aliases

18

14

14 18

14

2

1

R2002

201

MF

1/20W

5%

1K

RAMCFG0:L

2

1

R2011

201

RAMCFG1:L

1K

5% MF

1/20W

2

1

R2012

201

RAMCFG2:L

MF

1/20W

5%

1K

2

1

R2013

201

1/20W MF

5%

1K

RAMCFG3:L

2

1

R2070

MF

1/20W

201

5%

10K

34

2

1

R2040

470K

5%

1/20W

MF

201

20 28 13

12 40

2

1

R2075

10K

5% MF

201

1/20W

14 20 28 14 20 28

14

2

1

R2030

5% MF

100K

201

1/20W

13 20 81 86 91

13 20 81 86 91 13 20 81 86 91

13 20 81 86 91

14

28

2

1

R2063

10K

5% 1/20W MF 201

28

2

1

R2062

MF

1/20W

5%

201

10K

2

1

R2061

1/20W

10K

5% MF

201

81 86

2

1

C2060

X5R-CERM

0201

16V

0.1UF

10%

2

1

R2010

MF

1/20W

5%

100K

201

81 82 86

2

5

7

8

4

6

3

1

U2060

SN74AUP3G07DQER

X2SON

CRITICAL

4

5

3

1

2

U2030

CRITICAL

SOT665

TC7SZ08FEAPE

2

1

C2080

0.1UF

CERM

10V

20%

402

28

4

5

3

Q2040

SOT563

DMN5L06VK-7

1

2

6

Q2040

DMN5L06VK-7

SOT563

82

21

R2057

PLACE_NEAR=U1100.B42:6.35MM

201

5%

MF

22

1/20W

11 20

21

R2072

402

5%

MF-LF

1/16W

0

82

13 18

2

1

C2054

10% 10V

0201

X5R-CERM

0.1UF

PLACE_NEAR=U2050.1:3mm

2

1

R2052

5%

1/20W

10K

MF

201

PLACE_NEAR=U2050.1:3mm

5

4

1

2

3

U2050

MC74VHC1G08

CRITICAL

SC70-HF

21

R2050

NOSTUFF

0

5% MF

1/20W

0201

2

1

C2050

0201

X5R-CERM

0.1UF

10V

10%

BYPASS=U2050::3mm

21

R2051

33

5%

MF

1/20W

201

35

2

1

R2080

MF-LF 402

5% 1/16W

100K

13 36 91

2

1

R2020

MF

1/20W

84.5

1%

NOSTUFF

201

PLACE_NEAR=U1100.AT33:1mm

13 33 91

2

1

R2021

MF

84.5

1%

NOSTUFF

201

1/20W

PLACE_NEAR=U1100.AW33:1mm

5

4

1

2

3

U2080

CRITICAL

MC74VHC1G08

SC70-HF

21

R2091

402

5%

0

MF-LF

1/16W

21

R2087

0

1/16W MF-LF

5%

402

21

R2088

MF-LF

1/16W

0

5%

402

21

R2085

5%

402

1/16W MF-LF

0

2

1

C2030

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

R2041

201

470K

5% 1/20W MF

12 18 21 86

21

R2083

402

33

1/16W MF-LF

5%

35

28

33

34

40

82

2

1

3

Q2010

DMN32D2LFB4

DFN1006H4-3

5

14 18

20 28

3

7

8

4

6

2 5

1

U2000

74LVC2G08GT/S505

CRITICAL

SOT833

2

1

C2013

10%

0.1UF

X5R-CERM 0201

16V

28

28 40 41 42

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=01/14/2013

Project Chipset Support

PP3V3_S3RS0_CAMERA

PP3V3_S4

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

CAMERA_PWR_EN_RC

USB3_SD_D2R_N

USB3_SD_R2D_C_P

CAMERA_PWR_EN_R

CAMERA_PWR_EN

CAMERA_PWR_EN_PCH

USB3_SD_D2R_P

PP3V3_S3

SSD_DEVSLP

MLB_RAMCFG2

SDCONN_STATE_CHANGE_L

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

PP3V3_S0

LPC_PWRDWN_L

TBT_PWR_EN_PCH

JTAG_TBT_TCK

TBT_PWR_EN

MLB_RAMCFG0

XDP_DD1_MLB_RAMCFG1

MLB_RAMCFG3

MAKE_BASE=TRUE

USB3_SD_D2R_N

USB3_SD_D2R_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

DP_INT_IG_HPD

DP_IG_A_HPD_L

PP3V3_S0

PP3V3_S4

JTAG_ISP_TCK

TBT_PWR_EN

SMC_PME_S4_DARK_L

SMC_PME_SDCONN

HDMI_HPD

RIO_SDCONN_STATE_CHANGE_L

SD_SEL_PCIE_L_USB_H

PP3V3_S0

PP3V3_TBTLC

JTAG_TBT_TMS

PP3V3_S0

MAKE_BASE=TRUE

TBT_CIO_PLUG_EVENT_L TBT_CIO_PLUG_EVENT_L

JTAG_TBT_TDO

JTAG_TBT_TDIJTAG_ISP_TDI

JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

LPC_CLK33M_DPMUX_UC_R

PCIE_AP_D2R_P

PCIE_AP_D2R_N

LPC_CLK33M_DPMUX_UC_R

MAKE_BASE=TRUE

LPC_CLK33M_DPMUX_UC

PLT_RESET_L

MAKE_BASE=TRUE

SMC_LRESET_L

SSD_RESET_L

AP_RESET_L

TBT_PCIE_RESET_L

DPMUX_LRESET_L

CAM_PCIE_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

<SCH_NUM>

20 OF 119

20 OF 97

13 35 46 84

20 33 38 41 42 45 46 65 66 67 81 84 85 86

13 21 43 45 46 66 81 82 84 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51

52 55 66 67 68 69 82 83 84

86 96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

20 33 38 41 42 45 46 65 66 67 81 84 85 86

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

19 28 29 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83

84 86 96

11 20

69

IN IN

IN

OUT

IN

G

D

S

OUT

VER 3

D

SG

VER 3

D

SG

G

VER 5

SD

G

VER 5

S D

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1 3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

75mA max load @ 0.75V

S0

to

S3

to

60mW max power

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

S0

MEMVTT Clamp

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MEM S0 "PGOOD" for CPU

14 12 40 67 86

12 18 20 86

2

1

R2102

MF-LF

5%

CPUMEM:S0

100K

1/16W

402

21 60 85

2

1

R2110

CPUMEM:S0

5% 1/16W MF-LF

10K

402

2

1

R2115

CPUMEM:S0

402

MF-LF

1/16W

5%

100K

23 24 25 26

2

1

R2116

1K

MF-LF 402

1/16W

5%

CPUMEM:S0

66

2

1

R2105

402

MF-LF

5%

CPUMEM:S0

1/16W

10K

12 33 37 40 67 81 86

2

1

R2101

100K

402

1/16W MF-LF

CPUMEM:S0

5%

21 60 85

2

1

R2151

MF-LF

1/16W

100K

402

5%

CPUMEM:S0

2

1

C2151

402

CERM

20% 50V

NO STUFF

0.001UF

2

1

R2150

1/10W

603

MF-LF

5%

10

CPUMEM:S0

21

R2117

CPUMEM:S3

1/16W

5%

0

402

MF-LF

6

21

2

1

R2121

MF-LF

1%

1/16W

43.2K

402

2

1

R2120

402

27.4K

1/16W MF-LF

1%

4

3

5

Q2120

CRITICAL

DMB53D0UV

SOT-563

2

1

R2122

402

1/16W MF-LF

10K

5%

1

2

6

Q2120

DMB53D0UV

SOT-563

CRITICAL

6

12 89

2

1

C2120

0402

X5R-CERM

10%

0.047UF

10V

2

1

C2116

20%

402

CERM

10V

0.1UF

CPUMEM:S0

2

1

C2117

NO STUFF

10%

X5R

6.3V

201

0.047UF

1

2

6

Q2100

CRITICAL

SOT563

DMN5L06VK-7

CPUMEM:S0

1

2

6

Q2110

CRITICAL CPUMEM:S0

SOT563

DMN5L06VK-7

1

2

6

Q2115

SOT563

DMN5L06VK-7

CRITICAL

CPUMEM:S0

4

5

3

Q2115

SOT563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

4

5

3

Q2100

CPUMEM:S0

SOT563

DMN5L06VK-7

CRITICAL

4

5

3

Q2110

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT563

1

2

6

Q2105

SOT563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

4

5

3

Q2105

CPUMEM:S0

CRITICAL

SOT563

DMN5L06VK-7

1

2

6

Q2150

CRITICAL

SOT563

DMN5L06VK-7

CPUMEM:S0

4

5

3

Q2150

CRITICAL

CPUMEM:S0

DMN5L06VK-7

SOT563

SYNC_DATE=07/02/2014

SYNC_MASTER=CLEAN_MAXWELL

CPU Memory S3 Support

PP3V3_S3

MEMPWR_DIV

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PP3V3_S5

CPU_MEM_RESET_L

PPVTT_S0_DDR

PP5V_S3

MEM_RESET_L

CPU_MEM_RESET_L

MAKE_BASE=TRUE

MEMRESET_ISOL_LS5V_L

PLT_RESET_L

MEMVTT_EN

MEMVTT_EN_L

CPUVDDQ_EN

CPUVDDQ_EN_L

PM_SLP_S3_L

PM_SLP_S4_L

PP5V_S3

MEMVTT_EN

VTTCLAMP_L

VTTCLAMP_EN

ISOLATE_CPU_MEM_L

PP1V35_S3

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

21 OF 119

21 OF 97

13 20 43 45 46 66 81 82 84 86

12 14 15 17 18 19 31 32 33 61 64 66 67 82 84 85 86 96

27 60 84 86

21 36 60 66 67 84 86

22

21 36 60 66 67 84 86

45 60 66 84 86

6 8

10 66 67 84 96

IN

G

VER 5

S D

G

VER 5

S D

G

VER 5

S D

G

VER 5

S D

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Always used, regardless

VRef Dividers

CPU-Based Margining

Connected to 4 DRAMs.

NOTE: CPU has single output for VREFCA.

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

of margining option.

2

1

R2221

1/20W

1% MF

201

1K

2

1

R2241

1% 1/20W

201

MF

1K

2

1

R2222

1/20W

1%

201

MF

PLACE_NEAR=R2221.2:1mm

1K

21

R2220

MF

1%

1/20W

24.9

201

2

1

R2261

1/20W 201

MF

1%

1K

2

1

R2242

1/20W

1%

201

MF

PLACE_NEAR=R2241.2:1mm

1K

21

R2240

MF

1%

1/20W

24.9

201

2

1

R2262

PLACE_NEAR=R2261.2:1mm

1%

1/20W

201

MF

1K

21

R2260

24.9

MF

201

1%

1/20W

21

R2223

0201

1% MF

1/20W

2

1

C2220

X5R-CERM 0201

0.022UF

10%

6.3V

21

R2243

0201

MF

1%

2

1/20W

2

1

C2240

X5R-CERM

10%

0.022UF

6.3V 0201

21

R2263

1/20W

1% MF

2

0201

2

1

C2260

0201

10%

6.3V X5R-CERM

0.022UF

7

89

7

89

7

1

2

6

Q2220

SOT563

DMN5L06VK-7

CRITICAL

4

5

3

Q2220

DMN5L06VK-7

CRITICAL

SOT563

1

2

6

Q2260

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2260

DMN5L06VK-7

SOT563

CRITICAL

21

SYNC_DATE=08/11/2014

DDR3 VREF MARGINING

SYNC_MASTER=CLEAN_X425

MEMRESET_ISOL_LS5V_L

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFDQ_A_ISOL

MEM_VREFDQ_B_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_MEM_VREFDQ_B_ISOL

CPU_DIMMA_VREFDQ

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_MEM_VREFCA_ISOL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MEM_VREFCA_RC

MEM_VREFDQ_A_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

22 OF 97

22 OF 119

<SCH_NUM>

23 24 25 26 85 89 92

23 24 85 89 92

23 24 25 26 27 45 84 92

25 26 85 89

NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2

1

C2340

20% 10V

402

2.2UF

X5R-CERM

2

1

C2341

20% 10V

402

2.2UF

X5R-CERM

2

1

C2343

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2344

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2345

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2353

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2354

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2355

0201

CERM-X5R

6.3V

10%

0.1UF

2

1

C2363

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2364

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2365

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2373

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2374

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2375

6.3V CERM-X5R 0201

0.1UF

10%

1

2

R2300

MF

1/20W

1%

240

201

1

2

R2310

MF

240

1% 1/20W

201

1

2

R2320

MF

1/20W

1%

240

201

1

2

R2330

1%

240

1/20W MF 201

2

1

C2307

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2309

0.047UF

6.3V X5R 201

10%

2

1

C2308

0.047UF

6.3V X5R 201

10%

2

1

C2319

0.047UF

6.3V X5R 201

10%

2

1

C2318

0.047UF

6.3V X5R 201

10%

2

1

C2317

0.47UF

20%

4V

CERM-X5R-1

201

2

1

C2329

0.047UF

6.3V X5R 201

10%

2

1

C2328

0.047UF

6.3V X5R 201

10%

2

1

C2327

CERM-X5R-1

20%

4V

0.47UF

201

2

1

C2339

0.047UF

6.3V X5R 201

10%

2

1

C2338

0.047UF

6.3V X5R 201

10%

2

1

C2337

20%

4V

CERM-X5R-1

0.47UF

201

2

1

C2379

0.047UF

6.3V X5R 201

10%

2

1

C2378

0.047UF

6.3V X5R 201

10%

2

1

C2377

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2369

0.047UF

6.3V X5R 201

10%

2

1

C2368

0.047UF

6.3V X5R 201

10%

2

1

C2367

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2359

0.047UF

6.3V X5R 201

10%

2

1

C2358

0.047UF

6.3V X5R 201

10%

1

2

R2370

MF

1/20W

1%

240

201

1

2

R2360

240

1% 1/20W MF 201

2

1

C2357

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2349

0.047UF

6.3V X5R 201

10%

2

1

C2348

0.047UF

6.3V X5R 201

10%

2

1

C2347

CERM-X5R-1

4V

20%

0.47UF

201

1

2

R2350

MF

1/20W

1%

240

201

1

2

R2340

240

1% 1/20W MF 201

2

1

C2335

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2334

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2333

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2325

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2324

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2323

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2315

6.3V

0.1UF

10%

0201

CERM-X5R

2

1

C2314

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2313

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2305

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2304

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2303

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2301

20% 10V

402

2.2UF

X5R-CERM

2

1

C2300

402

10V

20%

2.2UF

X5R-CERM

2

1

C2311

X5R-CERM

2.2UF

402

10V

20%

2

1

C2351

X5R-CERM

2.2UF

402

10V

20%

2

1

C2310

2.2UF

20% 10V

402

X5R-CERM

2

1

C2350

X5R-CERM

2.2UF

402

10V

20%

2

1

C2321

X5R-CERM

2.2UF

402

10V

20%

2

1

C2361

2.2UF

X5R-CERM

402

10V

20%

2

1

C2320

X5R-CERM

2.2UF

20% 10V

402

2

1

C2360

20%

X5R-CERM

2.2UF

402

10V

2

1

C2331

X5R-CERM

2.2UF

402

10V

20%

2

1

C2330

X5R-CERM

2.2UF

20% 10V

402

2

1

C2371

2.2UF

X5R-CERM

402

10V

20%

2

1

C2370

2.2UF

10V

20%

402

X5R-CERM

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2300

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2310

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2320

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2330

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2340

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2350

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2360

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2370

OMIT_TABLE

DDR3-1333

FBGA

DDR3 SDRAM Bank A (1 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

MEM_A_ZQ<5>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA

MEM_A_DQ<6>

MEM_A_A<11>

MEM_A_DQS_N<5>

PP0V75_S3_MEM_VREFCA

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<50> MEM_A_DQ<51>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<7>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<62>

MEM_A_DQS_N<7>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<6>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<6>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<54>

MEM_A_DQS_N<6>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<46>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<5>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_A<2>

MEM_A_DQ<32>

MEM_A_CAS_L

MEM_A_DQ<37>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<4>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<38>

MEM_A_DQS_N<4>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<4>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<3>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CS_L<0>

MEM_A_DQS_P<3>

MEM_A_DQ<29>

MEM_A_DQ<25>

MEM_A_DQ<30>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_A<2>

MEM_A_A<3>

PP1V35_S3_MEM

MEM_A_A<2>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<2>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<20>

MEM_A_DQS_N<2>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<2>

MEM_A_DQ<19>

MEM_A_DQ<23>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQ<14>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_DQ<9>

MEM_A_A<0>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<1>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

PP0V75_S3_MEM_VREFCA

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<1>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_A<2>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_DQS_N<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<2>

MEM_A_DQ<0>

MEM_A_DQ<5> MEM_A_DQ<3> MEM_A_DQ<1>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_DQ<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3> MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<8> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<0>

MEM_A_RAS_L

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

<SCH_NUM>

23 OF 119

23 OF 97

22 23 24 85 89 92

22 23 24 25 26 85 89 92

22 23 24 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

22 23 24 85 89 92

22 23 24 25 26 85 89 92

7

24 92

7

23

24 27

92

7

23

24 27

92

7

24 92

22 23 24 25 26 85 89 92

22 23 24 85 89 92

7

24 92

7

24 92

22 23 24 85 89 92

7

23 27

92

7

23 27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 92

7

24 92

7

23 27

92

7

23 27

92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

23 24 27 92

7

23 24 27 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7 24 92

7

23 24 27 92

7

23 24

27 92

7

23 27 92

7

23

27

92

7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 27

92

22 23 24 85 89 92

7

23 27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 92

7

24 92

7

23 27

92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23 24

27 92

22 23 24 85 89 92

7

23 27 92

7

23

27

92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7 23 27

92

7

23 24 27

92

7

23 24 27 92

7

24 92

22 23 24 85 89 92

7

23

24 27 92

7

23 24 27 92

7

23 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 27

92

7

23 24

27 92

7

23 24

27 92

7 23 27

92

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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8 7 6 5 4 3

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2440

FBGA

OMIT_TABLE

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2450

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2460

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2470

OMIT_TABLE

FBGA

DDR3-1333

1

2

R2400

240

1% MF

1/20W 201

1

2

R2410

MF

1/20W

1%

240

201

1

2

R2420

1% MF

240

1/20W 201

1

2

R2430

MF

1/20W

1%

240

201

2

1

C2407

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2409

0.047UF

6.3V X5R 201

10%

2

1

C2408

0.047UF

6.3V X5R 201

10%

2

1

C2419

0.047UF

6.3V X5R 201

10%

2

1

C2418

0.047UF

6.3V X5R 201

10%

2

1

C2417

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2429

0.047UF

6.3V X5R 201

10%

2

1

C2428

0.047UF

6.3V X5R 201

10%

2

1

C2427

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2439

0.047UF

6.3V X5R 201

10%

2

1

C2438

0.047UF

6.3V X5R 201

10%

2

1

C2437

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2479

0.047UF

6.3V X5R 201

10%

2

1

C2478

0.047UF

6.3V X5R 201

10%

2

1

C2477

20%

4V

CERM-X5R-1

0.47UF

201

2

1

C2469

0.047UF

6.3V X5R 201

10%

2

1

C2468

0.047UF

6.3V X5R 201

10%

2

1

C2467

CERM-X5R-1

0.47UF

20%

4V

201

2

1

C2459

0.047UF

6.3V X5R 201

10%

2

1

C2458

0.047UF

6.3V X5R 201

10%

1

2

R2470

240

1% 1/20W MF 201

1

2

R2460

MF

1/20W

1%

240

201

2

1

C2457

20%

4V

0.47UF

CERM-X5R-1

201

2

1

C2449

0.047UF

6.3V X5R 201

10%

2

1

C2448

0.047UF

6.3V X5R 201

10%

2

1

C2447

20%

4V

CERM-X5R-1

0.47UF

201

1

2

R2450

240

1% 1/20W MF 201

1

2

R2440

MF

1/20W

1%

240

201

2

1

C2440

20%

402

2.2UF

X5R-CERM

10V

2

1

C2400

402

10V

20%

2.2UF

X5R-CERM

2

1

C2441

20% 10V

402

2.2UF

X5R-CERM

2

1

C2401

20% 10V

402

2.2UF

X5R-CERM

2

1

C2450

2.2UF

402

10V

20%

X5R-CERM

2

1

C2410

X5R-CERM

2.2UF

20% 10V

402

2

1

C2451

X5R-CERM

402

10V

20%

2.2UF

2

1

C2411

X5R-CERM

2.2UF

402

10V

20%

2

1

C2460

X5R-CERM

2.2UF

402

10V

20%

2

1

C2461

X5R-CERM

2.2UF

402

10V

20%

2

1

C2420

X5R-CERM

2.2UF

20% 10V

402

2

1

C2421

X5R-CERM

2.2UF

402

10V

20%

2

1

C2470

2.2UF

X5R-CERM

402

10V

20%

2

1

C2471

X5R-CERM

2.2UF

402

10V

20%

2

1

C2430

X5R-CERM

2.2UF

20% 10V

402

2

1

C2431

X5R-CERM

2.2UF

402

10V

20%

2

1

C2443

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2444

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2403

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2404

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2445

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2453

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2405

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2413

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2454

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2414

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2455

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2463

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2415

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2423

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2464

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2465

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2424

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2425

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2473

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2433

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2474

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2434

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2475

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2435

6.3V CERM-X5R 0201

0.1UF

10%

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2400

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2410

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2420

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2430

FBGA

DDR3-1333

OMIT_TABLE

DDR3 SDRAM Bank A (2 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MEM_A_A<10>

MEM_A_A<14>

PP0V75_S3_MEM_VREFCA

MEM_A_A<5>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<15>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<15>

MEM_A_DQ<61>

MEM_A_DQS_N<7>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_A<2>

MEM_A_DQ<43>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_DQS_N<5>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<14>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<6>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<53>

MEM_A_DQS_N<6>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_A<2>

MEM_A_CLK_N<1>

MEM_A_DQS_N<4>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_ODT<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<45>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<5>

MEM_A_DQ<44>

MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<12>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<4>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<11>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<25>

MEM_A_DQS_N<3>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<3>

MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_A<2>MEM_A_A<2>

MEM_A_A<6>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18> MEM_A_DQS_P<2>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4> MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_A_A<1>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<10>

MEM_A_RAS_L

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA

MEM_A_DQ<13>

PP1V35_S3_MEM

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_A<15>

MEM_A_DQS_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L

MEM_A_ZQ<9>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQS_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<9>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_A<15>

MEM_A_A<13>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<8>

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQ<1>

MEM_A_CKE<1>

MEM_A_DQS_P<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<41>

MEM_A_A<4>

MEM_A_A<1>

MEM_A_A<8> MEM_A_A<7>

MEM_A_DQ<46>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_ZQ<13>

PP1V35_S3_MEM

<SCH_NUM>

24 OF 119

24 OF 97

7

23 24

27 92

7

23 24 27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

22 23 24 85 89 92

7

24 27

92

7

24 27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27 92

7

23

24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 92

7

23 92

7

24 27

92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 24 27 92

7

23 92

7

23

24 27

92

7

23 24

27 92

7

23 24

27 92

7 23 92

7

24 27 92

7

24

27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24 27 92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

24 27 92

7

24 27 92

7

24

27

92

7

23 24 27 92

7

23 24

27 92

21 23 24

25 26

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 92

7

23 24 27 92

22 23 24 85 89 92

7 24 27 92

7

23 24

27 92

7

23 24

27 92

7

24 27

92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

24 27

92

7 23 92

7

23 92

7

23 24

27 92

7

23 24

27 92

7

23 24 27 92

7

24 27

92

22 23 24 85 89 92

7

24 27

92

7

23

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92 7

23 24

27 92

21 23 24 25 26

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

23 24 27 92

7

23

24 27

92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23 24 27 92

7

23 92

7

23 92

7

24 27

92

7

24 27

92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

7

23 24 27 92

7

23

24 27

92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27 92

7

23

24 27

92

22 23 24 25 26 27 45 84 92

22 23 24 25 26 85 89 92

7

23 24 27

92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23

24 27 92

7 24 27

92

22 23 24 85 89 92 22 23 24 85 89 92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

24 27

92

7

24 27

92

7

23 24 27 92

7

23 92

7

24 27 92

7

23 24 27 92

7

24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24 27

92

7

23 24 27 92

7

23

24 27

92

7

23 24 27 92

7

23 24 27 92

7

23 24

27 92

7

23 24

27 92

7

23

24 27 92

7

23 24 27 92

7

23

92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

7

23 24

27 92

7

23 24

27 92

22 23 24 85 89 92

7 24 27

92

7

23 24

27 92

7

24 27

92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

22 23 24 25 26 85 89 92

7

23 24

27 92

7

23 24

27 92 7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7

23 24

27 92

7 23 92

7

23 24

27 92

22 23 24 85 89 92 22 23 24 85 89 92

7

23 24 27 92

7

23 24

27 92

7

23 24 27 92

22 23 24 25 26 27 45 84 92

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2550

FBGA

DDR3-1333

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2560

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2570

OMIT_TABLE

FBGA

DDR3-1333

1

2

R2500

240

1% 1/20W MF 201

1

2

R2510

MF

1/20W

1%

240

201

1

2

R2520

1%

240

1/20W MF 201

1

2

R2530

1/20W

1%

240

MF 201

2

1

C2507

0.47UF

4V

20%

CERM-X5R-1

201

2

1

C2509

0.047UF

6.3V X5R 201

10%

2

1

C2508

0.047UF

6.3V X5R 201

10%

2

1

C2519

0.047UF

6.3V X5R 201

10%

2

1

C2518

0.047UF

6.3V X5R 201

10%

2

1

C2517

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2529

0.047UF

6.3V X5R 201

10%

2

1

C2528

0.047UF

6.3V X5R 201

10%

2

1

C2527

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2539

0.047UF

6.3V X5R 201

10%

2

1

C2538

0.047UF

6.3V X5R 201

10%

2

1

C2537

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2579

0.047UF

6.3V X5R 201

10%

2

1

C2578

0.047UF

6.3V X5R 201

10%

2

1

C2577

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2569

0.047UF

6.3V X5R 201

10%

2

1

C2568

0.047UF

6.3V X5R 201

10%

2

1

C2567

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2559

0.047UF

6.3V X5R 201

10%

2

1

C2558

0.047UF

6.3V X5R 201

10%

1

2

R2570

MF

1/20W

1%

240

201

1

2

R2560

1% 1/20W

240

MF 201

2

1

C2557

0.47UF

4V

20%

CERM-X5R-1

201

2

1

C2549

0.047UF

6.3V X5R 201

10%

2

1

C2548

0.047UF

6.3V X5R 201

10%

2

1

C2547

20%

4V

0.47UF

CERM-X5R-1

201

1

2

R2550

MF

1/20W

1%

240

201

1

2

R2540

240

1% 1/20W MF 201

2

1

C2540

20% 10V

402

2.2UF

X5R-CERM

2

1

C2500

402

10V

20%

X5R-CERM

2.2UF

2

1

C2541

20% 10V

402

2.2UF

X5R-CERM

2

1

C2550

X5R-CERM

2.2UF

402

10V

20%

2

1

C2501

20% 10V

402

2.2UF

X5R-CERM

2

1

C2510

X5R-CERM

2.2UF

20% 10V

402

2

1

C2551

X5R-CERM

2.2UF

402

10V

20%

2

1

C2511

X5R-CERM

2.2UF

402

10V

20%

2

1

C2560

X5R-CERM

2.2UF

402

10V

20%

2

1

C2561

X5R-CERM

2.2UF

402

10V

20%

2

1

C2520

X5R-CERM

2.2UF

20% 10V

402

2

1

C2521

X5R-CERM

2.2UF

402

10V

20%

2

1

C2570

X5R-CERM

2.2UF

402

10V

20%

2

1

C2571

2.2UF

X5R-CERM

402

10V

20%

2

1

C2530

2.2UF

10V

X5R-CERM

20%

402

2

1

C2531

X5R-CERM

2.2UF

402

10V

20%

2

1

C2543

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2544

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2503

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2504

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2545

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2553

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2505

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2513

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2554

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2514

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2555

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2563

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2515

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2523

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2564

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2565

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2524

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2525

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2573

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2533

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2534

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2574

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2575

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C2535

6.3V CERM-X5R 0201

0.1UF

10%

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2500

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2510

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2520

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2530

OMIT_TABLE

FBGA

DDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2540

OMIT_TABLE

FBGA

DDR3-1333

DDR3 SDRAM Bank B (1 OF 2)

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<54>

MEM_B_DQS_N<6>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

PP0V75_S3_MEM_VREFCA

MEM_B_A<5>

MEM_B_DQ<32>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<38>

MEM_B_DQS_N<4>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<22>

MEM_B_DQS_N<2>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<2>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_A<2>

MEM_B_DQ<11>

MEM_B_DQ<3>

MEM_B_A<12>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<1>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_A<2>

PP1V35_S3_MEM

MEM_B_DQ<2> MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<6>

MEM_B_A<2>

PP1V35_S3_MEM

<SCH_NUM>

25 OF 119

25 OF 97

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

22 25 26 85 89

7

25 27

92

7

25 27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

21 23 24 25 26

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

26 92

7

25 27

92

7

25 27

92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

25 26 27 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

22 23 24 25 26 85 89 92

7

25 26

27 92

7

26 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25 26

27 92

7

25 26

27 92

7

25 27

92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 27 45 84 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 27

92

7

25 27 92

7

25 27 92

7

25 26 27 92

7

26 92

22 25 26 85 89

7

25 27

92

7

25 27

92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

21 23 24 25 26

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

26 92

7

25 27

92

7

25 27

92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 25 26 85 89

7

25

26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25

26 27

92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

7

26 92

7

25

26 27

92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25

26 27 92

7

25 26 27 92

7

25 27 92

7

25 26 27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26 27

92

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45 84 92

7

25 26 27 92

7

25 26

27 92

7

25 26 27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25

26 27 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

22 23 24 25 26 27 45 84 92

22 25 26 85 89

7

25 27 92

7

25

27

92

7

25 26

27 92

7

25 27

92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 85 89 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92

7

25 26

27 92 7

25 26

27 92

7

25 26

27 92

22 23 24 25 26 27 45 84 92

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2650

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2660

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2670

FBGA

DDR3-1333

OMIT_TABLE

1

2

R2600

201

MF

1%

240

1/20W

1

2

R2610

201

240

1% 1/20W MF

1

2

R2620

201

MF

1/20W

1%

240

1

2

R2630

201

240

1% 1/20W MF

2

1

C2607

201

CERM-X5R-1

20%

4V

0.47UF

2

1

C2609

10%

201

X5R

6.3V

0.047UF

2

1

C2608

10%

201

X5R

6.3V

0.047UF

2

1

C2619

10%

201

X5R

6.3V

0.047UF

2

1

C2618

10%

201

X5R

6.3V

0.047UF

2

1

C2617

201

CERM-X5R-1

20%

4V

0.47UF

2

1

C2629

10%

201

X5R

6.3V

0.047UF

2

1

C2628

10%

201

X5R

6.3V

0.047UF

2

1

C2627

201

0.47UF

20%

4V

CERM-X5R-1

2

1

C2639

10%

201

X5R

6.3V

0.047UF

2

1

C2638

10%

201

X5R

6.3V

0.047UF

2

1

C2637

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2679

10%

201

X5R

6.3V

0.047UF

2

1

C2678

10%

201

X5R

6.3V

0.047UF

2

1

C2677

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2669

10%

201

X5R

6.3V

0.047UF

2

1

C2668

10%

201

X5R

6.3V

0.047UF

2

1

C2667

201

0.47UF

20%

CERM-X5R-1

4V

2

1

C2659

10%

201

X5R

6.3V

0.047UF

2

1

C2658

10%

201

X5R

6.3V

0.047UF

1

2

R2670

201

240

1% 1/20W MF

1

2

R2660

201

MF

1/20W

1%

240

2

1

C2657

201

20%

4V

CERM-X5R-1

0.47UF

2

1

C2649

10%

201

X5R

6.3V

0.047UF

2

1

C2648

10%

201

X5R

6.3V

0.047UF

2

1

C2647

201

0.47UF

20%

4V

CERM-X5R-1

1

2

R2650

201

240

1% 1/20W MF

1

2

R2640

201

MF

1/20W

1%

240

2

1

C2640

20% 10V

402

2.2UF

X5R-CERM

2

1

C2600

10V

20%

2.2UF

X5R-CERM

402

2

1

C2641

20% 10V

402

2.2UF

X5R-CERM

2

1

C2650

X5R-CERM

2.2UF

402

10V

20%

2

1

C2601

20% 10V

402

2.2UF

X5R-CERM

2

1

C2610

X5R-CERM

2.2UF

20% 10V

402

2

1

C2651

X5R-CERM

2.2UF

402

10V

20%

2

1

C2611

X5R-CERM

2.2UF

402

10V

20%

2

1

C2660

X5R-CERM

2.2UF

402

10V

20%

2

1

C2661

X5R-CERM

2.2UF

402

10V

20%

2

1

C2620

X5R-CERM

2.2UF

20% 10V

402

2

1

C2621

X5R-CERM

2.2UF

402

10V

20%

2

1

C2670

X5R-CERM

2.2UF

402

10V

20%

2

1

C2671

X5R-CERM

2.2UF

402

10V

20%

2

1

C2630

2.2UF

10V

X5R-CERM

20%

402

2

1

C2631

X5R-CERM

2.2UF

402

10V

20%

2

1

C2643

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2644

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2603

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2604

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2645

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2653

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2605

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2613

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2654

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2614

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2655

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2663

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2615

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2623

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2664

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2665

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2624

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2625

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2673

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2633

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2634

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2674

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2675

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C2635

10%

0.1UF

0201

CERM-X5R

6.3V

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2600

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9

F3N2L2

J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2610

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2620

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9D2B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3C2B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2630

DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9D9A9F3N2L2J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2G3G9D8A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11

N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3 G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2640

DDR3-1333

FBGA

OMIT_TABLE

DDR3 SDRAM Bank B (2 OF 2)

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

PP1V35_S3_MEM

MEM_B_A<2>

MEM_B_DQ<1>

MEM_B_DQ<5>

MEM_B_DQ<0> MEM_B_DQ<7>

MEM_B_DQS_P<0>

MEM_B_CKE<1>

MEM_B_DQS_N<0>

MEM_B_DQ<4>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<0>

PP1V35_S3_MEM

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_ZQ<8>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_A<11>

MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<11> MEM_B_DQ<8> MEM_B_DQ<15>

MEM_B_DQ<10> MEM_B_DQS_P<1>

MEM_B_CS_L<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

PP0V75_S3_MEM_VREFCA

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<9>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<9>

MEM_B_DQ<12>

MEM_B_DQS_N<1>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<20> MEM_B_DQ<18> MEM_B_DQ<16>

MEM_B_DQ<17> MEM_B_DQ<22>

MEM_B_DQ<23> MEM_B_DQS_P<2>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<2>

MEM_B_DQ<21>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<6> MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<10>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

PP1V35_S3_MEM

MEM_B_DQ<19>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_DQ<25> MEM_B_DQ<27> MEM_B_DQ<29> MEM_B_DQ<26> MEM_B_DQ<24> MEM_B_DQ<31>

MEM_B_DQ<30> MEM_B_DQS_P<3>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<11>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_WE_L

MEM_B_A<2>

MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<38>

MEM_B_DQ<36> MEM_B_DQS_P<4>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<4>

MEM_B_DQ<37>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<8> MEM_B_A<7> MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<12>

MEM_B_RAS_L

MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_P<1>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<2>

MEM_B_DQ<40> MEM_B_DQ<43> MEM_B_DQ<42>

MEM_B_DQ<46>

MEM_B_DQ<44> MEM_B_DQS_P<5>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8> MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<13>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

PP1V35_S3_MEM

MEM_B_DQ<41>

MEM_B_A<5>

MEM_RESET_L

MEM_B_DQ<49> MEM_B_DQ<48>

MEM_B_DQ<50> MEM_B_DQ<55> MEM_B_DQ<54>

MEM_B_DQ<52> MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<53>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP0V75_S3_MEM_VREFCA

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<14>

MEM_B_RAS_L

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CS_L<1>

MEM_B_DQ<47>

MEM_B_A<2> MEM_B_A<2>

MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<63> MEM_B_DQ<62>

MEM_B_DQ<60> MEM_B_DQS_P<7>

MEM_B_CS_L<1> MEM_B_CKE<1>

MEM_B_DQS_N<7>

MEM_B_DQ<61>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<4> MEM_B_A<3>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<0>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<7> MEM_B_A<9>

MEM_RESET_L

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_CAS_L

MEM_B_ODT<1>

MEM_B_WE_L

MEM_B_ZQ<15>

MEM_B_RAS_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CKE<1>

MEM_B_A<1>

MEM_B_A<6>

MEM_B_A<3>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_BA<2>

MEM_B_DQ<51>

PP1V35_S3_MEM

MEM_B_DQ<2>

PP0V75_S3_MEM_VREFCA

<SCH_NUM>

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IN

IN IN

IN

IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FOR DESENSE IMPROVEMENT

C2701,C2721 FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM

Place Source Cterm at neckdown at first DRAM

MEM Clock Termination

Place RC end termination after last DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

PLACE ONE AT EACH DDR3L MEMORY MODULE.

7

25 26 92

81

RP2730

1/32W

4X0201

5%

36

81

RP2703

5%361/32W

4X0201

81

RP2702

1/32W

4X0201

5%

36

72

RP2701

4X0201

1/32W

36

5%

54

RP2701

4X0201

1/32W

5%

36

72

RP2702

4X0201

1/32W

36

5%

72

RP2706

1/32W

4X0201

36

5%

2

1

C2704

CERM-X5R-1

4V

20%

0.47UF

201

2

1

C2702

CERM-X5R-1

20% 4V

0.47UF

201

2

1

C2700

CERM-X5R-1

0.47UF

20% 4V

201

2

1

C2723

20% 4V CERM-X5R-1

0.47UF

201

72

RP2728

5%

4X0201

1/32W

36

2

1

C2727

20% 4V

0.47UF

CERM-X5R-1 201

2

1

C2725

20% 4V CERM-X5R-1

0.47UF

201

2

1

C2707

20% CERM-X5R-1

0.47UF

4V 201

2

1

C2703

201

20%

0.47UF

CERM-X5R-1

4V

2

1

C2705

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2765

PLACE_NEAR=U2600.F8:3.2mm

25V

3.3PF

C0G

0201

+/-0.25PF

21

R2766

30

1/20W

MF

5%

201

2

1

C2755

PLACE_NEAR=U2470.F8:3.2mm

C0G

0201

25V

+/-0.25PF

3.3PF

72

RP2730

1/32W

36

4X0201

5%

21

R2765

30

1/20W

MF

5%

201

21

R2756

5% MF

1/20W

30

201

21

R2755

5%

30

MF

201

1/20W

21

C2766

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2756

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2751

6.3V

CERM-X5R

0201

0.1UF

10%

21

C2761

6.3V

CERM-X5R

0201

0.1UF

10%

21

R2750

30

1/20W

MF

5%

201

72

RP2724

36

4X0201

1/32W

5%

21

R2751

5% MF

1/20W

30

201

2

1

C2750

PLACE_NEAR=U2370.F8:3.2mm

25V

3.3PF

C0G

0201

+/-0.25PF

21

R2760

30

MF

1/20W

5%

201

21

R2761

30

MF

5%

201

1/20W

2

1

C2760

25V

3.3PF

C0G

0201

+/-0.25PF

PLACE_NEAR=U2500.F8:3.2mm

7

23 92

7

23 92

7

25 92

7

25 92

7

24 92

2

1

C2730

20% 4V CERM-X5R-1

0.47UF

201

7

24 92

7

26 92

7

26 92

81

RP2705

4X0201

1/32W

5%

36

7

24 92

72

RP2705

4X0201

5%361/32W

7

23 24 92

72

RP2725

36

4X0201

1/32W

5%

7

25 26 92

63

RP2725

1/32W

5%

4X0201

36

2

1

C2728

0.47UF

CERM-X5R-1

4V

20%

201

7

25 26 92

81

RP2725

5%

1/32W

4X0201

36

7

25 26 92

63

RP2705

4X0201

36

5%

1/32W

7

23 24 92

54

RP2705

36

5%

1/32W

4X0201

7

23 24 92

54

RP2725

4X0201

36

5%

1/32W

7

25 26 92

2

1

C2726

20% 4V CERM-X5R-1

0.47UF

201

2

1

C2701

12PF

25V

5% 0201

NP0-C0G

2

1

C2721

5% NP0-C0G 0201 25V

12PF

2

1

C2770

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2740

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2771

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2741

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2772

5%

12PF

NP0-C0G

25V

CRITICAL

0201

2

1

C2742

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2773

5%

CRITICAL

25V

12PF

NP0-C0G

0201

2

1

C2743

5%

12PF

0201

NP0-C0G

25V

CRITICAL

81

RP2720

5%

1/32W

4X0201

36

2

1

C2774

5%

12PF

25V

CRITICAL

NP0-C0G

0201

2

1

C2775

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2744

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2745

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2776

5%

0201

NP0-C0G

25V

CRITICAL

12PF

2

1

C2777

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2746

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2747

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

26 92

7

25 26 92

7

25 26 92

7

25 26 92

2

1

C2787

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2797

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2796

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2786

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2785

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2795

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

25 92

2

1

C2784

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2794

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2783

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2793

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2782

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2792

5%

12PF

NP0-C0G

25V

CRITICAL

0201

2

1

C2781

5%

12PF

0201

CRITICAL

25V

NP0-C0G

2

1

C2791

5%

0201

NP0-C0G

25V

CRITICAL

12PF

2

1

C2790

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2

1

C2780

5%

12PF

0201

NP0-C0G

25V

CRITICAL

7

25 92

7

25 26 92

7

25 26 92

7

25 26 92

7

26 92

7

26 92

7

25 26 92

7

25 26 92

7

25 26 92

7

25 92

7

25 26 92

7

25 26 92

7

25 26 92

7

25 26 92

7

23 24 92

7

23 24 92

7

23 92

7

23 92

7

23 24 92

7

25 26 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

54

RP2724

1/32W

4X0201

5%

36

54

RP2730

4X0201

5%361/32W

63

RP2720

1/32W

36

4X0201

5%

72

RP2720

4X0201

1/32W

36

5%

72

RP2722

36

1/32W

4X0201

5%

7

25 26 92

54

RP2722

4X0201

1/32W

36

5%

63

RP2726

5%361/32W

4X0201

63

RP2728

4X0201

1/32W

36

5%

54

RP2728

5%361/32W

4X0201

72

RP2726

36

5%

1/32W

4X0201

63

RP2724

1/32W

4X0201

36

5%

63

RP2722

36

5%

4X0201

1/32W

54

RP2720

5%361/32W

4X0201

81

RP2728

36

5%

1/32W

4X0201

81

RP2724

4X0201

5%

1/32W

36

7

25 26 92

81

RP2722

5%

36

4X0201

1/32W

54

RP2726

36

4X0201

1/32W

5%

2

1

C2724

20% 4V

0.47UF

CERM-X5R-1 201

2

1

C2722

CERM-X5R-1

0.47UF

4V

20%

201

2

1

C2720

CERM-X5R-1

0.47UF

20% 4V

201

63

RP2706

5%

1/32W

4X0201

36

81

RP2701

5%

1/32W

36

4X0201

63

RP2701

4X0201

1/32W

5%

36

54

RP2704

1/32W

5%

36

4X0201

72

RP2704

1/32W

5%

4X0201

36

7

25 26 92

54

RP2707

4X0201

1/32W

5%

36

54

RP2702

36

5%

4X0201

1/32W

63

RP2703

1/32W

4X0201

5%

36

81

RP2707

1/32W

5%

36

4X0201

2

1

C2710

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2708

20%

0.47UF

CERM-X5R-1

4V 201

2

1

C2706

0.47UF

CERM-X5R-1

4V

20%

201

72

RP2707

4X0201

5%

1/32W

36

7

23 24 92

7

23 24 92

63

RP2730

1/32W

4X0201

5%

36

7

23 24 92

7

24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 92

7

23 24 92

7

23 24 92

7

23 24 92

81

RP2726

4X0201

1/32W

36

5%

7

24 92

7

23 24 92

54

RP2703

36

1/32W

5%

4X0201

81

RP2704

4X0201

36

1/32W

5%

54

RP2706

36

1/32W

5%

4X0201

63

RP2702

4X0201

5%

1/32W

36

63

RP2704

4X0201

1/32W

5%

36

72

RP2703

5%

1/32W

4X0201

36

63

RP2707

4X0201

1/32W

5%

36

81

RP2706

4X0201

36

1/32W

5%

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

DDR3 Termination

PP1V35_S3_MEM

PPVTT_S0_DDR

MEM_A_BA<2>

PP1V35_S3_MEM

MEM_B_CLK0_TERM_R

MEM_A_CLK1_TERM_R

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK0_TERM_R

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2> MEM_A_A<1>

MEM_A_A<11> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<12>

MEM_A_CS_L<1> MEM_A_A<15>

MEM_A_ODT<1> MEM_A_A<10>

MEM_A_RAS_L MEM_A_CKE<0>

MEM_A_A<4>

MEM_A_A<5> MEM_A_BA<1>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_BA<0>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_BA<1> MEM_B_A<0>

MEM_B_CKE<1> MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_A<15>

MEM_B_A<9> MEM_B_A<14>

MEM_B_A<7> MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_A_CAS_L MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_B_A<12>

MEM_B_CS_L<1>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_WE_L

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_RAS_L MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_A<10>

MEM_A_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CLK1_TERM_R

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_CLK_P<1>

MEM_B_BA<2>

MEM_A_ODT<0>

PPVTT_S0_DDR

MEM_A_A<3>

MEM_A_A<6>

<SCH_NUM>

27 OF 119

27 OF 97

22 23 24 25 26 27 45 84 92

21 27 60 84 86

22 23 24 25 26 27 45 84 92

21 27 60 84 86

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

IN

IN IN

IN

OUT

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1 PETN_1

PETP_2

RSENSE

PETN_2

PETP_3 PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1 PERN_1

PERP_2 PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK TDO TEST_EN TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI TMS

PERN_0

PERP_3

IN IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(TBT_SPI_CLK) (TBT_SPI_CS_L)

(TBT_SPI_MISO)

SNK0 AC Coupling

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

SNK1 AC Coupling

(TBT_SPI_MOSI)

Used for straps in host mode

depends on the code in the flash.

Security strap setting is XORed with

If strap != bit then security is enabled?

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15 9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14 11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

DEBUG: For monitoring current/voltage

bit in the flash, so the active-level

2

1

R2890

MF

1/20W

201

3.3K

5%

82

2

1

R2825

100

5% MF

1/20W 201

31

31 93

31 87 93

31 93

31 87 93

32 93

32

32 93

2

1

R2830

MF

201

100K

5%

1/20W

2

1

R2831

MF

1/20W

201

100K

5%

31 93

2

1

R2893

201

MF

5%

3.3K

1/20W

21

C2829

0201

0.1UF

X5R-CERM

16V10%

83 89 97

76 89 97

21

C2828

0201

0.1UF

X5R-CERM

10% 16V

21

C2827

0201

0.1UF

X5R-CERM

16V10%

21

C2826

0201

0.1UF

X5R-CERM

10% 16V

21

C2825

0201

0.1UF

X5R-CERM

16V10%

21

C2824

0201

X5R-CERM

0.1UF

10% 16V

21

C2823

0201

0.1UF

X5R-CERM

16V10%

21

C2822

0201

0.1UF

X5R-CERM

10% 16V

2

1

R2855

1%

1K

201

1/20W MF

21

C2821

0201

0.1UF

X5R-CERM

16V10%

21

C2820

0201

0.1UF

X5R-CERM

16V10%

21

C2830

0201

0.1UF

X5R-CERM

16V10%

21

C2831

0201

0.1UF

X5R-CERM

16V10%

21

C2832

0201

0.1UF

X5R-CERM

16V10%

21

C2833

0201

0.1UF

X5R-CERM

16V10%

21

C2834

0201

X5R-CERM

0.1UF

16V10%

21

C2835

0201

0.1UF

X5R-CERM

16V10%

21

C2836

0201

0.1UF

X5R-CERM

16V10%

21

C2837

0201

0.1UF

X5R-CERM

16V10%

21

C2838

0201

0.1UF

X5R-CERM

16V10%

21

C2839

0201

X5R-CERM

0.1UF

16V10%

76 89 97

2

1

C2890

BYPASS=U2890::2mm

1UF

10%

6.3V CERM

402

83 89 97

31

32

20

32 93

32

20

31 93

31

28 30 31

31

28 31

28 30 32

32

28 32

28 29

20 40 41 42

11

19 90

21

R2895

201

MF

1/20W

1%

806

2

1

R2896

1/20W MF 201

1K

5%

2

1

R2899

MF

5%

1/20W

10K

201

NO STUFF

11 91

29

2

1

R2815

NOSTUFF

NONE NONE 0201

NONE

OMIT

2

1

R2888

5%

10K

201

1/20W

MF

2

1

R2887

10K

201

MF

1/20W

5%

2

1

R2886

NO STUFF

5%

201

1/20W MF

10K

2

1

R2885

NO STUFF

5%

10K

201

1/20W

MF

2

1

R2880

100K

MF

1/20W

201

5%

20

28 82

14 20

2

1

R2883

5%

201

1/20W MF

100K

3

8

9

7

4

25

1

6

U2890

4MBIT

USON

W25X40CLXIG

OMIT_TABLE

CRITICAL

28 30

28 31 32

2

1

R2861

5%

10K

201

1/20W MF

2

1

R2863

MF

1/20W 201

10K

5%

2

1

R2867

MF

1/20W 201

10K

5%

NO STUFF

2

1

R2862

MF

1/20W 201

10K

5%

2

1

R2881

MF

1/20W

201

5%

100K

2

1

R2829

10K

201

1/20W

MF

5%

2

1

R2884

100K

MF

1/20W

201

5%

2

1

R2882

MF

1/20W 201

5%

100K

28 85

2

1

R2878

100K

MF

1/20W

201

5%

2

1

R2879

5%

201

1/20W MF

100K

2

1

R2832

5%

201

1/20W

MF

100K

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

L8

AD1

U20

AB21 AD21

W20

R4

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5 P7

N6

A22 B23

A20 B21

M1

D3

W24 U24

W22 U22

R24 N24

R22 N22

K3 K1

N8 J6

M3

A18 B19

A16 B17

K5

P1

L24 J24

L22 J22

G24 E24

G22 E22

L4 L2

W18 W16

AC24

AD23

M7

V7

T7

Y1

Y7

H5

L6

U2

F1

V1

AD3

AB3

W6

T3

T1

F3P3

R2N2

R8

Y3

AA2

T5 U8

AC2

J4 J2

A14 B15

A12 B13

A10 B11

A8 B9

U4

H3 H1

E6 D5

E8 D7

E10

D9

E12 D11

AB5

G4 G2

E14 D13

E16 D15

E18 D17

E20 D19

U2800

CRITICAL

OMIT_TABLE

FCBGA

FALCON RIDGE

31 82 32 82

21

C2801

X5R-CERM

10%

16V

0201

0.1UF

21

C2800

16V

0201

10%

0.1UF

X5R-CERM

21

C2802

0.1UF

0201

10%

16V X5R-CERM

21

C2803

0.1UF

0201

10%

16V X5R-CERM

2

1

R2892

201

5% MF

1/20W

3.3K

21

C2804

0.1UF

10%

X5R-CERM

0201

16V

21

C2805

0201

10%

16V X5R-CERM

0.1UF

21

C2806

0201

10%

16V X5R-CERM

0.1UF

21

C2807

0201

10%

16V X5R-CERM

0.1UF

21

C2840

16V

X5R-CERM

0.1UF

0201

10%

21

C2841

16V10%

X5R-CERM

0.1UF

0201

21

C2842

16V10%

X5R-CERM

0.1UF

0201

2

1

R2891

MF

1/20W 201

3.3K

5%

21

C2843

16V10%

X5R-CERM

0.1UF

0201

21

C2845

16V10%

X5R-CERM

0.1UF

0201

21

C2844

16V10%

0.1UF

X5R-CERM

0201

21

C2846

10% 16V

0.1UF

X5R-CERM

0201

21

C2847

10% 16V

0.1UF

0201

X5R-CERM

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

5

85 89

SYNC_DATE=01/14/2013

SYNC_MASTER=T29_RR

Thunderbolt Host (1 of 2)

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_N<0>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

PP3V3_TBTLC

DP_TBTSRC_HPD

PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

PP3V3_S4_TBT

TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L TBTROM_HOLD_L

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_C_P<3>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<3>

DP_TBTSNK0_ML_C_P<0>

PP3V3_TBTLC

SYSCLK_CLK25M_TBT

TBT_A_HV_EN

TBT_B_DP_PWRDN

PP3V3_TBTLC

PCIE_TBT_R2D_P<3>

JTAG_TBT_TMS

JTAG_TBT_TDI

TBT_PCIE_RESET_L

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

TBT_A_R2D_C_P<0>

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

JTAG_TBT_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP TBT_MONOBSN

TBT_THERMDP

TBT_SPI_MOSI

TP_TBT_MONDC0 TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

DP_TBTPB_AUXCH_C_P

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_P<1>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

TBTDP_AUXIO_EN TBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RC

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_BATLOW_L

TBT_GPIO7

HDMITBTMUX_SEL_TBT

SMC_PME_S4_DARK_L

TBT_PWR_EN

NC_DP_TBTSRC_ML_CP<0>

NC_DP_TBTSRC_ML_CP<1>

NC_DP_TBTSRC_ML_CP<3>

NC_DP_TBTSRC_ML_CP<2>

DP_TBTSRC_HPD

TBT_GPIO2

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT_R

TBT_DFT_STRAP_1 TBT_ROM_SECURITY_XOR TBT_DFT_STRAP_3

TP_TBT_PCIE_RESET0_L

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_RBIAS

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0>

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_ML_CN<1>

NC_DP_TBTSRC_ML_CN<2>

NC_DP_TBTSRC_ML_CN<3>

TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<1>

TBT_B_R2D_C_N<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_R2D_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_B_CONFIG1_BUF

TBT_B_D2R_P<0>

28 OF 97

28 OF 119

<SCH_NUM>

19 20 28 29 84

28

28 29 30 45 84

28 29

28 85

28 82

28 31 32

28 29 30 45 84

28 30

28 30 32

28 31

28 89 97

19 20 28 29 84

28 30 31

28 32

19 20 28 29 84

87

89

28 89 97

93

48 96

93

87 89

87

89

87 89

87

89

87

89

87

28

90

87

89

87

89

87

89

87

89

87

89

87 89

28 89 97

87

28 89 97

87 89

NC

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

S G

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VER 3

D

S G

G

VER 5

S D

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Isolated to reduce noise from SVR

Pull-up (S0) on PCH page

SVR input to FR - 1100 mA EDP

EDP: 1.25 A

2.4 W (Single-Port)

3.1 W (Dual-Port)

700 mA EDP

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

TBT "POC" Power-up Reset

Delay = 4.04ms nominal

1200 mA EDP

8 mOhm Typ

@ 1.05V

R(on)

Type

Part

Push-pull output

U2950

Max Current = 4A (85C)

11.5 mOhm Max

100 mA EDP

J45 Implementation: 4 X 10uF

25 mA EDP

1900 mA EDP

Load Switch

TPS22920

1.05V TBT "CIO" Switch

Internal switch not functional on FR.

X425 Implementation: 3 X 20uF

POC input to FR - 150 mA EDP

2

1

C2906

6.3V X5R

1.0UF

20%

0201-1

2

1

C2911

6.3V

1.0UF

20%

0201-1

X5R

2

1

C2910

0201-1

1.0UF

20%

6.3V X5R

21

L2920

680NH-30%-3.6A-35MOHM

CRITICAL

SM

2

1

C2922

0402-2

X5R-CERM

4V

20%

20UF

K

A

D2920

CRITICAL

SOD-323

NSR1020MW2T1G

2

1

R2945

MF 201

100K

5% 1/20W

C1

B1

A1

C2

B2

A2

D2

D1

U2940

CRITICAL

CSP

TPS22920

2

1

C2940

0201-1

X5R

20%

6.3V

1.0UF

2

1

C2981

0201-1

6.3V X5R

1.0UF

20%

2

1

C2980

0201-1

6.3V X5R

1.0UF

20%

2

1

C2970

20% X5R

0201-1

6.3V

1.0UF

28

2

1

C2960

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2961

0201-1

6.3V X5R

1.0UF

20%

2

1

C2953

CERM-X5R

0402-1

10UF

20%

6.3V

2

1

C2952

CERM-X5R

20%

10UF

0402-1

6.3V

2

1

C2951

20%

10UF

CERM-X5R

6.3V

0402-1

2

1

C2950

10UF

20%

0402-1

CERM-X5R

6.3V

2

1

XW2960

PLACE_NEAR=C2953.1:1mm

SM

28

2

1

C2995

X7R

16V

0201

10%

330PF

2

1

R2991

24.9K

1%

201

MF

1/20W

2

1

C2990

402

0.1UF

10% X5R

25V

14

2

1

R2995

1/20W

100K

201

MF

5%

19 30 40 41

2

1

R2990

201

MF

1/20W

100K

5%

2

1

3

Q2995

DMN32D2LFB4

DFN1006H4-3

2

1

C2991

0402

0.001UF

50V

10%

X7R-CERM

12

6

4

3

2

1

5

U2990

CRITICAL

USON

TPS3895ADRY

2

1

R2992

5% MF

201

100K

1/20W

1

2

6

Q2945

DMN5L06VK-7

SOT563

4

5

3

Q2945

SOT563

DMN5L06VK-7

2

1

C2923

4V

0402-2

X5R-CERM

20%

20UF

NOSTUFF

Y9

AC12

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V9

V23

V21

AC10

V13

U16

U12

T9

T23

T21

T17

T13

R20

R16

AB17

R12

P9

P23

P21

P13

N20

N16

N12

M9

M23

AB11

M21

M13

L20

L12

K23

K21

K13

J20

J16

J14AA8

H23

H21

G8

G6

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C2

C18

C16

C14

C12

C10

AA14

B7

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

A24

A2

W10

R18

N18

L18

H7

H17

H15

H13

Y5

W4

V5

N4

H11

E2

D1

K17

K15

J18

H9

H19

G18

G16

W14

G14

W12

V17

V15

U18

T19

P19

M19

L16

K7

K19

G12

G10

R10

P15

P11

N14

N10

M11

L10

K11

V11

U14

U10

T15

T11

R14

J12

J10

V19

P17

M17

M15

L14

K9

J8

B3

A6

A4

B5

U2800

CRITICAL

FALCON RIDGE

OMIT_TABLE

FCBGA

2

1

C2907

12PF

5% 0201

CRITICAL

25V

NP0-C0G

2

1

C2908

25V 0201

NP0-C0G

+/-0.1PF

3.0PF

CRITICAL

2

1

C2913

CRITICAL

3.0PF

+/-0.1PF NP0-C0G

0201

25V

2

1

C2912

CRITICAL

NP0-C0G 25V

12PF

0201

5%

2

1

C2934

3.0PF

+/-0.1PF 25V

0201

CRITICAL

NP0-C0G

2

1

C2933

5% 0201

CRITICAL

12PF

25V

NP0-C0G

2

1

C2954

CRITICAL

NP0-C0G 25V

12PF

0201

5%

2

1

C2955

3.0PF

+/-0.1PF

0201

NP0-C0G

CRITICAL

25V

2

1

C2903

6.3V

1.0UF

0201-1

20% X5R

2

1

C2920

20%

4V

X5R-CERM

0402-2

20UF

2

1

C2921

X5R-CERM

20UF

0402-2

4V

20%

2

1

C2904

0201-1

1.0UF

X5R

6.3V

20%

2

1

C2905

0201-1

6.3V X5R

1.0UF

20%

2

1

C2900

X5R

0201-1

6.3V

1.0UF

20%

2

1

C2901

0201-1

6.3V

20% X5R

1.0UF

2

1

C2902

0201-1

6.3V

1.0UF

X5R

20%

2

1

C2932

1.0UF

0201-1

6.3V X5R

20%

2

1

C2931

0201-1

6.3V X5R

20%

1.0UF

2

1

C2930

0201-1

6.3V X5R

1.0UF

20%

SYNC_DATE=10/30/2014

SYNC_MASTER=CLEAN_X425

Thunderbolt Host (2 of 2)

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3_TBTRDV

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15 MM

PP3V3_TBTLC

PP3V3_S0

TBT_PWR_REQ_L

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

PP1V05_TBT

TBT_PWR_ON_POC_RST_L TBTPOCRST_CT

TBTPOCRST_SENSE

PP3V3_S4_TBT

SMC_DELAYED_PWRGD

TBTPOCRST_MR_L

TBT_POC_RESET_L

PP3V3_TBTLC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

PP1V05_TBT

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.50 MM

MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.38 MM

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_TBTCIO

VOLTAGE=1.05V

PP3V3_S0

PP3V3_S4_TBT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_S4_TBT_F

MIN_NECK_WIDTH=0.20 MM

<SCH_NUM>

29 OF 119

29 OF 97

19 20 28 29 84

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

29

28 29 30 45 84

19 20 28 29 84

29

11 12 13 14 15 17 19 20 29 34 43 44 45 46 47 48 49 51 52

55 66 67 68 69 82 83 84 86

96

28 29 30 45 84

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

IN

OUT

D

SYM_VER_3

S G

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

SG

IN

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

C3080 USING 0603 PAKAGE IS FOR DFM TO PROTECT Q3080 (CSP)

8-13V Input Changes required for 2S.

Vds(max): -30V

Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

Thunderbolt 15V Boost Regulator

add property on another page.

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

NOTE: Change R3097 to XW3095 at PVT

Max Vgs: 10V

Vout = 1.6V * (1 + Ra / Rb)

Freq = 480KHz

NOTE: MIRROR C3096 and C3098

BATLOW# Isolation

(NONE)

- =PP15V_TBT_REG (15V Boost Output)

Pull-up on RR page

Voltage not specified here,

BOM options provided by this page:

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

<R2>

UVLO = 4.55V (falling), 4.95 (rising)

GND inside package,

<Rb>

Vgs(th): -1.4V

Vgs(max): +/-12V

SI8409DB:

<R1>

- =PPVIN_SW_TBTBST (8-13V Boost Input)

no XW necessary.

Max Current = 2A?

SGND shorted to

Vout = 15.47V

<Ra>

2

1

R3081

402

MF-LF

5%

1/16W

330K

2

1

R3080

402

MF-LF

5%

1/16W

470K

2

1

C3080

603-1

X7R

0.1UF

10% 50V

2

1

R3092

402

73.2K

1/16W MF-LF

1%

2

1

R3087

402

5%

330K

MF-LF

1/16W

2

1

R3094

402

1/16W

1%

26.7K

MF-LF

2

1

C3094

10%

0.33UF

X6S-CERM 0402

6.3V

2

1

R3088

402

5% 1/16W MF-LF

330K

19 29 40 41

2

1

C3089

402

NO STUFF

5% 50V CERM

100PF

2

1

R3096

402

1/16W

15.8K

MF-LF

1%

2

1

C3095

20%

33UF-0.06OHM

POLY-TANT

25V CASE-D3L

2

1

C3096

20%

X5R-CERM

PLACE_SIDE=BOTTOM

10UF

0603

25V

2

1

C3097

NO STUFF

X7R-CERM 1206

10UF

25V

10%

2

1

C3087

CERM 0402

68PF

50V

5%

2

1

C3085

20%

2.2UF

0402

CER-X6S

10V

4

1

32

Q3080

BGA

CRITICAL

SI8409DB

2

1

R3093

402

1%

49.9K

1/16W MF-LF

2

1

R3091

402

1/16W MF-LF

200K

1%

2

1

C3090

20%

X5R-CERM

10UF

25V

0603

2

1

C3091

20%

X5R-CERM

0603

25V

10UF

21

L3095

CRITICAL

3.3UH-6.5A

PIMB063T-SM

2

1

C3088

CERM

10PF

0402

50V

5%

27

30

34

382120

9

8

32

37

24234

3

6

33

36

35

10

2

1

28

1716151413

12

31

25

U3090

CRITICAL

LT3957

QFN

2

1

R3095

402

137K

1/16W MF-LF

1%

2

1

R3089

1/20W

MF

5%

0

0201

2

1

C3099

0402

50V

10% X7R-CERM

0.001UF

2

1

C3093

0.0033UF

50V

10% X7R-CERM

0402

2

1

C3092

20%

2.2UF

0402

CER-X6S

10V

2

1

C3086

20%

2.2UF

0402

CER-X6S

10V

3

2

1

D3095

CRITICAL

PWRDI5

PDS540XF

28 32

28 30

2

1

3

Q3000

DFN1006H4-3

DMN32D2LFB4

12 40 42

2

1

C3098

20%

X5R-CERM

PLACE_SIDE=TOP

0603

25V

10UF

21

R3097

402

5%

10

MF-LF

1/16W

4

5

3

Q3088

SOT563

DMN5L06VK-7

1

2

6

Q3088

SOT563

DMN5L06VK-7

1

2

6

Q3005

DMN5L06VK-7

SOT563

28 31

4

5

3

Q3005

DMN5L06VK-7

SOT563

Thunderbolt Mobile Support

SYNC_DATE=06/24/2014

SYNC_MASTER=CLEAN_X305

TBTBST_PWREN_DIV_L

TBTBST_PWREN_L

TBT_B_HV_ENTBT_A_HV_EN

TBTBST_SNS2

PM_BATLOW_L

MAKE_BASE=TRUE

TBT_BATLOW_L

TBTBST_SS

TBT_BATLOW_L

PP3V3_S4_TBT

TBTBST_SNS1

TBTBST_FBX

PP15V_TBT

SMC_DELAYED_PWRGD

TBTBST_SHDN_DIV

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

TBTBST_BOOST

MIN_NECK_WIDTH=0.25 mm

TBTBST_VSNS

TBTBST_RT

TBTBST_VC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

TBTBST_VC_RC

TBTBST_EN_UVLO

TBTBST_INTVCC

30 OF 97

30 OF 119

<SCH_NUM>

28 30

28 29 45 84

31 32 84

84

44 47 56 57 63 65 84 86

Apple X425G Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual