Apple X304 Schematic

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

87 6 5 4 21

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

X304 MLB SCHEMATIC - DVT

Schematic / PCB #’s

051-1573

8.0.0

1 OF 82

1 OF 120

Fri Dec 19 12:14:48 2014

ENGINEERING RELEASED

dvt1

2014-12-19

8

0003549590

SCHEM,MLB,X304

54

42

JACK_J52

12/15/2013

Power Sensors: High Side

53

41

GKOO_J52

12/06/2013

SMBus Connections

52

40

JACK_J52

11/07/2013

SMC Project Support

51

39

JACK_J52

10/24/2013

SMC Shared Support

50

38

JACK_J52

11/07/2013

SMC

49

37

JACK_J52

01/31/2014

Keyboard & Trackpad (2 of 2)

48

36

JACK_J52

01/28/2014

Keyboard & Trackpad (1 of 2)

46

35

J41

10/23/2012

External A USB3 Connector

40

34

J41

12/21/2012

Camera (2 of 2)

39

33

J45

01/24/2013

Camera (1 of 2)

37

32

YHARTANTO_J44

12/18/2012

SSD Connector

35

31

J41

11/01/2012

Wireless Support

34

30

J14

10/23/2012

DDC Crossbar

33

29

T29_RR

10/26/2012

Thunderbolt Connector B

32

28

T29_RR

10/26/2012

Thunderbolt Connector A

30

27

T29_RR

11/19/2012

Thunderbolt Mobile Support

29

26

T29_RR

12/17/2012

Thunderbolt Host (2 of 2)

28

25

T29_RR

01/19/2013

Thunderbolt Host (1 of 2)

27

24

J41_MLB

02/06/2013

LPDDR3 DRAM Termination

26

23

J41_MLB

02/06/2013

LPDDR3 DRAM Channel B (32-63)

25

22

J41_MLB

02/06/2013

LPDDR3 DRAM Channel B (00-31)

24

21

J41_MLB

02/06/2013

LPDDR3 DRAM Channel A (32-63)

23

20

J41_MLB

02/06/2013

LPDDR3 DRAM Channel A (00-31)

22

19

YHARTANTO_J44

01/02/2013

LPDDR3 VREF Margining

20

18

J41

10/23/2012

Project Chipset Support

19

17

J41

01/30/2013

Chipset Support

18

16

WFERRY_J43

12/21/2012

CPU/PCH Merged XDP

16

15

J41

01/19/2013

PCH GPIO/MISC/LPIO

15

14

J41

10/23/2012

PCH PCIe,USB,LPC,SPI,SMBus

14

13

J41

02/21/2013

PCH PM/PCI/GFX

13

12

J41

12/17/2012

PCH Audio/JTAG/SATA/CLK

12

11

J41

10/23/2012

PCH Decoupling

10

J41

10/23/2012

CPU Decoupling

9

J41

10/23/2012

CPU & PCH Grounds

8

J41

10/23/2012

CPU & PCH Power

7

J41

10/23/2012

CPU LPDDR3 Interfaces

6

J41

10/23/2012

CPU Misc,JTAG,CFG,RSVD

5

J41

10/23/2012

CPU GFX,NCTF,RSVD

4

LDUNN_J44

01/13/2013

PD Parts

3

J14

09/04/2012

BOM Configuration

2

SHART_J44

11/27/2012

BOM Configuration

82

120

J14

10/23/2012

Reference

81

119

YHARTANTO_J44

01/13/2013

PCIe Constraints

80

118

YHARTANTO_J44

01/04/2013

Project Specific Constraints

79

117

YHARTANTO_J44

01/02/2013

SMC Constraints

78

116

YHARTANTO_J44

01/09/2013

Camera Constraints

77

115

GKOO_J52

12/06/2013

TBT,DP,HDMI Constraints

76

114

YHARTANTO_J44

01/02/2013

Memory Constraints

75

113

YHARTANTO_J44

01/08/2013

PCH Constraints

74

112

YHARTANTO_J44

01/07/2013

USB Constraints

73

111

YHARTANTO_J44

01/13/2013

CPU Constraints

72

110

YHARTANTO_J44

12/14/2012

PCB Rule Definitions

71

104

GKOO_J52

12/06/2013

Functional & ICT Test

70

103

AHARTMAN_J52

10/29/2013

Memory Bit & Byte Swizzle

69

102

SHART_J44

11/19/2012

Signal Aliases

68

100

SHART_J44

01/14/2013

Power Aliases

67

97

SRAMAN_J44

01/29/2013

Display Mux: HDMI vs DP

66

95

GKOO_J52

05/01/2014

RIO Connector

65

83

GKOO_J52

05/04/2014

eDP Display Connector

64

81

AHARTMAN_J52

11/06/2013

Power Control

63

80

J41

10/23/2012

Power FETs

62

79

AHARTMAN_J52

11/06/2013

X239 Power Supply

61

78

AHARTMAN_J52

11/06/2013

Misc Power Supplies

60

77

SHART_J44

11/20/2012

LCD & KBD Backlight Driver

59

76

AHARTMAN_J52

10/29/2013

1.05V Power Supply

58

75

J14

10/23/2012

5V & 3.3V Power Supply

57

74

J41_MLB

05/21/2013

LPDDR3 Supply

56

73

J41

10/23/2012

CPU VR12.6 VCC Power Stage

55

72

J41

10/23/2012

CPU VR12.6 VCC Regulator IC

54

71

AHARTMAN_J52

11/06/2013

PBus Supply & Battery Charger

53

70

YHARTANTO_J44

01/09/2013

DC-In & Battery Connectors

52

66

JCURCIO_J44

05/13/2013

Audio: Jack Translators

51

65

JCURCIO_J44

07/25/2013

Audio: Jack Support

50

64

DIRK_J44

01/09/2013

Audio: Speaker Amps

49

63

JCURCIO_J44

07/25/2013

Audio: Codec,Digital

48

62

JCURCIO_J44

05/13/2013

Audio: Codec,Analog

47

61

YHARTANTO_J44

01/09/2013

SPI Debug Connector

46

60

J41

10/23/2012

Fan

45

58

YHARTANTO_J44

01/07/2013

Thermal Sensors

44

56

JACK_J52

10/26/2013

Power Sensors: Extended

820-4924

1

PCBF,MLB,X304

PCB

CRITICAL

051-1573

SCHEM,MLB,X304

SCH1

CRITICAL

43

55

JACK_J52

12/06/2013

Power Sensors: Load Side

1

YHARTANTO_J44

12/21/2012

Table of Contents

Contents

(.csa)

Page DateSync

(.csa)

Page Sync Date

Contents

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

COMMENT

PART#

TABLE_STRATEGIC_HEAD

STRATEGIC VALUE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Main DRAM Parts

Variable BOM Groups

SMC

BOM Groups

Module Parts

Sub-BOMs

Main DRAM SPD Straps

Development/Base BOMs

EFI ROM

TBT

S2 DRAM Parts

Strategic Silicon

DVT

Programmables (All Builds)

U0500

337S00109

1

CPU_BDW23:3.1G

CRITICAL

CPU,BW,SR26E,PRQ,F0-B2,3.1,28W,1.1,1168

CRITICAL

1

998-7866

CPU_SOCKET

INTERPOSER,BGA1168P, SINGLE SIDE

U0500

ALTERNATE,ENGISNS,XDP_CONN,S0PGOOD_ISL

X304_DEVEL:DVT

SYS MEMORY HYNIX

07333S0784

SYNC_DATE=11/27/2012

BOM Configuration

SYNC_MASTER=SHART_J44

U2300,U2400,U2500,U2600

8G_HYNIX_1600

CRITICAL

4

333S0785

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 8Gb,LPDDR3-1600,178P FBGA

CRITICAL

4G_HYNIX_1600

U2300,U2400,U2500,U2600

4

333S0787

U2300,U2400,U2500,U2600

CRITICAL

IC,SDRAM,25nm 8Gb,LPDDR3-1600,178P FBGA

4

333S0793

4G_ELPIDA_1600

X304_PROGPARTS

SMC_PROG:PROTO0,BOOTROM_PROG,TBTROM_PROG

X304_COMMON3

XDP,SAMCONN,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO,TPADRC:NO

EFI ROM

01

341S00235

01

S2 MEMORY

333S0700

343S0511 01

PCIE DELAY IC

DDC CROSSBAR

353S00095

01

353S3931

TBT PWR MUX

01

GREEN CLOCK

01359S0197

KEYBOARD I2C EXPANDER

02311S0597

T29,EPROM,FALCON RIDGE (V27.1) EVT2,X304

TBTROM_PROG

341S00192

1

CRITICAL

U2890

CRITICAL341S3982

U5000

SMC_PROG:PROTO0

IC,SMC-B1,EXT(V2.21A5) PROTO 0,X304

1

X304_COMMON4

SMCBOARDID:16

685-1314

BASE

1

CRITICAL

X304 MLB COMMON BOM

BASE_BOM

341S00235

U6100

CRITICAL

1

BOOTROM_PROG

EFI ROM,MLB (V0145) DVT,X304

X304_COMMON2

EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,VCORE_FETS

X304_COMMON1

TBTHV:P15V,SKIP_5V3V3:AUDIBLE,PANEL:NEW,SSD_CLKREQ:BI

ALTERNATE,COMMON,X304_COMMON1,X304_COMMON2,X304_COMMON3,X304_COMMON4,X304_PROGPARTS

X304_COMMON

353S2888

AUDIO AMPS

01

AUDIO AMPS

353S2958

01

BAT CHARGER

353S2929

01

T29 ROM

341S00192

SMC

01341S3982

1

CRITICAL

DEVEL

DEVEL_BOM

X304 MLB DEVEL BOM

985-1319

16G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_16G_HYNIX_1600

RAM_16G_HYNIX_1866

16G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

VCOREFETS

VCORE FET,VSHY,X304

CRITICAL685-1318

1

VCORE_FETS

RAM_8G_HYNIX_1600

8G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_HYNIX_1866

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

4

333S0786

CRITICAL

8G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_8G_HYNIX_1866

16G_ELPIDA_1600

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

4

333S0789

CRITICAL

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

16G_HYNIX_1866

CRITICAL

4

333S0784

4G_HYNIX_1866

IC,SDRAM,29nm 8Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

4

333S0788

CRITICAL

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0791

8G_ELPIDA_1600

8G_ELPIDA_1866

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0792

4G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1600

4G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1866

16G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_16G_ELPIDA_1600

16G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_16G_ELPIDA_1866

8G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_8G_SAMSUNG_1600

8G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_8G_ELPIDA_1600

8G_SAMSUNG_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_8G_SAMSUNG_1866

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600

4G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1866

8G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_8G_ELPIDA_1866

4G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_4G_SAMSUNG_1600

8G_SAMSUNG_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

4

333S00004

4G_SAMSUNG_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 8Gb,LPDDR3-1866,178P FBGA

4

333S00002

U2300,U2400,U2500,U2600

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

16G_HYNIX_1600

CRITICAL

4

333S0783

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0790

16G_ELPIDA_1866

4G_ELPIDA_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,25nm 8Gb,LPDDR3-1866,178P FBGA

4

333S0794

8G_SAMSUNG_1600

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

4

333S00003

4G_SAMSUNG_1600

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 8Gb,LPDDR3-1600,178P FBGA

4

333S00001

U4000

IC,SDRAM,4GBIT.DDR3L-1600,HUMA,96B BGA

1

333S0700

4G_SAMSUNG_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_4G_SAMSUNG_1866

TPAD ELEC FUSE

07

353S00200

333S00004

07

SYS MEMORY SAMSUNG

CPU

337S00068

08

SYS MEMORY MICRON

07333S0792

333S0790 07

SYS MEMORY MICRON

SYS MEMORY HYNIX

07333S0786

FALCON RIDGE

338S1247 01

TBT MUX

01353S3812

TBT MUX

01353S3814

DDC CROSSBAR

01353S3328

338S1264S201

01353S3054

USB POWER/SAFETY

353S4080

AUDIO

01

337S00069

CPU

08

337S00071

CPU

08

337S00070

08

CPU

01

S2 MEMORY

333S0704

343S0649

SMC RESET CHIP

01

343S0666 01

SAK, HDMI SELECT

01

BEN

353S4160

01

VR12.6 CONTROLLER

353S00036

ALTERNATE,ENGISNS,XDP_CONN,DBGLED

X304_DEVEL:ENG

ALTERNATE

X304_DEVEL:PVT

LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS,TPADISNS

ENGISNS

1

CRITICAL

CPU_BDW23:2.7G

U0500

337S00107

CPU,BW,SR26K,PRQ,F0-B2,2.7,28W,1.05,1168

U0500

CPU,BW,SR26H,PRQ,F0-B2,2.9,28W,1.1,1168

337S00108

CRITICAL1CPU_BDW23:2.9G

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

CRITICAL

VCORE_FET:VSHY

2

376S1194

Q7310,Q7320

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

U2800

CRITICAL

1

338S1247

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

CRITICAL

VCORE_FET:VSHY

376S1193

2

Q7311,Q7321

338S1264

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

CRITICAL

1

U3900

MOSFET,N-CH,30V,52A,5.9MO,3.3X3.3 DFN8

CRITICAL

Q7310,Q7320

2

376S00036

VCORE_FET:ONSMI

MOSFET,N-CH,30V,64A,3.5MO,3.3X3.3 DFN8

VCORE_FET:ONSMI

2

376S00037

Q7311,Q7321

CRITICAL

dvt1

051-1573

8.0.0

2 OF 120

2 OF 82

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

BOM Variants

Alternate Parts

740S00003

ALL

AEM alt to Tyco

740S0135

639-00035

PCBA,MLB,NO CPU,X304

BASE_BOM,DEVEL_BOM,RAM_8G_HYNIX_1866

VCORE FET,VSHY,X304

685-1318

VCORE_FET:VSHY

VCORE FET,ONSMI,X304 VCORE_FET:ONSMI

685-00022

376S0761

376S00014

Toshiba alt to Vishay

ALL

ALL353S00231

353S3987

NXP alt to TI

ALL131S00041

Murata alt to Taiyo Yuden

131S00040

ALL

TFT alt to Cyntec

107S00011

107S00015

107S00032

107S00031

TFT alt to Cyntec

ALL

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_ELPIDA_1866

MLB,BDW2+3,3.1GHz,8GB-EP-1866,X304

639-00784

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_SAMSUNG_1866

639-00781

MLB,BDW2+3,2.9GHz,8GB-SM-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_ELPIDA_1866

639-00780

MLB,BDW2+3,2.9GHz,16GB-EP-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_SAMSUNG_1866

MLB,BDW2+3,2.7GHz,8GB-SM-1866,X304

639-00776

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_ELPIDA_1866

MLB,BDW2+3,2.7GHz,16GB-EP-1866,X304

639-00775

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_ELPIDA_1866

MLB,BDW2+3,2.7GHz,8GB-EP-1866,X304

639-00774

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_HYNIX_1866

MLB,BDW2+3,2.7GHz,16GB-HY-1866,X304

639-00773

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_HYNIX_1866

MLB,BDW2+3,2.7GHz,8GB-HY-1866,X304

639-00772

X304_DEVEL:ENG

DEV,MLB,X304

985-1319

X304_COMMON

685-1314

COMMON,MLB,X304

353S00095

353S3328

ALL

Pericom alt to TI

138S0706

ALL

138S0739

Samsung alt to Murata

ALL

376S00074

Toshiba alt for Diodes Dual

376S0855

ALL

128S0329128S0311 NEC alt to Sanyo

107S00030

107S00029

TFT alt to Cyntec

ALL

353S00133

ALL

353S2741 Onsemi alt to TI

107S0226

107S00024

ALL

Yageo alt to Cyntec

372S0186 372S0185

ALL

NXP alt to Diodes

353S00135

ALL

Onsemi alt to Fairchild

353S2220

371S0749

ALL

371S00017

Diodes alt to Onsemi

371S00019

Rohm alt to Rohm371S0463

ALL

Diodes alt to NXP

311S00015

311S0450

ALL

ALLANY

353S00107

353S3239

Onsemi alt to Intersil

311S00013

ALL

311S0508

Diodes alt to NXP

311S00008

311S0271

ALL

Diodes alt to NXP

311S00014

311S0515

ALL

Diodes alt to NXP

ALL

353S2220

353S00034

Pericom alt to Fairchild

ALL

128S0436

Kemet alt to Sanyo

128S0392

155S0897

ALL

155S0914

Panasonic alt to TDK

On Semi alt to Infineon

ALL

377S0155 377S0184

ALL

Elpida alt to Hynix for S2 Camera DDR3 Memory

333S0700333S0704

Onsemi alt to Vishay for CPU Core Mosfets

685-1318

685-00022

ALL

371S0713

ALL

ST Micro alt to Diodes

371S0558

371S00018

Rohm alt to Rohm371S0619

ALL

376S1053

Diodes alt to Fairchild

376S0604

Panasonic alt to Sanyo

128S0445 128S0392

ALL

197S0479 197S0478 Epson alt to NDK

ALL

127S0164

Rohm alt to Vishay

ALL

127S0162

ALL

377S00011

377S0184

Infineon alt to Infineon

128S0397 128S0325

ALL

Kemet alt to Sanyo

138S1101

Samsung alt to Murata for LCD BKL caps

138S0738

ALL

155S0513155S0660

Murata alt to TDK

ALL

Murata alt to TDK

ALL

155S0694 155S0387

Murata, TDK, Samsung, Taiyo Yuden alt to Murata, TDK

138S0578

ALL

138S0614

ALL

353S4070 353S4069

Pericom alt to TI DP Mux U9750

NXP alt to TI DP Mux U9750

ALL

353S4068 353S4069

138S0843

ALL

138S0674

Samsung alt to Murata (BKLT)

ALL

107S0250

TFT alt to Cyntec

107S0248

NDK alt to TXC

ALL

197S0542 197S0544

Cyntec alt to TFT

107S0254

ALL

107S0241

353S3452

ALL

353S1286

Maxim alt to Microchip

ALL

138S0725

Samsung alt to Murata

138S0724

ALL

Cyntec alt to Vishay

152S1645152S0461

ALL

Epson alt to NDK197S0480197S0481

ALL

Diodes alt to On Semi

376S0820376S1080

311S0426

ALL

Diodes alt to NXP

311S00007

128S0284

ALL

128S0386

Kemet alt to Sanyo

128S0220

ALL

128S0398

Kemet alt to Sanyo

311S0541

ONsemi alt to Toshiba

311S0649

ALL

138S0811138S0846

Samsung alt to Murata (BKLT)

128S0364

ALL

Sanyo 2nd Factory alt

128S0264

376S0855

NXP Alt for Diodes Dual

ALL

376S1129

376S1128376S1089

ALL

NXP Alt for Diodes Single

ALL

197S0545 Epson alt to TXC197S0544

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_SAMSUNG_1866

MLB,BDW2+3,3.1GHz,8GB-SM-1866,X304

639-00786

BOM Configuration

SYNC_DATE=09/04/2012

SYNC_MASTER=J14

TI alt to NXP

ALL

353S3812353S3814

MLB,BDW2+3,2.9GHz,8GB-HY-1866,X304

639-00777

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_HYNIX_1866

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_HYNIX_1866

MLB,BDW2+3,2.9GHz,16GB-HY-1866,X304

639-00778

MLB,BDW2+3,2.9GHz,8GB-EP-1866,X304

639-00779

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_ELPIDA_1866

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_HYNIX_1866

639-00782

MLB,BDW2+3,3.1GHz,8GB-HY-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_HYNIX_1866

639-00783

MLB,BDW2+3,3.1GHz,16GB-HY-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_ELPIDA_1866

639-00785

MLB,BDW2+3,3.1GHz,16GB-EP-1866,X304

BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_8G_HYNIX_1866

639-00036

PCBA,MLB,CPU SOCKET,X304

dvt1

051-1573

8.0.0

3 OF 120

3 OF 82

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IPD FLEX BRACKET BOSSES (860-00166)

RIO FLEX BRACKET BOSSES (860-00166)

SH0435 & SH0436 removed.

Mounting Holes & Slots

Memory Shield CAN (806-00037)

(998-3975)

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK

Shield Cans

USB can Ground slot

(998-5879)

Upper TBT can Ground slot

Lower TBT can Ground slot

(862-0118)

(998-3975)

(998-1195)

USB can Ground slot

USB Cage

Rubber Mount Standoffs (860-1448)

TBT Cage

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD

(998-5879)

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK

(862-0118)

THERMAL MODULE STANDOFF (860-00165)

FAN STANDOFF (860-00183)SSD STANDOFF (860-00164)

POGO PINS (870-00607)

2.9OD1.2ID-1.35H-SM

SM

POGO-2.3OD-5.5H-X304

5.0OD2.0H

3.5OD1.85ID-2.0H

4.5OD1.85ID-1.78H-SM4.5OD1.85ID-1.78H-SM

4.5OD1.85ID-1.78H-SM 4.5OD1.85ID-1.78H-SM

POGO-2.3OD-5.5H-X304

SM

2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM

SM

SHLD-FENCE-MLB-DRAM-X304

3.5OD1.85ID-2.0H

SM

SHIELD-FENCE-MLB-T29-X304

OMIT

4P5R2P3-3P5B

SM

SHLD-J44-MLB

STDOFF-4.5ID1.73H-SM

OMIT

6.19X4.60-SNOWMAN

OMIT

6.19X4.60-SNOWMAN

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.5-1.4x0.8

TH-NSP

2.9OD1.2ID-1.35H-SM

SYNC_MASTER=LDUNN_J44

BOM_COST_GROUP=PD PARTS

SYNC_DATE=01/13/2013

PD Parts

SH0432

1

SH0433

1

ZT0411

1

SH0451

1

SH0441

1

ZT0413

1

ZT0414

1

TH0405

1

TH0404

1

TH0403

1

TH0400

1

SH0460

1

2

SH0462

1

2

SH0464

1

2

SH0466

1

2

SH0461

1

2

SH0465

1

2

SH0463

1

2

SH0467

1

2

SH0440

1

SH0443

1

SH0421

1

SH0420

1

SH0426

1

SH0427

1

SH0469

1

2

SH0468

1

2

SH0452

1

101112131415161718

192202122232425262728

293303132333435363738

39440

4142434445464748495505152535455565758

5966061626364

789

SH0471

1

SH0450

1

dvt1

051-1573

8.0.0

4 OF 120

4 OF 82

OUT

BI

DDI

EDP

SYM 1 OF 19

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

SPARE

SYM 18 OF 19

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

TP

NC NC

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.

NO_TEST NO_TEST

Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

if necessary)

(MUXed with HDMI

TBT Sink 1

TBT Sink 0

69

65 77

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

TP-P6

1/20W

1%

201

MF

24.9

25 77

69

BOM_COST_GROUP=CPU

CPU GFX,NCTF,RSVD

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

MCP_DC_B2

MCP_DC_A60

MCP_DC_A4

MCP_DC_A62 MCP_DC_AV1 MCP_DC_AW1

MCP_DC_AW63

MCP_DC_AY60

DP_TBTSNK0_ML_C_N<1>

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

=DP_TBTSNK1_ML_C_P<3>

=DP_TBTSNK1_ML_C_N<3>

=DP_TBTSNK1_ML_C_P<2>

=DP_TBTSNK1_ML_C_N<2>

=DP_TBTSNK1_ML_C_P<1>

=DP_TBTSNK1_ML_C_N<1>

=DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

=DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

PPVCOMP_S0_CPU

TP_EDP_DISP_UTIL

MCP_EDP_RCOMP

TRUE

MCP_DC_C1_C2

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_A61_B61

TRUE

MCP_DC_AW2_AY2

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_A61_B61

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW2_AY2

TP0531

1

TP0500

1

TP0510

1

TP0501

1

TP0511

1

TP0520

1

TP0521

1

TP0530

1

R0530

1

2

U0500

C54

B58

B55

A57

C55

C58

A55

B57

C51

C53

C49

A53

C50

B54

B50

B53

A45 B45

A43

D20

C45

A47

C47

A49

B46

B47

C46

B49

U0500

A3 A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

AY2

AY3 AY60 AY61 AY62

B2

B3 B61 B62 B63

C1

C2

U0500

AL1 AM11 AP7

AT2

AU10 AU15

AU44 AV44

AW14 AY14

D15

F22 H22 J21

N23 R23 T23 U10

5 OF 82

5 OF 120

8.0.0

051-1573

dvt1

8

73

5

BI

NC NC

NC

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1 SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

RESERVED

SYM 19 OF 19

VSS VSS

RSVD

CFG_RCOMP

RSVD

RSVD RSVD

TD_IREF

CFG0 CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17 CFG19

RSVD RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

RSVD_B43

BI

OUT

NC

BI

OUT

IN

OUT

NC

NC NC NC NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD)

and are only for debug access

These can be placed close to J1800

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

(IPU)

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

HSW_PRE_ES2

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

NOSTUFF

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

38 39 55 73

1/20W

5%

201

MF

62

1/20W

5%

201

MF

56

39 73

38 73

1/20W

5%

201

MF

10K

PLACE_NEAR=U0500.C61:12.7mm

16 73

16

16 73

1/20W

1%

201

MF

100

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

1%

201

MF

121

PLACE_NEAR=U0500.AV60:12.7mm

1/20W

1%

201

MF

200

PLACE_NEAR=U0500.AU60:12.7mm

70

17

1/20W

1%

201

MF

49.9

1/20W

1%

201

MF

49.9

1/20W

1%

201

MF

8.25K

1/20W

5%

201

MF

1K

EDP

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU Misc,JTAG,CFG,RSVD

CPU_PROCHOT_L

=PP1V05_S0_CPU_VCCST

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<10> CPU_CFG<9>

CPU_CFG<4>

XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<0>

XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5>

CPU_PECI

CPU_PWRGD

CPU_PROCHOT_R_L

CPU_SM_RCOMP<0>

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<1>

=MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

XDP_CPU_PRDY_L

XDP_BPM_L<6> XDP_BPM_L<7>

CPU_OPI_RCOMP

TP_MCP_RSVD_C62

TP_MCP_RSVD_C63

TP_MCP_RSVD_AU63

TP_MCP_RSVD_AV63

CPU_CFG<19>

CPU_CFG<17>

CPU_CFG<16> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_CFG<11>

CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10>

CPU_CFG<6>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<5>

CPU_CFG<1>

CPU_CFG<0>

PCH_TD_IREF

CPU_CFG_RCOMP

TP_MCP_RSVD_L60

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

CPU_CFG<4>

XDP_BPM_L<1>

CPU_CATERR_L

R0610

1

2

R0611

12

R0620

1

2

R0652

1

2

R0651

1

2

R0650

1

2

R0680

1

2

R0690

1

2

R0685

1

2

R0634

1

2

R0640

1

2

R0639

1

2

R0638

1

2

R0631

1

2

R0630

1

2

U0500

J60 H60 H61 H62 K59 H63 K60 J61

K61

N62

J62 K62

D61

E60

F63 F62

E61 E59

K63

C61

AV15

AV61

AU60 AV60 AU61

U0500

AC60 AC62

V60 U60 T63 T62 T61 T60

AA62

AA61

U63

U62

AC63 AA63 AA60

Y62 Y61 Y60 V62 V61

V63

AY15

A5

AV62

B43

D1

D58

E1

H18

J20

N60

P20 R20

A51

AU63

AV63

B51

C62

C63

L60

W23 Y22

B12

N21

P22

6 OF 82

6 OF 120

8.0.0

051-1573

dvt1

8

15 16 17 55 68

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

73

BI

OUT

BI

OUT

BI

SYM 3 OF 19

MEMORY CHANNEL A

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55 SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45 SA_DQ46

SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ40 SA_DQ41

SA_DQ39

SA_DQ37 SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32 SA_DQ33

SA_DQ29 SA_DQ30 SA_DQ31

SA_DQ27 SA_DQ28

SA_DQ24 SA_DQ25

SA_DQ22 SA_DQ23

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ17 SA_DQ18

SA_DQ16

SA_DQ14 SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7 SA_DQ8

SA_DQ6

SA_DQ4 SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0* SA_CS1*

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3 SA_MA4 SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13 SA_MA14 SA_MA15

SA_BA2

SA_BA0 SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5 SA_DQSN6 SA_DQSN7

SYM 4 OF 19

MEMORY CHANNEL B

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3 SB_DQ9 SB_DQ10 SB_CS0* SB_DQ11 SB_CS1* SB_DQ12 SB_DQ13 SB_ODT0 SB_DQ14 SB_DQ15 SB_RAS* SB_DQ16

SB_WE* SB_DQ17 SB_CAS* SB_DQ18 SB_DQ19

SB_BA0 SB_DQ20

SB_BA1 SB_DQ21

SB_BA2 SB_DQ22 SB_DQ23

SB_MA0 SB_DQ24

SB_MA1 SB_DQ25

SB_MA2 SB_DQ26

SB_MA3 SB_DQ27

SB_MA4 SB_DQ28

SB_MA5 SB_DQ29

SB_MA6 SB_DQ30

SB_MA7 SB_DQ31

SB_MA8 SB_DQ32

SB_MA9 SB_DQ33 SB_MA10 SB_DQ34 SB_MA11 SB_DQ35 SB_MA12

SB_MA13 SB_DQ37 SB_MA14 SB_DQ38 SB_MA15 SB_DQ39 SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7 SB_DQ48 SB_DQ49

SB_DQSP0 SB_DQ50

SB_DQSP1 SB_DQ51

SB_DQSP2 SB_DQ52

SB_DQSP3 SB_DQ53

SB_DQSP4 SB_DQ54

SB_DQSP5 SB_DQ55

SB_DQSP6 SB_DQ56

SB_DQSP7 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAA5

CAB9

RSVD1

CAB6

CAB1

CAB8

RSVD4

CAA2

CAA4

CAB9

CAA4

CAB7

CAB8

CAA9

CAB4

RSVD2

CAB2

CAB3

CAB1

CAA3

CAA1

CAA7

CAA6

CAB0

CAA8

CAB5

CAA0

CAA2

LPDDR3

CAA5

CAB5

CAB3

CAB2

CAB4

CAB6

LPDDR3

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

CAA0

RSVD3

70 71 76

70 76

70

20 21 24 76

20 24 76

21 24 76

20 24 76

70

70 76

21 24 76

19 76

22 24 76

23 24 76

22 24 76

23 24 76

22 23 24 76

70

70 76

70 71 76

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BOM_COST_GROUP=CPU

CPU LPDDR3 Interfaces

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

MEM_A_DQ<33> MEM_A_DQ<34>

=MEM_A_A<12>

MEM_B_DQ<36>

MEM_B_DQ<42>

MEM_B_DQ<12>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<29>

MEM_B_DQ<17>

MEM_B_DQ<25> MEM_B_DQ<26>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0>

=MEM_A_A<14>

=MEM_A_A<13>

=MEM_A_A<11> MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<37>

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CLK_N<1>

MEM_A_CLK_N<0> MEM_A_CLK_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<1>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

=MEM_A_BA<1>

=MEM_A_A<15>

=MEM_A_A<9> =MEM_A_A<10>

=MEM_A_A<8>

=MEM_A_A<7>

=MEM_A_A<4>

=MEM_A_A<3>

=MEM_A_CAS_L

=MEM_A_ODT<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_CLK_P<1>

MEM_A_DQ<2>

MEM_A_DQ<26>

MEM_A_DQ<35>

CPU_DIMMA_VREFDQ

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

MEM_A_CLK_N<1>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_DQ<21>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

=MEM_A_BA<2>

=MEM_A_A<0> =MEM_A_A<1>

=MEM_A_A<6>

MEM_B_CLK_P<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQ<56>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQS_P<5>

MEM_B_DQ<54>

MEM_B_DQS_P<4>

MEM_B_DQ<53>

MEM_B_DQS_P<3>

MEM_B_DQ<52>

MEM_B_DQS_P<2>

MEM_B_DQ<51>

MEM_B_DQS_P<1>

MEM_B_DQ<50>

MEM_B_DQS_P<0>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQ<44>

MEM_B_DQS_N<3>

MEM_B_DQ<43>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQ<41>

MEM_B_DQS_N<0>

MEM_B_DQ<40>

MEM_B_DQ<39>

=MEM_B_A<15>MEM_B_DQ<38>

=MEM_B_A<14>

=MEM_B_A<13>

=MEM_B_A<12>

=MEM_B_A<11>

=MEM_B_A<10>MEM_B_DQ<33>

=MEM_B_A<9>

MEM_B_DQ<32>

=MEM_B_A<8>

MEM_B_DQ<31>

=MEM_B_A<7>

MEM_B_DQ<30>

=MEM_B_A<6>

=MEM_B_A<5>

MEM_B_DQ<28>

=MEM_B_A<4>

MEM_B_DQ<27>

=MEM_B_A<3>

=MEM_B_A<2>

=MEM_B_A<1>

MEM_B_DQ<24>

=MEM_B_A<0>

MEM_B_DQ<23>

MEM_B_DQ<22>

=MEM_B_BA<2>MEM_B_DQ<21>

=MEM_B_BA<1>MEM_B_DQ<20>

=MEM_B_BA<0>MEM_B_DQ<19>

MEM_B_DQ<18>

=MEM_B_CAS_L

=MEM_B_WE_L

MEM_B_DQ<16>

=MEM_B_RAS_LMEM_B_DQ<15>

MEM_B_DQ<14>

=MEM_B_ODT<0>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_CS_L<0>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_CKE<3>

MEM_B_DQ<8>

MEM_B_CKE<2>

MEM_B_DQ<7>

MEM_B_CKE<1>

MEM_B_DQ<6>

MEM_B_CKE<0>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CS_L<1>

MEM_A_DQ<39>

=MEM_A_A<5>

=MEM_A_A<2>

MEM_A_CS_L<0>

MEM_A_CKE<0>

=MEM_A_BA<0>

=MEM_A_WE_L

=MEM_A_RAS_L

MEM_A_DQ<14>

MEM_A_DQ<20>

MEM_A_DQ<27>

MEM_A_DQ<12>

MEM_A_DQ<15> MEM_A_DQ<16>

MEM_A_DQ<28>

U0500

AU35 AV35 AY41

AU34

AU43 AW43 AY42 AY43

AV37

AU37

AY36

AW36

AP33 AR32

AH63 AH62

AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AK63

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55

AK62

AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56

AH61

AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42

AH60

AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49

AK61

AM48 AK48 AM51 AK51

AK60 AM63 AM62

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AU36 AY37

AP35 AW41 AU41 AR35 AV42 AU42

AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40

AP32

AY34 AW34

AP49

AR51

AP51

U0500

AL35 AM36 AU49

AM33

AN38

AM38

AL38

AK38

AY49 AU50 AW49 AV50

AM32 AK32

AY31 AW31

AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28

AY29

AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26

AW29

AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21

AV31

AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22

AU31

AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18

AV29

AK20 AM20 AR18 AP18

AU29 AY27 AW27

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

AP40 AR40

AK36 AV47 AU47 AK33 AR46 AP46

AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46

AL32

AM35 AK35

dvt1

051-1573

8.0.0

7 OF 120

7 OF 82

OUT

IN

NC NC

NC

BI

NC NC

IN

OUT

IN

NC NC NC

NC

OUT

NC

NC NC

NC

NC NC NC

IN

NC

HSW ULT POWER

SYM 12 OF 19

VCC

VCCST

RSVD

RSVD RSVD

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC RSVD

VDDQ VDDQ

VDDQ

RSVD

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VDDQ

VCCIOA_OUT RSVD RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

VCCHSIO VCCHSIO VCCHSIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCDSW3_3

VCCCLK

VCCACLKPLL

DCPSUS4

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05 VCC1P05

VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1

VCCTS1_5

VCCSDIO

RSVD

RSVD RSVD RSVD

VCCAPLL

VCC1_05 VCC1_05

VCC3_3

VCCCLK VCCCLK

VCCSUS3_3

VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol.1 Doc# 514405, Rev.: 0.9v1 Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9 Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

NOTE: Aliases not used on CPU supply outputs

18mA Max

185mA Max[1]

1499mA Max[1]

Max load: 300mA

R0800.2:

1.1A Max (LPDDR3: 1.2V)

VCCCLK: 200mA Max

40mA Max[1]

59mA Max[1]

57mA Max

1mA Max[1]

1.4A Max (DDR3: 1.5-1.35V)

32A Max

???mA Max

11mA Max

17mA Max

3.3mA Max[1]

VCCCLK: 200mA Max

31mA Max

to avoid any extraneous connections.

R0810.2:

1838mA Max

29mA Max[1]

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

114mA Max

WF: RSVD on Sawtooth Peak rev 1.0

R0802.2:

Powered in DeepSx

213mA Max[1]

WF: RSVD on Sawtooth Peak rev 1.0

Max load: 300mA

3mA Max

473mA Max[1]

41mA Max

0.3mA Max[1]

1/20W

1%

201

MF

130

PLACE_NEAR=U0500.L63:2.54mm

55 73

16

1/20W

5%

201

MF

100

PLACE_NEAR=U0500.C50:50.8mm

55 73

16 17 73

17 55

17

55 73

BYPASS=R0899:U0500:2.54mm

1UF

6.3V

10%

402

CERM

1/20W

1%

201

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54MM

55 73

10V

20%

402

CERM

0.1UF

BYPASS=U0500.AE7::6.35mm

BYPASS=U0500.AG10::6.35mm

10V

20%

402

CERM

0.1UF

10V

20%

402

CERM

0.1UF

BYPASS=U0500.AG10::6.35mm

6.3V

10%

402

CERM

1UF

BYPASS=U0500.AG10::6.35mm

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

1/20W

5%

0201

MF

0

1/20W

5%

0201

MF

0

1/20W

5%

201

MF

43

PLACE_NEAR=U0500.L62:38.1mm

PLACE_NEAR=R0810.1:2.54mm

1/20W

1%

201

75

MF

BOM_COST_GROUP=CPU

CPU & PCH Power

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

CPU_VIDSCLK

=PP1V05_S0_CPU_VCCST

TP_CPU_RSVD_P61

=PPVCC_S0_CPU

=PP3V3_SUS_PCH_VCC_SPI

=PP1V05_S0M_PCH_VCCASW

=PP1V5_S0_PCH_VCCTS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S5_PCH_VCCDSW

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

PP1V05_S0_PCH_VCC_ICC

PP1V05_S0_PCH_VCCACLKPLL

=PP1V05_S0_PCH_VCCCLK

PP1V05_S0SW_PCH_VCCUSB3PLL

=PP3V3_SUS_PCH_VCCSUS_GPIO

PP1V05_S0_PCH_VCCAPLL_OPI

=PP1V05_S0_PCH_VCCIO_USB2

=PP3V3R1V8_S0_PCH_VCCSDIO

=PP1V05_S0_PCH_VCCIO_HSIO

=PP3V3_SUS_PCH_VCCSUS_ICC

PP1V05_S0SW_PCH_VCCSATA3PLL

=PP1V05_S0SW_PCH_VCCHSIO

CPU_VCCSENSE_P

CPU_VIDALERT_L

=PPVMEMIO_S0_CPU

=PPVCC_S0_CPU

=PP1V05_S0_CPU_VCCST

=PP3V3_S0_PCH_VCCTS

=PP1V05_S0M_PCH_VCCASW

CPU_VIDSOUT

TP_CPU_RSVD_N59 TP_CPU_RSVD_N61

=PP1V05_S0_PCH_VCC

=PPVRTC_G3_PCH

=PP3V3_SUS_PCH_VCCSUS_RTC

TP_CPU_RSVD_P60

CPU_VIDSCLK_R

CPU_VIDALERT_R_L

CPU_PWR_DEBUG

CPU_VIDSOUT_R

CPU_VCCST_PWRGD CPU_VR_EN CPU_VR_READY

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

TP_PPVCCIO_S0_CPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PPVCOMP_S0_CPU

VOLTAGE=1.05V

R0811

12

R0812

12

R0810

12

R0800

1

2

R0802

1

2

R0860

1

2

C0899

1

2

R0899

12

C0895

1

2

C0892

1

2

C0891

1

2

C0890

1

2

U0500

H59

AA23

AA59

AB23

AC58

AC59

AD23

AD59

AD60

AE59

AE60

AG58

J58

L59

N58

T59

N59 N61

P60 P61

U59 V59

F59

AB57 AD57 AG57

C24 C28 C32

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57

E63

U57 W57

A59 E20

AC22 AE22 AE23

B59

AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

L62 N63 L63

F60 C59

D63

P62

U0500

AE7

AD10 AD8

AH13

J13

AB8

AG19 AG20

AC20

K18 M20 V21

Y20

AE8 AF22

AG16 AG17

H11 H15

J11

N8 P9

K14 K16

V8 W9

A20

AA21

W21

AE9 AF9

AG13

AG14

AG8

J17

J18 K19

R21 T21

AH10

AH14

K9

L10

M9

AG10

B11

T9

U8

Y8

AA9

AC9

AE20 AE21

AH11

J15

B18

dvt1

8 OF 120

8 OF 82

8.0.0

051-1573

6 8

15 16 17 55 68

18

8

10 44 68

11 14 68

8

11 68

68

11 68

11 17 63

11

11 12

11 68

11 14

11 68

11

11 68

11 40 68

68

11 12

11 68

10 68

8

10 44 68

6 8

15 16 17 55 68

11 68

8

11 68

18

11 68

12 13 68

11 68

73

5

OUT

SYM 14 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

SYM 15 OF 19

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

SYM 16 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

55 73

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

OMIT_TABLE

CRITICAL

BGA

BROADWELL-ULT

2C+GT2

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

CRITICAL

BOM_COST_GROUP=CPU

CPU & PCH Grounds

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU_VCCSENSE_N

R0960

1

2

U0500

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

U0500

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

U0500

AH16

AH46

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

G3

G5

G6

G8 H13

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8

E62

T1 T58 U20 U22 U61 U9 V10

V23

V3

V58

V7 W20 W22 Y10 Y59 Y63

9 OF 82

9 OF 120

8.0.0

051-1573

dvt1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

CPU VCC Decoupling

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VDDQ DECOUPLING

Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

1x Bulk nostuff, Harris Beach has 2x nostuff

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603

CPU VCC Decoupling

NOTE: 38X capacitors are STUFFED and have been changed to 12pF for Noise Floor Reasons (Radar # 17754026).

OMIT_TABLE

4V X6S 0402

20%

10UF

CRITICAL

6.3V CERM-X5R 0402-1

OMIT_TABLE

20%

10UF

OMIT_TABLE

0402-1

20%

6.3V

10UF

CERM-X5R

0402-1

10UF

CERM-X5R

20%

6.3V

OMIT_TABLE

10UF

CERM-X5R 0402-1

20%

6.3V

OMIT_TABLE

10UF

CERM-X5R 0402-1

20%

6.3V

OMIT_TABLE

10UF

20%

6.3V CERM-X5R 0402-1

OMIT_TABLE

6.3V

20%

402-LF

CERM

2.2UF 2.2UF

6.3V

20%

402-LF

CERM

6.3V 402-LF

20% CERM

2.2UF

402-LF

CERM

20%

6.3V

2.2UF

2V

20%

CASE-B2-SM

TANT

270UF

2V

20%

CASE-B2-SM

TANT

270UF

NO STUFF

CRITICAL

0402

20%

10UF

X6S

4V

2%

12PF

CRITICAL

50V 0402

C0G-CERM

0402

NO STUFF

4V

10UF

X6S

20%

CRITICAL

OMIT_TABLE

10UF

20%

CRITICAL

0402

X6S

4V 4V

X6S

20%

0402

CRITICAL

10UF

OMIT_TABLE

CRITICAL

NO STUFF

0402

X6S

4V

10UF

20%

X6S 0402

4V

20%

10UF

NO STUFF

CRITICAL CRITICAL

0402

50V

12PF

C0G-CERM

2%

10UF

4V

20%

0402

X6S

CRITICAL

OMIT_TABLE

50V C0G-CERM

12PF

CRITICAL

2%

0402

OMIT_TABLE

0402

CRITICAL

10UF

4V

20% X6S

20%

OMIT_TABLE

CRITICAL

10UF

0402

X6S

4V

OMIT_TABLE

CRITICAL

10UF

X6S 0402

20% 4V

C0G-CERM

50V

12PF

0402

2%

CRITICAL

10UF

X6S

CRITICAL

4V

20%

0402

NO STUFF

C0G-CERM

12PF

CRITICAL

50V

2%

0402

CRITICAL

NO STUFF

4V

20%

0402

X6S

10UF

0402

CRITICAL

4V

20% X6S

10UF

NO STUFF

CRITICAL

NO STUFF

0402

4V

10UF

X6S

20%

CRITICAL

C0G-CERM 0402

12PF

50V

2%

OMIT_TABLE

20%

CRITICAL

10UF

0402

4V X6S

10UF

CRITICAL

0402

NO STUFF

X6S

20% 4V

10UF

20% 4V X6S 0402

NO STUFF

CRITICAL

10UF

20%

CRITICAL

4V X6S 0402

OMIT_TABLE

C0G-CERM

50V

12PF

2%

CRITICAL

0402

10UF

4V X6S 0402

CRITICAL

20%

NO STUFF

CRITICAL

10UF

NO STUFF

0402

X6S

4V

20%

CRITICAL

12PF

50V

2% C0G-CERM

04020402

50V

2% C0G-CERM

12PF

CRITICAL

C0G-CERM 0402

CRITICAL

50V

12PF

2%2%

12PF

0402

CRITICAL

50V C0G-CERM

10UF

NO STUFF

X6S

4V

20%

0402

CRITICAL

12PF

CRITICAL

50V 0402

C0G-CERM

2%

10UF

NO STUFF

CRITICAL

4V 0402

X6S

20%

CRITICAL

C0G-CERM

50V

2%

12PF

0402

CRITICAL

10UF

NO STUFF

4V

20%

0402

X6S

CRITICAL

0402

12PF

50V

2% C0G-CERM

C0G-CERM

2%

0402

50V

12PF

C0G-CERM 0402

12PF

50V

2%

C0G-CERM 0402

50V

2%

12PF12PF

2%

0402

50V C0G-CERM

20%

CRITICAL

10UF

4V X6S 0402

OMIT_TABLE

0402

C0G-CERM

50V

12PF

2%

X6S 0402

NO STUFF

4V

20%

10UF

NO STUFF

10UF

20% X6S

0402

4V

NO STUFF

4V 0402

X6S

10UF

20%

50V

12PF

C0G-CERM

2%

0402

10UF

NO STUFF

0402

4V X6S

20%

0402

C0G-CERM

12PF

50V

2%

0402

NO STUFF

20% 4V

10UF

X6S

12PF

0402

50V

2% C0G-CERM

0402

50V

2% C0G-CERM

12PF

50V

2% C0G-CERM

0402

20%

10UF

0402

X6S

NO STUFF

4V

X6S 0402

4V

10UF

NO STUFF

20%

X6S 0402

10UF

4V

NO STUFF

20%

NO STUFF

4V

20% X6S

0402

10UF

4V

20%

0402

X6S

10UF

NO STUFF

CRITICAL

20%

OMIT_TABLE

4V X6S 0402

10UF

NO STUFF

10UF

20% 4V

0402

X6SX6S

0402

4V

10UF

20%

NO STUFF

12PF

50V 0402

2% C0G-CERM

X6S

10UF

4V

20%

0402

NO STUFF

0402

X6S

4V

20%

10UF

CRITICAL

OMIT_TABLE

0402

10UF

NO STUFF

4V

20% X6S

NO STUFF

4V 0402

20% X6S

10UF

50V

12PF

2% C0G-CERM

0402

NO STUFF

4V

10UF

20% X6S

0402

NO STUFF

20% 4V

0402

X6S

10UF

C0G-CERM

2%

12PF

50V 0402

10UF

4V X6S 0402

20%

CRITICAL

OMIT_TABLE

C0G-CERM

12PF

50V 0402

2%

NO STUFF

10UF

0402

4V

20% X6S

50V C0G-CERM

12PF

0402

2%

C0G-CERM 0402

50V

12PF

2%

4V

NO STUFF

0402

20% X6S

10UF

50V 0402

2% C0G-CERM

12PF

4V

NO STUFF

0402

10UF

20% X6S

NO STUFF

10UF

0402

4V

20% X6S

12PF

0402

50V C0G-CERM

2%

NO STUFF

10UF

20% 4V X6S 0402

C0G-CERM

12PF

0402

50V

2%

NO STUFF

4V

20%

0402

X6S

10UF

NO STUFF

4V

20%

0402

X6S

10UF

12PF

50V 0402

2% C0G-CERM

4V

20%

0402

X6S

10UF

NO STUFF

4V

20%

0402

X6S

10UF

NO STUFF

POLY-TANT

2.5V

20%

SM

470UF-0.0045OHM

CRITICAL

C0G-CERM

12PF

CRITICAL

0402

50V

2% 2%

C0G-CERM

12PF

50V 0402

CRITICAL CRITICAL

OMIT_TABLE

0402

4V X6S

20%

10UF

CRITICAL

12PF

2% 50V

0402

C0G-CERM

12PF

50V

CRITICAL

0402

2% C0G-CERM

4V

20%

10UF

CRITICAL

OMIT_TABLE

0402

X6S

NO STUFF

X6S

4V

20%

10UF

CRITICAL

0402

OMIT_TABLE

0402

X6S

4V

20%

10UF

CRITICAL

OMIT_TABLE

20%

10UF

4V X6S

CRITICAL

0402

NO STUFF

CRITICAL

4V

20%

0402

X6S

10UF

OMIT_TABLE

CRITICAL

10UF

X6S 0402

20% 4V

5% NP0-C0G

12PF

0201

25V

NP0-C0G

12PF

0201

5% 25V

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU Decoupling

C1000,C1004,C1008,C1012,C1018,C1019,C1020,C1022,C1026,C1034,C1065,C1070,C1074,C105A,C105C,C105D,C104F,C105F

CAP,CER,10UF,20%,4V,X6S,HRZTL,0402

138S0942

18

CRITICAL

138S0801

6

CAP,CER,10UF,20%,6.3V,HRZTL,0402

CRITICAL

C1050,C1051,C1052,C1053,C1054,C1055

=PPVCC_S0_CPU

=PPVMEMIO_S0_CPU

C1000

1

2

C1050

1

2

C1051

1

2

C1052

1

2

C1053

1

2

C1054

1

2

C1055

1

2

C1040

1

2

C1041

1

2

C1042

1

2

C1043

1

2

C1060

1

2

C1061

1

2

C1001

1

2

C1002

1

2

C1003

1

2

C1004

1

2

C1008

1

2

C1009

1

2

C1010

1

2

C1011

1

2

C1012

1

2

C1014

1

2

C1018

1

2

C1019

1

2

C1020

1

2

C1021

1

2

C1084

1

2

C1083

1

2

C1082

1

2

C1081

1

2

C1077

1

2

C1075

1

2

C1074

1

2

C1073

1

2

C1072

1

2

C1070

1

2

C1097

1

2

C1096

1

2

C1095

1

2

C1094

1

2

C1093

1

2

C1092

1

2

C1091

1

2

C1090

1

2

C1089

1

2

C1088

1

2

C1087

1

2

C1086

1

2

C1085

1

2

C1038

1

2

C1037

1

2

C1036

1

2

C1035

1

2

C1034

1

2

C1033

1

2

C1032

1

2

C1029

1

2

C109A

1

2

C1099

1

2

C1098

1

2

C107B

1

2

C107A

1

2

C1069

1

2

C1068

1

2

C108F

1

2

C1067

1

2

C108E

1

2

C1066

1

2

C108D

1

2

C108C

1

2

C1065

1

2

C1028

1

2

C1027

1

2

C1049

1

2

C1048

1

2

C1026

1

2

C1047

1

2

C1025

1

2

C1024

1

2

C1046

1

2

C1045

1

2

C1023

1

2

C1022

1

2

C1044

1

2

C1039

1

2

C1064

1

2

C108B

1

2

C1063

1

2

C108A

1

2

C1062

1

2

C109F

1

2

C109E

1

2

C1059

1

2

C1058

1

2

C109D

1

2

C1057

1

2

C109C

1

2

C1056

1

2

C109B

1

2

C1031

1

23

C1030

1

2

C104E

1

2

C104F

1

2

C106D

1

2

C106E

1

2

C105A

1

2

C105B

1

2

C105C

1

2

C105D

1

2

C105E

1

2

C105F

1

2

C1079

1

2

C1080

1

2

10 OF 120

dvt1

051-1573

8.0.0

10 OF 82

8

44 68

8

68

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PCH VCCACLKPLL FILTER/BYPASS

PCH VCCCLK FILTER/BYPASS

(PCH 3.3V SUSPEND RTC PWR)

Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSUSHDA BYPASS

(PCH 3.3V/1.8V SDIO PWR)

(PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND PWR)

(PCH 3.3V DSW PWR)

(PCH 1.05V ACLK PLL PWR)

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR)

(PCH 3.3V THERMAL PWR)

PCH VCC3_3 BYPASS

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V ME CORE PWR)

PCH VCCASW BYPASS

(PCH 1.05V CORE PWR)

PCH VCC BYPASS

PCH VCCSUS3_3 BYPASS

PCH VCCDSW3_3 BYPASS

(PCH 1.05V SATA3 PLL PWR)

41mA Max

83mA Max 42mA Max

??mA Max

31mA Max

57mA Max

??mA Max

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS

PCH OPI VCCAPLL FILTER/BYPASS

PCH VCCSDIO BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SPI PWR)

(PCH 1.05V VCCCLK PWR)

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

PCH VCCSPI BYPASS

NO STUFF

0.1UF

CERM

402

20% 10V

BYPASS=U0500.Y8::6.35mm

NO STUFF

CRITICAL

2.2UH-240MA-0.221OHM

0603

0

MF-LF

402

5%

1/16W

X6S

0805

20%

BYPASS=U0500.B18::12.7mm

4V

47UF

X6S

0805

20%

BYPASS=U0500.B11::12.7mm

47UF

4V

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

BYPASS=U0500.B11::12.7mm

BYPASS=U0500.AA21::12.7mm

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

BYPASS=U0500.AA21::12.7mm

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

X6S

0805

20%

BYPASS=U0500.J18::12.7mm

4V

47UF

X6S

0805

20%

BYPASS=U0500.J18::12.7mm

47UF

4V

X6S

0805

20%

BYPASS=U0500.A20::12.7mm

47UF

4V

X6S

0805

20%

BYPASS=U0500.A20::12.7mm

47UF

4V

NO STUFF

BYPASS=U0500.AH10::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AH14::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.K14::6.35mm

0.1UF

CERM

402

20% 10V

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AH11::6.35mm

BYPASS=U0500.AG16::6.35mm

1UF

CERM

402

10%

6.3V

1UF

CERM

10%

6.3V 402

BYPASS=U0500.L10::6.35mm

OMIT_TABLE

BYPASS=U0500.M9::6.35mm

10UF

CERM-X5R

20%

6.3V 0402-1

BYPASS=U0500.J17::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.J11::12.7mm

10UF

X5R 603

20%

6.3V

BYPASS=U0500.AE9::12.7mm

NO STUFF

22UF

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.J11::6.35mm

1UF

CERM 402

10%

6.3V

BYPASS=U0500.AE8::6.35mm

1UF

CERM 402

10%

6.3V

BYPASS=U0500.AE9::6.35mm

1UF

CERM 402

10%

6.3V

BYPASS=U0500.R21::6.35mm

1UF

CERM

402

10%

6.3V

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.AC9::12.7mm

22UF

BYPASS=U0500.V8::12.7mm

22UF

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.U8::6.35mm

1UF

CERM

402

10%

6.3V

1UF

CERM

10%

6.3V

BYPASS=U0500.K9::6.35mm

402

1UF

BYPASS=U0500.J18::6.35mm

X5R 402

10% 10V

CRITICAL

2.2UH-240MA-0.221OHM

0603

BYPASS=U0500.B18::6.35mm

1UF

X5R 402

10% 10V

CRITICAL

0603

2.2UH-240MA-0.221OHM

BYPASS=U0500.B11::6.35mm

X5R 402

10% 10V

1UF

CRITICAL

2.2UH-240MA-0.221OHM

0603

MF-LF

402

5%

1/16W

0

BYPASS=U0500.A20::6.35mm

1UF

X5R 402

10% 10V

0603

CRITICAL

2.2UH-240MA-0.221OHM

0

MF-LF

402

5%

1/16W

BYPASS=U0500.AA21::6.35mm

10%

1UF

X5R 402

10V

CRITICAL138S0801

1

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C1262

SYNC_DATE=10/23/2012

PCH Decoupling

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

=PP1V05_S0SW_PCH_VCCHSIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S5_PCH_VCCDSW

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL_R

=PP1V05_S0SW_PCH_VCCPLL_HSIO

VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_ICC

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0SW_PCH_VCCUSB3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCACLKPLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

=PP3V3R1V8_S0_PCH_VCCSDIO

=PP1V05_S0_PCH_PLLFILTERS

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

=PP1V05_S0_PCH_VCC

=PP1V05_S0M_PCH_VCCASW

=PP1V05_S0_PCH_VCCCLK

=PP3V3_S0_PCH_VCCTS

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_RTC

C1210

1

2

C1206

1

2

C1202

1

2

C1200

1

2

C1214

1

2

C1264

1

2

C1261

1

2

C1262

1

2

C1266

1

2

C1255

1

2

C1250

1

2

C1256

1

2

C1257

1

2

C1251

1

2

C1267

1

2

C1204

1

2

C1212

1

2

C1208

1

2

C1260

1

2

C1277

1

2

L1275

12

C1297

1

2

L1295

12

C1292

1

2

L1290

12

R1275

12

C1272

1

2

L1270

12

R1270

12

C1282

1

2

L1280

12

R1280

12

C1295

1

2

C1290

1

2

C1291

1

2

C1280

1

2

C1281

1

2

C1275

1

2

C1276

1

2

C1270

1

2

C1271

1

2

11 OF 82

12 OF 120

8.0.0

051-1573

dvt1

8

68

8

14 68

8

68

8

12

8

14

8

12

8

40 68

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

17 63

8

68

IN IN

IN

OUT

BI

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1 RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

SYM 6 OF 19

CLOCK SIGNALS

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW TESTLOW

DIFFCLK_BIASREF

RSVD

OUT

IN

NC

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-PLTRST#)

SATA Port assignments:

SSD Lane 3

SSD Lane 1

SSD Lane 2

(IPU)

(IPD)

SSD Lane 0

PCIe Port assignments:

(IPD-PWROK)

(IPD)

Secondary HDD/SSD

Unused

Primary HDD/SSD

(IPD-PLTRST#)

(IPU)

Reserved: ODD

16 73

201

10K

5% MF

1/20W

201

5% MF

100K

1/20W

16

1/20W

100K

201

MF5%

16 73

CRITICAL

2C+GT2

BROADWELL-ULT

OMIT_TABLE

BGA

2C+GT2

OMIT_TABLE

BROADWELL-ULT

BGA

CRITICAL

49 75

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF33201

1/20W

5%

33

MF

PLACE_NEAR=U0500.AV11:1.27mm

201

49 71 75

MF

201

5%

1/20W

33

PLACE_NEAR=U0500.AW8:1.27mm

17 75

330K

1/20W

5%

201

MF

1/20W

5%

201

MF

1M

1UF

402

10% 10V X5R

20K

MF

201

5%

1/20W

X5R 402

1UF

10% 10V

MF

1/20W

20K

201

5%

16

3.01K

PLACE_NEAR=U0500.C12:2.54mm

MF

1/20W

1%

201

32 71 81

12 66

66 71 81

49 75

12 33

34 71 81

25 71 81

12 25

32 71 81

12 32

MF 201

1% 1/20W

3.01K

PLACE_NEAR=U0500.C26:2.54mm

17 75

10K

MF5%

201

1/20W

5%

10K

1/20W

201

MF

1/20W

5%

10K

MF

201

5%

10K

1/20W

MF

201

17 75

17

MF5%

1/20W

33

201

PLACE_NEAR=U0500.AU11:1.27mm

1/20W

5%

100K

201

MF

201

5%

1/20W

MF

100K

5%

201

100K

1/20W

MF

1/20W

5%

201

20K

MF

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=12/17/2012

PCH Audio/JTAG/SATA/CLK

PCH_CLK24M_XTALIN

PCH_DIFFCLK_BIASREF

FW_CLKREQ_L

AP_CLKREQ_L

PCIE_CLK100M_AP_P

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

PCH_INTVRMEN

TP_PCH_I2S1_SCLK

XDP_PCH_TDO

PCH_JTAGX

TP_PCH_I2S1_SFRM

HDA_RST_L

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

=PPVRTC_G3_PCH

PCH_SATALED_L

XDP_PCH_TMS

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TRST_L

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

HDA_SDOUT_R

TP_HDA_SDIN1

HDA_SYNC_R

HDA_RST_R_L

PCH_SRTCRST_L

PCH_INTRUDER_L

RTC_RESET_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

HDA_BIT_CLK_R

TP_PCH_I2S1_TXD

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0>

PP1V05_S0SW_PCH_VCCSATA3PLL

PCH_TESTLOW_C34

TP_PCIE_CLK100M_ENETSDP

PCH_CLK24M_XTALOUT

TP_PCIE_CLK100M_ENETSDN

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

ENETSD_CLKREQ_L

TP_PCIE_CLK100M_FWN TP_PCIE_CLK100M_FWP

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

TBT_CLKREQ_L

SSD_CLKREQ_L

LPC_CLK24M_SMC_R

PCH_TESTLOW_AK8

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_P<1>

XDP_SSD_PCIE3_SEL_L

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE1_SEL_L

PCH_TESTLOW_AL8

PCH_TESTLOW_C35

HDA_SDIN0

TP_LPC_CLK24M_LPCPLUS

PP1V05_S0_PCH_VCCACLKPLL

PCH_SATA_RCOMP

XDP_SSD_PCIE2_SEL_L

ENETSD_CLKREQ_L

PCH_SATALED_L

PCIE_CLK100M_AP_N

CAMERA_CLKREQ_L

CAMERA_CLKREQ_L AP_CLKREQ_L FW_CLKREQ_L TBT_CLKREQ_L

=PP3V3_S0_PCH_GPIO

SSD_CLKREQ_L

R1313

12

R1312

12

R1311

12

R1310

12

R1302

1

2

R1301

1

2

C1300

1

2

R1300

1

2

C1303

1

2

R1303

1

2

R1370

1

2

R1380

1

2

R1390

12

R1391

12

R1392

12

R1393

12

R1341

12

R1344

12

R1340

12

R1342

12

R1345

12

R1375

12

R1343

12

U0500

AW8

AW10 AV10

AU8

AY10 AU12

AU11

AV11

AY8

AU6

AV7

AE63

AE62

AD61

AE61

AD62

AU62

AC4

AL11

AV2

K10

L11

AU7

AW5 AY5

V1 U1 V6 AC1

A12

C12

J5

J8

J6

F5

H5

H8

H6

E5

B15

A17

B14

C17

A15

B17

C15

D17

U3

AV6

U0500

B35 A35

AN15

AP15

C43

B41

C41

B38

A39

B37

C42

A41

B42

C37

B39

A37

C26

U2

Y5

AD1

N1

U5

T2

K21 M21

AK8 AL8

C34

C35

A25 B25

13 OF 120

8.0.0

051-1573

dvt1

12 OF 82

12

69

75

69

8

13 68

12

17 75

69

75

69

8

11

69

12 71

69

8

11

75

12 71

12

12 33

12 66

12

12 25

13 15 18 26 65 68

12 32

IN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79 PIRQD*/GPIO80

PIRQA*/GPIO77 PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(IPU)

R1400 kept for debug purposes.

SLP_S0# Isolation

(IPD-DeepSx)

U1420 ensures signal will only be high in S0.

SLP_S0# can be driven high outside of S0

64 75

13 18 38

40

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

BGA

OMIT_TABLE

CRITICAL

BROADWELL-ULT

2C+GT2

13 32

15 16 18

17

17 75

16 17 38 75

17 38 71 75

13 64

13 17 18 38 64 66 71

13 18 31 37 38 64 66

13 38 64

39

38 71

13 38 71

13 31 33 75

100K

MF

1/20W

201

5%

38 75

330K

MF 201

5% 1/20W

13 65

65 71

13 65

25 77

69

25 77

30

69

30

25

69

65

100K

MF 201

1/20W

5%

100K

MF

1/20W

2015%

MF 2015%

1/20W

100K

5%

100K

201

1/20W

MF

5%

1/20W

MF

10K

201

NO STUFF

MF

1/20W

0201

0

5%

MF

100K

1/20W

2015%

13 26

13 38

13 71

13 69

13 71

13 27 38

10K

MF

1/20W

201

5%

MF

1/20W

201

5%

10K

100K

MF5% 201

1/20W

100K

MF

1/20W

2015%

100K

MF

1/20W

2015%

201

100K

MF

1/20W

5%

201

MF

100K

1/20W

5%

38 39

13 64

1K

MF

1/20W

201

5%

10K

MF

1/20W

201

5%

100K

MF

201

5%

1/20W

100K

MF

1/20W

201

5%

201

100K

MF

1/20W

5%

201

100K

MF

1/20W

5%

201

MF

100K

1/20W

5%

13 16 38 75

SOT891

74LVC1G08

CRITICAL

10% 10V

0.1UF

0201

X5R-CERM

SYNC_DATE=02/21/2013SYNC_MASTER=J41

PCH PM/PCI/GFX

BOM_COST_GROUP=CPU

ENET_LOW_PWR

DP_AUXCH_ISOL_L

ODD_PWR_EN_L

SSD_BOOT

PM_DSW_PWRGD

PM_SLP_S4_L

PM_SLP_S3_L

=PP3V3_S5_PCH_GPIO

ENET_LOW_PWR AUD_PWR_EN

SSD_BOOT

DP_TBTSNK0_AUXCH_C_P

=DP_TBTSNK1_AUXCH_C_N

AUD_IP_PERIPHERAL_DET

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L

EDP_BKLT_EN

EDP_BKLT_PWM

DP_INT_HPD

=DP_TBTSNK1_HPD

=DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_C_N

=DP_TBTSNK1_DDC_CLK =DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

EDP_PANEL_PWR

PCIE_WAKE_L

TP_PCH_SLP_WLAN_L

PCH_PM_SLP_S0_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PCH_SUSWARN_L

PM_RSMRST_L

PM_PCH_PWROK

PM_PCH_APWROK

PM_SYSRST_L

PCH_SUSACK_L

PLT_RESET_L

PM_PCH_SYS_PWROK

PCH_DSWVRMEN

PM_CLKRUN_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

=PP3V3_S0_PCH_GPIO

=PPVRTC_G3_PCH

PCIE_WAKE_L

PM_CLKRUN_L

DP_AUXCH_ISOL_L

PM_SLP_S0_L

PM_SLP_S4_L PM_SLP_S3_L

AUD_IP_PERIPHERAL_DET

TP_PCI_PME_L

AUD_PWR_EN

PM_PWRBTN_L

PM_BATLOW_L

EDP_BKLT_EN

SMC_RUNTIME_SCI_L

ODD_PWR_EN_L

=PP3V3_S0_PCH_GPIO

PM_SLP_SUS_L

EDP_PANEL_PWR

TBT_PWR_REQ_L

PM_SLP_S0_L

PM_SLP_S5_L

AUD_IPHS_SWITCH_EN

R1400

1

2

R1451

1

2

R1450

1

2

R1446

12

R1445

12

R1442

12

R1443

12

R1441

12

R1440

12

R1455

12

R1410

12

R1447

12

R1448

12

R1449

12

R1431

12

R1430

12

R1405

12

R1452

12

R1460

12

R1461

12

R1462

12

R1464

12

R1463

12

U1420

2

1

3

6

4

C1420

1

2

U0500

AJ8

AB5

AN4

V5

AV5

AW7

AY7

AG7

AL7

AW6

AL5

AJ7AF3

AT4

AJ6

AP5

AP4

AM5

AG4

AK2

AE6

AV4

AG2

AC3

AJ5

U0500

C5

B5

B9 C9

C8

B6

A6

D9 D11

A8

B8

A9

D6

C6

R5

L1

L4

L3

U7

U6 P4 N4 N2

AD4

13 OF 82

dvt1

051-1573

8.0.0

14 OF 120

5

13 32

15 68

13 71

13 64

69

75

71

69

12 13 15 18 26 65 68

8

12 68

13 31 33 75

13 38 71

13 69

13 18 31 37 38 64 66

13 17 18 38 64 66 71

13 71

69

13 16 38 75

13 27 38

13 65

13 38

13 71

12 13 15 18 26 65 68

13 64

13 65

13 26

13 18 38

13 38 64

13 71

OUT

IN

OUT

IN

OUT

USB

PCI-E

SYM 11 OF 19

PCIE_RCOMP PCIE_IREF

RSVD

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42 OC3*/GPIO43

RSVD RSVD

USBRBIAS*

USBRBIAS

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

PERN1/USB3RN3

PERN2/USB3RN4

PERP1/USB3RP3

PERP2/USB3RP4

PETN1/USB3TN3

PETN2/USB3TN4

PETP1/USB3TP3

PETP2/USB3TP4

USB3RN1

USB3RN2

USB3RP1

USB3RP2

USB3TN1

USB3TN2

USB3TP1

USB3TP2

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2 LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

NC NC

BI

IN

BI

OUT

BI

OUT

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU/IPD)

Ext A (SS)

Ext B (SS)

SML1ALERT# pull-up not provided on this

(IPU/IPD)

Reserved: Camera

USB Port Assignments:

page, may be wire-ORed into other signals. Otherwise, 100k pull-up to 3.3V SUS required.

Thunderbolt lane 1

Camera

(& Ethernet if combo)

Thunderbolt lane 3

Thunderbolt lane 2

PCIe Port Assignments:

Thunderbolt lane 0

Reserved: FireWire

AirPort

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

(IPU/IPD)

(IPU)

(IPD)

SD Card Reader

(IPU)

USB3 Port Assignments:

Unused

Trackpad

Reserved: SD (HS)

25 71 81

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

14 16

40

14 16

25 71 81

14 71

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

36 71 74

25 71 81

66 74

66 71 74

34 81

34 71 81

66 71 81

1/20W

1%

201

MF

3.01K

PLACE_NEAR=U0500.A27:2.54mm

66 71 74

35 71 74

25 71 81

35 71 74

1/20W

1%

201

MF

22.6

PLACE_NEAR=U0500.AJ10:2.54mm

69

25 71 81

69

31 74

66 74

25 71 81

35 74

38 71 75

1/20W

5% 201MF

33

1/20W

5% 201MF

33

25 71 81

1/20W

5% 201MF

33

1/20W

5% 201MF

33

1/20W

5% 201MF

33

47 75

41 75

25 71 81

41 75

41 71 75

47 75

25 71 81

14 47 75

1/20W

5% 201MF

100K

1/20W

5% 201MF

1K

1/20W

5% 201MF

100K

1/20W

5% 201MF

1K

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

BOM_COST_GROUP=CPU

PCH PCIe,USB,LPC,SPI,SMBus

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

USB3_EXTB_R2D_C_P

USB3_EXTB_D2R_P

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N

PCH_USB_RBIAS

USB_IR_N

USB_BT_N

TP_USB_SDN TP_USB_SDP

=PP3V3_SUS_PCH_VCC_SPI

XDP_USB_EXTA_OC_L

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

LPC_AD<3>

=PP3V3_SUS_PCH_GPIO

PCH_SMBALERT_L

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_CLINK_CLK

SML_PCH_1_DATA

PCH_SML1ALERT_L

SML_PCH_1_CLK

SML_PCH_0_DATA

SML_PCH_0_CLK

WOL_EN

LPC_AD_R<0>

SPI_CLK_R

LPC_AD_R<1>

LPC_AD_R<3>

LPC_AD_R<2>

LPC_FRAME_R_L

TP_SPI_CS1_L

SPI_CS0_R_L

SPI_MOSI_R

TP_SPI_CS2_L

SPI_IO<2>

SPI_MISO

SPI_IO<3>

XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

XDP_USB_EXTB_OC_L

WOL_EN

SPI_IO<2> SPI_IO<3>

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_R2D_C_N

USB3RPCIE_SD_R2D_C_N

PCIE_CAMERA_D2R_P

USB_IR_P

USB_EXTB_P

USB_EXTB_N

USB_EXTA_P

USB_EXTA_N

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<3>

PCIE_AP_R2D_C_N

TP_PCIE_FW_D2RN

USB3RPCIE_SD_D2R_N

LPC_AD<1>

TP_PCIE_FW_D2RP

TP_PCIE_FW_R2D_CN

XDP_USB_EXTD_OC_L

PCH_SMBALERT_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

PCH_PCIE_RCOMP

USB3_EXTA_R2D_C_N

PCIE_TBT_D2R_P<3>

PP1V05_S0SW_PCH_VCCUSB3PLL

PCIE_CAMERA_D2R_N

USB3RPCIE_SD_R2D_C_P

USB3RPCIE_SD_D2R_P

TP_PCIE_FW_R2D_CP

TP_USB_CAMERAP

TP_USB_CAMERAN

TP_USB_5P

TP_USB_5N

SMBUS_PCH_DATA

SMBUS_PCH_CLK

USB3_EXTB_R2D_C_N

USB_TPAD_P

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_TBT_R2D_C_P<3>

USB_BT_P

USB_TPAD_N

R1500

1

2

R1570

1

2

R1543

12

R1542

12

R1544

12

R1540

12

R1541

12

R1591

12

R1549

12

R1590

12

R1548

12

R1582

12

R1583

12

R1580

12

R1581

12

U0500

AL3 AT1 AH2 AV3B27

A27

G17

F15

G11

F13

F10

F8

H10

E6

F17

G15

F11

G13

E10

E8

G10

F6

C30

B31

C29

B29

C23

B23

B21

B22

C31

A31

B30

A29

C22

A23

C21

A21

AM10

AN10

E13

E15

AN8

AR7

AR8

AR10

AM15

AM13

AP11

AR13

AM8

AT7

AP8

AT10

AL15

AN13

AN11

AP13

G20

E18

H20

F18

C33

B33

B34

A33

AJ11

AJ10

U0500

AF2

AD2

AF4

AU14 AW12 AY12 AW11

AV12

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AA3

Y7

Y4

AC2

Y6

AF1

AA4

AA2

14 OF 82

15 OF 120

8.0.0

051-1573

dvt1

74

69

8

11 68

14 16

68

14

69

14 16

14 71

14 47 75

69

14

75

8

11

69

IN

OUT

BI

OUT

IN

LPIO

GPIO

CPU/MISC

SYM 10 OF 19

SPKR/GPIO81

GPIO10

GPIO9

GPIO46

GPIO45

GPIO14

GPIO25

GPIO13

HSIOPC/GPIO71

GPIO50

GPIO49

GPIO48

GPIO44

GPIO47

GPIO59

GPIO58

GPIO57

GPIO56

GPIO26

GPIO27

GPIO28

GPIO24

GPIO16

GPIO17

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

BMBUSY*/GPIO76

SDIO_D3/GPIO69

SDIO_D2/GPIO68

SDIO_D1/GPIO67

I2C0_SDA/GPIO4

UART1_TXD/GPIO1

UART1_CTS*/GPIO3

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

GSPI0_MOSI/GPIO86

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_CS*/GPIO83

RSVD RSVD

PCH_OPI_COMP

RCIN*/GPIO82

SERIRQ

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RST*/GPIO2

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

SDIO_POWER_EN/GPIO70

DEVSLP0/GPIO33

DEVSLP1/GPIO38

DEVSLP2/GPIO39

THERMTRIP*

OUT

IN

OUT

BI

IN

OUT

IN

BI

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

R1616 should also be stuffed if

TBTLC for CR, S0 for RR

platform does not use SD card

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

(IPD-PLTRST#)

STUFFED R1632

GPIO12:

(IPD-DeepSx)

(IPD-PLTRST#)

(IPD)

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

(IPD)

(IPD-RSMRST#)

Requires connection to SMC via 1K series R

(IPD-PLTRST#)

Pull-up on TBT page

MF

1/20W

5% 201

10K

201

100K

1/20W

5% MF 5% 201

100K

1/20W

MF

5%

1/20W

100K

201MF

100K

1/20W

5% 201MF

MF 2015%

100K

1/20W

100K

1/20W

5% 201MF

100K

1/20W

5% 201MF

MF 2015%

1/20W

100K

1/20W

5% 201MF

MF 2015%

1/20W

100K

1/20W

201

100K

MF

5%

201MF5%1K1/20W

MF 2015%

1/20W

100K

1/20W

5%

MF

201

13 15 16 18

18

15 38 71

66

15 31

201

100K

MF

5% 1/20W

13 15 16 18

15 67

15 18

2015%

100K

MF

1/20W

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

15 37 75

100K

MF

201

5%

1/20W

RAMCFG3:H

15 37 75

15 37

18 33

201

MF

5%

100K

1/20W

BAT54XV2T1

SOD-523

69

100K

MF 201

5% 1/20W

RAMCFG2:H

MF

5%

1M

1/20W

201

15 36 71

0201

1/20W

5%

0

MF

0

MF 0201

1/20W

5%

201

100K

MF

5%

1/20W

RAMCFG1:H RAMCFG0:H

5%

201

MF

100K

1/20W

26

15 71

15 65

15 71

65 71

40

15 16

15 16 18

15 16

15 32 64

15 71

15 66

15 25

15 16

15 18

15 63

15 47 71

15 18

15 32

15 31

32

15 38

15 66

39 75

15 16

15 16 18

18

15 16

5%

1K

1/20W

MF

201

1/20W

MF

100K

5% 201

MF

100K

1/20W

2015%

100K

MF5% 201

1/20W

5% MF

1/20W

100K

SD_ON_MLB

201

MF

1/20W

201

100K

5%

MF

1/20W

100K

5% 201

MF 201

100K

1/20W

5%

1/20W

MF 201

100K

5%

MF 201

1/20W

5%

100K

MF 2015%

100K

1/20W

201MF

100K

1/20W

5%

201

100K

5%

1/20W

MF MF5%

100K

201

1/20W

201MF

100K

5%

1/20W

MF 2015%

1/20W

100K

201MF5%

1/20W

100K

201

1/20W

MF

100K

5%

1/20W

201MF

100K

5%

100K

201

1/20W

MF5%

5% MF

1/20W

100K

201

1/20W

5% MF 201

100K

10K

201

MF

1/20W

5%

MF5%

1/20W

201

100K

MF

1/20W

1%

49.9

201

PLACE_NEAR=U0500.AW15:2.54mm

201MF5%

1/20W

100K

1/20W

5% 201MF

100K

MF

1/20W

5% 201

1/20W

5%

100K

MF 201

100K

MF

1/20W

5% 201

47K

1/20W

MF5% 201

5%

47K

MF

1/20W

201

MF

1/20W

5% 201

47K

201MF

1/20W

5%

47K

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

PCH GPIO/MISC/LPIO

SYNC_MASTER=J41 SYNC_DATE=01/19/2013

BOM_COST_GROUP=CPU

ENET_MEDIA_SENSE

=TBT_GO2SX_BIDIR

HDMI_TBT_MUX_SEL_GPIO12

PLT_RESET_L

PCH_GSPI0_CLK

BT_PWRRST_L

XDP_JTAG_ISP_TCK

TBT_PWR_EN

SD_PWR_EN

XDP_MLB_RAMCFG3

PCH_HSIO_PWR_EN

JTAG_TBT_TMS_PCH

PCH_TBT_PCIE_RESET_L

PCH_I2C1_SDA

PCH_STRP_TOPBLK_SWP_L

TBT_POC_RESET_L

PCH_I2C1_SCL

XDP_MLB_RAMCFG3

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

TP_MEM_VDD_SEL_1V5_L

XDP_MLB_RAMCFG0

PCH_I2C0_SDA

PCH_UART1_TXD

PCH_UART1_CTS_L

JTAG_ISP_TDO

AP_RESET_L

PCH_UART1_RXD

PCH_GSPI0_MOSI

TPAD_SPI_CLK

PCH_GSPI0_CS_L

PCH_OPI_COMP

=TBT_CIO_PLUG_EVENT

PCH_UART1_RTS_L

PCH_I2C0_SCL

XDP_MLB_RAMCFG2

PCH_I2C0_SDA

PCH_I2C1_SCL

=PP1V05_S0_CPU_VCCST

XDP_MLB_RAMCFG0

PCH_UART1_RXD

PCH_UART1_RTS_L

PCH_I2C0_SCL

PCH_I2C1_SDA

PCH_UART1_CTS_L

PCH_UART1_TXD

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_MISO

PCH_GSPI0_CS_L

PCH_GSPI0_MISO PCH_GSPI0_MOSI

TPAD_SPI_CS_L TPAD_SPI_CLK

XDP_MLB_RAMCFG1

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_MISO

TPAD_SPI_CS_L

XDP_JTAG_ISP_TDI

SD_RESET_L

SMC_WAKE_SCI_L

TPAD_USB_IF_EN

LCD_PSR_EN

XDP_MLB_RAMCFG1

CAMERA_PWR_EN_PCH

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TPAD_SPI_INT_GPIO28_L

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_INT_L

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_MOSI

SSD_PWR_EN

TPAD_SPI_INT_GPIO28_L

=PP3V3_S0_PCH_GPIO

TPAD_SPI_IF_EN

SPIROM_USE_MLB

JTAG_ISP_TDO

LPC_SERIRQ

LCD_PSR_EN

ENET_MEDIA_SENSE

BT_PWRRST_L

XDP_PCH_GPIO76

TPAD_SPI_IF_EN

PCH_GSPI0_MISO

PCH_GSPI0_CLK

LPC_SERIRQ

PM_THRMTRIP_L

PP3V3_S0_EDP_SW

LCD_IRQ_L

PLT_RESET_L

TBT_PWR_EN

PCH_HSIO_PWR_EN

AP_S0IX_WAKE_SEL

SSD_SR_EN_L

TPAD_SPI_INT_L

PCH_TCO_TIMER_DISABLE

XDP_MLB_RAMCFG2

XDP_PCH_GPIO76

XDP_LPCPLUS_GPIO

CAMERA_PWR_EN_PCH

SPIROM_USE_MLB

JTAG_TBT_TMS_PCH

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

SD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TPAD_USB_IF_EN SSD_PWR_EN

SD_RESET_L

XDP_PCH_GPIO17

=PP3V3_S5_PCH_GPIO

SMC_WAKE_SCI_L

AP_S0IX_WAKE_SEL

SSD_SR_EN_L

=PP3V3_S3RS4_PCH_GPIO

=PP3V3_S0RTBTLC_PCH_GPIO

HDD_PWR_EN

=PP3V3_S0_PCH_GPIO

=PP3V3_S3SW_SD_RESET

=PP3V3_S0_PCH_GPIO

SSD_RESET_L

CAM_PCIE_RESET_L

=PP3V3_S3RS0_CAMPWREN

=PP3V3_S3_PCH_GPIO

R1650

1

2

R1655

1

2

R1652

12

R1631

1

2

R1636

1

2

R1635

1

2

R1611

1

2

R1610

12

R1614

12

R1615

12

R1616

12

R1617

12

R1618

12

R1619

12

R1620

12

R1622

12

R1623

12

R1624

12

R1625

12

R1626

12

R1627

12

R1628

12

R1630

12

R1632

12

R1633

12

R1637

12

R1638

12

R1691

12

R1694

12

R1693

12

R1695

12

R1660

12

R1661

12

R1662

12

R1663

12

R1664

12

R1665

12

R1666

12

R1667

12

R1668

12

R1669

12

R1672

12

R1674

12

R1673

12

R1675

12

R1676

12

R1678

12

R1677

12

R1679

12

R1639

1

2

R1641

12

R1629

12

R1621

1

2

R1671

1

2

R1670

12

U0500

P1

P2

L2

N5

AM2

AT3

AH4

AD6

Y1

T3

AD5

AM4

AN3

AN5

AD7

AK4

AG5

AG3

AB6

U4

Y3

P3

AG6

AP1

AL4

AT5

AU2

AM3

L6

R6

N6

L8

L5

R7

N7

K2

Y2

F3

F2

F1

G4

AM7

AW15

V4

AB21

AF20

E3

F4

D3

E4

C3

E2

C4

T4

V2

D60

G1

J2

J1

K3

J4

J3

K4

G2

R1680

1

2

D1600

AK

R1600

1

2

R1682

1

2

R1681

1

2

16 OF 120

8.0.0

051-1573

dvt1

15 OF 82

15

15 16 18

15

75

15

15 16 18

15

6 8

16 17 55 68

15 16 18

15

15 67

15 31

15 37 75

15

15 37 75

15 16 18

15 37

15

12 13 15 18 26 65 68

15 18

15 38 71

15 65

15 71

15 37

15

41 65

15 25

15 63

15 36 71

15 16

15 18

15 47 71

15 18

15 16

15 66

15 16

15 37

15 32 64

15 66

15 16

13 68

15 38

15 31

15 32

68

15 71

12 13 15 18 26 65 68

68

12 13 15 18 26 65 68

18 44

68

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

IN

TP

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

OUT

BI

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

TP

IN

TP

VER 3

D

SG

VER 3

D

SG

IN

VER 3

D

SG

VER 3

D

SG

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH XDP Signals

OBSDATA_B0

OBSDATA_B2

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Non-XDP Signals

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

VCC_OBS_AB

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

Unused & MLB_RAMCFGx GPIOs have TPs.

NOTE: Must not short XDP pins together!

TDI and TMS are terminated in CPU.

HOOK2

TDO TRSTn

Merged (CPU/PCH) Micro2-XDP

OBSFN_D0

SCL

OBSDATA_A1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

TCK0

TCK1

SDA

HOOK1

OBSDATA_B3

PWRGD/HOOK0

OBSDATA_B1

OBSFN_B0

OBSDATA_A2 OBSDATA_A3

OBSFN_B1

OBSDATA_A0

ITPCLK/HOOK4

DBR#/HOOK7

OBSDATA_D3

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_D0

OBSDATA_C2 OBSDATA_C3

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

518S0847

support chipset debug.

Extra BPM Testpoints

RESET#/HOOK6

VCC_OBS_CD

OBSFN_A1

OBSFN_A0

CPU JTAG Isolation

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

XDP_PRESENT#

TMS

TDI

HOOK3

OBSDATA_D2

OBSDATA_D1

6

73

13 15 18

6

73

6

73

6

73

6

73

6

73

6

73

13 38 75

13 17 38 75

12 16 73

17 75

6

73

12 16 73

5% 201

1/20W

MF

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U0500.E60:28mm

5%

0

402

MF-LF

XDP

1/16W

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

5% 201

1/20W

MF

1K

XDP

PLACE_NEAR=U0500.C61:2.54mm

6

73

M-ST-SM1

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

TP-P6

8

5%

150

402

MF-LF

1/16W

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.F62:28mm

12 16 73

5%

XDP

MF-LF 402

1/16W

1K

5% 201

1/20W

MF

51

PLACE_NEAR=U0500.AE62:28mm

NO STUFF

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD62:28mm

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD61:28mm

XDP

5% 201

1/20W

MF

51

PLACE_NEAR=U0500.AE61:28mm

5% 201

1/20W

MF

1K

PLACE_NEAR=U0500.AE63:28mm

NO STUFF

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=J1800.58:28mm

12 16 73

6

73

6

73

6

16 73

XDP

CERM-X5R 0201

6.3V

0.1UF

10%

15

14

6

73

66

TP-P6

14 35

15 18

14

TP-P6

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

TP-P6

15 18

TP-P6

15 18

TP-P6

15 18

12

15

15 18

12

5% 201

1/20W

MF

1K

5% 201

1/20W

MF

1K

6

73

5% 201

1/20W

MF

1K

5% 201

1/20W

MF

1K

32

15

6

73

15

15 18

71

TP-P6

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

0.1UF

CERM-X5R 0201

XDP

6.3V

10%

6

73

12 16

5% 201

1/20W

MF

PLACE_NEAR=U0500.AU62:28mm

NO STUFF

51

SOT891

74LVC1G07GF

16V

0201

X5R-CERM

0.1UF

10%

6

73

5%

201

1/20W MF

330K

17 38 64

TP-P6

18

TP-P6

DMN5L06VK-7

SOT563

XDP

CRITICAL

SIGNAL_MODEL=DMN5L06VK_7

PLACE_NEAR=J1800.51:28mm

XDP

CRITICAL

SOT563

PLACE_NEAR=J1800.53:28mm

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

6

73

SOT563

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

XDP

CRITICAL

PLACE_NEAR=J1800.55:28mm

CRITICAL

PLACE_NEAR=J1800.57:28mm

XDP

SOT563

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

6

73

41

6

16 73

6

73

8

17 73

6

73

6

73

6

73

SYNC_MASTER=WFERRY_J43

CPU/PCH Merged XDP

SYNC_DATE=12/21/2012

BOM_COST_GROUP=CPU SUPPORT

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<15>

XDP_SYS_PWROK

XDP_CPU_TMS

CPU_CFG<11>

CPU_CFG<3>

CPU_CFG<12>

CPU_PWR_DEBUG

CPU_CFG<4>

ALL_SYS_PWRGD

XDP_PCH_TMS

XDP_PCH_TRST_L

XDP_CPU_TCK

XDP_BPM_L<6>

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PCH_JTAGX

XDP_PCH_TDI

XDP_CPU_TDO

XDP_PCH_TDO

=PP1V05_S0_CPU_VCCST

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

CPU_CFG<0>

CPU_CFG<2>

XDP_BPM_L<1>

CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

=SMBUS_XDP_SCL XDP_PCH_TCK

CPU_VCCST_PWRGD

XDP_CPU_PWRBTN_L

PM_PWRBTN_L

PCH_JTAGX

PM_PCH_SYS_PWROK

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<13>

CPU_CFG<14>

XDP_CPURST_L

PLT_RESET_L

XDP_PCH_TRST_L

CPU_CFG<10>

XDP_PCH_TCK

XDP_CPU_VCCST_PWRGD

SSD_PCIE_SEL_L

USB_EXTA_OC_L

USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

JTAG_ISP_TCK

LPCPLUS_GPIO

XDP_MLB_RAMCFG0

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_MLB_RAMCFG1

XDP_SSD_PCIE1_SEL_L

XDP_PCH_GPIO76

=SMBUS_XDP_SDA

JTAG_ISP_TDI

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE2_SEL_L

XDP_PCH_GPIO17

XDP_SSD_PCIE3_SEL_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

=PP1V05_SUS_PCH_JTAG

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_TRST_L

XDP_PCH_TDO

=PP1V05_S0_XDP

XDP_BPM_L<0>

CPU_CFG<1>

XDP_CPU_TDI

XDP_CPU_PRESENT_L

XDP_PCH_TDI

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TMS

XDP_DBRESET_L

=PP5V_S0_XDPJTAGISOL =PP3V3_S5_XDPJTAGISOL

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_LPCPLUS_GPIO

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

C1801

1

2

C1800

1

2

R1805

12

R1813

21

R1804

12

R1802

12

R1800

12

J1800

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

61

62

6364

78 9

TP1806

1

TP1807

1

TP1805

1

TP1804

1

TP1803

1

TP1802

1

R1830

1

2

R1810

12

R1831

1

2

R1896

21

R1892

21

R1891

21

R1890

21

R1899

21

R1835

12

TP1870

1

TP1874

1

TP1876

1

TP1877

1

TP1878

1

R1881

12

R1882

12

R1883

12

R1884

12

TP1887

1

C1804

1

2

C1806

1

2

R1897

21

U1845

2

3

1

5

6

4

C1845

1

2

R1845

1

2

TP1873

1

TP1886

1

Q1840

3

5

4

Q1840

6

2

1

Q1842

3

5

4

Q1842

6

2

1

16 OF 82

dvt1

051-1573

8.0.0

18 OF 120

75

12 16 73

12 16

6

16 73

12 16 73

6

16 73

12 16 73

6 8

15 17 55 68

75

12 16 73

73

68

73

68

73

OUT

IN

BIIN

OUT

IN

OUT

NC

NC NC

OUT

IN

NC

OUT

IN

NC

AY

NC NC

VCC

GND

NC

IN

OUT

IN

Y

A

B

08

Y

A

B

08

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC NC

VER 3

D

SG

VER 3

D

SG

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH ME Disable Strap

SMC controls strap enable to allow in-field control of strap setting.

PCH PWROK Generation

Must be powered if any VDDIO is powered.

This looks a little ugly to support

For SB RTC Power

to reduce VBAT draw.

+V3.3A should be first

create VDD_RTC_OUT.

internally ORed to

VBAT and +V3.3A are

Coin-Cell: VBAT (300-ohm & 10uF RC)

Coin-Cell & G3Hot: 3.42V G3Hot

GreenCLK 25MHz Power

Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

No bypass necessary

PCH 24MHz Outputs

CAM XTAL Power

PCH Reset Button

IPD = 9-50k

VCCST (1.05V S0) PWRGD

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

33uW when driven-low

Vih(min) = 1.8V

TPS51916 I(leak) = +/- 1uA,

WF: Do we need this?

available ~3.3V power

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

No Coin-Cell: 3.42V G3Hot (no RC)

PCH 24MHz Crystal

NOTE: 30 PPM or better required for RTC accuracy

TBT XTAL Power

System RTC Power Source & 32kHz / 25MHz Clock Generator

12 75

25 74

6.3V X5R

1UF

20%

0201

6.3V

20%

1UF

X5R 0201

25V

CERM

0201

12PF

5%

25V CERM 0201

12PF

5%

38

201

1/20W

MF

22

PLACE_NEAR=U0500.AN15:5.1mm

5%

12 75

13 38 71 75 16 75

16V

0.1UF

X5R-CERM

10%

0201

MF

0

1/20W

0201

5%

NO STUFF

201

1/20W MF

1M

5%

0

1/20W

MF

XDP

5%

0201

0

1/16W MF-LF

SILK_PART=SYS RESET

NO STUFF

5%

402

201

1/20W MF

10K

5%

201

1/20W MF

100K

5%

1K

5%

201

1/20W MF

12 75

38

0.1UF

10% 16V

X5R-CERM

0201

34 74

201

1/20W MF

1M

5%

0

1/20W

MF

0201

5%

C0G

6.8PF

+/-0.1PF

25V

0201

6.8PF

C0G

+/-0.1PF

25V

0201

12 75

12

8

16 73

201

1/20W MF

10K

5%

16V

X5R-CERM

10%

0.1UF

0201

13 18 38 64 66 71

201

1/20W MF

330K

5%

SOT891

74AUP1G07GF

0.1UF

10% 16V

X5R-CERM

0201

6

57

26 27 38 39 75

16 17 38 64

74LVC2G08GT/S505

SOT833

BYPASS=U1950::5MM

X5R-CERM

10% 16V

0.1UF

0201

74LVC2G08GT/S505

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

0

1/20W

MF

0201

5%

0

1/20W MF

NO STUFF

0201

5%

1/20W

201

MF

1K

5%

13 16 38 75

13 75

13

0

1/20W

MF

NO STUFF

0201

5%

201

1/20W

MF

10K

5%

201

1/20W

MF

10K

5%

8

55

8

55

201

1/20W

MF

NO STUFF

100K

5%

74AUP1G09

SOT891

CRITICAL

SLG3NB148CV

CRITICAL

TQFN

CKPLUS_WAIVE=PwrTerm2Gnd

CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

OMIT

CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

DMN5L06VK-7

SOT563

SIGNAL_MODEL=DMN5L06VK_7

SOT563

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

Chipset Support

SYNC_DATE=01/30/2013SYNC_MASTER=J41

BOM_COST_GROUP=CPU SUPPORT

197S0480

Y1905

1

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

CPU_VCCST_PWRGD

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

SYSCLK_CLK25M_X1

=PP3V3_S3RS0_SYSCLKGEN

LPC_CLK_SMC

=PPVDDIO_S3RS0_CAMCLK

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_X2_R

=PPVRTC_G3_OUT

=PP3V3_S0_SB_PM

CPUVR_PGOOD_R

PM_PCH_APWROK

PM_S0_PGOOD

PM_PCH_SYS_PWROK

=DDRVTT_EN

=PP3V3_S0_MEM_VTTPWRCTL

=PP1V2_S3_MEM_VTTPWRCTL

=PP5V_S0_PCH_STRAP

SYS_PWROK_R

LPC_CLK24M_SMC_R

PCH_CLK24M_XTALOUT

HDA_SDOUT_R

=PP3V3_S0_SB_PM

PM_SYSRST_L

XDP_DBRESET_L

=PP3V42_G3H_CSPWRGD

CPUVR_PGOOD

CPU_VR_EN

ALL_SYS_PWRGD

SMC_DELAYED_PWRGD

=PP1V05_S0_CPU_VCCST

=PP3V3_S5_CSPWRGD

ALL_SYS_PWRGD

PCH_CLK24M_XTALOUT_R

=PPVBAT_G3H_SYSCLK

=PPVDDIO_TBTLC_CLK

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2

=PP3V3_S5_SYSCLK

PM_SLP_S3_L

SYSCLK_CLK25M_X2

PCH_CLK24M_XTALIN

CPU_MEMVTT_PWR_EN_LSVDDQ

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

SPI_DESCRIPTOR_OVERRIDE_LS5V

MAKE_BASE=TRUE

CPU_VR_READY

MEMVTT_PWR_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_RTC_CLK32K_RTCX2

LPC_CLK24M_SMC

MAKE_BASE=TRUE

PM_PCH_PWROK

MAKE_BASE=TRUE

C1902

1

2

C1910

1

2

C1905

12

C1906

12

R1927

12

C1924

1

2

R1905

12

R1906

1

2

R1996

12

R1997

1

2

R1995

1

2

R1920

1

2

R1921

1

2

C1922

1

2

R1916

1

2

R1915

12

C1915

12

C1916

12

R1931

1

2

C1930

1

2

R1970

1

2

U1970

2

3

1

5

6

4

C1970

1

2

U1950

1

2

4

8

7

C1950

1

2

U1950

5

6

4

8

3

R1963

2

1

R1960

2

1

R1962

12

R1951

12

R1950

1

2

R1955

1

2

R1961

1

2

U1930

2

1

36

4

U1900

9 8 15

12

71016

17

5

13

11

6

14

1

4

3

Y1915

24

13

Y1905

24

13

Q1920

3

5

4

Q1920

6

2

1

dvt1

051-1573

8.0.0

19 OF 120

17 OF 82

5

2

74

18

33

74

68

17 68

75

68

75

17 68

68

6 8

15 16 55 68

68

16 17 38 64

75

68

18 68

74

8

11 63

71 75

OUT

IN

OUT

IN

OUT

IN

OUT

YA

B

NC

GND

VCC

NC

IN

OUT

IN

OUT

IN

OUT

VCC

1A 1Y

2A 2Y

GND

IN

OUT

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(For development only)

Power State Debug LEDs

To SMC

Buffered

Scrub for Layout Optimization

Platform Reset Connections

To PCH

From RR

From PCH

and TDI as well for PCH glitch-prevention.

S0 pull-up on PCH page

GreenCLK 25MHz Power

SDCONN_STATE_CHANGE Isolation

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

R2041/2 should be stuffed for

MAKE_BASE

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

THUNDERBOLT PULL-UP

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

Pull-downs for chip-down RAM systems

RAM Configuration Straps

Multi-router designs also require different circuitry.

different isolation techniques will likely be necessary.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

Pin N61 needs a TP for Power to perform iFDIM test

Isolation ensures no leakage to RR or PCH

TBTLC can be on when S0 is off, and vice-versa

Redwood Ridge JTAG Isolation

Renaming the pins N61 and P61 to remove automatic diffpari property

S0 pull-up on PCH page

To PCH

To RR

RAMCFG3:L

201

5%

1/20W

MF

10K

RAMCFG2:L

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

RAMCFG1:L

1/20W

RAMCFG0:L

5%

201

MF

10K

DBGLED

PLACE_SIDE=BOTTOM

LTQH9G-SM

SILK_PART=S5_ON

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

DBGLED

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

GREEN-56MCD-2MA-2.65V

DBGLED

1/20W

5%

201

MF

20K

PLACE_SIDE=BOTTOM

1/16W

5%

402

MF-LF

0

DBGLED

1/20W

5%

201

MF

20K

DBGLED

LTQH9G-SM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

1/20W

5%

201

MF

20K

LTQH9G-SM

DBGLED

SILK_PART=S0I3_ON

PLACE_SIDE=BOTTOM

GREEN-56MCD-2MA-2.65V

5%

201

20K

DBGLED

1/20W

MF

15 16

64

13 31 37 38 64 66

13 17 38 64 66 71

1/20W

201

20K

MF

5%

DBGLED

SILK_PART=S0_ON

PLACE_SIDE=BOTTOM

DBGLED

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

13 38

16V

10%

0201

X5R-CERM

0.1UF

MC74VHC1G08

CRITICAL

SC70-HF

201

MF

5% 1/20W

100K

1/20W

MF

0201

5%

0

13 15 16

38

15

MF

201

5%

1/20W

100K

25 75

0201

NO STUFF

1/20W

MF

5%

0

15 33

15

16

CERM-X5R

0.1UF

BYPASS=U2030.5::5MM

0201

6.3V

10%

74AUP1G09

SOT891

CRITICAL

1/20W

470K

201

MF

5%

201

5% 1/20W MF

470K

66

25

0201

1/20W

0

MF

5%

NOSTUFF

15

BYPASS=U2030::3mm

0201

10% 10V

X5R-CERM

0.1UF

33

1/20W

5%

0201

MF

0

1/20W

0201

5% MF

0

NO STUFF

I1608

1/20W

MF

0201

5%

0

NO STUFF

25

15

1/20W

100K

5%

201

MF

10V

20%

402

CERM

0.1UF

MF

5%

201

1/20W

100K

25

15

SOT891

74LVC2G07

16

25

DMN5L06VK-7

SOT563

DMN5L06VK-7

DBGLED

SOT563

DMN5L06VK-7

DBGLED

SOT563

DMN5L06VK-7

SOT563

DBGLED

DMN5L06VK-7

DBGLED

SOT563

MC74VHC1G08

SC70-HF

CRITICAL

BYPASS=U2030::3mm

X5R-CERM

0.1UF

0201

10V

10%

BYPASS=U2030::3mm

201

MF

5%

1/20W

10K

201

1/20W

MF

5%

33

BOM_COST_GROUP=CPU SUPPORT

SYNC_MASTER=J41

Project Chipset Support

SYNC_DATE=10/23/2012

TRUE

TBT_CIO_PLUG_EVENT_L

=PP3V3_S0_PCH_GPIO

PP3V3_TBTLC

JTAG_TBT_TMS

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2

JTAG_ISP_TDO

JTAG_TBT_TCK

JTAG_TBT_TDI

MAKE_BASE=TRUE

TP_CPU_RSVDN61

TP_CPU_RSVDP61

MAKE_BASE=TRUE

=TBT_CIO_PLUG_EVENT

=PP3V3_S3RS0_SYSCLKGEN

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM

=PP3V3_S3_SYSCLKGEN

=PP3V3_S5_SYSCLK

=PP3V3_S0_SYSCLKGEN

JTAG_TBT_TDO

JTAG_TBT_TMS_PCH

TP_CPU_RSVD_P61

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TCK

MAKE_BASE=TRUE

TP_CPU_RSVD_N61

=PP3V3_S4_SMC

SDCONN_STATE_CHANGE_RIO

XDP_MLB_RAMCFG3

CAMERA_PWR_EN

CAMERA_PWR_EN_R

=PP3V3_S4_CAMPWREN

CAMERA_PWR_EN_PCH

SMC_PME_SDCONN

=PP3V3_S3_SDBUF

=SMC_PME_SDCONN_L

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S5_DBGLED

DBGLED_S0

CAMERA_PWR_EN_RC

=PP3V3_S3RS0_CAMPWREN

DBGLED_S0_D

PM_SLP_S0_L

SDCONN_STATE_CHANGE_L

SMC_PME_S4_DARK_L

=PP3V3_S0_RSTBUF

PLT_RESET_L

SMC_LRESET_L

TBT_PCIE_RESET_L

CAM_PCIE_RESET_L

PLT_RST_BUF_L

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

DBGLED_S4 DBGLED_S3

DBGLED_S0I3

DBGLED_S0I3_D

PM_SLP_S3_L

DBGLED_S3_D

PM_SLP_S4_L

DBGLED_S4_D

S4_PWR_EN

=PP3V3_S5_DBGLEDS

DBGLED_S5

R2050

1

2

R2051

1

2

R2052

1

2

R2053

1

2

D2090

A

K

D2091

A

K

R2090

1

2

R2094

12

R2091

1

2

D2092

A

K

R2092

1

2

D2093

A

K

R2093

1

2

R2095

1

2

D2095

A

K

C2071

1

2

U2071

3

2

1

4

5

R2070

1

2

R2072

12

R2015

1

2

R2089

12

C2031

1

2

U2031

2

1

36

4

R2031

1

2

R2032

1

2

R2030

12

C2030

1

2

R2042

12

R2040

12

R2041

12

R2061

1

2

C2060

1

2

R2062

1

2

U2060

1

6

3

4

25

Q2030

3

5

4

Q2090

3

5

4

Q2030

6

2

1

Q2090

6

2

1

Q2091

6

2

1

Q2091

3

5

4

U2030

3

2

1

4

5

C2034

1

2

R2034

1

2

R2033

12

dvt1

051-1573

8.0.0

20 OF 120

18 OF 82

5

12 13 15 26 65 68

25 26 68

17 68

68

8

39 40 68

68

15 44

38 39

68

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

6.36mV / step @ output

0.000V - 2.397V (0x00 - 0xBA)

LPDDR3 (1.2V)

VRef Dividers

CPU-Based Margining

NOTE: CPU has single output for VREFCA.

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

3.53mV / step @ output

+25uA - -25uA (- = sourced)

0.000V - 2.694V (0x00 - 0xD1)

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

+21uA - -21uA (- = sourced)

4.28mV / step @ output

VREFCA. Connected to 4 DRAMs.

Always used, regardless of margining option.

0.000V - 1.354V (0x00 - 0x69)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

+73uA - -73uA (- = sourced)

0.000V - 1.199V (0x00 - 0x5D)

0.300V - 0.900V (+/- 300mV)

MEM A VREF DQ

1.343V (DAC: 0x68)

LPDDR3 (1.2V)

Margined target:

DAC step size:

VRef current:

Nominal value

DAC range:

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

4

C

DDR3L (1.35V)

MEM B VREF CA

3

C

MEM A VREF CA

2

B

MEM B VREF DQ

A

1

PCA9557D Pin:

DAC Channel:

0.800V - 1.600V (+/- 400mV)

MEM VREG

D

5

1.200V (DAC: 0x5D)

DDR3L (1.35V)

0.972V - 1.714V (+/- 371mV)

0.600V (DAC: 0x2E.5)

7

76

7

76

7

76

1/20W

201

24.9

MF

1%

0.022UF

6.3V X5R-CERM 0201

10%

24.9

MF

201

1%

1/20W

6.3V

0.022UF

X5R-CERM 0201

10%

201

24.9

MF

1%

1/20W

0.022UF

X5R-CERM 0201

10%

6.3V

10

MF

201

1%

1/20W

MF

10

201

1%

1/20W

5.1

MF

0201

1%

8.2K

MF 201

1% 1/20W

PLACE_NEAR=R2221.2:1mm

8.2K

MF

201

1%

1/20W

8.2K

MF 201

1% 1/20W

8.2K

MF

201

1%

1/20W

PLACE_NEAR=R2241.2:1mm

8.2K

MF 201

1% 1/20W

PLACE_NEAR=R2261.2:1mm

8.2K

MF

201

1%

1/20W

LPDDR3 VREF Margining

SYNC_DATE=01/02/2013

SYNC_MASTER=YHARTANTO_J44

BOM_COST_GROUP=CPU SUPPORT

MEM_VREFDQ_B_RC

CPU_DIMM_VREFCA

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PPVREF_S3_MEM_VREFDQ_A

MEM_VREFDQ_A_RC

MEM_VREFCA_RC

CPU_DIMMA_VREFDQ

=PPDDR_S3_MEMVREF

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_DIMMB_VREFDQ

R2260

12

C2260

1

2

R2240

12

C2240

1

2

R2220

12

C2220

1

2

R2223

12

R2243

12

R2263

12

R2221

1

2

R2222

1

2

R2241

1

2

R2242

1

2

R2261

1

2

R2262

1

2

22 OF 120

dvt1

19 OF 82

8.0.0

051-1573

68

BI

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0 DM1 DM2

CS0*

DQ13

SYM 1 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

70

10UF

20% 25V

0603

X5R-CERM

0603

X5R-CERM

20% 25V

10UF

1UF

402

10V X5R

10%

70

10%

0.1UF

16V

0201

X5R-CERM

10V

1UF

10% X5R

402

10V

402

1UF

10% X5R

16V

10%

0.1UF

X5R-CERM 0201

X5R 402

10%

1UF

10V

70

10V X5R

1UF

10%

402

10V X5R 402

1UF

10%

25V

0603

10UF

20%

X5R-CERM

10%

1UF

X5R

10V

402

10%

X5R

10V

1UF

402

10%

402

X5R

10V

1UF

70

X5R-CERM

20%

0603

25V

10UF

X5R-CERM

20%

10UF

0603

25V

20%

0603

25V X5R-CERM

10UF

0603

X5R-CERM

25V

20%

10UF

10% X5R

10V

402

1UF

10%

1UF

X5R

10V

402

70

6.3V X5R

10%

201

0.047UF

10%

6.3V X5R

0.047UF

201

LPDDR3-1600-32GB

CRITICAL

FBGA

OMIT_TABLE

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

EDFB232A1MA

50V

CRITICAL

C0G-CERM

2%

12PF

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

70

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2% 50V

CRITICAL

0402

12PF

C0G-CERM

2%

CRITICAL

0402

50V

12PF

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

21 24 76

7

21 24 76

21 24 70 76

70

243

1%

1/20W

MF

201 201

MF

1/20W

243

1%

70

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel A (00-31)

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

=MEM_A_DQ<13>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_CAA<8>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

=MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQ<21>

MEM_A_CAA<9>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<2>

MEM_A_CAA<2>

MEM_A_ODT<0>

=MEM_A_DQS_N<0> =MEM_A_DQS_N<1>

=MEM_A_DQ<25>

MEM_A_CLK_N<0>

MEM_A_CAA<6>

MEM_A_CAA<0> MEM_A_CAA<1>

MEM_A_CAA<5>

MEM_A_CKE<1>

=MEM_A_DQ<0>

=MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<12>

=MEM_A_DQ<15> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23> =MEM_A_DQ<24>

=MEM_A_DQ<26> =MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQ<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<3>

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

MEM_A_CAA<7>

=MEM_A_DQ<22>

=MEM_A_DQ<1>

MEM_A_ZQ<0> MEM_A_ZQ<1>

=MEM_A_DQ<5>

=MEM_A_DQ<14>

MEM_A_CAA<4>

MEM_A_CAA<3>

=MEM_A_DQ<4>

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDQ

R2300

1

2

R2301

1

2

C2306

1

2

C2307

1

2

C2302

1

2

C2300

1

2

C2303

1

2

C2304

1

2

C2301

1

2

C2305

1

2

C2310

1

2

C2311

1

2

C2312

1

2

C2320

1

2

C2321

1

2

C2322

1

2

C2324

1

2

C2323

1

2

C2333

1

2

C2332

1

2

C2331

1

2

C2330

1

2

C2341

1

2

C2340

1

2

U2300

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9

J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

D4 D5 D6 G5 H5 H6

H12

J5

F2 G2 H3 L2 M2

A11 C12

K8 K11 L12

N8 N12 R12 U11

E8 E12 G12

H8

H9 H11

J9 J10

B2 B5

N4 N5 R4 R5 T2 T3 T4 T5 H2

C5 E4 E5 F5 J12 K2 L6 M5

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12

K10 L9 M6 M12 N6 P12 R6 T6 T12

C6 D12 E6 F6 F12 G6 G9 H10

U2300

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

J2

J3

K3 K4

L3 L4

L8 G8 P8 D8

P9 N9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11

N10

R8 R9 R10 R11 C11 C10 C9 C8 B11 B10

N11

B9 B8

M8 M9 M10 M11 F11 F10

L11

L10

G11

G10

P11

P10

D11

D10

C4 K9 R3

A1 A2

U12 U13

A12 A13

B1

B13

T1

T13

U1 U2

J8

H4

J11

B3 B4

C2334

1

2

C2335

1

2

C2336

1

2

C2337

1

2

C2338

1

2

C2339

1

2

20 OF 82

dvt1

8.0.0

051-1573

23 OF 120

20 21 22 23 68

21 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0 DM1 DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

LPDDR3 CHANNEL A (32-63)

PLACEMENT_NOTE:

Distribute evenly.

70

X5R-CERM

20%

10UF

0603

25V

10V X5R 402

10%

1UF

10V X5R 402

1UF

10%

10V

402

1UF

10% X5R

10UF

20% 25V X5R-CERM 0603

70

20 24 70 76

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

10%

201

0.047UF

X5R

6.3V

70

201

0.047UF

10% X5R

6.3V

25V

20%

10UF

X5R-CERM 0603

20% 25V

0603

10UF

X5R-CERM

25V

0603

10UF

20%

X5R-CERM

FBGA

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

EDFB232A1MA

LPDDR3-1600-32GB

OMIT_TABLE

FBGA

CRITICAL

EDFB232A1MA

70

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

0402

12PF

50V

CRITICAL

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

20 24 76

7

20 24 76

70

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

10V X5R 402

1UF

10%

10V X5R 402

1UF

10%

70

25V

0603

10UF

20% X5R-CERM

25V

0603

20%

X5R-CERM

10UF

10%

1UF

402

X5R

10V

0201

16V X5R-CERM

0.1UF

10%

1UF

402

X5R

10V

0201

10% X5R-CERM

16V

0.1UF

10%

1UF

402

X5R

10V

X5R 402

1UF

10% 10V

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel A (32-63)

MEM_A_CS_L<0>

MEM_A_CLK_N<1>

MEM_A_CS_L<1>

MEM_A_ZQ<2>

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_A_DQ<34>

=MEM_A_DQ<39>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<46>

=MEM_A_DQS_P<7>

=MEM_A_DQ<35>

=MEM_A_DQ<45>

=MEM_A_DQ<50>

=MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38>

=MEM_A_DQ<41>

=MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQ<61>

=MEM_A_DQ<59> =MEM_A_DQ<60>

=MEM_A_DQ<57> =MEM_A_DQ<58>

=MEM_A_DQ<56>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQ<47> =MEM_A_DQ<48>

=MEM_A_DQ<44>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<40>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

MEM_A_CAB<7>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_CKE<3>

MEM_A_CAB<5>

MEM_A_CAB<4>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAB<6>

MEM_A_ODT<0>

MEM_A_CAB<2>

MEM_A_CAB<9>

MEM_A_CLK_P<1>

MEM_A_CKE<2>

MEM_A_CAB<8>

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDDQ

MEM_A_ZQ<3>

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

C2430

1

2

C2431

1

2

C2410

1

2

C2411

1

2

C2432

1

2

C2412

1

2

C2420

1

2

C2400

1

2

C2421

1

2

C2401

1

2

C2422

1

2

C2402

1

2

C2423

1

2

C2403

1

2

C2404

1

2

C2405

1

2

C2406

1

2

R2400

1

2

R2401

1

2

C2440

1

2

C2441

1

2

C2433

1

2

C2407

1

2

C2424

1

2

U2400

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

J2

J3

K3 K4

L3 L4

L8 G8 P8 D8

P9 N9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11

N10

R8 R9 R10 R11 C11 C10 C9 C8 B11 B10

N11

B9 B8

M8 M9 M10 M11 F11 F10

L11

L10

G11

G10

P11

P10

D11

D10

C4 K9 R3

A1 A2

U12 U13

A12 A13

B1

B13

T1

T13

U1 U2

J8

H4

J11

B3 B4

U2400

A3

A4

A5

A6 A10

U3

U4

U5

U6 U10

A8

A9

J6

K5

K6 K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6 H12

J5

F2

G2

H3

L2

M2

A11 C12

K8 K11 L12

N8 N12 R12 U11

E8 E12 G12

H8

H9 H11

J9 J10

B2 B5

N4 N5 R4 R5 T2 T3 T4 T5 H2

C5 E4 E5 F5 J12 K2 L6 M5

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12

K10 L9 M6 M12 N6 P12 R6 T6 T12

C6 D12 E6 F6 F12 G6 G9 H10

C2434

1

2

C2435

1

2

C2436

1

2

C2437

1

2

dvt1

8.0.0

051-1573

21 OF 82

24 OF 120

20 21 22 23 68

20 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0 DM1 DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Distribute evenly.

10uF caps are shared between DRAM.

LPDDR3 CHANNEL B (0-31)

PLACEMENT_NOTE:

70

20%

X5R-CERM

10UF

0603

25V

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

X5R-CERM

25V

20%

10UF

0603

70

23 24 70 76

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

0.047UF

X5R

6.3V

10%

201

0.047UF

10% X5R

6.3V

70

10UF

20%

0603

25V X5R-CERM

25V

0603

10UF

20% X5R-CERM

10UF

0603

25V X5R-CERM

20%

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

FBGA

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

EDFB232A1MA

12PF

50V

CRITICAL

0402

2% C0G-CERM

12PF

50V

CRITICAL

0402

2% C0G-CERM

70

12PF

50V

CRITICAL

0402

2% C0G-CERM

12PF

50V

CRITICAL

0402

2% C0G-CERM

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

23 24 76

7

23 24 76

70

10V X5R 402

1UF

10%

10V X5R 402

1UF

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

70

X5R-CERM

20%

10UF

0603

25V

X5R-CERM

20%

10UF

0603

25V

X5R 402

1UF

10% 10V

10% 16V

0201

X5R-CERM

0.1UF

10V X5R 402

1UF

10%

X5R-CERM

16V

10%

0201

0.1UF

10% 10V X5R 402

1UF

10%

1UF

402

X5R

10V

BOM_COST_GROUP=DRAM

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel B (00-31)

MEM_B_CS_L<0>

MEM_B_ODT<0>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_B_DQ<10>

MEM_B_CLK_P<0>

=MEM_B_DQ<22>

=MEM_B_DQ<14>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<16>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<26>

=MEM_B_DQ<23>

=MEM_B_DQ<28>

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<11>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQ<27>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<15>

=MEM_B_DQ<13>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=PP1V2_S3_MEM_VDDQ

MEM_B_ZQ<1>

MEM_B_ZQ<0>

MEM_B_CAA<7>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_CKE<1>

MEM_B_CAA<5>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_CAA<6>

MEM_B_CLK_N<0>

MEM_B_CAA<2>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CAA<8>

MEM_B_CS_L<1>

=PP1V2_S3_MEM_VDDCA

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

C2530

1

2

C2531

1

2

C2510

1

2

C2511

1

2

C2532

1

2

C2512

1

2

C2520

1

2

C2500

1

2

C2521

1

2

C2501

1

2

C2522

1

2

C2502

1

2

C2523

1

2

C2503

1

2

C2504

1

2

C2505

1

2

C2506

1

2

R2500

1

2

R2501

1

2

C2540

1

2

C2541

1

2

C2533

1

2

C2507

1

2

C2524

1

2

U2500

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

J2

J3

K3 K4

L3 L4

L8 G8 P8 D8

P9 N9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11

N10

R8 R9 R10 R11 C11 C10 C9 C8 B11 B10

N11

B9 B8

M8 M9 M10 M11 F11 F10

L11

L10

G11

G10

P11

P10

D11

D10

C4 K9 R3

A1 A2

U12 U13

A12 A13

B1

B13

T1

T13

U1 U2

J8

H4

J11

B3 B4

U2500

A3

A4

A5

A6 A10

U3

U4

U5

U6 U10

A8

A9

J6

K5

K6 K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6 H12

J5

F2

G2

H3

L2

M2

A11 C12

K8 K11 L12

N8 N12 R12 U11

E8 E12 G12

H8

H9 H11

J9 J10

B2 B5

N4 N5 R4 R5 T2 T3 T4 T5 H2

C5 E4 E5 F5 J12 K2 L6 M5

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12

K10 L9 M6 M12 N6 P12 R6 T6 T12

C6 D12 E6 F6 F12 G6 G9 H10

C2534

1

2

C2535

1

2

C2536

1

2

C2537

1

2

051-1573

8.0.0

dvt1

25 OF 120

22 OF 82

20 21 22 23 68

23 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0 DM1 DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM. Distribute evenly.

PLACEMENT_NOTE:

LPDDR3 CHANNEL B (32-63)

70

X5R-CERM

20%

10UF

0603

25V

10V X5R 402

1UF

10%

10V X5R 402

10%

1UF

X5R

1UF

402

10V

10%

X5R-CERM

10UF

20% 25V

0603

22 24 70 76

70

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

X5R 201

0.047UF

6.3V

10%

201

0.047UF

10% X5R

6.3V

70

20% X5R-CERM

25V

0603

10UF

0603

20%

10UF

25V X5R-CERM

X5R-CERM 0603

10UF

20% 25V

0603

20% 25V X5R-CERM

10UF

EDFB232A1MA

FBGA

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

70

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

22 24 76

7

22 24 76

70

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

10V X5R 402

1UF

10%

402

X5R

10V

1UF

10%

70

25V

0603

10UF

20% X5R-CERM

10%

1UF

402

X5R

10V

16V X5R-CERM

0.1UF

10%

0201

10%

1UF

402

X5R

10V

X5R-CERM

16V

0201

10%

0.1UF

10%

1UF

402

X5R

10V

10% 10V X5R 402

1UF

LPDDR3 DRAM Channel B (32-63)

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

BOM_COST_GROUP=DRAM

MEM_B_ODT<0>

MEM_B_ZQ<2> MEM_B_ZQ<3>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_B_DQ<51>

=MEM_B_DQS_P<7>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<47>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

MEM_B_CAB<7>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_CKE<3>

MEM_B_CAB<5>

MEM_B_CAB<4>

MEM_B_CAB<3>

MEM_B_CAB<1>

MEM_B_CAB<0>

MEM_B_CAB<6>

MEM_B_CLK_N<1>

MEM_B_CAB<2>

MEM_B_CAB<9>

MEM_B_CKE<2>

MEM_B_CAB<8>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

=PP1V2_S3_MEM_VDDCA

=MEM_B_DQ<46>

=PP1V2_S3_MEM_VDDCA

=MEM_B_DQS_N<5>

=PP1V8_S3_MEM

MEM_B_CLK_P<1>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDD2

C2630

1

2

C2631

1

2

C2610

1

2

C2611

1

2

C2632

1

2

C2620

1

2

C2600

1

2

C2621

1

2

C2601

1

2

C2622

1

2

C2602

1

2

C2623

1

2

C2603

1

2

C2604

1

2

C2605

1

2

C2606

1

2

R2600

1

2

R2601

1

2

C2640

1

2

C2641

1

2

C2633

1

2

C2607

1

2

C2624

1

2

C2612

1

2

U2600

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

J2

J3

K3 K4

L3 L4

L8 G8 P8 D8

P9 N9

F9 F8 E11 E10 E9 D9 T8 T9 T10 T11

N10

R8 R9 R10 R11 C11 C10 C9 C8 B11 B10

N11

B9 B8

M8 M9 M10 M11 F11 F10

L11

L10

G11

G10

P11

P10

D11

D10

C4 K9 R3

A1 A2

U12 U13

A12 A13

B1

B13

T1

T13

U1 U2

J8

H4

J11

B3 B4

U2600

A3

A4

A5

A6 A10

U3

U4

U5

U6 U10

A8

A9

J6

K5

K6 K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6 H12

J5

F2

G2

H3

L2

M2

A11 C12

K8 K11 L12

N8 N12 R12 U11

E8 E12 G12

H8

H9 H11

J9 J10

B2 B5

N4 N5 R4 R5 T2 T3 T4 T5 H2

C5 E4 E5 F5 J12 K2 L6 M5

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12

K10 L9 M6 M12 N6 P12 R6 T6 T12

C6 D12 E6 F6 F12 G6 G9 H10

C2634

1

2

C2635

1

2

C2636

1

2

C2637

1

2

26 OF 120

051-1573

8.0.0

dvt1

23 OF 82

20 21 22 23 68

22 68 76

20 21 22 23 68

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

CERM-X5R-1

20%

0.47UF

201

4V

0.47UF

20% CERM-X5R-1

201

CERM-X5R-1 201

4V

0.47UF

20%

4V CERM-X5R-1

20%

0.47UF

201

CERM-X5R-1

20% 4V

0.47UF

20% CERM-X5R-1

201

4V

0.47UF

CERM-X5R-1

0.47UF

201

20% 4V

201

0.47UF

20% 4V CERM-X5R-1

0.47UF

4V

20% CERM-X5R-1

201

20 70 76

7

20 76

7

20 76

7

20 76

7

21 76

21 70 76

20 70 76

7

20 76

20 70 76

21 70 76

20 70 76

21 70 76

20 70 76

21 70 76

CERM-X5R-1

0.47UF

201

4V

20%

22 70 76

CERM-X5R-1

4V 201

20%

0.47UF

CERM-X5R-1 201

20% 4V

0.47UF

CERM-X5R-1 201

20% 4V

CERM-X5R-1 201

0.47UF

20% 4V

0.47UF

20% 4V

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

0.47UF

201

20% 4V

CERM-X5R-1 201

20% 4V

0.47UF

201

CERM-X5R-1

0.47UF

4V

20%

CERM-X5R-1 201

0.47UF

20% 4V

22 70 76

7

22 76

7

22 76

7

22 76

7

22 76

22 70 76

23 70 76

7

23 76

7

23 76

7

23 76

7

23 76

23 70 76

7

21 76

7

21 76

7

21 76

23 70 76

7

22 23 76

7

22 23 76

22 23 70 76

20 70 76

7

20 21 76

7

20 21 76

20 21 70 76

201 MF1%

1/20W

56

MF201

39

1%

1/20W

39

MF1%

1/20W

201

82

MF1%

1/20W

201

82

1%

1/20W

201 MF 201 MF

56

1%

1/20W

201 MF

56

1%

1/20W

1/20W39201 MF1%

MF

1/20W392011%

1%

201

1/20W

MF

82

1% 201

1/20W82MF

20156MF

1/20W

1%

1% 20182MF

1/20W

1% MF201

82

1/20W

82

1% 201 MF

1/20W

56

1% 201 MF

1/20W

39

1% 201 MF

1/20W

1% 201 MF

1/20W

39

1/20W

1% 20182MF

2011%

1/20W

MF

82

1/20W

56

1% MF201

56

1/20W

MF2011%

MF

1/20W

2011%

39

1/20W

MF2011%

39

MF

1/20W

2011%

82 82

MF2011%

1/20W

56

1% MF

1/20W

201

2011%

1/20W82MF

1% 201

1/20W

MF

82

1% 20182MF

1/20W

201

1/20W

MF1%

56

1%

56

201 MF

1/20W

603

22UF

CRITICAL

X5R-CERM-1

6.3V

20%

X5R-CERM-1

CRITICAL

20%

603

22UF

6.3V

MF2011%

1/20W

56

201 MF1%

1/20W

56

MF201

1/20W

1%

56

1%

1/20W

MF201

56

MF2011%

1/20W

56

201

1/20W

MF1%

56

MF201

1/20W

56

1%

1/20W

MF562011%

201

1/20W56MF1%

201

1/20W

MF

56

1%

56

MF

1/20W

2011%

1%561/20W

201 MF

1%

56

201

1/20W

MF

1%561/20W

MF201

56

1% 201 MF

1/20W

1%

56

MF

1/20W

201

1% MF

1/20W

201

56

1/20W

1% MF201

56

1/20W

1% MF201

56

201

56

1/20W

MF1%

56

201

1/20W

MF1%

56

1% 201 MF

1/20W

56

201 MF1%

1/20W

56

201 MF1%

1/20W

56

201 MF1%

1/20W

201 MF1%561/20W

1%

56

201

1/20W

MF

201

1/20W

MF

56

1% 1%

56

201 MF

1/20W

1%

56

201 MF

1/20W

12PF

0201

NP0-C0G

5% 25V

0201

NP0-C0G

25V

5%

12PF

LPDDR3 DRAM Termination

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

BOM_COST_GROUP=DRAM

=PP0V6_S0_MEM_VTT_A

MEM_B_CAB<5>

MEM_B_ODT<0>

MEM_B_CS_L<1>

MEM_B_CAB<4>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAA<0>

MEM_B_CAA<4>

MEM_B_CAB<0>

MEM_B_CAB<2>

MEM_B_CAB<9>

MEM_A_CAB<6>

MEM_A_CAA<2>

MEM_A_CAA<4>

MEM_A_CLK_N<1>

MEM_B_CAB<1>

MEM_A_CLK_P<1>

MEM_A_CAB<5>

MEM_A_CAB<8>

MEM_A_CAA<3>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CAB<0>

MEM_A_ODT<0>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CKE<2>

MEM_B_CLK_P<0>

MEM_B_CAB<3>

MEM_A_CLK_P<0>

MEM_A_CAA<5>

MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_A_CKE<3>

MEM_A_CAB<7>

MEM_A_CAA<1> MEM_B_CAA<1>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_A_CAA<9> MEM_A_CAA<8> MEM_A_CAA<6> MEM_A_CAA<7>

MEM_A_CAA<0> MEM_A_CAB<9>

MEM_B_CKE<2>

MEM_B_CLK_N<1>

MEM_B_CAA<6>

MEM_B_CAA<7>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<1>

MEM_B_CAA<8>

MEM_B_CAA<5>

MEM_A_CAB<4>

MEM_A_CS_L<1>

MEM_A_CAB<1>

MEM_A_CS_L<0>

=PP0V6_S0_MEM_VTT_B

C2702

1

2

C2704

1

2

C2700

1

2

C2701

1

2

C2703

1

2

C2706

1

2

C2705

1

2

C2707

1

2

C2709

1

2

C2708

1

2

C2712

1

2

C2714

1

2

C2716

1

2

C2718

1

2

C2719

1

2

C2717

1

2

C2715

1

2

C2713

1

2

C2711

1

2

C2710

1

2

R2704

12

R2705

12

R2706

12

R2707

12

R2708

12

R2709

12

R2710

12

R2719

12

R2720

12

R2721

12

R2722

12

R2723

12

R2728

12

R2729

12

R2730

12

R2744

12

R2745

12

R2746

12

R2747

12

R2748

12

R2749

12

R2750

12

R2759

12

R2760

12

R2761

12

R2762

12

R2763

12

R2768

12

R2769

12

R2770

12

R2714

12

R2754

12

C2720

1

2

C2740

1

2

R2700

12

R2701

12

R2702

12

R2703

12

R2712

12

R2713

12

R2711

12

R2718

12

R2717

12

R2716

12

R2715

12

R2724

12

R2725

12

R2726

12

R2727

12

R2740

12

R2741

12

R2742

12

R2743

12

R2751

12

R2752

12

R2753

12

R2755

12

R2756

12

R2757

12

R2758

12

R2764

12

R2765

12

R2766

12

R2767

12

C2730

1

2

C2731

1

2

dvt1

051-1573

8.0.0

27 OF 120

24 OF 82

68 68

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1 PETN_1

PETP_2

RSENSE

PETN_2

PETP_3 PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1 PERN_1

PERP_2 PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK TDO TEST_EN TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI TMS

PERN_0

PERP_3

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Security strap setting is XORed with

Use AA8 GND ball for THERM_DN

depends on the code in the flash.

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

4 - GPIO_5

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15 9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14 11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

bit in the flash, so the active-level

If strap != bit then security is enabled?

Used for straps in host mode

5%

3.3K

201

1/20W

MF

13

67

201

1/20W MF

5%

100

28

28 71 77

28

28 71 77

29

29 71 77

29

29 71 77

5%

100K

201

1/20W

MF

5%

100K

201

1/20W

MF

28 77

5%

3.3K

201

1/20W MF

10% 16V X5R-CERM

0.1UF

0201

13 77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

16V10%

X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

16V10%

0.1UF

X5R-CERM

0201

10% 16V X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

MF

1/20W

201

1%

1K

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V

0.1UF

X5R-CERM

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V X5R-CERM

0.1UF

0201

10% 16V

0.1UF

X5R-CERM

0201

67 77

402

CERM

6.3V

10%

1UF

BYPASS=U2890::2mm

67 77

28

29

18

29 77

29

18

28 77

28

25 27 28

28

25 28

25 29 30

29

25 29

25 26

39

12

17 74

806

1%

1/20W

201

MF

201

1/20W

5%

1K

MF

201

10K

1/20W

5% MF

NO STUFF

12 71 81

26

0201

OMIT

NONE

NOSTUFF

NONE

MF

1/20W

201

10K

5% 5%

1/20W MF 201

10K

MF

1/20W

201

5%

NO STUFF

MF

1/20W

201

10K

5%

NO STUFF

5%

201

1/20W

MF

100K

15

25 30

18 75

100K

MF

1/20W

201

5%

CRITICAL OMIT_TABLE

W25X40CLXIG

USON

4MBIT

25 27

25 28 29

MF

1/20W

201

10K

5% 5%

201

1/20W MF

10K

NO STUFF

5%

10K

1/20W MF 201

5%

201

1/20W MF

10K

100K

5%

201

1/20W

MF

5% MF

1/20W

201

10K

5%

201

1/20W

MF

100K

5%

201

1/20W MF

25 69

5%

201

1/20W

MF

100K 100K

MF

1/20W

201

5%

100K

MF

1/20W

201

5%

FALCON RIDGE

OMIT_TABLE

CRITICAL

FCBGA

X5R-CERM

16V

10%

0201

0.1UF

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

10%

0201

0.1UF

X5R-CERM

16V

10%

0201

5%

3.3K

201

1/20W

MF

16V

0201

X5R-CERM

10%

0.1UF

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

10%

0201

0.1UF

X5R-CERM

10% 16V

0.1UF

0201

10% 16V

X5R-CERM

0201

0.1UF

X5R-CERM

10% 16V

5%

3.3K

201

1/20W MF

0201

0.1UF

X5R-CERM

10% 16V

0201

10% 16V

X5R-CERM

0.1UF

0201

X5R-CERM

0.1UF

10% 16V

X5R-CERM

0201

0.1UF

10% 16V

0201

X5R-CERM

16V10%

0.1UF

14 71 81

BOM_COST_GROUP=TBT

SYNC_MASTER=T29_RR

SYNC_DATE=01/19/2013

Thunderbolt Host (1 of 2)

TBT_SPI_MOSI

DP_TBTSRC_HPD

TP_DP_TBTSRC_ML_CN<3>

DP_TBTSRC_HPD

=PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

=PP3V3_S4_TBT

=TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L

TBTROM_HOLD_L

PCIE_TBT_D2R_P<2>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_C_P<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_R2D_C_P<3>

DP_TBTSNK0_ML_C_P<0>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

TBT_A_HV_EN

TBT_B_DP_PWRDN

PP3V3_TBTLC

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<0>

PP3V3_TBTLC

PCIE_TBT_R2D_P<3>

JTAG_TBT_TMS

JTAG_TBT_TDI

TBT_PCIE_RESET_L

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

JTAG_TBT_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP TBT_MONOBSN

TP_TBT_MONDC0 TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

DP_TBTPB_AUXCH_C_P

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_P<1>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

TBTDP_AUXIO_EN TBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_BUF

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_B_D2R_P<0>

=TBT_BATLOW_L

HDMITBTMUX_SEL_TBT

=TBT_WAKE_L

TBT_PWR_EN

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CP<2>

TBT_GPIO2

TBT_RBIAS

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0>

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_N<3>

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<1>

TBT_B_R2D_C_N<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

TP_DP_TBTSRC_AUXCH_CP TP_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_R2D_N<0>

SYSCLK_CLK25M_TBT

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_R2D_P<2>

TP_TBT_THERM_DP

TP_TBT_XTAL25OUT

TBT_TMU_CLK_OUT

TBT_GPIO7

SYSCLK_CLK25M_TBT_R

PCIE_TBT_D2R_N<3>

PCIE_CLK100M_TBT_P

TP_TBT_PCIE_RESET0_L TBT_DFT_STRAP_1 TBT_ROM_SECURITY_XOR TBT_DFT_STRAP_3

TBT_CLKREQ_L

R2890

1

2

C2890

1

2

R2892

1

2

R2891

1

2

R2855

1

2

C2801

12

C2800

12

C2802

12

C2803

12

C2804

12

C2805

12

C2806

12

C2807

12

C2840

12

C2841

12

C2842

12

C2843

12

C2845

12

C2844

12

C2846

12

C2847

12

R2825

1

2

R2830

1

2

R2831

1

2

R2893

1

2

C2829

12

C2828

12

C2827

12

C2826

12

C2825

12

C2824

12

C2823

12

C2822

12

C2821

12

C2820

12

C2830

12

C2831

12

C2832

12

C2833

12

C2834

12

C2835

12

C2836

12

C2837

12

C2838

12

C2839

12

R2895

12

R2896

1

2

R2899

1

2

R2815

1

2

R2888

1

2

R2887

1

2

R2886

1

2

R2885

1

2

R2880

1

2

R2883

1

2

U2890

6

1

52

479

8

3

R2861

1

2

R2863

1

2

R2867

1

2

R2862

1

2

R2881

1

2

R2829

1

2

R2884

1

2

R2882

1

2

R2878

1

2

R2879

1

2

R2832

1

2

U2800

D19

E20

D17

E18

D15

E16

D13

E14

G2

G4

AB5

D11

E12

D9

E10

D7

E8

D5

E6

H1

H3

U4

B9

A8

B11

A10

B13

A12

B15

A14

J2

J4

AC2

U8

T5

AA2

Y3

R8 N2 R2 P3 F3

T1 T3

W6 AB3 AD3 V1

F1

U2 L6 H5 Y7 Y1 T7 V7 M7

AD23 AC24

W16

W18

L2

L4

E22

G22

E24

G24

J22

L22

J24

L24

P1 K5

B17

A16

B19

A18

M3

J6

N8

K1

K3

N22

R22

N24

R24

U22

W22

U24

W24

D3 M1

B21

A20

B23

A22

N6

P7

M5

V3

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

P5

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

R4

W20

AD21

AB21

U20

AD1 L8

AA6

W2

U6 R6 W8

AB7

AB1

AA4

AA24 AB23

25 OF 82

28 OF 120

8.0.0

051-1573

dvt1

77

25

69

25

25 26 27 68

25 26

25 69

25 30

25 28 29

25 26 27 68

25 27

25 29 30

25 28

25 77

18 25 26 68

25 27 28

25 29

18 25 26 68

71

81

25 77

77

69

71 81

71

81

71

81

69

71

81

71

81

71

81

71

81

71 81

81

25 77

69

25 77

71 81

71

81

71

81

45

69

74

69

NC

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

SG

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VER 3

D

SG

VER 3

D

SG

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

8 mOhm Typ

R(on)

Type

Max Current = 4A (85C)

Load Switch

Internal switch not functional on RR.

700 mA EDP

TPS22920

Push-pull output

Part

@ 1.05V

11.5 mOhm Max

1900 mA EDP

2.4 W (Single-Port)

3.1 W (Dual-Port)

Delay = 4.04ms nominal

Vth = 2.508V nominal

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Pull-up (S0) on PCH page

U2950

100 mA EDP

Isolated to reduce noise from SVR

1200 mA EDP

1.05V TBT "CIO" Switch

POC input to RR - 150 mA EDP

SVR input to RR - 1100 mA EDP

TBT "POC" Power-up Reset

25 mA EDP

EDP: 1.25 A

6.3V

20%

0201-1

X5R

1.0UF

0201-1

X5R

6.3V

20%

1.0UF

0201-1

6.3V

20% X5R

1.0UF

680NH-30%-3.6A-35MOHM

CRITICAL

SM

10UF

20%

CERM-X5R

0402-1

6.3V

OMIT_TABLE

CERM-X5R

0402-1

10UF

20%

6.3V

OMIT_TABLE

CRITICAL

SOD-323

NSR1020MW2T1G

1/20W

5%

201

MF

100K

CSP

CRITICAL

TPS22920

6.3V

20%

0201-1

1.0UF

X5R

6.3V X5R 0201-1

20%

1.0UF

6.3V

20%

0201-1

X5R

1.0UF

6.3V

1.0UF

20%

0201-1

X5R

25

6.3V

20% X5R

1.0UF

0201-1

6.3V

20% X5R

0201-1

1.0UF

CERM-X5R

10UF

20%

6.3V

0402-1

OMIT_TABLE

10UF

CERM-X5R

0402-1

20%

6.3V

OMIT_TABLE

10UF

0402-1

20%

6.3V

OMIT_TABLE

CERM-X5R

10UF

CERM-X5R

0402-1

20%

6.3V

OMIT_TABLE

PLACE_NEAR=C2953.1:1mm

SM

25

16V

10%

0201

X7R

330PF

1/20W

1%

201

MF

24.9K

25V

10%

402

X5R

0.1UF

15

1/20W

5%

201

MF

100K

17 27 38 39 75

1/20W

5%

201

MF

100K

DFN1006H4-3

DMN32D2LFB4

50V

10%

0402

X7R-CERM

0.001UF

13

CRITICAL

USON

TPS3895ADRY

1/20W

5%

201

MF

100K

SOT563

DMN5L06VK-7

SOT563

FALCON RIDGE

CRITICAL

FCBGA

OMIT_TABLE

12PF

NP0-C0G 0201

25V

5%

0201-1

6.3V

20%

1.0UF

X5R

NP0-C0G

+/-0.1PF

0201

3.0PF

25V

12PF

0201

5% 25V NP0-C0G

0201

25V

12PF

5%

NP0-C0G

0201

5%

12PF

25V

NP0-C0G

0201

5%

12PF

NP0-C0G

25V

0201

3.0PF

+/-0.1PF

25V

NP0-C0G NP0-C0G

0201

12PF

25V

5%

12PF

NP0-C0G

25V

0201

5%

NP0-C0G

25V

+/-0.1PF

0201

3.0PF

6.3V

0201-1

X5R

20%

1.0UF

0402-1

6.3V

20%

CERM-X5R

10UF

OMIT_TABLE

6.3V

20%

0402-1

CERM-X5R

10UF

OMIT_TABLE

6.3V X5R

20%

1.0UF

0201-1

6.3V

20% X5R

1.0UF

0201-1

1.0UF

20%

6.3V X5R

0201-1

25V

NP0-C0G

3.0PF

+/-0.1PF

0201

1.0UF

6.3V

20% X5R

0201-1

6.3V

20%

0201-1

X5R

1.0UF

X5R

6.3V

20%

0201-1

1.0UF

X5R

6.3V

0201-1

20%

1.0UF

CRITICAL138S0801

8

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C2920,C2921,C2922,C2923,C2950,C2951,C2952,C2953

BOM_COST_GROUP=TBT

SYNC_DATE=12/17/2012

SYNC_MASTER=T29_RR

Thunderbolt Host (2 of 2)

PP1V05_TBTCIO

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S4_TBT_F

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

PP1V05_TBTRDV

=PP3V3_S4_TBT

TBT_PWR_REQ_L

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

TBT_POC_RESET_L

TBTPOCRST_MR_L

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

TBTPOCRST_SENSE

TBT_PWR_ON_POC_RST_L

PP1V05_TBT

PP3V3_TBTLC

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.50 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

PP3V3_TBTLC

=PP3V3_S0_PCH_GPIO

=PP3V3_S4_TBT

TBTPOCRST_CT

VOLTAGE=3.3V

PP3V3_TBTRDV

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM VOLTAGE=1.05V

PP1V05_TBT

=PP3V3_S4_TBT

C2904

1

2

C2905

1

2

C2900

1

2

C2901

1

2

C2902

1

2

C2906

1

2

C2903

1

2

C2920

1

2

C2921

1

2

C2932

1

2

C2931

1

2

C2930

1

2

C2911

1

2

C2910

1

2

L2920

12

C2922

1

2

C2923

1

2

D2920

A

K

R2945

1

2

U2940

D1

D2

A2 B2 C2

A1 B1 C1

C2940

1

2

C2981

1

2

C2980

1

2

C2970

1

2

C2960

1

2

C2961

1

2

C2953

1

2

C2952

1

2

C2951

1

2

C2950

1

2

XW2960

1

2

C2995

1

2

R2991

1

2

C2990

1

2

R2995

1

2

R2990

1

2

Q2995

3

1

2

C2991

1

2

U2990

5

1

2

3

4

6

R2992

1

2

Q2945

6

2

1

Q2945

3

5

4

U2800

B5

A4 A6 B3

J8

K9 L14 M15 M17 P17 V19

J10 J12

R14 T11 T15 U10 U14 V11

K11 L10 M11 N10 N14 P11 P15 R10

G10 G12

K19

K7 L16 M19 P19 T19 U18 V15 V17 W12

G14

W14

G16 G18 H19

H9 J18 K15 K17

D1 E2 H11 N4 V5 W4

Y5

H13 H15 H17 H7 L18 N18 R18 W10

A2 A24

AC14 AC16 AC18 AC20 AC22

AC4 AC6 AC8

B1

B7

AA14

C10 C12 C14 C16 C18

C2 C20 C22 C24

C4

AA20

C6

C8 D21 D23

E4 F11 F13 F15 F17 F19

AA22

F21 F23

F5

F7

F9

G20 G6 G8 H21 H23

AA8 J14

J16 J20 K13 K21 K23 L12 L20 M13 M21

AB11

M23 M9 N12 N16 N20 P13 P21 P23 P9 R12

AB17

R16 R20 T13 T17 T21 T23 T9 U12 U16 V13

AC10

V21 V23 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23

AC12

Y9

C290D

1

2

C290C

1

2

C290B

1

2

C290A

1

2

C291B

1

2

C291A

1

2

C291D

1

2

C291C

1

2

C291E

1

2

C292B

1

2

C292A

1

2

dvt1

051-1573

8.0.0

29 OF 120

26 OF 82

25 26 27 68

12 13 15 18 26 65 68

26

18 25 26 68

12 13 15 18 26 65 68

25 26 27 68

26

25 26 27 68

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

IN

SYM_VER_2

GS

D

OUT

D

SYM_VER_3

SG

IN

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(NONE)

- =PP15V_TBT_REG (15V Boost Output)

Voltage not specified here, add property on another page.

BOM options provided by this page:

Power aliases required by this page:

Signal aliases required by this page:

dual-port designs.

Second FET needed for

<R2>

for 2S.

Changes required

UVLO = 4.55V (falling), 4.95 (rising)

Max Vgs: 10V

SGND shorted to GND inside package, no XW necessary.

<Rb>

<Ra>

Id(max): 3.7A @ 70C

<R1>

Vout = 15.47V

Max Current = 2A?

FREQ = 480KHZ

SI8409DB: Vds(max): -30V Vgs(max): +/-12V

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1)

- =PPVIN_SW_TBTBST (8-13V Boost Input)

Page Notes

Pull-up on RR page

BATLOW# Isolation

8-13V Input

Rds(on): 46mOhm @ 4.5V Vgs

Thunderbolt 15V Boost Regulator

Vout = 1.6V * (1 + Ra / Rb)

Vgs(th): -1.4V

330K

MF-LF

402

5%

1/16W

470K

MF-LF

402

5%

1/16W

0.1UF

X5R 402

10% 25V

73.2K

MF-LF 402

1% 1/16W

330K

MF-LF 402

5% 1/16W

26.7K

MF-LF

402

1%

1/16W

0.33UF

CERM-X5R 402

10%

6.3V

330K

MF-LF 402

5% 1/16W

17 26 38 39 75

NO STUFF

100PF

CERM 402

5% 50V

15.8K

MF-LF

402

1%

1/16W

POLY-TANT CASE-D3L

20% 25V

33UF-0.06OHM

10UF

X5R

1206-2

10% 25V

10UF

X5R 805

10% 25V

NO STUFF

68PF

CERM 0402

5% 50V

2.2UF

X5R-CERM

402

20% 10V

CRITICAL

SI8409DB

BGA

49.9K

MF-LF

402

1%

1/16W

200K

MF-LF

402

1%

1/16W

0603

20%

10UF

X5R-CERM

25V

10UF

X5R-CERM

0603

20% 25V

CRITICAL

3.3UH-6.5A

PIMB063T-SM

10PF

CERM 0402

5% 50V

CRITICAL

LT3957

QFN

137K

MF-LF

402

1%

1/16W

PLACE_NEAR=C3095.1:2 mm

SM

0

MF

0201

5%

1/20W

0.001UF

10% 50V X7R-CERM 0402

0.0033UF

X7R-CERM 0402

10% 50V

2.2UF

X5R-CERM

402

20% 10V

2.2UF

X5R-CERM 402

20% 10V

PWRDI5

PDS540XF

CRITICAL

25 28

DMN32D2LFB4

DFN1006H4-3

25

DMN32D2LFB4

DFN1006H4-3

13 38

DMN5L06VK-7

SOT563

DMN5L06VK-7

SOT563

5%

12PF

25V NP0-C0G 0201

NP0-C0G 0201

12PF

5% 25V

5%

12PF

25V NP0-C0G 0201

SYNC_MASTER=T29_RR

SYNC_DATE=11/19/2012

Thunderbolt Mobile Support

BOM_COST_GROUP=TBT

=PP15V_TBT_REG

GND_TBTBST_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE DIDT=TRUE

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

TBTBST_SNS2

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_SW_TBTBST

SMC_DELAYED_PWRGD

TBTBST_SHDN_DIV

TBTBST_EN_UVLO

=TBT_BATLOW_L

=PPVIN_SW_TBTBST

TBTBST_FBX

TBTBST_INTVCC

TBTBST_SS

TBTBST_RT

TBTBST_VC

TBTBST_PWREN_DIV_L

TBTBST_PWREN_L

TBTBST_VC_RC

TBT_A_HV_EN

PM_BATLOW_L

TBTBST_SNS1

TBTBST_VSNS

=PP3V3_S4_TBT

TBT_BATLOW_L

MAKE_BASE=TRUE

R3081

1

2

R3080

1

2

C3080

1

2

R3092

1

2

R3087

1

2

R3094

1

2

C3094

1

2

R3088

1

2

C3089

1

2

R3096

1

2

C3095

1

2

C3096

1

2

C3097

1

2

C3087

1

2

C3085

1

2

Q3080

23

1

4

R3093

1

2

R3091

1

2

C3090

1

2

C3091

1

2

L3095

12

C3088

1

2

U3090

25

31

1213141516

17

28

1 2 10 35 36

33

6

3

42324

37

32

8

9

202138

34

30

27

R3095

1

2

XW3095

12

R3089

1

2

C3099

1

2

C3093

1

2

C3092

1

2

C3086

1

2

D3095

1

2

3

Q3005

3

1

2

Q3000

3

1

2

Q3088

6

2

1

Q3088

3

5

4

C3000

1

2

C3001

1

2

C3002

1

2

dvt1

051-1573

8.0.0

30 OF 120

27 OF 82

68

27 68

30

25 26 68

IN

OUT

IN

OUT

BI

IN

OUT

IN

BI

IN

OUT

ML_LANE1P

GND1

ML_LANE0N

GND0

ML_LANE0P

ML_LANE1N

ML_LANE2N

RETURN

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4

DP_PWR

AUX_CHP AUX_CHN

ML_LANE2P

GND3

SHIELD PINS

PORT B

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

470k R’s for ESD protection

(0-18.9V)

514-0876

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IV3P3 1100mA 1030mA 1200mA

V3P3 must be S4 to support

Nominal Min Max

TBT: Unused

(Both C’s)

DP Dir

TBT Dir

(Both C’s)

on AC-coupled signals.

(Both C’s)

TBT Dir

TBT: TX_0

(0-18.9V)

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

Low: 0 - 0.8V

High: 2.0 - 5.0V

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU)

(IPD)

(IPU)

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Nominal Min Max

Single-fault protection

below

requires two R’s per HV

Single R on ISET_V3P3 OK.

12V: See

For 12V systems:

TBT: TX_1

TBT: RX_0

TBT: RX_1

ISET_Sx with CD3210.

15.75V Max

Sink HPD range:

wake from Thunderbolt devices.

3.3V/HV Power MUX

<RV3P3>

ILIM = 40000 / RISET

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Thunderbolt Connector A

0402

50V

10%

0.01UF

X7R-CERM

25 71 77

0.01UF

X5R-CERM 0201

10% 16V

12

MF

201

5%

1/20W

0.01UF

X7R-CERM

10%

0402

50V

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1K

MF

201

5%

1/20W

NO_XNET_CONNECTION=TRUE

1K

MF 201

5% 1/20W

GND_VOID=TRUE

100K

MF 201

5% 1/20W

10UF

CERM-X5R 0402

20%

6.3V

0.1UF

X5R-CERM

0201

10% 16V

0.1UF

X5R-CERM 0201

10% 16V

22UF

X5R-CERM-1

603

20%

6.3V

CRITICAL

100UF

POLY-TANT

CASE-B2-SM

20%

6.3V

1M

MF

201

5%

1/20W

1M

MF 201

5% 1/20W

330PF

X7R

0201

10% 16V

330PF

X7R 0201

10% 16V

0603

CRITICAL

FERR-120-OHM-3A

25

0.1UF

X5R 402

10% 25V

GND_VOID=TRUE

470K

MF 201

5% 1/20W

GND_VOID=TRUE

470K

MF 201

5% 1/20W

GND_VOID=TRUE

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

0.22UF

X5R

0201

20%

6.3V

25 71 77

GND_VOID=TRUE

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

0.22UF

X5R

0201

20%

6.3V

GND_VOID=TRUE

470K

MF 201

5% 1/20W

GND_VOID=TRUE

470K

MF 201

5% 1/20W

25 27

64

29 64

201

36.5K

MF

1% 1/20W

0.1UF

X5R 402

10% 25V

0.1UF

X5R-CERM

0201

10% 16V

25

30

25

25 71 77

0.22UF

X5R

0201

20%

6.3V

0.22UF

X5R

0201

20%

6.3V

25 77

0.1UF

X5R-CERM

0201

10% 16V

0.1UF

X5R-CERM

0201

10% 16V

25 77

0.22UF

X5R

0201

20%

6.3V

0.22UF

X5R

0201

20%

6.3V

25 77

MF 201

22.6K

1% 1/20W

TBTHV:P15VTBTHV:P15V

22.6K

MF

201

1%

1/20W

TBTHV:P15V

22.6K

MF 201

1% 1/20W

TBTHV:P15V

22.6K

MF

201

1%

1/20W

4.7UF

X5R-CERM

0603

10% 25V

GND_VOID=TRUE

0.01UF

X5R-CERM

0201

10% 25V

GND_VOID=TRUE

0.01UF

X5R-CERM

0201

10% 25V

25

CRITICAL

MDP-J44

F-RT-TH

GND_VOID=TRUE

0.47UF

CERM-X5R-1

20120% 4V

GND_VOID=TRUE

0.47UF

CERM-X5R-1

20120% 4V

SIGNAL_MODEL=TBT_MUX

CRITICAL

CBTL05024

HVQFN24-COMBO

25 29

25

470K

MF

201

5%

1/20W

470K

MF

201

5%

1/20W

GND_VOID=TRUE

0.47UF

CERM-X5R-1

20120% 4V

GND_VOID=TRUE

0.47UF

CERM-X5R-1

20120% 4V

CRITICAL

CD3211A1RGP

QFN

0201

5%

12PF

25V

NP0-C0G

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

R3210,R3213

TBTHV:P12V

2

SYNC_DATE=10/26/2012

SYNC_MASTER=T29_RR

Thunderbolt Connector A

BOM_COST_GROUP=TBT

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3211,R3214

TBTHV:P12V

118S0145

2

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_S4_TBTAPWR

TBT_A_D2R_C_N<0>

TBT_A_D2R_C_P<0>

TBT_A_D2R_P<1>

TBT_A_D2R_C_P<1>

=PP3V3_S4_TBTAPWRSW

TBTAPWRSW_ISET_V3P3

TBT_A_HV_EN

=TBT_S0_EN

=TBTAPWRSW_EN

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

=PPHV_S4SW_TBTAPWRSW

TBT_A_D2R_N<1>

TBT_A_D2R_C_N<1>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_P

TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R

DP_TBTPA_HPD

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_DDC_DATA DP_TBTPA_DDC_CLK

TBT_A_CONFIG1_BUF

TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH_N

DP_TBTPA_ML_N<1>

DP_TBTPA_ML_P<1>

TBT_A_HPD

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_CONFIG1_RC

PP3V3_S4_TBTAPWR

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_P<1>

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R1_AUXDDC_P

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_P<3>

TBT_A_HPD

TBT_A_R2D_N<1>

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_D2R1_AUXDDC_P

TBT_A_DP_PWRDN

TBTDP_AUXIO_EN

TBT_A_CIO_SEL

TBT_A_R2D_N<0>

TBT_A_R2D_P<1>

TBT_A_R2D_P<0>

PP3V3_S4_TBTAPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_7_C

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_1_C

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_S4_TBTAPWR_F

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_20_RC

VOLTAGE=18V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

L3200

12

C3200

1

2

C3202

1

2

R3201

12

C3201

1

2

R3294

1

2

R3295

1

2

R3241

1

2

C3286

1

2

C3285

1

2

C3281

1

2

C3280

1

2

C3287

1

2

R3252

1

2

R3251

1

2

C3294

1

2

C3295

1

2

C3210

1

2

R3270

1

2

R3271

1

2

C3271

12

C3270

12

C3272

12

C3273

12

R3273

1

2

R3272

1

2

R3212

1

2

C3211

1

2

C3220

1

2

C3232

12

C3233

12

C3230

12

C3231

12

C3278

12

C3279

12

R3211

1

2

R3210

1

2

R3214

1

2

R3213

1

2

C3215

1

2

C3205

1

2

C3206

1

2

J3200

B18

B16

B4 B6

B20

B1

B7B8

B13B14

B2

B5

B3

B11

B9

B17

B15

B12

B10

B19

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S24

C3274

12

C3275

12

U3220

1 2

24

23 22

1816

5

4

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

R3279

1

2

R3278

1

2

C3277

12

C3276

12

U3210

5

16 4

123

13

15

11 10

9

8

12 14

17

21

19 20

18

6 7

C3260

1

2

dvt1

051-1573

8.0.0

32 OF 120

28 OF 82

71 77

68

71

68

71 77

77

71

28 77

77

28

28 77

28

28 77

77

28

71 77

28 77

71 77

28

IN

OUT

IN

OUT

BI

IN

OUT

IN

BI

IN

OUT

ML_LANE1P

GND3

GND4

HPD

CONFIG2 GND2

RETURN

AUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

GND0

DP_PWR

ML_LANE0P

GND1

ML_LANE0N

ML_LANE1N

ML_LANE2N

ML_LANE2P

PORT A

SHIELD PINS

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

wake from Thunderbolt devices.

514-0876

Single-fault protection

V3P3 must be S4 to support

below

<RV3P3>

3.3V/HV Power MUX

Nominal Min Max

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

ILIM = 40000 / RISET

greater than or equal

down HPD input with

TBT: RX_0

DP Dir

TBT: Unused

TBT: RX_1

TBT: TX_1

For 12V systems:

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

12V: See

Single R on ISET_V3P3 OK.

requires two R’s per HV ISET_Sx with CD3210.

IV3P3 1100mA 1030mA 1200mA

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

(IPU)

(IPD)

(IPU)

TBT: RX_1

TBT: LSX_A_R2P/P2R (P/N)

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

DP Source must pull

Thunderbolt Connector B

TBT: LSX_R2P/P2R (P/N)

(Both C’s)

DP Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

TBT Dir

(Both C’s)

470k R’s for ESD protection on AC-coupled signals.

(Both C’s)

TBT Dir

(Both C’s)

to 100K (DPv1.1a).

15.75V Max

50V

10%

0402

X7R-CERM

0.01UF

25 71 77

16V

10%

0201

X5R-CERM

0.01UF

1/20W

5%

201

MF

12

50V

10%

0402

X7R-CERM

0.01UF

1/20W

5%

201

MF

1K

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20W

5%

201

MF

1K

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1/20W

5%

201

MF

100K

6.3V

20%

0402

CERM-X5R

10UF

16V

10%

0201

X5R-CERM

0.1UF

16V

10%

0201

X5R-CERM

0.1UF

6.3V

20%

603

X5R-CERM-1

22UF

6.3V

20%

CASE-B2-SM

POLY-TANT

100UF

CRITICAL

1/20W

5%

201

MF

1M

1/20W

5%

201

MF

1M

16V

10%

0201

X7R

330PF

16V

10%

0201

X7R

330PF

0603

FERR-120-OHM-3A

CRITICAL

25

25V

10%

402

X5R

0.1UF

1/20W

5%

201

MF

470K

GND_VOID=TRUE

1/20W

5%

201

MF

470K

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

GND_VOID=TRUE

25 71 77

6.3V

20%

0201

X5R

0.22UF

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

GND_VOID=TRUE

1/20W

5%

201

MF

470K

GND_VOID=TRUE

1/20W

5%

201

MF

470K

GND_VOID=TRUE

25 30

64

28 64

1/20W

1%

201

MF

36.5K

25V

10%

402

X5R

0.1UF

16V

10%

0201

X5R-CERM

0.1UF

25

30

25

25 71 77

6.3V

20%

0201

X5R

0.22UF

6.3V

20%

0201

X5R

0.22UF

25 77

16V10% 0201

X5R-CERM

0.1UF

16V10% 0201

X5R-CERM

0.1UF

25 77

6.3V

20%

0201

X5R

0.22UF

6.3V

20%

0201

X5R

0.22UF

25 77

1/20W

1%

201

MF

22.6K

TBTHV:P15V

1/20W

1%

201

MF

22.6K

TBTHV:P15V

1/20W

1%

201

MF

22.6K

TBTHV:P15V

1/20W

1%

201

MF

22.6K

TBTHV:P15V

25V

10%

0603

X5R-CERM

4.7UF

25V

10%

0201

X5R-CERM

0.01UF

GND_VOID=TRUE

25V

10%

0201

X5R-CERM

0.01UF

GND_VOID=TRUE

25

F-RT-TH

MDP-J44

CRITICAL

4V20% 201

CERM-X5R-1

0.47UF

GND_VOID=TRUE

4V20% 201

CERM-X5R-1

0.47UF

GND_VOID=TRUE

HVQFN24-COMBO

CBTL05024

CRITICAL

SIGNAL_MODEL=TBT_MUX

25 28

25

1/20W

5%

201

MF

470K

1/20W

5%

201

MF

470K

4V20% 201

CERM-X5R-1

0.47UF

GND_VOID=TRUE

4V20% 201

CERM-X5R-1

0.47UF

GND_VOID=TRUE

QFN

CD3211A1RGP

CRITICAL

25V

0201

NP0-C0G

12PF

5%

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3311,R3314

2

118S0145

TBTHV:P12V

BOM_COST_GROUP=TBT

Thunderbolt Connector B

SYNC_MASTER=T29_RR

SYNC_DATE=10/26/2012

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3310,R3313

2

118S0145

TBTHV:P12V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

PP3V3RHV_S4_TBTBPWR

TBTBPWRSW_ISET_V3P3

TBT_B_CIO_SEL

TBTDP_AUXIO_EN

TBT_B_DP_PWRDN

DP_TBTPB_DDC_CLK

TBT_B_D2R_C_N<1> TBT_B_D2R_C_P<1>

TBT_B_D2R_P<1>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_P<0>

DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3>

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

TBT_B_R2D_C_N<0>

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_RC

PP3V3_S4_TBTBPWR

DP_TBTPB_AUXCH_P

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

TBT_B_HPD

DP_TBTPB_ML_P<1> DP_TBTPB_ML_N<1>

DP_TBTPB_AUXCH_N

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R1_AUXDDC_N

TBT_B_CONFIG1_BUF

DP_TBTPB_DDC_DATA

TBT_B_LSTX TBT_B_LSRX

DP_TBTPB_HPD

TBT_B_D2R_N<0>

TBT_B_R2D_P<1>

DP_B_LSX_ML_N<1>

TBT_B_R2D_N<0>

TBT_B_R2D_P<0>

DP_B_LSX_ML_P<1>

TBT_B_D2R1_AUXDDC_P

TBT_B_HPD

DP_TBTPB_ML_P<3>

TBT_B_D2R1_AUXDDC_N

DP_TBTPB_ML_N<3>

TBT_B_R2D_N<1>

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

TBT_B_D2R_C_N<0>

TBT_B_D2R_C_P<0>

TBT_B_D2R_N<1>

=PPHV_S4SW_TBTBPWRSW

TBTBPWRSW_ISET_S3

TBTBPWRSW_ISET_S0

=TBTBPWRSW_EN

=TBT_S0_EN

TBT_B_HV_EN

=PP3V3_S4_TBTBPWRSW

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V

PP3V3_S4_TBTBPWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

PP3V3RHV_S4_TBTBPWR_F

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=18V

TBTBCONN_20_RC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=18.9V

TBTBCONN_1_C

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=18.9V

TBTBCONN_7_C

L3300

12

C3300

1

2

C3302

1

2

R3301

12

C3301

1

2

R3394

1

2

R3395

1

2

R3341

1

2

C3386

1

2

C3385

1

2

C3381

1

2

C3380

1

2

C3387

1

2

R3352

1

2

R3351

1

2

C3394

1

2

C3395

1

2

C3310

1

2

R3370

1

2

R3371

1

2

C3371

12

C3370

12

C3372

12

C3373

12

R3373

1

2

R3372

1

2

R3312

1

2

C3311

1

2

C3320

1

2

C3332

12

C3333

12

C3330

12

C3331

12

C3378

12

C3379

12

R3311

1

2

R3310

1

2

R3314

1

2

R3313

1

2

C3315

1

2

C3305

1

2

C3306

1

2

J3200

A18

A16

A4 A6

A20

A1

A7A8

A13A14

A2

A5

A3

A11

A9

A17

A15

A12

A10

A19

S1

S10

S11S2S23

S3

S4

S5

S6S7S8

S9

C3374

12

C3375

12

U3320

1 2

24

23 22

1816

5

4

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

R3379

1

2

R3378

1

2

C3376

12

C3377

12

U3310

5

16 4

123

13

15

11 10

9

8

12 14

17

21

19 20

18

6 7

C3360

1

2

dvt1

051-1573

8.0.0

33 OF 120

29 OF 82

71

71 77

29

77

29

29 77

29

77

29 77

71 77

29 77

71 77

29 77

29

77

29 77

77

71 77

71

71 77

68

71

68

29

BI

OUT

BI

OUT

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

BI

IN

BI

IN

OUT

IN

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

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6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SAI/SBI = 0: INA == OUTB0, INB == OUTA0

SAI/SBI = 1: INA == OUTA0, INB == OUTB0

NEVER SEND AUXCH THROUGH CROSSBAR!

DDC Crossbar

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

DP++ spec violation, should remove!

2.2k pull-ups are required by PCH

pull-ups are unstuffed.

DDC Pull-Ups

NOTE: Only DDC_DATA is sensed, so DDC_CLK

to indicate active display interface.

Only necessary on dual-port hosts.

CONNECTS TO TBTBTS_PWREN_L ON PAGE 30.

dual-port designs.

Second FET needed for

29

28

QFN

TS3DS10224

CRITICAL

67

13

10V

20%

402

CERM

0.1UF

1/20W

1%

201

MF

2.2K

1/20W

1%

201

MF

2.2K

1/20W

1%

201

MF

2.2K

1/20W

1%

201

MF

2.2K

25 29

27

25

1/20W

5%

201

MF

100K

SOT563

DMN5L06VK-7

SOT563

DMN5L06VK-7

BOM_COST_GROUP=TBT

DDC Crossbar

SYNC_DATE=10/23/2012

SYNC_MASTER=J14

TBT_B_HV_EN

TBTBST_PWREN_L

TBT_DDC_XBAR_EN_L

TBT_DDC_XBAR_EN

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTPB_DDC_CLK DP_TBTPB_DDC_DATA

=PP3V3_S0_DDCMUX

DP_TBTPA_DDC_DATA

DP_TBTPA_DDC_CLK

DP_TBTSNK1_DDC_CLK

DP_TBTSNK0_DDC_DATA

U3400

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14

15

12 11

21

13

C3480

1

2

R3451

1

2

R3452

1

2

R3453

1

2

R3454

1

2

R3485

1

2

Q3485

6

2

1

Q3485

3

5

4

dvt1

051-1573

8.0.0

34 OF 120

30 OF 82

68

NC

BI

DP_2

DM_2

DM_1

DP_1

S

DP

GND

VDD

OE*

DM

OUT

SYM_VER_2

GS

D

GND

VCC

A

B0 B1

S

VER-3

OUT

IN

NC

08

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BLUETOOTH

H USB_BT (2)

L BT_WAKE (1)

PCIe Wake Muxing

SEL OUTPUT

L PCIE_WAKE_L (B0)

SEL OUTPUT

H AP_S0IX_WAKE_L (B1)

CERM-X5R 0201

10%

6.3V

0.1UF

14 74

SIGNAL_MODEL=BT_MUX

CRITICAL

USB3740

DFN

40

15K

MF 201

1% 1/20W

DMN32D2LFB4

DFN1006H4-3

NO_XNET_CONNECTION=TRUE

100K

MF 201

5% 1/20W

CRITICAL

NC7SB3157P6XG

SC70

0.1UF

CERM-X5R

0201

10%

6.3V

1/20W

5%

0201

MF

0

NOSTUFF

15

13 33 75

15

74LVC1G08

CRITICAL

SOT891

10V

10%

0.1UF

0201

X5R-CERM

BYPASS=U3520::5 mm

13 18 37 38 64 66

0201

1/20W

5% MF

0

NOSTUFF

Wireless Support

SYNC_MASTER=J41

SYNC_DATE=11/01/2012

BOM_COST_GROUP=WIRELESS

PM_SLP_S4_BTMUX_L

PM_SLP_S4_L

PCIE_WAKE_L

=PP3V3_S4_BT

USB_BT_CONN_P

USB_BT_CONN_N

AP_PCIE_WAKE_L

AP_S0IX_WAKE_SEL

AP_S0IX_WAKE_L

=PP3V3_S5_WLAN

BT_WAKE_L

USB_BT_P

USB_BT_N

=PP3V3_S4_BT

BT_WAKE

C3510

1

2

U3510

9

1

7

10

2

6

8

3

4

5

R3512

1

2

Q3510

3

1

2

R3561

1

2

U3560

4

3 1

2

6

5

C3560

1

2

R3560

12

U3520

2

1

3

6

4

C3520

1

2

R3520

12

dvt1

051-1573

8.0.0

35 OF 120

31 OF 82

5

31 68

66 74

66 75

68

31 68

OUT

IN

NC

08

NC

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

OUT

IN

NC

08

IN

NC

IN

NC

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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87 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Supervisor & CLKREQ# Isolation

Delay = 55ms

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

GND_VOIDGND_VOID

514S0449

OOB Isolation

Gumstick3 Connector

38

X5R-CERM

10V

10%

0201

0.1UF

PLACE_NEAR=L3700.1:1mm

CRITICAL

PLACE_NEAR=J3700.1:3mm

0603

FERR-26-OHM-6A

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=L3700.1:1mm

1%

201

MF

100K

1/20W

5%

201

MF

100K

SSD_CLKREQ:UNI

201

232K

1/20W

1% MF

12

6.3V

10%

0201

0.1UF

CERM-X5R

15

15 32 64

SOT891

CRITICAL

BYPASS=U3711::5 mm

74LVC1G08

0.1UF

X5R-CERM

0201

10% 10V

SLG4AP016V

TDFN

CRITICAL

12 71 81

16V10%

GND_VOID=TRUE

X5R-CERM

0.1UF

0201

16V10%

0201X5R-CERM

0.1UF

GND_VOID=TRUE

16V10%

0201

GND_VOID=TRUE

0.1UF

X5R-CERM

16V10%

0.1UF

0201X5R-CERM

GND_VOID=TRUE

0201

16V10%

X5R-CERM

0.1UF

GND_VOID=TRUE

16V10%

0.1UF

GND_VOID=TRUE

X5R-CERM 0201

16V10%

0201X5R-CERM

0.1UF

GND_VOID=TRUE

10%

0.1UF

0201

GND_VOID=TRUE

16V

X5R-CERM

12 71 81

15 32 64

TRUE TRUE

SSD-GS3

TRUE TRUE

TRUE

TRUETRUE

TRUE

F-RT-SM

CRITICAL

1/20W

1% MF

100K

201

NOSTUFF

SOT891

74LVC1G08

CRITICAL

38

10V

BYPASS=U3710::5 mm

0201

10% X5R-CERM

0.1UF

15

13

16

0201

5%

0

MF

1/20W

NOSTUFF

100K

201

MF

1/20W

1%

1/20W

MF

5%

0

0201

1/20W

0201

5%

0

SSD_CLKREQ:BI

MF

SSD_CLKREQ:UNI

1/20W

0

0201

MF

5%

0

0201

MF

1/20W

5%

SSD_CLKREQ:UNI

5% 25V NP0-C0G 0201

12PF

0201

5%

12PF

25V NP0-C0G

12PF

0201

5% 25V NP0-C0G NP0-C0G

25V

5%

12PF

NOSTUFF

0201

25V

12PF

5%

0201

NP0-C0G

12 71 81

1/20W

5%

0

0201

MF

PLACE_NEAR=C3721.1:1mm

0

5%

MF

1/20W

0201

PLACE_NEAR=C3721.2:1mm

0

5%

MF

0201

PLACE_NEAR=C3721.1:1mm

1/20W

0

5%

0201

1/20W

MF

PLACE_NEAR=C3721.2:1mm

NOSTUFF

47PF

0201

C0G

25V

5%

PLACE_NEAR=R3704.1:1mm

25V

47PF

5%

PLACE_NEAR=R3706.1:1mm

C0G

0201

NOSTUFF

BOM_COST_GROUP=SSD

SYNC_DATE=12/18/2012

SYNC_MASTER=YHARTANTO_J44

SSD Connector

PCIE_CLK100M_SSD_RC1_N

SSD_CLKREQ_CONN_L

PCIE_SSD_R2D_P<0>

SSD_PCIE_SEL_L

SSD_CLKREQ_L

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD_RC1_P

SMC_OOB1_D2R_L

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_P<0>

MIN_NECK_WIDTH=0.15mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=3.3V

PP3V3_S0SW_SSD_FLT

PCIE_CLK100M_SSD_P

PCIE_SSD_D2R_N<2>

=PP3V3_S0SW_SSD

PCIE_SSD_R2D_C_N<2>

SMC_OOB1_D2R_CONN_L

=PP3V3_S0_OOB1_PWRDN

PCIE_SSD_D2R_P<3>

SMC_OOB1_R2D_CONN_L

PCIE_SSD_R2D_N<2>

=PP3V3_S0SW_SSD

SSD_PWR_EN

PCIE_SSD_D2R_P<1>

SMC_OOB1_R2D_L

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

SSD_BOOT

PCIE_SSD_D2R_N<3>PCIE_SSD_R2D_N<3>

PCIE_SSD_R2D_P<3>

SSD_PWR_EN

SSD_RESET_L

SSD_SR_EN_L

SSD_CLKREQ_R_L

=PP3V3_S0SW_SSD

=PP3V42_G3H_SSDSAK

SSD_CLKREQ_CONN_R_L

P3V3SSD_VMON

SSD_BOOT_R

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<2>

PCIE_SSD_D2R_N<0>PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_C_P<1>

SSD_RESET_CONN_L

PCIE_CLK100M_SSD_RC2_P

PCIE_CLK100M_SSD_RC2_N

C3702

1

2

L3700

12

C3701

1

2

R3742

1

2

R3740

1

2

R3741

1

2

C3740

1

2

U3711

2

1

3

6

4

C3719

1

2

U3740

6

5

7

3

8

4

2

9

1

C3716

12

C3717

12

C3713

12

C3712

12

C3715

12

C3714

12

C3711

12

C3710

12

J3700

1

10 11 12 13 14 15 16

17 18 19

2

20 21 22 23 24 25 26 27 28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

51

52

53

54 55 56 57 58

59

6

60 61 62 63

7 8 9

R3700

1

2

U3710

2

1

3

6

4

C3718

1

2

R3701

12

R3703

1

2

R3702

12

R3743

12

R3745

12

R3744

12

C3722

1

2

C3723

1

2

C3724

1

2

C3726

1

2

C3725

1

2

R3704

12

R3706

12

R3705

12

R3707

12

C3721

1

2

C3720

1

2

dvt1

051-1573

8.0.0

37 OF 120

32 OF 82

5

81

71 81

81

32 68

68

71 81

32 68

71 81

32 68

68

71 81

81

NC NC

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03 DEBUG_04 DEBUG_05

DEBUG_09

PCIE_RDP0

DEBUG_06

DEBUG_00 DEBUG_01 DEBUG_02

DEBUG_07 DEBUG_08

DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13

DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

JTAG_TCK JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS UARTRTS

UARTRXD UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1 MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS*

DDR_DM0 DDR_DM1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

NC NC NC NC

NC

NC NC NC

NC NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(=PP3V3_S3RS0_CAMERA)

L3901:1 L3902:1

(=PP3V3_S3RS0_CAMERA)

A1 SILICON BUG

PD = 1.35V

PU = 25MHz

PU on PCH page

12

34

33 34 71

1/20W

NOSTUFF

100K

MF 201

5%

NOSTUFF

100K

MF 201

5% 1/20W

18

15 18

0.1UF

CERM-X5R 0201

10%

6.3V

CERM-X5R

0.1UF

0201

10%

6.3V

1.0UF

X5R

20%

6.3V 0201-1

0.1UF

CERM-X5R 0201

6.3V

10%

X5R 0201-1

6.3V

1.0UF

20%

BYPASS=U3900.D6::2.54MM

6.3V 0201

CERM-X5R

0.1UF

10%

BYPASS=U3900.D6::2.54MM

CERM-X5R 0201

6.3V

0.1UF

10%

100K

1/20W

5%

201

MF

34 74

34 81

100K

5%

201

MF

1/20W

CAM_XTAL:YES

100K

MF 201

5% 1/20W

CAM_XTAL:NO

100K

MF 201

1/20W

5%

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

1008

PLACE_NEAR=U3900.K13:4MM

1.0UH-1.6A-55MOHM

4.7UF

402

20%

6.3V X5R

BYPASS=U3900.K13::2.54MM

PLACE_NEAR=U3900.M13:2.54MM

4.7UF

X5R 402

20%

6.3V

22NH

0402

CERM-X5R

BYPASS=U3900.L7::2.54MM

0201

0.1UF

10%

6.3V

4.7UF

X5R 402

20%

6.3V

4.7UF

X5R 402

20%

6.3V

PLACE_NEAR=U3900.M14:2.54MM

0.1UF

BYPASS=U3900.J1::2.54MM

0201

10%

6.3V CERM-X5R

0.1UF

CERM-X5R

BYPASS=U3900::5mm

0201

10%

6.3V

CERM-X5R

BYPASS=U3900::5mm

0201

6.3V

10%

0.1UF0.1UF

CERM-X5R 0201

10%

BYPASS=U3900::5mm

6.3V

402

BYPASS=U3900::7mm

X5R

20%

6.3V

4.7UF

2.2UF

CERM 402-LF

20%

6.3V

BYPASS=U3900.F15::2.54MM

BYPASS=U3900.G15::2.54MM

10V

1UF

X5R 402

10%

CERM-X5R

6.3V

10%

0.1UF

0201

OMIT_TABLE

CRITICAL

BCM15700

FBGA

OMIT_TABLE

CRITICAL

FBGA

BCM15700

OMIT_TABLE

CRITICAL

FBGA

BYPASS=U3900.J1::2.54MM

X7R-1

1000PF

0201

16V

10%

1000PF

16V X7R-1 0201

BYPASS=U3900::3mm

0201

BYPASS=U3900.L7::2.54MM

1000PF

10% 16V X7R-1

X7R-1 0201

10% 16V

BYPASS=U3900::3mm

1000PF

BYPASS=U3900.D7::2.54MM

1000PF

X7R-1 0201

16V

10%

34 78

34 71 78

34 78

34 71 78

34

100K

MF 201

5% 1/20W

NO STUFF

100K

MF 201

5% 1/20W

240

MF

201

1%

1/20W

1K

201

5% MF

1/20W

1K

MF

201

5%

1/20W

34 71 78

SM

1/20W 201

100K

5% MF

CERM-X5R

6.3V 0201

NOSTUFF

0.1UF

10%

CERM-X5R 0201

0.1UF

10%

6.3V

0201-1

6.3V X5R

20%

1.0UF

34 71 78

0201-1

X5R

20%

6.3V

1.0UF

20%

10UF

6.3V CERM-X5R 0402-1

OMIT_TABLE

20%

10UF

CERM-X5R 0402-1

6.3V

OMIT_TABLE

CAM_A1

100K

MF 201

5% 1/20W

402

X5R

4.7UF

20%

6.3V

X5R

20%

6.3V

4.7UF

402

0603

220-OHM-1.4A

0603

0201

1/20W

MF

0

5%

NOSTUFF

13 31 75

BYPASS=U3900.L9::2.54MM

0.1UF

10%

6.3V CERM-X5R 0201

CERM-X5R

10%

6.3V 0201

0.1UF

BYPASS=U3900.L9::2.54MM

1000PF

X7R-1

10% 16V

0201

BYPASS=U3900.F9::2.54MM

0.1UF

CERM-X5R

10%

6.3V 0201

BYPASS=U3900.F9::2.54MM

1000PF

0201

16V

10% X7R-1

BYPASS=U3900.F6::2.54MM

10%

0.1UF

CERM-X5R

6.3V 0201

BYPASS=U3900.F6::2.54MM

51K

MF 201

5% 1/20W

51K

MF 201

5% 1/20W

100K

1/20W 201

MF

5%

100K

MF 201

5% 1/20W

NOSTUFF

100K

MF 201

5% 1/20W

MF 201

5% 1/20W

330K

201

MF

330K

5% 1/20W

330K

MF 201

5% 1/20W

NOSTUFF

100K

MF

201

5%

1/20W

NOSTUFF

100K

MF

201

5%

1/20W

34 78

NP0-C0G

25V

5%

12PF

0201

NP0-C0G

5%

12PF

25V 0201

NP0-C0G

25V

12PF

5%

0201

NP0-C0G

12PF

25V 0201

5%

NP0-C0G 0201

25V

5%

12PF

25V

12PF

5%

0201

NP0-C0G

25V

5%

12PF

NP0-C0G 0201

PLACE_NEAR=U3900.R10:5MM

PLACE_NEAR=U3900.R9:5MM

NP0-C0G 0201

25V

5%

12PF

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C3931,C3933

138S0801 CRITICAL

2

SYNC_MASTER=J45

Camera (1 of 2)

SYNC_DATE=01/24/2013

BOM_COST_GROUP=CAMERA

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V35_CAM

VOLTAGE=1.35V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V35_DDR_CLK

GND_CAM_PVSSD

PP1V2_CAM_PCIE_PVDD_FLT

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V8_CAM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V2_CAM

MEM_CAM_DQ<5>

CAM_DEBUG_RESET_L

CAM_PWR_SEL

CAM_PCIE_WAKE_L

CAM_PCIE_RESET_L

TP_CAM_JTAG_TMS

MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4>

MEM_CAM_DQ<9> MEM_CAM_DQ<10>

I2C_CAM_SMBDBG_DAT

I2C_CAM_SDA

CAM_TEST_MODE

DIDT=TRUE

P1V2_CAM_SRVLXC_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSC

PP1V8_CAM

I2C_CAM_SCK

PP1V2_CAM_XTALPCIEVDD

MIN_NECK_WIDTH=0.175MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

GND_CAM_PVSSD

PP1V8_CAM

CAMERA_PWR_EN

PP1V8_CAM

I2C_CAM_SDA

I2C_CAM_SCK

TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO

CAMERA_CLKREQ_L

I2C_CAM_SMBDBG_DAT

PCIE_CLK100M_CAMERA_C_N

CLK25M_CAM_CLKN

CAM_XTAL_FREQ

MEM_CAM_RESET_L

MEM_CAM_DQ<15>

MEM_CAM_DQS_P<1>

CAM_SENSOR_WAKE_L

GND_CAM_PVSSC

PCIE_WAKE_L

CAM_TEST_MODE

CAM_XTAL_SEL

CAM_RAMCFG2 CAM_GPIO3

MEM_CAM_DQ<8>

CAM_UARTCTS

CAM_TEST_OUT

CAM_RAMCFG1

CAM_XTAL_SEL

CAM_JTAG_SRST_L

P1V35_CAM_SRVLXD_PHASE

P1V2_CAM_SRVLXC_PHASE

PCIE_CAMERA_R2D_N

TP_CAM_LV_JTAG_TMS

TP_CAM_LV_JTAG_TDO

TP_CAM_LV_JTAG_TDI

TP_CAM_LV_JTAG_TCK

TP_CAM_TEST_MODE2

TP_CAM_TEST_MODE1

TP_CAM_TEST_MODE0

TP_CAM_LV_JTAG_TRSTN

=PPVDDIO_S3RS0_CAMCLK

MEM_CAM_A<12>

MEM_CAM_BA<0>

PCIE_CLK100M_CAMERA_C_P

GND_CAM_PVSSD

PP1V8_CAM

CAM_RAMCFG0

CAM_XTAL_FREQ

TP_CAM_UARTRTS

CAM_UARTRXD TP_CAM_UARTTXD

PP1V35_CAM

PP1V2_CAM

MEM_CAM_ZQ_S2

MEM_CAM_A<4>

MEM_CAM_A<6> MEM_CAM_A<7>

MEM_CAM_A<9>

MEM_CAM_A<11>

MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_CKE MEM_CAM_CS_L

MEM_CAM_DQ<14>

MEM_CAM_DQ<13>

MEM_CAM_DQ<12>

MEM_CAM_DQ<11>

MEM_CAM_DQ<7>

TP_CAM_JTAG_TRST_L

I2C_CAM_SMBDBG_CLK

MIPI_DATA_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_C_P

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_DQS_N<1>

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L

CAM_TEST_OUT

MIPI_CLK_N

MIPI_CLK_P

CAM_RAMCFG2 CAM_RAMCFG1 CAM_RAMCFG0

PP1V8_CAM

MEM_CAM_DQ<6>

DIDT=TRUE

P1V35_CAM_SRVLXD_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSC

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.175MM

PP0V675_CAM_VREF

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2MM

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3>

MEM_CAM_A<13>

PP1V2_CAM

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.2V

PP1V2_CAM_XTALPCIEVDD

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

CAM_UARTRXD

CAM_UARTCTS

MEM_CAM_A<14>

PP1V8_CAM

MEM_CAM_DQ<0>

MEM_CAM_A<10>

MEM_CAM_A<8>

PP1V2_CAM_XTALPCIEVDD

I2C_CAM_SMBDBG_CLK

MIPI_DATA_N

MEM_CAM_A<5>

PP1V8_CAM

CLK25M_CAM_CLKP

PCIE_CAMERA_D2R_C_N

=PP3V3_S3RS0_CAMERA

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_PCIE_VDD_FLT

CAM_JTAG_SRST_L

=PP3V3_S3RS0_CAMERA

R3930

1

2

R3932

1

2

C3900

1

2

C3924

1

2

C3923

1

2

C3922

1

2

C3921

1

2

C3910

1

2

C3951

1

2

R3901

1

2

R3906

1

2

R3907

1

2

R3904

1

2

L3901

12

L3902

12

C3912

1

2

C3915

1

2

L3906

12

C3916

1

2

C3928

1

2

C3926

1

2

C3919

1

2

C3937

1

2

C3935

1

2

C3940

1

2

C3942

1

2

C3941

1

2

C3939

1

2

C3960

1

2

U3900

B11 C14 B14 A15 E11 E10 F11 F10 G11 G10 H11 H10 J10 K11 K10 L11 L10

R12 P12 P11 P10 P9 N11 N10 N9

D15 R10 C15

R9

C11

F13 E12 F12 D12 D11

R7

P7

R8

R6

P8

P6

P13

A7

B7

A10

B10

R14

B8

A8

C9

B9

N12

G12 E15 R13 H12

C13

C12

M10

J12

D13 D14

E13 E14

A12

A13

U3900

L3 M4 N3 M3 M1 M2 P4 N2 P3 P2 J4 R2 L1 P1 R4

K3 L2 K2

H4

G2

H2

J3 L4

C1 C4

C2 E3 E4 D3 F3 F1 F4 F2 B5 C3 B1 B4 A5 C5 B2 B3

D2

A3

E2

A2

H3

R3

J2

G3

U3900

J1

A4 D4 G4 K4 N4

G5

N5

N7 N8 N6

L7

D7

C10

C7

D9

C8

D6

G14 M12

N13 P14 P15 R15

K15 L12 L13 L14 L15

M14 M15 N15

H14 H15 J13 J14 J15

M13 N14

K13 K14

F15

G15

F14

J11

F6 F7 F8 F9 L6 L5 L8 L9

B15

R11

M11 K12

A1 A6

G9 H5 H6 H7 H8 H9 J5 J6 J7 J8

B6

J9 K1 K5 K6 K7 K8 K9

A14

M9 N1

D1

P5 R1 R5

E9

D5 E5 G1 G6 G7 G8

B13

B12

C3918

1

2

C3934

1

2

C3917

1

2

C3936

1

2

C3938

1

2

R3910

1

2

R3911

1

2

R3912

12

R3913

1

2

R3914

1

2

XW3900

12

XW3901

12

R3990

1

2

C3990

1

2

C3927

1

2

C3930

1

2

C3932

1

2

C3931

1

2

C3933

1

2

R3915

1

2

C3914

1

2

C3913

1

2

L3903

12

L3904

12

R3991

12

C3975

1

2

C3974

1

2

C3973

1

2

C3972

1

2

C3971

1

2

C3970

1

2

R3975

1

2

R3976

1

2

R3920

1

2

R3921

1

2

R3934

1

2

R3931

1

2

R3933

1

2

R3935

1

2

R3936

1

2

R3937

1

2

C3976

1

2

C3977

1

2

C3978

1

2

C3979

1

2

C3980

1

2

C3981

1

2

C3983

1

2

C3982

1

2

dvt1

051-1573

8.0.0

39 OF 120

33 OF 82

33 34 78

33

75

33

33 34 71

33

33 34

33 34 71

33 34

33

17

33

33 34

33

33 34 78

33

33 34

33

34 78

33

33 34

33

33 44

33

33 44

OUT

IN

BI

IN

BI

IN

A4

A14

DQSL*

DQL1

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML DMU

DQL5 DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NC NC NC NC NC

BI

IN

BI

IN

NC NC

SYM_VER-1

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

77.2 mA nominal max

96.2 mA peak

ALS

518S0892

NOTE: TBD PPM crystal required

CAMERA SENSOR

33 81

14 71 81

0201

16V

X5R-CERM

0.1UF

10%

0201

16V

X5R-CERM

0.1UF

10%

16V

0201X5R-CERM

0.1UF

10%

0201X5R-CERM

16V

0.1UF

10%

14 81

33 81

5%

0201

CAM_XTAL:YES

MF

1/20W

0

1/20W

MF

0201

5%

CAM_XTAL:YES

0

5%

0201

CAM_XTAL:NO

MF

1/20W

0

5%

0201

CAM_XTAL:YES

MF

1/20W

0

5%

0201

MF

1/20W

0

201

CERM-X5R-1

4V

20%

0.47UF

BYPASS=U4000.H9::4mm

BYPASS=U4000.K2::4mm

10V

2.2UF

20% X5R-CERM

402

X5R-CERM

20% 10V

402

2.2UF

BYPASS=U4000.D2::4mm

1%

1M

NOSTUFF

MF

1/20W

201

5%

0201

25V

CERM

CAM_XTAL:YES

12PF

5%

0201

CERM

CAM_XTAL:YES

12PF

25V

0201

CERM-X5R

6.3V

0.1UF

10%

0201

6.3V

0.1UF

10% CERM-X5R

BYPASS=U4000.R9::4mm

10V

CERM

20%

0.1uF

402

33 71

0201

CERM-X5R

6.3V

0.1UF

10%

33 71 78

FERR-120-OHM-1.5A

0402-LF

10UF

20%

6.3V CERM-X5R 0402-1

BYPASS=U4000.B2::4mm

OMIT_TABLE

20% CERM-X5R

0402-1

6.3V

OMIT_TABLE

10UF

BYPASS=U4000.A1::4mm

41

1%

1K

MF

1/20W

201

1%

1K

MF

1/20W

201

K4B4G1646B-HYK0

FBGA

CRITICAL

OMIT_TABLE

4GB-DDR3-256MX16

33 78

0201

CERM-X5R

6.3V

10%

0.1UF

33 78

0201

CERM-X5R

6.3V

10%

0.1UF

33 78

33

33 78

84.5

1%

MF

1/20W

201

33 78

82

1%

NO STUFF

MF

1/20W

201

33 78

5%

1K

MF

1/20W

201

5%

NOSTUFF

1K

MF

1/20W

201

1/20W

240

1%

MF 201

5%

0201

MF

1/20W

0

CAM_WAKE:YES

5%

100PF

0201

C0G

25V

CAM_XTAL:NO

5%

0201

CAM_WAKE:NO

MF

1/20W

0

F-RT-SM

CCR20-AK7100-1

CRITICAL

0201

16V

X5R-CERM

0.1UF

10%

0201

16V

X5R-CERM

0.1UF

10%

NOSTUFF

FERR-120-OHM-1.5A

0402-LF

5%

100PF

0201

25V C0G

NO STUFF

33 78

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

CRITICAL

CAM_XTAL:YES

PLACE_NEAR=J4002.2:2.54MM

TAM0605-4SM

CRITICAL

3.25-OHM-0.1A-2.4GHZ

CRITICAL

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

PLACE_NEAR=J4002.5:2.54MM

5% 25V

0201

12PF

NP0-C0GNP0-C0G

5%

12PF

25V 0201

NP0-C0G

5%

12PF

25V 0201

NP0-C0G 0201

5%

12PF

25V

33 74

33 81

12 71 81

5%

100K

MF

1/20W 201

17 74

CAP,CER,10UF,20%,6.3V,HRZTL,0402

138S0801 CRITICAL

2

C4002,C4003

SYNC_MASTER=J41

SYNC_DATE=12/21/2012

Camera (2 of 2)

BOM_COST_GROUP=CAMERA

MEM_CAM_DQS_N<1>

MEM_CAM_DQ<3>

MIN_NECK_WIDTH=0.2 mm

PP0V675_MEM_CAM_VREFDQ

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0.675V

PP0V675_MEM_CAM_VREFCA

MEM_CAM_BA<1>

MEM_CAM_DQ<5>

CLK25M_CAM_CLKN

CLK25M_CAM_XTALN

CAM_SENSOR_WAKE_L_CONN

=I2C_ALS_SDA

MEM_CAM_ODT

MEM_CAM_A<5>

I2C_CAM_SDA

I2C_CAM_SCK

=I2C_ALS_SCL

CAM_SENSOR_WAKE_L_CONN

=PP5V_S3_ALSCAM

=PP5V_S0_ALSCAM

MEM_CAM_DQ<8>

CAM_SENSOR_WAKE_L

PCIE_CLK100M_CAMERA_P

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

PP1V8_CAM

MEM_CAM_A<0>

CLK25M_CAM_XTALP_R

MEM_CAM_DM<0>

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_C_N

CLK25M_CAM_CLKP

MEM_CAM_DQS_N<0>

MEM_CAM_DQ<7>

MEM_CAM_DQ<4>

MEM_CAM_DQ<2>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<12>

MEM_CAM_DQ<14>

MEM_CAM_DQS_P<0>

MEM_CAM_DQ<6>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<9>

MEM_CAM_DQ<13>

MEM_CAM_A<2>

MEM_CAM_A<8>

MEM_CAM_A<10>

MEM_CAM_A<9>

MEM_CAM_CAS_L

MEM_CAM_CS_L

MEM_CAM_WE_L

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

MEM_CAM_A<4>

MEM_CAM_CKE

MEM_CAM_CKE_R

MEM_CAM_A<13>

MEM_CAM_A<12>

MEM_CAM_A<11>

MEM_CAM_A<6>

MEM_CAM_DM<1>

MEM_CAM_BA<2>

MEM_CAM_BA<0>

MEM_CAM_A<14>

MEM_CAM_CLK_N

MEM_CAM_CLK_P

MEM_CAM_RAS_L

MEM_CAM_DQ<15>

PP0V675_CAM_VREF

CLK25M_CAM_XTALP

MIPI_CLK_CONN_N

MIPI_CLK_P

MIPI_CLK_N

MIPI_DATA_CONN_N MIPI_DATA_CONN_P

MIPI_DATA_N

MIPI_CLK_CONN_P

MIPI_DATA_P

PCIE_CAMERA_D2R_P

SYSCLK_CLK25M_CAMERA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

PP5V_S3RS0_ALSCAM_F

MEM_CAM_A<7>

MEM_CAM_A<3>

MEM_CAM_A<1>

MEM_CAM_DQ<0> MEM_CAM_DQ<1>

PP1V35_CAM

C4009

1

2

C4007

1

2

C4005

1

2

C4011

1

2

C4010

1

2

R4005

1

2

C4033

12

C4032

12

C4031

12

C4030

12

R4009

12

R4010

12

R4008

12

R4007

12

R4000

12

C4004

1

2

C4008

1

2

C4006

1

2

R4012

1

2

C4015

12

C4014

12

C4013

1

2

L4010

12

C4003

1

2

C4002

1

2

R4022

1

2

R4023

1

2

U4000

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

F3 G3

C7 B7

D7 C3 C8 C2 A7 A2 B8 A3

J1 J9 L1 L9 M7

K1

J3

T2

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

R4020

1

2

R4021

1

2

R4002

1

2

R4003

1

2

R4004

1

2

R4030

12

C4016

1

2

R4031

1

2

J4002

14

13

1

10

11

12

2

3

4

5

6

7

8

9

C4061

12

C4062

12

L4011

12

R4006

1

2

Y4000

24

13

L4009

1

23

4

L4007

1

23

4

C4020

1

2

C4019

1

2

C4018

1

2

C4017

1

2

dvt1

051-1573

8.0.0

40 OF 120

34 OF 82

78

74

34 71

78

34 71

68

33

74

33 78

74

71 78

71

33 78

SYM_VER-1

OUT

IN

FAULT*

IN_1

IN_0

ILIM

OUT1 OUT2

EN

GND

THRM

PAD

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

IN

OUT

IN

GND

VBUS

SSTX+

SSRXGND

SSTX-

D+

D-

GND SXRX+

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Mojo SMC Debug Mux

USB Port Power Switch

RIGHT USB PORT A

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

THE PI3USB102E CAN CLAMP VOLTAGE IN THE INTERNAL USB PINS

H USB (D)

L SMC (M)

SEL OUTPUT

0.01UF

X5R-CERM

0201

10% 16V

CRITICAL

90-OHM

DLP0NS

14 71 74

GND_VOID=TRUE

0.1UF

CERM-X5R0201

10%

6.3V

GND_VOID=TRUE

0.1UF

CERM-X5R0201

10%

6.3V

GND_VOID=TRUE

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

GND_VOID=TRUE

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

GND_VOID=TRUE

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

GND_VOID=TRUE

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

22.1K

MF 201

1% 1/20W

TPS2557DRB

SON

CRITICAL

SIGNAL_MODEL=MOJO_MUX_SMSC

CRITICAL

PI3USB102EZLE

TQFN

BYPASS=U4650.9:3:5mm

0.1UF

X5R-CERM

0201

10% 10V

100K

MF 201

5% 1/20W

14 74

38 39 74

38

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

CRITICAL

5.5V-0.28PF

0201-THICKSTNCL

CRITICAL

USB3.0-J44-ALT

F-RT-TH

5%

12PF

25V

NP0-C0G

0201

10UF

0402-2

20%

6.3V

CERM-X5R

0.1UF

X5R-CERM 0201

10% 16V

16

10UF

CERM-X5R

0402-2

20%

6.3V

22.1K

MF

201

1%

1/20W

CRITICAL

220UF-35MOHM

POLY-TANT CASE-B2-SM1

20%

6.3V

CRITICAL

FERR-120-OHM-3A

0603

SYNC_MASTER=J41

External A USB3 Connector

SYNC_DATE=10/23/2012

BOM_COST_GROUP=IO PORTS

=PP5V_S3_LTUSB

PP5V_S3_LTUSB_A_ILIM

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N

SMC_DEBUGPRT_EN_L

=PP3V42_G3H_SMCUSBMUX

USB_EXTA_P USB_EXTA_N

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

USB_ILIM

USB_ILIM_L

PP5V_S3_LTUSB_A_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

USB2_EXTA_MUXED_N

USB_EXTA_OC_L

=USB_PWR_EN

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_F_N USB2_EXTA_MUXED_F_P

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

C4695

1

2

C4691

1

2

C4690

1

2

R4600

1

2

C4696

1

2

L4605

12

C4605

1

2

L4600

12

34

C4620

12

C4621

12

D4610

1

2

D4620

1

2

D4611

1

2

D4621

1

2

R4601

1

2

U4600

4

8

1

5

2 3

6 7

9

U4650

6

7

3

4

5

8

10

9

2

1

C4650

1

2

R4650

1

2

D4600

1

2

D4601

1

2

J4600

5 6

4

7

10

11

20 21 22 23

12 13 14 15 16 17 18 19

9

3

2

8

1

C4606

1

2

dvt1

051-1573

8.0.0

46 OF 120

35 OF 82

68

71

74

64

74

71 74

OUT

IN

VDD

OUT_1

GND

THRM

OE

OUT_ALL#

OUT_3

OUT_2

IN_1

IN_3

IN_2

(IPD)

PAD

OUT

IN

BI

IN

OUT

IN

OUT

BI

IN

BI

OUT

SYM_VER_2

GS

D

OUT

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7

INT*

ADDR

SCL SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4 P1_5 P1_6 P1_7

GND

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7

INT*

ADDR

SCL SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4 P1_5 P1_6 P1_7

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

SHEET

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DRAWING NUMBER

REVISION

BRANCH

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

516S1037

NOTE: Mates with 516S1035 on IPD Flex

IO Expander / Keyboard Interface

No IPD on OE input pin PP3V3_S4 (symbol error).

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

(Write: 0x40 Read: 0x41)

518S0752

Keyboard Connector

(Write: 0x42 Read: 0x43)

311S0597

TBT

Pull-up in U5110.

Keys ANDed with PSoC power to isolate when PSoC is not powered.

IPD Interface

NOSTUFF

0.01UF

X5R-CERM

0201

10% 10V

201

MF

1/20W

10K

5%

201

MF

1/20W

10K

5%

201

MF

1/20W

10K

5%

201

MF

1/20W

10K

5% 5%

1/20W MF 201

10K

BYPASS=U4820.B3:E2:2MM

0.1UF

CERM-X5R 0201

10%

6.3V

BYPASS=U4820.B4:E2:2MM

0.1UF

CERM-X5R 0201

10%

6.3V

DF40BG-48DP-0.4V

CRITICAL

M-ST-SM

40 42 71

SM

PLACE_NEAR=J4802:3MM

40 71

38 39 40 71

37 71

TQFN

SLG4AP4103

15 71

37 71

14 71 74

37 71

36 71

39

36 71

41 71

62 71

BYPASS=U4850.10:5:5 mm

0402

10%

X7R-CERM

0.1UF

16V

402

10% 25V X5R

0.1UF

PLACE_NEAR=J4802.1:8MM

0201

NP0-C0G

25V

5%

12PF

5%

12PF

0201

NP0-C0G

25V

CRITICAL

2.5A-16V-0.1OHM

1812

2.0K

MF

201

5%

1/20W

1%

MF-LF

1/16W

100K

402

DFN1006H4-3

DMN32D2LFB4

2.0K

MF

201

5%

1/20W

10V

10%

X5R-CERM

NOSTUFF

0201

0.01UF

201

5% MF

10K

1/20W

100K

MF

1/20W

5%

201

10%

6.3V CERM 402

BYPASS=U4830.B4:E2:5MM

1UF

10K

MF

201

5%

1/20W

38 39 71

VFBGA

PCAL6416A

BYPASS=U4830.B3:E2:2MM

0.1UF

6.3V

10%

0201

CERM-X5R

BYPASS=U4830.B4:E2:2MM

CERM-X5R

6.3V

10%

0201

0.1UF

20%

PLACE_NEAR=J4813.5:5MM

0.1UF

CERM

402

10V

402

1K

MF-LF

5%

1/16W

0

402

5% 1/16W MF-LF

402

MF-LF

1%

113

1/16W

F-RT-SM

FF14A-30C-R11DL-B-3H

CRITICAL

100K

MF 201

5% 1/20W

BYPASS=U4820.B4:E2:5MM

402

1UF

CERM

10%

6.3V

PCAL6416A

VFBGA

402

0.1uF

10V

20%

CERM

PLACE_NEAR=J4802:3MM

0402-LF

FERR-120-OHM-1.5A

1/20W

201

MF

10K

5%

10K

1/20W MF

5%

201

MF

10K

201

1/20W

5%

10K

5% 1/20W MF 201

5%

10K

1/20W MF 201

10K

5% 1/20W MF 201

10K

5%

201

MF

1/20W

201

MF

1/20W

10K

5%

BOM_COST_GROUP=TRACKPAD

SYNC_MASTER=JACK_J52 SYNC_DATE=01/28/2014

Keyboard & Trackpad (1 of 2)

WS_CONTROL_KEY

SMC_TPAD_RST_L

WS_LEFT_OPTION_KEY

=PP5V_S4_TPAD

WS_KBD15_C

TPAD_SPI_INT_L

=TPAD_SPI_SCLK

WS_KBD16_NUM

WS_KBD14

=TPAD_SPI_BUS_EN

WS_KBD17

WS_KBD2

WS_KBD18

WS_KBD21 WS_KBD22

WS_KBD11

WS_KBD15_CAP

WS_KBD9

WS_KBD7

SMC_ONOFF_L

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

I2C_IOXP_SDA

I2C_IOXP_SCL

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

WS_KBD12

WS_KBD6

WS_KBD5

WS_KBD3

WS_KBD23

WS_KBD20

WS_KBD10

WS_KBD13

WS_KBD19

WS_KBD16N

WS_KBD2

WS_KBD4

WS_KBD3

WS_KBD1

TP_IOXP1_0

WS_KBD16N

TP_IOXP1_1 TP_IOXP1_2

TP_IOXP1_4

WS_KBD21

IOXP1_INT_L

I2C_IOXP_SCL

IOXP1_RESET_L

TP_IOXP1_DEBUG

WS_KBD15_C

WS_KBD5

IOXP2_INT_L

WS_CONTROL_KEY

WS_KBD12

WS_KBD18

WS_KBD6

WS_KBD17

WS_KBD8

WS_KBD19

WS_KBD13

WS_KBD10 WS_KBD14

WS_KBD11

=PP3V42_G3H_TPAD

WS_KBD4

WS_KBD_ONOFF_L

WS_KBD9

WS_KBD8

WS_KBD7

WS_KBD1

WS_KBD23

WS_KBD20 WS_KBD22

TP_IOXP1_3

I2C_IOXP_SDA

WS_LEFT_SHIFT_KEY

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

=PP3V42_G3H_TPAD

IOXP2_RESET_L

IOXP1_LED_DRV

USB_TPAD_N

I2C_IOXP_SCL IOXP2_INT_L

SMC_LID

=TPAD_WAKE_L

=I2C_TPAD_SDA

GND_ACTUATOR

I2C_IOXP_SDA

=I2C_TPAD_SCL

TPAD_ACTUATOR_EN_L

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

GND_ACTUATOR

USB_TPAD_P

=PP3V3_S4_TPAD

PP5V_S4_TPAD_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

PP5V_S4_TPAD_F

=TPAD_SPI_MISO =TPAD_SPI_CS_L =TPAD_SPI_MOSI

TPAD_ACTUATOR_THRMTRIP_L

TPAD_VBUS_EN

=PPVIN_S4_TPAD

PPVIN_S4_TPAD_FUSE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.6V

=PP3V3_S4_TPAD

C4824

1

2

R4822

1

2

R4823

1

2

R4821

1

2

R4820

1

2

C4820

1

2

U4820

B5

E2

A3 A1

C3 B1 C1 C2 D1 E1 D2

E3 E4 D3 E5 D4 D5 C5 C4

A2

A5 A4

B3

B4

C4821

1

2

C4822

1

2

U4850

5

1

2

3

4

9

8

7

6

11

10

C4850

1

2

R4840

1

2

Q4840

3

1

2

C4834

1

2

R4831

1

2

R4830

1

2

C4830

1

2

U4830

B5

E2

A3 A1

C3 B1 C1 C2 D1 E1 D2

E3 E4 D3 E5 D4 D5 C5 C4

A2

A5 A4

B3

B4

C4831

1

2

C4832

1

2

C4810

1

2

R4810

12

R4815

12

R4814

12

J4813

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

C4803

1

2

L4803

12

R4850

1

2

R4851

1

2

R4852

1

2

R4853

1

2

R4854

1

2

R4855

1

2

R4856

1

2

R4857

1

2

R4858

1

2

R4859

1

2

R4860

1

2

R4861

1

2

R4862

1

2

J4802

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48

49

5

50

51 52

6

78 9

XW4801

12

C4862

1

2

C4863

1

2

C4864

1

2

F4800

12

48 OF 120

8.0.0

051-1573

dvt1

36 OF 82

36

68

36

71

36 71

71

36 71

36

36 71

36

36 71

36

36 71

36

36 71 36 71

36

36 71

36 68

36 71

71

36 71

36

36 71

36 68

36 71

36 37 68 71

36 71

68 71

42

36 37 68 71

IN

D

SYM_VER_3

SG

IN

Y

A

B

08

Y

A

B

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ON KEYBOARD BACKLIGHT FLEX

Keyboard Backlight Connector

J4915 PIN 5 IS GROUNDED

.

516S0899

PIN 6 WAS USED KEYBOARD BKLT DETECTION

From PCH

NOT USED ANYMORE

TPAD SPI WITH SRC TERMINATION

(TPAD_SPI_CS_CONN_L)

From PCH

(TPAD_SPI_IF_EN_CONN)

AA07A-S010-VA1

CRITICAL

F-ST-SM

2015%1/20W

MF

15

5%

1/20W

MF15201

02010MF 5%

1/20W

15 75

SIGNAL_MODEL=TPAD_SPI_ISOL

DMN32D2LFB4

DFN1006H4-3

1/20W

5%

201

MF

100K

15

13 18 31 37 38 64 66

15

13 18 31 37 38 64 66

NOSTUFF

MF

100K

201

5% 1/20W

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

CRITICAL

74LVC2G08GT/S505

SOT833

BYPASS=U4810::3mm

0.1UF

CERM-X5R

6.3V 0201

10%

100PF

5%

0201

25V C0G

201

MF

1/20W

5%

33 33

5%

1/20W

MF

201

33

5%

201

MF

1/20W

0201

C0G

25V

100PF

5%

33

5%

1/20W

MF

201

BOM_COST_GROUP=TRACKPAD

SYNC_MASTER=JACK_J52SYNC_DATE=01/31/2014

Keyboard & Trackpad (2 of 2)

PM_SLP_S4_L

TPAD_SPI_IF_EN_CONN

TRUE

TPAD_VBUS_EN_R

TPAD_VBUS_EN

TRUE

TPAD_SPI_MOSI_R

TPAD_VBUS_EN_R_C

TPAD_SPI_MISO_R

TRUE

TPAD_SPI_IF_EN_R_C

TPAD_SPI_IF_EN_R

PM_SLP_S4_L

TPAD_SPI_IF_EN

=PP3V3_S4_TPAD

TPAD_SPI_CS_L

=PP3V3_S0_TPAD

TPAD_SPI_CS_CONN_L

TRUE

=PP3V3_S4_TPAD

=TPAD_SPI_BUS_EN

TPAD_USB_IF_EN

TPAD_SPI_MOSI

=TPAD_SPI_MISO

=TPAD_SPI_CS_L

=TPAD_SPI_MOSI

KBDLED_CATHODE1

TPAD_SPI_CLK

TPAD_SPI_MISO

=TPAD_SPI_SCLK

PPVOUT_S0_KBDBKLT

KBDLED_CATHODE2 PPVOUT_S0_KBDBKLT TP_KBKLT_NC

TRUE

TPAD_SPI_CLK_R

J4915

11

12

13 14

1

10

2

34 56 78 9

R4903

12

R4904

12

R4902

12

Q4960

3

1

2

R4960

1

2

R4910

1

2

U4910

5

6

4

8

3

U4910

1

2

4

8

7

C4941

1

2

C4942

1

2

R4911

12

R4912

12

R4914

12

C4943

1

2

R4913

12

dvt1

051-1573

8.0.0

49 OF 120

37 OF 82

36 71

36 37 68 71

68

36 37 68 71

36 71

15 75

36 71

60 71

15 75

36 71

37 60 71

60 71

37 60 71

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI

IN

BI

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(OD)

(PL6)

(PL7)

(OD)

(OD) (OD)

(OD)

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

(OD)

SMS INTERRUPT IS NOT USED, PULL UP TO SMC RAIL.

NOTE:

OMIT_TABLE

LM4FSXAH5BB

BGA

LM4FSXAH5BB

OMIT_TABLE

SM

PLACE_NEAR=U5000.A1:4MM

39 40 47 54 71

39

1/20W

5%

201

MF

1M

10V

10%

0201

X5R-CERM

0.1UF

10% X5R-CERM

0.1UF

10V 0201

X5R-CERM

0.1UF

10V

10%

02010201

X5R-CERM

0.1UF

10% 10V

10V

10%

0201

X5R-CERM

0.1UF

10V

10%

0201

X5R-CERM

0.1UF

10V

10%

0201

X5R-CERM

14 71 75

17

14 71 75

18

15 71

13 71

13

41 79

41 71 79

41 79

40

41 71 79

40

39 64

13 75

17 26 27 39 75

39

35 39 74

40

47 75

35

40

16 17 64

39

13 16 75

13 17 71 75

13 39

15

39 73

39 71

40

60

46

39

40

36 39 40 71

39

39 53

13 18

13 17 18 64 66 71

13 18 31 37 64 66

13 64

36 39 71

18 39

39 64

13 27

66

40

64

17

0402

30-OHM-1.7A

6

39 55 73

32

40

32

53

13 16 17 75

6

73

39

40

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U5000.K13:5MM

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U5000.K13:5MM

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U5000.J1:5MMPLACE_NEAR=U5000.D6:5MM

20%

6.3V 0201-1

X5R

1.0UF

10V

10%

0201

X5R-CERM

0.1UF

6.3V

20%

0201

X5R

1UF

40

6.3V

20%

0201

X5R

1UF

BYPASS=U5000.D2:D1:1MM

10V

10%

0201

X5R-CERM

0.01UF

BYPASS=U5000.D2:D1:1MM

40

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U5000.J1:5MM

10V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U5000.J6:5MM

6.3V

20%

0201-1

X5R

1.0UF

PLACE_NEAR=U5000.J6:5MM

6.3V

20%

0201-1

1.0UF

PLACE_NEAR=U5000.D6:5MM

X5R

39 40

40

39

40

62

25V

5%

12PF

0201

NP0-C0G

12PF

5% 25V

0201

NP0-C0G

BOM_COST_GROUP=SMC

SMC

SYNC_MASTER=JACK_J52 SYNC_DATE=11/07/2013

=PP3V3_S5_SMC

SMC_EXTAL

PP1V2_S5_SMC_VDDC

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.25MM VOLTAGE=1.2V

SMC_CLK32K

SMC_ADC6

LPC_SERIRQ

SMC_ADC23

SMC_ADC22

CPU_THRMTRIP_3V3

SMC_ADC20 SMC_ADC21

SMC_XTAL

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.25MM VOLTAGE=3.3V

PP3V3_S5_SMC_VDDA

SMC_WIFI_PWR_EN

SMC_TX_L

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

SMC_TDO SMC_TDI

SMC_RESET_L

NC_SMC_HIB_L

SMC_WAKE_L

WIFI_EVENT_L

NC_SMC_XOSC1

SMC_TCK SMC_TMS

SPI_SMC_MOSI

SMC_VCCIO_CPU_DIV2

SMC_CPU_DBGPWR_RD_L

CPU_CATERR_L

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_4_ASF_SCL

PM_SLP_S3_L

PM_SLP_S0_L

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_1_S0_SDA

SMC_PROCHOT

SMBUS_SMC_4_ASF_SDA

PM_SLP_S5_L

SMC_PME_S4_WAKE_L

SMBUS_SMC_1_S0_SCL

PM_DSW_PWRGD

SMC_PM_G2_EN

SMC_SYS_KBDLED

SMBUS_SMC_3_SCL

SMC_GFX_OVERTEMP

SMC_ONOFF_L

SMC_DELAYED_PWRGD

SPI_DESCRIPTOR_OVERRIDE_L

SPI_SMC_CS_L

SMBUS_SMC_3_SDA

SMC_DEBUGPRT_EN_L

SMC_LID

PM_SLP_S4_L

SMC_THRMTRIP

ALL_SYS_PWRGD

CPU_PROCHOT_L

SMC_S4_WAKESRC_EN

PM_BATLOW_L

MEM_EVENT_L

SMC_ADC19

SMC_ADC18

SMC_TOPBLK_SWP_L

SMC_ADC16 SMC_ADC17

SMC_RUNTIME_SCI_L

SMC_DEBUGPRT_RX_L

SMC_BC_ACOK

SMC_SYS_LED SMC_GFX_THROTTLE_L

SMC_ADC2 SMC_ADC3

SMC_DEBUGPRT_TX_L

SMBUS_SMC_0_S0_SCL

SMS_INT_L

SMC_ADC0 SMC_ADC1

SMBUS_SMC_0_S0_SDA

SMC_SENSOR_PWR_EN

SMC_PCH_SUSWARN_L

SMC_LRESET_L

SMC_FAN_1_CTL

SMC_ADC12

LPC_AD<0>

SMC_WAKE_SCI_L

SMC_ADC10

SMC_ADC15

SMC_ADC11

SMC_ADC9

SMC_ADC5

SMBUS_SMC_2_S3_SDA

SMC_ADC4

SMC_FAN_0_CTL SMC_FAN_0_TACH

SMC_ADC14

SMC_ADC13

LPC_PWRDWN_L

PM_CLKRUN_L

SMC_ADC7 SMC_ADC8

LPC_AD<2>

LPC_AD<1>

LPC_FRAME_L

LPC_CLK_SMC

LPC_AD<3>

S5_PWRGD

SPI_SMC_CLK

SMC_FAN_5_CTL

SMC_5VSW_PWR_EN SYS_ONEWIRE

CPU_PECI_R SMC_PECI_L

SMC_ACTUATOR_DISABLE_L

SMC_BIL_BUTTON_L SMC_DP_HPD_L

SMC_PME_S4_DARK_L

SMC_SENSOR_ALERT_L

SPI_SMC_MISO

SMC_PCH_SUSACK_L

SMC_S5_PWRGD_VIN

SMC_ACTUATOR_EN_L

BDV_BKL_PWM

SMC_OOB1_D2R_L

SMC_ADAPTER_EN

PM_SYSRST_L

PM_PWRBTN_L

SMC_OOB1_R2D_L

PM_PCH_SYS_PWROK

SMC_RX_L

SMC_PWRFAIL_WARN_L

SMC_FAN_1_TACH

U5000

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2

E10 D13

M4 N2 N8 M8 L8 K8 N7 M7 N4 N3

B13 A13 C12 D11 H12

G11

D12

F13

C13

F12

H13

L1

C4 C6

L9 K9

J4 J2

B12

C11

A12

H11 L13

G3

D10

L11 N12 N11 M11

M13 L12

M5

J12

J13

L5 D8 K6

D4 E4 F5

N5 N6 K5 M6 L6

M2 M3 L4 N1

L10 K10

M9 N9

F4 F3

C9 B9 A9 C8

D5

C5

L3 M1

F11 E11

E13 E12

K7 L7

K3 K4

J3 H4 H3 G4

H10

U5000

A1 C7

K11

D9 E5 F9 H5 H9 J5 J8 J11

C3

E3

M12

G12

G13

B11

G10 C10

A10 A11 B10

K12

D7 E6 E8 E9

F10

J7 J9

J10

D3

J1 J6

K13

D6

D1

D2

N13

M10

N10

XW5000

12

R5002

1

2

C5006

1

2

C5005

1

2

C5009

1

2

C5008

1

2

C5004

1

2

C5003

1

2

C5007

1

2

L5001

12

C5016

1

2

C5015

1

2

C5013

1

2

C5010

1

2

C5001

1

2

C5002

1

2

C5021

1

2

C5020

1

2

C5011

1

2

C5012

1

2

C5014

1

2

C5017

1

2

C5024

1

2

C5025

1

2

dvt1

051-1573

8.0.0

50 OF 120

38 OF 82

A2

39 40 68

39

39 39 71

39

40

42 43

44

39 71

71

39 47 71

IN

OUT

BI

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

SYM_VER_2

GS

D

NCNC

IN

SN0903049

PAD

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Used on mobiles to support SMC reset via keyboard.

SMC USB Clock require these crystal

SMC_DP_HD_L IS NOT USED ANY MORE

To SMC

SMC Crystal Circuit

SMC Reset "Button", Supervisor & AVREF Supply

Debug Power "Buttons"

values:5,6,8,10,12,16,18,20,24,25 MHz

MR1* and MR2* must both be low to cause manual reset.

Mobiles: 3.42V

(IPU) (IPU)

From SMC

From/To CPU/PCH

NOTE: Internal pull-ups are to VIN, not V+.

Desktops: 5V

SMC12 PECI Support

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

38 39

15 39 75

0

PLACE_SIDE=TOP

MF-LF

SILK_PART=PWR_BTN

OMIT

603

5% 1/10W

6

38 55 73

38

2.49K

MF

201

1/20W

1%

0201

CERM

25V

5%

12PF

100K

MF 2015%

1/20W

PLACE_SIDE=BOTTOM

SILK_PART=PWR_BTN

OMIT

0

MF-LF

603

5%

1/10W

SILK_PART=SMC_RST

PLACE_SIDE=BOTTOM

OMIT

0

MF-LF 603

5% 1/10W

36 38 39 71

36

0.01UF

X5R-CERM

0201

10% 10V

0.47UF

CERM-X5R

402

10%

6.3V

0.01UF

X5R-CERM 0201

10% 10V

100K

MF 201

5% 1/20W

38 40 47 54 71

13

PLACE_NEAR=U0500.AE6:5.1mm

22

MF 2015%

1/20W

38

100K

MF 2015%

1/20W

20K

MF 2015%

1/20W

20K

MF 2015%

1/20W

10K

MF 2015%

1/20W

12PF

5% 25V CERM 0201

100K

MF 201

1% 1/20W

100K

MF 201

1% 1/20W

36 38 39 71

38 73

NOSTUFF

1.6K

MF 201

5% 1/20W

0

MF

0201

5%

1/20W

MF 201

5% 1/20W

330

100K

MF 2015%

1/20W

100K

MF 2015%

1/20W

6 73

38 73

1/20W

5%

43

201

MF

15 39 75

CRITICAL

MMBT3904LP-7

DFN1006-3

38 39

10UF

X5R-CERM

0402-1

20% 10V

3.3K

MF

201

5%

1/20W

100K

MF 2015%

1/20W

CRITICAL

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

SIGNAL_MODEL=CPU_PECI_FET

CRITICAL

DMN32D2LFB4

DFN1006H4-3

NOSTUFF

4.7UF

X5R 402

20%

6.3V

0

MF-LF

402

5%

1/16W

10K

MF 2015%

1/20W

25

0201

C0G

25V

5%

47PF

NOSTUFF

PLACE_NEAR=Q5150.2:5MM

PLACE_NEAR=Q5159.6:5MM

0201

C0G

25V

5%

47PF

CRITICAL

VREF-3.3V-VDET-3.0V

DFN

100K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

SOT563

SIGNAL_MODEL=DMN5L06VK_7

SOT563

DMN5L06VK-7

BOM_COST_GROUP=SMC

SYNC_DATE=10/24/2013

SMC Shared Support

SYNC_MASTER=JACK_J52

SMC_PROCHOT

SMC_TPAD_RST_L

SMC_THRMTRIP

=PP3V3_S5_SMC

SMC_DELAYED_PWRGD

SMC_ADAPTER_EN

SMC_VCCIO_CPU_DIV2

CPU_THRMTRIP_3V3

=PPVIN_S5_SMCVREF

SMC_CLK32K

=TBT_WAKE_L

SMC_XTAL_R

SMC_DEBUGPRT_RX_L

SMC_TDI

SMC_PM_G2_EN

SMC_S4_WAKESRC_EN

SMC_TMS SMC_TDO

CPU_THRMTRIP_3V3

SMC_DEBUGPRT_TX_L

SMC_RESET_L

GND_SMC_AVSS

PM_CLK32K_SUSCLK_R

SMC_XTAL

PM_THRMTRIP_R_L

CPU_PECI

=PP1V05_S0_SMC

SMC_ONOFF_L

SMC_PECI_L

PM_THRMTRIP_L

SMC_MANUAL_RST_L

SMC_ONOFF_L

=PP3V3_S5_SMC

=PP1V05_S0_SMC

SMC_ONOFF_L SMC_SENSOR_ALERT_L

SMC_PME_S4_DARK_L SMC_DP_HPD_L

=PP3V3_S0_SMC

=PP3V3_S4_SMC

SMC_RX_L

SMC_TX_L

SMC_LID

SMS_INT_L

SMC_TCK

SMC_BC_ACOK

SMC_S5_PWRGD_VIN

SMC_EXTAL

=CHGR_ACOK

CPU_PROCHOT_L

PM_THRMTRIP_L

SMC_THRMTRIP

SMC_PECI_L_R

CPU_PECI_R

GND_SMC_AVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PP3V42_G3H_SMC_SPVSR

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

R5170

12

R5171

12

R5173

12

R5174

12

R5177

12

R5178

12

R5179

12

R5180

12

R5185

12

R5115

1

2

R5110

12

C5111

1

2

R5187

12

R5116

1

2

R5101

1

2

C5101

1

2

C5120

1

2

C5126

1

2

R5100

1

2

R5112

12

R5190

12

R5175

12

R5176

12

R5186

12

C5110

1

2

R5197

1

2

R5196

1

2

R5153

1

2

R5152

12

R5151

1

2

R5117

12

R5167

12

R5134

12

Q5158

1

3

2

C5125

1

2

R5158

12

R5191

12

Y5110

24

13

Q5150

3

1

2

C5127

1

2

R5127

12

R5172

12

C5134

1

2

C5131

1

2

U5110

4

2

6 7

8

5

9

1

3

R5198

12

R5192

12

R5193

12

R5168

12

Q5159

3

5

4

Q5159

6

2

1

dvt1

051-1573

8.0.0

51 OF 120

39 OF 82

38 39

38 39 40 68

17 26 27 38 75

13 38

38

68

35 38 74

38 71

38 64

38 47 71

38 71

38 39

35 38 74

38 39 40 42 43 44

38

75

39 68

38 39 40 68

39 68

36 38 39 71

38 40

18 38 39

38

68

18 40 68

38 71

36 38 40 71

38

38 47 71

38 39 53

38

54

38 39 40 42 43 44

18 38 39

38 39 53

38 71

OUT

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

IN

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

639-00525 (PCBA,HALL EFFECT,X304) REPORTS TO 677-01216

APN: 998-00296

Specify one of these BOM GROUPs.

Hall Effect Pads

RC Placeholder to filter noise on this signal towards SMC IO.

S4 SMC Wake Sources

Thermal Alerts

SMC12 ADC Assignments

SMC12 Pin Assignments

Top Block Swap

Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.

CPUTHRM_ALRT:SMC

MF

201

5%

100

1/20W

38

NOSTUFF

100

201

1/20W

5% MF

38

BMONHYS

201

5%

100

1/20W

MF

38

42

38 39

42

44

43

44

43

38

42

43

42

43

44

42

1K

5%

1/20W

MF

201

CPUTHRM_THRM:SMC

100

MF

201

5%

1/20W

TBTTHRM_THRM:SMC

100

MF

201

5%

1/20W

45

1K

5%

201

MF

1/20W

45

10%

NOSTUFF

0201

X7R-1

16V

1000PF

43

15

43

44

HALL-EFFECT-MLB-J44

SM

OMIT_TABLE

0

MF-LF

402

5%

1/16W

0.001UF

X7R-CERM 0402

10% 50V

MF 201

1/20W

5%

NOSTUFF

10K

MF 201

1/20W

5%

NOSTUFF

10K

38

MF

0201

5%

1/20W

0

13

MF

0201

5%

1/20W

0

CPUHYS

100

MF

201

5%

1/20W

43

SMCBOARDID:8

10K

MF 201

1/20W

5%

SMCBOARDID:16

10K

MF

1/20W

5%

201

42

43

42

36 42 71

1%

100

1/20W

MF

201

220PF

25V X7R-CERM

10%

45

31

36 71

100K

MF

5% 1/20W

201

38

45

44

14

TBTTHRM_ALRT:SMC

MF

5%

100

1/20W

201

TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU

TBTTHRM:NONE

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU

TBTTHRM:THRM

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC

TBTTHRM:BOTH

TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC

TBTTHRM:ALRT

CPUTHRM:NONE

CPUTHRM_THRM:PU,CPUTHRM_ALRT:PU

677-01216

CRITICAL

1

J5250

SUBASSY,PCBA,HALL EFFECT,X304

SMC Project Support

BOM_COST_GROUP=SMC

CPUTHRM_THRM:PU,CPUTHRM_ALRT:SMC

CPUTHRM:ALRT

CPUTHRM:THRM

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC

CPUTHRM:BOTH

SMC_TBT_ISENSE

MAKE_BASE=TRUE

SMC_PP5VS0_ISENSE

MAKE_BASE=TRUE

SMC_PCH_ISENSE

MAKE_BASE=TRUE

TPAD_ACTUATOR_EN_RC_L

SMC_BOARDID

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_BMON_DISCRETE_ISENSE

MAKE_BASE=TRUE

SMC_DDR_ISENSE

MAKE_BASE=TRUE

SMC_DDR1V8_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_TPAD_BOOST_DISABLE_L

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_5VSW_PWR_EN

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_5_CTL

MAKE_BASE=TRUE

SMC_TPAD_VSENSE

MAKE_BASE=TRUE

SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_PP3V3S0_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_BIL_BUTTON_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PWRFAIL_WARN_L

NO_TEST=TRUE

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUE

SMC_PCH_SUSACK_L

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

MAKE_BASE=TRUE

SMC_PCH_SUSWARN_L

MAKE_BASE=TRUE

SMC_TOPBLK_SWP_L

BDV_BKL_PWM

SMC_FAN_1_TACH

SMC_GFX_OVERTEMP

SMC_SYS_LED

SMC_5VSW_PWR_EN

SMC_FAN_1_CTL

SMC_GFX_THROTTLE_L

SMC_BIL_BUTTON_L

MEM_EVENT_L

SMC_FAN_5_CTL

SMC_PWRFAIL_WARN_L

SMBUS_SMC_4_ASF_SCL

SMC_ADC18

SMBUS_SMC_4_ASF_SDA

SMC_ADC21

SMC_ADC19

SMC_ADC23

SMC_ADC16

SMC_ADC15

SMC_ADC20

SMC_ADC14

SMC_ADC22

=PP3V3R1V8_S0_PCH_VCCSDIO

PCH_STRP_TOPBLK_SWP_L

PBUSVSENSE_EN

PM_WLAN_EN

P3V3S4SW_SNS_EN

PCH_SUSWARN_L

PCH_SUSACK_L

=TPAD_WAKE_L

SMC_CPU_DBGPWR_RD_L

TBTTHMSNS_THM_L

CPUTHMSNS_THM_L

SMC_ADC13

SMC_ADC12

SMC_ADC11

SMC_ADC8

SMC_ADC1

SMC_ADC5

SMC_ADC7

SMC_ADC10

SMC_ADC2

SMC_ADC3

SMC_ADC6

SMC_ADC9

SMC_ADC0

SMC_ADC4

PCH_SML1ALERT_L

CPUTHMSNS_ALERT_L

SMC_BMON_COMP_ALERT_L

SMC_CPUHI_COMP_ALERT_L

TPAD_ACTUATOR_EN_L

=PP3V3_S4_SMC

=PP3V3_S5_SMC

SMC_RESET_L

SMC_SENSOR_PWR_EN

=PP3V3_S4_SMC

BT_WAKE_L

SMC_ACTUATOR_EN_L

SMC_WIFI_PWR_EN

GND_SMC_AVSS

SMC_ADC17

=PP3V42_G3H_HALL

SMC_LID_R

SMC_LID

SMC_SENSOR_ALERT_L

TBTTHMSNS_ALERT_L

R5210

12

R5214

12

R5215

12

R5213

12

R5283

12

R5296

1

2

R5282

1

2

R5216

12

R5220

12

C5270

1

2

J5250

1 2 3 45

6

7

8

R5250

12

C5250

1

2

R5295

12

R5294

12

R5231

12

R5230

12

R5217

12

R5233

1

2

R5232

1

2

R5297

12

C5271

1

2

dvt1

051-1573

8.0.0

52 OF 120

40 OF 82

38 40

38

8

11 68

42

66

63

38

18 39 40 68

38 39 68

38 39 47 54 71

38 40

18 39 40 68

38

38 40

38 39 42 43 44

68

36 38 39 71

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC SMBus "2" S3 Connections

Parade T-con - (0x10-0x2F or 0x30-0x4F) Y Y

Samsung LGD

Internal DP

Battery Manager - (Write: 0x16 Read: 0x17)

Battery

SMC

U5000

(MASTER)

HDMI Redriver (on RIO)

U5000

J9510

(WRITE: 0xCC READ: 0xCD)

(Write: 0x98 Read: 0x99)

(Write: 0x12 Read: 0x13)

(Write: 0xD8 Read: 0xD9)

U0500

J4002

EMC1704-02: U5870

EMC1412: U5850

TMP105: J9510

J7050

ISL6259 - U7100

U5000

J8300

U5000

J1800

(Write: 0x88 Read: 0x89)

(Write: 0x72 Read 0x73)

access PCH.

SMLink 1 is slave port to

(MASTER)

SMC

ALS

Fixstack Prox

CPU, Mem, Airflow,

TBT & MLB Prox

X29 Temp (on RIO)

SMC

(See Table)

Battery

Battery Charger

(MASTER)

SMC

(See Table)

Internal DP

(MASTER)

SMC

(MASTER)

SMC SMBus "5" G3H Connections

U5000

J44

XDP Connectors

Trackpad

J4802

(Write: 0x98 Read: 0x99)

SMC SMBus "0" S0 Connections

SMC SMBus "1" S0 Connections

(MASTER)

SMC SMBus "3" S0 Connections

(MASTER)

(Write: 0x92 Read: 0x93)

WILDCAT POINT LP S0 "SMBus 0" Connections

WILDCAT POINT LP

U0500

WILDCAT POINT LP

WILDCAT POINT LP S0 "SMLink 1" Connections

WILDCAT POINT LP

U0500

WILDCAT POINT LP S0 "SMLink 0" Connections

2.0K

1/20W

5%

201

MF

2.0K

1/20W

5%

201

MF

2.0K

MF

201

5%

1/20W

2.0K

MF 201

5% 1/20W

MF

201

5%

1/20W

1K 1K

1/20W MF

5%

201

8.2K

MF

201

5%

1/20W

MF 201

5% 1/20W

8.2K

1/20W

1K

MF 201

5%5%

1K

MF

201

1/20W

2.0K

MF 201

5% 1/20W

2.0K

MF

201

5%

1/20W

2.0K

1/20W

5%

201

MF

2.0K

1/20W

5%

201

MF

SYNC_MASTER=GKOO_J52 SYNC_DATE=12/06/2013

SMBus Connections

BOM_COST_GROUP=SMC

=PP3V3_S0_SMBUS_SMC_3

=SMBUS_XDP_SCL

=I2C_ALS_SCL

=I2C_CPUTHMSNS_SCL

SML_PCH_1_CLK

=I2C_ALS_SDA

SML_PCH_1_DATA

=I2C_TPAD_SDA

=I2C_TPAD_SCL

=I2C_TBTTHMSNS_SCL

=I2C_TBTTHMSNS_SDA

=SMBUS_XDP_SDA

=I2C_X29THMSNS_SDA

=I2C_X29THMSNS_SCL

=SMBUS_BATT_SDA

=SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

=SMBUS_BATT_SCL

=I2C_TCON_SCL

=PP3V42_G3H_SMBUS_SMC_5

=PP3V3_S0_SMBUS_SMC_1

=I2C_TCON_SDA

=I2C_CPUTHMSNS_SDA

=I2C_HDMIRDRV_SCL

=PP3V3_S0_SMBUS_PCH

PP3V3_S0_EDP_SW

=PP3V3_S4_SMBUS_SMC_2

=I2C_HDMIRDRV_SDA

MAKE_BASE=TRUE

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

R5361

1

2

R5360

1

2

R5380

1

2

R5381

1

2

R5370

1

2

R5371

1

2

R5310

1

2

R5311

1

2

R5301

1

2

R5300

1

2

R5391

1

2

R5390

1

2

R5351

1

2

R5350

1

2

8.0.0

051-1573

dvt1

53 OF 120

41 OF 82

68

16

34

45

14 75

34

14 75

36 71

45

16

66

53

54

53

65 71

68

65 71

45

66

41 68

15 65

68

66

14 71 75 38 71 79

14 75

38 71 79

38 79

38 71 79

38 79

38 71 79

IN

OUT

IN-

IN+ REF

V+

GND

IN

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

NC NC

NCNC

SYM_VER_2

GS

D

IN

GND

OUT

VIN+ VIN-

V+

V-

V+

+

-

V-

V+

+

-

V-

V+

+

-

IN

SYM_VER_2

GS

D

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN-

IN+ REF

V+

GND

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

OTHER 3.3V High Side Current Sense (IO3R)

Final Filter RC TBD

SMC ADC: 16

Vnominal: 28 V, Range: 30.64 V

Trackpad Actuator X239 Voltage Sense (VTPC)

Charger Gain: 20x, EDP: 4.6 A

DC-IN (AMON) Current Sense (ID0R)

Trackpad Actuator X239 Current Sense (ITPC)

Gain: 4.99x, EDP: 2.61 A (Transient)

Vsense: 261 mV, Range: 5 A SMC ADC: 11

Short Rsense

LCD Backlight Current Sense (IBLC)

Gain: 100x. EDP: 0.9 A Rsense: 0.025 (R7700) Vsense: 22.5 mV, Range: 1.32 A

Charger (BMON) Current Sense (IPBR)

Vsense: 15 mV, Range: 5.5 A

SMC AD: 10

Vsense: 30 mV, Range: 6.6 A SMC ADC: 07

Rsense: 0.005 (R5410) or Rsense SHORT

OTHER 5V High Side Current Sense (IO5R)

Gain: 0.10771

Gain: 0.148x Vnominal: 16.5 V, Range: 22.29 V

(to CPU High Side Threshold

Vsense: 31.5 mV, Range: 11 A

Rsense: 0.003 (R5400)

Gain: 100x, EDP: 10.5 A

divider when AC present.

Rthevenin = 4573 Ohms

SMC ADC: 00

Rsense: 0.020 (R7120)

SMC ADC: 01

Rthevenin = 4573 Ohms

divider when in S0.

PBUS Voltage Sense & Enable (VP0R)

Gain: 0.167x

SMC ADC: 04

SMC ADC: 03

100x

Alert circuit)

CPU High Side Current Sense (IC0R)

Enables DC-In VSense

Vnominal: 12.6 V, Range: 19.7 V

Enables PBUS VSense

100x

SMC ADC: 02

DC In Voltage Sense & Enable (VD0R)

Gain: 100x, EDP: 6 A

200x

Rsense: 0.003 (R5440) or Rsense SHORT

Gain: 200x, EDP: 5 A

Short Rsense

SMC ADC: 08

Rsense: 0.005 (R7150)

Charger Gain: 36x, EDP: 8 A

100x

Gain: 200uA/V * 24.9KOhm = 4980

Rsense: 0.02 (R5460)

54

X7R-CERM 0201

10% 10V

3300PF

PLACE_NEAR=U5000.F2:5MM

PLACE_NEAR=U7700.1:10MM

CRITICAL

LOADISNS

INA214

PLACE_NEAR=U7700.2:10MM

SC70

60 80

MF

OTHERISNS

1%

15K

PLACE_NEAR=U5410.6:5MM

201

1/20W

PLACE_NEAR=U5440.6:5MM

MF

1/20W

1%

201

OTHERISNS

15K

40

6.04K

PLACE_NEAR=U5450.6:5MM

1% MF

201

1/20W

LOADISNS

201

15K

MF

1/20W

PLACE_NEAR=U5400.6:5MM

5%

43

68

0.1UF

20% 10V

402

CERM

TPADISNS

BYPASS=U5460.5::5MM

SC70

INA214

CRITICAL

OTHERISNS

201

4.53K

MF

1/20W

1%

TPADRC:YES

PLACE_NEAR=U5000.A6:5MM

6.3V

0.22UF

TPADRC:YES

0201

X5R

20%

PLACE_NEAR=U5000.A6:5MM

68

40

SM

BYPASS=U5410.3:2:5MM

0.1UF

CERM

20%

402

OTHERISNS

10V

10.2K

MF

1%

201

1/20W

201

MF

1/20W

84.5K

1%

PLACE_NEAR=U5000.G2:5MM

4.53K

1%

201

MF

1/20W

PLACE_NEAR=U5000.G2:5MM

0201

X5R

20%

6.3V

0.22UF

40

MF

1 W

PLACE_NEAR=U5410.5:10MM

0

PLACE_NEAR=U5410.4:10MM

0612-SHORT

CRITICAL

OMIT

0612-SHORT

0.003

CRITICAL

1%

MF

1W

PLACE_NEAR=U5440.4:10MM

PLACE_NEAR=U5440.5:10MM

MF

1%

1/20W

4.53K

201

OTHERRC:YES PLACE_NEAR=U5000.A4:5MM

NOSTUFF

402

10V

CERM

20%

0.1UF

BYPASS=U5461.5::5MM

MF

1%

CRITICAL

1W

0.001

0612-SHORT

OMIT

PLACE_NEAR=U5460.4:3MMPLACE_NEAR=U5460.3:3MM

BAT54DW-X-G

SOT-363

NOSTUFF

CRITICAL

NOSTUFF

CRITICAL

SOT-363

BAT54DW-X-G

0201

X5R

6.3V

OTHERRC:YES

20%

0.22UF

PLACE_NEAR=U5000.A4:5MM

BYPASS=U5462.5::5MM

TPADISNS

CERM

10V

0.1UF

20%

402

DMN32D2LFB4

DFN1006H4-3

NOSTUFF

36 40

42

71

SOT23-5

CRITICAL

INA139

TPADISNS

CRITICAL

NOSTUFF

SOT-23

OPA340NA

CRITICAL

OPA340NA

SOT-23

TPADISNS

5%

MF-LF

NOSTUFF

402

39

1/16W

1%

402

MF-LF

1/16W

100

PLACE_NEAR=U5462:5MM

NOSTUFF

2200PF

CERM

5%

0402

10V

NOSTUFF

TPADISNS

402

1/16W

5%

MF-LF

0

OPA340NA

SOT-23

CRITICAL

TPADRC:YES

1/20W

TPADRC:YES

MF

1%

201

10K

TPADRC:YES

10K

1% MF

201

1/20W

NOSTUFF

1/20W

1%

10K

MF

201

54

DFN1006H4-3

DMN32D2LFB4

NOSTUFF

TPADISNS

24.9K

MF-LF 402

1/16W

1%

NOSTUFF

0

5%

402

1/16W MF-LF

10%

0201

0.15UF

X5R

6.3V

NOSTUFF

201

47

5%

MF

1/20W

NOSTUFF

10K

201

TPADRC:YES

1/20W

1% MF

402

CERM

20% 10V

0.1UF

BYPASS=U5400.3:2:5MM

0.22UF

X5R 0201

20%

6.3V

PLACE_NEAR=U5000.E2:5MM

4.53K

MF

201

1%

1/20W

PLACE_NEAR=U5000.E2:5MM

402

1/16W

69.8K

1%

MF-LF

40

1/16W

1%

402

MF-LF

100K

5.49K

MF-LF

402

1%

1/16W

PLACE_NEAR=U5000.B3:5MM

31.6K

MF-LF

402

1%

1/16W

PLACE_NEAR=U5000.B3:5MM

6.3V

20%

0201

X5R

0.22UF PLACE_NEAR=U5000.B3:5MM

SOT-963

NTUD3169CZ

CRITICAL

MF-LF

402

1%

200K

1/16W

5.49K

MF-LF

402

1%

1/16W

PLACE_NEAR=U5000.E1:5MM

0.22UF

X5R 0201

20%

6.3V

PLACE_NEAR=U5000.E1:5MM

40

SOT-963

CRITICAL

NTUD3169CZ

100K

MF-LF

402

1%

1/16W

PLACE_NEAR=U5000.E1:5MM

27.4K

MF-LF

402

1%

1/16W

40

PLACE_NEAR=R5400.1:10 MM

SM

SC70

INA214

CRITICAL

20%

0.1UF

402

10V CERM

OTHERISNS BYPASS=U5440.3:2:5MM

1%

4.53K

201

MF

1/20W

OTHERRC:YES PLACE_NEAR=U5000.B5:5MM

OTHERRC:YES

6.3V

20% X5R

0.22UF

0201

PLACE_NEAR=U5000.B5:5MM

40

64

201

45.3K

MF

1%

1/20W

PLACE_NEAR=U5000.F1:5MM

SC70

INA210

CRITICAL

OTHERISNS

0612

1% 1W

CYN

0.003

PLACE_NEAR=U5400.5:10MM

CRITICAL

PLACE_NEAR=U5400.4:10MM

0201

2200PF

X7R-CERM

10% 10V

PLACE_NEAR=U5000.F1:5MM

BYPASS=U5450.3:2:5MM

0.1UF

10V CERM

LOADISNS

20%

402

PLACE_NEAR=U5000.B6:5MM

LOADRC:YES

4.53K

1/20W

1% MF

201

20%

0.22UF

X5R

6.3V

PLACE_NEAR=U5000.B6:5MM

LOADRC:YES

0201

40

1/20W

MF

1%

201

PLACE_NEAR=U5000.F2:5MM

300K

LOADRC:NO

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5459

117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

2

117S0008

C5419,C5449

OTHERRC:NO

C5469

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

TPADRC:NO

117S0008

Power Sensors: High Side

SYNC_DATE=12/15/2013

BOM_COST_GROUP=SENSORS

SYNC_MASTER=JACK_J52

ISNS_LCDBKLT_IOUT

=PPVIN_S5_HS_OTHER3V3_ISNS_R

ISNS_HS_OTHER3V3_P

ISNS_HS_OTHER3V3_N

=PP3V3_S4_ISNS

=PP3V3_S4_HS_OTHER_ISNS

SMC_BMON_ISENSE

SMC_OTHER3V3_HI_ISENSE

ISNS_X239_PEAK_R

ISNS_X239_PEAK_CAP

DCINVSENSE_EN

=PPVIN_X239_PBUS_ISNS_R

ISNS_X239_IOUT_D

=PP3V3_S4_HS_OTHER_ISNS

TPAD_ACTUATOR_EN_L

ISNS_X239_IOUT_BUF

=PP3V3_S4_ISNS

GND_SMC_AVSS

PBUSVSENSE_EN

HS_OTHER3V3_IOUT

ISNS_HS_OTHER5V_N

SMC_OTHER5V_HI_ISENSE

GND_SMC_AVSS

ISNS_X239_IOUT

ISNS_X239_IOUT_INT

GND_SMC_AVSS

ISNS_TPAD_N

=PP3V3_S4_ISNS

VOUT_X239_XW

ISNS_X239_INT_DIS

TPAD_ACTUATOR_EN_L

ISNS_TPAD_P

CHGR_AMON

=PP3V3_S0_HS_COMPUTING_ISNS

SMC_DCIN_ISENSE

GND_SMC_AVSS

SMC_DCIN_VSENSE

SMC_PBUS_VSENSE

DCINVSENS_EN_L

PBUSVSENS_EN_L_DIV

GND_SMC_AVSS

PBUS_S0_VSENSE_IN

=PPBUS_S0_VSENSE

PBUSVSENS_EN_L

SMC_CPU_HI_ISENSE

PBUS_S0_VSENSE

PDCINVSENS_EN_L_DIV

GND_SMC_AVSS

SMC_TPAD_ISENSE

CHGR_BMON

VOUT_X239_DIV

ISNS_X239_PEAK_FBK

CPUHI_IOUT

DCIN_S5_VSENSE

=PPVIN_S5_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

GND_SMC_AVSS

=PPVIN_S5_HS_COMPUTING_ISNS_R

HS_OTHER5V_IOUT

GND_SMC_AVSS

=PPDCIN_S5_VSENSE

SMC_LCDBKLT_ISENSE

=PP3V3_S4_ISNS

ISNS_HS_OTHER5V_P

=PPVIN_S5_HS_OTHER5V_ISNS_R

=PPVIN_S5_HS_OTHER5V_ISNS

=PPVIN_S5_HS_OTHER3V3_ISNS

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

=PPVIN_X239_PBUS_ISNS

SMC_TPAD_VSENSE

ISNS_X239_INT_NI

=PP3V3_S4_ISNS

ISNS_X239_IOUT_INT

PPVIN_S4_TPAD_FUSE

ISNS_X239_INT_I

R5439

12

C5439

1

2

R5429

12

C5429

1

2

U5410

2

5

4

6

1

3

C5411

1

2

R5419

12

C5419

1

2

C5401

1

2

C5409

1

2

R5409

12

R5491

1

2

R5481

1

2

R5499

1

2

R5498

1

2

C5499

1

2

Q5490

6

3

2

5

1

4

R5492

1

2

R5489

1

2

C5489

1

2

Q5480

6

3

2

5

1

4

R5482

1

2

R5488

1

2

XW5480

12

U5400

2

5

4

6

1

3

C5441

1

2

R5449

12

C5449

1

2

U5440

2

5

4

6

1

3

R5400

123

4

C5450

1

2

R5459

12

C5459

1

2

U5450

2

5

4

6

1

3

R5415

1

2

R5445

1

2

R5455

1

2

R5405

1

2

C5460

1

2

R5469

12

C5469

1

2

XW5470

12

R5478

1

2

R5477

1

2

R5479

12

C5479

1

2

R5410

123

4

R5440

123

4

C5461

1

2

R5460

12 34

D5461

16

D5461

43

C5462

1

2

Q5460

3

1

2

U5460

2

15

34

U5461

3

4

1

2

5

U5462

3

4

1

2

5

R5463

1

2

R5462

12

C5463

12

R5464

12

U5463

3

4

1

2

5

R5467

12

R5468

12

R5466

12

Q5461

3

1

2

R5461

1

2

R5471

12

C5464

1

2

R5470

1

2

R5465

12

dvt1

051-1573

8.0.0

54 OF 120

42 OF 82

52

68

80

42 43 44 68

42 68

42 43 44 68

38 39 40 42 43 44

80

38 39 40 42 43 44

80

42 43 44 68

36 40 42 71

80

43 68

38 39 40 42 43 44

68

38 39 40 42 43 44

68

44

80

44

80

38 39 40 42 43 44

68

38 39 40 42 43 44

68

42 43 44 68

80

68

58 68

42 43 44 68

42

36

OUT

IN

SYM_VER_2

GS

D

OUT

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

V+

V-

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

200x

DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)

CPU High Side Current (IC0R) Threshold Alert

Vth = 0.616 V -> 2.054 A on CPU High current

Rsense: 0.005 (R7829) or Rsense SHORT

3.3V S0 Rail Current Sense (IR3C)

Vsense: 5.5 mV, Range: 1.32 A

Rsense: 0.005 (R5520) or Rsense SHORT

Vtl = 0.771 V -> 2.571 A on CPU High current

Hysteresis Circuit:

DDR 1.8V Current Sense (IM2C)

Vsense: 5.5 mV, Range: 1.32 A

Gain: 500x, EDP: 1.1 A

SMC ADC: 14

SMC ADC: 18

SSD Current Sense (ISDC)

Rsense: 0.003 (R7640) or Rsense SHORT Vsense: 15.6 mV, Range: 5.5 A

Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375

SMC ADC: 06

Rsense: 0.005 (R5580) Vsense: 12.5 mV, Range: 3.3 A

200x

SMC ADC: 19

SMC ADC: 17

Gain: 219.33x, EDP: 40 A

Vsense: 15 mV, Range: 40.12 A

SMC ADC: 13

SMC ADC: 12

500x

Gain: 200x, EDP: 5.2 A

200x

CPU Fixed Current Sense (IC0C)

Gain: 500x, EDP: 0.45 A

PCH 1.05V Current Sense (IC1C)

Hysteresis Margin = 0.518 A

107S00030

Vref = 0.737 V

Trip Target on CPU High current: 2.5 A

Gain: 200x, EDP: 2.5 A (8.2 W)

Gain: 200x, EDP: 9.5 A Rsense: 0.002 (R7450) or XW7450

SMC ADC: 09

Rsense: 0.003 (R5400)

500x

Rsense: 0.005 (R5510) or Rsense SHORT

500x

Gain: 100x

Vsense: 2.25 mV, Range: 1.32 A

Gain: 500x, EDP: 1.1 A

Short Rsense

500x

Rsense: 0.005 (R5530) or Rsense SHORT Vsense: 5 mV, Range: 1.32 A

Gain: 500x, EDP: 1.0 A

5V S0 Rail Current Sense (IR5C)

Short Rsense

CPU DDR 1.2V S3 (CPU Only) Current Sense (IM1C)

Vsense: 19 mV, Range: 8.25 A

LOADISNS

1.05K

MF

201

1%

1/20W

LOADISNS

1.05K

MF

201

1%

1/20W

40

20%

PLACE_NEAR=U5000.C2:5MM

0.22UF

X5R 0201

6.3V

201

4.53K

MF

1%

1/20W

PLACE_NEAR=U5000.C2:5MM

0.1uF

CERM 402

20% 10V

BYPASS=U5580.3:2:5MM

10V

0.1UF

CERM

20%

DDRISNS BYPASS=U5570.3:2:5MM

402

MF

4.53K

201

1%

DDRRC:YES PLACE_NEAR=U5000.A5:5MM

1/20W

X5R

20%

6.3V

PLACE_NEAR=U5000.A5:5MM DDRRC:YES

0.22UF

0201

40

PLACE_NEAR=U5000.H1:5MM

6.3V

LOADRC:YES

X5R

20%

0.22UF

0201

1%

1/20W

4.53K

MF

201

PLACE_NEAR=U5000.H1:5MM

LOADRC:YES

10V

BYPASS=U5510.3:2:5MM

20%

402

CERM

LOADISNS

0.1UF

40

20%

0.22UF

0201

X5R

6.3V

LOADRC:YES

PLACE_NEAR=U5000.B1:5MM

4.53K

201

LOADRC:YES

MF

1%

1/20W

PLACE_NEAR=U5000.B1:5MM

BYPASS=U5520.3:2:5MM

20% 10V

402

CERM

LOADISNS

0.1UF

40

CERM

10V

BYPASS=U5530.3:2:5MM

LOADISNS

0.1UF

402

20%

X5R

20%

6.3V

0.22UF

0201

LOADRC:YES

PLACE_NEAR=U5000.G1:5MM

1/20W

MF

1%

4.53K

LOADRC:YES

201

PLACE_NEAR=U5580.4:10MM

1% 1W MF

PLACE_NEAR=U5580.5:10MM

0612-6

0.005

CRITICAL

57 68

57

1/20W

20K

MF 201

5%

NOSTUFF PLACE_NEAR=U5560.6:5MM

1/20W

20K

MF 201

5%

PLACE_NEAR=U5570.6:5MM

NOSTUFF

MF 201

PLACE_NEAR=U5520.6:5MM

1/20W

5%

20K

1/20W

PLACE_NEAR=U5530.6:5MM

LOADISNS

51K

MF 201

5%

PLACE_NEAR=U5580.6:5MM

20K

NOSTUFF

MF 201

5% 1/20W

PLACE_NEAR=U5540.4:5MM

20K

1/20W

NOSTUFF

MF 201

5%

NOSTUFF

SM-201

RB521ZS-30

1/20W

0

MF 0201

5%

NOSTUFF

201

MF

1% 1/20W

84.5K

CPUHYS

294K

1/20W

CPUHYS

MF 201

1%

CPUHYS

0

MF 0201

5% 1/20W

X5R

NOSTUFF

0.1UF

402

10% 25V

BYPASS=U5551.5:2:3MM

CPUHYS

CERM-X5R 0201

10%

6.3V

0.1UF

CPUHYS

DMN32D2LFB4

DFN1006H4-3

40

CPUHYS

255K

MF-LF

402

1%

1/16W

NOSTUFF

0.22UF

X5R

0201

20%

6.3V

CPUHYS

MCP6541T

SC70-5

PLACE_NEAR=U5510.6:5MM

MF

20K

5% 1/20W

201

NOSTUFF

CPUHYS

12K

MF

201

1%

1/20W

CRITICAL

SC70

LOADISNS

INA211

CRITICAL

SC70

INA211

LOADISNS

CRITICAL

DDRISNS

SC70

INA210

40

PLACE_NEAR=U5000.G2:5MM

0.22UF

X5R 0201

20%

6.3V

LOADRC:YES

201

PLACE_NEAR=U5000.G2:5MM

LOADRC:YES

4.53K

MF

1%

1/20W

NOSTUFF

20K

MF 201

5%

PLACE_NEAR=U5590.6:5MM

LOADISNS

CERM 402

20% 10V

0.1uF

BYPASS=U5590.3:2:5MM

INA211

SC70

LOADISNS

CRITICAL

PLACE_NEAR=R7829.3:5MM

PLACE_NEAR=R7829.4:5MM

61 80

42

OMIT

0

0612-SHORT

1 W

0

PLACE_NEAR=U5510.4:10MM

PLACE_NEAR=U5510.5:10MM

CRITICAL

MF

OMIT

PLACE_NEAR=U5520.5:10MM

MF

CRITICAL

0

1 W

0612-SHORT

PLACE_NEAR=U5520.4:10MM

PLACE_NEAR=U5530.4:10MM

PLACE_NEAR=U5530.5:10MM

CRITICAL

MF

0

1 W

OMIT

0612-SHORT

SC70

LOADISNS

INA210

CRITICAL

SC70

LOADISNS

INA211

INA210

SC70

CRITICAL

59 80

CERM

BYPASS=U5560.3:2:5MM

LOADISNS

0.1uF

402

20% 10V

LOADRC:YES

MF

201

1%

1/20W

4.53K

PLACE_NEAR=U5000.H2:5MM

X5R 0201

20%

6.3V

0.22UF

LOADRC:YES

PLACE_NEAR=U5000.H2:5MM

40

56 80

4.42K

NO_XNET_CONNECTION=TRUE

0402

1/16W

LOADISNS

MF

0.1%

PLACE_NEAR=R7320.4:5MM

NO_XNET_CONNECTION=TRUE

LOADISNS

715K

MF 402

0.1% 1/16W

0.1%

1/16W

715K

MF

402

NO_XNET_CONNECTION=TRUE

LOADISNS

56 80

4.42K

0.1%

LOADISNS

0402

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7310.3:5MM

1/16W

MF

LOADISNS

4.42K

MF

0402

0.1%

1/16W

PLACE_NEAR=R7320.3:5MM NO_XNET_CONNECTION=TRUE

MF

0402

0.1%

1/16W

4.42K

LOADISNS

PLACE_NEAR=R7310.4:5MM NO_XNET_CONNECTION=TRUE

CRITICAL

ISL28133

LOADISNS

SC70-5

10V

LOADISNS

BYPASS=U5540.5:2:3MM

0.1UF

CERM 402

20%

LOADRC:YES

6.3V

PLACE_NEAR=U5000.B4:5MM

X5R 0201

20%

0.22UF

PLACE_NEAR=U5000.B4:5MM

201

1/20W

1%

LOADRC:YES

4.53K

MF

40

C5569,C5519,C5599

3

LOADRC:NO

117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5529,C5539,C5549

LOADRC:NO

3

117S0008

C5579

DDRRC:NO117S0008

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

BOM_COST_GROUP=SENSORS

SYNC_DATE=12/06/2013SYNC_MASTER=JACK_J52

Power Sensors: Load Side

=PPDDR_S3_REG

PPDDR_S3_REG_R

P1V8S3_IOUT

ISNS_PP5VS0_N

ISNS_PP5VS0_P

=PP5V_S0_ISNS_R

SMC_PP5VS0_ISENSE

=PP3V3_S4_ISNS

ISNS_PP3V3S0_N

ISNS_PP3V3S0_P

=PP3V3_S4_ISNS

=PP3V3_S0_ISNS

=PP3V3_S0_ISNS_R

ISNS_CPUDDR_P

ISNS_CPUDDR_N

=PP3V3_S4_ISNS

=PP3V3_S0_HS_COMPUTING_ISNS

GND_SMC_AVSS

P1V05S0_IOUT

CPUVR_ISNS2_N

DIFFERENTIAL_PAIR=CPUVR_ISEN2

ISNS_1V8_S3_N

GND_SMC_AVSS

ISNS_SSD_N

ISNS_SSD_P

CPUVR_ISNS1_P

DIFFERENTIAL_PAIR=CPUVR_ISEN1

CPUVR_ISNS1_N

DIFFERENTIAL_PAIR=CPUVR_ISEN1

CPUVR_ISNS2_P

DIFFERENTIAL_PAIR=CPUVR_ISEN2

SMC_CPU_ISENSE

CPUVR_ISNS_N

SMC_PCH_ISENSE

ISNS_1V05_S0_P

ISNS_1V05_S0_N

GND_SMC_AVSS

CPUHI_COMP_VREF

GND_SMC_AVSS

=PP3V3_S4_ISNS

SMC_DDR1V8_ISENSE

ISNS_PP5VS0_IOUT

GND_SMC_AVSS

SMC_SSD_ISENSE

CPUHI_COMP_OUT

CPUHI_COMP_FB

SMC_CPUHI_COMP_ALERT_L

BMON_IOUT_D

ISNS_1V8_S3_P

=PP3V3_S4_ISNS

CPUHI_IOUT

CPUVR_ISNS_P

CPUVR_ISNS_R_P

=PP3V3_S0_VRISNS

CPUVR_ISNS_R_N

CPUVR_ISUM_IOUT

=PP3V3_S4_ISNS

=PP3V3_S0SW_SSD_ISNS

=PP3V3_S0SW_SSD_ISNS_R

=PP5V_S0_ISNS

ISNS_DDR_IOUT

GND_SMC_AVSS

ISNS_PP3V3S0_IOUT

SMC_CPUDDR_ISENSE

=PP1V2_S3_CPUDDR_ISNS

SMC_PP3V3S0_ISENSE

=PP1V2_S3_CPUDDR_ISNS_R

CPUHI_IOUT_R

ISNS_S0_SSD_IOUT

ISNS_CPUDDR_IOUT

=PP3V3_S4_ISNS

SMC_DDR_ISENSE

C5560

1

2

R5569

12

C5569

1

2

R5548

12

R5544

1

2

R5541

12

R5547

12

R5546

12

R5545

12

U5540

3

1

4

2

5

C5540

1

2

C5549

1

2

R5549

12

R5543

12

R5542

12

C5589

1

2

R5589

12

C5580

1

2

C5570

1

2

R5579

12

C5579

1

2

C5519

1

2

R5519

12

C5510

1

2

C5529

1

2

R5529

12

C5520

1

2

C5530

1

2

C5539

1

2

R5539

12

R5580

123

4

R5565

1

2

R5575

1

2

R5525

1

2

R5535

1

2

R5585

1

2

R5540

1

2

D5557

A

K

R5557

1

2

R5555

1

2

R5554

1

2

R5552

1

2

C5552

1

2

C5551

1

2

U5552

3

1

2

R5553

12

C5553

12

U5551

3

4

1

5

2

R5515

1

2

R5556

12

U5520

2

5

4

6

1

3

U5530

2

5

4

6

1

3

U5570

2

5

4

6

1

3

C5599

1

2

R5599

12

R5595

1

2

C5590

1

2

U5590

2

5

4

6

1

3

R5510

123

4

R5520

123

4

R5530

123

4

U5560

2

5

4

6

1

3

U5510

2

5

4

6

1

3

U5580

2

5

4

6

1

3

dvt1

051-1573

8.0.0

55 OF 120

43 OF 82

80

68

42 43 44 68

80

42 43 44 68

68

80

42 68

38 39 40 42 43 44

80

38 39 40 42 43 44

44

42 43

44

68

80 80

68

80

42 43 44 68

68

38 39 40 42 43 44

68

42 43 44 68

OUT

IN

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

SYM_VER_2

GS

D

IN

V+

REFIN+

IN-

OUT

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

CHGR_CSO_R_P/N are swapped on purpose

Thunderbolt TBT Current/Voltage Sense (IHSC/VHSC)

Vref = 0.854 V

Hysteresis Margin = 0.518 A

Gain: 200x. EDP: 2.8 A

SMC ADC: 22

With R7210 (Ri) set to 316 Ohm,

CPU Core IMON Current Sense (IC2C)

Gain: 1 A / 28.273 mV, Range: 40 A.

present on IN+/- pins with INA output voltage decreasing

With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV

This deviation has been designed in our Peak Detection circuit.

SENSE+ pins of EMC1704 sink 10-20uA current.

from 3.3V with increasing discharge current.

CPU High Side (IC0R) Peak Detection Support

200x

Vsense: 50 mV, Range: 13.2 A

Gain: 50x. EDP: 8 A Rsense: 0.005 (R7150)

SMC AD: 05

50x

Hysteresis Circuit:

SMC ADC: 20

R7230 set to 95.3 kOhm,

R7310 (Rsen) set to 0.75 mOhm,

Num Phases (N) is 2, and Io (ICCmax) is 40A, then 1A of Io gives 28.273mV at the Vimon.

Rsense: 0.005 (R5640) or Rsense SHORT Vsense: 14 mV, Range: 3.3 A SMC AD: 23

200x

500x

SMC AD: 21

Battery BMON Discrete Current Sense (IP0R) & Threshold Alert

into system.

to measure Battery discharge power

500x

CPU Core Voltage Sense (VC0C)

Vtl = 0.887 V -> 3.549 A on Battery current

Trip Target on Battery current: 3.5 A

Vth = 0.758 V -> 3.031 A on Battery current

Short Rsense

Vsense: 5 mV, Range: 1.32 A

RSENSE: 0.005 (R8320) or Rsense SHORT

Gain: 500x. EDP: 1 A

LCD Panel Current Sense (ILDC)

SMC AD: 15

Gain: 500x. EDP: 0.82 A Rsense: 0.005 (R5610) or XW5610 Vsense: 4.1 mV, Range: 1.32 A

Camera (S2 Controller) Current Sense (ICMC)

In battery discharge scenario negative voltage will be

0.22UF

0201

20%

6.3V X5R

BMONRC:YES

PLACE_NEAR=U5000.A3:5MM

1% MF

201

4.53K

1/20W

BMONRC:YES

40

0201

MF

0

5% 1/20W

BMONHYS

0.1UF

402

10% 25V X5R

NOSTUFF

BMONHYS

MCP6541T

SC70-5

6.3V 0201

CERM-X5R

10%

BMONHYS

0.1UF

BYPASS=U5671.5:2:3MM

BMONHYS

402

1%

255K

MF-LF

1/16W

0201

X5R

6.3V

20%

0.22UF

NOSTUFF

201

16K

1/20W MF

1%

MF 201

1/20W

1K

1%

NOSTUFF

0.22UF

0201

20%

6.3V X5R

5%

0201

1/20W

MF

0

5%

201

1/20W

MF

47

42 44 80

0201

6.3V

10% CERM-X5R

0.1UF

BYPASS=U5660.3:2:5MM

SC70

CKPLUS_WAIVE=NdifPr_badTerm

PLACE_NEAR=R5400:10MM

INA210

CRITICAL

65 80

SM

PLACE_NEAR=R7310.2:5 MM

NOSTUFF

0201

6.3V X5R

20%

0.22UF

PLACE_NEAR=U5000.B8:5MM

5%

0

0201

1/20W

MF

X5R

6.3V 0201

20%

0.22UF

PLACE_NEAR=U5000.B7:5MM

4.53K

1/20W

1%

201

MF

40

LOADRC:YES

PLACE_NEAR=U5000.B2:5MM

X5R

20%

0201

0.22UF

6.3V

PLACE_NEAR=U5000.B2:5MM

MF

1%

1/20W

4.53K

LOADRC:YES

201

BYPASS=U5630.3:2:5MM

0.1UF

402

LOADISNS

10V

20% CERM

INA211

SC70

LOADISNS

CAMERA_3V3:S0

MF-LF

1/16W

0

5%

402

CAMERA_3V3:S3

402

MF-LF

1/16W

0

5%

65 80 40

0.22UF

X5R 0201

20%

6.3V

PLACE_NEAR=U5000.A7:5MM

LOADRC:YES

201

MF

1/20W

1%

BMONHYS

69.8K

201

200K

MF

1/20W

1%

BMONHYS

1/20W

20K

5%

201

MF

NOSTUFF

PLACE_NEAR=U5640.6:5MM

5%

201

1/20W MF

51K

PLACE_NEAR=U5620.6:5MM

LOADISNS

NOSTUFF

PLACE_NEAR=U5610.6:5MM

5%

201

MF

1/20W

20K

201

MF

5%

15K

1/20W

PLACE_NEAR=U5660.6:5MM

MF 201

1/20W

5%

15K

NOSTUFF

PLACE_NEAR=U5670.6:5MM

BMONHYS

MF

201

1%

1/20W

10K

45 80

PLACE_NEAR=U5660.6:10MM

5%

0

0201

1/20W

MF

PLACE_NEAR=U5660.6:10MM

5% MF

0201

1/20W

0

NOSTUFF

42 44 80

45 80

0201

MF

5%

0

1/20W

PLACE_NEAR=U5660.6:10MM

MF

0

5%

0201

1/20W

NOSTUFF

42 44 80

MF

CRITICAL

PLACE_NEAR=U5640.5:10MM

PLACE_NEAR=U5640.4:10MM

0

1 W

0612-SHORT

OMIT

SM

TBTISNS

CERM

20% 10V

0.1UF

402

BYPASS=U5640.3:2:5MM

4.53K

1/20W

201

TBTRC:YES

1% MF

PLACE_NEAR=U5000.A8:5MM

0.22UF

0201

20%

6.3V X5R

TBTRC:YES

40

1%

1/20W

PLACE_NEAR=U5000.A7:5MM

4.53K

201

MF

LOADRC:YES

0.1UF

CERM

20% 10V

LOADISNS

BYPASS=U5620.3:2:5MM

402

INA211

LOADISNS

SC70

PLACE_NEAR=R5640.1:10 MM

SM

0201

1/20W

MF

5%

0

NOSTUFF

PLACE_NEAR=XW5640.2:10MM

TBTISNS

5%

0201

1/20W

MF

0

TBTISNS

SC70

INA210

40

DMN32D2LFB4

DFN1006H4-3

BMONHYS

54 80

CKPLUS_WAIVE=NdifPr_badTerm

BMONISNS

SC70

CRITICAL

INA213

0.1UF

BYPASS=U5670.3:2:3MM

BMONISNS

10%

CERM-X5R

0201

6.3V

NOSTUFF

RB521ZS-30

SM-201

0201

MF

0

5%

NOSTUFF

1/20W

117S0008

1

TBTRC:NO

RES,MTL FILM,100K,1/16W,0201,SMD,LF

C5649

117S0008

1

RES,MTL FILM,100K,1/16W,0201,SMD,LF

BMONRC:NO

C5679

2

117S0008

LOADRC:NO

RES,MTL FILM,100K,1/16W,0201,SMD,LF

C5619,C5629

BOM_COST_GROUP=SENSORS

Power Sensors: Extended

SYNC_MASTER=JACK_J52 SYNC_DATE=10/26/2013

=PP3V3_S0_SNS_BMON

=PP3V3_S4_ISNS

PP3V3_S3RS0_CAMERA_R

=PP3V3_S3RS0_CAMERA

PP3V3_S3RS0_CAMERA_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

=PP3V3_S3RS0_CAMERA

GND_SMC_AVSS

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.175MM

MIN_LINE_WIDTH=0.5MM

PP3V3_S3RS0_CAMERA

ISNS_CAMERA_IOUT

=PP3V3_S4_ISNS

ISNS_TBT_P

GND_SMC_AVSS

BMON_COMP_OUT

=PP3V3_S3_CAMERA_R

=PP3V3_S0_CAMERA_R

ISNS_LCDPANEL_P

ISNS_LCDPANEL_N

ISNS_TBT_IVIN

=PP3V3_S4_ISNS

ISNS_LCDPANEL_IOUT

ISNS_TBT_IOUT

SMC_TBT_ISENSE

CPUVR_IMON

CHGR_CSO_R_N

CHGR_CSO_R_P

CPUVSENSE_IN

BMON_IOUT_D

ISNS_TBT_IVOUT

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

=PP3V3_S0_CPUTHMSNS

ISNS_CPUHIGAIN_OUT

GND_SMC_AVSS

SMC_CPU_IMON_ISENSE

GND_SMC_AVSS

SMC_CPU_VSENSE

SMC_BMON_DISCRETE_ISENSE

GND_SMC_AVSS

BMON_IOUT

BMON_IOUT_R

SMC_BMON_COMP_ALERT_L

BMON_COMP_FB

ISNS_CPUHIGAIN_OUT_R

ISNS_HS_COMPUTING_P

ISNS_CPUHIGAIN_R_P

ISNS_HS_COMPUTING_N

ISNS_CPUHIGAIN_R_N

ISNS_CPUHIGAIN_N

ISNS_CPUHIGAIN_P

=PPVCC_S0_CPU

SMC_CAMERA_ISENSE

ISNS_TBT_N

=PP3V3_S4_TBT_ISNS

=PP3V3_S3RS0_CAMPWREN

BMON_COMP_VREF

=PP3V3_S4_TBT_ISNS_R

C5640

1

2

R5649

12

C5649

1

2

R5629

12

C5620

1

2

U5620

2

5

4

6

1

3

XW5640

12

R5648

12

R5647

12

U5640

2

5

4

6

1

3

U5672

3

1

2

U5670

2

5

4

6

1

3

C5670

1

2

D5677

A

K

R5677

1

2

C5679

1

2

R5679

12

R5672

1

2

C5672

1

2

U5671

3

4

1

5

2

C5671

1

2

R5673

12

C5673

12

R5661

1

2

R5662

1

2

C5665

1

2

R5665

12

R5660

12

C5660

1

2

U5660

2

5

4

6

1

3

XW5680

12

C5699

1

2

R5699

12

C5689

1

2

R5689

12

C5619

1

2

R5619

12

C5610

1

2

U5610

2

5

4

6

1

3

R5611

12

R5612

12

C5629

1

2

R5675

1

2

R5674

1

2

R5645

1

2

R5625

1

2

R5615

1

2

R5664

1

2

R5671

1

2

R5676

12

R5666

12

R5667

12

R5668

12

R5669

12

R5640

123

4

XW5610

1

2

dvt1

051-1573

8.0.0

56 OF 120

44 OF 82

68

42 43 44 68

44

33 44

44

33 44

38 39 40 42 43 44

42 43 44 68

80

38 39 40 42 43 44

68

42 43 44 68

55

43

45 68

38 39 40 42 43 44

80

8

10 68

80

68

15 18

68

BI

OUT

NC

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PAD

GND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

IN

OUT

THERM*/ADDR

ALERT*

GND

VDD

DN

DP

SMDATA SMCLK

THRM

PAD

BI

NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Place Q5872 between two rows of Memory devices,

Placement Note:

Thermal Diode: Airflow (TA0P)

By setting R5851 to 15k, I2C address

on the TOP side.

Place U5870 at corner near Fan,

Placement Note:

Thermal Sensor A: Thunderbolt Die, MLB Proximity

Thermal Diode: TBT Die (THSP)

Thermal Diode: MLB Proximity (TMLB)

Thermal Diode: Memory Proximity (TM0P)

Thermal Diode: CPU Proximity (TC0P)

Thermal Sensor: Fin Stack Proximity (Th1H)

Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector.

Placement Note:

for U5850 is 0xD8/0xD9.

U5850 I2C Address:

Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AA8.

Placement Note: Place Q5871, Airflow thermal indicator, above the SSD, on the BOTTOM side.

Placement Note: Place Q5873 under the CPU, on the BOTTOM side.

Note: Use GND pin AA8 on U2800 for N leg.

I2C Write: 0xD8, I2C Read: 0xD9

between channel A and B, on the BOTTOM side.

Placement Note: Place C5800 and C5801 near Q5871.

I2C Write: 0x98, I2C Read: 0x99

CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity

Thermal Sensor B & CPU High Peak Detection:

CRITICAL

BC846BLP

DFN1006H4-3

47

MF-LF

402

1/16W

5%

0.0022uF

CERM

402

10% 50V

PLACE_NEAR=U5870.4:5MM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5870.5:5MM

0.0022uF

CERM

402

10% 50V

PLACE_NEAR=U5870.2:5MM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5870.3:5MM

0.1uF

CERM 402

20% 10V

41

0.1uF

CERM 402

20% 10V

TBTTHRM_SNS

47

MF-LF

402

1/16W

5%

CRITICAL

BC846BLP

DFN1006H4-3

CRITICAL

BC846BLP

DFN1006H4-3

40

15K

1% MF

1/20W 201

TBTTHRM_THRM:PU TBTTHRM_ALRT:PU

100K

1% MF

1/20W 201

CPUTHRM_ALRT:PU

100K

1% MF

1/20W 201

100K

1%

CPUTHRM_THRM:PU

MF

1/20W 201

40

MF

1/20W 0201

0

5%

CRITICAL

EMC1704-2

QFN

44 80

NOSTUFF

10K

MF

1/20W 201

5%

NOSTUFF

10K

MF

1/20W 201

5%

40

EMC1412-A

TQFN

TBTTHRM_SNS

41

0.0022uF

CERM

402

10% 50V

PLACE_NEAR=U5850.3:5MM

PLACE_NEAR=U5850.2:5MM

NO_XNET_CONNECTION=TRUE

TBTTHRM_SNS

SM

PLACE_NEAR=U2800.AA8:2MM

25

0.0022UF

0603

10% CERM-X7R

50V

0603

50V CERM-X7R

0.0022UF

10%

BOM_COST_GROUP=SENSORS

Thermal Sensors

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/07/2013

CPUTHMSNS_D2_P

TBTTHMSNS_D1_P

MAKE_BASE=TRUE

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S0_TBTTHMSNS_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.2 mm

ISNS_CPUHIGAIN_N

ISNS_CPUHIGAIN_P

TBTTHMSNS_D1_N

=I2C_TBTTHMSNS_SCL

=I2C_TBTTHMSNS_SDA

TBTTHMSNS_THM_L

TBTTHMSNS_ALERT_L

=PP3V3_S0_TBTTHMSNS

CPUTHMSNS_ALERT_L

CPUTHMSNS_ADDR_SEL

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

=PP3V3_S0_CPUTHMSNS

CPUTHMSNS_TH_SEL

CPUTHMSNS_DUR_SEL

TP_TBT_THERM_DP

CPUTHMSNS_THM_L

CPUTHMSNS_D1_N

CPUTHMSNS_D2_N

CPUTHMSNS_D1_P

Q5871

1

3

2

R5870

12

C5872

1

2

C5871

1

2

C5870

1

2

C5850

1

2

R5850

12

Q5872

1

3

2

Q5873

1

3

2

R5851

1

2

R5852

1

2

R5872

1

2

R5871

1

2

R5875

1

2

U5870

6

103

5

2

4

13

8

7

15

16

12

11

14

9

17

1

R5874

1

2

R5873

1

2

U5850

6

3

2

5

8

7

4

9

1

C5851

1

2

XW5851

12

C5800

1

2

C5801

1

2

dvt1

051-1573

8.0.0

58 OF 120

45 OF 82

80

68

44 68

80

D

SYM_VER_3

SG

OUT

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Placement Note: Place C6002 and C6003 near Q6060

GND

MOTOR CONTROL

KEEP THE 5 PIN CONNECTOR FROM D1

TACH

FAN CONNECTOR

5V DC

518S0769

1/20W

5%

201

MF

47K

1/20W

5%

201

MF

47K

1/20W

5%

201

MF

100K

DFN1006H4-3

DMN32D2LFB4

38

F-RT-SM

CRITICAL

FF14A-5C-R11DL-B-3H

12PF

NP0-C0G

0201

5%

25V

NP0-C0G

0201

5%

12PF

0.0022UF

10% 50V

0603

CERM-X7R

0.0022UF

10% CERM-X7R

50V

0603

BOM_COST_GROUP=FAN

Fan

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

=PP3V3_S0_FAN

=PP5V_S0_FAN

=PP3V3_S0_FAN

SMC_FAN_0_CTL

FAN_RT_TACH

SMC_FAN_0_TACH

FAN_RT_PWM

R6065

12

R6060

1

2

R6061

1

2

Q6060

3

1

2

J6050

7

6

1 2 3 4 5

C6000

1

2

C6001

1

2

C6002

1

2

C6003

1

2

dvt1

051-1573

8.0.0

60 OF 120

46 OF 82

46 68

www.vinaﬁx.vn

BIBI

IN

OUT

BI

OUTOUT

VCC

D

B

AY

OE*

C

GND

BI

CS*

DI(IO0)

THRM_PAD

CLK

WP*(IO2) HOLD*(IO3)

DO(IO1)

VCC

GND

OUT

IN

OUT

IN

BIBI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

NOTE: If HOLD* is asserted ROM will ignore SPI cycles

IO0

IO1

SPI Frequency: 50MHz for CPU, 20MHz for SMC.

SPI+SWD SAM Connector

SPI ROM Slave

SMC12 Master

IO3

IO2

in normal and Dual-IO modes.

(SPI_IO<0>)

Quad-IO Mode (Mode 0 & 3) supported.

SPI ROM

(SPI_IO<1>)

CPU Master

Sam Card ROM Slave

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

(SWCLK)

(SWDIO)

SPI Bus Series Termination

0201

0

5% 1/20W MF

PLACE_NEAR=J6100.3:5MM

SAMCONN

47 75

1/20W

PLACE_NEAR=U6100.5:12MM

MF

201

22

5%

201

5%

1/20W

22

PLACE_NEAR=U0500.AA2:50MM

MF

14 75

SAMCONN

0

0201

MF

1/20W

5%

PLACE_NEAR=J6100.4:5MM

1/20W

SAMCONN

0

0201

MF

5%

PLACE_NEAR=J6100.6:5MM

38 75

201

1/20W

5% MF

PLACE_NEAR=U5000.K10:12MM

22

201

1/20W

MF

22

PLACE_NEAR=U5000.N9:12MM

5%

201

22

5%

1/20W

MF

PLACE_NEAR=U5000.L10:12MM

201

5%

1/20W

MF

22

PLACE_NEAR=U5000.M9:12MM

201

1/20W

22

5% MF

PLACE_NEAR=U0500.AA2:50MM

201

1/20W

MF

PLACE_NEAR=U6100.3:12MM

22

5%

1/20W

5%

22

PLACE_NEAR=U6100.7:12MM

201

MF

14 75

38 39 71

15 47 71

38 39 71

SAMCONN

CRITICAL

DF40PC-12DP-0.4V-51

M-ST-SM

38 39 40 54 71

SAMCONN

PLACE_NEAR=J6100.8:5MM

0

5% MF

1/20W 0201

PLACE_NEAR=J6100.10:5MM

SAMCONN

1/20W MF

0

0201

5%

0201

BYPASS=U6100::3mm

10% 16V

X5R-CERM

0.1UF

0201

16V

10%

BYPASS=U6101::3mm

0.1UF

X5R-CERM

74LVC1G99

CRITICAL

SOT833

PLACE_NEAR=U6100.1:12MM

47 75

OMIT_TABLE

WSON

64MBIT

W25Q64FVZPIG

CRITICAL

201

5%

1/20W

MF

22

PLACE_NEAR=U0500.Y6:50MM

201

5%

1/20W

22

MF

PLACE_NEAR=U0500.AF1:50MM

47 75

201

22

PLACE_NEAR=U0500.Y7:50MM

5%

1/20W

MF

14 75

47 75

201

5%

1/20W

22

PLACE_NEAR=U0500.AA3:50MM

MF

14 75

47 75

PLACE_NEAR=U6100.2:12MM

201

5% MF

1/20W

22

14 75

22

5%

1/20W

MF

PLACE_NEAR=U6100.1:12MM

201

SAMCONN

1/20W

PLACE_NEAR=J6100.5:5MM

0201

MF

0

5%

PLACE_NEAR=U6100.6:12MM

22

1/20W

MF

201

5%

BOM_COST_GROUP=CPU SUPPORT

SPI Debug Connector

SYNC_DATE=01/09/2013SYNC_MASTER=YHARTANTO_J44

SMC_TCK

SMC_TMS

SPI_ALT_IO2_WP_L

SMC_RESET_L

=PP3V3_G3H_T112

SPI_ALT_CLK SPI_ALT_CS_L SPIROM_USE_MLB

SPI_ALT_IO0_MOSI SPI_ALT_IO1_MISO

SPI_ALT_IO3_HOLD_L

SPI_IO2_R

SPI_MISO

SPI_CLK

SPI_CS0_L

SPI_MOSI

SPI_MLB_IO3_HOLD_L

SPI_MISO_R

SPI_MLB_CLK

SPI_SMC_CLK

SPI_SMC_CS_L

SPI_IO<3> SPI_IO3_R

SPI_SMC_MISO

SPI_IO<2>

SPI_MLB_IO1_MISO

SPI_MLB_IO0_MOSI

SPI_MLB_CS_L

SPI_CS0_R_L

SPI_MOSI_R

SPI_SMC_MOSI

SPI_ALT_IO1_MISO SPI_ALT_IO0_MOSI

SPI_MLB_IO2_WP_L

SPI_ALT_CLK

SPI_MLB_CS_L

SPI_CLK_R

SPIROM_USE_MLB

SPI_ALT_CS_L

SPI_MLB_IO1_MISO

SPI_MLB_IO0_MOSI

SPI_ALT_IO2_WP_L

SPI_MLB_IO3_HOLD_L

SPI_MLB_IO2_WP_L

SPI_MLBROM_CS_L

SPI_MLB_CLK

=PP3V3_SUS_ROM

R6110

12

R6111

12

R6123

12

R6120

12

R6125

1

2

R6121

12

R6126

1

2

R6122

12

R6112

12

R6127

1

2

R6128

1

2

R6117

12

R6115

12

R6116

12

R6114

12

R6113

12

R6130

12

R6131

12

J6100

1

10

1112

1314

15

16

2

34

56

78

9

R6132

1

2

R6133

1

2

C6100

1

2

C6101

1

2

U6101

2 3 5 6

4

1

8

7

U6100

6

1

5

2

479

8

3

R6118

12

R6119

12

dvt1

051-1573

8.0.0

61 OF 120

47 OF 82

47 75

68

47 75

75

47 75

15 47 71

47 75

68

ANALOG

SYM 1 OF 2

AGND

HPGND

HSGND

PLLGND

VA_PLL

VA

VA_REF

VA_HP

SENSE_A1 SENSE_A2

HPOUT_L HPOUT_R

HS3 HS4

HS4_REF

SENSE_B2

SENSE_B1

SENSE_D

SENSE_C

HS3_REF

HSIN+ HSIN-

LINEOUT1_L-

LINEOUT1_L+

LINEOUT1_R+ LINEOUT1_R-

LINEOUT2_L-

LINEOUT2_L+

LINEOUT2_R-

LINEOUT2_R+

LINEOUT3_R+

LINEOUT3_L+

LINEOUT3_R-

LINEOUT4_L+ LINEOUT4_L-

LINEOUT4_R+ LINEOUT4_R-

LINEOUT3_L-

VREF_ADC

VCOM

FLYN

FLYP

VHP_FILT-

VREF_DAC

LINEIN_L+

LINEIN_R-

LINEIN_R+

LINEIN_L-

MICBIAS2_R

MICBIAS2_L

MICBIAS1_R

MICBIAS1_L

MICIN1_L+

MICIN2_L-

MICIN1_L-

MICIN1_R+

MICIN2_L+

MICIN2_R+ MICIN2_R-

HSBIAS_IN HSBIAS HSBIAS_REF HSBIAS_FILT

MICIN1_R-

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

PLACE XW6201 NEAR 5V SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SUBWOOFER AMP. SIG. SOURCE

AUDIO CODEC, ANALOG BLOCKS

APPLE P/N 353S4080

APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC

VFBGA

CS4208-CRZR

10V

0.1UF

20%

0402

X7R-CERM

0.1UF

BYPASS=U6201.A1:A2:5 MM

0402

10% 16V

X7R-CERM

BYPASS=U6201.N13:M11:5 mm

10%

0402

X7R-CERM

0.1UF

16V

BYPASS=U6201.H12:H13:5 mm

16V

20%

TANT-POLY

10UF

CRITICAL

0805-LLP-1

CRITICAL

15UF

X5R

0402

20%

4V

50 80

25V

1UF-10OHM

TANT

0603-LLP

20%

CRITICAL

20%

10UF

CRITICAL

TANT-POLY

16V 0805-LLP-1

BYPASS=U6201.A8:B10:5 mm

CRITICAL

15UF

X5R

0402

20%

4V

4.7UF

X5R-CERM 0402

20% 10V

402

25V

10%

1UF

X5R

2.21K

MF

201

1%

1/20W

40225V

X5R

10%

1UF

402

25V X5R

10%

SM

201

2.2K

5% MF

1/20W

NO STUFF

0201

FERR-22-OHM-1A-0.055OHM

10% 10V

1UF

X5R 402

SON

TPS71745

CRITICAL

SM

CRITICAL

1.0UF

X5R-CERM 0201-1

20% 10V

10%

0402

X7R-CERM

0.1UF

16V

BYPASS=U6201.H12:L10:5 mm

52

52 80

51 80

10UF

0805-LLP-1

TANT-POLY

20% 16V

52

0.01UF

25V

CRITICAL

X5R-CERM

0201

10%

16V

0402

X7R-CERM

0.1UF

10%

10UF

20%

CRITICAL

X5R-CERM 0402-1

10V

CRITICAL

120-OHM-25%-1.3A

0402

0.1UF

X5R-CERM 0201

10%

16V

22K

402

5% 1/16W MF-LF

BOM_COST_GROUP=AUDIO

SYNC_DATE=05/13/2013

SYNC_MASTER=JCURCIO_J44

Audio: Codec,Analog

PP5V_S3_AUDIO_XW

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.60MM VOLTAGE=5V

AUD_TIPDET_2

AUD_TIPDET_1

AUD_TYPEDET

NC_AUD_LO1_LN

NC_AUD_LO1_RN

AUD_LO2_L_P

=PP3V3_S0_AUDIO_DIG

=PP5V_S3_AUDIO

4V5_NR

GND_AUDIO_CODEC

NC_AUD_LO4_RN

NC_AUD_LO4_RP

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

TP_AUD_CODEC_MICBIAS1_L

TP_AUD_CODEC_MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

AUD_HSBIAS_REF

AUD_HSBIAS

TP_AUD_CODEC_MICBIAS2_R

AUD_LO2_R_P

CODEC_VREF_ADC

CODEC_MICIN2

GND_AUDIO_CODEC

AUD_LO3_L_N

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_LO3_L_P

NC_AUD_LO4_LN

NC_AUD_LO1_LP

AUD_LO2_R_N

NC_AUD_LO4_LP

AUD_LO2_L_N

AUD_LO3_R_P AUD_LO3_R_N

GND_AUDIO_CODEC

CODEC_VCOM

AUD_HSBIAS_FILT

AUD_HSBIAS_IN

GND_AUDIO_CODEC

NC_AUD_LO1_RP

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.07MM

CODEC_FLYP

MIN_LINE_WIDTH=0.20MM

4V5_REG_IN

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.15MM

VHP_FILTN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFCH

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.20MM

CODEC_FLYN

HS_MIC_P

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.3MM

VREF_DAC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

HS_MIC_N

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

CODEC_HS_MIC_N

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

CODEC_HS_MIC_P

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.5MM

MAX_LINE_WIDTH=0.5MM

AUD_CH_HS_GND

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.5MM

AUD_US_HS_GND

MAX_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFUS

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_R

PP3V3_S0_AUDIO_ANALOG

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.1 mm

PM_SLP_S3_BUF_L

4V5_REG_EN

U6201

M11

L6

L9

L10

B10 B11

A8

A10C8C10

A12 A13

C13

B13

C12

B12

L13

N11

L12

M13

D13

M6

N6

M10

N10

M9

N9

E13

E12

F12

F11

G11

F13

G13

G12

J11

H11

J13

J12

K12

K11

L11

K13

L8 L7

L5 L4

M8

N8

M7

N7

M5

N5

M4

N4

A2

C11 D12

E11 D11 M3 L3

N13A9A1

H12

M12

A11

N12

H13

C6218

1

2

C6217

1

2

C6212

1

2

C6216

1

2

C6215

1

2

C6219

12

C6210

1

2

C6211

1

2

C6222

1

2

C6221

1

2

C6220

12

R6206

12

C6224

12

C6225

12

XW6201

12

R6200

12

L6200

12

C6201

1

2

U6200

4

2

6

3

1

XW6200

12

C6203

1

2

C6202

1

2

C6214

1

2

C6213

1

2

L6201

12

C6226

12

R6207

12

C6200

1

2

dvt1

051-1573

8.0.0

62 OF 120

48 OF 82

5

71

49 52 68

68

48 52

71

48

48 52

69

48 52

68

48 52

71

48 52

71

48 52

48

80

64

DIGITAL

SYM 2 OF 2

VD

VL_HD

VL_IF

VL_SP

VL_DM

NC

DMIC_SCL3

DMIC_SDA3

DMIC_SCL2

DMIC_SDA2

DMIC_SCL1

DMIC_SDA1

DMIC_SCL0

DMIC_SDA0

SPDIF_OUT

SPDIF_IN

SCL

SDA

SDIN_B

SDOUT_B

LRCK_B

SCLK_B

MCLK_B

RST*

SDO3

SDO2

SDO1

SDO0

GPIO0 GPIO1

GPIO5

GPIO4

GPIO3

GPO0

SYNC

BCLK

SDI0

GPO1

SDI1

SCLK_A

MCLK_A

LRCK_A SDOUT_A SDIN_A

GPIO2

DGND

LGND

OUT

IN

OUT

IN

OUT

IN

OUT

PP

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AUDIO CODEC, DIGITAL BLOCKS

APPLE P/N 353S4080

CS4208-CRZR

VFBGA

402

SHORT

OMIT

201

100K

MF

5%

1/20W

5% MF

100K

201

51

FERR-22-OHM-1A-0.055OHM

0201

12 75

12 71 75

12 75

5% MF

22

1/20W

201

10V

20%

0402-1

X5R-CERM

10UF

BYPASS=U6201.E1:F1:5 mm

16V 0402

X7R-CERM

0.1UF

10%

10V

20%

0402-1

X5R-CERM

10UF

BYPASS=U6201.A7:E3:5 mm

CERM-X5R 0201

6.3V

0.1UF

10%

BYPASS=U6201.G1:F1:5 mm

CERM-X5R 0201

6.3V

0.1UF

10%

402

X5R-1

4V

20%

4.7UF

BYPASS=U6201.K1:K3:5 mm

CERM-X5R 0201

6.3V

0.1UF

10%

12 49 75

1/16W

5%

402

MF-LF

33

52

1/16W

1%

402

MF-LF

75

52 71

49 52 71

16V 0402

10%

0.1UF

X7R-CERM

BYPASS=U6201.J2:J1:5 mm

50

1/20W

5% MF

100K

201

NOSTUFF

1/20W

5% MF

100K

201

PLACE_NEAR=U6201.N3:5 mm

SM

P3MM

PLACE_NEAR=U6201.D2:5 mm

SM

P3MM

51

52 71

BOM_COST_GROUP=AUDIO

SYNC_MASTER=JCURCIO_J44

SYNC_DATE=07/25/2013

Audio: Codec,Digital

=PP1V5_S0_AUDIO

DMIC_SDA3

NC_CS4208_SCLKB

NC_DMIC_CLK1

NC_CS4208_MCLKB

NC_CS4208_SDOUTA

HDA_SDOUT

NC_CS4208_SCLKA NC_CS4208_LRCLKA

NC_CS4208_LRCLKB NC_CS4208_SDOUTB

GPIO0_SPKR_SHUTDOWN

DMIC_CLK3

CS4208_SPDIF_IN

CS4208_HDA_SDOUT0_R

TP_CS4208_HDA_SDOUT1

HDA_SDOUT

SPDIF_OUT_JACK

HDA_RST_L

=PP3V3_S0_AUDIO_DIG

DMIC_SDA3

NC_DMIC_CLK0

SPKRCONN_L_ID

NC_CS4208_GPO1

HDA_SYNC

SPKRCONN_R_ID

DFET_OPENUS

NC_CS4208_GPO0

=PP3V3_S0_AUDIO_DIG

NC_CS4208_MCLKA

HDA_BIT_CLK

HDA_SDIN0

PD_CS4208_GPIO1

DFET_OPENCH

CS4208_SPDIF_OUT

NC_DMIC_CLK2

DMIC_CLK3_R

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.07MM

PP1V5_S0_AUDIO_DIG

VOLTAGE=1.5V

U6201

F2

J1

N2

M1

L1

L2

N3

N1

M2

K2

H3 H2 H1 C4 C5 C7

C9 B9

F1E3F3J3K3

B4

B5

A5

A6

F6 F7 F8 G6 G7 G8 H6 H7 H8

D3

B7

B2

B6

C6

D1 C1

B3

A4

D2 C2 C3 B1

A3

B8

G3 G2

E2

J2K1E1G1A7

L6300

12

C6300

1

2

C6301

1

2

R6331

12

C6305

1

2

C6302

1

2

C6306

1

2

C6307

1

2

C6303

1

2

C6304

1

2

R6330

12

R6332

12

R6324

1

2

R6322

12

PP6301

1

PP6304

1

R6302

12

R6323

12

R6325

1

2

dvt1

051-1573

8.0.0

63 OF 120

49 OF 82

68

49 52 71

71

75

12 49 75

48 49 52 68

71

48 49 52 68

71

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

NC

IN

OUT

IN

OUT

IN

OUT

IN-

IN+

OUT+ OUT-

GAINSHDN*

PVDD

NC

PGND

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Placement Note: Place C6451 near U6440Placement Note: Place C6450 near U6410

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

1ST ORDER FC (L&R) = NOM 569 HZ

GAIN = +3 DB

1ST ORDER FC (SUB) = NOM 9 HZ

Placement Note: Place C6448 and C6449 near U6430Placement Note: Place C6447 and C6452 near U6420

0402

CRITICAL

FERR-1000-OHM

CRITICAL

0.22UF

CERM

402

10% 16V

10%

402

16V

CRITICAL

0.22UF

CERM

402

16V

10%

CERM

0.22UF

CRITICAL

CERM

402

10% 16V

CRITICAL

0.22UF

WLCSP

SSM2375

CRITICAL

52 71 80

0201

0.1UF

16V

10% X5R-CERM

BYPASS=U6430.C2:C1:5 mm

WLCSP

SSM2375

CRITICAL

52 71 80

TANT-POLY

CASE-A4

20%

6.3V

47UF

CRITICAL

TANT

CRITICAL

100UF

CASE-AL1

6.3V

20%

CASE-AL1

CRITICAL

100UF

TANT

20%

6.3V

50V 0402

10%

4700PF

X7R-CERM

X7R-CERM 0402

50V

4700PF

10%

16V

10% X5R-CERM

0201

0.1UF

BYPASS=U6440.C2:C1:5 mm

10% 16V

0201

X5R-CERM

0.1UF

BYPASS=U6410.A1:A2:5 mm

0.0022UF

0603

10% 50V CERM-X7R

50V CERM-X7R

0.0022UF

10%

0603 0603

CERM-X7R

0.0022UF

10% 50V 50V

CERM-X7R

0.0022UF

10%

06030603

50V CERM-X7R

0.0022UF

10% 50V CERM-X7R

0.0022UF

10%

0603

1/16W

100K

MF-LF

402

5%

0402

CRITICAL

FERR-1000-OHM

48 80

49

0402

CRITICAL

FERR-1000-OHM

52 71 80

16V

10%

0201

X5R-CERM

BYPASS=U6420.A1:A2:5 mm

0.1UF

CRITICAL

FERR-1000-OHM

0402

48 80

52 71 80

47UF

TANT-POLY

CASE-A4

20%

6.3V

CRITICAL

0402

CRITICAL

FERR-1000-OHM

48 80

0402

FERR-1000-OHM

CRITICAL

48 80

0402

50V

10%

CRITICAL

0.01UF

X7R-CERM

CRITICAL

0402

0.01UF

50V

10%

X7R-CERM

50V

10%

0402

0.01UF

X7R-CERM

CRITICAL

0.01UF

X7R-CERM

0402

50V

10%

CRITICAL

52 71 80

MAX98300

WLP

CRITICAL

MF-LF

402

1/16W

5%

100K

MAX98300

WLP

CRITICAL

402

100K

MF-LF

1/16W

5%

48 80

FERR-1000-OHM

0402

CRITICAL

0402

FERR-1000-OHM

CRITICAL

48 80

FERR-1000-OHM

0402

CRITICAL

48 80

BOM_COST_GROUP=AUDIO

SYNC_MASTER=DIRK_J44

Audio: Speaker Amps

SYNC_DATE=01/09/2013

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_N

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_L_OUT_N

NO_TEST=TRUE

SPKRAMP_LIN_P

NO_TEST=TRUE

SPKRAMP_LIN_N

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

NO_TEST=TRUE

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

SPKRAMP_RIN_P

NO_TEST=TRUE

SPKRAMP_RIN_N

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_P

MAX_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_SL_OUT_P

SPKRCONN_SL_OUT_N

MAX_LINE_WIDTH=0.40 MM

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_N

MIN_NECK_WIDTH=0.10 MM

MAX_LINE_WIDTH=0.40 MM

MIN_LINE_WIDTH=0.40 MM

NO_TEST=TRUE

AUD_SPKRAMP_RIN_N

AUD_SPKRAMP_RIN_P

NO_TEST=TRUE

RSUBIN_N

NO_TEST=TRUE

RSUBIN_P

NO_TEST=TRUE

LSUBIN_N

NO_TEST=TRUE

LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_N

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

NO_TEST=TRUE

AUD_LO3_R_N

AUD_LO3_L_N

AUD_LO3_L_P

AUD_LO3_R_P

SPKR_SHUTDOWN

LSUB_GAIN

PP5V_S0_AUDIO_AMP_L

RSUB_GAIN

AUD_LO2_R_N

AUD_LO2_R_P

PP5V_S0_AUDIO_AMP_R

SPKR_SHUTDOWN

SPKR_R_GAIN

PP5V_S0_AUDIO_AMP_R

AUD_LO2_L_N

AUD_LO2_L_P

GPIO0_SPKR_SHUTDOWN

SPKR_SHUTDOWN

SPKR_L_GAIN

PP5V_S0_AUDIO_AMP_L

R6400

1

2

L6401

12

L6411

12

C6421

1

2

L6421

12

C6412

1

2

L6410

12

L6420

12

C6423

12

C6424

12

C6414

12

C6413

12

U6410

C3

B3

A3

C1

B1

A2

A1

C2

R6410

1

2

U6420

C3

B3

A3

C1

B1

A2

A1

C2

R6420

1

2

L6441

12

L6440

12

L6431

12

L6430

12

C6443

12

C6444

12

C6434

12

C6433

12

U6430

B2

A3

C1

A1

B1

B3

C3

A2

C2

C6431

1

2

U6440

B2

A3

C1

A1

B1

B3

C3

A2

C2

C6422

1

2

C6432

1

2

C6442

1

2

C6436

1

2

C6446

1

2

C6441

1

2

C6411

1

2

C6447

1

2

C6448

1

2

C6449

1

2

C6451

1

2

C6450

1

2

C6452

1

2

dvt1

051-1573

8.0.0

64 OF 120

50 OF 82

B2

80

80 50

50

50 69

50

50 69

50

50 69

OUT

IN

OUT

IN

PSEL

CP

GND

OUT2

OUT1

VDD

PSEL

CP

GND

OUT2

OUT1

VDD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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NOTICE OF PROPRIETARY PROPERTY:

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D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR # 6210118)

48 80

100K

5% MF

201

1/20W

5%

402

2.2K

MF-LF

1/16W

27PF

CRITICAL

25V

5% C0G

0201

5%

2.2K

1/16W MF-LF

402

52 80

5%

1000PF

NP0-C0G

25V 0402

49

51 52 80

49

0402

25V NP0-C0G

1000PF

5%

MF-LF

1/16W

10K

402

5%

X5R-CERM 0201

16V

10%

0.1UF

BYPASS=U6501.B2:B1:3MM

CERM-X5R 0402

35V

10%

1.0UF

0201

CRITICAL

3300PF

X7R-CERM

10% 10V

10V

10%

0201

X5R-CERM

0.01UF

BYPASS=U6501.B2:B1:3MM

WCSP

TAIC3027A0YFFR

WCSP

5%

402

10K

1/16W MF-LF

0.01UF

X5R-CERM 0201

10% 10V

BYPASS=U6500.B2:B1:3MM

0.1UF

10% 16V

0201

X5R-CERM

BYPASS=U6500.B2:B1:3MM

1.0UF

10% 35V

0402

CERM-X5R

Audio: Jack Support

BOM_COST_GROUP=AUDIO

SYNC_DATE=07/25/2013

SYNC_MASTER=JCURCIO_J44

DFET_CPO1

AUD_CONN_SLEEVE_XW

HS_MIC_P

HS_MIC_N

DFET_CPO2

AUD_CONN_RING2_XW

DFET_OPENUS

DFET_OPENCH

AUD_HS_MIC_N

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.06MM

AUD_HS_MIC_P

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.06MM

R6556

1

2

R6550

12

C6558

1

2

R6559

12

C6501

1

2

C6502

1

2

R6520

1

2

C6542

1

2

C6530

1

2

C6550

1

2

C6543

1

2

U6500

C1

B1

A1 A2

C2

B2

U6501

C1

B1

A1 A2

C2

B2

R6521

1

2

C6563

1

2

C6562

1

2

C6560

1

2

dvt1

051-1573

8.0.0

65 OF 120

51 OF 82

IN

OUT

IN

OUT

IN

OUT

IN

GND

VDD

AUDIO GND

SHELL

VIN

MIC

DET2 DET1 1RTN

2RTN

R.AUDIO

AUDIO GND

PINS

POF

OPERATING VOLTAGE 3.3

AUDIO

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APN: 514-0875

CODEC GPIO0

HIGH = DFETs OPEN

GPIO4

GPIO3

SPDIF OUT 0X0E (14) 0X21 (33) N/A

OUTPUT

CODEC OUTPUT SIGNAL PATHS

N/A

CODEC INPUT SIGNAL PATHS

0X09 (9)

HIGH = FG, LOW = MERRY

GPIO2

RIGHT SPEAKER ID

SPEAKER CONNECTOR

2-MIC CONNECTOR

0X1C (28)

APN: 518S0672

HP=80HZ

APN: 518S0818

3.3V

VREF

0X18 (24)

0X1C (28)

PIN COMPLEX

CONVERTER 0X09 (9)

0X07 (7)

LEFT SPEAKER ID

DFET CONTROL

HEADSET MIC

DMIC 2

DMIC 1

FUNCTION

CODEC GPIO0

N/A

MUTE CONTROL

0X13 (19)

0X12 (18)

0X10 (16)

PIN COMPLEX

0X04 (4)

0X02 (2)

CONVERTERVOLUME 0X02 (2) 0X03 (3) 0X04 (4)

SUB

TWEETERS

HP/HS OUT

INPUT

OTHER CODEC GPIO LINES

FUNCTION

2.7V

HIGH = FG, LOW = MERRY

0X03 (3)

M-RT-SM

78171-6006

CRITICAL

M-RT-SM

78171-6006

CRITICAL

50 71 80

49 71

50 71 80

49 71

50 71 80

49 71

CRITICAL

FF14A-6C-R11DL-B-3H

F-RT-SM

OMIT

SHORT

402

48

51 80

48

48 80

48

0201

FERR-470-OHM

CRITICAL

120-OHM-25%-1.3A

CRITICAL

0402

CRITICAL

0201

FERR-470-OHM

0402

CRITICAL

120-OHM-25%-1.3A

48 80

0201

CRITICAL

FERR-470-OHM

402

X5R

10V

10%

1UF

0.1UF

0201

CERM-X5R

6.3V

10%

5% MF-LF

1/16W

10K

402

SM

PLACE_NEAR=J6600.5:5mm

PLACE_NEAR=J6600.6:5mm

SM

CRITICAL

SOD882

ESDALC5-1BM2

CRITICAL

ESDALC5-1BM2

SOD882

CRITICAL

ESDALC5-1BM2 ESDALC5-1BM2

CRITICAL

SOD882

CRITICAL

SOD882

ESDALC5-1BM2

CRITICAL

SOD882

ESDALC5-1BM2

CRITICAL

ESDALC5-1BM2

SOD882

49

F-RT-TH

AUDIO-SPDIF-J44

25V

5%

100PF

0201

C0G

5%

0201

25V

100PF

0201

5%

100PF

C0G

25V

0201

5%

100PF

C0G

25V

100PF

C0G

25V

5%

0201

100PF

0201

C0G

5% 25V

5%

100PF

0201

C0G

25V

120-OHM-25%-1.3A

CRITICAL

0402

CRITICAL

120-OHM-25%-1.3A

0402

120-OHM-25%-1.3A

CRITICAL

0402

CRITICAL

120-OHM-25%-1.3A

5%

2.2K

402

MF-LF

1/16W

5%

2.2K

402

1/16W MF-LF

SYNC_DATE=05/13/2013

BOM_COST_GROUP=AUDIO

Audio: Jack Translators

SYNC_MASTER=JCURCIO_J44

AUD_CONN_TIPDET_2

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.1MM

AUD_CONN_RING2_XW

SPKRCONN_SR_OUT_N

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.4MM

AUD_CONN_SLEEVE

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.3MM

AUD_CONN_HP_LEFT

MIN_NECK_WIDTH=0.06MM

AUD_CONN_RING2

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_L

AUD_TIPDET_2

AUD_HP_PORT_REFUS

AUD_HP_PORT_R

AUD_TYPEDET

GND_AUDIO_CODEC

AUD_HP_PORT_REFCH

AUD_US_HS_GND

AUD_CH_HS_GND

DMIC_SDA2

DMIC_CLK3

DMIC_SDA3

=PP3V3_S0_AUDIO_DIG

SPKRCONN_SL_OUT_P

AUD_HS_MIC_P

SPKRCONN_L_OUT_N

SPKRCONN_R_OUT_N

SPKRCONN_R_ID

SPKRCONN_L_OUT_P

SPKRCONN_L_ID

AUD_TIPDET_1

SPKRCONN_SL_OUT_N

SPKRCONN_R_OUT_P

AUD_HS_MIC_N

SPKRCONN_SR_OUT_P

MIN_NECK_WIDTH=0.06MM

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.3MM

=PP3V3_S0_AUDIO_DIG

AUD_CONN_SLEEVE_XW

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.1MM

AUD_CONN_TIPDET_1

AUD_CONN_TYPEDET

SPDIF_OUT_JACK

J6602

7

8

1 2 3 4 5 6

J6603

7

8

1 2 3 4 5 6

J6601

1 2 3 4 5 6

7

8

R6680

12

L6606

12

L6605

12

L6607

12

L6604

12

L6608

12

C6600

1

2

C6601

1

2

R6601

1

2

XW6600

12

XW6602

12

XW6601

12

XW6603

12

DZ6601

1

2

DZ6602

1

2

DZ6603

1

2

DZ6606

1

2

DZ6605

1

2

DZ6604

1

2

DZ6607

1

2

J6600

1

10 11

12 13 14 15

2

3 4

5 6

7

8

9

C6608

1

2

C6607

1

2

C6606

1

2

C6605

1

2

C6604

1

2

C6603

1

2

C6602

1

2

L6611

12

L6612

12

L6613

12

L6614

12

R6602

1

2

R6603

1

2

dvt1

051-1573

8.0.0

66 OF 120

52 OF 82

51 80

80

71

48 49 52 68

51 80

VCC

EXT INT

NC GND

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

BI

NC

G

D

S

G

S

D

Y

B

A

IN

G

D

S

NC

BI

GND

SMBUSSDA

SMBUSSCL

PWR

SYSDETL

GND GND

PWR

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518-0394

MagSafe DC Power Jack

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

<Ra>

connected.

1-Wire OverVoltage Protection

send transients onto ADAPTER_SENSE when AC is

conduct and power charger and 3.42V reg

The chassis ground will otherwise float and can

518S0508

Input impedance of 68K meets

for both MPM4 and MPM5.

6.8V Zener

sparkitecture requirements

When input voltage is 2V the FET will be off blocking the leakage path and 22.1K can be properly detected.

When input voltage is at 16V+, FET will

(Switcher limit)

300MA MAX OUTPUT

Vout = 3.425V

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

CRITICAL

6AMP-32V-0.0095OHM

0603

0.1UF

NO STUFF

X7R 603-1

10% 50V

CRITICAL

MAX9940

SC70-5

DFN

LT3470AED

CRITICAL

0201

C0G

5% 50V

22PF

200K

1% MF

1/20W

201

6.3V X5R 0603

CRITICAL

22UF

20%

348K

1% MF

1/20W

201

1/8W

10

MF-LF

805

5%

47

805

1%

1/3W

MF

CRITICAL

SBR0330CW

SOT-323

2520

CRITICAL

10UH-20%-0.85A-0.46OHM

402

0.22UF

CERM

10% 10V

25V

4.7UF

0603

10%

X6S-CERM

38

402

2.0K

MF-LF

1/16W

5%

SI5419DU

POWERPAK

100K

MF

1/20W 201

5%

GDZ-0201

GDZT2R6.8

68K

1% MF

1/20W 201

25V

4.7UF

X6S-CERM

0603

10%

25V

4.7UF

X6S-CERM

0603

10%

10K

MF

1%

201

1/20W

25V

0.047UF

10%

0402

X7R

BLEEDER

2N7002

SOT23-HF1

MF-LF 402

BLEEDER

1K

1/16W

5%

603-1

0.1UF BLEEDER

X7R

10% 50V

BLEEDER

CRITICAL

SBR0330CW

SOT-323

MF-LF 402

BLEEDER

10K

1/16W

5%

402

0.1UF

CERM

20% 10V

CRITICAL

TC7SZ08FEAPE

SOT665

402

PLACE_NEAR=U7001.5:1MM

0.1UF

CERM

20% 10V

38 39

BLEEDER

SOT23

AO3407A

1000PF

25V

0402

CERM

NO STUFF

5%

49.9K

1%

NO STUFF

MF

1/20W 201

MF

1/20W 0201

0

5%

402

25V

0.1UF

X5R

10%

25V

1UF

X5R

603-1

10%

CRITICAL

RCLAMP2402B

SC-75

402

10K

MF-LF

1/16W

5%

41

WTB-PWR-M82

M-RT-SM

CRITICAL

BAT-J44

CRITICAL

F-ST-TH

0201

12PF

5%

NP0-C0G

25V

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/09/2013

DC-In & Battery Connectors

BOM_COST_GROUP=POWER

=PP3V42_G3H_REG

PPVIN_G3H_P3V42G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=18.5V

=PP18V5_DCIN_ISOL

P3V42G3H_SHDN_L

ADAPTER_SENSE

TP_TDM_ONEWIRE_MPM

PPVBAT_G3H_CONN

DCIN_ISOL_GATE

=PP3V42_G3H_ONEWIREPROT

SMC_BC_ACOK

=PPBUS_G3H

SYS_ONEWIRE

=SMBUS_BATT_SDA

SYS_DETECT_L

=SMBUS_BATT_SCL

=PP18V5_DCIN_CONN

DCIN_ISOL_GATE_R

P3V42G3H_FB

SMC_BC_ACOK_VCC

P3V42G3H_BOOST

NO_TEST=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPBUS_G3H_R

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE DIDT=TRUE

P3V42G3H_SW

MIN_NECK_WIDTH=0.25 mm

DCIN_ISOL_BLEEDER_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM

DCIN_ISOL_BLEEDER_NGATE

MIN_NECK_WIDTH=0.25 mm

PP18V5_DCIN_CONN_R

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM

DCIN_ISOL_BLEEDER_PSRC

F7005

12

C7005

1

2

U7000

5

2

4

1

U7090

2

3

1

5

84

9

6

C7095

1

2

R7096

1

2

C7099

1

2

R7095

1

2

R7005

12

R7020

12

D7005

1

2

3

L7095

12

C7094

1

2

C7090

1

2

R7029

1

2

Q7010

1

4

5

5A

R7010

1

2

D7010

A

K

R7012

1

2

C7091

1

2

C7092

1

2

R7011

12

C7012

1

2

Q7030

3

1

2

R7030

1

2

C7020

1

2

D7020

1

2

3

R7021

1

2

C7000

1

2

U7001

2

1

3

5

4

C7008

1

2

Q7020

3

1

2

C7080

1

2

R7081

1

2

R7080

1

2

C7050

1

2

C7060

1

2

D7050

3

1

2

R7050

1

2

J7000

1 2 3 4 5 6

J7050

1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 9 18

C7010

1

2

dvt1

051-1573

8.0.0

70 OF 120

53 OF 82

3

7

68

71

69

54 71

68

54 68

71

68

71

IN

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

IN

BI

IN

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

G

D

SYM-VER-2

S

G

S

D

S

D

NCNCNC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

36V/V

Float CELL for 1S

Vout = 1.25V * (1 + Ra / Rb)

(PPVBAT_G3H_CHGR_R)

(CHGR_CSO_N)

(CHGR_CSO_P)

For Erp Lot6 spec

sparkitecture requirements

(P5V1_BIAS)

(AGND)

(GND)

<Rb>

<Ra>

20V/V

(OD)

353S2929

Vout = 5.50V

(Switcher limit)

250MA MAX OUTPUT

(CHGR_AGATE)

Divider sets ACIN threshold at 13.55V

TO/FROM BATTERY

Inrush Limiter

FROM ADAPTER

(CHGR_DCIN)

(CHGR_BGATE)

Reverse-Current Protection

30mA max load

Input impedance of ~90K meets

ACIN pin threshold is 3.2V, +/- 50mV

TO SYSTEM

(CHGR_SGATE)

f = 400 kHz

(L7130 limit)

Max Current = 8.5A

(PPVBAT_G3H_CHGR_R)

10V

10%

0402

X5R-CERM

0.068UF

38 39

40

47

71

25V

20% POLY-TANT

22UF

CRITICAL

CASE-D2-SM

25V

10%

0603

X6S-CERM

4.7UF

DFN

LT3470A

CRITICAL

50V

5%

0201

C0G

22PF

DP418C-SM

33UH-20%-0.39A-0.435OHM

CRITICAL

402

10V

10% X5R

1UF

10V

10%

402

CERM

0.22UF

1/20W

1%

201

MF

200K

1/20W

1%

201

MF

681K

25V

20%

0603

X5R-CERM

10UF

CRITICAL

25V

20%

0603

X5R-CERM

10UF

CRITICAL

1/16W

5% 402

MF-LF

0

1/16W

5% 402

MF-LF

0

NOSTUFF

CRITICAL

PIME103T-4R7MS

4.7UH-20%-8.5A-18.3MOHM

1/16W

5% 402

MF-LF

0

16V

10%

0402

X7R-CERM

0.01UF

25V

10%

0603

X6S-CERM

4.7UF

NOSTUFF

DFN

CRITICAL

NTMFD4902NF

25V NP0-C0G 0201

5%

12PF

25V NP0-C0G

12PF

5%

0201

NP0-C0G

5%

0201

25V

12PF

10V

10%

402

X5R

1UF

SM

PLACE_NEAR=U7100.29:1MM

PLACE_NEAR=U7100.22:1MM

50V

10%

0603-1

X5R-CERM

0.22UF

16V

10%

402

X5R

1UF

64

41

50V

10%

0402

CERM

470PF

1/16W

5%

402

MF-LF

0

402

NO STUFF

1/16W

5% MF-LF

100K

MF-LF

4.7

5%

402

1/16W

402

1/16W

5%

MF-LF

20

1UF

10V

10%

402

X5R

SBR0330CW

CRITICAL

SOT-323

25V

10%

402

X5R

0.1UF

1/16W

1%

402

MF-LF

470K

1/16W

1%

402

MF-LF

332K

39

42

50V

10%

0402

X7R-CERM

0.001UF

402

MF-LF

5%

2.2

1/16W

5%

0

402

MF-LF

1/16W

1%

402

MF-LF

21.5K

CERM

10%

402

10V

0.22UF

PLACE_NEAR=U7100.23:2MM

NO_XNET_CONNECTION=TRUE

25V

10%

402

X5R

0.1UF

0402

X5R-CERM

10V

10%

0.047UF

25V

10%

402

X5R

0.1UF

NO_XNET_CONNECTION=TRUE

402

1/16W

5%

MF-LF

10

1/16W

402

MF-LF

10

5%

25V

1UF

X5R 402

10%

25V

10%

402

X5R

0.1UF

0402

50V

10%

X7R-CERM

0.01UF

68UF

16V POLY-TANT

20%

CASE-D2E-SM

CRITICAL

25V

20%

CASE-D2-SM

POLY-TANT

22UF

CRITICAL CRITICAL

POLY-TANT

25V

20%

CASE-D2-SM

22UF

1/16W

1%

402

MF-LF

3.01K

1.0UF

0603

50V X5R

10%

0402

X7R-CERM

50V

10%

0.001UF

1206

12AMP-32V

CRITICAL

PLACE_NEAR=Q7130.2:1MM

50V

10%

0603

X5R

1.0UF

0402

CERM

50V

20%

0.001UF

PLACE_NEAR=C7136.1:3mm

1/16W

5%

402

MF-LF

62K

1/16W

5%

402

MF-LF

100K

CRITICAL

TQFN

ISL6259

CRITICAL

0.005

MF

1% 1W

0612-6

1/16W

1%

402

MF-LF

68.1K

1/16W

1%

402

MF-LF

100K

50V

5%

402

COG

330PF

SO-8

SI7137DP

CRITICAL

1/16W

1%

402

MF-LF

1K

1/16W

1%

402

MF-LF

1K

CRITICAL

0.02

OMIT_TABLE

MF RL1632W

1W

0.5%

IRF9395TRPBF

CRITICAL

DIRECTFET-MC

BOM_COST_GROUP=POWER

SYNC_MASTER=AHARTMAN_J52

SYNC_DATE=11/06/2013

PBus Supply & Battery Charger

CRITICAL

R7120

1

107S0387

RES,MTL FILM,1W,20MOHM,0.5%,0612,LF,BLK

CHGR_VNEG

CHGR_AGATE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_PHASE

CHGR_CSO_R_N

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm

CHGR_ACIN

=SMBUS_CHGR_SDA

CHGR_RST_L

CHGR_BGATE

CHGR_CSO_R_P

CHGR_SGATE

CHGR_CSI_R_P

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

PPDCIN_G3H_CHGR

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_SGATE_DIV

VOLTAGE=0V

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PPBUS_G3H

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

MIN_NECK_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

CHGR_DCIN_D_R

P5V1_BIAS

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

NO_TEST=TRUE

P5V1_BOOST

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P5V1_SW

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.116 mm

MIN_LINE_WIDTH=0.116 mm VOLTAGE=18.5V

PPDCIN_G3H_INRUSH

CHGR_BOOT

MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_UGATE

GATE_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE DIDT=TRUE

CHGR_LGATE

CHGR_CSI_P

CHGR_CSO_N

CHGR_CSO_P

CHGR_CELL

=PPDCIN_S5_CHGR

CHGR_BMON =CHGR_ACOK

CHGR_DCIN_D_R

CHGR_VFRQ

CHGR_AMON

=SMBUS_CHGR_SCL

CHGR_DCIN

CHGR_ICOMP_RC

SMC_RESET_L

PP5V1_CHGR_VDDP

GND_CHGR_AGND

=PPDCIN_S5_CHGR_ISOL

=PP3V42_G3H_CHGR

CHGR_VCOMP_R

CHGR_VCOMP

CHGR_ICOMP

P5V1_FB

CHGR_VNEG_R

CHGR_CSI_R_N

CHGR_DCIN

CHGR_CSI_N

C7142

1

2

C7116

1

2

R7111

1

2

R7116

1

2

R7110

1

2

R7112

1

2

C7102

1

2

C7111

1

2

C7100

1

2

XW7100

12

C7105

1

2

C7150

1

2

R7100

12

R7102

1

2

R7101

12

R7105

12

C7101

1

2

D7105

1

2

3

C7185

1

2

R7185

1

2

R7186

1

2

C7126

1

2

R7151

12

R7152

12

C7125

1

2

C7122

1

2

C7120

1

2

C7121

1

2

R7122

12

R7121

12

C7155

1

2

C7156

1

2

C7157

1

2

C7140

1

2

C7130

1

2

C7131

1

2

C7135

1

2

C7145

1

2

F7140

12

C7136

1

2

C7137

1

2

R7181

1

2

R7180

1

2

U7100

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11 10

26

13

29

24

7

19

20

4

12

8

R7150

12 34

R7115

1

2

C7115

1

2

Q7155

5

4

1

2

3

R7142

1

2

R7120

123

4

Q7180

879

10

6

3

415

2

C7132

1

2

C7190

1

2

U7190

2

3

1

5

84

9

6

C7195

1

2

L7195

12

C7194

1

2

R7196

1

2

R7195

1

2

C7198

1

2

C7199

1

2

R7191

12

R7190

12

L7130

12

R7192

12

C7180

1

2

Q7130

2349

1

8

10

567

C7146

1

2

C7147

1

2

C7148

1

2

dvt1

051-1573

8.0.0

71 OF 120

54 OF 82

7

44 80

80

54

53 68

54

53 71

80

68

54

68

80

54

80

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

NC NC

OUT

IN

OUT

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(CPUVR_ISUMP)

FCCM = 0: DCM

(GND)

FCCM = 1: Forced CCM

FCCM = FLOATING: PS4

8

73

8

73

8

73

8

17

6

38 39 73

54.9

1/20W

1%

201

MF

PLACE_NEAR=U7200.32:2mm

1/20W 201

MF

130

PLACE_NEAR=U7200.30:2mm

1%

OMIT_TABLE

ISL95826

CRITICAL

LLP

17

56

1/20W

5%

0201

MF

0

402

10

5%

MF-LF

1/16W

0.22UF

PLACE_NEAR=U7200.17:2mm

X7R

25V

10%

0402

MF-LF

1/16W

5%

1

402

X6S-CERM

10V

PLACE_NEAR=U7200.16:2mm

10%

0402

1UF

56

10V

10%

0201

X7R-CERM

0.01UF

10V

10%

0201

X7R-CERM

0.01UF

56

0201

X6S

0.1UF

10%

6.3V

1/20W

6.04K

MF 201

1%1%

MF 201

1/20W

34K

44

1/20W

1%

201

MF

95.3K

10V

10%

0201

X7R

1500PF

56

X7R-CERM

25V

10%

201

220PF

NO_XNET_CONNECTION=TRUE

1/20W

1% 201

MF

845

25V

0201

X7R-CERM

820PF

10%

25V

5%

0201

C0G

22PF

8

73

9

73

16V

10%

0201

X7R

330PF

16V

10%

0201

X7R

330PF

10V

+/-10%

CERM

1.2NF

0201-1

25V

5%

0201

C0G

100PF

NO_XNET_CONNECTION=TRUE

25V

5%

0201

NP0-C0G

39PF

NO_XNET_CONNECTION=TRUE

1/20W

1%

201

MF

75K

NO_XNET_CONNECTION=TRUE

1/20W

1%

201

MF

1K

NO_XNET_CONNECTION=TRUE

1/20W

5%

0201

MF

0

1%

1/20W

10K

MF

201

95.3K

1/20W

1%

201

MF

PLACE_NEAR=L7310.1:3MM

PLACE_NEAR=Q7310.3:3MM

0201

100KOHM

1/20W

1%

201

MF

2K

NOSTUFF

NO_XNET_CONNECTION=TRUE

0201

16V

10% X7R

330PF

NOSTUFF

1/20W

1%

201

MF

1.69K

1%

201

MF

1/20W

316

1/20W

1%

201

MF

16.9KMF9.31K

201

1% 1/20W

SM

NO_XNET_CONNECTION=TRUE

1/20W

5%

0201

MF

NOSTUFF

0

6.3V

0.1UF

10%

0201

PLACE_NEAR=R7279.1:3mm

X6S

U7200

1

CRITICAL

353S00036

IC,ISL95826AS2378,PWM,PG,VR12.5/6,QFN-32

BOM_COST_GROUP=POWER

CPU VR12.6 VCC Regulator IC

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

CPUVR_PWM1

CPUVR_FCCM

CPUVR_NTC

CPUVR_ISEN1

CPUVR_NTC_R

CPUVR_ISEN2

=PP1V05_S0_CPU_VCCST

=PP5V_S0_CPUVR

CPUVR_DRSEL

CPUVR_PROG1

CPUVR_IMON

CPUVR_PGOOD

CPU_VCCSENSE_P_R

CPUVR_FB_RC

CPU_VCCSENSE_P_RC

=PPVIN_S0_CPUVR

CPU_PROCHOT_L

CPUVR_PWM2

CPU_VR_EN

CPUVR_COMP_RC

CPUVR_ISUMN_RC

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=12.9V

MIN_NECK_WIDTH=0.2 mm

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUVR_COMP

CPU_VIDALERT_L

CPUVR_PROG3

CPUVR_PROG2

CPUVR_SLOPE

CPUVR_FB CPUVR_FB2

CPU_RTN

CPUVR_ISUMN_R

CPU_VIDSOUT

CPUVR_ISUMN

CPU_VIDSCLK

MIN_LINE_WIDTH=0.3 mm VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_CPUVR_VDD

CPUVR_ISUMP

R7279

1

2

R7280

1

2

U7200

31

6

25

7 8

18

3

12 11 10

14

15

9

19 21 24

5

2

28 27 26 20

22

23

13

32

30

29

33

16

17

4

1

R7224

12

R7202

12

C7202

1

2

R7201

12

C7201

1

2

C7210

1

2

C7211

1

2

C7213

1

2

R7220

1

2

R7221

1

2

R7230

1

2

C7230

1

2

C7214

1

2

R7215

12

C7215

12

C7216

12

C7260

1

2

C7261

1

2

C7240

1

2

C7242

12

C7241

1

2

R7240

1

2

R7242

12

R7243

12

R7235

12

R7236

1

2

R7237

1

2

R7250

12

C7250

1

2

R7241

12

R7210

12

R7223

1

2

R7222

1

2

XW7261

12

R7225

1

2

C7278

1

2

55 OF 82

72 OF 120

8.0.0

051-1573

dvt1

6 8

15 16 17 68

56 68 56 68

IN

OUT

IN

OUT

IN

D

S

G

D

S

G

D

S

G

D

S

G

OUTOUT

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

THESE TWO CAPS ARE FOR EMC

152S1821

THESE TWO CAPS ARE FOR EMC

PHASE 2

F = 800KHZ

Vout = 1.85V max

.

353S3942

PHASE 1

353S3942

40A MAX OUTPUT

where the pads used to reside was preserved.

Note: C7377, C7379 were removed. Area

Additonal Input Bulk Caps

152S1821

68UF

20% 16V

CRITICAL

POLY-TANT CASE-D2E-SM

33UF

CASED12-SM

POLY-TANT

CRITICAL

16V

20%

33UF

20% 16V

CRITICAL

CASED12-SM

POLY-TANT

0.001UF

X7R-CERM

10% 50V

0402

X7R-CERM

10% 50V

0402

0.001UF

0402

35V CER-X6S

1UF

20%

0603

20% 16V

NOSTUFF

CRITICAL

10UF

X6S-CERMX6S-CERM

16V

10UF

0603

20%

CRITICAL

NOSTUFF

MF-LF 0201

1% 1/20W

1.00

CRITICAL

68UF

CASE-D2E-SM

20% 16V POLY-TANT

CASE-D2E-SM

CRITICAL

POLY-TANT

68UF

20% 16V

0.4UH-20%-23A

PILE063T-SM

CRITICAL

1/10W MF-LF

NOSTUFF

2.2

603

5%

50V

10%

0402

X7R-CERM

0.001UF

NOSTUFF

55

55 56

68UF

20% 16V

POLY-TANT CASE-D2E-SM

CRITICAL

NO_XNET_CONNECTION=TRUE

1/20W MF 201

1%

200K

201

1K

MF

1%

1/20W

55

55 56

NONE

NO_XNET_CONNECTION=TRUE

NONE

NOSTUFF

OMIT

0201

10% 50V

0.001UF

X7R-CERM 0402

55 56

0.001UF

10% 50V X7R-CERM 0402

20%

1UF

CER-X6S

35V 0402

1.00

MF-LF 0201

1% 1/20W

0603

16V

20%

CRITICAL

NOSTUFF

10UF

X6S-CERM

NOSTUFF

10UF

20% 16V

CRITICAL

0603

X6S-CERM

16V

CRITICAL

POLY-TANT

33UF

CASED12-SM

20%

16V

68UF

POLY-TANT CASE-D2E-SM

20%

CRITICAL

PILE063T-SM

0.4UH-20%-23A

CRITICAL

0.001UF

X7R-CERM 0402

10% 50V

NOSTUFF

200K

MF 201

1% 1/20W

NO_XNET_CONNECTION=TRUE

1K

MF

201

1%

1/20W

2.2

MF-LF

603

5%

1/10W

NOSTUFF

55

NOSTUFF

NONE 0201

NONE NONE

OMIT

NO_XNET_CONNECTION=TRUE

55

55 56

2.2

MF-LF

402

5%

1/16W

0.22UF

CERM

402

10% 16V

1UF

10% 16V

X6S-CERM

0402

1UF

X6S-CERM

0402

10% 16V

55 56

CRITICAL

POLY-TANT CASED12-SM

16V

20%

33UF

CASE-D2E-SM

68UF

20% 16V

POLY-TANT

CRITICAL

POLY-TANT

16V

20%

33UF

CASED12-SM

CRITICAL

2.2

MF-LF

402

5%

1/16W

0.22UF

CERM

402

10% 16V

OMIT_TABLE

CRITICAL

SISA18DN

PWRPAK-SM

SISA18DN

PWRPAK-SM

CRITICAL

OMIT_TABLE

0612-1

CRITICAL

1% MF

1W

0.00075

0612-1

0.00075

CRITICAL

1% 1W MF

SISA12DN

PWRPAK-SM

CRITICAL

OMIT_TABLE

PWRPAK-SM

CRITICAL

OMIT_TABLE

SISA12DN

43 56 80 43 80

ISL6208D

DFN

CRITICAL

ISL6208D

CRITICAL

DFN

20%

33UF

CRITICAL

16V

CASED12-SM

POLY-TANT

CRITICAL

CASED12-SM

POLY-TANT

33UF

20% 16V

CASED12-SM

33UF

20%

CRITICAL

NOSTUFF

POLY-TANT

16V

CASED12-SM

CRITICAL

NOSTUFF

POLY-TANT

33UF

16V

20%

BOM_COST_GROUP=POWER

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

CPU VR12.6 VCC Power Stage

DIDT=TRUE

CPUVR_PH1_SNUB

=PPVIN_S0_CPUVR

DIDT=TRUE

CPUVR_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUVR_ISNS1_N

PPVCC_S0_CPU_PH1

MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

CPUVR_ISEN1

CPUVR_ISUMN

CPUVR_ISUMP

CPUVR_ISNS1_P

CPUVR_PHASE2

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

CPUVR_PHASE1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT1

DIDT=TRUE

CPUVR_ISNS2_N

CPUVR_UGATE2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

GATE_NODE=TRUE

=PP5V_S0_CPUVR

CPUVR_ISNS2_N

CPUVR_ISEN2

CPUVR_PWM2

CPUVR_FCCM

CPUVR_PWM1

CPUVR_ISNS1_N

CPUVR_ISUMP

=PP5V_S0_CPUVR

CPUVR_ISUMN

CPUVR_ISNS2_P

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

PPVCC_S0_CPU_PH2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

CPUVR_BOOT2

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT2_RC

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_PH2_SNUB

MIN_NECK_WIDTH=0.2 MM

CPUVR_UGATE1

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

CPUVR_LGATE2

MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

CPUVR_LGATE1

=PPVCC_S0_CPU_REG

C7372

1

2

C7371

1

2

C7370

1

2

C7319

1

2

C7318

1

2

C7317

1

2

C7316

1

2

C7315

1

2

R7314

1

2

C7314

1

2

C7313

1

2

L7310

12

R7312

1

2

C7312

1

2

C7373

1

2

R7316

1

2

R7315

1

2

R7317

12

C7329

1

2

C7328

1

2

C7327

1

2

R7324

1

2

C7326

1

2

C7325

1

2

C7324

1

2

C7323

1

2

L7320

12

C7322

1

2

R7326

1

2

R7325

1

2

R7322

1

2

R7327

12

R7311

21

C7311

12

C7310

1

2

C7320

1

2

C7376

1

2

C7375

1

2

C7374

1

2

R7321

12

C7321

12

Q7310

5

4

123

Q7320

5

4

123

R7310

12 34

R7320

12 34

Q7311

5

4

123

Q7321

5

4

123

U7310

2

7

4

5

8

3

9

1

6

U7320

2

7

4

5

8

3

9

1

6

C7380

1

2

C7378

1

2

C7381

1

2

C7382

1

2

dvt1

051-1573

8.0.0

73 OF 120

56 OF 82

55 68

55 56 68

43 56 80

55 56 68

68

OUT

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

PHASE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(DDRREG_VDDQSNS)

VTT Enable

VDDQ/VTTREF Enable

10mA max load

C7460, C7461 close to memory

1.2V S3 Regulator

(DDRREG_LL)

(DDRREG_DRVL)

(DDRREG_DRVH)

152S1822

f = 400 kHz

9A MAX OUTPUT

VOUT = 1.2V

43 57

43 57 68

1% 1/16W MF-LF 402

57.6K

PLACE_NEAR=U7400.8:5mm

1/16W

1%

402

MF-LF

28.7K

PLACE_NEAR=U7400.8:5mm

PLACE_NEAR=U7400.6:1MM

0402

X7R-CERM

16V

10%

0.1UF

64

17

0402

16V

10%

0.01UF

X7R-CERM

PLACE_NEAR=U7400.8:1MM

PLACE_NEAR=U7400.19:3MM

402

1%

200K

MF-LF

1/16W

402

1%

PLACE_NEAR=U7400.18:3MM

51.1K

MF-LF

1/16W

CRITICAL

10UF

X5R-CERM

0402-1

20% 10V

PLACE_NEAR=U7400.12:1MM

QFN

CRITICAL

TPS51916

SM

PLACE_NEAR=U7400.21:1MM

10UF

X5R-CERM

0402-1

10V

PLACE_NEAR=U7400.2:1MM

20%

CRITICAL

0.22UF

10V

10%

CERM

402

PLACE_NEAR=C7461.1:3mm

SM

PLACE_NEAR=C7461.1:4mm

X5R-CERM

0603

10UF

20% 25V

CRITICAL

10UF

0603

20% 25V

CRITICAL

X5R-CERM

PLACE_NEAR=C7460.1:4mm

64

402

5%

MF-LF

1/16W

0

16V

20%

68UF

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

POLY-TANT

20% 16V

CASE-D2E-SM

MF

201

1/20W

5%

10

FDMS3602S

POWER56

CRITICAL

10% X5R

25V 402

0.1UF

0402

35V

10%

1.0UF

CERM-X6S

PLACE_NEAR=Q7430.5:3mm PLACE_NEAR=Q7430.5:3MM

CERM-X6S 0402

1.0UF

10% 35V

PLACE_NEAR=Q7430.2:1MM

PLACE_NEAR=C7435.1:3MM

0402

CERM

20%

0.001UF

50V

CRITICAL

PIME063T-SM

1.0UH-20%-15A-0.0066OHM

CRITICAL

CASE-B2-SM1

POLY-TANT

2.0V

20%

330UF

20%

CRITICAL

2.0V POLY-TANT CASE-B2-SM1

CASE-B2-SM1

POLY-TANT

2.0V

330UF

20%

CRITICAL

20% 25V

0603

10UF

X5R-CERM

PLACE_NEAR=C7442.1:2MM

SM

50V

10% X7R-CERM

0402

0.001UF

0201

25V

5%

12PF

NP0-C0G

SM

BOM_COST_GROUP=POWER

SYNC_MASTER=J41_MLB

LPDDR3 Supply

SYNC_DATE=05/21/2013

=PPDDR_S3_REG

PPDDR_S3_REG_R

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

=PPVIN_S3_DDRREG

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS_R

DDRREG_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVL

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST_RC

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

=PPVIN_S0_DDRREG_LDO

=PP5V_S3_DDRREG

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

VOLTAGE=0V

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

NO_TEST=TRUE

DDRREG_PGOOD

DDRREG_VTTSNS

DDRREG_1V8_VREF

=DDRREG_EN

=DDRVTT_EN

DDRREG_MODE DDRREG_TRIP

DDRREG_FB

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

=PPDDR_S3_REG

PPDDR_S3_REG_R

DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

R7416

1

2

R7415

1

2

C7415

1

2

C7416

1

2

R7417

1

2

R7418

1

2

C7400

1

2

U7400

14

11

7

19

10

20

8

17 16

13

21

18

12 15

9

2

6

3

4

5

1

XW7400

1

2

C7401

1

2

C7450

1

2

XW7460

12

C7460

1

2

C7461

1

2

R7425

12

C7431

1

2

C7434

1

2

R7401

12

Q7430

2

1

6

7

345

C7425

12

C7432

1

2

C7435

1

2

C7433

1

2

L7430

12

C7442

1

2

C7440

1

2

C7441

1

2

C7445

1

2

XW7401

1

2

C7446

1

2

C7420

1

2

XW7450

12

dvt1

051-1573

8.0.0

74 OF 120

57 OF 82

43 57

68

43 57 68

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

PHASE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(P5VP3V3_VREF2)

100MA MAX OUTPUT

(P5VP3V3_VREF2)

376S0958

152S0754152S0688

VOUT = 3.3V

F = 600 KHZ

10.5A MAX OUTPUT

VOUT = 5.0V

F = 600 KHZ

10.8A MAX OUTPUT

VOUT = 5V

25V

10%

603-1

X5R

1UF

PCMC063T-SM

1.0UH-22A

CRITICAL

50V

10%

603-1

X7R

0.1UF

25V

20%

0603

X5R-CERM

10UF

CRITICAL

50V

10% X7R

0.1UF

603-1

6.3V

20%

CASE-D3L-SM

POLY-TANT

330UF

CRITICAL

25V

20%

0603

X5R-CERM

10UF

CRITICAL

25V

10% X6S-CERM

4.7UF

0603

10V

20%

402

X5R-CERM

2.2UF

10UF

CRITICAL

6.3V

20%

603

X5R

1/16W

1%

402

MF-LF

165K

64

SM

PLACE_NEAR=L7560.1:3MM

10V

10%

402

CERM

0.22UF

1/16W

0.5%

0402

MF-LF

23.2K

1/16W

0.5%

402

MF

10.0K

41.2K

1/16W

1%

402

MF-LF

1/16W

0.5%

402

MF

10.0K

16V

20%

CASE-D2E-SM

POLY-TANT

CRITICAL

68UF

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

16V

10%

0402

X7R-CERM

0.1UF

SM

PLACE_NEAR=L7560.2:3MM

10%

0402

X7R-CERM

0.1UF

16V

1/16W

1%

402

MF-LF

2.49K

1/16W

1%

402

MF-LF

3.01K

PLACE_NEAR=L7520.1:3MM

SM

PLACE_NEAR=L7520.2:3MM

SM

402

MF-LF

1%

12.1K

1/16W

10K

1%

402

MF-LF

1/16W

100V

10%

402

CERM

4700PF

50V

5%

402

CERM

150PF

SM

PLACE_NEAR=C7592.1:3MM

SM

PLACE_NEAR=C7553.1:3MM

6.3V

20%

CASE-D3L-SM

POLY-TANT

330UF

CRITICAL

1/16W

1%

402

MF-LF

10K

47PF

0402

CER

50V

5%

1%

402

MF-LF

12.1K

1/16W

100V

10%

402

CERM

4700PF

64

10%

0.0033UF

NO STUFF

402

CERM

50V

NO STUFF

5%

603

1

1/10W MF-LF

1/10W

5%

603

MF-LF

10

NO STUFF

50V

10%

0402

X7R-CERM

0.001UF

50V

20%

0402

CERM

0.001UF

50V

20%

0402

CERM

0.001UF

50V

10%

0402

X7R-CERM

0.001UF

TPS51980

QFN

CRITICAL

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

64

1/16W

1%

402

MF-LF

1.82K

1/16W

1%

402

MF-LF

5.23K

1/16W

5%

402

MF-LF

0

5%

402

MF-LF

1

1/16W

25V

10%

0603

X6S-CERM

4.7UF

64

50V

10%

0402

X7R-CERM

NO STUFF

0.001UF

PCMB103T-1R0MS

CRITICAL

1.0UH-21A-0.006OHM

SM

PLACE_NEAR=U7501.28:1MM

CSD58872Q5D

SON5X6

CRITICAL

POLY-TANT CASE-D3L-SM

6.3V

20%

330UF

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

5%

0201

MF

0

1/20W

SKIP_5V3V3:AUDIBLE

0201

5% MF

1/20W

0

SKIP_5V3V3:INAUDIBLE

POWER56

FDMS3602S

CRITICAL

CASE-D2E-SM

16V

20%

POLY-TANT

68UF

CRITICAL CRITICAL

16V

CASE-D2E-SM

68UF

20%

POLY-TANT

1/16W

5%

402

MF-LF

10

1/16W MF-LF

5%

10

402

0201

12PF

5% NP0-C0G

25V

0201

25V

NP0-C0G

5%

12PF

25V NP0-C0G

5%

12PF

0201

12PF

NP0-C0G

25V

5%

BOM_COST_GROUP=POWER

SYNC_MASTER=J14

SYNC_DATE=10/23/2012

5V & 3.3V Power Supply

P5VS3_CSP1

P5VS3_VFB1_R

P5VS3_CSP1_R

DIDT=TRUE

P5VS3_SNUBR

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_REG

P5VP3V3_VREF2

=PP3V3_S5_REG

P5VS3_COMP1

P5VS5_EN

P5VS3_CSN1

MIN_LINE_WIDTH=0.6 MM

P5VS3_DRVL

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

P5VS3_LL

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP5V_S5_LDO

=PPVIN_S5_HS_OTHER3V3_ISNS

P3V3S5_LL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

P3V3S5_VFB2

P5VS3_VFB1

=PP5V_S3_REG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_DRVL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

P3V3S5_VBST

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS3_VBST

DIDT=TRUE

SWITCH_NODE=TRUE

=PPVIN_S5_HS_OTHER5V_ISNS

P5VP3V3_VREG3

=PP5V_S3_REG

P5VP3V3_SKIPSEL

P3V3S5_PGOOD

P3V3S5_EN

P3V3S5_VFB2_R

P3V3S5_RF

P3V3S5_VFB2_RR

5VS3_VFB1_RR

P3V3S5_CSP2

P3V3S5_COMP2_R

P3V3S5_COMP2

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

P5VS3_TG

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

P3V3S5_TG

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_DRVH

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P3V3S5_SNUBR

DIDT=TRUE

SWITCH_NODE=TRUE

P3V3S5_CSN2

P3V3S5_CSP2_R

DIDT=TRUE

P5VS3_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

P5VS3_PGOOD

P5VS3_EN

P5VS3_COMP1_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

P5VS3_VSW

GND_5V3V3_AGND

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM VOLTAGE=0V

C7500

1

2

L7560

12

C7564

1

2

C7590

1

2

C7524

1

2

C7552

1

2

C7550

1

2

C7581

1

2

C7503

1

2

C7505

1

2

R7506

1

2

XW7561

1

2

C7501

1

2

R7560

1

2

R7561

1

2

R7520

1

2

R7521

1

2

C7580

1

2

C7540

1

2

C7588

12

XW7560

1

2

C7518

12

R7547

12

R7556

1

2

XW7520

1

2

XW7521

1

2

R7536

1

2

R7537

1

2

C7536

1

2

C7537

1

2

XW7562

1

2

XW7522

1

2

C7592

1

2

R7539

1

2

C7539

1

2

R7538

1

2

C7538

1

2

C7599

1

2

R7599

1

2

R7598

1

2

C7572

1

2

C7583

1

2

C7570

1

2

C7571

1

2

U7501

10

15

8

17

7

18

1

24

30

27

12

4

21

28

11

14

5

20

3

6

19

32

25

33

2

31

26

9

16

23

13

22

29

C7542

1

2

R7546

12

R7516

1

2

R7563

12

R7544

1

2

C7541

1

2

C7598

1

2

L7520

1

2

XW7500

1

2

Q7520

5

9

3

4

1

6 7 8

C7553

1

2

C7582

1

2

R7500

1

2

R7501

1

2

Q7560

2

1

6

7

345

C7543

1

2

C7584

1

2

R7562

1

2

R7522

1

2

C7520

1

2

C7521

1

2

C7522

1

2

C7523

1

2

75 OF 120

8.0.0

051-1573

58 OF 82

dvt1

58 68

68

42 68

58 68

42 68

58 68

GND

HSG

V+

LSG

SW

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1.05V S0 Regulator

Scrub S3 & S5 pins connections!

F = 400 KHZ

Vout = 1.05V

Short Rsense

5A MAX OUTPUT

16V

10%

0402

X7R-CERM

0.1UF

25V

5%

0402

CERM

1000PF

PLACE_NEAR=L7630.2:1.5mm

PLACE_NEAR=Q7630.8:1.5mm

0402

25V

CERM

1000PF

5%

MF-LF

1/10W

5%

603

2.2

1/16W

5%

402

MF-LF

0

2.0V

20% POLY-TANT

CRITICAL

330UF

CASE-B2-SM1

CRITICAL

2.0V

20%

POLY-TANT

330UF

1.0UH-13A-7.8MOHM

CRITICAL

SPM6530T-SM

CASE-D2E-SM

16V

68UF

POLY-TANT

20%

CRITICAL

LLP

FDPC1012S

0402

35V CER-X6S

1UF

20%

NOSTUFF

50V

10%

0402

X7R-CERM

0.001UF

NOSTUFF

MF-LF

1/10W

5%

603

2.2

X6S-CERM

0402

1UF

10V

10%

SM

PLACE_NEAR=U7600.21:1mm

10V

10UF

BYPASS=U7600.2::1mm

20%

0603

X6S-CERM

QFN

TPS51916

CRITICAL

1/20W

1%

201

MF

14.7K

PLACE_NEAR=U7600.18:3mm

10V

BYPASS=U7600.12::1mm

10UF

20%

0603

X6S-CERM

1/20W

1%

201

MF

47.5K

PLACE_NEAR=U7600.19:3mm

16V

10%

0402

X7R-CERM

0.01UF

BYPASS=U7600.8::1mm

1/20W

1%

201

MF

35.7K

PLACE_NEAR=U7600.8:5mm

1/20W

1%

201

MF

49.9K

PLACE_NEAR=U7600.8:5mm

16V

10%

0402

X7R-CERM

0.1UF

BYPASS=U7600.6::1mm

1/20W

1%

201

MF

1K

SM

PLACE_NEAR=C7648.1:1mm

1/20W

5%

201

MF

10

43 80

64

1W

1% MF

0.003

0612-SHORT

OMIT

0201

NP0-C0G

25V

5%

12PF

5%

12PF

0201

NP0-C0G

25V

BOM_COST_GROUP=POWER

SYNC_MASTER=AHARTMAN_J52

SYNC_DATE=10/29/2013

1.05V Power Supply

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P1V05S0_DRVH_R

GATE_NODE=TRUE

ISNS_1V05_S0_N

=PP1V05_S0_REG

=PPVIN_S0_1V05S0

=PPVIN_S0_1V05S0_LDO

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P1V05_S0_VREF

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P1V05S0_FB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

P1V05S0_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

P1V05S0_VDDQSNS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVL

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P1V05S0_BOOT_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V05S0_VTT

P1V05S0_MODE

=P1V05S0_EN

P1V05S0_PGOOD

P1V05S0_TRIP

P1V05S3_EN

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

P1V05S0_VDDQSNS_R

=PP1V05_S0_REG

=PP5V_S0_1V05S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

P1V05S0_AGND

P1V05S0_VTTREF

PP1V05_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

ISNS_1V05_S0_P

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVH

DIDT=TRUE

GATE_NODE=TRUE

P1V05S0_LL_SNUB

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_LL

SWITCH_NODE=TRUE

C7630

1

2

C7623

1

2

C7622

1

2

R7630

1

2

R7631

12

C7648

1

2

C7649

1

2

L7630

12

C7619

1

2

Q7630

5

6

10

1

7

2 3 4

8 9

C7624

1

2

C7632

1

2

R7632

1

2

C7650

1

2

XW7600

1

2

C7601

1

2

U7600

14

11

7

19

10

20

8

17 16

13

21

18

12 15

9

2

6

3

4

5

1

R7614

1

2

C7600

1

2

R7613

1

2

C7616

1

2

R7611

1

2

R7612

1

2

C7615

1

2

R7610

1

2

XW7610

1

2

R7641

12

R7640

12 34

C7621

1

2

C7620

1

2

dvt1

051-1573

8.0.0

76 OF 120

59 OF 82

59 68

68

64

59 68

68

SW

VDDD

VDDA

GD

SW

VSENSE_N

SD

GND_SW2

GNDD

GNDA

THRM

FB

SENSE_OUT

PWM_KEYB

SCL SDA

KEYB2

KEYB1

FB2

SW2

GND_SW

ISET_KEYB

EN

VSENSE_P

PAD

IN

BI

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Power aliases required by this page:

- =PP5V_S0SW_KBDLED (5V KEYBOARD BACKLIGHT INPUT)

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds

SENSOR ON PAGE 54 USES R7700 TO MEASURE THE

PLACEMENT_NOTE:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

BKLT:PROD - Stuffs 0 ohm series R for production

152S1701

LCD BKLT LINE WIDTHS

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

371S0704

PBUS LINE WIDTHS

KBD BKLT LINE WIDTHS

PLACEMENT_NOTE:

Page Notes

BOM options provided by this page:

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

740S0159

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

371S0572

PLACEMENT_NOTE:

353S4160

(IPU)

152S1527

POWER GOING TO LCD BACKLIGHT

LLP

LP8548B1SQ_-04

CRITICAL

0603

3AMP-32V

22UH-20%-2.4A-0.105OHM

CRITICAL

PLACE_NEAR=Q7701.5:3MM

DEM8030C-SM

PST041H-SM

10UH-20%-1.4A-0.17OHM

CRITICAL

PLACE_NEAR=U7700.6:5MM

1/16W

1%

402

MF-LF

80.6K

1000PF

16V

10%

0201

X7R-1

1/16W

1%

402

MF-LF

63.4K

SSOT6-HF

FDC638APZ_SBMS001

CRITICAL

PLACE_NEAR=L7710.2:3MM

POWERDI-123

DFLS2100

CRITICAL

1000PF

X7R-CERM

10% 100V

0603

PLACE_NEAR=D7710.K:5MM

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=L7720.1:5MM

25V

10%

603

X5R-CERM

2.2UF

PLACE_NEAR=L7720.1:5MM

SANDWICH C7720 AND C7721

50V

10%

0402

X7R-CERM

0.001UF

PLACE_NEAR=D7720.K:5MM

1/20W

5%

0201

MF

0

25V

5%

0201

NPO-C0G

33PF

NO STUFF

1/20W

5%

0201

MF

0

PLACE_NEAR=U7700.15:10MM

1/20W

5%

0201

MF

0

PLACE_NEAR=U7700.16:10MM

1/20W

5%

0201

MF

0

1UF

X5R

10V

10%

402

PLACE_NEAR=U7700.5:5MM

PLACE_NEAR=U7700.18:5MM

10% 10V

402

X5R

1UF

1/20W

5%

201

MF

2.4K

1/20W

5%

201

MF

2.4K

1/20W

5%

201

MF

1M

SM

25V

10%

402

X5R

0.1UF

PLACE_NEAR=L7710.1:5MM

65

38

69

50V

10%

402

CERM

0.001UF

NOSTUFF

25V

10%

0603

X6S-CERM

4.7UF

SANDWICH C7710 AND C7711

PLACE_NEAR=L7710.1:5MM

4.7UF

25V

10%

0603

X6S-CERM

PLACE_NEAR=L7710.1:5MM

SANDWICH C7710 AND C7711

PLACE_NEAR=D7710.K:2MM

SM

PLACE_NEAR=U7700.20:5MM

1/20W

1%

201

MF

31.6K

SOD-123

RB160M-60G

CRITICAL

PLACE_NEAR=L7720.2:5MM

50V

10%

0805

X7R

1.0UF

SANDWICH C7723 AND C7724

PLACE_NEAR=D7720.K:5MM

50V

10%

0805

X7R

1.0UF

SANDWICH C7723 AND C7724

PLACE_NEAR=D7720.K:5MM

25V

10%

603

X5R-CERM

2.2UF

PLACE_NEAR=L7720.1:5MM

SANDWICH C7720 AND C7721

25V

5%

0201

NPO-C0G

33PF

NO STUFF

SM

PLACE_NEAR=D7720.K:2MM

PLACE_NEAR=U7700.1:3MM

SI7812DN

CRITICAL

PWRPK-1212-8

1%

402

13.3K

MF-LF

1/16W

150K

1%

402

MF-LF

402

1/16W

5% MF-LF

0

42 80

1W

1%

0612

MTL

0.025 OMIT_TABLE

42 80

1/16W

5%

402

MF-LF

0

50V

10%

0805

X7R

1.0UF

T-BONE C7726 AND C7727

PLACE_NEAR=D7720.K:9MM

10%

0805

X7R

50V

1.0UF

PLACE_NEAR=D7720.K:9MM

1/16W

5%

402

MF-LF

0

1/16W

0.1%

402

TF

10.2

PLACE_NEAR=U7700.13:10MM

BKLT:ENG

1/16W

0.1%

402

TF

10.2

BKLT:ENG

PLACE_NEAR=U7700.14:10MM

10%

PLACE_NEAR=D7710.K:5MM

1206

2.2UF

100V X5R

10% 100V X5R

2.2UF

1206

PLACE_NEAR=D7710.K:5MM

2.2UF

100V X5R

10%

1206

PLACE_NEAR=D7710.K:5MM

10%

2.2UF

X5R

PLACE_NEAR=D7710.K:5MM

100V

1206

2.2UF

10%

PLACE_NEAR=D7710.K:5MM

1206

100V X5R

2.2UF

PLACE_NEAR=D7710.K:5MM

1206

10%

X5R

100V

100V X5R 1206

PLACE_NEAR=D7710.K:5MM

2.2UF

10%

PLACE_NEAR=D7710.K:5MM

100V X5R

2.2UF

10%

1206

PLACE_NEAR=D7710.K:5MM

10%

2.2UF

X5R

100V

2.2UF

PLACE_NEAR=D7710.K:5MM

1206

10%

X5R

100V

10%

X5R 1206

2.2UF

PLACE_NEAR=D7710.K:5MM

10%

2.2UF

X5R

100V

1206

PLACE_NEAR=D7710.K:5MM

10%

X5R 1206

2.2UF

100V

1206

PLACE_NEAR=D7710.K:5MM

10% 100V

2.2UF

X5R

5%

0402

12PF

100V CERM

5%

0402

100V

12PF

CERM

5%

0402

12PF

100V CERM

5% CERM

100V

12PF

0402

5% CERM

100V

12PF

0402

116S0004

BKLT:PROD

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

R7720,R7721

1

CRITICAL

RES,MTL FILM,1W,25MOHM,1%,4TERM,0612,BLK

R7700

1

107S0386 CRITICAL

BOM_COST_GROUP=DISPLAY

SYNC_MASTER=SHART_J44

LCD & KBD Backlight Driver

SYNC_DATE=11/20/2012

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM

MAKE_BASE=TRUE

VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_F

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=5V

PP5V_S0_BKLT_D

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=53V

PPVIN_SW_LCDBKLT_SW

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V

GND_BKLT_SGND

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=53V

LCDBKLT_SW

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_FET

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=53V

PPVOUT_BKLT_FB

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=5V

LCDBKLT_FET_DRV

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=5V

LCDBKLT_FET_DRV_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_R

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=40V

PPVOUT_BKLT_FB2

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=40V

PP5V_S0_KBDBKLT_SW

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V

PPVOUT_S0_KBDBKLT

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=2 MM VOLTAGE=5V

PP5V_S0_BKLT_A

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=53V

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.3 MM

KBDLED_CATHODE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_CATHODE1

PPVOUT_S0_LCDBKLT

LCDBKLT_SW

PP5V_S0_BKLT_D

PPVIN_SW_LCDBKLT_SW

GND_BKLT_SGND

LCDBKLT_EN_L

PP5V_S0_KBDBKLT_SW

GND_BKLT_SGND

=I2C_BKLT_SDA

BKLT_SCL

GND_BKLT_SGND

LCDBKLT_FET_DRV

BKLT_SDA

=I2C_BKLT_SCL

EDP_BKLT_PSR_EN

LCDBKLT_FET_DRV_R

SMC_SYS_KBDLED

BKLT_EN_R

=PP5V_S0_BKLT

BKLT_SD

BKLT_SENSE_OUT

=PP5V_S0SW_KBDLED

BKLT_PWM_KEYB

BKLT_KEYB1 BKLT_KEYB2

PP5V_S0_BKLT_A

LCDBKLT_TB_XWR

=PPVIN_S0SW_LCDBKLTFET

PPVOUT_S0_KBDBKLT

BKLT_ISET_KEYB

PPVIN_S0SW_LCDBKLT_R

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

LCDBKLT_FB

=PP5V_S0_BKLT

PPVIN_S0SW_LCDBKLT_F

PPVOUT_BKLT_FB2

U7700

17

21

8

4

7

232422

3

20

13 14

12

15

11

16

19

6

1

2

25

18

5

9

10

F7700

12

L7710

12

L7720

12

R7701

1

2

C7700

1

2

R7702

1

2

Q7700

1

2

5

6

3

4

D7710

AK

C7717

1

2

C7722

1

2

C7721

1

2

C7725

1

2

R7747

12

C7747

1

2

R7750

12

R7751

12

R7742

12

C7740

1

2

C7741

1

2

R7752

1

2

R7753

1

2

R7740

1

2

XW7700

12

C7712

1

2

C7701

1

2

C7710

1

2

C7711

1

2

XW7710

1

2

R7741

1

2

D7720

AK

C7723

1

2

C7724

1

2

C7720

1

2

C7742

1

2

XW7720

1

2

Q7701

5

4

123

R7731

1

2

R7732

1

2

R7733

1

2

R7700

12 34

R7744

1

2

C7726

1

2

C7727

1

2

R7745

1

2

R7720

12

R7721

12

C7770

1

2

C7771

1

2

C7772

1

2

C7773

1

2

C7765

1

2

C7760

1

2

C7766

1

2

C7767

1

2

C7761

1

2

C7762

1

2

C7768

1

2

C7769

1

2

C7763

1

2

C7764

1

2

C7774

1

2

C7775

1

2

C7776

1

2

C7777

1

2

C7778

1

2

dvt1

8.0.0

77 OF 120

60 OF 82

051-1573

60

37 60 71

60

60 65 71

37 71

60 65 71

60

60 68

68

60

68

37 60 71

60

60 68

60

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

OUT

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Freq = 1 MHz

Max Current = 1.8A

Freq = 1.6MHZ

152S1870

<Rb>

<Ra>

Max Current = 0.35A

1.05V SUS LDO

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

353S2535

<Ra>

Vout = 1.05V

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production).

Short Rsense

1.8V S3 REGULATOR

1.5V S0 Switcher

152S1051

70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.508V

MAX CURRENT = 0.6A

Vout = 1.794V

XDP

1UF

10%

6.3V CERM

402

CRITICAL

TPS720105

SON

XDP_CONN

X5R 402

10%

XDP

6.3V

2.2UF

1/16W

1%

402

MF-LF

113K

1%

402

MF-LF

100K

1/16W

6.3V

20%

0603

X5R

22UF

CRITICAL

64

6.3V

20%

0603

X5R

22UF

CRITICAL

2512

CRITICAL

2.2UH-2A-0.155-OHM

0402

CERM

10PF

5%

50V

CRITICAL

DFN

ISL8009B

1/16W

5%

402

10

MF-LF

CRITICAL

0603

6.3V

20% X5R

22UF

603

X5R-CERM-1

CRITICAL

20%

6.3V

603

X5R-CERM-1

CRITICAL

22UF

20%

6.3V

C0G

5% 25V

47PF

0201

20%

22UF

CRITICAL

603

6.3V

X5R-CERM-1

1/20W

113K

1%

MF

201

2.2UH-20%-2.0A-0.108OHM

2520-SM

CRITICAL

90.9K

1/20W

1%

201

MF

ISL8009B

DFN

CRITICAL

16V

X7R-1

0201

1000PF

10%

64

43 80

OMIT

0612-SHORT

0.002

1W MF

1%

X5R-CERM-1

20%

22UF

603

CRITICAL

6.3V

X5R

10V

20%

10UF

0603-1

CRITICAL

X5R

CRITICAL

0603-1

10V

10UF

20%

5%

402

10

MF-LF

1/16W

0201

NP0-C0G

25V

5%

12PF

5% NP0-C0G

25V 0201

Misc Power Supplies

SYNC_MASTER=AHARTMAN_J52

BOM_COST_GROUP=POWER

SYNC_DATE=11/06/2013

=PP3V3_S3_P1V8S3

=PP1V05_SUS_LDO

PP1V8_S3_REG_R

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

P1V8S3_FB

=PP1V5_S0_REG

ISNS_1V8_S3_N

=PP1V8_S3_REG

ISNS_1V8_S3_P

=PP1V8_S3_REG

DIDT=TRUE

SWITCH_NODE=TRUE

P1V8S3_SW

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

P1V5_S0_SW

SWITCH_NODE=TRUE DIDT=TRUE

P1V8S3_FB_R

=P1V8S3_EN

P1V8S3_PGOOD

P1V5_S0_FB_R

=PP3V3_SUS_P1V05SUSLDO

P1V5S0_PGOOD

=P1V5S0_EN

=PP3V3_S0_P1V5S0

P1V5_S0_FB

C7840

1

2

U7840

4

3

5

6

1

7

C7841

1

2

R7881

1

2

R7880

1

2

C7873

1

2

C7870

1

2

L7870

12

C7876

1

2

U7870

2

7

8

3

54

9

6

1

R7882

1

2

C7874

1

2

C7825

1

2

C7821

1

2

C7823

1

2

C7822

1

2

R7820

1

2

L7820

12

R7821

1

2

U7820

2

7

8

3

54

9

6

1

C7824

1

2

R7829

12 34

C7826

1

2

C7820

1

2

C7827

1

2

R7822

1

2

C7800

1

2

C7801

1

2

dvt1

051-1573

8.0.0

78 OF 120

61 OF 82

2

68

61 68

68

IN

BI

SYM_VER_2

GS

D

S

G

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RC Value not Final

(Open-Drain)

5%

33K

1/16W

402

MF-LF

16V

10%

402

X5R

0.033UF

X7R-CERM

16V

10%

0402

0.01UF

36 71

X5R-CERM

10UF

0603

20% 25V

0603

X5R-CERM

10UF

38

DMN32D2LFB4

CRITICAL

DFN1006H4-3

402

1/16W MF-LF

5%

47K

PWRPK-1212-8

SI7121DN

CRITICAL

201

1/20W

100K

5% MF

0

5% 1/16W MF-LF 402

402

MF-LF

1/16W

5%

0

BOM_COST_GROUP=TRACKPAD

SYNC_MASTER=AHARTMAN_J52

SYNC_DATE=11/06/2013

X239 Power Supply

PVIN_S4_TPAD_EN_L

PVIN_S4_TPAD_EN

TPAD_ACTUATOR_THRMTRIP_L

SMC_ACTUATOR_DISABLE_L

=PPVIN_X239

=PP3V3_S4_X239

PVIN_S4_TPAD_SS

=PPBUS_X239_REG

C7900

1

2

C7901

1

2

Q7972

3

1

2

R7972

1

2

Q7979

5

4

123

R7976

1

2

R7926

12

R7922

12

R7970

12

C7971

1

2

C7970

1

2

dvt1

051-1573

8.0.0

79 OF 120

62 OF 82

68

IN

GND

VOUT

ON

VIN

NC NC

IN

NCNC

IN

NC NC

GND

VDD

D

SON

CAP

IN

GND

VOUT

ON

VIN

IN

S

D

ON S

D

VDD

GND

VDD

D

SON

CAP

GND

VOUT

ON

VIN

VOUT

GND

ON

VIN

ON

GND

VOUT

VIN

ON

GND

VOUT

NC

NC NC

NC

IN

GND

VDD

D

SON

CAP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Sense R on sensor page

Load Switch

63 mOhm Typ

3.3V SSD Switch

CAPACITORS ADDED FOR NOISE FLOOR REASONS:

1.5V S0 Audio Switch (BYPASSED)

2A Max

8.5 mOhm Max

5V S4 Switch

5V S0 Switch

Placement Note: Place C8090, C8091 and C8092 near U8000

Type

SLG5AP1443V

Load Switch

17 mOhm Typ

EDP: 16mA

Part

U8040

EDP: 2.4A

3.3V S4 Switch

SLG5AP1453V

Load Switch

R(on)

U8000

3.3V SUS Switch

U8050

3.3V Sensor Switch

Current

TBD mOhm Max

9.8 mOhm Typ

Type

R(on) @ 4V Vgs

SLG5AP1417V

1.05V PCH HSIO Switch

Part

U8005

6A Max

Load Switch

EDP: 1.84A

EDP: 1A

U8030

Sense R on sensor page

18.5 mOhm Typ

Load Switch

TPS22924C

R(on)

EDP: 50mA

TPS22924C

U8010

Type

R(on) @ 2.5V

25.8 mOhm Max

@ 2.5V

R(on)

Type

Current

2A Max

@ 1.8V

Current

19.6 mOhm Typ

25.8 mOhm Max

Type

EDP: 5A

21.8 mOhm Max

Type

Part

Current

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

Part Part

U8020

@ 3.6V

77 mOhm Max

Current

TPS22934

Part

Type

R(on)

Load Switch

TPS22934

77 mOhm Max

63 mOhm Typ

1A Max

Current

@ 3.6V

U8070

EDP: 167mA

1A Max

Load Switch

Type

@ 25C

3.3V S3 Switch

TPS22920

5.5 MOHM TYP

8.8 MOHM MAX

4A MAX

@ 3.6V

Part

Current

Type

3.3V S0 Switch

EDP: 0.5A

Load Switch

R(on)

Load Switch

7.8 mOhm Typ

R(on)

EDP: 1.1A

Current

2.5A

R(on)

Type

Part

U8080

SLG5AP1443V

Load Switch

19 mOhm Max

2.5A

Current

Part

18.5 mOhm Typ

U8060

TPS22924C

5.3A Max

EDP: 1.02A

Current

R(on)

17 mOhm Typ

REMOVED THE ANALOG POWER GATE AS SLG5AP1471 SHOULD BE AVAILABLE BY THEN

63 64

1.0UF

X5R

0201-1

20%

6.3V

CRITICAL

TPS22924

CSP

64

1.0UF

X5R

0201-1

20%

6.3V

0201-1

1.0UF

X5R

20%

6.3V

64

SLG5AP1453V

CRITICAL

TDFN

4700PF

X7R 201

10% 10V

0.1UF

CERM-X5R 0201

10%

6.3V

64

1.0UF

X5R

0201-1

20%

6.3V

CRITICAL

TPS22924

CSP

0.002

0612-SHORT

OMIT

MF

1% 1W

0612-SHORT

0.002

OMIT

MF

1% 1W

OMIT

0.002

MF

0612-SHORT

1% 1W

NOSTUFF

1.0UF

X5R

0201-1

20%

6.3V

64

NOSTUFF

10K

MF

201

5%

1/20W

NOSTUFF

0

MF

0201

5%

1/20W

63 64

0

MF

0201

5%

1/20W

40

1.0UF

X5R

0201-1

20%

6.3V

0

MF-LF

402

5%

1/16W

0201

X5R-CERM

16V

10%

0.1UF

64

15

SLG5AP1471V

TDFN

CRITICAL

TDFN

SLG5AP1443V

CRITICAL

10V

10%

201

X7R

4700PF

CRITICAL

TPS22924

CSP

NOSTUFF

CSP

CRITICAL

TPS22920

1UF

X5R 402

10% 10V

CRITICAL

TPS22934

DSBGA

CRITICAL

TPS22934

DSBGA

CERM-X7R 0603

50V

10%

0.0022UF

0603

50V CERM-X7R

10%

0.0022UF

0603

50V CERM-X7R

10%

0.0022UF

NP0-C0G

25V

5%

0201

12PF

NP0-C0G

12PF

0201

25V

5%

NP0-C0G 0201

12PF

25V

5% 5%

25V

12PF

0201

NP0-C0G

0.1UF

10% 16V

0201

X5R-CERM

64

CRITICAL

SLG5AP1443V

TDFN

10V

10%

201

X7R

4700PF

NP0-C0G

12PF

0201

25V

5%

NP0-C0G

25V

5%

12PF

0201

NP0-C0G 0201

5%

12PF

25V

NP0-C0G

25V

12PF

5%

0201

NP0-C0G 0201

25V

12PF

5%

SYNC_MASTER=J41

BOM_COST_GROUP=POWER

SYNC_DATE=10/23/2012

Power FETs

=PP5V_S5_FET

=PP5V_S5_P5VS5FET

=PP3V3_S4SW_SNS_FET

=P5VS4_EN

MIN_NECK_WIDTH=0.17 mm

PP1V5_S0SW_AUDIO_HDA

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm

P5VS5_FET_RAMP

=PP3V3_SUS_P3V3SUSFET

=PP5V_S0_FET

=P5VS0_EN

P5VS0_FET_RAMP

=PP3V3_S4_FET

=P3V3S0_EN

=PP1V5_S0SW_P1V5S0SWAUDIOFET

P1V5S0SW_AUDIO_EN

=P3V3S0_EN

=P3V3S4_EN

=PP3V3_S4_P3V3S4FET

=PP3V3_S0_P3V3S0FET

=PP3V3_SUS_FET

=PP3V3_S3_P3V3S3FET

P3V3S0SW_SSD_FET_RAMP

=PP3V3_S3_FET

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

=P3V3S3_EN

=PP3V3_S0_FET

=PP1V05_S0SW_PCH_HSIO_FET

=PP3V3_S0SW_P3V3S0SWSSDFET

PCH_HSIO_PWR_EN

P3V3S4SW_SNS_EN

=PP3V3_S4SW_P3V3S4SWSNSFET

=P3V3SUS_EN

P3V3S0SW_SSD_EN

=PP5V_S0_HSIOFET

MIN_LINE_WIDTH=0.50MM

PP3V3_S4_FET_R

VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

PP3V3_S0SW_SSD_FET_R

PP3V3_S3_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S4SW_SNS_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

PP3V3_SUS_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP1V05_S0_PCHHSIOFET

=PP3V3_S4SW_SNS_FET

=PP5V_S0_P5VS0FET

=PP3V3_S4_FET

C8030

1

2

U8030

C1

C2

A2 B2

A1 B1

C8000

1

2

C8020

1

2

U8070

73

8

25

1

C8071

1

2

C8070

1

2

C8010

1

2

U8010

C1

C2

A2 B2

A1 B1

R8011

12 34

R8000

12 34

R8020

12 34

C8040

1

2

R8040

1

2

R8070

12

R8042

12

C8050

1

2

R8050

12

C8080

1

2

U8005

2 3

8

95

7

1

U8080

73

8

25

1

C8081

1

2

U8040

C1

C2

A2 B2

A1 B1

U8000

D1

D2

A2 B2 C2

A1 B1 C1

C8005

1

2

U8050

B1

B2

A2

A1

U8020

B1

B2

A2

A1

C8090

1

2

C8091

1

2

C8092

1

2

C8093

1

2

C8094

1

2

C8095

1

2

C8096

1

2

C8060

1

2

U8060

73

8

25

1

C8061

1

2

C8082

1

2

C8083

1

2

C8084

1

2

C8086

1

2

C8085

1

2

dvt1

051-1573

8.0.0

80 OF 120

63 OF 82

68

63 68

68

63 68

68

68 68

8

11 17

68

63 68

68

63 68

OUT

IN

NC

Q3

Q2

Q4

Q1

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

IN

OUT

NC

IN

OUT

IN

SYM_VER_2

GS

D

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Deep Sleep (S5AC)

Battery Off (G3Hot)

Run (S0)

X

CHGR VFRQ Generation

3.3V SUS Detect

No stuff C8131, 12ms Min delay time

U8130 Sense input threhold is 3.07V

(ISL version used for development)

376S0854

Vce(sat) 0.1V max @ 1mA Q1 Vth 0.7~1V @Id 250uA

S0 Rail PGOOD Circuitry

00

Deep Sleep (S4AC)

1

SMC_ADAPTER_EN

Standby Enables

1

0

1

VFRQ High: Variable Frequency

0

1

0

VFRQ Low: Fix Frequency

0

V4MON: 0.572V-0.630V

(IPU)

V3MON: 0.572V-0.630V

Thresholds:

Battery Off (G3HotAC)

Sleep (S3AC)

Deep Sleep (S4)

SSD Enable

5V Divider:

1.5V Divider:

1.05V Divider:

3.19V @ 4.5Vmin

0.718V @ 1.45Vmin

0.723V @ 1.02Vmin

353S2310

0

1

PM_SLP_S4_LPM_SLP_S5_L

11

PM_SUS_EN

1

11 1

0

1

0

00

0

1

0

1

0

1

0

1

0

toggle 3Hz

Sleep (S3)

SMC-->PM_DSW_PWRGD

SUS Enables

3.3V Divider: 1.07V

VDD: 2.734V-3.010V

5.0V Divider: 1.07V

V2MON: 2.815V-3.099V

0

9ms RC delay

1

0

00

S0 Rail PGOOD (BJT Version)

S5 Enables

1

so 1.05V can fall after 1.5V

5V needs to be held up

0

1

PM_SLP_S3_L

SMC_PM_G2_ENABLE

Vbe 0.7V max @ 2mA

S5_PWRGD-->SMC

S5 Power Good

S3 Enables

0

Deep Sleep (S5)

1.5V Codec Enable(BYPASSED NOW)

SMC_S4_WAKESRC_EN

Mobile System Power State Table

S0 Enables

State

5V S3 Enables

330K

201

1/20W

5% MF

54

10K

1/20W

5%

201

MF

16 17 38 64

1/20W

5%

201

MF

100

5%

201

MF

1/20W

100

1/20W

5%

201

MF

330

S0PGOOD_ISL

59

1/20W

1%

201

MF

150K

6.3V

10%

0201

CERM-X5R

0.1UF

S0PGOOD_ISL

1/20W

1%

201

MF

54.9K

1/20W

1%

201

MF

15K

DFN2015H4-8

ASMCC0179

CRITICAL

1/20W

5%

201

MF

1K

1/20W

5%

201

MF

1K

16V

10%

0201

X7R-1

NO STUFF

1000PF

1/20W

5%

201

MF

100K

CERM-X5R

10%

6.3V 0201

0.1UF

BYPASS=U8130.6::2.3mm

13 75

TDFN

ISL88042IRTEZ

CRITICAL

S0PGOOD_ISL

1/20W

1%

201

MF

15K

S0PGOOD_ISL

1/20W

1%

201

MF

15K

S0PGOOD_ISL

1/20W

1%

201

MF

15K

S0PGOOD_ISL

1/20W

1%

201

MF

15K

S0PGOOD_ISL

1/20W

1%

201

MF

6.04K

S0PGOOD_ISL

1/20W

1%

201

MF

6.04K

S0PGOOD_ISL

13

63

1/20W

5%

201

MF

1K

5%

0201

MF

0

1/20W

SOT891

74LVC1G32

NOSTUFF

13 38

6.3V

10%

0201

BYPASS=U8170.6::2.3mm

CERM-X5R

NOSTUFF

0.1UF

38 39

28

63

57

DFN1006H4-3

DMN32D2LFB4

1/20W

5%

201

MF

100

38

1/20W

5%

201

MF

100K

PLACE_NEAR=U7501.20:7mm

38 39

1/20W

5%

201

MF

100

PLACE_NEAR=U7501.21:7mm

58

13 18 31 37 38 64 66

10V

20%

402

CERM

0.1UF

PLACE_NEAR=U7400.16:6mm PLACE_NEAR=U8010.C2:6mm

6.3V

10%

402

CERM-X5R

0.47UF

NO STUFF

201

PLACE_NEAR=U7400.16:6mm

1/20W

5% MF

20K

1/20W

5%

0201

MF

0

PLACE_NEAR=U8010.C2:6mm

CERM-X5R 402

10%

6.3V

NO STUFF

PLACE_NEAR=U4600.4:6mm

0.47UF

57

63

35

42

1/20W

1%

201

MF

15K

1/20W

1%

201

MF

7.15K

13 17 18 38 66 71

100

MF

201

5%

1/20W

28 29

SC70-HF

MC74VHC1G08

MF 201

330K

5% 1/20W

NOSTUFF

402

CERM

10% 10V

NO STUFF

0.22UF

PLACE_NEAR=U7600.16:6mm

NO STUFF

MF

5%

1/20W

201

820

5%

0

PLACE_NEAR=U7600.16:6mm

0201

MF

1/20W

PLACE_NEAR=U8030.C2:6mm

0.1UF

20%

402

CERM

10V

201

MF

PLACE_NEAR=U8030.C2:6mm

39K

1/20W

5%

402

PLACE_NEAR=U8080.2:6mm

CERM

20%

0.1UF

10V

47K

PLACE_NEAR=U8080.2:6mm

MF

5% 1/20W

201

59

61

63

63 15 32

63

PLACE_NEAR=U8040.C2:7mm

25V

10%

402

X5R

0.1UF

NOSTUFF

1/20W

201

MF

1K

NOSTUFF

1%

1/20W

1%

201

MF

100K

NOSTUFF

PLACE_NEAR=U8040.C2:7mm

13

0201

0.1UF

BYPASS=U8180.6::3mm

10% CERM-X5R

6.3V

QFN

TPS3808G33

CRITICAL

PLACE_NEAR=U7501.4:15mm

SM-201

RB521ZS-30

NO STUFF

1/20W

5%

201

MF

240

PLACE_NEAR=U7501.4:15mm

NO STUFF

MF

1/20W

5%

0

PLACE_NEAR=U7501.4:15mm

0201

402

PLACE_NEAR=U7501.4:15mm

X5R

10%

6.3V

2.2UF

NO STUFF

6.3V

10%

402

CERM-X5R

NOSTUFF

PLACE_NEAR=U7501.21:7mm

0.47UF

RB521ZS-30

PLACE_NEAR=U7600.16:6mm

NO STUFF

SM-201

RB521ZS-30

NOSTUFF

PLACE_NEAR=U8040.C2:7mm

63

1/20W

5%

0201

MF

0

25V

10%

402

X5R

0.1UF

NO STUFF

201

MF

100

5% 1/20W

PLACE_NEAR=U4600.4:6mm

58

1/20W

5%

0201

MF

0

1/20W

5% MF

100

201

58

10V

10%

402

X5R

1UF

5%

201

MF

1/20W

100

29

PLACE_NEAR=U8030.C2:6mm

201

MF

1/20W

330

5%

RB521ZS-30

SM-201

PLACE_NEAR=U8030.C2:6mm

68K

1/20W 201

5% MF

PLACE_NEAR=U7870.2:6mm

0.1UF

20%

PLACE_NEAR=U7870.2:6mm

402

CERM

10V

RB521ZS-30

SM-201

PLACE_NEAR=U7870.2:6mm

5%

PLACE_NEAR=U7870.2:6mm

201

MF

330

1/20W

5%

201

MF

100

61

6.3V

10%

402

CERM-X5R

0.47UF

NO STUFF

61

1/20W

5%

0201

MF

0

PLACE_NEAR=U7820.2:6mm

SM-201

RB521ZS-30

PLACE_NEAR=U8080.2:6mm

330

MF 201

1/20W

5%

PLACE_NEAR=U8080.2:6mm

RB521ZS-30

PLACE_NEAR=U8060.2:6mm

SM-201

1/20W

PLACE_NEAR=U8060.2:6mm

5%

201

MF

330

PLACE_NEAR=U8060.2:6mm

MF

1/20W 201

1%

120K

PLACE_NEAR=U8060.2:6mm

10% CERM-X5R

6.3V 402

0.47UF

63

SYNC_DATE=11/06/2013

SYNC_MASTER=AHARTMAN_J52

Power Control

BOM_COST_GROUP=CPU SUPPORT

ALL_SYS_PWRGD_R

=P5VS4_EN

PM_SLP_S4_L

=USB_PWR_EN

MAKE_BASE=TRUE

P1V5S0_EN

MAKE_BASE=TRUE

P5VS0_EN

=P1V5S0_EN

PM_SLP_S3_BUF_L

MAKE_BASE=TRUE

P1V8S3_EN

P1V05S0_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

MAKE_BASE=TRUE

P3V3SUS_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

SSD_PWR_EN

MAKE_BASE=TRUE

S5_PWR_EN

S0PGD_BJT_GND_R

MIN_NECK_WIDTH=0.116 mm MIN_LINE_WIDTH=0.116 mm

MAX_LINE_WIDTH=0.116 mm

=PP3V3_S5_PWRCTL

P1V5S0_EN_D

=PP3V3_SUS_PWRCTL

=PP3V42_G3H_PWRCTL

=TBT_S0_EN

PM_SLP_S3_L

P1V05_EN_D

P1V5CODEC_EN_D

AUD_PWR_EN

P1V5S0SW_AUDIO_EN

PM_SLP_S3_BUF_L

P5VS3_EN_RC

=PP3V3_S0_VMON

=TBTBPWRSW_EN

=TBTAPWRSW_EN

=P3V3S4_EN

PM_SLP_S3_R_L

PM_RSMRST_L

=DDRREG_EN

=P3V3S3_EN

PM_SLP_S4_L

=PP3V42_G3H_PWRCTL

P5VS5_EN

P3V3S5_EN

=PP1V5_S0_VMON

VMON_Q3_BASE

TP_SUS_PGOOD_MR_L

=PP5V_S0_VMON

DCINVSENSE_EN

ALL_SYS_PWRGD

S0PGD_C

P1V05_DIV_VMON

P5V_DIV_VMON P1V5_DIV_VMON

=PP5V_S0_VMON

CHGR_VFRQ

=PP1V05_S0_VMON

=PP1V5_S0_VMON

P3V3S5_PGOOD

SUS_PGOOD_CT

=P3V3SUS_EN

P3V3S0SW_SSD_EN

=PP3V3_S5_VMON

=PP3V3_S5_PWRCTL

VMON_5V_DIV

=PP3V3_SUS_PWRCTL

=PP3V3_S0_VMON

SMC_S4_WAKESRC_EN

PM_SLP_S5_L

P1V05S0_PGOOD

DDRREG_PGOOD

VMON_Q4_BASE

P1V5S0_PGOOD

P5VS3_PGOOD

P1V8S3_PGOOD

=P1V8S3_EN

VMON_3V3_DIV

=P5VS0_EN

=P3V3S0_EN

=P1V05S0_EN

ALL_SYS_PWRGD

VMON_Q2_BASE

S5_PWRGD

MAKE_BASE=TRUE

P3V3S0_EN_D

PM_SLP_S3_R_L

DDRREG_EN

MAKE_BASE=TRUE

P3V3S0_EN

MAKE_BASE=TRUE

USB_PWR_EN

MAKE_BASE=TRUE

P5VS4_EN_D

MAKE_BASE=TRUE

S4_PWR_EN

P5VS4_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

P5VS3_EN_D

P5VS3_EN

P5VS0_EN_D

R8131

1

2

R8167

1

2

R8157

1

2

R8164

12

R8162

12

R8156

1

2

C8160

1

2

R8151

1

2

R8152

1

2

Q8150

5

7

1

6

4

8

2

3

R8154

12

R8155

12

C8131

1

2

R8133

1

2

C8130

1

2

U8160

4

1

8

9

3 5 6

2

7

R8173

1

2

R8171

1

2

R8161

1

2

R8170

1

2

R8172

1

2

R8160

1

2

R8153

12

R8115

12

U8170

2

1

3

6

4

C8170

1

2

Q8131

3

1

2

R8168

12

R8141

1

2

R8140

12

C8111

1

2

C8112

1

2

R8111

1

2

R8112

1

2

C8114

1

2

R8158

1

2

R8159

1

2

R8178

12

U8180

3

2

1

4

5

R8180

1

2

C8185

1

2

R8138

12

R8185

1

2

C8186

1

2

R8186

1

2

C8187

1

2

R8187

1

2

C8146

1

2

R8146

12

R8145

12

C8180

1

2

U8130

3

5

4

62

7

1

D8175

A

K

R8176

12

R8175

1

2

C8175

1

2

C8142

1

2

D8185

A

K

D8146

AK

R8190

1

2

C8190

1

2

R8117

1

2

R8179

12

R8165

12

C8159

1

2

R8169

12

R8184

1

2

D8184

AK

R8188

1

2

C8188

1

2

D8183

AK

R8183

1

2

R8166

12

C8110

1

2

R8110

1

2

D8189

AK

R8189

1

2

D8191

AK

R8191

1

2

R8192

1

2

C8192

1

2

dvt1

8.0.0

81 OF 120

051-1573

64 OF 82

5

48 64

64 68

48 64

64 68

64

13 18 31 37 38 64 66

64 68

69

64 68

16 17 38 64

64 68

68

64 68

58

68

64 68

18

64 68

IN

BI

NC

OUT

VCC

GND

A B

Y

YA

B

C

VCC

GND

SYM_VER-2

VIN

ON

GND

VOUT

GND

VDD

D

SON

CAP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Short Rsense

518S0829

LCD PANEL INTERFACE (eDP)

SLG5AP1443V

TPS22904

R(on)

75 mOhm Typ

Type

PANEL USES EDP_PANEL_PWR_PSR_EN TO DISCHARGE THE LCD BEFORE POWER GOES AWAY

3.3V TCON Switch

Load Switch

EDP: 1 A

EDP: 1.02A

19 mOhm Max

17 mOhm Typ

0.5A Max

U8300

Type

2.5A

Current

PANEL COMPATIBILITY

Y = B

Part

NEEDS TO BE LEVEL SHIFTED TO 3.3V

R(on)

U8310

Load Switch

Part

95 mOhm Max

@ 2.5V

Current

LCD_HPD_CONN IS A 2.5V SIGNAL

S0 Enables

LCD Panel AUX strapping

10% 16V

0201

X5R-CERM

0.1UF

0805

CRITICAL

FERR-220-OHM

100K

MF-LF

5%

1/16W

402

X5R-CERM

0.1UF

10% 16V

0201

16V

0402

10%

X7R-CERM

0.1UF

0402

10% 16V

0.1UF

X7R-CERM

X5R

20%

10UF

603

6.3V

GND_VOID=TRUE

0.1UF

X5R-CERM

10%

16V

0201

16V 10% X5R-CERM

0.1UF

GND_VOID=TRUE

5

77

5

77

GND_VOID=TRUE

0201

16V

0.1UF

10% X5R-CERM

X5R-CERM

GND_VOID=TRUE

10%

0.1UF

16V

0201

5

77

5

77

GND_VOID=TRUE

0201

X5R-CERM

10%

16V

0.1UF

GND_VOID=TRUE

10%

0201

0.1UF

16V X5R-CERM

5

77

5

77

GND_VOID=TRUE

X5R-CERM

0.1UF

0201

10%

16V

0201

GND_VOID=TRUE

0.1UF

10%

16V X5R-CERM

5

77

5

77

0.1UF

10% X5R-CERM

16V

0201

X5R-CERM

10% 16V

0201

0.1UF

5

77

5

77

TRUE TRUE

TRUE

CRITICAL

20525-130E-01

F-RT-SM

TRUE

TRUE TRUE

TRUE

13

NO_XNET_CONNECTION=TRUE

NOSTUFF

1M

MF 201

5% 1/20W

1M

MF 201

1/20W

5%

NOSTUFF

NO_XNET_CONNECTION=TRUE

201

5%

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1M

MF

1/20W

NOSTUFF

1M

MF

201

5%

1/20W

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

NOSTUFF

1M

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

NOSTUFF

1M

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

NOSTUFF

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

1M

NOSTUFF

1M

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

NOSTUFF

1M

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

TRUE

GND_VOID=TRUE

MF

201

5%

1/20W

1M

NOSTUFF

NO_XNET_CONNECTION=TRUE

1000PF

X7R-CERM

100V

10%

0603

X7R-CERM

0603

1000PF

100V

10%

44 80

SOT833

74LVC2G32GT

NO STUFF

0

MF5%

1/20W

0201

0

5%

1/20W

MF

NO STUFF

NOSTUFF

0.1UF

CERM-X5R

0201

10%

6.3V

BYPASS=U8330.8::3MM

74AUP1T97

SOT891

PANEL:OLD

0.1UF

X5R-CERM 0201

10% 16V

BYPASS=U8340.5::3MM

1/16W

100K

402

5%

MF-LF

1/16W

100K

5%

402

10V

10%

201

X7R

4700PF

CERM 402

1UF

10%

6.3V

201

MF

1/20W

1%

11K

EDP_LS_CAP

0201 25V

NP0-C0G

5%

12PF

0201 25V

NP0-C0G

5%

12PF

EDP_LS_CAP

0201 25V

NP0-C0G

5%

12PF

EDP_LS_CAP

0201 25V

NP0-C0G

5%

12PF

EDP_LS_CAP

0201 25V

5%

12PF

NP0-C0G

0201 25V

5%

12PF

EDP_LS_CAP

NP0-C0G

0201

EDP_LS_CAP

25V

NP0-C0G

5%

12PF

0201

EDP_LS_CAP

25V

NP0-C0G

5%

12PF

0201 25V

5% NP0-C0G

EDP_LS_CAP

12PF 12PF

5% NP0-C0G

25V

0201

EDP_LS_CAP

0612-SHORT

OMIT

MF

1 W

0

BYPASS=J8300.5::5MM

0201

0.1UF

6.3V

10% CERM-X5R

OMIT_TABLE

1/20W

5%

10K

201

MF

0201

5%

1/20W

PANEL:NEW

0

6.3V

20% X5R

1.0UF

0201-1

MF

201

1/20W

1%

24.9K

1UF

402

6.3V

10% CERM

GND_VOID=TRUE

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

GND_VOID=TRUE

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

GND_VOID=TRUE

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

GND_VOID=TRUE

TPS22904

CSP

CRITICAL

SLG5AP1443V

CRITICAL

TDFN

PLACE_NEAR=U8310.B1:6mm

RB521ZS-30

SM-201

PLACE_NEAR=U8300.2:6mm

SM-201

RB521ZS-30

PLACE_NEAR=D8323.A:2mm

201

MF

1/20W

1%

3.01K

4.32K

PLACE_NEAR=D8322.K:2mm

1/20W MF 201

1%

12PF

5%

25V

NP0-C0G 0201

PLACE_NEAR=J8300.28:5mm

5%

12PF

NP0-C0G 0201 25V

PLACE_NEAR=J8300.29:5mm

PLACE_NEAR=J8300.30:5mm

0201 25V

NP0-C0G

5%

12PF

PLACE_NEAR=J8300.1:5mm

0402

12PF

100V CERM

5%

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

CRITICAL

PANEL:NEW

117S0201

1

R8342

RES,MF,1/20W,10K OHM,5,0201,SMD

PANEL:OLD

CRITICAL117S0007

1

R8342

BOM_COST_GROUP=DISPLAY

SYNC_MASTER=GKOO_J52

eDP Display Connector

SYNC_DATE=05/04/2014

EDP_PANEL_PWR_OR_PSR_EN_D2

DP_INT_ML_N<1>

DP_INT_ML_F_N<3>

EDP_PANEL_PWR_OR_PSR_EN_D1

EDP_PANEL_PWR_OR_PSR_EN

PPVOUT_S0_LCDBKLT

DP_INT_ML_N<3>

DP_INT_ML_N<2>

DP_INT_ML_P<1>

DP_INT_ML_N<0>

DP_INT_ML_P<0>

EDP_BKLT_PWM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5VR3V3_SW_LCD

MIN_NECK_WIDTH=0.25 mm

=I2C_TCON_SDA

I2C_BKLT_SCL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PP3V3_S0_EDP_R

I2C_BKLT_SDA

=I2C_TCON_SCL

EDP_PANEL_PWR_EN_RC

DP_INT_ML_C_P<0>

DP_INT_ML_F_N<0>

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V

PP3V3_S0_EDP_SW

MIN_NECK_WIDTH=0.20MM

PP5V_S0_LCD_FETCAP

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=5V

DP_INT_ML_C_P<2>

DP_INT_AUX_N

EDP_PANEL_PWR_OR_PSR_EN

DP_INT_AUX_P

=PP3V3_S0_LCD

LCD_PSR_EN

=PP3V3_S0_PCH_GPIO

DP_INT_ML_N<3>

DP_INT_ML_P<3>

DP_INT_ML_P<2>

DP_INT_ML_N<2>

DP_INT_ML_C_N<0>

DP_INT_ML_P<0>

DP_INT_ML_P<1>

DP_INT_ML_N<0>

DP_INT_ML_N<1>

DP_INT_AUXCH_C_P

DP_INT_ML_F_P<3>

EDP_BKLT_EN

EDP_PANEL_PWR

DP_INT_ML_F_N<1>

DP_INT_ML_F_N<2>

DP_INT_HPD

=PP3V3_S0_EDP

DP_INT_ML_C_N<1>

PP3V3_S0_EDP_SW

EDP_TCON_PWR_EN_RC

DP_INT_ML_F_P<0>

DP_INT_ML_F_P<1>

DP_INT_ML_F_P<2>

PP5VR3V3_SW_LCD

DP_INT_ML_C_P<1>

EDP_BKLT_PSR_EN

DP_INT_AUXCH_C_N

DP_INT_ML_P<2>

ISNS_LCDPANEL_N ISNS_LCDPANEL_P

DP_INT_ML_C_N<2>

MIN_LINE_WIDTH=0.5 mm

PP5VR3V3_SW_LCD_ISNS

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

DP_INT_ML_P<3>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

LCD_IRQ_L

LCD_HPD_CONN

DP_INT_AUX_P DP_INT_AUX_N

=PP5V_S0_LCD

C8301

1

2

L8300

12

R8310

1

2

C8302

1

2

C8309

1

2

C8311

1

2

C8312

1

2

C8321

12

C8320

12

C8323

12

C8322

12

C8325

12

C8324

12

C8327

12

C8326

12

C8329

12

C8328

12

J8300

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

31

32

33 34 35 36 37 38 39

4

40 41

5 6 7 8 9

R8302

1

2

R8303

1

2

R8313

12

R8314

12

R8315

12

R8316

12

R8312

12

R8317

12

R8318

12

R8311

12

C8300

1

2

C8303

1

2

U8330

5

1

6

2

48

3

7

R8330

12

R8331

12

C8330

1

2

U8340

2

3

1

6

5

4

C8340

1

2

R8309

1

2

R8340

1

2

C8310

1

2

C8319

1

2

R8319

12

C8350

1

2

C8351

1

2

C8352

1

2

C8353

1

2

C8354

1

2

C8355

1

2

C8356

1

2

C8357

1

2

C8358

1

2

C8359

1

2

R8320

12 34

C8304

1

2

R8342

12

R8341

12

C8308

1

2

R8321

12

C8318

1

2

FL8300

1

23

4

FL8301

1

23

4

FL8302

1

23

4

FL8303

1

23

4

U8310

B2

B1

A1

A2

U8300

73

8

25

1

D8322

AK

D8323

AK

R8323

1

2

R8322

1

2

C8306

1

2

C8307

1

2

C8313

1

2

C8305

1

2

051-1573

8.0.0

83 OF 120

65 OF 82

dvt1

65 71 77

77

65 71

60 71

65 71 77

13 71

65 71

41 71

69 71

41 71

77

15 41 65

65 71 77

65 71

65 71 77

68

15

12 13 15 18 26 68

65 71 77

77

13

77

68

15 41 65

77

65 71

60

65 71 77

15 71

71

65 71 77

68

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

BI

OUT

IN

OUT

BI

OUT

IN

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

TP

SYM_VER-1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RIO Power Connector

MAKE BASE

516S1059

518S0882

MAKE BASE FOR I2C IS ON I2C PAGE

RIO FLEX CONNECTOR

NOTE: This connector is shielded 70P Hirose Plug APN 516S1059, mates with APN 516S1058.

(USB3_EXTB_R2D caps on RIO)

14 71 81

12 71 81

14 66 71 81

12 71 81

66 71 81

14 66 71 81

66 81

14 71 74

67 71 77

14 74

67

31 74

41

18

66 81

PLACE_NEAR=J9500.2:2.5MM

0201

X5R-CERM

16V

10%

0.1UF

PLACE_NEAR=J9500.1:2.5MM

0.1UF

16V

10%

0201

X5R-CERM

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=J9510.39:2.54MM

66

14 66 71 81

14 74

14 71 74

66 67

14 71 74

66

66 71 81

12

66

15

16

13 18 31 37 38 64

13 17 18 38 64 71

66 71 81

66 31 75

66

40

38

M-RT-SM

504050-0491

66 67

300K

MF

1/20W

5%

201

CRITICAL

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

DF40BG-70DP-0.4V

M-ST-SM

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

BEAD-PROBE

SM SM

BEAD-PROBE

SM

BEAD-PROBE BEAD-PROBE

SM

BEAD-PROBE

SM SM

BEAD-PROBE

SM

BEAD-PROBE

SM

BEAD-PROBE

10% 16V

X5R-CERM

0201

GND_VOID=True

0.1UF

PLACE_NEAR=J9510.2:2.54MM

PLACE_NEAR=J9510.4:2.54MM

0201

10% 16V

X5R-CERM

0.1UF

GND_VOID=True

CRITICAL

PLACE_NEAR=J9510.1:2.54MM

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

PLACE_NEAR=J9500:2.5MM

5% 25V

0201

12PF

NP0-C0G

PLACE_NEAR=J9500:2.5MM

25V

12PF

5%

0201

NP0-C0G

PLACE_NEAR=J9500:2.5MM

12PF

25V 0201

5% NP0-C0G

PLACE_NEAR=J9500:2.5MM

5%

12PF

25V 0201

NP0-C0G

12PF

5%

0201

NP0-C0G

25V

BOM_COST_GROUP=IO PORTS

SYNC_MASTER=GKOO_J52 SYNC_DATE=05/01/2014

RIO Connector

=PP5V_S3_RIO

HDMI_IG_DATA_C_P<2>

TRUE

HDMI_IG_DATA_C_N<2>

TRUE

HDMI_IG_CLK_C_P

TRUE

=PP1V5_S0_CONN

I2C_HDMIRDRV_SCL_CONN I2C_HDMIRDRV_SDA_CONN

=HDMI_DATA_C_P<2>

USB_EXTB_N

USB3_EXTB_D2R_N

I2C_X29THMSNS_SDA_CONN

I2C_X29THMSNS_SCL_CONN

HDMI_DDC_LS_DATA

AP_RESET_L

USB_EXTB_OC_L

PM_SLP_S3_L

=PP5V_S3_RIO

AP_PCIE_WAKE_L

TRUE

USB3RPCIE_SD_R2D_C_P

TRUE

USB3RPCIE_SD_R2D_C_N

TRUE

USB3RPCIE_SD_D2R_N

USB3RPCIE_SD_D2R_P

TRUE

SDCONN_STATE_CHANGE_RIO

TRUE

HDMI_IG_DDC_DATA

TRUE

HDMI_IG_DDC_CLK

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

USB_BT_CONN_N

TRUE

USB_BT_CONN_P

TRUE

HDMI_IG_DATA_C_P<0>

TRUE

HDMI_IG_DATA_C_N<1>

TRUE

HDMI_IG_CLK_C_N

TRUE

HDMI_IG_DATA_C_N<0>

HDMI_IG_DATA_C_P<1>

TRUE

=HDMI_DATA_C_N<0>

PCIE_CLK100M_AP_P

PCIE_AP_R2D_C_P

PCIE_AP_R2D_P

PCIE_AP_R2D_N

PCIE_AP_D2R_P

PCIE_CLK100M_AP_CONN_P

PCIE_CLK100M_AP_CONN_N

I2C_HDMIRDRV_SCL_CONN

PCIE_AP_R2D_P

SD_RESET_L

PM_SLP_S4_L

PCIE_AP_R2D_N

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_N USB3_SD_D2R_P

WIFI_EVENT_L SD_PWR_EN SDCONN_STATE_CHANGE_SAK_L

HDMI_DDC_LS_CLK

PM_WLAN_EN

=HDMI_DATA_C_P<1>

HDMI_HPD

USB3_EXTB_R2D_C_N

USB_EXTB_P

=HDMI_DATA_C_N<0>

PCIE_AP_D2R_N

HDMI_HPD

=PCIE_WAKE_L

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_P

SDCONN_STATE_CHANGE_SAK_L

USB3_SD_D2R_N

I2C_X29THMSNS_SDA_CONN

I2C_X29THMSNS_SCL_CONN

HDMI_DDC_LS_DATA

HDMI_DDC_LS_CLK

I2C_HDMIRDRV_SDA_CONN

=PCIE_CLK100M_AP_N

=PCIE_CLK100M_AP_P

=I2C_X29THMSNS_SDA

=I2C_X29THMSNS_SCL

=I2C_HDMIRDRV_SDA

=I2C_HDMIRDRV_SCL

=USB_BT_N

=USB_BT_P

=HDMI_CLK_C_LS_N

=HDMI_CLK_C_LS_P

=HDMI_DATA_C_P<0>

=HDMI_DATA_C_P<1> =HDMI_DATA_C_N<1>

=HDMI_DATA_C_N<2>

=HDMI_DATA_C_P<2>

=HDMI_CLK_C_LS_N =HDMI_CLK_C_LS_P

AP_CLKREQ_L

=PCIE_WAKE_L

=HDMI_DATA_C_N<2>

=USB_BT_P

USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_P

=USB_BT_N

PCIE_AP_D2R_N PCIE_AP_D2R_P

=PCIE_CLK100M_AP_P =PCIE_CLK100M_AP_N

=HDMI_DATA_C_N<1>

=HDMI_DATA_C_P<0>

=PP1V5_S0_RDRVR

PCIE_CLK100M_AP_N

=PP3V3_S4_RIO

PCIE_AP_R2D_C_N

=PP3V3_S4_RIO

C9591

1

2

C9592

1

2

C9593

1

2

J9500

5

6

1

2

3

4

R9530

1

2

J9510

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71

72

73 74

8

9

BP9500

1

BP9501

1

BP9502

1

BP9503

1

BP9504

1

BP9505

1

BP9506

1

BP9507

1

C9533

12

C9532

12

L9501

1

23

4

C9500

1

2

C9501

1

2

C9503

1

2

C9502

1

2

C9504

1

2

dvt1

051-1573

8.0.0

95 OF 120

66 OF 82

66 68

66

66 68

66

68

66 68

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

OUT

BI

OUT

BI

IN

NC NC

OUT

BI

SYM_VER_2

GS

D

THRM_PAD

VDD

GPIO(3)

GPI(2)

GPIO(4)

GPIO(6)

GPIO(5)

GPIO(12) GPIO(11)

GPIO(9)

GPIO(10)

GND

GPIO(8)

NC

THRM

IO_3

IO_2

IO_4

VDD

IO_8

IO_7

IO_6

GND

PAD

SYM_VER_2

GS

D

DDCDAT_B

DDCDAT_A

DDCDAT_C

DDCCLK_B

DDCCLK_A

DDCCLK_C

HPDB

HPDA

HPDC

DX_SEL

AUX_SEL

DB3(P)

DA3(P)

DC3(P)

DB3(N)

DA3(N)

DC3(N)

DB2(P)

DA2(P)

DC2(P)

DB2(N)

DA2(N)

DC2(N)

DB1(P)

DA1(P)

DC1(P)

DB1(N)

DA1(N)

DC1(N)

DB0(P)

DA0(P)

DC0(P)

DB0(N)

DA0(N)

DC0(N)

AUXB(P)

AUXA(P)

AUXC(P)

AUXB(N)

AUXA(N)

AUXC(N)

VDDOEVDD

GND

BI

OUT

BI

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: HDMI ML SWIZZLED INTENTIONALLY AS PER TABLE 9-1 HASWELL-ULT PDG

TOWARDS PORTS

TOWARDS CPU

AUX_SEL Vdd/2 = AUX & DDC

AUX_SEL 1 = DDC ONLY

AUX_SEL 0 = AUX ONLY

PRIORITY 1 = DP WINS OVER HDMI

PRIORITY 0 = HDMI WINS OVER DP

DISP MUX SEL_L

SEL_L 0 = DP

DISPLAY MUX: DP OR HDMI

TOWARDS CPU

SEL 1 = DP

SEL 0 = HDMI

DISP MUX SEL

TOWARDS PORTS

DP 1:2 ANALOG DEMUX

SEL_L 1 = HDMI

SEL 1 = DP

SEL 0 = HDMI

DISP MUX SEL

X7R-CERM 0402

20% 10V

0.1UF

X6S-CERM

0201

20% 16V

0.1UF

TQFN

PI3USB102ZLE

CRITICAL

SIGNAL_MODEL=MOJO_MUX

NO STUFF

201

5%

10K

1/20W

NO STUFF

MF

69 77

67 69

69

69 77

10K

5% 1/20W MF 201

10K

MF

5% 1/20W

201

25 77

25 67

66 67

66 71 77

30 67

66 67

1/20W

5% MF

100K

201

DMN32D2LFB4

DFN1006H4-3

1/20W

100K

MF

5%

201

1/20W

5% MF

100K

NOSTUFF

201

1/20W

MF

5%

100K

201

NOSTUFF

TDFN

SLG46400V

CRITICAL

10%

0.1UF

6.3V 0201

CERM-X5R

0201

6.3V

0.1UF

10%

OMIT_TABLE

TDFN

SLG4APXXX

201

1/20W

5% MF

100K

DMN32D2LFB4

DFN1006H4-3

NO STUFF

MF

5%

1/20W

201

NO STUFF

100K

CRITICAL

HD3SS213ZQE

BGA

66 67

30 67

10V X7R-CERM 0402

20%

0.1UF

30 67

66 67

67 69

510K

5%

1/20W

MF

201

510K

1/20W

MF

5%

201

69 77

BOM_COST_GROUP=TBT

Display Mux: HDMI vs DP

SYNC_DATE=01/29/2013

SYNC_MASTER=SRAMAN_J44

U9700

CRITICAL

1

343S0666

IC, SAK,AP4179,DP MUX CTRLR,TDFN-8

DISP_MUX_SEL

HDMITBTMUX_FLAG_L

HDMI_HPD

=PP3V3_S4_DPMUX

DISP_MUX_EN

HDMITBTMUX_LATCH

DISP_MUX_PRIORITY

DP_TBTSNK1_HPD

=PP3V3_S0_DPMUX

DP_TBTSNK1_DDC_CLK

HDMI_IG_DDC_CLK

DISP_MUX_SEL_L

=PP3V3_S0_DPMUX

HDMITBTMUX_FLAG_L

HDMITBTMUX_LATCH

HDMI_HPD

DISP_MUX_SEL

DISP_MUX_EN

DP_TBTSNK1_HPD

=PP3V3_S0_DPMUX

DISP_MUX_EN

=PP3V3_S0_DPMUX

DISP_MUX_SEL

=PP3V3_S0_DPMUX

DP_HDMI_TBT_AUX_P

DP_TBTSNK1_AUXCH_C_P

DP_HDMI_TBT_ML_N<0>

DP_HDMI_TBT_ML_N<1>

DP_TBTSNK1_ML_C_N<1>

DP_HDMI_TBT_ML_P<1>

DP_TBTSNK1_ML_C_P<1>

HDMI_IG_DATA_C_P<1>

DP_TBTSNK1_ML_C_N<2>

DP_HDMI_TBT_ML_P<2>

HDMI_IG_CLK_C_P

DP_HDMI_TBT_ML_N<2>

DP_HDMI_TBT_ML_P<3>

DP_TBTSNK1_DDC_DATA

DP_HDMI_TBT_ML_P<0>

HDMI_IG_DATA_C_P<2>

HDMI_IG_DATA_C_N<0>

HDMI_HPD

=PP3V3_S0_DPMUX

DISP_MUX_PRIORITY

DISP_MUX_EN

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_HPD

HDMI_IG_DATA_C_N<2>

HDMI_IG_DATA_C_N<1>

DPMUX_AUX_DDC_SEL

=PP3V3_S0_DPMUX

DP_TBTSNK1_DDC_CLK

HDMI_IG_DDC_DATA

HDMI_IG_DDC_CLK

HDMI_IG_CLK_C_N

HDMI_IG_DATA_C_P<0>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<0>

DP_HDMI_TBT_ML_N<3>

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_AUX_DDC_SEL

DP_TBTSNK1_DDC_DATA

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<3>

DP_HDMI_TBT_AUX_N

DPMUX_HPD_OUT

=PP3V3_S0_DPMUX

DP_TBTSNK1_ML_C_N<0>

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA

HDMI_IG_DDC_DATA

DISP_MUX_SEL

DISP_MUX_EN_L

C9751

1

2

C9750

1

2

C9725

1

2

U9725

6

7

3

4

5

8

10

9

2

1

R9725

1

2

R9726

1

2

R9727

1

2

R9752

1

2

Q9700

3

1

2

R9753

1

2

R9701

1

2

R9702

1

2

U9775

7

2

10

11

12

3 4 5 6

8

9

13

1

C9775

1

2

C9700

1

2

U9700

5

2

3

4

6

7

8

9

1

R9754

1

2

Q9701

3

1

2

R9755

1

2

U9750

C2

J9

H9

J6

H6

H1

H2

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

D2

E1

E2

F1

F2

H8

H5

J3

J8

J5

J7

A1

B3C8G8H4H7

G2

J2

H3

J1

B7

A2

J4

R9703

1

2

R9704

1

2

dvt1

051-1573

8.0.0

97 OF 120

67 OF 82

67 69

15 67

66 67

68

67

67 69

67

25 67

67 68

15 67

67 69

66 67

67 69

67

25 67

67 68

67

67 68

67 69

67 68

67

67 68

67

67 68

67 69

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU "VCORE" RAILS

1.5V/1.2V/1.8V/1.05V RAILS

TBT RAILS (OFF WHEN NO CABLE)

3.3V Rails

? mA

1.84A

Digital Ground

"G3Hot" (Always-Present) Rails

5V Rails

SYNC_MASTER=SHART_J44

SYNC_DATE=01/14/2013

Power Aliases

=PP3V3_S4_CAMPWREN

=PP5V_S4_TPAD

=PP5V_S3_LTUSB

PP5V_S3

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.175 MM

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S4

=PP5V_S3_AUDIO

=PP5V_S3_REG

=PP3V3_S0_DPMUX

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.2 MM

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

=PP3V3_S0_PCH_VCCTS

=PP3V3_S0_SMBUS_SMC_0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.50MM

PP3V3_S0_FET

=PP3V3_SUS_ROM

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_FAN

=PP3V3_S0RTBTLC_PCH_GPIO

=PP1V5_S0SW_P1V5S0SWAUDIOFET

=PP1V5_S0_PCH_VCCTS

=PP1V5_S0_VMON

MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE

PP0V6_S0_DDRVTT

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0.6V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPBUS_S4_X239

VOLTAGE=12.9V

PPBUS_S5_HS_COMPUTING

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

VOLTAGE=3.3V

PPVIN_S4_TPAD

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_OTHER3V3

VOLTAGE=8.6V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.20MM

PP3V3_S3

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.8V

PP1V8_S3

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

PP1V2_S3_CPUDDR

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S4_TBT

MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.20MM

PP3V3_S4SW_SNS

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.20MM

PP15V_TBT

VOLTAGE=15V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.5 mm

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.25 mm

PP1V05_S0SW_PCH_HSIO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

PP3V3_S0SW_SSD_FET

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S0SW_SSD

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.675V MAKE_BASE=TRUE

PPVRTC_G3H

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM VOLTAGE=3V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

PP5V_S0_FET

MAKE_BASE=TRUE

VOLTAGE=5V

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_B

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V

PPBUS_S5_HS_OTHER5V

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S3_DDRREG

=PPVIN_S0SW_LCDBKLTFET =PPBUS_S0_VSENSE =PPVIN_SW_TBTBST

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PP3V3_S5_PWRCTL

=PP1V2_S3_CPUDDR_ISNS

=PP1V2_S3_MEM_VDDQ

=PP3V3_S0SW_SSD_ISNS

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S4_RIO

=PP3V3_S4_DPMUX

=PP3V3_S3_P1V8S3

=PP3V3_S5_CAMPWREN

=PP3V3_S5_WLAN

=PP3V3_S0_P1V5S0

=PP3V3_S5_XDPJTAGISOL

=PP3V3_S4_TBTAPWRSW

=PP3V3_S5_PCH_GPIO

=PP1V8_S3_MEM

=PP3V3_S4_BT

=PP3V3_S4_TBT_ISNS_R

=PPVIN_S5_SMCVREF

=PP3V42_G3H_ONEWIREPROT =PP3V42_G3H_SSDSAK

=PP3V3_S0_TBTTHMSNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_SMBUS_SMC_1

=PP3V3_S0_VMON

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_RSTBUF

=PPVIN_S5_HS_OTHER3V3_ISNS_R

=PPVIN_S5_HS_OTHER5V_ISNS_R

=PP3V3_S0_SMC

=PP1V05_S0_PCH_VCCIO_USB2

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S0_TPAD

=PP3V3_S0_SMBUS_SMC_3

=PP1V8_S3_REG

=PP1V5_S0_REG

=PP5V_S0_ISNS_R

PPVREF_S3_MEM_VREFCA

=PPVIN_S5_HS_OTHER5V_ISNS

=PP18V5_DCIN_ISOL

=PPDCIN_S5_CHGR

=PPDCIN_S5_VSENSE

=PP3V3_S0_CAMERA_R

=PP3V42_G3H_REG

=PPVIN_S5_HS_COMPUTING_ISNS

=PP1V05_S0_PCH_VCC

=PP3V42_G3H_SMBUS_SMC_5

=PP3V3_S4_P3V3S4FET =PP3V3_S5_DBGLEDS

=PP3V3_S4_TBTBPWRSW

=PP3V3_S0SW_SSD_ISNS_R

PP3V3_S0SW_SSD_FET_R

=PPVRTC_G3_OUT

=PP1V05_S0_XDP

=PP1V05_S0_SMC

=PPVIN_S0_1V05S0_LDO

=PP1V05_S0_PCH_VCCIO_HSIO

=PP1V05_S0_CPU_VCCST

=PP3V3_S0_VRISNS

=PPBUS_G3H

=PP15V_TBT_REG

=PPHV_S4SW_TBTBPWRSW

=PP3V3_S0_P3V3S0FET

=PP1V05_S0_REG

=PP1V05_S0SW_PCH_VCCPLL_HSIO

=PP1V05_S0SW_PCH_HSIO_FET

=PP1V05_S0SW_PCH_VCCHSIO

=PP1V05_S0_PCHHSIOFET

=PP1V05_S0_VMON

=PP1V05_S0_PCH_PLLFILTERS

=PP1V05_S0_PCH_VCCCLK

=PP1V05_S0M_PCH_VCCASW

PPVREF_S3_MEM_VREFCA

=PP3V3_S4SW_SNS_FET

=PP3V3_S4_HS_OTHER_ISNS =PP3V3_S4_ISNS

=PP18V5_DCIN_CONN

=PPVRTC_G3_PCH

=PP3V3_S4_TBT_ISNS

=PPVTT_S0_DDR_LDO

=PP0V6_S0_MEM_VTT_B

=PP0V6_S0_MEM_VTT_A

=PP3V3_S3_P3V3S3FET

=PP3V3_S0SW_P3V3S0SWSSDFET

=PPDDR_S3_REG

=PP3V3_S5_SMC

=PP3V3_S4_FET

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR

=PP3V3_S0_SNS_BMON

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S5_CSPWRGD

=PP3V3_SUS_P3V3SUSFET

=PPVDDIO_TBTLC_CLK

=PPVCC_S0_CPU

=PP1V5_S0_AUDIO

=PP1V05_SUS_PCH_JTAG

=PP1V5_S0_RDRVR

=PP3V3_S0SW_SSD

=PP1V2_S3_CPUDDR_ISNS_R

=PP1V2_S3_MEM_VDDCA =PP1V2_S3_MEM_VDD2

=PP3V3_S0_MEM_VTTPWRCTL

=PP3V3_S0_FET

PPVREF_S3_MEM_VREFDQ_A

=PP3V3_S0_ISNS_R

PPVREF_S3_MEM_VREFDQ_B

=PPVBAT_G3H_SYSCLK

=PP3V3_S0_LCD

=PP3V42_G3H_HALL

=PP3V3_S0_ISNS

=PP3V42_G3H_SMCUSBMUX

=PP3V3_S5_REG

=PP3V3_G3H_T112

=PP3V42_G3H_X239_COFET_EN

=PP1V05_SUS_LDO

=PP3V3_S3_PCH_GPIO =PP3V3_S3_SDBUF =PP3V3_S3RS4_PCH_GPIO =PP3V3_S3_SYSCLKGEN =PP3V3_S3_CAMERA_R =PP3V3_S3_TPAD

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP3V3_S3_FET

=PP3V3_S4_TPAD

=PP3V3_S3SW_SD_RESET

=PP3V3_SUS_PCH_GPIO

=PP3V3_S4_TBT

=PP1V2_S3_MEM_VTTPWRCTL

=PPVIN_S0_DDRREG_LDO

=PP3V3_S4SW_P3V3S4SWSNSFET

=PP3V3_S5_VMON

=PP3V3_S5_SYSCLK

=PPVCC_S0_CPU_REG

=PPVIN_S4_TPAD

=PPVIN_S0_CPUVR

=PP3V3_S4_SMC

=PPHV_S4SW_TBTAPWRSW

=PPBUS_X239_REG

=PPDCIN_S5_CHGR_ISOL

=PPVIN_S5_HS_OTHER3V3_ISNS

=PP3V3_SUS_FET

=PPVIN_X239

=PPVIN_X239_PBUS_ISNS

=PPVIN_X239_PBUS_ISNS_R

=PP3V3_SUS_PCH_VCCSUS_ICC

=PP3V3_SUS_P1V05SUSLDO

=PP3V42_G3H_CSPWRGD

=PP3V3_S0_OOB1_PWRDN

=PPVIN_S0_1V05S0

MIN_NECK_WIDTH=0.2 MM VOLTAGE=18.5V

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP3V42_G3H

MIN_LINE_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=8.6V

PPBUS_G3H

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S0_EDP

=PP3V3_S0_DDCMUX

=PP3V3_S0_AUDIO

=PP3V3_S0_SB_PM

=PP3V3R1V8_S0_PCH_VCCSDIO

=PP5V_S0_FAN =PP5V_S0_BKLT

=PP5V_S0_HSIOFET

=PP5V_S0_ALSCAM

=PP5V_S0SW_KBDLED

=PP5V_S0_CPUVR

=PP5V_S0_PCH_STRAP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S0

=PP5V_S0_LPCPLUS

=PP5V_S0_ISNS

=PP5V_S3_ALSCAM

=PP5V_S3_RIO

=PP5V_S0_1V05S0

=PP5V_S0_P5VS0FET

=PP5V_S0_AUDIO_AMP =PP5V_S0_LCD =PP5V_S0_FET

=PP5V_S5_LDO

=PP5V_S0_XDPJTAGISOL

=PP5V_S0_VMON

=PP5V_S3_DDRREG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP5V_S5

MIN_LINE_WIDTH=0.5 MM VOLTAGE=5V

=PP5V_S5_P5VS5FET

=PP5V_S5_FET

=PPVMEMIO_S0_CPU

=PPVTT_S3_DDR_BUF

=PPDDR_S3_MEMVREF

MIN_NECK_WIDTH=0.17 mm

PP1V2_S3

VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 mm

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PWRCTL

=PP3V3_S4_X239

=PP3V42_G3H_TPAD

=PP3V3_S4_SMBUS_SMC_2

VOLTAGE=3.3V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM

PP3V3_S4

MIN_LINE_WIDTH=0.20MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

PP3V3_SUS

GND

VOLTAGE=0V MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

dvt1

051-1573

8.0.0

100 OF 120

68 OF 82

18

36

35

71

48

58

67

71 80

8

11

71

47

48 49 52

8

11

46

15

63

8

64

71 76

18 25 26

71 80

71

20 21 76

76

71

27

71

71 76

20 21 76

22 23 76

57

60

42

27

42

64

43

20 21 22 23

43

8

11 14

66

67

61

31

61

16

28

13 15

20 21 22 23

31

44

39

53

32

45

44 45

12 13 15 18 26 65

41

64

18

42

39

8

11

8

11

37

41

61

43

19 68

42 58

53

54

42

44

53

42

8

11

41

63

18

29

43

63

17

16

39

59

8

6 8

15 16 17 55

43

53 54

27

29

63

59

11

63

8

11

63

64

11

8

11

8

11

19 68

63

42

42 43 44

53

8

12 13

44

57

24

63

43 57

38 39 40

63

64

54

44

42 43

17

63

17

8

10 44

49

16

66

32

43

20 21 22 23

17

63

19

43

19

17

65

40

43

35

58

47

61

15

18

15

18

44

8

11

63

36 37 71

15

14

25 26 27

17

57

63

64

17 18

56

36 71

55 56

18 39 40

28

62

54

42 58

63

62

42

8

61

17

32

59

71

65

30

48

17

8

11 40

46

60

63

34

60

55 56

17

71 43

34

66

59

63

69

65 63

58

16

64

57

71

63

8

10

57

19

76

8

11

64

62

36

41

71

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE_BASE

UNUSED SIGNALS

HDMI VS TBT

Digital Ground

EPD PANEL

TBT UNUSED NETS

SM

SYNC_MASTER=SHART_J44

SYNC_DATE=11/19/2012

Signal Aliases

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_AUXCH_CP

TP_AUD_CODEC_MICBIAS1_L TP_AUD_CODEC_MICBIAS1_R TP_AUD_CODEC_MICBIAS2_L

TP_USB_5P

TP_USB_5N

TP_TBT_XTAL25OUT

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<3>

TP_PCIE_FW_R2D_CP

TP_SPI_CS2_L

TP_AUD_CODEC_MICBIAS2_R

TP_SUS_PGOOD_MR_L

TP_TDM_ONEWIRE_MPM

TP_SMC_MD1

TP_SMC_TRST_L

=PP5V_S0_AUDIO_AMP

TP_PCIE_CLK100M_FWP

TP_PCIE_FW_R2D_CN

TP_USB_CAMERAN

TP_DP_TBTSRC_ML_CP<2> TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<1>

TP_TBT_PCIE_RESET0_L

TP_TBT_MONDC1

=TBT_GO2SX_BIDIR

DP_AUXCH_ISOL_L

=DP_TBTSNK1_DDC_DATA

DISP_MUX_SEL

TP_PCIE_FW_D2RN

TP_PCIE_FW_D2RP

TP_USB_CAMERAP

TP_CLINK_CLK

TP_CLINK_RESET_L

TP_CLINK_DATA

=DP_TBTSNK1_ML_C_P<1>

=DP_TBTSNK1_HPD

=DP_TBTSNK1_DDC_CLK

=I2C_BKLT_SDA

=DP_TBTSNK1_ML_C_N<0>

=DP_TBTSNK1_ML_C_N<1>

TP_USB_SDP

=DP_TBTSNK1_AUXCH_C_N

TP_DP_TBTSRC_ML_CP<0>

=DP_TBTSNK1_ML_C_N<3>

=DP_TBTSNK1_ML_C_P<3>

=DP_TBTSNK1_ML_C_N<2>

=DP_TBTSNK1_ML_C_P<2>

=DP_TBTSNK1_ML_C_P<0>

=DP_TBTSNK1_AUXCH_C_P

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM TP_PCH_I2S1_SCLK TP_PCH_SLP_WLAN_L

TP_SPI_CS1_L

TP_PCH_SLP_LAN_L

TP_DP_TBTSRC_ML_CN<1>

TP_PCIE_CLK100M_FWN

TP_TBT_MONDC0

TP_PCIE_CLK100M_ENETSDP TP_PCIE_CLK100M_ENETSDN

USB_IR_P USB_IR_N

TP_USB_SDN

TP_PCI_PME_L

TP_HDA_SDIN1

=I2C_BKLT_SCL

I2C_BKLT_SCL

TRUE

NC_PCIE_FW_D2RP

TRUE

NO_TEST=TRUE

NC_PCIE_FW_D2RN

TRUE

NO_TEST=TRUE

NC_DP_TBTSRC_ML_CP<3>

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN1

TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_ENETSDP

TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_ENETSDN

TRUE

NO_TEST=TRUE

NC_USB_CAMERAP

TRUE

NO_TEST=TRUE

NC_USB_SDP

TRUE

NO_TEST=TRUE

NC_USB_IRN

TRUE

NO_TEST=TRUE

NC_USB_CAMERAN

TRUE

NO_TEST=TRUE

NC_PCI_PME_L

TRUE

NO_TEST=TRUE

NC_TBT_MONDC0

MAKE_BASE=TRUE

TRUE

NC_USB_SDN

TRUE

NO_TEST=TRUE

NC_SUS_PGOOD_MR_L

TRUE

NO_TEST=TRUE

NC_AUD_CODEC_MICBIAS2_R

TRUE

NO_TEST=TRUE

NC_AUD_CODEC_MICBIAS1_R

TRUE

NO_TEST=TRUE

NC_TBT_MONDC1

MAKE_BASE=TRUE

TRUE

NC_TBT_XTAL25OUT

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_AUXCH_CP

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<0>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<2>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<2>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<3>

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET0_L

MAKE_BASE=TRUE

TRUE

DP_HDMI_TBT_ML_N<3>

TRUE

DP_HDMI_TBT_ML_P<3>

TRUE

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DP_HDMI_TBT_DDC_DATA

TRUE

PP5V_S0_AUDIO_AMP_L

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DP_HDMI_TBT_ML_P<2>

TRUE

DPMUX_HPD_OUT

TRUE

HDMITBTMUX_LATCH

MAKE_BASE=TRUE

HDMITBTMUX_SEL_TBT

MAKE_BASE=TRUE

I2C_BKLT_SDA

TRUE

NC_PCIE_CLK100M_FWP

TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_FWN

TRUE

NO_TEST=TRUE

NC_PCH_I2S1_SCLK

TRUE

NO_TEST=TRUE

DP_HDMI_TBT_DDC_CLK

TRUE

DP_HDMI_TBT_ML_P<1>

TRUE

DP_HDMI_TBT_ML_N<0>

TRUE

DP_HDMI_TBT_ML_P<0>

TRUE

DP_HDMI_TBT_ML_N<1>

TRUE

DP_HDMI_TBT_ML_N<2>

TRUE

DP_HDMI_TBT_AUX_N

TRUE

DP_HDMI_TBT_AUX_P

TRUE

NC_PCIE_FW_R2D_CP

TRUE

NO_TEST=TRUE

NC_TDM_ONEWIRE_MPM

TRUE

NO_TEST=TRUE

NC_DP_TBTSRC_ML_CP<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<0>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_AUXCH_CN

MAKE_BASE=TRUE

TRUE

NC_SMC_TRST_L

TRUE

NO_TEST=TRUE

NC_SMC_MD1

TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_CN

TRUE

NO_TEST=TRUE

NC_USB_IRP

TRUE

NO_TEST=TRUE

NC_USB_5N

TRUE

NO_TEST=TRUE

NC_AUD_CODEC_MICBIAS1_L

TRUE NO_TEST=TRUE

NC_AUD_CODEC_MICBIAS2_L

TRUE NO_TEST=TRUE

NC_CLINK_CLK

TRUE

NO_TEST=TRUE

NC_SPI_CS2_L

TRUE

NO_TEST=TRUE

NC_SPI_CS1_L

TRUE

NO_TEST=TRUE

NC_PCH_SLP_LAN_L

TRUE

NO_TEST=TRUE

NC_PCH_SLP_WLAN_L

TRUE

NO_TEST=TRUE

NC_ITPXDP_CLK100MN

TRUE

NO_TEST=TRUE

NC_CLINK_DATA

TRUE

NO_TEST=TRUE

NC_CLINK_RESET_L

TRUE

NO_TEST=TRUE

NC_ITPXDP_CLK100MP

TRUE

NO_TEST=TRUE

NC_PCH_I2S1_TXD

TRUE NO_TEST=TRUE

NC_PCH_I2S1_SFRM

TRUE

NO_TEST=TRUE

NC_USB_5P

TRUE

NO_TEST=TRUE

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

XWA202

12

XWA203

12

dvt1

051-1573

8.0.0

102 OF 120

69 OF 82

25

48

14

25

14

48

64

53

68

12

14

25

15

13

67

14

5

13

60

5

14

13

25

5

13

12

13

14

13

25

12

25

12

14

13

12

60 65 71

74

67 77

50

67

50

67 77

67

25

65 71

67

67 77

74

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE_BASE

UNUSED MEMORY SIGNALS

MAKE_BASE

LPDDR3 COMMAND/ADDRESS

Memory Bit/Byte Swizzle

SYNC_MASTER=AHARTMAN_J52

SYNC_DATE=10/29/2013

Memory Bit & Byte Swizzle

TRUE

TP_LPDDR3_RSVD4

TRUE

MEM_B_CAB<8>

TRUE

MEM_B_CAB<7>

TRUE

MEM_B_CAB<5>

TRUE

MEM_B_CAB<4>

TRUE

MEM_B_CAB<3>

MEM_B_CAB<2>

TRUE

MEM_B_CAB<1>

TRUE

MEM_B_CAB<0>

TRUE

MEM_B_CAA<9>

TRUE

MEM_B_ODT<0>

TRUE

MEM_B_CAA<5>

TRUE

MEM_B_CAA<4>

TRUE

MEM_A_CAB<9>

TRUE

MEM_A_CAB<8>

TRUE

MEM_A_CAB<7>

TRUE

MEM_A_CAB<6>

TRUE

MEM_A_CAB<5>

TRUE

MEM_A_CAB<4>

TRUE

MEM_A_CAB<3>

MEM_A_CAB<2>

TRUE

MEM_A_ODT<0>

TRUE

TP_LPDDR3_RSVD2

TRUE

MEM_B_CAA<0>

TRUE

MEM_B_CAA<2>

TRUE

TP_LPDDR3_RSVD3

TRUE

MEM_B_CAA<1>

MEM_B_CAA<7>

TRUE TRUE

MEM_B_CAA<8>

TRUE

MEM_B_CAA<6>

TRUE

MEM_B_CAA<3>

TRUE

MEM_A_CAA<9>

TRUE

MEM_A_CAA<2> MEM_A_CAA<3>

TRUE TRUE

MEM_A_CAA<4> MEM_A_CAA<5>

TRUE

MEM_A_CAA<7>

TRUE TRUE

MEM_A_CAA<8>

TRUE

MEM_A_CAA<1>

MEM_A_CAB<0>

TRUE

MEM_A_CAB<1>

TRUE

MEM_B_CAB<6>

TRUE

MEM_B_CAB<9>

TRUE

MEM_A_CAA<0>

MEM_A_CAA<6>

TRUE

MEM_B_DQ<0>

TRUETRUE

MEM_A_DQ<0>

MEM_B_DQS_P<0>

TRUE

MEM_B_DQS_N<0>

TRUE

MEM_B_DQS_P<1>

TRUE

MEM_B_DQS_N<1>

TRUE

MEM_B_DQS_P<2>

TRUE

MEM_B_DQS_N<2>

TRUE

MEM_B_DQS_P<3>

TRUE

MEM_B_DQS_N<3>

TRUE

MEM_B_DQS_N<4>

TRUE

MEM_B_DQS_P<4>

TRUE

MEM_B_DQS_P<5>

TRUE

MEM_B_DQS_N<5>

TRUE

MEM_B_DQS_P<6>

TRUE

MEM_B_DQS_N<6>

TRUE

MEM_B_DQS_P<7>

TRUE

MEM_B_DQS_N<7>

TRUE

MEM_A_DQS_P<0>

TRUE

MEM_A_DQS_N<0>

TRUE

MEM_A_DQS_P<1>

TRUE

MEM_A_DQS_P<2>

TRUE

MEM_A_DQS_N<1>

TRUE

MEM_A_DQS_P<3>

TRUE

MEM_A_DQS_N<2>

TRUE

MEM_A_DQS_N<4>

TRUE

MEM_A_DQS_P<4>

TRUE

MEM_A_DQS_N<3>

TRUE

MEM_A_DQS_P<7>

TRUE

MEM_A_DQS_N<5>

TRUE

MEM_A_DQS_P<5>

TRUE

MEM_A_DQS_P<6>

TRUE

MEM_A_DQS_N<7>

TRUE

MEM_A_DQS_N<6>

TRUE

TP_LPDDR3_RSVD1

TRUE

TP_CPU_MEM_RESET_L=MEM_RESET_L

MEM_A_DQ<15>

=MEM_A_DQ<13>

MEM_B_DQ<18>

MEM_B_DQ<21>

=MEM_B_A<3>

=MEM_B_ODT<0>

=MEM_B_A<0>

=MEM_B_A<1>

=MEM_B_A<10>

=MEM_B_BA<1>

=MEM_B_A<2>

=MEM_B_BA<0>

=MEM_B_RAS_L

=MEM_B_WE_L

=MEM_B_CAS_L

=MEM_B_A<13>

=MEM_A_A<0>

=MEM_A_A<1>

=MEM_A_A<10>

=MEM_A_BA<1>

=MEM_A_A<2>

=MEM_A_BA<0>

=MEM_A_RAS_L

=MEM_A_WE_L

=MEM_A_CAS_L

=MEM_B_A<4>

=MEM_B_A<15>

=MEM_B_A<12>

=MEM_B_A<7>

=MEM_B_A<8>

=MEM_B_A<9>

=MEM_B_A<11>

=MEM_B_BA<2>

=MEM_B_A<6>

=MEM_B_A<5>

=MEM_B_A<14>

=MEM_A_A<15>

=MEM_A_A<11>

=MEM_A_A<12>

=MEM_A_BA<2>

=MEM_A_A<7>

=MEM_A_A<8>

=MEM_A_A<6>

=MEM_A_A<9>

=MEM_A_A<4>

=MEM_A_A<5>

MEM_B_DQ<49>

MEM_B_DQ<51>

=MEM_A_A<3>

=MEM_A_ODT<0>

=MEM_A_A<13>

=MEM_A_A<14>

=MEM_B_DQ<7> =MEM_B_DQ<6>

MEM_B_DQ<1>

=MEM_B_DQ<5>

MEM_B_DQ<2>

=MEM_B_DQ<1>

MEM_B_DQ<3>

=MEM_B_DQ<3>

MEM_B_DQ<4>

=MEM_B_DQ<2>

MEM_B_DQ<5>

=MEM_B_DQ<0>

MEM_B_DQ<6>

=MEM_B_DQ<4>

MEM_B_DQ<7>

=MEM_B_DQ<10>

MEM_B_DQ<8>

=MEM_B_DQ<14>

MEM_B_DQ<9>

=MEM_B_DQ<8>MEM_B_DQ<10>

=MEM_A_DQ<7>

=MEM_A_DQ<5>

MEM_A_DQ<2>

=MEM_A_DQ<1>

MEM_A_DQ<3>

=MEM_A_DQ<6>

MEM_A_DQ<1>

=MEM_A_DQ<3>

MEM_A_DQ<4>

=MEM_A_DQ<2>

MEM_A_DQ<5>

=MEM_A_DQ<4>

MEM_A_DQ<7>

=MEM_A_DQ<0>

MEM_A_DQ<6>

=MEM_A_DQ<10>

MEM_A_DQ<8>

=MEM_A_DQ<8>MEM_A_DQ<10>

=MEM_A_DQ<14>

MEM_A_DQ<9>

=MEM_B_DQ<9>MEM_B_DQ<11> =MEM_B_DQ<15>

MEM_B_DQ<12>

=MEM_B_DQ<11>

MEM_B_DQ<13>

=MEM_B_DQ<12>

MEM_B_DQ<14>

=MEM_B_DQ<13>

MEM_B_DQ<15>

=MEM_B_DQ<22>

MEM_B_DQ<16>

=MEM_B_DQ<18>

MEM_B_DQ<17>

=MEM_B_DQ<17> =MEM_B_DQ<16>

MEM_B_DQ<19>

=MEM_B_DQ<23>

MEM_B_DQ<20>

=MEM_B_DQ<19> =MEM_B_DQ<20>

MEM_B_DQ<22>

=MEM_B_DQ<21>

MEM_B_DQ<23>

=MEM_B_DQ<27>

MEM_B_DQ<24>

=MEM_B_DQ<26>

MEM_B_DQ<25>

=MEM_B_DQ<24>

MEM_B_DQ<26>

=MEM_B_DQ<28>

MEM_B_DQ<27>

=MEM_B_DQ<31>

MEM_B_DQ<28>

=MEM_B_DQ<30>

MEM_B_DQ<29>

=MEM_B_DQ<29>

MEM_B_DQ<30>

=MEM_B_DQ<25>

MEM_B_DQ<31>

=MEM_B_DQ<38>

MEM_B_DQ<33>

=MEM_B_DQ<39>

MEM_B_DQ<32>

=MEM_B_DQ<37>

MEM_B_DQ<34>

=MEM_B_DQ<33>

MEM_B_DQ<35>

=MEM_B_DQ<35>

MEM_B_DQ<36>

=MEM_B_DQ<34>

MEM_B_DQ<37>

=MEM_B_DQ<32>

MEM_B_DQ<38>

=MEM_B_DQ<36>

MEM_B_DQ<39>

=MEM_B_DQ<42>

MEM_B_DQ<40>

=MEM_B_DQ<46>

MEM_B_DQ<41>

=MEM_B_DQ<40>

MEM_B_DQ<42>

=MEM_B_DQ<47>

MEM_B_DQ<44>

=MEM_B_DQ<41>

MEM_B_DQ<43>

=MEM_B_DQ<43>

MEM_B_DQ<45>

=MEM_B_DQ<44>

MEM_B_DQ<46>

=MEM_B_DQ<45>

MEM_B_DQ<47>

=MEM_B_DQ<53>

MEM_B_DQ<48>

=MEM_B_DQ<49>

MEM_B_DQ<50>

=MEM_B_DQ<51>

MEM_B_DQ<52>

=MEM_B_DQ<54>

=MEM_B_DQ<52>

MEM_B_DQ<53>

=MEM_B_DQ<48>

MEM_B_DQ<54>

=MEM_B_DQ<50>

MEM_B_DQ<55>

=MEM_B_DQ<62>

MEM_B_DQ<56>

=MEM_B_DQ<63>

MEM_B_DQ<57>

=MEM_B_DQ<57>

MEM_B_DQ<58>

=MEM_B_DQ<61>

MEM_B_DQ<60>

=MEM_B_DQ<60>

MEM_B_DQ<59>

=MEM_B_DQ<56>

MEM_B_DQ<61>

=MEM_B_DQ<58>

MEM_B_DQ<62>

=MEM_B_DQ<59>

MEM_B_DQ<63>

=MEM_A_DQ<9>MEM_A_DQ<11> =MEM_A_DQ<15>

MEM_A_DQ<12>

=MEM_A_DQ<11>

MEM_A_DQ<13>

=MEM_A_DQ<12>

MEM_A_DQ<14>

=MEM_A_DQ<16>

MEM_A_DQ<17>

=MEM_A_DQ<21>

MEM_A_DQ<16>

=MEM_A_DQ<18>

MEM_A_DQ<19>

=MEM_A_DQ<23>

MEM_A_DQ<18>

=MEM_A_DQ<19>

MEM_A_DQ<20>

=MEM_A_DQ<22>

MEM_A_DQ<21>

=MEM_A_DQ<17>

MEM_A_DQ<22>

=MEM_A_DQ<20>

MEM_A_DQ<23>

=MEM_A_DQ<27>

MEM_A_DQ<24>

=MEM_A_DQ<29>

MEM_A_DQ<27>

=MEM_A_DQ<25>

MEM_A_DQ<26>

=MEM_A_DQ<26>

MEM_A_DQ<25>

=MEM_A_DQ<30>

MEM_A_DQ<28>

=MEM_A_DQ<31>

MEM_A_DQ<29>

=MEM_A_DQ<24>

MEM_A_DQ<30>

=MEM_A_DQ<28>

MEM_A_DQ<31>

=MEM_A_DQ<38>

MEM_A_DQ<32>

=MEM_A_DQ<37>

MEM_A_DQ<34>

=MEM_A_DQ<39>

MEM_A_DQ<33>

=MEM_A_DQ<33>

MEM_A_DQ<35>

=MEM_A_DQ<35>

MEM_A_DQ<36>

=MEM_A_DQ<34>

MEM_A_DQ<37>

=MEM_A_DQ<36>

MEM_A_DQ<39>

=MEM_A_DQ<32>

MEM_A_DQ<38>

=MEM_A_DQ<46>

MEM_A_DQ<41>

=MEM_A_DQ<42>

MEM_A_DQ<40>

=MEM_A_DQ<47>

MEM_A_DQ<44>

=MEM_A_DQ<40>

MEM_A_DQ<42>

=MEM_A_DQ<41>

MEM_A_DQ<43>

=MEM_A_DQ<44>

MEM_A_DQ<46>

=MEM_A_DQ<43>

MEM_A_DQ<45>

=MEM_A_DQ<61>

MEM_A_DQ<48>

=MEM_A_DQ<45>

MEM_A_DQ<47>

=MEM_A_DQ<60>

MEM_A_DQ<49>

=MEM_A_DQ<58>

MEM_A_DQ<50>

=MEM_A_DQ<62>

MEM_A_DQ<51>

=MEM_A_DQ<63>

MEM_A_DQ<52>

=MEM_A_DQ<59>

MEM_A_DQ<53>

=MEM_A_DQ<56>

MEM_A_DQ<55>

=MEM_A_DQ<57>

MEM_A_DQ<54>

=MEM_A_DQ<48>

MEM_A_DQ<56>

=MEM_A_DQ<49>

MEM_A_DQ<57>

=MEM_A_DQ<53>

MEM_A_DQ<60>

=MEM_A_DQ<55>

MEM_A_DQ<58>

=MEM_A_DQ<51>

MEM_A_DQ<59>

=MEM_A_DQ<54>

MEM_A_DQ<62>

=MEM_A_DQ<52>

MEM_A_DQ<61>

=MEM_A_DQ<50>

MEM_A_DQ<63>

=MEM_B_DQ<55>

=MEM_B_DQS_P<0> =MEM_B_DQS_N<0> =MEM_B_DQS_P<1> =MEM_B_DQS_N<1> =MEM_B_DQS_P<2> =MEM_B_DQS_N<2> =MEM_B_DQS_P<3> =MEM_B_DQS_N<3>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<6> =MEM_B_DQS_N<6> =MEM_B_DQS_P<7> =MEM_B_DQS_N<7>

=MEM_A_DQS_P<0> =MEM_A_DQS_N<0> =MEM_A_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_N<1>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

dvt1

051-1573

8.0.0

103 OF 120

70 OF 82

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21

PP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NO_TESTs

J6603 (AUDIO RIGHT SPEAKER CONN)

J6601 (AUDIO 2-MIKE CONN)

J4802 (TPAD CONN)

U5000 CHARZ TPS

2 TP needed

FUNC_TEST

per Fan

3 TPs

NC NO_TEST

J7050 (MAIN BATT CONN)

J6601 (2 MIC CONN)

J4600 (LEFT USB CONN)

6 TPs

J6050 (LEFT FAN CONN)

FUNC_TEST

U0500 CHARZ TPS

J7715 (KBD BACKLIGHT CONN)

Functional Test Points

High Speed NO_TEST

J9500 (RIO POWER PINS)

POWER RAILS

FUNC_TEST

4 TPs

J6100 (LPC + SPI CONN)

J6602 (AUDIO LEFT SPEAKER CONN)

J8300 (EDP CONN)

J7000 (DC POWER CONN)

J4002 (ALS/CAMERA CONN)

Unused nets with offpage

(Nets with offpages not used on this project)

J4813 (KEY BOARD CONN)

ICT Test Points

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MMSMP2MM

SM

P2MM

SM

P2MM

SM

P2MM

PLACE_NEAR=U0500.AY10:6MM

I2160

I2161

I2162

I2163

I2164

I2165

I2166

I2167

SYNC_DATE=12/06/2013SYNC_MASTER=GKOO_J52

Functional & ICT Test

PP3V3_S5_AVREF_SMC

TRUE

WS_KBD_ONOFF_L

TRUE

PP3V42_G3H

TRUE

PP3V3_S3

PPVCC_S0_CPU

TRUE

PP0V6_S0_DDRVTT

TRUE

WS_KBD7

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

PPBUS_G3H

PP5V_S5

TRUE

NC_AUD_LO4_RP

TRUE TRUE

NC_CS4208_GPO0 NC_CS4208_GPO1

TRUE

NC_CS4208_LRCLKA

TRUE TRUE

NC_CS4208_LRCLKB

ODD_PWR_EN_L

AUD_IP_PERIPHERAL_DET

BT_PWRRST_L

USB3RPCIE_SD_D2R_N

LPC_CLK24M_SMC

TP_PM_SLP_A_L

MIPI_CLK_N

USB3RPCIE_SD_D2R_P

PCIE_AP_D2R_N

PCIE_AP_D2R_P

HDA_SDIN0

PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

PCIE_CLK100M_TBT_N

ENETSD_CLKREQ_L

AUD_IPHS_SWITCH_EN

ENET_LOW_PWR

ENET_MEDIA_SENSE

TP_XDP_PCH_OBSFN_A<0>

TP_XDP_PCH_HOOK4

TP_AUD_MIC_INRN

TP_1V05_S0_PCH_VCCAPLLEXP

TP_XDP_PCH_OBSFN_D<1> TP_XDP_PCH_TRST_L

TP_XDP_PCH_OBSFN_A<1> TP_XDP_PCH_OBSFN_D<0>

TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_B<0>

TP_XDP_PCH_HOOK5

TP_AUD_CODEC_MICBIAS

TP_AUD_MIC_INRP

PCIE_CLK100M_TBT_P

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_CAMERA_D2R_P PCIE_CAMERA_D2R_N

HDD_PWR_EN

=I2C_TPAD_SCL

TRUE

=TPAD_SPI_BUS_EN

TRUE

DMIC_SDA3

TRUE

=TPAD_SPI_SCLK

TRUE

MIPI_DATA_CONN_P

TRUE

MIPI_CLK_CONN_N

TRUE

PPVTTDDR_S3

TRUE

ADAPTER_SENSE

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

PM_SLP_S3_L

TRUE

NC_AUD_LO1_LN

TRUE

NC_AUD_LO1_LP

TRUE

NC_AUD_LO4_LN

TRUE

NC_DMIC_CLK1

TRUE

NC_DMIC_CLK2

TRUE

NC_AUD_LO4_RN

TRUE

NC_AUD_LO1_RP

TRUE

NC_AUD_LO1_RN

TRUE

USB3_EXTB_D2R_N

USB3_EXTB_D2R_P

TRUE

USB3_EXTA_D2R_P

TRUE

USB3_EXTA_R2D_N

TRUE

PCIE_TBT_D2R_C_N<3..1>

TRUE

PCIE_TBT_D2R_N<3..1>

TRUE

PCIE_TBT_D2R_P<3..1>

TRUE

PCIE_TBT_R2D_P<3..0>

PPDCIN_G3H

TRUE

PCIE_CLK100M_TBT_N

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_CAMERA_P

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_TBT_P

TRUE

PCIE_CLK100M_SSD_P

TRUE

USB3_EXTA_R2D_C_P

TRUE

PCIE_SSD_D2R_N<3..0>

TRUE

PCIE_TBT_R2D_C_N<3..0>

TRUE

PCIE_TBT_R2D_C_P<3..0>

TRUE

PCIE_SSD_D2R_P<3..0>

TRUE

PCIE_SSD_R2D_N<3..0>

TRUE

PCIE_SSD_R2D_P<3..0>

TRUE

PCIE_SSD_R2D_C_N<3..0>

TRUE

PCIE_SSD_R2D_C_P<3..0>

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_R2D_C_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_R2D_C_P

TRUE

USB3_EXTA_R2D_C_N

PP1V05_S0

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

KBDLED_CATHODE1

TRUE

PP3V3_S4

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

WS_KBD13

TRUE

TBT_A_D2R_P<0>

TRUE

TBT_B_D2R_C_P<0>

TRUE

TBT_B_D2R_C_N<0>

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

TBT_B_D2R_P<1>

TRUE

TBT_B_D2R_N<0>

TRUE

HDMI_IG_DATA_C_N<2..0>

SMC_TX_L

TRUE

CON_DMIC_CLK

TRUE

PCH_VSS_NCTF<19>

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

HDMI_IG_DATA_C_P<2..0>

TRUE MAKE_BASE=TRUE

NC_AUD_MIC_INRP

TRUE MAKE_BASE=TRUE

NC_1V05_S0_PCH_VCCAPLLEXP

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_D<1>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_TRST_L

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_D<0>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<0>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_B<1>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_B<0>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_HOOK5

LPC_SERIRQ

TRUE

TRUE MAKE_BASE=TRUE

NC_AUD_MIC_INRN

CON_DMIC_PWR

TRUE

PCH_VSS_NCTF<19>

TRUE

HDMI_IG_CLK_C_N

TRUE

TBT_B_R2D_C_N<1..0>

TRUE

TBT_B_R2D_P<1..0>

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_HOOK4

PM_CLKRUN_L

TRUE

USB_LT1_N

TRUE

CON_DMIC_SDA1

TRUE

USB_LT1_P

TRUE

PP5V_S3_LTUSB_A_F

TRUE

SYS_DETECT_L

TRUE

PM_CLKRUN_L

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

TBT_B_D2R_C_P<1>

KBDLED_CATHODE2

TRUE

WS_KBD16_NUM

TRUE

SMBUS_PCH_CLK

TRUE

SMBUS_PCH_DATA

TRUE

WS_KBD12

TRUE

WS_KBD15_CAP

TRUE

WS_KBD2

TRUE

FAN_LT_PWM

TRUE

WS_KBD14

TRUE

SMC_TDI

TRUE

LPCPLUS_RESET_L

TRUE

TBT_B_R2D_N<1..0>

SPIROM_USE_MLB

TRUE

LPC_FRAME_L

TRUE

LPCPLUS_GPIO

TRUE

TBT_B_D2R_N<1>

SMC_TDO

TRUE

HDMI_IG_CLK_C_P

SPKRCONN_R_OUT_N

TRUE

WS_KBD17

TRUE

WS_KBD20

TRUE

WS_KBD6

TRUE

WS_KBD3

TRUE

WS_KBD1

TRUE

WS_KBD5

TRUE

WS_KBD4

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

LPC_PWRDWN_L

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_ROMBOOT

TRUE

SMC_RX_L

TRUE

SMC_TMS

TRUE

PP5VR3V3_SW_LCD

TRUE

EDP_BKLT_PWM

TRUE

EDP_PANEL_PWR_OR_PSR_EN

TRUE

DP_INT_AUX_N

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_N<1>

TRUE

DP_INT_ML_N<3>

TRUE

PPVOUT_S0_LCDBKLT

TRUE

DP_INT_ML_P<3>

TRUE

DP_INT_ML_N<2>

TRUE

DP_INT_ML_P<2>

TRUE

DP_INT_ML_P<0>

TRUE

LCD_HPD_CONN

TRUE

I2C_BKLT_SDA

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

SPKRCONN_L_OUT_N

TRUE

DMIC_SDA2

TRUE

PPVBAT_G3H_CONN

TRUE

PPVOUT_S0_KBDBKLT

TRUE

SMBUS_SMC_1_S0_SCL

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

PP5V_S3

MIPI_DATA_CONN_N

TRUE

WS_KBD22

TRUE

WS_KBD18

TRUE

MIPI_CLK_CONN_P

TRUE

I2C_CAM_SDA

TRUE

I2C_CAM_SCK

TRUE

PCIE_CLK100M_CAMERA_N

TRUE

PP5V_S0

TRUE

PP3V3_S5

WS_KBD21

TRUE

PP3V3_S4

TRUE

PP3V3_S0

TRUE

NC_CS4208_MCLKA

TRUE

NC_CS4208_MCLKB

TRUE

NC_CS4208_SCLKA

TRUE

NC_CS4208_SCLKB

TRUE

NC_CS4208_SDOUTA

TRUE

NC_CS4208_SDOUTB

TRUE

NC_DMIC_CLK0

WS_KBD19

TRUE

TBT_A_R2D_P<1..0>

WS_LEFT_SHIFT_KBD

TRUE

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

TRUE

TBT_A_R2D_C_P<1..0>

TRUE

LPC_AD<0>

TRUE

TBT_A_D2R_C_P<0>

SMC_ONOFF_L

TRUE

PP5V_S0

TRUE

PP3V42_G3H

TRUE

LPC_AD<3>

TRUE

LPC_AD<1>

TRUE

LPC_AD<2>

TRUE

PP1V5_S0

TRUE

TBT_B_D2R_C_N<1>

TRUE

TBT_B_D2R_P<0>

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SR_OUT_P

TRUE

=I2C_TCON_SCL

TRUE

=I2C_TCON_SDA

TRUE

LCD_IRQ_L

TRUE

I2C_BKLT_SCL

TRUE

SPKRCONN_SL_OUT_N

TRUE

DMIC_CLK3

TRUE

DP_INT_AUX_P

TRUE

TBTBPWRSW_ISET_V3P3

TBT_A_D2R_C_N<1>

TRUE

TBT_A_R2D_N<1..0>

TRUE

SPKRCONN_R_ID

TRUE

TBTAPWRSW_ISET_S3_R

SPKRCONN_L_ID

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

TDM_ONEWIRE_MPM

TRUE

TBT_A_D2R_P<1>

TRUE

TBT_A_D2R_C_N<0>

=PPVIN_S4_TPAD

TRUE

TPAD_ACTUATOR_EN_L

TRUE

TPAD_ACTUATOR_THRMTRIP_L

TRUE

=TPAD_WAKE_L

TRUE

SMC_LID

TRUE

=PP3V3_S4_TPAD

TRUE

I2C_IOXP_SDA

TRUE

I2C_IOXP_SCL

TRUE

TPAD_SPI_INT_L

TRUE

USB_TPAD_N

TRUE

=I2C_TPAD_SDA

TRUE

USB_TPAD_P

TRUE

GND_ACTUATOR

=TPAD_SPI_CS_L

TRUE

IOXP2_INT_L

TRUE

PP5V_S4_TPAD_F

TRUE

PCIE_TBT_D2R_C_P<3..1>

TRUE

PCIE_TBT_R2D_N<3..0>

TRUE

WS_KBD23

TBTBPWRSW_ISET_S0_R

TRUE

TBTBPWRSW_ISET_S3

TRUE

PCIE_CLK100M_SSD_N

TRUE MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<1>

TRUE MAKE_BASE=TRUE

NC_AUD_CODEC_MICBIAS

PM_SYSRST_L

TRUE

PPVTTDDR_S3

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

FAN_LT_TACH

TRUE

SPKRCONN_SL_OUT_P

TRUE

USB3_EXTB_R2D_C_N

NC_AUD_LO4_LP

TRUE

PP5V_S3

WOL_EN

TRUE

TBTAPWRSW_ISET_V3P3

=TPAD_SPI_MOSI

TRUE

=TPAD_SPI_MISO

MIPI_CLK_P

MIPI_DATA_N MIPI_DATA_P

TRUE

TBT_A_R2D_C_N<1..0>

TBT_A_D2R_C_P<1>

TRUE

USB3_EXTA_D2R_N

TRUE

USB3_EXTA_R2D_N

NC_SMC_HIB_L

TRUE TRUE

NC_SMC_XOSC1

USB3_EXTB_R2D_C_P

TRUE

TBT_A_D2R_N<1>

TRUE

TBT_A_D2R_N<0>

TRUE

TBT_B_R2D_C_P<1..0>

MEM_B_DQ<63..0>

TRUE

TBTAPWRSW_ISET_S3

PP18V5_DCIN_FUSE

TRUE

MAKE_BASE=TRUE

NC_PM_SLP_A_L

TRUE

TBTAPWRSW_ISET_S0

MEM_A_DQ<63..0>

TRUE

TPAD_VBUS_EN

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

PPA400

1

PPA401

1

PPA410

1

PPA411

1

PPA419

1

PPA423

1

PPA424

1

PPA403

1

PPA402

1

PPA405

1

PPA404

1

PPA420

1

PPA421

1

PPA441

1

PPA442

1

PPA443

1

PPA444

1

PPA408

1

dvt1

051-1573

8.0.0

104 OF 120

71 OF 82

38 39

36

68 71

68

68 76

36

38 41 79

68

48

49

13

15

14 66 74

17

75

13

33

34 78

14 66 74

14 66 71 81

12 49 75

12 32 71 81

12

13

15

12

25 71 81

14 25 81

14 34 81

15

36 41

36 37

49 52

36 37

34 78

68 71 76

53

38 41 79

13 17 18 38 64 66

48

49

48

14 66 74

14 35 74

35 71 74

25 81

14 25 81

25 81

68

12 25 71 81

12 66 81

12 34 81

12 66 81

12 25 71 81

12 32 81

14 35 74

12 32 71 81

14 25 81

12 32 71 81

32 81

12 32 81

14 66 71 81

14 66 81

14 66 71 81

14 66 81

14 35 74

68

38 41 79

37 60

68 71

36

25 28 77

29 77

14 66 71 81

25 29 77

66 67 77

38 39

71

66 81

66 67 77

15 38

71

66 67 77

25 29 77

29 77

13 38 71

74

35

53

13 38 71

38 41 79

29 77

37 60

36

14 41 75

36

38 39

29 77

15 47

14 38 75

16

25 29 77

38 39

66 67 77

50 52 80

36

38 41 79

13 38

38 39 47

38 39 40 47 54

38 39

38 39 47

65

13 65

65

65 77

60 65

65 77

65

65 69

36

50 52 80

52

53 54

37 60

38 41 79

34

68 71

34 78

36

34 78

33 34

12 34 81

68 71

68 80

36

68 71

68 80 49

49

36

28 77

36

25 28 77

14 38 75

28 77

36 38 39

68 71

14 38 75

68

29 77

25 29 77

50 52 80

41 65

15 65

65 69

50 52 80

49 52

65 77

29

28 77

49 52

28

49 52

50 52 80

25 28 77

28 77

36 68

36 40 42

36 62

36 40

36 38 39 40

36 37 68

36

15 36

14 36 74

36 41

14 36 74

36

36 37

36

25 81

36

29

12 32 81

13 17 38 75

68 71 76

34

50 52 80

14 66 74

48

68 71

14

28

36 37

33

34 78

25 28 77

28 77

14 35 74

35 71 74

38

14 66 74

25 28 77

25 29 77

7

70 76

28

53

28

7

70 76

36 37

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Inner dielectric is 0.053 mm nominal.

Note: Outer dielectric is 0.058 mm nominal,

X304 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

Stackup-Defined Spacing Rules

Y

=STANDARD=STANDARD

0.090 MM0.102 MM

40_OHM_SE

*

=STANDARD

1:1_SPACING

?

*

0.1 MM

PCB Rule Definitions

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=12/14/2012

16.5

MM

NO_TYPE,BGA,P65BGA,BGA_MEM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

DEFAULT

=45_OHM_SE =45_OHM_SE

Y

0 MM

*

10 MM

0 MM

STANDARD =DEFAULT =DEFAULT

10 MM

Y*

=DEFAULT=DEFAULT

*

P072_SPACE

BGA

*

1TO1_DIFFPAIR

0.1 MM=STANDARD=STANDARD=STANDARD

Y*

0.1 MM

1x_DIELECTRIC

?

TOP,BOTTOM

0.058 MM

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

1X_DIELECTRIC

?

0.101 MM

0.1 MM

?*

DEFAULT

*N

=STANDARD=STANDARD

73_OHM_DIFF

=STANDARD=STANDARD =STANDARD

1x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10

0.053 MM

?

*

P65BGA

P65_BGA

*

P075_SPACE

P65BGA

*

=DEFAULT

?*

STANDARD

0.071 MM

?*

P072_SPACE

*?

P075_SPACE

0.075 MM

=STANDARD =STANDARD =STANDARD=STANDARD

N*

=STANDARD

80_OHM_DIFF

0.120 MM

ISL2,ISL11

0.120 MM

Y

72_OHM_DIFF

0.105 MM 0.105 MM

0.105 MM

ISL3,ISL4,ISL9,ISL10

72_OHM_DIFF

0.120 MM 0.120 MM

Y

0.105 MM

=STANDARD

72_OHM_DIFF

=STANDARD =STANDARD

N

=STANDARD

*

=STANDARD

0.190 MM

*

0.090 MM

=STANDARD =STANDARD=STANDARD

Y

27P4_OHM_SE

Y

0.095 MM0.145 MM

TOP,BOTTOM

40_OHM_SE

0.090 MM

=STANDARD =STANDARD

*Y

0.118 MM

37_OHM_SE =STANDARD

Y

0.265 MM 0.095 MM

27P4_OHM_SE

TOP,BOTTOM

0.120 MM

TOP,BOTTOM

Y

72_OHM_DIFF

0.120 MM0.146 MM 0.146 MM

Y

ISL2,ISL11

0.092 MM

80_OHM_DIFF

0.092 MM 0.120 MM 0.120 MM

ISL3,ISL4,ISL9,ISL10

0.120 MM0.120 MM

Y

0.092 MM

80_OHM_DIFF

0.092 MM

0.125 MM

Y

TOP,BOTTOM

80_OHM_DIFF

0.125 MM 0.155 MM 0.155 MM

85_OHM_DIFF

Y

0.120 MM 0.120 MM

ISL2,ISL11

0.080 MM 0.080 MM

0.125 MM

85_OHM_DIFF

0.105 MM 0.125 MM0.105 MM

Y

TOP,BOTTOM

N

=STANDARD

90_OHM_DIFF

=STANDARD=STANDARD

*

=STANDARD =STANDARD

0.200 MM

90_OHM_DIFF

0.078 MM0.078 MM

Y

ISL3,ISL4,ISL9,ISL10

0.200 MM

Y

0.125 MM0.120 MM 0.120 MM

70_OHM_DIFF

0.125 MM

ISL2,ISL11

0.075MM 0.126MMP65_BGA

*Y

0.071MM 0.071MM

85_OHM_DIFF

=STANDARD=STANDARD

*

=STANDARD=STANDARD

N

=STANDARD

0.080 MM0.080 MM

Y

0.120 MM

85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.120 MM

0.200 MM

Y

90_OHM_DIFF

ISL2,ISL11

0.200 MM0.078 MM0.078 MM

90_OHM_DIFF

0.180 MM

Y

0.180 MM

TOP,BOTTOM

0.101 MM 0.101 MM

0.120 MM0.120 MM 0.125 MM

Y

70_OHM_DIFF

0.125 MM

ISL3,ISL4,ISL9,ISL10

0.110 MM

Y

0.120 MM

ISL2,ISL11

73_OHM_DIFF

0.120 MM0.110 MM

Y

TOP,BOTTOM

73_OHM_DIFF

0.120 MM0.141 MM0.141 MM 0.120 MM

=STANDARD =STANDARD

N*

70_OHM_DIFF

=STANDARD =STANDARD =STANDARD

0.125 MM0.155 MM 0.125 MM

70_OHM_DIFF

TOP,BOTTOM

Y

0.155 MM

ISL3,ISL4,ISL9,ISL10

Y

0.120 MM

73_OHM_DIFF

0.120 MM0.110 MM0.110 MM

0.116 MM

Y

0.116 MM

TOP,BOTTOM

45_OHM_SE

Y

50_OHM_SE

TOP,BOTTOM

0.095 MM0.095 MM

0.066 MM

Y

=STANDARD =STANDARD=STANDARD50_OHM_SE

*

0.066 MM

0.095 MM

TOP,BOTTOM

Y

0.165 MM

37_OHM_SE

0.083 MM

45_OHM_SE =STANDARD =STANDARD=STANDARD

Y

0.083 MM

*

dvt1

051-1573

8.0.0

110 OF 120

72 OF 82

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPACING

ELECTRICAL CONST SET

PHYSICAL

NET TYPE

CPU Signal Constraints

CPU Signal Properties

=27P4_OHM_SE

7 MIL7 MIL

=27P4_OHM_SE=27P4_OHM_SE

*

CPU_27P4S

CPU_12MIL

0.305 MM

*?

0.457 MM

CPU_18MIL

*?

0.635 MM

CPU_25MIL

=45_OHM_SE=45_OHM_SE

=45_OHM_SE

CPU_45S

*

=STANDARD =STANDARD

=45_OHM_SE

?

25 MIL

CPU_VCCSENSE

*

0.203 MM

?*

CPU_08MIL

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/13/2013

CPU Constraints

CPU_08MIL

CPU_45S

CPU_CATERR_L

CPU_CATERR

CPU_45S

CPU_VIDALERT_R_L

CPU_18MIL

CPU_VIDALERT

CPU_45S

CPU_18MIL

CPU_VIDSCLK_R

CPU_VIDSCLK

CPU_CFG<19..11>

CPU_45SCPU_CFG

CPU_18MIL

CPU_45S

CPU_VIDSCLK

CPU_PECI

CPU_45S

CPU_18MIL

CPU_PECI

XDP_TDI

XDP_CPU_TDI

CPU_45S

CPU_18MIL

XDP_TCK1

XDP_PCH_TCK

CPU_45S

CPU_18MIL

XDP_TCK0

CPU_45S

XDP_CPU_TCK

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_45S

SMC_PECI_L

CPU_PECI

CPU_18MIL

CPU_45S

CPU_PECI_R

CPU_18MIL

CPU_PECI

CPU_45S

SMC_PECI_L_R

CPU_18MIL

CPU_PECI

XDP_CPU_PREQ_L

XDP_PREQ_L

CPU_45S

CPU_CFG_PD

CPU_45S

CPU_CFG<10..8>

CPU_CFG_PD

CPU_45S

CPU_CFG<4>

CPU_CFG_3

CPU_45S

CPU_CFG<3>

CPU_CFG CPU_45S

CPU_CFG<2>

CPU_45S

CPU_CFG<1..0>

CPU_CFG_PD

CPU_08MIL

CPU_45S

MEM_RESET_L

CPU_MEM_RESET

CPU_VCCSENSE_P

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_CFG<7..5>

CPU_CFG CPU_45S

CPU_18MIL

XDP_TCK0

PCH_JTAGX

CPU_45S

XDP_TDO

XDP_CPU_TDO

CPU_45S

XDP_TDO

XDP_PCH_TDO

CPU_45S

XDP_CPU_PRDY_L

CPU_45S

XDP_PRDY_L

XDP_CPUPCH_TRST_L

CPU_45S

XDP_TRST_L

CPU_45S

XDP_PCH_TMS

XDP_TMS

XDP_TMS CPU_45S

XDP_CPU_TMS

XDP_TDI

XDP_PCH_TDI

CPU_45S

CPU_VIDSOUT_R

CPU_VIDSOUT

CPU_18MIL

CPU_45S

CPU_VIDSOUT

CPU_18MIL

CPU_VIDSOUT

CPU_18MIL

CPU_VIDALERT_L

CPU_45S

CPU_VIDALERT

CPU_12MIL

CPU_RCOMP_OPI

CPU_OPI_RCOMP

CPU_27P4S

XDP_BPM_L<7..2>

CPU_45S

CPU_BPM_TP

CPU_08MIL

XDP_BPM_L<1..0>

CPU_45SCPU_BPM

CPU_VCCST_PWRGD

CPU_08MIL

XDP_CPU_VCCST_PWRGD

CPU_45S

CPU_08MIL

CPU_PROCHOT_R_L

CPU_45S

CPU_PROCHOT

CPU_08MIL

CPU_PROCHOT_L

CPU_45S

CPU_PROCHOT

CPU_25MIL

CPU_RCOMP_EDP

MCP_EDP_RCOMP

CPU_27P4S

CPU_25MIL

CPU_RCOMP_SM

CPU_SM_RCOMP<2..0>

CPU_27P4S

CPU_VCCST_PWRGD

CPU_45S

CPU_08MIL

dvt1

051-1573

8.0.0

111 OF 120

73 OF 82

6

38

8

6

16

8

55

6

39

6

16

12 16

6

16

9

55

38 39

39

6

16

6

16

6

16

6

16

6

16

6

16

8

55

6

16

12 16

6

16

12 16

6

16

12 16

6

16

12 16

8

55

8

55

6

16

6

16

6

38 39 55

5

6

8

16 17

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SATA Interface Constraints (Not Used)

Notes:

SPACING

PHYSICAL

NET TYPE

ELECTRICAL CONST SET

USB Constraints

USB 3 Interface Constraints

USB 2 Interface Constraints

System Clock Signal Constraints

This is here to keep the SATA rules.

I330

I331

=45_OHM_SE

=STANDARD

=45_OHM_SE=45_OHM_SE

*

CLK_25M_45S

=STANDARD

SATA_2OTHER

TOP,BOTTOM

=6X_DIELECTRIC

?

=6X_DIELECTRIC

TOP,BOTTOM

USB3_2OTHER

?

=10X_DIELECTRICTOP,BOTTOM

USB_RBIAS

SATA_45SE

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

=45_OHM_SE

SATA_2SAME

*

=SAME

SATA_*

SATA_2OTHER

**

SATA_*

SATA_TX

SATA_TXRX

*

*_RX

SATA_RX

SATA_TXRX

*

*_TX

USB3_2OTHER

*

=4X_DIELECTRIC

?

USB3_TXRX

*

=6X_DIELECTRIC

?

SATA_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

SATA_TXRX

TOP,BOTTOM=10X_DIELECTRIC

?

SATA_2SAME

*?

=3X_DIELECTRIC

SATA_TXRX

*?

=6X_DIELECTRIC

SATA_2OTHER

*?

=4X_DIELECTRIC

?

=6X_DIELECTRIC

TOP,BOTTOM

USB

?

=10X_DIELECTRICTOP,BOTTOM

USB3_TXRX

USB3_*

USB3_2OTHER

**

USB3_2SAME

*

=3X_DIELECTRIC

?

USB_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

?

=4X_DIELECTRIC

*

USB

?

=6X_DIELECTRIC

USB_RBIAS

*

PCH_USB_RBIAS

*

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD=STANDARD

USB3_*

=SAME USB3_2SAME

*

USB3_TX

*_RX

USB3_TXRX

*

SATA_2SAME TOP,BOTTOM

=4x_DIELECTRIC

?

=5x_DIELECTRIC

*

CLK_25M

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/07/2013

USB Constraints

USB3_RX

*_TX

USB3_TXRX

*

?

=4x_DIELECTRIC

USB3_2SAME TOP,BOTTOM

USB3_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

USB

USB_85D

USB_TPAD

USB_TPAD_N

USB

USB_85D

USB_TPAD

USB_TPAD_P

USB3_EXTA_R2D

USB3_EXTA_R2D_N

USB3_TXUSB_85D

USB3_EXTA_D2R_P

USB3_RXUSB_85D

USB3_EXTA_D2R

USB_85D

USB

USB_EXTB

USB_EXTB_P

USB_85D

USB

USB_EXTB

USB_EXTB_N

USB3_EXTA_R2D

USB3_TXUSB_85D

USB3_EXTA_R2D_C_P

DUMMY_SATA_D2R_N

SATA_RX

SATA_85D

DUMMY_SATA_D2R_P

SATA_RX

SATA_85D

USB_85D

USB3_EXTB_R2D_C_P

USB3_TX

USB3_EXTB_R2D

USB_85D USB3_RX

USB3_EXTB_D2R

USB3_EXTB_D2R_N

USB_85D USB3_RX

USB3_EXTB_D2R

USB3_EXTB_D2R_P

USB3_EXTA_R2D

USB3_TXUSB_85D

USB3_EXTA_R2D_C_N

USB3_TXUSB_85D

USB3_EXTA_R2D

USB3_EXTA_R2D_P

USB3_EXTA_D2R_N

USB_85D USB3_RX

USB3_EXTA_D2R

USB3_85D

USB3_RX

USB3_SD_D2R

USB3RPCIE_SD_D2R_P

NC_USB_IRP

USB_85D

USB

USB_NC

USB_85D

USB_NC

NC_USB_IRN

USB

NC_USB_5N

USB

USB_85D

USB_NC

NC_USB_CAMERAP

USB

USB_85D

USB_NC

PCH_USB_RBIAS

USB_RBIAS

PCH_USB_RBIAS

USB_85D

USB

USB_NC

NC_USB_SDP

USB_85D

USB

USB_NC

NC_USB_SDN

SATA_TX

SATA_85D

DUMMY_SATA_R2D_P DUMMY_SATA_R2D_N

SATA_TX

SATA_85D

USB_EXTA

USB

USB_85D

USB2_EXTA_MUXED_F_P

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_X1

SYSCLK_CLK25M

USB2_EXTA_MUXED_N

USB

USB_85D

USB_EXTA

USB_LT1_N

USB

USB_EXTA

USB_85D

USB3_EXTB_R2D_C_N

USB3_EXTB_R2D

USB3_TX

SMC_DEBUGPRT_RX_L

DEFAULTDEFAULT

USB_EXTA_N

USB

USB_85D

USB_EXTA

USB_EXTA_P

USB

USB_85D

USB_EXTA

SMC_DEBUGPRT_TX_L

DEFAULTDEFAULT

USB_BT_CONN_N

USB_BT

USB

USB_85D

USB_BT_P

USB_BT

USB

USB_85D

USB_BT_N

USB_BT

USB

USB_85D

USB_BT_CONN_P

USB_BT

USB

USB_85D

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_CAM

CLK25M_CAM_XTALP_R

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_CAM

CLK25M_CAM_XTALP

SYSCLK_CLK25M_TBT

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_TBT_R

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_CAM

CLK25M_CAM_XTALN

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_CAM

CLK25M_CAM_CLKN

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_X2

SYSCLK_CLK25M

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_CAM

CLK_25M

CLK_25M_45S

CLK25M_CAM_CLKP

SYSCLK_CLK25M_CAM

USB2_EXTA_MUXED_P

USB

USB_85D

USB_EXTA

USB3RPCIE_SD_R2D_C_P

USB3_85D

USB3_TX

USB3_SD_R2D

USB3_85D

USB3_TX

USB3_SD_R2D

USB3RPCIE_SD_R2D_C_N

USB_EXTA

USB

USB_85D

USB2_EXTA_MUXED_F_N USB_LT1_P

USB_85D

USB

USB_EXTA

USB3_85D

USB3_RX

USB3_SD_D2R

USB3RPCIE_SD_D2R_N

NC_USB_5P

USB_85D

USB

USB_NC

USB

USB_85D

NC_USB_CAMERAN

dvt1

051-1573

8.0.0

112 OF 120

74 OF 82

14 36 71

35 71

14 35 71

14 66

14 35 71

14 66 71

14 35 71

35

14 35 71

14 66 71

69

14

69

35

17

35

71

14 66 71

35 38 39

14 35

35 38 39

31 66

14 31

31 66

34

17 25

25

34

33 34

17

17 34

33 34

35

14 66

35

71

14 66 71

69

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LPC Bus Constraints

SPI Interface Constraints

SMBus Interface Constraints

HD Audio Interface Constraints

PCH Net Properties

SPACING

NET TYPE

PHYSICAL

ELECTRICAL CONST SET

PCH Single Net Constraints

I381

I382

I383

I384

I385

I386

I387

I388

SYNC_DATE=01/08/2013

SYNC_MASTER=YHARTANTO_J44

PCH Constraints

CLK_LPC_45S

*

=45_OHM_SE =45_OHM_SE

=STANDARD =STANDARD

=45_OHM_SE

LPC_45S

*

=45_OHM_SE

=STANDARD =STANDARD

=45_OHM_SE

=45_OHM_SE=45_OHM_SE

SMB_45S

=45_OHM_SE =45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE

*

=27P4_OHM_SE

7 MIL

=27P4_OHM_SE

PCH_27P4S

7 MIL

=27P4_OHM_SE

SPI

8 MIL

*?

?

HDA

*

=2x_DIELECTRIC

?*

0.381 MM

PCH_15MIL

PCH_18MIL

0.457 MM

?*

*?

PCH_20MIL

0.508 MM

CLK_LPC

*

8 MIL

?

SMB

?*

=2x_DIELECTRIC

LPC

*

6 MIL

?

=45_OHM_SE

HDA_45S

*

=45_OHM_SE

=45_OHM_SE=45_OHM_SE

=STANDARD=STANDARD

SPI_45S

*

=45_OHM_SE

=45_OHM_SE=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

PCH_12MIL

0.305 MM

*?

PCH_45S

*

=45_OHM_SE =45_OHM_SE

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

SPI_IO2_R

SPI

SPI_45S

SPI_MLB_IO2

SPI

SPI_45S

SPI_MLB_IO2_WP_L

SPI_MLB_IO2

SPI

SPI_MLB_IO2

SPI_45S

SPI_ALT_IO2_WP_L

SPI_MLB_IO3

SPI

SPI_45S

SPI_IO3_R

SPI_45S

SPI

SPI_MLB_IO2

SPI_IO<2>

SPI

SPI_IO<3>

SPI_MLB_IO3

SPI_45S

SPI

SPI_45S

SPI_MLB_IO3

SPI_MLB_IO3_HOLD_L

SPI_45S

SPI_MLB_IO3

SPI_ALT_IO3_HOLD_L

SPI

TPAD_SPI_CLK

SPI_TPAD

SPI_45S

SPI

TPAD_SPI_CS_L

SPI

SPI_45S

SPI_TPAD_CS SPI_TPAD

TPAD_SPI_MISO

SPI

SPI_45S

TPAD_SPI_MOSI

SPI_TPAD

SPI

SPI_45S

SPI

SPI_MLB

SPI_ALT_CS_L

SPI_ALT_IO0_MOSI

SPI_45SSPI_MLB

SPI

SPI_45SSPI_MLB

SPI

SPI_MOSI_R

SPI_MLB

SPI

SPI_45S

SPI_MLB_IO0_MOSI

SPI_45S

SPI

SPI_MLB

SPI_SMC_MOSI

SPI_MLB SPI_45S

SPI_MOSI

SPI

SPI_45S

SPI_MISO_R

SPI

SPI_MLB

SPI_45S

SPI

SPI_MLB

SPI_SMC_CS_L

SPI_45S

SPI

SPI_MLB

SPI_ALT_IO1_MISO

SPI_45SSPI_MLB

SPI

SPI_MISO

SPI_SMC_MISO

SPI_45SSPI_MLB

SPI

PM_THRMTRIP_R_L

PCH_THRMTRIP

PCH_18MIL

PCH_45S

PCH_INTRUDER_L

PCH_15MIL

PCH_SRTCRST_L

PCH_45S

PCH_SRTCRST

PCH_15MIL PCH_15MIL

RTC_RESET_L

PCH_RTCRST

PCH_45S

PM_THRMTRIP_L

PCH_THRMTRIP

PCH_18MIL

PCH_45S

PCH_15MIL

PCH_45S

PCH_RTCX

PCH_CLK32K_RTCX1

SPI_MLB_IO1_MISO

SPI_MLB SPI_45S

SPI

SPI_45S

SPI_CS0_R_L

SPI_MLB

PCH_45S

XDP_DBRESET_L

PCH_15MIL

SPI_45S

SPI

SPI_MLB

SPI_CLK_R

HDA

HDA_SDIN

HDA_SDIN0

HDA_45S

HDA

HDA_SYNC

HDA_SYNC_R

HDA_45S

HDA

HDA_SYNC

HDA_45S

HDA

HDA_SDOUT

SPI_45S

SPI

SPI_MLB_CS_L

SPI_MLB

SPI

SPI_45S

SPI_CS0_L

SPI_45SSPI_MLB

SPI_SMC_CLK

SPI

SPI_MLB SPI_45S

SPI_MLB_CLK

SPI_MLB SPI_45S

SPI

SPI_CLK

SPI_45S

SPI

SPI_MLB

SPI_ALT_CLK

HDA_45S

HDA

HDA_SDIN

CS4208_HDA_SDOUT0_R

SMB_45S

SMB

SML_PCH_1_CLK

SMB_45S

SMB

SML_PCH_0_DATA

SML_PCH_0

SMB_45S

SMB

SML_PCH_0_CLK

SML_PCH_0

LPC_CLK24M_SMC

CLK_LPC_45S

CLK_LPCLPC_CLK24M_SMC

LPC_CLK24M_SMC_R

CLK_LPC_45S

LPC_CLK24M_SMC CLK_LPC

SMB_45S

SMB

SMBUS_PCH

SMBUS_PCH_CLK

SMB_45S

SMB

SMBUS_PCH

SMBUS_PCH_DATA

HDA_45S

HDA

HDA_BIT_CLK

LPC_45S

LPC_AD

LPC

LPC_AD<3..0>

LPC_AD

LPC_45S

LPC_FRAME_L

LPC

HDA_45S

HDA

HDA_BIT_CLK

HDA_BIT_CLK_R

HDA_SDOUT_R

HDA_45S

HDA

HDA_SDOUT

HDA_45S

HDA

HDA_RST

HDA_RST_L

HDA_45S

HDA

HDA_RST

HDA_RST_R_L

SMB_45S

SMB

SML_PCH_1_DATA

PCH_45S

PCH_15MIL

PCH_INTVRMEN

PCH_15MIL

PCH_45S

PCH_DSWVRMEN

PCH_45S

PM_RSMRST_L

PCH_15MIL

PCH_45S

PM_PCH_SYS_PWROK

PCH_15MIL

PCH_45S

XDP_SYS_PWROK

PCH_15MIL

PCH_45S

PCH_15MIL

PM_PCH_PWROK

PCH_45S

PCH_15MIL

SYS_PWROK_R

PCH_45S

PM_S0_PGOOD

PCH_15MIL

PCH_45S

SMC_DELAYED_PWRGD

PCH_15MIL

PCH_45S

PM_DSW_PWRGD

PCH_15MIL

PCH_45S

PCH_15MIL

PM_PWRBTN_L

PCH_45S

XDP_CPU_PWRBTN_L

PCH_15MIL

PCH_45S

PCH_15MIL

AP_PCIE_WAKE_L

PCH_45S

PCIE_WAKE_L

PCH_15MIL

PCH_45S

PCH_15MIL

CAM_PCIE_WAKE_L

PCH_15MIL

TBT_CIO_PLUG_EVENT_L

PCH_45S

PCH_CLK24M_XTAL

PCH_20MIL

PCH_CLK24M_XTALIN

PCH_45S

PCH_CLK24M_XTALOUT

PCH_45S

PCH_20MIL

PCH_CLK24M_XTAL

PCH_CLK24M_XTALOUT_R

PCH_45S

PCH_20MIL

PCH_CLK24M_XTAL

PCH_PCIE_RCOMP

PCH_12MILPCH_27P4S

PCH_RCOMP_PCIE

PCH_OPI_COMP

PCH_12MILPCH_27P4S

PCH_RCOMP_OPI

PCH_SATA_RCOMP

PCH_12MILPCH_27P4S

PCH_RCOMP_SATA

PCH_45S

PCH_15MIL

PM_SYSRST_L

dvt1

051-1573

8.0.0

113 OF 120

75 OF 82

47

14 47

47

15 37

47

14 47

47

38 47

47

38 47

47

14 47

38 47

39

12

15 39

12 17

47

14 47

16 17

14 47

12 49 71

12

12 49

47

38 47

47

49

14 41

17 71

12 17

14 41 71

12 49

14 38 71

12

12 17

12 49

12

14 41

12

13

13 64

13 16 17 38

16

13 17

17

17 26 27 38 39

13 38

13 16 38

16

31 66

13 31 33

33

18 25

12 17

17

14

15

12

13 17 38 71

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

CMD to CLK mils CLK - 250 CLK + 250

(CMDmax - CMDmin) mils 0 50

CTL/CKE to CLK mils CLK - 100 0

CTL/CKEmax - CTL/CKEmin mils 0 50

ELECTRICAL CONST SET

Memory Net Properties

Spacing Rule Sets

Memory Bus Constraints

SPACING

PHYSICAL

NET TYPE

Memory Bus Spacing Group Assignments

Memory to GND Spacing

Memory to Power Spacing

CLK to CLK# mils -2.5 2.5

DQS to CLK (Rule 1) mils CLK - 750 CLK + 1250

DQS to DQS# mils -2.5 2.5

DQmax to DQs per byte mils DQS - 200 DQS + 50

DQmax - DQmin per byte mils 0 125

Broadwell ULT Memory Down LPDDR3 1x4 Length Matching

LPDDR3 Signal Group Unit Min Length Max Length

SYNC_DATE=01/02/2013

SYNC_MASTER=YHARTANTO_J44

Memory Constraints

=73_OHM_DIFF=73_OHM_DIFF

*

=73_OHM_DIFF=73_OHM_DIFF

=73_OHM_DIFF

MEM_73D

0.066 MM

=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF

MEM_70D

=70_OHM_DIFF

=40_OHM_SE

MEM_40S

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

*

=50_OHM_SE

=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

MEM_50S

=50_OHM_SE=50_OHM_SE

TOP,BOTTOM?=5x_DIELECTRIC

MEM_DATA2SELF

=5x_DIELECTRIC

?

TOP,BOTTOM

MEM_DQS2OWNDATA

*

MEM_PWR

*

DEFAULT

0.305 MM

?*

MEM_12MIL

=3x_DIELECTRICMEM_CMD2CTL_BM

* ?

=3x_DIELECTRICMEM_CMD2CMD_BM

?*

* ?

=2x_DIELECTRIC

MEM_2PWR

* ?

=8x_DIELECTRIC

MEM_DATA2OTHERMEM

=6x_DIELECTRIC

* ?

MEM_CLK2CLK

?

=3x_DIELECTRIC

*

MEM_CTL2CTL

=4x_DIELECTRIC

?

MEM_2OTHERMEM

*

?

MEM_CMD2CMD

=5x_DIELECTRIC

TOP,BOTTOM

MEM_2OTHER

**

MEM_*_DQS_*

?

=8x_DIELECTRIC

MEM_CLK2CLK

TOP,BOTTOM

?

MEM_CTL2CTL

TOP,BOTTOM

=5x_DIELECTRIC

MEM_CMD2CTL

=3x_DIELECTRIC

* ?

MEM_B_DQS_1

*

MEM_DQS2OWNDATA

MEM_B_DQBYTE_1

MEM_DQS2OWNDATA

MEM_B_DQS_4*MEM_B_DQBYTE_4

MEM_CMD2CMD

* ?

=3x_DIELECTRIC

=2x_DIELECTRIC

?*

MEM_DATA2SELF

=3x_DIELECTRIC

?

MEM_DQS2OWNDATA

*

MEM_2OTHERMEM

MEM_*

*

MEM_*

*

MEM_A_DQS_6

MEM_DQS2OWNDATA

MEM_A_DQBYTE_6

?

=3x_DIELECTRIC

*

MEM_CTL2CTL_BM

=2x_DIELECTRIC

MEM_2GND

* ?

=6x_DIELECTRIC

MEM_2OTHER

* ?

MEM_CLK MEM_CLK

*

MEM_CLK2CLK

MEM_CMD BGA_MEMMEM_CMD MEM_CMD2CMD_BM

MEM_CMD2CMD

*

MEM_CMDMEM_CMD

MEM_*_DQBYTE_*

*

MEM_*

MEM_DATA2OTHERMEM

MEM_*_DQBYTE_*

=SAME

MEM_DATA2SELF

*

MEM_2OTHER

MEM_CTL

**

MEM_CMD

MEM_2OTHER

**

*

MEM_DQS2OWNDATA

MEM_B_DQBYTE_3

MEM_B_DQS_3

MEM_B_DQS_2*MEM_B_DQBYTE_2

MEM_DQS2OWNDATA

*

MEM_A_DQBYTE_7

MEM_A_DQS_7

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_A_DQBYTE_3

MEM_A_DQS_3

MEM_2OTHER

**

MEM_CLK

?

=10x_DIELECTRIC

MEM_2OTHER TOP,BOTTOM

MEM_A_DQBYTE_5

MEM_A_DQS_5

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_B_DQS_5

MEM_B_DQBYTE_5

*

GND

MEM_*

MEM_2GND

MEM_B_DQS_0

MEM_DQS2OWNDATA

MEM_B_DQBYTE_0

*

MEM_A_DQBYTE_4

MEM_A_DQS_4

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_A_DQBYTE_2

MEM_A_DQS_2

*

MEM_DQS2OWNDATA

*

MEM_B_DQS_6

MEM_B_DQBYTE_6

MEM_2OTHER

MEM_*_DQBYTE_*

**

MEM_DQS2OWNDATA

*

MEM_A_DQBYTE_0

MEM_A_DQS_0

MEM_A_DQBYTE_1

MEM_A_DQS_1

*

MEM_DQS2OWNDATA

=3x_DIELECTRIC

?

MEM_CTL2CTL_BM

TOP,BOTTOM

MEM_CMD2CTL_BM =3x_DIELECTRIC

?

TOP,BOTTOM

=3x_DIELECTRICMEM_CMD2CMD_BM?TOP,BOTTOM

MEM_2GND

=4x_DIELECTRIC

?

TOP,BOTTOM

MEM_2PWR

?

=4x_DIELECTRIC

TOP,BOTTOM

?

=8x_DIELECTRIC

TOP,BOTTOM

MEM_2OTHERMEM

?

TOP,BOTTOM

MEM_CMD2CTL

=5x_DIELECTRIC

MEM_73DMEM_70D

BGA_MEM

MEM_50SMEM_40S

BGA_MEM

MEM_PWR

MEM_*

*

MEM_2PWR

MEM_CMD2CTL_BMBGA_MEMMEM_CTLMEM_CMD

MEM_CMD2CTL

*

MEM_CTLMEM_CMD

MEM_CTL2CTL

MEM_CTLMEM_CTL

*

BGA_MEMMEM_CTLMEM_CTL MEM_CTL2CTL_BM

*

MEM_B_DQS_7

MEM_B_DQBYTE_7

MEM_DQS2OWNDATA

MEM_B_DQS0

MEM_70D

MEM_B_DQS_0

MEM_B_DQS_P<0>

MEM_B_DQS_2

MEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_B_DQS_2

MEM_B_DQS_P<2>

MEM_70D

MEM_B_DQBYTE7

MEM_B_DQBYTE_7

MEM_40S

MEM_B_DQ<63..56>

MEM_B_DQBYTE6

MEM_40S

MEM_B_DQ<55..48>

MEM_B_DQBYTE_6

PP0V6_S0_DDRVTT

MEM_PWR

MEM_A_DQS_7

MEM_A_DQS7

MEM_70D

MEM_A_DQS_N<7>

MEM_70D

MEM_B_DQS_3

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_12MIL

CPU_DIMMA_VREFDQ

MEM_B_CTL

MEM_40S MEM_CTL

MEM_B_CS_L<1..0>

MEM_B_DQS6

MEM_70D

MEM_B_DQS_6

MEM_B_DQS_N<6>

MEM_B_DQS_6

MEM_B_DQS6

MEM_70D

MEM_B_DQS_P<6>

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_B_DQS_5

MEM_70D

MEM_B_DQS_P<5>

MEM_B_DQS5

MEM_B_DQS_5

MEM_70D

MEM_B_DQS_N<4>

MEM_70D

MEM_B_DQS4

MEM_B_DQS_4

MEM_B_DQS_1

MEM_B_DQS1

MEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS0

MEM_B_DQS_0

MEM_70D

MEM_B_DQS_N<0>

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_70D

MEM_B_DQS_4

MEM_B_DQS_7

MEM_70D

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_B_DQBYTE5

MEM_B_DQBYTE_5

MEM_40S

MEM_B_DQ<47..40>

MEM_40S

MEM_B_DQBYTE_1

MEM_B_DQBYTE1

MEM_B_DQ<15..8>

MEM_B_DQBYTE4

MEM_B_DQBYTE_4

MEM_40S

MEM_B_DQ<39..32>

MEM_B_CLK_N<0>

MEM_CLK

MEM_B_CLK0

MEM_70D

MEM_PWR

PPVTTDDR_S3

MEM_12MIL

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

MEM_12MIL

MEM_70D

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_B_DQS_3

MEM_B_DQS1

MEM_B_DQS_1

MEM_70D

MEM_B_DQS_P<1>

MEM_B_DQBYTE3

MEM_B_DQBYTE_3

MEM_40S

MEM_B_DQ<31..24>

MEM_PWR

PP1V2_S3_CPUDDR

MEM_A_CLK0

MEM_CLKMEM_70D

MEM_A_CLK_N<0>

MEM_A_CLK0

MEM_70D MEM_CLK

MEM_A_CLK_P<0>

MEM_CMDMEM_40S

MEM_A_CKE0

MEM_A_CKE<1..0>

MEM_CMDMEM_40S

MEM_A_CKE1

MEM_A_CKE<3..2>

MEM_CMDMEM_40S

MEM_A_CMD1

MEM_A_CAB<9..0>

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_70D

MEM_A_DQS_1

MEM_A_DQS_7

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_70D

MEM_CLK

MEM_B_CLK_P<0>

MEM_B_CLK0

MEM_70D

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_70D

MEM_A_DQS_2

MEM_A_DQ<39..32>

MEM_A_DQBYTE4

MEM_A_DQBYTE_4MEM_40S

MEM_A_DQ<55..48>

MEM_A_DQBYTE6

MEM_A_DQBYTE_6MEM_40S

MEM_B_DQBYTE_2

MEM_40S

MEM_B_DQ<23..16>

MEM_B_DQBYTE2

MEM_A_DQS6

MEM_A_DQS_6

MEM_70D

MEM_A_DQS_P<6>

MEM_CMD

MEM_B_CKE1

MEM_40S

MEM_B_CKE<3..2>

MEM_A_DQBYTE7

MEM_40S MEM_A_DQBYTE_7

MEM_A_DQ<63..56>

MEM_40S MEM_CTL

MEM_B_CTL

MEM_B_ODT<0>

MEM_B_DQS_7

MEM_B_DQS7

MEM_70D

MEM_B_DQS_N<7>

PP0V6_S3_MEM_VREFCA_A

MEM_12MIL

PP0V6_S3_MEM_VREFDQ_B

MEM_12MIL

PP0V6_S3_MEM_VREFCA_B

MEM_12MIL

PP0V6_S3_MEM_VREFDQ_A

MEM_12MIL

MEM_PWR

PP1V2_S3

MEM_A_CLK1

MEM_CLKMEM_70D

MEM_A_CLK_P<1>

MEM_CTLMEM_40S

MEM_A_CTL

MEM_A_CS_L<1..0>

MEM_CTLMEM_40S

MEM_A_CTL

MEM_A_ODT<0>

MEM_A_DQBYTE2

MEM_40S MEM_A_DQBYTE_2

MEM_A_DQ<23..16>

MEM_A_DQS3

MEM_70D

MEM_A_DQS_3

MEM_A_DQS_P<3>

MEM_A_DQS2

MEM_70D

MEM_A_DQS_2

MEM_A_DQS_P<2>

MEM_A_DQBYTE5

MEM_A_DQBYTE_5MEM_40S

MEM_A_DQ<47..40>

MEM_CLKMEM_70D

MEM_A_CLK1

MEM_A_CLK_N<1>

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_A_DQS_6

MEM_70D

MEM_A_DQS1

MEM_A_DQS_1

MEM_70D

MEM_A_DQS_N<1>

MEM_A_DQS0

MEM_70D

MEM_A_DQS_0

MEM_A_DQS_N<0>

MEM_A_DQBYTE1

MEM_40S MEM_A_DQBYTE_1

MEM_A_DQ<15..8>

MEM_A_DQBYTE_0MEM_40S

MEM_A_DQBYTE0

MEM_A_DQ<7..0>

MEM_CMDMEM_40S

MEM_A_CMD0

MEM_A_CAA<9..0>

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D

MEM_A_DQS_3

MEM_A_DQS4

MEM_70D

MEM_A_DQS_4

MEM_A_DQS_P<4> MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_70D

MEM_A_DQS_4

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_70D

MEM_A_DQS_0

MEM_A_DQ<31..24>

MEM_A_DQBYTE3

MEM_40S MEM_A_DQBYTE_3

MEM_A_DQS5

MEM_70D

MEM_A_DQS_5

MEM_A_DQS_P<5>

MEM_70D

MEM_A_DQS5

MEM_A_DQS_5

MEM_A_DQS_N<5>

MEM_CLKMEM_70D

MEM_B_CLK1

MEM_B_CLK_N<1>

MEM_40S MEM_CMD

MEM_B_CKE<1..0>

MEM_B_CKE0

MEM_B_CMD0

MEM_CMDMEM_40S

MEM_B_CAA<9..0>

MEM_40S MEM_CMD

MEM_B_CMD1

MEM_B_CAB<9..0>

MEM_B_DQBYTE_0

MEM_B_DQBYTE0

MEM_40S

MEM_B_DQ<7..0>

MEM_B_CLK_P<1>

MEM_B_CLK1

MEM_70D MEM_CLK

dvt1

051-1573

8.0.0

114 OF 120

76 OF 82

7

70

7

70

7

70

7

70 71

7

70 71

68 71

7

70

7

70

7

19

7

22 23 24

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70 71

7

70 71

7

70 71

7

22 24

68 71

7 19

7

19

7

70

7

70

7

70 71

68

7

20 24

7

20 24

7

20 24

7

21 24

21 24 70

7

70

7

70

7

22 24

7

70

7

70 71

7

70 71

7

70 71

7

70

7

23 24

7

70 71

22 23 24 70

7

70

20 21 68

22 23 68

20 21 68

68

7

21 24

7

20 21 24

20 21 24 70

7

70 71

7

70

7

70

7

70 71

7

21 24

7

70

7

70

7

70

7

70 71

7

70 71

20 24 70

7

70

7

70

7

70

7

70

7

70 71

7

70

7

70

7

23 24

7

22 24

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23 24 70

7

70 71

7

23 24

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Thunderbolt, DP, HDMI Net Properties

SPACING

to save routing space.

Notes:

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

DisplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

DisplayPort & HDMI Constraints

PHYSICAL

NET TYPE

ELECTRICAL CONST SET

Only used on hosts supporting Thunderbolt video-in

SPACING

PHYSICAL

NET TYPE

ELECTRICAL CONST SET

TBTDP_RX/TX because it’s not high speed, and

AUX and DDC was removed from DISPLAYPORT or

Thunderbolt & DisplayPort Constraints

Thunderbolt SPI Signal Constraints

Thunderbolt, DP, HDMI Constraints

Only used on dual-port hosts.

I308

I309

I310

I311

I312

I313

I314

I315

I316

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

I357

I358

I359

I360

SYNC_DATE=12/06/2013

TBT,DP,HDMI Constraints

SYNC_MASTER=GKOO_J52

*

=4x_DIELECTRIC

?

DP_2OTHER

* ?

HDMICLK_2DPHDMI

=4x_DIELECTRIC

*

=3x_DIELECTRIC

?

HDMIDATA_2SAME

*

=4x_DIELECTRIC

?

HDMIDATA_2OTHER

DP_2SAME

*

=SAME

DISPLAYPORT

DP_2SAME

*

TBTDP_TX

DISPLAYPORT

TBTDP_TX

*_RX

*

TBTDP_TXRX

HDMI_CLK

HDMI_DATA

*

HDMICLK_2DPHDMI

=6x_DIELECTRIC

?

TOP,BOTTOM

HDMIDATA_2OTHER

HDMI_DATA

**

HDMIDATA_2OTHER

HDMI_DATA

=SAME

*

HDMIDATA_2SAME

TOP,BOTTOM

=4x_DIELECTRIC

?

HDMIDATA_2SAME

TBT_SPI_45S

=45_OHM_SE*=45_OHM_SE =45_OHM_SE =45_OHM_SE

=STANDARD =STANDARD

TBTDP_TXRX

*

TBTDP_RX

DISPLAYPORT

HDMI_CLK

DISPLAYPORT

*

HDMICLK_2DPHDMI

HDMI_CLK TBTDP_TX

*

HDMICLK_2DPHDMI

HDMI_CLK

**

HDMICLK_2OTHER

DP_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

?

DP_2SAME

TOP,BOTTOM

=4x_DIELECTRIC

?

DP_2SAME

*

=3x_DIELECTRIC

?

TBTDP_*

**

TBTDP_2OTHER

?

=4X_DIELECTRIC

*

TBTDP_2OTHER

?

=3X_DIELECTRIC

*

TBTDP_2SAME

TOP,BOTTOM

=10x_DIELECTRIC

?

HDMICLK_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

?

HDMICLK_2DPHDMI

?

=2x_DIELECTRIC

*

TBT_SPI

?

=6X_DIELECTRIC

*

TBTDP_TXRX

*

=7x_DIELECTRIC

?

HDMICLK_2OTHER

**

DISPLAYPORT

DP_2OTHER

*

HDMI_DATA

DP_2SAME

DISPLAYPORT

HDMI_DATA

TBTDP_RX

*

TBTDP_TXRX

HDMI_DATA

TBTDP_TX

*

HDMIDATA_2SAME

TBTDP_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

=6X_DIELECTRIC

TOP,BOTTOM

TBTDP_2OTHER

?

=10X_DIELECTRIC

?

TOP,BOTTOMTBTDP_TXRX

=4x_DIELECTRIC

?

TOP,BOTTOM

TBTDP_2SAME

TBTDP_*

=SAME

*

TBTDP_2SAME

TBTDP_RX

*_TX

*

TBTDP_TXRX

DP_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

HDMI_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

DP_INT_ML_C_P<3..0>

DP_85D

DP_INT_ML

DISPLAYPORT

DP_INT_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_ML_F_N<3..0>

DP_TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML

DISPLAYPORT

DP_TBTSNK1_ML_N<3..0>

DP_85D

DP_TBTSNK1_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML

DP_85D

DP_TBTSNK1_ML_C_N<3..0>

DISPLAYPORT

DP_TBTSNK1_ML

DP_85D

DP_TBTSNK0_AUXCH_N

DP_TBTSNK_AUXCH

DISPLAYPORT

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_ML

DP_85D

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK_AUXCH

DP_TBTSNK0_AUXCH_P

DP_85D

DP_TBTSNK_AUXCH

DP_TBTSNK0_AUXCH_C_P

DP_85D

DP_TBTSNK_AUXCH

DISPLAYPORT

DP_TBTSNK0_ML

DP_TBTSNK0_ML_N<3..0>

DP_85D

DP_TBTSNK0_ML_P<3..0>

DP_TBTSNK0_ML

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_N<3..0>

DP_85D

DP_TBTSNK0_ML

DISPLAYPORT

DP_TBTSNK0_ML_C_P<3..0>

DP_TBTSNK0_ML

DISPLAYPORT

DP_85D

DP_INT_AUXCH

DP_INT_AUXCH_C_N

DP_85D

DP_INT_AUXCH

DP_INT_AUXCH_C_P

DP_85D

DP_INT_AUXCH

DP_INT_AUX_P

DP_85D

DP_INT_AUXCH

DP_INT_AUX_N

DP_INT_ML

DP_85D

DP_INT_ML_N<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_ML_P<3..0>

DP_INT_ML

TBT_B_R2D_C_N<1..0>

TBT_B_R2D

TBTDP_TX

TBTDP_85D

DP_TBTPB_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_TBTPA_ML_C_P<1>

DISPLAYPORT

DP_85D

DP_A_LSX_ML

DISPLAYPORT

DP_85D

DP_A_LSX_ML

DP_A_LSX_ML_N<1>

DISPLAYPORT

DP_85D

DP_A_LSX_ML

DP_TBTPA_ML_P<1>

DP_TBTPA_ML_C_N<1>

DISPLAYPORT

DP_85D

DP_A_LSX_ML

DP_TBTPA_ML DISPLAYPORT

DP_85D

DP_TBTPA_ML_N<3>

TBT_A_D2R_C_N<1>

TBTDP_RX

TBTDP_85D

TBT_A_D2R_1

TBT_A_D2R_0

TBTDP_RX

TBTDP_85D

TBT_A_D2R_N<0> TBT_A_D2R_C_P<1>

TBT_A_D2R_1

TBTDP_RX

TBTDP_85D

TBT_A_D2R_P<0>

TBTDP_RX

TBTDP_85D

TBT_A_D2R_0

TBT_A_D2R_C_P<0>

TBT_A_D2R_0

TBTDP_RX

TBTDP_85D

TBT_A_D2R_C_N<0>

TBT_A_D2R_0

TBTDP_RX

TBTDP_85D

DP_TBTPA_ML_P<3>

DP_TBTPA_ML DISPLAYPORT

DP_85D

DP_TBTPA_ML_C_N<3>

DISPLAYPORT

DP_85D

DP_TBTPA_ML

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML DISPLAYPORT

DP_85D

TBT_A_R2D_C_P<1..0>

TBT_A_R2D

TBTDP_TX

TBTDP_85D

DP_85D

DISPLAYPORT

DP_A_LSX_ML_P<1>

DP_A_LSX_ML

DP_85D

DISPLAYPORTDP_A_LSX_ML

DP_TBTPA_ML_N<1>

TBT_A_R2D_N<1..0>

TBTDP_TX

TBTDP_85DTBT_A_R2D

DP_TBTPA_AUXCH_C_N

DP_85D

DP_TBTPA_AUXCH

DP_TBTPB_AUXCH_P

DP_85D

DP_TBTPB_AUXCH

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R_1

TBTDP_85D

TBTDP_RX

TBT_B_D2R_N<1>

TBT_B_D2R_1

TBTDP_RX

TBTDP_85D

TBT_B_D2R_C_N<1>

TBT_B_D2R_1

TBTDP_RX

TBTDP_85D

TBT_B_D2R_C_P<1>

TBTDP_RX

TBT_B_D2R_1

TBTDP_85D

TBT_B_D2R_N<0>

TBT_B_D2R_0

TBTDP_RX

TBTDP_85D

TBT_B_D2R_0

TBTDP_RX

TBTDP_85D

TBT_B_D2R_C_N<0>

TBT_B_D2R_C_P<0>

TBTDP_RX

TBTDP_85D

TBT_B_D2R_0

DP_TBTPB_ML_C_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_TBTPB_ML_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_TBTPA_AUXCH_N

DP_85D

DP_TBTPA_AUXCH

DP_TBTPA_AUXCH_C_P

DP_85D

DP_TBTPA_AUXCH

TBT_A_D2R_N<1>

TBT_A_D2R_1

TBTDP_RX

TBTDP_85D

TBT_A_D2R_P<1>

TBT_A_D2R_1

TBTDP_RX

TBTDP_85D

DP_B_LSX_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_B_LSX_ML_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

TBT_B_R2D_C_P<1..0>

TBT_B_R2D

TBTDP_TX

TBTDP_85D

DP_HDMI_TBT_ML_N<3..0>

DP_85D

DP_HDMI_TBT_ML

DISPLAYPORT

DP_85D

DP_HDMI_TBT_ML

DP_HDMI_TBT_ML_P<3..0>

TBT_SPI_MISO

TBT_SPI

TBT_SPI_45S

SPI_TBT_MISO

DISPLAYPORT

DP_85D

DP_TBTSRC_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_TBTSRC_AUXCH_C_P

HDMI_IG_DATA_C_N<2..0>

HDMI_DATA HDMI_DATA

HDMI_85D

HDMI_IG_DATA_C_P<2..0>

HDMI_DATA HDMI_DATA

HDMI_85D

HDMI_IG_CLK_C_N

HDMI_CLOCK

HDMI_CLKHDMI_85D

HDMI_IG_CLK_C_P

HDMI_CLOCK

HDMI_CLKHDMI_85D

TBT_SPI

TBT_SPI_45S

TBT_SPI_CLK

SPI_TBT_CLK

DISPLAYPORT

DP_85D

DP_TBTSRC_ML_C_N<3..0>

DP_HDMI_TBT_AUX_P

DP_85D

DP_HDMI_TBT_AUX

DP_HDMI_TBT_AUX_N

DP_85D

DP_HDMI_TBT_AUX

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R_1

TBTDP_RX

TBTDP_85D

DP_TBTPB_ML DISPLAYPORT

DP_85D

DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

DP_TBTPB_ML

DP_85D

DISPLAYPORT

TBT_A_R2D_C_N<1..0>

TBT_A_R2D

TBTDP_TX

TBTDP_85D

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML DISPLAYPORT

DP_85D

DP_TBTPA_AUXCH

DP_TBTPA_AUXCH_P

TBT_B_R2D TBTDP_85D

TBTDP_TX

TBT_B_R2D_N<1..0>

DP_TBTSRC_ML_C_P<3..0>

DISPLAYPORT

DP_85D

TBT_SPI_MOSI

TBT_SPI

TBT_SPI_45S

SPI_TBT_MOSI

TBT_SPI_CS_L

TBT_SPI

TBT_SPI_45S

SPI_TBT_CS_L

TBT_A_D2R1_AUXDDC_P

TBTDP_RX

TBTDP_85D

TBT_A_D2R_1

TBT_A_R2D_P<1..0>

TBT_A_R2D

TBTDP_TX

TBTDP_85D

DP_TBTPB_AUXCH_C_P

DP_85D

DP_TBTPB_AUXCH

TBT_B_R2D_P<1..0>

TBT_B_R2D

TBTDP_TX

TBTDP_85D

DP_TBTPB_ML_C_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

TBT_B_D2R_P<0>

TBT_B_D2R_0

TBTDP_RX

TBTDP_85D

DP_TBTSNK1_AUXCH_P

DP_85D

DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_N

DP_TBTSNK_AUXCH

DP_85D

DP_TBTSNK1_AUXCH_C_N

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML

DP_85D

DISPLAYPORT

TBT_B_D2R_P<1>

TBT_B_D2R_1

TBTDP_RX

TBTDP_85D

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R_1

TBTDP_85D

TBTDP_RX

DP_TBTPB_AUXCH_C_N

DP_85D

DP_TBTPB_AUXCH

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH

DP_85D

DISPLAYPORT

DP_INT_ML

DP_85D

DP_INT_ML_F_P<3..0>

dvt1

051-1573

8.0.0

115 OF 120

77 OF 82

5

65

5

65

25 67

25

25 67

25

25 67

13 25

25

13 25

25

5

25

5

25

5

65

5

65

65 71

25 29 71

29

25 28

28

25 28

28

28 71

25 28 71

28 71

25 28 71

28 71

28

25 28

25 28 71

28

28 71

25 28

29

25 29 71

29 71

25 29 71

29 71

25 29

29

28

25 28

25 28 71

29

25 29 71

67 69

25

66 67 71

25

67 69

28

29

25 28 71

25 29

28

29 71

25

28

28 71

25 29

29 71

25 29

25 29 71

25

25 67

25 29

25 29 71

29

25 29

29

65

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Memory to GND Spacing

MIPI Interface Constraints

Memory Bus Constraints

Spacing Rule Sets

Memory to Power Spacing

Memory Bus Spacing Group Assignments

Camera Net Properties

SPACING

NET TYPE

PHYSICAL

ELECTRICAL CONST SET

I149

S2_2OTHERMEM

TOP,BOTTOM

=6x_DIELECTRIC

?

S2_2OTHERMEM

*

=4x_DIELECTRIC

?

S2MEM_2GND

*

S2_MEM_*

GND

MIPI_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

=4X_DIELECTRIC

?*

MIPI_2OTHER

=6X_DIELECTRIC

?*

MIPI_2CLK

S2_MEM_45S

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

=STANDARD=STANDARD

=45_OHM_SE

S2_MEM_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

=2x_DIELECTRIC

?

S2_DQS2OWNDATA

S2_CMD2CTRL

*

=2x_DIELECTRIC

?

S2MEM_2OTHER

TOP,BOTTOM=10x_DIELECTRIC

?

S2MEM_2PWR TOP,BOTTOM

=4x_DIELECTRIC

?

S2_CMD2CTRL

TOP,BOTTOM

=4x_DIELECTRIC

?

=10X_DIELECTRICTOP,BOTTOM

MIPICLK_2OTHER

?

=8X_DIELECTRIC

TOP,BOTTOM

MIPI_2CLK

?

=6X_DIELECTRIC

TOP,BOTTOM

MIPI_2OTHER

S2_DATA2SELF

TOP,BOTTOM

=4x_DIELECTRIC

?

TOP,BOTTOM

=4x_DIELECTRIC

?

S2_DQS2OWNDATA

S2_CMD2CMD TOP,BOTTOM

=4x_DIELECTRIC

?

S2MEM_2GND TOP,BOTTOM

=4x_DIELECTRIC

?

S2_CTRL2CTRL

TOP,BOTTOM

=4x_DIELECTRIC

?

S2_CMD2CMD

*

=2x_DIELECTRIC

?

S2_CTRL2CTRL

*

=2x_DIELECTRIC

?

S2MEM_2PWR

*

=2x_DIELECTRIC

?

S2_MEM_CMD

S2_MEM_CTRL

*

S2_CMD2CTRL

S2_MEM_DQS*

**

S2MEM_2OTHER

S2_MEM_DATA*

**

S2MEM_2OTHER

S2_MEM_DATA*

=SAME

*

S2_DATA2SELF

S2_MEM_PWR

S2_MEM_*

*

S2MEM_2PWR

S2_MEM_PWR

**

DEFAULT

S2_MEM_DQS0

S2_MEM_DATA0

*

S2_DQS2OWNDATA

S2_MEM_CMD

**

S2MEM_2OTHER

S2_MEM_CTRL

**

S2MEM_2OTHER

S2_MEM_CLK

**

S2MEM_2OTHER

S2_MEM_CMD

*

S2_CMD2CMD

S2_MEM_CTRL S2_MEM_CTRL

*

S2_CTRL2CTRL

S2_MEM_* S2_MEM_*

*

S2_2OTHERMEM

MIPI_DATA

CLK_MIPI

*

MIPI_2CLK

MIPI_DATA

**

MIPI_2OTHER

=7X_DIELECTRIC

?*

MIPICLK_2OTHER

S2_MEM_DQS1

S2_MEM_DATA1

*

S2_DQS2OWNDATA

S2_DATA2SELF

*

=2x_DIELECTRIC

?

CLK_MIPI

**

MIPICLK_2OTHER

S2MEM_2GND

*

=2x_DIELECTRIC

?

S2MEM_2OTHER

*

=6x_DIELECTRIC

?

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/09/2013

Camera Constraints

MIPI_CLK_P

CLK_MIPIMIPI_85D

MIPI_CLK_S2

MIPI_DATA

MIPI_85D

MIPI_DATA_CONN_P

MIPI_DATA_S2

S2_MEM_DQS1 S2_MEM_DQS1

S2_MEM_85D

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

S2_MEM_DQS1 S2_MEM_DQS1

S2_MEM_85D

MIPI_CLK_N

CLK_MIPIMIPI_85D

MIPI_CLK_S2

MEM_CAM_BA<2>

S2_MEM_CMD S2_MEM_CMDS2_MEM_45S

MEM_CAM_BA<0>

S2_MEM_CMD S2_MEM_CMDS2_MEM_45S

MEM_CAM_CS_L

S2_MEM_CTRL

S2_MEM_45S

S2_MEM_CS

MEM_CAM_CLK_N

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

MEM_CAM_WE_L

S2_MEM_CMD S2_MEM_CMDS2_MEM_45S

MEM_CAM_RAS_L

S2_MEM_CMD

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_CKE

S2_MEM_CTRL

S2_MEM_45SS2_MEM_CKE

MEM_CAM_CAS_L

S2_MEM_CMD

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_ODT

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_CLK_P

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

MEM_CAM_BA<1>

S2_MEM_CMD S2_MEM_CMDS2_MEM_45S

MEM_CAM_DM<0>

S2_MEM_DATA_0

S2_MEM_DATA0

S2_MEM_45S

MEM_CAM_DQS_P<0>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DQS0

MEM_CAM_DQS_N<0>

S2_MEM_DQS0 S2_MEM_DQS0

S2_MEM_85D

S2_MEM_PWR

PP0V675_MEM_CAM_VREFDQ

MIPI_CLK_CONN_N

CLK_MIPIMIPI_85D

MIPI_CLK_S2

MIPI_CLK_CONN_P

CLK_MIPIMIPI_85D

MIPI_CLK_S2

MIPI_DATA_S2 MIPI_85D

MIPI_DATA

MIPI_DATA_N

MIPI_DATA

MIPI_85DMIPI_DATA_S2

MIPI_DATA_P

S2_MEM_DATA_0

S2_MEM_DATA0

S2_MEM_45S

MEM_CAM_DQ<7..0>

S2_MEM_DATA_1

S2_MEM_DATA1

S2_MEM_45S

MEM_CAM_DQ<15..8>

MEM_CAM_DM<1>

S2_MEM_DATA1

S2_MEM_45S

S2_MEM_DATA_1

MIPI_DATA_CONN_N

MIPI_DATA

MIPI_85DMIPI_DATA_S2

PP1V35_CAM

S2_MEM_PWR

PP0V675_CAM_VREF

S2_MEM_PWR S2_MEM_PWR

PP0V675_MEM_CAM_VREFCA

S2_MEM_CMDS2_MEM_45S

S2_MEM_A

MEM_CAM_A<14..0>

dvt1

051-1573

8.0.0

116 OF 120

78 OF 82

33 34 71

34 71

33 34

33 34 71

33 34

34

33 34

34

34 71

33 34 71

33 34

34 71

33 34

34

33 34

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC SMBus & Charger Net Properties

ELECTRICAL CONST SET

NET TYPE

PHYSICAL

SPACING

SMC Constraints

SYNC_DATE=01/02/2013

SYNC_MASTER=YHARTANTO_J44

SMB_45S

SMBUS_SMC_1_S0_SCL

SMB

SMBUS_SMC_1

SMB_45S

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1

SMBUS_SMC_3_SCL

SMB

SMB_45S

SMBUS_SMC_3

SMBUS_SMC_5_G3_SDA

SMB

SMB_45S

SMBUS_SMC_5

SMBUS_SMC_0_S0_SDA

SMB

SMB_45S

SMBUS_SMC_0

SMBUS_SMC_2_S3_SCL

SMB

SMB_45S

SMBUS_SMC_2

SMBUS_SMC_2_S3_SDA

SMB

SMB_45S

SMBUS_SMC_2

SMBUS_SMC_0_S0_SCL

SMB

SMB_45S

SMBUS_SMC_0

SMB

SMB_45S

SMBUS_SMC_5

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_3_SDA

SMB

SMB_45S

SMBUS_SMC_3

dvt1

051-1573

8.0.0

117 OF 120

79 OF 82

38 41 71

38 41

38 41 71

38 41

38 41 71

38 41

38 41 71

38 41

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

ELECTRICAL CONST SET

PHYSICAL

NET TYPE

X304 Specific Net Properties

ELECTRICAL CONST SET

PHYSICAL

SPACING

DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS

SPACING

The signals below have no topologies assigned.

X304 Specific Net Properties

NET TYPE

MEM_40S

*

0.090 MM

100 MIL

CLK_PCIE_85D

BGA

P65_BGA

HDMI_85D

BGA

P65_BGA

PCIE_85D

BGA

P65_BGA

BGADP_85D

P65_BGA

GND_P2MM

*

0.20 MM

1000

PWR_P2MM

*

0.20 MM

1000

GND

*

=STANDARD

?

THERM_45STHERM_45S

*

SB_POWER

SATA_*

*

PWR_P2MM

USB

SB_POWER

*

PWR_P2MM

CLK_PCIE SB_POWER

*

PWR_P2MM

GND_P2MM

*

GND PCIE_*

AUDIO

*

=2X_DIELECTRIC

?

THERM

*

=2X_DIELECTRIC

?

SENSE

*

=2X_DIELECTRIC

?

DIG_AUDIO

*

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

0.1 MM 0.1 MM

ANL_AUDIO_WIDE

*

=1TO1_DIFFPAIR

0.3 MM 0.3 MM

10 MM

0.1 MM 0.1 MM

THERM_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE =45_OHM_SE =45_OHM_SE

0.1 MM 0.1 MM

SENSE_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE =45_OHM_SE =45_OHM_SE

0.1 MM 0.1 MM

CLK_PCIE

GND

*

GND_P2MM

GND

CPU_VCCSENSE

*

GND_P2MM

ANL_AUDIO

*

ANL_AUDIO

DIG_AUDIO

*

DIG_AUDIO

SENSE_45SSENSE_45S

*

Project Specific Constraints

SYNC_DATE=01/04/2013

SYNC_MASTER=YHARTANTO_J44

ANL_AUDIO

*

=1TO1_DIFFPAIR

0.1 MM 0.1 MM

10 MM

0.1 MM 0.1 MM

MEM_45S

*

0.070 MM

100 MIL

MEM_72D

*

0.090 MM

100 MIL

MEM_85D

*

0.090 MM

100 MIL

PCIE_85D

*

0.090 MM

10 MM

USB_85D

TOP

0.100 MM

500 MIL

0.230 MM

CPU_27P4S BOTTOM

100 MIL

USB3_85D

TOP

0.100 MM

500 MIL

USB3_85D

ISL10

0.075 MM 0.090 MM

DP_85D

ISL9

0.090 MM0.075 MM

PCIE_85D

ISL10

0.075 MM 0.090 MM

USB

GND *

GND_P2MM

GND SATA_*

*

GND_P2MM

SENSE_45S

SENSE

SENSE_DP

ISNS_1V05_S0_N

SENSE_DP

SENSE_45S

SENSE

ISNS_TPAD_P

SENSE_DP

SENSE_45S

SENSE

ISNS_TPAD_N

SENSE_DP

SENSE

SENSE_45S

ISNS_1V8_S3_P

SENSE

SENSE_DP

SENSE_45S

ISNS_1V8_S3_N

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_HP_PORT_REFCH

ISNS_LCDPANEL_N

SENSE_DP

SENSE

SENSE_45S

SENSE_DP_CPUVR

SENSE

CPUVR_ISNS_R_N

ISNS_LCDBKLT_N

SENSE_DP_LCDBKLT

SENSE

SENSE_45S

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

HS_MIC_P

AUDIO_DP_MIC

AUDIO

AUD_CONN_SLEEVE_XW

ANL_AUDIO_WIDE

AUDIO_DP_SPKSUB

DIG_AUDIO

AUDIO

SPKRCONN_SR_OUT_P

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_LO3_R_N

SENSE_45S

SENSE

SENSE_DP

ISNS_PP3V3S0_P

SB_POWER

PP3V3_S0

SENSE_45S

ISNS_CPUHIGAIN_R_P

SENSE

SENSE_DP_CPUHIGN

CPUVR_ISNS1_P

DP_NO_TOPOLOGY

SENSE

SENSE_45S

ISNS_CPUHIGAIN_R_N

SENSE

SENSE_45S

SENSE_DP_CPUHIGN

DP_NO_TOPOLOGY

SENSE_45S

SENSE

CPUVR_ISNS2_N

DP_NO_TOPOLOGY

SENSE_45S

SENSE

CPUVR_ISNS2_P

CPUVR_ISNS1_N

DP_NO_TOPOLOGY

SENSE

SENSE_45S

CHGR_CSO_R_P

SENSE_45S

SENSE_DP_CHGR_CSO

SENSE

SENSE_45S

CHGR_CSI_R_P

SENSE

SENSE_DP_CHGR_CSI

SENSE_45S

SENSE

SENSE_DP_CPUHIGN

ISNS_CPUHIGAIN_N

SENSE_45S

ISNS_PP5VS0_N

SENSE

SENSE_DP

ISNS_PP5VS0_P

SENSE_45S

SENSE

SENSE_DP

SENSE

CHGR_CSI_P

SENSE_45S

SENSE_DP_CHGR_CSI

SENSE_45S

CHGR_CSI_N

SENSE

SENSE_DP_CHGR_CSI

SENSE_45S

SENSE

SENSE_DP_CPUHIGN

ISNS_CPUHIGAIN_P

SENSE_DP_CHGR_CSI

CHGR_CSI_R_N

SENSE_45S

SENSE

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

CODEC_HS_MIC_N

AUDIO_DP_MIC

AUDIO

AUD_CONN_RING2

ANL_AUDIO_WIDE

SENSE_DP

SENSE

SENSE_45S

ISNS_1V05_S0_P

THERM_DP_CPU_D2

THERM_45S

THERM

CPUTHMSNS_D2_P

THERM_DP_CPU_D1

THERM_45S

THERM

CPUTHMSNS_D1_N

THERM_DP_CPU_D1

THERM_45S

THERM

CPUTHMSNS_D1_P

THERM_DP_CPU_D2

THERM_45S

THERM

CPUTHMSNS_D2_N

THERM_DP_TBT_D1

THERM

TBTTHMSNS_D1_N

THERM_45S

THERM_DP_TBT_D1

THERM

TBTTHMSNS_D1_P

THERM_45S

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_CH_HS_GND

DIG_AUDIO

AUDIO_DP_SPKTWT

SPKRCONN_R_OUT_P

AUDIO

AUDIO_DP_SPKTWT

DIG_AUDIO

AUDIO

SPKRCONN_R_OUT_N

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_LO3_L_N

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_SPKRAMP_LSUBIN_N

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

LSUBIN_P

DIG_AUDIO

AUDIO

SPKRCONN_SL_OUT_N

AUDIO_DP_SPKSUB

AUDIO

AUDIO_DP_AMPSUB

ANL_AUDIO

RSUBIN_N

AUDIO_DP_AMPSUB

ANL_AUDIO

RSUBIN_P

AUDIO

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_SPKRAMP_RSUBIN_P

ANL_AUDIO

AUDIO

LSUBIN_N

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_SPKRAMP_LSUBIN_P

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_LO3_L_P

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

AUD_SPKRAMP_RIN_N

ANL_AUDIO

AUDIO_DP_AMPTWT

AUDIO

AUD_LO2_R_P

AUDIO

AUDIO_DP_AMPTWT

ANL_AUDIO

AUD_SPKRAMP_LIN_N

ANL_AUDIO

AUDIO

AUD_LO2_L_N

AUDIO_DP_AMPTWT

AUDIO_DP_SPKSUB

DIG_AUDIO

AUDIO

SPKRCONN_SL_OUT_P

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

CODEC_HS_MIC_P

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_CONN_SLEEVE

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_CONN_HS_MIC_P

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_HS_MIC_P

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_CONN_HS_MIC_N

AUDIO_DP_MIC

AUDIO

AUD_HP_PORT_REFUS

ANL_AUDIO_WIDE

AUDIO

HS_MIC_N

AUDIO_DP_MIC

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_SPKRAMP_RSUBIN_N

AUDIO_DP_AMPSUB

ANL_AUDIO

AUDIO

AUD_LO3_R_P

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

AUD_LO2_L_P

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_CONN_RING2_XW

AUDIO_DP_MIC

AUDIO

AUD_HS_MIC_N

ANL_AUDIO_WIDE

AUDIO_DP_MIC

ANL_AUDIO_WIDE

AUDIO

AUD_US_HS_GND

SB_POWER

PP3V3_S5

SENSE_DP_CHGR_CSO

SENSE_45S

CHGR_CSO_R_N

SENSE

SENSE_DP_CHGR_CSO

CHGR_CSO_N

SENSE_45S

SENSE

SENSE_DP_CHGR_CSO

SENSE_45S

SENSE

CHGR_CSO_P

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

SPKRAMP_RIN_N

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

SPKRAMP_RIN_P

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

AUD_SPKRAMP_RIN_P

ANL_AUDIO

AUDIO_DP_AMPTWT

AUDIO

AUD_LO2_R_N

AUDIO_DP_AMPTWT

ANL_AUDIO

AUDIO

SPKRAMP_LIN_N

AUDIO

ANL_AUDIO

SPKRAMP_LIN_P

AUDIO_DP_AMPTWT

AUDIO_DP_SPKTWT

DIG_AUDIO

AUDIO

SPKRCONN_L_OUT_N

DIG_AUDIO

AUDIO

SPKRCONN_L_OUT_P

AUDIO_DP_SPKTWT

DIG_AUDIO

AUDIO

SPKRCONN_SR_OUT_N

AUDIO_DP_SPKSUB

ANL_AUDIO

AUDIO

AUD_SPKRAMP_LIN_P

AUDIO_DP_AMPTWT

SENSE_DP_CPUVR

SENSE

SENSE_45S

CPUVR_ISNS_P

ISNS_TBT_N

SENSE_DP_TBT

SENSE_45S

SENSE

SENSE_DP

SENSE_45S

SENSE

ISNS_SSD_P

ISNS_CPUDDR_P

SENSE_45S

SENSE

SENSE_DP

SENSE_45S

SENSE

ISNS_SSD_N

ISNS_LCDBKLT_P

SENSE_DP_LCDBKLT

SENSE

SENSE_45S

ISNS_LCDPANEL_P

SENSE

SENSE_DP

SENSE_45S

SENSE

SENSE_DP

SENSE_45S

ISNS_HS_OTHER3V3_P

SENSE

SENSE_DP

SENSE_45S

ISNS_HS_OTHER5V_N

SENSE

SENSE_DP

SENSE_45S

ISNS_HS_OTHER5V_P

ISNS_TBT_P

SENSE

SENSE_DP_TBT

SENSE_45S

ISNS_CPUDDR_N

SENSE_45S

SENSE

SENSE_DP

SENSE_45S

SENSE

ISNS_PP3V3S0_N

SENSE

SENSE_DP_CPUVR

SENSE_45S

CPUVR_ISNS_R_P

SENSE_DP_CPUVR

SENSE

SENSE_45S

CPUVR_ISNS_N

SENSE

SENSE_DP

SENSE_45S

ISNS_HS_OTHER3V3_N

SENSE

SENSE_45S

ISNS_HS_COMPUTING_N

SENSE

SENSE_45S

ISNS_HS_COMPUTING_P

GND

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42

43 61

48 52

44 65

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42 60

48 51

51 52

50 52 71

48 50

43

68 71

44

43 56

44

43 56

44 54

54

44 45

43

54

44 45

54

48

52

43 59

45

48 52

50 52 71

48 50

50

50 52 71

50

48 50

50

48 50

50

48 50

50 52 71

48

52

51 52

48 52

48 51

50

48 50

51 52

48 52

68 71

44 54

54

50

48 50

50

50 52 71

50

43

44

43

42 60

44 65

42

44

43

42

42 44

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

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C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PCI Express Properties

PCI Express Constraints

SPACING

PHYSICAL

NET TYPE

ELECTRICAL CONST SET

I302

I303

I304

I305

SYNC_MASTER=YHARTANTO_J44

SYNC_DATE=01/13/2013

PCIe Constraints

=85_OHM_DIFF

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFFCLK_PCIE_85D

=4X_DIELECTRIC

?

TOP,BOTTOMPCIE_2SAME

=10X_DIELECTRIC

?

TOP,BOTTOM

PCIECLK_2OTHER

*?

PCIE_2SAME

=3X_DIELECTRIC

*?

=6X_DIELECTRIC

PCIE_TXRX

PCIE_2OTHER

*?

=4X_DIELECTRIC

PCIE_2CLK

*?

=7X_DIELECTRIC

*?

PCIECLK_2OTHER

=7X_DIELECTRIC

=6X_DIELECTRIC

?

TOP,BOTTOM

PCIE_2OTHER

=10X_DIELECTRIC

?

PCIE_2CLK

TOP,BOTTOM

PCIE_RX

*_TX

PCIE_TXRX

*

=10X_DIELECTRIC

?

PCIE_TXRX

TOP,BOTTOM

*

PCIE_*

*

PCIE_2OTHER

PCIE_*

CLK_*

PCIE_2CLK

*

=SAME

*

PCIE_2SAME

PCIE_*

PCIE_TX

*_RX

PCIE_TXRX

*

CLK_PCIE

**

PCIECLK_2OTHER

PCIE_CLK100M_SSD

CLK_PCIE_85D

PCIE_CLK100M_SSD_RC1_N

CLK_PCIE

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD

CLK_PCIE_85D

PCIE_CLK100M_CAMERA_C_N

CLK_PCIE

PCIE_CLK100M_CAM

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAM

CLK_PCIECLK_PCIE_85D

CLK_PCIE

PCIE_CLK100M_SSD_RC1_P

CLK_PCIE_85D

PCIE_CLK100M_SSD

CLK_PCIE

PCIE_CLK100M_SSD_N

CLK_PCIE_85D

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_TBT

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_TBT

PCIE_CAMERA_R2D

PCIE_85D

PCIE_TX

PCIE_CAMERA_R2D_C_N

PCIE_85D

PCIE_TX

PCIE_CAMERA_R2D

PCIE_CAMERA_R2D_C_P

PCIE_TX

PCIE_CAMERA_R2D

PCIE_85D

PCIE_CAMERA_R2D_N

PCIE_85D

PCIE_TX

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D

PCIE_CAMERA_D2R_C_N

PCIE_RX

PCIE_85D

PCIE_CAMERA_D2R

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP

PCIE_AP_D2R_N

PCIE_RX

PCIE_85D

PCIE_AP_D2R

PCIE_AP_D2R_P

PCIE_RX

PCIE_85D

PCIE_RX

PCIE_CAMERA_D2R

PCIE_CAMERA_D2R_N

PCIE_85D

PCIE_RX

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R

PCIE_SSD_D2R_P<3..1>

PCIE_SSD_D2R

PCIE_RX

PCIE_85D

PCIE_SSD_D2R_N<3..1>

PCIE_SSD_D2R

PCIE_RX

PCIE_85D

PCIE_SSD_D2R_PP

PCIE_SSD_D2R_P<0>

PCIE_85D

PCIE_RX

PCIE_SSD_D2R_PP

PCIE_SSD_D2R_N<0>

PCIE_85D

PCIE_RX

PCIE_SSD_R2D_P<3..0>

PCIE_TX

PCIE_85DPCIE_SSD_R2D

PCIE_SSD_R2D_C_P<3..0>

PCIE_TX

PCIE_85DPCIE_SSD_R2D

PCIE_SSD_R2D_C_N<3..0>

PCIE_TX

PCIE_85DPCIE_SSD_R2D

PCIE_85D

PCIE_TX

PCIE_SSD_R2D

PCIE_SSD_R2D_N<3..0>

PCIE_TBT_D2R_0

PCIE_TBT_D2R_P<0>

PCIE_RX

PCIE_85D

PCIE_TBT_D2R_0

PCIE_TBT_D2R_N<0>

PCIE_85D

PCIE_RX

PCIE_TBT_D2R_0 PCIE_RX

PCIE_85D

PCIE_TBT_D2R_C_P<0>

PCIE_85D

PCIE_RXPCIE_TBT_D2R_0

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R PCIE_85D

PCIE_RX

PCIE_TBT_D2R_P<3..1>

PCIE_TBT_D2R

PCIE_TBT_D2R_C_P<3..1>

PCIE_RX

PCIE_85D

PCIE_TBT_D2R PCIE_85D

PCIE_RX

PCIE_TBT_D2R_N<3..1>

PCIE_TBT_R2D PCIE_85D

PCIE_TX

PCIE_TBT_R2D_P<3..0>

PCIE_TBT_D2R_C_N<3..1>

PCIE_TBT_D2R PCIE_85D

PCIE_RX

PCIE_85D

PCIE_TX

PCIE_TBT_R2D

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D PCIE_85D

PCIE_TX

PCIE_TBT_R2D_C_N<3..0>

PCIE_85D

PCIE_TX

PCIE_TBT_R2D

PCIE_TBT_R2D_C_P<3..0>

PCIE_AP_R2D

PCIE_85D

PCIE_TX

PCIE_AP_R2D_P

PCIE_AP_R2D

PCIE_85D

PCIE_TX

PCIE_AP_R2D_N

PCIE_AP_R2D

PCIE_85D

PCIE_TX

PCIE_AP_R2D_C_N

PCIE_AP_R2D

PCIE_85D

PCIE_TX

PCIE_AP_R2D_C_P

PCIE_CAMERA_D2R_C_P

PCIE_85D

PCIE_RX

PCIE_CAMERA_D2R

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_SSD_RC2_N

PCIE_CLK100M_SSD

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP

CLK_PCIE_85D

PCIE_CLK100M_AP

CLK_PCIE

PCIE_CLK100M_AP_CONN_P

PCIE_CLK100M_AP_N

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_AP

PCIE_CLK100M_CAMERA_P

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_CAM

PCIE_CLK100M_CAMERA_N

CLK_PCIE

PCIE_CLK100M_CAM

CLK_PCIE_85D

PCIE_CLK100M_SSD_RC2_P

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_SSD

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32

12 32 71

12 25 71

14 34

33 34

66

14 66 71

14 34 71

12 32 71

32 71

12 32 71

32 71

14 25 71

25

14 25 71

25 71

14 25 71

25 71

14 25 71

66 71

14 66 71

33 34

32

12 66 71

66

12 66 71

12 34 71

32

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

<rdar://component/497591> MobileMac HW | Task

Other Info:

<rdar://component/497585> MobileMac HW | New Bugs

Kismet:

<rdar://component/497588> MobileMac HW | Layout <rdar://component/497590> MobileMac HW | Investigation

<rdar://component/497587> MobileMac HW | Schematic

Change List:

<rdar://component/497589> MobileMac HW | Architecture

MobileMac HW Radar:

Useful Wiki Links:

<RDAR://COMPONENT/XXXXXX> X304 HW EE SCHEMATIC | PROTO 0

AFP://KISMET.APPLE.COM/KISMET-PROJECTS/X304

Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions

SYNC_DATE=10/23/2012

SYNC_MASTER=J14

Reference

dvt1

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www.vinaﬁx.vn

Apple X304 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual