Apple X1782 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X1782 MLB SCHEMATIC

2 1

CK

ECNREV DESCRIPTION OF REVISION

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

APPD

DATE

2020-01-2400218246376 ENGINEERING RELEASED

D

1
2

1
2

4
4
5

5

6
6 7
7 8
8
9

9

10
10
11
12

12

13
13 14
14

15

TABLE OF CONTENTS
SYSTEM PCB SUMMARY
PD PARTS3
CPU GFX
CPU MISC/JTAG/CFG/RSVD
CPU LPDDR3 INTERFACE
CPU & PCH POWER
CPU & PCH GROUNDS
CPU CORE DECOUPLING
CPU GT DECOUPLING
PCH DECOUPLING
PCH AUDIO/LPC/SPI/SMBUS
PCH POWER MANAGEMENT
PCH PCIE/USB/CLKS

61
62
63
64

67 KEYBOARD & TRACKPAD 1
68
69
70

65 71

7266
67
68
69
7011

74 VR GT & GTX IMVP

76

77

78
71 79
72
73
74

80

81

82

KEYBOARD & TRACKPAD 2
BATTERY CONN, 3V3 G3H RTC VR
PBUS SUPPLY & BATTERY CHARGER
VR CORE & SA IMVP CTRL
VR CORE & SA IMVP

VR 5V, 3V3
VR EOPIO EDRAM
PMIC BUCKS AND SWS
PMIC LDOS
PMIC GPIOS & CONTROL
VR VDDQ VCCIO
POWER FETS

X1412_SHAN

05/17/2019

D

C

15
16
17
18
19
20

22
23
24
25
26
27
28

16
18
19
20
22
23
2421

26
27
28
29
30
31

PCH SPI/UART/GPIO
CPU/PCH MERGED XDP
CHIPSET SUPPORT 1
CHIPSET SUPPORT 2
LPDDR3 VREF MARGINING
LPDDR3 DRAM CHANNEL A (00-31)
LPDDR3 DRAM CHANNEL A (32-63)
LPDDR3 DRAM CHANNEL B (00-31)
LPDDR3 DRAM CHANNEL B (32-63)
LPDDR3 DRAM TERMINATION
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2
USB-C SUPPORT
USB-C PORT CONTROLLER A

75
76
77

84

85

86
78 87

8879
80

89 S4E<3>

9081
82
83
84
85
86
87
88

124

125

135

136

137 DESENSE 3

138

LCD BACKLIGHT DRIVER
EDP DISPLAY CONNECTOR
S4E<0>
S4E<1>
S4E<2>

C

OCARINA PMIC & NAND VCC VR & VDDIO1 SWCH
SSD SUPPORT9625
FCT
PROBE POINTS
DESENSE 1
DESENSE 2

DESENSE 4

B

29
30
31
32
33
34
35
36
37
38
39

32
33
36
37
38
39
40 SOC AOP/AON/SMC
41
42
43
44

4540
41 46
42

47

USB-C PORT CONTROLLER B
USB-C CONNECTOR A
WIFI/BT SUPPORT
WIFI/BT MODULE 1
WIFI/BT MODULE 2
SOC GPIO/SEP/USB/DDR/TEST

SOC ISP/I2C/UART/SPI/I2S
SOC PCIE
SOC POWER 1
SOC POWER 2
SOC POWER 3
SOC GROUND
SOC SHARED SUPPORT

J223_METE
J223_METE
J223_METE

05/14/2019
05/14/2019
05/14/2019

89
90
91
92
93
94
95
96
97
98

140
141
400
401
403
405
406
407
410
500

DEV SUPPORT 1
DEV SUPPORT 2
BOM CONFIGURATION
BOM CONFIGURATION
BOM GROUPS
BOM VARIANT TABLES
BOM VARIANT TABLES
BOM VARIANT TABLES
BOM ALTERNATES

B

BOARD RULES

A

43
44
45
46
47
48
49
50
51
52
53
54
55
56

48

49

50

51

52

53

54

55

56

57

58

59

60

62

SOC PROJECT SUPPORT
T151
SECURE ELEMENT
T139 SUPPORT
I2C CONNECTIONS 1
I2C CONNECTIONS 2
POWER SENSORS HIGH SIDE
POWER SENSORS LOAD SIDE
POWER SENSORS EXTENDED
POWER SENSORS EXTENDED 2
THERMAL SENSORS
POWER SENSORS EXTENDED 3
FANS/SMC/AMUX SUPPORT
AUDIO PLACEHOLDER

A

DRAWING TITLE

SCHEM,MLB,X1782

8

57
58
59
60

63

64

65

66

AUDIO JACK CODEC
AUDIO LEFT AMPLIFIERS
AUDIO RIGHT AMPLIFIERS
AUDIO FLEX CONNECTORS

LAST_MODIFICATION=Fri Jan 17 17:25:04 2020

3

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-05309

REVISION

6.0.0

BRANCH

pvt

PAGE

1 OF 500

SHEET

1 OF 98

124567

SIZEDRAWING NUMBER

D

678

3 245

1

D

DESIGN

J223/MLB 051-05309 820-01987 056-09380

J213/FLEX_AUDIOJACK

J680/FLEX_USBC

J130/FLEX_BMU_SIGNAL

DESCRIPTION

POR CFL MLB
AUDIO JACK,

AMR, AND MESA
LEFT SIDE USB

TONGUE FLEX

SIGNALS TO

BMU

SCHEMATIC

051-04122

051-03140

MCOBOARD

PANEL

057-01595-D

821-02091

821-01646

056-07548-27

N/A

N/A056-05483-A

821-01726051-01247 056-05589-A N/A

D

C

J130/FLEX_BMU_PWR

J130/FLEX_TCON_MLB_A

J213/FLEX_TRACKPAD

J130/FLEX_KB

J213/FLEX_3MIC

POWER TO/FROM

BMU

DISPLAYPORT FROM

MLB TO TCON

MLB TO

TRACKPAD

KB FLEX FOR ALL

3 KB TYPES

MIC FLEX

051-01195

051-01897

821-00583

821-00981

821-02218051-04335

821-01046051-02011

821-02265051-04441

056-02919-A

056-02852-A

N/A

C

N/A

N/A056-07655-08

N/A056-03725-B

N/A056-07754-24

B

J79/GRAPE_FLEX

DFR DAUGHTER FLEX

DFR TOUCH FLEX

DFR DAUGHTER

FLEX

051-01338

VENDOR

821-00681

VENDOR

056-02220-A

N/A

N/A099-14398

B

A

8

A

PAGE TITLE

SYSTEM PCB SUMMARY

DRAWING NUMBER

051-05309

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

REVISION

6.0.0

BRANCH

pvt

PAGE

2 OF 500

SHEET

2 OF 98

1

SIZE

D

678

3 245

1

D

TOP SIDE STANDOFFS

OMIT_TABLE

Z0400

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

OMIT_TABLE

Z0401

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

OMIT_TABLE

Z0402

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

860-01216

EAST OF NAND ALIGNED WITH
BOTTOM SIDE STANDOFF

860-01216

NORTH OF NAND

860-01216

NORTH OF NAND

USB-C BOSS

CRITICAL

Z0420

3.4OD1.75ID-1.12H-SM

1

CRITICAL

Z0421

3.4OD1.75ID-1.12H-SM

1

DFR BOSS

CRITICAL

Z0430

3.4OD1.75ID-1.5H-SM

1

860-00392

860-00392

860-01484

DFR WASHER

CRITICAL

Z0431

4.75OD2.73ID-H0.2

RING-TH

1

860-01519

WIFI WASHER

CRITICAL

Z0432

4.75OD2.73ID-H0.2

RING-TH

1

POGO PINS BACKLIGHT

CRITICAL

PP0400

POGO-2.3OD-4.06H-SM

SM-1

1

870-09670

POGO PIN DISPLAY

CRITICAL

PP0420

POGO-2.3OD-4.0H-SM

SM-1

1

870-09667

POGO PINS DRAM

CRITICAL

MLB MTG HOLES 2.1X3.36 MM

CRITICAL

ZT0420

TH-NSP

1

SL-2.1X3.51-4.6X6.01

CRITICAL

ZT0421

TH-NSP

1

SL-2.1X3.51-4.6X6.01

CRITICAL

ZT0422

TH-NSP

1

SL-2.1X3.51-4.6X6.01

998-19711

NEAR RIGHT SPKR CONNECTOR

998-19711

NEAR TRACKPAD CONNECTOR

998-19711

NEAR LEFT SPKR CONNECTOR

D

C

B

OMIT_TABLE

Z0404

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

OMIT_TABLE

860-01216

FAR SIDE NEAR AJ CONN

Z0405

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

OMIT_TABLE

860-01216

SOUTH OF NAND

Z0406

2.8OD1.2ID-1.49H-SM

1

2

CRITICAL

860-01216

NORTH OF NAND

BOTTOM SIDE TALL STANDOFF

OMIT_TABLE

Z0460

2.8OD1.2ID-3.15H-SM

1

860-01485

2

EAST OF NAND ALIGNED WITH
TOP SIDE STANDOFF

POGO PIN HEAT PIPE

CRITICAL

TRACKPAD BOSS

CRITICAL

Z0440

3.5OD1.85ID-1.41H-SM

1

860-00381

CRITICAL

Z0441

3.5OD1.85ID-1.41H-SM

1

860-00381

DISPLAY BOSS

CRITICAL

Z0450

2.7X1.8R-1.4ID-0.91H-SM

1

860-00469

CRITICAL

Z0451

2.7X1.8R-1.4ID-0.91H-SM

1

860-00469

AJ FLEX COWLING BOSS

CRITICAL

Z0470

3.5OD1.85ID-1.92H-SM

1

860-00382

860-01519

POGO PIN FAN

CRITICAL

PP0430

POGO-2.3OD-4.0H-SM

SM-1

1

870-09667

SHIELD CAN ALIGMENT HOLES

CRITICAL

ZT0441

TH-NSP

1

SL-1.2X0.4-1.5X0.7

CRITICAL

ZT0442

TH-NSP

1

SL-1.2X0.4-1.5X0.7

CRITICAL

ZT0443

TH-NSP

1

SL-1.2X0.4-1.5X0.7

CRITICAL

ZT0444

TH-NSP

1

SL-1.2X0.4-1.5X0.7

CRITICAL

ZT0445

TH-NSP

1

SL-1.2X0.4-1.5X0.7

PP0410

POGO-2.3OD-4.0H-SM

SM-1

1

CRITICAL

PP0411

POGO-2.3OD-4.0H-SM

SM-1

1

998-04440

998-04440

998-04440

998-04440

998-04440

870-09667

870-09667

CPU THERM STAGE HOLES 3.15 MM

CRITICAL

ZT0400

3P9R3P15

1

998-0845

CORNER NEAREST KEYBOARD

CPU THERM STAGE HOLES 3.6 MM

CRITICAL

ZT0401

4.0R3.6-NSP

1

CRITICAL

998-03850

ZT0402

4.0R3.6-NSP

1

CRITICAL

998-03850

ZT0403

4.0R3.6-NSP

1

998-03850

FAN MTG HOLE 2.0X2.6 MM

CRITICAL

ZT0430

TH-NSP

1

SL-2.6X2.0-4.7X4.1

998-03974

C

B

PP0499

POGO-2.3OD-4.0H-SM

SM-1

1

870-09667

NOTE: REFER TO BOM TABLES. ONLY SOLDERED PARTS REMAIN IN RAMP/PVT SMT BOM. OTHERS MOVED TO POST-SMT ENCLOSURE BOM

USB-C SHIELD

806-24341

1
1 USBC_CAN_TAPE870-08656

MEGA SHIELD

604-27117

1

SHIELD CAN,HOLES,TITAN RIDGE,X1781

TAPE,NON COND,STIFFENER,TITAN RIDGE,CAN,X1533

MEGA CAN,INSULATED,X1781

MEGA_CAN CRITICAL

CRITICALUSBC_CAN
CRITICAL

USBC_SHLD
USBC_TAPE

MEGA_SHLD

LIQUID SPILL INDICATOR

4825-00493

CPU SLEDS

806-14839

CRITICAL

ZT0446

1

SL-1.2X0.4-1.5X0.7

LSI,BLACK,REEL,X1030

SLED,METAL,MATT NICKEL,X940

TH-NSP

998-04440

SLED1,SLED2 CRITICAL2

SHIELD CAN ALIGNMENT SLOTS DRAM

CRITICAL

SL0490

TH-NSP

1

SL-1.2X0.4-1.5X0.7

CRITICAL

SL0491

TH-NSP

1

SL-1.2X0.4-1.5X0.7

2X PLATED SLOTS IN MEM AREA DUE TO

SPACE CONSTRAINTS <RDAR://44382678>
ALL OTHER SHIELD ALIGNMENT SLOTS ARE
NPTH + GND RING FOR BETTER TOLERANCE

CRITICALLSI1,LSI2,LSI3,LSI4

LSI

CPU_SLEDS

998-04440

998-04440

A

DRAM SHIELD TOP

806-24340
870-07840 1

1

FENCE,DRAM,UNIV,X1781

TAPE,COND,DRAM,UNIV,X1533

DRAM SHIELD BOTTOM

806-24339

8

1

SHIELD CAN,HOLES,DRAM,UNIV,X1781

TAPE,NON COND,STIFFENER,DRAM,CAN

DRAM_TOP_FENCE CRITICAL

DRAM_TOP_FENCE_TAPE

DRAM_BOT_CAN

DRAM_BOT_CAN_TAPE

CRITICAL

CRITICAL
CRITICAL1870-08657

DRAM_TOP_FENC
DRAM_TOP_TAPE

DRAM_BOT_CAN

DRAM_BOT_TAPE

67

TOP SIDE STANDOFFS

860-01216

6

BOSS,STANDOFF,MLB,X1533

BOTTOM SIDE STANDOFFS

860-01485

1

BOSS,STANDOFF,MLB,TALL,X1533

Z0400-Z0402,Z0404-Z0406

Z0460

CRITICAL

CRITICAL

STANDOFFS_TOP

STANDOFFS_BOT

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

A

PD PARTS

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=MECHANICALS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

4 OF 500

SHEET

3 OF 98

1

SIZE

D

678

3 245

1

D

C

PPVCCIO_S0_CPU

PLACE_NEAR=U0500.AM6:15.24MM

1

R0530

24.9

1%
1/20W
MF
201

2

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

27 4

25

25

43 4

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN

IN

IN

IN

DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_ML_C_P<3>

DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<2>
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_ML_C_P<3>

UPC_XB_FAULT_L

DP_X_SNK0_HPD
DP_X_SNK1_HPD

18

18

TEST_NOA_N_10
TEST_NOA_N_11

XDP_DP_INT_HPD

EDP_COMP

AL5
AL6
AJ5
AJ6
AF6
AF5
AE5
AE6

AC4
AC3
AC1
AC2
AE4
AE3
AE1
AE2

CK9

CN6

CM6
CP7

CP6
CM7

AM6

DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]
DDI1_TXN[3]
DDI1_TXP[3]

DDI2_TXN[0]
DDI2_TXP[0]
DDI2_TXN[1]
DDI2_TXP[1]
DDI2_TXN[2]
DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]

DISPLAY SIDEBANDS

GPP_E12_USB2_OC3*

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1
GPP_E15/DPPD_HPD2

GPP_E16/DPPE_HPD3
GPP_E17/EDP_HPD

DISP_RCOMP

U0500

CFL-U

4+3E

BGA

SYM 1 OF 20

OMIT_TABLE

DDI

EDP

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUX_N
EDP_AUX_P

DISP_UTILS

DDI1_AUX_N
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3_AUX_N
DDI3_AUX_P

GPP_E7/CPU_GP1

GPP_E8/SATALED*

GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1

AH4
AH3

AM7

AC7
AC6
AD4
AD3
AG7
AG6

CN3
CN7
CK6
CK5
CK8

CK11
CH11
CG11

EDP_ML_N<0>
EDP_ML_P<0>
EDP_ML_N<1>
EDP_ML_P<1>
EDP_ML_N<2>
EDP_ML_P<2>
EDP_ML_N<3>
EDP_ML_P<3>

EDP_AUXCH_N
EDP_AUXCH_P

NC

DP_X_SNK0_AUXCH_C_N
DP_X_SNK0_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
DP_X_SNK1_AUXCH_C_P

NC
NC

XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
UPC_XA_FAULT_L

EDP_BKLT_EN
EDP_BKLT_PWM
EDP_PANEL_PWR_EN

D

76

OUT

76

OUT

76

OUT

76

OUT

76

OUT

76

OUT

76

OUT

76

OUT

76

BI

76

BI

25

BI

25

BI

25

BI

25

BI

16

OUT

16

OUT

4 87 83 73 9 7

4

27 4

IN

OUT
OUT
OUT

83 75 4

83 76 4

83 76 4

C

B

PP3V3_S5

U0500

CFL-U

4+3E

BGA

AL2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

89 83 74 73 71

69 47 43 42 18 14 13 12 11 7 5

BV25

RSVD RSVD

AN2

RSVD

AN4

RSVD

AT3

RSVD

AU3

RSVD

H4

RSVD
RSVD

CG1

RSVD

CG2

RSVD

AL1

RSVD

AL3

RSVD

AL4

RSVD

AM3

RSVD

AM4

RSVD

AN1

RSVD

AN3

RSVD

AY9

RSVD

BB9

RSVD

SYM 20 OF 20

SPARE

OMIT_TABLE

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

CR3
CR4
CR35
CP3
G1
G2
H3
W3
Y3
BB24
BC24
BC28
BK35
BK36
BT8
BT9
BV24
BP8
BP9

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

B

A

R0550
R0551
R0552
R0553

R0557
R0540
R0541
R0542

100K
100K
100K
100K

100K
100K
100K
100K

21
21

5% 2011/20W

21

5% MF

21

21

21

21

21

1/20W 2015% MF

MF

MF 2015% 1/20W

2015% 1/20W MF

UPC_XB_FAULT_L

XDP_USB_EXTC_OC_L

UPC_XA_FAULT_L

2011/20W

XDP_USB_EXTD_OC_L

XDP_DP_INT_HPD

EDP_BKLT_EN

2011/20W5% MF

EDP_BKLT_PWM

2011/20W5% MF

EDP_PANEL_PWR_EN

201MF5% 1/20W

27 4

27 4

4

4

43 4

83 75 4

83 76 4

83 76 4

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

CPU GFX

SIZE

Apple Inc.

DRAWING NUMBER

051-05309

REVISION

A

D

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

BRANCH

pvt

PAGE

5 OF 500

SHEET

4 OF 98

8

67

35 4

2

1

D

42

42

BI
BI

PP1V_S0SW

7 9 16 71 83

PLACE_NEAR=R0611:1MM

R0610

1K

5%

1/20W

MF

201

CPU_PECI
CPU_PROCHOT_L

1

PLACE_NEAR=U4750.4:13MM

2

R0613
R0611

PLACE_NEAR=U0500.Y4:38MM

2 1

678

TP0600

A

PLACE_SIDE=BOTTOM

PLACE_NEAR=DS0601.A:13MM

PP1V_S3

7 9 17 18 42 65 69 70 83

PLACE_NEAR=U0500.BJ1:25MM

1K

5%

1/20W

MF

201

1

2

R0612

72 83

OUT

21

43

300

5% 1/20W MF 201

201MF1/20W5%

CPU_PECI_R

17 72 83 85

OUT

PLACE_NEAR=U7800.L6:13MM

1

R0614

49.9

1%
1/20W
MF
201

2

CPU_CATERR_L

CPU_PROCHOT_R_L

83

PM_THRMTRIP_L

84

BI

XDP_BPM_L<0>
NC_XDP_BPM_L<1>
NC_XDP_BPM_L<2>
NC_XDP_BPM_L<3>

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP

OPC_RCOMP

TP-P5

NC

1

U0500

CFL-U

AA4
AR1

Y4

BJ1

E1

U1
U2
U3
U4

BP27
BW25

L5
N5

CATERR*
PECI
PROCHOT*
THRMTRIP*
SKTOCC*

BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

4+3E

BGA

SYM 4 OF 20

OMIT_TABLE

JTAG

CPU MISC

PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST*

PCH_TCK
PCH_TDI
PCH_TDO

PCH_TMS
PCH_TRST*
PCH_JTAGX

T6
U6
Y5
T5
AB6

W6
U5
W5
P5
Y6
P6

3 245

PP3V3_S5

74 83 89

4 7 11 12 13 14 18 42 43 47
69 71 73

DBGLED

1

R0690

750K

1%
1/20W
MF
201

2

DBGLED

R0691

1K

5%

1/20W

MF

201

1

2

1

CATERR_LED_ACATERR_LED_G

DS0601

A

VALUE=GRN-90MCD-5MA-2.85V

PLACE_SIDE=BOTTOM
SILK_PART=CATERR

0402

DBGLED

K

CATERR_LED_K

DBGLED

6

D

CRITICAL

D

VER-1

5

G S

D

CRITICAL

DBGLED

3

Q0601

SSM6N15AFEAP

SOT563

4

Q0601

XDP_CPU_TCK
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_PCH_TCK
XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
XDP_PCH_TRST_L
PCH_JTAGX

OUT

OUT

IN
IN

IN
IN

IN
IN

IN
IN

BI

16

16

16

16

16

16

16

16

16

16

16

VER-1

2

G S

SSM6N15AFEAP

SOT563

1

C

B

1%

1/20W

MF

201

1

2

R0681

49.9

PLACE_NEAR=U0500.BP27:12.7MM

PLACE_NEAR=U0500.BW25:12.7MM

R0682

49.9

PLACE_NEAR=U0500.L5:12.7MM

1%

1/20W

MF

201

1

2

CFG<4> :EDP ENABLE/DISABLE: 1 = DISABLED 0 = ENABLED

16

BI

CPU_CFG<4>

EDP_ENABLE

1K

5%

1/20W

MF

201

1%

1/20W

MF

201

1

2

1

2

R0634

PLACE_NEAR=U0500.AB5:13MM

R0680

49.9

1%

1/20W

MF

201

1

2

1

R0683

49.9

1%

1/20W

MF

201

PLACE_NEAR=U0500.N5:12.7MM

16

BI

16

BI
BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

16

BI

R0684

49.9

2

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>

CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>

CPU_CFG<16>
CPU_CFG<17>

CPU_CFG<18>
CPU_CFG<19>

CPU_CFG_RCOMP

16

OUT

ITP_PMODE
TEST_CPU_A35

18

T4
R4
T3
R3
J4
M4
J3
M3
R2
N2
R1
N1
J2
L2
J1
L1

L3
L4

N3
N4

AB5

W4

A35

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_TP

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

U0500

SYM 19 OF 20

RESERVED

OMIT_TABLE

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

CFL-U

4+3E

BGA

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

TP

TP
TP

B35
A34

BJ34
D34

BP36

BP35
BR18

NC_CPU_B35
NC_CPU_A34

TEST_CPU_BJ34
TEST_CPU_D34

NC_CPU_BP36

NC_CPU_BP35
NC_CPU_BR18

C

18

18

B

A

TEST_CPU_F37

18

TEST_CPU_BJ36

18

F37

BJ36

RSVD_TP

RSVD_TP

TP1

TP

ZVM*

RSVD_TP
RSVD_TP

MSM*

UFS_RESET*

INPUT3VSEL

IST_TRIG

BP34
BK34

AH26

F34
CN36

AJ27

AR3

BT27

CP36

NC_CPU_BP34
NC_CPU_BK34

CPU_ZVM_L
TEST_CPU_F34

TEST_CPU_CN36

NC_CPU_MSM_L

NC

CPU_INPUT3VSEL

CPU_IST_TRIG

TP0630

A

TP-P5

PLACE_SIDE=BOTTOM

For iFDIM test

CONNECT TO OPC VRS

69

OUT

18

18

CONNECT TO EOPIO VRS. Not used with combined VR for OPC/EOPIO

A

SYNC_DATE=SYNC_MASTER=

1

NOSTUFF

1

R0632

5%
1/20W
MF
0201

2

1

R0631

47K0

5%
1/20W
MF
201

2

PAGE TITLE

CPU MISC/JTAG/CFG/RSVD

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

SIZE

D

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

BRANCH

pvt

PAGE

6 OF 500

SHEET

5 OF 98

8

67

35 4

2

1

678

3 245

1

D

C

B

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

A26
D26
D28
C28
B26
C26
B28
A28
B30
D30
B33
D32
A30
C30
B32
C32
J22
H25
G22
H22
F25
J25
G25
F22
D22
C22
C24
D24
A22
B22
A24
B24
H37
H34
K34
K35
H36
H35
K36
K37
N36
N34
R37
R34
N37
N35
R36
R35
G31
G32
H29
H28
G28
G29
H31
H32
L31
L32
N29
N28
L28
L29
N31
N32

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]
DDR0_DQ[17]
DDR0_DQ[18]
DDR0_DQ[19]
DDR0_DQ[20]
DDR0_DQ[21]
DDR0_DQ[22]
DDR0_DQ[23]
DDR0_DQ[24]
DDR0_DQ[25]
DDR0_DQ[26]
DDR0_DQ[27]
DDR0_DQ[28]
DDR0_DQ[29]
DDR0_DQ[30]
DDR0_DQ[31]
DDR0_DQ[32]
DDR0_DQ[33]
DDR0_DQ[34]
DDR0_DQ[35]
DDR0_DQ[36]
DDR0_DQ[37]
DDR0_DQ[38]
DDR0_DQ[39]
DDR0_DQ[40]
DDR0_DQ[41]
DDR0_DQ[42]
DDR0_DQ[43]
DDR0_DQ[44]
DDR0_DQ[45]
DDR0_DQ[46]
DDR0_DQ[47]
DDR0_DQ[48]
DDR0_DQ[49]
DDR0_DQ[50]
DDR0_DQ[51]
DDR0_DQ[52]
DDR0_DQ[53]
DDR0_DQ[54]
DDR0_DQ[55]
DDR0_DQ[56]
DDR0_DQ[57]
DDR0_DQ[58]
DDR0_DQ[59]
DDR0_DQ[60]
DDR0_DQ[61]
DDR0_DQ[62]
DDR0_DQ[63]

U0500

CFL-U

4+3E

BGA

SYM 2 OF 20

LPDDR3 NON-INTERLEAVED0

OMIT_TABLE

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKP[1]
DDR0_CKN[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS*[0]
DDR0_CS*[1]

DDR0_ODT[0]

NC/DDR0_ODT[1]

DDR0_CAA[0]
DDR0_CAA[1]
DDR0_CAA[2]
DDR0_CAA[3]
DDR0_CAA[4]
DDR0_CAA[5]
DDR0_CAA[6]
DDR0_CAA[7]
DDR0_CAA[8]
DDR0_CAA[9]

DDR0_CAB[0]
DDR0_CAB[1]
DDR0_CAB[2]
DDR0_CAB[3]
DDR0_CAB[4]
DDR0_CAB[5]
DDR0_CAB[6]
DDR0_CAB[7]
DDR0_CAB[8]
DDR0_CAB[9]

DDR0_DQSN[0]
DDR0_DQSN[1]
DDR0_DQSN[2]
DDR0_DQSN[3]
DDR0_DQSN[4]
DDR0_DQSN[5]
DDR0_DQSN[6]
DDR0_DQSN[7]

DDR0_DQSP[0]
DDR0_DQSP[1]
DDR0_DQSP[2]
DDR0_DQSP[3]
DDR0_DQSP[4]
DDR0_DQSP[5]
DDR0_DQSP[6]
DDR0_DQSP[7]

NC/DDR0_ALERT_L

NC/DDR0_PAR

NC/DDR0_MA[3]
NC/DDR0_MA[4]

DDR_VREF_CA

DDR0_VREF_DQ[0]
DDR0_VREF_DQ[1]

DDR1_VREF_DQ

DDR_VTT_CNTL

V31
V32
T31
T32

U36
U37
U34
U35

AE32
AF32

AE31
AF31

AB35
W36
AA37
AB34
AA36
V34
AA34
W34
V35
W35

AC32
AB32
AC31
Y32
W32
AC34
AB31
Y31
AC36
AC37

C27
D31
H24
C23
J35
P34
G30
L30

D27
C31
G24
D23
J34
P35
H30
N30

W37
W31

AC35
AA35

F36

D35
D37
E36

C35

NC

NC

NC
NC

NC

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

CPU_DDDR0_ALERT_L

CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ
PM_MEMVTT_EN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

20

BI

20

BI

21

BI

21

BI

20

BI

20

BI

21

BI

21

BI

20

BI

20

BI

21

BI

21

BI

20

BI

20

BI

21

BI

21

BI

R0703

19

OUT

19

OUT

19

OUT

73

OUT

24 20

24 20

24 21

24 21

24 20

24 20

24 21

24 21

24 20

24 20

24 20

24 20

24 20

24 20

24 20

24 20

24 20

24 20

24 21

24 21

24 21

24 21

24 21

24 21

24 21

24 21

24 21

24 21

24 21 20

24 21 20

24 21 20

0

5%

1/20W

MF

0201

U0500

CFL-U

4+3E

BGA

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

21

23

23

23

23

23

23

23

23

23

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AN35
AN34
AR35
AR34
AN37
AN36
AR36
AR37
AU35
AU34
AW35
AW34
AU37
AU36
AW36
AW37
AJ29
AJ30
AM32
AM31
AM30
AM29
AJ31
AJ32
AR31
AR32
AV30
AV29
AR30
AR29
AV32
AV31
BA35
BA34
BC35
BC34
BA37
BA36
BC36
BC37
BE35
BE34
BG35
BG34
BE37
BE36
BG36
BG37
BA32
BA31
BD31
BD32
BA30
BA29
BD29
BD30
BG31
BG32
BK32
BK31
BG29
BG30
BK30
BK29

DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[4]
DDR1_DQ[5]
DDR1_DQ[6]
DDR1_DQ[7]
DDR1_DQ[8]
DDR1_DQ[9]
DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[12]
DDR1_DQ[13]
DDR1_DQ[14]
DDR1_DQ[15]
DDR1_DQ[16]
DDR1_DQ[17]
DDR1_DQ[18]
DDR1_DQ[19]
DDR1_DQ[20]
DDR1_DQ[21]
DDR1_DQ[22]
DDR1_DQ[23]
DDR1_DQ[24]
DDR1_DQ[25]
DDR1_DQ[26]
DDR1_DQ[27]
DDR1_DQ[28]
DDR1_DQ[29]
DDR1_DQ[30]
DDR1_DQ[31]
DDR1_DQ[32]
DDR1_DQ[33]
DDR1_DQ[34]
DDR1_DQ[35]
DDR1_DQ[36]
DDR1_DQ[37]
DDR1_DQ[38]
DDR1_DQ[39]
DDR1_DQ[40]
DDR1_DQ[41]
DDR1_DQ[42]
DDR1_DQ[43]
DDR1_DQ[44]
DDR1_DQ[45]
DDR1_DQ[46]
DDR1_DQ[47]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

SYM 3 OF 20

LPDDR3 NON-INTERLEAVED

OMIT_TABLE

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKP[1]
DDR1_CKN[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS*[0]
DDR1_CS*[1]

DDR1_ODT[0]

NC/DDR1_ODT[1]

DDR1_CAA[0]
DDR1_CAA[1]
DDR1_CAA[2]
DDR1_CAA[3]
DDR1_CAA[4]
DDR1_CAA[5]
DDR1_CAA[6]
DDR1_CAA[7]
DDR1_CAA[8]
DDR1_CAA[9]

DDR1_CAB[0]
DDR1_CAB[1]
DDR1_CAB[2]
DDR1_CAB[3]
DDR1_CAB[4]
DDR1_CAB[5]
DDR1_CAB[6]
DDR1_CAB[7]
DDR1_CAB[8]
DDR1_CAB[9]

DDR1_DQSN[0]
DDR1_DQSN[1]
DDR1_DQSN[2]
DDR1_DQSN[3]
DDR1_DQSN[4]
DDR1_DQSN[5]
DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[0]
DDR1_DQSP[1]
DDR1_DQSP[2]
DDR1_DQSP[3]
DDR1_DQSP[4]
DDR1_DQSP[5]
DDR1_DQSP[6]
DDR1_DQSP[7]

NC/DDR1_ALERT_L

NC/DDR1_PAR

NC/DDR1_MA[3]
NC/DDR1_MA[4]

DRAM_RESET*

DDR_COMP[0]
DDR_COMP[1]
DDR_COMP[2]

AF29
AF28
AE29
AE28

T28
T29
V28
V29

AL37
AL35

AL36
AL34

AF35
AB29
AE37
AE36
AC29
W29
AB28
AC28
W28
Y28

AK35
AK34
AJ35
AJ34
AJ37
AF34
AJ36
AG34
AG35
AG36

AP35
AV34
AL31
AU31
BB35
BF34
BC31
BH31

AP34
AV35
AL30
AU30
BB34
BF35
BC30
BH30

Y29
AE34

AG37
AE35

BU31

BN28
BN27
BN29

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>

NC

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

CPU_DDDR1_ALERT_L

NC

NC
NC

CPU_DRAM_RESET_L

CPU_DDR_RCOMP<0>
CPU_DDR_RCOMP<1>
CPU_DDR_RCOMP<2>

R0704

0

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5%

1/20W

MF

0201

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

24 22

24 22

24 23

24 23

24 22

24 22

24 23

24 23

24 23 22

24 23 22

24 23 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

22

22

23

23

22

22

23

23

22

22

23

23

22

22

23

23

21

PP1V2_S3_CPUDDR

1

R0705

470

5%
1/20W
MF
201

2

D

C

B

88 83 50 9 7

A

BOM_COST_GROUP=CPU & CHIPSET

1

2

PLACE_NEAR=U0500.BN29:6MM

PAGE TITLE

PLACE_NEAR=U0500.BN27:6MM

CPU LPDDR3 INTERFACE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

R0700

162

1%
1/20W
MF
201

R0701

80.6

2

PLACE_NEAR=U0500.BN28:6MM

Apple Inc.

1%
1/20W
MF
201

1

R0702

200

1%
1/20W
MF
201

2

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

SHEET

6.0.0

pvt

7 OF 500

6 OF 98

SIZE

D

A

SYNC_DATE=SYNC_MASTER=

8

67

35 4

2

1

678

3 245

1

D

C

B

A

PLACE_NEAR=U0500.BU15:30MM

86 83 70 54 11

86 83 73 70 54 16 11 7

11

11

47 43 42 18 14 13 12 11 7 5 4

XW0801
XW0802
XW0803
XW0804

88 83 50 9 6

83 70 69 65 42 18 17 9 7 5

83 71 16 9 5

83 74 9

83 70 69 65 42 18 17 9 7 5

R0850

R0852

2 1

0

21

0

PP1V2_S3_CPUDDR

PP1V_S3

PP1V_S0SW

PP1V2_S0SW

PP1V_S3

NO_XNET_CONNECTION=1

PLACE_NEAR=R7819.2:5MM

PVPCORES5_FB_P

5%0201 1/20W

NO_XNET_CONNECTION=1

PLACE_NEAR=R7821.2:5MM

MF

PVPCORES5_FB_N

02011/20W MF5%

PVCC_FB_N
PVCC_FB_P

54

NO_XNET_CONNECTION=1

XW0850

2

SM

1

NO_XNET_CONNECTION=1

PLACE_NEAR=XW0850::5mm

2

XW0852

SM

1

PPVPCORE_S5

PP1V_PRIM

PP1V05_PRIMSW_PCH_VCCAMPHYPLL_F

PP1V05_PRIM_PCH_VCCAPLL_AUD_F

PP1V05_S5_PCH_VCCDSW

11

89 83 74 73 71 69

1

C0824

4.7UF

20%

6.3V

2

X5R-CERM1
402

BYPASS=U0500.CP25::5MM

SHORT-L8-SM

21

SHORT-L8-SM

21

SHORT-L8-SM

21

SHORT-L8-SM

21

11

PP3V3_S5

PP1V8_PRIM_PCH_VCCHDA_F

11

PP1V24_S5_PCH_VCCDPHY

PLACE_NEAR=U0500.CC12:5MM

PP1V05_PRIM_PCH_VCCDUSB_XW

PLACE_NEAR=U0500.BR12:5MM

PP1V05_PRIM_PCH_VCCA19P2_XW

PLACE_NEAR=U0500.BP14:5MM

PP1V05_PRIM_PCH_VCCABCLK_XW

PLACE_NEAR=U0500.BU12:5MM

PP1V05_PRIM_PCH_VCCASRC_XW
PP1V05_PRIM_PCH_VCCAXTAL_F

OUT

OUT

70

70

AD36
AH32
AH36
AM36
AN32
AW32
AY36
BE32
BH36

R32
Y36

BP11

BP2

BG1
BG2
BG3

BL27
BM26

BR11
BT11

BU15
BU22
BV15
BV16
BV18
BV19
BV20
BV22
BW20
BW22
CA12
CA16
CA18
CA19
CA20
CB12
CB14
CB15

BV12
BV14
BW12
BW14
BY12
BY14

BV2

BR14
BR15
BT12
BU14

BT24

BR24
BT23

BT20

BV23

BY23
BY24
CA23
CA24

CP25

CC12

BR12

BP14

BU12

CP5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCCST
VCCST

VCCSTG
VCCSTG
VCCSTG

VCCPLL_OC
VCCPLL_OC

VCCPLL
VCCPLL

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

VCCPRIM_MPHY_1P05
VCCPRIM_MPHY_1P05
VCCPRIM_MPHY_1P05
VCCPRIM_MPHY_1P05
VCCPRIM_MPHY_1P05
VCCPRIM_MPHY_1P05

VCCAMPHYPLL_1P05

VCCAPLL_1P05
VCCAPLL_1P05
VCCAPLL_1P05
VCCAPLL_1P05

VCCDSW_1P05

VCCDSW_3P3
VCCDSW_3P3

VCCHDA

VCCSPI

VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24

VCCDPHY_EC_1P24

VCCDUSB_1P05

VCCA_19P2_1P05

VCCA_BCLK_1P05

VCCA_SRC_1P05

VCCA_XTAL_1P05

SYM 14 OF 20

OMIT_TABLE

U0500

CFL-U

4+3E

BGA

POWER 3

U0500

CFL-U

4+3E

BGA

SYM 15 OF 20

POWER 4

OMIT_TABLE

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05

VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

AK24
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18

BG10
BG8
BH9
BJ10
BJ8
BJ9
BK25
BK27
BK8
BL10
BL24
BL26
BL8
BL9
BM24
BN25

BP28
BP29

BE7
BG7

VCCRTC

DCPRTC

PPVCCIO_S0_CPU

PPVCCSA_S0_CPU

PLACE_NEAR=U0500::13MM

1

R0804

100

5%
1/20W
MF
201

2

CPU_VCCSASENSE_N
CPU_VCCSASENSE_P

PLACE_NEAR=U0500::13MM

1

R0803

100

5%
1/20W
MF
201

2

BP20
BP22
BR20
BT18
BT19
BT22
BU18
BU19
BW16
BW18
BW19
BY16
BY20
CA14

CC15
CC18
CC19
CD15
CD16
CD18
CD19
CP17
CP23

BP23
BW23
CB16
CB22
CB23
CC22
CC23
CD22
CD23
CP29

BR23

BP24

CB36
CB35

PP1V_PRIM

PLACE_NEAR=U0500.BP20:30MM

2

XW0853

SM

1

P1VPRIM_FB_R P1VPRIM_FB

54

PP1V8_S5

PP3V3_S5

PP3V_G3H_RTC

PPDCPRTC_PCH

NC_PCH_CORE_VID0
NC_PCH_CORE_VID1

11

87 83 73 9 4

87 83 66 52 9

PLACE_NEAR=U0500::13MM

1

R0801

100

5%
1/20W
MF
201

2

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

65

OUT

65

OUT

PLACE_NEAR=R7820.2:5MM

PLACE_NEAR=U0500::13MM

1

R0802

100

5%
1/20W
MF
201

2

86 83 73 70 54 16 11 7

R0853

0

21

5%

1/20W

MF

0201

32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42

42 32 18 17 16 15 14 13 12 11 7

83 74 73 72 70 69 65 53 47

86 83 69 9

69

69

47 43 42 18 14 13 12 11 7 5 4

CPU_VCCEOPIOSENSE_P

OUT

CPU_VCCEOPIOSENSE_N

OUT

89 83 74 73 71 69

83 71 13 11

87 83 66 50 9

PPVCC_S0_CPU

OUT
OUT

PP1V8_S5

PPVCCEDRAM_S0_CPU

PLACE_NEAR=U0500::13MM

R0823

100

1/20W

PLACE_NEAR=U0500::13MM

R0824

100

1/20W

OUT

5%
MF

201

5%
MF

201

73

73

1

2

1

2

70

AN10
AN24
AN26
AN27

AN9

AP2
AP24
AP26

AP9
AR10
AR25
AR27

AR5

AR6

AR7

AR8
AT24
AT26

AT9
AU24
AU25
AU26
AU27

AU5

AU6

AU7

AU8

AU9
AV10

AV2
AV27

AV5

AV7
AW10
AW24
AW25
AW26

V24

W25

Y24

Y25

AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26

V25

T25

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

VCC_OPC_1P8
VCC_OPC_1P8
VCC_OPC_1P8
VCC_OPC_1P8

VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

U0500

CFL-U

4+3E

BGA

SYM 12 OF 20

POWER 1

OMIT_TABLE

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

VCC_SENSE
VSS_SENSE

VIDALERT*

VIDSCK

VIDSOUT

AW27
AW5
AW6
AW7
AW8
AW9
AY24
AY26
BA25
BA27
BA5
BA7
BA8
BB2
BB26
BC10
BC26
BC27
BC5
BC6
BC7
BC9
BD10
BD25
BD27
BD5
BD8
BE24
BE25
BE26
BE27
BE9
BF2
BF24
BF26
BF9
BG27

K12
K14
K15
K17
K18
K20
L25
M24
M26
P24
R24
P26
R25
R26

AN6
AN5

AA3
AA1
AA2

87 83 67 50 10

65

OUT

65

OUT

PLACE_NEAR=U0500::13MM

1

R0825

100

5%
1/20W
MF
201

2

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

BOM_COST_GROUP=CPU & CHIPSET

PPVCCGT_S0_CPU

PLACE_NEAR=U0500::13MM

R0811

CPU_VCCGTSENSE_P
CPU_VCCGTSENSE_N

PLACE_NEAR=U0500::13MM

R0812

65

OUT

65

OUT

PLACE_NEAR=U0500::13MM

1

R0826

100

5%
1/20W
MF
201

2

R0829
R0830
R0831

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

U0500

CFL-U

56

1%

1/20W

MF

201

SYM 13 OF 20

POWER 2

OMIT_TABLE

1

2

1

2

1

2

220

21

0

21

0

21

PAGE TITLE

A11

VCCGT

A12

VCCGT

A14

VCCGT

A15

VCCGT

A17

VCCGT

A18

VCCGT

A20

VCCGT

A5

VCCGT

A6

VCCGT

A8

VCCGT

AA9

VCCGT

AB10

AE10

AF10

AJ10

AL10

PLACE_NEAR=U0500::13MM

VCCGT

AB2

VCCGT

AB8

VCCGT

AB9

VCCGT

AC8

VCCGT

AD9

VCCGT
VCCGT

AE8

VCCGT

AE9

VCCGT
VCCGT

AF2

VCCGT

AF8

VCCGT

AG8

VCCGT

AG9

VCCGT

AH9

VCCGT
VCCGT

AJ8

VCCGT

AK2

VCCGT

AK9

VCCGT
VCCGT

AL8

VCCGT

AL9

VCCGT

AM8

VCCGT

B11

VCCGT

B14

VCCGT

B17

VCCGT

B20

VCCGT

B3

VCCGT

B4

VCCGT

B6

VCCGT

B8

VCCGT

C11

VCCGT

C12

VCCGT

C14

VCCGT

C15

VCCGT

C17

VCCGT

C18

VCCGT

C2

VCCGT

C20

VCCGT

C3

VCCGT

C6

VCCGT

C7

VCCGT

C8

VCCGT

D11

VCCGT

D12

VCCGT

D14

VCCGT

D15

VCCGT

D17

VCCGT

D18

VCCGT

E3

VCCGT_SENSE

D2

VSSGT_SENSE

R0827

PLACE_NEAR=U0500.AA3:12.7MM

201 1% 1/20WMF

PLACE_NEAR=U0500.AA1:12.7MM

0201 5% MF 1/20W

PLACE_NEAR=U0500.AA2:12.7MM

0201 5% MF 1/20W

CPU & PCH POWER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

4+3E

BGA

PP1V_S3

PLACE_NEAR=U0500::13MM

1

R0828

100

1%
1/20W
MF
201

2

CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

D20
D4
D7
E4
F11
F14
F17
F20
F5
F6
F7
F8
G11
G12
G14
G15
G17
G18
G20
H11
H12
H14
H15
H17
H18
H20
H5
H6
H7
H8
J11
J14
J17
J20
J7
J8
K11
K2
L10
L7
L8
M9
N10
N7
N8
N9
P2
P8
R9
T10
T8
T9
U10
U8
V2
V9
W8
W9
Y10
Y8

051-05309

8 OF 500

7 OF 98

IN

OUT

BI

6.0.0

pvt

65

65

65

D

C

B

83 70 69 65 42 18 17 9 7 5

A

SYNC_DATE=SYNC_MASTER=

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

A3

A4
A32
A36
AB3
AB4
AB7

AB27
AB30
AB33
AB36

AC5

AC10
AC27
AC30
AD33
AD35

AE7

AE24
AE25
AE26
AE27
AE30

AF3
AF4
AF7

AF25
AF27
AF30
AF33
AF36

AG5

AG10
AG24
AG26
AH24
AH25
AH27
AH28
AH29
AH30
AH31
AH33
AH35

AJ7

AJ25
AJ28

AK3
AK4

AK33
AK36

AL7

AL28
AL29
AL32

AM5

AM10
AM28
AM33
AM35

AN7
AN8

AN25
AN28
AN29
AN30
AN31

AP3
AP4

AP33

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-U

4+3E

BGA

SYM 16 OF 20

GND1

OMIT_TABLE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AP36
AR4
AR28
AT4
AT33
AT35
AT36
AU4
AU10
AU28
AU29
AU32
AV3
AV4
AV6
AV8
AV25
AV28
AV33
AV36
AW1
AW3
AW4
AW28
AW29
AW30
AW31
AY4
AY33
AY35
B2
B5
B7
B9
B12
B15
B18
B21
B23
B25
B27
B29
B31
B34
B36
B37
BA3
BA4
BA6
BA10
BA28
BB3
BB4
BB33
BB36
BC4
BC8
BC25
BC29
BC32
BD4
BD6
BD7
BD28
BD33
BD35
BD36
BE3
BE4
BE8

BE10
BE28
BE29
BE30
BE31

BF3

BF4
BF33
BF36

BG4
BG25
BG28
BH28
BH29
BH32
BH33
BH35

BJ7

BK2

BK3

BK4

BK7
BK10
BK28
BK33

BL7
BL25
BL28
BL29
BL30
BL31
BL32

BM9
BM33
BM35
BM36

BN7
BN30

BP3

BP4

BP7
BP12
BP15
BP19
BP25
BP32
BP33

BR16
BR19
BR22
BR25

BT5
BT14
BT15
BT16
BT25
BT28
BT33
BT35
BT36

BU7
BU11
BU16
BU20
BU23
BU24
BU25

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-U

4+3E

BGA

SYM 17 OF 20

GND2

OMIT_TABLE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BV3
BV4
BV11
BV31
BV33
BW7
BW11
BW15
BW24
BY5
BY11
BY15
BY18
BY19
BY22
BY25
BY28
BY33
BY35
BY36
C1
C4
C9
C21
C25
C29
C33
C34
C36
C37
CA11
CA15
CA22
CA25
CB2
CB3
CB4
CB7
CB11
CB18
CB19
CB20
CB24
CB25
CB33
CC7
CC11
CC14
CC16
CC20
CC24
CC25
CC28
CC31
CD11
CD12
CD14
CD20
CD24
CD25
CE7
CE33
CE35
CE36
CF2
CF3
CF4
CF11
CF14

CF19
CF23
CF28

CG7
CG33
CH31

CJ2

CJ3

CJ4
CJ11
CJ14
CJ19
CJ23
CJ28
CJ33
CJ35
CJ36

CK1

CK4

CK7
CK37

CL2

CM1

CM4

CM5

CM9
CM13
CM17
CM21
CM25
CM29
CM31
CM33
CM37

CN1

CN2

CN5

CN9
CN13
CN17
CN21
CN25
CN29
CN37

CP1

CP2

CP9
CP11
CP13
CP15
CP19
CP21
CP27
CP35
CP37

CR2

CR6
CR34
CR36

D1
D5
D6
D8

D9
D21
D25

E9
E23
E27
E29
E31
E33
E35

F2

F3

F4
F12
F15
F18
F21
F24
F33

G3

G4

G9
G21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-U

4+3E

BGA

SYM 18 OF 20

GND 3

OMIT_TABLE

BOM_COST_GROUP=CPU & CHIPSET

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G27
G33
G35
G36
H9
H21
H27
J5
J6
J12
J15
J18
J21
J24
J33
J36
K3
K4
K9
K21
K22
K24
K25
K27
K28
K29
K30
K31
K32
L6
L27
L33
L35
L36
N6
N25
N27
P3
P4
P7
P10
P33
P36
R27
R28
R29
R30
R31
T7
T27
T30
T33
T35
T36
U7
U24
U26
V3
V4
V26
V27
V30
V33
V36
W7
W10
W27
W30
Y7
Y26
Y27
Y30
Y33
Y35

PAGE TITLE

CPU & PCH Grounds

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

9 OF 500

SHEET

8 OF 98

6.0.0

pvt

SIZE

D

D

C

B

A

SYNC_DATE=SYNC_MASTER=

8

67

35 4

2

1

678

3 245

1

D

83 66 50 7

PPVCC_S0_CPU

87

CRITICAL

1

C10G0

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C10G1

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C10H1

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C10G3

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C10G4

220UF

20%
2V

2

ELEC
SM

88 83 50 7 6

PP1V2_S3_CPUDDR

1

C1070

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1050

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1052

1UF

20%

6.3V

2

X6S-CERM
0201

BacksidePrimary

1

C1051

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1053

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1071

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1064

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1054

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1065

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1055

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1066

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1060

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1061

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1062

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1063

20UF

20%

2.5V

2

X6S-CERM
0402-1

D

C

1

C1010

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1020

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1030

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1011

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1021

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1031

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1012

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1022

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1032

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1013

20UF

20%

2.5V

2

X6S-CERM

1

C1023

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1033

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1014

20UF

20%

2.5V

2

X6S-CERM
04020402

1

C1024

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1034

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1015

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1025

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1035

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1016

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1026

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1036

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1017

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1027

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1037

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1018

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1028

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1038

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1019

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1029

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1039

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1040

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1041

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1042

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1043

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1044

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C1045

20UF

20%

2.5V

2

X6S-CERM
0402-1

87 83 73 7 4

PPVCCIO_S0_CPU

1

C1080

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1090

20UF

20%

2.5V

2

X6S-CERM
0402-1

CRITICAL

1

C1086

220UF

20%
2V

2

ELEC
SM

1

C1081

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1091

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1092

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1093

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1087

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C1094

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1082

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1095

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1083

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1084

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1085

1UF

20%

6.3V

2

X6S-CERM
0201

C

B

86 83 69 7

1

2

1

2

PPVCCEDRAM_S0_CPU

C1000

1UF

20%

6.3V
X6S-CERM
0201

C100I

1UF

20%

6.3V
X6S-CERM
0201

1

C1001

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100J

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C10H2

220UF

20%
2V

2

ELEC
SM

1

C1002

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100K

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1003

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100L

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1004

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100M

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1005

1UF

20%

6.3V

2

X6S-CERM

1

C100N

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1006

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100O

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1007

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100P

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1008

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100Q

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1009

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100R

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100A

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100S

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100B

1UF

20%

6.3V

2

X6S-CERM
02010201

1

C100T

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100C

1UF

20%

6.3V

2

X6S-CERM
0201 0201

1

C100U

1UF

20%

6.3V

2

X6S-CERM
0201

1

2

1

2

C100D

1UF

20%

6.3V
X6S-CERM

C100V

1UF

20%

6.3V
X6S-CERM
0201 0201

1

C100E

1UF 1UF

20%

6.3V

2

X6S-CERM
0201

1

C100W

1UF

20%

6.3V

2

X6S-CERM X6S-CERM

1

C100F

20%

6.3V

2

X6S-CERM
0201

1

C100X

1UF

20%

6.3V

2

0201

1

C100G

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100Y

1UF

20%

6.3V

2

X6S-CERM
0201

1

C100H

1UF

20%

6.3V

2

X6S-CERM
0201

87 83 66 52 7

PPVCCSA_S0_CPU

CRITICAL

1

C10H0

220UF

20%
2V

2

ELEC
SM

NOSTUFF

1

C10B0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10B6

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10B1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10B7

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10B2

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10B3

20UF

20%

2.5V

2

X6S-CERM
0402-1

B

A

1

C10D0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D1

1UF

20%

6.3V

2

X6S-CERM
0201

83 70 69 65 42 18 17 9 7 5 83 74 7 83 70 69 65 42 18 17 9 7 5

PP1V_S3 PP1V2_S0SW PP1V_S3

1

C10F0

1UF

20%

6.3V

2

X6S-CERM

1

C10H3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D2

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10E0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D3

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10F1

1UF

20%

6.3V

2

X6S-CERM
02010201

1

C10E1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D4

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10E2

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D5

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10E3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D6

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10E4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10F2

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10E5

20UF

20%

2.5V

2

X6S-CERM
0402-1

83 71 16 7 5

PP1V_S0SW

1

C10F3

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A0

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A1

1UF

20%

6.3V

2

X6S-CERM
0201

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

1

C10A2

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A3

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A4

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A5

1UF

20%

6.3V

2

X6S-CERM
0201

1

C10A6

1UF

20%

6.3V

2

X6S-CERM
0201

CPU Core Decoupling

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

BRANCH

PAGE

10 OF 500

SHEET

9 OF 98

pvt

SIZE

D

A

SYNC_DATE=SYNC_MASTER=

8

67

35 4

2

1

678

3 245

1

D

87 83 67 50 7

PPVCCGT_S0_CPU

1

C1162

220UF

20%
2V

2

ELEC
SM

CRITICAL

NOSTUFF

1

C1110

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1111

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1163

220UF

20%
2V

2

ELEC
SM

CRITICAL

NOSTUFF

1

C1112

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1113

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1164

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C1114

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1115

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1190

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C1116

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1117

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1191

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C1118

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1119

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1124

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1125

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1126

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1127

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1128

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1129

20UF

20%

2.5V

2

X6S-CERM
0402

D

C

1

C1170

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1140

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1171

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1141

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1172

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1142

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1173

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1143

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1174

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1144

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1175

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1145

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1176

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1146

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1177

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1147

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1184

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1148

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1187

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

1

C1149

20UF

20%

2.5V

2

X6S-CERM
0402-1

C

B

NOSTUFF

1

C1150

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1100

1UF

20%

6.3V

2

0201

1

C110G

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1151

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1101

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110H

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1152

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1102

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110I

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1153

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1103

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110J

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1154

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1104

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110K

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1155

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1105

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110L

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1156

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1106

1UF

20%

2

X6S-CERM
0201

1

C110M

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

1

C1157

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1107

1UF

20%

6.3V6.3V

2

X6S-CERM
0201

1

C110N

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1108

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110O

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1109

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110P

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110A

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110Q

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110B

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110R

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110C

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110S

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110D

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110T

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110E

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110U

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110F

1UF

20%

6.3V

2

X6S-CERMX6S-CERM
0201

1

C110V

1UF

20%

6.3V

2

X6S-CERM
0201

B

A

8

1

C110W

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110X

1UF

20%

6.3V

2

X6S-CERM
0201

A

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

CPU GT Decoupling

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

11 OF 500

SHEET

10 OF 98

1

SIZE

D

678

3 245

1

FILTERS

D

C

86 83 70 54 7

86 83 73 70 54 16 11 7

86 83 73 70 54 16 11 7

PPVPCORE_S5

PP1V_PRIM

PP1V_PRIM

NOSTUFF

1

C1200

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BV18::3MM

1

C1201

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BP20::3MM

CRITICAL

1

C1203

20UF

20%

6.3V

2

CERM-X5R
0402

BYPASS=U0500.BV12::12MM

47 43 42 18 14 13 12 11 7 5 4

89 83 74 73 71 69

83 71 13 7

PP3V3_S5

PP1V05_S5_PCH_VCCDSW

7

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP3V_G3H_RTC

NOSTUFF

1

C1221

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BR24::3MM

1

C1232

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BT24::3MM

1

C1227

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BR23::3MM

1

C1228

0.1UF

10%
10V

2

X5R-CERM
0201

BYPASS=U0500.BR23::3MM

32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42

86 83 73 70 54 16 11 7

PP1V8_S5

PP1V_PRIM

RAIL SIDE

1

2

1

2

C1265

3.0PF

+/-0.1PF
25V
NP0-C0G
0201

C1267

3.0PF

+/-0.1PF
25V
NP0-C0G
0201

L1260

220-OHM-0.7A-0.28-OHM

21

0402-1

U0500.BT20::10mm

L1261

220-OHM-0.7A-0.28-OHM

21

0402-1

U0500.BR15::3mm

PCH SIDE

1

C1226

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

BYPASS=U0500.BT20::10mm

1

C1262

2.0PF

+/-0.1PF
25V

2

C0G-CERM
0201

BYPASS=U0500.BR15::3mm

1

C1260

4.7UF

20%

6.3V

2

X5R-CERM1
402

BYPASS=U0500.BT20::10MM

1

C1261

4.7UF

20%

6.3V

2

X5R-CERM1
402

BYPASS=U0500.BR15::3MM

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V8_PRIM_PCH_VCCHDA_F

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V05_PRIM_PCH_VCCAPLL_AUD_F

D

7

7

C

B

32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42

47 43 42 18 14 13 12 11 7 5 4

89 83 74 73 71 69

PP1V8_S5

PP3V3_S5

NOSTUFF

1

C1205

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.CP17::3MM

1

C1206

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.CP23::3MM

NOSTUFF

1

C1207

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

BYPASS=U0500.CD23::7MM

1

C1208

0.1UF

10%
10V

2

X5R-CERM
0201

BYPASS=U0500.CP29::3MM

PPDCPRTC_PCH

7

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

C1231

0.1UF

10%
10V

2

X5R-CERM
0201

BYPASS=U0500.BP24::3MM

86 83 73 70 54 16 11 7

86 83 73 70 54 16 11 7

PP1V_PRIM

PP1V_PRIM

R1250

0

21

5%
1/16W
MF-LF

402

R1253

0

21

5%
1/16W
MF-LF

402

CRITICAL

1

C1250

20UF

20%

6.3V

2

CERM-X5R
0402

BYPASS=U0500.BV2::5MM

CRITICAL

1

C1253

20UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C1251

20UF

20%

6.3V

2

CERM-X5R
0402

BYPASS=U0500.BV2::4MM

CRITICAL

1

C1254

20UF

20%

6.3V

2

CERM-X5R
0402

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V05_PRIMSW_PCH_VCCAMPHYPLL_F

1

C1252

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.BV2::3MM

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V05_PRIM_PCH_VCCAXTAL_F

1

C1255

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U0500.CP5::3MM

7

7

B

BYPASS=U0500.CP5::3MM

BYPASS=U0500.CP5::3MM

A

8

A

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

PCH Decoupling

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

12 OF 500

SHEET

11 OF 98

1

SIZE

D

678

3 245

1

D

C

MLB_RAMCFG0

12

MLB_RAMCFG1

12

MLB_RAMCFG2

12

MLB_RAMCFG3

12

MLB_RAMCFG4

12

MEMORY CONFIGURATION STRAPS:

(PCH INTERNAL PULL-UPS ARE TO 1.8V)

RAMCFG4_L

1

R1334

1K

5%
1/20W
MF
201

2

RAMCFG3_L

1

R1333

1K

5%
1/20W
MF
201

2

RAMCFG2_L

1

R1332

1K

5%
1/20W
MF
201

2

RAMCFG1_L

1

R1331

1K

5%
1/20W
MF
201

2

25 12

RAMCFG0_L

1

R1330

1K

5%
1/20W
MF
201

2

OUT

JTAG_TBT_X_TMS

PCH_DDPB_CTRLDATA

12

JTAG_TBT_T_TMS

12

PCH_DDPC_CTRLDATA

12

MLB_RAMCFG0

12

MLB_RAMCFG1

12

PCH_STRP_JTAGODTDIS

12

NC_PCH_I2S0_SYNC
NC_PCH_I2S0_CLK
NC_HDA_SDOUT
NC_PCH_I2S0_D2R

NC

NC_PCH_I2S1_CLK
NC_PCH_GPP_D17

NC
NC

NC_PCH_GPP_D11

NC_PCH_STRP_TOPBLK_SWP_L

NC_PCH_GPP_F0
NC_PCH_GPP_F1
NC_PCH_GPP_F2

NC_PCH_GPP_F3
NC_PCH_I2C_UPC_SDA
NC_PCH_I2C_UPC_SCL

NC_PCH_GPP_H6

NC_PCH_GPP_H7

NC_PCH_GPP_H8

NC_PCH_GPP_H9

NC_PCH_GPP_H10

NC_PCH_GPP_H11

BN34
BN37
BN36
BN35
BL36
BL35
CK25
BL37
BL34

CC8
CC9
CH4
CH3

CM24
CN23

CM22
CP22

CF35

CP20
CK19
CG17
CN20
CF27
CF29
CH27
CH28
CJ30
CJ31
CJ27
CJ29

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BCLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST*/I2S1_SCLK
GPP_D17/DMIC_CLK1
I2S1_SFRM
I2S1_TXD

GPP_E18/DPPB_CTRLCLK
GPP_E19/DPPB_CTRLDATA
GPP_E20/DPPC_CTRLCLK
GPP_E21/DPPC_CTRLDATA

GPP_D13/ISH_UART0_RXD/

SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/

SML0BCLK/I2C4B_SCL

GPP_D11
GPP_D12

GPP_B14/SPKR

GPP_F0/CNV_PA_BLANKING
GPP_F1
GPP_F2
GPP_F3
GPP_H4/I2C2_SDA
GPP_H5/I2C2_SCL
GPP_H6/I2C3_SDA
GPP_H7/I2C3_SCL
GPP_H8/I2C4_SDA
GPP_H9/I2C4_SCL
GPP_H10/I2C5_SDA/ISH_I2C2_SDA
GPP_H11/I2C5_SCL/ISH_I2C2_SCL

(STRAP)

(STRAP)

(STRAP)

(BSSB_CLK)

(BSSB_DATA_IN)

U0500

CFL-U

4+3E

BGA

SYM 7 OF 20

OMIT_TABLE

(1.8V)

SDIO/SDXC

GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F22/EMMC_RESET*

GPP_F23

GPP_G0/SD_CMD

GPP_G1/SD3_DATA0

GPP_A17/SD_VDD1_PWR_EN*/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP
SD_3P3_RCOMP

(1.8V)

GPP_F17/EMMC_DATA5

GPP_H12/M2_SKT2/CFG[0]
GPP_H13/M2_SKT2/CFG[1]
GPP_H14/M2_SKT2/CFG[2]
GPP_H15/M2_SKT2/CFG[3]

GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA
GPP_H18/CPU_C10_GATE*

GPP_H19/TIMESYNC[0]

GPP_H20/IMGCLKOUT[1]

GPP_H21
GPP_H22
GPP_H23

CP18
CM18
CM16
CP16
CN16
CF17
CH36
CL35

BW36
BY31

CK33
CM34

CR18

CR28
CP28
CN28
CM28
CR26
CP26
CN27
CM27
CH25
CF25
CN26
CM26

ALL GPP_F* PINS ARE 1.8V ONLY!

NC_PCH_GPP_F18
NC_PCH_GPP_F19
NC_PCH_GPP_F20
NC_PCH_GPP_F21
NC_PCH_GPP_F22
NC_PCH_GPP_F23
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

OUT
OUT

NC_PCH_GPP_A17
NC_PCH_GPP_A16

SD_RCOMP

R1370

NC_PCH_GPP_F17

JTAG_ISP_TCK
JTAG_ISP_TDI
JTAG_ISP_TDO
TBT_POC_RESET
NC_PCH_GPP_H16
NC_PCH_DDPF_CTRLDATA
CPU_C10_GATE_L
PCH_WLAN_AUDIO_SYNC
NC_PCH_GPP_H20
PCH_STRP_XTAL_24MHZ
NC_PCH_GPP_H22
PCH_STRP_SPIROM_SAF

12

12

OUT
OUT

IN

OUT

OUT

IN

200

1%

1/20W

MF

201

25 12

25 12

25 12

18 12

29 28 25 12

29 28 25 12

PLACE_NEAR=U0500.CK33:12.7MM

1

2

29 28 12

83 74 73 71 12

D

C

B

PP3V3_S5

R1399

R1346
R1355
R1356
R1359
R1347

R1366
R1367
R1368

R1340
R1341

R1358

1K

100K

10K
10K
10K

100K

100K
100K
100K

2.2K

2.2K
10K

NOSTUFF

89 83 74 73 71

NOSTUFF

21

21
21
21

5% 201MF1/20W

21
21

21
21

5% 201MF1/20W

21

21
21

21

69 47 43 42 18 14 13 11 7 5 4

1/20W 201MF5%

1/20W

U0500

CFL-U

4+3E

BGA

SYM 5 OF 20

OMIT_TABLE

SPI-FLASH

SMBUS,SMLINK

(STRAP)

LPC

SPI-TOUCH

C LINK

(STRAP)

GPP_C0/SMBCLK

GPP_C1/SMBDATA

(STRAP)

GPP_B23/SML1ALERT*/PCHHOT*

GPP_A5/LFRAME*/ESPI_CS*

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN*

NC
NC
NC

CH37
CF37
CF36
CF34
CG34
CG36
CG35
CH34

CR12
CP12
CN12
CM12
CM23
CR24
CG23

CH7
CH8
CH9

BV29
BV28

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0*
SPI0_CS1*
SPI0_CS2*

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS*
GPP_C23/UART2_CTS*
GPP_D15/ISH_UART0_RTS*
GPP_D16/ISH_UART0_CTS*
GPP_D21/SPI1_IO2

CL_CLK
CL_DATA
CL_RST*

GPP_A0/RCIN*
GPP_A6/SERIRQ

IO1

IO0

TP_SPI_PCHROM_CLK
NC_SPI_PCHROM_MISO

SPI_PCHROM_MOSI

12

16 12

MF1/20W5%

201

PCH_STRP_SPIROM_SAF

12

SPI_PCHROM_IO<2>
SPI_PCHROM_IO<3>

12

TP_SPI_PCHROM_CS_L
NC_SPI_CS1_L
NC_SPI_CS2_L

201MF1/20W5%
201MF1/20W5%

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_ISP_TDO

CPU_C10_GATE_L

PCH_STRP_JTAGODTDIS

201MF1/20W5%

SPI_PCHROM_MOSI

201MF5%

SPI_PCHROM_IO<2>
SPI_PCHROM_IO<3>

201MF1/20W5%

201MF1/20W5%
201MF1/20W5%

PCH_DDPB_CTRLDATA
PCH_DDPC_CTRLDATA

ENABLE DPPB/C INTERFACES

12

12

12

12

12

12

25 12

25 12

16 12

83 27 12

83 27 12

83 74 73 71 12

IN

OUT

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

NC_PCH_GPP_C22

PCH_UART2_CTS_L

12

MLB_RAMCFG2

12

MLB_RAMCFG3

12

MLB_RAMCFG4

12

18 12

PCH_BT_AUDIO_SYNC
PCH_GPP_A6

201MF1/20W5%

CK14
CH15
CJ15

CH14
CF15
CG15

CN15
CM15
CC34

CA29
BY29
BY27
BV27
CA28
CA27

BV32
BV30
BY30

SMBUS_PCH_CLK
SMBUS_PCH_DATA
NC_PCH_STRP_TLSCONF

SML_PCH_0_CLK
SML_PCH_0_DATA
PCH_STRP_ESPI

SML_PCH_1_CLK
SML_PCH_1_DATA

NC_PCH_STRP_BSSB_SEL_GPIO

ESPI_IO_PCH<0>
ESPI_IO_PCH<1>
ESPI_IO_PCH<2>
ESPI_IO_PCH<3>
ESPI_CS_PCH_L

R1320
R1321
R1322
R1323
R1324

ESPI_RESET_L
ESPI_CLK60M_R

R1327

NC_PCH_GPP_A10
NC_PCH_GPP_A8

12

OUT

OUT

OUT

BI

BI

BI

20
20
20
20
20

22

47

47

47

47

47 12

47 12

21
21
21
21
21

21

201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%

201MF1/20W5%

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

ESPI_CLK60M

OUT
OUT

OUT

BI
BI
BI
BI

35 12

35 12

35 12

35 12

35 12

35 12

35 12

B

A

PP1V8_S5

R1344
R1345
R1352
R1353
R1363
R1365

R1348
R1349
R1350
R1351
R1357

R1369

R1375
R1376

PM_SLP_S3_L

R1371
R1372

R1360
R1361
R1354
R1362
R1364

R1374

100K

1K
47K
47K

1K

1K

100K
100K
100K
100K
100K

100K

2.2K

2.2K

100K
100K

100K
100K

47K

100K
100K

100K

1/20W

1/20W 201MF5%

47 42 32 18 17 16 15 14 13 11 7

MF 2015%
MF

83 74 73 72 70 69 65 53

NOSTUFF

21
21
21
21
21

5% 1/20W MF 201

21

21
21
21
21
21

21

NOSTUFF

21

21

89 83 25 15 13

21
21

21
21
21
21

5% 201MF1/20W

21

21

PCH_BT_AUDIO_SYNC

PCH_STRP_ESPI

2011/20W5%
201MF1/20W5%
201MF1/20W5%

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
PCH_STRP_SPIROM_SAF

PCH_STRP_XTAL_24MHZ

201MF1/20W5%

ESPI_IO<0>

201MF1/20W5%
201MF1/20W5%
201MF1/20W5%

ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

201MF1/20W5%

PCH_WLAN_AUDIO_SYNC

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

SML_PCH_1_CLK
SML_PCH_1_DATA

TBT_X_CIO_PWR_EN

201MF1/20W5%

TBT_X_USB_PWR_EN

201MF1/20W5%

JTAG_ISP_TCK

201MF1/20W5%

JTAG_ISP_TDI

201MF1/20W5%

PCH_UART2_CTS_L

201MF1/20W5%

TBT_POC_RESET

PCH_WLAN_AUDIO_SYNC

201MF1/20W5%

PCH_BT_AUDIO_SYNC

201MF1/20W5%

12

12

12

12

ESPI ANALYZER CONNECTOR

18 12

83 27 12

83 27 12

35 12

35 12

35 12

35 12

35 12

18 12

47 12

47 12

29 28 25 12

29 28 25 12

25 12

25 12

29 28 12

18 12

18 12

35 12 35 12

35 12

35 12

35 12

35 12

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

R1380
R1381
R1382
R1383
R1384

ESPI_DBG
ESPI_DBG
ESPI_DBG
ESPI_DBG
ESPI_DBG

43
43
43
43

21

1/20W 5% MF 201

21
21
21
21

ESPI_IO_DBG<0>
ESPI_IO_DBG<1>

201MF5%1/20W

ESPI_IO_DBG<2>

201MF1/20W 5%

ESPI_IO_DBG<3>

201MF1/20W 5%

ESPI_DBG_CS_L

201MF1/20W435%

BOM_COST_GROUP=CPU & CHIPSET

516S00115

505070-1222

J1301

M-ST-SM

1413

21
43
65
87
109

NC

15

1211

16

ESPI_DBG

ESPI_RESET_L

NC

ESPI_CLK60M_DBG

NC
NC
NC

43

21

ESPI_CLK60M

201 MF 1/20W 5%

R1385

ESPI_DBG

PAGE TITLE

PCH AUDIO/LPC/SPI/SMBUS

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 12

DRAWING NUMBER

051-05309

REVISION

6.0.0

BRANCH

pvt

PAGE

13 OF 500

SHEET

12 OF 98

SIZE

D

A

SYNC_DATE=SYNC_MASTER=

8

67

35 4

2

1

678

3 245

1

D

18

IN

CPU_VCCST_PWRGD

VCCST_PWRGD 1V TOLERANT

83 42 16

PLACE_NEAR=U0500.CN10:5mm

IN

C1400

100PF

5%
25V
C0G

0201

1

2

R1406

1%

60.4

201

PLACE_NEAR=U0500.BJ2:38mm

MF

21
1/20W

83 18 17 15 13

83 42 16 13

83 42

83 42

83 42 16 13

OUT

IN

IN
IN
IN

PLT_RST_L
PM_SYSRST_L
PM_RSMRST_L

TP_CPU_PWRGD
CPU_VCCST_PWRGD_R

PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_RSMRST_L

NC_PCH_GPP_A13
NC_PCH_GPP_A15

PCIE_WAKE_L

13

PCH_LAN_WAKE_L

13

NC_PCH_LANPHYPC
PCH_STRP_GPD7

13

BJ35
CN10
BR36

AR2
BJ2

CR10
BP31
BP30

BV34
BY32

BU30
BU32
BU34
BV35

U0500

SYM 11 OF 20

SYSTEM POWER MANAGEMENT

OMIT_TABLE

GPP_B13/PLTRST*
SYS_RESET*
RSMRST*

PROCPWRGD
VCCST_PWRGOOD

SYS_PWROK
PCH_PWROK
DSW_PWROK

GPP_A13/SUSWARN*/SUSPWRDACK
GPP_A15/SUSACK*

WAKE*
GPD2/LAN_WAKE*
GPD11/LANPHYPC
GPD7

(1V ONLY)

CFL-U

4+3E

BGA

GPP_B12/SLP_S0*

GPD4/SLP_S3*
GPD5/SLP_S4*

GPD10/SLP_S5*

SLP_SUS*
SLP_LAN*

GPD9/SLP_WLAN*

GPD6/SLP_A*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD0/BATLOW*

GPP_A11/PME*

INTRUDER*

GPP_B11/EXT_PWR_GATE*

GPP_B2/VRALERT*

BJ37
BU36
BU27
BT29

BU29
BT31
BT30
BU37

BU28
BU35
BV36

CA32
BR35

CC37
CC36

PM_SLP_S0_3V3_L

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L

PM_SLP_SUS_L

NC

NC_PCH_SLP_WLAN_L
NC_PCH_SLP_A_L

PCH_PWRBTN_L
SPIROM_USE_MLB
PCH_BATLOW_L

NC_PCH_GPP_A11
PCH_INTRUDER_L

PCH_HSIO_PWR_EN
NC_PCH_GPP_B2

13

13

13

13

OUT
OUT
OUT
OUT

IN

D

18 13

89 83 25 15 13 12

89 83 13

89 83 13

PP3V_G3H_RTC

83 72 16 13

1

R1401

1M

5%
1/20W
MF
201

2

83 71 11 7

C

C

B

A

PP1V8_S5

R1461
R1446
R1445

PP3V3_S5

R1440
R1441
R1451
R1452
R1453
R1459
R1463

R1460
R1444
R1454
R1455
R1456
R1457
R1458

16 15 14 12 11 7

1K
100K
100K

100K
100K
100K

10K
100K
100K

10K

100K
100K
100K
100K
100K
100K
100K

NOTE: =PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED.
THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE.
THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.

21
21
21

21
21
21
21
21
21
21

21
21
21
21
21
21
21

1/20W5% MF
1/20W 2015%

5% 2011/20W MF

1/20W 2015%

5% MF1/20W

1/20W5% MF 201

5%

1/20W5% MF 201

1/20W5% 201MF

1/20W 201

5%

1/20W 201MF

5% 1/20W MF 201

5% 1/20W MF 201

1/20W5% 201MF

MF

MF

MF1/20W5% 201

MF5%

MF1/20W 2015%

201

89 83 74 73 71

201

2011/20W MF

2011/20W MF5%

83 74 73 72 70 69 65 53

PCH_STRP_CNV_DISABLE
PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO

SPIROM_USE_MLB
PCH_STRP_GPD7

PCH_BATLOW_L
PCIE_WAKE_L
PCH_LAN_WAKE_L
PCH_HSIO_PWR_EN
PCH_PWRBTN_L

PLT_RST_L
SOC_SWD_MUX_SEL_PCH
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

PM_SLP_S0_3V3_L

PM_SLP_SUS_L

47 42 32 18 17

69 47 43 42 18 14 12 11 7 5 4

13

13

13

13

13

13

13

13

13

13

U0500

CFL-U

4+3E

BGA

CR30

NC

CP30

NC

CM30

NC

CN30

NC

CN32

NC

CM32

NC

CP33

NC

CN33

NC

changed

83 72 16 13

83 18 17 15 13

83 13

89 83 13

89 83 13

89 83 25 15 13 12

18 13

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

SYM 9 OF 20

OMIT_TABLE

CNV

(1.8V)

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_RCOMP[0]
CNV_WT_RCOMP[1]

GPP_D0/SPI1_CS0*/BK0/SBK0

EMMC

GPP_F7/CNV_RGI_RSP
GPP_F8/CNV_MFUART2_RXD
GPP_F9/CNV_MFUART2_TXD

GPP_F10

GPP_F11/EMMC_CMD
GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2

GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4

GPP_F6/CNV_RGI_DT

EMMC_RCOMP

CN31
CP31

CP34
CN34

CP32
CR32

CG20

CH19
CJ17
CH17
CK17
CR16
CR20
CM20
CN19

CM19
CN18
CG19

CK15

NC
NC

NC
NC

CSI2_COMP

NC

NC_PCH_GPP_F7
NC_PCH_GPP_F8
NC_PCH_GPP_F9
NC_PCH_GPP_F10
PCH_BT_ROM_BOOT_L
PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO
SOC_SWD_MUX_SEL_PCH

DP_INT_HPD_MASK
NC_PCH_GPP_F16
PCH_STRP_CNV_DISABLE

EMMC_RCOMP

1

R1481

200

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.CP32:12.7MM

1

R1480

100

1%
1/20W
MF
201

2

ALL GPP_F* PINS ARE 1.8V ONLY!

changed

32

OUT

13

13

83 13

IN

13

PLACE_NEAR=U0500.CK15:12.7MM

43 35

CKPLUS_WAIVE=CLK_DATA_CON

changed

changed

PAGE TITLE

PCH POWER MANAGEMENT

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

SIZE

D

B

A

SYNC_DATE=SYNC_MASTER=

6.0.0

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

BRANCH

pvt

PAGE

14 OF 500

SHEET

13 OF 98

8

67

35 4

2

1

D

C

B

EXT A (SS,DCI)

FIXTURE USB-A

AIRPORT

EXT USB-A

THUNDERBOLT X LANE 0

THUNDERBOLT X LANE 1

THUNDERBOLT X LANE 2

THUNDERBOLT X LANE 3

PLACE_NEAR=U0500.CE6:12.7mm

100

1%

1/20W

MF

201

1

2

R1504

27

27

27

27

83

83

83

83

32

32

32

32

83

83

83

83

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

16

16

IN
IN
OUT
OUT

IN
IN
OUT
OUT

IN

IN
OUT
OUT

IN
IN
OUT
OUT

IN
IN
OUT
OUT

IN
IN
OUT
OUT

IN
IN
OUT
OUT

IN
IN
OUT
OUT

OUT
IN

678

USB3_BSSB_D2R_N
USB3_BSSB_D2R_P
USB3_BSSB_R2D_C_N
USB3_BSSB_R2D_C_P

TP_USB3_EXTC_D2R_N
TP_USB3_EXTC_D2R_P
TP_USB3_EXTC_R2D_C_N
TP_USB3_EXTC_R2D_C_P

PCH_PCIE_WLAN_D2R_N
PCH_PCIE_WLAN_D2R_P
PCH_PCIE_WLAN_R2D_C_N
PCH_PCIE_WLAN_R2D_C_P

USB3_EXTD_D2R_N
USB3_EXTD_D2R_P
USB3_EXTD_R2D_C_N
USB3_EXTD_R2D_C_P

PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_X_R2D_C_P<3>

PCH_PCIE_RCOMP_N
PCH_PCIE_RCOMP_P

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

PCH_GPP_A7

14

NC
NC
NC
NC

NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

CB5
CB6
CA4
CA3

BY8
BY9
CA2
CA1

BY7
BY6
BY4
BY3

BW6
BW5
BW2
BW1

BW9
BW8
BW4
BW3

BU6
BU5
BU4
BU3

BT7
BT6
BU2
BU1

BU9
BU8
BT4
BT3

BP5
BP6
BR2
BR1

BN6
BN5
BR4
BR3

CE6
CE5

W1
W2

CC32

BN10

BN8
BN4
BN3
BL6
BL5
BN2
BN1

PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN
PCIE2_RXP/USB31_2_RXP
PCIE2_TXN/USB31_2_TXN
PCIE2_TXP/USB31_2_TXP

PCIE3_RXN/USB31_3_RXN
PCIE3_RXP/USB31_3_RXP
PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN
PCIE4_RXP/USB31_4_RXP
PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP

PCIE5_RXN/USB31_5_RXN
PCIE5_RXP/USB31_5_RXP
PCIE5_TXN/USB31_5_TXN
PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN
PCIE6_RXP/USB31_6_RXP
PCIE6_TXN/USB31_6_TXN
PCIE6_TXP/USB31_6_TXP

PCIE7_RXN
PCIE7_RXP
PCIE7_TXN
PCIE7_TXP

PCIE8_RXN
PCIE8_RXP
PCIE8_TXN
PCIE8_TXP

PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP

PCIE_RCOMP_N
PCIE_RCOMP_P

PROC_PRDY*
PROC_PREQ*

GPP_A7/PIRQA*

PCIE11_RXN/SATA0_RXN
PCIE11_RXP/SATA0_RXP
PCIE11_TXN/SATA0_TXN
PCIE11_TXP/SATA0_TXP
PCIE12_RXN/SATA1A_RXN
PCIE12_RXP/SATA1A_RXP
PCIE12_TXN/SATA1A_TXN
PCIE12_TXP/SATA1A_TXP

U0500

CFL-U

4+3E

BGA

SYM 8 OF 20

OMIT_TABLE

USB2

PCIE/USB3/SATA

PCIE13_RXN
PCIE13_RXP
PCIE13_TXN
PCIE13_TXP

PCIE14_RXN
PCIE14_RXP
PCIE14_TXN
PCIE14_TXP

PCIE15_RXN/SATA1B_RXN
PCIE15_RXP/SATA1B_RXP
PCIE15_TXN/SATA1B_TXN
PCIE15_TXP/SATA1B_TXP

PCIE16_RXN/SATA2_RXN
PCIE16_RXP/SATA2_RXP
PCIE16_TXN/SATA2_TXN
PCIE16_TXP/SATA2_TXP

USB2_1N
USB2_1P

USB2_2N
USB2_2P

USB2_3N
USB2_3P

USB2_4N
USB2_4P

USB2_5N
USB2_5P

USB2_6N
USB2_6P

USB2_7N
USB2_7P

USB2_8N
USB2_8P

USB2_9N
USB2_9P

USB2_10N
USB2_10P

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E3/CPU_GP0
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_D22/SPI1_IO3
GPP_D23/I2S_MCLK

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

BK6
BK5
BM4
BM3

BJ6
BJ5
BL2
BL1

BG5
BG6
BL4
BL3

BE5
BE6
BJ4
BJ3

CE3
CE4

CE1
CE2

CG3
CG4

CD3
CD4

CG5
CG6

CC1
CC2

CG8
CG9

CB8
CB9

CH5
CH6

CC3
CC4

CC5
CE8
CC6

CE9
CP8
CR8
CM8

CH23
CK23

CJ25
CP24
CN24

CN8
CM10
CP10

PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>

PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>

PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>
PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>

PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>

USB_EXTA_N
USB_EXTA_P

NC_USB_EXTBN
NC_USB_EXTBP

NC_USB_EXTCN
NC_USB_EXTCP

TP_USB_FIXT2_N
TP_USB_FIXT2_P

NC_USB_EXTDN
NC_USB_EXTDP

USB2_UPC_PCH_XA_N
USB2_UPC_PCH_XA_P

NC_TP_USB_UPC_PCH_TA_N
NC_TP_USB_UPC_PCH_TA_P

USB2_UPC_PCH_XB_N
USB2_UPC_PCH_XB_P

NC_TP_USB_UPC_PCH_TB_N
NC_TP_USB_UPC_PCH_TB_P

TP_USB_FIXT1_N
TP_USB_FIXT1_P

PCH_USB2_COMP

PCH_USB2_VBUSSENSE
XDP_PCH_OBSFN_C1

XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2

NC_SDCONN_OC_L
NC_PCH_ENET_LOW_PWR

NC_PCH_GPP_D18
NC_PCH_GPP_D19
NC_PCH_GPP_D20

XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3

3 245

37

IN

37

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN
IN
IN

IN
IN
IN

43

43

37

37

43

43

37

37

43

43

37

37

43

43

BI
BI

83

83

28

28

29

29

83

83

16

16

16

16

16

16

16

SOC LANE 0

SOC LANE 1

SOC LANE 2

SOC LANE 3

TO TP

NOT USED

NOT USED

TP FOR FIXTURE

NOT USED

XA RP

NOT USED

XB RP

NOT USED

TP FOR FIXTURE

(GROUNDED PER CFL EDS)

1

R1503

1K

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.CC6:12.7MM

1

R1501

113

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.CC5:12.7MM

1

D

C

B

A

PP3V3_S5

R1531
R1532

PP1V8_S5

R1533
R1534

R1521

R1520

NOSTUFF

89 83 74 73 71

47K
10K

47K
47K

0

PLACE_NEAR=U0500.CM3:25.4mm

60.4

PLACE_NEAR=U0500.CJ1:25.4mm

21

21

21
21

21

21

69 47 43 42 18 13 12 11 7 5 4

83 74 73 72 70 69 65 53

5%

1% MF1/20W 201

U0500

CFL-U

4+3E

BGA

SYM 10 OF 20

ANY CLKREQ CAN MAP TO ANY CLK.
ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT.
UNUSED CLKREQS AND CLKS SHOULD BE DISABLED.
PER SKYLAKE PDG, SKYLAKE PCH EDS.

MF1/20W 2015%

201MF1/20W5%

TBT_X_CLKREQ_L

PCH_GPP_A7

14

84 37

84 37

37 14

25 14

84 25

84 25

25 14

OUT
OUT

IN

OUT
OUT

IN

PCIE_CLK100M_SOC_N
PCIE_CLK100M_SOC_P
SOC_CLKREQ_L

PCIE_CLK100M_TBT_X_N
PCIE_CLK100M_TBT_X_P
TBT_X_CLKREQ_L

NC_PCIE_CLK100M0N
NC_PCIE_CLK100M0P
NC_DEBUG_CLKREQ0_L

NC_PCIE_CLK100M3N
NC_PCIE_CLK100M3P
NC_DEBUG_CLKREQ3_L

47 42 32 18 17 16 15 13 12 11 7

32

OUT

MF1/20W 2015%
MF1/20W 2015%

SOC_CLKREQ_L
PCH_WLAN_CLKREQ_L

37 14

32 14

32

32 14

OUT

IN

PCH_PCIE_CLK100M_WLAN_N
PCH_PCIE_CLK100M_WLAN_P
PCH_WLAN_CLKREQ_L

NC_PCIE_CLK100M5N
NC_PCIE_CLK100M5P
NC_DEBUG_CLKREQ5_L

MF1/20W 0201

PCH_CLKIN_XTAL

PCH_DIFFCLK_BIASREF

14

14

AW2
AY3

CF32

BC1
BC2

CE32

BD3
BC3

CF30

BH3
BH4

CE31

BA1
BA2

CE30

BE1
BE2

CF31

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5*

CLOCK SIGNALS

OMIT_TABLE

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

CLKIN_XTAL

CLK_BIASREF

RTCX1
RTCX2

SRTCRST*

RTCRST*

AU1
AU2

BT32

CK3
CK2

CM3
CJ1

BN31
BN32

BR37
BR34

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP

NC_PCH_CLK32K_SUS
PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT
PCH_CLKIN_XTAL

PCH_DIFFCLK_BIASREF

NC_TP_PCH_RTCX2_OUT
PCH_RTC_RESET_L

OUT

IN

IN

17

17

14

14

83 72

R1572

127K

1%

1/20W

MF

201

R1573

100K

1

2

1/20W

PLACE_NEAR=U0500.BN31:5MM
PLACE_NEAR=U0500.BN31:5MM

1%
MF

201

21

PMU_CLK32K_PCHPMU_CLK32K_PCH_1V0

BOM_COST_GROUP=CPU & CHIPSET

72

IN

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

PCH PCIE/USB/CLKS

DRAWING NUMBER

051-05309

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

6.0.0

BRANCH

pvt

PAGE

15 OF 500

SHEET

14 OF 98

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

83 18 17 13

34 15

85 35

PLT_RST_L

IN

R1675

PCH_SOC_SYNC

OUT

SOC_PERST_L

OUT

NC_PCH_BT_UART_D2R

IN

NC_PCH_BT_UART_R2D

OUT

NC_PCH_BT_UART_RTS_L

OUT

NC_PCH_BT_UART_CTS_L

IN

100K

5%

1/20W

MF

201

D

ALL GPP_F* PINS ARE 1.8V ONLY!

1

1

2

R1676

100K

5%
1/20W
MF
201

2

NC_PCH_ENETSD_RESET_L
PCH_STRP_NO_REBOOT

15

NC_PCH_GPP_B19
NC_PCH_GPP_B20
NC_PCH_GPP_B21
NC_PCH_STRP_BOOT_SPI_L

NC_PCH_GPP_C16
NC_PCH_GPP_C17
NC_PCH_GPP_C18
NC_PCH_GPP_C19

NC_PCH_GPP_C12
NC_PCH_GPP_C13

NC_PCH_GPP_C14
NC_PCH_GPP_C15

NC_MEM_OK
NC_PCH_DDPD_CTRLDATA

NC_PCH_I2S_BT_CLK
NC_PCH_I2S_BT_SYNC

NC_PCH_I2S_BT_R2D
NC_PCH_I2S_BT_D2R

CC27
CE28
CE27
CE29

CA31
CC29
CC30
CA30

CR14
CP14
CN14
CM14

CM11
CN11
CK12
CJ12

CG12
CH12

CF12
CG14

CP4
CN4

CH32
CJ32

CH29
CH30

U0500

GPP_B15/GSPI0_CS0*
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS0*
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS*
GPP_C11/UART0_CTS*

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_E22/DPPD_CTRLCLK
GPP_E23/DPPD_CTRLDATA

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

(STRAP)

(STRAP)

SYM 6 OF 20

OMIT_TABLE

CFL-U

4+3E

BGA

(1.8V)
(1.8V)

(1.8V)

ISHLPSS

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO_IO1

GPP_D3/SPI1_MOSI_IO0

GPP_D4/IMGCLKOUT0

GPP_F4/CNV_BRI_DT

GPP_F5/CNV_BRI_RSP

GPP_G6/SD_CLK

GPP_D9

GPP_D10

GPP_G7/SD_WP

GPP_G2/SD3_DATA1
GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD*

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/ISH_GP6/BM_BUSY*/

SX_EXIT_HOLDOFF*

CK22
CH20
CH22
CJ22

CF20
CG22

CF22
CG25

CJ20
CK20

CK36
CN22
CR22
CK34

CL36
CM35
CN35
CH35

BW35
BW34
CA37
CA36
CA35
CA34
BW37

NC_PCH_GPP_D5
NC_PCH_GPP_D6
NC_PCH_GPP_D7
NC_PCH_UPC_I2C_INT_L

NC_PCH_GPP_D1
NC_PCH_GPP_D2

NC_PCH_GPP_D3
NC_PCH_GPP_D4

NC_PCH_GPP_F4
NC_PCH_GPP_F5

NC_TBT_X_DPMUX_SEL
TBT_X_PLUG_EVENT_L
TBT_T_PLUG_EVENT_L
NC_TBT_T_DPMUX_SEL

NC_TBT_T_CIO_PWR_EN
NC_TBT_T_USB_PWR_EN
TBT_X_PCI_RESET_L
NC_TBT_T_PCI_RESET_L

NC_PCH_GPP_A18
NC_PCH_GPP_A19
NC_PCH_GPP_A20
NC_PCH_GPP_A21
NC_BTI2SMUX_SEL_PCH
NC_PCH_BT_DEV_WAKE
NC_PCH_GPP_A12

R1671

100K

5%

1/20W

MF

201

PM_SLP_S3_L

1

2

1

R1670

100K

5%
1/20W
MF
201

2

OUT

IN

25

25 18

89 83 25 13 12

C

B

32

PCH_WLAN_PERST_L

OUT

PCH_WLAN_DEV_WAKE

15

CB34
CC35

GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

B

A

PP1V8_S5

R1656

R1677
R1674

1K

100K
100K

83 74 73 72 70 69 65 53

21

47 42 32 18 17 16 14 13 12 11 7

1/20W5% MF 201

PCH_STRP_NO_REBOOT

15

PAGE TITLE

A

SYNC_DATE=SYNC_MASTER=

PCH SPI/UART/GPIO

DRAWING NUMBER

051-05309

21

21

1/20W5% MF

MF5% 2011/20W

201

PCH_WLAN_DEV_WAKE

PCH_SOC_SYNC

15

34 15

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

Apple Inc.

REVISION

6.0.0

BRANCH

pvt

PAGE

16 OF 500

SHEET

15 OF 98

SIZE

D

8

67

35 4

2

1

678

3 245

1

Primary / Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

D

C

83 42 13

83 72 13

16 5

86 83 73 70 54 11 7

PP1V_PRIM

XDP_CONN:YES

J1800

DF40RC-60DP-0.4V

NO_XNET_CONNECTION

PULLS CFG<3> LOW
WHEN XDP PRESENT

PLACE_NEAR=U0500.BR36:18MM

XDP:YES

R1801

1K

5%

1/20W

MF

201

XDP_PRESENT_CPU

14

BI

14

1

2

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

XDP_CPU_PREQ_L
XDP_CPU_PRDY_L

CPU_CFG<0>
CPU_CFG<1>

CPU_CFG<2>
CPU_CFG<3>

NC
NC

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

XDP_PIN_1

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

XDP:YES

IN

OUT

OUT

PM_RSMRST_L
PCH_PWRBTN_L

XDP_CPU_TCK

R1800

R1802

1K

10

XDP:YES

PLACE_NEAR=U0500.BU28:8MM

21

21

1/20W5% MF 201

XDP_CPU_PWRBTN_L

1/20W5% 201MF

XDP:YES

PLACE_NEAR=J1800.42:28MM

16 5

XDP_PCH_TCK

OUT

XDP_PM_RSMRST_L

10%
10V

0201

1

2

C1804

0.1UF

X5R-CERM

NC
NC

NC
NC

HOOK0
HOOK1

VCC_OBS_AB

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

XDP:YES

5

PCH_JTAGX

OUT

R1835

0

21

MF5%

PLACE_NEAR=J1800.58:28MM

02011/20W

PLACE_NEAR=J1800.44:28MM

XDP:YES

C1800

0.1UF

10%
10V

X5R-CERM

0201

1

2

M-ST-SM1

62

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49
52 51
54 53
56 55
58 57
60 59

64 63

61

518S0847

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#

XDP:YES

1

C1801

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=J1800.43:28MM

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC
NC

XDP_DBRESET_L

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

XDP_PCH_TDO

16 5

XDP_PCH_TDI

5

5

5

5

5

5

5

5

5

5

1

R1830

2

1K

5%
1/20W
MF
201

5

5

PLACE_NEAR=J1800.45:32MM

16 5

XDP_PCH_TMS

16 5

XDP_CPU_TDO

16 5

XDP_CPU_TCK

16 5

XDP_PCH_TCK

16 5

PLACE_NEAR=U0500.W5:28MM

PLACE_NEAR=U0500.U5:28MM

PLACE_NEAR=U0500.P5:28MM

PLACE_NEAR=U0500.Y5:28MM

PLACE_NEAR=U0500.T6:28MM

PLACE_NEAR=U0500.W6:28MM

R1890

R1891

R1892

R1810

R1813

R1897

100

51

51

100

51

51

ITP_PMODE

1

C1806

0.1UF

10%
10V

2

X5R-CERM
0201

R1806

XDP:YES

PLACE_NEAR=J1800.47:28MM

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821
R1822
R1823
R1824

0

XDP:YES

0

0

XDP:YES

0

XDP:YES

0

XDP:YES

21

21

5% MF1/20W

21

5% MF 02011/20W

21

1/20W

0201

21

PM_SYSRST_L

5%
MF

XDP_CPU_TDO

MF1/20W5%

0201

XDP_CPU_TRST_L

0201

XDP_CPU_TDI

XDP_CPU_TMS

0201MF5% 1/20W

XDP_PCH_TDO

83 71 9 7 5

XDP:YES

XDP:YES

XDP:YES

XDP:YES

XDP:YES

NOSTUFF

5

IN

BI

16 5

IN

5

OUT

5

OUT

5

OUT

16 5

IN

12

12

12

12

PP1V_S0SW

12

12

1/20W5%

5% MF1/20W

83 42 13

MF5% 1/20W

201

201

MF5% 1/20W

2011/20W MF5%

201

MF5% 1/20W

201MF

201

D

C

B

14

14

14

14

14

14

14

PLACE NEARS FOR R1801, R1821, R1822, R1823, R1824

REQUIRE UPDATE FOR P1 PER <RDAR://42934724>

XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

XDP_PRESENT_L

OUT

OUT

OUT

OUT

5

16 5

16 5

35

PCH XDP Signals

B

These signals do not connect to the Primary (Merged) XDP connector in this architecture.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PCH/XDP Signals

BI

BI

BI

4

BI

4

BI

BI

BI

BI

BI

XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSFN_C1

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1868
TP1869
TP1870
TP1871
TP1872
TP1878
TP1879
TP1880
TP1881

Non-XDP Signals

42 32 18 17 15 14 13 12 11 7

83 74 73 72 70 69 65 53 47

PP1V8_S5

XDP:YES

R1850

100K

1/20W

5%
MF

201

1

2

NC

6

VCC

U1830

74AUP1G07GF

SOT891

2

(OD)

1

GND

3

XDP:YES

4

YA

NCNC

SPI_IO2_STRAP_L

5

NC

XDP:YES

1

C1830

0.1UF

10%
10V

2

X5R-CERM
0201

XDP:YES

R1831

1.5K

1/20W

PLACE_NEAR=U0500.CF34:10MM

NO_XNET_CONNECTION=1

PULL STRAP LOW WHEN XDP IS PLUGGED IN.
(UNDOCUMENTED STRAP FUNCTION)

5%
MF

201

21

SPI_PCHROM_IO<2>

(STRAP TO PCH)

OUT

12

A

Unused GPIOs have TPs.

8

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

A

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

CPU/PCH Merged XDP

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

18 OF 500

SHEET

16 OF 98

1

SIZE

D

CRITICAL

24MHz CLOCK

678

3 245

1

D

C1907

9.5PF

21

+/-0.1PF

50V

CER-C0G

0201

42

CRITICAL

C1908

9.5PF

21

+/-0.1PF

50V

CER-C0G

0201

R1900

0

5%
MF

0201

21

1

R1901

200K

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.CK2:25.4mm

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT_R PCH_CLK24M_XTALOUT

1/20W

CRITICAL

31

Y1900

24MHZ-10PPM-8PF-40OHM

2.5X2.0MM-SM

NOTE: 30 PPM or better required for SKL PCH

OUT

IN

14

14

D

C

85 83 72 5

83 18 15 13

IN

IN

THRMTRIP# ISOLATION & LEVEL-SHIFT TO 1V8

C1900

0.1UF

X5R-CERM

PM_THRMTRIP_L

PLT_RST_L

10%
10V

PP1V8_S5PP1V_S3

1

2

1

C1901

0.1UF

10%
10V

2

X5R-CERM
02010201

83 74 73 72 70 69 65 53

U1900

8

1

3

7

5

4

2

74AXP1T57

SOT833

6

CPU_SMC_THRMTRIP_L

NOSTUFF

1

R1902

100K

5%
1/20W
MF
201

2

47 42 32 18 16 15 14 13 12 11 7 83 70 69 65 42 18 9 7 5

OUT

C

35

B

B

A

8

A

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

Chipset Support 1

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

19 OF 500

SHEET

17 OF 98

1

SIZE

D

PLATFORM RESET LEVEL-SHIFTER TO 3V3

678

3 245

1

D

83 18 17 15 13

69 47 43 42 14 13 12 11 7 5 4

PLT_RST_L

IN

89 83 74 73 71

PP3V3_S5

1

C2006

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

U2002

74AUP1T97

5

SOT891

4

6

3

R2003

100K

5%

1/20W

MF

201

1

2

SLP_S0# LEVEL SHIFTER TO 1V8

PLT_RST_3V3_L

100K

2 1

R2000

5% 2011/20W MF

TBT_X_PCI_RESET_L

OUT

BT AUDIO SYNC BUFFER

D

58 57 55 51 48 47 45 44 43 18

25 15

83 18 17 15 13

IN

PLT_RST_L

83 76 74 68 62 61 60 59

PP1V8_G3S

1

OE

6

VCC

U2021

SN74LVC1G126DRYR-M

LLP

C2021

0.1UF

10%
16V

X5R-CERM

0201

1

2

C

32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42

13

IN OUT

PM_SLP_S0_3V3_L

PP1V8_S5

1

C2010

0.1UF

10%
16V

2

X5R-CERM
0201

U2010

74AUP1G34GX

5

SOT1226

2

NC

1

NC

4

3

PM_SLP_S0_L

1

R2001

100K

5%
1/20W
MF
201

2

VCCST_PWRGD LEVEL SHIFTER TO 1VALL_SYS_PWRGD QUALIFIER &

NC

4

Y

PCH_BT_AUDIO_SYNC

OUT

12

32

IN

89 83 72 35

BT_AUDIO_SYNC

1

R2023

10K

5%
1/20W
MF
201

2

2

A

GND

3

NC

5

NOSTUFF

R2022

0

21

5%

1/20W

MF

0201

C

B

32 18 17 16 15 14 13 12 11 7
83 74 73 72 70 69 65 53 47 42

42 35

83 72

SMC_RSMRST_L

IN

ALL_SYS_PWRGD

IN

PP1V8_S5

C2009

0.1UF

X5R-CERM

0201

10%
16V

1

2

2

B

1

A

NC

5

NC

NOSTUFF

R2007

0

5%

1/20W

MF

0201

U2009

74LVC1G08FZ4

DFN1410-COMBO

6

4

Y

3

21

C2007

1

R2004

1M

5%
1/20W
MF
201

2

0.1UF

10%
16V

X5R-CERM

0201

83 70 69 65 42 17 9 7 5

1

2

6

VCC

U2003

74AUP1G07GF

SOT891

2

NC NC

1

GND

3

4

YA

NCNC

CPU_VCCST_PWRGD

5

ALL_SYS_PWRGD_R

PP1V_S3

1

R2094

1K

5%
1/20W
MF
201

2

OUT

OUT

13

WLAN AUDIO SYNC BUFFER

58 57 55 51 48 47 45 44 43 18

83 76 74 68 62 61 60 59

83 18 17 15 13

34 32

69 65

IN

IN

PLT_RST_L

WLAN_AUDIO_SYNC

1

R2020

100K

5%
1/20W
MF
201

2

PP1V8_G3S

SN74LVC1G126DRYR-M

1

OE

2

A

6

VCC

U2020

LLP

GND

3

NC

5

Y

NC

C2020

0.1UF

10%
16V

X5R-CERM

0201

4

PCH_WLAN_AUDIO_SYNC

1

2

12

OUT

B

A

NOSTUFF

R2021

0

21

5%

1/20W

MF

0201

TPs for Chipset Debug Pins

P2MM

SM

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

4

IN

4

IN

TEST_CPU_D34

TEST_CPU_BJ34

TEST_CPU_A35

TEST_CPU_F37

TEST_CPU_BJ36

TEST_CPU_F34

TEST_CPU_CN36

TEST_NOA_N_10

TEST_NOA_N_11

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

PP2001

PP2002

PP2003

PP2004

PP2005

PP2006

PP2007

PP2008

PP2009

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CHIPSET SUPPORT 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05309

REVISION

6.0.0

BRANCH

pvt

PAGE

20 OF 500

SHEET

18 OF 98

SIZE

D

A

SYNC_DATE=SYNC_MASTER=

8

67

35 4

2

1

678

3 245

1

D

C

B

6

IN

6

IN

6 23 22 21 20

IN

NOTE: CPU has single output for VREFCA.
VREFCA. Connected to 4 DRAMs.

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU-Based Margining

VRef Dividers

R2223

10

21

1%

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

10

21

1%

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

5.1

1/20W

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_RC

21
1%
MF

PLACE_NEAR=R2221.2:1mm

1%

1/20W

MF

201

1

2

R2222

8.2K

R2220

24.9

1/20W

PLACE_NEAR=R2241.2:1mm

R2242

1%
MF

201

21

8.2K

1%

1/20W

MF

201

1

2

R2240

24.9

1/20W

PLACE_NEAR=R2261.2:1mm

R2262

1%
MF

201

21

8.2K

1%

1/20W

MF

201

1

2

R2260

24.9

1/20W

1%
MF

201

21

PP1V2_S3

1

R2221

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFDQ_A

1

R2241

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFDQ_B

1

R2261

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFCA_A

D

88 83 74 73 50 23 22 21 20

21 20

C

23 22

B

A

8

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

A

LPDDR3 VREF MARGINING

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

22 OF 500

SHEET

19 OF 98

1

SIZE

D

D

678

3 245

1

LPDDR3 CHANNEL A (0-31)

D

C

B

R2300

243

1%

1/20W

MF

201

1

2

R2301

243

1%

1/20W

MF

201

U2300

LPDDR3-1600-32GB

EDFB232A1MA

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 21 6

24 21 6

24 21 6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0>
MEM_A_ZQ<1>

1

23 22 21 19

21 19

2

C2340

0.047UF

1

10%

6.3V
2

X5R
201

88 83 74 73 50 23 22 21 20 19

1

2

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A

C2341

0.047UF

10%

6.3V
X5R
201

PP1V2_S3

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2300

0.1UF

10%
16V

2

X5R-CERM
0201

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

K3
K4

J3
J2

L3
L4

L8
G8
P8
D8

J8

B3
B4

H4

J11

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

1

2

OMIT_TABLE

C2301

0.1UF 1UF

10%
16V
X5R-CERM
0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2302

1UF

20%
10V

2

X5R
0201

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2303

1UF

20%
10V

2

X5R
0201

MEM_A_DQ<15> PP1V8_S3_MEM
MEM_A_DQ<14>
MEM_A_DQ<9>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<13>
MEM_A_DQ<8>
MEM_A_DQ<32>
MEM_A_DQ<37>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<7>
MEM_A_DQ<3>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<6>
MEM_A_DQ<2>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<47>
MEM_A_DQ<42>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<43>
MEM_A_DQ<46>

MEM_A_DQS_N<1>
MEM_A_DQS_N<4>
MEM_A_DQS_N<0>
MEM_A_DQS_N<5>

MEM_A_DQS_P<1>
MEM_A_DQS_P<4>
MEM_A_DQS_P<0>
MEM_A_DQS_P<5>

1

C2304

20%
10V

2

X5R
0201

1

C2305

1UF

20%
10V

2

X5R
0201

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

1

C2306

10UF

20%
10V

2

X5R-CERM
0402-7

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

1

C2307

10UF

20%
10V

2

X5R-CERM
0402-7

PP1V2_S3

PP1V2_S3

PP1V2_S3

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8
A9
D4
D5
D6
G5
H5
H6

H12

J5
J6
K5
K6

K12

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12

E8
E12
G12

H8

H9
H11

J9
J10

K8
K11
L12

N8
N12
R12
U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2300

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

PP1V2_S3

PP1V2_S3

PP1V8_S3_MEM

1

C2320

1UF

20%
10V

2

X5R
0201

1

C2310

1UF

20%

2

X5R
0201

1

C2330

1UF

20%
10V

2

X5R
0201

1

C2321

1UF

20%
10V

2

X5R
0201

1

C2311

1UF

20%
10V10V

2

X5R
0201

1

C2331

1UF 10UF

20%
10V

2

X5R
0201

1

C2322

2

1

C2312

2

1

C2332

2

1UF

20%
10V
X5R
0201

10UF

20%
10V
X5R-CERM
0402-7

20%
10V
X5R-CERM
0402-7

1

C2323

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2333

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2324

10UF

20%
10V

2

X5R-CERM
0402-7

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

LPDDR3 DRAM Channel A (00-31)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

23 OF 500

SHEET

20 OF 98

A

SIZE

D

6.0.0

pvt

8

67

35 4

2

1

D

678

3 245

1

LPDDR3 CHANNEL A (32-63)

D

C

B

R2400

243

1%

1/20W

MF

201

1

2

R2401

243

1%

1/20W

MF

201

U2400

LPDDR3-1600-32GB

EDFB232A1MA

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 20 6

24 20 6

24 20 6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>

MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2>
MEM_A_ZQ<3>

1

23 22 20 19

20 19

2

C2440

0.047UF

1

10%

6.3V
2

X5R
201

88 83 74 73 50 23 22 21 20 19

1

2

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A

C2441

0.047UF

10%

6.3V
X5R
201

PP1V2_S3

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2400

0.1UF

10%
16V

2

X5R-CERM
0201

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

K3
K4

J3
J2

L3
L4

L8
G8
P8
D8

J8

B3
B4

H4

J11

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

1

2

OMIT_TABLE

C2401

0.1UF

10%
16V
X5R-CERM
0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2402

1UF

20%
10V

2

X5R
0201

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2403

20%
10V

2

X5R
0201

MEM_A_DQ<48> PP1V8_S3_MEM
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<55>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<49>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQ<17>
MEM_A_DQ<20>
MEM_A_DQ<23>
MEM_A_DQ<19>
MEM_A_DQ<16>
MEM_A_DQ<59>
MEM_A_DQ<63>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<58>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<27>
MEM_A_DQ<31>
MEM_A_DQ<29>
MEM_A_DQ<25>
MEM_A_DQ<30>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<24>

MEM_A_DQS_N<6>
MEM_A_DQS_N<2>
MEM_A_DQS_N<7>
MEM_A_DQS_N<3>

MEM_A_DQS_P<6>
MEM_A_DQS_P<2>
MEM_A_DQS_P<7>
MEM_A_DQS_P<3>

1

C2404

1UF1UF

20%
10V

2

X5R
0201

1

C2405

1UF

20%
10V

2

X5R
0201

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

1

C2406

10UF

20%
10V

2

X5R-CERM
0402-7

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

1

C2407

10UF

20%
10V

2

X5R-CERM
0402-7

PP1V2_S3

PP1V2_S3

PP1V2_S3

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8
A9
D4
D5
D6
G5
H5
H6

H12

J5
J6
K5
K6

K12

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12

E8
E12
G12

H8

H9
H11

J9
J10

K8
K11
L12

N8
N12
R12
U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2400

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

PP1V2_S3

PP1V2_S3

PP1V8_S3_MEM

1

C2420

1UF

20%
10V

2

X5R
0201

1

C2410

1UF

20%
10V

2

X5R
0201

1

C2430

1UF

20%
10V

2

X5R
0201

1

C2421

1UF

20%
10V

2

X5R
0201

1

C2411

1UF

20%
10V

2

X5R
0201

1

C2431

1UF

20%
10V

2

X5R
0201

1

C2422

1UF

20%
10V

2

X5R
0201

1

C2412

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2432

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2423

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2433

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2424

10UF

20%
10V

2

X5R-CERM
0402-7

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

24 OF 500

SHEET

21 OF 98

6.0.0

pvt

SYNC_DATE=SYNC_MASTER=

SIZE

A

D

8

67

35 4

2

1

D

678

3 245

1

LPDDR3 CHANNEL B (0-31)

D

C

B

R2500

243

1%

1/20W

MF

201

1

2

R2501

243

1%

1/20W

MF

201

U2500

LPDDR3-1600-32GB

EDFB232A1MA

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 23 6

24 23 6

24 23 6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0>
MEM_B_ZQ<1>

1

23 21 20 19

23 19

2

C2540

0.047UF

1

10%

6.3V
2

X5R
201

88 83 74 73 50 23 22 21 20 19

1

2

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_B

C2541

0.047UF

10%

6.3V
X5R
201

PP1V2_S3

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2500

0.1UF

10%
16V

2

X5R-CERM
0201

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

K3
K4

J3
J2

L3
L4

L8
G8
P8
D8

J8

B3
B4

H4

J11

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

1

2

OMIT_TABLE

C2501

0.1UF

10%
16V
X5R-CERM
0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2502

1UF

20%
10V

2

X5R
0201

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2503

20%
10V

2

X5R
0201

MEM_B_DQ<7> PP1V8_S3_MEM
MEM_B_DQ<2>
MEM_B_DQ<6>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<39>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<8>
MEM_B_DQ<13>
MEM_B_DQ<15>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<12>
MEM_B_DQ<14>
MEM_B_DQ<11>
MEM_B_DQ<40>
MEM_B_DQ<44>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<45>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<41>

MEM_B_DQS_N<0>
MEM_B_DQS_N<4>
MEM_B_DQS_N<1>
MEM_B_DQS_N<5>

MEM_B_DQS_P<0>
MEM_B_DQS_P<4>
MEM_B_DQS_P<1>
MEM_B_DQS_P<5>

1

C2504

1UF1UF

20%
10V

2

X5R
0201

1

C2505

1UF

20%
10V

2

X5R
0201

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

1

C2506

10UF

20%
10V

2

X5R-CERM
0402-7

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

1

C2507

10UF

20%
10V

2

X5R-CERM
0402-7

PP1V2_S3

PP1V2_S3

PP1V2_S3

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8
A9
D4
D5
D6
G5
H5
H6

H12

J5
J6
K5
K6

K12

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12

E8
E12
G12

H8

H9
H11

J9
J10

K8
K11
L12

N8
N12
R12
U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2500

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

PP1V2_S3

PP1V2_S3

PP1V8_S3_MEM

1

C2520

1UF

20%
10V

2

X5R
0201

1

C2510

1UF

20%
10V

2

X5R
0201

1

C2530

1UF

20%

2

X5R
0201

1

C2521

1UF

20%
10V

2

X5R
0201

1

C2511

1UF

20%
10V

2

X5R
0201

1

C2531

1UF

20%
10V10V

2

X5R
0201

1

C2522

1UF

20%
10V

2

X5R
0201

1

C2512

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2532

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2523

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2533

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2524

10UF

20%
10V

2

X5R-CERM
0402-7

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

LPDDR3 DRAM Channel B (00-31)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

25 OF 500

SHEET

22 OF 98

6.0.0

pvt

SYNC_DATE=SYNC_MASTER=

SIZE

A

D

8

67

35 4

2

1

D

678

3 245

1

LPDDR3 CHANNEL B (32-63)

D

C

B

R2600

243

1%

1/20W

MF

201

1

2

R2601

243

1%

1/20W

MF

201

U2600

LPDDR3-1600-32GB

EDFB232A1MA

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 6

24 22 6

24 22 6

24 22 6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2>
MEM_B_ZQ<3>

1

22 21 20 19

22 19

2

C2640

0.047UF

1

10%

6.3V
2

X5R
201

88 83 74 73 50 23 22 21 20 19

1

2

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_B

C2641

0.047UF

10%

6.3V
X5R
201

PP1V2_S3

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2600

0.1UF

10%
16V

2

X5R-CERM
0201

R2
P2
N2
N3
M3
F3
E3
E2
D2
C2

K3
K4

J3
J2

L3
L4

L8
G8
P8
D8

J8

B3
B4

H4

J11

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

1

2

OMIT_TABLE

C2601

0.1UF

10%
16V
X5R-CERM
0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2602

1UF

20%
10V

2

X5R
0201

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2603

1UF

20%
10V

2

X5R
0201

MEM_B_DQ<48> PP1V8_S3_MEM
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<54>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<55>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<18>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<58>
MEM_B_DQ<61>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<27>
MEM_B_DQ<31>
MEM_B_DQ<28>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<24>

MEM_B_DQS_N<6>
MEM_B_DQS_N<2>
MEM_B_DQS_N<7>
MEM_B_DQS_N<3>

MEM_B_DQS_P<6>
MEM_B_DQS_P<2>
MEM_B_DQS_P<7>
MEM_B_DQS_P<3>

1

C2604

1UF

20%
10V

2

X5R
0201

1

C2605

1UF

20%
10V

2

X5R
0201

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI
BI
BI

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

1

C2606

10UF

20%
10V

2

X5R-CERM
0402-7

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

1

C2607

10UF

20%
10V

2

X5R-CERM
0402-7

PP1V2_S3

PP1V2_S3

PP1V2_S3

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8
A9
D4
D5
D6
G5
H5
H6

H12

J5
J6
K5
K6

K12

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12

E8
E12
G12

H8

H9
H11

J9
J10

K8
K11
L12

N8
N12
R12
U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2600

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

88 83 74 73 50 23 22 21 20 19

88 83 74 73 50 23 22 21 20 19

88 83 51 23 22 21 20

PP1V2_S3

PP1V2_S3

PP1V8_S3_MEM

1

C2620

1UF

20%
10V

2

X5R
0201

1

C2610

1UF

20%
10V

2

X5R
0201

1

C2630

1UF

20%
10V

2

X5R
0201

1

C2621

1UF

20%
10V

2

X5R
0201

1

C2611

1UF

20%
10V

2

X5R
0201

1

C2631

1UF

20%
10V

2

X5R
0201

1

C2622

1UF

20%
10V

2

X5R
0201

1

C2612

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2632

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2623

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2633

10UF

20%
10V

2

X5R-CERM
0402-7

1

C2624

10UF

20%
10V

2

X5R-CERM
0402-7

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

26 OF 500

SHEET

23 OF 98

6.0.0

pvt

SYNC_DATE=SYNC_MASTER=

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

C

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

20 6

21 6

21 6

21

21 6

21 6

21 6

21 6

21 6

21 6

21 6

21 6

21 6

21 6

21 6

21 20 6

21 20 6

21 20 6

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

88 83 73 24 88 83 73 24

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_A_CAA<9>
MEM_A_CAA<8>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<5>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_CAA<4>
MEM_A_CAA<3>
MEM_A_CAA<2>
MEM_A_CAA<1>
MEM_A_CAA<0>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<5>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_CAB<4>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>

R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730

68
68
68
68
68
39
39
82
82
68
68
68
68
68
68
68
68
68
68
39
39
82
82
68
68
68
68
68
82
82
82

PP0V6_S0_DDRVTT

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

1/20W MF2011%

1/20W1%

1% MF

1/20W 201 MF1%

1/20W 201 MF1%

1%

1/20W MF201
1/20W MF1%

1% 201 MF

1/20W

1% MF1/20W

201 MF1/20W1%

201 MF1/20W1%

201 MF1/20W1%

201 MF1/20W1%

201 MF1/20W1%
201 MF1/20W1%

2011/20W
201 MF1% 1/20W
201 MF1/20W1%

2011/20W1%
201 MF1/20W1%
2011/20W1%

2011/20W1%

201

201
201 MF1% 1/20W

MF2011/20W1%

MF2011/20W1%
MF2011/20W1%

MF2011/20W1%

MF2011/20W1%
MF2011/20W1%

MF2011/20W1%

MF201

MF2011/20W1%

MF

MF
MF2011/20W1%
MF

1

C2700

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2701

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2703

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2705

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2707

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2709

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

22 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 6

23 22 6

23 22 6

23 22 6

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<4>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_CAB<4>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<1>
MEM_B_CAB<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>

R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770

68
68
68
68
68
39
39
82
82
68
68
68
68
68
68
68
68
68
68
39
39
82
82
68
68
68
68
68
82
82
82

PP0V6_S0_DDRVTT

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

1% 201 MF1/20W

201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%

201 MF1/20W1%

201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%
201 MF1/20W1%

D

MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%
MF2011/20W1%

MF1/20W 2011%
MF2011/20W1%
MF2011/20W1%

MF2011/20W1%

MF2011/20W1%
MF2011/20W1%

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2711

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2713

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2715

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2717

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2719

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2712

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2714

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2716

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2718

0.47UF

20%
4V

2

CERM-X5R-1
201

C

B

CRITICAL

1

C2720

20UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C2740

20UF

20%

6.3V

2

CERM-X5R
0402

B

A

8

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

A

LPDDR3 DRAM Termination

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

27 OF 500

SHEET

24 OF 98

1

SIZE

D

678

3 245

1

D

C

B

A

1

R2890

3.3K

5%
1/20W
MF
201

2

TBT_X_SPI_CLK

27

TBT_X_SPI_CS_L

27

TBT_X_ROM_WP_L

25

TBT_X_ROM_HOLD_L

4

4

4

4

4

4

4

4

4

BI

4

BI

4

4

4

4

4

4

4

4

4

BI

4

BI

100K

10K

NOSTUFF

100K

100K

100K

100K

100K

100K

DP_X_SNK0_ML_C_P<0>

IN

DP_X_SNK0_ML_C_N<0>

IN

DP_X_SNK0_ML_C_P<1>

IN

DP_X_SNK0_ML_C_N<1>

IN

DP_X_SNK0_ML_C_P<2>

IN

DP_X_SNK0_ML_C_N<2>

IN

DP_X_SNK0_ML_C_P<3>

IN

DP_X_SNK0_ML_C_N<3>

IN

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

IN

DP_X_SNK1_ML_C_N<0>

IN

DP_X_SNK1_ML_C_P<1>

IN

DP_X_SNK1_ML_C_N<1>

IN

DP_X_SNK1_ML_C_P<2>

IN

DP_X_SNK1_ML_C_N<2>

IN

DP_X_SNK1_ML_C_P<3>

IN

DP_X_SNK1_ML_C_N<3>

IN

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

21

21

PU for NVM

21

5% 1/20W MF 201

21

5% MF1/20W 201

21

21

21

21

R2891

R2864

MF

R2839

MF1/20W

R2863
R2873
R2862

MF1/20W5% 201

R2872

1/20W5% MF

R2860

1/20W5% MF

R2861

1/20W

MF5% 201

1

3.3K

5%

1/20W

MF

201

1

2

R2893

3.3K

5%
1/20W
MF
201

2

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

PP3V3_TBT_X_SX

2011/20W5%

2015%

TBT_X_BATLOW_L

TBT_X_TMU_CLK_IN

TBT_X_TMU_CLK_OUT

DP_XA_HPD

201

201

DP_XB_HPD

TBT_XA_USB2_MXCTL

TBT_XB_USB2_MXCTL

PP3V3_UPC_XB_LDO

5%

1/20W

MF

201

1

2

R2892

3.3K

8

VCC

U2890

8MBIT-3.0V

W25Q80DVUXIE

USON

DI(IO0)
DO(IO1)

5
2

OMIT_TABLE

CRITICAL

GND EPAD

9

4

SNK0 AC Coupling

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

C2828

0.22UF

C2829

0.22UF

21
X5R

21
20% 6.3V 0201

X5R
21
X5R

21
X5R
21

20% 02016.3V
X5R

21
X5R
21

20% 6.3V 0201
X5R

21
20% 6.3V 0201

X5R

21
X5R

21
X5R

DP_X_SNK0_ML_P<0>

6.3V 020120%

DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

6.3V

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

DP_X_SNK0_AUXCH_N

SNK1 AC Coupling

C2830

0.22UF

C2831

0.22UF

C2832

0.22UF

C2833

0.22UF

C2834

0.22UF

C2835

0.22UF

C2836

0.22UF

C2837

0.22UF

C2838

0.22UF

C2839

0.22UF

21
20%

X5R
21
20%

X5R
21

20%
X5R

21
X5R
21
X5R

21
20%

X5R
21
X5R

21
X5R

21
X5R

21
X5R

25

25

25

25

25

DP_X_SNK1_ML_P<0>

6.3V 0201

DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>

DP_X_SNK1_ML_N<1>

6.3V 020120%

DP_X_SNK1_ML_P<2>

6.3V

DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>

6.3V20%

DP_X_SNK1_ML_N<3>

6.3V 020120%

DP_X_SNK1_AUXCH_P

6.3V 020120%

DP_X_SNK1_AUXCH_N

6.3V 020120%

74 29 28 26 25

28 25

29 25

1

C2890

1UF

10%

6.3V

2

CERM
402

TBT_X_SPI_MOSI
TBT_X_SPI_MISO

02016.3V20%

020120%

02016.3V20%

02016.3V20%

02016.3V20%

02016.3V

02016.3V

020120%

02016.3V

0201

29 27 25

V23
V22

P23
P22

K23
K22

F23
F22

T4

N16Y6

AB21
AC21

AC19
AB19

AB17
AC17

AC15
AB15

N4
N5

R5

W1
W2

W4
Y1
Y2
AA1
W6

V2
V1
V5
V4
U2
U1
T5

E5

D22
D23

Y18
W16
W18
Y16

B7
A7

A9
B9

A11
B11

A13
B13

L4
L5

E19
D19

T1

M5

R1
F19

B23

AB23

D5

H5

J9
J11

V8

PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS

NC_DP_X_SRC_ML_P<0>
NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1>
NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2>
NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3>
NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK

TBT_X_ROM_WP_L

TBT_X_TMU_CLK_OUT
TBT_WAKE_3V3_L
TBT_X_PLUG_EVENT_L

TBT_X_TMU_CLK_IN

I2C_TBT_X_SCL

I2C_TBT_X_SDA

TBT_X_USB_PWR_EN

TBT_X_CIO_PWR_EN
TBT_X_BATLOW_L

PM_SLP_S3_L

TBT_X_RTD3_PWR_EN

USBC_X_RESET_L

TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT

UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK

USBC_XB_D2R_P<2>

USBC_XB_D2R_N<2>
USBC_XB_R2D_CR_P<2>

USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<1>
USBC_XB_R2D_CR_N<1>

USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>

USBC_XB_AUXLSX1

USBC_XB_AUXLSX2

NC
NC

DP_XB_HPD

I2C_TBT_XB_INT_L

TBT_XB_USB2_MXCTL
TBT_XB_USB2_RBIAS

NC

NC

NC

NC
NC

TBTTHMSNS_D1_P

USE NEAREST GND BALL

(V9) FOR THERM_D_N

27

27

27

27

IN

PLACE_NEAR=U2800.F19:2MM

1

R2853

200

1%
1/20W
MF
201

2

To SPI Flash

BI
BI

29 25

25

53

OUT

BOM_COST_GROUP=TBT

27

OUT

27

OUT

27

OUT

27

OUT

D

27

OUT

27

OUT

27

OUT

27

OUT

PLACE_NEAR=U2800.N16:2MM

25

18 15

R2851

3.01K

1%

1/20W

MF

201

27

27

1

R2834

2

89 83 15 13 12

2.2K

5%
1/20W
MF
201

BI

27

15

29 28 12

PU at PCH

29 28 12

29

27

27

30

30

30

30

30

30

30

30

PP3V3_TBT_X_SX

NOSTUFF

1

R2837

2.2K

5%
1/20W
MF
201

2

IN

PAGE TITLE

21

29 27

29

PP3V3_UPC_XB_LDO

29 27 25

C

PP3V3_TBT_X_SX

1

R2835

2.2K

5%
1/20W
MF
201

2

28 27

BI

29 28 27

1

R2810

100K

5%
1/20W
MF
201

2

74 29 28 26 25

B

74 29 28 26 25

A

SYNC_DATE=SYNC_MASTER=

IN

27

OUT
OUT

25

25

OUT
OUT

IN
IN

25

IN

IN

IN

OUT

IN
IN

OUT
OUT

OUT
OUT

IN
IN

84 29

84 29

USB-C HIGH SPEED 1

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05309

REVISION

6.0.0

BRANCH

pvt

PAGE

28 OF 500

SHEET

25 OF 98

27

27

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

14

OUT

74 29 28 26 25

PLACE_NEAR=U2800.H19:2MM

TBT_X_CLKREQ_L

R2854

1/20W

PLACE_NEAR=U2800.J5:2MM
PLACE_NEAR=U2800.J6:2MM

4

R2830

4

R2831

1

R2825

100

5%
1/20W
MF
201

2

PP3V3_TBT_X_SX

R2836

28 27

TBT_XA_USB2_RBIAS

1

200

1%
MF

201

2

TF

R2828

1/20W

201

OUT

1

100K

5%

1/20W

MF

201

2

OUT

1

100K

5%

1/20W

MF

201

2

NOSTUFF

1

2.2K

5%

1/20W

MF

201

2

IN

1/20W

R2855

1K

21
5%
MF

1

R2829

100

5%
1/20W
MF
201

2

21

4.75K

0.5%
0201

27

27

27

27

27

27

27

27

84 14

84 14

12

12

12

12

30

30

30

30

30

30

30

84 28

84 28

28 25

PCIE_TBT_X_R2D_P<0>

IN

PCIE_TBT_X_R2D_N<0>

IN

PCIE_TBT_X_R2D_P<1>

IN

PCIE_TBT_X_R2D_N<1>

IN

PCIE_TBT_X_R2D_P<2>

IN

PCIE_TBT_X_R2D_N<2>

IN

PCIE_TBT_X_R2D_P<3>

IN

PCIE_TBT_X_R2D_N<3>

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_R_L

DP_X_SNK0_ML_P<0>

25

DP_X_SNK0_ML_N<0>

25

DP_X_SNK0_ML_P<1>

25

DP_X_SNK0_ML_N<1>

25

DP_X_SNK0_ML_P<2>

25

DP_X_SNK0_ML_N<2>

25

DP_X_SNK0_ML_P<3>

25

DP_X_SNK0_ML_N<3>

25

DP_X_SNK0_AUXCH_P

25

DP_X_SNK0_AUXCH_N

25

DP_X_SNK0_HPD
DP_X_SNK1_ML_P<0>

25

DP_X_SNK1_ML_N<0>

25

DP_X_SNK1_ML_P<1>

25

DP_X_SNK1_ML_N<1>

25

DP_X_SNK1_ML_P<2>

25

DP_X_SNK1_ML_N<2>

25

DP_X_SNK1_ML_P<3>

25

DP_X_SNK1_ML_N<3>

25

DP_X_SNK1_AUXCH_P

25

DP_X_SNK1_AUXCH_N

25

DP_X_SNK1_HPD

JTAG_ISP_TDI

IN

JTAG_TBT_X_TMS

IN

JTAG_ISP_TCK

IN

OUT

JTAG_ISP_TDO
TBT_X_TEST_EN

TBT_X_TEST_PWR_GOOD

USBC_XA_D2R_P<2>

IN

USBC_XA_D2R_N<2>

IN

USBC_XA_R2D_CR_P<2>

OUT

USBC_XA_R2D_CR_N<2>

OUT

USBC_XA_R2D_CR_P<1>

OUT
OUT

BI
BI

USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>

IN

USBC_XA_D2R_N<1>

IN

USBC_XA_AUXLSX1
USBC_XA_AUXLSX2

DP_XA_HPD

IN

I2C_TBT_XA_INT_L

TBT_XA_USB2_MXCTL

25

TBT_X_RBIAS
TBT_X_RSENSE

NC
NC
NC
NC

NC
NC

Y23
Y22

T23
T22

M23
M22

H23
H22

V19
T19

AC7
AB7

AB9
AC9

AC11
AB11

AB13
AC13

N1
N2

AA2

A5
B5

B3
A3

C2
C1

E2
E1

P1
P2

Y4

AC5
AB5
AC3
AB3

W20
Y20
W19
Y19

R4
W5

A15
B15

A17
B17

A19
B19

B21
A21

H4
J4

E20
D20

T2

M4

R2

H19

J6
J5

A23

A1

AC23

AC1

D4

L8

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*

DPSNK1_ML0_P
DPSNK1_ML0_N

DPSNK1_ML1_P
DPSNK1_ML1_N

DPSNK1_ML2_P
DPSNK1_ML2_N

DPSNK1_ML3_P
DPSNK1_ML3_N

DPSNK1_AUX_P
DPSNK1_AUX_N

SNK1_HPD

DPSNK2_ML0_P
DPSNK2_ML0_N

DPSNK2_ML1_P
DPSNK2_ML1_N

DPSNK2_ML2_P
DPSNK2_ML2_N

DPSNK2_ML3_P
DPSNK2_ML3_N

DPSNK2_AUX_P
DPSNK2_AUX_N

SNK2_HPD

U0_SSTXP1
U0_SSTXN1
U0_SSRXP1
U0_SSRXN1

TDI
TMS
TCK
TDO

TEST_EN
TEST_PWR_GOOD

ASSRXP2
ASSRXN2

ASSTXP2
ASSTXN2

ASSTXP1
ASSTXN1

ASSRXP1
ASSRXN1

ASBU1
ASBU2

PA_USB2_D_P
PA_USB2_D_N

PA_HPD

PA_I2C_INT

PA_USB2_MXCTL
PA_USB2_RBIAS

RBIAS
RSENSE

PA_MONDC

PB_MONDC

PC_MONDC

USB_MONDC

TEST_EDM

FUSE_VQPS_64

U2800

TITAN-RIDGE-DP

CSP

SYM 1 OF 2

OMIT_TABLE

CRITICAL

PCIE GEN3

SINK PORT 1SINK PORT 2

USBSSJTAG

TBT PORT A

DEBUG

SOURCE PORT

LC GPIOPOC GPIOFLASH

TBT PORT B

PCIE_TX0_P
PCIE_TX0_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_TX3_P
PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P
DPSRC_ML0_N

DPSRC_ML1_P
DPSRC_ML1_N

DPSRC_ML2_P
DPSRC_ML2_N

DPSRC_ML3_P
DPSRC_ML3_N

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD

GPIO_0
GPIO_1

EE_WP*

TMU_CLKOUT

WAKE*

CIO_PLUG_EVENT*

TMU_CLKIN

I2C_SCL
I2C_SDA

USB_FORCE_PWR

FORCE_PWR

BATLOW*
SLP_S3*

RTD3_PWR_EN

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO
EE_CS*
EE_CLK

BSSRXp2
BSSRXn2

BSSTXp2
BSSTXn2

BSSTXp1
BSSTXn1

BSSRXp1
BSSRXn1

BSBU1
BSBU2

PB_USB2_D_P
PB_USB2_D_N

PB_HPD

PB_I2C_INT
PB_USB2_MXCTL
PB_USB2_RBIAS

USB2_ATEST

PCIE_ATEST

MONDC_SVR

VGA_RES

ATEST_P
ATEST_N

THERMDA

8

67

35 4

2

1

678

3 245

1

D

C

B

A

88 26

PP0V9_TBT_X_SVR

1

C2930

4UF

20%

6.3V

2

CER-X5R
0201

1

2

1

C2931

4UF

20%

6.3V
CER-X5R
0201

SOURCED BY INTERNAL SWITCH

1

2

C2932

4UF

20%

6.3V

2

CER-X5R

1

C2968

10UF

20%

6.3V

2

CERM-X5R
0402-4

C2984

1.0UF

20%

6.3V
X5R
0201-1

1

C2934

4UF

20%

6.3V

2

CER-X5R

1

C2964

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2936

2

1

C2965

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

4UF

20%

6.3V
CER-X5R
0201

1

C2966

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V

1

C2920

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

SOURCED BY INTERNAL SWITCH

C2935

2.2UF

20%

6.3V
CER-X5R
02010201

1

C2967

2

1.0UF

20%

6.3V
X5R
0201-1

1

C2933

2.2UF

20%

6.3V

2

CER-X5R
02010201

PP0V9_TBT_X_PCIE

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

VOLTAGE=3.3V

PP3V3_TBT_X_ANA
PP3V3_TBT_X_ANA_PCIE
PP3V3_TBT_X_ANA_USB2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY
INTERNAL SWITCH

H11

H9
H12
H13
H15
H16

T12
T13
T15

N6

T11

T9

E8

J18

L19
M19

L18
M18
M16

E16
L16
H18

W11
Y11

Y5
W12
Y12

Y8
AB4
AC4
C23
C22
W13
AB2

D6
W15
Y15

A4

B4

F2

D2

F1

D1

B1

B2
E18
V11
V12
V13

M6
N19
N18
E12
E13
F11
F12
F13
F15
J16

A2

F8

A6

A8

B8
AB8

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC6
AC8
B10

AC10
AC12
AC14
AC16
AC18
AC20
AC22

B12

B14
B16
B18
B20
B22

D8

D9
A10
D11
D12

VCC0P9_SVR_PAB_ANA

VCC0P9_SVR_PC_ANA

VCC0P9_SVR_DPAUX_ANA

VCC0P9_SVR_USB_ANA

VCC0P9_SVR_BRD_SENSE

VCC0P9_PCIE

VCC0P9_ANA_PCIE_1

VCC0P9_ANA_PCIE_2

VCC3P3_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

N15

VSS

L15

V18

VSS

VSS

F4

VSS

R9

U2800

TITAN-RIDGE-DP

CSP

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M9

L9

R12

L12

M15

R15

VSS

M1

VCC3P3_SVR

VCC0P9_SVR

VCC0P9_LVR_SENSE

VSS

VSS

VSS

VSS

V16

M12

N9

N12

M2

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

SVR_IND

SVR_VSS

VCC0P9_LC

VCC0P9_LVR

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

VSS

T6

T18

V6

F18
R6

L6

E6

G1
G2
H2

R8
R11
L11
M8
M13
R16
R13
J13
L13
N8
N11
N13
T8
T16
M11

L1
L2
K1
K2

J1
J2
H1

J8
H8
H6

D13

D15
D16
D18
E9
E11
E15
A12
E22
E23
F9
F20
F16
G22
G23
A14
H20
J19
J20
J22
A16
J23
L20
L22
L23
A18
M20
N20
N22
N23
R18
A20
R19
R20
R22
R23
T20
U23
U22
A22
V9
V15
V20
W8
B6
W9
W22
W23
Y9
Y13
AA22
AA23
AB6
E4
J15
AB1
AC2
F5
F6
J12

PP3V3_TBT_X_LC
PP3V3_TBT_X_SX

1

C2991

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2975

10UF

20%

6.3V

2

CERM-X5R
0402-4

BYPASS=U2800.G1:J1:10MM

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_X

SWITCH_NODE=TRUE
DIDT=TRUE

PP0V9_TBT_X_LC

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V

Add XW or alias on
support page

XW

XW2900

SM

PLACE_NEAR=U2800.V9:6MM

NO_XNET_CONNECTION=1

1

C2976

10UF

20%

6.3V

2

CERM-X5R
0402-4

C2992

1.0UF

20%

6.3V
X5R

27

21

VOLTAGE=3.449
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

C2977

10UF

20%

6.3V

2

CERM-X5R
0402-4

CRITICAL

L2950

21

1210

SOURCED BY

1

2

C2993

TBTTHMSNS_D1_N

INTERNAL SWITCH

1.0UF

20%

6.3V
X5R

0201-1

SOURCED BY

74 29 28 25

FROM USB-C PORT
CONTROLLER (UPC)

1

C2981

1.0UF

20%

C2990

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2994

47UF

20%

6.3V

CER-X5R

0603

1

C2995

2

47UF

20%

6.3V

CER-X5R

0603

1

2

6.3V

2

X5R
0201-1

PP3V3_TBT_X_S0

1

C2978

10UF

20%

6.3V

2

CERM-X5R
0402-4

1

C2917

12PF

5%
25V

2

NP0-C0G
0201

1

C2950

10UF

20%
25V

2

X5R-CERM
0603

20%

6.3V

1

2

C2955

10UF

20%

6.3V

CERM-X5R

0402-40201-1

2x 10uF outside BGA area

1

C2954

10UF

2

CERM-X5R

0402-4

1

C2910

4UF

20%

6.3V

2

CER-X5R
0201

1

C2951

47UF

20%

6.3V

2

CER-X5R
0603

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.945

1

2

1

C2911

4UF

20%

6.3V

2

CER-X5R
0201 0201

1

C2952

47UF

20%

6.3V

2

CER-X5R
0603

1

2

20%

6.3V
X5R
0201-1

1

C2913

4UF

20%

6.3V

2

CER-X5R
0201

C2912

4UF

20%

6.3V
CER-X5R

INTERNAL SWITCHING VR OUTPUT

1

C2982

1.0UF

2

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.0910
MIN_NECK_WIDTH=0.0910
VOLTAGE=0V

53

OUT

PAGE TITLE

1

C2914

4UF

20%

6.3V

2

CER-X5R
0201

(SEE INTEL LAYOUT GUIDELINES)

1

C2983

1.0UF

20%

6.3V

2

X5R
0201-1

88 51 27

1

C2915

4UF

20%

6.3V

2

CER-X5R
0201

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

1

C2980

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V

1

C2916

4UF

20%

6.3V

2

CER-X5R
0201

INTERNAL SWITCH

88 26

D

C

B

A

SYNC_DATE=SYNC_MASTER=

USB-C HIGH SPEED 2

SIZE

D

BOM_COST_GROUP=TBT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05309

REVISION

6.0.0

BRANCH

pvt

PAGE

29 OF 500

SHEET

26 OF 98

8

67

35 4

2

1

678

3 245

1

D

70 62 43 42 40 37

83 72

87 83 30 28

PP1V8_AWAKE

PP20V_USBC_XA_VBUS

<rdar://25149752>

NOSTUFF

Ridge 0.9V SVR XW

P0V9_TBT_X_SVR_AGND

26

DP SRC OPTIONS

DP_X_SRC_HPD

25

USB VBUS Detect

R3081

0

21

0201MF 1/20W5%

R3080

30K

21

5%

1/20W

MF

201

XW3001

NO_XNET_CONNECTION=1

R3040

100K

1/20W

5%
MF

201

21

SOC_USB_VBUS

I1023

K

D3001

BZT52C3V0LP-COMBO

DFN1006

A

NOSTUFF

SHORT-L6-SM

21

DEBUG PATHS

PCH USB3 (DCI)

14

OUT

83 34

14

14

14

OUT

IN

IN

USB3_BSSB_D2R_P

USB3_BSSB_D2R_N

USB3_BSSB_R2D_C_P

USB3_BSSB_R2D_C_N

H9M

89 28

89 28

OUT

BI

SWD_SOC_DEBUG_SWCLK

SWD_SOC_DEBUG_SWDIO

PCH UART 2

83 12

83 12

IN

OUT

PCH_UART_DEBUG_R2D

PCH_UART_DEBUG_D2R

R3012
R3013

C3010
C3011

PLACE_NEAR=U3100.G16:5MM

R3014

R3015

PLACE_NEAR=U3100.F15:5MM

PLACE_NEAR=U3100.D15:5MM

R3016
R3017

0

21

0

21

0.1UF

21

0.1UF

21

1/20W

5%

10% 0201

10% X5R-CERM 020116V

0

0

21

0

21

PCH_UART_DEBUG_R_R2D

5% 1/20W MF 0201

0

21

PCH_UART_DEBUG_R_D2R

PLACE_NEAR=U3100.D19:5MM

XB UPC DBG [3:0]

USB3_BSSB_D2R_R_P

0201MF5%

USB3_BSSB_D2R_R_N

0201MF1/20W

USB3_BSSB_R2D_P

X5R-CERM16V

USB3_BSSB_R2D_N

XB UPC DBG [5:4]

21

SWD_SOC_SWCLK_XB

1/20W 02015% MF

SWD_SOC_SWDIO_XB

5% 0201

MF1/20W

XA UPC DBG [7:6]

1/20W5% 0201

MF

OUT

IN

IN

IN

OUT

OUT

IN

BI

28

28

PP3V3_TBT_X_S0

83 29

83 29

83 29

83 29

83 29

83 29

83 47 35 29

83 47 35 29

FOR LAYOUT PURPOSES: DIRECTLY CONNECT TO XB
THEN BRANCH OFF TO XA AND ARKANOID CONNECTOR

PLACE_NEAR=U3200.B7:7MM

I2C_UPC_SDA

I2C_UPC_SCL

PLACE_NEAR=U3200.A6:7MM

X ACE-SMC I2C SERIES R'S

RIDGE PULL UP/DOWN

88 51 26

R3043

R3044

R3045
R3046

100K

100K

21

TBT_X_HDMI_DDC_CLK

21

TBT_X_HDMI_DDC_DATA

1/20W

0

21

0

21

MF

CKPLUS_WAIVE=I2C_PULLUP

I2C_UPC_X_SDA2

5% 1/20W

CKPLUS_WAIVE=I2C_PULLUP

I2C_UPC_X_SCL2

1/20W MF5%

R3094

USBC_AARDVARKANOID

R3086

2011/20W5%

25

R3087
R3088

201MF5%

25

ROM

TBT_X_SPI_CLK
TBT_X_SPI_CS_L
TBT_X_SPI_MOSI
TBT_X_SPI_MISO

0201MF

0201

25

OUT

25

OUT

25

OUT

25

28 27

28 27

R3089

R3095
R3096
R3097
R3098

R3090
R3091
R3092
R3093

USBC_ARKANOID

100

15
15

15

15

21

15

21

15

21

15

21

15

21

15

21

15

21

15

21

ARKANOID

21

TBT_X_SPI_ARK_CLK

201MF5% 1/20W

AARDVARKANOID

21

TBT_X_SPI_DBG_CLK

21

TBT_X_SPI_DBG_CS_L

21

TBT_X_SPI_DBG_MOSI

21

TBT_X_SPI_DBG_MISO

MF 2011/20W5%

MF1/20W 2015%

201MF5%151/20W

2015% MF1/20W

XB ACE

UPC_XB_SPI_CLK

5%

201MF1/20W

UPC_XB_SPI_CS_L

1/20W5% 201

MF

UPC_XB_SPI_MOSI

1/20W5%

MF 201

UPC_XB_SPI_MISO

1/20W

MF 2015%

TR

UPC_X_SPI_CLK

1/20W5%

UPC_X_SPI_CS_L

1/20W5% 201MF

UPC_X_SPI_MOSI
UPC_X_SPI_MISO

201MF

201MF1/20W5%

201MF1/20W5%

27

OUTIN

OUT

IN

IN

IN

IN

IN

IN

27

27

27

27

29

29

29

29

25

25

25

25

USBC_AARDVARKANOID

USBC_AARDVARKANOID

USBC_AARDVARKANOID

D

USB2 OC

R3047

C

B

74 72 71 70 64
42 40 34 29 28
63 60 47 44 43

89 86 83 81

25

25

IN

OUT

TBT_X_XTAL25M_OUT

TBT_X_XTAL25M_IN

PP1V8_SLPS2R

TBT_WAKE_L

SMC HAS IPU

RIDGE TBT X ARKANOID CONN

SIGNALS CAN BE CONNECTED AT ICT TP

TR XTAL

CRITICAL

Y3000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

1

G

2

S

3

D

Q3001

DMN2250UFB

DFN1006-3

NOTE:J3001 IS DELETED DUE

TO SPACE LIMITATION.

42

PP3V3_G3H_RTC

21

R3065

100K

1/20W
5%

TBT_WAKE_3V3_L

0

21

UPC_XA_FAULT_L_R

MF1/20W5% 0201

28

Ridge PCIE Caps

C

ACE2 PULL DOWNS

UPC_XA_FAULT_L

4

R3048

0

21

UPC_XB_FAULT_L

1

C3002

20PF

31

5%
25V

2

C0G
0201

0201
C0G

2

25V
5%

20PF

1

C3003

R3039
R3038
R3037
R3036
R3035
R3034
R3033

89 86

72 71 63
50 29 28
61 57 54
83 76 74

R3032
R3031
R3030

MF201

R3029
R3028

25 35

INOUT

R3027
R3026
R3025
R3024
R3023
R3022
R3021
R3020

100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K
100K

0
0
0
0

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

1/20W5% MF 201

1/20W MF 201

5%

5% 1/20W 201MF

1/20W

5% MF1/20W

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W 201

5% 1/20W MF 201

5% 1/20W MF

1/20W

5% MF 2011/20W

1/20W5% MF 201

5%

NOSTUFF
NOSTUFF

MF5% 201

201MF1/20W5%

201

MF

201

2015% MF

201MF1/20W

201MF1/20W5%

02011/20W MF5%

02011/20W MF5%

0201MF1/20W5%

0201MF1/20W5%

PD_UPC_XA_GPIO4
PD_UPC_XB_GPIO1
PD_UPC_XB_GPIO4
PD_UPC_XB_GPIO9
PD_UPC_XB_GPIO10
PD_UPC_X_5V_EN
SPARE_UPC_XA_USB3_RN
SPARE_UPC_XA_USB3_RP
SPARE_UPC_XB_USB3_RN
SPARE_UPC_XB_USB3_RP
SPARE_UPC_XB_USB2_RN
SPARE_UPC_XB_USB2_RP
SPARE_UPC_XA_DBG0_R
SPARE_UPC_XA_DBG1_R
SPARE_UPC_XA_DBG2_R
SPARE_UPC_XA_DBG3_R
UPC_XA_VDDIO_CFG
UPC_XB_VDDIO_CFG
UPC_XA_RESET
UPC_XB_RESET

28

29

29

29

29

29 28

28

28

29

29

29

29

28

28

28

28

28

29

28

29

4

UPC_XB_FAULT_L_R

02015% MF1/20W

29

25

25

25

25

25

25

25

25

14

14

14

14

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PCIE_TBT_X_D2R_C_P<0>

0201 X5R 20%

6.3V

PCIE_TBT_X_D2R_C_N<0>

0201 X5R 6.3V 20%

PCIE_TBT_X_D2R_C_P<1>

0201 X5R 6.3V 20%

PCIE_TBT_X_D2R_C_N<1>

0201 X5R 6.3V 20%

PCIE_TBT_X_D2R_C_P<2>

0201 X5R 6.3V 20%

PCIE_TBT_X_D2R_C_N<2>

X5R0201 6.3V 20%

PCIE_TBT_X_D2R_C_P<3>

0201 X5R 6.3V

PCIE_TBT_X_D2R_C_N<3>

0201 6.3VX5R

PCIE_TBT_X_R2D_C_P<0>

0201 X5R 6.3V 20%

PCIE_TBT_X_R2D_C_N<0>

0201 X5R 6.3V 20%

PCIE_TBT_X_R2D_C_P<1>

0201 X5R 6.3V 20%

PCIE_TBT_X_R2D_C_N<1>

0201 X5R 6.3V 20%

D2R

2 1

2 1

2 1

2 1

2 1

2 1

2 1

20%

2 1

20%

R2D

2 1

2 1

2 1

2 1

C3050

0.22UF

C3051

0.22UF

C3052

0.22UF

C3053

0.22UF

C3054

0.22UF

C3055

0.22UF

C3056

0.22UF

C3057

0.22UF

C3040

0.22UF

C3041

0.22UF

C3042

0.22UF

C3043

0.22UF

PCIE_TBT_X_D2R_P<0>

PCIE_TBT_X_D2R_N<0>

PCIE_TBT_X_D2R_P<1>

PCIE_TBT_X_D2R_N<1>

PCIE_TBT_X_D2R_P<2>

PCIE_TBT_X_D2R_N<2>

PCIE_TBT_X_D2R_P<3>

PCIE_TBT_X_D2R_N<3>

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

14

14

14

14

14

14

14

14

B

25

25

25

25

A

29 25

28 27

28 27

47 35 29 28

27

29 28

ACE2 ARKANOID DEBUG CONN

I2C_TBT_XB_INT_L
I2C_UPC_X_SCL2
I2C_UPC_X_SDA2
UPC_I2C_INT_L
TBT_X_SPI_ARK_CLK
UPC_XA_UART_TX

USBC_ARKANOID

J3000

505070-1222

M-ST-SM

1413

21
43
65
87
109
1211

15

16

I2C_TBT_XA_INT_L
I2C_TBT_X_SDA
I2C_TBT_X_SCL
UPC_XA_SER_DBG
UPC_XB_SER_DBG
UPC_XA_UART_RX

14

14

14

IN

IN

IN

PCIE_TBT_X_R2D_C_P<2>

6.3V0201 X5R 20%

PCIE_TBT_X_R2D_C_N<2>

0201 X5R 6.3V 20%

PCIE_TBT_X_R2D_C_P<3>

0201 X5R 6.3V 20%

2 1

2 1

2 1

FUSES FOR UPC

AARDVARKANOID CONN

F3000

14

IN

PCIE_TBT_X_R2D_C_N<3>

0201 X5R 6.3V 20%

6A-32V

NO 3D BODY PART USED PER <RDAR://48050692>

PPDCIN_G3H

10%
35V

0201

10%
35V

0201

1

2

1

2

0603-1

F3001

6A-32V

0603-1

OMIT_TABLE

J3002

505070-1222

28 25

29 28 27 25

29 28 27 25

84 28

84 29

29 28

29 25

29

29

27

29 28 27 25

29 28 27 25

PP3V3_UPC_XB_LDO

UPC_XB_SWD_DATA
UPC_XB_SWD_CLK
TBT_X_SPI_DBG_MISO
I2C_TBT_X_SDA
I2C_TBT_X_SCL

15

SM

1413

21
43
65
87
109
1211

16

TBT_X_SPI_DBG_CS_L
TBT_X_SPI_DBG_CLK
TBT_X_SPI_DBG_MOSI
UPC_XA_SWD_CLK
UPC_XA_SWD_DATA

PP3V3_UPC_XA_LDO

27

27

27

28

28

28

C3020

0.1UF

CER-X5R

C3021

0.1UF

CER-X5R

21

PPDCIN_XA_G3H_F

PLACE_NEAR=U3100:5MM

CRITICAL

740S00053

21

PPDCIN_XB_G3H_F

PLACE_NEAR=U3200:5MM

CRITICAL

87 28

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

87 29

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=TBT

IV ALL RIGHTS RESERVED

2 1

C3044

0.22UF

C3045

0.22UF

C3046

0.22UF

C3047

0.22UF

USB-C SUPPORT

Apple Inc.

PCIE_TBT_X_R2D_P<2>

PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>

PCIE_TBT_X_R2D_N<3>

DRAWING NUMBER

051-05309

REVISION

BRANCH

PAGE

30 OF 500

SHEET

27 OF 98

OUT

OUT

OUT

OUT

6.0.0
pvt

25

25

25

25

A

SIZE

D

8

67

35 4

2

1

678

PRIMARY USB-C PORT CONTROLLER (UPC) [FRONT LEFT]

3 245

1

D

C

GND I2C_ADDR
PRIMARY ONLY

R3103

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

15K

0.1%
1/20W
TF-LF

0201

1

2

TO SMC

C3101

1UF

10%
35V
X5R

0402

PP20V_USBC_XA_VBUS

1

2

27 28 30 83 87

<CVBUS>

D

27 28 87

PP3V3_G3H_RTCPPDCIN_XA_G3H_F

MAX 100UF TOTAL ON RAIL

20%

6.3V

1

2

29 46 50 51 52 54 55 68 75 83
86

PP5V_G3S

C3100

10UF

CERM-X5R

0402-1

<CVIN_3V3>

NOSTUFF

1

C3111

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

K9

L10

M9

K11

N10

PP_5V0

L12

M11

N12

<CPP_5V0>

27

12 29

IN
IN

UPC_XA_RESET
TBT_POC_RESET
NC_USBC_XA_RESET_L

27 84

34 72 83 89

12 25 29

27 29

27

27

12 25 29

29 35 83

29 63 72 83 85

34 83

34 72 83 89

27 28

OUT

IN

IN
OUT
BI
OUT

IN
OUT
OUT

IN
OUT

IN

UPC_XA_SER_DBG

PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN
PD_UPC_X_5V_EN
PD_UPC_XA_GPIO4
UPC_XA_FAULT_L_R
TBT_X_USB_PWR_EN
SOC_DOCK_CONNECT
UPC_PMU_RESET
SOC_DFU_STATUS
SOC_FORCE_DFU

PP3V3_UPC_XA_LDO

UPC_XA_R_OSC
I2C_UPC_XA_DBG_CTL_SDA

28

I2C_UPC_XA_DBG_CTL_SCL

28

25 27 29

BI

25 27 29

BI

25 27

OUT

27

BI

27

BI

27 47

29 35

OUT

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XA_INT_L

I2C_UPC_X_SDA2
I2C_UPC_X_SCL2
UPC_I2C_INT_L

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

(LDO_CORE)
(LDO_3V3)
(LDO_3V3)

(T.B.D.)

(VDDIO)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(VDDIO, PMOS O/D)
(VDDIO)
(VDDIO)
(VDDIO)

(LDO_3V3)

(LDO_3V3)
(LDO_CORE)

(LDO_3V3, 4K IPU)
(LDO_3V3, 4K IPU)

(LDO_3V3)
(LDO_3V3)
(N/A, NMOS O/D)

(VDDIO)
(VDDIO)
(N/A, NMOS O/D)

DIGITAL CORE I/O & CONTROL

M13

N14

PP_CABLE

G2

G4

H1

H3

J2

J4

K1

K3

PP_HV

M1

L4

L2

OMIT_TABLE

U3100

CD3217

FCBGA

VER-2

CRITICAL

M3

N2

N4

POWER

TYPE-C

G6

G8

H5

H7

J6

J8

K5

K7

VBUS

L6

L8

M5

M7

N8

N6

VDDIO_CFG

LDO_3V3

VIN_3V3

VDDIO

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

20%
X5R

1

2

C3102

1.0UF

6.3V

0201-1

<CVDDIO>

UPC_XA_VDDIO_CFG

PP3V3_TBT_X_SX

UPC_XA_SS

PP1V5_UPC_XA_LDO_CORE

USBC_XA_CC1

USBC_XA_CC2

USBC_XA_CC1
USBC_XA_CC2

USBC_XA_USB_TOP_P
USBC_XA_USB_TOP_N

USBC_XA_USB_BOT_P
USBC_XA_USB_BOT_N

USBC_XA_SBU1
USBC_XA_SBU2

PP1V8_SLPS2R

27

PP3V3_UPC_XA_LDO

25 26 29 74

1

C3105

10UF

20%

6.3V

2

CERM-X5R
0402-1

<CLDO_CORE>

28 30 83

BI

28 30 83

BI

30

BI

30

BI

30

BI

30

BI

30 83

BI

30 83

BI

1

C3109

0.68UF

5%

6.3V

2

X6S
0402

<CSS>

27 29 50 54 57 61 63 71 72 74
76 83 86 89

27 29 34 40 42 43 44 47 60 63
64 70 71 72 74 81 83 86 89

1

C3114

220PF

10%
16V

2

CER-X7R
0201

1

C3113

220PF

10%
16V

2

CER-X7R
0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R
0402-1

<CLDO_3V3>

28 30 83

BI

28 30 83

BI

27 28

C

B

14

BI

14

BI

PP3V3_UPC_XA_LDO

USB2_UPC_PCH_XA_P

USB2_UPC_PCH_XA_N

27 28

L3100

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

4

32

PLACE_NEAR=U3100:5MM

29

29

84

27

27

27 28

27

83 89

83 89

27

27

25

25 84

25

27

27

27

27

27 89

27 89

27

27

BI
BI

IN

OUT

BI
BI
BI
BI

BI
BI

OUT

BI
BI
BI
BI
OUT
BI

IN

OUT

UPC_XA_SWD_DATA
UPC_XA_SWD_CLK

UPC_XA_UART_RX
UPC_XA_UART_TX

USB2_UPC_PCH_XA_F_P
USB2_UPC_PCH_XA_F_N

USB_SOC_TYPEC_P
USB_SOC_TYPEC_N
SPARE_UPC_XA_USB3_RP
SPARE_UPC_XA_USB3_RN

USBC_XA_AUXLSX1
USBC_XA_AUXLSX2

DP_XA_HPD

SPARE_UPC_XA_DBG0_R
SPARE_UPC_XA_DBG1_R
SPARE_UPC_XA_DBG2_R
SPARE_UPC_XA_DBG3_R
SWD_SOC_DEBUG_SWCLK
SWD_SOC_DEBUG_SWDIO
PCH_UART_DEBUG_R_R2D
PCH_UART_DEBUG_R_D2R

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

(LDO_3V3)
(LDO_3V3)

(LDO_3V3)
(LDO_3V3)

(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)

B

DNU
DNU
DNU

GNDPORT_MUX

GND

DNU
DNU
DNU

E18
C18
F5
D5
D17
G18

PPDCIN_XA_G3H_F
PP20V_USBC_XA_VBUS

27 28 87

27 28 30 83 87

A

1M

1M

1M

R3109

21

5% MF 201

1/20W

R3108

21

1/20W5% MF

21

R3105

MF1/20W5% 201

8

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

201

UPC_XA_UART_RX

27 28 29

28

28

A22

H9

N20

B21

K15

N22

SYNC_MASTER= SYNC_DATE=

PAGE TITLE

A

USB-C PORT CONTROLLER A

DRAWING NUMBER

051-05309

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

67

35 4

IV ALL RIGHTS RESERVED

2

REVISION

6.0.0

BRANCH

pvt

PAGE

31 OF 500

SHEET

28 OF 98

1

SIZE

D

678

SECONDARY USB-C PORT CONTROLLER (UPC) [REAR LEFT]

3 245

1

D

C

CRITICAL

R3203

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

87 29 27

83 75 68 55 54 52 51 50 46 28

28 12

84 27

28 25 12

28 27

28 25 12

83 35 28

85 83 72 63 28

29 27 25

1

15K

0.1%
1/20W
TF-LF

0201

2

28 27 25

28 27 25

27 25

83 47 35 27

83 47 35 27

47 35 28 27

86

27

25

27

27

27

27

27

27

27

27

27

PPDCIN_XB_G3H_F

MAX 100UF TOTAL ON RAIL

PP5V_G3S

IN
IN

OUT

OUT

BI

IN
OUT
BI
OUT

IN
OUT
OUT
BI
BI

IN

UPC_XB_RESET

TBT_POC_RESET
USBC_X_RESET_L

UPC_XB_SER_DBG

PD_UPC_XB_GPIO1
TBT_X_CIO_PWR_EN
PD_UPC_X_5V_EN
PD_UPC_XB_GPIO4
UPC_XB_FAULT_L_R
TBT_X_USB_PWR_EN
SOC_DOCK_CONNECT
UPC_PMU_RESET
PD_UPC_XB_GPIO9
PD_UPC_XB_GPIO10

PP3V3_UPC_XB_LDO

NC_UPC_XB_I2C_ADDR

UPC_XB_R_OSC
I2C_UPC_XB_DBG_CTL_SDA

29

I2C_UPC_XB_DBG_CTL_SCL

29

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN
OUT

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XB_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

UPC_XB_SPI_CLK
UPC_XB_SPI_MOSI
UPC_XB_SPI_MISO
UPC_XB_SPI_CS_L

NOSTUFF

1

C3211

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

<CPP_5V0>

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

N10

M9

L10

K9

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

N14

N12

M11

L12

K11

PP_5V0

(LDO_CORE)
(LDO_3V3)
(LDO_3V3)

(T.B.D.)

(VDDIO)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(LDO_3V3)
(VDDIO, PMOS O/D)
(VDDIO)
(VDDIO)
(VDDIO)

(LDO_3V3)

(LDO_3V3)
(LDO_CORE)

(LDO_3V3, 4K IPU)
(LDO_3V3, 4K IPU)

(LDO_3V3)
(LDO_3V3)
(N/A, NMOS O/D)

(VDDIO)
(VDDIO)
(N/A, NMOS O/D)

DIGITAL CORE I/O & CONTROL

G4

G2

M13

PP_CABLE

H1

H3

J2

J4

K1

K3

PP_HV

M3

M1

L4

L2

OMIT_TABLE

U3200

CD3217

FCBGA

VER-2

CRITICAL

N2

N4

POWER

TYPE-C

G6

G8

H5

H7

J6

J8

K5

K7

VBUS

L6

L8

M5

M7

N8

N6

VDDIO_CFG

LDO_3V3

VIN_3V3

VDDIO

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

1UF

10%
35V
X5R

0402

1

2

C3201

<CVBUS>

20%

6.3V

1

2

C3200

10UF

CERM-X5R

0402-1

<CVIN_3V3>

20%
X5R

1

2

C3202

1.0UF

6.3V

0201-1

<CVDDIO>

UPC_XB_VDDIO_CFG
PP3V3_UPC_XB_LDO

PP3V3_TBT_X_SX

UPC_XB_SS

PP1V5_UPC_XB_LDO_CORE

USBC_XB_CC1

USBC_XB_CC2

USBC_XB_CC1
USBC_XB_CC2

USBC_XB_USB_TOP_P
USBC_XB_USB_TOP_N

USBC_XB_USB_BOT_P
USBC_XB_USB_BOT_N

USBC_XB_SBU1
USBC_XB_SBU2

PP20V_USBC_XB_VBUS

PP3V3_G3H_RTC

PP1V8_SLPS2R

27

74 28 26 25

1

C3205

10UF

20%

6.3V

2

CERM-X5R
0402-1

<CLDO_CORE>

BI
BI

BI
BI

BI
BI

BI
BI

83 30 29

83 30 29

30

30

30

30

83 30

83 30

1

C3209

0.68UF

5%

6.3V

2

X6S
0402

<CSS>

1

C3214

220PF

2

10%
16V
CER-X7R
0201

87 83 30 29

89 86 83 76

BI

BI

1

C3213

220PF

10%
16V

2

CER-X7R
0201

D

74 72 71 63 61 57 54 50 28 27

63 60 47 44 43 42 40 34 28 27

89 86 83 81 74 72 71 70 64

29 27 25

1

C3208

10UF

20%

6.3V

2

CERM-X5R
0402-1

<CLDO_3V3>

C

83 30 29

83 30 29

B

14

14

BI

BI

USB2_UPC_PCH_XB_P

USB2_UPC_PCH_XB_N

PP3V3_UPC_XB_LDO

UPC_XB_SWD_DATA
UPC_XB_SWD_CLK

UPC_XA_UART_TX
UPC_XA_UART_RX

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

27

BI

27

BI

29 28 27

4

28 27

IN

OUT

USB2_UPC_PCH_XB_F_P

32

PLACE_NEAR=U3100:5MM

29 27 25

27

27

27

27

84 25

84 25

25

83 27

83 27

83 27

83 27

83 27

83 27

89

89

BI
BI
BI
BI

BI
BI

OUT

OUT
OUT

IN

IN
OUT
BI

IN
OUT

USB2_UPC_PCH_XB_F_N

SPARE_UPC_XB_USB2_RP
SPARE_UPC_XB_USB2_RN
SPARE_UPC_XB_USB3_RP
SPARE_UPC_XB_USB3_RN

USBC_XB_AUXLSX1
USBC_XB_AUXLSX2

DP_XB_HPD

USB3_BSSB_D2R_R_P
USB3_BSSB_D2R_R_N
USB3_BSSB_R2D_P
USB3_BSSB_R2D_N
SWD_SOC_SWCLK_XB
SWD_SOC_SWDIO_XB
SMC_DEBUGPRT_R_TX
SMC_DEBUGPRT_R_RX

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

(VDDIO, IPU)
(VDDIO, IPU)

(LDO_3V3)
(LDO_3V3)

(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)
(T.B.D.)

B

DNU
DNU
DNU

GNDPORT_MUX

GND

DNU
DNU
DNU

E18
C18
F5
D5
D17
G18

PPDCIN_XB_G3H_F
PP20V_USBC_XB_VBUS

87 29 27

87 83 30 29

A

1M

1M

1M

R3209

21

5% 201

1/20W MF

R3208

21

5% 2011/20W

21

R3205

5% MF1/20W

MF

201

8

I2C_UPC_XB_DBG_CTL_SCL

I2C_UPC_XB_DBG_CTL_SDA

UPC_XA_UART_TX

H9

N20

A22

29

29

29 28 27

67

B21

K15

N22

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

A

USB-C PORT CONTROLLER B

DRAWING NUMBER

051-05309

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

35 4

IV ALL RIGHTS RESERVED

2

REVISION

6.0.0

BRANCH

pvt

PAGE

32 OF 500

SHEET

29 OF 98

1

SIZE

D

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

678

3 245

1

D

C

B

CC1

TBT_R2D0

TBT_D2R0

SBU2
USB2 BOT

USB2 BOT

SBU1

TBT_R2D1

TBT_D2R1

CC2

NSR20F40NX_G

29 83

BI

25

IN

25

IN

25

25

29 83

29

29

OUT

OUT

BI
BI
BI

USBC_XB_D2R_N<1>

USBC_XB_D2R_P<1>
USBC_XB_SBU2

USBC_XB_USB_BOT_N
USBC_XB_USB_BOT_P

D3386

28

BI

28

BI

28 83

BI

25

25

25

25

28 83

IN

IN

OUT

OUT
BI

USBC_XA_R2D_CR_P<2>

USBC_XA_R2D_CR_N<2>

USBC_XA_CC2

21

GND_VOID=TRUE

D3374

SESDL2011

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

27 28 30 83 87

CRITICAL

PP20V_USBC_XA_VBUS

K

DSN2-THICKSTNCL

D3300

DSN2

A

29 83 87

USBC_XB_CC1

USBC_XB_R2D_CR_N<1>

USBC_XB_R2D_CR_P<1>

21

21

D3371

SESDL2011

SESDL2011

GND_VOID=TRUE

DSN2-THICKSTNCL

GND_VOID=TRUE

DSN2-THICKSTNCL

USBC_XA_USB_BOT_N
USBC_XA_USB_BOT_P

USBC_XA_SBU1

USBC_XA_D2R_P<2>

USBC_XA_D2R_N<2>

21

GND_VOID=TRUE

D3375

SESDL2011

DSN2-THICKSTNCL

21

GND_VOID=TRUE

D3376

SESDL2011

DSN2-THICKSTNCL

K

D3301

A

PP20V_USBC_XB_VBUS

NSR20F40NX_G

GND_VOID=TRUE

R3371

GND_VOID=TRUE

R3370

GND_VOID=TRUE

R3352

GND_VOID=TRUE GND_VOID=TRUE

R3353

21

D3372

SESDL2011

DSN2-THICKSTNCL

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

21

GND_VOID=TRUE

GND_VOID=TRUE

21

D3373

SESDL2011

R3373

1

5%

1/20W

R3372

R3326

1

5% 1/20W

R3327

1

1/20W

5%

GND_VOID=TRUE

DSN2-THICKSTNCL

GND_VOID=TRUE

2

21

GND_VOID=TRUE

2

MF 201

2

MF

D3377

SESDL2011

1610-COMBO

ESDA25P35-1U1M-COMBO

DSN2-THICKSTNCL

PLACE_NEAR=J3300.53:5mm

NOSTUFF

CRITICAL

K

D3370

DSN2

A

GND_VOID=TRUE

21

2

5%

GND_VOID=TRUE

21

2

5%

1/20W

GND_VOID=TRUE

21

5% 1/20W MF 201

21

2

201MF

GND_VOID=TRUE

2

2011/20W5% MF

2

GND_VOID=TRUE

2

201

DZ3301

ESDL20-1BF4

USBC_XB_D2R_R_N<1>

2

USBC_XB_D2R_R_P<1>

2

1/20W

GND_VOID=TRUE

D3354

ESD-SLP-COMBO

USBC_XA_R2D_C_P<2>

USBC_XA_R2D_C_N<2>

USBC_XA_D2R_R_P<2>

USBC_XA_D2R_R_N<2>

21

0201

201MF1/20W

USBC_XB_R2D_C_P<1>

USBC_XB_R2D_C_N<1>

201MF

MF 2015%

GND_VOID=TRUE

2

X3DFN2

1

GND_VOID=TRUE

2

X3DFN2

2

1

GND_VOID=TRUE

GND_VOID=TRUE

2

D3312

1

ESD-SLP-COMBO

1

GND_VOID=TRUE

C3381

GND_VOID=TRUE

C3380

X3DFN2

D3349

DZ3350

ESDL20-1BF4

ESD-SLP-COMBO

GND_VOID=TRUE

25V X5R

GND_VOID=TRUE

C3383

C3382

GND_VOID=TRUE

X3DFN2

GND_VOID=TRUE

21

0.33UF

21

0.33UF

25V 10%

D3328

DZ3303

ESDL20-1BF4

0201

ESD-SLP-COMBO

<RDAR://52485973>
<RDAR://48380003>

D3399

TVS2200

WSON

4

IN

5

IN

6

IN

GND

GND

GND

3

2

1

K

1610-COMBO

ESDA25P35-1U1M-COMBO

D3302

A

NOSTUFF

GND_VOID=TRUE

C3391

GND_VOID=TRUE

C3390

21

21

21

0201

C3373

10% 0201

C3372

25V10%

GND_VOID=TRUE

25V10%

21

R3325

220K

EPAD

7

0.33UF

25V10% 0201

0.33UF

10% 25V

GND_VOID=TRUE

2015% 1/20W

2

MF

R3351

1

220K

GND_VOID=TRUE

21

0.22UF

GND_VOID=TRUE

21

0.22UF

X5R 0201

CER-X5R

CER-X5R

201MF

GND_VOID=TRUE

2

2

GND_VOID=TRUE

1

1

1/20W

5%

GND_VOID=TRUE

21

21

GND_VOID=TRUE

CER-X5R

GND_VOID=TRUE

GND_VOID=TRUE

2

1

0.22UF

0.22UF

0201CER-X5R

GND_VOID=TRUE

2015% 1/20W MF

R3350

220K

R3349

220K

PLACE_NEAR=J3300.3:5mm

GND_VOID=TRUE

2011/20W MF5%

USBC_XA_R2D_P<2>

USBC_XA_R2D_N<2>

USBC_XA_D2R_CR_P<2>

0201

USBC_XA_D2R_CR_N<2>

0201

2011/20W

2015%

GND_VOID=TRUE

2

2

MF

R3324

220K

R3329

5%

MF

1/20W

220K

GND_VOID=TRUE

R3328

1

1

220K

PLACE VBUS CAP NEAR EACH VBUS PIN

X5R 020125V10%

USBC_XB_D2R_CR_N<1>

USBC_XB_D2R_CR_P<1>

GND_VOID=TRUE

2

2

R3348

1

1

220K

MF 2015%

1/20W

020110% 25V X5R

21

2011/20W MF5%

DZ3352

ESDL20-1BF4

<RDAR://52485973>
<RDAR://48380003>

D3398

TVS2200

WSON

4

IN

5

IN

6

IN

GND

GND

GND

3

2

1

USBC_XB_R2D_N<1>

USBC_XB_R2D_P<1>

0201

EPAD

7

20875-056E-01

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

J3300

F-ST-SM

PWR

SIGNAL

PWR

GND

5857

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645

GND_VOID=TRUE

4847

GND_VOID=TRUE

5049
5251
5453
5655

6059

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

TP_USBC_PP20V_XB

USBC_XB_R2D_N<2>

USBC_XB_R2D_P<2>

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

USBC_XA_D2R_CR_P<1>
USBC_XA_D2R_CR_N<1>

TP_USBC_PP20V_XA

USBC_XA_R2D_P<1>
USBC_XA_R2D_N<1>

83

GND_VOID=TRUE

2

2

R3319

1

1

5% 201MF1/20W

220K

83

OUT

GND_VOID=TRUE GND_VOID=TRUE

C3392

GND_VOID=TRUE GND_VOID=TRUE

C3393

USBC_XB_D2R_CR_N<2>
USBC_XB_D2R_CR_P<2>

GND_VOID=TRUE

GND_VOID=TRUE

201

2

2

R3354

1

1

1/20W5% MF

220K

GND_VOID=TRUE GND_VOID=TRUE

C3370

GND_VOID=TRUE

C3371

GND_VOID=TRUE

201

MF

R3318

R3321

5% 1/20W

220K

220K

R3358

220K

10%25V X5R

C3384

C3385

25V

GND_VOID=TRUE

201

2

2

MF5%

1

1

1/20W

GND_VOID=TRUE

201

MF

R3356

1/20W

1/20W 2015% MF

5%

220K

21

0.22UF

GND_VOID=TRUE

21

0.22UF

X5R10%25V

GND_VOID=TRUE

10%25V CER-X5R 0201

GND_VOID=TRUE

10% 0201

GND_VOID=TRUE

MF

R3320

1/20W5% 201

220K

21

10%25V X5R 0201

10%25V X5R 0201

C3386
C3387

GND_VOID=TRUE

2

2

0.22UF

21

0.22UF

10%25V CER-X5R

10%25V CER-X5R 0201

GND_VOID=TRUE

201

MF1/20W

R3355

1

1

5%

220K

0201

0201

GND_VOID=TRUE

21

0.33UF

GND_VOID=TRUE

21

0.33UF

CER-X5R

0201

DZ3300

ESDL20-1BF4

USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<2>

GND_VOID=TRUEGND_VOID=TRUE

21

0.33UF

0201

21

0.33UF

GND_VOID=TRUE

GND_VOID=TRUE

21

X3DFN2

DZ3353

D3358

ESDL20-1BF4

0201

ESD-SLP-COMBO

USBC_XA_R2D_C_P<1>

USBC_XA_R2D_C_N<1>

USBC_XA_D2R_R_P<1>

USBC_XA_D2R_R_N<1>

GND_VOID=TRUE

21

X3DFN2

2

2

D3304

1

1

ESD-SLP-COMBO

R3376
R3377

GND_VOID=TRUE

USBC_XB_D2R_R_N<2>
USBC_XB_D2R_R_P<2>

GND_VOID=TRUE

2

2

X3DFN2

0201

D3360

1

1

ESD-SLP-COMBO

GND_VOID=TRUE

R3374

GND_VOID=TRUE

R3375

5% MF1/20W

5% MF 2011/20W

GND_VOID=TRUE

R3323

1/20W MF 2015%

GND_VOID=TRUE

R3322

GND_VOID=TRUE

X3DFN2

21

D3329

DZ3302

ESDL20-1BF4

ESD-SLP-COMBO

PLACE_NEAR=J3300.52:5mm

PP20V_USBC_XA_VBUS

GND_VOID=TRUE

R3359
R3357

GND_VOID=TRUE

21

5%1/20W

5% MF 2011/20W

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

21

MF 201

21

5%1/20W MF 201

5%1/20W MF 201

DZ3351

ESDL20-1BF4

PLACE_NEAR=J3300.6:5mm

21

2

201

21

2

5%1/20W MF 201

0201

GND_VOID=TRUE

GND_VOID=TRUE

21

2

21

2

2

2

21

2

21

2

21

D3382

SESDL2011

GND_VOID=TRUE

GND_VOID=TRUE

21

GND_VOID=TRUE

D3378

SESDL2011

USBC_XB_CC2
USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<2>

GND_VOID=TRUE

USBC_XB_USB_TOP_P
USBC_XB_USB_TOP_N
USBC_XB_D2R_N<2>

GND_VOID=TRUE

USBC_XB_D2R_P<2>

USBC_XB_SBU1

21

D3383

SESDL2011

GND_VOID=TRUE

DSN2-THICKSTNCL

D3384

SESDL2011

GND_VOID=TRUE

DSN2-THICKSTNCL

USBC_XA_SBU2

USBC_XA_R2D_CR_P<1>

USBC_XA_R2D_CR_N<1>

USBC_XA_USB_TOP_P
USBC_XA_USB_TOP_N

USBC_XA_D2R_P<1>

USBC_XA_D2R_N<1>

USBC_XA_CC1

21

GND_VOID=TRUE

D3379

DSN2-THICKSTNCL

SESDL2011

27 28 30 83 87

D3380

SESDL2011

DSN2-THICKSTNCL

21

GND_VOID=TRUE

DSN2-THICKSTNCL

21

GND_VOID=TRUE

DSN2-THICKSTNCL

OUT

OUT

21

D3385

SESDL2011

21

GND_VOID=TRUE

D3381

SESDL2011

DSN2-THICKSTNCL

29 83

BI

25

IN

25

IN

29

BI

29

BI

25

25

29 83

BI

GND_VOID=TRUE

DSN2-THICKSTNCL

28 83

BI

25

IN

25

IN

28

BI

28

BI

25

OUT

CC2

TBT_R2D1

USB2 TOP

TBT_D2R1

SBU1

SBU2

TBT_R2D0

USB2 BOT

TBT_D2R0

25

OUT

BI

28 83

CC1

D

C

B

A

8

LAST CHANGE: Wed Apr 1 22:57:37 2015

A

SYNC_DATE=SYNC_MASTER=

PAGE TITLE

USB-C CONNECTOR A

DRAWING NUMBER

051-05309

Apple Inc.

REVISION

6.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

pvt

PAGE

33 OF 500

SHEET

30 OF 98

1

SIZE

D