Apple X1190 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

SCHEM,MLB,X1190

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2018-01-2600110840694 ENGINEERING RELEASED

D

C

B

CSAPAGE

1
2
3
4 PD Parts
5
6
7
8

1
2
3
4
5
6
7

8
9
10

10

CONTENTS

Table of Contents 05/24/2017
BOM Configuration 1
BOM Configuration 2

CPU DMI/PEG/FDI/RSVD
CPU Clock/Misc/JTAG/CFG
CPU DDR4 Interfaces
CPU Power
CPU Ground

CPU Decoupling 1
11 11 CPU Decoupling 2
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27
28
29
30
31
32
33

35

12

PCH RTC/CLK/ESPI/PM

13
14
15
16
17
18
19
20
22
23
24
25
26
27

PCH PCI-E/USB

PCH GPIO/MISC/NCTF

PCH Power

PCH Decoupling

CPU/PCH Merged XDP

Chipset Support 1

Chipset Support 2

DDR4 VREF Margining

DDR4 SDRAM Channel A 1 02/09/2017

DDR4 SDRAM Channel A 2

DDR4 SDRAM Channel B 1

DDR4 SDRAM Channel B 2

DDR4 Termination26

28 USB-C HIGH SPEED 1
29
30
31
32
33
34
35
36

USB-C HIGH SPEED 2

USB-C X Support

USB-C PORT CONTROLLER A

USB-C PORT CONTROLLER B

USB-C CONNECTOR A

USBC X Connector Support

TBT 5V REGULATOR

WIFI/BT: Support
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

38
39
40
41
42
43
44
45
46
47
48
49
50
51

AP & BT Conn

SoC GPIO/SEP/USB/DDR/Test

SoC AOP/AON/SMC

SoC ISP/I2C/UART/SPI/I2S

SoC PCIe

SoC Power 1

SoC Power 2

SoC Power 3

SoC Ground

SoC Project Support

MESA

Secure Element

DFR & T208 Support

SILU
SEAN
SEAN

ZIFENG_CONSTRAINTS

ZIFENG
j380_mlb
j380_mlb

ZIFENG_CONSTRAINTS

j380_mlb
SILU
SILU
ZIFENG
SILU
ZIFENG
ZIFENG
ZIFENG
ZIFENG
ZIFENG
SILU
ZIFENG
j380_mlb
j380_mlb
j380_mlb
j380_mlb
j380_mlb
j380_mlb

J132

ADITYA

ADITYA
ZIFENG
ZIFENG
SILU_J680
ADITYA

J132
J132

METE
METE
SILU
SILU

H9M and PMIC

SILU
SILU

H9M and PMIC

SILU

H9M and PMIC

SILU

SILU
SILU
SILU

SILU

DATESYNC

11/29/2017
11/29/2017
03/03/2017
09/07/2017
02/09/2017
02/09/2017
02/24/2017
02/09/20179
03/29/2017
05/24/2017
05/18/2017
07/27/2017PCH DMI/JTAG/SPI/HDA
05/18/2017
05/18/2017
05/18/2017
05/18/2017
05/24/2017
08/09/2017
05/18/2017
02/09/2017

02/09/2017
02/09/2017
02/09/2017
02/10/2017
05/11/2017
03/30/2017
04/19/2017
05/26/2017
05/26/2017
08/09/2017
04/05/2017
04/05/201734
03/29/2017
05/10/2017WIFI/BT: MODULE 137
08/11/2017
05/26/2017
03/22/2017
03/02/2017
03/15/2017
04/04/2017
03/02/2017
05/26/2017
03/02/2017
08/09/2017SoC Shared Support
07/27/2017
05/26/2017
05/05/2017
07/27/2017

CSAPAGE DATESYNC

51
52
53

52
53
54

55
55
56
57
58
59
60
61
62
63
64
65

56

57

58

59

60

62

63 07/24/2017Audio Jack Codec

64

65

66

67

68
67 VR 3.3V G3H & Battery Conn
68
69
70
71
72
73
74
75
76
77
78
79

69

70

71

72

73 05/10/2017

74

76

77

78

79 PMIC LDOs

80

81

82
80 83
81
82
83

84

85

86
84
85
86 SSD0 S4E 3
87
88
89

88

89

90

91

92

9390
91
92
93

94

95

98
94
95
96
97
98
99

101

102

103

104

105100

CONTENTS

I2C Connections 1
I2C Connections 2
Power Sensors High Side
Power Sensors Load Side54
Power Sensors Extended 1
Power Sensors Extended 2
Thermal Sensors
Power Sensor Extended 3
Fans/SMC/AMUX Support
Audio Placeholder

Audio Right Amplifiers
Audio Flex Connectors TROY
Keyboard & Trackpad 1
Keyboard & Trackpad 266

PBUS Supply & Battery Charger
IMVP IC
IMVP VCC Block 05/24/2017
IMVP SA Block
IMVP GT Block
Power - 5V 3.3V Supply
VR 2.5V & 1.2V/VTT
PMIC BUCKS AND SWs

PMIC GPIOs & Control
VR VCCIO
Power FETs
SOC/PMIC Aliases
LCD Backlight Driver
eDP Display Connector

SSD0 S4E 187
SSD0 S4E 2

SSD0 PMIC & VR
SSD1 S4E 0
SSD1 S4E 1
SSD1 S4E 2
SSD1 S4E 3
SSD1 PMIC & VR
EDP Mux
GPU PCC
GPU Baffin PCIe
GPU Baffin Core/FB Power
GPU Baffin FB
VR 1.05V GPU & 1.35V FB
GDDR5 VRAM FB 1 [104]
GDDR5 VRAM FB 2

RAYMOND

RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
j132-audio
TROY
TROY
TROY

j132

j132
SILU
ZIFENG
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
RAYMOND

SEAN

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

SEAN
SEAN
SEAN
SEAN
SEAN

SILU

SEAN

SEAN

DATESYNC

10/02/2017
10/02/2017
10/09/2017
10/13/2017
10/13/2017
10/13/2017
06/28/2017
10/13/2017
06/13/2017
03/15/2017

12/11/2017Audio Left Amplifiers
12/11/2017
03/22/2017
03/23/2017
03/23/2017
04/27/2017
05/24/2017
05/24/2017

05/24/2017
05/16/2017
05/01/2017
06/06/2017
07/10/2017
07/27/2017
05/10/2017
06/27/2017
08/09/2017
08/07/2017
08/09/2017
01/26/2017SSD0 S4E 0
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017

05/01/2017
11/09/201799
11/09/2017100
06/21/2017
04/19/2017
04/27/2017
04/19/2017
04/19/2017

CSAPAGE

101
102
103
104

106
107
108
109

110105
106
107
108
109
110

111

112

113

114

115

116
112
113
114
115
116
117
118
119
120
121
122
123
124
125 Memory Bite/Byte Swizzle
126
127

117

118

119 GDDR5 VRAM FB 4

120

121

122

123

124

125

126

127

128

129

130

140

141
128 143
129

144

147

CONTENTS

VR GPU Core
GPU Baffin GPIO/CLK/Straps
GPU Baffin DP/GPIO
GPU Baffin VSS/Misc
USB-C HIGH SPEED 1 05/11/2017
USB-C HIGH SPEED 2
USB-C T Support
USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR A
USBC T Connector Support111
USB-C T 5V VR
GDDR5 VRAM FB 3

Power Alias 1
Power Alias 2
Signal Alias
High speed No Testpoints
DFU TEST POINTS
FCT TESTPOINTS 2
ICT, MAC-1 ,EE Testpoints
Desense Caps 1
Desense Caps 2
Desense Caps 3

Dev Support
BOM-639 2.2GHz
BOM-639 2.6GHz
BOM-639 2.9GHz
BOM Alt Table

SILU
SEAN
SILU
SEAN
J132
ADITYA
ADITYA
ZIFENG
ZIFENG
SILU_J680
ADITYA
SILU
j680_copy
j680_copy
SILU
SILU
METE
RAYMOND
RAYMOND
RAYMOND
RAYMOND
SEAN
j380_mlb
blah
j380_mlb

Debug
SEAN
j380_mlb
j380_mlb
SEAN

05/24/2017
04/19/2017
07/27/2017
11/09/2017

04/03/2017
04/19/2017
05/26/2017
05/26/2017
08/09/2017
04/05/2017
05/11/2017
02/01/2017
02/01/2017
05/01/2017
06/27/2017
05/10/2017
06/02/2017
08/07/2017
08/07/2017
08/31/2017
06/27/2017
02/09/2017
06/27/2017
02/09/2017

05/03/2017
11/29/2017
02/09/2017
02/09/2017
11/29/2017130
03/22/2017ADITYA200131 Dev Support

D

C

B

A

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Fri Jan 26 13:24:05 2018

Schematic / PCB #'s

8

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

3

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

DRAWING TITLE

SCHEM,MLB,X1190

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

1 OF 200

SHEET

1 OF 131

124567

A

SIZEDRAWING NUMBER

D

D

X1190 BOM Groups

BOM GROUP BOM OPTIONS

X1190_8L
X1190_6L
X1190_COMMON
X1190_COMMON1
X1190_COMMON2
X1190_PROGPARTS
X1190_SNS
X1190_DEVEL:ENG
X1190_DEVEL:DVT
X1190_DEVEL:PVT

ALTERNATE,S4E_L5,S4E_L6,S4E_L7,S4E_L8,OCARINA_2,S4E_X4PLUS,S4E_X8
ALTERNATE,S4E_L5,S4E_L6,OCARINA_2,S4E_X4PLUS,S4E_X6
SCH,PCB,COMMON,ALTERNATE,X1190_COMMON1,X1190_COMMON2,X1190_PROGPARTS,VRAM_ALTS
CPUPEG:X8X4X4,EDP:YES,BOARD_ID,BOARD_REV:011,SE:PROD_2017,EN_VP0R_LPS:YES

SKIP_5V3V3:AUDIBLE,XDP:YES,SYSDET:FET,VCCSPI:3V3,OCARINA_I2C:1K,SVID_PU:CORE,RF_TUNING,PBUS:3S

UPCROM_PROG:P1,WIFI_ROM:P0,BT_ROM:P2

LOADISNS,LOADRC:YES,SENSOR:DEV

ALTERNATE,X1190_SNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,WIFI_DBG,DBG_FAN,GPUROM:BLANK,VITAMIN-C:YES,PCC:YES,GPU_ROM:YES,BOOTCFG0

ALTERNATE,LOADRC:NO

ALTERNATE,LOADRC:NO

678

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

3 245

1

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00179

685-00198
985-00362

1 CRITICAL

685-00193 CRITICAL BOM_8L1

985-00362 CRITICAL DEVEL_BOM

685-00198 BOM_6L

1 CRITICAL

COMMON PARTS,MLB,X1190
S4E 8L Parts,MLB,X1190685-00193
S4E 6L Parts,MLB,X1190

DEV,MLB,X1190

COMMON PARTS, MLB, X1190

S4E 8L PARTS (8L),MLB,X1190

DEV PARTS,MLB,X1190

S4E 6L PARTS (6L),MLB,X1190

BASE

8L

DEVEL1

6L

X1190_COMMON
X1190_8L
X1190_6L
X1190_DEVEL:ENG

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BASE_BOM685-00179

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

B

DRAM Options

BOM GROUP BOM OPTIONS

MC_32G
HY_32G
HY_16G
MC_16G

S4E Options

BOM GROUP BOM OPTIONS

TS_256_PMLC
WD_256_PMLC
TS_512_PMLC
WD_512_PMLC
TS_1TB_PMLC
WD_1TB_PMLC
TS_2TB_PMLC
WD_2TB_PMLC
SM_2TB_3DV4
SM_4TB_3DV4

TS_2TB_TLC
WD_2TB_TLC

32G_MICRON_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L

32G_HYNIX_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

16G_HYNIX_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG1:L,RAMCFG0:L

16G_MICRON_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG1:L

S4E_256_TB,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_256_WD,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_512_TB,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_512_WD,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_1TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_1TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_SM,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_4TB_SM,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TLC_2TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TLC_2TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

A

BOARD ID

BOM GROUP BOM OPTIONS

BOARD_ID BOARDID0,BOARDID1,BOARDID3

VRAM ALT BOM GROUPS

BOM NUMBER BOM NAME BOM OPTIONS

685-00221
685-00222
685-00223
685-00224

VRAM PARTS,HYNIX,2X,MLB,X1190

VRAM PARTS,MICRON,2X,MLB,X1190

VRAM PARTS,SAMSUNG,2X,MLB,X1190

VRAM PARTS,HYNIX,1Z,MLB,X1190

685-00225 VRAM PARTS,MICRON,1Z,MLB,X1190

VRAM SUB-BOM

1 CRITICAL VRAM_ALTS685-00221

VRAM PARTS,HYNIX,2X,MLB,X1190

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

VRAMSSSS

FB_4GB_HYNIX

FB_4GB_MICRON

FB_4GB_SAMSUNG

FB_4GB_HYNIX_1Z

FB_4GB_MICRON_1Z

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

2 OF 200

SHEET

2 OF 131

SYNC_DATE=11/29/2017SYNC_MASTER=SEAN

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

GPU Baffin

337S00493 1 CRITICALUA000
337S00494 UA000 CRITICAL1
998-04866 UA000
998-04867

1
1

GPU,AMD,BAFFIN,ULX,A3,0.83,QS,BGA769

GPU,AMD,BAFFIN,PROX,A3,0.83,QS,BGA769

INTERPOSER,AMD,C989,BGA769,VDDCI/MVDD

INTERPOSER,AMD,C988,BGA769,VDDC

UA000

FB VDRAM Parts

333S00074
333S00075
333S00100

4
4

4
333S00173 4
333S00175

4

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,1ZNM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,1ZNM,A,170 BGA

CPU Parts CFL (Needs to be updated)

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

BAFFIN_ULX

BAFFIN_PROX

STARDUST:VDDCI_MVDD

STARDUST:VDDC

FB_4GB_SAMSUNG

FB_4GB_MICRON

FB_4GB_HYNIX

FB_4GB_MICRON_1Z

FB_4GB_HYNIX_1Z

Programmable Parts

335S00199
341S01017

1 CRITICALUB090341S01018
341S01025 1 U3750 CRITICAL
341S00725 1

IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

T29,TR1(V2.1),NEW-PROTO-2,X1190

T29,TR2(V2.1),NEW-PROTO-2,X1190

IC, BT ROM, EVT,VXX, X1190

IC, WIFI ROM, PROTO0, X1190

H9M

POP,GIBRALTAR+2GB 21NM,H,B0,SCK,CSP1406

PART NUMBER

339S00372339S00373 ALL

339S00378

339S00377

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

UA7011 CRITICAL
U2890 CRITICAL1

U3710 CRITICAL

GPUROM:BLANK

UPCROM_PROG:P1

UPCROM_PROG:P1

BT_ROM:P2

WIFI_ROM:P0

Updated-P1

Updated-P1

Updated

Updated

D

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 SOC:2GBU3900339S00373

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

2GB,20NM,M,B0,SCK,CSP1406

TABLE_ALT_ITEM

ALL339S00372

ALL339S00372

2GB,21NM,H,B0,ATK,CSP1406

TABLE_ALT_ITEM

2GB,20NM,M,B0,ATK,CSP1406

C

337S00509
337S00510
337S00513

1 CRITICALU0500

CPU,CFLH,QP87,QS,U0,2.2,45W,1.1,LGA1440

CPU,CFL-H,QP86,QS,U0,2.6,6C,45W,1.15,BGA1440

CPU,CFL-H,QPQG,QS,U0,2.9,6C,45W,1.2,BGA1440

998-12472

Main DRAM Parts

333S00131 16
333S00134
333S00147
333S00163 16

16
16

INTERPOSER,CFH-H,BGA1440

IC,SDRAM,DDR4-2400,16GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,16GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,8GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,8GBIT,20NM,BGA78

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 U0500

U05001 CRITICAL

CRITICALU05001

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

CRITICAL
CRITICAL
CRITICAL
CRITICAL

CPU_CFL:2.2
CPU_CFL:2.6
CPU_CFL:2.9

CPU_SKL:SOCKET

32G_MICRON_2400

32G_HYNIX_2400

16G_HYNIX_2400

16G_MICRON_2400

PART NUMBER

339S00375

339S00371 339S00376

339S00370

339S00376 ALL

339S00376 ALL

S4E Parts
256GB

998-12418

998-12418998-12419

4335S00324
4

POP,GIBRALTAR+1GB 21NM,H,B0,ATK,CSP1406

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

1GB,20NM,M,B0,ATK,CSP1406

ALL

NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,85GBP,S4E,170G,T,SUBX,ULGA110

ALL

1GB,21NM,H,B0,SCK,CSP1406

1GB,21NM,M,B0,SCK,CSP1406

SUBW

U3900 SOC:1GBCRITICAL1339S00376

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900

U8600,U8700,U8800,U8900

TABLE_ALT_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL

C

S4E_256_WD
S4E_256_TB

B

PCH CNL-H (Needs to be updated)

337S00523

IC,CNL,PCH-H,USFF,QNYP,QS,B0,BGA499

ACE & Ridges (Needs to Be Updated)

353S01442

338S00408

4 CRITICAL

IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96

IC,TBT,TITAN RIDGE DP,QUJK,QS,C1,CSP337

U3100,U3200,UB300,UB400

Hall Effect AMR

677-10608 CRITICALJ4800,J48012

SUBASSY T&00 PCBA, AMR, INTERPOSER, X1190

Power Controllers

353S01525 1 CRITICALU7000

IC,ISL9240HIB1Z,PMU,SOUNA,WCSP40,2.1X3.3MM

512GB

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALU12001

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALU2800,UB0002

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

335S00325
998-12420

998-12421 998-12420

1TB

998-12422

998-12422998-12423

2TB

335S00327 8
335S00321

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-12424 8

998-12426

998-12424

4
4

6335S00326
6

8

NAND,3DV3,128GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,128GBP,S4E,170G,T,SUBX,ULGA110

ALL

NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,170GBP,S4E,170G,T,SUBX,ULGA110

ALL

NAND,3DV3,256GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV4,256GBP,XXX,S4E,256G,SS,ULGA110

NAND,3DV3,256GBP,S4E,170G,T,SUBX,ULGA110

ALL

SUBW

SUBW

SUBW

U8600,U8700,U8800,U8900

U8600,U8700,U8800,U8900

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900,U9100,U9200

U8600,U8700,U8800,U8900,U9100,U9200

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

TABLE_ALT_ITEM

CRITICAL S4E_512_WD

S4E_512_TBCRITICAL

CRITICAL
CRITICAL

CRITICAL
CRITICAL

S4E_1TB_WD
S4E_1TB_TB

S4E_2TB_WD
S4E_2TB_SM

CRITICAL S4E_2TB_TB

B

338S00267 U7800 CRITICAL1

IC,SUPPLY,INTERSIL,ISL6277AHRZ,SVI2.0,QFN48

Harpoon

1339S00458 U3730

PART NUMBER

339S00428 ALL339S00458

IC,MODULE,WIFI/BT,MURATA,HARPOON,M,ES7.7,LGA385

USB-C Connector

IC,PMU,P650839,7X7MM.BGA168

IC,ISL95828A,IMVP8 CPU REG,QFN48,6X6MM

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IC,MODULE,WIFI/BT,HARPOON,USI,ES7.5,LGA385

TABLE_ALT_HEAD

TABLE_ALT_ITEM

4TB

CRITICALUA6001353S01229

335S00322 8

U7100 CRITICAL1353S00928

NAND,3DV4,512GBP,S4E,256G,SS,ULGA110

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

CRITICAL

S4E_4TB_SM

2TB TLC

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

335S00228
335S00247

8
8

NAND,3DV3,256GBT,S4E,256G,T,SLGA110

NAND,3DV3,256GBT,S4E,256G,SD,SLGA110

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

CRITICAL
CRITICAL

TLC_2TB_TB
TLC_2TB_WD

A

Ocarina

8

2998-12556

1338S00410 CRITICAL
1338S00410 CRITICAL

CONN,RCPT,56+4,P=0.35,H=0.7,SHLD,THKR

IC,PMU,OCARINA,D2499A0,OTP-AG,WLCSP56

IC,PMU,OCARINA,D2499A0,OTP-AG,WLCSP56

U9000

CRITICALJ3300,JB500

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

A

SYNC_DATE=11/29/2017SYNC_MASTER=SEAN

PAGE TITLE

BOM Configuration 2

DRAWING NUMBER

051-02643

OCARINA_2U9500

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-0

PAGE

3 OF 200

SHEET

3 OF 131

1

SIZE

D

678

3 245

1

D

C

B

A

Pogo Pins

APN 870-01771

PG0410

POGO-2.3OD-4.63H-SM

SM

1

PG0411

POGO-2.3OD-4.63H-SM

SM

1

PG0420

POGO-2.3OD-4.63H-SM

SM

1

PG0421

POGO-2.3OD-4.63H-SM

SM

1

PG0430

POGO-2.3OD-4.63H-SM

SM

1

PG0471

POGO-2.3OD-4.63H-SM

SM

1

PG0470

POGO-2.3OD-4.63H-SM

APN 870-01772

SM

1

PG0400

POGO-2.3OD-4.06H-SM

SM

1

PG0401

POGO-2.3OD-4.63H-SM

Dummy Parts to act as bumpers

SM

1

C0402

1UF

21

10%

6.3V CERM 402

CKPLUS_WAIVE=TERMSHORTED

C0403

1UF

21

10% 6.3V CERM

CKPLUS_WAIVE=TERMSHORTED

402

C0404

1UF

21

10% 6.3V CERM

CKPLUS_WAIVE=TERMSHORTED

402

C0405

1UF

21

402

CERM

6.3V10%

CKPLUS_WAIVE=TERMSHORTED

C0406

1UF

21

6.3V10% CERM

CKPLUS_WAIVE=TERMSHORTED

402

APN 860-00392

3.4OD1.75ID-1.12H-SM 3.4OD1.75ID-1.12H-SM

3.4OD1.75ID-1.12H-SM

APN 806-06520

3.4OD1.75ID-1.45H-SM

APN 806-06521

APN 860-00469

Bumpers

860-00986

SMT Bosses

BS0400

1

USB-C Left
BOT side - North

BS0410

1

USB-C Right
BOT side - North

BS0420

1

DFR Touch
BOT side

BS0430

3.4OD1.75ID-1.9H-SM

1

DFR Display
BOT side - Left

BS0450

3.4OD1.75ID-1.9H-SM

1

Trackpad
BOT side - Left

BS0470

2.7X1.8R-1.4ID-0.91H-SM

1

APN 806-07958

TOUCH-COWLING-HOOK-X378

BS0472

1

SM

DFR Touch - TOP side

1 BM0400860-00948
5

11

eDP
TOP side - Left

bumper 1

bumper 2

bumper 3

bumper 4

BS0401

1

USB-C Left
BOT side - South

BS0411

3.4OD1.75ID-1.12H-SM

1

APN 806-06600

USB-C Right
BOT side - South

BS0480

3.4OD1.75ID-2.12H-SM

1

BS0431

3.4OD1.75ID-1.9H-SM

1

DFR Display
BOT side - Right

BS0441

3.4OD1.75ID-1.9H-SM

1

Keyboard
BOT side - Right

BS0471

2.7X1.8R-1.4ID-0.91H-SM

1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 BM0411
CRITICAL

BM0484,BM0485,BM0486,BM0487,BM0488

BM0401,BM0402,BM0403,BM0406,BM0410,BM0407,BM0408,BM0483,BM0405,BM0409,BM0404

CRITICAL860-00954
CRITICAL860-00949

USB-C Right

BOT side - Left

OMIT_TABLE

APN 860-00500

BM0488

2.8OD1.2ID-3.5H-SM

1

2

eDP
TOP side - Right

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

2.8OD1.2ID-1.55H-SM

Rubber Mount

Standoffs

APN 860-00452

BM0400

3.09OD1.4ID-3.25H-SM

1
2

APN 860-00435

OMIT_TABLE

BM0401

2.8OD1.2ID-1.55H-SM

1
2

BM0402

2.8OD1.2ID-1.55H-SM

1
2

BM0403

2.8OD1.2ID-1.55H-SM

1
2

BM0404

2.8OD1.2ID-1.55H-SM

1
2

BM0405

2.8OD1.2ID-1.55H-SM

1
2

BM0483

2.8OD1.2ID-1.55H-SM

1
2

APN 860-00500

BM0484

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

BM0411

1

2

OMIT_TABLE

Shield Cans

806-11170

806-13328
806-13329
806-13324

1 SH0400 CRITICAL
2 CRITICAL806-13323 SH0401,SH0402
4

1806-13326

2

BM0406

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0407

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0408

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0409

2.8OD1.2ID-1.55H-SM

1

2

OMIT_TABLE

BM0410

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

OMIT_TABLE

APN 860-00500

BM0485

2.8OD1.2ID-3.5H-SM

1
2

BM0486

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

BM0487

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

SHIELD,FENCE,DIPLEX,X1181

SHIELD,FENCE,NAND_L5_L6,X1181

SHIELD,FENCE,NAND_L5_L6_L7_L8,X1181

SHIELD,FENCE,H9M,X1181

SHIELD,FENCE,VRAM,X1181

SHIELD,FENCE,TR,RT,X1181

SHIELD,FENCE,NAND_L1_L2_L3_L4,X1181

SHIELD,FENCE,TR,LT,X1181

SHIELD,FENCE,DRAM,X1181

SHIELD,SLED,GPU,X1181

SHIELD,SLED,CPU,X1181

Diplexer Can

OMIT_TABLE

1

SH0400

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

NAND L5/L6

OMIT_TABLE

1

OMIT_TABLE

1

SH0402

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

NAND L7/L8

OMIT_TABLE

1

1

SH0404

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

H9M

1

OMIT_TABLE

SH0405

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

VRAM

1

OMIT_TABLE

SH0406

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

TR RT

1

OMIT_TABLE

SH0407

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

NAND Right

OMIT_TABLE

1

1

SH0408

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

TR LT

1

SH0410

SM

OMIT_TABLE

SHIELD-DIPLEX-BLACK-X378A-X1099

DRAM

OMIT_TABLE

1

SH0411

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

CPU/GPU Sleds

OMIT_TABLE

1

SH0413

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SH0401,SH0402,SH0403,SH0404

SH0405
SH0406
SH0407

SH0408,SH0409

SH0410

SH0411,SH04122 CRITICAL
SH0413,SH0415
SH0414,SH0416

CRITICAL
CRITICAL806-13325 1
CRITICAL
CRITICAL806-13327 1
CRITICAL
CRITICAL1

CRITICAL806-13996 2
CRITICAL806-13997 2

BOM_COST_GROUP=MECHANICALS

SH0401

SM

SH0403

SM

OMIT_TABLE

SH0409

SM

OMIT_TABLE

1

SH0412

OMIT_TABLE

1

SH0414

SM

OMIT_TABLE

SM

S4E_X6
S4E_X8806-13323

Shield Can TH

APN 998-2691

DRAM

VRAM

SSD Right

TH0402

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0403

1

SL-1.2X0.4-1.5X0.7

TH0450

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0451

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0400

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0401

TH-NSPTH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0460

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0461

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0440

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0441

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SSD Left

1

1

1

1

TH0407

TH-NSP

TH0416

TH-NSP

TH0415

TH-NSP

TH0406

TH-NSP

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

1

1

1

1

TH0413

TH-NSP

TH0412

TH-NSP

TH0417

TH-NSP

TH0414

TH-NSP

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

H9M

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

TH0409

TH-NSP

TH0408

TH-NSP

TBT Left

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

TH0410

TH-NSP

TH0411

TH-NSP

TBT Right

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

OMIT_TABLE

1

SH0415

SM

OMIT_TABLE

1

SH0416

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

SYNC_MASTER=ZIFENG_CONSTRAINTS SYNC_DATE=03/03/2017

PAGE TITLE

TH0420

TH-NSP

TH0421

TH-NSP

PD Parts

DRAWING NUMBER

051-02643

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

4.0.0

BRANCH

evt-0

PAGE

4 OF 200

SHEET

4 OF 131

D

C

B

A

SIZE

D

8

67

35 4

2

1

D

C

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

E8

F6

E5

J9

D8
E6
D5

J8

A8
B6
A5
B4

B8
C6
B5
D4

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 1 OF 13

CRITICAL

OMIT_TABLE

DMI

PEG_RCOMP

PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

678

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9

G2

D25
F24
D23
F22
D21
F20
D19
F18
E17
E16
E15
E14
E13
E12
E11
E10

E25
E24
E23
E22
E21
E20
E19
E18
D17
F16
D15
F14
D13
F12
D11
F10

CPU_PEG_RCOMP

PEG_GPU_D2R_N<0>
PEG_GPU_D2R_N<1>
PEG_GPU_D2R_N<2>
PEG_GPU_D2R_N<3>
PEG_GPU_D2R_N<4>
PEG_GPU_D2R_N<5>
PEG_GPU_D2R_N<6>
PEG_GPU_D2R_N<7>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_T_D2R_N<0>
PCIE_TBT_T_D2R_N<1>
PCIE_TBT_T_D2R_N<2>
PCIE_TBT_T_D2R_N<3>

PEG_GPU_D2R_P<0>
PEG_GPU_D2R_P<1>
PEG_GPU_D2R_P<2>
PEG_GPU_D2R_P<3>
PEG_GPU_D2R_P<4>
PEG_GPU_D2R_P<5>
PEG_GPU_D2R_P<6>
PEG_GPU_D2R_P<7>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_T_D2R_P<0>
PCIE_TBT_T_D2R_P<1>
PCIE_TBT_T_D2R_P<2>
PCIE_TBT_T_D2R_P<3>

From Intel EDS
PEG RCOMP Range = 24.76,25.25

Voltage = VCCIO (Page 121, Note 3)

PPVCCIO_S0_CPU

1

R0510

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.G2:5mm

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

5 8 10 115

117

NC_DDI1_ML_C_N<0>

NC_DDI1_ML_C_P<0>

117

117

NC_DDI1_ML_C_N<1>
NC_DDI1_ML_C_P<1>

117

117

NC_DDI1_ML_C_N<2>
NC_DDI1_ML_C_P<2>

117

117

NC_DDI1_ML_C_N<3>
NC_DDI1_ML_C_P<3>

117

NC_DDI2_ML_C_N<0>

117

NC_DDI2_ML_C_P<0>

117

117

NC_DDI2_ML_C_N<1>

117

NC_DDI2_ML_C_P<1>
NC_DDI2_ML_C_N<2>

117

NC_DDI2_ML_C_P<2>

117

117

NC_DDI2_ML_C_N<3>

117

NC_DDI2_ML_C_P<3>

117

NC_DDI3_ML_N<2>
NC_DDI3_ML_P<2>

117

117

NC_DDI3_ML_N<3>
NC_DDI3_ML_P<3>

117

NC_DDI3_ML_N<0>

117

117

NC_DDI3_ML_P<0>

117

NC_DDI3_ML_N<1>
NC_DDI3_ML_P<1>

117

Port D pins out of order
to match Intel symbol.

K37
K36

J34

J35
H36
H37

J38

J37

H33
H34

G38

F37
F35

F34
E36
E37

E33

F33
B33
C33

D34
C34
B34
B36

3 245

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

DDI3_TXN2
DDI3_TXP2
DDI3_TXN3
DDI3_TXP3

DDI3_TXN0
DDI3_TXP0
DDI3_TXN1
DDI3_TXP1

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 11 OF 13

CRITICAL

OMIT_TABLE

EDP

DIGITAL DISPLAY INTERFACES

DISP_RCOMP

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

DDI1_AUXN
DDI1_AUXP

DDI2_AUXN
DDI2_AUXP

DDI3_AUXN
DDI3_AUXP

B26
C26

E29
E28
B29
B28

D29
F28
A29
C28

D37
A33

E27
D27

E26
F26

B27
A27

NC

DP_INT_IG_AUX_N
DP_INT_IG_AUX_P

DP_INT_IG_ML_N<0>
DP_INT_IG_ML_N<1>
DP_INT_IG_ML_N<2>
DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_P<1>
DP_INT_IG_ML_P<2>
DP_INT_IG_ML_P<3>

CPU_EDP_RCOMP

NC_DDI1_AUXCH_C_N
NC_DDI1_AUXCH_C_P

NC_DDI2_AUXCH_C_N
NC_DDI2_AUXCH_C_P

NC_DDI3_AUXCH_N
NC_DDI3_AUXCH_P

117

117

117

117

117

117

1

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

PPVCCIO_S0_CPU

1

R0530

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.D37:5mm

D

5 8 10

115

C

B

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TXN6
PEG_TXN7
PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0

PEG_TXP1

PEG_TXP2

PEG_TXP3

PEG_TXP4

PEG_TXP5

PEG_TXP6

PEG_TXP7

PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

A25
C24
A23
C22
A21
C20
A19
C18
B17
B16
B15
B14
B13
B12
B11
B10

B25
B24
B23
B22
B21
B20
B19
B18
A17
C16
A15
C14
A13
C12
A11
C10

PEG_GPU_R2D_C_N<0>
PEG_GPU_R2D_C_N<1>
PEG_GPU_R2D_C_N<2>
PEG_GPU_R2D_C_N<3>
PEG_GPU_R2D_C_N<4>
PEG_GPU_R2D_C_N<5>
PEG_GPU_R2D_C_N<6>
PEG_GPU_R2D_C_N<7>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_T_R2D_C_N<0>
PCIE_TBT_T_R2D_C_N<1>
PCIE_TBT_T_R2D_C_N<2>
PCIE_TBT_T_R2D_C_N<3>

PEG_GPU_R2D_C_P<0>
PEG_GPU_R2D_C_P<1>
PEG_GPU_R2D_C_P<2>
PEG_GPU_R2D_C_P<3>
PEG_GPU_R2D_C_P<4>
PEG_GPU_R2D_C_P<5>
PEG_GPU_R2D_C_P<6>
PEG_GPU_R2D_C_P<7>
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_R2D_C_P<1>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_R2D_C_P<3>
PCIE_TBT_T_R2D_C_P<0>
PCIE_TBT_T_R2D_C_P<1>
PCIE_TBT_T_R2D_C_P<2>
PCIE_TBT_T_R2D_C_P<3>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

TP-P5
TP-P5

TP-P5
TP-P5
TP-P5

TP0501
TP0502

TP0503
TP0504
TP0505

TP
TP

TP
TP
TP

U0500

CFL-H-DDR4-IL

BGA

1
1

1
1
1

CPU_DC_B2_C1
CPU_DC_B38_C38

CPU_DC_BR2_BR1
CPU_DC_C1_B2
CPU_DC_C38_B38

NC

NC

NC

NC

BR33

AT13

AW13

RSVD IST_TRIG

B2

RSVD

B38

RSVD

BP1

RSVD

BR2

RSVD

C1

RSVD

C38

SKTOCC*
ZVM*

MSM*

45W

SYM 13 OF 13

PROC_TRIGIN

PROC_TRIGOUT

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDR_VTT_CNTL

PM_DOWN

Impedance Spectrum Tool

E3

H23
J23

G27
G25
G29

BT13
BP31

CPU_IST_TRIG

PCH_CPU_TRIGGER
CPU_PCH_TRIGGER_R

PCH_DISPA_BCLK
PCH_DISPA_SDO
CPU_PROC_AUD_SDO_R

PM_MEMVTT_EN
CPU_PCH_PM_DOWN_R

Each corner of CPU has two testpoints.

5

5

IN

IN
IN

5

OUT

13

20

20

1

TP-P6

1

TP-P6

PLACE_NEAR=TP0506.1:5mm

119 74

A

TP0506

A

TP0507

B

Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP's on each corner.

R0524

5

CPU_PCH_TRIGGER_R

30

5%

1/20W

MF

201

CPU_PCH_TRIGGER

21

OUT

13

A

5

5

BOM_COST_GROUP=CPU & CHIPSET

CPU_PCH_PM_DOWN_R

CPU_PROC_AUD_SDO_R

SYNC_MASTER=ZIFENG SYNC_DATE=09/07/2017

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R0525

20

5%

1/20W

MF

201

R0526

20

5%

1/20W

MF

201

CPU_PCH_PM_DOWN

21

21

PCH_DISPA_SDI

Apple Inc.

13

OUT

20

OUT

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

5 OF 200

SHEET

5 OF 131

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

8 11 115

8 11 46 115

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

PP1V05_S0SW
PP1V05_S3

46

CPU_PROCHOT_L

IN

119 46

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1K

5%

1/20W

MF

201

NOSTUFF

R0647

1K

5%

1/20W

MF

201

CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1K

5%

1/20W

MF

201

1

2

1

2

R0648

NOSTUFF

1

R0643

1K

5%
1/20W
MF
201

2

NOSTUFF

R0641

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0640

1K

5%
1/20W
MF
201

2

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>

CPUCFG5_PDCPUCFG6_PD

1

R0645

1K

5%
1/20W
MF
201

2

EDP:YES

R0644

1K

5%

1/20W

MF

201

1

2

1

2

R0646

1K

5%

1/20W

MF

201

1

2

CPU_CFG<2>

NOSTUFF

1

R0642

1K

5%
1/20W
MF
201

2

18 6

18 6

18 6

18 6

18 6

PP0600
PP0601

PP0602
PP0603

18 6

18 6

18 6

18 6

18 6

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

OUT

1

CPU_RSVD_R14

1

CPU_RSVD_N29

1

CPU_RSVD_AE29

1

CPU_RSVD_AA14

TP0619

1

R0605

1K

1%
1/16W
MF-LF
402

2

A

TP-P6

NOSTUFF

1

R0604

1K

1%
1/16W
MF-LF
402

2

1

TP_CPU_RSVD_TP_D1

PPVCC_S0_CPU

8 58 115

6

6

6

6

1

R0601

1K

1%
1/16W
MF-LF
402

2

6

6

6

6

CPU_RSVD_R14
CPU_RSVD_N29
CPU_RSVD_AE29
CPU_RSVD_AA14

77

OUT

PLACE_NEAR=U0500.BR30:5mm

R0603

499

201

1%
1/20W

MF

46 13

21

13

13

121 119 13

118 12

118 12

118 12

118 12

118 12

118 12

BI

IN
IN
IN

IN
IN

IN
IN

IN
IN

D1

V30
V12
V29
Y35

R14

N29
AE29
AA14

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC
CPU_RESET_L
CPU_PWRGD

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

CRITICAL
OMIT_TABLE

RSVD_TP

VSS
VSS
VSS
VCC

RSVD
RSVD
RSVD
RSVD

PLACE_NEAR=U0500.BT31:157mm

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 12 OF 13

RESERVED

CFG_RCOMP

(IPU)

(IPU)

R0611

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD
RSVD
RSVD

RSVD

10K

5%
1/16W
MF-LF

402

BT25
BP23

BN22
BN23
BP22

AU13
AY13
J24
J3

BN33

U0500

CFL-H-DDR4-IL

BN1

NC

BM30

BT34

BR30

BM34

BP35
BT31

1

2

PROC_SELECT*

CATERR*

PECI

PROCHOT*

J31

THERMTRIP*

PM_SYNC
RESET*
PROCPWRGD

D31

CLK24N

E31

CLK24P

C36

PCI_BCLKN

D35

PCI_BCLKP

A32

BCLKN

B31

BCLKP

CRITICAL
OMIT_TABLE

CPU_CFG_RCOMP
CPU_CFG<16>

CPU_CFG<18>
CPU_CFG<17>
CPU_CFG<19>

NC
NC
NC
NC

NC

BGA
45W

SYM 2 OF 13

THERMALPWRCLOCK

18 6

18

1

TP-P5

1

TP-P5

DDR3

(IPU)
(IPU)

(IPD)
(IPU)

(IPU)

(IPU)

JTAG

TP

TP0617

TP

TP0618

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

PROC_PRDY*

PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

(IPU)
(IPU)
(IPU)
(IPU)

BPM0*
BPM1*
BPM2*
BPM3*

G1
H1
J2

BP27
BL30

BR28
BP28
BP30

BL32
BT28

BR27
BT27
BM31
BT30

1

R0690

49.9

1%
1/16W
MF-LF
402

2

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

OUT

IN

IN
IN
IN

IN

OUT

BI
BI
BI
BI

18

18

18

18

1

R0614

100

2

1%
1/16W
MF-LF
402

121 18 13

121 18 13

121 18

121 18

121 18 13

121 18

121 18

1

R0613

121

1%
1/16W
MF-LF
402

2

1

R0612

121

1%
1/16W
MF-LF
402

2

D

C

B

TP0601
TP0602
TP0603
TP0604
TP0605
TP0606
TP0607
TP0608
TP0609
TP0610
TP0611
TP0612
TP0613
TP0614
TP0615
TP0616

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

1

CPU_CFG<0>

1

CPU_CFG<1>

1

CPU_CFG<2>

1

CPU_CFG<3>

1

CPU_CFG<4>

1

CPU_CFG<5>

1

CPU_CFG<6>

1

CPU_CFG<7>

1

CPU_CFG<8>

1

CPU_CFG<9>

1

CPU_CFG<10>

1

CPU_CFG<11>

1

CPU_CFG<12>

1

CPU_CFG<13>

1

CPU_CFG<14>

1

CPU_CFG<15>

NC
NC

BN25
BN27
BN26
BN28
BR20

BM20

BT20
BP20
BR23
BR22

BT23

BT22

BM19

BR19

BP19

BT19

G3

G13

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD
RSVD

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

RSVD
RSVD

RSVD

RSVD

RSVD_TP
RSVD_TP

VSS
VSS

VSS
VSS

RSVD
RSVD
RSVD

BR35
BR31

BN35

C30

BT2
BR1

W3
W2

V6
W1

H24
E30
F30

NC
NC

NC

NC

TP_CPU_RSVD_TP_BT2
CPU_DC_BR1_BR2

NC
NC
NC

TP-P5

TP-P5

B

1

TP

1

TP0620

TP

TP0600

A

8

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM

CPUPEG:X8X8 CPUCFG5_PD

CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD

TABLE_BOMGROUP_ITEM

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

PAGE TITLE

A

CPU Clock/Misc/JTAG/CFG

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

6 OF 200

SHEET

6 OF 131

1

SIZE

D

D

C

B

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

26 23 22

26 23 22

21

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT

IN

OUT

MEM_A_DQ<45>
MEM_A_DQ<41>
MEM_A_DQ<44>
MEM_A_DQ<40>
MEM_A_DQ<47>
MEM_A_DQ<43>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<53>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<48>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<35>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<26>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<0>
MEM_A_DQ<5>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<13>
MEM_A_DQ<8>
MEM_A_DQ<14>
MEM_A_DQ<9>
MEM_A_DQ<15>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<16>
MEM_A_DQ<19>

MEM_A_PAR
MEM_A_ALERT_L
CPU_DIMM_VREFCA
MEM_A_ACT_L

BR6

DDR0_DQ0

BT6

DDR0_DQ1

BP3

DDR0_DQ2

BR3

DDR0_DQ3

BN5

DDR0_DQ4

BP6

DDR0_DQ5

BP2

DDR0_DQ6

BN3

DDR0_DQ7

BL4

DDR0_DQ8

BL5

DDR0_DQ9

BL2

DDR0_DQ10

BM1

DDR0_DQ11

BK4

DDR0_DQ12

BK5

DDR0_DQ13

BK1

DDR0_DQ14

BK2

DDR0_DQ15

BG4

DDR0_DQ16

BG5

DDR0_DQ17

BF4

DDR0_DQ18

BF5

DDR0_DQ19

BG2

DDR0_DQ20

BG1

DDR0_DQ21

BF1

DDR0_DQ22

BF2

DDR0_DQ23

BD2

DDR0_DQ24

BD1

DDR0_DQ25

BC4

DDR0_DQ26

BC5

DDR0_DQ27

BD5

DDR0_DQ28

BD4

DDR0_DQ29

BC1

DDR0_DQ30

BC2

DDR0_DQ31

AB1

DDR0_DQ32

AB2

DDR0_DQ33

AA4

DDR0_DQ34

AA5

DDR0_DQ35

AB5

DDR0_DQ36

AB4

DDR0_DQ37

AA2

DDR0_DQ38

AA1

DDR0_DQ39

V5

DDR0_DQ40

V2

DDR0_DQ41

U1

DDR0_DQ42

U2

DDR0_DQ43

V1

DDR0_DQ44

V4

DDR0_DQ45

U5

DDR0_DQ46

U4

DDR0_DQ47

R2

DDR0_DQ48

P5

DDR0_DQ49

R4

DDR0_DQ50

P4

DDR0_DQ51

R5

DDR0_DQ52

P2

DDR0_DQ53

R1

DDR0_DQ54

P1

DDR0_DQ55

M4

DDR0_DQ56

M1

DDR0_DQ57

L4

DDR0_DQ58

L2

DDR0_DQ59

M5

DDR0_DQ60

M2

DDR0_DQ61

L5

DDR0_DQ62

L1

DDR0_DQ63

DDR0_PAR

AG3
AU5

DDR0_ALERT*
DDR_VREF_CA

BN13

AU3

DDR0_ACT*

U0500

BGA

SYM 3 OF 13

45W

CFL-H-DDR4-IL

CRITICAL
OMIT_TABLE

DDR0_CKN0
DDR0_CKP0
DDR0_CKE0

DDR0_CKN1
DDR0_CKP1
DDR0_CKE1

DDR0_CKN2
DDR0_CKP2
DDR0_CKE2

DDR0_CKN3
DDR0_CKP3
DDR0_CKE3

DDR0_CS0*
DDR0_CS1*
DDR0_CS2*
DDR0_CS3*

DDR0_ODT0
DDR0_ODT1
DDR0_ODT2
DDR0_ODT3

MEMORY CHANNEL DDR0

DDR0_ECC0
DDR0_ECC1
DDR0_ECC2
DDR0_ECC3
DDR0_ECC4
DDR0_ECC5
DDR0_ECC6
DDR0_ECC7

DDR0_DQSN0
DDR0_DQSN1
DDR0_DQSN2
DDR0_DQSN3
DDR0_DQSN4
DDR0_DQSN5
DDR0_DQSN6
DDR0_DQSN7
DDR0_DQSN8

DDR0_DQSP0
DDR0_DQSP1
DDR0_DQSP2
DDR0_DQSP3
DDR0_DQSP4
DDR0_DQSP5
DDR0_DQSP6
DDR0_DQSP7
DDR0_DQSP8

VSS

AG2
AG1
AT1

AK1
AK2
AT2

AK3
AL3
AT3

AL1
AL2
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

U38

BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2

BR5
BL3
BG3
BD3
AA3
U3
P3
L3
BA3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3
AY3

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC

NC

678

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
MEM_A_CKE<1>

NC_MEM_A_CKE<2>

NC_MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>

MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_P<4>
MEM_A_DQS_P<3>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

26

26

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

3 245

BT11

125

118 26 23 22

118 26 23 22

26 23 22

118 26

118 26

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 25 24

26 25 24 26 23 22

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT

INOUT

MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<23>
MEM_B_DQ<19>
MEM_B_DQ<21>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<12>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<8>
MEM_B_DQ<10>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<7>
MEM_B_DQ<1>
MEM_B_DQ<4>
MEM_B_DQ<0>
MEM_B_DQ<25>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<26>
MEM_B_DQ<31>
MEM_B_DQ<24>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<35>
MEM_B_DQ<32>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<60>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<53>
MEM_B_DQ<41>
MEM_B_DQ<46>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<42>
MEM_B_DQ<47>
MEM_B_DQ<40>
MEM_B_DQ<45>

MEM_B_PAR
MEM_B_ALERT_L

DDR1_DQ0

BR11

DDR1_DQ1

BT9

DDR1_DQ2

BR8

DDR1_DQ3

BP11

DDR1_DQ4

BN11

DDR1_DQ5

BP8

DDR1_DQ6

BN8

DDR1_DQ7

BL12

DDR1_DQ8

BL11

DDR1_DQ9

BL8

DDR1_DQ10

BJ8

DDR1_DQ11

BJ11

DDR1_DQ12

BJ10

DDR1_DQ13

BL7

DDR1_DQ14

BJ7

DDR1_DQ15

BG11

DDR1_DQ16

BG10

DDR1_DQ17

BG8

DDR1_DQ18

BF8

DDR1_DQ19

BF11

DDR1_DQ20

BF10

DDR1_DQ21

BG7

DDR1_DQ22

BF7

DDR1_DQ23

BB11

DDR1_DQ24

BC11

DDR1_DQ25

BB8

DDR1_DQ26

BC8

DDR1_DQ27

BC10

DDR1_DQ28

BB10

DDR1_DQ29

BC7

DDR1_DQ30

BB7

DDR1_DQ31

AA11

DDR1_DQ32

AA10

DDR1_DQ33

AC11

DDR1_DQ34

AC10

DDR1_DQ35

AA7

DDR1_DQ36

AA8

DDR1_DQ37

AC8

DDR1_DQ38

AC7

DDR1_DQ39

W8

DDR1_DQ40

W7

DDR1_DQ41

V10

DDR1_DQ42

V11

DDR1_DQ43

W11

DDR1_DQ44

W10

DDR1_DQ45

V7

DDR1_DQ46

V8

DDR1_DQ47

R11

DDR1_DQ48

P11

DDR1_DQ49

P7

DDR1_DQ50

R8

DDR1_DQ51

R10

DDR1_DQ52

P10

DDR1_DQ53

R7

DDR1_DQ54

P8

DDR1_DQ55

L11

DDR1_DQ56

M11

DDR1_DQ57

L7

DDR1_DQ58

M8

DDR1_DQ59

L10

DDR1_DQ60

M10

DDR1_DQ61

M7

DDR1_DQ62

L8

DDR1_DQ63

AJ7

DDR1_PAR

AR8

DDR1_ALERT*

U0500

BGA

SYM 4 OF 13

45W

CFL-H-DDR4-IL

CRITICAL

OMIT_TABLE

DDR1_CKN0
DDR1_CKP0
DDR1_CKE0

DDR1_CKN1
DDR1_CKP1
DDR1_CKE1

DDR1_CKN2
DDR1_CKP2
DDR1_CKE2

DDR1_CKN3
DDR1_CKP3
DDR1_CKE3

DDR1_CS0*
DDR1_CS1*
DDR1_CS2*
DDR1_CS3*

DDR1_ODT0
DDR1_ODT1
DDR1_ODT2
DDR1_ODT3

MEMORY CHANNEL DDR1

DDR1_ECC0
DDR1_ECC1
DDR1_ECC2
DDR1_ECC3
DDR1_ECC4
DDR1_ECC5
DDR1_ECC6
DDR1_ECC7

DDR1_DQSN0
DDR1_DQSN1
DDR1_DQSN2
DDR1_DQSN3
DDR1_DQSN4
DDR1_DQSN5
DDR1_DQSN6
DDR1_DQSN7
DDR1_DQSN8

DDR1_DQSP0
DDR1_DQSP1
DDR1_DQSP2
DDR1_DQSP3
DDR1_DQSP4
DDR1_DQSP5
DDR1_DQSP6
DDR1_DQSP7
DDR1_DQSP8

VSS

AN9
AM9
AT8

AM8
AM7
AT10

AM10
AM11
AT7

AJ11
AJ10
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

Y38

AW11
AY11
AY8
AW8

AY10
AW10
AY7
AW7

BN9
BL9
BG9
BC9
AC9

W9

R9

M9
AY9

BP9

BJ9
BF9
BB9
AA9
V9

P9

L9
AW9

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC
NC

NC

NC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>

NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
MEM_B_CKE<1>

NC_MEM_B_CKE<2>

NC_MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

NC
NC
NC
NC

MEM_B_DQS_N<2>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>

MEM_B_DQS_P<2>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
MEM_B_DQS_P<5>

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

118 26 25 24

118 26 25 24

26 25 24

118 26

118 26

26 25 24

26

26

26 25 24

26 25 24

26 25 24

26 25 24

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

1

D

C

B

A

21

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CPU_DIMMB_VREFDQ

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

NC

DDR0_VREF_DQ

BP13

DDR1_VREF_DQ

BR13

AH3

DDR0_MA0

AP4

DDR0_MA1
DDR0_MA2

AN4

DDR0_MA3

AP5

DDR0_MA4

AP2

DDR0_MA5

AP1

DDR0_MA6

AP3

DDR0_MA7

AN1

DDR0_MA8

AN3

DDR0_MA9

AT4

DDR0_MA10

AH2

DDR0_MA11

AN2

DDR0_MA12

AU4

DDR0_MA13

AE3

DDR0_MA14

AG4

DDR0_MA15

AD1

DDR0_MA16

AH4

RSVD
RSVD
RSVD

DDR0_BA0

DDR0_BA1
DDR0_BG0
DDR0_BG1

AJ8
B30
BH30

AH5
AH1
AU1
AU2

NC
NC
NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

OUT
OUT
OUT
OUT

26 25 24

26 23 22

26 23 22

26 23 22

26 23 22

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

MEM_B_ACT_L

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

AT9

AJ9
AK6
AK5

AL5
AL6

AM6

AN7

AN10

AN8

AR11

AH7

AN11
AR10

AF9

AH11

AF8

AH10

DDR1_ACT*

DDR1_MA0
DDR1_MA1
DDR1_MA2
DDR1_MA3
DDR1_MA4
DDR1_MA5
DDR1_MA6
DDR1_MA7
DDR1_MA8
DDR1_MA9
DDR1_MA10
DDR1_MA11
DDR1_MA12
DDR1_MA13
DDR1_MA14
DDR1_MA15
DDR1_MA16

RSVD

RSVD

DDR1_BA0

DDR1_BA1
DDR1_BG0
DDR1_BG1

BK28

BJ28

AH8
AH9
AR9
AR7

NC

NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

BOM_COST_GROUP=CPU & CHIPSET

OUT
OUT
OUT
OUT

26 25 24

26 25 24

26 25 24

26 25 24

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

A

CPU DDR4 Interfaces

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

051-02643

REVISION

4.0.0

4.0.0

BRANCH

evt-0

evt-0

PAGE

7 OF 200

7 OF 200

SHEET

7 OF 131

7 OF 131

8

67

35 4

2

1

678

3 245

1

D

C

B

A

6 8 58 115

PP1V05_S3

6 8 11

46 115

8

CPU_VCCST_PWRGD_R

6 11 115

PP1V05_S0SW

PULL-UPS FOR SENSE LINES

1

R0864

100

5%
1/20W
MF
201

2

PPVCC_S0_CPU

1

1

R0865

100

5%
1/20W
MF

2

201

R0866

100

5%
1/20W
MF

2

201

VCC
AP37
AP36
AP35
AP32
AP31
AP30
AP13

AN38
AN37
AN36
AN35
AN34
AN33
AN32
AN31
AN14

AN13
AM36
AM35
AM34
AM33
AM32
AM31
AM30
AM29
AM14
AM13

AL38
AL37
AL36
AL35
AL32
AL31
AL30
AL29

AL13
AK38
AK37
AK36
AK35
AK34
AK33
AK32
AK31

AJ36
AJ35
AJ34
AJ33
AJ32
AJ31
AJ30
AJ29

AJ14
AH32
AH31
AH30
AH29
AH14
AH13

AG36
AG35
AG34
AG33
AG32
AG31
AG14

AF34
AF33
AF32
AF31
AF30
AF29

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

H30

VCCST

H13

VCCST_PWRGD

G30

VCCSTG

H29

VCCSTG

PPVCCGT_S0_CPU
PPVCCSA_S0_CPU

PPVCCIO_S0_CPU

1

R0861

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.H14:50.8mm
PLACE_NEAR=U0500.AG37:50.8mm
PLACE_NEAR=U0500.AH38:50.8mm
PLACE_NEAR=U0500.M38:50.4mm

CPU_VCCIOSENSE_P
CPU_VCCSASENSE_P

CPU_VCCGTSENSE_P

CPU_VCCSENSE_P

U0500

BGA

SYM 6 OF 13

POWER

45W

CFL-H-DDR4-IL

CRITICAL

OMIT_TABLE

VCCSA_SENSE
VSSSA_SENSE

PPVCC_S0_CPU

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCIO_SENSE

VSSIO_SENSE

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCPLL
VCCPLL

VCCPLL_OC
VCCPLL_OC
VCCPLL_OC

6 8 58 115

8 58 115

8 58 115

5 8 10 115

78 8

69 8

69 8

69 8

PPVCCIO_S0_CPU

AG12AP38
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27

H14
J14

J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36

M38
M37

H28
J28

BH13
G11
BJ13

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

PPVCCSA_S0_CPU

CPU_VCCSASENSE_P

CPU_VCCSASENSE_N

PP1V05_S3

Place C0802 on bottom side of U0500
Place C0803 on bottom side of U0500
PP1V2_S0SW

80 46

IN

6 8 11 46 115

PP1V05_S3

69

BI

6 8 11 46 115

5 8 10 115

OUT
OUT

8 58 115

OUT
OUT

69 8

69 9

11 115

CPU_VIDSOUT

1

C0802

1UF

20%

2

6.3V
X6S-CERM
0201

PP1V05_S3

78 8

78 9

1

C0803

1UF

20%

2

6.3V
X6S-CERM
0201

NOSTUFF

NOSTUFF

1

R0802

100

5%
1/20W
MF
201

2

69

69

CPU_VIDALERT_L

IN

CPU_VIDSCLK

OUT

R0812

0

5%
1/16W
MF-LF

402

115

PLACE_NEAR=U0500.H13:1MM

1

R0840

1K

1%
1/16W
MF-LF
402

2

1

R0842

100

5%
1/20W
MF
201

2

PP1V2_S3_CPUDDR

115

6 8 58 115

PPVCC_S0_CPU

69 8

OUT

69 9

OUT

1

R0800

56.2

1%
1/20W
MF
201

2

R0810

220

1/20W

R0811

0

5%
1/16W
MF-LF

402

21

PLACE_NEAR=U0500.H13:1MM

R0841

60.4

1/20W

5%
MF

201

21

1%
MF

201

21

TP0800
TP0801

6 8 58 115

21

PPVCC_S0_CPU

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

1

TP
TP

TP_CPU_RSVD_TP75

TP-P5

1

TP_CPU_RSVD_TP76

TP-P5

CPU_VCCST_PWRGD_RCPU_VCCST_PWRGD

NC
NC
NC
NC

BL31
BL34
AP14
AP29

AA6

AE12

AF5

AF6
AG5
AG9

AJ12

AL11

AP6

AP7

AR12

AR6

AT12

AW6

AY6

J5
J6

K12

K6

L12

L6
R6
T6

W6

Y12

U36

V13

AG37
AG38

BH31
BH32
BH29

Y7

Y8
E2
E1

Y9

Y13

W4

W34

Y10

W5

Y14

W12

Y37

W33

Y11

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AB30
AB31
AA38
AB29

V14
V31
V32
V33
V34
V35
V36
V37

V38
W13
W14

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
VCC

VCC_SENSE
VSS_SENSE

VIDALERT*
VIDSCK
VIDSOUT

VSS

VSS
RSVD_TP
RSVD_TP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 5 OF 13

CRITICAL

OMIT_TABLE

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PPVCC_S0_CPU

AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y36

6 8 58 115

BOM_COST_GROUP=CPU & CHIPSET

PPVCCGT_S0_CPU

8
58 115

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36

AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE33

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

PAGE TITLE

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 7 OF 13

POWER

CRITICAL

OMIT_TABLE

VCCGT_SENSE

VSSGT_SENSE

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

CPU Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BP37
BP38
BR15
BR16
BR17
BR37
BT15
BT16
BT17
BT37

AH38

CPU_VCCGTSENSE_P

AH37

CPU_VCCGTSENSE_N

DRAWING NUMBER

051-02643

REVISION

BRANCH

PAGE

8 OF 200

SHEET

8 OF 131

4.0.0
evt-0

D

C

B

OUT
OUT

SYNC_DATE=02/24/2017SYNC_MASTER=ZIFENG_CONSTRAINTS

69 8

69 9

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

A3
A4
A6

A9
A10
A12
A14
A16
A18
A20
A22
A24
A26
A34
A36
A37

AA12
AA29
AA30

AB6
AB33
AB34

AC1
AC2
AC3
AC4
AC5

AC6
AC12
AC37
AC38

AD6

AD7

AD8

AD9
AD10
AD11
AD12
AD29
AD30

AE6
AE33
AE34

AF1
AF2
AF3

AF4
AF12
AF13
AF14

AG6
AG7

AG8
AG10
AG11
AG13
AG29
AG30

AH6
AH12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 8 OF 13

GROUND

CRITICAL
OMIT_TABLE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH33
AH34
AH35
AH36
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ13
AJ37
AJ38
AK4
AK29
AK30
AL4
AL7
AL8
AL9
AL10
AL12
AL14
AL33
AL34
AM1
AM2
AM3
AM4
AM5
AM12
AM37
AM38
AN5
AN6
AN12
AN29
AN30
AP8
AP9
AP10
AP11
AP12
AP33
AP34
AR1
AR2
AR3
AR4
AR5
AR13
AR14
AR29
AR30
AR31
AR32
AR33
AR34
AR35

AR36
AR37
AR38

AT6
AT29
AT30

AU6
AU7
AU8

AU9
AU10
AU11
AU12
AU33
AU34

AV37
AV38

AW1
AW2
AW3
AW4

AW5
AW12
AW29
AW30

AY12
AY14
AY33
AY34

B3

B9
B37
BA6
BA7
BA8
BA9

BA10
BA11
BA12
BA37
BA38

BB1
BB2
BB3
BB4
BB5
BB6

BB12
BB29
BB30

BC6
BC12
BC13
BC14
BC33
BC34

BD6

BD7

BD8

BD9
BD10
BD11
BD12
BD37
BD38

BE1
BE2
BE3
BE4
BE5

BE6
BE29
BE30

BF6
BF12
BF33
BF34

BG6
BG12
BG13
BG14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 9 OF 13

GROUND

CRITICAL

OMIT_TABLE

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BG37
BG38
BH1
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
BH10
BH11
BH12
BH14
BJ12
BJ14
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK6
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BL6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BM2
BM3
BM5
BM6
BM7
BM8
BM9
BM11
BM12
BM13
BM14
BM18
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM33
BM35
BM38
BN2
BN19
C37
D3
D28
D30
D33
L33

A28

A30
BN4
BN7

BN12
BN14
BN18
BN20
BN21
BN24
BN29
BN30
BN31
BN34

BP7

BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BR7
BR9

BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36
BR38

BT3

BT4

BT5

BT8

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32
BT35
BT36

C2
C5
C8

C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31

D6

D9
D10
D12
D14
D16
D18
D20
D22
D24
D26
D38

E4

E9
E34
E35
E38

F2

F3

F4

F5

F8

F9
F11
F13
F15
F17
F19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 10 OF 13

GROUND

CRITICAL
OMIT_TABLE

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F21
F23
F25
F27
F29
F31
F36
G4
G5
G6
G8
G9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
H11
H12
H18
H22
H25
H32
H35
J4
J7
J10
J18
J22
J25
J32
J33
J36
K1
K2
K3
K4
K5
K7
K8
K9
K10
K11
K38
L29
L30
L34
M6
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N33
N34
P6
P12
P37
P38
R12
R29
R30
T1
T2
T3
T4
T5
T7
T8
T9
T10
T11
T12
T13
T14
T33
T34
U6
U37

CPU_VCCGTSENSE_N
CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N
CPU_VCCSENSE_N

1

R0961

5%
1/20W
MF
201

2

8 69

OUT

8 78

OUT

8 69

OUT

8 69

OUT

1

R0963

100100

5%
1/20W
MF
201

2

1

R0965

5%
1/20W
MF
201

2

1

R0966

100100

5%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

CPU Ground

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

9 OF 200

SHEET

9 OF 131

D

C

B

A

8

67

35 4

2

1

678

3 245

1

D

PPVCC_S0_CPU

115

CPU VCORE Decoupling

Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side
Apple Implementation:

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1000

1

1UF

20%
4V

2

CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1023

1UF

20%

2

4V
CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1001

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1024

1UF

20%

2

4V
CERM-X6S
0201

C1002

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1025

1UF

20%

2

4V
CERM-X6S
0201

C1003

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1026

1UF 1UF

20%

2

4V
CERM-X6S
0201

1

2

1

2

C1004

1UF

20%
4V
CERM-X6S
0201

C1027

20%
4V
CERM-X6S
0201

C1005

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1028

1UF

20%

2

4V
CERM-X6S
0201

C1006

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1029

1UF

20%

2

4V
CERM-X6S
0201

C1007

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1030

1UF

20%

2

4V
CERM-X6S
0201

Vcc CPU Core Decoupling from 20140905 BOM

C1008

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1031

1UF

20%

2

4V
CERM-X6S
0201

C1009

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1032

1UF

20%

2

4V
CERM-X6S
0201

C1010

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1033

1UF

20%

2

4V
CERM-X6S
0201

C1011

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1034

1UF

20%

2

4V
CERM-X6S
0201

C1012

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1035

1UF

20%

2

4V
CERM-X6S
0201

C1013

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1036

1UF

20%

2

4V
CERM-X6S
0201

C1014

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1037

1UF

20%

2

4V
CERM-X6S
0201

C1015

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1038

1UF

20%

2

4V
CERM-X6S
0201

C1016

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1039

1UF

20%

2

4V
CERM-X6S
0201

C1017

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1040

1UF

20%

2

4V
CERM-X6S
0201

C1018

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1041

1UF

20%

2

4V
CERM-X6S
0201

C1019

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1042

1UF

20%

2

4V
CERM-X6S
0201

C1020

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1043

1UF

20%

2

4V
CERM-X6S
0201

C1021

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1044

1UF

20%

2

4V
CERM-X6S
0201

C1022

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1045

1UF

20%

2

4V
CERM-X6S
0201

D

C

C1046

1

1UF

20%
4V

2

CERM-X6S
0201

1

C10A0

20%

2

2.5V
X6S-CERM
0402-1

C1047

1

1UF

20%
4V

2

CERM-X6S
0201 0201

1

C10A3

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

1

C10A4

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1048

1UF

20%
4V
CERM-X6S

1

2

1

2

C1049

1

2

C10Z4

20UF

20%

2.5V
X6S-CERM
0402-1

C10D2

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

1

C10A6

2

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C10D3

20UF

20%

2.5V
X6S-CERM
0402-1

C1050

1UF

20%
4V
CERM-X6S
0201

C10A7

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1051

1

1UF

20%
4V

2

CERM-X6S
0201

C1052

1

1UF

20%
4V

2

CERM-X6S
0201

C1053

1

1UF

20%
4V

2

CERM-X6S
0201

Place near inductors on bottom side.

1

C10A8

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D5

1

20%

2

2.5V
X6S-CERM
0402-1

1

C10ZB

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D6

1

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C10B0

20UF

20%

2

2.5V
X6S-CERM

C10E2

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1054

1

1UF

20%
4V

2

CERM-X6S
0201

C10B1

20UF

20%

2.5V
X6S-CERM
0402-10402-1

C10E3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10B4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1055

1

1UF

20%
4V

2

CERM-X6S
0201

C10C0

1

2

C10N1

12PF

5%
25V
NP0-C0G
0201

20UF

20%

2.5V
X6S-CERM
0402-1

C10N2

1

2

C1056

1

1UF

20%
4V

2

CERM-X6S
0201

12PF

5%
25V
NP0-C0G

C10C1

20UF

1

20%

2.5V
X6S-CERM

2

0402-1

1

2

C1057

1

1UF

20%
4V

2

CERM-X6S
0201

1

2

C10N3

12PF

5%
25V
NP0-C0G0201
0201

C10C4

20UF

20%

2.5V
X6S-CERM
0402-1

C10N4

1

12PF

5%

2

25V
NP0-C0G
0201

C1058

1

1UF

20%
4V

2

CERM-X6S
0201

1

C10C5

20%

2

2.5V
X6S-CERM
0402-1

C10N5

1

12PF

5%

2

25V
NP0-C0G
0201

C1059

1

2

1

C10C6

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1060

1

1UF

20%
4V
CERM-X6S
0201

1

2

C10C7

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V

2

CERM-X6S
0201

Noise Floor caps

C10N6

5%
25V
NP0-C0G
0201

C10N7

1

12PF12PF

5%

2

25V
NP0-C0G
0201

C1061

1

1UF

20%
4V

2

CERM-X6S
0201

C1062

1

1UF

20%
4V

2

CERM-X6S
0201

C

B

115 122

PP1V2_S3_CPUDDR

1

3 2

C1068

220UF

20%
2V
ELEC

C10F0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C1069

3 2

Place on bottom side of U0500.

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500

20%
2V
ELEC
SM-COMBOSM-COMBO

C10F1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10F2

1

2

1

C1070

220UF220UF

3 2

20UF

20%

2.5V
X6S-CERM
0402-1

20%
2V
ELEC
SM-COMBO

C10F3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10F4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1 0402-1

C10F5

1

2

1

C1072

3 2

20UF

20%

2.5V
X6S-CERM

20%
2V
ELEC
SM-COMBO

1

C10F6

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

3 2

C1073

220UF220UF

20%
2V
ELEC
SM-COMBO

1

C10F7

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C10F8

20UF

20%

2

2.5V
0402-1

1

C10F9

20UF

20%

2

2.5V
X6S-CERMX6S-CERM

1

C10G0

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

B

C1080

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1090

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1081

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1091

1

20UF

20%

2

2.5V
X6S-CERM

C1082

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1092

1

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

C1083

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1093

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1084

1

20UF 20UF

20%

2.5V

2

X6S-CERM
0402-1

C1094

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1085

1

2

C1095

1

2

20%

2.5V
X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

CPU VDDQ Decoupling

Intel recommendation: 10x 10uF 0402, 4x 22uF 0602
Apple Implementation:

1

C1096

220UF

20%

3 2

2V
ELEC
SM-COMBO

CPU VCCIO Decoupling

Intel recommendation: 3x 10uF 0402 (opposite CPU)
Apple Implementation:

Place near U0500 on bottom side

A

PPVCCIO_S0_CPU

5 8 115

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

8

67

C1086

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1087

1

20UF

20%

2

2.5V
X6S-CERM

C1088

1

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

C1089

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108A

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108B

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108C

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

BOM_COST_GROUP=CPU & CHIPSET

35 4

C108D

20UF

20%

2.5V
X6S-CERM
0402-1

PAGE TITLE

CPU Decoupling 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

10 OF 200

SHEET

10 OF 131

1

SYNC_DATE=03/29/2017SYNC_MASTER=SILU

SIZE

A

D

678

3 245

1

D

PPVCCGT_S0_CPU

115 122

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1100

1UF

20%
4V
CERM-X6S
0201

C1124

1UF

20% 20%
4V
CERM-X6S
0201

C1101

1

2

1

C1125

2

CPU VGTSlice Decoupling

Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201
Apple Implementation:

1UF

20%
4V
CERM-X6S
0201

1UF

4V
CERM-X6S
0201

C1102

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1126

1UF

20%

2

4V
CERM-X6S
0201

C1103

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1127

1UF 1UF

20%

2

4V
CERM-X6S
0201

1

2

1

2

C1104

1UF

20%
4V
CERM-X6S
0201

C1128

20%
4V
CERM-X6S
0201

C1105

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1129

1UF

20%

2

4V
CERM-X6S
0201

C1106

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1130

1UF

20%

2

4V
CERM-X6S
0201

C1107

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1131

1UF

20%

2

4V
CERM-X6S
0201

C1108

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1132

1UF

20%

2

4V
CERM-X6S
0201

Vcc GT Slice Core Decoupling from 20140905 BOM

Board Edge: 4x220uF, 7x 47uF rest on back side

C1109

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1133

1UF

20%

2

4V
CERM-X6S
0201

C1110

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1134

1UF

20%

2

4V
CERM-X6S
0201

C1111

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1135

1UF

20%

2

4V
CERM-X6S
0201

C1112

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1136

1UF

20%

2

4V
CERM-X6S
0201

C1113

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1137

1UF

20%

2

4V
CERM-X6S
0201

C1114

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1138

1UF

20%

2

4V
CERM-X6S
0201

C1115

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1139

1UF

20%

2

4V
CERM-X6S
0201

C1116

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1140

1UF

20%

2

4V
CERM-X6S
0201

C1117

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1141

1UF

20%

2

4V
CERM-X6S
0201

C1118

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1142

1UF

20%

2

4V
CERM-X6S
0201

C1119

1

2

1

C1143

2

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

C1120

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1144

1UF

20%

2

4V
CERM-X6S
0201

C1121

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1145

1UF

20%

2

4V
CERM-X6S
0201

C1122

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1146

1UF

20%

2

4V
CERM-X6S
0201

C1123

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1147

1UF

20%

2

4V
CERM-X6S
0201

D

C

C1148

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11F0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1149

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A1

1

20UF

20%

2.5V

2

X6S-CERM

C11F1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

NOSTUFF

C11A2

1

20UF

20%

2.5V

2

X6S-CERM
0402-10402-1

1

2

C1150

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F2

20UF

20%

2.5V
X6S-CERM
0402-1

C1151

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11F3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1152

1

1UF

20%
4V

2

CERM-X6S
0201

C11A5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

NOSTUFFNOSTUFF

C11A6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F5

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1153

1UF

20%
4V
CERM-X6S
0201

C11A7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C1154

1

2

NOSTUFF

C11F6

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

C11A8

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F7

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C1155

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A9

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11B0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1156

1

1UF

20%
4V

2

CERM-X6S
0201

1

2

C11B1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E1

20UF

20%

2.5V
X6S-CERM
0402-1

C1157

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E2

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1158

1

1UF

20%
4V

2

CERM-X6S
0201

C11B3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11E3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1159

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11E4

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C1160

1

2

NOSTUFF

C11B5

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11E5

1

2

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

C11B6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

C1161

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1162

1

1UF

20%
4V

2

CERM-X6S
0201

C11B8

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C11B9

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1163

1UF

20%
4V
CERM-X6S
0201

C11C0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1164

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11C1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1165

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11C2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1166

1

2

NOSTUFF

C11C3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

1

2

1

2

C11C4

20UF

20%

2.5V
X6S-CERM
0402-1

C1167

1UF

20%
4V
CERM-X6S
0201

C11C5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11C6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11C7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11D4

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11C8

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11D3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C11C9

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C11D0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11D2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11D1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C

B

1

C1168

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

3 2

C1170

220UF

20%
2V
ELEC
SM-COMBO

1

C1171

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

C1172

220UF

3 2

20%
2V
ELEC
SM-COMBO

B

A

PPVCCSA_S0_CPU

115

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

C11H0

1

1UF

20%

2

4V
0201

C11H1

1

1UF

20%

2

4V
CERM-X6S
0201

1

C11K9

220UF

3 2

C11H2

1

1UF

20%

2

4V
CERM-X6S
0201

20%
2V
ELEC
SM-COMBO

NOSTUFF

C11I0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11I1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11I3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1CERM-X6S

NOSTUFF

C11I7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

CPU VCCSA Decoupling

Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_

Apple Implementation:

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

CPU VCCSTG Decoupling

PP1V05_S0SW

6 8 115

Place near U0500 on bottom side

Place near U0500 on bottom side

2x 220uF, 1x 22uF on board edge, everything else on back side

C11L1

1

1UF

20%
4V

2

CERM-X6S
0201

C11L2

1

1UF

20%
4V

2

CERM-X6S
0201

CPU VCCPLL and VCCST Decoupling

8 115

PP1V05_S3

BOM_COST_GROUP=CPU & CHIPSET

6 8 46

PP1V05_S3

115

C11M1

1

1UF

20%
4V

2

CERM-X6S
0201

Place near U0500 on bottom side

Place near U0500 on bottom side

PAGE TITLE

C11M2

1

1UF

20%
4V

2

CERM-X6S
0201

CPU Decoupling 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

11 OF 200

SHEET

11 OF 131

SYNC_DATE=05/24/2017SYNC_MASTER=SILU

SIZE

D

A

8

67

35 4

2

1

D

121 119 46 18 12

119 46

121 119 46 35

119 46 20

119 112 46 34 18 12

80 77 12

IN

IN

IN

OUT

IN

IN

12

PM_SYSRST_L
PM_PCH_SYS_PWROK

PM_PCH_PWROK

PLT_RST_L
PM_RSMRST_L

PM_PWRBTN_L
SPIROM_USE_MLB

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 4 OF 11

SYSTEM POWER MANAGEMENT

AL17

AK16

H23

U25

J24

L22

SYS_RESET*
SYS_PWROK
PCH_PWROK

GPP_B13/PLTRST*
RSMRST*

GPD3/PWRBTN*
GPD1/ACPRESENT

(IPU)

DRAM_RESET*

(OD)

(IPD-DeepSx)

GPP_A14/SUS_STAT*/ESPI_RESET*

(IPU-RSMRST#)

DSW_PWROK

WAKE*

GPD10/SLP_S5*

GPD5/SLP_S4*
GPD4/SLP_S3*

K25
H25
K23

P23

H22
J21
K20K22

PCH_DRAM_RESET_L

PM_RSMRST_L

PCIE_WAKE_L

ESPI_RESET_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

IN

OUT

OUT

OUT

OUT

OUT

26

119 112 46 34 18 12

19 12

119 39 20

PCH_STRP_GPD7

119 12

119 12

131 119 105 27 14 12

12

SPIROM_USE_MLB

12

PCIE_WAKE_L

19 12

PCH_BATLOW_L

12

PP3V3_S5

16 17 80

13 15 16 19 20 52 80

PP1V8_S5
PP1V8_S5

16 80

PP3V3_S5

16 17 80

R1204
R1205

R1206
R1208

100K
100K

100K

10K

21

21

NOSTUFF

21

5%

21

D

201MF5% 1/20W

2011/20W MF5%

1/20W MF 201

MF5% 1/20W 201

C

77

IN

PP3V0_G3H_RTC

PMU_CLK32K_PCH

1

R1201

1M

5%
1/20W
MF
201

2

PCH_INTRUDER_L

16 17 80

12

R1220

100K

21

1/20W

201

MF

5%

131 77 39 12

1

R1221

127K

1%
1/20W
MF
201

2

121 41

121 41

121 36

121 36

121 117

121 117

PCH_BATLOW_L
PM_SLP_S0_L

119

12

OUT

PCH_CLK32K_RTCX1

20

OUT

12

119 77

PCIE_CLK100M_SOC_N

OUT

PCIE_CLK100M_SOC_P

OUT

PCH_PCIE_CLK100M_WLAN_N

OUT

PCH_PCIE_CLK100M_WLAN_P

OUT

EG_PEG_CLK100M_N

OUT

EG_PEG_CLK100M_P

OUT

IN

NC_PCH_CLK32K_RTCX2
PCH_INTRUDER_L

PCH_RTC_RESET_L

L24

U23

G24
G22

H20

F25
F23

AR10
AN10

AP9

AM9

AR8
AN8

GPD0/BATLOW*
GPP_B12/SLP_S0*

RTCX1
RTCX2

INTRUDER*
SRTCRST*
RTCRST*

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

GPP_A0/RCIN*/ESPI_ALERT1*

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1

RTC

ESPI/LPC

GPP_A7/PIRQA*/ESPI_ALERT0*

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME*/ESPI_CS0*

GPP_A6/SERIRQ/ESPI_CS1*

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 2 OF 11

SLP_SUS*

GPD7

XTAL_IN

XTAL_OUT

CLKIN_XTAL

J25

R24
N20
N21
M20
M22
M25
N25
N24

J20

AN3
AN1

AR4

TP_PCH_SLP_SUS_L

PCH_GPP_A0_PU
ESPI_IO_PCH<0>
ESPI_IO_PCH<1>

ESPI_IO_PCH<2>
ESPI_IO_PCH<3>
ESPI_CS_L
PCH_SOC_SYNC
PCH_ESPI_ALERT0_L

PCH_STRP_GPD7

PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT

118

PCH_CLKIN_XTAL

12

12

OUT

PCH_ESPI_ALERT0_L

12

PCH_GPP_A0_PU

12

SOC_CLKREQ_L

41 12

DEBUG_CLKREQ_L

12

12

22

21

1%

22

21

1%

22

21

1% 1/20W MF 201

22

21

BI

39 20

38 12

R1260

201MF1/20W

R1261

201MF1/20W

R1262
R1263

201MF1/20W1%

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>

121 119 46 18 12

PM_SYSRST_L

BI
BI
BI
BI

118 39 20

118 39 20

118 39 20

118 39 20

R1209
R1210

R1211
R1213

R1214

100K
100K

47K

47K

3.0K

NEED TO CHANGE PER INTEL SPEC

21
21

21

201

21

201

21

5% 1/20W 201MF

MF1/20W

2015%

201MF5% 1/20W

C

CRITICAL

C1250

12

1

R1251

200K

1%
1/20W
MF
201

2

R1250

1/20W

0201

0

5%
MF

Y1250

24MHZ-10PPM-8PF-30OHM

2.5X2.0-SM

4 2

3 1

21

CRITICAL

PCH_CLK24M_XTALOUT_R

10PF

21

5%
50V
C0G

0201

CRITICAL

C1251

10PF

21

5%
50V
C0G

0201

Ce1=Ce2=2*(C_L - C_S - C_I) = 2*(8-0.7)=14.6pF
C_L = Load Capacitance = 8pF
C_S = Trace Capacitace + XTAL Pad Capacitance = 0.7pF
C_I= PCH Pin Capacitance = 0

B

121

121

121 27

121 27

121 105

121 105

PCIE_CLK100M_DEBUG_N

OUT

PCIE_CLK100M_DEBUG_P

OUT

PCIE_CLK100M_TBT_X_N

OUT

PCIE_CLK100M_TBT_X_P

OUT

PCIE_CLK100M_TBT_T_N

OUT

PCIE_CLK100M_TBT_T_P

OUT

NC
NC

NC
NC

AM6

CLKOUT_PCIE_N3

AK6

CLKOUT_PCIE_P3

AM8

CLKOUT_PCIE_N4

AK8

CLKOUT_PCIE_P4

AL7

CLKOUT_PCIE_N5

AJ7

CLKOUT_PCIE_P5

AK1

CLKOUT_PCIE_N6

AK3

CLKOUT_PCIE_P6

AJ5

CLKOUT_PCIE_N7

AK4

CLKOUT_PCIE_P7

CLOCK SIGNALS

GPP_A9/CLKOUT_LPC0

CLKOUT_CPUBCLK_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N

CLKOUT_CPUNSSC_P

XCLK_BIASREF

/ESPI_CLK

AP2

M23

AR7
AP7

AR6
AN6

PCH_XCLK_BIASREF

ESPI_CLK60M_PCH_R

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

12

R1237

22

PLACE_NEAR=U1200.M23:4mm

21

OUT
OUT

OUT
OUT

ESPI_CLK60M_PCH

MF 2011/20W1%

118 6

118 6

118 6

118 6

OUT

20

131 119 105 27 14 12

131 119 77 39 12

131 119 77 39 12

119 12

119 12

38 12

12

12

PM_SLP_S0_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
PCH_SOC_SYNC

PCH_CLKIN_XTAL
PCH_XCLK_BIASREF

R1236

R1230
R1231
R1232
R1233
R1215

R1235

R1234

PLACE_NEAR=U1200.AP2:2.54mm

100K

100K
100K
100K
100K

100K

10K

60.4

PP1V8_S5

36 77 80

21

NOSTUFF

1/20W MF 2015%

21
21

5% MF1/20W 201

21
21

21

21
21

1/20W5% MF

5% 201MF1/20W

1%

1/20W MF

MF1/20W5%

MF1/20W5%

B

201

201

201

2015% 1/20W MF

201

A

PP3V3_S5

R1207

10K

80

21

1/20W MF5%

201

PM_PWRBTN_L

12 77 80

PCI EXPRESS

CLOCKS & CONTROL

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

GPP_B5/SRCCLKREQ0*
GPP_B6/SRCCLKREQ1*
GPP_B7/SRCCLKREQ2*
GPP_B8/SRCCLKREQ3*
GPP_B9/SRCCLKREQ4*

GPP_B10/SRCCLKREQ5*

GPP_H0/SRCCLKREQ6*
GPP_H1/SRCCLKREQ7*

AP5
AM5

W22
AB22
U20
V20
W20
V21

D12
A10

NC
NC

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

SOC_CLKREQ_L
PCH_WLAN_CLKREQ_L

PCH_GPU_CLKREQ_L
DEBUG_CLKREQ_L

TBT_X_CLKREQ_L
TBT_T_CLKREQ_L

12

OUT
OUT

BI
BI
BI

IN
IN

19

118 6

118 6

41 12

37 19

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PAGE TITLE

27 19

105 19

PCH RTC/CLK/ESPI/PM

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-0

PAGE

12 OF 200

SHEET

12 OF 131

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

C

Intel Spec: 1k Pull-up for IO2 and IO3

PP1V8_S5

PPVCCSPI_PRIM_PCH

R1330
R1331
R1332

R1318
R1303

R1317

100K
100K
100K

1K

1K

100K

21

VCCSPI:3V3

21

VCCSPI:3V3

21

VCCSPI:3V3

5% MF 201

21

NOSTUFF

21

21

12 15 16 19 20 52 80

16

1/20W5% MF 201

1/20W5%

1/20W

1/20W MF 2015%

201MF

MF 2011/20W5%

MF1/20W 2015%

SPI_MOSI_R

SPI_IO<2>
SPI_IO<3>

PCH_STRP_BSSB_SEL_GPIO

PCH_STRP_NO_REBOOT

18 13

13

13

13

PCH_WLAN_DEV_WAKE

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

18 13

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN
IN

DMI_S2N_N<0>
DMI_S2N_P<0>

DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_S2N_N<2>
DMI_S2N_P<2>

DMI_S2N_N<3>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_P<0>

DMI_N2S_N<1>
DMI_N2S_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>

DMI_N2S_N<3>
DMI_N2S_P<3>

H3
H1

J2
J1

K3
K1

L4
L2

C3

B2

C1

E1
E2

F1
F4

F3

DMI0_TXN
DMI0_TXP

DMI1_TXN
DMI1_TXP

DMI2_TXN
DMI2_TXP

DMI3_TXN
DMI3_TXP

DMI0_RXN
DMI0_RXP

DMI1_RXN
DMI1_RXP

DMI2_RXN
DMI2_RXP

DMI3_RXN
DMI3_RXP

DMI

SYM 5 OF 11

(IPD)

CPU/MISC

GPP_B23/SML1ALERT*/PCHHOT*

OMIT_TABLE

CPUPWRGD

THRMTRIP*

PECI

GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1

CPU_TRST*

PLTRST_CPU*

PRDY*

PREQ*

TRIGGER_IN

TRIGGER_OUT

PM_DOWN

PM_SYNC

AR16
AP12
AR12
V25

V24
B12
C13
U22

AR17
AM14
AJ16
AP14
AR13

AN13
AL12

AJ12

PCH_PROCPWRGD
PCH_PM_THRMTRIP_L_R

PCH_PECI
PCH_WLAN_PERST_L

PCH_WLAN_DEV_WAKE
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_B2
PCH_STRP_BSSB_SEL_GPIO

XDP_CPU_TRST_L
CPU_RESET_L

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_PCH_TRIGGER
PCH_CPU_TRIGGER_R

PLACE_NEAR=U1200.AN13:5mm

CPU_PCH_PM_DOWN
PM_SYNC_R

PLACE_NEAR=U1200.AJ12:10mm

R1319

R1308

R1309
R1315

R1314

PM_SYNC

21

1/20W MF 2015%

33

0

620

13

13

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

21

21
21

37 36 20

18

18

6

5

37 36 13

BSS GPIO 0=BSSB CLK/DI on USB-SS

121 18 6

121 18 6

121 18 6

33

21

5% MF 2011/20W

OUT

IN

1/20W

5%
MF

5% 1/20W
MF 201

1/20W

5%
MF

6

CPU_PWRGD

0201

PCH_PMTHRMTRIP_L
CPU_PECI

201

PCH_CPU_TRIGGER

NOSTUFF

1

R1326

150K

5%
1/20W
MF
201

2

OUT

IN

OUT

IN

BI

121 119 6

46

46 6

D

5

5

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

A24

NC
NC
NC
NC
NC
NC
NC

37 36 13

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

NC
NC
NC
NC
NC
NC
NC
NC

AJ10

AK10

AM10

AR24

AB1

AJ2
AJ4
AJ8

G2
G4
M1
M3

V1
V2

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

SYM 1 OF 11

HDA_BCLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD

(IPD)

RSVD & TP PINS

AUDIO

GPP_D5/I2S2_SFRM/CNV_RF_RESET*

GPP_D6/I2S2_TXD/MODEM_CLKREQ

HDA_SDO/I2S0_TXD

HDA_RST*/I2S1_SCLK

HDACPU_SCLK

HDACPU_SDI

HDACPU_SDO

AC24

NC

AD23

NC

AD25

NC

AD22

TP_HDA_SDI1

AC25

TP_HDA_SDO

AD20

TP_HDA_RST

AJ13

PCH_DISPA_BCLK_R

AK13
AM13

PCH_DISPA_SDO_R

L21
AJ21

NC
NC

TP-P5

TP-P5

TP-P5

1

TP

TP1306

1

TP

TP1307

1

TP

TP1308

R1320

5%

R1321

1/20W

5%

C

33

21

201

MF1/20W

33

21

201MF

PCH_DISPA_BCLK
PCH_DISPA_SDI

PCH_DISPA_SDO

OUT

IN

OUT

20

20

20

B

117S0134 3

R1330,R1331,R1332

VCCSPI:1V8RES,MF,5%,1/20W,201,75K

TP1300

TP1301

121 18

121 18

121 18

121 18

121 18

121 18

TP
TP

IN

IN

IN

OUT

IN

IN

1

TP-P5

1

TP-P5

TP_PCH_TP1_F22
TP_PCH_TP3_B24

PCH_ITP_PMODE
XDP_PCH_TCK

XDP_PCH_TDI
XDP_PCH_TDO

XDP_PCH_TMS
XDP_PCH_JTAGX

(IPD)

(IPU)

(Undriven)

(IPU)

F22
B24

AN16
AP17
AR18

AM16

AL14

AN18

TP1

TP2

ITP_PMODE
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_JTAGX

JTAG

B

OMIT_TABLE

A

18 13

18 13

13

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 3 OF 11

C23
E25
C25

D21
A20
E22
B21

SPI0_CLK
SPI0_CS0*
SPI0_CS1*

SPI0_MOSI
SPI0_MISO
SPI0_IO2
SPI0_IO3

(IPU 20K)

(IPU 20K)
(IPU 20K)

SPI

GSPI

(IPD)

(IPD)

GPP_B18/GSPI0_MOSI

GPP_B22/GSPI1_MOSI

P20

P22

PCH_STRP_NO_REBOOT

TP_PCH_STRP_BOOT_SPI_L

13

No Rebort: 0=Disable; 1=Enable

BootBIOS Strap: 0=SPI; 1=LPC

PAGE TITLE

A

SYNC_DATE=07/27/2017SYNC_MASTER=SILU

NC
NC
NC

BI

BI

BI

SPI_MOSI_R

NC

SPI_IO<2>
SPI_IO<3>

8

PCH DMI/JTAG/SPI/HDA

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

13 OF 200

SHEET

13 OF 131

1

SIZE

D

678

3 245

1

D

29

29

29

29

119

119

119

119

IN
IN

OUT
OUT

IN
IN

OUT
OUT

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_TEST_D2R_N
USB3_TEST_D2R_P

USB3_TEST_R2D_N
USB3_TEST_R2D_P

AA4

USB31_1_RXN

AA2

USB31_1_RXP

AD3

USB31_1_TXN

AD1

USB31_1_TXP

W3

USB31_2_RXN

W1

USB31_2_RXP

AC2

USB31_2_TXN

AC1

USB31_2_TXP

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 7 OF 11

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

AG1
AG2

AF1
AF3

AH1
AH3

AF4
AE5

USB2_UPC_TA_N
USB2_UPC_TA_P

USB2_UPC_TB_N
USB2_UPC_TB_P

USB2_UPC_XA_N
USB2_UPC_XA_P

USB2_UPC_XB_N
USB2_UPC_XB_P

OMIT_TABLE

U1200

961822

BGA

SYM 8 OF 11

PCIE/SATA/USB3

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

PCIE19_RXN/SATA6_RXN

PCIE19_RXP/SATA6_RXP

PCIE19_TXN/SATA6_TXN

PCIE19_TXP/SATA6_TXP

F6
D6

B4
A4

G8
G7

B5
A5

F8
D8

C6
A6

PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>

PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>

PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<1>

PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>

PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>

PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

118 41

118 41

118 47

118 47

118 41

118 41

118 47

118 47

118 41

118 41

118 47

118 47

D

29

29

29

29

119 107

119 107

119 107

119 107

118 36

118 36

118 36

118 36

126

126

126

126

119

119

119

119

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

PCH_PCIE_WLAN_D2R_N
PCH_PCIE_WLAN_D2R_P

PCH_PCIE_WLAN_R2D_C_N
PCH_PCIE_WLAN_R2D_C_P

USB3_TEST2_D2R_N
USB3_TEST2_D2R_P

USB3_TEST2_R2D_N
USB3_TEST2_R2D_P

USB3_SOCDEBUG_D2R_N
USB3_SOCDEBUG_D2R_P

USB3_SOCDEBUG_R2D_C_N

USB3_SOCDEBUG_R2D_C_P

W4

PCIE1_RXN/USB31_7_RXN

W6

PCIE1_RXP/USB31_7_RXP

U1

PCIE1_TXN/USB31_7_TXN

U3

PCIE1_TXP/USB31_7_TXP

U6

PCIE2_RXN/USB31_8_RXN

V5

PCIE2_RXP/USB31_8_RXP

R2

PCIE2_TXN/USB31_8_TXN

R1

PCIE2_TXP/USB31_8_TXP

P4

PCIE3_RXN/USB31_9_RXN

R5

PCIE3_RXP/USB31_9_RXP

P3

PCIE3_TXN/USB31_9_TXN

P1

PCIE3_TXP/USB31_9_TXP

CNL-PCH-H-USFF-QNYP

BI
BI

BI
BI

BI
BI

BI
BI

C

USB3

USB2

GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*

E12
G10
D10
F10

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

P6

NC
NC

NC
NC

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

107 14

107 14

107 14

109 108 107 105 14

29 27 14

105 14

29 14

29 14

107 14

107 14

OUT
OUT
OUT

OUT
OUT
OUT

XDP_PCH_OBSFN_C0
XDP_PCH_OBSDATA_A0

XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_D0

XDP_PCH_OBSDATA_D1
XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TDO

TBT_T_USB_PWR_EN
TBT_X_PLUG_EVENT_L

TBT_T_PLUG_EVENT_L

NC

PCH_PCIE_RCOMPP
PCH_PCIE_RCOMPN

PCIE4_RXN/USB31_10_RXN

N5

PCIE4_RXP/USB31_10_RXP

N2

PCIE4_TXN/USB31_10_TXN

N1

PCIE4_TXP/USB31_10_TXP

D16

GPP_E0/SATAXPCIE0/SATAGP0

F16

GPP_E1/SATAXPCIE1/SATAGP1

G14

GPP_E2/SATAXPCIE2/SATAGP2

C20

GPP_F0/SATAXPCIE3/SATAGP3

A19

GPP_F1/SATAXPCIE4/SATAGP4

B19

GPP_F2/SATAXPCIE5/SATAGP5

A22

GPP_F3/SATAXPCIE6/SATAGP6

G18

GPP_F4/SATAXPCIE7/SATAGP7

D18

GPP_F10/SATA_SCLOCK

C18

GPP_F11/SATA_SLOAD

G16

GPP_F12/SATA_SDATAOUT1

E17

GPP_F13/SATA_SDATAOUT0

L5

PCIE_RCOMPP

K4

PCIE_RCOMPN

PCIE20_RXN/SATA7_RXN

PCIE20_RXP/SATA7_RXP

PCIE20_TXN/SATA7_TXN

PCIE20_TXP/SATA7_TXP

GPP_E4/SATA_DEVSLP0
GPP_E5/SATA_DEVSLP1
GPP_E6/SATA_DEVSLP2

GPP_F5/SATA_DEVSLP3
GPP_F6/SATA_DEVSLP4
GPP_F7/SATA_DEVSLP5
GPP_F8/SATA_DEVSLP6
GPP_F9/SATA_DEVSLP7

GPP_E8/SATALED*

G9
E9

B7
A7

E14
F13
D13

F20
G19
D20
E19
F18

G13

PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>

PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>

XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1

TBT_X_PCI_RESET_L
TBT_T_PCI_RESET_L
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_CIO_PWR_EN

XDP_PCH_OBSDATA_B3

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT

OUT

18

18

18

18

118 41

118 41

118 47

118 47

29 27 20

105 20

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

C

IN
IN

B

PP3V3_S5

PM_SLP_S3_L
PP3V3_S0SW_TBT_T_SNS
PP3V3_S0SW_TBT_X_SNS

PM_SLP_S3_L

16 80

116

116

GPP_F15/USB2_OC4*
GPP_F16/USB2_OC5*

USB2_COMP

USB2_ID

USB2_VBUSSENSE

131 119 105 27 14 12

B17
D17

AB6
AE4
AE2

NC
NC

USB2_COMP
USB2_ID
USB2_VBUSSENSE

PLACE_NEAR=U1200.AB6:10.0mm

1

R1410

1K

5%
1/20W
MF
201

2

1

R1411

1K

5%
1/20W
MF
201

2

1

R1470

113

1%
1/20W
MF
201

2

1

R1400

100

1%
1/20W
MF
201

2

B

131 119 105 27 14 12

A

R1441
R1442

R1443
R1444

R1446

R1445
R1447

R1460
R1461
R1420
R1421

R1448

R1491
R1492
R1493
R1494

100K
100K

100K
100K

100K

100K

10K
10K

10K
10K
10K

100K

100K
100K
100K
100K

21

21

21

5% MF1/20W

21

5% 1/20W MF

21
21

21
21

5% 1/20W MF 201

21
21

21

21
21
21
21

21

1/20W MF5%
1/20W5% MF

5% MF 2011/20W

1/20W MF5% 201

5%

1/20W5%

5%

MF

MF

MF 201

MF5% 1/20W

MF1/20W

MF5% 1/20W 201

201
201

2011/20W MF5%

2011/20W

2011/20W5%

2011/20W5% MF

201

201

2011/20W MF5%

201

201

NOSTUFF
NOSTUFF

NOSTUFF
NOSTUFF

107 14

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_CIO_PWR_EN
TBT_T_USB_PWR_EN

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

TBT_T_CIO_PWR_EN
TBT_T_USB_PWR_EN

TBT_T_PLUG_EVENT_L
TBT_X_PLUG_EVENT_L

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDO

107 14

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

29 14

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

29 14

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

107 14

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

107 14

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

109 108 107 105 14

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

109 108 107 105 14

105 14

29 27 14

XDP_JTAG_ISP_TDO
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

18

18

18

18

18

SYNC_MASTER=ZIFENG SYNC_DATE=05/18/2017

PAGE TITLE

A

PCH PCI-E/USB

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

18

18

BOM_COST_GROUP=CPU & CHIPSET

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

14 OF 200

SHEET

14 OF 131

SIZE

D

8

67

35 4

2

1

D

C

RAMCFG0:L

1K

5%

1/20W

MF

201

1

2

R1530

RAMCFG1:L

1

R1531

1K

5%
1/20W
MF
201

2

RAMCFG2:L

R1532

1K

5%

1/20W

MF

201

SPEED

2400MHZ
2133MHZ

1

2

CONGIF3

0

1

RAMCFG3:L

1

R1533

1K

5%
1/20W
MF
201

2

STORAGE

16GB
32GB

1

R1534

1K

5%
1/20W
MF
201

2

RAMCFG4:L

CONGIF2

1
0

VENDOR

SAMSUNG

MICRON
HYNIX

CONGIF1

1
0

MLB_RAMCFG0
MLB_RAMCFG1

MLB_RAMCFG2
MLB_RAMCFG3

MLB_RAMCFG4

CONGIF0

0
1
00

15

15

15

15

15

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

93 15

93 15

J680 Display Port DDPF Disabled

PDG recommends to NC the HPD
lines not being used

93 15

J680 Display Port DDPB/C/D Disabled

107 29 15

eSPI Flash Mode: 0=MAF; 1=SAF

OUT
OUT

NC
NC
NC
NC

IN

OUT

EDP_IG_PANEL_PWR
EDP_IG_BKLT_EN

DP_INT_IG_HPD

TBT_POC_RESET

PCH_STRP_SPIROM_SAF

15

PCH_STRP_GPP_H15

15

NC

NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

A18
A16
C16
A14
B14
A13

AN23
AN25

AP24
AP22

AR22

AP19
AM19
AR20
AN20

AP21
AR21

AL24
AL25

AK25

A9

B9

GPP_F14/PS_ON*
GPP_F19/EDP_VDDEN
GPP_F20/EDP_BKLTEN
GPP_F21/EDP_BKLTCTL
GPP_F22/DDPF_CTRLCLK
GPP_F23/DDPF_CTRLDATA

GPP_I0/DDPB_HPD0/DISP_MISC0
GPP_I1/DDPC_HPD1/DISP_MISC1
GPP_I2/DDPD_HPD2_DISP_MISC2
GPP_I3/DDPF_HPD3_DISP_MISC3
GPP_I4/EDP_HPD/DISP_MISC4
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2

GPP_H12/SML2ALERT*

GPP_H15/SML3ALERT*

(IPD)

GPPF/

BACKLIGHT

GPPG

GPPI/DISPLAY

/SMLINK

BGA

SYM 9 OF 11

(IPD)

(IPD)

GPP_J0/CNV_PA_BLANKING

GPP_J1/CPU_C10_GATE*

GPP_J2
GPP_J3

GPP_J4/CNV_BRI_DT/UART0B_RTS*

GPP_J5/CNV_BRI_RSP/UART0B_RXD

GPP_J6/CNV_RGI_DT/UART0B_TXD

GPP_J7/CNV_RGI_RSP/UART0B_CTS*

GPP_J8/CNV_MFUART2_RXD

GPP_J9/CNV_MFUART2_TXD

GPP_J10

GPP_J11/A4WP_PRESENT

GPP_K20
GPP_K21

GPPJ_RCOMP_1P8

CNV_WR_CLKP

CNV_WR_CLKN

CNV_WR_D0P

CNV_WR_D0N

CNV_WR_D1P

CNV_WR_D1N

CNV_WT_CLKP
CNV_WT_CLKN

CNV_WT_D0P
CNV_WT_D0N

CNV_WT_D1P
CNV_WT_D1N

CNV_WT_RCOMP

AM18
AK18
AL19
AJ18
AJ22
AH23
AJ25
AH25
AK22
AK23
AM20
AK20

A8
C8

AJ17

AG24
AG25

AF23
AF25

AE22
AE24

AH22
AH20

AG21
AG20

AF22
AF20

AE21

SOC_SWD_MUX_SEL_PCH
CPU_C10_GATE_L
PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO
PCH_STRP_XTAL_24MHZ
MLB_RAMCFG2
PCH_STRP_CNV_L
MLB_RAMCFG3
MLB_RAMCFG4
PCH_STRP_VCCPSPI_1V8
PCH_BT_ROM_BOOT_L
PCH_BT_DEV_WAKE

MLB_RAMCFG0
MLB_RAMCFG1

PCH_GPPJ_RCOMP_1P8

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

15

OUT

GPP_J2:Unused

15

GPP_J3:Unused

15

GPP_J4: 0=38.4MHz 1=24MHz XTAL

15

15

15

GPP_J6: 0=ENABLE 1=DISABLE

15

15

15

GPP_J9: 0=3.3V; 1=1.8V

36 15

36 15

15

15

15

131 79 78 76 15

D

C

B

PP1V8_S5

PP3V3_S5
PP1V8_S5
PP3V3_S5

R1501
R1502

R1503
R1505

R1506
R1507
R1508
R1509
R1510

R1511
R1512

R1526
R1543

R1514
R1515
R1516

R1517
R1518

10K
10K

1K

47K

47K
47K
47K
47K
47K

1K

100K

20K

1K
100K
100K
100K

1K

1K

VCCSPI:1V8

VCCSPI:3V3

80

16 19 80

12 13 16 19 20 52 80

16 80

21

21

21

21

21
21
21
21
21

21
21

21

21

21
21
21

21

21

1/20W5% MF 201

1/20W MF5% 201

1/20W5% MF 201

1/20W MF5%

1/20W5%

1/20W

1/20W 201

1% 2011/20W

1/20W5% 201MF

1/20W 201

5% MF

5% 201MF

1/20W

1/20W5%

MF5% 2011/20W

MF5% 1/20W

201

201

201MF

MF5% 201

MF5%

MF5% 1/20W 201

MF 2015% 1/20W

MF

201MF1/20W5%

MF5% 1/20W

201MF

201

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

PCH_STRP_ESPI

PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

PCH_STRP_SPIROM_SAF
PCH_STRP_GPP_H15

PCH_STRP_CNV_L
PCH_STRP_XTAL_24MHZ

PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO
CPU_C10_GATE_L

PCH_STRP_VCCPSPI_1V8

15

15

15

15

15

15

15

15

GPPH/I2C/INTEGRATED SENSOR

19 15

IN

WLAN_AUDIO_SYNC_LS3V3

C10

GPP_H23/TIME_SYNC0

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

121 27 15

121 105 15

35 15

39 20

35 15

35 15

35 15

126 119 29 15

126 119 29 15

TP1501

121 27 15

121 105 15

131 79 78 76 15

39

TP-P5

TP

OUT
IN

1

OUT
OUT

SOC_PERST_L
PCH_GCON_INT_L

TP_PCH_STRP_TOPBLK_SWP_L

PLACE_SIDE=BOTTOM

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

NC

R22

P25

R21

AC20
AC21

AB20

GPP_A20/ISH_GP2
GPP_A21/ISH_GP3

GPP_B14/SPKR

GPP_D0/SPI1_CS*/SBK0/BK0
GPP_D1/SPI1_CLK/SBK1/BK1

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

(IPD)

961822

BGA

SYM 6 OF 11

GPPA/

INTEGRATED SENSOR

GPPC/SMLINK/I2C/UART

(IPD)

(IPD)

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_C5/SML0ALERT*

GPP_C8/UART0A_RXD

GPP_C9/UART0A_TXD

GPP_C10/UART0A_RTS*

GPP_C11/UART0A_CTS*

GPP_C20/UART2_RXD

GPP_C21/UART2_TXD

W23
W25
AA22

AB19

AA24
AA21
AA18
Y19

AB25
AB23

SMBUS_PCH_CLK
SMBUS_PCH_DATA
TP_PCH_STRP_TLSCONF

PCH_STRP_ESPI

PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

15

OUT

BI

OUT
OUT

OUT

52

52

IN

IN

IN

PROJ-SPECIFIC PULLUP

TLS: 0=Disbale; 1=Enable

GPP_C5: 0=LPC; 1=eSPI

35 15

35 15

35 15

35 15

126 119 29 15

126 119 29 15

B

A

R1522
R1523

R1524
R1525

R1527
R1528

R1529
R1540
R1542

100K

100K
100K
100K

100K
100K

100K
100K

200

21

21

5% MF1/20W 201

21
21

NOSTUFF

21
21
21

21
21

1/20W MF 201

5%

1/20W

NOSTUFF

5% 1/20W 201MF

201MF1/20W5%

201MF1/20W5%

2015% 1/20W MF

201MF1/20W5%

MF5% 201

MF

GPPD/INTEGRATED SENSOR/UART/I2C GPPB

DP_INT_IG_HPD
TBT_POC_RESET

WLAN_AUDIO_SYNC_LS3V3
PCH_BT_DEV_WAKE

EDP_IG_PANEL_PWR
EDP_IG_BKLT_EN

SOC_SWD_MUX_SEL_PCH
PCH_BT_ROM_BOOT_L
PCH_GPPJ_RCOMP_1P8

2011/20W1%

15

15

93 15

107 29 15

19 15

36 15

93 15

93 15

PAGE TITLE

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PCH GPIO/MISC/NCTF

36 15

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-0

PAGE

15 OF 200

SHEET

15 OF 131

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

C

B

115 80 17

80 17 12

17

115

115

115

17

PP1V05_PRIM

PP3V3_S5

PP1V05_PRIM_PCH_VCCAPLL_F

PP1V05_PRIM

PP1V05_PRIM

PP1V05_PRIM

PP1V05_PRIM_PCH_VCCAXTAL_F

AB12
AB14
AB17

AB7

AB9
AD12
AD14

AD9
AE11

AF7

H7
H9

J15
K14
K17

K7

K9
M7
M9

P12
P14
P17

P7

P9

T12
T14
T17

T7

T9
V12
V14
V17

V9
Y12
Y14
Y17

Y7

Y9

AD17

AE15
AE18

M17

V7

AF6

AG8

AC5

AJ6

AG5

AD7

PRIMARY WELL

VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05

PRIMARY WELL HVCMOS

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

VCCAPLL_1P05
VCCAPLL_1P05

VCCDUSB_1P05

VCCA_BCLK_1P05

VCCA_SRC_1P05

VCCA_XTAL_1P05

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 10 OF 11

POWER

AUDIO PLL

MOD PHY PRIMARY

DEEP SX WELL

VCCAMPHYPLL_1P05

LDO

GPPA PRIMARY WELL

GPPB/GPPC
PRIMARY WELL

GPPD PRIMARY WELL

GPPE/GPPEF
PRIMARY WELL

GPPH/GPPK PRIMARY WELL

RTC WELL SUPPLY

RTC LOGIC PW/VRM

SPI

VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24

VCCDSW_3P3

VCCDSW_1P05

VCCPHVLDO_1P8
VCCPHVLDO_1P8

VCCPGPPA

VCCPGPPBC

VCCPGPPD

VCCPGPPEF
VCCPGPPEF

VCCPGPPHK

DCPRTC

VCCRTC
VCCRTC

VCCSPI

AF19
AG18
AH17
AH19

M19
N18

M6

AF12
AF14

P19

T19

V19

M12
M14

K12

H17

G20
H19

K19

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 11 OF 11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L8
L11
L13
L15
L18
L25
M4
N4
N6
N8
N11
N13
N22
U4
U8
R11
R13
R15
R18
R20
R25
U15
U11
W13
W18
U18
V4
V6
V22
W8
W11
W15
A25
AA1
AA5
A17
A21
AA25
AB3
AA6
AA8
AA11
AA13
AA15
AC4
AC6
AB4
AC8
AE1
AE6
AE8
AE13
AC11
AC13
AC15
AC18
AD4
AD6
AE20
AE25
AF9
AF17
AG6
AG15
AG22
AH4
AH6
AH7
B22

D

C

B

PP1V24_S5_PCH_VCCDPHY

PP3V3_S5

PP1V05_S5_PCH_VCCDSW

PP1V_PRIM_PCH_VCCAMPHYPLL_F

PP1V8_PCH_VCCPHYLDO

Internal Supply

17

17

17

PP1V8_S5

PP1V8_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PPDCPRTC_PCH

17

PP3V0_G3H_RTC

VOLTAGE=3.3V

0201

R1601

VCCSPI:3V3

R1602

PPVCCSPI_PRIM_PCH

0201

VCCSPI:1V8

17

80 17 12

Internal LDO, leave this pin as NC

80 12

80 52 20 19 15 13 12

80 15

80 14

80 19 15

80 17 12

21

0

0

1/20W 5%MF

21

1/20W 5%MF

PP3V3_S5

PP1V8_S5

80

80

R6
U13
A12

A1

A2

AJ24

AP4

D5
G17

J11

L20

AL1

AA20
AC22

AG4
AH9

AJ1

AJ9
AJ14
AJ19
AJ20

AL2
AR14
AR19

AL4

AL9

AL22

AM7
AM12
AM17
AM21

AP1

AP25

AR1
AR2
AR5
AR9

E24

G1

AR25

B1

B25

D7

D9
D14
D19

E4

E7

J5
J8

G5
G12
G21
G25

H4

H6
H12
H14

J4

J6
J13
J22
J18

N15

R4
R8

L1
L6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A

PP1V8_S5

80 17

Share with GPIO J Group Power

PP1V05_PRIM

115 17

PP1V8_S0_PCH_VCCHDA_F

17

AG11
AG13
AH12
AH14

K6

AD19

VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8

VCCPRIM_MPHY_1P05

HD AUDIO POWER

VCCHDA

ANALOG PLL USB2/VRM

Current data from LPT EDS (doc #486708, Rev 1.0).

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

PCH Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

16 OF 200

SHEET

16 OF 131

SIZE

D

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

8

67

35 4

2

1

678

3 245

1

D

PP1V05_PRIM

16 80 115

C1750

NP0-C0G

PP3V3_S5

12 16 80

PP1V8_S5

16 80

PLACE_NEAR=U1200.K14:1MM

1

12PF

5%

25V

2

0201

PLACE_NEAR=U1200.AB14:5MM

PLACE_NEAR=U1200.K14:1MM

1

C1715

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.AE15:1MM

C1751

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1200.AG13:2MM

1

C1716

0.1UF

10%

16V

2

X5R-CERM
0201

1

2

1

C1752

12PF

5%

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.V9:3MM

C1700

22UF

X5R-CERM-1

PLACE_NEAR=U1200.AE15:1MM

1

2

PLACE_NEAR=U1200.AG13:2MM

1

2

1

20%

6.3V

2

603

C1703

0.1UF

10%

16V

X5R-CERM
0201

C1705

1UF

20%

6.3V

X6S-CERM
0201

PLACE_NEAR=U1200.P9:1MM

1

C1701

1UF

10%

6.3V

2

CERM
402

PLACE_NEAR=U1200.AE15:1MM

1

C1702

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.AH12:2MM

1

C1704

0.1UF

10%

16V

2

X5R-CERM
0201

PP1V05_S5_PCH_VCCDSW

17 16

PP3V0_G3H_RTC

12 16 80

PP1V05_PRIM

16 115

1

C1714

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.N18:1MM
PLACE_NEAR=U1200.N18:1MM

1

C1709

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.G19:1MM
PLACE_NEAR=U1200.H20:1MM

1

C1711

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.K6:1MM
PLACE_NEAR=U1200.K6:5MM
PLACE_NEAR=U1200.K6:1MM

1

C1713

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C1708

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1710

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1712

1UF

20%

6.3V

2

X6S-CERM
0201

VOLTAGE=1.05V

PP1V05_S5_PCH_VCCDSW

17 16

VOLTAGE=3V

PPDCPRTC_PCH

16

PP1V24_S5_PCH_VCCDPHY

16

PLACE_NEAR=U1200.N18:1MM

1

C1742

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.H17:1MM

1

C1743

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.AH19:3MM

NOSTUFF

1

C1740

4.7UF

20%

6.3V

2

X6S
0402

D

C

B

PP1V05_PRIM

115

C1721

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

L1703

220-OHM-0.7A-0.28-OHM

PLACE_NEAR=U1200.AG8:3MM

1

2

PP3V3_S5

12 16 17 80

21

PP1V05_PRIM_PCH_VCCAPLL_F

0402-1

PLACE_NEAR=U1200.AG8:3MM

MAKE_BASE=TRUE

PLACE_NEAR=U1200.AG8:1MM

1

C1722

3.0PF

+/-0.1PF

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.M19:1MM
PLACE_NEAR=U1200.M19:1MM
PLACE_NEAR=U1200.M19:1MM

C1753

12PF

NP0-C0G

PLACE_NEAR=U1200.AG8:1MM

1

2

1

5%

25V

2

0201

C1720

4.7UF

20%

6.3V

X6S
0402

C1707

0.1UF

20%

10V

CERM

402

PP1V05_PRIM_PCH_VCCAPLL_F

C

1

2

1

C1706

0.1UF

20%

10V

2

CERM
402

16

PP1V05_PRIM

115

PP3V3_S5

12 16 17 80

C1755

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1200.AD7:3MM

1

PLACE_NEAR=U1200.AD7:5MM

2

PLACE_NEAR=U1200.M19:2MM

1

C1741

1UF

20%

6.3V

2

X6S-CERM
0201

OMIT_TABLE

L1701

2.2UH-20%-0.19A-0.221OHM

21

0603

1

C1726

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1200.AD7:3MM

PP1V8_PCH_VCCPHYLDO

MAKE_BASE=TRUE

16

VOLTAGE=1.05V

PP1V05_PRIM_PCH_VCCAXTAL_F

1

C1727

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.AD7:3MM
PLACE_NEAR=U1200.AD7:3MM

1

2

C1728

1UF

20%

6.3V

X6S-CERM
0201

NOSTUFF

1

C1744

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V05_PRIM_PCH_VCCAXTAL_F

16

B

PP1V8_S5

80

C1724

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

L1704

75OHM-25%-0.2A-1.3OHM

21

PLACE_NEAR=U1200.AD19:3MM

1

2

0402

PLACE_NEAR=U1200.AD19:3MM

MAKE_BASE=TRUE

PP1V8_S0_PCH_VCCHDA_F

PLACE_NEAR=U1200.AD19:1MM

1

C1725

3.0PF

+/-0.1PF

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.AD19:1MM

1

C1723

4.7UF

20%

6.3V

2

X6S
0402

PP1V8_S0_PCH_VCCHDA_F

16

PP1V05_PRIM

115

C1756

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

PLACE_NEAR=U1200.M6:3MM

OMIT_TABLE

L1702

2.2UH-20%-0.19A-0.221OHM

21

PLACE_NEAR=U1200.M6:3MM

0603

MAKE_BASE=TRUE

1

C1729

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1200.M6.3MM

VOLTAGE=1V

PP1V_PRIM_PCH_VCCAMPHYPLL_F

1

C1730

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M6:3MM

1

C1731

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V_PRIM_PCH_VCCAMPHYPLL_F

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

16

A

Current data from LPT EDS (doc #486708, Rev 1.0).

8

L1701,L1702RES,MF,1A MAX,0OHM,5%,0603113S0022 2

SYNC_MASTER=ZIFENG SYNC_DATE=05/18/2017

PAGE TITLE

A

PCH Decoupling

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

17 OF 200

SHEET

17 OF 131

1

SIZE

D

D

C

6

IN

6

IN

6

IN

6

IN

119 112 46 34 12

119 80

121 18 6

121 13

Extra BPM Testpoints

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

IN

OUT

13

OUT

OUT

PM_RSMRST_L

PM_PWRBTN_L

SPI_MOSI_R

IN

XDP_CPU_TCK

XDP_PCH_JTAGX

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1800
TP1801
TP1802
TP1803

PP3V3_S5

80

PLACE_NEAR=J1800.48:2.54MM

R1800

PLACE_NEAR=U1200.H25:2.54MM

PLACE_NEAR=U1200.K22:5MM

R1802
R1803

PLACE_NEAR=U1200.D21:10MM

R1835

PLACE_NEAR=J1800.58:28MM

1K

10

1.5K

0

XDP:YES

21

XDP:YES

21

XDP:YES

XDP:YES

21

XDP:YES

1K

5%

1/20W

MF

201

1

2

MF 2011/20W5%

R1804

21

5% MF 2011/20W

1/20W

5% MF 0201

678

3 245

1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V05_PRIM

115

NOTE: This is not the standard XDP pinout.

XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49
52 51
54 53
56 55
58 57
60 59

64 63

61

518S0847

1.5K

5%

1/20W

MF

201

1

XDP:YES

NO_XNET_CONNECTION

2

XDP_PIN_1

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

NC
NC

NC

NC
NC

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

HOOK0
HOOK1

VCC_OBS_AB

HOOK2
HOOK3

XDP:YES

C1800

0.1UF

CERM-X5R

PLACE_NEAR=J1800.42:28MM

PLACE_NEAR=J1800.44:28MM

SDA TDO
SCL

TCK1

1

10%

6.3V

2

0201

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

PLACE_NEAR=J1800.2:5MM

XDP_PRESENT_CPU

121 13 6

121 13 6

6

6

6

6

6

6

6

6

XDP_CPU_PREQ_L

BI

XDP_CPU_PRDY_L

IN

CPU_CFG<0>

IN

CPU_CFG<1>

IN

CPU_CFG<2>

IN

CPU_CFG<3>

IN

CPU_CFG<4>

IN

CPU_CFG<5>

IN

CPU_CFG<6>

IN

CPU_CFG<7>

IN

XDP_PM_RSMRST_L
XDP_CPU_PWRBTN_L

2011/20W5% MF

SPI_MOSI_R_CONN

121 18 13

OUT

XDP_PCH_TCK

XDP:YES

10%

6.3V
0201

1

2

C1804

0.1UF

CERM-X5R

Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TRSTn
TDI
TMSTCK0
XDP_PRESENT#

XDP:YES

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.43:28MM

PLACE_NEAR=J1800.47:28MM

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC_ITPXDP_CLK100MP
NC_ITPXDP_CLK100MN

PCH_ITP_PMODE
XDP_DBRESET_L

XDP:YES

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

121 18 13

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

IN
IN

118 20

118 20

1

R1830

1K

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.E8:2.54MM

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

121 18 13

121 18 13

121 18 13

IN

0

0

0

0

121 18 6

121 18 6

121 13

XDP:YES

XDP:YES

XDP:YES

XDP_PCH_TDO

PLACE_NEAR=U1200.AM16:28MM

XDP_PCH_TDI

PLACE_NEAR=U1200.AR18:28MM

XDP_PCH_TMS

PLACE_NEAR=U1200.AL14:28MM

XDP_CPU_TDO

PLACE_NEAR=U0500.BT28:28MM

XDP_CPU_TCK

PLACE_NEAR=U0500.BR28:28MM

XDP_PCH_TCK

PLACE_NEAR=U1200.AP17:28MM

XDP_PCH_TRST_L

18

PROPER WAY TO TERMINATE?

21

5%

1/20W 0201MF

21

21

21

1/20W

5% MF 0201

5% 1/20W MF 0201

5% 1/20W

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

MF

XDP:YES

R1890
R1891
R1892
R1810

R1813
R1897

R1898

R1806

0

21

5%

1/20W

MF

0201

0201

PM_SYSRST_L

XDP:YES

PP1V05_S0SW

115

XDP:YES

100

XDP:YES

51

XDP:YES

51

100

XDP:YES

XDP:YES

51

NOSTUFF

51

NOSTUFF

51

IN

OUT

OUT

OUT

12

5% 201

1/20W MF

12

5%

MF 2011/20W

D

12

12

12

12

12

BI

1/20W MF

5%

1/20W MF

5%

5% 201

1/20W

MF

MF1/20W5%

121 119 46 12

201

201

201

2015% 1/20W MF

C

121 18 6

121 13 6

121 6

121 6

B

14

14

13

14

14

14

13

14

14

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PCH/XDP Signals

XDP_PCH_OBSDATA_A0

BI

XDP_PCH_OBSDATA_A1

BI

XDP_PCH_OBSDATA_A2

BI

XDP_PCH_OBSDATA_A3

BI

XDP_PCH_OBSDATA_B0

BI

XDP_PCH_OBSDATA_B1

BI

XDP_PCH_OBSDATA_B2

BI

XDP_PCH_OBSDATA_B3

BI

XDP_PCH_OBSFN_C0

BI

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1810
TP1811
TP1812
TP1813
TP1814
TP1815
TP1816
TP1817
TP1818

14

14

14

Non-XDP Signals

XDP_JTAG_ISP_TDO

BI

XDP_JTAG_ISP_TCK

BI

XDP_JTAG_ISP_TDI

BI

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1819
TP1826
TP1827

PP1V8_S5

18 80

XDP:YES

1

R1850

100K

5%
1/20W
MF
201

2

PP1V8_S5

18 80

XDP:YES

2
1

6

VCC

U1830

74AUP1G07GF

SOT891

YA

(OD)

NCNC

GND

3

XDP:YES

1

C1830

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U1830.4:7.54MM

SPI_IO2_STRAP_L

4
5

NCNC

PLACE_NEAR=U1830.4:2.54MM

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

XDP_PCH_TDO
XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

R1831

1.5K

MF

XDP:YES

NO_XNET_CONNECTION

21

R1832

49.9

MF

NO_XNET_CONNECTION

NOSTUFF

XDP_PRESENT_L

21

SPI_IO<2>

5%

1/20W

201

(STRAP TO PCH)

1/20W1%

201

18

IN

OUT
OUT

OUT

OUT

121 18 13

121 18 13

121 18 13

13

B

39

A

14

14

14

14

14

14

XDP_USB_EXTA_OC_L

BI

XDP_USB_EXTB_OC_L

BI

XDP_USB_EXTC_OC_L

BI

XDP_USB_EXTD_OC_L

BI

XDP_PCH_OBSDATA_D0

BI

XDP_PCH_OBSDATA_D1

BI

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1820
TP1821
TP1822
TP1823
TP1824
TP1825

BOM_COST_GROUP=DEBUG

DESIGN: X502/MLB
LAST CHANGE: Mon Jun 15 22:04:28 2015

SYNC_MASTER=ZIFENG SYNC_DATE=05/24/2017

PAGE TITLE

CPU/PCH Merged XDP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

18 OF 200

SHEET

18 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

PP1V8_G3S_WLANBT_VDDIO

35 36 37 116 122

10%
16V

0201

1

2

NC

WLAN_AUDIO_SYNC

100K

5%

1/20W

MF

201

1

2

R1900

C1900

0.1UF

X5R-CERM

1

VCCA VCCB

U1900

SLSV1T34AMU-COMBO

2

CRITICAL

5

NC

UDFN

GND

3

PP3V3_S5

6

4

BA

10%
16V

0201

1

2

C1901

0.1UF

X5R-CERM

WLAN_AUDIO_SYNC_LS3V3

15 16 19 80

OUTIN

D

15 38 36

C

PCIE CLKREQS

PP1V8_S5
PP3V3_S5

R1940
R1941

R1942

R1944

100K

100K

47K

47K

21

5% 1/20W MF 201

21

21

21

PCH_WLAN_CLKREQ_L

5% 1/20W

PCH_GPU_CLKREQ_L

1/20W5%

12

1/20W MF5%

37 12

MF 201

MF 201

12 13 15 16 20 52 80

15 16 19 80

TBT_X_CLKREQ_L

TBT_T_CLKREQ_L

5% MF1/20W 201

1/20W 201MF

5%201

R1943

R1945

1K

1K

27 12

105 12

PCH_WLAN_CLKREQ_R_L

21

21

GPU_CLKREQ_L_R

MAKE_BASE=TRUE

GPU_CLKREQ_L_R

36

19

Will be reomved

NOSTUFF

R1910

MF 5%1/20W

0201

21

PCIE_WAKE_LAP_PCIE_WAKE_L

0

12 37 36

OUTIN

C

B

95 93

PP1V8_G3S

116

PLACE_NEAR=U1950.1:2mm

19

1

C1950

0.1UF

10%

6.3V

2

CERM-X5R
0201

2
3

NLSX4402

UDFN-COMBO

IO/VL1
IO/VL2

1

8

VCCVL

U1950

IO/VCC1
IO/VCC2

PP3V3_S0_GPU

1

C1951

0.1UF

10%

6.3V

2

CERM-X5R
0201

7
6

GPU_CLKREQ_LGPU_CLKREQ_L_R

NCNC

PLACE_NEAR=U1950.8:2mm

1

R1952

47K

5%
1/20W
MF
201

2

115

B

103

BI

R1950

0

IN

GPUFB_PGOOD

MF

21

5%1/20W0201

GPU_CLKREQ_EN

5

EN

GND

4

A

8

SYNC_MASTER=SILU SYNC_DATE=08/09/2017

PAGE TITLE

A

Chipset Support 1

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

19 OF 200

SHEET

19 OF 131

1

SIZE

D

678

3 245

1

NC ALIASES 3

MAKE_BASE=TRUE

NC_PCH_CLK32K_RTCX2

12

SIGNAL ALIASES

NC_PCH_CLK32K_RTCX2

D

12 13 15 16 19 52 80

119 46 12

PP1V8_S5

IN

PLACE_NEAR=U2072.1:5MM

C2072

0.1UF

10%
16V

X5R-CERM

0201

13

PCH_DISPA_BCLK

13

PCH_DISPA_SDI

13

Platform Reset Connections

PP3V3_S5

10%
16V

0201

1

PLACE_NEAR=U2072.6:5MM

2

1

C2073

0.1UF

2

1

VCCA VCCB

6

X5R-CERM

80

Placement study first

PCH_DISPA_SDO

18 118

NC_ITPXDP_CLK100MN

18 118

NC_ITPXDP_CLK100MP

eSPI Analyzer

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCH_DISPA_BCLK
PCH_DISPA_SDI
PCH_DISPA_SDO

TRUE

TRUE

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP

5

5

5

D

U2072

NC

SLSV1T34AMU-COMBO

2

5

NC

UDFN

GND

3

93

4

BA

PLT3V3_RST_LPLT_RST_L

R2061

100K

5%

1/20W

MF

201

ESPI_DBG
ESPI_DBG

1

118 39 12

118 39 12

100K

2

2 1

100K

2 1

R2000

5% 2011/20W MF

R2001

5% 2011/20W MF

TBT_X_PCI_RESET_L

TBT_T_PCI_RESET_L

OUT

OUT

29 27 14

105 14

118 39 12

118 39 12

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3> ESPI_IO_DBG<3>

R2050
R2051
R2052
R2053

0
0

ESPI_DBG
ESPI_DBG

21

5%

21

5%

1/20W MF

21

5%01/20W MF

21

5%01/20W MF

0201
0201
0201
0201

ESPI_IO_DBG<0>

MF1/20W

ESPI_IO_DBG<1>

ESPI_IO_DBG<2>

39 12

ESPI_CS_L

ESPI_DBG

NC

J2001

M-ST-SM

1413

21
43
65
87
109
1211

505070-1222

ESPI_RESET_L

NC

ESPI_CLK60M_DBG

NC
NC
NC

119 39 12

0201 1/20WMF

R2055

ESPI_DBG

0

21

ESPI_CLK60M_PCH

5%

20 12

C

R2060

100K

5%

1/20W

MF

201

15

100K

2 1

1

2

100K

2 1

R2002

5% 2011/20W MF

R2005

5% 2011/20W MF

PCH_WLAN_PERST_L

SOC_PERST_L

OUT

OUT

37 36 13

39 15

ESPI_CLK60M_PCH

20 12

0201 1/20WMF

R2054

16

0

21

ESPI_CLK60M

5%

OUT

39

C

B

B

A

8

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PAGE TITLE

Chipset Support 2

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

20 OF 200

SHEET

20 OF 131

1

SIZE

D

678

3 245

1

D

DDR4 VDDQ = 1.2V

----------------­ MIMINUM Step Size = 0.50% * VDDQ = 6.0mV per step

TYPICAL Step Size = 0.65% * VDDQ = 7.8mV per step
MAXIMUM Step Size = 0.80% * VDDQ = 9.6mV per step

KBL PLATFORM GUIDE Page.102 FOR DDR4 X8 MEMORY DOWN

-------------------------------------------------­ DDR0_VREF_DQ = Not Used
DDR1_VREF_DQ = Reference For Channel B

DDR_VREF_CA = Reference For Channel A

D

CPU-Based Margining

VRef Dividers

C

B

PP1V2_S3

115

C

1

R2241

1.8K

1%
1/20W
MF
201

R2243

7

IN

7

IN

CPU_DIMMB_VREFDQ

1

2

CPU_DIMM_VREFCA

1

2

2.7

1/20W

5%
MF

201

21

PLACE_NEAR=R2241.2:1mm

C2240

0.022UF

10%

6.3V
X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

2.7

1/20W

5%
MF

201

21

PLACE_NEAR=R2261.2:1mm

C2260

0.022UF

10%

6.3V
X5R-CERM
0201

MEM_VREFCA_A_RC

R2242

1.8K

1/20W

R2240

24.9

1%

1/20W

MF

201

R2262

1.8K

1/20W

R2260

24.9

1%

1/20W

MF

201

1%
MF

201

21

1%
MF

201

21

1

2

1

2

2

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

1

R2261

1.8K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

115

115

B

A

8

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

A

DDR4 VREF Margining

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

BOM_COST_GROUP=DRAM

67

35 4

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

22 OF 200

SHEET

21 OF 131

1

SIZE

D

678

RepairLap.com

3 245

1

D

23 22 7

26

C

C2307

0.47UF

CERM-X5R-1

26
23
22
7

MEM_A_A<0>

23
7

MEM_A_A<1>

22
26

MEM_A_A<2>

23
7

MEM_A_A<3>

22
26

7

MEM_A_A<4>

22
23

MEM_A_A<5>

26

23
7

MEM_A_A<6>

22
26

7

MEM_A_A<7>

22
23

MEM_A_A<8>

26

23
7

MEM_A_A<9>

22
26

MEM_A_A<10>

23
7

MEM_A_A<11>

22
26

7

MEM_A_A<12>

22
23

MEM_A_A<13>

26

23
7

MEM_A_A<14>

22
26

MEM_A_A<15>

23
7

MEM_A_A<16>

22
26

23
7

MEM_A_BA<0>

22
26

MEM_A_BA<1>

23
7

MEM_A_BG<0>

22
26

7

MEM_A_BG<1>

22
23
26

23
7

MEM_A_PAR

22
26

MEM_A_ACT_L

26
23
22
7

MEM_A_CKE<0>

23
7

MEM_A_CS_L<0>

22
26

7

MEM_A_ODT<0>

22
23
26

23

MEM_A_CKE<1>

7
22
26

MEM_A_CS_L<1>

23
7

MEM_A_ODT<1>

22
26

26
24
22

MEM_RESET_L

23
25

118
23
7

MEM_A_CLK_P<0>

22
26

7

MEM_A_CLK_N<0>

22
23
26
118

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

H1

F9

F1

C7

VDD

VDD

VDD

VDD

OMIT_TABLE

16GB-64X8X2-2400

VSS

E9

VSS

G1

VSS

C8

VSS

E1

N9

M1

J9

VDD

VDD

VDD

U2300

MT40A2G8-NRE

FBGA

VSS

VSS

VSS

K9

K1

H9

A1

N1

B2

VDD

VSS

22 23 26 115

E8

E2

C9

C1

B8

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

PP1V2_S3

C2317

0.47UF

CERM-X5R-1

C2

MEM_A_DQ<0>

B7

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

D7

MEM_A_DQ<3>

D2

MEM_A_DQ<4>

D8

MEM_A_DQ<5>

E3

MEM_A_DQ<6>

E7

MEM_A_DQ<7>

C3

MEM_A_DQS_P<0>

B3

MEM_A_DQS_N<0>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

MEM_A_TEN MEM_A_TENMEM_A_TENMEM_A_TEN

B9

MEM_A_ZQ<0>

240

1%

1/20W

MF

201

2

1

R2300

C2308

0.047UF

10%

6.3V
X5R
201

1

25 24 23 22

2

22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26

26 23 22

115

26 23 22 7

26 23 22 7

26 23 22

26 23 22 7

22 23 115

26 23 22

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26

26 23 22 7

26 23 22 7

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

7

MEM_A_PAR
MEM_A_ACT_L

7

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

16GB-64X8X2-2400

OMIT_TABLE

VSS

VSS

VSS
E9

E1

C8

U2310

MT40A2G8-NRE

VSS

VSS

VSS

K1

H9

G1

FBGA

VSS
K9

22 23 26 115

C9

C1

B8

B2

A1

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

VSS

A2

N1

VDDQ

VDDQ

VSSQ
A8

VDDQ

NF/TDQS_C

VSSQ

VSSQ
D9

D1

E8

E2

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

ALERT*

VPP0
VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

C2

MEM_A_DQ<8>

B7

MEM_A_DQ<9>

D3

MEM_A_DQ<10>

D7

MEM_A_DQ<11>

D2

MEM_A_DQ<12>

D8
E3

MEM_A_DQ<14>

E7

MEM_A_DQ<15>

C3

MEM_A_DQS_P<1>

B3

MEM_A_DQS_N<1>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

B9

MEM_A_ZQ<1> MEM_A_ZQ<2>

R2310

1/20W

240

1%
MF

201

C2318

0.047UF

2

1

10%

6.3V
X5R
201

125 118

26 23 22 7

125 118

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22 7

26 23 22 7

23 22 7

26

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

26 23 22 7

26 23 22 7

22 23 26 115

26 23 22 7

7

26 23 22 7

26 23 22

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

1

26 23 22 7

2

26 25 24 23 22

118 26 23 22 7

118 26 23 22 7

A1

N1

B2

VDD

VSS

22 23 26 115

E8

E2

C9

C1

B8

VDDQ

VDDQ

VSSQ

A8

VDDQ

VDDQ

NF/TDQS_C

VSSQ

VSSQ

D9

D1

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

A9

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

A2

ZQ

C2
B7

MEM_A_DQ<17>

D3

MEM_A_DQ<18>

D7
D2

MEM_A_DQ<20>

D8

MEM_A_DQ<21>

E3

MEM_A_DQ<22>

E7

MEM_A_DQ<23>

C3

MEM_A_DQS_P<2>

B3

MEM_A_DQS_N<2>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

G9

B9

R2320

240

1%

1/20W

MF

201

PP1V2_S3

C2327

0.47UF

CERM-X5R-1

22 7

MEM_A_A<0> MEM_A_DQ<16>

26 23

MEM_A_A<1>

22 7

MEM_A_A<2>

26 23

MEM_A_A<3> MEM_A_DQ<19>
MEM_A_A<4>
MEM_A_A<5>MEM_A_DQ<13>

22 7 125 118
26 23

MEM_A_A<6>

22 7
26 23

MEM_A_A<7>

22 7
26 23

MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

20%

4V

201

1

2

NC

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

U2320

16GB-64X8X2-2400

MT40A2G8-NRE

OMIT_TABLE

VSS

VSS

VSS

VSS

VSS

K9

G1

H9

K1

E1

E9

VDD

FBGA

VSS

C2328

0.047UF

2

1

10%

6.3V
X5R
201

1

2

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26
115

26 23 22

26 23 22 7

26 23 22 7

26 23 22

26 23 22 7

22 23 115

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

26 23 22 7

25 24 23 22

26 23 22 7

26 23 22 7

26

C2337

0.47UF

20%

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

MEM_A_PAR

7

MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>

26

MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

201

4V

1

2

NC

PP1V2_S3

C7

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2330

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

VSS

VSS

VSS

K1

K9

VSS
N1

VSS
E1

VSS
E9

VSS
G1

H9

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

C2
B7
D3
D7
D2
D8
E3
E7

C3
B3

A7
A3

L9

B1
M9

J1

G9

B9

MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

PP1V2_S3

NC

MEM_A_ALERT_L

PP2V5_S3

C2338

0.047UF

MEM_A_ZQ<3>

240

1%

1/20W

MF

201

2

1

R2330

10%

6.3V
X5R
201

D

118
125

125 118

125 118

125 118

125 118

125 118

125 118

125 118

118
125

118
125

26
22
23
115

23
7
22
26

C

115
22
23

1

2

B

PP2V5_S3

C2350

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2300

2.2UF

20%

6.3V

X5R-CERM

0201

22 23 115

1

2

1

C2351

1.0UF

0201-1

C2301

2.2UF

2

X5R-CERM

20%

6.3V
X5R

20%

6.3V

0201

1

2

C2352

1.0UF

22 23 26 115

1

C2302

2.2UF

2

X5R-CERM

20%

6.3V
X5R

0201-1

20%

6.3V

0201

1

2

1

C2353

1.0UF

0201-1

C2303

2.2UF

2

X5R-CERM

20%

6.3V
X5R

20%

6.3V

0201

1

2

1

C2354

1.0UF

C2310

2.2UF

2

X5R-CERM

20%

6.3V
X5R

0201-1

20%

6.3V

0201

1

2

1

C2355

1.0UF

6.3V

0201-1

C2311

2.2UF

2

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2356

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2357

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2358

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2359

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2360

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2361

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2362

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

20%

1

2

C2312

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2313

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2304

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2305

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2306

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1.0UF

20%

6.3V
X5R

0201-1

C2370

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2363

1.0UF

0201-1

C2309

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2364

1.0UF

0201-1

C2314

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2365

1.0UF

0201-1

C2315

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2316

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2371

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2319

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

PP1V2_S3

C2320

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

PP1V2_S3

C2321

2.2UF

20%

6.3V

X5R-CERM

0201

C2380

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

22 23 26 115

1

2

C2322

22 23 26 115

1

2

1

2.2UF

20%

6.3V

X5R-CERM

2

0201

C2381

0.1UF

10%

6.3V
CERM-X5R
0201

C2323

2.2UF

20%

6.3V

X5R-CERM

0201

C2382

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2330

2.2UF

2

X5R-CERM

C2383

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

6.3V
0201

1

2

C2331

2.2UF

20%

6.3V

X5R-CERM

0201

C2384

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2332

2.2UF

20%

6.3V

X5R-CERM

0201

C2385

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2333

2.2UF

20%

6.3V

X5R-CERM

0201

C2386

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2324

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2325

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

5x 0.1uF per chip

C2387

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2388

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2326

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2389

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2390

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2372

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2391

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2329

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2392

0.1UF

10%

6.3V

2

CERM-X5R
0201 0201

C2334

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2393

0.1UF

10%

6.3V

2

CERM-X5R

C2335

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2394

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

1

C2395

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2336

0.1UF

10%

6.3V
CERM-X5R
0201

1

C2396

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2397

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2373

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2398

0.1UF

10%

6.3V
CERM-X5R
0201

C2339

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2399

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

BOM_COST_GROUP=DRAM

PAGE TITLE

DDR4 SDRAM Channel A 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

23 OF 200

SHEET

22 OF 131

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

C2407

0.47UF

20%

CERM-X5R-1

4V

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7

N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2400

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

C2

MEM_A_DQ<32>

B7

MEM_A_DQ<33>

D3

MEM_A_DQ<34>

D7

MEM_A_DQ<35>

D2

MEM_A_DQ<36>

D8

MEM_A_DQ<37>

E3

MEM_A_DQ<38>

E7

MEM_A_DQ<39>

C3

MEM_A_DQS_P<4>

B3

MEM_A_DQS_N<4>

A7
A3

NC

125 118

22 7
26 23

125 118

22 7
26 23

22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

22 7
26 23

26 23 22 7

22 23 26 115

26 23 22 7

C2417

0.47UF

20%

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

4V

201

1

2

NC

PP1V2_S3

C7

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

H1

F9

F1

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

N9

M1

J9

VDD

VDD

VDD

U2410

MT40A2G8-NRE

FBGA

22 23 26 115

C9

C1

B8

B2

A1

VDD

VDDQ

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

E8

E2

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

NF/TDQS_C

C2

MEM_A_DQ<40>

B7

MEM_A_DQ<41>

D3

MEM_A_DQ<42>

D7

MEM_A_DQ<43>

D2

MEM_A_DQ<44>

D8

MEM_A_DQ<45>

E3

MEM_A_DQ<46>

E7

MEM_A_DQ<47>

C3

MEM_A_DQS_P<5>

B3

MEM_A_DQS_N<5>

A7

PP1V2_S3

A3

NC

125 118

22 7
26 23

125 118

22 7
26 23

22 7

125 118

26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26

26 23 22

115

26 23 22 7

C2427

0.47UF

CERM-X5R-1

MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

H1

F9

F1

C7

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

A1

N9

M1

J9

VDD

VDD

VDD

VDD

U2420

MT40A2G8-NRE

FBGA

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

NF/TDQS_C

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

C2

MEM_A_DQ<48>MEM_A_A<0>

B7

MEM_A_DQ<49>

D3

MEM_A_DQ<50>

D7

MEM_A_DQ<51>

D2

MEM_A_DQ<52>

D8

MEM_A_DQ<53>

E3

MEM_A_DQ<54>

E7

MEM_A_DQ<55>

C3

MEM_A_DQS_P<6>

B3

MEM_A_DQS_N<6>

A7

PP1V2_S3PP1V2_S3

A3

NC

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

23 22 7

26

26 23 22 7

23 22 7

26

26 23 22 7

C2437

0.47UF

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

20%

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3
N2

J7
N8

H2

H7

H8

N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

U2430

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

22 23 26 115

E2

C9

C1

B8

B2

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

VDDQ

NF/TDQS_C

E8

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2

MEM_A_DQ<56>

B7

MEM_A_DQ<57>

D3

MEM_A_DQ<58>

D7

MEM_A_DQ<59>

D2

MEM_A_DQ<60>

D8

MEM_A_DQ<61>

E3

MEM_A_DQ<62>

E7

MEM_A_DQ<63>

C3

MEM_A_DQS_P<7>

B3

MEM_A_DQS_N<7>

A7

PP1V2_S3

A3

NC

D

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

22 23
26 115

22 7
26 23

22 7

C

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26
24
22
23
25

26 23 22 7

22 7

118 26 23

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

MEM_A_TEN

MEM_A_ZQ<4>

B9

R2400

240

1/20W

201

1%
MF

2

1

C2408

0.047UF

10%

6.3V
X5R
201

7

26 23 22 7

26 23 22 7

22 23 115

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

1

25 24 23 22

2

26 23 22 7

26 23 22 7

26 23 22

7

26 23 22

23 22

115

26

118

118

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A2

VSSQ

A8

VSSQ

D1

RFU/TEN

VSSQ

A9

D9

ALERT*

VPP0
VPP1

VREFCA

ZQ

VSSQ

L9

MEM_A_ALERT_L

B1
M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

MEM_A_TEN MEM_A_TEN MEM_A_TEN

B9

MEM_A_ZQ<5>

R2410

240

1/20W

201

2

1%
MF

1

C2418

0.047UF

10%

6.3V
X5R
201

1

2

26 23 22 7

7

26 23 22

26 23 22 7

22 23 115

26 23 22

26 23 22 7

26 23 22 7

115 23 22

26 23 22

26 23 22 7

26 23 22 7

25 24 23 22

26 23 22 7

26 23 22 7

26

MEM_A_PAR
MEM_A_ACT_L

7

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

7

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ
A9

ZQ

L9

MEM_A_ALERT_L

B1

PP2V5_S3PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

B9

MEM_A_ZQ<6>

R2420

240

1/20W

201

2

1%
MF

1

C2428

0.047UF

10%

6.3V
X5R
201

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

1

23 22 7

2

25 24 23 22

26 23 22 7

26 23 22 7

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>

26

MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>

26

MEM_A_CS_L<1>
MEM_A_ODT<1>

26

MEM_RESET_L

26

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

N3

H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A8

A2

VSSQ

VSSQ

D1

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

A9

D9

VPP0

VPP1

ZQ

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

MEM_A_ZQ<7>

B9

R2430

240

1/20W

1%
MF

201

C2438

0.047UF

2

1

10%

6.3V
X5R
201

23
7
22
26

C

22 23
115

1

2

B

PP2V5_S3

C2450

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2400

2.2UF

20%

6.3V

X5R-CERM

0201

22 23 115

1

2

1

2

C2451

1.0UF

0201-1

C2401

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

C2452

1.0UF

22 23 26 115

1

2

C2402

20%

6.3V
X5R

0201-1

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2453

1.0UF

0201-1

C2403

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

1

2

C2454

1.0UF

0201-1

C2410

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

1

2

C2455

1.0UF

6.3V

0201-1

C2411

2.2UF

X5R-CERM

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2456

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2457

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2458

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2459

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2460

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2461

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

C2406

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
0201

1

C2404

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
0201

1

2

C2413

2.2UF

X5R-CERM

1

2

C2412

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2405

0.1UF

10%

6.3V
CERM-X5R

2

0201

1.0UF

20%

6.3V
X5R

0201-1

C2470

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2462

1.0UF

0201-1

1

C2414

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2463

1.0UF

1

C2409

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
X5R

0201-1

1

2

C2464

1.0UF

0201-1

C2416

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

6.3V
X5R

1

2

C2465

1.0UF

1

C2415

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
X5R

0201-1

1

B

2

1

C2419

0.1UF

10%

6.3V
CERM-X5R

2

0201

C2471

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

A

PP1V2_S3

C2420

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

22 23 26 115

1

C2473

1

C2424

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2487

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

22 23 26 115

1

2

C2422

2.2UF

X5R-CERM

C2481

0.1UF

10%

6.3V
CERM-X5R
0201

1

2

C2421

2.2UF

X5R-CERM

1

C2480

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2423

2.2UF

X5R-CERM

1

C2482

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2430

2.2UF

X5R-CERM

1

C2483

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2431

2.2UF

X5R-CERM

1

C2484

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2432

2.2UF

X5R-CERM

1

C2485

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2433

2.2UF

X5R-CERM

1

C2486

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

5x 0.1uF per chip

1

C2425

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2488

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2426

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2489

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2490

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2472

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2491

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2429

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2492

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2493

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2434

0.1UF

10%

6.3V
CERM-X5R
0201

1

2

C2494

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2435

0.1UF

10%

6.3V
CERM-X5R
0201

C2495

1

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2436

0.1UF

10%

6.3V
CERM-X5R
0201

C2496

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2439

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2497

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2498

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2499

0.1UF

10%

6.3V

2

CERM-X5R
0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

DDR4 SDRAM Channel A 2

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

24 OF 200

SHEET

23 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

25 24 7

26

25 24 7

26

25 24 7

26

C

25 24 7

26

25 24 7

26

C2507

0.47UF

CERM-X5R-1

25

MEM_B_A<0>

7
24
26

MEM_B_A<1>

25

MEM_B_A<2>

7
24
26

MEM_B_A<3>

7
24
25

MEM_B_A<4>

26

25

MEM_B_A<5>

7
24
26

MEM_B_A<6>

7
24
25

MEM_B_A<7>

26

25

MEM_B_A<8>

7
24
26

MEM_B_A<9>

25

MEM_B_A<10>

7
24
26

MEM_B_A<11>

7
24
25

MEM_B_A<12>

26

25

MEM_B_A<13>

7
24
26

MEM_B_A<14>

25

MEM_B_A<15>

7
24
26

MEM_B_A<16>

7
24
25
26

25

MEM_B_BA<0>

7
24
26

MEM_B_BA<1>

7
24
25

MEM_B_BG<0>

26

25

MEM_B_BG<1>

7
24
26

MEM_B_PAR

25

MEM_B_ACT_L

7
24
26

25

MEM_B_CKE<0>

7
24
26

MEM_B_CS_L<0>

7
24
25

MEM_B_ODT<0>

26

25

MEM_B_CKE<1>

7
24
26

MEM_B_CS_L<1>

7
24
25

MEM_B_ODT<1>

26

26
24

MEM_RESET_L

22
23
25

118
25

MEM_B_CLK_P<0>

7
24
26

7

MEM_B_CLK_N<0>

24
25
26
118

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

H1

F9

F1

C7

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

VSS

E9

VSS

G1

VSS

C8

VSS

E1

N9

M1

J9

VDD

VDD

VDD

U2500

MT40A2G8-NRE

FBGA

VSS

VSS

VSS

K9

K1

H9

A1

VDD

VSS

N1

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

VDDQ

DQ0
DQ1
DQ2
DQ3

VPP0

VPP1

ZQ

1

2

NC

PP1V2_S3

C7

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2530

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

VSS

VSS

VSS

K1

K9

VSS
N1

VSS
E1

VSS
E9

VSS
G1

H9

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

C2

MEM_B_DQ<24>

B7

MEM_B_DQ<25>

D3

MEM_B_DQ<26>

D7

MEM_B_DQ<27>

D2

MEM_B_DQ<28>

D8

MEM_B_DQ<29>

E3

MEM_B_DQ<30>

E7

MEM_B_DQ<31>

C3

MEM_B_DQS_P<3>

B3

MEM_B_DQS_N<3>

A7
A3

NC

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

MEM_B_TENMEM_B_TENMEM_B_TEN

B9

MEM_B_ZQ<3>

R2530

1/20W

PP1V2_S3

C2517

0.47UF

CERM-X5R-1

C2

MEM_B_DQ<0>

B7

MEM_B_DQ<1>

D3

MEM_B_DQ<2>

D7

MEM_B_DQ<3>

D2

MEM_B_DQ<4>

D8

MEM_B_DQ<5>

E3

MEM_B_DQ<6>

E7

MEM_B_DQ<7>

C3

MEM_B_DQS_P<0>

B3

MEM_B_DQS_N<0>

A7

PP1V2_S3

A3

NC

L9

MEM_B_ALERT_L

B1

PP2V5_S3 PP2V5_S3 PP2V5_S3 PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

MEM_B_TEN

B9

MEM_B_ZQ<0> MEM_B_ZQ<1>

R2500

240

1%

1/20W

MF

201

C2508

0.047UF

2

1

10%

6.3V
X5R
201

24 25 115

1

25 24 23 22

2

24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

125 118

26 25 24

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 7

26 25 24 7

26 25 24 7

26

26 25 24 7

26 25 24 7

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

7

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>

7

MEM_B_BG<1>

7

MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>

26

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

16GB-64X8X2-2400

OMIT_TABLE

VSS

VSS

VSS
E9

E1

C8

U2510

MT40A2G8-NRE

VSS

VSS

VSS

K1

H9

G1

FBGA

VSS
K9

24 25 115

C9

C1

B8

B2

A1

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

VSS

A2

N1

VDDQ

VDDQ

VSSQ
A8

VDDQ

NF/TDQS_C

VSSQ

VSSQ
D9

D1

E8

E2

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

ALERT*

VPP0
VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

C2527

0.47UF

20%

CERM-X5R-1

C2

MEM_B_DQ<8>

B7

MEM_B_DQ<9>

D3

MEM_B_DQ<10>

D7

MEM_B_DQ<11>

D2

MEM_B_DQ<12>

D8

MEM_B_DQ<13>

E3

MEM_B_DQ<14>

E7

MEM_B_DQ<15>

C3

MEM_B_DQS_P<1>

B3

MEM_B_DQS_N<1>

A7

PP1V2_S3 PP1V2_S3

A3

NC

L9

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

B9

R2510

1/20W

240

201

2

1%
MF

1

C2518

0.047UF

10%

6.3V
X5R
201

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7 26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

7 26 25 24 7

MEM_B_PARMEM_B_ALERT_LMEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>

26 25 24 7

1

26 25 24 7

2

26 25 24 23 22

118 26 25 24 7

118 26 25 24 7

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

U2520

16GB-64X8X2-2400

MT40A2G8-NRE

OMIT_TABLE

VSS

VSS

VSS

VSS

VSS

G1

H9

K1

E1

E9

N9

VDD

FBGA

VSS

K9

A1

VDD

VSS

N1

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VSSQ

A8

VDDQ

VDDQ

NF/TDQS_C

VSSQ

VSSQ

D9

D1

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

ALERT*

VREFCA

RFU/TEN

VSSQ

A9

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

A2

VDDQ

DQ0
DQ1
DQ2
DQ3

VPP0

VPP1

ZQ

C2

MEM_B_DQ<16>

B7

MEM_B_DQ<17>

D3

MEM_B_DQ<18>

D7

MEM_B_DQ<19>

D2

MEM_B_DQ<20>

D8

MEM_B_DQ<21>

E3

MEM_B_DQ<22>

E7

MEM_B_DQ<23>

C3

MEM_B_DQS_P<2>

B3

MEM_B_DQS_N<2>

A7

PP1V2_S3

A3

NC

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

B9

MEM_B_ZQ<2>

R2520

240

1/20W

201

2

1%
MF

1

C2528

0.047UF

10%

6.3V
X5R
201

1

2

24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

26 25 24 7

24 25 115

26 25 24

26 25 24 7

26 25 24 7

7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 23 22

26 25 24 7

26 25 24 7

26

C2537

0.47UF

20%

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>

7

MEM_B_BG<0>
MEM_B_BG<1>

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

201

4V

240

1%
MF

201

C2538

0.047UF

2

1

10%

6.3V
X5R
201

D

118
125

125 118

125 118

125 118

125 118

125 118

125 118

125 118

118
125

118
125

115
24
25

25
7
24
26

C

115
24
25

1

2

B

PP2V5_S3

C2550

PP1V2_S3

C2500

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2501

2.2UF

20%

6.3V

X5R-CERM

0201

C2551

1.0UF

20%

6.3V
X5R

0201-1

24 25 115

1

2

C2502

24 25 115

24 25 115

1

2

2.2UF

20%

6.3V

X5R-CERM

0201

C2552

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2503

2.2UF

X5R-CERM

C2553

20%

6.3V
0201

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2510

2.2UF

X5R-CERM

C2554

20%

6.3V
0201

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2511

2.2UF

20%

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

C2555

1.0UF

20%

6.3V
X5R

0201-1

1

C2556

1.0UF

2

0201-1

20%

6.3V
X5R

1

2

C2557

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2558

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2559

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2560

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2561

1.0UF

20%

6.3V
X5R

0201-1

1

2

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

2

C2512

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2513

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2504

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2505

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2506

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2570

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2509

0.1UF

10%

6.3V

2

CERM-X5R
0201

VDD/VDDQ Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

C2562

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

C2514

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2563

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2515

0.1UF

10%

6.3V
CERM-X5R
0201

C2564

1.0UF

20%

6.3V
X5R

0201-1

1

C2516

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2565

1.0UF

20%

6.3V
X5R

0201-1

1

C2571

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

1

C2519

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

C2520

2.2UF

6.3V

X5R-CERM

0201

PP1V2_S3

20%

1

2

1

2

C2521

2.2UF

X5R-CERM

C2580

0.1UF

10%

6.3V
CERM-X5R
0201

1

20%

2

6.3V
0201

24 25 115

1

C2581

2

C2522

0.1UF

10%

6.3V
CERM-X5R
0201

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2582

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2523

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2583

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2530

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2584

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2531

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2585

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2532

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2586

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2533

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2524

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

5x 0.1uF per chip

1

C2587

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2588

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2525

0.1UF

10%

6.3V
CERM-X5R
0201

C2589

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2526

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2590

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2572

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2591

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2529

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2592

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2534

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2593

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2535

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2594

0.1UF

10%

6.3V
CERM-X5R
0201

C2536

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2595

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2573

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2596

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2539

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2597

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2598

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2599

0.1UF

10%

6.3V

2

CERM-X5R
0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

DDR4 SDRAM Channel B 1

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

25 OF 200

SHEET

24 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

C2607

0.47UF

20%

CERM-X5R-1

4V

201

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7

N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2600

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

C2

MEM_B_DQ<32>

B7

MEM_B_DQ<33>

D3

MEM_B_DQ<34>

D7

MEM_B_DQ<35>

D2

MEM_B_DQ<36>

D8

MEM_B_DQ<37>

E3

MEM_B_DQ<38>

E7

MEM_B_DQ<39>

C3

MEM_B_DQS_P<4>

B3

MEM_B_DQS_N<4>

A7

PP1V2_S3

A3

NC

26 25 24 7

26 25 24 7

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25

24 7

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

C2617

0.47UF

20%

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

4V

201

1

2

NC

PP1V2_S3

C7

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

A1

N9

M1

VDD

VDD

VDD

VDD

U2610

MT40A2G8-NRE

FBGA

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

VDDQ

DQ0
DQ1
DQ2
DQ3

PP1V2_S3

C2627

0.47UF 0.47UF

CERM-X5R-1

C2

MEM_B_DQ<40>

B7

MEM_B_DQ<41>

D3

MEM_B_DQ<42>

D7

MEM_B_DQ<43>

D2

MEM_B_DQ<44>

D8

MEM_B_DQ<45>

E3

MEM_B_DQ<46>

E7

MEM_B_DQ<47>

C3

MEM_B_DQS_P<5>

B3

MEM_B_DQS_N<5> MEM_B_DQS_N<6>

A7

PP1V2_S3 PP1V2_S3

A3

NC

26 25 24 7 125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

125 118 125 118

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

MEM_B_A<0> MEM_B_DQ<48>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

7

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

16GB-64X8X2-2400

OMIT_TABLE

U2620

MT40A2G8-NRE

FBGA

24 25 115

C9

C1

B8

B2

A1

VDD

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

NF/TDQS_C

E8

E2

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2
B7

MEM_B_DQ<49>

D3

MEM_B_DQ<50>

D7

MEM_B_DQ<51>

D2

MEM_B_DQ<52>

D8

MEM_B_DQ<53>

E3

MEM_B_DQ<54>

E7

MEM_B_DQ<55>

C3

MEM_B_DQS_P<6>

B3

A7
A3

NC

125 118

125 118

125 118

125 118

125 118

125 118

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

24 25 115

26 25 24

26 25 24 7

MEM_B_A<0>

24 7
26 25

MEM_B_A<1>

24 7
26 25

MEM_B_A<2>

24 7
26 25

MEM_B_A<3>

24 7
26 25

MEM_B_A<4>

24 7
26 25

MEM_B_A<5>

24 7
26 25

MEM_B_A<6>

24 7
26 25

MEM_B_A<7>

24 7
26 25

MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>

24 7
26 25

MEM_B_BA<1>
MEM_B_BG<0>

7

MEM_B_BG<1>

C2637

20%

CERM-X5R-1

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3
N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

U2630

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

24 25 115

E2

C9

C1

B8

B2

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

VDDQ

NF/TDQS_C

E8

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2

MEM_B_DQ<56>

B7

MEM_B_DQ<57>

D3

MEM_B_DQ<58>

D7

MEM_B_DQ<59>

D2

MEM_B_DQ<60>

D8

MEM_B_DQ<61>

E3

MEM_B_DQ<62>

E7

MEM_B_DQ<63>

C3

MEM_B_DQS_P<7>

B3

MEM_B_DQS_N<7>

A7

PP1V2_S3

A3

NC

D

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

24 25 115

24 7
26 25

24 7

C

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26
24
22
23
25

26 25 24 7

24 7

118 26 25

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

L9

MEM_B_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_B

MEM_B_TEN

G9

B9

MEM_B_ZQ<4>

26

25 24

R2600

240

1%

1/20W

MF

201

C2608

0.047UF

2

1

10%

6.3V
X5R
201

7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

1

2

25 24 23 22

26 25 24 7

26 25 24 7

ZQ

L9

MEM_B_ALERT_L

26 25 24 7

B1

PP2V5_S3 PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_B

J1

MEM_B_TEN MEM_B_TEN MEM_B_TEN

G9

B9

24
25
26

MEM_B_ZQ<5> MEM_B_ZQ<6>

R2610

240

1/20W

201

2

1%
MF

1

C2618

0.047UF

10%

6.3V
X5R
201

1

2

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 23 22

26 25 24 7

26 25 24 7

7

26 25 24 7

26 25 24

26

118

118

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ
A9

26 25 24

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

115 25 24

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

26

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A2

VSSQ

A8

VSSQ

D1

RFU/TEN

VSSQ

A9

D9

ALERT*

VPP0
VPP1

VREFCA

VSSQ

ZQ

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_BMEM_B_CKE<1>

G9

B9

R2620

1/20W

24
25
26

240

1%
MF

201

C2628

0.047UF

2

1

10%

6.3V
X5R
201

26 25 24

26 25 24 7

24 25 115

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

1

26 25 24 7

2

26 25 24 23 22

118 26 25 24 7

118 26 25 24 7

1

2

25
7
24
26

C

24 25 115

25 24

115

ZQ

L9

MEM_B_ALERT_L

B1

PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_B

J1

G9

B9

MEM_B_ZQ<7>

R2630

24
25
26

240

1%

1/20W

MF

201

C2638

0.047UF

2

1

10%

6.3V
X5R
201

MEM_B_PAR

7

26 25 24 7

MEM_B_ACT_L

MEM_B_CKE<0>

7

MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>MEM_B_CLK_N<0>

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A8

A2

VSSQ

VSSQ

D1

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

A9

D9

VPP0

VPP1

B

PP2V5_S3

C2650

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2600

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

24 25 115

1

2

1

2

C2651

1.0UF

20%

6.3V
X5R

0201-1

C2601

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

24 25 115

1

2

24 25 115

C2652

1.0UF

20%

6.3V
X5R

0201-1

C2602

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2653

1.0UF

20%

6.3V
X5R

0201-1

C2603

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2654

1.0UF

20%

6.3V
X5R

0201-1

C2610

2.2UF

20%

6.3V

X5R-CERM

0201

1

C2655

1.0UF

2

1

2

C2611

6.3V

0201-1

2.2UF

20%

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2656

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2657

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2658

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2659

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2660

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2661

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2662

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

C2604

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2613

2.2UF

X5R-CERM

1

2

C2612

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2605

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2606

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2670

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2609

0.1UF

10%

6.3V

2

CERM-X5R
0201

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2663

1.0UF

20%

6.3V
X5R

0201-1

1

C2614

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2664

1.0UF

0201-1

1

C2615

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2665

1.0UF

0201-1

1

C2616

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

1

C2671

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2619

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

C2620

PP1V2_S3

2.2UF

20%

6.3V

X5R-CERM

0201

C2680

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2621

2.2UF

6.3V

X5R-CERM

0201

24 25 115

C2681

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

1

2

C2622

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2623

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2630

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2631

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2632

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2633

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2624

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2625

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2626

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2672

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2629

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2634

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2635

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2636

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2673

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2639

0.1UF

10%

6.3V

2

CERM-X5R
0201

5x 0.1uF per chip

A

D

C2682

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2683

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2684

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2685

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2686

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2687

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2688

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2689

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2690

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2691

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2692

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2693

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2694

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2695

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2696

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2697

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2698

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2699

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

BOM_COST_GROUP=DRAM

PAGE TITLE

DDR4 SDRAM Channel B 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

26 OF 200

SHEET

25 OF 131

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

SIZE

8

67

35 4

2

1

678

3 245

1

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

D

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

PP0V6_S0_DDRVTT

26 115

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>

MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

R2700
R2701
R2702
R2703

R2704
R2705
R2706
R2707

R2708
R2709
R2710
R2711

R2712
R2713
R2714
R2715

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

C2701,C2721 FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

1

1

C2700

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2702

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2704

2.2UF

20%

2

4V
X5R-CERM
0201

C2701

12PF

5%
NP0-C0G

2

0201
25V

1

C2703

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2705

0.47UF

20%

2

4V
CERM-X5R-1
201

D

C

MEM_A_TEN

23 22

MEM_B_TEN

25 24

1

R2753

100

5%
1/20W
MF
201

2

1

R2755

100

5%
1/20W
MF
201

2

R2752

0

5%

1/20W

MF

0201

R2754

0

5%

1/20W

MF

0201

23 22 7

23 22 7

21

21

MEM_A_TEN_R

NOSTUFF

1

C2752

0.47UF

20%

2

4V
CERM-X5R-1
201

MEM_B_TEN_R

NOSTUFF

1

C2753

0.47UF

20%

2

4V
CERM-X5R-1
201

TP2700

1

TP

TP2701

1

TP

TP-P5

TP-P5

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN

MEM_A_A<16>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>

MEM_A_BG<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CKE<0>

MEM_A_CKE<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_ACT_L

MEM_A_PAR

R2716
R2717
R2718
R2719

R2720
R2721
R2722
R2723

R2724
R2725
R2726
R2727

R2728

36
36
36
36

36
36
36
36

36
36
36
36

36

21
21
21
21

21
21
21
21

21
21
21
21

21

26 115

PP0V6_S0_DDRVTT

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF

1

C2706

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2708

0.47UF

20%

2

4V
CERM-X5R-1
201

C2710

1

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2707

0.47UF

20%

2

4V
CERM-X5R-1
201

C

B

118 23 22 7

118 23 22 7

118 25 24 7

118 25 24 7

7 118

7 118

7

7

7 118

7 118

7

7

MEM Clock Termination

Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM

IN

IN

IN

IN

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>

MEM_A_CLK_N<0>

C2750

NOSTUFF

MEM_A_CLK_P<0>

NOSTUFF

MEM_B_CLK_P<0>

3300PF

10%
10V
X7R-CERM
0201

C2760

3300PF

10%
10V
X7R-CERM
0201

1

PLACE_NEAR=U2430.F8:10mm

2

PLACE_NEAR=U2630.F8:10mm

1

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3> MEM_B_ACT_L
NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>

PLACE_NEAR=U2430.F8:8mm

PLACE_NEAR=U2430.F7:8mm

PLACE_NEAR=U2630.F8:8mm

PLACE_NEAR=U2630.F7:8mm

R2750

30

5%

1/20W

MF

201

R2751

30

5%

1/20W

MF

201

R2760

30

5%

1/20W

MF

201

R2761

30

5%

1/20W

MF

201

21

MEM_A_CLK0_TERM_R

21

MEM_B_CLK0_TERM_RMEM_B_CLK_N<0>

21

21

C2751

0.01UF

21

10%
25V

X5R-CERM

0201

C2761

0.01UF

21

10%
25V

X5R-CERM

0201

PP0V6_S0_DDRVTT

PP0V6_S0_DDRVTT

26 115

26 115

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>

MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_A<16>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>

MEM_B_BG<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CKE<0>

MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_PAR

R2770
R2771
R2772
R2773

R2774
R2775
R2776
R2777

R2778
R2779
R2780
R2781

R2782
R2783
R2784
R2785

R2786
R2787
R2788
R2789

R2790
R2791
R2792
R2793

R2794
R2795
R2796
R2797

R2798

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF

C2720

1

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2722

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2724

2.2UF

20%

2

4V
X5R-CERM
0201

C2726

1

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2728

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2730

0.47UF

20%

2

4V
CERM-X5R-1
201

C2721

1

12PF

5%
NP0-C0G

2

0201
25V

1

C2723

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2725

0.47UF

20%

2

4V
CERM-X5R-1
201

C2727

1

0.47UF

20%

2

4V
CERM-X5R-1
201

B

A

8

PP1V2_S3

470

1%

1/20W

MF

201

1

2

23 22 7

25 24 7

12

R2730

IN
IN

IN

MEM_A_ALERT_L
MEM_B_ALERT_L

PCH_DRAM_RESET_L

1

51

1%

1/20W

MF

201

2

R2732

0

5%

1/20W

MF

0201

R2731

21

51

1%

1/20W

MF

201

1

2

R2733

BOM_COST_GROUP=DRAM

67

35 4

22 23 115

MEM_RESET_L

NOSTUFF

1

C2732

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_DATE=02/10/2017SYNC_MASTER=j380_mlb

PAGE TITLE

A

DDR4 Termination

DRAWING NUMBER

25 24 23 22

Apple Inc.

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

27 OF 200

SHEET

26 OF 131

1

SIZE

D

678

3 245

1

D

C

B

A

1

R2890

3.3K

5%
1/20W
MF
201

2

TBT_X_SPI_CS_L

29

121 27

TBT_X_ROM_WP_L

TBT_X_ROM_HOLD_L

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

DP_X_SNK0_ML_C_P<0>

DP_X_SNK0_ML_C_N<0>

DP_X_SNK0_ML_C_P<1>

DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<2>

DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<3>

DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

DP_X_SNK1_ML_C_N<0>

DP_X_SNK1_ML_C_P<1>

DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<2>

DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<3>

DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

100K

10K

NOSTUFF

100K

100K

100K

100K

100K

100K

R2891

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

21

21

21

21

21

21

21

21

R2864

MF 2011/20W5%

R2839

PU for NVM

MF1/20W5%

R2863

5% 1/20W MF 201

R2873

5% MF1/20W

R2862

MF1/20W5% 201

R2872

1/20W5% MF

R2860

1/20W5% MF

R2861

1/20W 201

MF5%

1

3.3K

5%

1/20W

MF

201

1

2

R2893

3.3K

5%
1/20W
MF
201

2

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

SNK0 AC Coupling

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

C2828

0.1UF

C2829

0.1UF

SNK1 AC Coupling

C2830

0.22UF

C2831

0.22UF

C2832

0.22UF

C2833

0.22UF

C2834

0.22UF

C2835

0.22UF

C2836

0.22UF

C2837

0.22UF

C2838

0.1UF

C2839

0.1UF

PP3V3_TBT_X_SX

TBT_X_BATLOW_L

201

TBT_X_TMU_CLK_IN

201

201

201

TBT_X_TMU_CLK_OUT

DP_XA_HPD

DP_XB_HPD

TBT_XA_USB2_MXCTL

TBT_XB_USB2_MXCTL

PP3V3_UPC_XB_LDO

8

VCC

U2890

8MBIT-3.0V

W25Q80DVUXIE

USON

OMIT_TABLE

CRITICAL

GND EPAD

9

4

21

20%

6.3V

X5R

21

20%
X5R

21

20% 6.3V 0201
X5R

21

20% 0201

6.3V

X5R

21

6.3V

20%
X5R

21

20% 6.3V 0201
X5R

21

20%
X5R

21

20% 6.3V 0201
X5R

21

6.3V

10%
CERM-X5R

21

10%
CERM-X5R

21

20% 0201

6.3V

X5R

21

20%

6.3V 0201

X5R

21

20%

6.3V 0201

X5R

21

20% 0201

6.3V

X5R

21

20% 0201

6.3V

X5R

21

20%

6.3V 0201

X5R

21

20% 02016.3V
X5R

21

20% 02016.3V
X5R

21

10%

6.3V

CERM-X5R

21

10%
CERM-X5R

28 29

1

2

TBT_X_SPI_MOSITBT_X_SPI_CLK
TBT_X_SPI_MISO

R2892

3.3K

1/20W

DI(IO0)

DO(IO1)

5%
MF

201

5
2

1

2

DP_X_SNK0_ML_P<0>

0201

DP_X_SNK0_ML_N<0>

02016.3V

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>

0201

DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>

02016.3V

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

02016.3V

DP_X_SNK1_ML_P<0>

DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>

DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>

DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>

DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P

0201

DP_X_SNK1_AUXCH_N

02016.3V

27

27

27

30 27

31 27

27

27

29

C2890

1UF

10%

6.3V
CERM
402

118 29

118 29

118 29

118 29

29 29

29

R2828

5%
MF

201

5%

1/20W

MF

201

1K

5%

1/20W

MF

201

1

2

1

2

1

R2829

100

5%
1/20W
MF
201

2

NOSTUFF

1

R2836

2.2K

5%
1/20W
MF
201

2

19 12

118 27

118 27

118 27

118 27

118 27

118 27

118 27

OUT

TBT_X_CLKREQ_L

93

OUT

R2830

93

100K

1/20W

OUT

118 27

118 27

118 27

118 27

118 27

R2831

100K

118 27

118 27

118 27

118 27

1

118 27

118 27

118 27

118 27

79 29 27

PP3V3_TBT_X_SX

R2825

100

5%
1/20W
MF
201

2

29

IN

118 29

118 29

118 29

118 29

121 12

121 12

21

121 107 105

121 15

121 107 105

121 107 105

118 32

32

32

32

32

118 32

118 32

30

30

30 27

PCIE_TBT_X_R2D_P<0>

IN

PCIE_TBT_X_R2D_N<0>

IN

PCIE_TBT_X_R2D_P<1>

IN

PCIE_TBT_X_R2D_N<1>

IN

PCIE_TBT_X_R2D_P<2>

IN

PCIE_TBT_X_R2D_N<2>

IN

PCIE_TBT_X_R2D_P<3>

IN

PCIE_TBT_X_R2D_N<3>

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_R_L

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>
DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P
DP_X_SNK0_AUXCH_N

DP_X_SNK0_HPD

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

DP_X_SNK1_ML_P<0>
DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_N

DP_X_SNK1_HPD

IN
IN
IN

OUT

JTAG_ISP_TDI
JTAG_TBT_X_TMS
JTAG_ISP_TCK
XDP_JTAG_ISP_TDO

TBT_X_TEST_EN

121

TBT_X_TEST_PWR_GOOD

USBC_XA_D2R_P<2>

IN

USBC_XA_D2R_N<2>

IN

USBC_XA_R2D_CR_P<2>

OUT

USBC_XA_R2D_CR_N<2>

OUT

USBC_XA_R2D_CR_P<1>

OUT
OUT

BI
BI

USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>

IN

USBC_XA_D2R_N<1>

IN

USBC_XA_AUXLSX1

USBC_XA_AUXLSX2

IN

DP_XA_HPD

I2C_TBT_XA_INT_L

TBT_XA_USB2_MXCTL

27

NC
NC
NC
NC

NC
NC

TBT_XA_USB2_RBIAS

PLACE_NEAR=U2800.H19:3MM

1

Y23
Y22

T23
T22

M23
M22

H23
H22

V19
T19

AC7

AB7
AB9

AC9

AC11

AB11
AB13

AC13

N1
N2

AA2

A5
B5

B3
A3

C2
C1

E2
E1

P1
P2
Y4

AC5

AB5

AC3

AB3

W20

Y20

W19

Y19

R4

W5

A15
B15

A17
B17

A19
B19

B21
A21

H4

J4

E20

D20

T2

M4

R2

H19

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*

DPSNK1_ML0_P
DPSNK1_ML0_N

DPSNK1_ML1_P
DPSNK1_ML1_N

DPSNK1_ML2_P
DPSNK1_ML2_N

DPSNK1_ML3_P
DPSNK1_ML3_N

DPSNK1_AUX_P
DPSNK1_AUX_N

SNK1_HPD

DPSNK2_ML0_P
DPSNK2_ML0_N

DPSNK2_ML1_P
DPSNK2_ML1_N

DPSNK2_ML2_P
DPSNK2_ML2_N

DPSNK2_ML3_P
DPSNK2_ML3_N

DPSNK2_AUX_P
DPSNK2_AUX_N

SNK2_HPD

U0_SSTXP1
U0_SSTXN1
U0_SSRXP1
U0_SSRXN1

TDI
TMS
TCK
TDO

TEST_EN
TEST_PWR_GOOD

ASSRXP2
ASSRXN2

ASSTXP2
ASSTXN2

ASSTXP1
ASSTXN1

ASSRXP1
ASSRXN1

ASBU1
ASBU2

PA_USB2_D_P
PA_USB2_D_N

PA_HPD

PA_I2C_INT

PA_USB2_MXCTL
PA_USB2_RBIAS

U2800

TITAN-RIDGE-DP

CSP

SYM 1 OF 2

OMIT_TABLE

CRITICAL

PCIE GEN3

SOURCE PORT

SINK PORT 2 SINK PORT 1

JTAG USBSS

TBT PORT A

FLASH POC GPIO LC GPIO

TBT PORT B

PCIE_TX0_P
PCIE_TX0_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_TX3_P
PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P

DPSRC_ML0_N

DPSRC_ML1_P

DPSRC_ML1_N

DPSRC_ML2_P

DPSRC_ML2_N

DPSRC_ML3_P

DPSRC_ML3_N
DPSRC_AUX_P

DPSRC_AUX_N

DPSRC_HPD

GPIO_0
GPIO_1

EE_WP*

TMU_CLKOUT

WAKE*

CIO_PLUG_EVENT*

TMU_CLKIN

I2C_SCL

I2C_SDA

USB_FORCE_PWR

FORCE_PWR

BATLOW*

SLP_S3*

RTD3_PWR_EN

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO

EE_CS*

EE_CLK

BSSRXp2
BSSRXn2

BSSTXp2
BSSTXn2

BSSTXp1
BSSTXn1

BSSRXp1
BSSRXn1

BSBU1
BSBU2

PB_USB2_D_P
PB_USB2_D_N

PB_HPD

PB_I2C_INT

PB_USB2_MXCTL

PB_USB2_RBIAS

R2854

200

1%

1/20W

MF

2

201

PLACE_NEAR=U2800.H6:2MM
PLACE_NEAR=U2800.J6:2MM

TF

1/20W

R2855

21

4.75K

0.5%
0201

TBT_X_RBIAS
TBT_X_RSENSE

J6
J5

A23

A1

AC23

AC1

D4

L8

RBIAS

RSENSE
PA_MONDC
PB_MONDC
PC_MONDC
USB_MONDC
TEST_EDM

FUSE_VQPS_64

DEBUG

USB2_ATEST

PCIE_ATEST

MONDC_SVR

VGA_RES

ATEST_P
ATEST_N

THERMDA

V23
V22

P23
P22

K23
K22

F23
F22

T4
N16Y6

AB21
AC21

AC19
AB19

AB17
AC17

AC15
AB15

N4
N5

R5

W1
W2

W4
Y1
Y2
AA1
W6

V2
V1
V5
V4
U2
U1
T5

E5
D22

D23
Y18

W16
W18
Y16

B7
A7

A9
B9

A11
B11

A13
B13

L4
L5

E19
D19

T1

M5

R1
F19

B23
AB23
D5

H5
J9

J11
V8

PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS

NC_DP_X_SRC_ML_P<0>
NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1>

NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2>

NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3>

NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

TBT_X_HDMI_DDC_DATA

TBT_X_HDMI_DDC_CLK
TBT_X_ROM_WP_L

TBT_X_TMU_CLK_OUT
TBT_WAKE_3V3_L
TBT_X_PLUG_EVENT_L

TBT_X_TMU_CLK_IN

I2C_TBT_X_SCL
I2C_TBT_X_SDA

TBT_X_USB_PWR_EN

TBT_X_CIO_PWR_EN

TBT_X_BATLOW_L

PM_SLP_S3_L

TBT_X_RTD3_PWR_EN

USBC_X_RESET_L

TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT

UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK

USBC_XB_D2R_P<2>

USBC_XB_D2R_N<2>

USBC_XB_R2D_CR_P<2>

USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<1>
USBC_XB_R2D_CR_N<1>

USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>

USBC_XB_AUXLSX1

USBC_XB_AUXLSX2

NC
NC

DP_XB_HPD

I2C_TBT_XB_INT_L

TBT_XB_USB2_MXCTL
TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:3MM

1

R2853

200

1%

NC
NC

NC
NC

NC

1/20W
MF
201

2

TBTTHMSNS_X_D1_P

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

IN

BOM_COST_GROUP=TBT

29

29

29

29

27

27

To SPI Flash

31

BI
BI

31

31 27

27

OUT

NOSTUFF

1

R2837

2.2K

5%
1/20W
MF
201

2

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

118 29

118 29

118 29

118 29

118 29

118 29

118 29

118 29

PLACE_NEAR=U2800.N16:2MM

29 20 14

R2851

3.01K

1%

1/20W

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

29

OUT
OUT

OUT
OUT

IN
IN

IN

IN

IN

OUT

IN
IN

OUT
OUT

OUT
OUT

IN
IN

29

29

29

29

29

29

29

29

29

29

29

29

121 27

29

32

32

32

32

105 29

29 14

31 30 29 14

PU at PCH

31 30 29 14

118 29

118 29

118 32

118 32

118 32

118 32

MF

201

131 119 105 14 12

PP3V3_TBT_X_SX

29

IN

PAGE TITLE

57

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

21

PP3V3_TBT_X_SX

29

1

R2835

2.2K

5%
1/20W
MF
201

2

BI

29

1

R2834

2.2K

5%
1/20W
MF

2

201

BI

27

79 29 27

USB-C HIGH SPEED 1

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

BRANCH

PAGE

28 OF 200

SHEET

27 OF 131

1

R2827

100K

5%
1/20W
MF
201

2

SYNC_DATE=05/11/2017SYNC_MASTER=J132

4.0.0
evt-0

D

C

79 29 27

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2931

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2932

1.0UF1.0UF

20%

2

X5R
0201-1

1

C2968

10UF

20%

6.3V

2

CERM-X5R
0402-4

1

C2984

1.0UF 1.0UF

20%

6.3V

2

X5R
0201-1

1

C2933

20%

6.3V6.3V

2

X5R
0201-1

1

C2964

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2985

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2934

1.0UF1.0UF

20%

6.3V

2

X5R
0201-1

1

C2965

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2935

1.0UF

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2966

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1

2

VOLTAGE=3.3V

C2920

1.0UF

20%

6.3V
X5R
0201-1

122 28

1

C2936

1.0UF

20%20%

6.3V

2

X5R
0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R
0201-1

29

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

PP0V9_TBT_X_PCIE

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

PP3V3_TBT_X_ANA
PP3V3_TBT_X_ANA_PCIE
PP3V3_TBT_X_ANA_USB2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY
INTERNAL SWITCH

H11

H9
H12
H13
H15
H16

T12
T13
T15

N6
T11

T9

E8

J18

L19

M19

L18
M18
M16

E16

L16

H18

W11

Y11

Y5

W12

Y12

Y8
AB4
AC4

C23
C22

W13

AB2

D6

W15

Y15

A4

B4

F2

D2

F1

D1

B1

B2

E18
V11
V12
V13

M6
N19
N18
E12
E13
F11
F12
F13
F15

J16

A2
F8
A6
A8
B8

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC6

AC8

B10
AC10
AC12
AC14
AC16
AC18
AC20
AC22

B12

B14
B16
B18
B20
B22

D8
D9

A10
D11
D12

VCC0P9_SVR_PAB_ANA

VCC0P9_SVR_PC_ANA

VCC0P9_SVR_DPAUX_ANA

VCC0P9_SVR_USB_ANA

VCC0P9_SVR_BRD_SENSE
VCC0P9_PCIE

VCC0P9_ANA_PCIE_1

VCC0P9_ANA_PCIE_2

VCC3P3_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

N15

VSS

L15

VSS

V18

F4

VSS

R9

VSS

R12

U2800

TITAN-RIDGE-DP

CSP

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

L12

M15

L9

M9

R15

M1

M2

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VCC0P9_LC

VCC0P9_LVR

VCC0P9_LVR_SENSE

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

VSS

VSS

VSS

VSS

T6

V16

M12

N9

N12

T18

V6
F18

R6
L6
E6
G1

G2
H2

R8
R11
L11
M8
M13
R16
R13
J13
L13
N8
N11
N13
T8
T16
M11

L1
L2
K1
K2

J1
J2
H1

J8
H8
H6

D13

D15
D16
D18
E9
E11
E15
A12
E22
E23
F9
F20
F16
G22
G23
A14
H20
J19
J20
J22
A16
J23
L20
L22
L23
A18
M20
N20
N22
N23
R18
A20
R19
R20
R22
R23
T20
U23
U22
A22
V9
V15
V20
W8
B6
W9
W22
W23
Y9
Y13
AA22
AA23
AB6
E4
J15
AB1
AC2
F5
F6
J12

PP3V3_TBT_X_LC
PP3V3_TBT_X_SX

1

C2991

2

1

C2975

10UF

20%

6.3V

2

CERM-X5R
0402-4

122 28

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

DIDT=TRUE
SWITCH_NODE=TRUE

VR0V9_IND_TBT_X

PP0V9_TBT_X_LC

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

Add XW or alias on
support page

XW

XW2900

SM

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

1.0UF

20%

6.3V
X5R
0201-1

1

C2976

10UF

20%

6.3V

2

CERM-X5R
0402-4

C2992

1.0UF

6.3V

0201-1

21

29

PP3V3_TBT_X_F

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C2990

1

C2977

20%

6.3V

2

CERM-X5R
0402-4

CRITICAL

1

C2978

10UF10UF

20%

6.3V

2

CERM-X5R
0402-4

L2950

0.68UH-20%-6.1A-0.020OHM

21

1210

SOURCED BY

20%
X5R

29

1

2

C2993

TBTTHMSNS_X_D1_N

INTERNAL SWITCH

1

1.0UF

20%

6.3V

2

X5R

0201-1

C2954

10UF

CERM-X5R

0402-4

OUT

NOSTUFF

1

C2995

2

1

C2910

1.0UF

20%

6.3V

2

X5R
0201-1

C2951

47UF

20%

6.3V
CER-X5R
0603

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

1

2

1.0UF

20%

6.3V
X5R

0201-1

1

C2950

47UF

20%

6.3V

2

CER-X5R
0603

1

20%

6.3V

2

NOSTUFF

1

C2994

47UF

20%

2

1

C2917

12PF

5%
25V

2

NP0-C0G
0201

6.3V

CER-X5R

0603

1

2

C2955

10UF

20%

6.3V

CERM-X5R

0402-4

2x 10uF outside BGA area

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0V

57

BOM_COST_GROUP=TBT

47UF

20%

6.3V

CER-X5R

0603

1

2

1

2

1

2

L2990

1/10W
MF-LF

C2911

1.0UF

20%

6.3V
X5R
0201-1

C2952

47UF

20%

6.3V
CER-X5R
0603

0

5%

603

FROM USB-C PORT
CONTROLLER (UPC)

21

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

PP3V3_S0SW_TBT_X_SNS

1

C2912

1.0UF

20%

6.3V

2

X5R
0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2982

1.0UF

2

1

C2913

1.0UF

20%

6.3V

2

X5R
0201-1

20%

6.3V
X5R
0201-1

SYNC_MASTER=ADITYA SYNC_DATE=03/30/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

27 29

1

C2980

1.0UF

2

1

C2983

1.0UF

20%

6.3V

2

X5R
0201-1

29 95 116 122

1

C2914

1.0UF

20%

6.3V

2

X5R
0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

1

C2915

1.0UF

20%

6.3V

2

X5R
0201-1

29

20%

6.3V
X5R
0201-1

1

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

C2916

1.0UF

20%

6.3V
X5R
0201-1

SOURCED BY
INTERNAL SWITCH

USB-C HIGH SPEED 2

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

BRANCH

PAGE

29 OF 200

SHEET

28 OF 131

D

C

B

A

SIZE

D

4.0.0
evt-0

8

67

35 4

2

1

678

3 245

1

D

C

TBT WAKE LEVEL SHIFTER

PP1V8_SLPS2R

29 80
107

SMC HAS IPU

39

TBT_WAKE_L

DP SRC OPTIONS

IF DP SRC NOT USED

27

=DP_X_SRC_ML_P<3..0>
=DP_X_SRC_ML_N<3..0>

27

NC_DP_X_SRC_AUX_P

27

NC_DP_X_SRC_AUX_N

27

FUSES FOR UPC

PP20V_USBC_XA_VBUS

29 30

29 31

PP20V_USBC_XB_VBUS

PP3V3_G3H_RTC_X29 116

Q3001

1

S G

2

PLACE_NEAR=Q3100:5MM

CRITICAL

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

D

TBT_WAKE_3V3_L

3

27

DP_X_SRC_HPD

NC_DP_X_SRC_ML_P<3..0>
NC_DP_X_SRC_ML_N<3..0>
NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

0603

F3000

6AMP-32V-0.0095OHM

PP20V_USBC_XA_VBUS_F

21

PLACE_NEAR=Q3200:5MM

CRITICAL

0603

740S0135

F3001

6AMP-32V-0.0095OHM

PP20V_USBC_XB_VBUS_F

21

1

R3065

100K

5%
1/20W
MF

2

201

INOUT

R3040

100K

1/20W 5% MF 201

MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1

21

29

31

Ridge and ACE PDs

USBC_XA_CC1

30

USBC_XA_CC2

30

29 30

105 29 27

UPC_X_5V_EN

30

TBT_XA_LSTX

30

TBT_XA_LSRX

31

TBT_XB_LSTX

31

TBT_XB_LSRX

USB_UPC_XA_P

30

30

USB_UPC_XA_N

R3032

MF5% 1/20W

R3020
R3021
R3022

1/20W

R3023

1/20W1MMF

R3024
R3025

5% 201

100K

201

2015% MF1/20W

2015% MF1/20W

2015% MF

2015%

MF1/20W5% 201

MF1/20W

1M

1M

1M

1M

1M

21

21

21

21

21

21

21

GND ALIASES

GND

31

30

GND

30

30

30

30

GND

30

GND

31

30

GND

RIDGE 0.9V SVR XW

28

RIDGE ARKANOID CONN

Place on bottom

J3001

M-ST-SM

1413

21
43
65
87
109
1211

1615

505070-1222

TBT_X_PCI_RESET_LTBT_X_PLUG_EVENT_L

USBC_X_RESET_L

PP3V3_TBT_T_ANA_PCIE
PP3V3_TBT_X_ANA
PP3V3_TBT_X_LC

105 29

27

30 27 14

TBT_WAKE_3V3_L

27

TBT_X_CIO_PWR_EN

14 30 30
31

TBT_X_USB_PWR_EN

31
29 30 31

TBT_POC_RESET

28

PP3V3_TBT_X_F

USBC_DBG

ACE A RPD STRAPPING ACE B RPD STRAPPING

MAKE_BASE=TRUE

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

33 30

33 30

USBC_XB_CC1

31

USBC_XB_CC2

31

SIGNAL ALIASES

34

GND
GND
GND
GND

P0V9_TBT_X_SVR_AGND

NO_XNET_CONNECTION=1

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

XW3000

27 20 14 27 14

29 27

79 29 27

106

28

28

SM

29 30

UPC_X_5V_EN
UPC_X_5V_EN

31

USB2_UPC_XB_P

31

USB2_UPC_XB_P

14

USB2_UPC_XB_N

31

14

USB2_UPC_XB_N

USB2_UPC_XA_P29
USB2_UPC_XA_P

14

29

USB2_UPC_XA_N
USB2_UPC_XA_N

14

21

30

UPC_PMU_RESET
UPC_PMU_RESET

31

31

27 29

27 29

27 29

27 29

105 107

105 107

105 107

105 107

USBC_X_RESET_L

UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_T_SPI_CLK
UPC_T_SPI_CS_L
UPC_T_SPI_MOSI
UPC_T_SPI_MISO

UPC_X_5V_EN

MAKE_BASE=TRUE

USB2_UPC_XB_P

MAKE_BASE=TRUE

USB2_UPC_XB_N

MAKE_BASE=TRUE

USB2_UPC_XA_P

MAKE_BASE=TRUE

USB2_UPC_XA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

UPC_PMU_RESET

MAKE_BASE=TRUE

USBC_X_RESET_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

29

27

I2C_UPC_X_SDA2

33 31

33 31

119 107 77 67

30

I2C_UPC_X_SDA2

31

29

30

31

29

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2
I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

30 29

PP20V_USBC_XA_VBUS_F

TBT

Alpine Ridge U2800

(MASTER)

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

27
29

27
29

27
29

I2C SERIES R'S

PLACE_NEAR=U3900.J4:5mm

201

33

33

R3080

I2C_UPC_SDA

21

PLACE_NEAR=U3900.M3:10mm

I2C_UPC_SCL

21

30K

5%

1/20W

MF

201

R3041

5% MF

1/20W

R3042

5% 1/20W MF 201

TBT to ACE

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L
I2C_TBT_XB_INT_L

I2C_UPC_SDA

I2C_UPC_SCL

21

SOC_USB_VBUS

K

DFN1006

BZT52C3V0LP

A

D3080

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L

Sec ACE

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XB_INT_L

Pri ACE

U3100

U3200

51

51

51

51

D

126 119 38

30

30

30

31

31

31

C

IN

TBT_X_XTAL25M_OUT

to/from Ridge

OUT

TBT_X_XTAL25M_IN

TR/ACE SPI BUS SERIES R'S

TBT_X_SPI_CLK

27

B

TBT_X_SPI_CS_L

27

27

TBT_X_SPI_MOSI

27

TBT_X_SPI_MISO

ROM

14

USB3_EXTA_R2D_C_P

IN

DCI

PCH USB3

14

USB3_EXTA_R2D_C_N

IN

A

25MHz xtal

31

42

R3094
R3095
R3096
R3097
R3098
R3090
R3091
R3092
R3093

C3020

0.1UF

21

10%
16V

X5R-CERM

0201

C3021

0.1UF

21

10%
16V

X5R-CERM

0201

14

14

USB3_EXTA_R2D_P
USB3_EXTA_R2D_N

126 119

126 119

47 29

47 29

30

30

C3002

CRITICAL

Y3000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG
UPC_XB_SPI_CLK

1/20W

UPC_XB_SPI_CS_L
UPC_XB_SPI_MOSI

1/20W

UPC_XB_SPI_MISO

1/20W

UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO

MF

2015% 1/20W MF

201

MF 2011/20W5%

MF5% 1/20W 201

OUT
OUT

BI
BI

OUT

BI

BI
BI

100

15
15
15
15
15
15
15
15

21

5% 1/20W MF 201

21

5% MF 201

21

5% 1/20W 201MF

21

5% 201

21

5% MF 201

21
21

5% 1/20W MF

21
21

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

USB_SOC_TYPEC_P
USB_SOC_TYPEC_N

SWD_SOC_SWCLK
SWD_SOC_SWDIO

USBC_XA_USB_TOP_P
USBC_XA_USB_TOP_N

20PF

21

5%
25V
C0G

0201

C3003

20PF

21

5%
25V
C0G

0201

29 116

107 51 39

31

31

Ace

31

31

29 27

AR

29 27

29 27

29 27

29 27

29

29

29

31 30

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

29

IN

IN

IN

OUT

IN

IN

IN

OUT

PP3V3_G3H_RTC_X

PI3USB32324

PCH_USB3_RX_P

3

PCH_USB3_RX_N

4

PCH_USB3_TX_P

6

PCH_USB3_TX_N

7

USB2_EP_P

1

USB2_EP_N

2

SWCLK

24 10

SWDIO

23

ANALOG1

11

ANALOG2

12

ACE ARKANOID CONN

USBC_DBG

I2C_TBT_XB_INT_L
I2C_UPC_X_SCL2
I2C_UPC_X_SDA2

UPC_I2C_INT_L

TBT_X_SPI_CLK_DBG
UPC_XA_UART_TX

NC ALIASES / NO TEST

31

IN

NC_USBC_XA_USB_BOTP30

30

NC_USBC_XA_USB_BOTN

C3022

20

VDD

U3000

QFN-1

5

GND

14

17

USB2_RP_P

USB2_RP_N

USB2_B_P
USB2_B_N

USB2_T_N

USB2_T_P

SDA

SCL

DEBUG1
DEBUG2

EPAD

25

8
9

16
15

18
19

13
22

21

Place on bottom

31

30

IN

IN

J3000

505070-1222

M-ST-SM

NO_TEST=1

1413

21
43
65
87
109
1211

1615

I2C_TBT_XA_INT_L
I2C_TBT_X_SDA

I2C_TBT_X_SCL
I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL
UPC_XA_UART_RX

29 27

29 27

29 27

30 29

30 29

31 30

NC_UPC_XB_I2C_ADDR PCIE_TBT_X_D2R_P<0>

MAKE_BASE=TRUE

NC_USBC_XA_USB_BOTP

MAKE_BASE=TRUE

NC_USBC_XA_USB_BOTN

NO_TEST=1

TBT_POC_RESET

UPC_XA_FAULT_L

UPC_XB_FAULT_L

30

TP_USBC_XA_RESET_L

TBT_X_HDMI_DDC_DATA

27

TBT_X_HDMI_DDC_CLK

27

R3079

5%

POWER ALIASES

27

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XB_LDO
PP3V3_UPC_XA_LDO

30

29 30

PP20V_USBC_XA_VBUS
PP20V_USBC_XB_VBUS

29 31

30 31 107 108

PPDCIN_G3H

109

PP5V_S4_X_USBC

30

31

PP5V_S4_X_USBC
PP5V_S4_X_USBC

34 122

PP3V3_S0SW_TBT_X_SNS

28 95 116 122

30

PP3V3_TBT_X_SX
PP3V3_TBT_X_SX31

PP3V3_TBT_X_SX27 28

PP1V8_SLPS2R30
PP1V8_SLPS2R

31

0

1/20W

0201MF

R3078

0

5% 1/20W
MF 0201

21

DEBUG ALIASES

0.1UF

21

10%
16V

X5R-CERM

0201

USB_DBG_PCH_XA_F_P
USB_DBG_PCH_XA_F_N

USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_BOT_N

USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_TOP_P

I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL

UPC_XA_DBG1
UPC_XA_DBG2

L3000

90-OHM-0.1A

EXCX4CE

SYM_VER-1

4

3 2

PLACE_NEAR=U3000:5mm

BI
BI

BI
BI

BI
BI

BI
BI

USB2_UPC_XA_P

1

USB2_UPC_XA_N

32 29

32 29

32

29

32 29

30 29

30

29

30

30

29

29

Diodes for USB2

USBC_XA_USB_DBG_BOT_P

32 29

USBC_XA_USB_DBG_BOT_N

32

29

USBC_XA_USB_DBG_TOP_N

32 29

USBC_XA_USB_DBG_TOP_P

32 29

PLACE_NEAR=U3000.19:10mm

PLACE_NEAR=U3000.18:10mm

PLACE_NEAR=U3000.15:10mm

PCH_UART_DEBUG_R2D31
PCH_UART_DEBUG_D2R31
SOC_DFU_STATUS30
SOC_FORCE_DFU30

SWD_SOC_SWCLK29 47

PLACE_NEAR=U3000.24:5mm

SWD_SOC_SWDIO29 47

PLACE_NEAR=U3000.23:5mm

PLACE_NEAR=U3000.16:10mm

R3076

5%
MF 0201

R3077

5% 1/20W

K

BAS70LP

DFN1006-2 DFN1006-2

A

D3001

TBT_POC_RESET

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

21

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

TP_USBC_XA_RESET_L

MAKE_BASE=TRUE

TBT_X_HDMI_DDC_DATA

MAKE_BASE=TRUE

TBT_X_HDMI_DDC_CLK

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PPDCIN_G3H

MAKE_BASE=TRUE

PP5V_S4_X_USBC

MAKE_BASE=TRUE

PP3V3_S0SW_TBT_X_SNS

MAKE_BASE=TRUE

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

PP1V8_SLPS2R

PCH_UART_DEBUG_R2D

MAKE_BASE=TRUE

PCH_UART_DEBUG_D2R

MAKE_BASE=TRUE

SOC_DFU_STATUS

MAKE_BASE=TRUE

SOC_FORCE_DFU

MAKE_BASE=TRUE

0

21

1/20W

21

0201MF

K

UPC_XB_DBG3

0

UPC_XB_DBG4

K

BAS70LP BAS70LP

DFN1006-2

A

D3002

A

D3003

OUTIN

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

K

107 15 31 30 29

14

14

120 95

120 95

31

30

38

BAS70LP

DFN1006-2

A

D3004

122 120 32

79 29 27

126 119 15

126 119 15

131 119 38

BI

BI

122 120 119 32

122 119 68 55 53

29 80 107

131 119 77

31

119

119

31

117
118

117
118

117
118

117
118

117
118

117
118

117
118

118 117

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

IN

IN

IN

IN

IN

IN

IN

PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_R2D_C_N<0>

PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_R2D_C_N<1>

PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_R2D_C_N<2>

PCIE_TBT_X_R2D_C_P<3>

PCIE_TBT_X_R2D_C_N<3>

IN

PCIE_TBT_X_D2R_C_P<0>

IN

PCIE_TBT_X_D2R_C_N<0>

IN

IN

PCIE_TBT_X_D2R_C_N<1>

IN

PCIE_TBT_X_D2R_C_P<2>

IN

PCIE_TBT_X_D2R_C_N<2>

IN

IN

PCIE_TBT_X_D2R_C_N<3>

IN

BOM_COST_GROUP=TBT

Ridge PCIE Caps

GND_VOID=TRUE

0201 X5R 6.3V 20%

GND_VOID=TRUE

0201

GND_VOID=TRUE

GND_VOID=TRUE

0201 X5R 6.3V 20%

GND_VOID=TRUE

0201 6.3V 20%

GND_VOID=TRUE

GND_VOID=TRUE

0201

GND_VOID=TRUE

0201

0201

0201

0201

0201

0201 X5R 6.3V 20%

0201 X5R 6.3V 20%

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6.3VX5R 20%

6.3V 20%

X5R0201

X5R

X5R 6.3V

X5R 20%6.3V

X5R 6.3V 20%

X5R 6.3V 20%

X5R

6.3V0201 20%

X5R

X5R 6.3V 20%

X5R 6.3V 20%

X5R 6.3V 20%

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

20%0201

2 1

0.22UF

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

20%6.3V0201

2 1

0.22UF

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

USB-C X Support

Apple Inc.

C3040
C3041
C3042
C3043
C3044
C3045
C3046
C3047

GND_VOID=TRUE

C3050

GND_VOID=TRUE

C3051
C3052
C3053
C3054
C3055
C3056
C3057

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2>

PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>

PCIE_TBT_X_R2D_N<3>

PCIE_TBT_X_D2R_N<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<1>PCIE_TBT_X_D2R_C_P<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>

PCIE_TBT_X_D2R_N<3>

GND_VOID=TRUE

DRAWING NUMBER

051-02643

REVISION

BRANCH

PAGE

30 OF 200

SHEET

29 OF 131

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

4.0.0
evt-0

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

SIZE

D

B

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

A

SYNC_DATE=04/19/2017SYNC_MASTER=ADITYA

8

67

35 4

2

1

D

678

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

3 245

1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

29

PP1V8_SLPS2R

1

C3115

1.0UF

20%

6.3V

2

X5R
0201-1

PP20V_USBC_XA_VBUS

29

PP3V3_G3H_RTC_X

116

PP5V_S4_X_USBC

29

CAP FOR PP_5V0 ON VR PAGE

FUSE

Add on
support page

R3169

5%

1

C3100

10UF

20%

6.3V

2

CERM-X5R
0402-1

100K

201MF1/20W

29

21

PHV_INT_XA_G3H

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

C11

B11

A11

PP_5V0

PP_5V0

D11

PP_5V0

PP_5V0

1

C3101

1UF

10%
35V

2

X5R
0402

A8

A7

A6

PP_HV

PP_HV

PP_HV

B7

H10

PP_HV

J10

H11

VBUS

VBUS

PP_CABLE

S2
5

K11

J11

VBUS

G2
4

H1

VBUS

B1

VDDIO

VIN_3V3

3

2

NC

TP_Q3100_DRAIN

UPC_XA_GATE2

G1

H2

LDO_3V3

VOUT_3V3

A2

K1

LDO_1V8A

LDO_1V8D

G1

S1

1

8

UPC_XA_GATE1

E1

LDO_BMC

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20%
4V

2

X5R-CERM
0201

29 31 107 108 109

PP3V3_TBT_X_SX

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R
0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R
0402-1

29

C

B

PP3V3_UPC_XA_LDO

1M

1M

R3109

21

5% 201MF1/20W

R3108

21

5% 1/20W

21

R3105

5%1M1/20W 201MF

29

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

201MF

UPC_XA_UART_RX

31 29

TESTPOINTS MUST BE

30 29

30 29

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

119 77 38

131

31 29 27 14

31 29 27 14

119 39 31

GND I2C_ADDR
PRIMARY ONLY

29

121

27

29

29

29

29

IN
OUT

IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT

IN

TBT_POC_RESET
TP_USBC_XA_RESET_L

UPC_XA_GPIO0

PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

DP_XA_HPD

UPC_PMU_RESET

UPC_X_5V_EN

SOC_DOCK_CONNECT

UPC_XA_FAULT_L

GND

GND

UPC_XA_R_OSC

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

TO SMC

1

2

R3103

31 30 29

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

29

29

29

29

29

51

29

29

29

29

30 29

30 29

BI
BI
OUT

BI
BI
OUT

OUT
OUT
IN
OUT

I2C_UPC_XA_DBG_CTL_SCL
I2C_UPC_XA_DBG_CTL_SDA

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XA_INT_L

I2C_UPC_X_SCL2

UPC_I2C_INT_L
GND

GND
GND
GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL
OMIT_TABLE

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1
C_SBU2

NC

H7
B10

A10
B9

A9

L9
L10

K9
K10

K6
L6

K7
L7

K8
L8

L11

UPC_XA_SS

USBC_XA_CC1
USBC_XA_CC2

USBC_XA_CC1

USBC_XA_CC2
USBC_XA_USB_TOP_P

USBC_XA_USB_TOP_N
NC_USBC_XA_USB_BOTP

NC_USBC_XA_USB_BOTNI2C_UPC_X_SDA2
USBC_XA_SBU1

USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R
0201

BI

BI

BI
BI

29

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

BI

BI

1

C3114

29

BI

29

BI

29

BI

29

BI

120 32

120 32

220PF

10%
16V

2

CER-X7R
0201

1

C3113

220PF

10%
16V

2

CER-X7R
0201

33 29

33 29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

B

A

31 30 29

31 29

27

27

29

29

29

29

TP_UPC_XA_SWD_DATA

TP_UPC_XA_SWD_CLK

IN
OUT

BI
BI

BI
BI
BI
BI

UPC_XA_UART_RX
UPC_XA_UART_TX

TBT_XA_LSTX

29

TBT_XA_LSRX

29

USB_UPC_XA_P

29

USB_UPC_XA_N

29

USBC_XA_AUXLSX1

USBC_XA_AUXLSX2

UPC_XA_DBG1

UPC_XA_DBG2

SOC_DFU_STATUS
SOC_FORCE_DFU

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

L1

B8

H4

H5

G8

H8

D8

GND

E8

GND

F6

GND

F7

GND

F8

GND

G6

GND

G7

PAGE TITLE

SYNC_DATE=05/26/2017SYNC_MASTER=ZIFENG

A

8

USB-C PORT CONTROLLER A

DRAWING NUMBER

051-02643

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

67

29

BOM_COST_GROUP=USB-C

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

4.0.0

BRANCH

evt-0

PAGE

31 OF 200

SHEET

30 OF 131

1

SIZE

D

D

678

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3200

FDPC4044

PWR-CLIP-33

PP20V_USBC_XB_VBUS

29

FUSE

Add on
support page

PP20V_USBC_XB_VBUS_F

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

S2
5

G2
4

NC

3 245

1

D

G1

S1

3

2

1

8

UPC_XB_GATE1

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

29 30 107 108 109

C

B

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

PP3V3_UPC_XB_LDO

1M

1M

1M

1M

R3209

21

R3208

21

21

21

1/20W MF 2015%

1/20W 201MF5%

R3212
R3205

1/20W 201MF5%

29

I2C_UPC_XB_DBG_CTL_SCL

I2C_UPC_XB_DBG_CTL_SDA

2011/20W5% MF

UPC_XB_GPIO1

UPC_XA_UART_TX

31

31

29

PP1V8_SLPS2R

1

C3201

1UF

10%
35V

2

X5R
0402

TP_Q3200_DRAIN

UPC_XB_GATE2

PP3V3_TBT_X_SX

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

PP3V3_UPC_XB_LDO

29

29

PP1V8_UPC_XB_LDOA

PP3V3_G3H_RTC_X

1

C3219

1.0UF

20%

6.3V

2

X5R
0201-1

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

1

2

R3203

121 31

31 30 29

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

NEED 0.1%

116

29

TO SMC

PP5V_S4_X_USBC

CAP FOR PP_5V0 ON VR PAGE

30 29

29

121

30 29 27 14

30 29 27 14

27

29

29

119 39 30

29

29

29

IN

OUT

IN

121 31

IN

IN
OUT
OUT
OUT
OUT
OUT

IN

TBT_POC_RESET
USBC_X_RESET_L

UPC_XB_GPIO0

UPC_XB_GPIO1
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

DP_XB_HPD

UPC_PMU_RESET

UPC_X_5V_EN
SOC_DOCK_CONNECT

UPC_XB_FAULT_L

GND

NC_UPC_XB_I2C_ADDR

UPC_XB_R_OSC

I2C_UPC_XB_DBG_CTL_SCL

31

I2C_UPC_XB_DBG_CTL_SDA

31

29

29

29

29

29

51

29

29

29

29

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN

OUT

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XB_INT_L

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

UPC_I2C_INT_L

UPC_XB_SPI_CLK
UPC_XB_SPI_MOSI
UPC_XB_SPI_MISO
UPC_XB_SPI_CS_L

R3269

1/20W MF

1

C3200

10UF

20%

6.3V

2

CERM-X5R
0402-1

100K

2015%

E11
F11

B2

C2
D10
G11
C10

E10

G10

D7

H6

F10

F1

G2

E4

D5

D1

D2

C1

A5

B5

B6

A3

B4

A4

B3

21

PHV_INT_XB_G3H

C11

B11

A11

PP_5V0

PP_5V0

PP_5V0

MRESET
RESET*

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

BUSPOWERZ
I2C_ADDR

R_OSC
DEBUG_CTL1

DEBUG_CTL2
I2C_SDA1

I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

A6

D11

PP_HV

PP_5V0

A8

A7

PP_HV

PP_HV

B7

PP_HV

J10

H11

H10

VBUS

VBUS

PP_CABLE

U3200

CD3215A

BGA

K11

J11

VBUS

VBUS

HV FET/SENSE

TYPE-C

H1

B1

VDDIO

VIN_3V3

CRITICAL
OMIT_TABLE

G1

H2

LDO_3V3

VOUT_3V3

E1

A2

K1

LDO_1V8A

LDO_BMC

LDO_1V8D

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1
C_SBU2

NC

PP1V8_UPC_XB_LDOD
PP1V1_UPC_XB_LDO_BMC

H7
B10

A10
B9

A9

L9

USBC_XB_CC1

L10

USBC_XB_CC2

K9

USBC_XB_CC1

K10

USBC_XB_CC2

K6

USBC_XB_USB_TOP_P

L6

USBC_XB_USB_TOP_N

K7

USBC_XB_USB_BOT_P

L7

USBC_XB_USB_BOT_N

K8

USBC_XB_SBU1

L8

USBC_XB_SBU2

GROUND

L11

UPC_XB_SS

NC or GND to dissipate heat

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.1V

1

C3209

0.47UF

10%

6.3V

2

CERM-X5R
0201

29

BI

29

BI

32

BI

32

BI

32

BI

32

BI

BI
BI

119 32

119 32

1

C3204

2.2UF

20%
4V

2

0201

1

C3214

220PF

10%
16V

2

CER-X7R
0201

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V

1

C3205

1.0UF

20%

6.3V

2

X5R
0201-1

BI

BI

1

C3213

220PF

10%
16V

2

CER-X7R
0201

33 29

33 29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V

1

C3206

0.47UF

10%

6.3V

2

CERM-X5R
0201

1

C3208

10UF

20%

6.3V

2

CERM-X5RX5R-CERM
0402-1

C

B

29

29

TP_UPC_XB_SWD_DATA
TP_UPC_XB_SWD_CLK

31 30 29

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

BI

USB2_UPC_XB_P

1

4

PLACE_NEAR=U3200.L5:5mm

30 29

IN

OUT

UPC_XA_UART_TX

UPC_XA_UART_RX

TBT_XB_LSTX

29

TBT_XB_LSRX

29

USB_UPC_XB_F_P

BI

USB2_UPC_XB_N

32

PLACE_NEAR=U3200.K5:5mm

27

27

29

29

119 29

119 29

USB_UPC_XB_F_N

BI
BI

BI
BI
BI
BI

USBC_XB_AUXLSX1

USBC_XB_AUXLSX2

PCH_UART_DEBUG_R2D

PCH_UART_DEBUG_D2R

UPC_XB_DBG3
UPC_XB_DBG4

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

L1

B8

H4

H5

G8

H8

D8

GND

E8

GND

F6

GND

F7

GND

F8

GND

G6

GND

G7

A

8

SYNC_DATE=05/26/2017SYNC_MASTER=ZIFENG

PAGE TITLE

A

USB-C PORT CONTROLLER B

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

29

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

32 OF 200

SHEET

31 OF 131

1

SIZE

D

678

3 245

1

D

C

B

CC1

TBT_R2D0

TBT_D2R0

SBU2
USB2 BOT

USB2 BOT

SBU1

TBT_R2D1

TBT_D2R1

CC2

122 120 32 29 119

CRITICAL

D3300

NSR20F40NX_G

120 33

27

27

27

118

118 27

119 31

31

31

29

29

120 30

27

27

118 27

118 27

120 33

DSN2

122 120 29

BI

IN

IN

OUT

OUT

BI
BI
BI

USBC_XB_CC1_CONN
USBC_XB_R2D_CR_N<1>

USBC_XB_R2D_CR_P<1>

USBC_XB_D2R_N<1>

USBC_XB_D2R_P<1>
USBC_XB_SBU2

USBC_XB_USB_BOT_N
USBC_XB_USB_BOT_P

2

GND_VOID=TRUE

D3386

1

SESDL2011

DSN2-THICKSTNCL

BI
BI
BI

IN

IN

OUT

OUT
BI

USBC_XA_R2D_CR_P<2>

USBC_XA_R2D_CR_N<2>

USBC_XA_CC2_CONN

2

GND_VOID=TRUE

D3374

1

VOLTAGE=20V

PP20V_USBC_XA_VBUS

K

A

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

USBC_XA_USB_DBG_BOT_N
USBC_XA_USB_DBG_BOT_P

USBC_XA_SBU1

USBC_XA_D2R_P<2>

USBC_XA_D2R_N<2>

2

GND_VOID=TRUE

D3375

1

SESDL2011

DSN2-THICKSTNCL

SESDL2011

DSN2-THICKSTNCL

VOLTAGE=20V

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

GND_VOID=TRUE

D3371

1

SESDL2011

DSN2-THICKSTNCL

2

GND_VOID=TRUE

D3376

1

SESDL2011

K

A

PP20V_USBC_XB_VBUS

CRITICAL

D3370

DSN2

NSR20F40NX_G

GND_VOID=TRUE

R3371

GND_VOID=TRUE GND_VOID=TRUE

R3370

GND_VOID=TRUE

R3352

GND_VOID=TRUE

R3353

2

GND_VOID=TRUE

D3372

1

SESDL2011

DSN2-THICKSTNCL

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

2

GND_VOID=TRUE

D3377

DSN2-THICKSTNCL

1

SESDL2011

DSN2-THICKSTNCL

1610-COMBO

ESDA25P35-1U1M-COMBO

D3301

2

D3373

1

R3373

1/20W

R3372

5%

R3326

1/20W

5%

1/20W

GND_VOID=TRUE

SESDL2011

DSN2-THICKSTNCL

R3327

K

A

21

2

5%

21

2

21

2

21

2

5%

GND_VOID=TRUE

GND_VOID=TRUE

21

2

201

MF5%

GND_VOID=TRUE

21

2

2011/20W

MF

GND_VOID=TRUE

21

2

201MF5%

GND_VOID=TRUE

21

2

201MF

DZ3301

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

201MF1/20W

MF1/20W5%

GND_VOID=TRUE

201

USBC_XB_D2R_R_N<1>

201MF1/20W5%

GND_VOID=TRUE

USBC_XB_D2R_R_P<1>

201

MF1/20W

2

D3354

ESD8011

X3DFN2-THICKSTNCL

1

118

118

USBC_XA_D2R_R_P<2>

USBC_XA_D2R_R_N<2>

GND_VOID=TRUE

GND_VOID=TRUE

2

2

D3312

X3DFN2-THICKSTNCL

1

1

ESD8011

K

1610-COMBO

ESDA25P35-1U1M-COMBO

D3302

A

USBC_XB_R2D_C_N<1>

USBC_XB_R2D_C_P<1>

GND_VOID=TRUE

C3381

C3380

GND_VOID=TRUE

2

D3349

ESD8011

1

2

1

X3DFN2-THICKSTNCL

DZ3350

C3383

21

GND_VOID=TRUE

C3382

21

D3328

DZ3303

X3DFN2-THICKSTNCL

ESD8011

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUEGND_VOID=TRUE

0.33UF

10% 25V CER-X5R 0201

0.33UF

10% 25V CER-X5R

2

1

5.5V-6.2PF

0201-THICKSTNCL

BYPASS=J3300.59::10MM

GND_VOID=TRUE

C3391

GND_VOID=TRUE

C3390

21

10%

21

10%

GND_VOID=TRUE

2

1

C3373

21

C3372

21

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

2011/20W

2

MF

R3325

1

5%

220K

CRITICAL

1

2

GND_VOID=TRUE

21

0.22UF

10%

GND_VOID=TRUE

21

0.22UF

GND_VOID=TRUE

0.33UF

25V CER-X5R 0201

GND_VOID=TRUEGND_VOID=TRUE

0.33UF

25V CER-X5R 0201

GND_VOID=TRUE

GND_VOID=TRUE

201

201

2

R3351

1

1/20W5% MF

220K

GND_VOID=TRUEGND_VOID=TRUE

0.22UF

GND_VOID=TRUEGND_VOID=TRUE

0.22UF

2

1

MF

R3350

220K

5%

1/20W

USBC_XA_R2D_P<2>USBC_XA_R2D_C_P<2>

020110% 25V X5R

USBC_XA_R2D_N<2>USBC_XA_R2D_C_N<2>

0201X5R25V10%

USBC_XA_D2R_CR_P<2>

USBC_XA_D2R_CR_N<2>

0201

GND_VOID=TRUE

GND_VOID=TRUE

201

2

201

2

MF5% 1/20W

2

R3324

R3329

1

1

5% MF1/20W

220K

1

220K

BYPASS=J3300.59::10MM

PLACE VBUS CAP NEAR EACH VBUS PIN

CRITICAL

1

C3301

0.01UF

10%
25V
X5R-CERM
0201

C3302

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3308

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

25V X5R 0201

X5R25V10%

0201

USBC_XB_D2R_CR_N<1>

USBC_XB_D2R_CR_P<1>

GND_VOID=TRUE

201

2

2

MF5%

R3348

R3349

1

220K

5% 1/20W MF 201

MF 201

R3328

1/20W5%

220K

1

BYPASS=J3300.59::10MM

220K

0201-THICKSTNCL

1/20W

CRITICAL

1

C3303

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3309

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

USBC_XB_R2D_N<1>

USBC_XB_R2D_P<1>

2

DZ3352

5.5V-6.2PF

1

BYPASS=J3300.59::10MM

CRITICAL

1

C3312

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3305

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

OMIT_TABLE

20759-056E-02

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

J3300

F-ST-SM

PWR

SIGNAL

PWR

GND

5857

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433

GND_VOID=TRUE

3635

GND_VOID=TRUE

3837
4039
4241
4443
4645

GND_VOID=TRUE

4847

GND_VOID=TRUE

5049
5251
5453
5655

6059

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

TP_USBC_PP20V_XB

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

USBC_XA_R2D_N<1>

USBC_XA_D2R_CR_P<1>
USBC_XA_D2R_CR_N<1>

TP_USBC_PP20V_XA

120

GND_VOID=TRUE

220K

120

GND_VOID=TRUE

GND_VOID=TRUE

2011/20W

220K

R3319

5% MF

201
MF

2

2

1

1

1/20W5%

BYPASS=J3300.58::10MM
BYPASS=J3300.58::10MM
BYPASS=J3300.58::10MM
BYPASS=J3300.58::10MM

CRITICAL

1

2

CRITICAL

1

2

BYPASS=J3300.58::10MM
BYPASS=J3300.58::10MM
BYPASS=J3300.58::10MM

C3392

GND_VOID=TRUE

C3393

USBC_XB_D2R_CR_N<2>
USBC_XB_D2R_CR_P<2>

GND_VOID=TRUE

2

2

MF 201

GND_VOID=TRUE

201

GND_VOID=TRUE

201

2

2

201
MF1/20W5%

220K

R3358

R3354

1

1

1/20W MF

5% 1/20W

GND_VOID=TRUE

5%

220K

C3370

C3371

C3384

C3385

GND_VOID=TRUE

GND_VOID=TRUE

220K

220K

R3318

2

R3321

1

5% MF1/20W 201

2

1

R3356

1

1

5% 1/20W MF

21

21

GND_VOID=TRUE GND_VOID=TRUE

25V CER-X5R10% 0201

GND_VOID=TRUE

25V CER-X5R10%

201

MF5%

220K

1/20W

R3320

GND_VOID=TRUE

0.22UF

GND_VOID=TRUEGND_VOID=TRUE

0.22UF

21

21

PP20V_USBC_XA_VBUS

C3350

0.01UF

10%
25V
X5R-CERM
0201

C3356

0.01UF

10%
25V
X5R-CERM
0201

GND_VOID=TRUEGND_VOID=TRUE

21

0.22UF

10% 25V X5R 0201

GND_VOID=TRUE

21

0.22UF

C3386

25V CER-X5R10% 0201

C3387

2

R3355

1

DZ3353

5.5V-6.2PF

0201-THICKSTNCL

220K

0.33UF

GND_VOID=TRUE

0.33UF

0201

DZ3300

21

21

10%25V CER-X5R 0201

USBC_XA_R2D_C_P<1>USBC_XA_R2D_P<1>

020110% 25V X5R

USBC_XA_R2D_C_N<1>

0201X5R25V10%

2

5.5V-6.2PF

0201-THICKSTNCL

1

PLACE VBUS CAP NEAR EACH VBUS PIN

CRITICAL

1

C3352

2

CRITICAL

1

C3357

0.01UF

10%
25V

2

X5R-CERM
0201

118

USBC_XB_R2D_C_N<2>USBC_XB_R2D_N<2>

118

USBC_XB_R2D_C_P<2>USBC_XB_R2D_P<2>

X5R

020125V10%

GND_VOID=TRUEGND_VOID=TRUE

0.33UF

0.33UF

GND_VOID=TRUEGND_VOID=TRUE

GND_VOID=TRUE

ESD8011

D3358

USBC_XA_D2R_R_P<1>

USBC_XA_D2R_R_N<1>

GND_VOID=TRUE

GND_VOID=TRUE

2

ESD8011

D3304

X3DFN2-THICKSTNCL

1

CRITICAL

1

C3358

2

USBC_XB_D2R_R_N<2>
USBC_XB_D2R_R_P<2>

2

X3DFN2-THICKSTNCL

1

2

D3329

1

0.01UF

10%
25V
X5R-CERM
0201

0.01UF

10%
25V
X5R-CERM
0201

GND_VOID=TRUE

GND_VOID=TRUE

2

ESD8011

D3360

1

GND_VOID=TRUE

R3374

1/20W 201

GND_VOID=TRUE

R3375

1/20W

GND_VOID=TRUE

R3323

GND_VOID=TRUE

R3322

ESD8011

X3DFN2-THICKSTNCL

DZ3302

5.5V-6.2PF

0201-THICKSTNCL

122 120 119 32 29

CRITICAL

1

C3353

0.01UF

10%
25V

2

X5R-CERM
0201

GND_VOID=TRUE

R3376

R3377

GND_VOID=TRUE GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

5% MF

5%

1/20W

GND_VOID=TRUE

R3359

1/20W

R3357

DZ3351

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

21

2

GND_VOID=TRUE

21

2

201

MF5%

CRITICAL

1

C3362

0.01UF

10%
25V

2

X5R-CERM
0201

GND_VOID=TRUE

21

2

201

MF

21

2

2015%

MF1/20W

GND_VOID=TRUE

5% MF

GND_VOID=TRUE

21

2

201

21

2

201

MF5%1/20W

2

GND_VOID=TRUE

D3382

1

SESDL2011

DSN2-THICKSTNCL

USBC_XA_USB_DBG_TOP_P
USBC_XA_USB_DBG_TOP_N

GND_VOID=TRUE

21

2

5%1/20W MF

2

201

GND_VOID=TRUE

21

2

201

MF1/20W 5%

2

GND_VOID=TRUE

D3378

1

1

SESDL2011

DSN2-THICKSTNCL

USBC_XB_CC2_CONN
USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<2>

USBC_XB_USB_TOP_P
USBC_XB_USB_TOP_N
USBC_XB_D2R_N<2>

USBC_XB_D2R_P<2>

USBC_XB_SBU1

2

GND_VOID=TRUE

2

GND_VOID=TRUE

D3383

1

SESDL2011

USBC_XA_SBU2

USBC_XA_R2D_CR_P<1>

USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>

USBC_XA_D2R_N<1>

USBC_XA_CC1_CONN

2

GND_VOID=TRUE

D3379

1

SESDL2011

DSN2-THICKSTNCL

D3384

DSN2-THICKSTNCL

1

2

GND_VOID=TRUE

D3380

1

SESDL2011

SESDL2011

DSN2-THICKSTNCL

DSN2-THICKSTNCL

2

GND_VOID=TRUE

D3385

1

2

GND_VOID=TRUE

D3381

1

BI

IN

IN

BI
BI

OUT

OUT

BI

SESDL2011

DSN2-THICKSTNCL

OUT

OUT

SESDL2011

DSN2-THICKSTNCL

120 33

27

27

31

31

118 27

118 27

119 31

BI

IN

IN

BI
BI

BI

120 30

27

27

29

29

118 27

118 27

119 33

D

CC2

TBT_R2D1

USB2 TOP

TBT_D2R1

SBU1

C

SBU2

TBT_R2D0

USB2 BOT

TBT_D2R0

CC1

B

A

8

LAST CHANGE: Wed Apr 1 22:57:37 2015

A

SYNC_DATE=08/09/2017SYNC_MASTER=SILU_J680

PAGE TITLE

USB-C CONNECTOR A

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=USB-C

67

35 4

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

33 OF 200

SHEET

32 OF 131

1

SIZE

D

678

3 245

1

XA CC Protection

D

C

USBC_XA_CC1_CONN

32 119

C3432

680PF

10%
25V

X7R-CERM

0201

1

2

SAVE_XA_CC1_Z

GDZ5V6LP3

DFN0201-THICKSTNCL

OMIT_TABLE

R3432

4.02K

1%

1/20W

MF

201

CRITICAL

D3432

R3433

4.99K

1%

1/20W

MF

201

D

OMIT_TABLEOMIT_TABLE

CRITICAL

R3430

100OHM-20%-24V-0.3A

0603

21

CRITICAL

Q3430

DMT5015LFDF

76521

1

2

K

A

SAVE_XA_CC1_B

1

2

UDFN202-6

D

2

G

3

7 6

84

S

SAVE_XA_CC1_G

Q3431

NSS60101DMT

WDFN6

1

R3431

10K

21

5%

1/20W

MF

201

USBC_XA_CC1

PPBUS_G3H

29 30

BI

115 111 33

32 120

C3442

680PF

10%
25V

X7R-CERM

0201

1

2

R3442

4.02K

1%

1/20W

MF

201

1

2

SAVE_XA_CC2_Z SAVE_XA_CC2_G

OMIT_TABLE

CRITICAL

K

D3442

GDZ5V6LP3

1%

1/20W

MF

201

A

SAVE_XA_CC2_B

1

2

DFN0201-THICKSTNCL

R3443

4.99K

CRITICAL

Q3440

DMT5015LFDF

76521

UDFN202-6

D

5

100OHM-20%-24V-0.3A

S

G

3

8 3

Q3431

NSS60101DMT

WDFN6

4

CRITICAL

R3440

0603

84

21

R3441

10K

21

5%

1/20W

MF

201

USBC_XA_CC2USBC_XA_CC2_CONN

PPBUS_G3H

29 30

BI

115 111 33

C

XB CC Protection

B

OMIT_TABLE OMIT_TABLE

CRITICAL

R3450

100OHM-20%-24V-0.3A

CRITICAL

0603

21

Q3450

DMT5015LFDF

76521

32 120 32 120

C3452

680PF

10%
25V

X7R-CERM

0201

1

2

SAVE_XB_CC1_Z

OMIT_TABLE

R3452

4.02K

CRITICAL

1%

1/20W

MF

201

1

2

K

D3452

GDZ5V6LP3

1%

1/20W

MF

201

A

SAVE_XB_CC1_B

1

2

DFN0201-THICKSTNCL

R3453

4.99K

UDFN202-6

D

2

G

3

7 6

84

S

SAVE_XB_CC1_G

Q3451

NSS60101DMT

WDFN6

1

R3451

10K

21

5%

1/20W

MF

201

BI

PPBUS_G3H

29 31

115 111 33

C3462

680PF

10%
25V

X7R-CERM

0201

1

2

SAVE_XB_CC2_Z

OMIT_TABLE

CRITICAL

GDZ5V6LP3

DFN0201-THICKSTNCL

R3462

4.02K

1%

1/20W

MF

201

D3462

R3463

4.99K

1%

1/20W

MF

201

CRITICAL

R3460

100OHM-20%-24V-0.3A

CRITICAL

0603

21

Q3460

DMT5015LFDF

76521

1

2

K

A

SAVE_XB_CC2_B

1

2

UDFN202-6

D

5

G

3

8 3

84

S

SAVE_XB_CC2_G

Q3451

NSS60101DMT

WDFN6

4

R3461

10K

21

5%

1/20W

MF

201

USBC_XB_CC2USBC_XB_CC1USBC_XB_CC1_CONN USBC_XB_CC2_CONN

PPBUS_G3H

29 31

BI

115 111 33

B

A

8

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

371S00181 4
740S00050 4 CRITICAL

DIODE,ZENER,5.6V,250MW,DFN0201

FUSE,THRMSTR,PTC,470OHM,24V,60MA,0603

D3432,D3442,D3452,D3462

R3430,R3440,R3450,R3460

CRITICAL

DESIGN: X1032/MLB_P4BP
LAST CHANGE: Fri Jan 6 16:01:21 2017

PAGE TITLE

SYNC_DATE=04/05/2017SYNC_MASTER=ADITYA

A

USBC X Connector Support

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=USB-C

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

.

BRANCH

evt-0

PAGE

34 OF 200

SHEET

33 OF 131

1

SIZE

D

678

3 245

1

D

PP5V_S4_X_USBC

29 34 122

2

XW3502

R3503

NO_XNET_CONNECTION=1

SM

27.4K

0.1%

1/20W

MF

0201

1

1

2

2

XW3501

SM

1

P5VUSBC_X_SENSE_DIV_XW

P5VUSBC_X_RTN_DIV_XW

1

R3531

27.4K

0.1%
1/20W
MF
0201

2

NO_XNET_CONNECTION=1

1

R3517

191K

0.1%
1/20W
MF
0201

2

1

C3517

22PF

5%
50V

2

C0G
0201

PP5V_USBC_X_VCC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=5V

1

C3522

2.2UF

10%
10V

2

X6S-CERM
0402

34

34

PP5V_G3S

116

UPC_X_5V_EN_R

P5VUSBC_X_SENSE_DIV

P5VUSBC_X_SREF

P5VUSBC_X_VO

P5VUSBC_X_OCSET

P5VUSBC_X_PGOOD

P5VUSBC_X_RTN_DIV

P5VUSBC_X_FSEL

2.2

5%

1/20W

MF

201

1

2

19

20

PVCCVCC

R3501

U3500

ISL95870AHRUZ-_R5749

15 18

EN

10

FB

7

SREF

12

VO

11

OCSET

14

PGOOD

4

RTN

13

FSEL

UTQFN

CRITICAL

BOOT

UGATE

PHASE

LGATE

1

C3521

10UF

20%
10V

2

X5R-CERM
0402-7

17
16
1

PPBUS_G3H

112 115 122

2.2

5%

1/20W

MF

201

1

2

R3509

P5VUSBC_X_VBST

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

P5VUSBC_X_DRVH

P5VUSBC_X_LL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
SWITCH_NODE=TRUE

DIDT=TRUE

P5VUSBC_X_DRVL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

P5VUSBC_X_BOOT_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

1

C3516

0.1UF

10%
16V

2

X7R-CERM
0402

R3539

0

5%

P5VUSBC_X_DRVH_R

1/20W

MF

0201

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

21

CAPDERATE

C3504

33UF

20%
16V

TANT-POLY

CASE-B3

Q3501

FDPC1012S

1

HSG

2

SW

3
4

1

2

LLP

CAPDERATE

C3503

33UF

20%
16V

TANT-POLY

CASE-B3

8

V+

9

V+

LSG

7

CAPDERATE

1

C3500

2.2UF

25V

2

X5R-CERM
0402-1

20%
16V

1

2

1

C3502

33UF

2

TANT-POLY

CASE-B3

L3500

1.5UH-20%-12.5A-0.017OHM

PIMB062D-SM

1

C3501

2.2UF

20%20%
25V

2

X5R-CERM
0402-1

21

P5VUSBC_X_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=5V

P5VUSBC_X_POS

CRITICAL

R3530

0.002

1%

1/2W

MF

0306

2 1
4 3

C3505

2.2UF

20%
25V

0402-1

PP5V_S4_X_USBC

1

C3510

12PF

5%
25V

2

NP0-C0G
0201

2.4G DESENSE

5G DESENSE

CAPDERATE

20%
25V

1

2

1

C3508

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

1

C3506

2.2UF

2

X5R-CERMX5R-CERM

0402-1

1

C3511

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CAPDERATE

1

C3507

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

29 34 122

D

C

1

C3526

10PF

5%
50V

2

C0G
0201

1

R3504

10K

0.1%
1/20W
MF
0201-1

2

1

R3502

10K

0.1%
1/20W
MF
0201-1

2

C3523

1

C3515

10PF

5%
50V

2

C0G
0201

0.1UF

10%
16V

X5R-CERM

0201

P5VUSBC_X_SET0

P5VUSBC_X_SET1

1

2

1

R3518

95.3K

0.1%
1/20W
MF
0201

2

P5VUSBC_X_SET_R

NOSTUFF

R3513

5%

1/20W

MF

201

1

0

2

R3500

11K

21

1%

1/20W

MF

201

8

SET0

9

SET1

6

VID0

5

VID1

353S01281

3

GND

GND

GND

6

5

10

1%

1/20W

MF

201

1

C3570

2

2200PF

2 1

R3521

2.87K

PGNDGND

2

P5VUSBC_X_NEG

CAPDERATE

1

C3509

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

Vout = 5.230V

10%
25V

CER-X7R

0201

1

R3572

2.87K

1%
1/20W
MF
201

2

Freq = 500 kHz
Max OCP = 15.71A

Nom OCP = 12.2A

C

Min OCP = 7.94A

P5VUSBC_X_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0V

XW3500

SM

21

PLACE_NEAR=U3500.2:1mm

34

P5VUSBC_X_PGOOD

P2MM

SM

1

PP

PP3500

IccMax = 6.6A

B

BYPASS=U3540.5::8MM

119 112 46 18 12

29

PP3V3_G3H_RTC_X

116

IN

IN

PM_RSMRST_L

UPC_X_5V_EN

1

C3540

0.1UF

20%
10V
X7R-CERM

2

0402

1

2

SOT353

74LVC1G08GW

NOSTUFF

R3540

0

21

5%

1/20W

MF

0201

5

B

U3540

A

3

B

4

Y

UPC_X_5V_EN_R

34

A

8

A

SYNC_DATE=04/05/2017SYNC_MASTER=J132

PAGE TITLE

TBT 5V REGULATOR

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

35 OF 200

SHEET

34 OF 131

1

SIZE

D

678

3 245

1

D

D

C

BTUARTMUX_SEL_PCH

39 35

1

R3640

100K

5%
1/20W
MF
201

2

BTUARTMUX_OE_L

PP3V3_G3S_WLAN

35 116

PP1V8_G3S_WLANBT_VDDIO

19 35 36 37 116 122

1

R3641

100K

5%
1/20W
MF
201

40 37 36

IN OUT

40

OUT

UART_BT_R2D
UART_BT_D2R

2

BYPASS=U3640::5mm

C3640

0.1UF

X5R-CERM

10%
10V

0201

1

2

5

M+

4

M-

9

VCC

U3640

Y+

Y-

1

UART_BT_MUX_R2D

2

UART_BT_MUX_D2R

IN

PI3USB102J

15

15

IN
IN

PCH_UART_BT_R2D
PCH_UART_BT_D2R

7

D+

6

D-

8

OE* SEL

X2QFN

CRITICAL

GND

3

10

BTUARTMUX_SEL_PCH

IN

SEL OUTPUT

L SOC (M)
H PCH (D)

C

37 36

39 35

B

121 119 46 12

Q3640 is to protect PCH from Harpoon in G3S

PM_PCH_PWROK

IN

3

PP3V3_G3S_WLAN

D

PP1V8_G3S_WLANBT_VDDIO

40

40

19 35 36 37 116 122

IN
OUT

UART_BT_R2D_RTS_L
UART_BT_D2R_CTS_L

1

S

2

DMN32D2LFB4

DFN1006H4-3

SYM_VER_1

G

Q3640

35 116

BYPASS=U3650::5mm

1

R3651

100K

5%
1/20W
MF
201

2

C3650

0.1UF

X5R-CERM

10%
10V

0201

1

B

2

5

M+

4

M-

9

VCC

U3650

Y+

Y-

1

UART_BT_MUX_CTS_L

2

UART_BT_MUX_RTS_L

OUT

IN

37 36

37 36

PI3USB102J

15

15

IN
OUT

PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L

7

D+

6

D-

8

OE* SEL

X2QFN

CRITICAL

GND

3

10

BTUARTMUX_SEL_PCH

39 35

A

8

SYNC_MASTER=J132 SYNC_DATE=03/29/2017

PAGE TITLE

A

WIFI/BT: Support

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=WIRELESS

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

36 OF 200

SHEET

35 OF 131

1

SIZE

D

678

3 245

1

D

C

PP1V8_G3S_WLANBT_VDDIO

19 35 36 37 116 122

1

R3791

100K

5%
1/20W
MF
201

2

PP3V3_G3S_WLAN

36 37 116 122

1

R3790

100K

5%
1/20W
MF
201

2

TP3701

TP3700

R3700

A

A

PLACE_NEAR=U3730.89:5MM

1

C3725

10UF

20%

6.3V

2

CERM-X5R
0402-4

118 37

118 37

118 37

118 37

118 37

118 37

1

10K

5%

1/20W

MF

201

2

PP3700

P3MM

SM

39

1

TP-P5

39

1

TP-P5

PLACE_NEAR=U3730.74:5MM

1

C3721

10UF

20%

6.3V

2

CERM-X5R
0402-4

BI
BI
BI
BI
BI
BI

121 37

121 37

121 37

40 37

40 37

PP

50_G_0_MATCH
50_A_0_MATCH
50_G_1_MATCH
50_A_1_MATCH
50_G_2_MATCH
50_A_2_MATCH

WLAN_JTAG_SEL
WLAN_JTAG_TCK

37

WLAN_JTAG_TDI

37

WLAN_JTAG_TMS

37

WLAN_JTAG_TRST_L
WLAN_JTAG_TDO

UART_WLAN_R2D

40 37

UART_WLAN_D2R
UART_WLAN_D2R_CTS_L

40 37

UART_WLAN_R2D_RTS_L

SPROM_DOUT

36

SPROM_DIN

36

SPROM_CLK

36

SPROM_CS

36

1

WL_GPIO_13

WLAN_CONTEXT_B

38 19

WLAN_AUDIO_SYNC

WLAN_SROM_STRAP

36

TP_WLAN_PMU_TEST

NO_TEST=1

NC_WLAN_GPIO_14

WLAN_CONTEXT_A

39 37

37 13

WLAN_HOST_WAKE
PCH_WLAN_DEV_WAKE

PLACE_NEAR=U3730.42:5MM

1

C3722

10UF

20%

6.3V

2

CERM-X5R
0402-4

91

2G_ANT_CORE0

87

5G_ANT_CORE0

76

2G_ANT_CORE1

72

5G_ANT_CORE1

49

2G_ANT_CORE2

65

5G_ANT_CORE2

44

NC

BT_ONLY_ANT

1

WL_JTAG_SEL

81

WL_JTAG_TCK

82

WL_JTAG_TDI

83

WL_JTAG_TMS

84

WL_JTAG_TRST

85

WL_JTAG_TDO

93

WL_UART_RX

94

WL_UART_TX

95

WL_UART_RTS

96

WL_UART_CTS

67

WL_SPROM_MO

68

WL_SPROM_MI

69

WL_SPROM_CLK

70

WL_SPROM_CS

97

WL_GPIO_13

100

WL_GPIO_21

99

WL_GPIO_20

98

WL_GPIO_17

159

WL_PMU_TEST_O

161

WL_GPIO_14

163

WL_GPIO_12

78

WL_HOST_WAKE

79

WL_DEV_WAKE

PLACE_NEAR=U3730.63:5MM

1

C3724

10UF

20%

6.3V

2

CERM-X5R
0402-4

30

29

VDDBAT_HP

28

VDDBAT_LP

42

VDD3P3_BT

35

89

74

63

VDD3P3_PAD

VDD3P3_FEM_CORE0

VDD3P3_FEM_CORE1

VDD3P3_FEM_CORE2

U3730

LBEE5ZZ1HP-049

LGA

SYM 1 OF 3

CRITICAL

OMIT_TABLE

2

18

17

VDDIO_PMU

VDDIO_RFSW

VDD3P3_SD&OTP

BT_GPIO_2/BT_SF_STRAP

3

VDDIO_DIG

PCIE_REFCLK_P
PCIE_REFCLK_N

PCIE_CLKREQ*

PCIE_WAKE*

BT_UART_RX

BT_UART_TX
BT_UART_CTS
BT_UART_RTS

BT_JTAG_STRAP

BT_SF_MISO
BT_SF_MOSI

BT_DEV_WAKE

BT_HOST_WAKE

PCIE_TX_P

PCIE_TX_N
PCIE_RX_P
PCIE_RX_N

PERST*

BT_SF_CS

BT_SF_CLK

BT_I2S_WS

BT_I2S_DO

BT_I2S_CLK

BT_I2S_DI

BT_GPIO_3

BT_GPIO_4

37

PLACE_NEAR=U3730.3:1MM

PP1V8_G3S_WLANBT_VDDIO

1

C3723

0.1UF

10%

6.3V

2

CERM-X5R
0201

6

PCH_PCIE_CLK100M_WLAN_P

5

PCH_PCIE_CLK100M_WLAN_N

9

PCH_PCIE_WLAN_D2R_C_P

8

PCH_PCIE_WLAN_D2R_C_N

12

PCH_PCIE_WLAN_R2D_P

11

PCH_PCIE_WLAN_R2D_N

14

PCH_WLAN_CLKREQ_R_L

15

AP_PCIE_WAKE_L

16

PCH_WLAN_PERST_L

54

UART_BT_MUX_R2D

55

UART_BT_MUX_D2R

56

UART_BT_MUX_CTS_L

57

UART_BT_MUX_RTS_L

53

BT_ROM_BOOT_HPN_L

60

TP_BT_JTAG_STRAP

36

BT_SPI2_CSN
BT_SPI2_CLK

37

BT_SPI2_MISO

38
39

BT_SPI2_MOSI

40

UART_BT_LH_R2D

41

NC

123

UART_BT_LH_D2R

124

NC

59

BT_GPIO_3

58

BT_GPIO_4

61

HRN_BT_DEV_WAKE

62

BT_HOST_WAKE

19 35 36 37 116 122

IN
IN

19

121 12

121 12

37 19

37 20 13

37 35

37 35

37 35

37 35

37 36

37 36

37 36

37 36

UART_BT_LH_R2D

MAKE_BASE=TRUE

MAKE_BASE=TRUE

37

37

R3718

39 37

R3719

C3707
C3706

C3709
C3708

R3717

OUT

NOSTUFF

0201 1/20WMF

0201 1/20WMF

118

2 1

118

2 1

GND_VOID=TRUE

118

2 1

GND_VOID=TRUE

118

2 1

GND_VOID=TRUE GND_VOID=TRUE

0201 1/20WMF

R3716

0201 1/20WMF

0.1UF

10%

6.3V

X7R 0201

0.1UF

6.3V

0.1UF

10% 0201

6.3V

X7R

0.1UF

6.3V

X7R

0

2 1

5%

NOSTUFF

0

2 1

5%

PCH_PCIE_WLAN_D2R_P

GND_VOID=TRUEGND_VOID=TRUE

PCH_PCIE_WLAN_D2R_N

GND_VOID=TRUE

0201X7R10%

PCH_PCIE_WLAN_R2D_C_P

GND_VOID=TRUE

PCH_PCIE_WLAN_R2D_C_N

020110%

(PCH)

(SOC)

PP1V8_G3S_WLANBT_VDDIO

1

R3750

100K

5%

40

1/20W
MF
201

2

UART_BT_LH_D2R

0

2 1

5%

0

2 1

5%

PP1V8_G3S_WLANBT_VDDIO

19 35 36 37 116 122

PP1V8_S5

12 77 80

R3715

10K

1/20W

201

PCH_BT_ROM_BOOT_L

BT_ROM_BOOT_L

19 35 36 37 116 122

40

IN

PCH_BT_DEV_WAKE

BT_DEV_WAKE

5%
MF

OUT

OUT

IN

IN

1

2

IN

IN

118 14

118 14

118 14

118 14

NOSTUFF

R3713

10K

1/20W

201

15

IN

15

39

5%
MF

D

1

2

38

IN

C

B

37 36

BLUETOOTH SERIAL FLASH

PP1V8_G3S_WLANBT_VDDIO

19 35 36 37 116
122

100K

5%

1/20W

MF

201

1

R3753

2

100K

5%

1/20W

MF

201

1

2

37 36 37 36

BT_SPI2_CLK

R3754

1K

21

5%

1/20W

MF

201

BT_SFLASH_WP_L

121

BT_SFLASH_HOLD_L

PP3V3_G3S_WLAN

36 37 116 122

R3751

100K

5%

1/20W

MF

201

1

2

R3752

BT_SPI2_CSN BT_SFLASH_CS_L

8

VCC

OMIT_TABLE

U3750

2MBIT

6

SCLK

MX25L2006EZUI-12G

1

CS*

3

WP*

7

HOLD*

USON

GND

4

PLACE_NEAR=U3710.8:2MM

SI/SIO0

SO/SIO1

THRM

PAD

9

BT_REG_ON

WL_REG_ON

19

20

21

VDD1P5_1X1

SR1P4_VLX

SR1P8_VLX

22

23

24

VIN_RFLDO

34

SR1P2_VLX

26

25

VDD1P2_3X3

CLK32K

33

32

52

B

PLACE_NEAR=U3750.8:2MM

1

C3710

0.1UF

10%

6.3V

2

CERM-X5R
0201

5

2

BT_SPI2_MOSI

BT_SPI2_MISO

PLACE_NEAR=U3750.8:4MM

1

C3712

10UF

20%

6.3V

2

CERM-X5R
0402-4

37 36

P1V5_WLANBT_VLX

36

36

DIDT=TRUE
SWITCH_NODE=TRUE

P1V2_WLANBT_VLX

DIDT=TRUE
SWITCH_NODE=TRUE

WLAN_PWR_EN

77 37

PP1V5_WLANBT

BT_PWR_EN

77 37

122 120 36

L3701

P1V5_WLANBT_VLX

PVIN_RFLDO_WLANBT_VLX

36

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.5V

2.2UH-1.2A

21

0806

PLACE_NEAR=U3730.23:10MM

L3702

PP1V5_WLANBT_C

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1UH-20%-4.1A-0.048OHM

21

2520-1

PLACE_NEAR=U3730.25:10MM

PP1V2_WLANBT_C

PPVIN_RFLDO_WLANBT

P1V2_WLANBT_VLX

36

PLACE_NEAR=L3702.2:10MM

36

PLACE_NEAR=L3701.2:10MM

VOLTAGE=1.2V

PP1V2_WLANBT

122 120 36

PMU_CLK32K_WLANBT

37 36

C3701

1

4

2

C3702

1

4

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.5V

3

7.5UF

0402-THICKSTNCL

3

7.5UF

0402-THICKSTNCL

20%

4V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.2V

20%

4V

PP1V5_WLANBT

PP1V2_WLANBT

122 120 36

122 120 36

A

BOOT_STRAPS

WLAN_SROM_STRAP

36

R3705

WLAN_SROM_STRAP:
LOW: SROM Enabled
HIGH: SROM Disabled

8

10K

5%

1/20W

MF

201

1

C3711

0.1UF

10%

6.3V

2

CERM-X5R
0201

SPROM_DIN

WIFI_SROM_ORG

36

R3712

10K

2 1

5%

1/20W

MF

201

PVIN_RFLDO_WLANBT_VLX

36

DIDT=TRUE
SWITCH_NODE=TRUE

119 77

IN

10K

5%

1/20W

MF

201

NC

1

2

1

CS

2

SK

7

PE

R3701

SPROM_DOUT

1

2

36

SPROM_CS

36

SPROM_CLK

36

8

VCC

U3710

CAS93C86B

UDFN8

OMIT_TABLE

5

DODI

ORG

EPADGND

9

43
6

WLAN SERIAL EEPROM

67

L3703

2.2UH-1.2A

2 1

0806

PLACE_NEAR=U3730.24:5MM

PMU_CLK32K_WLANBT

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

PPVIN_RFLDO_WLANBT_C

PLACE_NEAR=L3703.1:5MM

PMU_CLK32K_WLANBT

MAKE_BASE=TRUE

C3703

1

3

4

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

PPVIN_RFLDO_WLANBT

7.5UF

0402-THICKSTNCL

20%

4V

37 36

122 120 36

BOM_COST_GROUP=WIRELESS

35 4

PAGE TITLE

WIFI/BT: MODULE 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

37 OF 200

SHEET

36 OF 131

1

SIZE

D

A

SYNC_DATE=05/10/2017SYNC_MASTER=METE

155S00196 2

FILTER,DIPLEXER,LB/HB,LGA6

678

U3810,U3830

3 245

CRITICAL

1

L3814

2.7NH+/-0.1NH-0.6A

118

50_A_0_DIPLEXER

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

RF_TUNINGCRITICAL

CORE0 DIPLEXER AND MATCHING NETWORK

NO STUFF

C3815

0.2PF

+/-0.05PF

25V

COG-CERM

0201

1

2

0201

RF_TUNING

21

50_A_0_MATCH

NO STUFF

1

C3813

0.2PF

+/-0.05PF

2

25V

COG-CERM
0201

118 36

D

C

B

A

10
13
27
31
43
45
46
47
48
50
51
64
66
71
73
75
77
80
86
88
90
92

101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153

4
7

GND

THRM_PAD

U3730

LBEE5ZZ1HP-049

LGA

SYM 2 OF 3

CRITICAL

OMIT_TABLE

THRM_PAD

154
155
156
157
158
160
162
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232

233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308

U3730

LBEE5ZZ1HP-049

LGA

SYM 3 OF 3

CRITICAL

OMIT_TABLE

THRM_PAD THRM_PAD

309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385

36 13

39 36

77 36

40 36

40 36

40 36

40 36

37 36

37 36

37 36

121 36

121 36

121 36

19 12

36 20 13

36

19

36 116 122

DEBUG CONNECTOR

AA25D-S038VA1

PCH_WLAN_DEV_WAKE
WLAN_HOST_WAKE

WLAN_PWR_EN
UART_WLAN_D2R
UART_WLAN_R2D
UART_WLAN_R2D_RTS_L

UART_WLAN_D2R_CTS_L
WLAN_JTAG_TCK

WLAN_JTAG_TMS
WLAN_JTAG_TDI
WLAN_JTAG_TDO
WLAN_JTAG_TRST_L
WLAN_JTAG_SEL

PCH_WLAN_CLKREQ_L
PCH_WLAN_PERST_L
AP_PCIE_WAKE_L
PP3V3_G3S_WLAN

37 36

37 36

37 36

WLAN_JTAG_TCK
MAKE_BASE=TRUE
WLAN_JTAG_TMS
MAKE_BASE=TRUE
WLAN_JTAG_TDI
MAKE_BASE=TRUE

ACCELERATION SENSOR

PLACE_NEAR=U3840.8:2MM
PLACE_NEAR=U3840.8:2MM

VOLTAGE=1.8V

1

C3842

0.22UF

20%

10V

2

0201

SPI_ACCEL_CS_L

37

ACCEL_INT1

37

ACCEL_INT2

37

37

SPI_ACCEL_CS_L
MAKE_BASE=TRUE

37

ACCEL_INT1
MAKE_BASE=TRUE

37

ACCEL_INT2
MAKE_BASE=TRUE

PP1V8_ACCEL_FILT

1

C3841

0.22UF

20%

10V

2

0201

4

6
5

WIFI_DBG

J3801

F-ST-SM

4039

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837

4241

WLAN_JTAG_TCK
WLAN_JTAG_TMS
WLAN_JTAG_TDI

240-OHM-25%-0.42A-0.31DCR

8

VDD

U3840

BMA282

LGA

CS*

INT1
INT2

GND

9

12

11

SPI_ACCEL_CS_L

ACCEL_INT1
ACCEL_INT2

HRN_BT_DEV_WAKE
BT_HOST_WAKE
BT_PWR_EN
UART_BT_MUX_D2R
UART_BT_MUX_R2D
UART_BT_MUX_CTS_L
UART_BT_MUX_RTS_L
BT_SPI2_CLK_R
BT_SPI2_CSN_R
BT_SPI2_MISO_R
BT_SPI2_MOSI_R
BT_GPIO_3
BT_GPIO_4

PMU_CLK32K_WLANBT

PP1V8_G3S_WLANBT_VDDIO

R3880
R3881
R3882
R3883

39 121

39 121

40 121

L3841

0201

7

VDDIO

GNDIO

14

SCX
SDX

SDO

PS

10

119 116 37

39

39

39

SPI_AOP_SENSOR_CLK

1
2

SPI_AOP_SENSOR_MOSI
SPI_AOP_SENSOR_MISO_R

3

13

PP1V8_G3S

PP1V8_G3S

21

36

39 36

IN

35

35

77 36

36 35

36 35

36

36

0
0
0
0

36

36

36

19 35 36 116 122

R3870
R3871

R3872

R3873

RF_TUNING

21

WIFI_DBG

21

WIFI_DBG

21

WIFI_DBG

21

WIFI_DBG

RF_TUNING

47 37

47 37

47 37

RF_TUNING

100K

100K

100K

100K

CRITICAL

J3810

20449-001E-03

PLACE_NEAR=U3730.37:20MM

PLACE_NEAR=U3730.36:20MM

PLACE_NEAR=U3730.38:20MM

PLACE_NEAR=U3730.39:20MM

F-ST-SM

118

2

5%
5%
5%
5%

3

CRITICAL

L3810

DPX205950DT-9063B2SJ

1.2NH-+/-0.05NH-1.1A-0.04OHM

50_0_ANT 50_0_COM

1

NO STUFF

4

02011/20W MF
02011/20W MF
02011/20W MF
02011/20W MF

C3817

0.2PF

+/-0.05PF

COG-CERM

BT_SPI2_CLK
BT_SPI2_CSN
BT_SPI2_MISO
BT_SPI2_MOSI

25V

0201

1

2

36

IN

36

IN

36

IN

36

OUT

0201

RF_TUNING

21

CRITICAL

1

C3816

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

RF_TUNING

2

U3810

COM

CORE1 DIPLEXER AND MATCHING NETWORK

CRITICAL

J3820

20449-001E-03

119 116 37

F-ST-SM

118

3

2

4

CRITICAL

L3820

1.2NH-+/-0.05NH-1.1A-0.04OHM

50_1_ANT 50_1_COM

1

NO STUFF

C3827

0.2PF

+/-0.05PF

25V

COG-CERM

0201

1

RF_TUNING

2

0201

21

CRITICAL

C3826

1

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

RF_TUNING

DPX205950DT-9163C1SJ

2

U3820

0805

CRITICAL

COM

GND

5

CORE2/Aux DIPLEXER AND MATCHING NETWORK

CRITICAL

J3830

20449-001E-03

F-ST-SM

3

2

21

21

21

21

1

4

SPI_ACCEL_CS_L

5% 2011/20W MF

SPI_AOP_SENSOR_MISO_R

5% 2011/20W MF

SPI_AOP_SENSOR_MOSI

5% 2011/20W MF

SPI_AOP_SENSOR_CLK

5% 2011/20W MF

1.2NH-+/-0.05NH-1.1A-0.04OHM

50_2_ANT 50_2_COM

NO STUFF

25V

0201

1

2

37

47 37

47 37

47 37

C3837

0.2PF

+/-0.05PF

COG-CERM

CRITICAL

L3830

0201

RF_TUNING

21

CRITICAL

1

C3836

0.2PF

+/-0.05PF

2

25V

COG-CERM
0201

RF_TUNING

2

COM

CRITICAL

DPX205950DT-9063B2SJ

U3830

BOM_COST_GROUP=WIRELESS

0805

CRITICAL

HI

118

LO

GND

5

3

1

HI

LO

3

1

RF_TUNING

5

3

1

GND

LO

HI

0805

OMIT_TABLE

4
6

OMIT_TABLE

118

6
4

118

118

6
4

118

50_G_0_DIPLEXER

50_A_1_DIPLEXER

NO STUFF

C3825

0.2PF

+/-0.05PF

50_G_1_DIPLEXER

25V

COG-CERM

0201

NO STUFF

C3822

0.2PF

+/-0.05PF

COG-CERM

0201

50_G_2_DIPLEXER

C3835

0.2PF

+/-0.05PF

NO STUFF

50_A_2_DIPLEXER

25V

COG-CERM

0201

NO STUFF

C3832

0.2PF

+/-0.05PF

25V

COG-CERM

0201

CRITICAL

L3811

1.0NH-+/-0.05NH-1.1A-0.04OHM

50_G_0_MATCH

1

CRITICAL

L3812

5.1NH-3%-0.4A

0201

2

118 36

NO STUFF

1

C3812

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

21

0201

RF_TUNING

CRITICAL

L3824

2.7NH+/-0.1NH-0.6A

21

0201

1

2

RF_TUNING

CRITICAL

50_A_1_MATCH

NO STUFF

C3823

1

0.2PF

+/-0.05PF

2

25V

COG-CERM
0201

118 36

L3821

1.2NH-+/-0.05NH-1.1A-0.04OHM

50_G_1_MATCH

1

CRITICAL

L3822

5.1NH-3%-0.4A

0201

2

118 36

25V

21

0201

1

2

RF_TUNING

CRITICAL

L3834

2.9NH+/-0.1NH-0.6A

21

0201

RF_TUNING

1

2

CRITICAL

NO STUFF

C3833

1

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

50_G_2_MATCH

118 36

L3831

1.2NH-+/-0.05NH-1.1A-0.04OHM

21

0201

1

2

SYNC_MASTER=METE SYNC_DATE=08/11/2017

PAGE TITLE

RF_TUNING

1

CRITICAL

L3832

5.1NH-3%-0.4A

0201

2

50_A_2_MATCH

118 36

AP & BT Conn

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

38 OF 200

SHEET

37 OF 131

D

C

B

A

8

67

35 4

2

1

Note 1) IPU represents SW configured state, not HW default

678

3 245

1

D

C

47

47

47

61

49

12

48

48

47

46

63 62

63 62

46

66

91 90 89 88 86 85 84 83

49

46

46

46

119 92 87 47

120 50

OUT
OUT
OUT

IN

OUT

IN

IN
OUT
OUT

IN

IN
OUT

IN
OUT
OUT
OUT

IN

IN

IN
OUT

IN

NC_PLCAM_TX_THROTTLE
NC_GNSS_HOST_TIME
NC_GNSS_DEV_WAKE
CODEC_INT_L
SE_CTLR_FW_DWLD
PCH_SOC_SYNC
MESA_INT
MESA_PWR_EN
NC_WLAN_DEV_WAKE
BOARD_REV0
SPKRAMP_INT_L
SPKRAMP_RESET_L
BOARD_REV1
TPAD_SPI_EN
SSD_BFH
SE_DEV_WAKE
BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2
SSD_PMU_RESET_L
DFR_DISP_INT

A13
A12
B12

AJ36

R36
AB36
AC36

V34

V36
AA36

U36

U35

V32

R32

L36

M33

J33
P33
K32

J32

AA34

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

(IPD)
(IPD)

(IPU)

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 3 OF 18

GPIO/TEST/MISC

(IPD)

(IPD)

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

CFSB

FORCE_DFU

DFU_STATUS

HOLD_RESET

ANALOGMUX_OUT

TST_CLKOUT

TESTMODE

DROOP

SOCHOT

XO0

XI0

L33
L35
K36

K34
W32

V33
J34
AN36

P32
C12

L32
L34

AV23
AV24

WLAN_AUDIO_SYNC
DFR_PWR_EN
BT_ROM_BOOT_L

PMU_ACTIVE_READY
SOC_FORCE_DFU

SOC_DFU_STATUS
SOC_HOLD_RESET
NC_SOC_AMUXOUT

NC_SOC_TST_CLKOUT
SOC_TESTMODE

PMU_DROOP_L
SOC_SOCHOT_L

SOC_XTAL24M_OUT
SOC_XTAL24M_IN

38

IN
OUT
OUT

IN

IN
OUT

121 38

IN
OUT

36 19

50

36

47

47

77

1

R3940

511K

1%
1/20W
MF
201

2

D

131 119 77 30

131 119 77 29

131 119 29

126 119 77 38

R3941

0

5%

1/20W

MF

0201

SOC_XTAL24M_OUT_R

21

CRITICAL

Y3940

1.60X1.20MM-SM

24MHZ-30PPM-9.5PF-60OHM

C

B

46

46

64

64

64

126

126

126 119 29

BI
OUT

OUT
OUT
OUT

BI
BI

IN

I2C_SEP_SDA
I2C_SEP_SCL

SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE

USB_SOC_P
USB_SOC_N

NC_SOC_USB_ID

47

SOC_USB_VBUS
SOC_USB_REXT

1

R3960

200

1%
1/20W
MF
201

2

AV8

SEP_I2C0_SDA

AT7

SEP_I2C0_SCL

AU9

SEP_SPI0_MISO

AV9

SEP_SPI0_MOSI

AT8

SEP_SPI0_SCLK

B23

USB_DP

A23

USB_DM

D23

USB_ID

E23

USB_VBUS

F22

USB_REXT

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 7 OF 18

SEP/USB/DDR

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

H3
H35
AL3
AL35

N2
AF36

H4
H34
AL4
AL34

G3
G35
AM3
AM35

240

1%

1/20W

MF

201

1

2

R3970

SOC_DDR0_RREF
SOC_DDR1_RREF
SOC_DDR2_RREF
SOC_DDR3_RREF

SOC_DDR0_ZQ
SOC_DDR3_ZQ

AON_SLEEP1_RESET_L

PMU_SYS_ALIVE

R3971

240

1%

1/20W

MF

201

IN

IN

CRITICAL

1

R3972

1/20W

2

39

C3940

12PF

1

240

1%
MF

201

2

119 93 92 87 77 39

5%

25V
CERM
0201

R3973

1

2

240

1%

1/20W

MF

201

NC GND

4312

1

2

C3941

1

2

R3974

240

1%

1/20W

201

12PF

5%
25V
CERM
0201

1

2

CRITICAL

R3975

240

1%

1/20W

MFMF

201

PP1V1_SLPDDR

1

2

80

B

A

PP1V8_SLPS2R

R3939
R3976
R3977

47K
10K
10K

8

SYNC_MASTER=SILU SYNC_DATE=05/26/2017

PAGE TITLE

A

SoC GPIO/SEP/USB/DDR/Test

DRAWING NUMBER

47 80

21
21
21

1/20W MF

MF

SOC_SOCHOT_L

2015%

SOC_TESTMODE

2015% 1/20W MF

SOC_HOLD_RESET

2015% 1/20W

38

126 119 77 38

121 38

BOM_COST_GROUP=SOC

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

39 OF 200

SHEET

38 OF 131

1

SIZE

D

D

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

36

36

37

37

35

20 15

47

37

47

47

47

OUT
OUT

IN
IN

OUT

IN

IN
OUT
OUT

OUT
BI

WLAN_CONTEXT_A
WLAN_CONTEXT_B
ACCEL_INT1
ACCEL_INT2
BTUARTMUX_SEL_PCH
SOC_PERST_L
NC_ALTIMETER_INT
SPI_ACCEL_CS_L
NC_SPI_ALTIMETER_CS_L

NC_I2C_AOP_SCL
NC_I2C_AOP_SDA

D3

AOP_FUNC[0]

F4

AOP_FUNC[1]

M6

AOP_FUNC[2]

D4

AOP_FUNC[3]

F3

AOP_FUNC[4]

K6

AOP_FUNC[5]

E4

AOP_FUNC[6]

J3

AOP_FUNC[7]

H6

AOP_FUNC[8]

N6

AOP_I2C0_SCL

G5

AOP_I2C0_SDA

(IPD)
(IPD)

(IPD)

BGA

SYM 6 OF 18

AOP

(IPU)
(IPU)
(IPU)

(IPD)
(IPD)

AOP_PDM_CLK0
AOP_PDM_CLK1
AOP_PDM_CLK2
AOP_PDM_CLK3
AOP_PDM_CLK4

AOP_PDM_DATA0
AOP_PDM_DATA1

AOP_SPI_MOSI

AOP_SPI_SCLK

AOP_SPI_MISO

P6

PDM_DMIC_CLK0_R

K2

PDM_DMIC_CLK1_R

J6

SMC_FIXTURE_MODE_L

L6

NC_PLCAM_PROX_INT_L

L5

NC_PLCAM_ROMEO_B2B_DETECT

J5

PDM_DMIC_DATA0

K4

PDM_DMIC_DATA1

D2

SPI_AOP_SENSOR_MOSI_R

F2

SPI_AOP_SENSOR_CLK_R

E2

SPI_AOP_SENSOR_MISO

OUT
OUT

IN
IN
IN

IN
IN

OUT
OUT

IN

47

47

47

47

64

64

47

47

47

119 47

D

C

77

77

OUT
BI

SPMI_CLK
SPMI_DATA

R4036
R4037

PLACE_NEAR=U3900.AD6:5MM
PLACE_NEAR=U7800.M7:5MM

20
20

21
21

1/20W MF5%

OMIT_TABLE

CRITICAL

U3900

H9M

AL6

120 50

201
2011/20W

MF5%

119 77

46

117

47

18

61

36

47

47

47

47

47

77

IN
IN
IN

OUT

IN
OUT
OUT

IN
OUT

IN

IN

IN

IN

IN

DFR_TOUCH_INT_L

CPU_SMC_THRMTRIP_L

GFX_SELF_THROTTLE_1V8
SMC_GPU_THRMTRIP
XDP_PRESENT_L
CODEC_RESET_L
BT_DEV_WAKE
NC_PCIEDN_WAKE_L
NC_ENET_LOW_PWR
TPAD_SPI_INT_L
NC_SDCONN_STATE_CHANGE_L
NC_ENET_MEDIA_SENSE
PMU_INT_L

SPMI_CLK_R
SPMI_DATA_R

PMU_CLK32K_SOC

AON_GPIO0

AE6

AON_GPIO1

AT5

AON_GPIO2

AN4

AON_GPIO3

AK4

AON_GPIO4

AV5

AON_GPIO5

AR3

AON_GPIO6

AG6

AON_GPIO7

AU5

AON_GPIO8

AP2

AON_GPIO9

AR4

AON_GPIO10

AN3

AON_GPIO11

AT6

AON_GPIO12

AD6

AON_SPMI_SCLK

AR2

AON_SPMI_SDATA

AR5

RT_CLK32768

(IPU)

(IPU)

(IPU)
(IPD)
(IPU)

BGA

SYM 5 OF 18

AON

(IPU)

(IPU)
(IPU)
(IPU)(IPD)

(IPD)

AON_SWD01_TCK

AON_SLEEP1_RESET*

JTAG_TCK
JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TRST*

JTAG_SEL

DOCK_CONNECT

AON_SWD0_TMS
AON_SWD1_TMS

WDOG

AK6
AN5
AH6
AP4
AJ6
AC6

AN2
AJ4

AH4
AJ2

AJ5
AF6

SWD_SOC_SWCLK
SWD_SOC_SWDIO
DEBUG_JTAG_SOC_TDI
DEBUG_JTAG_SOC_TDO
TP_JTAG_SOC_TRST_L
SOC_JTAG_SEL

(DAP=0, TAP=1)

SOC_DOCK_CONNECT
WLAN_JTAG_TMS

NC_MESA_MENUKEY_L
WLAN_JTAG_TCK

SOC_WDOG
AON_SLEEP1_RESET_L

IN

BI

119 126

119 126

121

121 39

IN

BI

IN

OUT

OUT

OUT

47

38

126 47

126 47

119 39 31 30

121 37

121 37

119 77

C

B

118 39 20 12

118 39 20 12

118 39 20 12

118 39 20 12

AK2

COLD_RESET*

AK3

CFSB_AON

121 119 77 64

SOC_COLD_RESET_L

R4039

5%

IN

PMU_COLD_RESET_L

21

4.7K

201MF1/20W

OMIT_TABLE

CRITICAL

PLACE_NEAR=U3900.U2:5MM
PLACE_NEAR=U3900.V2:5MM
PLACE_NEAR=U3900.U3:5MM
PLACE_NEAR=U3900.V4:5MM

V2

BI
BI
BI
BI

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>

R4050
R4051
R4052
R4053

20
20
20

21
21
21
21

1/20W MF5%

1/20W5%

MF5%201/20W 201

201
201

MF1/20W5%
MF 201

119 20 12

121 119 46

131 119 77 12

119 93 92 87 77 38

20

39 20 12

46

46

121 46

121 46

46

69 47 46

119 51

119 51

51

51

51

51

51

51

119 51

119 51

51

51

IN
IN
IN

IN

OUT

OUT
OUT

OUT
OUT

IN

BI

IN

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

ESPI_IO_R<0>
ESPI_IO_R<1>
ESPI_IO_R<2>
ESPI_IO_R<3>
ESPI_CLK60M
ESPI_CS_L
ESPI_RESET_L

SMC_PECI_RX
SMC_PECI_TX

SMC_PCH_PWROK
SMC_PCH_SYS_PWROK

SMC_RSMRST_L
SMC_SYSRST_L

PM_SLP_S0_L
SMC_PROCHOT_L

PMU_SYS_ALIVE
I2C_UPC_SCL

I2C_UPC_SDA
I2C_SNS0_S0_SCL

I2C_SNS0_S0_SDA
I2C_SNS1_S0_SCL

I2C_SNS1_S0_SDA
I2C_DISP_SCL

I2C_DISP_SDA
I2C_PWR_SCL

I2C_PWR_SDA
I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA

SMC_ESPI_IO0

U3

SMC_ESPI_IO1
SMC_ESPI_IO2

U4

SMC_ESPI_IO3

V8
U2

SMC_ESPI_CLK

V7

SMC_ESPI_CS*

V6

SMC_ESPI_RESET*
SMC_PECI_IN

M5

SMC_PECI_OUT

T6

W7

PCH_PWROK
SYS_PWROK

W8
W6

RSMRST*
SYS_RESET*

W4

AA4

SLP_S0B

R5

PROCHOT*
SYS_ALIVE

AA6

SMC_I2C0_SCL

M3

SMC_I2C0_SDA

J4

SMC_I2C1_SCL

N4

SMC_I2C1_SDA

P4

SMC_I2C2_SCL

U5

SMC_I2C2_SDA

M2

SMC_I2C3_SCL

U6

SMC_I2C3_SDA

R4

SMC_I2C4_SCL

P3

SMC_I2C4_SDA

T4

SMC_I2C5_SCL

R2

SMC_I2C5_SDA

P2

(IPD)

(IPD)

(IPD)

U3900

H9M

BGA

SYM 9 OF 18

SMC

(IPD)
(IPD)

(IPD)

(IPU)

(IPU)
(IPU)
(IPD)

SMC_GPIO0
SMC_GPIO1
SMC_GPIO2
SMC_GPIO3
SMC_GPIO4
SMC_GPIO5
SMC_GPIO6
SMC_GPIO7
SMC_GPIO8

SMC_GPIO9
SMC_GPIO10
SMC_GPIO11
SMC_GPIO12
SMC_GPIO13
SMC_GPIO14
SMC_GPIO15

SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7

REFP_ADC

REFM_ADC

58 56 54 53 46

SMC_PWM0

SMC_TACH0

SMC_PWM1

SMC_TACH1

SMC_PWM2

Y4
Y8
Y5
AA2
Y7
Y6
AB2
AD5
AD2
AB4
AC2
AC3
AA8
AB3
AE2
L4

AG2
AC4
AH3
AD4
AB6
AH2
AG4
AC5

AF4
AG3

J2
L3

R6
L2

M4

CODEC_WAKE_L
BT_HOST_WAKE
WLAN_HOST_WAKE
GFX_THROTTLE_1V8_L
LID_OPEN_RIGHT
PCC_EVENT
NC_TPAD_VIBE_L
TPAD_KBD_WAKE_L
LID_OPEN_LEFT
NC_SPI_DSCRPTR_OVERRIDE_L
DISP_GCON_INT_L
PCH_GCON_INT_L
TPAD_ACTUATOR_DISABLE_L
TBT_WAKE_L
UPC_I2C_INT_L
NC_GNSS_HOST_WAKE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HI_ISENSE
SMC_GPU_HS_ISENSE
SMC_P3V3_WLAN_ISENSE
SMC_P3V3_CAPLE_ISENSE

PP1V25_SLPS2R_SMC_AVREF
GND_SMC_AVSS

SMC_FAN_0_PWM
SMC_FAN_0_TACH

SMC_FAN_1_PWM
SMC_FAN_1_TACH

NC_SMC_LED_ONEWIRE

61

IN
IN
IN

117

OUT

47

IN

94

IN

47

OUT

47

IN

47

BI

47

OUT

93

IN

15

OUT

47

BI

29

IN
IN

47

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

46

PLACE_NEAR=U3900.AF3:4MM

OUT

IN

OUT

IN

47

BI

37 36

37 36

107 51 29

XW4089

SM

21

119 59

119 59

119 59

119 59

B

A

PP1V8_S5

R4046
R4047
R4054
R4055
R4056
R4057
R4059

8

10K
100K
100K
100K
100K
100K
100K

80

21
21
21

5% 1/20W 201MF

21
21
21
21

MF1/20W5% 201
MF 2011/20W5%

MF5% 2011/20W
MF5% 2011/20W
MF5% 2011/20W
MF5% 2011/20W

SOC_JTAG_SEL
SOC_DOCK_CONNECT
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

SMC_I2C6_SCL

51

OUT

51

BI

121 39

119 39 31 30

118 39 20 12

118 39 20 12

118 39 20 12

118 39 20 12

39 20 12

I2C_SSD_SCL
I2C_SSD_SDA

R3

SMC_I2C6_SDA

T2

(IPU)

67

SMC_UART0_RXD

SMC_UART0_TXD

SWD_OUT0_TCK

SWD_OUT0_TMS

SWD_OUT1_TCK

SWD_OUT1_TMS

V4
V5

AE3
AA5

AF2
AA7

SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX

SSD0_SWCLK_UART_R2D
SSD0_SWDIO_UART_D2R

SSD1_SWCLK_UART_R2D
SSD1_SWDIO_UART_D2R

IN

OUT

OUT

BI

OUT

BI

126 119 47

126 119 47

121 86 85 84 83

121 86 85 84 83

121 91 90 89 88

121 91 90 89 88

SYNC_MASTER=SILU SYNC_DATE=03/22/2017

PAGE TITLE

SoC AOP/AON/SMC

DRAWING NUMBER

SIZE

051-02643

Apple Inc.

REVISION

A

D

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

40 OF 200

SHEET

39 OF 131

1

D

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

82 47

82 47

47

47

82 47

82 47

47

47

47

47

IN
IN
IN
IN

IN
IN

IN
IN
IN
IN

MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
GND
GND

MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N

GND
GND
GND
GND

MIPI0C_DATA0_P

B27

MIPI0C_DATA0_N

A27

MIPI0C_DATA1_P

B25

MIPI0C_DATA1_N

A25

MIPI0C_CLK_P

B26

MIPI0C_CLK_N

A26

MIPI1C_DATA0_P

B28

MIPI1C_DATA0_N

A28

MIPI1C_DATA1_P

B30

MIPI1C_DATA1_N

A30

BGA

SYM 4 OF 18

ISP

ISP_I2C0_SDA

ISP_I2C0_SCL

ISP_I2C1_SDA

ISP_I2C1_SCL

SENSOR0_CLK

SENSOR0_RST

SENSOR0_ISTRB

SENSOR1_CLK

SENSOR1_RST

SENSOR1_ISTRB

AF32
AH36

AB32
AG32

AK35
AK34
AJ33

AD33
AC32
AC34

I2C_FTCAM_SDA
I2C_FTCAM_SCL

NC_I2C_PLCAM_SDA
NC_I2C_PLCAM_SCL

NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
DFR_TOUCH_RESET_L

NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
DFR_DISP_RESET_L

BI

OUT

BI

OUT

OUT
OUT
OUT

OUT
OUT
OUT

52

52

47

47

47

47

52

52

D

120 50

120 50

C

1

R4100

4.02K

1%
1/20W
MF
201

2

47

47

50

50

50

50

1

R4101

4.02K

1%
1/20W
MF
201

2

IN
IN

OUT
OUT

OUT
OUT

GND
GND

MIPI_DFR_DATA_P
MIPI_DFR_DATA_N

MIPI_DFR_CLK_P
MIPI_DFR_CLK_N

SOC_MIPI0C_REXT
SOC_MIPI1C_REXT
SOC_MIPID_REXT

1

R4102

4.02K

1%
1/20W
MF
201

2

MIPI1C_CLK_P

B29

MIPI1C_CLK_N

A29

B33

MIPID_DATA0_P

A33

MIPID_DATA0_N

B32

MIPID_CLK_P

A32

MIPID_CLK_N

MIPI0C_REXT

F23

MIPI1C_REXT

F26
F27

MIPID_REXT

(IPD)

(IPD)

SENSOR2_CLK

SENSOR2_RST

SENSOR_INT

DISP_TE

DISP_VSYNC

CLK32K_OUT

AD32
AJ32
AA33

H32
T36
AK33

NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_INT

DFR_DISP_TE
BOARD_REV2
DFR_TOUCH_CLK32K_RESET_L

OUT
OUT

IN

IN

IN

OUT

47

47

47

120 50

46

120 50

C

52

52

52

52

52

52

120 52

120 52

52

52

52

52

47

120 63

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

IN
IN

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL

I2C_CODEC_SDA
I2C_CODEC_SCL

I2C_ALS_SDA
I2C_ALS_SCL

I2C_DFR_SDA
I2C_DFR_SCL

NC_I2C_SOC_5_SDA
NC_I2C_SOC_5_SCL

NC_SPKR_ID1
SPKR_ID0

AE35

AD35

AF34

AG35

M34

R33
Y32

AE34

T34

U32
R35

U33
P34

R34

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

I2C2_SDA
I2C2_SCL

I2C3_SDA
I2C3_SCL

I2C4_SDA
I2C4_SCL

I2C5_SDA
I2C5_SCL

I2C6_SDA
I2C6_SCL

(IPU)
(IPU)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 2 OF 18

I2C/UART/SPI/I2S

(IPU)

SPI0_MISO
SPI0_MOSI

SPI0_SCLK

SPI0_SSIN

SPI1_MISO
SPI1_MOSI

SPI1_SCLK

SPI1_SSIN

SPI2_MISO
SPI2_MOSI

SPI2_SCLK

SPI2_SSIN

SPI3_MISO
SPI3_MOSI

SPI3_SCLK

SPI3_SSIN

AR9
AR7
AU7
AT9

P36
N34
P35
T32

A19
A20
C19
A18

C17
C18
B18
A17

SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R

SPI_SOCROM_CS_L
SPI_TPAD_MISO

SPI_TPAD_MOSI_R
SPI_TPAD_CLK_R
SPI_TPAD_CS_L

SPI_MESA_MISO
SPI_MESA_MOSI_R
SPI_MESA_CLK_R
WLAN_JTAG_TDI

SPI_DFR_MISO
SPI_DFR_MOSI_R
SPI_DFR_CLK_R
SPI_DFR_CS_L

IN

OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

46

46

47

47

66

48

47

47

47

47

47

PLACE_NEAR=U3900.AR7:5MM
PLACE_NEAR=U3900.AU7:5MM

R4171
R4172

47 46

121 37

120 50

20
20

21
21

5% MF1/20W

MF1/20W5% 201

SPI_SOCROM_MOSI
SPI_SOCROM_CLKSPI_SOCROM_CLK_R

201

OUT
OUT

46

46

B

126 119

126 119

49

49

49

49

35

35

35

35

36

36

47

47

37 36

37 36

37 36

37 36

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

SOC_DEBUGPRT_RX
SOC_DEBUGPRT_TX

UART_SE_D2R
UART_SE_R2D
UART_SE_D2R_CTS_L
UART_SE_R2D_RTS_L

UART_BT_D2R
UART_BT_R2D
UART_BT_D2R_CTS_L
UART_BT_R2D_RTS_L

UART_BT_LH_D2R
UART_BT_LH_R2D
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L

UART_WLAN_D2R
UART_WLAN_R2D
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L

Y33

UART0_RXD

Y34

UART0_TXD

B15

UART1_RXD

A15

UART1_TXD

C15

UART1_CTS*

D15

UART1_RTS*

J36

UART2_RXD

J35

UART2_TXD

N32

UART2_CTS*

M32

UART2_RTS*

M36

UART3_RXD
UART3_TXD

N36

M35

UART3_CTS*

U34

UART3_RTS*
UART4_RXD

B14

UART4_TXD

A14
C14

UART4_CTS*
UART4_RTS*

C13

(IPU)

(IPD)

(IPD)

(IPD)

(IPD)

I2S0_DIN

I2S0_DOUT

I2S0_BCLK
I2S0_LRCK

I2S0_MCK

I2S1_DIN

I2S1_DOUT

I2S1_BCLK
I2S1_LRCK

I2S1_MCK

I2S2_DIN

I2S2_DOUT

I2S2_BCLK
I2S2_LRCK

I2S2_MCK

I2S3_DIN

I2S3_DOUT

I2S3_BCLK
I2S3_LRCK

I2S3_MCK

AC33
AG34
AA32
AG33
AR35

B20
C20
C21
A21
D21

AH34
AB34
AF33
AH35
AR33

AD36
AB35
AE36
W34
AG36

I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_L_R2D_R
I2S_SPKRAMP_L_BCLK_R
I2S_SPKRAMP_L_LRCLK
NC_DFR_TOUCH_RSVD

I2S_SPKRAMP_R_D2R
I2S_SPKRAMP_R_R2D_R
I2S_SPKRAMP_R_BCLK_R
I2S_SPKRAMP_R_LRCLK
NC_PCHROM_SW_EN

I2S_CODEC_D2R
I2S_CODEC_R2D_R
I2S_CODEC_BCLK_R
I2S_CODEC_LRCLK
NC_I2S_CODEC_MCLK

NC_I2S_HAWKING_D2R
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK
NC_I2S_HAWKING_LRCLK
NC_I2S_CODEC1_MCLK

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

63 62

B

47

47

47

47

BI

47

47

47

47

47

61

47

47

47

47

47

47

47

47

47

A

8

SYNC_DATE=03/02/2017SYNC_MASTER=H9M and PMIC

PAGE TITLE

A

SoC ISP/I2C/UART/SPI/I2S

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

41 OF 200

SHEET

40 OF 131

1

SIZE

D

678

3 245

1

OMIT_TABLE

CRITICAL

D

118 14

118 14

118 14

118 14

118 14

118 14

118 14

118 14

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

PCIE_SOC_D2R_P<0>
PCIE_SOC_D2R_N<0>

PCIE_SOC_D2R_P<1>
PCIE_SOC_D2R_N<1>

PCIE_SOC_D2R_P<2>
PCIE_SOC_D2R_N<2>

PCIE_SOC_D2R_P<3>
PCIE_SOC_D2R_N<3>

(All Caps)

GND_VOID=TRUE

C4210

0.22UF

C4211

0.22UF

C4212

0.22UF

C4213

0.22UF

C4214

0.22UF

C4215

0.22UF

C4216

0.22UF

C4217

0.22UF

21

6.3V X5R 020120%

21

21

20% 6.3V X5R 0201

21

20% 0201X5R6.3V

21

6.3V20% 0201

21

21

6.3V20% X5R 0201

21

X5R 02016.3V20%

X5R

X5R

020120% 6.3V

020120% X5R6.3V

118 47

118 47

118 47

118 47

118 47

118 47

118 47

118 47

U3900

H9M

PCIE_SOC_D2R_C_P<0>
PCIE_SOC_D2R_C_N<0>

IN
IN

PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

PCIE_SOC_D2R_C_P<1>
PCIE_SOC_D2R_C_N<1>

IN
IN

PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

PCIE_SOC_D2R_C_P<2>
PCIE_SOC_D2R_C_N<2>

IN
IN

PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_D2R_C_P<3>
PCIE_SOC_D2R_C_N<3>

IN
IN

PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

PCIE_UP_TX0_P

B10

PCIE_UP_TX0_N

C10

PCIE_UP_RX0_P

E10

PCIE_UP_RX0_N

F10

PCIE_UP_TX1_P

A9

PCIE_UP_TX1_N

B9

PCIE_UP_RX1_P

D9

PCIE_UP_RX1_N

E9

PCIE_UP_TX2_P

B8

PCIE_UP_TX2_N

C8

PCIE_UP_RX2_P

E8

PCIE_UP_RX2_N

F8

PCIE_UP_TX3_P

A7

PCIE_UP_TX3_N

B7

PCIE_UP_RX3_P

D7

PCIE_UP_RX3_N

E7

BGA

SYM 1 OF 18

PCIE UP/DN

PCIE_DN_TX0_P

PCIE_DN_TX0_N
PCIE_DN_RX0_P
PCIE_DN_RX0_N

PCIE_DN_TX1_P

PCIE_DN_TX1_N
PCIE_DN_RX1_P
PCIE_DN_RX1_N

PCIE_DN_TX2_P

PCIE_DN_TX2_N
PCIE_DN_RX2_P
PCIE_DN_RX2_N

PCIE_DN_TX3_P

PCIE_DN_TX3_N
PCIE_DN_RX3_P
PCIE_DN_RX3_N

AV31
AU31
AR31
AP31

AU30
AT30
AP30
AN30

AV29
AU29
AR29
AP29

AU28
AT28
AP28
AN28

NC_PCIE_WLAN_R2D_C_P
NC_PCIE_WLAN_R2D_C_N
NC_PCIE_WLAN_D2R_P
NC_PCIE_WLAN_D2R_N

NC_PCIE_ENET_R2D_C_P
NC_PCIE_ENET_R2D_C_N
NC_PCIE_ENET_D2R_P
NC_PCIE_ENET_D2R_N

PCIE_LIFEBOAT_R2D_C_P
PCIE_LIFEBOAT_R2D_C_N
PCIE_LIFEBOAT_D2R_P
PCIE_LIFEBOAT_D2R_N

NC_PCIE_DN3_R2D_CP
NC_PCIE_DN3_R2D_CN
NC_PCIE_DN3_D2RP
NC_PCIE_DN3_D2RN

47

47

47

47

47

47

47

47

OUT
OUT

IN
IN

OUT
OUT

IN
IN

47

47

47

47

47

47

47

47

D

C

12

OUT

SOC_CLKREQ_L

R4218

21

5%1K1/20W MF 201

121 12

121 12

SOC_CLKREQ_R_L

IN
IN

PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N

SOC_PCIE_UP_REXT

1

R4200

3.01K

1%
1/20W
MF
201

2

PCIE_UP_CLKREQ*

B21

PCIE_UP_EXT_REFCLK_P

G13

PCIE_UP_EXT_REFCLK_N

G12

PCIE_UP_REXT

G11

PCIE_DN_REFCLK0_P
PCIE_DN_REFCLK0_N

PCIE_DN_CLKREQ0*

PCIE_DN_PERST0*

PCIE_DN_REFCLK1_P
PCIE_DN_REFCLK1_N

PCIE_DN_CLKREQ1*

PCIE_DN_PERST1*

PCIE_DN_REFCLK2_P
PCIE_DN_REFCLK2_N

PCIE_DN_CLKREQ2*

PCIE_DN_PERST2*

PCIE_DN_REFCLK3_P
PCIE_DN_REFCLK3_N

PCIE_DN_CLKREQ3*

PCIE_DN_PERST3*

PCIE_DN_EXT_REFCLK_P
PCIE_DN_EXT_REFCLK_N

AP26
AR26
AM33
AN34

AN25
AP25
AN35
AK32

AU26
AV26
AH32
AE32

AT25
AU25
AJ34
AK36

AM27
AM26

NC_PCIE_CLK100M_WLAN_P
NC_PCIE_CLK100M_WLAN_N
NC_WLAN_CLKREQ_L
NC_WLAN_PERST_L

NC_PCIE_CLK100M_ENET_P
NC_PCIE_CLK100M_ENET_N
ENET_CLKREQ_L
NC_ENET_RESET_L

PCIE_CLK100M_LIFEBOAT_P
PCIE_CLK100M_LIFEBOAT_N
PCIE_LIFEBOAT_CLKREQ_L
PCIE_LIFEBOAT_RESET_L

NC_PCIE_CLK100M_DN3P
NC_PCIE_CLK100M_DN3N
NC_PCIEDN3_CLKREQ_L
NC_PCIEDN3_RESET_L

41

47

47

47

47

47

47

47

47

OUT
OUT

IN

OUT

OUT
OUT

OUT

47

47

47

47

47

47

(UID_MODE strap on A00)

47

C

B

118 83

118 83

118 83

118 83

118 84

118 84

118 84

118 84

OUT
OUT
IN
IN

OUT
OUT
IN
IN

PCIE_SSD0_R2D_C_P<0>
PCIE_SSD0_R2D_C_N<0>
PCIE_SSD0_D2R_P<0>
PCIE_SSD0_D2R_N<0>

PCIE_SSD0_R2D_C_P<1>
PCIE_SSD0_R2D_C_N<1>
PCIE_SSD0_D2R_P<1>
PCIE_SSD0_D2R_N<1>

PCIE_STG0_TX0_P

AU11

PCIE_STG0_TX0_N

AT11

PCIE_STG0_RX0_P

AP11

PCIE_STG0_RX0_N

AN11

PCIE_STG0_TX1_P

AV12

PCIE_STG0_TX1_N

AU12

PCIE_STG0_RX1_P

AR12

PCIE_STG0_RX1_N

AP12

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 8 OF 18

PCIE STG 0/1

PCIE_DN_REXT

PCIE_STG1_TX0_P
PCIE_STG1_TX0_N
PCIE_STG1_RX0_P

PCIE_STG1_RX0_N

PCIE_STG1_TX1_P
PCIE_STG1_TX1_N
PCIE_STG1_RX1_P

PCIE_STG1_RX1_N

AM25

AU16
AT16
AP16
AN16

AV17
AU17
AR17
AP17

SOC_PCIE_DN_REXT

R4201

3.01K

PCIE_SSD1_R2D_C_P<0>
PCIE_SSD1_R2D_C_N<0>
PCIE_SSD1_D2R_P<0>
PCIE_SSD1_D2R_N<0>

PCIE_SSD1_R2D_C_P<1>
PCIE_SSD1_R2D_C_N<1>
PCIE_SSD1_D2R_P<1>
PCIE_SSD1_D2R_N<1>

1%

1/20W

MF

201

1

2

OUT
OUT

IN
IN

OUT
OUT

IN
IN

118 88

118 88

118 88

118 88

118 89

118 89

118 89

118 89

B

118 85

118 85

118 85

118 85

118 86

118 86

118 86

118 86

84 83

84 83

83 47

84 47

86 85

86 85

121 85 47

121 86 47

86 85 84 83 47

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT

PCIE_SSD0_R2D_C_P<2>
PCIE_SSD0_R2D_C_N<2>
PCIE_SSD0_D2R_P<2>
PCIE_SSD0_D2R_N<2>

PCIE_SSD0_R2D_C_P<3>
PCIE_SSD0_R2D_C_N<3>
PCIE_SSD0_D2R_P<3>
PCIE_SSD0_D2R_N<3>

PCIE_CLK100M_SSD0_01_P
PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_CLKREQ1_L

PCIE_CLK100M_SSD0_23_P
PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ2_L
SSD0_CLKREQ3_L

SSD0_PCIE_RESET_L

PCIE_STG0_TX2_P

AU13

AT13

PCIE_STG0_TX2_N
PCIE_STG0_RX2_P

AP13

PCIE_STG0_RX2_N

AN13

PCIE_STG0_TX3_P

AV14

PCIE_STG0_TX3_N

AU14

PCIE_STG0_RX3_P

AR14

PCIE_STG0_RX3_N

AP14

PCIE_STG0_REFCLK01_P

AP21

PCIE_STG0_REFCLK01_N

AR21

PCIE_STG0_CLKREQ0*

AT33

PCIE_STG0_CLKREQ1*

AR34

PCIE_STG0_REFCLK23_P

AN22

PCIE_STG0_REFCLK23_N

AP22

PCIE_STG0_CLKREQ2*

AP34

PCIE_STG0_CLKREQ3*

AN33

PCIE_STG0_PERST*

AR36

PCIE_STG1_TX2_P
PCIE_STG1_TX2_N
PCIE_STG1_RX2_P

PCIE_STG1_RX2_N

PCIE_STG1_TX3_P
PCIE_STG1_TX3_N
PCIE_STG1_RX3_P

PCIE_STG1_RX3_N

PCIE_STG1_REFCLK01_P

PCIE_STG1_REFCLK01_N

PCIE_STG1_CLKREQ0*
PCIE_STG1_CLKREQ1*

PCIE_STG1_REFCLK23_P

PCIE_STG1_REFCLK23_N

PCIE_STG1_CLKREQ2*
PCIE_STG1_CLKREQ3*

PCIE_STG1_PERST*

AU18
AT18
AP18
AN18

AV19
AU19
AR19
AP19

AU21
AV21
B17
D18

AT22
AU22
C16
A16

AP36

PCIE_SSD1_R2D_C_P<2>
PCIE_SSD1_R2D_C_N<2>
PCIE_SSD1_D2R_P<2>
PCIE_SSD1_D2R_N<2>

PCIE_SSD1_R2D_C_P<3>
PCIE_SSD1_R2D_C_N<3>
PCIE_SSD1_D2R_P<3>
PCIE_SSD1_D2R_N<3>

PCIE_CLK100M_SSD1_01_P
PCIE_CLK100M_SSD1_01_N
SSD1_CLKREQ0_L
SSD1_CLKREQ1_L

PCIE_CLK100M_SSD1_23_P
PCIE_CLK100M_SSD1_23_N
SSD1_CLKREQ2_L
SSD1_CLKREQ3_L

SSD1_PCIE_RESET_L

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT

118 90

118 90

118 90

118 90

118 91

118 91

118 91

118 91

89 88

89 88

88 47

89 47

91 90

91 90

90 47

91 47

91 90 89 88 47

A

PP1V8_AWAKE

R4232

8

47K

47

OUT

SSD0_CLK24M_R

PCIE_STG0_NANDCLK

AP7

AM14

PCIE_STG0_EXT_REFCLK_P
PCIE_STG0_EXT_REFCLK_N

AM15

PCIE_STG1_NANDCLK

PCIE_STG1_EXT_REFCLK_P
PCIE_STG1_EXT_REFCLK_N

AV7

AM19
AM20

SSD1_CLK24M_R

OUT

47

PAGE TITLE

SYNC_DATE=03/15/2017SYNC_MASTER=SILU

A

SoC PCIe

SOC_PCIE_STG0_REXT

1

R4250

3.01K

1%

46 47 80

21

1/20W

ENET_CLKREQ_L

201MF5%

41

1/20W
MF
201

2

PCIE_STG0_REXT

AM16

PCIE_STG1_REXT

AM21

67

SOC_PCIE_STG1_REXT

R4251

3.01K

1%

1/20W

MF

201

DRAWING NUMBER

051-02643

1

Apple Inc.

REVISION

SIZE

D

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

2

BOM_COST_GROUP=SOC

35 4

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

42 OF 200

SHEET

41 OF 131

1

678

3 245

1

D

C

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

PPVDDCPU_AWAKE

80

0.625V - 1.06V

12.5A Max

C4300

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4305

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4320

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4330

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4301

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4306

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4321

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4331

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4302

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4307

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4322

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4332

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4303

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4308

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4323

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4333

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4304

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4309

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4324

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4334

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

AA12
AA14
AA16
AB11
AB13
AB15
AC12
AC14
AC16
AD11
AD13
AD15
AD17
AE10
AE12
AE14
AE16
AE18

P11
P13
P15

P17
R12
R14
R16

T11

T13

T15
U12
U14
U16

V17

W12
W14
W16

Y17

VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU

OMIT_TABLE
CRITICAL

U3900

H9M

BGA

SYM 10 OF 18

VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM

VDD_CPU_SENSE

VSS_CPU_SENSE

AA10
AB17
AC10
R10
T17
U10
V11
V13
V15
W10
Y11
Y13
Y15

N18
N17

C4350

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4355

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4351

0402-THICKSTNCL

1

C4356

0402-THICKSTNCL

1

C4360

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

SOC_VDDCPU_SENSE
NC_SOC_VSSCPU_SENSE

3

4

2

9.1UF

20%

4V

CERM

4

2

4.3UF

20%

4V

CERM

4

2

PPVDDCPUSRAM_AWAKE

80

0.8V - 1.06V

0.9A Max

C4352

9.1UF

20%

4V

CERM

0402-THICKSTNCL

3

1

3

C4353

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4354

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

C4357

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

D

4

4

4

2

3

OUT

47

77 47

4

2

2

2

C

B

A

PP0V82_SLPDDR

80

3.93A Max

4

4

4

4

4

2

2

2

2

2

OMIT_TABLE
CRITICAL

U3900

H9M

BGA

SYM 11 OF 18

VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

VDD_SOC_SENSE

VSS_SENSE

J22
J24
J26
J28
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
N10
N12
N14
N16
N20
N22
N24
N26
N28
R18
R20
R22
R24
R26
R28
U18
U20
U22
U24
U26
U28
W20
W22
W24
W26
W28

AD27
AD28

SOC_VDDSOC_SENSE
NC_SOC_VSSSOC_SENSE

47

47

SYNC_MASTER=SILU SYNC_DATE=04/04/2017

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

IV ALL RIGHTS RESERVED

SoC Power 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

43 OF 200

SHEET

42 OF 131

B

A

SIZE

D

C4370

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4380

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4385

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4371

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4381

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4386

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4372

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

C4373

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

3

4

2

AA20
AA22
AA24
AA26
AA28
AC18
AC20
AC22
AC24
AC26
AC28
AE20
AE22
AE24
AE26

AE28
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28

AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28

J10
J12
J14
J16
J18
J20

VDD_SOC VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

8

67

35 4

2

1

D

C

B

A

678

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

80

PP1V1_SLPDDR

0.86A Max

C4451

2.2UF

20%

4V

X6S-CERM

0201

C4455

2.2UF

20%

4V

X6S-CERM

0201

0402-THICKSTNCL

0402-THICKSTNCL

0402-THICKSTNCL

80

PP0V9_SLPDDR

1.9A Max

43 80

PP0V9_SLPDDR

80

25mA Max

PP0V9_SLPDDR

330mA Max

C4400

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

2

C4405

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

2

C4410

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

2

9mA Max

80

PP0V9_SLPDDR
PP0V9_SLPDDR

80

5mA Max

80

PP0V8_SLPS2R

102mA Max

20%

4V

0201

20%

4V

0201

K19
K21
K23
K25
K27
M11
M13
M15
M17
M19
M21
M23
M25
M27
P19
P21
P23
P25
P27
T19
T21
T23
T25
T27
V19
V21
V23
V25
V27
Y19
Y21
Y23
Y25
Y27

AL14
AL16
AL12

AK13
AK15
AK17

AL18
AL20
AL22

AK19
AK21
AL17

AL26
AL28

AL30
AK25

AK27
AK29

AK23
AJ15

AL24
AJ21
AJ27

1

2

1

2

C4450

2.2UF

X6S-CERM

C4454

2.2UF

X6S-CERM

C4401

9.1UF

20%

4V

CERM

0402-THICKSTNCL

4

20%

4V

4

20%

4V

4

4.3UF

20%

4V

CERM

1

2

3

3

3

4

3

4

3

4

3

4

1

2

C4406

4.3UF

CERM

0402-THICKSTNCL

1

2

C4411

4.3UF

CERM

0402-THICKSTNCL

1

2

C4425

0402-THICKSTNCL

C4402

9.1UF

20%

4V

CERM

0402-THICKSTNCL

1

2

C4420

0402-THICKSTNCL

1

C4423

C4426

0402-THICKSTNCL

3

1

3

4

4.3UF

20%

4V

CERM

4

2

2.2UF

20%

4V

X6S-CERM

0201

4.3UF

20%

4V

CERM

4

2

U3900

H9M

AB19
AB21
AB23
AB25

AB27
AD19
AD21
AD23
AD25

AF11

AF13

AF15

AF17

AF19

AF21

AF23

AF25

AF27
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27

AK11

3

1

2

3

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

K11

VDD_FIXED

K13

VDD_FIXED

K15

VDD_FIXED

K17

VDD_FIXED

W18

VDD_FIXED_CPU

G22

VDD_FIXED_USB

H23

VDD_FIXED_MIPI

H25

VDD_FIXED_MIPI

H27

VDD_FIXED_MIPI

AB9

VDD_LOW

AD9

VDD_LOW

P9

VDD_LOW

T9

VDD_LOW

V9

VDD_LOW

Y9

VDD_LOW

H11

VDD_FIXED_UP_PCIE_ANA

H13

VDD_FIXED_UP_PCIE_ANA

H15

VDD_FIXED_UP_PCIE_ANA

J15

VDD_FIXED_UP_PCIE_CLK

J11

VDD_FIXED_UP_PCIE_CLK

J13

VDD_FIXED_UP_PCIE_CLK

BGA

SYM 12 OF 18

OMIT_TABLE
CRITICAL

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA

VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK

VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA

VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK

VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA

VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK

VDD_FIXED_DN_PCIE_CLK

VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF

1

C4452

2

1

C4456

2

C4430

4.3UF

20%

4V

CERM

1

4

2

C4435

4.3UF

20%

4V

CERM

1

4

2

C4440

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

4

2

C4445

4.3UF

20%

4V

CERM

1

4

2

2.2UF

20%

4V

X6S-CERM

0201

2.2UF

20%

4V

X6S-CERM

0201

1

2

1

2

C4453

2.2UF

X6S-CERM

C4457

2.2UF

X6S-CERM

20%

4V

0201

20%

4V

0201

1

2

1

2

PP0V9_SLPDDR

C4431

4.3UF

20%

4V

CERM

0402-THICKSTNCL

3

1

2

3

4

PP0V9_SLPDDR

C4436

4.3UF

20%

4V

CERM

0402-THICKSTNCL

3

1

2

3

4

PP0V9_SLPDDR

C4441

4.3UF

20%

4V

CERM

0402-THICKSTNCL

3

3

1

2

PP0V9_SLPDDR_SOC_PCIEREFBUF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

3

4

C2

VDDIO11_DDR0

E1

VDDIO11_DDR0

G1

VDDIO11_DDR0

H8

VDDIO11_DDR0

J9

VDDIO11_DDR0

K8

VDDIO11_DDR0

L9

VDDIO11_DDR0

M8

VDDIO11_DDR0

N9

VDDIO11_DDR0

P1

VDDIO11_DDR0

R1

VDDIO11_DDR0

U1

VDDIO11_DDR0

C36

VDDIO11_DDR1

E37

VDDIO11_DDR1

G37

VDDIO11_DDR1

H30

VDDIO11_DDR1

J29

VDDIO11_DDR1

K30

VDDIO11_DDR1

L29

VDDIO11_DDR1

M30

VDDIO11_DDR1

N29

VDDIO11_DDR1

P37

VDDIO11_DDR1

R37

VDDIO11_DDR1

U37

VDDIO11_DDR1

AB1

VDDIO11_DDR2

AD1

VDDIO11_DDR2

AE1

VDDIO11_DDR2

AF9

VDDIO11_DDR2

AG8

VDDIO11_DDR2

AH9

VDDIO11_DDR2

AJ8

VDDIO11_DDR2

AK9

VDDIO11_DDR2

AL8

VDDIO11_DDR2

AM1

VDDIO11_DDR2

AP1

VDDIO11_DDR2

AT2

VDDIO11_DDR2

AB37

VDDIO11_DDR3

AD30

VDDIO11_DDR3

AD37

VDDIO11_DDR3

AE29

VDDIO11_DDR3

AE37

VDDIO11_DDR3

AF30

VDDIO11_DDR3

AG29

VDDIO11_DDR3

AH30

VDDIO11_DDR3

AJ29

VDDIO11_DDR3

AM37

VDDIO11_DDR3

AP37

VDDIO11_DDR3

AT36

VDDIO11_DDR3

330mA Max

330mA Max

330mA Max

R4445

0

2 1

5%

1/20W

MF

0201

OMIT_TABLE
CRITICAL

U3900

H9M

BGA

SYM 13 OF 18

43 80

43 80

43 80

PP0V9_SLPDDR

3 245

VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR

VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR

G9
G29
AM9
AK30

G4
G34
AM4
AM34

45mA Max

PP1V1_SLPDDR

80

8mA Max

1

C4460

0.22UF 0.22UF

20%

2

6.3V
X6S-CERM
0201

1

C4470

2.2UF

20%

2

4V
X6S-CERM
0201

43 80

1

C4461

20%

2

6.3V
X6S-CERM
0201

1

C4471

2.2UF

20%

2

4V
X6S-CERM
0201

BOM_COST_GROUP=SOC

1

R4460

5.1

1% MF1/20W

21

0201

L4460

120-OHM-25%-0.48A-0.21DCR

21

0201

PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F

1

C4462

0.22UF

20%

2

6.3V
X6S-CERM
0201

1

C4463

0.22UF

20%

2

6.3V
X6S-CERM
0201

PP1V1_SLPS2R

1

C4472

2.2UF

20%

2

4V
X6S-CERM
0201

SYNC_MASTER=H9M and PMIC SYNC_DATE=03/02/2017

PAGE TITLE

1

C4473

2.2UF

20%

2

4V
X6S-CERM
0201

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.1V

Current included in VDD2

80

SoC Power 2

DRAWING NUMBER

051-02643

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

4.0.0

BRANCH

evt-0

PAGE

44 OF 200

SHEET

43 OF 131

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

3 245

1

D

C

B

A

PP1V8_AWAKE

80

40mA Max

PP1V8_SLPS2R

80

1mA Max

PP1V8_SLPS2R

80

1mA Max

80

PP1V8_SLPS2R
20mA Max

C4521

2.2UF

20%

4V

X6S-CERM

0201

80

PP1V8_SLPS2R

80

134mA Max

1

2

C4522

2.2UF

20%

4V

X6S-CERM

0201

PP1V8_AWAKE
2mA Max

PP1V8_AWAKE

80

20mA Max

80

PP1V8_AWAKE
1mA Max

R4546

49.9

1/20W

201

1

2

C4510

21

1%
MF

R4519

49.9

1%

1/20W

MF

201

C4523

2.2UF

X6S-CERM

0201

C4540

C4500

2.2UF

X6S-CERM

0201

21

1

20%

2

4V

0.1UF

6.3V
0201

1

2.2UF

20%

2

4V

X6S-CERM

0201

1

20%

2

4V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.8V

C4501

C4511

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

2

2.2UF

X6S-CERM X6S-CERM

3

4

1

20%

2

4V

0201

0402-THICKSTNCL

C4512

4.3UF

20%

4V

CERM

1

2

PP1V8_SLPS2R_SOC_LPADC_RC
PP1V8_SLPS2R_SOC_LPOSC_RC

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C4524

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

4

2

R4530

0

5%

1/20W

MF

0201

PP1V8_AWAKE

80

3

21

C4525

20%

4V

CERM

0402-THICKSTNCL

4

1UF

20%
16V
CER-X5R
0201

3

1

2

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.8V

PP1V8_AWAKE_SOC_TSADC_RC

1

C4530

2

7mA Max

1

10%
X6S

2

PP1V8_AWAKE_SOC_FMON_RC

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

R4545

49.9

1/20W

1%
MF

201

21

1

C4545

1UF

20%
16V

2

CER-X5R
0201

C4502

2.2UF

20%

0201

3

4

C4519

2.2UF

20%

4V

X6S-CERM

0201

C4526

4.3UF4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

2

C4535

2.2UF

20%

4V

X6S-CERM

0201

1

2

4V

C4513

0.1UF

1

2

3

4

1

2

C4503

2.2UF

X6S-CERM

0201

1

10%

2

6.3V
X6S

0201

C4515

20UF

2.5V

X6S-CERM

0402

C4527

4.3UF

20%

4V

CERM

0402-THICKSTNCL

1

2

C4536

0.1UF

6.3V
0201

20%

4V

20%

4

10%
X6S

D

OMIT_TABLE
CRITICAL

U3900

H9M

A4

VDD1 VDD12_CPU_UVD

AV34

VDD1

1

2

1

2

3

1

2

AV4

B35

W1

W37

Y1

Y37

AA9

P8

R9

T8

U9

W9

AC9
AD8
AE9

AB8

AB10

AA29
AB30
AC29

P30
R29

T30
U29
V30

W29

Y30

G16
G18
G20

H17
H19
H21

AK31

AM31

AL11

AM10

AA18

P16

AD16

AF18

H28

G23
G25
G27

H22

AF12

AM30

AK12

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1

VDDIO18_AOP2
VDDIO18_AOP2
VDDIO18_AOP2

VDD18_LPADC
VDD18_LPOSC

VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1

VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2

VDDIO18_GRP3
VDDIO18_GRP3

VDDIO18_GRP4
VDDIO18_GRP4

VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC

VDD18_MIPI
VDD18_MIPI
VDD18_MIPI

VDD18_USB
VDD18_FMON
VDD18_EFUSE1

VDD18_EFUSE2

BGA

SYM 14 OF 18

VDD12_PLL_CPU

VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF

VDD12_DN_PCIE

VDD12_UP_PCIE

VDD12_STG0_PCIE
VDD12_STG1_PCIE

VDD12_PLL_SOC
VDD12_PLL_SOC
VDD12_PLL_SOC

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

VDD11_XTAL

VDD33_USB

Y18

V18
AK24

AM23

AM29
G14

AM13
AM18

AC23
AD24
AE23

AG1
AG37
AJ1
AJ37
AK1
AK37
AU3
AU34
AU35
AU4
B3
B4
C34
D34
J1
J37
K1
K37
M1
M37
W3
W35
Y3
Y35

AN23

F21

PP1V2_AWAKE

10mA Max

1

C4550

2.2UF

20%

2

4V
X6S-CERM
0201

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

PP1V2_AWAKE_SOC_PLLCPU_F
PP1V2_AWAKE_SOC_PCIEREFBUF_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

PP1V2_AWAKE_SOC_PCIEPLL_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

PP1V2_AWAKE_SOC_PLLSOC_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C4580

1

2.2UF

20%

2

4V
X6S-CERM
0201

PP1V1_SLPDDR_SOC_XTAL_F

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C4581

1

2.2UF

20%

2

4V
X6S-CERM

PP3V3_AWAKE

C4582

1

2

80

12mA Max

1

C4595

0.1UF

10%

2

6.3V
X6S
0201

80

C4560

0.1UF

10%

6.3V
X6S

0201

C4565

2.2UF

20%

4V

X6S-CERM

0201

C4570

0.1UF

10%

6.3V
X6S

0201

2.2UF

20%
4V
X6S-CERM
02010201

C4590

C4555

0.1UF

R4560

5%

1

2

1

2

1

2

0.1UF

10%

6.3V
X6S

0201

1/20W

MF

0201

C4566

2.2UF

X6S-CERM

C4571

0.1UF

PP1V1_SLPS2R

C4583

1

2.2UF

20%

2

4V
X6S-CERM
0201

1%

240-OHM-25%-0.42A-0.31DCR

1

2

R4555

0

5%

1

10%

2

6.3V
X6S

0201

0

21

1

2

1

20%

2

4V

0201

1

10%

2

6.3V
X6S

0201

R4590

5.1

1/20W MF 0201

1/20W

MF

0201

C4561

0.1UF

10%

6.3V
X6S
0201

C4567

2.2UF

X6S-CERM

R4570

0

5%

1/20W

MF

0201

21

L4590

21

0201

21

1

20%

2

4V

0201

21

1.74A Max

1

C4591

2.2UF

20%

2

4V
X6S-CERM
0201

PP1V2_AWAKE

PP1V2_AWAKE

C4562

1

2.2UF

20%

2

4V
X6S-CERM
0201

20%

4V

0201

1

2

C4568

2.2UF

X6S-CERM

PP1V2_AWAKE

1

C4572

2.2UF

20%

2

4V
X6S-CERM
0201

80

PP1V1_SLPDDR

PAGE TITLE

13mA Max

80mA Max

R4565

0

21

5%

1/20W

MF

0201

31mA Max

4mA Max

80

44 80

PP1V2_AWAKE

80

80

60mA Max

44 80

C

B

SYNC_DATE=05/26/2017SYNC_MASTER=SILU

A

SoC Power 3

SIZE

D

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

IV ALL RIGHTS RESERVED

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

45 OF 200

SHEET

44 OF 131

8

67

35 4

2

1

678

3 245

1

D

C

B

A1
A10
A11

A2
A22
A24

A3
A31
A34
A35
A36
A37

A5

A6

A8

AA1
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27

AA3
AA30
AA31
AA35
AA37
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB29
AB31
AB33

AB5

AB7

AC1

AC11
AC13
AC15
AC17
AC19
AC21
AC25
AC27
AC30
AC31
AC35
AC37

AC7

AC8

AD10
AD12
AD14
AD18
AD20
AD22
AD26
AD29

AD3

AD31
AD34

AD7
AE11
AE13
AE15
AE17
AE19
AE21
AE25
AE27
AE30
AE31
AE33

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 15 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE4
AE5
AE7
AE8
AF1
AF10
AF14
AF16
AF20
AF22
AF24
AF26
AF28
AF29
AF3
AF31
AF35
AF37
AF5
AF7
AF8
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG30
AG31
AG5
AG7
AG9
AH1
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH29
AH31
AH33
AH37
AH5
AH7
AH8
AJ11
AJ13
AJ17
AJ19
AJ23
AJ25
AJ3
AJ30
AJ31
AJ35
AJ7
AJ9
AK10
AK14
AK16
AK18
AK20
AK22
AK26
AK28
AK5
AK7
AK8
AL1
AL10
AL13
AL15
AL19
AL2

AL21
AL23
AL25
AL27
AL29
AL31
AL32
AL33
AL36
AL37

AL5
AL7

AL9
AM11
AM12
AM17

AM2
AM22
AM24
AM28
AM32
AM36

AM5

AM6

AM7

AM8

AN1
AN10
AN12
AN14
AN15
AN17
AN19
AN20
AN21
AN24
AN26
AN27
AN29
AN31
AN32
AN37

AN6

AN7

AN8

AN9

AP10
AP15
AP20
AP23
AP24
AP27

AP3
AP32
AP33
AP35

AP5

AP6

AP8

AP9

AR1
AR10
AR11
AR13
AR15
AR16
AR18
AR20
AR22
AR23
AR24
AR25
AR27
AR28
AR30
AR32
AR37

AR6

AR8

AT1
AT10
AT12
AT14
AT15
AT17

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 16 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT19
AT20
AT21
AT23
AT24
AT26
AT27
AT29
AT3
AT31
AT32
AT34
AT35
AT37
AT4
AU1
AU10
AU15
AU2
AU20
AU23
AU24
AU27
AU32
AU33
AU36
AU37
AU6
AU8
AV1
AV10
AV11
AV13
AV15
AV16
AV18
AV2
AV20
AV22
AV25
AV27
AV28
AV3
AV30
AV32
AV33
AV35
AV36
AV37
AV6
B1
B11
B13
B16
B19
B2
B22
B24
B31
B34
B36
B37
B5
B6
C1
C11
C22
C23
C24
C25
C26
C27
C28
C29
C3
C30
C31
C32
C33
C35
C37
C4
C5
C6

C7
C9

D1
D10
D11
D12
D13
D14
D16
D17
D19
D20
D22
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D35
D36
D37

D5

D6

D8

E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E24
E25
E26
E27
E28
E29

E3

E30
E31
E32
E33
E34
E35
E36

E5

E6

F1
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F24
F25
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37

F5

F6

F7

F9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 17 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G10
G15
G17
G19
G2
G21
G24
G26
G28
G30
G31
G32
G33
G36
G6
G7
G8
H1
H10
H12
H14
H16
H18
H2
H20
H24
H26
H29
H31
H33
H36
H37
H5
H7
H9
J17
J19
J21
J23
J25
J27
J30
J31
J7
J8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K29
K3
K31
K33
K35
K5
K7
K9
L1
L11
L13
L15
L17
L19
L21
L23
L25
L27
L30
L31
L37
L7
L8
M10
M12
M14
M16
M18
M20

M22
M24
M26
M28
M29
M31

M7
M9

N1
N11
N13
N15
N19
N21
N23
N25
N27

N3
N30
N31
N33
N35
N37

N5

N7

N8
P10
P12
P14
P18
P20
P22
P24
P26
P28
P29
P31

P5

P7
R11
R13
R15
R17
R19
R21
R23
R25
R27
R30
R31

R7
R8

T1

T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 18 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T3
T31
T33
T35
T37
T5
T7
U11
U13
U15
U17
U19
U21
U23
U25
U27
U30
U31
U7
U8
V1
V10
V12
V14
V16
V20
V22
V24
V26
V28
V29
V3
V31
V35
V37
W11
W13
W15
W17
W19
W2
W21
W23
W25
W27
W30
W31
W33
W36
W5
Y10
Y12
Y14
Y16
Y2
Y20
Y22
Y24
Y26
Y28
Y29
Y31
Y36

D

C

B

A

8

SYNC_DATE=03/02/2017SYNC_MASTER=H9M and PMIC

PAGE TITLE

A

SoC Ground

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

46 OF 200

SHEET

45 OF 131

1

SIZE

D

678

3 245

1

D

38

38

38

40 46

40 46

40 46

47 66

40 47

47 66

Boot Config

OUT
OUT
OUT

BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2

Board ID

OUT
OUT
OUT
OUT
OUT
OUT

SPI_SOCROM_CLK
SPI_SOCROM_MOSI
SPI_SOCROM_MISO
SPI_TPAD_MOSI
SPI_TPAD_MISO
SPI_TPAD_CLK

BOOTCFG0

1

R4700

1K

5%
1/20W
MF
201

2

BOARDID0

1

R4710

3.0K

5%
1/20W
MF
201

2

BOOTCFG1

1

R4701

1K

5%
1/20W
MF
201

2

BOARDID1

1

R4711

3.0K

5%
1/20W
MF
201

2

PP1V8_AWAKE

BOOTCFG2

1

R4702

1K

5%
1/20W
MF
201

2

BOARDID2

1

R4712

3.0K

5%
1/20W
MF
201

2

BOARDID3

1

R4713

3.0K

5%
1/20W
MF
201

2

BOOTCFG2

BOARDID4

1

R4714

3.0K

5%
1/20W
MF
201

2

80 47 46 41

0
0
1
1

BOOTCFG0

0
1

BOOTCFG1

0
1
0
1

PP1V8_AWAKE

BOARDID5

1

R4715

3.0K

5%
1/20W
MF
201

2

Test Mode

Disabled

Enabled

Frequency

40 MHz

6 MHz

24 MHz

Invalid

80

47 46 41

39

PECI Level Shifting

PP1V05_S3

U4750

74AUC1G126

A2

BGA-YZP

C2

Y

CRITICAL

A1

BYPASS=U4750::5MM

PLACE_NEAR=U3900.T6:15MM

C4750

0.1UF

10%
10V

X5R-CERM

0201

B1

A

126

OE

1

C1

2

R4750

21

P3MM

SMC_PECI_TX_RSMC_PECI_TX

C4755

0.1UF

X5R-CERM

10%
10V

0201

40

BYPASS=U4755::5MM

1

1

2

6

VCCBVCCA

U4755

74AVC1T45

A

SOT886

5

DIR

GND

2

43

B

1

C4756

0.1UF

10%
10V

2

X5R-CERM
0201

CPU_PECI

R4755

330

1/20W

5%
MF

201

46

40

1

2

IN

5%01/20W MF 0201

PP1V8_S5

80

BYPASS=U4755::5MM

39

PP4700

OUT

SMC_PECI_RX

1

SM

PP

115

PP1V8_AWAKE

80

SPI_SOCROM_CLK

IN

SPI_SOCROM_CS_L

IN

SPI_SOCROM_WP_L

121

6 13

BI

R4770

100K

5%

1/20W

MF

201

SoC ROM

40
46

40
46

D

BYPASS=U4770::5MM

1

C4770

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_SOCROM_MOSI

IN

10K

5%

1/20W

MF

201

1

8

CRITICAL

VCC

U4770

2

SCLK SI/SIO0

4MX8-1.8V

USON

56

1

2

R4771

MX25U3235F

1

CS*

3

WP*/SIO2

7

RESET*/SIO3

VER 2

GND

4

SO/SIO1

EPAD

10

9

EPAD

2

SPI_SOCROM_MISO_R SPI_SOCROM_MISO

PLACE_NEAR=U4770.2:5MM

R4773

20

21

5% 2011/20WMF

OUT

C

Board Revision

38

OUT

38

OUT

40

OUT

343S00234 CRITICAL1

BOARD_REV0
BOARD_REV1
BOARD_REV2

BOARDREV0

1

R4720

1K

5%
1/20W
MF
201

2

IC,SLG4AP41484,THERMTRIP,STQFN14

BOARDREV1

1

R4721

1K

5%
1/20W
MF
201

2

PP1V8_AWAKE

BOARDREV2

1

R4722

1K

5%
1/20W
MF
201

2

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U4740

80 47 46 41

PP1V8_SLPS2R

80

PCH PM Level Shifting

PP3V3_S5

80

C

BYPASS=U4760::5MM

1

C4765

0.1UF

10%
10V

2

X5R-CERM
0201

1

R4765

100K

5%
1/20W
MF
201

2

1

R4767

100K

5%
1/20W
MF
201

2

1

R4766

5%
1/20W
MF
201

2

1

R4768

100K

5%
1/20W
MF
201

2

PM_SYSRST_R_L

R4769

2.2K

MF1/20W 2015%

21

PM_SYSRST_L
PM_PCH_SYS_PWROK

PM_PCH_PWROK
PM_RSMRST_L

12 18 119 121

OUT

12 119 39 121

12 35 119 121

OUT

12 18 34 112 119

OUT

39 119 121

IN
IN OUT

39 121

IN

39 46

IN

SMC AVREF Supply

Footprint supports 353S01042 alternate

SMC_SYSRST_L
SMC_PCH_SYS_PWROK

SMC_PCH_PWROK
SMC_RSMRST_L

R4760

100K

5%

1/20W

MF

201

2

1

R4761

100K

5%

1/20W

MF

201

2

1

BYPASS=U4760::5MM

10%
10V

0201

1

2

1

2

6

1A1

8

2A1

4

1DIR

1

1OE*

7

1A2

9

2A2

5

2DIR

16

2OE*

C4760

0.1UF

X5R-CERM

5%

1/20W

MF

201

1

2

R4763

100K

5%

1/20W

MF

201

R4762

100K 100K

3

U4760

SN74AVC4T245RSV

CRITICAL

PQFP

GND

10

2

11

VCCBVCCA

15

1B1

13

2B1

14

1B2

12

2B2

B

A

SEP EEPROM

(Write: 0xA2, Read 0xA3)

PP1V8_AWAKE

80

38

R4730

2.2K

1/20W

I2C_SEP_SCL

5%
MF

201

1

2

No Pull-up or TP on SDA in POR

BYPASS=U4730::3MM

1

C4730

0.1UF

10%
10V

2

X5R-CERM
0201

VCCVSS

U4730

M34128-FCS6_P/T

SCL

WLCSP

SDA

A2B1

I2C_SEP_SDA

CRITICAL

B2 A1

Qualifier with RSMRST#

115 46 11 8 6

39 46

77 119

SMC_RSMRST_L

IN

ALL_SYS_PWRGD

IN

PP1V05_S3

R4718

0

NO STUFF

R4719

5%

0

1/20W

MF1/20W 02015%

MF

21

21

0201

C4710

0.1UF

CERM-X5R

ALL_SYS_PWRGD_R

NC

10%

6.3V
0201

1

2

2

A Y

1

B

5

NC

6

VCC

GND

3

U4710

74AUP1G08GF

SOT891

4

CPU_VCCST_PWRGD

CRITICAL

PP1V8_SLPS2R

80

1

R4731

2.2K

5%
1/20W
MF
201

2

BIIN

47 103

95 117 119

38

BYPASS=U4780::3MM BYPASS=U4780::3MM

GPU_GFX_OVERTEMP

IN

GPU_RESET_L

IN

8

OUT

80

C4780

1.0UF

20%

6.3V
X5R

0201-1

U4780

REF3312AIRSE

UQFN-COMBO

5

IN

OUT

8

CRITICAL

1

NC0

1

2

GND

4

NC1

NC2

NC3
NC4

NC

2

NC

3

NC

6

NC

7

NC

PP1V25_SLPS2R_SMC_AVREF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.25V

1

C4781

1.0UF

20%

6.3V

2

X5R
0201-1

GND_SMC_AVSS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

39 53 54 56 58

39

PROCHOT Isolation

PP1V8_S5

80

CRITICAL

1

R4790

10K

5%
1/20W
MF
201

2

39 47 69

SMC_PROCHOT_L CPU_PROCHOT_OUT_L

NC

DFN1010-THICKSTNCL

2

A

1

6

VCC

U4790

74LVC1G07FW5

GND

3

BYPASS=U4790::5MM

C4790

0.1UF

10%

6.3V

CERM-X5R

0201

4

Y

5

NCNC

NC

1

2

R4791

75

21

1/20W 201

5% MF

CPU_PROCHOT_L

OUTIN

B

6

THRMTRIP# Isolation

PP1V8_S5

15K

5%1/20W MF

R4740

21

201

15K

5%201 1/20WMF

R4741

21

R4742

18K

1%

1/20W

MF

201

1

R4743

2

18K

1%

1/20W

MF

201

80

BYPASS=U4740::5MM

C4740

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

1

VDD

U4740

SOC_PM_THRMTRIP_L_R

115 46 11 8 6

PP1V05_S3

SLG4AP41484

STQFN

NC
NC
NC

135
8

PCH_PMTHRMTRIP_L_R

12

SOC_GPU_THRMTRIP

10

SMC_GPU_THRMTRIP

11

CPU_SMC_THRMTRIP_L

6
7
14

NC
NC
NC

6 119

12 20 119

1

2

PM_THRMTRIP_L

IN

GPU_GFX_OVERTEMP_R

GPU_RESET_L_R

PLT_RST_L

IN

CPU_THERMTRIP*_IN

2

GPU_THERMTRIP_IN

3

GPU_RESET*_IN

4

PLT_RST*

OMIT_TABLE

GND

9

CPU_THERMTRIP*_TO_CALPE

THERMTRIP*_TO_PCH

GPU_THERMTRIP_TO_CALPE

GPU_THERMTRIP_TO_H9M

CPU_THERMTRIP*_TO_H9M

R4744

15K

5% 2011/20W MF

R4745

OUT

OUT

OUT

BOM_COST_GROUP=SOC

5%002011/20W MF

77

47

39

21

SOC_PM_THRMTRIP_L

1

R4747

1K

1%
1/16W
MF-LF
402

2

21

PCH_PMTHRMTRIP_L

SYNC_MASTER=SILU

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

77

OUT

1

R4746

22K

5%

1/20W

MF

201

2

13

OUT

SoC Shared Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SYNC_DATE=08/09/2017

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

47 OF 200

SHEET

46 OF 131

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

118 14

118 14

118 14

118 14

118 14

118 14

118 14

PCIe Up R2D AC Caps

IN
IN

IN
IN

IN
IN

IN

PCIE_SOC_R2D_C_P<0>
PCIE_SOC_R2D_C_N<0>

PCIE_SOC_R2D_C_P<1>
PCIE_SOC_R2D_C_N<1>

PCIE_SOC_R2D_C_P<2>
PCIE_SOC_R2D_C_N<2>

PCIE_SOC_R2D_C_P<3>
PCIE_SOC_R2D_C_N<3>

C4820
C4821

C4822
C4823

C4824
C4825

C4826
C4827

(All Caps)

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

0.22UF

GND_VOID=TRUE

21

20% 6.3V X5R

21

GND_VOID=TRUE

21

GND_VOID=TRUE

21

GND_VOID=TRUE

20%

21

GND_VOID=TRUE

21

GND_VOID=TRUE

21

20% 6.3V 0201X5R

GND_VOID=TRUEGND_VOID=TRUE

21

20% 02016.3V

0201

02016.3V20%

X5R

X5R20% 6.3V 0201

X5R 02016.3V

0201X5R6.3V20%

020120%

X5R6.3V

X5R

PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUTIN

GPIO Source Termination

40

IN

40

IN

62

IN OUT

40

IN OUT

40

IN

63

IN OUT

40

IN

40

IN

61

IN OUT

40 66 46

IN OUT

40

IN

40

IN

40

IN

120 50 40

46 40 66

OUT IN

40

IN

40

IN

41

IN

41

IN

39

IN

39

IN

39

IN

39

IN

37 39

OUT IN

OUT IN

I2S_SPKRAMP_L_R2D_R
I2S_SPKRAMP_L_BCLK_R
I2S_SPKRAMP_L_LRCLK_R
I2S_SPKRAMP_R_R2D_R
I2S_SPKRAMP_R_BCLK_R
I2S_SPKRAMP_R_LRCLK_R
I2S_CODEC_R2D_R
I2S_CODEC_BCLK_R
I2S_CODEC_LRCLK_R
SPI_TPAD_MOSI_R
SPI_TPAD_CLK_R
SPI_MESA_MOSI_R
SPI_MESA_CLK_R
SPI_DFR_MISO_R
SPI_DFR_MOSI_R
SPI_DFR_CLK_R

SSD0_CLK24M_R
SSD1_CLK24M_R

PDM_DMIC_CLK0_R
PDM_DMIC_CLK1_R

SPI_AOP_SENSOR_MOSI_R
SPI_AOP_SENSOR_CLK_R

PLACE_NEAR=U3900.AG34:5MM

PLACE_NEAR=U3900.AA32:5MM

PLACE_NEAR=U3900.AA32:10MM

PLACE_NEAR=U3900.C20:5MM

PLACE_NEAR=U3900.C21:5MM

PLACE_NEAR=U3900.C21:10MM

PLACE_NEAR=U3900.AB34:5MM

PLACE_NEAR=U3900.AF33:5MM

PLACE_NEAR=U3900.AF33:5MM

PLACE_NEAR=U3900.N34:5MM

PLACE_NEAR=U3900.P35:5MM

PLACE_NEAR=U3900.A20:5MM

PLACE_NEAR=U3900.C19:5MM

PLACE_NEAR=J5100.7:5MM

PLACE_NEAR=U3900.C18:5MM

PLACE_NEAR=U3900.B18:5MM

PLACE_NEAR=U3900.AP7:5MM

PLACE_NEAR=U3900.AV7:5MM

PLACE_NEAR=U3900.P6:15MM

PLACE_NEAR=U3900.K2:15MM

PLACE_NEAR=U3900.D2:10MM

PLACE_NEAR=U3900.F2:15MM

SPI_AOP_SENSOR_MISO_R

PLACE_NEAR=U3900.E2:5MM

SPI_TPAD_MISO

PLACE_NEAR=U3900.P36:20MM

R4843
R4844
R4863
R4845
R4846
R4864
R4847
R4848
R4865
R4851
R4852
R4853
R4854
R4866
R4855
R4856

R4857
R4858

R4859
R4860

R4861
R4862

R4869
R4809

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

20
20

20
20

20
20
20

20

21

I2S_SPKRAMP_L_R2D

5% 2011/20W

I2S_SPKRAMP_L_BCLK

21

I2S_SPKRAMP_L_LRCLK

21

I2S_SPKRAMP_R_R2D

21

5% MF

1/20W 201

I2S_SPKRAMP_R_BCLK

21

5%

21

I2S_SPKRAMP_R_LRCLK

1/20W5%

21

I2S_CODEC_R2D
I2S_CODEC_BCLK

21

5% 1/20W MF 201

21

I2S_CODEC_LRCLK

5% MF1/20W 201

SPI_TPAD_MOSI

21

5%

21

SPI_TPAD_CLK

5% 201

21

SPI_MESA_MOSI

21

SPI_MESA_CLK

1/20W

21

SPI_DFR_MISO

1/20W5%

SPI_DFR_MOSI

21

5%

SPI_DFR_CLK

21

21

21

21

21

21

21

21

21

1/20W

5% MF 201

SSD0_CLK24M

5% MF 2011/20W

SSD1_CLK24M

5% 1/20W 201MF

PDM_DMIC_CLK0

5% MF1/20W 201

PDM_DMIC_CLK1

5% 1/20W MF 201

SPI_AOP_SENSOR_MOSI

5% 2011/20W

SPI_AOP_SENSOR_CLK

5% 1/20W 201MF

SPI_AOP_SENSOR_MISO

SPI_TPAD_MISO_R

1/20W MF5% 201

MF

MF 201

MF1/20W5% 201

MF1/20W

MF

MF5%

MF 201

MF

MF1/20W5%

201MF5% 1/20W

2011/20W5% MF

201MF1/20W

2011/20W MF

2015% 1/20W

201

201MF1/20W

S4E_X4PLUS

201

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

62

62

40

63

63

40

61

61

40

48

48

64

64

37

37

Lifeboat

PCIE_LIFEBOAT_R2D_C_P

41

PCIE_LIFEBOAT_R2D_C_N

41

PCIE_LIFEBOAT_D2R_P

41

PCIE_LIFEBOAT_D2R_N

41

PCIE_CLK100M_LIFEBOAT_P

41

PCIE_CLK100M_LIFEBOAT_N

41

PCIE_LIFEBOAT_CLKREQ_L

41

PCIE_LIFEBOAT_RESET_L

41

SMC_FIXTURE_MODE_L

39 119

MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE

MAKE_BASE

PCIE_LIFEBOAT_R2D_C_P
PCIE_LIFEBOAT_R2D_C_N
PCIE_LIFEBOAT_D2R_P
PCIE_LIFEBOAT_D2R_N
PCIE_CLK100M_LIFEBOAT_P
PCIE_CLK100M_LIFEBOAT_N
PCIE_LIFEBOAT_CLKREQ_L
PCIE_LIFEBOAT_RESET_L

SMC_FIXTURE_MODE_L

FIXMODE_NO

1

R4801

100K

5%
1/20W
MF
201

2

TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

TP4800
TP4801
TP4802
TP4803
TP4804
TP4805
TP4806
TP4807

PP1V8_SLPS2R

47 80

Clamshell Open = High
Clamshell Closed = Low

118 41

118 41

118 41

118 41

118 41

118 41

118 41

118 41 118 14

NC_SPI_ALTIMETER_CS_L

39

NC_ALTIMETER_INT

39

NC_PMU_CLK32K_GNSS_R

77

NC_UART_GNSS_D2R_CTS_L

40

NC_UART_GNSS_R2D_RTS_L

40

NC_GNSS_HOST_TIME

66 46

120 50

120 50

85 83 47

90 88 47

42

77 42

87 86 85 84 83

92 91 90 89 88

126 39

126 39 29

OUT
BI BI

SSD0_OCARINA_WP_L

69 46 39

SWD_SOC_SWCLK
SWD_SOC_SWDIO

38

NC_GNSS_HOST_WAKE

39

NC_GNSS_DEV_WAKE

38

NC_ENET_MEDIA_SENSE

39

NC_ENET_LOW_PWR

39

NC_I2S_HAWKING_D2R

40

NC_I2S_HAWKING_LRCLK

40

NC_I2S_HAWKING_BCLK

40

NC_I2S_CODEC1_R2D_R

40

NC_PLCAM_RX_CLK12M_R

40

NC_PLCAM_RX_RESET_L

40

NC_PLCAM_TX_CLK12M_R

40

NC_PLCAM_TX_RESET_L

40

NC_PLCAM_TX_INT

40

NC_PLCAM_TX_THROTTLE

38

NC_PLCAM_PROX_INT_L

39

NC_PLCAM_ROMEO_B2B_DETECT

39

NC_PCHROM_SW_EN

40

NC_SDCONN_STATE_CHANGE_L

39

NC_FTCAM_RESET_L

40

NC_FTCAM_CLK12M_R

40

NC_I2S_CODEC_MCLK

40

40

NC_I2S_CODEC1_MCLK

39

NC_SPI_DSCRPTR_OVERRIDE_L
NC_I2C_AOP_SCL

39

NC_I2C_AOP_SDA

39

38

NC_SOC_USB_ID
NC_SOC_TST_CLKOUT

38

NC_SOC_AMUXOUT

38

SOC_VDDSOC_SENSE
SOC_VDDCPU_SENSE

SSD1_OCARINA_WP_L

SMC_PROCHOT_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE

P3MM

P3MM

P5MM-SP

P5MM-SP

P3MM

1

SM

PP

1

SM

PP

1

SM-SP

SM-SP

SM

PP

1

PP

1

PP

SWD_SOC_SWCLK
SWD_SOC_SWDIO

OMIT_TABLE

J4800

AMR-MLB-X502

SM

8
7
6
5 4

PP1V8_SLPS2R

47 80

1
2
3

OMIT_TABLE

J4801

AMR-MLB-X502

SM

8
7
6
5 4

1
2
3

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PP4800
PP4801
PP4802
PP4803
PP4808

AMR_PU

1

R4807

330K

5%
1/20W
MF
201

2

SMC_LID_LEFT
PP1V8_SLPS2R

AMR_PU

1

R4808

330K

5%
1/20W
MF
201

2

SMC_LID_RIGHT

PP1V8_SLPS2R

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1

IN

INT PU SOC 50k

Lid Detect Sensors

R4804

47 80

47 80

NC_SPI_ALTIMETER_CS_L
NC_ALTIMETER_INT

NC_PMU_CLK32K_GNSS_R
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L

NC_GNSS_HOST_TIME
NC_GNSS_HOST_WAKE

NC_GNSS_DEV_WAKE
NC_ENET_MEDIA_SENSE
NC_ENET_LOW_PWR
NC_I2S_HAWKING_D2R
NC_I2S_HAWKING_LRCLK
NC_I2S_HAWKING_BCLK
NC_I2S_CODEC1_R2D_R

NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_INT
NC_PLCAM_TX_THROTTLE
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT
NC_PCHROM_SW_EN
NC_SDCONN_STATE_CHANGE_L

NC_FTCAM_RESET_L
NC_FTCAM_CLK12M_R
NC_I2S_CODEC_MCLK
NC_I2S_CODEC1_MCLK
NC_SPI_DSCRPTR_OVERRIDE_L
NC_I2C_AOP_SCL
NC_I2C_AOP_SDA

NC_SOC_USB_ID
NC_SOC_TST_CLKOUT
NC_SOC_AMUXOUT

29

10K

1/20W

21

5%
MF

201

R4805

10K

21

5%

1/20W

MF

201

PP1V8_SLPS2R

47 80

BYPASS=U4802::5MM

No Connects

NC_SPKR_ID1

40

NC_SMC_LED_ONEWIRE

39

NC_PCIEDN_WAKE_L

39

NC_MESA_MENUKEY_L

39

NC_TPAD_VIBE_L

39

NC_ENET_RESET_L

41

NC_WLAN_DEV_WAKE

38

NC_SOC_VSSCPU_SENSE

42

NC_SOC_VSSSOC_SENSE

42

NC_DFR_TOUCH_RSVD

40

NC_PCIE_DN3_R2D_CP

41

NC_PCIE_DN3_R2D_CN

41

NC_PCIE_DN3_D2RP

41

NC_PCIE_DN3_D2RN

41

NC_PCIE_CLK100M_DN3P

41

NC_PCIE_CLK100M_DN3N

41

NC_PCIEDN3_CLKREQ_L

41

NC_PCIEDN3_RESET_L

41

NC_PCIE_WLAN_R2D_C_P

41

NC_PCIE_WLAN_R2D_C_N

41

NC_PCIE_WLAN_D2R_P

41

NC_PCIE_WLAN_D2R_N

41

NC_WLAN_CLKREQ_L

41

NC_WLAN_PERST_L

41

NC_PCIE_ENET_R2D_C_P

41

NC_PCIE_ENET_R2D_C_N

41

NC_PCIE_ENET_D2R_P

41

NC_PCIE_ENET_D2R_N

41

NC_PCIE_CLK100M_ENET_P

41

NC_PCIE_CLK100M_ENET_N

41

NC_PCIE_CLK100M_WLAN_P

41

NC_PCIE_CLK100M_WLAN_N

41

Signal Aliases

TPAD_KBD_WAKE_L

39

TPAD_SPI_INT_L

39

TPAD_ACTUATOR_DISABLE_L

39

GPU_GFX_OVERTEMP

126 119 39

126 119 39

SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX

SMC_GPU_THRMTRIP

39

GND

40

GND

40

GND

40

GND

40

GND

40

GND

40

GND

40

GND

40

C4802

0.1UF

10%

6.3V

CERM-X5R

0201

LID_OPEN_LEFT
LID_OPEN_LEFT

MAKE_BASE

120 64

OUT

39

D

1

2

2

1

NC

NC

U4802

74LVC1G32

6

SOT891

4

5 3

LID_OPEN_RIGHT
LID_OPEN_RIGHT

MAKE_BASE

IPD_LID_OPEN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

120 64

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE

OUT

OUT

120 65 50

39

NC_SPKR_ID1
NC_SMC_LED_ONEWIRE
NC_PCIEDN_WAKE_L
NC_MESA_MENUKEY_L
NC_TPAD_VIBE_L
NC_ENET_RESET_L
NC_WLAN_DEV_WAKE
NC_SOC_VSSCPU_SENSE
NC_SOC_VSSSOC_SENSE
NC_DFR_TOUCH_RSVD
NC_PCIE_DN3_R2D_CP
NC_PCIE_DN3_R2D_CN
NC_PCIE_DN3_D2RP
NC_PCIE_DN3_D2RN
NC_PCIE_CLK100M_DN3P
NC_PCIE_CLK100M_DN3N
NC_PCIEDN3_CLKREQ_L
NC_PCIEDN3_RESET_L
NC_PCIE_WLAN_R2D_C_P
NC_PCIE_WLAN_R2D_C_N
NC_PCIE_WLAN_D2R_P
NC_PCIE_WLAN_D2R_N
NC_WLAN_CLKREQ_L
NC_WLAN_PERST_L
NC_PCIE_ENET_R2D_C_P
NC_PCIE_ENET_R2D_C_N
NC_PCIE_ENET_D2R_P
NC_PCIE_ENET_D2R_N
NC_PCIE_CLK100M_ENET_P
NC_PCIE_CLK100M_ENET_N
NC_PCIE_CLK100M_WLAN_P
NC_PCIE_CLK100M_WLAN_N

TPAD_KBD_WAKE_L
TPAD_SPI_INT_L
TPAD_ACTUATOR_DISABLE_L
GPU_GFX_OVERTEMP

SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX

SMC_GPU_THRMTRIP

C

B

120 66 65

66

66

103 46

107 108

107 108

46

A

S4E_X4PLUS
S4E_X4PLUS
S4E_X4PLUS
S4E_X4PLUS

S4E_X4PLUS
S4E_X4PLUS

PP1V8_SLPS2R
PP1V8_AWAKE

R4883
R4884
R4887
R4888
R4889
R4890
R4891
R4892
R4895
R4885

100K
100K

R4886
R4893

100K

R4894
R4870

47K
47K
47K
47K
47K
47K
47K
47K

47K

47K

0

38 80

41 46 80

21
21
21
21
21
21
21
21
21
21
21
21
21

21

1/20W5% 201MF
1/20W5%
1/20W5% MF
1/20W5% MF 201

5% 201MF

1/20W

5% MF 2011/20W

1/20W5%

5% MF1/20W
5% MF1/20W

201MF
201

MF 2015% 1/20W
MF5% 2011/20W

MF 201
MF1/20W5%

201
201MF5% 1/20W
2011/20W MF5%
201

0201

SSD0_CLKREQ0_L
SSD0_CLKREQ1_L
SSD0_CLKREQ2_L
SSD0_CLKREQ3_L
SSD1_CLKREQ0_L
SSD1_CLKREQ1_L
SSD1_CLKREQ2_L
SSD1_CLKREQ3_L
SSD_PMU_RESET_L
SSD0_PCIE_RESET_L
SSD0_CLK24M
SSD1_PCIE_RESET_L
SSD1_CLK24M
I2S_SPKRAMP_R_D2R

40

77 68

82 40

----------

83 41

84 41

121 85 41

121 86 41

88 41

89 41

90 41

91 41

119 92 87 38

86 85 84 83 41

85 83 47

91 90 89 88 41

90 88 47

---------­Proto 0

---------­Proto 1

---------­Proto 2

---------­Pre-EVT

---------­EVT

---------­DVT

---------­PVT

----------

----------

-----------------------------

BOM GROUP BOM OPTIONS

BOARDREV2,BOARDREV1,BOARDREV0BOARD_REV:111

BOARDREV2,BOARDREV1BOARD_REV:110
BOARDREV2,BOARDREV0BOARD_REV:101

BOARDREV2BOARD_REV:100
BOARD_REV:011 BOARDREV1,BOARDREV0
BOARD_REV:010 BOARDREV1

BOARDREV0BOARD_REV:001
BOARD_REV:000

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

82 40

82 40

82 40

IN

IN
IN
IN
IN

BOM_COST_GROUP=SOC

CHGR_INT_L

MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N

SYNC_MASTER=SILU SYNC_DATE=07/27/2017

PAGE TITLE

PLACE_SIDE=BOTTOM

PLACE_NEAR=U3900.B27:10MM
PLACE_NEAR=U3900.A26:10MM
PLACE_NEAR=U3900.B26:10MM
PLACE_NEAR=U3900.A26:10MM

SM

SM
SM
SM
SM

P2MM

P2MM
P2MM
P2MM
P2MM

SoC Project Support

DRAWING NUMBER

051-02643

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

1

PP

PP4809

1

PP

PP4804

1

PP

PP4805

1

PP

PP4806

1

PP

PP4807

4.0.0

evt-0
48 OF 200
47 OF 131

A

SIZE

D

8

67

35 4

2

1

MOJAVE 16V BOOST

678

3 245

1

ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE

D

PP3V3_G3H_T

48 116

1

2

C4910

10UF

20%

6.3V
CERM-X5R
0402-9

MIN_LINE_WIDTH=0.2000

L4901

MIN_NECK_WIDTH=0.1200

1.0UH-0.4A-0.636OHM

21

PP3V3_G3H_MESA_SW

0402

DIDT=TRUE
VOLTAGE=3.3V

MESA_BOOST_EN

48

B1
A2
B2

A3
C2

SW

VIN
EN_M

EN_S
LDOIN

U4900

LM3638

BGA

PGND

AGND

A1

B3

VOUT

PMID

C3

C1

PP16V0_MESA

VOLTAGE=17V

PP17V0_MOJAVE_LDOIN

1

C4923

2.2UF

20%
25V

2

X5R
0402-3

1

C4924

2.2UF

20%
25V

2

X5R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=16V

1

C4925

2.2UF

20%
25V

2

X5R
0402-30402-3

1

C4926

56PF

5%
25V

2

NP0-C0G
0201

EDP:12.5mA

48

47

47

48 40

IN

IN

OUT

SPI_MESA_MISO

R4950

0

21

5%

1/20W

MF

0201

R4951

56

21

5%

1/20W

MF

201

R4912

0

21

5%

1/20W

MF

0201

PLACE_NEAR=J4900:3MM

SPI_MESA_MOSI_CONNSPI_MESA_MOSI

1

C4950

56PF

5%
25V

2

NP0-C0G
0201

SPI_MESA_CLK_CONNSPI_MESA_CLK

1

C4951

56PF

5%
25V

2

NP0-C0G
0201

SPI_MESA_MISO_CONN

1

C4952

56PF

5%
25V

2

NP0-C0G
0201

120 48

120 48

131 77 67

120 48

38

OUT

MESA_INT

OUT

MESA_BOOST_EN

PMU_ONOFF_L

R4953

680

5%

1/20W

MF

201

R4954

680

5%

1/20W

MF

201

R4911

0

5%

1/20W

MF

0201

21

MESA_INT_CONN

1

C4953

100PF

5%
25V

2

C0G
0201

21

MESA_BOOST_EN_CONN

1

C4954

100PF

5%
25V

2

C0G
0201

21

PMU_ONOFF_R_L

1

C4955

100PF

5%
25V

2

C0G
0201

120 48

D

120 48 48

119 48

C

3.0V MESA

Option to feed LDO from 5V in case of dropout issue

PP3V3_G3H_T

48 116

1

C4911

1UF

10%
10V

2

X5R-CERM
0402

PP1V8_MESA

48

FL4900

80-OHM-25%-500MA

PP16V0_MESA

48

21

0201

PP16V0_MESA_CONN

VOLTAGE=16V
MIN_NECK_WIDTH=0.1200

1

C4927

100PF

5%
25V

2

C0G
0201

MIN_LINE_WIDTH=0.2000

120 48

MESA FLEX CONNECTOR

Proto1 Connector for X434/X435 Support

PLUG (516S00115) - X434/ X435 Jumper

C

Recptacle (516S00203) - X362/X363 MLB

120 48

PP3V0_MESA_CONN

U4910

NCP160AMX300

4

IN

3

EN

XDFN-COMBO-THICKSTNCL

EPADGND

5

2

OUT

1

PP3V0_MESA

1

C4916

1UF

10%
10V

2

X5R-CERM
0402

EDP:100mA

48

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.0V

120 48

48 120

48 120

SPI_MESA_MISO_CONN
MESA_INT_CONN
MESA_BOOST_EN_CONN

NC

NC

J4900

505066-1222

F-ST-SM1

14 13

2 1
4 3
6 5

8 7
10 9
12 11

PP1V8_MESA_CONN

SPI_MESA_MOSI_CONN
PMU_ONOFF_R_L
SPI_MESA_CLK_CONN
PP16V0_MESA_CONN

48
120

B

1.8V MESA

48 116

PP3V3_G3H_T

1

C4912

2

1UF

10%
10V
X5R-CERM
0402

48 38

MESA_PWR_EN

IN

U4920

LP5907SNX-1.825

X2SON-COMBO-THICKSTNCL

VIN

3

EN

PP3V0_MESA

48

1

C4920

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C4921

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C4922

2.2UF

20%

6.3V

2

X5R-CERM
0201

FL4910

80-OHM-25%-500MA

21

0201

C4928

0.1UF

10%
10V

X6S-CERM

0201

PP3V0_MESA_CONN

1

C4929

100PF

2

0201

5%
25V
C0G

1

2

120 48

VOLTAGE=3.0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

Mesa Power Sequencing Requirements

16 15

Power On: 1V8 -> 3V3 -> 16V0

B

VOUT

EPADGND

5

2

14

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

PP1V8_MESA

1

C4914

1UF

10%
10V

2

X5R-CERM
0402

48

EDP:1.5mA

PP1V8_G3S

116

A

FL4920

80-OHM-25%-500MA

PP1V8_MESA PP1V8_MESA_CONN

48 120 48

0201

1

C4918

2.2UF

20%

6.3V

2

X5R-CERM
0201

21

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1200

1

C4917

100PF

5%
25V

2

C0G
0201

MIN_LINE_WIDTH=0.2000

R4922

PP1V8_MESA

R4924
R4923

BOM_COST_GROUP=T151

100K

100K

100K

21

5% 2011/20W MF

48

21

5% 2011/20W MF

21

5% 2011/20W MF

SYNC_MASTER=SILU SYNC_DATE=05/26/2017

PAGE TITLE

MESA_PWR_EN

SPI_MESA_MISO

MESA_BOOST_EN

48 38

48 40

48

MESA

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

evt-0

PAGE

49 OF 200

SHEET

48 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

PP3V3_G3S_T

116

BYPASS=U5005::3MM
BYPASS=U5005::3MM

C5014

4.7UF

20%
25V
X5R

0402

D

STOCKHOLM 2017

PP4V7_SE_TVDD

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

C5019

4.7UF

2

20%
25V
X5R

0402

1

PP1V8_G3S

2

49 116

BYPASS=U5005::3MM

C5018

1.0UF

20%

6.3V
X5R

0201-1

1

NCNC

2

C7

VDD

E8

A7

A4

VBAT

SIM_PMU_VCC_2

SIM_PMU_VCC_1

D2

PVDD

H3

VUP

G7

TVDD

D7

AVDD

C5

B8

SVDD

ESE_VDD

G1

GPIOVDD

A8

A5

SIM_VCC1

PP1V8_SE_AVDD

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V8_SE_ESE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SIM_VCC2

4UF

20%

6.3V
0201

1

2

C5016

CER-X5R

1

C5015

0.47UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U5005::3MM

C5017

4UF

20%

6.3V

CER-X5R

0201

1

2

C5025

2.2UF

X5R-CERM

BYPASS=U5005::3MM
BYPASS=U5005::3MM

20%

6.3V
0201

1

2

BYPASS=U5005::3MM

C

49 38

49 40

49 40

49 40

49 40

77

IN

IN
OUT
IN
OUT

IN

SE_CTLR_FW_DWLD

UART_SE_R2D
UART_SE_D2R
UART_SE_R2D_RTS_L
UART_SE_D2R_CTS_L

SE_PWR_EN

NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

E3

IRQ

D3

DWL

B1

CLK_REQ

C8

NFC_CLK_XTAL1

E1

UART_RX

D1

UART_TX

E2

UART_CTS

C3

UART_RTS

H1

VEN

B5

IC0

C4

IC1

D5

IC2

E4

IC3

E6

IC4

F4

IC5

F5

IC6

F6

IC7

F8

IC8

G4

IC9

B3

IC10

B6

IC11

D6

IC12

E7

IC13

F7

IC14

U5005

PN80VEU3-C004B011

UFLGA

OMIT_TABLE

SIM_SWIO_1

SIM_SWIO_2

ESE_GPIO

TX_PWR_REQ_P

ESE_DWPM_DBG

ESE_DWPS_DBG

RX+

RX-

TX1

TX2

WKUP_REQ

VMID

NFC_GPIO0
NFC_GPIO1
NFC_GPIO2
NFC_GPIO3
NFC_GPIO4
NFC_GPIO5
NFC_GPIO6

XTAL2

A3
A6

E5
A2
B7

D4
H5

H6
G8

H7
A1
H4
C2

B2
F3
F2
H2
G2
F1

D8

NC
NC

NC
NC
NC

NC
NC

NC
NC

NC

SE_DEV_WAKE
PP0V9_SE_VMID

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

NC
NC
NC
NC
NC
NC
NC

NC

IN

49 38

BYPASS=U5005::3MM

1

C5026

0.1UF

10%

6.3V

2

CERM-X5R
0201

C

B

AVSS

G5

G3

AVSS

AVSS

G6

DVSS

C6

TVSS

H8

C1

B4

ESE_VSS

PVSS

B

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 SE:DEV_2017U5005 CRITICAL998-11132

IC,RTM4,ES2.1,PN80V,DEV,UFLGA64

IC,RTM4,ES2.1,PN80V,PRD,UFLGA64

U5005 SE:PROD_20171338S00253

CRITICAL

A

PP1V8_G3S

R5001
R5002
R5003
R5004
R5000
R5006

8

100K
100K
100K
100K
100K
100K

49 116

21

5% MF 2011/20W

21

5% MF 2011/20W

21

5% MF1/20W 201

21

5% MF1/20W 201

21
21

5% 2011/20W MF

MF1/20W 2015%

UART_SE_R2D
UART_SE_D2R
UART_SE_R2D_RTS_L
UART_SE_D2R_CTS_L
SE_CTLR_FW_DWLD
SE_DEV_WAKE

SYNC_MASTER=SILU SYNC_DATE=05/05/2017

PAGE TITLE

A

Secure Element

49 40

49 40

49 40

49 40

49 38

49 38

BOM_COST_GROUP=T151

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

50 OF 200

SHEET

49 OF 131

1

SIZE

D

678

3 245

1

T208 Support

D

C

120 65 47

IPD_LID_OPEN

PP5V_G3S

116

R5102

100K

2 1

5%

1/20W

MF

201

IPD_LID_OPEN_R

L5199

1.2UH-20%-0.12A-1.17OHM

21

0402

1

G

120 50

120 40

120 47

120 50 40

120 52 50

C5100

4.7UF

20%
25V
X5R

0402

PP1V8_SLPS2RSW_DFR

2

S

Q5100

DMP31D0UFB4

DFN1006H4-3

D

3

DFR_LID_OPEN_L
TP_DFR_TOUCH_RSVD

SPI_DFR_CS_L

IN

SPI_DFR_MOSI

IN

I2C_DFR_SCL_R

52 120

I2C_DFR_SDA_R

52 120

DFR_TOUCH_RESET_L

IN

PP1V8_SLPS2RSW_DFR

120

PP5V_G3S_DFR_FILT

VOLTAGE=5V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

1

2

C5101

4.7UF

20%
25V
X5R

0402

120 52 50

DFR Touch Conn

J5100

AA07-S022VA1

F-ST-SM

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21

1

2

24
23

25
26

TP_DFR_TOUCH_PANEL_DETECT
DFR_DISP_VSYNC

SPI_DFR_MISO_R
SPI_DFR_CLK

DFR_TOUCH_INT_L
DFR_TOUCH_CLK32K_RESET_L

TP_DFR_TOUCH_ROM_WC
PP1V8_SLPS2RSW_DFR

120

OUT

OUT

120

D

120 50

120 50 47

120 47

IN

120 50 39

120 40

IN

120 52 50

C

B

50 116

120 52 50

PP3V3_G3H_DFR

P1V8_SLPS2RSW_DFR_R

PP1V8_SLPS2RSW_DFR

Slew Rate

R(on)
@ 3.3V

Current

Load Cap

R5112

24K

1/20W

2.5V/ms

43 mOhm Typ
55 mOhm Max

1A Max

22.2uF nom

5%
MF

201

21

U5111

SLG5AP1449V

STDFN

1

ON

GND

DFR Disp Conn

J5110

DF40SG(1.5)-26DS-0.4V

120 50

120 40

120 38

120 40

2

D

3

S

4

OUT

OUT

IN

DFR_DISP_VSYNC MIPI_DFR_CLK_CONN_FILT_P

DFR_DISP_TE

DFR_DISP_INT
DFR_DISP_RESET_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

EDP: 145mA

PP3V3_G3HSW_DFR

120

10%

6.3V
X5R

0201

1

2

C5110

0.1UF

F-ST-SM

28 27

2 1

GND

4 3
6 5

8 7

GND

10 9
12 11

14 13

16 15
18 17
20 19
22 21
24 23

26 25

30 29

GND

GND

GND_VOID=TRUE

120

MIPI_DFR_CLK_CONN_FILT_N

120

GND_VOID=TRUE

GND_VOID=TRUE

MIPI_DFR_DATA_CONN_FILT_P

120

MIPI_DFR_DATA_CONN_FILT_N

120

GND_VOID=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

PP1V8_SLPS2RSW_DFR

I2C_DFR_SCL_R
I2C_DFR_SDA_R

1

C5111

1.0UF

20%

6.3V

2

X5R
0201-1

EDP: 57mA

52

IN

BI

GND_VOID=TRUE
GND_VOID=TRUE

52

L5110

3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM

4

3 2

SYM_VER-2

L5111

3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM

4

3 2

GND_VOID=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

SYM_VER-2

PLACE_NEAR=J5110:5mm

1

1

GND_VOID=TRUE
GND_VOID=TRUEGND_VOID=TRUE

1

C5171

1UF

10V

2

X5R-CERM
0402

MIPI_DFR_CLK_P
MIPI_DFR_CLK_N

GND_VOID=TRUE
GND_VOID=TRUE

MIPI_DFR_DATA_P
MIPI_DFR_DATA_N

1

C5103

1UF

10%10%

10V

2

X5R-CERM
0402

40

IN

40

IN

40

IN

40

IN

U5104

NCP160AMX180

XDFN-COMBO-THICKSTNCL

1

OUT

EPAD GND

5

2

IN

EN

4

PP3V3_G3H_DFR

3

DFR_PWR_EN_R

C5104

1UF

20%

16V

CER-X5R

0201

50 116

1

C5102

1UF

10%

10V

2

1

2

1

R5101

100K

5%
1/20W
MF
201

2

X5R-CERM
0402

R5111

1K

21

5%

1/20W

MF

201

DFR_PWR_EN

38

IN

B

A

120 52 50

120 50 40

120 50 39

120 50 47

120 50

PP1V8_SLPS2RSW_DFR

DFR_TOUCH_RESET_L

DFR_TOUCH_INT_L
SPI_DFR_MISO_R
DFR_LID_OPEN_L

R5106

100K

5%

1/20W

MF

201

1

R5103

4.7K

5%
1/20W
MF
201

2

1

2

1

R5104

100K

5%
1/20W
MF
201

2

1

R5105

100K

5%
1/20W
MF
201

2

BOM_COST_GROUP=T151

SYNC_MASTER=SILU SYNC_DATE=07/27/2017

PAGE TITLE

DFR & T208 Support

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

51 OF 200

SHEET

50 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

51 80

SMC (SoC)

U3900

(MASTER)

51 39

I2C_SNS0_S0_SCL

MAKE_BASE=TRUE

51 39

I2C_SNS0_S0_SDA

MAKE_BASE=TRUE

PP1V8_S5

SMC I2C "1" S0 Connections

1

R5206

2.2K

5%
1/16W
MF-LF

402

1

2

R5205

2.2K

5%
1/16W
MF-LF
402

2

LEVEL

SHIFTER

51

I2C_SNS0_S0_5V_SCL

MAKE_BASE=TRUE

I2C_SNS0_S0_5V_SDA

MAKE_BASE=TRUE

EADC1

U5700

(Write: 0x10 Read: 0x11)

I2C_SNS0_S0_5V_SCL

I2C_SNS0_S0_5V_SDA

EADC2

U5710

(Write: 0x12 Read: 0x13)

I2C_SNS0_S0_5V_SCL

56

56

56

PP1V8_S5

51 80

SMC (SoC)

U3900

(MASTER)

I2C_DISP_SCL

39

MAKE_BASE=TRUE

39

I2C_DISP_SDA

MAKE_BASE=TRUE

SMC I2C "3" S0 Connections

PP1V8_S5

51 80

1

C5210

0.1UF

10%

R5215

2.2K

5%

1/20W

MF

201

1

2

1

R5216

2.2K

5%
1/20W
MF
201

2

82

IN

PANEL_P3V3_EN
I2C_DISP_SCL

I2C_DISP_SDA

6.3V

2

CERM-X5R
0201

1

VCCA

U5210

TXS0102DQM

5

OE

CRITICAL

2

A1

3

A2

X2SON

GND

4

8

VCCB

B1

B2

PP3V3_S0SW_LCD

C5211

1

0.1UF

10%
10V

2

X5R-CERM
0201

7
6

R5218

2.2K

5%

1/20W

MF

201

120 82

Internal DP

J8500

1

2

1

R5219

2.2K

5%
1/20W
MF
201

2

16 addresses

(Write: 0x20 Read: 0x21)

thru

(Write: 0x3E Read: 0x3F)

( when VRR_FLAG = 0 )

I2C_TCON_SCL
I2C_TCON_SDA

120 82

D

120 82

GMUX IOEXP

U9801

(WRITE 0X44 READ 0X45)

I2C_DISP_SCL

93

C

PP1V8_S5

51 80

LOADISNS

R5270

100K

5%

1/20W

MF

201

1

2

1

C5270

0.1UF

10%

6.3V

2

CERM-X5R
0201

LOADISNS

MLBSNS_I2CLS_EN

51 39

51 39

I2C_SNS0_S0_SCL
I2C_SNS0_S0_SDA

SMC I2C "2" S0 Connections

PP1V8_S5

51 80

SMC (SoC)

U3900

(MASTER)

39

I2C_SNS1_S0_SCL

MAKE_BASE=TRUE

I2C_SNS1_S0_SDA

39

MAKE_BASE=TRUE

TBT LEFT THERM

TMP461: U5850

(Write: 0x98 Read: 0x99)

I2C_SNS1_S0_SCL

51 57

51 57

I2C_SNS1_S0_SDA

1

VCCA

U5270

TXS0102DQM

5

OE

2
3

CRITICAL

A1

A2

LOADISNS

R5250

2.2K

5%

1/20W

MF

201

X2SON

GND

4

1

2

PP5V_G3S

LOADISNS

C5271

0.1UF

10%
10V
X5R-CERM
0201

8

VCCB

7

B1

6

B2

1

R5251

2.2K

5%
1/20W
MF
201

2

1

NOSTUFF

2.2K

5%

1/20W

MF

201

1

2

R5278

2

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

CPU, Mem, Airflow,

GPU Analog Die

(Write: 0x90 Read: 0x91)

I2C_SNS1_S0_SCL

I2C_SNS1_S0_SDA

116

NOSTUFF

1

R5279

2.2K

5%
1/20W
MF
201

2

I2C_SNS0_S0_5V_SCL
I2C_SNS0_S0_5V_SDA

Fixstack Prox

WLAN,FB

TMP468:U5870

57

57

I2C_SNS0_S0_5V_SDA

51

56

SMC I2C "5" G3S Connections

PP1V8_G3S

116

SMC (SoC)

U3900

(MASTER)

I2C_SNS_G3S_SCL

39

MAKE_BASE=TRUE

I2C_SNS_G3S_SDA

39

MAKE_BASE=TRUE

I2C_DISP_SDA

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

2117S0059

RES,2.2K,1/20W,0201,SMD,MF

R5230,R5231

OCARINA_I2C:2.2K

93

SMC I2C "4" G3H Connections

PP1V8_SLPS2R

R5225

2.2K

5%
1/16W
MF-LF

402

80

5%

1/20W

MF

201

1

2

SMC (SoC)

R5220

4.7K

U3900

(MASTER)

119 39

119 39

1

2

1

R5226

2.2K

5%
1/16W
MF-LF

2

402

I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA

Trackpad

J6701

(WRITE: 0X98 READ: 0X99)

(See trackpad)

(10K IPU)

(10K IPU)

(Write:0xE8 Read:0xE9)

66

66

I2C_PWR_SCL

MAKE_BASE=TRUE

I2C_PWR_SDA

MAKE_BASE=TRUE

CALPE

U7800

I2C_PWR_SCL

77

I2C_PWR_SDA

77

R5221

1

4.7K

5%
1/20W
MF
201

2

Battery

J6950

(Write:0x16 Read:0x17)

I2C_PWR_SCL
I2C_PWR_SDA

Battery Charger

U7000
(Write:0x12 Read:0x13)
I2C_PWR_SCL

I2C_PWR_SDA

67

67

68

68

C

B

A

GPU Analog Die

TMP461: U5880

(Write: 0x92 Read: 0x93)

I2C_SNS1_S0_SCL

51 57

51 57

I2C_SNS1_S0_SDA

PP1V8_S5

51 80

1

C5260

0.1UF

10%

6.3V

2

CERM-X5R
0201

95

IN

PM_ALL_GPU_PGOOD
I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA

1

VCCA

U5260

TXS0102DQM

5

OE

2
3

CRITICAL

A1
A2

X2SON

GND

4

PP3V3_S0_GPU

C5261

0.1UF

1

X5R-CERM

0201

8

VCCB

B1

B2

2

7
6

TBT RIGHT THERM

TMP461: U5800

(Write: 0x96 Read: 0x97)

I2C_SNS1_S0_SCL

I2C_SNS1_S0_SDA

10%
10V

103 115

57

57

GPU DIE

UA000

(Write: 0x82 Read: 0x83)

GPU_SMB_CLK
GPU_SMB_DAT

103

BI

103

BI

SMC I2C "0" G3H Connections

PP1V8_SLPS2R

80

SMC (SoC)

U3900
(MASTER)

39

I2C_UPC_SCL

119

MAKE_BASE=TRUE

39

I2C_UPC_SDA

119

MAKE_BASE=TRUE

39 29

UPC_I2C_INT_L

107

MAKE_BASE=TRUE

USB-C PORT CONTROLLER TA

CD3215A (ACE) - UB300

(WRITE: 0X40 READ: 0X41)

107

I2C_UPC_SCL

I2C_UPC_SDA

107

108

USB-C PORT CONTROLLER TB

UPC_I2C_INT_L

CD3215A (ACE) - UB400

(WRITE: 0X4E READ: 0X4F)

I2C_UPC_SCL

107

107

I2C_UPC_SDA

109

UPC_I2C_INT_L

(IPU)

1

R5246

2.2K

5%
1/20W
MF
201

2

1

R5200

5%
1/20W
MF
201

2

1

R5201

2.2K2.2K

5%
1/20W
MF
201

2

USB-C PORT CONTROLLER XA

CD3215A (ACE) - U3100

(WRITE: 0X70 READ: 0X71)

I2C_UPC_SCL
I2C_UPC_SDA

UPC_I2C_INT_L

USB-C PORT CONTROLLER XB

29

29

30

CD3215A (ACE) - U3200

(WRITE: 0X7E READ: 0X7F)

I2C_UPC_SCL
I2C_UPC_SDA

UPC_I2C_INT_L

29

29

31

SMC I2C "6" G3H Connections

PP1V8_SLPS2R

80

OCARINA_I2C:1K

R5230

SMC (SoC)

1/20W

U3900

(MASTER)

I2C_SSD_SCL

39

MAKE_BASE=TRUE

39

I2C_SSD_SDA

MAKE_BASE=TRUE

BOM_COST_GROUP=SMC

1K

5%
MF

201

1

2

OCARINA_I2C:1K

1

R5231

1K

5%
1/20W
MF
201

2

R5240
R5241

S4E_X4PLUS

S4E_X4PLUS

SYNC_MASTER=RAYMOND SYNC_DATE=10/02/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R5242
R5243

SSD 0

Ocarina

(Write:0xF2 Read:0xF3)

CKPLUS_WAIVE=I2C_PULLUP

33

5%MF
5%MF

33

21
21

1/20W 201

I2C_SSD0_SCL

2011/20W

I2C_SSD0_SDA

CKPLUS_WAIVE=I2C_PULLUP

SSD 1

Ocarina

(Write:0xF0 Read:0xF1)

CKPLUS_WAIVE=I2C_PULLUP

33

MF 5% 201

5% 1/20W 201MF

33

21

1/20W

21

I2C_SSD1_SCL
I2C_SSD1_SDA

CKPLUS_WAIVE=I2C_PULLUP

I2C Connections 1

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

52 OF 200

SHEET

51 OF 131

B

87

87

92

92

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

AP I2C "0" G3S Connections

116

PP1V8_G3S

AP (SoC)

U3900

(MASTER)

I2C_SPKRAMP_L_SCL

40

I2C_SPKRAMP_L_SDA

40

AP I2C "1" G3S Connections

PP1V8_G3S

116

AP (SoC)

U3900

(MASTER)

I2C_SPKRAMP_R_SCL

40

MAKE_BASE=TRUE

I2C_SPKRAMP_R_SDA

40

MAKE_BASE=TRUE

R5300

2.2K

1/20W

MAKE_BASE=TRUE

MAKE_BASE=TRUE

R5305

2.2K

1/20W

1

5%
MF

201

2

1

5%
MF

201 201

2

1

R5301

2.2K

5%
1/20W
MF
201

2

1

R5306

2.2K

5%
1/20W
MF

2

Left Speaker Amps

U6400

(WRITE:0XD8,READ 0XD9)

U6450

(WRITE:0XDA,READ 0XDB)

I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_L_SDA

Right Speaker Amps

U6500

(WRITE:0XDC,READ 0XDD)

U6550

(WRITE:0XDE,READ 0XDF)

I2C_SPKRAMP_R_SCL
I2C_SPKRAMP_R_SDA

62

62

63

63

AP I2C "5" Awake Connections

AP (SoC)

U3900

(MASTER)

NC_I2C_SOC_5_SCL

40

40

NC_I2C_SOC_5_SDA

ISP I2C "1" G3S Connections

ISP (SoC)

U3900

(MASTER)

NC_I2C_PLCAM_SCL

40

NC_I2C_PLCAM_SDA

40

ISP I2C "0" G3S Connections

PP1V8_G3S

82 116

MAKE_BASE=TRUE

NC_I2C_SOC_5_SCL
NC_I2C_SOC_5_SDA

MAKE_BASE=TRUE

NC_I2C_PLCAM_SCL

MAKE_BASE=TRUE

NC_I2C_PLCAM_SDA

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

I2C Device Address

Device
ACE XA
ACE XB
ACE TA
ACE TB

EADC1
EADC2

Temp. Sensor Left

Temp. Sensor Right

CPU,MEM,WLAN Thermal

GPU Analog Die Thermal

GPU Digital Die Thermal

TCON

GMUX IOEXP

SMC IF

ADDR. (8b)
I2C0
I2C0
I2C0
I2C0

0X70/1
0X7E/F
0X40/1

0X4E/F
I2C1 0X10/1
I2C1

I2C2
I2C2
I2C2
I2C2

I2C2
I2C3

0X12/3

0X98/9

0X96/7

0X90/1

0X92/3

0X82/3

0X20-3F

0X44/5I2C3

D

C

B

40

40

120 40

120 40

AP I2C "2" Codec Connections

AP (SoC)

U3900

(MASTER)

I2C_CODEC_SCL

MAKE_BASE=TRUE

I2C_CODEC_SDA

MAKE_BASE=TRUE

AP I2C "3" G3S Connections

116

AP (SoC)

U3900

(MASTER)

I2C_ALS_SCL

MAKE_BASE=TRUE

I2C_ALS_SDA

MAKE_BASE=TRUE

61 116

PP1V8_G3S

PP1V8_G3S

R5310

R5315

2.2K

5%

1/20W

201

1.1K

5%

1/20W

MF

201

1

1

ISP (SoC)

U3900

(MASTER)

40

I2C_FTCAM_SCL

MAKE_BASE=TRUE

I2C_FTCAM_SDA

40

MAKE_BASE=TRUE

1

2

1

R5311

2.2K

5%
1/20W
MFMF
201

2

Audio Codec

U6300

(WRITE:0X90,READ 0X91)

I2C_CODEC_SCL
I2C_CODEC_SDA

61

61

CNL-H uSFF SMBUS Connections

12 13 15 16 19 20 80

PCH

U1200

(MASTER)

SMBUS_PCH_CLK

15

SMBUS_PCH_DATA

15

1

1

2

R5316

1.1K

5%

1/20W

MF

201

2

(See camera flex)

(WRITE:0X29,READ 0X2A)

I2C_ALS_SCL
I2C_ALS_SDA

ALS

J8500

82

82

R5335

1.1K

5%

1/20W

MF

201

PP1V8_S5

R5360

2.2K

1/20W

2

5%
MF

201

R5336

1.1K

5%

1/20W

MF

201

2

1

2

(WRITE:0X6C,READ 0X6D)

1

R5361

2.2K

5%
1/20W
MF
201

2

FaceTime Camera

J8500

I2C_FTCAM_SCL
I2C_FTCAM_SDA

82

82

Charger
Battery

Calpe

SSD0
SSD1

Left Spkr Amp.(U6400)

Left Spkr Amp.(U6450)
Right Spkr Amp.(U6500)
Right Spkr Amp.(U6550)

Audio Codec

ALS

DFR Display

DFR Touch

NC.

I2C4
I2C4

I2C4

I2C6

SoC IF

I2C0
I2C0
I2C1
I2C1
I2C2
I2C3
I2C4
I2C4
I2C5

0X12/3
0X16/7

0XE8/9
0X98/9I2C5Trackpad

0XF2/3I2C6
0XF0/1

0XD8/9
0XDA/B
0XDC/D
0XDE/F
0X90/1
0X29/A
0X98/9
0XA0/1

C

B

40

AP I2C "4" DFR Connections

120 50

AP (SoC)

U3900

CKPLUS_WAIVE=I2C_PULLUP

BI

CKPLUS_WAIVE=I2C_PULLUP

(MASTER)

I2C_DFR_SCL I2C_DFR_SCL_R
I2C_DFR_SDA

201 MF 1/20W 5%

201 MF 1/20W 5%

R5322
R5323

PP1V8_SLPS2RSW_DFR

15

2 1

15

2 1

MAKE_BASE=TRUE

I2C_DFR_SDA_R

MAKE_BASE=TRUE

R5320

1

2.2K

5%

1/20W

MF

201

2

R5321

1

2.2K

5%
1/20W
MF
201

2

(Write:0x98 Read:0x99)

I2C_DFR_SCL_R
I2C_DFR_SDA_R

DFR Display

J5110

NC. Spkr ID1 I2C6_SDA

I2C6_SCLSpkr ID0

ISP IF

FT Camera I2C0

NC.

I2C1

0X6C/D

AOP IF

NC.

50 40

OUTIN

50

BI

NC.

PULL-UP

I2C0

PCH IF

A

8

DFR Touch ROM

J5100

(Write:0xA0 Read:0xA1)

I2C_DFR_SCL_R
I2C_DFR_SDA_R

OUT

SYNC_DATE=10/02/2017SYNC_MASTER=RAYMOND

PAGE TITLE

A

I2C Connections 2

DRAWING NUMBER

120 50

Apple Inc.

BI

120 50

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=SMC

67

35 4

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

53 OF 200

SHEET

52 OF 131

1

SIZE

D

D

DC-IN Voltage Sense (VD0R)

Gain: 0.05322x
Vnominal: 20 V, Range: 23.49 V
SMC ADC: 00
Enables DC-In VSense
divider when AC present.

2.2KHz

PPDCIN_G3H

29 55 68 119
122

1%

1/20W

MF

201

1%

1/20W

MF

201

1

2

1

2

R5498

84.5K

R5499

4.75K

PLACE_NEAR=U3900.AG2:5MM

Rthevenin = 4497 Ohms

SMC_DCIN_VSENSE

PLACE_NEAR=U3900.AG2:5MM

1

C5499

0.022UF

10%

6.3V

2

X5R-CERM
0201

OUT

59 121

H9M
CALPE
EADC

Vref(V)

1.25

1.5

2.5

678

J680 SENSOR SETTINGS

Vmax

1.8

5

5

SMC sample Freq.

10khz

100hz
1-2hz(10hz)

3 245

1

OTHER 5V High Side Current Sense (IO5R)

ADR RC filterCHIP

0.1ms
10ms

115

100ms

115

Gain: 200x, EDP: 1.766 A
Rsense: 0.005 (R5410) or Rsense SHORT
Vsense: 8.83 mV, Range: 3.3 A
CALPE: AMUX_B7

PLACE_NEAR=U5410.2:3:10MM

PPBUS_G3H

CRITICAL

R5410

0.005

SENSOR:DEV

121

1%

1/3W

MF

0306

1

ISNS_HS_OTHER5V_P

ISNS_HS_OTHER5V_N

432

PPBUS_HS_OTH5V

PLACE_NEAR=U5410.4:5:10MM

116 53

PP3V3_G3SSW_SNS

LOADISNS

CRITICAL

IN+

2
3

IN+

IN-

4

IN-

5

6

V+

U5410

INA210A

UQFN

200x

GND

9

OUT

REF

NC
NC

10
8
1

7

1

C5411

0.1UF

10%

2

6.3V
CERM-X5R
0201

NC
NC

PLACE_NEAR=U7800.H13:15MM

LOADISNS

BYPASS=U5410.6::5MM

PLACE_NEAR=U7800.H13:15MM

LOADISNS

R5418

9.09K

1/20W

21

1%
MF

201

LOADRC:YES

PMU_OTHER5V_HI_ISENSEHS_OTHER5V_IOUT

R5419

9.09K

1/20W

1%
MF

201

59

D

OUT

1

2

PLACE_NEAR=U7800.H13:15MM

C5419

1

2.2UF

20%

2

6.3V
X5R-CERM
0201

LOADISNS

GND_CALPE_AVSS

53 54 55 58
76 94 121

C

PLACE_NEAR=U3900.AG2:5MM

GND_SMC_AVSS

39 46 53 54 56 58

DC-IN Current Sense (ID0R)

DISCharger Gain: 20x, EDP: 4.6 A
Rsense: 0.010 (R7020)
SMC ADC: 01

68

IN

CHGR_AMON

PLACE_NEAR=U3900.AC4:5MM

R5439

4.53K

1%

1/20W

MF

201

LEFT SIDE 3.3V High Side Current Sense (IOLR)

Gain: 200x, EDP: 4.82 A
Rsense: 0.003 (R5440) or Rsense SHORT
Vsense: 14.46 mV, Range: 5.5 A
SMC ADC:TBD

116 53

PP3V3_G3SSW_SNS

CALPE: AMUX_B5

LOADISNS

6

V+

115

21

SMC_DCIN_ISENSE

PLACE_NEAR=U3900.AC4:5MM

1

C5439

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

59

OUT

39 46 53 54 56 58

115

PPBUS_G3H

SENSOR:DEV

PPBUS_HS_3V3G3HRTC_X

CRITICAL

R5440

0.003

1/2W

121

0306

PLACE_NEAR=U5440.2:3:10MM

ISNS_HS_3V3_X_P

1

1%
MF

ISNS_HS_3V3_X_N

432

PLACE_NEAR=U5440.4:5:10MM

U5440

INA210A

IN+

2
3

IN+

IN-

4

IN-

5

UQFN

CRITICAL

200x

GND

9

OUT

REF

NC
NC

HS_3V3_X_IOUT

10
8
1

NC

7

NC

LOADISNS

BYPASS=U5440.6::5MM

1

C5441

0.1UF

10%

6.3V

2

CERM-X5R
0201

LOADISNS

R5448

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.G14:15MM

21

PMU_3V3_X_HI_ISENSE

R5449

9.09K

LOADRC:YES

PLACE_NEAR=U7800.G14:15MM

1%

1/20W

MF

201

59

OUT

PLACE_NEAR=U7800.G14:15MM

1

2

1

C5449

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_CALPE_AVSS

LOADISNS

121
53 54 55
58 76 94

C

B

A

EN_VP0R_LPS:NO

PBUS Voltage Sense (VP0R)

Gain: 0.08513x
Vnominal: 13.1 V, Range: 14.68 V
SMC ADC: 02
Enables PBUS VSense
divider when in S0.

PPBUS_G3H

115

PLACE_NEAR=R5400.1:75 MM

XW5480

SM

21

1

R5482

100K

1%

1/20W

MF

201

2

EN_VP0R_LPS:NO

PP3V3_G3SSW_SNS

54

56 55 53

116 58

PBUSVSENS_EN_L_DIV

2

EN_VP0R_LPS:NO

R5481

100K

201
MF

1

1/20W
1%

PBUS_S0_VSENSE_IN

EN_VP0R_LPS:YES

R5441

0

21

5%

1/20W

MF

0201

2

1

5

4

Discharger BMON Current Sense (IPBR)

Charger Gain: 8X OR 64x, Use 8X, EDP: 25 A
Rsense: 0.005 (R7060)
SMC ADC: 03

R5429

68

IN OUT

CHGR_BMON

PLACE_NEAR=U3900.AD4:15MM

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U3900.AD4:15MM

21

NOSTUFF

R5428

9.09K

1/20W

1%
MF

201

1

2

SMC_BMON_ISENSE

PLACE_NEAR=U3900.AD4:15MM

1

C5429

0.022UF

10%

2

6.3V
X5R-CERM
0201

GND_SMC_AVSS

CPU High Side Curent Sense (IC0R)

Gain: 100x, EDP: 16.8 A

115

115

Rsense: 0.001 (R5400)
Vsense: 16.8 mV, Range: 25 A
SMC ADC: 04

3.3KHz

PLACE_NEAR=R5400.3:5MM

PPBUS_G3H

121

ISNS_HS_COMPUTING_P

1%

1W
MF-3
0612

1

PLACE_NEAR=U5400.3:10MM
PLACE_NEAR=U5400.4:10MM

432

ISNS_HS_COMPUTING_N

R5400

0.001

CRITICAL

PPBUS_HS_CPU

IN+

2
3

IN+

IN-

4

IN-

5

PLACE_NEAR=R5400.4:5MM

BYPASS=U5400.6::5MM

PP3V3_G3SSW_SNS

116

6

V+

U5400

INA214A

UQFN

CRITICAL

100x

GND

9

OUT

REF

NC
NC

10
8
1

7

1

C5401

0.1UF

10%

6.3V

2

CERM-X5R
0201

ISNS_HS_COMPUTING_OUT

NOSTUFF

NC
NC

1

R5405

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U5400.6:5MM

PLACE_NEAR=U3900.AB6:10MM

CRITICAL

Q5480

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

S

D

PBUSVSENS_EN_L

6

PBUS_S0_VSENSE

3

R5488

G

S

P-CHANNEL

R5489

PLACE_NEAR=U3900.AH3:15MM

59

39 46 53 54 56 58

PLACE_NEAR=U3900.AB6:10MM

R5409

9.09K

1/20W

1%
MF

201

21

R5401

9.09K

1/20W

201

1%
MF

SMC_CPU_HI_ISENSE

PLACE_NEAR=U3900.AB6:5MM

1

C5409

1

2

0.022UF

10%

6.3V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AH3:15MM

1

59K

1%

1/20W

MF

2

201

Rthevenin = 5023 Ohms

SMC_PBUS_VSENSE

1

5.49K

1%

1/20W

MF

2

201

1

2

GND_SMC_AVSS

C5489

0.022UF

10%

6.3V
X5R-CERM
0201

PLACE_NEAR=U3900.AH3:15MM

GND_SMC_AVSS

OUT

39 46 53 54 56 58

59

59 121

OUT

39 46 53 54 56 58

121

RIGHT SIDE 3.3V High Side Current Sense (IORR)

Gain: 100x, EDP: 10.6 A
Rsense: 0.003 (R5460) or Rsense SHORT
Vsense: 31.8 mV, Range: 11 A
SMC ADC:TBD
CALPE: AMUX_B6

115

PPBUS_G3H

CRITICAL

R5460

0.002

115

SENSOR:DEV

PPBUS_HS_3V3G3H_T

1/2W
0306

1%
MF

PP3V3_G3SSW_SNS

116 53

PLACE_NEAR=R5460.3:10MM

1

121

ISNS_HS_3V3_T_P

121

ISNS_HS_3V3_T_N

432

PLACE_NEAR=R5460.4:10MM

LOADISNS

IN+

2
3

IN+

IN-

4

IN-

5

6

V+

U5460

INA214A

UQFN

CRITICAL

100x

GND

9

OUT

REF

NC
NC

1

2

ISNS_HS_3V3_T_OUT

10
8
1

NC

7

NC

LOADISNS

BYPASS=U5460.6::5MM

C5461

0.1UF

10%

6.3V
CERM-X5R
0201

LOADISNS

R5468

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.H14:15MM

21

R5469

9.09K

LOADRC:YES

PLACE_NEAR=U7800.H14:15MM

LCD Backlight Current Sense (IBLR)

Gain: 100x. EDP: 0.87 A
Rsense: 0.025 (R8400)
Vsense: 21.75 mV, Range: 1.32 A
EADC1: CH0

81

IN

81 121

IN

116 58 56 55 54 53

PP3V3_G3SSW_SNS

PLACE_NEAR=R8400.4:10MM

ISNS_LCDBKLT_N

PLACE_NEAR=R8400.3:10MM

3 LOADRC:NO117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

LOADISNS

IN+

2
3

IN+

IN-

4

IN-

5

6

V+

U5450

INA214A

UQFN

CRITICAL

100x

GND

9

R5449,R5469,R5419

OUT

REF

NC
NC

LOADISNS

1

C5450

0.1UF

10%

2

6.3V
CERM-X5R
0201

BYPASS=U5450.6::5MM

ISNS_LCDBKLT_IOUT

10
8
1

NC

7

NC

NOSTUFF

1

R5455

6.04K

1%
1/20W
MF
201

2

PLACE_NEAR=U5450.10:5MM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LOADISNS

R5459

45.3K

1%

1/20W

MF

201

PLACE_NEAR=U5700.22:5MM

21

EADC1_LCDBKLT_ISENSEISNS_LCDBKLT_P

C5459

1

2.2UF

20%

2

6.3V
X5R-CERM
0201

PLACE_NEAR=U5700.22:5MM

GND_EADC1_COM

BOM_COST_GROUP=SENSORS

OUT

LOADISNS

55 56 58

SYNC_MASTER=RAYMOND SYNC_DATE=10/09/2017

PAGE TITLE

Power Sensors High Side

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PMU_3V3_T_HI_ISENSE

PLACE_NEAR=U7800.H14:15MM

1

C5469

2.2UF

20%

6.3V
X5R-CERM

2

0201

LOADISNS

1%

1/20W

MF

201

1

2

GND_CALPE_AVSS

56

59

OUT

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

54 OF 200

SHEET

53 OF 131

121
53 54 55
58 76 94

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

115

116

PCH 1.0V Current Sense (IS1C)

Gain: 200x, EDP: 4.7 A
Rsense: 0.001 (R5560) or XWTBD
Vsense: 14.1 mV, Range: 5.5 A
EADC2:CH1

PPVCCPRIMCORE_PRIM_REG

PLACE_NEAR=R5560.4:5MM

432

SENSOR:DEV

PP1V05_PRIM

R5560

0.001

1/3W

1%
MF

121

0306

ISNS_1V0_P

1

ISNS_1V0_N

PLACE_NEAR=R5560.3:5MM

LOADISNS

PP3V3_G3SSW_SNS

53 54 55 56 58 116

6

V+

U5560

INA210A

2

IN+

3

IN+

UQFN

CRITICAL

200x

IN-

4
5

IN-

GND

9

OUT

REF

NC
NC

LOADISNS

BYPASS=U5560.6::5MM

1

C5560

0.1UF

10%

2

6.3V
CERM-X5R
0201

PCH_1V0_IOUT

10
8
1

NC

7

NC

PLACE_NEAR=U5560.10:5MM

1

2

DDR4 1.2V Current Sense (IM0C)

Gain: 100x, EDP: 11 A
Rsense: 0.002 (R7718) or XWTBD
Vsense: 22.2 mV, Range: 16.5 A
CALPE: AMUX_A7

53 54 55 56 58 116

PP3V3_G3SSW_SNS

LOADISNS

V+

6

LOADISNS

BYPASS=U5570.3::5MM

C5570

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

R5565

51K

5%
1/20W
MF
201

NOSTUFF

PLACE_NEAR=U5710.23:5MM

LOADISNS

R5569

45.3K

1%

1/20W

MF

201

EADC2_PCH_1V0_ISENSE

21

1

C5569

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_EADC2_COM

PLACE_NEAR=U7800.F14:15MM

LOADISNS

OUT

PLACE_NEAR=U5710.23:5MM

LOADISNS

56

CPU Core Curent Sense (ICAC)

Gain: 89.48x, EDP: 128 A
Rsense: 3x of 0.00075
R7210,R7220,R7230),Rsum: 0.00025
Vsense:16.75 mV, Range: 134.11 A
CALPE AMUX: A0

116

LOADISNS

70

IN

CPUCORE_ISNS1_P

NO_XNET_CONNECTION=1
PLACE_NEAR=R7210:5MM

LOADISNS

70

IN

CPUCORE_ISNS2_P

NO_XNET_CONNECTION=1
PLACE_NEAR=R7220:5MM

LOADISNS

70

IN

121 58 56 55 54

70

IN

CPUCORE_ISNS3_P

NO_XNET_CONNECTION=1
PLACE_NEAR=R7230:5MM

LOADISNS

CPUCORE_ISNS1_N

NO_XNET_CONNECTION=1
PLACE_NEAR=R7210:5MM

LOADISNS

70

IN

CPUCORE_ISNS2_N

NO_XNET_CONNECTION=1
PLACE_NEAR=R7220:5MM

LOADISNS

70

IN

CPUCORE_ISNS3_N

NO_XNET_CONNECTION=1
PLACE_NEAR=R7230:5MM

R5545

4.42K

MF0.1%

02011/20W

R5546

4.42K

0.1%

1/20W

R5550

4.42K

0.1%

1/20W

R5547

4.42K

MF0.1%

1/20W 0201

R5548

4.42K

0.1%

1/20W

R5551

4.42K

0.1%

1/20W

21

CPUVR_ISNS_P

21

MF

0201

21

MF

0201

NO_XNET_CONNECTION=1

21

CPUVR_ISNS_N

21

MF

0201

21

MF

0201

LOADISNS

R5542

2.55K

0.1%

1/20W

0201

21

MF

LOADISNS

R5543

2.55K

0.1%

1/20W

0201

21

MF

CPUVR_ISNS_R_P

LOADISNS

1

R5544

360K

0.1%
1/20W
MF

2

0201

CPUVR_ISNS_R_N

PP3V3_G3SSW_SNS

LOADISNS CRITICAL

U5540

52

1

3

ISL28133

SC70-5

V+

V-

CPUVR_ISUM_IOUT

4

LOADISNS

R5541

360K

0.1%

1/20W

0201

21

MF

NO_XNET_CONNECTION=1

LOADISNS

BYPASS=U5540.5::5MM

C5540

1

0.1UF

10%

2

6.3V
X7R
0201

LOADISNS

R5540

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.A16:15MM

21

PMU_CPU_ISENSE

R5549

9.09K

1/20W

201

PLACE_NEAR=U7800.A16:15MM

LOADRC:YES

1%
MF

D

59

OUT

PLACE_NEAR=U7800.A16:15MM

1

1

2

C5549

2.2UF

20%

6.3V

2

X5R-CERM
0201

LOADISNS

GND_CALPE_AVSS

121 94

76 58 55 54 53

C

B

115

115

U5570

121 74

121 74

ISNS_CPUDDR_P

IN

ISNS_CPUDDR_N

IN

INA214A

IN+

2
3

IN+

IN-

4

IN-

5

UQFN

CRITICAL

100x

GND

9

OUT

REF

NC
NC

ISNS_DDR_IOUT

10
8
1

NC

7

NC

CPUDDR 1.2V Curent Sense (IMCC)

Gain: 200x, EDP: 2.8 A
Rsense: 0.005 (R5510)
Vsense: 14 mV, Range: 3 A
CALPE: AMUX_A6

PP1V2_S3

SENSOR:DEV

PP1V2_S3_CPUDDR

R5510

0.005

1/3W

1%
MF

121

0306

PLACE_NEAR=R5510.4:5MM

ISNS_CPUVDDQ_P

432

1

ISNS_CPUVDDQ_N

PLACE_NEAR=R5510.3:5MM

PP3V3_G3SSW_SNS

53 54 55 56 58 116

LOADISNS

2
3

4
5

U5510

INA210A

IN+

CRITICAL

IN+

200x

IN­IN-

6

V+

UQFN

GND

9

OUT

REF

NC
NC

LOADISNS

BYPASS=U5510.3::5MM

C5510

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

10
8
1

7

ISNS_CPUDDR_IOUT

NC
NC

R5579

9.09K

1/20W

LOADRC:YES

PLACE_NEAR=U7800.F14:15MM

LOADRC:YES

PLACE_NEAR=U7800.E14:15MM

21

1%
MF

201

LOADISNS

R5518

9.09K

1%

1/20W

MF

201

PMU_DDR1V2_ISENSE

R5576

9.09K

PLACE_NEAR=U7800.E14:15MM

21

1

1%

1/20W

MF

201

2

PMU_CPUDDR_ISENSE

1%

1/20W

MF

201

1

2

R5519

9.09K

LOADISNS

1

C5579

2.2UF

20%

6.3V

2

X5R-CERM
0201

PLACE_NEAR=U7800.F14:15MM

GND_CALPE_AVSS

59

OUT

PLACE_NEAR=U7800.E14:15MM

1

C5519

2.2UF

20%

6.3V
X5R-CERM

2

0201

LOADISNS

OUT

59

116

116

121 94 76 58 55 54 53

PP3V3_G3S_X

PLACE_NEAR=R5533.1:10MM

SENSOR:DEV

PP3V3_G3S_WLAN

WLANBT 3V3 Current Sense (IAPC)

Gain: 200x, EDP: 1.5 A
Rsense: 0.005 (R5530) or Rsense SHORT
Vsense: 7.5 mV, Range: 1.72 A
SMC: ADC 06

PP5V_G3S

56 116

1

R5530

0.005

1%

1/3W

MF

0306

121

PLACE_NEAR=R5532.1:10MM

ISNS_WLAN_N

ISNS_WLAN_P

432

LOADISNS

D5530

SC2

PP5V_G3S_ISNS_D

KA

DSF01S30SCAP

LOADISNS

R5533

120

R5532

120

1/20W

LOADISNS

LOADISNS

BYPASS=U5530.6::5MM

1

C5530

0.1UF

10%

6.3V

2

CERM-X5R
0201

21

ISNS_WLAN_R_N

0201

MF0.1%1/20W

ISNS_WLAN_R_P

21

0201MF0.1%

U5530

LTC2050HVCS5

TSOT23-5

LOADISNS

CRITICAL

145x

C

LOADISNS

Q5530

DMP31D0UFB4

DFN1006H4-3

2

S

G

4

1

3

2 5

R5535

1/20W

1

IAPC_OPA_OUT

1

100K

5%
MF

201

2

LOADISNS

ISNS_P3V3S_WLAN_IOUT

3

D

1

R5534

17.4K

0.1%
1/20W
MF
0201

2

LOADISNS

R5538

4.53K

LOADISNS

1%

1/20W

MF

201

PLACE_NEAR=U3900.AG4:10MM

21

SMC_P3V3_WLAN_ISENSE

PLACE_NEAR=U3900.AG4:5MM

1

C5539

0.022UF

10%

6.3V

2

X5R-CERM
0201

LOADRC:YES

GND_SMC_AVSS

59

58 56 53 46 39

B

2.5V Current Sense (IM1C)

Gain: 200x, EDP: 2.24 A
Rsense: 0.005 (R7724) or Rsense SHORT
Vsense: 11.2 mV, Range: 3.3 A
EADC2: CH0

PLACE_NEAR=R7724.3:5MM

74

74

PLACE_NEAR=R7724.4:5MM

ISNS_2V5_S3_P

IN

ISNS_2V5_S3_N

IN

LOADISNS

PP3V3_G3SSW_SNS

53 54 55 56 58 116

6

V+

U5590

INA210A

IN+

2
3

IN+

IN-

4

IN-

5

UQFN

CRITICAL

200x

GND

9

OUT

REF

NC
NC

10
8
1

7

LOADISNS

BYPASS=U5590.6::5MM

1

C5590

0.1UF

10%

6.3V
CERM-X5R

2

0201

DDR2V5_IOUT

1

R5595

NC
NC

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5590.10:5MM

PLACE_NEAR=U5710.22:5MM

LOADISNS

R5599

45.3K

1/20W

1%
MF

201

21

EADC2_DDR2V5_ISENSE

LOADISNS

1

C5599

2.2UF

20%

6.3V
X5R-CERM

2

0201

GND_EADC2_COM

GND_CALPE_AVSS

OUT

PLACE_NEAR=U5710.22:5MM

121 58 56 55 54

56

121 94 76 58 55 54 53

WLANBT 1V8 Current Sense (IA8C)

Gain: 200x, EDP: 0.1 A
Rsense: 0.05 (R5520) or Rsense SHORT
Vsense: 5 mV, Range: 0.3 A
CALPE: AMUX_A5

PP1V8_G3S

116

R5520

0.05

121

1%

1/3W

MF

0306

SENSOR:DEV

PP1V8_G3S_WLANBT_VDDIO

116

PLACE_NEAR=U5520.2:10MM

ISNS_WL1V8_P

1

ISNS_WL1V8_N

432
PLACE_NEAR=U5520.4:10MM

PP3V3_G3SSW_SNS

LOADISNS

IN+

2

CRITICAL

3

IN+

IN-

4

IN-

5

6

V+

U5520

INA210A

UQFN

200x

GND

9

OUT

REF

NC
NC

BYPASS=U5520.6::5MM

C5520

1

2

ISNS_WL1V8_IOUT

10
8
1

NC

7

NC

LOADISNS

0.1UF

10%

6.3V
CERM-X5R
0201

PLACE_NEAR=U7800.D15:15MM

LOADISNS

R5528

9.09K

1/20W

1%
MF

201

21

PMU_P1V8_WLAN_ISENSE

R5529

LOADRC:YES

PLACE_NEAR=U7800.D15:15MM

9.09K

1%

1/20W

MF

201

59

OUT

1

2

C5529

1

2.2UF

20%

2

6.3V
X5R-CERM
0201

LOADISNS

PLACE_NEAR=U7800.D15:15MM

GND_CALPE_AVSS

121 94 76 58 55 54 53

A

8

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

5117S0008 LOADRC:NO

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

R5576,R5519,R5549,C5539,R5529

67

SYNC_MASTER=RAYMOND SYNC_DATE=10/13/2017

PAGE TITLE

A

Power Sensors Load Side

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SENSORS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

55 OF 200

SHEET

54 OF 131

1

SIZE

D

678

3 245

1

D

PP3V3_G3W_SSD0 HIGH SIDE CURRENT SENSE (KEY IH0C)

GAIN: 200X, EDP: 1.48 A
RSENSE: 0.005 (RK710) OR RSENSE SHORT
VSENSE: 13 MV, RANGE: 2.5 A

CALPE: AMUX_B3

PP3V3_G3H_T

116

SENSOR:DEV

PP3V3_G3H_SSD0_SNS

116

121

1%

1/3W

MF

0306

1

R5600

0.005

121

CRITICAL

53 54 55 56 58 116

PLACE_NEAR=R5600.3:5MM

ISNS_P3V3_G3W_SSD0_P

ISNS_P3V3_G3W_SSD0_N

432

PLACE_NEAR=R5600.4:5MM

PP3V3_G3SSW_SNS

LOADISNS

V+

U5600

IN+

2
3

IN+

IN-

4

IN-

5

INA210A

UQFN

CRITICAL

200x

GND

PP3V3_G3W_SSD1 HIGH SIDE CURRENT SENSE (KEY IH1C)

GAIN: 200X, EDP: 1.48 A
RSENSE: 0.005 (RK760) OR RSENSE SHORT
VSENSE: 13 MV, RANGE: 2.5 A

CALPE: AMUX_B4

LOADISNS

1

C5600

6

REF

NC
NC

10
8
1

7

NC
NC

OUT

9

0.1UF

10%

6.3V

2

CERM-X5R
0201

HS_P3V3_G3W_SSD0_OUT

LOADISNS

R5601

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.F13:16MM

21

PMU_P3V3_G3W_SSD0_ISENSE

1%

1/20W

MF

201

1

2

R5602

9.09K

LOADRC:YES

PLACE_NEAR=U7800.F13:16MM

1

C5601

2.2UF

20%

6.3V

2

X5R-CERM
0201

PP3V3_G3H_RTC_X

116

SENSOR:DEV

59

116

PP3V3_G3H_SSD1_SNS

CRITICAL

R5610

0.005

1%

121

1/3W

MF

0306

PLACE_NEAR=R5610.3:10MM

1

ISNS_P3V3_G3W_SSD1_P

ISNS_P3V3_G3W_SSD1_N

432

PLACE_NEAR=R5610.4:10MM

LOADISNS

PP3V3_G3SSW_SNS

53 54 55 56 58 116

LOADISNS

2
3

4
5

U5610

INA210A

IN+

CRITICAL

IN+

200x

IN­IN-

6

V+

UQFN

GND

9

OUT

REF

NC
NC

LOADISNS

1

C5610

0.1UF

10%

6.3V

2

CERM-X5R
0201

HS_P3V3_G3W_SSD1_OUT

10
8
1

NC

7

NC

LOADISNS

R5611

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.G13:15MM

21

PMU_P3V3_G3W_SSD1_ISENSE

PLACE_NEAR=U7800.G13:15MM

1

C5611

2.2UF

20%

6.3V

2

X5R-CERM
0201

LOADISNS

R5612

9.09K

1%

1/20W

MF

201

LOADRC:YES

1

2

D

59

OUTOUT

C

PP12V SSD0 HIGH SIDE CURRENT SENSE (KEY IH0R)

GAIN: 200X, EDP: 0.5 A

RSENSE: 0.005 (RK610) OR RSENSE SHORT
VSENSE: 13 MV, RANGE: 2.5 A

CALPE: AMUX_B1

PPBUS_G3H

115

SENSOR:DEV

PPBUS_G3H_SSD0_SNS

116

1%

1/3W

MF

0306

1

R5620

0.005

121

CRITICAL

53 54 55 56 58 116

PLACE_NEAR=R5620.3:5MM

ISNS_PPBUS_MAIN_SSD0_P

ISNS_PPBUS_MAIN_SSD0_N

432

PLACE_NEAR=R5620.4:5MM

PP3V3_G3SSW_SNS

LOADISNS

IN+

2
3

4
5

CRITICAL

IN+

IN­IN-

6

V+

U5620

INA210A

UQFN

200x

GND

9

OUT

REF

NC
NC

PLACE_NEAR=U7800.F13:16MM

LOADISNS

1

C5620

0.1UF

10%

6.3V

2

CERM-X5R
0201

HS_PBUS_MAIN_SSD0_OUT

10
8
1

NC

7

NC

LOADISNS

R5621

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.E13:15MM

21

PLACE_NEAR=U7800.E13:15MM

GND_CALPE_AVSS

PMU_PBUS_MAIN_SSD0_ISENSE

PLACE_NEAR=U7800.E13:15MM

1

C5621

2.2UF

20%

6.3V

2

X5R-CERM
0201

LOADISNS

1%

1/20W

MF

201

1

2

R5622

9.09K

LOADRC:YES

121 94 76 58 55 54 53

PPBUS SSD1 HIGH SIDE CURRENT SENSE (KEY IH1R)

GAIN: 200X, EDP: 0.5 A

GND_CALPE_AVSS

RSENSE: 0.005 (R5607) OR RSENSE SHORT

PLACE_NEAR=U7800.G13:15MM

VSENSE: 13 MV, RANGE: 2.5 A

CALPE: AMUX_B2

PPBUS_G3H

115

SENSOR:DEV

1%

1/3W

MF

0306

1

ISNS_PPBUS_MAIN_SSD1_P
ISNS_PPBUS_MAIN_SSD1_N

432

59

OUT OUT

R5630

121

0.005

121

CRITICAL

116

PLACE_NEAR=R5630.3:10MM

PPBUS_G3H_SSD1_SNS

PLACE_NEAR=R5630.4:10MM

PP3V3_G3SSW_SNS

53 54 55 56 58 116

LOADISNS

LOADISNS

1

C5630

0.1UF

10%

6

V+

U5630

INA210A

IN+

2
3

IN+

IN-

4

IN-

5

UQFN

CRITICAL

200x

GND

9

OUT

REF

NC
NC

10
8
1

7

6.3V

2

CERM-X5R
0201

HS_PBUS_MAIN_SSD1_OUT

NC
NC

LOADISNS

R5631

9.09K

1%

1/20W

MF

201

PLACE_NEAR=U7800.E12:15MM

21

PMU_PBUS_MAIN_SSD1_ISENSE

PLACE_NEAR=U7800.E12:15MM

1

C5631

2.2UF

20%

6.3V

2

X5R-CERM
0201

LOADISNS

R5632

9.09K

1%

1/20W

MF

201

LOADRC:YES

1

2

121 94 76 58 55 54 53

59

C

B

LCD Panel Current Sense (ILDC)

Gain: 200x. EDP: 1 A
RSENSE: 0.01 (R8520) or Rsense SHORT
Vsense: 5 mV, Range: 1.25 A

EADC1: CH1

BYPASS=U5640.6::5MM

LOADISNS

1

C5640

0.1UF

10%

6.3V
CERM-X5R

2

0201

ISNS_LCDPANEL_IOUT

1

R5645

NC
NC

51K

5%
1/20W
MF

2

201 0201

NOSTUFF

LOADISNS

R5649

45.3K

1/20W

1%
MF

201

21

PLACE_NEAR=U5700.23:15MM

EADC1_LCDPANEL_ISENSE

1

C5649

2.2UF

20%

6.3V

2

X5R-CERM

LOADISNS

PLACE_NEAR=U5700.23:15MM

GND_EADC1_COM

121 82

PP3V3_G3SSW_SNS

53 54 55 56 58 116

PLACE_NEAR=R8520.1:5MM

ISNS_LCDPANEL_P

ISNS_LCDPANEL_N

IN

LOADISNS

2

IN+

3

CRITICAL

IN+

4

IN-

5

IN-

6

V+

U5640

INA210A

UQFN

200x

GND

9

OUT

REF

NC
NC

10
8
1

7

Battery BMON Discrete Current Sense (IP0R)

Gain: 11.82x, EDP: 24 A
Rsense: 0.005 (R7060)

Vsense: 120 mV, Range: 25.37 A

CALPE: AMUX_B0

122 119 68

29
53

PPDCIN_G3H

NOSTUFF

R5684

0

21

5%
1/10W
MF-LF

603

GND_CALPE_AVSS

121 94 76 58 55 54 53

PLACE_NEAR=U7800.E12:15MM

GND_CALPE_AVSS

121 94 76 58 55 54 53

T139 Current Sense (IF3C)

Gain: 200x, EDP: 0.06 A

56 121 82

OUTIN

116

58 56 53

116

PP3V3_G3H_RTC_X

PP3V3_G3H_DFR

Rsense: 0.05 (R5660) or Rsense SHORT
Vsense: 3 mV, Range: 0.25 A
EADC2: CH7

SENSOR:DEV

R5660

0.005

121

1%

1/3W

MF

0306

1

ISNS_T139_P

ISNS_T139_N

432

CRITICAL

PP3V3_G3SSW_SNS

53 54 55
56 58 116

LOADISNS

2
3

4
5

INA210A

IN+

CRITICAL

IN+

IN­IN-

6

V+

U5660

UQFN

200x

GND

9

OUT

REF

NC
NC

LOADISNS

BYPASS=U5660.6::5MM

1

C5660

0.1UF

10%

6.3V

2

CERM-X5R
0201

10

ISNS_PP3V3S0_IOUT

8
1

7

NC
NC

1

R5661

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5660.10:5MM

LOADISNS

PLACE_NEAR=U5710.5:5MM

R5666

45.3K

1/20W

1%
MF

201

21

EADC2_PP3V3S5_T139_ISENSE

1

C5666

2.2UF

20%

6.3V

2

X5R-CERM
0201

LOADISNS

PLACE_NEAR=U5710.5:5MM

GND_EADC2_COM

OUT

121 58 56 54

B

56

A

119 115

PPBUS_G3H

CHGR_CSO_R_P

121 68

R5681

DO NOT CONNECT PIN 1 TO PIN 2 DIRECTLY

CONNECT U5670 PIN 1 TO PIN 2 NEAR R5681

CHGR_CSO_R_N

121 68

R5682

422

1/20W

201

R5683

0

LOADISNS

1

PLACE_NEAR=R7060.4:15MM

422

1%

1/20W

MF

201

2

CHGR_CSO_BMON_R_P

CKPLUS_WAIVE=NDIFPR_BADTERM

1

PLACE_NEAR=R7060.3:15MM

1%
MF

NO_XNET_CONNECTION=1

2

LOADISNS

CHGR_CSO_BMON_R_N

5%
1/10W
MF-LF

603

LOADISNS

NO_XNET_CONNECTION=1

CKPLUS_WAIVE=PDIFPR_BADTERM
CKPLUS_WAIVE=PDIFPR_BADTERM

PPBUS_G3H_R_IP0R

21

LOADISNS

BYPASS=U5670.7::10MM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LOADISNS

7

V+

1

C5671

0.1UF

10%
25V

2

X6S-CERM
0201

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

R5602,R5612,R5622,R5632,R5679

LOADRC:NO5117S0008

U5670

LTC6102AP

DFN

2

-INF

-INS

+IN

CRITICAL

V-

5

1
8

VREG

SHDN

THM
PAD

9

OUT

6
4
3

CHGR_CSO_BMON_VREG

PMU_PBUS_BMON_DIS_ISENSE

1%

1/20W

MF

201

1

2

R5679

4.99K

LOADRC:YES

PLACE_NEAR=U7800.D13:15MM

59

OUT

PLACE_NEAR=U7800.D13:15MM

1

C5679

2.2UF

20%

6.3V
X5R-CERM

2

0201

LOADISNS

GND_CALPE_AVSS

SYNC_MASTER=RAYMOND SYNC_DATE=10/13/2017

PAGE TITLE

A

Power Sensors Extended 1

DRAWING NUMBER

051-02643

Apple Inc.

121 94 76 58 55 54 53

BOM_COST_GROUP=SENSORS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

4.0.0

BRANCH

evt-0

PAGE

56 OF 200

SHEET

55 OF 131

SIZE

D

8

67

35 4

2

1

D

116

116

678

Thunderbolt TBT RIGHT Current Sense (IURC)

Gain: 200x. EDP: 0.6 A
Rsense: 0.025 (R5720) or Rsense SHORT
Vsense: 15 mV, Range: 0.66 A
EADC2: CH2

PP3V3_S0SW_TBT_T

SENSOR:DEV

R5720

CRITICAL

PP3V3_S0SW_TBT_T_SNS

0.025

1%

1/3W

MF

0306

PLACE_NEAR=U5720.2:10MM

1

ISNS_TBT_T_P

ISNS_TBT_T_N

432

PP3V3_G3SSW_SNS

53 54 55 56 58 116

LOADISNS

6

V+

U5720

INA210A

2

IN+

3

IN+

IN-

4
5

IN-

UQFN

CRITICAL

200x

GND

9

OUT

REF

NC
NC

10

8
1

7

BYPASS=U5720.6::5MM

LOADISNS

1

C5720

0.1UF

10%

6.3V

2

CERM-X5R
0201

ISNS_TBT_T_IOUT

1

R5725

NC
NC

20K

5%
1/20W
MF

2

201

NOSTUFF

PLACE_NEAR=U5720.10:5MM

LOADISNS

PLACE_NEAR=U5710.24:5MM

R5729

45.3K

1%

1/20W

MF

201

EADC2_TBT_T_ISENSE

21

1

C5729

2.2UF

20%

6.3V
X5R

2

0201

LOADISNS

PLACE_NEAR=U5710.24:5MM

GND_EADC2_COM

56

3 245

1

CPU GT Current Sense (ICTC)

Gain: 240.78x, EDP: 32 A
Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375
Vsense: 12 mV, Range:36.55 A
EADC1: CH3

R5745

72

CPUGT_ISNS1_P

IN

PLACE_NEAR=R7410.4:5MM

NO_XNET_CONNECTION=1

LOADISNS

72

CPUGT_ISNS2_P

IN

PLACE_NEAR=R7420.4:5MM

NO_XNET_CONNECTION=1

LOADISNS

LOADISNS

72

121 58 56 55 54

CPUGT_ISNS1_N

IN

PLACE_NEAR=R7410.3:5MM

NO_XNET_CONNECTION=1

4.42K

0.1%

1/20W

MF

0201

R5746

4.42K

0.1%

1/20W

MF

0201

R5748

4.42K

0.1%

1/20W

MF

0201

21

CPUGT_ISNS_R_P

21

CPUGT_ISNS_R_N

121

21

LOADISNS

R5742

2.94K

LOADISNS

R5743

2.94K

1%

1/20W

MF

201

1%

1/20W

MF

201

116

21

CPUGT_ISNS_P

1

R5744

1.24M

1%
1/20W
MF
0201

2

NO_XNET_CONNECTION=1

CPUGT_ISNS_N

21

LOADISNS

PP3V3_G3SSW_SNS

LOADISNS

1

3

52

V+

V-

R5741

1.24M

1%

1/20W

MF

0201

CRITICAL

U5740

ISL28133

SC70-5

4

CPUGT_ISUM_IOUT

1

R5740

20K

5%
1/20W
MF

2

201

21

NO_XNET_CONNECTION=1

PLACE_NEAR=U5740.4:5MM

BYPASS=U5740.5::5MM

LOADISNS

1

C5740

0.1UF

10%

6.3V

2

X7R
0201

LOADISNS

R5749

45.3K

1%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U5700.1:15MM

EADC1_CPUGT_ISENSE

21

1

C5749

2.2UF

20%

2

6.3V
X5R-CERM
0201

LOADISNS

PLACE_NEAR=U5700.1:15MM

GND_EADC1_COM

D

56

58 56 55 53

C

B

A

Thunderbolt TBT LEFT Current Sense (IULC)

Gain: 200x. EDP: 0.6 A
Rsense: 0.025 (R5730) or Rsense SHORT
Vsense: 15 mV, Range: 0.66 A
EADC1: CH7

116

116

PP3V3_S0SW_TBT_X

PP3V3_S0SW_TBT_X_SNS

Calpe 3V3 Current Sense (ISLC)

Gain: 200x, EDP: 8 A
RSENSE: 0.001 (R5750)
Vsense: 8 mV, Range: 15 A
SMC ADC:07

PP3V3_G3H_T

116

PP3V3_G3H_SOCPMU

116

54 56 116

121 58

121 58

58 56 55 53

PP5V_G3S

BYPASS=U5700.12::5MM

53

IN

55

IN

56

56

IN

56

IN

56

SENSOR:DEV

R5730

0.025

1%

1/3W

MF

0306

1

CRITICAL

R5750

0.001

1/2W

1%

0306

121

MF

LOADISNS

R5700

0

21

PP5V_EADC1_AVDD

5%

1/20W

MF

0201

BYPASS=U5700.12::5MM

EADC1_LCDBKLT_ISENSE

EADC1_LCDPANEL_ISENSE

EADC1_VCCIO_ISENSE
EADC1_CPUGT_ISENSE
EADC1_CPUGT_VSENSE
EADC1_CPUSA_ISENSE
EADC1_CPUSA_VSENSE

EADC1_TBT_X_ISENSE

VOLTAGE=0V

GND_EADC1_COM

PLACE_NEAR=U5700.6:1MM

PLACE_NEAR=U5700.25:1MM

53 54 55 56 58 116

PLACE_NEAR=U5730.2:10MM

PP3V3_G3SSW_SNS

ISNS_TBT_X_P

ISNS_TBT_X_N

432

PLACE_NEAR=U5750.2:5:10MM

PLACE_NEAR=R5750.4:5MM

ISNS_CALPE_P

121

432

MAKE_BASE=TRUE

ISNS_CALPE_N

1

PLACE_NEAR=R5750.3:5MM

MAKE_BASE=TRUE

PLACE_NEAR=U5750.4:3:10MM

1

C5701

0.1UF

10%

10V

2

X5R-CERM

0201

1

C5702

4.7UF

20%

10V

2

X5R-CERM
0402

BYPASS=U5700.12::5MM

LOADISNS

XW5700

SM

2 1

LOADISNS

22

CH0

23

CH1

24

CH2

1

CH3

2

CH4

3

CH5

4

CH6

5

CH7
COM

6

LOADISNS

U5730

2

IN+

3

IN+

4

IN-

5

IN-

PP3V3_G3SSW_SNS

53 54 55 56 58 116

INA210A

UQFN

CRITICAL

200x

IN+

2
3

IN+

IN-

4

IN-

5

EADC1

13

12

AVDD DVDD

U5700

LTC2309

QFN

CRITICAL

LOADISNS

GND

9

11

10

20

19

18

BYPASS=U5700.8::5MM

BYPASS=U5730.6::5MM

1

C5730

6

V+

GND

9

OUT

REF

NC
NC

6

V+

10
8
1

7

0.1UF

10%

6.3V

2

CERM-X5R
0201

NC
NC

U5750

INA210A

UQFN

CRITICAL

200x

GND

9

1

C5703

0.1UF

10%

10V

2

X5R-CERM
0201

LOADISNS

21

BYPASS=U5700.21::5MM

AD0
AD1

SDA

SCL

VREF

REFCOMP

THRM

PAD

25

OUT

REF

NC
NC

1

2

(Write: 0x10 Read: 0x11)

14
15

17
16

7

8

LOADISNS

I2C_SNS0_S0_5V_SDA
I2C_SNS0_S0_5V_SCL

PP2V5_ADC1_VREF

ADC1_REFCOMP

1

C5705

0.1UF

10%

6.3V

2

CERM-X5R
0201

LOADISNS

ISNS_TBT_X_IOUT

1

R5735

20K

5%
1/20W
MF

2

201

NOSTUFF

PLACE_NEAR=U5730.10:5MM

BYPASS=U5750.6::5MM

1

C5750

0.1UF

10%

6.3V

2

CERM-X5R
0201

ISNS_CALPE_IOUT

10
8
1

NC

7

NC

C5704

4.7UF

20%

10V

X5R-CERM
0402

LOADISNS

BYPASS=U5700.21::5MM

1

C5700

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C5706

10UF

20%

10V

2

X5R-CERM
0402-10

LOADISNS

BYPASS=U5700.7::5MM

LOADISNS

BYPASS=U5700.8::5MM

LOADISNS

PLACE_NEAR=U5700.5:5MM

R5739

45.3K

1/20W

1%
MF

201

21

EADC1_TBT_X_ISENSE

PLACE_NEAR=U3900.AC5:5MM

R5759

7.5K

1/20W

PLACE_NEAR=U3900.AC5:5MM

51

IN

1%
MF

201

21

121 58 56 55 54

1

C5739

2.2UF

20%

6.3V

2

X5R-CERM
0201

PLACE_NEAR=U5700.5:5MM

LOADISNS

GND_EADC1_COM

SMC_P3V3_CAPLE_ISENSE

R5755

4.99K

1%

1/20W

MF

201

1

2

1

C5759

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

LOADISNS

54 56 116

PP5V_G3S

BYPASS=U5710.12::=5MM

BYPASS=U5710.12::5MM

54

54

58

121 58

58

58

55

EADC2_DDR2V5_ISENSE

IN

EADC2_PCH_1V0_ISENSE

IN

EADC2_TBT_T_ISENSE

56

EADC2_GPU_VDDCI_ISENSE

IN

EADC2_GPU_VDDCI_VSENSE

IN

EADC2_GPU_FBIC_ISENSE

IN

EADC2_GPU_1V8_ISENSE

IN

EADC2_PP3V3S5_T139_ISENSE

IN

GND_EADC2_COM

VOLTAGE=0V

56

58 56 55 53

59

OUT

PLACE_NEAR=U3900.AC5:5MM

R5710

0

21

5%

1/20W

MF

0201

1

C5711

0.1UF

10%

2

6.3V

CERM-X5R
0201

LOADISNS

BYPASS=U5710.12::5MM

XW5710

SM

2 1

PLACE_NEAR=U5710.6:1MM

PLACE_NEAR=U5710.25:1MM

72

CPUGT_ISNS2_N

IN

PLACE_NEAR=R7420.3:5MM

CPU SA Current Sense (ICSC)

Gain: 100x, EDP: 11.1 A
Rsense: 0.002 (R7370)
Vsense: 22.2 mV, Range: 16.5 A
EADC1: CH5

CPU VCCIO Current Sense (ICIC)

Gain: 100x, EDP: 6.4 A
Rsense: 0.003 (R8102)
Vsense: 19.2 mV, Range: 11 A
EADC1: CH2

58 54 53 46 39

EADC2

PP5V_EADC2_AVDD

1

C5712

4.7UF

20%

2

10V

X5R-CERM
0402

LOADISNS

AVDD DVDD

22

CH0
23
24

1
2
3
4
5

6

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CRITICAL

LOADISNS

9

10

LOADISNS

NO_XNET_CONNECTION=1

121 71

121 71

121 78

121 78

1

C5713

0.1UF

10%

10V

2

X5R-CERM
0201

LOADISNS

12

13

BYPASS=U5710.21::5MM

21

U5710

LTC2309

QFN

GND

20

19

18

11

BYPASS=U5710.10::5MM

AD0
AD1

SDA

SCL

VREF

REFCOMP

THRM

PAD

25

14
15

17
16

7

ADC2_REFCOMP

8

1

2

LOADISNS

R5757

4.42K

0.1%

1/20W

0201

IN

IN

IN

IN

R5712

1/20W 201

I2C_SNS0_S0_5V_SDA
I2C_SNS0_S0_5V_SCL

PP2V5_ADC2_VREF

C5715

0.1UF

10%

6.3V

CERM-X5R
0201

21

MF

CPUSA_ISNS_P

PLACE_NEAR=R7370.3:10MM

CPUSA_ISNS_N

PLACE_NEAR=R7370.4:10MM

ISNS_CPUVCCIO_POS

PLACE_NEAR=R8102.3:5MM

ISNS_CPUVCCIO_NEG

PLACE_NEAR=R8102.4:5MM

BYPASS=U5710.21::5MM

1

C5714

4.7UF

20%

10V

2

X5R-CERM
0402

LOADISNS

EADC2_AD0

100K

PP5V_G3S

21

BOMOPTION=NOSTUFF

MF5%

1

C5716

10UF

20%

10V

2

X5R-CERM
0402-10

BYPASS=U5710.10::5MM

LOADISNS

53 54 55 56 58 116

PP3V3_G3SSW_SNS

LOADISNS

6

V+

U5770

IN+

2
3

IN+

IN-

4

IN-

5

PP3V3_G3SSW_SNS

53 54 55 56 58
116

LOADISNS

INA214A

UQFN

CRITICAL

100x

GND

9

6

V+

OUT

REF

NC
NC

10
8
1

7

U5780

IN+

2
3

IN+

IN-

4

IN-

5

(Write: 0x12 Read: 0x13)

54 56 116

51 51

BIBI

51

IN

1

C5710

2.2UF

20%

2

6.3V

X5R-CERM
0201

BYPASS=U5710.7::5MM

LOADISNS

INA214A

UQFN

CRITICAL

100x

GND

9

BOM_COST_GROUP=SENSORS

OUT

REF

NC
NC

10
8
1

7

LOADISNS

LOADISNS

BYPASS=U5770.6::5MM

C5770

1

0.1UF

10%

2

6.3V
X7R
0201

ISNS_CPUSA_IOUT

1

R5775

NC
NC

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5770.10:5MM

LOADISNS

BYPASS=U5780.6::5MM

1

C5780

0.1UF

10%

2

6.3V
X7R
0201

ISNS_VCCIO_IOUT

1

R5785

NC
NC

20K

5%
1/20W
MF
201

2

NOSTUFF

LOADISNS

PLACE_NEAR=U5700.3:5MM

R5779

45.3K

1%

1/20W

MF

201

EADC1_CPUSA_ISENSE

21

C5779

1

2.2UF

20%

2

6.3V
X5R-CERM
0201

PLACE_NEAR=U5700.3:5MM

GND_EADC1_COM

56

LOADISNS

58 56 55 53

LOADISNS

R5789

45.3K

1%

1/20W

MF

201

SYNC_MASTER=RAYMOND SYNC_DATE=10/13/2017

PAGE TITLE

PLACE_NEAR=U5700.24:5MM

21

EADC1_VCCIO_ISENSE

1

C5789

2.2UF

20%

2

6.3V
X5R-CERM
0201

GND_EADC1_COM

56

LOADISNS

PLACE_NEAR=U5700.24:5MM

58 56 55 53

Power Sensors Extended 2

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

57 OF 200

SHEET

56 OF 131

C

B

A

8

67

35 4

2

1

D

THERMAL DIODE: VRAM PROXIMITY (KEY )

Place Q5877 Bottom,underVRAM shiled can, but not within 2mm of any IC

TSNS_T1_DX7_P

Q5877.3:2MM

3

1

Q5877

BC846BLP

DFN1006H4-3

1

C5877

100PF

5%
50V 0402

2

C0G

NO_XNET_CONNECTION=1

2

TSNS_T1_DX7_N

THERMAL DIODE: GPU ANALOG DIE (KEY TA0P)

57

57

678

Thermal Sensor A:

PP1V8_S5

80

Thunderbolt Die, Airflow Left

U5850 I2C Address:TMP461 A1->Floating A0->Floating 0X98/0X99

Thermal Diode: TBT Die (TTLD)

Placement Note:
The P leg connects to THERMDA pin of the TBT
chip, the N leg connect to pin AC22.

28

27

BI

BI

TBTTHMSNS_X_D1_P

TBTTHMSNS_X_D1_N

TBTTHMSNS_X_D1_P

MAKE_BASE=TRUE

TBTTHMSNS_X_D1_N

MAKE_BASE=TRUE

Note: Use GND pin AC22 on U2800 for N leg.

3 245

R5850

47

21

5%

1/20W

MF

201

PLACE_NEAR=U5850.2:5MM

C5851

2200PF

X7R-CERM

PLACE_NEAR=U5850.3:5MM

PP1V8_S5_TBTTHMSNS_X_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

1

10%
10V

2

2

0201

NC
NC

D+

3

D-

5

A0

10

A1 THERM*

CRITICAL

1

V+

U5850

TMP461

QFN

ALERT*/THERM2*

SCL
SDA

BYPASS=U5850.1::5MM

C5850

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

9
8
7
4

I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA

NC
NC

1

51

BI

D

51

BI

C

Connect GPU Analog Die to U5870 channel 8

GPU Digital DIE TG0D:

U5880 I2C Address:TMP461 A0->Floating A1->GND 0X92/0X93

PP1V8_S5

57 80

GPU_TDIODE_P

103

PLACE_NEAR=U5880.2:5MM

GPU_TDIODE_N

103

Note: Use GND pin AC22 on UB000 for N leg.

PLACE_NEAR=U5880.3:5MM

R5890

47

5%

1/20W

MF

201

C5898

2200PF

X7R-CERM

PP1V8_S5_GPUTHMSNS_R

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

1

10%
10V

2

0201

NC

CRITICAL

1

V+

U5880

TMP461

QFN

2

D+

3

D-

5

A0

10

A1 THERM*

ALERT*/THERM2*

SCL

SDA

Thermal Sensor C:
Thunderbolt Die, Air Flow Right

U5800 I2C Address:TMP461 A1->Floating A0->GND 0X96/0X97

Thermal Diode: TBT Die (TTRD)

Placement Note:

The P leg connects to THERMDA pin of the TBT
chip, the N leg connect to pin AC22.

BYPASS=U5880.1::5MM

1

C5890

0.1UF

10%

6.3V

2

CERM-X5R
0201

I2C_SNS1_S0_SCL

9

I2C_SNS1_S0_SDA

8
7
4

NC
NC

GND

6

Thermal Diode: Airflow Left Proximity (TaLC)

Placement Note:
Place U5850 on the TOP side, on the left portion

R5800

47

5%
MF

201

C5801

2200PF

21

PP1V8_S5_TBTTHMSNS_T_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

10%
10V

X7R-CERM

0201

1

2

NC

PP1V8_S5

80

1/20W

105

106

BI

BI

57 51

57 51

TBTTHMSNS_T_D1_P

BI

TBTTHMSNS_T_D1_N

BI

Note: Use GND pin AC22 on UB000 for N leg.

TBTTHMSNS_T_D1_P

MAKE_BASE=TRUE

TBTTHMSNS_T_D1_N

MAKE_BASE=TRUE

PLACE_NEAR=U5800.2:5MM

PLACE_NEAR=U5800.3:5MM

of the board, 1" to the right of USB connector.

BYPASS=U5800.1::5MM

1

C5800

0.1UF

10%

6.3V

2

CERM-X5R

1

CRITICAL

V+

0201

U5800

TMP461

QFN

I2C_SNS1_S0_SCL

2

D+

3

D-

5

A0

10

A1 THERM*

ALERT*/THERM2*

GND

6

SCL

SDA

9

I2C_SNS1_S0_SDA

8
7
4

NC
NC

51

BI

51

BI

C

B

THERMAL DIODE: CPU PROX (KEY TC0P)

Placement Note:

Place Q5871 under the CPU ON BOTTOM SIDE

TSNS_T1_DX1_P

Q5871.3:2MM

3

1

Q5871

BC846BLP

DFN1006H4-3

1

C5871

100PF

5%

0201

25V
C0G

2

NO_XNET_CONNECTION=1

2

TSNS_T1_DX1_N

THERMAL DIODE: FIN STACK RIGHT (KEY TH1H)

Placement Note:

Place Q5873 AT THE CORNER NEAR RIGHT FAN, ON THE TOP SIDE

TSNS_T1_DX3_P

Q5873.3:2MM

3

1

Q5873

BC846BLP

DFN1006H4-3

C5873

1

100PF

5%
25V 0201
C0G

2

NO_XNET_CONNECTION=1

2

TSNS_T1_DX3_N

57

57

57

57

GND

6

THERMAL DIODE: FIN STACK LEFT (KEY TH2H)

Placement Note:

Place Q5872,AIRFLOW THERMAL INDICATOR,ABOVETHE X100, ON THE TOP SIDE

TSNS_T1_DX2_P

Q5872.3:2MM

3

1

Q5872

BC846BLP

DFN1006H4-3

C5872

1

100PF

5%

0201

25V
C0G

2

NO_XNET_CONNECTION=1

2

TSNS_T1_DX2_N

THERMAL DIODE: Memory Proximity (KEY TM0P)

Place Q5874 between two rows of Memory devices, between channel A and CHANNEHL b PN BOTTOM SIDES

TSNS_T1_DX4_P

Q5874.3:2MM

3

1

Q5874

BC846BLP

DFN1006H4-3

C5874

1

100PF

0402

5%
50V
C0G

2

NO_XNET_CONNECTION=1

2

TSNS_T1_DX4_N

57

57

57

57

57

TSNS_T1_DX1_N

TSNS_T1_DX2_N

57

57

TSNS_T1_DX3_N

57

TSNS_T1_DX4_N

57

TSNS_T1_DX5_N

57

57

57

57

57

57

57

TSNS_T1_DX1_P
TSNS_T1_DX2_P
TSNS_T1_DX3_P
TSNS_T1_DX4_P
TSNS_T1_DX5_P
TSNS_T1_DX6_P
TSNS_T1_DX7_P

XW5801
XW5802
XW5803
XW5804
XW5805

PP1V8_S5

57 80

MLB THERMAL SENSE 1 (TMP468)

I2C DEVICE ADDRESS 0X48:
I2C WRITE 0X90, I2C READ 0X91

21

SM

NO_XNET_CONNECTION=1

21

SM

NO_XNET_CONNECTION=1

SM

21

NO_XNET_CONNECTION=1

SM

21

NO_XNET_CONNECTION=1

SM

21

NO_XNET_CONNECTION=1

U5870.A3:10MM
U5870.A3:10MM
U5870.A3:10MM

U5870.A3:10MM
U5870.A3:10MM

NOSTUFF

U5870.B1:10MM

1
2

C5880

2.2PF

+/-0.1PF
C0G-CERM
25V
0201

NO_XNET_CONNECTION=1

NOSTUFF

U5870.B1:10MM

C5881

1

2.2PF

2

+/-0.1PF
C0G-CERM
25V
0201

NO_XNET_CONNECTION=1

R5870

10

5%

1/20W

MF

201

PP1V8_S5_CPUTHMSNS_R

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1020

VOLTAGE=1.8V

TSNS_T1_DN

CPUTHMSNS_ADD

NOSTUFF

U5870.B1:10MM

C5882

1

2.2PF

2

+/-0.1PF
C0G-CERM
25V
0201

NO_XNET_CONNECTION=1

Thermal Diode: Airflow Right Proximity (TaRC)

Placement Note:
Place U5800 on the TOP side, on the left portion
of the board, 1" to the right of USB connector.

R5880

1

100K

5%

1/20W

MF

201

2

A1
B1
C1
D1
A2
B2
C2
D2

A3
B4

D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+

D-

ADD

D3

V+

U5870

TMP468

DSBGA

CRITICAL

THERM2*

GND

A4

SCL

SDA

THERM*

1

C5870

0.1UF

10%

2

6.3V
CERM-X5R
0201

D4
C4
C3
B3

I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA

NC
NC

IN

BI

57 51

57 51

B

A

THERMAL DIODE: X100 PROXIMITY (KEY TW0P)

Place Q5875 near X100 on bottom

TSNS_T1_DX5_P TSNS_T1_DX6_P

Q5875.3:2MM

3

1

Q5875

BC846BLP

DFN1006H4-3

2

1

C5875

100PF

5%
50V

0402

C0G

2

NO_XNET_CONNECTION=1

57 57

THERMAL DIODE: GPU PROXIMITY(KEY )

Place Q5876 near GPU, Top side

Q5876.3:2MM

3

1

Q5876

BC846BLP

DFN1006H4-3

1

C5876

100PF

5%
50V

0402

C0G

2

NO_XNET_CONNECTION=1

2

TSNS_T1_DX6_NTSNS_T1_DX5_N

TSNS_T1_DX6_N

57

TSNS_T1_DX7_N

57

57 57

XW5806

NO_XNET_CONNECTION=1

XW5807

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

SM

21

SM

21

U5870.A3:10MM

U5870.A3:10MM

MLB PROX 2 is read from the on-chip temp sensors U5870

U5870.A3:10MM

NOSTUFF

1

C5891

2.2PF

2

+/-0.1PF
C0G-CERM
25V
0201

Place U5870 near Calpe (U7800)

BOM_COST_GROUP=SENSORS

SYNC_MASTER=RAYMOND SYNC_DATE=06/28/2017

PAGE TITLE

Thermal Sensors

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

58 OF 200

SHEET

57 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

CPU Core Voltage Sense (VCAC)

CALPE : AMUX-A1

PPVCC_S0_CPU

6 8 115

XW5900

SM

21

PLACE_NEAR=R7210.2:5 MM

CPUVSENSE_IN

PLACE_NEAR=U7800.A15:5MM

R5900

CPU GT Voltage Sense (VCTC)

EADC1: CH4

XW5910

SM

CPUGTVSENSE_IN

PPVCCGT_S0_CPU

8 115

PLACE_NEAR=R7410.2:5 MM

21

PLACE_NEAR=U5700.2:5MM

4.53K

1/20W

R5910

45.3K

1%
MF

201

1%

1/20W

MF

201

21

PMU_CPU_VSENSE

C5900

1

2.2UF

20%

6.3V

2

X5R-CERM
0201

PLACE_NEAR=U7800.A15:5MM

GND_CALPE_AVSS

EADC1_CPUGT_VSENSE

21

1

C5910

2.2UF

20%

2

6.3V

X5R-CERM
0201

PLACE_NEAR=U5700.2:5MM

GND_EADC1_COM

CPU SA Voltage Sense (VCSC)

EADC1: CH6

XW5930

SM

PPVCCSA_S0_CPU

OUT OUT

OUT

121 59 121 56

121 94 76 58 55 54 53

121 56

58 56 55 53

8 115

21

CPUSAVSENSE_IN

R5930

45.3K

1%

1/20W

MF

201

21

EADC1_CPUSA_VSENSE

1

C5930

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_EADC1_COM

GPU SENSORS

GPU CORE Voltage Sense (VG0C)

CALPE: AMUX-A3

XW5980

(PRODUCTION)

PPVCORE_S0_GPU

96 115 124

PLACE_NEAR=UA000.AR13:2 MM

58 56 55 53

SM

GPUCOREVSENSE_IN

21

R5980

4.53K

1/20W

PLACE_NEAR=U7800.B14:5MM

PMU_GPU_CORE_VSENSE

21

1%
MF

201

PLACE_NEAR=U7800.B14:5MM

1

C5980

2.2UF

20%

2

6.3V

X5R-CERM
0201

GND_CALPE_AVSS

VOLTAGE=0V

OUT

121

121 59

D

94 76 58 55 54 53

GPU VDDCI Voltage Sense (VG2C)

EADC2: CH4

PPVDDCI_S0_GPU

96 115 124

XW5982

SM

GPUVDDCIVSENSE_IN

21

PLACE_NEAR=U5710.2:5MM

R5982

45.3K

1%

1/20W

MF

201

21

EADC2_GPU_VDDCI_VSENSE

C5983

1

2.2UF

20%

2

6.3V

X5R-CERM
0201

PLACE_NEAR=U5710.2:5MM

GND_EADC2_COM

OUT

121 56

121 58 56 55 54

C

B

A

GPU CORE Current Sense (IG0C)
no longer lives on this page
it's merged with the PCC circuit
on CSA 99

Gain: 154.87x, EDP: 78 A
Rsense: 3X OF 0.00075 (RA651,RA641,RA346)
Vsense: 19.5 mV, Range: 109 A
CALPE : AMUX A2

GPU VDDCI Current Sense (IG2C)

Gain: 100x, EDP: 10 A

Rsense: 0.003 (RA368)

Vsense: 20 mV, Range: 16.5 A

EADC2: CH3

121 98

121 98

GPU 1V8 Current Sense (IG3C)

Gain: 200x, EDP: 1.5 A
Rsense: 0.005 (R5950)

Vsense: 7.5 mV, Range: 3 A
EADC2: CH6

115

115
122

PP1V8_GPU

R5950

0.005

SENSOR:DEV

121

PP1V8_S0_GPU

53 54 55 56 58 116

PP3V3_G3SSW_SNS

PLACE_NEAR=XWA353.1:5MM

VDDCIS0_CS_P

IN

VDDCIS0_CS_N

IN

PLACE_NEAR=XWA354.1:5MM

53 54 55 56 58 116

121

ISNS_GPU1V8_P

1

PLACE_NEAR=U5950.3:10MM

1/3W

1%

0306

MF

ISNS_GPU1V8_N

PLACE_NEAR=U5950.4:10MM

432

LOADISNS

6

V+

U5940

IN+

2
3

IN+

IN-

4

IN-

5

PP3V3_G3SSW_SNS

LOADISNS

IN+

2
3

IN+

INA214A

UQFN

CRITICAL

100x

GND

9

6

V+

U5950

INA210A

UQFN

CRITICAL

200x

IN-

4

IN-

5

GND

9

OUT

REF

NC
NC

OUT

REF

NC
NC

LOADISNS

BYPASS=U5940.3::5MM

C5940

1

0.1UF

10%

6.3V

2

X7R
0201

ISNS_GPUVDDCI_IOUT

10
8
1

NC

7

NC

1

R5940

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5940.6:5MM

LOADISNS

BYPASS=U5950.3::5MM

C5950

1

0.1UF

10%

2

6.3V

CERM-X5R
0201

ISNS_GPU1V8_IOUT

10
8
1

NC

7

NC

1

2

NOSTUFF

PLACE_NEAR=U5950.6:5MM

R5951

20K

5%
1/20W
MF
201

LOADISNS

PLACE_NEAR=U5710.1:5MM

R5941

45.3K

1%

1/20W

MF

201

EADC2_GPU_VDDCI_ISENSE

21

LOADISNS

C5941

1

2.2UF

20%

6.3V

2

X5R
0201

GND_EADC2_COM

PLACE_NEAR=U5710.4:5MM

LOADISNS

R5952

45.3K

1%

1/20W

MF

201

PLACE_NEAR=U5710.4:5MM

EADC2_GPU_1V8_ISENSE

21

PLACE_NEAR=U5710.1:5MM

1

C5951

2.2UF

20%

6.3V

2

X5R
0201

LOADISNS

GND_EADC2_COM

OUT

OUT

56

121 58 56 55 54

56

GPU FB Current Sense (IG1C)

Gain: 100x, EDP: 13 A
Rsense: 0.002 (RA300)
Vsense: 26 mV, Range: 18.7 A
CALPE : AMUX A4

121 98

121 98

GPU FB IC Current Sense (IG4C)

Gain: 200x, EDP: 4.8 A
Rsense: 0.005 (R5970)
Vsense: 10 mV, Range: 3 A
EADC2: CH5

PP1V5R1V35_S0_GPU_MEM

115

SENSOR:DEV

PP1V5R1V35_S0_GPU_IC

115

PLACE_NEAR=RA300.3:10MM

GPUFB_CS_P

IN

GPUFB_CS_N

IN

PLACE_NEAR=RA300.4:10MM

PLACE_NEAR=U5970.3:5:10MM

R5970

0.005

1/3W

121

0306

ISNS_GPUFBIC_P

1

1%
MF

ISNS_GPUFBIC_N

432

PLACE_NEAR=U5970.4:3:10MM

PP3V3_G3SSW_SNS

53 54 55 56 58 116

LOADISNS

6

V+

U5960

IN+

2
3

IN+

IN-

4

IN-

5

PLACE_NEAR=R5970.3:10MM

INA214A

UQFN

CRITICAL

100x

GND

9

PP3V3_G3SSW_SNS

53 54 55 56 58 116

PLACE_NEAR=R5970.4:10MM

OUT

REF

NC
NC

LOADISNS

U5970

INA210A

IN+

2
3

4
5

CRITICAL

IN+

IN­IN-

ISNS_GPUFB_IOUT

10
8
1

NC

7

NC

6

V+

UQFN

200x

GND

9

OUT

REF

NC
NC

LOADISNS

BYPASS=U5960.3::5MM

C5960

1

0.1UF

10%

2

6.3V

X7R
0201

1

R5960

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5960.6:5MM

LOADISNS

BYPASS=U5970.3::5MM

C5970

1

0.1UF

10%

2

6.3V

CERM-X5R
0201

ISNS_GPUFBIC_IOUT

10
8
1

NC

7

NC

1

R5971

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5970.6:5MM

LOADISNS

R5961

7.5K

1/20W

21

1%
MF

201

LOADRC:YES

R5969

4.99K

PLACE_NEAR=U7800.C14:5MM

PMU_GPU_FB_ISENSE

1%

1/20W

MF

201

1

2

1

2

PLACE_NEAR=U7800.C14:5MM

LOADISNS

PLACE_NEAR=U5710.3:5MM

R5972

45.3K

1%

1/20W

MF

201

EADC2_GPU_FBIC_ISENSE

21

1

C5971

2.2UF

20%

2

6.3V

X5R-CERM
0201

GND_EADC2_COM

59

OUT

PLACE_NEAR=U7800.C14:5MM

C5969

2.2UF

20%

6.3V

X5R-CERM
0201

GND_CALPE_AVSS

PLACE_NEAR=U5710.3:5MM

LOADISNS

LOADISNS

OUT

56

C

121 94 76 58 55 54 53

B

121 58 56 55 54

GPU HIGH SIDE Current Sense (IG0R)

Gain: 200x, EDP: 4 A
Rsense: 0.002 (R5990) or Rsense SHORT

53 54 55 56 58 116

Vsense: 8 mV, Range: 7.82 A
SMC ADC: 05

(PRODUCTION)

PPBUS_G3H

115

CRITICAL

1%
1W

CYN

0612

1

432

R5990

0.002

PPBUS_HS_GPU

115

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

121 58 56 55 54

PLACE_NEAR=R5990.4:5MM

121

ISNS_GPU_HS_P

121

ISNS_GPU_HS_N

PLACE_NEAR=R5990.3:5MM

R5969

PP3V3_G3SSW_SNS

IN+

2
3

IN+

IN-

4

IN-

5

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BYPASS=U5990.3::5MM

C5990

1

0.1UF

6

V+

U5990

INA210A

UQFN

OUT

10

10%

6.3V

2

CERM-X5R
0201

ISNS_GPU_HS_IOUT

CRITICAL

8

200x

GND

9

REF

NC
NC

1

NC

7

NC

LOADRC:NO117S0008 1

BOM_COST_GROUP=SENSORS

R5992

7.5K

1%

1/20W

MF

PLACE_NEAR=U3900.AH2:5MM

SYNC_MASTER=RAYMOND SYNC_DATE=10/13/2017

PAGE TITLE

201

Power Sensor Extended 3

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=U3900.AH2:5MM

21

R5993

4.99K

SMC_GPU_HS_ISENSE

1

1%

1/20W

MF

201

2

Apple Inc.

59

OUT

PLACE_NEAR=U3900.AH2:5MM

1

C5992

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

59 OF 200

SHEET

58 OF 131

56 54 53 46 39

A

SIZE

D

8

67

35 4

2

1

D

FAN CONNECTOR

PP1V8_G3S

59 116 119

R6000

R6005

47K

5%

1/20W

MF

201

2

1

S G

119 39

119 39

NOSTUFF

R6001

100K

1/20W

201

SMC_FAN_0_PWM FAN_LT_PWM

IN

R6002

100K

1/20W

201

1

5%
MF

2

1

5%
MF

2

OUT

SMC_FAN_0_TACH

1

47K

5%

1/20W

MF

201

2

21

Q6000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

D

3

FAN_LT_TACH

678

3 245

1

H9M SMC ADC Assignments

MAKE_BASE=TRUE

121 53

DBG_FAN

121 53

116

PP5V_G3S

120 65

NC

NC

NC
NC

NC

120 65

J6000

F-RT-SM

6

1
2
3
4
5

7

FF14A-5C-R11DL-B-3HFF14A-5C-R11DL-B-3H

NC

NC

NC
NC

NC

DBG_FAN

J6001

F-RT-SM

6

1
2
3
4
5

7

53

53

53

58

54

56

77

77

77

77

77

77

77

77

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HS_ISENSE

MAKE_BASE=TRUE

SMC_P3V3_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_P3V3_CAPLE_ISENSE

CALPE AMUX Assignments

PMU_CPU_ISENSE
PMU_CPU_VSENSE
PMU_GPU_CORE_ISENSE
PMU_GPU_CORE_VSENSE
PMU_GPU_FB_ISENSE
PMU_P1V8_WLAN_ISENSE
PMU_CPUDDR_ISENSE
PMU_DDR1V2_ISENSE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HI_ISENSE
SMC_GPU_HS_ISENSE

SMC_P3V3_WLAN_ISENSE
SMC_P3V3_CAPLE_ISENSE

MAKE_BASE=TRUE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

39

39

39

39

39

39

39

39

PMU_CPU_ISENSE

MAKE_BASE=TRUE

PMU_CPU_VSENSE

MAKE_BASE=TRUE

PMU_GPU_CORE_ISENSE

MAKE_BASE=TRUE

PMU_GPU_CORE_VSENSE

MAKE_BASE=TRUE

PMU_GPU_FB_ISENSE

MAKE_BASE=TRUE

PMU_P1V8_WLAN_ISENSE

MAKE_BASE=TRUE

PMU_CPUDDR_ISENSE

MAKE_BASE=TRUE

PMU_DDR1V2_ISENSE

D

54

IN

IN

IN

IN

IN

IN

IN

IN

121 58

94

121 58

58

54

54

54

C

119 39

59 116 119

PP1V8_G3S

5%
MF

201

1

2

R6050

47K

1/20W

R6055

119 39

NOSTUFF

R6051

100K

1/20W

201

SMC_FAN_1_PWM FAN_RT_PWM

IN

1

5%
MF

2

SMC_FAN_1_TACH

OUT

47K

5%

1/20W

MF

201

21

FAN_RT_TACH

Q6050

1

S G

2

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

D

3

C

MAKE_BASE=TRUE

77 55

OUT IN

77

OUT

77

77

77

77

77

77

OUT

OUT

OUT

OUT

OUT

OUT

120 65

120 65

PMU_PBUS_BMON_DIS_ISENSE

PMU_PBUS_MAIN_SSD0_ISENSE
PMU_PBUS_MAIN_SSD1_ISENSE

PMU_P3V3_G3W_SSD0_ISENSE
PMU_P3V3_G3W_SSD1_ISENSE
PMU_3V3_X_HI_ISENSE

PMU_3V3_T_HI_ISENSE
PMU_OTHER5V_HI_ISENSE

PMU_PBUS_BMON_DIS_ISENSE

MAKE_BASE=TRUE

PMU_PBUS_MAIN_SSD0_ISENSE

MAKE_BASE=TRUE

PMU_PBUS_MAIN_SSD1_ISENSE

MAKE_BASE=TRUE

PMU_P3V3_G3W_SSD0_ISENSE

MAKE_BASE=TRUE

PMU_P3V3_G3W_SSD1_ISENSE

MAKE_BASE=TRUE

PMU_3V3_X_HI_ISENSE

MAKE_BASE=TRUE

PMU_3V3_T_HI_ISENSE

MAKE_BASE=TRUE

PMU_OTHER5V_HI_ISENSE

55

IN

55

IN

55

IN

55

IN

53

IN

53

IN

53

IN

B

R6052

100K

5%

1/20W

MF

201

1

2

B

A

8

SYNC_MASTER=RAYMOND SYNC_DATE=06/13/2017

PAGE TITLE

A

Fans/SMC/AMUX Support

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=FAN

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

60 OF 200

SHEET

59 OF 131

1

SIZE

D

678

3 245

1

D

D

C

C

B

B

A

8

DESIGN: X502/DEV_MLB_U
LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_DATE=03/15/2017SYNC_MASTER=j132-audio

PAGE TITLE

A

Audio Placeholder

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=AUDIO

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

62 OF 200

SHEET

60 OF 131

1

SIZE

D

AUDIO JACK CODEC I2C ADDRESS

678

3 245

1

D

AD1 AD0
GND
GND

1.8V

1.8V

GND

1.8V
GND

1.8V

ADDRESS
0x48 <-­0x49
0x4A
0x4B

PP1V8_AUDIO

61

MIN_NECK_WIDTH=0.1200

PP1V8_G3S

PP1V8_G3S

52 61 116

52 61 116

R6391

0

21

5%

1/20W

MF

0201

R6390

0

21

5%

1/20W

MF

0201

R6393

0

21

5%

1/20W

MF

0201

R6392

0

21

5%

1/20W

MF

0201

122 119 61

FERR-22-OHM-1A-0.055OHM

VOLTAGE=1.8V

PP1V8_L83_VL_R

PP1V8_L83_VCP_R

FERR-22-OHM-1A-0.055OHM

VOLTAGE=1.8V

GND_AUDIO_CODEC

L6301

21

0201

C6303

0.1UF

10%

16V

X7R-CERM

0402

L6300

21

0201

MAX CURRENT = 5mA

MIN_LINE_WIDTH=0.2000MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

1

C6301

2.2UF

10%

10V

2

X5R-CERM
0402

MAX CURRENT = 3mA

PP1V8_L83_VL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

PLACE_NEAR=U6300.A3:3 MM

1

2

PLACE_NEAR=U6300.B1:5 MM

MAX CURRENT = 100mA

PP1V8_L83_VCP

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

AUD_PWR_EN

77

PP3V3_G3S_T

61 116

L6361

FERR-470-OHM

L83_LDO_EN

21

0201

L6360

FERR-22-OHM-1A-0.055OHM

PP3V3_G3S_AUD_F

21

0201

BYPASS=U6360.A1:B2:3 MM

1

20%

2

10V

L83_VCP_FILT_GND

C6302

2.2UF

21

C6360

1.0UF

X5R-CERM

0201-1

VOLTAGE=3.3V

NOSTUFF

R6360

2 1

SHORT-8L-0.25MM-SM

47K

5%

1/20W

MF

201

XW6300

21

XW6301

SM

21

NOSTUFF

U6360

NCP160AMX180

4

3

XDFN-COMBO-THICKSTNCL

IN
EN

2

OUT

1

PP1V8_AUDIO

VOLTAGE=1.8V

61

D

EPADGND

5

BYPASS=U6360.A2:B2:3 MM

20%
10V

1

2

C6361

1.0UF

X5R-CERM

0201-1

GND_AUDIO_CODEC

122 119 61

C

B

A

64

64

L6302

PP3V3_G3S_T

61 116

64

122 119 61

64

R6351

0

IN

NOSTUFF

C6352

27PF

0201

IN

AUD_HS_MIC_N

5%

25V

C0G

1

2

2 1

5%

1/20W

MF

0201

NOSTUFF

C6351

3300PF

X7R-CERM

0201

R6352

0

2 1

5%

1/20W

MF

0201

64

64

NOSTUFF

1

1

10%

10V

2

R/C6550 FILTER TO ADDRESS OUT-OF-BAND

NOISE ISSUE SEEN ON EARLY HEADSETS

IN

IN

R6350

100K

5%
1/20W
MF
201

2

(SEE RADAR # 6210118)

AUD_RING_SENSE
AUD_TIP_SENSE

AUD_HP_PORT_L

OUT

GND_AUDIO_CODEC

OUT

AUD_HP_PORT_R

HS_MIC_PAUD_HS_MIC_P

HS_MIC_N

PP3V3_L83_VP

61

NOSTUFF

R6309

470K

5%

1/20W

MF

201

1

2

1

2

NOSTUFF

R6310

470K

5%
1/20W
MF
201

1

R6300

1K

5%
1/20W
MF
201

2

1

R6301

1K

5%
1/20W
MF
201

2

C6309

FERR-22-OHM-1A-0.055OHM

21

0201

PLACE_NEAR=U6300.D7:5 MM

64

64

64

64

4.7UF

20%

6.3V
X5R

0402

BI

BI

1

2

AUD_HP_SENSE_L

IN

AUD_HP_SENSE_R

IN

AUD_HP_PORT_CH_GND

AUD_HP_PORT_US_GND

L83_HSBIAS_FILT

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PLACE_NEAR=U6300.F3:5 MM

PLACE_NEAR=U6300.E3:5 MM

L83_HSBIAS_FILT_REF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

MAX CURRENT = 1mA

PP3V3_L83_VP

61

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C6304

1

10UF

20%

2

10V

X5R-CERM
0402-7

VOLTAGE=3.3V

D5
E5

G5

E2
E1

G2

D1

G4
G3

E4

E3

122 119 61

VP

HPSENSA
HPOUTA

HPSENSB

F5

HPOUTB

HS4

F1

HS_CLAMP2
HSIN+
HS3
HS_CLAMP1

F2

HSIN-

HS4_REF

F4

HS3_REF
RING_SENSE

TIP_SENSE

HSBIAS_FILT

F3

HSBIAS_FILT_REF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=0V

NC

D7C4A3

VL VA VCP

A7

VD_FILT

B1

CRITICAL

U6300

CS42L83A

WLCSP-SKT

SWIRE_CLK/ASP_SCLK

GNDL

B3

GND_AUDIO_CODEC

B6

C7

GNDHS GNDAGNDD

G1

D6

+VCP_FILT

-VCP_FILT
GNDCP

VL_SEL

DIGLDO_PDN*

INT*

WAKE*

RESET*

SPDIF_TX

SWIRE_SEL

ASP_LRCK/FSYNC

SWIRE_SD/ASP_SDIN

ASP_SDOUT

AD0
AD1

SDA

SCL

FLYP
FLYC
FLYN

FILT_P

D2

C2

PLACE_NEAR=U6300.C1:5 MM

PLACE_NEAR=U6300.C2:5 MM

E6
G6

F6

D4
B7
C6
C5

A6

NC

D3
B5
A5
A4
B4

C3
B2

A1
A2
E7
F7
G7

L83_FILT

C1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

C6310

PLACE_NEAR=U6300.D6:5 MM

PLACE_NEAR=U6300.E6:5 MM

L83_VCP_FILTP

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PLACE_NEAR=U6300.G6:5 MM

L83_VCP_FILTN

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PLACE_NEAR=U6300.A4:5mm

L83_SDOUT

L83_FLYP
L83_FLYC
L83_FLYN

1

10UF

20%

2

10V

X5R

0603

10%

10V

X5R-CERM

0402

C6305

4.7UF

21

20%

10V

X5R-CERM

0402

C6306

4.7UF

21

20%

10V

X5R-CERM

0402

PLACE_NEAR=U6300.F6:5 MM

PLACE_NEAR=U6300.F6:5 MM

PP1V8_G3S

R6307

33

21

5% 2011/20W MF

I2C_CODEC_SDA
I2C_CODEC_SCL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

52 61 116

PP1V8_AUDIO

61

52

BI

52

IN

C6307

2.2UF

X5R-CERM

C6308

2.2UF

X5R-CERM

PLACE_NEAR=U6300.G7:5 MM

10%

10V

0402

10%

10V

0402

1

R6302

47K

5%
1/20W
MF
201

2

1

R6303

47K

5%
1/20W
MF
201

2

1

R6304

47K

5%
1/20W
MF
201

2

I2S_CODEC_LRCLK_R

I2S_CODEC_R2D

I2S_CODEC_D2R

I2S_CODEC_BCLK

PLACE_NEAR=U6300.E7:5 MM

1

2

PLACE_NEAR=U6300.F7:5 MM
PLACE_NEAR=U6300.F7:5 MM

1

2

PAGE TITLE

PP1V8_G3S

CODEC_INT_L
CODEC_WAKE_L

CODEC_RESET_L

1

2

52 61 116

C6320

1000PF

10%

25V

X7R
0201

IN

IN

OUT

IN

OUT

OUT

IN

38

39

39

47

47

40

47

DESIGN: X502/DEV_MLB_U
LAST CHANGE: Wed Feb 18 17:31:01 2015

Audio Jack Codec

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

C

B

A

SYNC_DATE=07/24/2017SYNC_MASTER=TROY

4.0.0

BRANCH

evt-0

PAGE

63 OF 200

SHEET

61 OF 131

BOM_COST_GROUP=AUDIO

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

C

2X MONO SPEAKER LEFT AMPLIFIERS

APN: 353S01252
GAIN: 0DBFS = xxVRMS

MAX CURRENT = 15mA PER AMPLIFIER

PP1V8_G3S

62 116

47K

5%

1/20W

MF

201

1

1

C6400

1UF

10%

2

2

10V
X5R
402-1

62 52

62 52

R6410

33

5% MF1/20W 201

63 62 38

63 62 38

62 47

63 62 40

62 47

62 47

R6400

SPKRAMP_RESET_L

IN

1

R6401

47K

5%
1/20W
MF

2

201

OUT

SPKRAMP_INT_L

I2S_SPKRAMP_L_R2D

IN

I2S_SPKRAMP_L_D2R

BI

I2S_SPKRAMP_L_LRCLK_R

IN

IN

I2S_SPKRAMP_L_BCLK

PLACE_NEAR=U6400.C1:5 MM
PLACE_NEAR=U6400.D2:3 MM
PLACE_NEAR=U6400.D2:5 MM
PLACE_NEAR=U6400.C1:3 MM

1

C6401

0.1UF

10%

2

25V
X7R-CERM-1
0402

BI

21

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

IN

62

PLACE_NEAR=U6400.E1:5 MM

I2S_SPKRAMP_L_D2R_R1

C6402

1

1UF

10%

2

10V
X5R
402-1

SPKRAMP_LW_MODE

1

C6403

0.1UF

2

25V
X7R-CERM-1
0402

C3

F3
F4

D4

F2

E1
E2

F1

E4
E3

E5

F5

SDZ*
SDA

SCL

IRQZ

MODE
SDIN

SDOUT
FSYNC
SBCLK
PDMD0

PDMCK0
PDMD1

PDMCK1

C1

D2

IOVDDAVDD

U6400

PTAS5770LB2

CSP

CRITICAL

GND

C2

PGND

B4

A4

C5

C4

VBAT

VSNS_P

VSNS_N

BST_P
OUT_P
OUT_P

BST_N
OUT_N
OUT_N

AREG
DREG

1

C6404

0.1UF

10%

2

25V
X7R-CERM-110%
0402

B2

SPKRAMP_LW_BSTP

A3

SPKRAMP_LW_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_LW_SNSP

A2

SPKRAMP_LW_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_LW_OUTN

B1

SPKRAMP_LW_SNSN

D5

D1

SPKRAMP_LW_AREG

SPKRAMP_LW_DREG

C6407

1

0.1UF

10%

2

25V
X7R-CERM-1
0402

PLACE_NEAR=U6400.C4:3 MM
PLACE_NEAR=U6400.C4:10 MM
PLACE_NEAR=U6400.C4:10 MM

1

C6405

22UF

20%

2

25V
X5R-CERM
0805-1

C6408

1

1UF

10%

2

10V
X5R
402-1

C6406

1

22UF

20%
25V

2

X5R-CERM
0805-1

C6411

0.1UF

21

10%
25V

X7R-CERM-1

0402

BYPASS=U6400.A2:A5:5 MM
NO_XNET_CONNECTION=1

C6412

0.1UF

21

10%
25V

X7R-CERM-1

0402

C6409

1

0.1UF

10%

2

25V
X7R-CERM-1
0402

MAX CURRENT = 2A PER AMPLIFIER

62

PPBUS_G3H_SPKRAMPL

BYPASS=U6400.B2:B3:5 MM
NO_XNET_CONNECTION=1

L6400

180OHM-3.4A

0806

PLACE_NEAR=U6400.A3:10 MM

CRITICAL

21

DIDT=TRUE

SHORT-8L-0.25MM-SM

21

XW6400

PLACE_NEAR=J6410.2:3 MM

PLACE_NEAR=U6400.A5:10 MM

CRITICAL

L6401

180OHM-3.4A

0806

21

DIDT=TRUE

SHORT-8L-0.25MM-SM

21

XW6401

PLACE_NEAR=J6410.1:3 MM

C6410

1

PLACE_NEAR=U6400.D1:3 MM
PLACE_NEAR=U6400.D1:5 MM
PLACE_NEAR=U6400.D5:3 MM
PLACE_NEAR=U6400.D5:5 MM

2

1UF

10%
10V
X5R
402-1

C6470

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

C6413

SENSOR:DEV

220PF

5%

25V

C0G-CERM

0402

NO_XNET_CONNECTION=1

CRITICAL

R6470

0.01

0.5%
1W
MF

0612-6

2 1
4 3

TP_ISNS_SKPRLN

LEFT WOOFER

SPKRCONN_LW_OUTP

SPKRCONN_LW_OUTN

CRITICAL

1

2

C6414

1

220PF

5%
25V

2

C0G-CERM
0402

TP_ISNS_SKPRLP

PPBUS_G3H

63 115

APN: 518S0521

J6410

78171-0004

M-RT-SM

5

1
2
3
4

6

D

C

B

62 47

63 62 40

62 47

62 47

MAX CURRENT = 15mA PER AMPLIFIER

PP1V8_G3S

62 116

I2S_SPKRAMP_L_R2D

IN

I2S_SPKRAMP_L_D2R

BI

I2S_SPKRAMP_L_LRCLK_R

IN

IN

I2S_SPKRAMP_L_BCLK

PLACE_NEAR=U6450.C1:5 MM
PLACE_NEAR=U6450.D2:5 MM
PLACE_NEAR=U6450.D2:3 MM
PLACE_NEAR=U6450.C1:3 MM

1

C6450

1UF

10%

2

10V
X5R
402-1 0402

63 62 38

63 62 38

R6460

33

5% MF

1

C6451

0.1UF

10%

2

25V
X7R-CERM-1

1

C6452

1UF

10%

2

10V
X5R
402-1

SPKRAMP_RESET_L

52 62

I2C_SPKRAMP_L_SDA

52 62

I2C_SPKRAMP_L_SCL
SPKRAMP_INT_L

62

SPKRAMP_LT_MODE

PLACE_NEAR=U6450.E1:5 MM

I2S_SPKRAMP_L_D2R_R2

21

2011/20W

1

C6453

0.1UF

10%

2

25V
X7R-CERM-1
0402

C3

F3
F4

D4

F2

E1
E2

F1

E4
E3

E5

F5

SDZ*
SDA

SCL

IRQZ

MODE
SDIN

SDOUT
FSYNC
SBCLK
PDMD0

PDMCK0
PDMD1

PDMCK1

C1

D2

IOVDDAVDD

U6450

PTAS5770LB2

CSP

CRITICAL

GND

C2

PGND

B4

A4

C5

C4

VBAT

VSNS_P

VSNS_N

BST_P
OUT_P
OUT_P

BST_N
OUT_N
OUT_N

AREG

DREG

PLACE_NEAR=U6450.C4:10 MM
PLACE_NEAR=U6450.C4:10 MM
PLACE_NEAR=U6450.C4:3 MM

1

C6454

0.1UF

10%

2

25V
X7R-CERM-1
0402

B2

SPKRAMP_LT_BSTP

A3

SPKRAMP_LT_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_LT_SNSP

A2

SPKRAMP_LT_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_LT_OUTN

B1

SPKRAMP_LT_SNSN

D5

D1

SPKRAMP_LT_AREG

SPKRAMP_LT_DREG

1

C6457

0.1UF

10%

2

25V
X7R-CERM-1
0402

1

C6455

22UF

20%

2

25V
X5R-CERM
0805-1

1

C6458

1UF

10%

2

10V
X5R
402-1

1

C6456

22UF

20%

2

25V
X5R-CERM
0805-1

C6461

0.1UF

21

10%
25V

X7R-CERM-1

0402

C6462

0.1UF

21

10%
25V

X7R-CERM-1

0402

1

C6459

0.1UF

10%

2

25V
X7R-CERM-1
0402

MAX CURRENT = 2A PER AMPLIFIER

PPBUS_G3H_SPKRAMPL

BYPASS=U6450.B2:B3:5 MM
NO_XNET_CONNECTION=1

CRITICAL

L6450

PLACE_NEAR=U6450.A3:10 MM

180OHM-3.4A

0806

BYPASS=U6450.A2:A5:5 MM
NO_XNET_CONNECTION=1

L6451

21

SHORT-8L-0.25MM-SM

PLACE_NEAR=J6410.3:3 MM

XW6450

CRITICAL

PLACE_NEAR=U6450.A5:10 MM

180OHM-3.4A

0806

21

SHORT-8L-0.25MM-SM

XW6451

PLACE_NEAR=J6410.4:3 MM

1

C6460

1UF

10%

2

10V
X5R
402-1

PLACE_NEAR=U6450.D1:3 MM
PLACE_NEAR=U6450.D1:5 MM
PLACE_NEAR=U6450.D5:3 MM
PLACE_NEAR=U6450.D5:5 MM

62

21

SPKRCONN_LT_OUTP

B

LEFT TWEETER

SPKRCONN_LT_OUTN

21

CRITICAL

C6463

220PF

5%

25V

C0G-CERM

0402

1

2

CRITICAL

1

C6464

220PF

5%

2

25V
C0G-CERM
0402

A

LEFT BULK CAPACITANCE

CAPDERATE

1

C6480

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C6481

33UF

20%

2

16V
TANT-POLY
CASE-B3

8

CAPDERATE

1

C6482

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C6483

33UF

20%

2

16V
TANT-POLY
CASE-B3

1

C6484

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

PPBUS_G3H_SPKRAMPL

1

C6485

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

62

PP1V8_G3S

62 116

NOSTUFF

1

R6480

10K

5%
1/20W
MF
201

62

SPKRAMP_LW_MODE
SPKRAMP_LT_MODE

62

2

1

R6481

470

5%
1/20W
MF
201

2

67

NOSTUFF

1

R6482

2.2K

5%
1/20W
MF
201

2

1

R6483

0

5%
1/20W
MF
0201

2

I2C ADDRESS

MODE PIN
GND
470 to GND
470 to IOVDD
2k2 to GND
2k2 to IOVDD 0x35
10k to GND
10k to IOVDD
47k to IOVDD

0x31
0x32
0x33
0x34

0x36
0x37
0x38

CHANNEL7-BIT

L TW
L WF
R TW
R WF

SYNC_DATE=12/11/2017SYNC_MASTER=TROY

PAGE TITLE

A

Audio Left Amplifiers

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=AUDIO

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

64 OF 200

SHEET

62 OF 131

1

SIZE

D

D

2X MONO SPEAKER RIGHT AMPLIFIERS

APN: 353S01252
GAIN: 0DBFS = xxVRMS

MAX CURRENT = 15mA PER AMPLIFIER

PP1V8_G3S

63 116

1

C6508

2

1UF

10%
10V
X5R
402-1

PLACE_NEAR=U6500.D2:3 MM
PLACE_NEAR=U6500.D2:5 MM PLACE_NEAR=U6500.C4:10 MM
PLACE_NEAR=U6500.C1:3 MM
PLACE_NEAR=U6500.C1:5 MM

1

2

C6500

0.1UF

10%
25V
X7R-CERM-1
0402

C6509

1

1UF

10%

2

10V
X5R
402-1

678

1

C6505

2

0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U6500.C4:10 MM
PLACE_NEAR=U6500.C4:3 MM

1

C6501

0.1UF

10%

2

25V
X7R-CERM-1
0402

1

C6503

22UF

20%

2

25V
X5R-CERM
0805-1

C6504

1

22UF

20%
25V

2

X5R-CERM
0805-1

MAX CURRENT = 2A PER AMPLIFIER

PPBUS_G3H

62 63 115

3 245

1

D

PP1V8_G3S

63 116

C

63 62 38

63 62 38

63 47

63 62 40

63 47

63 47

SPKRAMP_RESET_L

IN

OUT

SPKRAMP_INT_L

I2S_SPKRAMP_R_R2D

IN

I2S_SPKRAMP_L_D2R

BI

I2S_SPKRAMP_R_LRCLK_R

IN

IN

I2S_SPKRAMP_R_BCLK

63 52

63 52

R6510

33

BI

21

201MF1/20W5%

I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL

IN

SPKRAMP_RT_MODE

63

PLACE_NEAR=U6500.E1:5 MM

I2S_SPKRAMP_R_D2R_R1

C3

F3
F4

D4

F2

E1
E2

F1

E4
E3

E5

F5

SDZ*
SDA

SCL

IRQZ

MODE
SDIN

SDOUT
FSYNC
SBCLK
PDMD0

PDMCK0
PDMD1

PDMCK1

C1

D2

IOVDDAVDD

U6500

PTAS5770LB2

CSP

CRITICAL

GND

C2

PGND

B4

A4

C5

C4

VBAT

VSNS_P

VSNS_N

BST_P
OUT_P
OUT_P

BST_N
OUT_N
OUT_N

AREG
DREG

B2

SPKRAMP_RT_BSTP

A3

SPKRAMP_RT_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_RT_SNSP

A2

SPKRAMP_RT_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_RT_OUTN

B1

SPKRAMP_RT_SNSN

D5

D1

SPKRAMP_RT_AREG

SPKRAMP_RT_DREG

C6513

1

0.1UF

10%

2

25V
X7R-CERM-1
0402

C6514

1

1UF

10%

2

10V
X5R
402-1

C6511

0.1UF

21

10%
25V

X7R-CERM-1

0402

C6512

0.1UF

21

10%
25V

X7R-CERM-1

0402

C6515

1

0.1UF

10%

2

25V
X7R-CERM-1
0402

BYPASS=U6500.B2:B3:5 MM
NO_XNET_CONNECTION=1

L6500

180OHM-3.4A

0806

PLACE_NEAR=J6500.2:3 MM

BYPASS=U6500.A2:A5:5 MM
NO_XNET_CONNECTION=1

L6501

180OHM-3.4A

0806

PLACE_NEAR=J6500.1:3 MM

C6516

1

1UF

2

10%
10V
X5R
402-1

PLACE_NEAR=U6500.D1:3 MM
PLACE_NEAR=U6500.D1:5 MM
PLACE_NEAR=U6500.D5:3 MM
PLACE_NEAR=U6500.D5:5 MM

CRITICAL

PLACE_NEAR=U6500.A3:10 MM

21

DIDT=TRUE

SHORT-8L-0.25MM-SM

21

XW6500

CRITICAL

PLACE_NEAR=U6500.A5:10 MM

21

DIDT=TRUE

SHORT-8L-0.25MM-SM

21

XW6501

CRITICAL

C6506

220PF

5%

25V

C0G-CERM

0402

1

R6590

47K

5%
1/20W
MF

RIGHT TWEETER

SPKRCONN_RT_OUTP

120 40

OUT

201

2

SPKR_ID0

APN: 518S0672

J6500

78171-6006

M-RT-SM

7

1
2
3
4
5
6

SPKRCONN_RT_OUTN

8

CRITICAL

1

2

C6507

1

220PF

5%
25V

2

C0G-CERM
0402

C

B

63 47

63 62 40

63 47

63 47

MAX CURRENT = 15mA PER AMPLIFIER MAX CURRENT = 2A PER AMPLIFIER

PP1V8_G3S

63 116

I2S_SPKRAMP_R_R2D

IN

I2S_SPKRAMP_L_D2R

BI

I2S_SPKRAMP_R_LRCLK_R

IN

I2S_SPKRAMP_R_BCLK

IN

CAPDERATE

1

C6558

1UF

10%

2

10V
X5R
402-1

PPBUS_G3H

PLACE_NEAR=U6550.D2:3 MM
PLACE_NEAR=U6550.D2:5 MM
PLACE_NEAR=U6550.C1:3 MM
PLACE_NEAR=U6550.C1:5 MM

63 62 38

63 62 38

R6560

33

1/20W MF5%

1

C6550

0.1UF

10%

2

25V
X7R-CERM-1
0402

1

C6559

1UF

10%

2

10V
X5R X7R-CERM-1
402-1

SPKRAMP_RESET_L

52 63

I2C_SPKRAMP_R_SDA

52 63

I2C_SPKRAMP_R_SCL
SPKRAMP_INT_L
SPKRAMP_RW_MODE

63

PLACE_NEAR=U6550.E1:5 MM

I2S_SPKRAMP_R_D2R_R2

21

201

62 63 115

1

C6555

0.1UF

10%

2

25V
0402

C3

F3
F4

D4

F2

E1
E2

F1

E4
E3

E5

F5

SDZ*
SDA

SCL

IRQZ

MODE
SDIN

SDOUT
FSYNC
SBCLK
PDMD0

PDMCK0
PDMD1

PDMCK1

C1

D2

IOVDDAVDD

U6550

PTAS5770LB2

CSP

CRITICAL

GND

C2

PGND

B4

A4

C5

C4

VBAT

VSNS_P

VSNS_N

BST_P
OUT_P
OUT_P

BST_N
OUT_N
OUT_N

AREG
DREG

PLACE_NEAR=U6550.C4:10 MM
PLACE_NEAR=U6550.C4:10 MM
PLACE_NEAR=U6550.C4:3 MM

1

C6551

0.1UF

10%

2

25V
X7R-CERM-1
0402

B2

SPKRAMP_RW_BSTP

A3

SPKRAMP_RW_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_RW_SNSP

A2

SPKRAMP_RW_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_RW_OUTN

B1

SPKRAMP_RW_SNSN

D5

D1

SPKRAMP_RW_AREG

SPKRAMP_RW_DREG

1

C6563

0.1UF

10%

2

25V
X7R-CERM-1
0402

1

C6553

22UF

20%

2

25V
X5R-CERM
0805-1

1

C6564

1UF

10%

2

10V
X5R
402-1

1

C6554

22UF

20%

2

25V
X5R-CERM
0805-1

C6561

0.1UF

21

10%
25V

X7R-CERM-1

0402

C6562

0.1UF

21

10%
25V

X7R-CERM-1

0402

1

C6565

0.1UF

10%

2

25V
X7R-CERM-1
0402

PPBUS_G3H

BYPASS=U6550.B2:B3:5 MM
NO_XNET_CONNECTION=1

L6550

180OHM-3.4A

0806

PLACE_NEAR=J6500.5:3 MM

BYPASS=U6550.A2:A5:5 MM
NO_XNET_CONNECTION=1

L6551

180OHM-3.4A

0806

PLACE_NEAR=J6500.6:3 MM

1

C6566

2

1UF

10%
10V
X5R
402-1

PLACE_NEAR=U6550.D5:5 MM
PLACE_NEAR=U6550.D5:3 MM
PLACE_NEAR=U6550.D1:5 MM
PLACE_NEAR=U6550.D1:3 MM

62 63 115

CRITICAL

PLACE_NEAR=U6550.A3:10 MM

21

21

SHORT-8L-0.25MM-SM

XW6550

CRITICAL

PLACE_NEAR=U6550.A5:10 MM

21

21

SHORT-8L-0.25MM-SM

XW6551

CRITICAL

C6556

220PF

5%

25V

C0G-CERM

0402

SPKRCONN_RW_OUTP

B

RIGHT WOOFER

SPKRCONN_RW_OUTN

CRITICAL

1

1

2

C6557

220PF

5%

2

25V
C0G-CERM
0402

A

1

C6580

2

CAPDERATE

33UF

20%
16V
TANT-POLY
CASE-B3

1

C6581

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C6582

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C6583

33UF

20%

2

16V
TANT-POLY
CASE-B3

1

C6584

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C6585

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

63

SPKRAMP_RT_MODE

63

SPKRAMP_RW_MODE

PP1V8_G3S

63 116

1

R6580

470

5%
1/20W
MF
201

2

NOSTUFF

1

R6581

0

5%
1/20W
MF
0201

2

NOSTUFF

1

R6582

2.2K

5%
1/20W
MF
201

2

1

R6583

2.2K

5%
1/20W
MF
201

2

MODE PIN
GND
470 to GND

2k2 to GND
2k2 to IOVDD
10k to GND
10k to IOVDD
47k to IOVDD

I2C ADDRESS

7-BIT

0x31
0x32
0x33470 to IOVDD
0x34
0x35
0x36
0x37
0x38

CHANNEL

L TW
L WF
R TW
R WF

BOM_COST_GROUP=AUDIO

PAGE TITLE

Audio Right Amplifiers

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

65 OF 200

SHEET

63 OF 131

SIZE

D

A

SYNC_DATE=12/11/2017SYNC_MASTER=TROY

8

67

35 4

2

1

678

3 245

1

PP1V8_SLPS2R

PLACE_NEAR=U6650.4:5MM

DMIC Secure Disable

D

BYPASS=U6650.5:U6650.2:8MM

SEP_CAM_DISABLE_L

38

IN

SEP_DMIC_DISABLE_L

38

IN

SEP_DISABLE_STROBE

38

IN

PMU_COLD_RESET_L

39 77 119 121

IN

47 120

47 120

LID_OPEN_RIGHT

IN

LID_OPEN_LEFT

IN

LID_CTRL_DMIC

C6650

0.1UF

10%
10V

X5R-CERM

0201

1

2

1

R6651

2

1K

5%
1/20W
MF
201

1

VDD

SEP_CAM_DISABLE_DFF_L

SEP_DMIC_DISABLE_Q_L

OUT

82

116 64

U6650

2

CAM_DIS*

3

DMIC_DIS*

4

DIS_STROBE

9

PMU_COLD_RST*

13

LID_RIGHT

14

LID_LEFT

6

SEL

SLG4AP41496V

(IPD)

(IPD)

(IPD)

STQFN

(PUSH-PULL)

CRITICAL

(IPD)

CAM_DIS_OUT*

(PUSH-PULL)

DMIC_DIS_OUT*

CAM_DIS_OUT

DMIC_DIS_OUT

(IPD)

RFU

12

10
11

5

NC
NC

NC

PDM_DMIC_DATA0_UNSEC

64

PP1V8_G3S

1

B

U6640

2

A

SOT353

74LVC1G08GW

5

Y

3

R6648

1/20W
MF

NOSTUFF

PLACE_NEAR=U6640.4:5MM

BYPASS=U6640.5:U6640.3:8MM

1

C6641

0.1UF

20%
10V

2

X7R-CERM
0402

4

PDM_DMIC_DATA0_RR

0

21

5%

0201

PLACE_NEAR=U6640.4:5MM

R6647

1/20W

MF

33

5%

201

PDM_DMIC_DATA0

21

OUT

D

39

C

APN: 518S0818

FF14A-6C-R11DL-B-3H

J6640

F-RT-SM

7

1
2
3
4
5
6

8

AUD_DMIC0_CLK_CONN
AUD_DMIC0_DATA_CONN
PP1V8_DMIC
AUD_DMIC1_CLK_CONN

AUD_DMIC1_DATA_CONN

120

Digital Mic Flex Connector

R6606

PLACE_NEAR=J6640.1:8MM

PLACE_NEAR=J6640.2:8MM

PLACE_NEAR=J6640.4:8MM

PLACE_NEAR=J6640.5:8MM

0

1/20W
MF

R6608

0

1/20W
MF 10%16V

5%

0201

5%

0201

21

R6605

1/20W
MF

21

R6607

1/20W
MF

0

0

5%

0201

5%

0201

PDM_DMIC_CLK0

PDM_DMIC_DATA0_UNSEC

21

PDM_DMIC_CLK1

PDM_DMIC_DATA1_UNSEC

21

64

64

GND

8

PP1V8_G3S

116 64

47

IN

1

L6640

PP1V8_G3S

21

1000-OHM-EMI

0402

47

IN

C6640

1

116

PDM_DMIC_DATA1_UNSEC

64

SOT353

74LVC1G08GW

B

2

A

5

U6641

3

4

Y

PDM_DMIC_DATA1_RR

PLACE_NEAR=U6641.4:5MM

BYPASS=U6641.5:U6641.3:8MM

C6642

1

0.1UF

20%
10V
X7R-CERM

2

0402

PLACE_NEAR=U6641.4:5MM

R6649

33

1/20W

MF

5%

201

PDM_DMIC_DATA1

21

OUT

39

C

1UF

2

X5R
402

R6650

5%002011/20WMF

NOSTUFF

21

B

A

61

61

61

61

61

61

61

61

61

61

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Audio Jack Flex Connector

CRITICAL

FL6601

120-OHM-25%-1.3A

AUD_HP_PORT_L

0402

21

CRITICAL

FL6600

120-OHM-25%-1.3A

AUD_HP_PORT_R

CRITICAL

0402

21

FL6603

120-OHM-25%-1.3A

AUD_HP_PORT_US_GND

0402

21

CRITICAL

FL6605

120-OHM-25%-1.3A

AUD_HP_PORT_CH_GND

CRITICAL

0402

21

FL6606

120-OHM-25%-1.3A

AUD_HP_SENSE_L

0402

21

CRITICAL

FL6607

120-OHM-25%-1.3A

AUD_HP_SENSE_R

0402

R6600

AUD_TIP_SENSE AUD_CONN_TIP_SENSE

AUD_RING_SENSE

120-OHM-25%-1.3A

AUD_HS_MIC_P

2.0K

2 1

5%

1/20W

MF

201

CRITICAL

FL6602

0402

R6601

2 1

21

2.0K

5%

1/20W

MF

201

CRITICAL

21

FL6604

120-OHM-25%-1.3A

AUD_HS_MIC_N

0402

21

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000

AUD_CONN_RING2

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000

AUD_CONN_SLEEVE

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000

AUD_CONN_HP_SENSE_L

AUD_CONN_HP_SENSE_R

AUD_CONN_RING_SENSE

AUD_CONN_SLEEVE_XW

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0920

AUD_CONN_RING2_XW

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0920

APN: 510S0009

J6600

51138-0274

F-ST-SM

22
21

21
43
65
87
109
1211
1413
1615
1817
2019

23
24

BOM_COST_GROUP=AUDIO

AUD_CONN_HP_LEFT

AUD_CONN_HP_RIGHT

AUD_CONN_RING2

AUD_CONN_SLEEVE

64 119 120

64 119 120

64 119 120

64 119 120

DESIGN: X502/DEV_MLB_U
LAST CHANGE: Wed Feb 18 17:12:24 2015

PAGE TITLE

Audio Flex Connectors

DRAWING NUMBER

051-02643

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/22/2017SYNC_MASTER=TROY

4.0.0

evt-0
66 OF 200
64 OF 131

B

A

SIZE

D

8

67

35 4

2

1

D

C

120 65

120 65

120 59

120 59

65 116

116

116

120 65

KBD CONNECTOR

GND_FAN

PP5V_G3S_FAN_CONN

FAN_LT_TACH
FAN_LT_PWM

PP5V_G3S

PP3V3_G3H_RTC_X
KBD_BLC_GSSOUT

PP3V3_G3S_T
KBD_BLC_GSSIN

J6700

DF40PC-40DS-0.4V-51

F-ST-SM

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039

120 65

XW6700

SM

GND_FAN

VOLTAGE=0V

21

XW6702

SM

PP5V_G3S_FAN_CONN

VOLTAGE=5V

add pace near

FAN_RT_TACH

FAN_RT_PWM

PP5V_G3S

I2C_KBD_SDA
KBD_INT_LKBD_BLC_GSLAT
I2C_KBD_SCL

120 59

120 59

65 116

120 65 120 65

120 65 120 65

120 65

R6700

PMU_RSLOC_RST_R_L

KBD_BLC_GSSCKKBD_BLC_XBLANK

120 65 120 65

516S00177 (RCPT, 0.3A per pin)

MATE WITH PLUG 516S00054

5%

0

0201

PP5V_G3S

21

21

1/20WMF

678

1

C6701

12PF

5%
25V

2

NP0-C0G
0201

PMU_RSLOC_RST_L

C4501 FOR DESENSE

116

3 245

1

TPAD CONNECTOR

J6701

DF40C-50DS-0.4V-51

120 66

120 66

120 65

120 65

120 65

120 65

120 65

120 65

120 65

120 65

131 77 67

I2C_TPAD3V3_SCL
I2C_TPAD3V3_SDA
KBD_INT_L
I2C_KBD_SDA

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

I2C_KBD_SCL
KBD_BLC_XBLANK

KBD_BLC_GSSIN

KBD_BLC_GSSOUT

KBD_BLC_GSSCK
KBD_BLC_GSLAT

120 65

ACT_GND

F6700

2.5A-16V-0.1OHM

PPBUS_G3H

115

21

PPVIN_G3H_TPAD_FUSE

120

F-ST-SM

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49

IPD_LID_OPEN
TPAD_KBD_WAKE_L
TPAD3V3_ACTUATOR_DISABLE_L
TPAD3V3_SPI_INT_L

SPI_TPAD3V3_MOSI
SPI_TPAD3V3_CS_L
SPI_TPAD3V3_MISO
TPAD3V3_SPI_EN
SPI_TPAD3V3_CLK

120

PP5V_G3S_TPAD_CONN

PP3V3_G3S_T

VOLTAGE=5V

116
120

NC_J6701_PIN31

NO_TEST=1

XW6701

SM

120 65

ACT_GND

add pace near

21

120 50 47

120 66 47

C6700

0.1UF

10%
25V
X5R
402

OUT

1

2

D

120 66

120 66

120 66

120 66

120 66

120 66

120 66

FERR-120-OHM-1.5A

L6700

0402A

21

PP5V_G3S

116

C

1812

VOLTAGE=13.1V

516S00187, MATE WITH 516S00188

B

B

A

8

SYNC_MASTER=j132 SYNC_DATE=03/23/2017

PAGE TITLE

A

Keyboard & Trackpad 1

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=KEYBOARD

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

67 OF 200

SHEET

65 OF 131

1

SIZE

D

678

3 245

1

Trackpad Level Shifting

D

PP1V8_AWAKE

80

40

47 46

47 46

47

IN

IN

IN

OUT

SPI_TPAD_CS_L

SPI_TPAD_CLK

SPI_TPAD_MOSI

SPI_TPAD_MISO_R

1

R6887

100K

5%
1/20W
MF
201

2

BYPASS=U6860::5MM

C6860

0.1UF

X5R-CERM

10%
10V

0201

PP3V3_G3S_T

1

14

2

1

15

2

16

3
5

4
6

7

U6860

SN74AVC4T774

A1
DIR1

A2
DIR2

A3
DIR3

A4
DIR4

OE*

QFN

GND

13

VCCBVCCA

12

B1

11

B2

10

B3

9

B4

8

BYPASS=U6860::10MM

1

C6861

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_TPAD3V3_CS_L

SPI_TPAD3V3_CLK_R

SPI_TPAD3V3_MOSI_R

SPI_TPAD3V3_MISO

1

R6870

5%
1/20W
MF
201

2

IN

1

R6871

100K100K

5%
1/20W
MF
201

2

NOSTUFF

1

R6872

100K

5%
1/20W
MF
201

2

PLACE_NEAR=U6860.9:2MM

R6875

PLACE_NEAR=U6860.8:2MM

R6876

120 65

1

R6880

100K

5%
1/20W
MF
201

2

20

5%

1/20W

MF

201

21

1

R6873

100K

5%
1/20W
MF
201

2

OUT

20

5%

1/20W

MF

201

21

SPI_TPAD3V3_CLK

SPI_TPAD3V3_MOSI

120 65

OUT

120 65

66 116

OUT

D

120 65

C

51

I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA

BI

66 116

PLACE_NEAR=U6861.3:5MM

PP1V8_G3S

R6879

30

21

I2C_TPAD_SDA_R

MF 5% 1/20W201

CKPLUS_WAIVE=I2C_PULLUP

PP3V3_G3S_T

66 116

C

2.2K

5%

1/20W

MF

201

1

2

201 5%

PLACE_NEAR=U6861.6:2MM

PLACE_NEAR=U6861.3:2MM

R6877

30

21

1/20WMF

R6878

30

5%201 1/20WMF

I2C_TPAD3V3_SCL

CKPLUS_WAIVE=I2C_PULLUP

I2C_TPAD3V3_SDA

21

CKPLUS_WAIVE=I2C_PULLUP

PP1V8_G3S

66 116

1

R6863

OUTIN

120 65 51

47

OUT

BI

120 65

120 65 47

OUT

TPAD_SPI_INT_L

PP1V8_G3S

66 116

TPAD_KBD_WAKE_L

100K

5%
1/20W
MF
201

2

1

R6865

100K

5%
1/20W
MF
201

2

5

G

4

Q6862

DMN5L06VK-7

SOT563

VER 5

DS

3

PP3V3_G3S_T

66 116

TPAD3V3_SPI_INT_L

1

R6864

100K

5%
1/20W
MF
201

2

IN

120 65

1

R6812

2.2K

2

G

DMN5L06VK-7

SOT563

VER 5

5%

1/20W

MF

201

2

R6813

U6861

DS

1

5

G

6

I2C_TPAD3V3_SCL_R

DMN5L06VK-7

SOT563

VER 5

U6861

DS

4

3

I2C_TPAD3V3_SDA_R

B

PP1V8_G3S

66 116

1

R6852

100K

5%
1/20W
MF
201

2

38

IN OUT

BYPASS=U6855::5MM

C6855

0.1UF

10%
10V

X5R-CERM

0201

BYPASS=U6855::5MM

1

C6856

0.1UF

10%
10V

2

X5R-CERM
0201

UDFN

6

4

BA

1

2

1

VCCA VCCB

U6855

SLSV1T34AMU-COMBO

2

CRITICAL

NOSTUFF

1

R6854

100K

5%
1/20W
MF
201

2

PP3V3_G3S_T

TPAD3V3_SPI_ENTPAD_SPI_EN

66 116

PP1V8_G3S

66 116

PP3V3_G3S_T

66 116

NOSTUFF

R6867

47

BI

120 65

TPAD_ACTUATOR_DISABLE_L TPAD3V3_ACTUATOR_DISABLE_L

1

100K

5%
1/20W
MF
201

2

Q6862

2

G

1

DMN5L06VK-7

SOT563

VER 5

DS

6

Pull-Up on IPD module

1

R6868

100K

5%
1/20W
MF
201

2

B

BI

120 65

A

NC

5

NC

GND

3

1

R6853

100K

5%
1/20W
MF
201

2

PAGE TITLE

SYNC_DATE=03/23/2017SYNC_MASTER=j132

A

Keyboard & Trackpad 2

SIZE

D

BOM_COST_GROUP=KEYBOARD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

68 OF 200

SHEET

66 OF 131

8

67

35 4

2

1

J80 Battery Hotbar Flex Pads 998-03902

Flex Pad TO MLB 998-03780.

CRITICAL

OMIT_TABLE

J6950

PWR-MLB-X363

HB-SM

10

D

9
8
3

2
7

1

6

5

4

17

16

15

14

13

12

11

C6950

0.1UF

10%

25V

X5R
402

PPVBAT_G3H_CONN

1

2

C6960

1UF

10%

25V

X5R

603-1

678

APN:518S0818

FF14A-6C-R11DL-B-3H

119 68

1

2

J6951

F-RT-SM

7

1
2
3
4
5
6

8

NC

NC

119

119

SYS_DETECT_L
SMBUS_3V3_BATT_SCL
SMBUS_3V3_BATT_SDA
TP_BMON_IOUT

SYSDET:AON

1

R6950

10K

5%
1/16W
MF-LF
402

2

RCLAMP3552T

U6950

SLP1006N3T

CRITICAL

1

3

3 245

PP3V3_G3H_RTC_X

116

119

R6952

4.7K

5%

1/20W

MF

201

1

2

1

R6951

4.7K

5%
1/20W
MF
201

2

119

DMN5L06VK-7

SOT563

VER 5

Q6950

D S

3

DMN5L06VK-7

SOT563

VER 5

5

G

4

2

G

Q6950

2

3

SYSDET:FET

D

Q6955

G

DMN32D2LFB4

DFN1006H4-3

SYM_VER_1

S

2

1

119

SYS_DETECT

D S

6

PP3V3_G3H_RTC_X
SYSDET:FET

1

R6955

10K

5%
1/16W
MF-LF
402

2

1

PP1V8_SLPS2R

I2C_PWR_SCL

I2C_PWR_SDA

116

1

80

51

IN

D

51

BI

C

BMU POWER FLEX HOTBAR'd TO THE MLB:

1 J6950PCBA,FLEX,BMU PWR,X363632-00862 CRITICAL

SMC Reset Circuit

Right Shift & Left Option Control
followed by ON OFF button press.

116

PP3V3_G3H_RTC_X

BYPASS=U6940::3MM

C6940

0.1UF

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

131 77 48

131 77 65

IN
IN

PMU_ONOFF_L
PMU_RSLOC_RST_L

10%

25V

X5R

0201

1

2

3
4

SLG4AP41183

BTN1
BTN2

1

VDD

U6940

STQFN

RESET

CRITICAL

GND

7

NC
NC
NC
NC
NC
NC
NC

10

2
5
6
8
9
11
12

R6940

CHGR_RST_IN_R CHGR_RST_IN

NC
NC
NC
NC
NC
NC
NC

1K

5%
1/16W
MF-LF

402

R6941

1K

5%
1/16W
MF-LF

402

21

UPC_PMU_RESET

21

OUT

OUT

C

68

119 107 77 29

B

A

PPBUS_HS_3V3G3HRTC_X

115

R6900

0

0%

1/4W

MF

0603

1

2

CAPDERATE

PPVIN_G3H_P3V3G3HRTC_R

1

C6900

2.2UF

20%

25V

2

X5R-CERM
0402-1

1

C6901

2.2UF

20%

25V

2

X5R-CERM
0402-1

CAPDERATE

119 68

CAPDERATE

IN

1

C6963

33UF

20%

2

16V
TANT-POLY
CASE-B3

CHGR_EN_MVR

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000

VOLTAGE=13.1V

1

C6964

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

R6968

2 1

0.033UF

C6961

1

2.2UF

20%

2

25V

X5R-CERM
0402-1

0

5%

1/20W

MF

0201

C6998

10%

50V

X7R

0402

C6962

1

2.2UF

20%

2

25V

X5R-CERM
0402-1

CHGR_EN_MVR_R

P3V3G3HRTC_SS

1

2

GND_P3V3G3HRTC_AGND

VOLTAGE=0V
MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

3.3V G3H VR

U6960

TPS62180

VIN1

A1

VIN1

B1

VIN1

C1
D1

VIN2

E1

VIN2

F1

VIN2
EN VO

E4
D4

SS/TR

AGND

C4

BGA

CRITICAL

PGND

PGND

PGND

B3

A3

D3

C3

XW6960

SM

PGND

PGND

E3

21

PGND

F3

SW1
SW1
SW1

SW2
SW2
SW2

PG

FB

P3V3G3HRTC_PHASE1

DIDT=TRUE

A2
B2
C2

P3V3G3HRTC_PHASE2

D2

DIDT=TRUE

E2
F2

A4

P3V3G3HRTC_PGOOD

F4
B4

P3V3G3HRTC_FB

R6967

100K

2 1

5%

1/20W

MF

201

APN 152S1617
CRITICAL

L6960

1.0UH-20%-3.9A-0.035OHM

21

PILE32251E-SM

CRITICAL

L6961

1.0UH-20%-3.9A-0.035OHM

21

PILE32251E-SM

P3V3G3HRTC_FB_R

<Ra>

10%

16V

0201

1

2

<Rb>

C6969

220PF

CER-X7R

R6970

10

5%

1/20W

MF

201

R6976

0.00

1%

1/20W

MF

0201

R6971

365K

0.1%

1/20W

TF

0201

R6972

113K

0.1%

1/20W

MF

0201

Vout = 3.384V
6A Max Output
f = 1.25 MHZ

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000

PP3V3_G3H_RTC_REG_R

C6972

1

10UF

20%

10V

2

X5R-CERM

1

2

1

0402-1

C6973

1

10UF

20%

10V

2

X5R-CERM
0402-1

Vout = 0.8 * (1 + <Ra>/<Rb>) = 3.384V

For tuning

2

P3V3G3HRTC_RA_R

1

2

1

2

BOM_COST_GROUP=PLATFORM POWER

VOLTAGE=3.3V

C6976

1

10UF

20%

10V

2

X5R-CERM
0402-1

C6977

1

10UF

20%

10V

2

X5R-CERM
0402-1

SYNC_MASTER=SILU SYNC_DATE=04/27/2017

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP3V3_G3H_RTC_X

R6934

CRITICAL

1

C6970

150UF

20%

6.3V

2

TANT
CASE-B-SM

CAPDERATE

0%

1/4W

MF

0603

1

0

2

1

R6935

0

0%
1/4W
MF
0603

2

CRITICAL

1

C6971

150UF

20%

6.3V

2

TANT
CASE-B-SM

CAPDERATE

VR 3.3V G3H & Battery Conn

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

CAPDERATE

CRITICAL

1

C6974

150UF

20%

6.3V

2

TANT
CASE-B-SM

116

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

69 OF 200

SHEET

67 OF 131

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

CRITICAL

1

C7042

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7043

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7024

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

122 119 55 53 29

CRITICAL

1

C7025

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7026

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

From USB-C Source

PPDCIN_G3H

CRITICAL

1

C7027

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

(AMON)

CRITICAL

R7020

2 1
4 3

121 121

CHGR_CSI_R_P CHGR_CSI_R_N

1

R7021

1.00

1%
1/20W
MF-LF
0201

2

CHGR_CSI_P

C7021

1

0.047UF

10%

2

50V
CER-X7R
0402

1

R7015

750K

1%
1/20W
MF
201

2

CHGR_AUX_DET

CRITICAL

1

C7028

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

0.01

0.5%

0.5W
MF

0306

CRITICAL

1

C7029

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

PPDCIN_G3H_CHGR

1%
1/20W
MF-LF

0201

1

2

R7022

1.00

CHGR_CSI_N

C7022

0.047UF

CER-X7R

10%
50V

0402

1

2

C7032

1

2.2UF

20%
35V

2

X5R-CERM
0402

13

3

2

1

D1

DFN

Q7030

FDMD8800

G1

12

CHGR_GATE_Q1

CHGR_VDDA

C7033

1

2.2UF

20%
35V

2

X5R-CERM
0402

PLACE_NEAR=Q7030.2:5mm

2.7UH-20%-21.5A-0.0135OHM

CHGR_PHASE1

6

5

10

9

8

7

S1/D2

G1R

11

G2

4

S2

CHGR_GATE_Q2

CHGR_LX1

1

C7030

0.1UF

10%

2

25V
X7R-CERM-1
0402

CHGR_BOOT1_RC

1

R7030

0

5%
1/16W
MF-LF
402

2

CHGR_BOOT1

R7075

4.7

1/20W

5%
MF

201

21

CHGR_VDDP

C7034

1

2.2UF

20%
35V

2

X5R-CERM
0402

PLACE_NEAR=Q7030.1:3mm

C7035

1

2.2UF

20%
35V

2

X5R-CERM
0402

152S00413

L7030

IHLP4040CZ-PIMA103T-SM-COMBO

CRITICAL

14

21

CHGR_PHASE2

1465

S2

G2

4

CHGR_GATE_Q3

CHGR_LX2

C7040

0.1UF

10%

X7R-CERM-1

CHGR_BOOT2_RC

25V

0402

R7040

1/16W
MF-LF

CHGR_BOOT2

1098

1

0

5%

402

2

CRITICAL

1

C7050

68UF 1000PF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7051

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7052

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7056

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

C7053

1

2.2UF

20%
25V

2

X5R
0402-1

C7055

1

2.2UF

20%
25V

2

X5R
0402-1

C7057

1

2.2UF

20%
25V

2

X5R
0402-1

C7058

1

2.2UF

20%
25V

2

X5R
0402-1

C7054

1

10%
25V

2

X7R
0201

D

CRITICAL

F7000

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200

7

1332

1

VOLTAGE=12.6V

12AMP-32V

1206

21

PPBUS_G3H

To System

115 122

CRITICAL

S1/D2

D1

F7001

12AMP-32V

DFN

1206

G1R

11

G1

12

Q7040

FDMD8800

CHGR_GATE_Q4

C7066

1

2

(BMON)

2.2UF

0402-1

20%
25V
X5R

1

2

C7069

2.2UF

0402-1

CRITICAL

R7060

(PBUS)

121
55

CHGR_CSO_R_P

1

R7061

1.00

1%
1/20W
MF-LF
0201

2

0.005

1%
1W
MF

0612-5

2 1
4 3

121 55

CHGR_CSO_R_N

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200

VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

1%
1/20W
MF-LF

0201

1

2

R7062

1.00

20%
25V
X5R

21

1

2

C7064

1000PF

C7067

0.1UF

0201

CRITICAL

Q7065

SI7137DP

S

3
2
1

G

21

10%
25V
X7R

0201

10%
25V
X5R

SYM-VER-2

1

2

SO-8

4

C7068

0.01UF

X5R-CERM

D

5

1

TP

TP-P5

1

10%

2

25V

0201

To/From Battery

TP7000

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=12.6V

PLACE_NEAR=Q7065.5:2MM

C7060

1

0.1UF

10%
25V

2

X5R
0201

C

67 119

B

A

51

51

67

3.3V = Tuba

1.8V = Suona

PP1V8_SLPS2R

80

BI

I2C_PWR_SDA
I2C_PWR_SCL

IN

CHGR_RST_IN

IN

119 68

NO STUFF

C7016

0.01UF

10%
25V

X5R-CERM

0201

PPVBAT_G3H_CHGR_REG

C7080

1.0UF

20%
10V

X5R-CERM

0201-1

1

2

C7081

2.2UF

20%
35V

X5R-CERM

0402

PLACE_NEAR=U7000.A5:2MM

C7075

1

1

1

2

R7016

255K

1%
1/20W
MF
201

2

PLACE_NEAR=U7000.C5:1MM

C7023

0.47UF

2 1

20%

4V

CERM-X5R-1

201

CHGR_COMP

NOSTUFF

1

2

C7070

0.12UF

10%
10V
X5R
0402

1

2

C7071

1

0.12UF

10%
10V

2

X5R
0402

NOSTUFF

1

R7074

100K

5%
1/20W
MF
201

2

2.2UF

20%

2

25V
X6S-CERM
0402

D2

A2

VDDA

VDDP

U7000

B5

P_IN

C5

CSIN

D5

CSIP

PBUS_PWR

A5

D3

AUX_DET

VDDIO1P8

F5

G5

SDA

H5

SCL

SMC_RST_IN

G2

HPWR_EN*

G3

E5

COMP

G4 H2

CELL

B2

NC0

C2

NC1

E4

ISL9240

WCSP

OMIT_TABLE

AGND

PGND
E2

E3

C7077

10UF

20%
25V

X5R-CERM

0603

GATE_Q1

BOOT1

LX1
GATE_Q2
GATE_Q3

LX2

BOOT2

GATE_Q4

PBUS

CSOP

CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ*
CBC_ON
EN_MVR

AUX_OK

AMON
BMONNC2

1

2

H1
F1
G1
E1
D1
B1
C1
A1
A3
A4

CHGR_CSO_P

B4

CHGR_CSO_N

B3

CHGR_BGATE

CHGR_VBAT

C3
F2

TP_CHGR_EN_VR1

H4

TP_CHGR_SMC_RST_L

H3

CHGR_INT_L
CHGR_CBC_ON

F4

CHGR_EN_MVR

F3

NC_CHGR_AUX_OK

D4

CHGR_AMON

C4

CHGR_BMON

OUT
OUT
OUT
OUT
OUT
OUT

77

80

53

53

B

1

PLACE_NEAR=U7000.A4:1MM

C7020

0.47UF

2 1

20%

4V

CERM-X5R-1

201

77 47

119 67

C7061

0.047UF

CER-X7R

10%
50V

0402

1

2

C7062

1

0.047UF

10%
50V

2

CER-X7R
0402

C7063

1

4700PF

10%
25V

2

CER-X5R
0201

SYNC_MASTER=ZIFENG SYNC_DATE=05/24/2017

PAGE TITLE

PBUS Supply & Battery Charger

R7063

Apple Inc.

1K

1%

1/20W

MF

201

2

A

DRAWING NUMBER

051-02643

REVISION

SIZE

D

4.0.0

BRANCH

evt-0

PAGE

70 OF 200

SHEET

68 OF 131

BOM_COST_GROUP=PLATFORM POWER

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

C

B

A

8

9 8

IN

IN

72 69

72

72 69

72 69

71 69

8

9 8

CPU_VCCGTSENSE_N

IN

IN

IN

IN

CPUGT_ISUMP

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISEN2

R7160

88.7K

1%

1/20W

MF

201

IN

CPUSA_ISUMP

C7181

71

IN

CPUSA_ISUMN

R7190

2 1

CPU_VCCSASENSE_P

IN

CPU_VCCSASENSE_N

IN

C7154

0.01UF

X7R-CERM

21

C7160

150PF

2 1

CER-C0G

220PF

10%
25V

X7R-CERM

201

C7182

0.01UF

10%
10V

X7R-CERM

0201

100K

1%

1/20W

MF

201

C7141

C7151

220PF

X7R-CERM

1

10%
10V

2

0201

IMON_B_CPUGT

5%

50V

0201

1

2

1

2

C7190

150PF

2 1

5%

50V

CER-C0G

0201

C7153

0.01UF

X7R-CERM

R7181

1K

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

R7142

NO_XNET_CONNECTION=1

1

330PF

10%
16V

2

X7R

1

10%

2

25V
201

1

10%
10V

2

0201

C7152

1

2

69

R7180

499

2 1

1%

1/20W

MF

201

21

SA_ISUMN_R

IMON_C_CPUSA

NO_XNET_CONNECTION=1

C7171

330PF

10%
16V
X7R

0201

1

2

0

21

5%

1/20W

MF

0201

XW7140

C7142

1

330PF

10%
16V

2

X7R
02010201

R7151

1/20W

0.01UF

10%
10V
X7R-CERM
0201

C7180

3300PF

X7R-CERM

R7172

0

5%

1/20W

MF

0201

C7172

1

330PF

10%

2

16V
X7R
0201

FB_GT_R

C7144

3300PF

2 1

10%
10V

X7R-CERM

0201

SM

21

R7150

332

2 1

1%

1/20W

MF

201

1K

21

1%

GT_ISUMN_R

MF

201

C7161

6800PF

2 1

COMP_B_CPUGT_L

10%
10V

X7R-CERM

0201

21

10%
10V

0201

69

FB_SA_R

21

XW7170

C7174

1000PF

2 1

SM

R7143

1.8K

1%

1/20W

MF

201

FB_B_GT_R

RTN_B_CPUGT

CPU VCC GT + GTx Merged

C7162

68PF

2 1

5%
25V
C0G

0201

CPUSA_ISUMN_R

C7191

6800PF

2 1

10%
10V

X7R-CERM

0201

R7173

2.49K

2 1

1%

1/20W

MF

201

FB_C_SA_R

10%
25V
X5R

0201

21

RTN_C_CPUSA

21

R7144

1K

2 1

1%

1/20W

MF

201

69

115

CPUGT_ISUMN_R

C7150

3300PF

21

10%
10V

X7R-CERM

0201

COMP_B_CPUGT

R7161

4.64K

2 1

1%

1/20W

MF

201

CPU VCC SA

69

C7192

150PF

2 1

5%

50V

CER-C0G

0201

COMP_C_CPUSA_L

R7174

1K

2 1

1%

1/20W

MF

201

69

FB_B_CPUGT

R7145

560

1%

1/20W

MF

201

FB_B_CPUGT_RC

21

C7143

1

1.2NF

+/-10%
10V

2

CERM
0201-1

PPBUS_HS_CPU

69

72

72

72

72 69

72 69

72 69

69

71

71

71 69

R7191

2.7K

2 1

1%

1/20W

MF

201

FB_C_CPUSA

R7175

560

1%

1/20W

MF

201

FB_C_CPUSA_RC

21

1

2

69

R7101

10

21

5%

1/20W

MF

201

OUT

OUT
OUT

IN

69 69

IN
IN

69

69

69

69

69

OUT

OUT

IN

69

69

69

69

69

69

69

69

69

69

COMP_C_CPUSA

CPUGT_FCCM
CPUGT_PWM1

CPUGT_PWM2

CPUGT_ISUMP
CPUGT_ISUMN_R

CPUGT_ISEN1
CPUGT_ISEN2

COMP_B_CPUGT
FB_B_CPUGT
RTN_B_CPUGT
IMON_B_CPUGT
NTC_B_CPUGT

CPUSA_FCCM
CPUSA_PWM
CPUSA_ISUMP

CPUSA_ISUMN_R
COMP_C_CPUSA
FB_C_CPUSA
RTN_C_CPUSA
IMON_C_CPUSA
PROG1_CPUCOREVR

PROG2_CPUCOREVR
PROG3_CPUCOREVR
PROG4_CPUCOREVR
PROG5_CPUCOREVR

69

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=12.6V

1

C7101

0.22UF

10%

2

25V
X7R
0402

11 24
12 25

13 26

7 19
8 20

9 21

10 22

4 16
5 17
6 18
2 14
3 15

34
35 47
32

33
29
30

28
40

39
38
37
36

FCCM_B
PWM1_B

PWM2_B

ISUMP_B
ISUMN_B

ISEN1_B
ISEN2_B

COMP_B
FB_B
RTN_B
IMON_B
NTC_B

FCCM_C

PWM_C

ISUMP_C
ISUMN_C

COMP_C
FB_C
RTN_C
IMON_C
PROG1

PROG2
PROG3
PROG4
PROG5

41
VIN

U7100

ISL95828HRTZ

LLP

OMIT_TABLE

THRM_PAD
49

PP5V_COREVR_VCCPPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

42

VCC

FCCM_A

PWM1_A
PWM2_A
PWM3_A

ISUMP_A
ISUMN_A

ISEN1_A
ISEN2_A
ISEN3_A

COMP_A

FB_A

RTN_A

IMON_A

NTC_A

VR_HOT*

VR_READY

VR_ENABLE

SDA

ALERT*

SCLK
PSYS

27

23

46

48

43
44
4531
1

CPUCORE_FCCM
CPUCORE_PWM1

CPUCORE_PWM2
CPUCORE_PWM3

CPUCORE_ISUMP
CPUCORE_ISUMN_R

CPUCORE_ISEN1
CPUCORE_ISEN2
CPUCORE_ISEN3

COMP_A_CPUCORE
FB_A_CPUCORE
RTN_A_CPUCORE
IMON_A_CPUCORE
NTC_A_CPUCORE

CPUCORE_PROCHOT_R_L
CPUVR_PGOOD

CPU_VR_EN_R

CPUCORE_VIDSOUT_R
CPUCORE_VIDALERT_R_L
CPUCORE_VIDSCLK_R

R7100

1/20W

201

1

C7100

1UF

10%

2

10V
CER-X6S
0402

1

5%
MF

CPUCORE_PSYS

C7108

1

4700PF

10%

2

10V
X7R
201

69

69

PROG3_CPUCOREVR

PROG4_CPUCOREVR

1

R7114

182K

1%
1/20W
MF
201

2

1

R7115

121K

1%
1/20W
MF
201

2

69

69

PROG5_CPUCOREVR

C7173

680PF

10%
25V
X7R-CERM
0201

1

R7111

110K

1%
1/20W
MF
201

2

PROG1_CPUCOREVR

PROG2_CPUCOREVR

1

R7112

215K

1%
1/20W
MF
201

2

1

R7113

1.87K

1%
1/20W
MF
201

2

21

69

69

69

69

69

R7106

NOSTUFF

1

R7107

12.1K

1%
1/20W
MF
201

2

1

R7108

12.1K

1%
1/20W
MF
201

2

69

PP5V_G3S

70

OUT

70

OUT

70

OUT

70

OUT

70 69

IN

70 69

IN

70 69

IN

70 69

IN

PP1V8_S5

1

2

OUT

R7103

49.9

1/20W

1%
MF

201

21

PP5V_G3S

69 70 71 116

CPU VCC Core

R7163

10K

5%
1/20W
MF
201

R7102

100

80

0

21

5%

1/20W

MF

0201

SVID_PU:CORE

1

R7110

45.3

1%
1/20W
MF
201

2

R7105

0

5%

1/20W

MF

0201

69

69 69

5%

1/20W

MF

201

21

69 70 71 116

NTC_B_CPUGT

69

74 78 80

21

R7104

10

5%

1/20W

MF

201

FB_A_CPUCORECPU_VCCGTSENSE_P

FB_A_CPUCORE_RC

C7148

390PF

69

CPUCORE_ISUMN_R

5%
25V
C0G

0201

1

2

SMC_PROCHOT_L

CPU_VCCST_PWRGD

PP1V05_S3

R7149

560

1%

1/20W

MF

201

C7155

3300PF

21

10%
10V

X7R-CERM

0201

OUT

21

IN

R7148

1K

21

1%

1/20W

MF

201

RTN_A_CPUCORE

69

R7154

442

1%

1/20W

MF

201

CORE_ISUMN_R

47 46 39

80

115

SVID_PU:CORE

1

R7109

100

1%
1/20W
MF
201

2

CPU_VIDSOUT

21

CPU_VIDALERT_L

CPU_VIDSCLK

8

BI

8

IN

8

IN

R7121

17.8K

1%
MF

1/20W

201

21

NTC_B_CPUGT_R

R7120

17.8K

1%MF1/20W

201

21

NTC_A_CPUCORE_RNTC_A_CPUCORE

1

R7123

220KOHM-3%

0201

2

NTC_A_CPUCORE_XW

2

XW7123

BOM_COST_GROUP=CPU & CHIPSET

SM

1

R7147

4.75K

1/20W

1%
MF

201

21

FB_CORE_R

FB_A_CORE_R

X5R-X7R-CERM

XW7141

21

R7155

1K

21

1%

1/20W

MF

201

COMP_A_CPUCORE

69

1

R7124

220KOHM-3%

0201

2

NTC_B_CPUCORE_XW

2

XW7124

SM

1

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NO_XNET_CONNECTION=1

C7145

1

330PF

10%

2

16V
X7R
0201

C7158

1

0.01UF

10%

2

10V
X7R-CERM
0201

21

1%

1/20W

MF

201

COMP_A_CPUCORE_L

CPU_VCCSENSE_P

C7147

470PF

21

10%
16V

0201

SM

2 1

C7146

C7156

1

2

C7149

1

0.01UF

10%

2

10V
X7R-CERM
0201

69

R7146

0

2 1

5%

1/20W

MF

0201

NO_XNET_CONNECTION=1

1

330PF

10%

2

16V
X7R

0201

220PF

10%
25V
X7R-CERM
201

C7157

1

0.01UF

10%

2

10V
X7R-CERM
0201

R7193

2.87K

IMON_A_CPUCORE

IMVP IC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

CPU_VCCSENSE_N

CPUCORE_ISUMP

CPUCORE_ISUMN

CPUCORE_ISEN1
CPUCORE_ISEN2
CPUCORE_ISEN3

C7159

1

0.01UF

10%

2

10V
X7R-CERM
0201

C7193

56PF

21

5%

25V

NP0-C0G

0201

C7195

150PF

5%

50V

CER-C0G

0201

21

C7194

6800PF

R7194

102K

1/20W

201

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

IN

IN

IN

IN

IN

21

10%
10V

X7R-CERM

0201

21

1%
MF

051-02643

4.0.0

evt-0
71 OF 200
69 OF 131

8

IN

D

9 8

IN

70 69

70

C

70 69

70 69

70 69

B

SYNC_DATE=05/24/2017SYNC_MASTER=SILU

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

PPBUS_HS_CPU

70 115

PP5V_G3S

69 70 71
116

70 115

PPBUS_HS_CPU

R7216

1

5%
1/16W
MF-LF

402

70

PVCCCORE_PH1_AGND

70 69

69

IN

IN

CPUCORE_FCCM

CPUCORE_PWM1

CPU VCC Phase 1

PVCCCORE_PH1_VCC

21

C7217

2.2UF

20%
25V

X6S-CERM

0402

1

2

353S00519 & 353S00831

8
9

2
1

30 33
31

NC
NC

NC
NC

PVCCCORE_PH1_AGND

70

3

29

VCC

PVCC

U7210

VIN
VIN

FCCM
PWM

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

AGND
4

PLACE_NEAR=U7210.32:2MM

32

XW7210

2 1

PGND
12

SM

OMIT_TABLE

BOOT

PHASE

SW
SW

GL0
GL1

GH

PGND
28

5
7
16

24
27

6

NC
NC

NC

1

C7216

2.2UF

20%

2

25V
X6S-CERM
0402

CRITICAL

1

C7251

33UF

20%
16V

2

TANT-POLY
CASE-B3

CAPDERATE

CPUCORE_SW1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUCORE_BP1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CAPDERATE

CPUCORE_PHASE1

CRITICAL

1

C7252

33UF

20%

2

16V
TANT-POLY
CASE-B3

R7219

0

5%
1/16W
MF-LF

402

C7219

0.22UF

10%
25V
X7R

0402

CRITICAL

1

C7253

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

1

C7254

33UF

20%
16V

2

TANT-POLY
CASE-B3

CAPDERATE

CAPDERATE

L7211

0.15UH-20%-50A-0.0008OHM

21

PPVCC_CPU_PH1

PILE083T

CRITICAL

152S00772 & 152S00782

1

R7218

2.2

5%
1/10W
MF-LF
603

1

2

1

2

2

CPUCORE_SW1_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7218

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

CRITICAL

1

C7255

33UF

20%
16V

2

TANT-POLY
CASE-B3

CAPDERATE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V

NO_XNET_CONNECTION

CAPDERATE

1K

1%

1/20W

MF

201

1

2

R7212

CRITICAL

1

C7256

33UF

20%

2

16V
TANT-POLY
CASE-B3

R7210

0.0005

1%
1W
MF

0612-2

21
43

1

R7213

200K

1%
1/20W
MF
201

2

CRITICAL

1

C7257

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

CRITICAL

CPUCORE_ISNS1_P
CPUCORE_ISNS1_N

1

R7211

2.2

NO_XNET_CONNECTION

1%
1/20W
MF
201

2

NO_XNET_CONNECTION

7x 33uF B3

1

C7258

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

C7259

33UF

2

CAPDERATE

OUT
OUT

CPUCORE_ISUMN

CPUCORE_ISEN1

CPUCORE_ISUMP

20%
16V
TANT-POLY
CASE-B3

54

70 54

6X 2.2UF 0402

THESE TWO CAPS ARE FOR EMC

C7290

1

0.001UF

10%
50V

2

X7R-CERM
0402

OUT

69

OUT

OUT

70 69

70 69

1

2

R7214

200K

2 1

1/20W

C7291

0.001UF

10%
50V
X7R-CERM
0402

1%

MF

201

R7215

200K

2 1

1%

1/20W

MF

201

CRITICAL

1

C7295

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

CPUCORE_ISNS2_N

NO_XNET_CONNECTION

CPUCORE_ISNS3_N

NO_XNET_CONNECTION

CRITICAL

1

C7260

33UF

20%
16V

2

TANT-POLY
CASE-B3

CAPDERATE

70 54

CRITICAL

1

C7261

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

70 54

CAPDERATE

CRITICAL

1

C7262

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

1

C7263

33UF

20%
16V

2

TANT-POLY
CASE-B3

CAPDERATE

CRITICAL

1

2

CAPDERATE

PPVCC_S0_CPU

Vout = 0.55 - 1.5V
ICCMAX = 128A
F = 750kHz

C7264

33UF

20%
16V
TANT-POLY
CASE-B3

115

CAPDERATE

CRITICAL

1

C7265

33UF

20%
16V

2

TANT-POLY
CASE-B3

D

C

B

69 70 71

PP5V_G3S

116

70

PVCCCORE_PH2_AGND

CPU VCC Phase 2

70 69

69

R7226

1

5%
1/16W
MF-LF

402

IN

IN

PVCCCORE_PH2_VCC

21

C7227

2.2UF

X6S-CERM

CPUCORE_FCCM

CPUCORE_PWM2

20%
25V

0402

1

2

353S00519 & 353S00831

8
9

2
1

30 33
31

NC
NC

NC
NC

70

PVCCCORE_PH2_AGND

3

29

VCC

PVCC

U7220

VIN
VIN

FCCM
PWM

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

AGND
4

32

XW7220

2 1

PGND
12

SM

OMIT_TABLE

BOOT

PHASE

SW
SW

GL0
GL1

GH

PGND
28

5
7
16

24
27

6

NC
NC

NC

C7226

1

2.2UF

20%

2

25V
X6S-CERM
0402

CPUCORE_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUCORE_BP2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUCORE_PHASE2

R7229

1/16W
MF-LF

C7229

0.22UF

10%
25V
X7R

0402

L7221

0.15UH-20%-50A-0.0008OHM

21

PILE083T

CRITICAL

152S00772 & 152S00782

1

R7228

2.2

5%
1/10W
MF-LF
603

2

CPUCORE_SW2_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7228

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

5%

402

1

0

2

1

2

PPVCC_CPU_PH2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V

NO_XNET_CONNECTION

R7222

1K

1%

1/20W

MF

201

R7220

0.0005

1

2

C7271

2.2UF

X6S-CERM

0402

1%
1W
MF

0612-2

1

R7223

200K

1/20W
MF
201

2

1

20%
25V

2

CRITICAL

21
43

1

R7221

2.2

1%

NO_XNET_CONNECTION

1/20W
MF
201

2

NO_XNET_CONNECTION

C7272

2.2UF

X6S-CERM

0402

20%
25V

1

2

CPUCORE_ISNS2_P
CPUCORE_ISNS2_N

C7273

2.2UF

X6S-CERM

0402

20%
25V

1

2

OUT
OUT

CPUCORE_ISUMN

CPUCORE_ISEN2

CPUCORE_ISUMP

C7274

2.2UF

X6S-CERM

54

70 54

20%
25V

0402

OUT

OUT

OUT

THESE TWO CAPS ARE FOR EMC

1

1

C7275

2.2UF

2

70 69

69

70 69

X6S-CERM

0402

1

20%
25V

2

R7224

200K

2 1

1%

1/20W1%

MF

201

C7299

2.2UF

X6S-CERM

CPUCORE_ISNS1_N

R7225

200K

2 1

1%

1/20W

MF

201

1

20%
25V

2

0402

NO_XNET_CONNECTION

CPUCORE_ISNS3_N

NO_XNET_CONNECTION

C7292

0.001UF

10%
50V

2

X7R-CERM
0402

70 54

1

C7293

0.001UF

10%
50V

2

X7R-CERM
0402

70 54

C

B

A

PPBUS_HS_CPU

70 115

69 70 71

PP5V_G3S

116

PVCCCORE_PH3_AGND

70

CPU VCC Phase 3

70 69

69

R7236

1

5%
1/16W
MF-LF

402

IN

IN

PVCCCORE_PH3_VCC

21

C7237

2.2UF

X6S-CERM

CPUCORE_FCCM

CPUCORE_PWM3

20%
25V

0402

1

2

353S00519 & 353S00831

8
9

2
1

30 33
31

NC
NC

NC
NC

PVCCCORE_PH3_AGND

70

PLACE_NEAR=U7220.32:2MM

3

29

VCC

PVCC

U7230

VIN
VIN

FCCM
PWM

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

AGND
4

PLACE_NEAR=U7230.32:2MM

32

XW7230

2 1

PGND
12

SM

OMIT_TABLE

BOOT

PHASE

SW
SW

GL0
GL1

GH

PGND
28

5
7
16

24
27

6

NC
NC

NC

C7236

1

2.2UF

20%

2

25V
X6S-CERM
0402

CPUCORE_SW3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUCORE_BP3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUCORE_PHASE3

R7239

1/16W
MF-LF

C7239

0.22UF

10%
25V
X7R

0402

5%

402

L7231

0.15UH-20%-50A-0.0008OHM

PILE083T

CRITICAL

1

1

0

2

1

2

2

CPUCORE_SW3_SNUB

DIDT=TRUE

1

2

152S00772 & 152S00782

R7238

2.2

5%
1/10W
MF-LF
603

NOSTUFF

C7238

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

21

PPVCC_CPU_PH3

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.15V

NO_XNET_CONNECTION

CRITICAL

R7232

1K

1%

1/20W

MF

201

R7230

0.0005

0612-2

2 1
4 3

1

2

1%
1W
MF

1

R7231

2.2

1%
1/20W
MF
201

2

1

R7233

200K

1%
1/20W
MF
201

2

CPUCORE_ISNS3_P
CPUCORE_ISNS3_N

NO_XNET_CONNECTION

NO_XNET_CONNECTION

OUT
OUT

CPUCORE_ISUMN

CPUCORE_ISEN3

CPUCORE_ISUMP

54

70 54

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL3353S00519

A

D

DRAWING NUMBER

051-02643

REVISION

SYNC_DATE=05/24/2017SYNC_MASTER=SILU

SIZE

OUT

OUT

OUT

69

IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5

70 69

R7234

200K

2 1

1%

1/20W

MF

201

R7235

2 1

70 69

CPUCORE_ISNS1_N

NO_XNET_CONNECTION

200K

1%

1/20W

MF

201

CPUCORE_ISNS2_N

NO_XNET_CONNECTION

70 54

PAGE TITLE

70 54

U7210,U7220,U7230

IMVP VCC Block

Apple Inc.

4.0.0

BRANCH

evt-0

PAGE

72 OF 200

SHEET

70 OF 131

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

PPBUS_HS_CPU

115

69 70 116

PP5V_G3S

PVCCCSA_AGND

71

69

IN

69

IN

CPU VCCSA

R7375

1

5%
1/16W
MF-LF

402

21

PVCCCSA_VCIN

C7377

CPUSA_FCCM

CPUSA_PWM

1

2.2UF

20%

2

25V

X6S-CERM

0402

NC

OMIT_TABLE

353S00525 & 353S4471

11

2

VCIN

VDRV

U7370

SIC535CD

6

VIN

1

ZCD_EN*

12

PWM

3

NC

XW7370

2 1

PLACE_NEAR=U7370.10:2MM

MLP4535

CRITICAL

PGND

PGND

7

10

SM

PVCCCSA_AGND

71

CGND

13

BOOT

PHASE

VSWH

GL
GL

5

8

9
14

CAPDERATE

CAPDERATE

CAPDERATE

CAPDERATE

3X 33UF B3 2X 2.2UF 0402

CRITICAL

1

C7380

33UF

20%
16V

2

TANT-POLY

1

C7376

2.2UF

20%

2

25V
X6S-CERM
0402

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

SWITCH_NODE=TRUE

4

NC
NC

CPUSA_BOOTSA

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUSA_PHASESA

CPUSA_BPSA

DIDT=TRUE

C7379

0.22UF

R7379

0

5%
1/16W
MF-LF

402

10%
25V
X7R

0402

1

2

1

2

152S00689/152S00707

CRITICAL

L7330

0.47UH-20%-17.5A-0.0047OHM

21

PPVCCSA_CPU_RCPUVR_SWSA

PIMA052D-SM

1

R7378

2.2

5%
1/10W
MF-LF
603

2

CPUSA_SW_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7378

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200DIDT=TRUE
VOLTAGE=1.15V

CRITICAL

R7370

0.002

1%

1/2W

MF

0306

21
43

R7372

CASE-B3

CPUSA_ISNS_P
CPUSA_ISNS_N

NO_XNET_CONNECTION=1

0

21

5%

1/20W

MF

0201

R7374

1K

1%

1/20W

MF

201

CRITICAL

1

C7381

33UF

20%
16V

2

TANT-POLY
CASE-B3

CPUSA_ISUMN

21

CPUSA_ISUMP

NO_XNET_CONNECTION=1

CRITICAL

1

C7382

33UF

20%

2

16V
TANT-POLY
CASE-B3

OUT
OUT

1

C7383

33UF

20%

2

16V
TANT-POLY
CASE-B3

C7395

2.2UF

20%
25V

X6S-CERM

0402

1

C7396

2.2UF

2

X6S-CERM

0402

20%
25V

1

2

D

PPVCCSA_S0_CPU

121 56

121 56

69

OUT

69

OUT

Vout = 0.55 - 1.15V
ICCMAX = 11.1A
F = 750kHz

115

C

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1353S00525 CRITICAL

IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5

U7370

C

B

B

A

8

SYNC_DATE=05/10/2017SYNC_MASTER=SILU

PAGE TITLE

A

IMVP SA Block

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

73 OF 200

SHEET

71 OF 131

1

678

3 245

1

D

72 115

72 116

PPBUS_HS_CPU

72 115

PPBUS_HS_CPU

PP5V_G3S

R7416

1

21

5%
1/16W
MF-LF

402

72

PVCCCGT_PH1_AGND

72 69

69

IN

IN

CPU VCCGT Phase 1

PVCCCGT_PH1_VCC

C7417

2.2UF

20%
25V

X6S-CERM

0402

CPUGT_FCCM

CPUGT_PWM1

353S00525 & 353S4471

1

2

OMIT_TABLE

NC

6
1

ZCD_EN*

12

3

VIN

PWM
NC

2

VCIN

U7410

SIC535CD

MLP4535

CRITICAL

PGND

7

10

XW7410

SM

2 1

72

C7416

4

5

8

9
14

NC
NC

1

2

2.2UF

20%
25V
X6S-CERM
0402

11

VDRV

BOOT

PHASE

VSWH

GL
GL

CGND

13

PVCCCGT_PH1_AGND

PLACE_NEAR=U7410.10:2MM

CAPDERATE

CRITICAL

1

C7400

33UF

20%

2

16V
TANT-POLY
CASE-B3

CPUGT_SW1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

CPUGT_BOOT1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUGT_BP1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUGT_PHASE1

CAPDERATE

CRITICAL

1

C7401

33UF

20%

2

16V
TANT-POLY
CASE-B3

1/16W
MF-LF

10%
25V
X7R

0402

5%

402

1

0

2

1

2

R7419

C7419

0.22UF

CAPDERATE

CRITICAL

1

C7402

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

CRITICAL

1

C7403

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

L7410

0.22UH-20%-22A-0.0042OHM

21

PPVCCGT_CPU_PH1

IHLP2020BD-SM

152S00412

1

R7418

2.2

5%
1/10W
MF-LF
603

2

CPUGT_SW1_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7418

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V

NO_XNET_CONNECTION

CAPDERATE

CRITICAL

1

C7404

33UF

20%

2

16V
TANT-POLY
CASE-B3

R7412

1/20W

1K

1%

MF

201

1

2

CAPDERATE

CRITICAL

1

C7405

33UF

20%

2

16V
TANT-POLY
CASE-B3

R7410

0.001

1%

1/2W

MF

0306

2 1
4 3

1

2

1

R7413

200K

1%
1/20W
MF
201

2

CRITICAL

1

C7406

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

CPUGT_ISNS1_P
CPUGT_ISNS1_N

R7411

2.2

1%
1/20W
MF
201

NO_XNET_CONNECTION

NO_XNET_CONNECTION

CAPDERATE

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISUMP

4x 2.2uF 0402

7X 33UF B3

56

OUT
OUT

72 56

OUT

OUT

OUT

69

PPVCCGT_S0_CPU

115

D

Vout = 0.55 - 1.5V
ICCMAX = 32A
F = 750kHz

72 69

R7414

200K

2 1

1%

1/20W

MF

201

72 69

CPUGT_ISNS2_N

NO_XNET_CONNECTION

72 56

C

R7426

69

1

5%
1/16W
MF-LF

402

IN

IN

21

72 116

PP5V_G3S

72

PVCCCGT_PH2_AGND

72 69

CPU VCCGT Phase 2

PVCCCGT_PH2_VCC

C7427

2.2UF

20%
25V

X6S-CERM

0402

CPUGT_FCCM

CPUGT_PWM2

353S00525 & 353S4471

1

2

OMIT_TABLE

NC

72 116

6
1

12

3

PP5V_G3S

VIN

ZCD_EN*

PWM
NC

XW7420

2 1

2

11

VCIN

VDRV PGND

U7420

SIC535CD

MLP4535

CRITICAL

PGND

PGND

CGND

7

10

13

SM

72

PVCCCGT_PH2_AGND

C7426

1

2.2UF

20%

2

25V
X6S-CERM
0402

GL
GL

4

5

8

9
14

NC
NC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

BOOT

PHASE

VSWH

CPUGT_PHASE2

PLACE_NEAR=U7420.10:2MM

CPUGT_BOOT2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

CPUGT_BP2

MIN_LINE_WIDTH=0.2000

DIDT=TRUEMIN_NECK_WIDTH=0.1200

CPUGT_SW2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

R7429

1/16W
MF-LF

402

C7429

0.22UF

10%
25V
X7R

0402

C7420

2.2UF

20%
25V

0402

1

C7421

2.2UF

2

X6S-CERMX6S-CERM

0402

20%
25V

1

2

C7422

2.2UF

20%
25V

X6S-CERM

0402

1

2

C7423

2.2UF

20%
25V

X6S-CERM

0402

1

2

C

CRITICAL

L7420

0.22UH-20%-22A-0.0042OHM

21

PPVCCGT_CPU_PH2

IHLP2020BD-SM

152S00412

1

R7428

2.2

5%
1/10W
MF-LF
603

1

0

5%

2

1

2

2

CPUGT_SW2_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7428

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V

NO_XNET_CONNECTION

R7422

1K

1%

1/20W

MF

201

R7420

0.001

2 1
4 3

1

2

1%

1/2W

MF

0306

1

R7421

2.2

1%
1/20W
MF
201

2

1

R7423

200K

1%
1/20W
MF
201

2

CRITICAL

CPUGT_ISNS2_P
CPUGT_ISNS2_N

NO_XNET_CONNECTION

NO_XNET_CONNECTION

CPUGT_ISUMN

CPUGT_ISEN2

CPUGT_ISUMP

OUT
OUT

56

72 56

69

72 69

R7424

200K

2 1

1%

1/20W

MF

201

72 69

CPUGT_ISNS1_N

NO_XNET_CONNECTION

72 56

OUT

OUT

OUT

B

B

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

2 CRITICAL353S00525

IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5

U7410,U7420

A

8

SYNC_MASTER=SILU SYNC_DATE=05/24/2017

PAGE TITLE

A

IMVP GT Block

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

74 OF 200

SHEET

72 OF 131

1

678

3 245

1

D

C

B

115

PPBUS_HS_OTH5V

116 73

C7608

1

2.2UF

20%

2

25V
X6S-CERM
0402

PP5V_G3S

VOUT = 5V

1.58A MAX OUTPUT
F = 500 KHZ

C7606

2.2UF

X6S-CERM

20%
25V

0402

1

2

P5VG3S_VFB1_R

1

R7677

200

1%
1/20W
MF
201

2

5VG3S_VFB1_RR

1

R7678

41.2K

0.1%
1/16W
MF
0402

2

1

R7679

10K

0.1%
1/16W
MF
0402

2

CAPDERATE

C7600

33UF

TANT-POLY

CASE-B3

CAPDERATE

TANT-POLY

CASE-B1S-1

1

C7605

150UF

20%

2

6.3V
TANT-POLY
CASE-B1S-1

CAPDERATE

1

20%

2

16V

C7607

150UF

20%

6.3V

XW7675

XW7671

NO_XNET_CONNECTION=1

5V S0 - V5

1

C7601

2.2UF

20%

2

25V
X6S-CERM
0402

OMIT_TABLE

1

CRITICAL

L7600

2.2UH-20%-4.5A-0.043OHM

PIMA042T-COMBO

MIN_LINE_WIDTH=0.2000

2

MIN_NECK_WIDTH=0.1200

1

2

2

SM

1

SM

P5VG3S_VSW

NO STUFF

1

R7674

1

5%
1/10W
MF-LF

PLACE_NEAR=C7607.1:3MM

PLACE_NEAR=L7600.1:3MM

2

1

603

2

P5VG3S_SNUBR

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE SWITCH_NODE=TRUE
SWITCH_NODE=TRUE

PLACE_NEAR=L7600.2:3MM

2

XW7670

SM

NO_XNET_CONNECTION=1

1

P5VG3S_CSP1_R

1

C7602

2.2UF

20%

2

25V
X6S-CERM
0402

1

6
7
8

NO STUFF

1

C7674

0.0033UF

10%
50V

2

X7R-CERM
0402

DIDT=TRUE

CRITICAL

U7600

CSD58879Q3D

Q3D

VIN

VSW

PGND

9

TG

TGR

BG

R7672

4.87K

3

4

5

1%

1/20W

MF

201

D

3.3V DSW - V6

115

PPBUS_HS_3V3G3H_T

C7650

1.0UF

0402

P5VG3S_TG

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

SKIP_5V3V3:AUDIBLE

P5VG3S_VBST_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

C7609

1

0.1UF

10%

2

25V
X6S-CERM
0201

MIN_LINE_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000 DIDT=TRUESWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000 DIDT=TRUE
MIN_NECK_WIDTH=0.1200

C7673

0.1UF

21

10%

6.3V
X7R

0201

R7673

698

1

2

1/20W

201

21

1%
MF

R7609

0

5%

1/20W

MF

0201

1

2

GATE_NODE=TRUE

C7678

270PF

10%
16V

X7R-CERM

0201-1

SKIP_5V3V3:INAUDIBLE

1

R7665

1

5%
1/20W
MF
201

2

1

2

1

10%

2

25V
X6S

R7651

1/20W

BOMOPTION=NOSTUFF

1

R7676

10K

1%
1/20W
MF
201

2

1

0

5%
MF

0201

2

73

73 77 119

P5VS4_COMP1_R

C7679

1

4700PF

10%

2

10V
X7R
201

(P5VP3V3_VREF2)

116 73

P5VP3V3_SKIPSEL

P5VG3S_VBST

DIDT=TRUESWITCH_NODE=TRUE SWITCH_NODE=TRUEDIDT=TRUE

P5VG3S_DRVH
P5VG3S_SW
P5VG3S_DRVL
P5VG3S_CSP1

P5VG3S_CSN1

P5VG3S_VFB1
P5VG3S_COMP1

P5VG3S_EN_R
P5VG3S_PGOOD

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PP5V_G3S

1

R7650

0

5%

1/20W

MF

0201

2

R7675

3.92K

1%

1/20W

MF

201

PP1V8_G3S

116

2

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

VBST1 VBST2
DRVH1 DRVH2
SW1 SW2
DRVL1
CSP1

CSN1 CSN2

11

MODE

COMP1 COMP2
EN1 EN2

PGOOD1 PGOOD2

GND

1

2

XW7650

PLACE_NEAR=U7650.28:1MM

23
VIN

29

VREG5

CRITICAL

U7650

QFN

28

2

SM

1

22

VREG3

13

VREF2

TPS51980A

DRVL2

CSP2

VFB2VFB1

THRM_PAD

33

P5VP3V3_VREG3
P5VP3V3_VREF2

C7652

0.22UF

CERM

12

EN

RF

2631
241
2532
2730
187

178
3

169
1510

214
205

P5V_3V3G3H_EN

P3V3G3H_VBST
P3V3G3H_DRVH
P3V3G3H_SW

DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000

P3V3G3H_DRVL

DIDT=TRUE

P3V3G3H_CSP2
P3V3G3H_CSN2

P3V3G3H_RF
P3V3G3H_VFB2

P3V3G3H_EN
P3V3MAIN_PGOOD

1

R7695

3.92K

1%
1/20W
MF
201

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

116 73

1

10%
10V

2

402

GATE_NODE=TRUE

BOMOPTION=NOSTUFF

2700PF

PP3V3_G3H_T

PP5V_S5_LDO

VOUT = 5V

CRITICAL

C7651

1

10UF

20%

2

10V
X5R-CERM
0402-1

C7653

1

2.2UF

10%
10V

2

X5R-CERM
0402

73

GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000

73

73 77

10K

1%

1/20W

MF

201

1

2

1

2

R7696

C7699

10%
16V
X7R

0201

100MA MAX OUTPUT

R7685

1

5%

1/20W

MF

201

P3V3G3H_VBST_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

1

R7669

0

5%
1/20W
MF
0201

2

MIN_LINE_WIDTH=0.2000DIDT=TRUE
MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

MIN_NECK_WIDTH=0.1200

R7655

200K

1%

1/20W

MF

201

C7698

1

330PF

10%
16V

2

X7R
0201

P3V3G3H_TG

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE

1

2

0.1UF

X6S-CERM

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

C7671

10%
25V

0201

1

2

3

4

5

CRITICAL

C7693

0.1UF

21

10%

6.3V
X7R

0201

R7693

1.37K

1/20W

201

1%
MF

21

1

R7692

3.83K

1%
1/20W
MF
201

2

P3V3G3H_CSP2_R

1.0UH-20%-14A-0.0107OHM

U7660

CSD58873Q3D

Q3D

TG

TGR

BG

9

CRITICAL

1

C7660

33UF

20%

2

16V
TANT-POLY
CASE-B3

APN: 152S0269

VIN

1

6

VSW

PGND

7
8

P3V3G3H_SNUBRP3V3G3H_COMP2

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

NO STUFF

C7694

1

0.001UF

10%

2

50V
X7R-CERM
0402

DIDT=TRUE

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

P3V3G3H_VSW

NO_XNET_CONNECTION=1

CAPDERATE

L7660

PIMB062D-SM

NO STUFF

R7694

1

10

5%
1/10W
MF-LF

603

2

XW7690

CAPDERATE

CRITICAL

1

C7661

33UF

20%

2

16V
TANT-POLY
CASE-B3

1

CAPDERATE

2

CRITICAL

1

C7662

33UF

20%

2

16V
TANT-POLY
CASE-B3

1

C7665

150UF

20%

2

6.3V
TANT-POLY
CASE-B1S-1

C7666

150UF

6.3V

TANT-POLY

CASE-B1S-1

PLACE_NEAR=C7665.1:6MM

2

XW7695

SM

1

PLACE_NEAR=L7660.1:3MM

P3V3G3H_VFB2_R

2

PLACE_NEAR=L7660.2:3MM

XW7691

2

SM

NO_XNET_CONNECTION=1

1

SM

1

P3V3G3H_VFB2_RR

R7697

R7698

R7699

CAPDERATE

CAPDERATE

1

20%

2

CAPDERATE

C7669

2.2UF

20%
25V

X6S-CERM

0402

1

931

1%

1/20W

MF

201

2

1

110K

0.1%

1/16W

MF

402

2

1

47K

0.1%

1/16W

TK

0402

2

CAPDERATE

CRITICAL

1

C7680

33UF

20%

2

16V
TANT-POLY
CASE-B3

PP3V3_G3H_T

VOUT = 3.3V

12.2A MAX OUTPUT
F = 500 KHZ

1

C7667

150UF

20%

2

6.3V
TANT-POLY
CASE-B1S-1

C7668

150UF

TANT-POLY

CASE-B1S-1

1

1

20%

2

6.3V

CAPDERATE

C7670

2.2UF

2

X6S-CERM

0402

C7664

2.2UF

20%
25V

X6S-CERM

0402

CAPDERATE

1

C7672

150UF

20%

2

6.3V
TANT-POLY
CASE-B1S-1

C7676

150UF

TANT-POLY

CASE-B1S-1

1

20%

2

25V

1

2

20%

6.3V

2.2UF

X6S-CERM

116 73

CAPDERATE

1

2

C7663

20%
25V

0402

1

2

C

B

A

152S00703 1

IND,MLD,2.2UH,20%,43mOHM,5.5A,4.2x4x2MM

L7600

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL

77 119

IN

PMU_PVDDMAIN_EN

R7653

1/20W

47K

5%
MF

201

100K

5%

1/20W

MF

201

1

2

R7690

100K

5%

1/20W

MF

201

1

2

73 77

OUT

P3V3MAIN_PGOOD

R7670

73 77 119

OUT

P5VG3S_PGOOD

R7652

3.3K

NOSTUFF

R7671

1/20W

1

2

0201

0

5%
MF

21

MF1/20W 2015%

P5V_3V3G3H_EN

1

C7642

1000PF

10%
25V

2

X7R
0201

73

R7691

0

21

C7640

2.2UF

20%

6.3V

X5R-CERM

0201

NOSTUFF

P3V3G3H_EN

1

2

73

77 119

IN

P5VG3S_EN P5VG3S_EN_R

1/20W

0201

C7641

X5R-CERM

NOSTUFF

21

5%
MF

2.2UF

20%

6.3V
0201

73

SYNC_MASTER=SILU SYNC_DATE=05/16/2017

PAGE TITLE

Power - 5V 3.3V Supply

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

BRANCH

evt-0

PAGE

76 OF 200

SHEET

73 OF 131

SIZE

47K

5%

1/20W

MF

201

1

2

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=PLATFORM POWER

IV ALL RIGHTS RESERVED

1

2

R7681

A

D

8

67

35 4

2

1

678

3 245

1

D

115

PPBUS_HS_CPU

CRITICAL

C7700

1

12PF

5%
25V

2

NP0-C0G
0201

CRITICAL

C7701

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CAPDERATE

CRITICAL

1

C7702

33UF

20%

2

16V
TANT-POLY
CASE-B3

131 77

CRITICAL

C7703

1

2.2UF

20%
25V

2

X6S-CERM
0402

IN

CRITICAL

10

5%

1/20W

MF

201

1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

2

VOLTAGE=2.5V

PPVIN_S3_DDR2V5_RC

C7704

1

2.2UF

20%
25V

2

X6S-CERM
0402

R7700

R7709

0

PVDDQ_EN PVPP_EN_R

47K

5%

1/20W

MF

201

1

2

R8153

2 1

5%

1/20W

MF

0201

C7705

0.1UF

10%
25V
X6S

0402

NOSTUFF

2.5V VPP

D7700

SOD523

K A

PP1V2_S3

74 115
122

Output voltage:
Max peak current:
Switching freq:

12

11

CRITICAL

PVIN

PVIN

U7700

10

8

13

7

1

2

TPS62130B-S

AVIN
DEF
EN
FSW

PGND

16

15

VQFN

CRITICAL

AGND

PGND

6

17

SS/TR

PAD

THRM

SW
SW
SW

VOS

FB

PG

DIDT=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

REG_PHASE_2V5S3

1
2
3

REG_VOS_P2V5S3 ISNS_2V5_S3_N

14

REG_FB_P2V5S3

5

P2V5_VPP_PGOOD

4

REG_SSTR_P2V5S3

9

XW7700

SM

2 1

74

1

C7706

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1.5UH-20%-2.61A-0.068OHM

4700PF

10%

10V

X7R
201

AGND_P2V5S3

L7700

PIFE32251B-SM

2 1

P2V5S3_REG

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

VOLTAGE=2.5V

1

R7702

162K

0.1%
1/16W
TK
0402

2

<Ra>

1

R7703

76.8K

0.1%
1/16W
MF
0402

2

<Rb>

P2V5S3_FSW

SENSOR:DEV

R7724

0.005

2 1
4 3

0306

MF

1/3W

1%

ISNS_2V5_S3_P

21

R7701

10

5%
1/20W
MF
201

XW7701

SM

21

OUT

OUT

54

54

CRITICAL

1

C7707

100UF

20%

2

6.3V
TANT-POLY
CASE-A3-LLP

NOSTUFF

CRITICAL

1

C7708

100UF

20%

2

6.3V
TANT-POLY
CASE-A3-LLP

2.5 V

2.24 A
1250 kHz

NOSTUFF

CRITICAL

C7709

1

100UF

20%

2

6.3V
TANT-POLY
CASE-A3-LLP

NOSTUFF

1

C7764

10UF

20%
4V

2

X6S
0402

PMEG3010EB/S500

D7701

SOD523

K A

PMEG3010EB/S500

PP2V5_S3

1

C7765

10UF

20%
4V

2

X6S
0402

115

D

C

B

74 115 122

116

74

74

BYPASS=U7701.6::5mm

C7715

0.1UF

115

PP1V05_PRIM

10%

6.3V
X7R

0201

1

2

PP1V2_S3

PP5V_G3S

MEMVTT_EN
P2V5_VPP_PGOOD

PLACE_NEAR=U7701.19:5mm

1

R7711

3.3K

1%
1/20W
MF
201

2

P1V2REG_VREF_R

1

R7717

21K

0.1%
1/20W
MF
0201

2

PLACE_NEAR=U7701.8:5mm

1

R7712

48.7K

0.1%
1/20W
MF
0201

2

R7754

0201 MF 1/20W05%

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

PLACE_NEAR=U7701.19:3mm

BYPASS=U7701.8::5mm

C7716

1

0.01UF

10%

2

10V
X7R-CERM
0201

P1V2REG_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=0V

LEVEL SHIFT

VOLTAGE=5V

PP5V_EDRAM_V5IN

21

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

R7756

0

5%

1/20W

MF

0201

119

R7713

47K

1%

1/20W

MF

201

1

2

1

2

1

R7755

0

5%
1/20W
MF
0201

2

MEMVTT_EN_R
PVDDQ_EN_R

P1V2REG_VREF

PVCCEDRAM_REFIN
P1V2REG_MODE

P1V2REG_TRIP

1

R7714

57.6K

1%
1/20W
MF
201

2

PLACE_NEAR=U7701.18:3mm

PP1V8_S5

BYPASS=U7701.12::10mm

C7710

1

10UF

20%

2

10V
X5R-CERM
0402-1

V5IN

S3

17

S5

16

VREF

6

REFIN

8

MODE

19

TRIP

18

PGND GND

10

80

BYPASS=U7701.2::10mm

BYPASS=U7701.2::10mm

C7714

1

10UF

20%

2

10V
X5R-CERM
0402-1

2

VLDOIN

VBST

U7701

DRVH

TPS51916

QFN

CRITICAL

VTT THRM

GND PAD

4

7

PLACE_NEAR=U7701.21:1mm

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

21

2

XW7702

1

C7711

1

10UF

20%

2

10V

SW

X5R-CERM
0402-1

1512
14
13

11
20
9
3
1

5

P1V2_VBST

SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

SWITCH_NODE=TRUE

PVTT_VTTSNS

PPVTT_VTTREF

VOLTAGE=0.6V

C7740

0.22UF

10%
16V

CERMSM

402

1.2V VDDQ & 0.6V VTT

R7730

2.2

2 1

5%

1/20W

MF

201

P1V2_DRVH

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

P1V2_SW

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

DIDT=TRUESWITCH_NODE=TRUE

P1V2_DRVL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE

PVDDQ_PGOOD

R7757

2 1

0201 5%MF

1

2

DIDT=TRUE

0

1/20W

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

P1V2_BOOT_RC

R7733

1

21

5%

1/20W

MF

201

R7732

1

21

5%

120

77 74

1/20W

MF

201

DIDT=TRUE

OUT

PLACE_NEAR=U7701.1:5mm

DDRREG_VTTSNS

PLACE_NEAR=C7737.1:5mm

C7730

1

0.1UF

10%

2

25V
X6S-CERM
0201

P1V2_DRVH_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
SWITCH_NODE=TRUE
DIDT=TRUE

P1V2_DRVL_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

XW7705

SM

21

115

PPBUS_HS_CPU

Q7700

CSD58873Q3D

TG

3

TGR

4

BG

5

Q3D

VSW

9

C7731

1

15UF

20%

2

2V
X6S
0402

VIN

PGND

1

6
7
8

C7732

1

15UF

20%

2

2V
X6S
0402

CAPDERATE

C7721

33UF

20%
16V

TANT-POLY

CASE-B3

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

SWITCH_NODE=TRUE
DIDT=TRUE

P1V2_PHASE

NOSTUFF

2.2

5%
1/10W
MF-LF

603

NOSTUFF

10%
50V

0402

1

2

1

2

R7710

C7712

0.001UF

X7R-CERM

C7733

1

15UF

20%

2

2V
X6S
0402

CAPDERATE

20%
16V

1

2

1

2

C7722

33UF

CASE-B3

152S00140

L7701

0.68UH-20%-14A

PILE063T-SM

DIDT=TRUE

SWITCH_NODE=TRUE

P1V2_LL_SNUB

C7734

1

15UF

20%

2

2V
X6S
0402

CAPDERATE

C7725

33UF

TANT-POLY

CASE-B3

21

121 54

121 54

C7736

1

15UF

20%

2

2V
X6S
0402

C7723

1

20%

2

16V

PP1V2_S3_REG_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.2V

OUT
OUT

CRITICAL

1

C7713

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

1

2.2UF

20%

2

25V
X6S-CERMTANT-POLY
0402

ISNS_CPUDDR_P
ISNS_CPUDDR_N

CRITICAL

1

C7717

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

P1V2_SNS

PP0V6_S0_DDRVTT

C7737

1

15UF

20%

2

2V
X6S
0402

C7724

1

2.2UF

20%

2

25V
X6S-CERM
0402

R7718

0.002

1%
1W

CYN

0612

2 1
4 3

CRITICAL

1

C7718

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

R7741

10

5%

1/20W

MF

201

115

CRITICAL

P1V2_SNS_R

21

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

1

C7719

10UF

20%

2

4V
X6S
0402

CRITICAL

1

C7720

10UF

20%

2

4V
X6S
0402

1

C7727

220UF

3 2

20%
2V
ELEC
SM-COMBO

PP1V2_S3

Vout = 1.2V

8.2A MAX OUTPUT
F = 400 KHZ

CRITICALCRITICAL

1

C7728

220UF

20%
2V

3 2

ELEC
SM-COMBO

74 115 122

PLACE_NEAR=C7713.1:5mm

2

XW7710

SM

1

C

B

A

119 5

PP2V5_S3

PP1V8_S5

PM_MEMVTT_EN

IN

R7758

R7716

1.5K

100K

C7790

0.1UF

10%
10V

X5R-CERM

0201

21

21

1

2

1

VCCA VCCB

U7790

SLSV1T34AMU-COMBO

2

NC

115

1% 1/20W MF 201

69 78 80

5% 1/20W MF 201

5

UDFN

CRITICAL

NC

GND

1

C7791

0.1UF

6

4

BA

10%

2

10V
X5R-CERM
0201

R7791

3

P2V5_VPP_PGOOD

PVDDQ_PGOOD

100K

5%

1/20W

MF

201

TPS51916 Ileak) = +/-1uA
Vih(min) = 1.5V
33uW when driven-low

MEMVTT_EN

1

2

74

120 77 74

74

BOM_COST_GROUP=PLATFORM POWER

SYNC_MASTER=SILU

PAGE TITLE

VR 2.5V & 1.2V/VTT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

77 OF 200

SHEET

74 OF 131

SIZE

D

SYNC_DATE=05/01/2017

A

8

67

35 4

2

1

D

C

B

A

678

3 245

1

Note : Design based on Calpe ERS - D2449-A0-110-00_0v3.pdf (Radar# 24696002)
System Block Diagram - T290 Power System Architecture . v9
Optimize componentS for individual projects based on EDP(A)

CRITICAL

OMIT_TABLE

CRITICAL

L7806

U7800

VDD_MAIN_E

116

PP3V3_G3H_SOCPMU

C7801

1

2

1

C7810

10UF 10UF

20%

2

6.3V
CER-X6S
0402

PLACE_NEAR=U7800.R1:5MM

PLACE_NEAR=U7800.L1:5MM PLACE_NEAR=U7800.G1:5MM

1

C7860

1UF 1UF

20%

2

4V
CERM-X6S
0201

PLACE_NEAR=U7800.A11:5MM

PLACE_NEAR=U7800.B18:5MM

1

C7865

1UF

20%

2

4V
CERM-X6S
0201

10UF

20%

6.3V
CER-X6S
0402

C7802

1

10UF

20%

2

6.3V
CER-X6S
0402

1

C7809

20%

2

6.3V
CER-X6S
0402 0402

1

C7891

1UF

20%

2

4V
CERM-X6S
0201

1

C7861

20%

2

4V
CERM-X6S
0201

PLACE_NEAR=U7800.K18:5MM

1

C7866

1UF

20%

2

4V
CERM-X6S
0201

C7803

1

10UF

20%

2

6.3V
CER-X6S
0402

1

C7808

10UF

20%

2

6.3V
CER-X6S

1

C7892

1UF

20%

2

4V
CERM-X6S
0201

PLACE_NEAR=U7800.C1:5MM

1

C7862

1UF

20%

2

4V
CERM-X6S
0201

PLACE_NEAR=U7800.P18:5MM

1

C7867

1UF

20%

2

4V
CERM-X6S
0201

C7804

1

10UF

20%

2

6.3V
CER-X6S
0402

1

C7807

10UF

20%

2

6.3V
CER-X6S
0402

1

C7893

1UF

20%

2

CERM-X6S
0201

PLACE_NEAR=U7800.A7:5MM

1

C7863

1UF

20%

2

4V
CERM-X6S
0201

PLACE_NEAR=U7800.F18:5MM

1

C7868

1UF

20%

2

4V
CERM-X6S
0201

C7805

1

10UF

20%

2

6.3V
CER-X6S
0402

1

C7806

10UF

20%

2

6.3V
CER-X6S
0402

1

C7894

1UF

20%

2

4V4V
CERM-X6S
0201

1

C7864

1UF

20%

2

4V
CERM-X6S
0201

1

C7869

1UF

20%

2

4V
CERM-X6S
0201

119 75

Resistor Divider from PBUS
VDD_HI < 3.1V

77

IN

PMU_VDD_HI

PP1V8_SLPS2R_PMUVDDGPIO

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

C7800

1

0.1UF

10%

6.3V

2

X6S
0201

NC
NC

Note : All Bucks are default Local Sense

Buck 0,2, and 8 have option for Remote Sense for Future Use.

NC

NC
NC

NC
NC

NC

SWITCH_NODE=TRUE

CRITICAL

L7821

116 122

PPVCCPRIMCORE_PRIM_REG

Vout = 1.05V

C7872

Iout_Max = 6A

1

F = 3MHz

2

C7899

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7898

1

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402

C7877

20UF

20%

2.5V
X6S-CERM
0402

C7882

20UF

20%

2.5V
X6S-CERM
0402

C7873

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7878

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7883

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7874

1

20UF

20%

2.5V

2

X6S-CERM X6S-CERM
0402

C7879

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7884

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7875

1

20UF

20%

2.5V

2

0402

C7880

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7885

1

20UF

2.5V

2

X6S-CERM
0402

C7876

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7881

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7886

1

20UF

20%20%

2.5V

2

X6S-CERM
0402

0806-COMBO

0.47UH-20%-4.8A-0.034OHM

CRITICAL

L7822

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

NOSTUFF

PLACE_NEAR=L7822.1:5MM

5%0201 1/20WMF

5%0201 MF 1/20W

21

21

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE

R7820

0

R7821

0

DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

PVCCPRIMCORE_SW0

121

PVCCPRIMCORE_SW1

121

PVCCPRIMCORE_FB

21

80

IN

PPVCCPRIM_FETIN

21

NC
NC
NC

NC

NC
NC
NC

NC

P5

D10

VDD_MAIN_N

P9

VDD_MAIN_S

K14

VDD_MAIN_W

K13

VDD_HI
VDD_GPIO

J11

C1
C2

VDD_BUCK0_01

C3
G1

G2

VDD_BUCK0_23

G3
R1

VDD_BUCK16

R2

L1
L2

VDD_BUCK2

L3

B16
B17

VDD_BUCK3

B18

A7

VDD_BUCK4

B7

A11

VDD_BUCK5

B11

F17

VDD_BUCK7

F18

K16
K17

VDD_BUCK8

K18
P16

P17

VDD_BUCK910

P18

T1

BUCK6_LX0

T2

R7

BUCK6_IN

T4

BUCK6_FB

E17

BUCK7_LX0

E18

G17

BUCK7_LX1

G18

F15

BUCK7_RTP

G15

BUCK7_RTN

L16
L17

BUCK8_LX0

L18

J16
J17

BUCK8_LX1

J18

L14

BUCK8_FB

P12

R12

T12

BUCK8_IN

U12

V12

N16
N17

BUCK9_LX0

N18

P14

BUCK9_RTP

N14

BUCK9_RTN

R16
R17

BUCK10_LX0

R18

R14

BUCK10_FB

CALPE-PMU

BGA

SYM 2 OF 4

338S00267-A0

121

BUCK0_LX0

121

BUCK0_LX1

121

BUCK0_LX2

121

BUCK0_LX3

BUCK0_FB

121

BUCK1_LX0

BUCK1_FB

121

BUCK2_LX0

121

BUCK2_LX1

BUCK2_FB

121

BUCK3_LX0

BUCK3_FB

BUCK3_IN

121

BUCK4_LX0

121

BUCK4_LX1

BUCK4_FB

BUCK4_IN

121

BUCK5_LX0

121

BUCK5_LX1

BUCK5_FB

BUCK3_SW1
BUCK3_SW2
BUCK3_SW3
BUCK3_SW4
BUCK3_SW5

BUCK4_SW1
BUCK6_SW1
BUCK8_SW1

BUCK8_SW2

B1

PVDDCPUAWAKE_SW0

SWITCH_NODE=TRUE

B2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

B3

DIDT=TRUE

D1

PVDDCPUAWAKE_SW1

SWITCH_NODE=TRUE

D2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

D3

DIDT=TRUE

0.22UH-20%-6.7A-0.023OHM

F1

PVDDCPUAWAKE_SW2

SWITCH_NODE=TRUE

F2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

F3

DIDT=TRUE

H1

PVDDCPUAWAKE_SW3

SWITCH_NODE=TRUE

H2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

H3

DIDT=TRUE

G5

PVDDCPUAWAKE_FB

80

IN

P1

PVDDCPUSRAMAWAKE_SW0

SWITCH_NODE=TRUE

P2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

R4

PVDDCPUSRAMAWAKE_FB

K1

P0V8SLPDDR_SW0

SWITCH_NODE=TRUE

K2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

K3

DIDT=TRUE

M1

P0V8SLPDDR_SW1

SWITCH_NODE=TRUE

M2

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

M3

DIDT=TRUE

L5

P0V8SLPDDR_FB

80

IN

C16

P1V8SLPS2R_SW0

SWITCH_NODE=TRUE

C17

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000

C18

DIDT=TRUE

D14

R9
T10
T9
U10
U9
V10
V9

A8
B8

A6
B6

D7

P7

A10
B10

A12
B12

D12

T8
T11
V11
V8
R8

P6
R6
P13

R13

P1V8SLPS2R_FB

PP1V8_SLPS2R

P1V1SLPS2R_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P1V1SLPS2R_SW1

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P0V9SLPDDR_SW0

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
SWITCH_NODE=TRUE
DIDT=TRUE

P0V9SLPDDR_SW1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

SWITCH_NODE=TRUE

DIDT=TRUE

P0V9SLPDDR_FB

NC
NC
NC

1UH-20%-3.8A-0.055OHM

21

2016-COMBO

CRITICAL

L7807

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

CRITICAL

L7808

21

PINA20121T-SM

CRITICAL

L7809

0.22UH-20%-6.7A-0.023OHM

21

PINA20121T-SM

R7806

0

21

1/20W0201 5% MF

L7810

1.0UH-20%-2.6A-0.095OHM

0805-COMBO

R7811

0

5% MF

0201

1/20W

1UH-20%-4.7A-0.04OHM

2520

21

L7811

CRITICAL

21

CRITICAL

CRITICAL

21

PLACE_NEAR=L7810.2:5MM

L7812

0.47UH-20%-4.8A-0.034OHM

21

0806

R7812

0

21

MF 0201

L7813

1UH-20%-3.8A-0.055OHM

21

2016-COMBO

R7813

0

5% 1/20WMF

PLACE_NEAR=L7813.2:5MM

5%

CRITICAL

21

0201

80

CRITICAL

L7814

1UH-20%-3.8A-0.055OHM

21

2016-COMBO

CRITICAL

L7815

0.47UH-20%-4.8A-0.034OHM

21

0806-COMBO

P1V1SLPS2R_FB

R7814

0

1/20W

0201

5%

MF

L7816

CRITICAL

21

2016-COMBO

1UH-20%-3.8A-0.055OHM

L7817

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7816

0

1/20W

0201

MF

CRITICAL

21

5%

21

PLACE_NEAR=L7816.2:5MM

C7821

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7812

1

20UF

20%

2.5V

2

X6S-CERM
0402

PLACE_NEAR=L7806.2:5MM

C7833

1

20UF

20%

2

2.5V
X6S-CERM
0402

PLACE_NEAR=L7812.2:5MM

1/20W

C7839

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7846

1

20UF

20%

2.5V

2

X6S-CERM
0402

21

PLACE_NEAR=L7815.2:5MM

C7852

1

2

20UF

20%

2.5V
X6S-CERM
0402

C7822

1

2

C7811

1

2

1

2

C7840

1

20UF

20%

2.5V

2

X6S-CERM
0402

PP1V8_AWAKE
PP1V8_SLPS2R_PMUVDDGPIO
PP1V8_S5
NC_PP1V8_S3
NC_PP1V8_S0

PP1V05_S3

C7823

1

20UF

20%

2.5V
X6S-CERM
0402

20UF

20%

2.5V
X6S-CERM
0402

C7829

1

10UF

20%
4V

2

X6S
0402-1

C7834

20UF

20%

2.5V
X6S-CERM
0402

C7847

1

20UF

20%

2.5V

2

X6S-CERM
0402 0402

C7853

1

20UF

20%

2

2.5V
X6S-CERM
0402

20UF

20%

2.5V

2

X6S-CERM
0402

C7826

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7830

1

10UF

20%

2

4V
X6S
0402-1

C7835

1

20UF

20%

2

2.5V
X6S-CERM
0402

C7841

1

20UF

20%

2.5V

2

X6S-CERM
0402 0402

C7848

1

20UF

20%

2.5V

2

X6S-CERM

C7854

1

20UF

20%

2

2.5V
X6S-CERM
0402

Supplied Current

80 131

119 75

80

80

80

0.3A

0.3A

1.0A

1.0A

0.5A

0.5A

0.3A

0.3A

115

0.3A

BOM_COST_GROUP=SOC

C7824

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7827

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7836

1

20UF

20%

2

2.5V
X6S-CERM
0402

C7842

1

20UF

20%

2.5V

2

X6S-CERM

C7849

1

2

1

2

C7825

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7828

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7843

1

2

20UF

20%

2.5V
X6S-CERM
0402

C7855

20UF

20%

2.5V
X6S-CERM
0402

PAGE TITLE

C7837

1

20UF

20%

2

2.5V
X6S-CERM
0402

20UF

20%

2.5V
X6S-CERM
0402

C7850

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402

C7856

20UF

20%

2.5V
X6S-CERM
0402

1

2

C7844

1

20UF

20%

2.5V

2

X6S-CERM
0402

PMIC BUCKS AND SWs

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PPVDDCPU_AWAKE

Vout = 0.625V - 1.06V
Iout_Max = 13.4A
F = 2MHz & 4MHz

C7813

1

20UF

20%

2.5V

2

X6S-CERM
0402

PPVDDCPUSRAM_AWAKE

Vout = 0.8V - 1.06V
Iout_Max = 1A
F = 3MHz

PP0V82_SLPDDR

C7838

20UF

20%

2.5V
X6S-CERM
0402

C7814

1

20UF

20%

2

2.5V
X6S-CERM
0402

Vout = 0.82V
Iout_Max = 6A
F = 3MHz

PP1V8_SLPS2R

C7845

1

20UF

20%

2.5V

2

X6S-CERM
0402

PP1V1_SLPS2R

C7851

1

20UF

20%

2.5V

2

X6S-CERM
0402

PP0V9_SLPDDR

C7818

1

20UF

20%

2

2.5V
X6S-CERM
0402

C7816

1

20UF

20%

2.5V

2

X6S-CERM
0402

C7819

1

20UF

20%

2

2.5V
X6S-CERM
0402

80 122

C7815

1

20UF

20%

2

2.5V
X6S-CERM
0402

Vout = 1.8V
Iout_Max = 2.5A
F = 3MHz

80 122

C7817

1

20UF

20%

2.5V

2

X6S-CERM
0402

Vout = 1.1V
Iout_Max = 4A

F = 3MHz

Vout = 0.9V
Iout_Max = 4A
F = 3MHz

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

78 OF 200

SHEET

75 OF 131

80 122

80

80 122
131

80
122

SYNC_DATE=06/06/2017SYNC_MASTER=SILU

SIZE

D

D

C

B

A

8

67

35 4

2

1

678

3 245

1

D

116

PP3V3_G3H_SOCPMU

80

PP1V1_SLPS2R

116

PP3V3_G3H_RTC_X
PP1V8_SLPS2R

80

1

C7903

0.1UF

10%

6.3V

2

X6S
0201

1

C7904

0.1UF

10%

6.3V

2

X6S
0201

C7909

1

0.1UF

10%

6.3V

2

X6S
0201

N11
N12

V3P3

LDO1_IN
LDO2_IN

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

SYM 1 OF 4

338S00267-A0

LDO_CORE

LDO0
LDO1LDO0_IN
LDO2
LDO3

HIO_SW_EN

HIO_SW

L8

V15
U15V14
U17U14
P8U16

N6

T13
U13
V13

C7910

0.1UF

LDO_CORE

6.3V

0201 10%

PMU_LDO3_OUT

D

21

X6S

PP0V8_SLPS2R
PP3V0_G3H_RTC

PP1V2_AWAKE

CPU_C10_GATE_L

PP1V05_S0SW

80

115

Max Current = 150mA

80

80

IN

131 79 78 15

Max Current = 10mA
Max Current = 300mA

Max Current = 3A

C

B

A

XW7903

SHORT-14L-0.1MM-SM

PLACE_NEAR=U7800.V5:3mm

21

For SI

XW7902

SHORT-14L-0.1MM-SM

PLACE_NEAR=U7800.E4:3mm

21

PP7902

P3MM

SM

1

PP

XW7901

SHORT-14L-0.1MM-SM

2 1

PP7901

P3MM

SM

PP

GND_PMU_XW2

VOLTAGE=0V

PLACE_NEAR=U7800.J15:3mm

1

GND_PMU_XW1

VOLTAGE=0V

GND_PMU_XW3

VOLTAGE=0V

A1
E1
E2

VSS_BUCK0

E3
A2
A3

J1
J2

VSS_BUCK02

J3

B5

VSS_BUCK4

A5

A13

VSS_BUCK5

B13

U1

VSS_BUCK6

U2
T16
T17

VSS_BUCK10

T18

N1

N2

VSS_BUCK21

N3

D16
D17

VSS_BUCK37

D18

B9

VSS_BUCK45

A9

H16
H17

VSS_BUCK78

H18
M16
M17

VSS_BUCK89

M18

V5

VSS_RTC

M9

AVSS_C

R11

AVSS_S

E11

PVSS_N

U11

PVSS_S

T5

PVSS_SE

V16

PVSS_SW

E4

VSSA_BUCK0

R5

VSSA_BUCK1_6/AVSS_SE

M4

VSSA_BUCK2

C13

VSSA_BUCK3

C10

VSSA_BUCK4_5

H15

VSSA_BUCK7

J15

VSSA_BUCK8/AVSS_W

M15

VSSA_BUCK9

T14

VSSA_BUCK10/AVSS_SW

SYM 4 OF 4

338S00267-A0

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

VSS

116

PP3V3_G3H_RTC_X

A4
A17
A18
B4
B15
C4
C5
C6
C7
C8
C9
C12
C15
D4
E15
E16
F4
F12
F16
G4
G12
G16
H4
H12
J4

GND_CALPE_AVSS

J12
K4
K15
L15
N4
N15
P3
P4
P11
P15
R3
R15
T3
T15
U18
U3
U4
U5
U8
V1
V2
V17
V18

R7900

PLACE_NEAR=U7800.J12:3mm

XW7900

SM

21

IN

1

C7920

1500PF

10%

10V

2

X7R
0201

0

21

PP3V3_G3H_PMU_VINRTC_R

5%

116

02011/20W MF

C7907

1

10UF

20%

6.3V

2

CER-X6S
0402

PP3V3_G3H_RTC_X

1

C7921

0.1UF

10%

6.3V

2

X6S
0201

P1V1SLPDDR_RAMP
P1V1_SLPDDR_SOCFET_EN

C7908

1

10UF

20%

6.3V

2

CER-X6S
0402

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

C7912

1

1UF

20%

6.3V

2

X6S-CERM
0201

1.1V SLPDDR SWITCH

1

VDD

U7901

SLG5AP1668V

CAP
ON S

TDFN8

GND

8

C7913

1

1UF

20%

6.3V

2

X6S-CERM
0201

37

D

52

LDO_RTC

T6

PP1V1_SLPS2R

PP1V1_SLPDDR

VIN_RTC

U6

VIN_RTC_E

H5

VIN_RTC_N

D11

VIN_RTC_S

P10

VIN_RTC_W

M14

VOUT_RTC

VPUMP

V3P3_SW1
V3P3_SW2

80

80

Part : SLG5AP1668V
R(ON) : 7.8 mohm (Typical) , 9.6 mohm (max)
Current: 5.3A Max

V7

T7
U7

R10

N13
N10

C7905

1

2

C7906

1

2.2UF

10%

10V

2

X6S-CERM
0402

PMU_VPUMP

2.2UF

10%

10V

X6S-CERM
0402

1

C7911

0.1UF

10%

6.3V

2

X6S
0201

C7914

1

2.2UF

10%

10V

2

X6S-CERM
0402

BOM_COST_GROUP=SOC

LDO_RTC

1

C7902

0.01UF

10%

10V

2

X5R-CERM
0201

PP3V3_AWAKE
PP3V3_S5

1

C7901

0.1UF

10%

6.3V

2

X6S
0201

PP3V3_G3H_SOCPMU

80

80

PAGE TITLE

PMIC LDOs

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

116

Max Current = 300mA
Max Current = 500mA

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

79 OF 200

SHEET

76 OF 131

C

B

SYNC_DATE=07/10/2017SYNC_MASTER=SILU

SIZE

A

D

8

67

35 4

2

1

D

C

119 39

126 119 38

119 39

131 119 38 29

12

OUT

OUT

OUT

PMU_CLK32K_SOC

PMU_CLK32K_PCH

1

1

R8011

33

5%
1/20W
MF

2

201

2

119 93 92 87 77 39 38

2.2K

SOC_FORCE_DFU

R8012

33

5%

1/20W

MF

201

R8010

Use SOC's Internal Pull Up

119 107 67 29

121 119 77

131 119 39 12

119 77 38 30

39
64

131

119 36

47

39

51

51

39

39

119 77 46

80 12

46

46

80

Caution : AMUX programmed with Gain 1 should not have inputs greater than 1.5V

IN
IN
IN
IN
IN

OUT

IN

OUT

SOC_WDOG
SOC_SOCHOT_L
UPC_PMU_RESET
SOC_PM_THRMTRIP_L
SOC_GPU_THRMTRIP

PMU_COLD_RESET_L

PM_SLP_S0_L
PMU_ACTIVE_READY
PMU_CLK32K_SOC_R

PMU_CLK32K_PCH_R

OUT
OUT

PMU_CLK32K_WLANBT
NC_PMU_CLK32K_GNSS_R

NC_PMU_CLK32K

OUT

21

OUT

IN

BI

IN
BI
OUT
OUT

PMU_SYS_ALIVE
PMU_FORCE_DFU

PMU_INT_L
I2C_PWR_SCL

I2C_PWR_SDA

SPMI_CLK
SPMI_DATA
ALL_SYS_PWRGD
PM_PWRBTN_L

678

5%2011/20W MF

PMU_CPU_ISENSE

59

PMU_CPU_VSENSE

59

PMU_GPU_CORE_ISENSE

59

PMU_GPU_CORE_VSENSE

59

PMU_GPU_FB_ISENSE

59

PMU_P1V8_WLAN_ISENSE

59

PMU_CPUDDR_ISENSE

59

PMU_DDR1V2_ISENSE

59

NC_PMU_AMUX_AY

80

F5

RESET_IN1

E5

RESET_IN2

K5

RESET_IN3

K6

RESET_IN4

N5

RESET_IN5

L13

RESET*

M12

SYS_SLEEP*

J5

ACTIVE_RDY

H6

CLKOUT0_32K

H7

CLKOUT1_32K

J7

CLKOUT2_32K

K7

CLKOUT3_32K

K8

CLKOUT4_32K

L11

SYS_ALIVE

D6

FORCE_DFU

L9

IRQ*

M11

SCL

L10

SDA

M8

SCLK

M7

SDATA

K11

SYS_ACTIVE

C11

SYS_BTN

A16

AMUX_A0

A15

AMUX_A1

A14

AMUX_A2

B14

AMUX_A3

C14

AMUX_A4

D15

AMUX_A5

E14

AMUX_A6

F14

AMUX_A7

J14

AMUX_AY

(IPD)

(IPD)

(IPD)

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

SYM 3 OF 4

338S00267-A0

(IPU)
(IPU)

IREF

VREF

VDROOP

VDROOP_DET

CHG_CBC_ON

NCHG_INT

CHG_POK
VPWR_EN

LDO1_POK

PFN

VIN_BBAT

BUTTON1
BUTTON2

L12

K12

L7

M5
D9

J6
L4

D5
M13
D8
V6

N7
M6

PMU_IREF

PMU_VREF

PMU_DROOP_L

PMU_PVDDMAIN_EN

NC

PMU_ONOFF_L
PMU_RSLOC_RST_L

1

1

C8001

0.1UF

10%

6.3V

2

X6S
0201

R8001

200K

1%
1/20W
MF
201

2

SOC_VDDCPU_SENSE
CHGR_CBC_ON

CHGR_INT_L
GND

PCH_RTC_RESET_L

GND

80

OUT

IN

IN
IN
IN

OUT

OUT

IN
IN

3 245

77 38

47 42

68

68 47

80

119 73

119 12

To be Grounded on Portables Only, RC on Coin Cell on Desktops

131 77 67 48

131 77 67 65

1

D

C

B

PP1V05_S3

PP3V3_G3H_RTC_X

PP1V8_AWAKE

PP1V8_S5

115

116

80

12 36 80

PMU_XTAL1_R

CRITICAL

Y8001

32.768KHZ-20PPM-12.5PF

1

C8002

22PF

5%
50V

2

C0G
0201

1.60X1.00-SM

21

R8013

0

21

5%

1

C8003

22PF

5%
50V

2

C0G
0201

02011/20W MF

NOSTUFF

PMU_PBUS_BMON_DIS_ISENSE

59

PMU_PBUS_MAIN_SSD0_ISENSE

59

PMU_PBUS_MAIN_SSD1_ISENSE

59

PMU_P3V3_G3W_SSD0_ISENSE

59

PMU_P3V3_G3W_SSD1_ISENSE

59

PMU_3V3_X_HI_ISENSE

59

PMU_3V3_T_HI_ISENSE

59

PMU_OTHER5V_HI_ISENSE

59

NC_PMU_AMUX_BY

80

1

R8018

1M

5%
1/20W
MF
201

2

118

PMU_XTAL1

118

PMU_XTAL2

77 6

1

C8004

0.1UF

10%

6.3V

2

X6S
0201

IN

CPU_CATERR_L

PMU_VDD_MAX

NC
NC

D13

E13
E12

F13
G13
G14

H14
H13

J13

N9

M10

V3
V4

L6

N8
E6

AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_B4
AMUX_B5
AMUX_B6
AMUX_B7
AMUX_BY

LS_BID1
LS_BID2

XTAL1
XTAL2

SYS_ERR*

VDD_MAX
VDD_OTP

(IPU)
(IPU)

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25

E9
E8
E7
F6
F7
F8
F9
F10
G10
G9
G8
G7
G6
H8
H9
J9
J8
K9
K10
J10
H10
H11
G11
F11
E10

P3V3MAIN_PGOOD
NC_P3V3G3W_EN
NC_P3V3G3W_PGOOD
P5VG3S_EN
P5VG3S_PGOOD
P3V3G3S_EN
P1V8G3S_EN
CPUVR_PGOOD
PVCCIO_EN
PVCCIO_PGOOD
PVDDQ_EN
PVDDQ_PGOOD
AUD_PWR_EN
WLAN_PWR_EN
BT_PWR_EN
SE_PWR_EN
SENSOR_PWR_EN
PVCCPLLOC_EN
NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD
NC_PEARL_P2V7NAND_EN
NC_NAND_DISCHARGE_HDD_PWR_EN
NC_NAND_RESET_L_SD_PWR_EN
NC_NAND_WP_L_ENET_PWR_EN
TBT_PWR_EN
P1V1_SLPDDR_SOCFET_EN

IN

OUT

IN

OUT

IN
OUT
OUT

IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT
OUT
OUT

73

80

80

78

61

49

79

79

80

80

80

80

80

79

119 73

119 73

119 79

131 119 79

119 80

119 78

131 74

120 74

37 36

37 36

B

131 119 76

A

PP1V8_SLPS2R

R8002
R8003

R8006

10K
10K

10K

R8005

R8015
R8014

10K
10K

R8017
R8007

10K

51

47K

21

21

NOSTUFF

80

VDD_HI Threshold Select

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PMU_COLD_RESET_L

5%2011/20W MF

PMU_SYS_ALIVE

5%2011/20W MF

21

21

21

21

21

21

PMU_DROOP_L

5%2011/20W MF

ALL_SYS_PWRGD

5%2011/20W MF

5%2011/20W MF

PMU_RSLOC_RST_L

5%2011/20W MF

5%201 1/20W MF

PMU_ACTIVE_READY

5%201 1/20W MF

PMU_ONOFF_L

CPU_CATERR_L

77 38

119 77 46

77 6

121 119 77 64 39

119 93 92 87 77 39 38

118S0481

118S00077

PPBUS_G3H

115

131 77 67 48

131 77 67 65

131 119 77 38 30

1
1118S00077 CRITICAL
1

RES,MF,649K,1%,1/20W,0201
RES,MF,1.15M,1%,1/16W,0201
RES,MF,1.15M,1%,1/16W,0201

R8050

1.15M

1%

1/20W

TK

0201

1

2

OMIT_TABLE

PMU_VDD_HI

OUT

75

NOSTUFF

C8051

220PF

10%
16V

CER-X7R

0201

1

2

R8051

357K

1%

1/20W

MF

201

1

2

R8050
R8050
R8050

PBUS
2S

12V

CRITICAL PBUS:2S

Rising Vth

6.059V

9.076V3S

9.076V

PBUS:3S

PBUS:12VCRITICAL

Falling Vth

5.636V

8.443V

8.443V

BOM_COST_GROUP=SOC

SYNC_MASTER=SILU SYNC_DATE=07/27/2017

PAGE TITLE

PMIC GPIOs & Control

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

80 OF 200

SHEET

77 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

C

8

9 8

D

0.95V VCCIO

PP5V_G3S

116

PVCCIO_BOOT_RC

IN
IN

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

XW8102

SM

2

1

1

R8150

75

1%
1/20W
MF
201

2

Vout = 0.5V * (1 + Ra / Rb)

PP5V_G3S_VCCIOVCC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

R8144

CPU_VCCIOSENSEPOS_RCPU_VCCIOSENSENEG_R

NO_XNET_CONNECTION=1

R8160

4.42K

1%

1/20W

MF

201

<Ra>

R8162

4.99K

1%

1/20W

MF

201

1

2

1

R8161

4.42K

0.1%
1/20W
MF
0201

2

<Ra>

1

2

1

R8180

4.99K

0.1%
1/20W
MF
0201

2

<Rb><Rb>

C8160

NO_XNET_CONNECTION=1

1

10PF

5%

50V

2

C0G

0201

1

C8161

10PF

5%
50V

2

C0G
0201

C8170

3300PF

5.0%
50V

CERM
0603

1

C8163

270PF

5%
50V

2

C0G
0402

C8162

2.2UF

20%
25V

X6S-CERM

0402

21

1

2

PVCCIOS0_EN_FILT_BUF

78

PVCCIOS0_FB

PVCCIOS0_VO

78

PVCCOIOS0_OCSET

78

77
78

OUT

PVCCIO_PGOOD
PVCCIOS0_RTN
PVCCIOS0_FSEL

1

R8164

100K

1%
1/20W
MF
201

2

PVCCIOS0_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=0V

3 12

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

XW8101

PLACE_NEAR=U8110.1:1mm

1

2.2

5%

1/20W

MF

201

2

13

14

PVCCVCC

1

2

U8110

ISL95870HRUZ

UTQFN

CRITICAL

PGNDGND

1

SM

21

BOOT

UGATE

PHASE
LGATE

16

C8143

10UF

20%
10V
X5R-CERM
0402-7

11
10
15

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

2.2

5%

1/20W

MF

201

1

2

R8145

PVCCIO_VBST

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

PVCCIO_DRVH

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

PVCCIO_LL

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE

PVCCIO_DRVL_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

PVCCIO_DRVL

1

C8144

0.1UF

20%

2

16V
X6S-CERM
0201

PVCCIO_DRVH_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

1

R8146

1

5%
1/16W
MF-LF
402

2

2

GATE_NODE=TRUE

Q8102

CSD58889Q3D

3

TG

4

TGR

5

BG

R8148

1

5%
1/16W
MF-LF

1

402

Q3D

9

VIN

VSW

PGND

CAPDERATE

1

C8153

33UF

20%
16V

2

TANT-POLY
CASE-B3

1

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE

6
7

PVCCIO_PHASEPVCCIOS0_SREF

8

1

R8116

2.2

5%
1/10W
MF-LF
603

2

DIDT=TRUEGATE_NODE=TRUE

0.56UH-20%-16A-0.0072OHM

NOSTUFF

PVCCIO_LL_SNUB

NOSTUFF

1

C8120

0.001UF

10%
50V

2

X7R-CERM
0402

CAPDERATE

1

C8152

33UF

20%
16V

2

TANT-POLY
CASE-B3

L8102

PILA052D-SM

PPBUS_HS_CPU

1

C8151

2.2UF

20%
25V

2

X6S-CERM
0402

21

PP0V95_S0_CPUVCCIO_REG_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.95V

1

C8150

2.2UF

20%
25V

2

X6S-CERM
0402

PVCCIOS0_CS_P

CRITICAL

NO_XNET_CONNECTION=1

PVCCOIOS0_OCSET

78

NO_XNET_CONNECTION=1

X5R-X7R-CERM

NO_XNET_CONNECTION=1

115

R8142

3.83K

1%

1/20W

MF

201

C8142

470PF

10%
16V

0201

CRITICAL

R8102

0.002

1%
1W

CYN

0612

1

2

1

2

21
43

PVCCIOS0_CS_N

CRITICAL

C8174

10UF

20%

4V

X6S

0402

R8171

10

1/20W

1%

201MF

R8170

10

1% 1/20W

201

MF

Vout = 0.95V
IccMax = A
F = 600kHz

PPVCCIO_S0_CPU

CRITICAL

20%

4V

X6S

1

2

1

C8175

10UF

2

0402

21

ISNS_CPUVCCIO_POS

21

ISNS_CPUVCCIO_NEG

CRITICAL

1

C8164

220UF

3 2

20%
2V
ELEC
SM-COMBO

OUT

OUT

CRITICAL

1

C8165

220UF

3 2

121 56

121 56

20%
2V
ELEC
SM-COMBO

115 122

C

B

A

PP1V8_S5

R8152

131 79 76 15

119 77

PP3V3_S5

80

IN

IN

69 74 80

100K

21

CPU_C10_GATE_L

PVCCIO_EN

1

C8176

0.1UF

10%

6.3V

2

CERM-X5R
0201

6

MF1/20W5% 201

5

132

PVCCIO_PGOOD

VCCIO ENABLE LOGIC

U8111

74AUP1T97GM

SOT886

4

PVCCIOS0_EN

100K

5%

1/20W

MF

201

1

2

R8159

NOSTUFF

R8158

3.92K

2 1

1/20W

1%MF201

78 77

1

C8191

0.1UF

10%

6.3V

2

CERM-X5R
0201

PVCCIOS0_EN_R

1

C8190

330PF

5%
25V

2

C0G
0201

0201

1

R8190

0

2 1

MF 5%

U8112

74AUP2G17GM/S500-COMBO-1

52

SOT886

6

PVCCIOS0_EN_FILT

C8192

100PF

21

5%
25V
C0G

0201

NOSTUFF

1/20W

R8143

3.83K

PVCCIOS0_VO

78

2 1

1%

1/20W

MF

201

B

U8112

52

74AUP2G17GM/S500-COMBO-1

SOT886

3

4

R8191

47K

5%

1/20W

MF

201

PVCCIOS0_EN_FILT_BUF

1

2

78

PAGE TITLE

A

SYNC_DATE=05/10/2017SYNC_MASTER=SILU

VR VCCIO

SIZE

D

BOM_COST_GROUP=PLATFORM POWER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

81 OF 200

SHEET

78 OF 131

8

67

35 4

2

1

678

3 245

1

D

119 79 77

C8215

4700PF

10%
10V
X7R
201

3.3V G3 Standby Switch X

PP3V3_G3H_RTC_X

116

1

C8216

1

VDD

U8215

SLG5AP1445V

P3V3G3SX_SS
P3V3G3S_EN

IN

47K

5%

1/20W

MF

201

1

2

1

2

R8200

CAP
ON S

TDFN8

GND

8

Part
R(on)

@ 3.6V
Current

37

D

52

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max
4A Max

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_G3H_RTC_X
PP3V3_G3S_X

116

116

119 79 77

C8210

4700PF

10%
10V
X7R
201

1

2

3.3V G3 Standby Switch T

PP3V3_G3H_T

116

1

VDD

U8210

SLG5AP1445V

P3V3G3ST_SS
P3V3G3S_EN

IN

R8220

NOSTUFF

47K

5%

1/20W

MF

201

CAP
ON S

1

TDFN8

GND

8

Part

2

R(on)
@ 3.6V

Current

37

D

52

1

C8211

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_G3H_T
PP3V3_G3S_T

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max
4A Max

116

116

C8220

4700PF

10%
10V
X7R
201

1

2

1.8V G3 Standby Switch

PP3V3_G3H_T

116

1

VDD

U8220

SLG5AP1445V

P1V8G3S_SS
P1V8G3S_EN

IN

NOSTUFF

R8221

47K

5%

1/20W

MF

201

CAP
ON S

1

2

TDFN8

GND

8

D

Part
R(on) 7.8 mOhm Typ

@ 3.6V
Current

1

C8221

0.1UF

10%
10V

2

X5R-CERM
0201

37
52

PP1V8_SLPS2R
PP1V8_G3S

80

116

D

SLG5AP1445V

8.5 mOhm Max
4A Max

C

77

131 78 76 15

1.1V S0SW VCCPLL_OC Switch

PP3V3_S5

80

10%

6.3V
0201

1

1

2

VDD

U8240

SLG5AP1635V

CAP
ON

STDFN

CRITICAL

GND

8

Part
Type
R(on)

37

D

52

S

C8240

0.1UF

PP1V8_S5

80

CERM-X5R

U8245

74AUP1G08GF

6

SOT891

VCC

IN

IN

PVCCPLLOC_EN
CPU_C10_GATE_L

C8245

0.1UF

10%

6.3V

CERM-X5R

0201

NC

1

2

2

A Y

AND

1

B

5

NC

GND

3

4

P1V1S0SW_FET_EN

1

R8245

100K

5%
1/20W
MF
201

2

C8242

100PF

5%
25V
C0G

0201

P1V1S0SW_RAMP

1

2

@ 3.3V 31 mOhm Max
Current

PP1V2_S3

1

C8241

1.0UF

20%

6.3V

2

X5R
0201-1

SLG5AP1635V
Load Switch

27.5 mOhm Typ

2.5A Max

115

C

PP1V2_S0SW

115

EDP: 130mA

B

A

29 27

79 77

107 105

79 77

PP3V3_G3H_RTC_X

116

PP3V3_TBT_X_SX

TBT_PWR_EN

PP3V3_G3H_T

116

BYPASS=U8291.5::5MM

PP3V3_TBT_T_SX

TBT_PWR_EN

BYPASS=U8292.5::5MM

C8286

1.0UF

0201-1

R8298

33

1/20W

1%

C8288

1.0UF

20%

6.3V
X5R

0201-1

21

P3V3_TBT_X_SX_R

201

MF

1

2

R8297

33

21

P3V3_TBT_T_SX_R

201

1%

1/20W

MF

1

20%

6.3V

2

X5R

U8292

74AUP1T97GM

R8294

NOSTUFF

1

47K

5%

1/20W

MF

201

2

NO STUFF

U8291

74AUP1T97GM

R8292

47K

5%

1/20W

MF

201

NO STUFF

R8295

1/20W

5%

6

1

2

R8296

5%

1/20W

0

6

0

5

SOT886

132

21

MF

5

SOT886

132

21

MF

0201

0201

4

TBT_PWR_EN_U8297

100K

5%

1/20W

MF

201

1

2

R8293

3.3V S0SW TBT T Switch

4

TBT_PWR_EN_U8295

100K

5%

1/20W

MF

201

1

2

R8291

3.3V S0SW TBT X Switch

C8297

1.0UF

20%

6.3V
X5R

0201-1

P3V3TBTX_RAMP

10%
10V
X7R
201

1

2

C8298

4700PF

C8295

1.0UF

0201-1

P3V3TBTT_RAMP

10%
10V
X7R
201

1

2

C8296

4700PF

20%

6.3V
X5R

1

2

SLG5AP1445V

CAP
ON S

1

2

SLG5AP1445V

CAP
ON S

1

VDD

U8297

TDFN8

CRITICAL

GND

8

1

VDD

U8295

TDFN8

CRITICAL

GND

8

37

D

52

Part SLG5AP1445V
Type

@ 4A
Current

37

D

52

Part
Type
R(on)

@ 4A
Current

PP3V3_S0SW_TBT_X

Load Switch

7.8 mOhm TypR(on)
TBD mOhm Max

4A Max

PP3V3_S0SW_TBT_T

SLG5AP1445V
Load Switch

7.8 mOhm Typ
TBD mOhm Max

4A Max

116

116

VCCPLL_OC has turn-on requirement of
11uS min and 240uS max
from EN to 1.1V

3.3V Sensor Switch

PP3V3_G3H_T

116

77

IN

BOM_COST_GROUP=PLATFORM POWER

SENSOR_PWR_EN

C8250

1.0UF

20%

6.3V
X5R

0201-1

SYNC_MASTER=SILU

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

1

2

LOADISNS

LOADISNS

VIN

1

ON

U8250

SLG5AP1569V

STDFN

CRITICAL

VOUT

GND

4

Part

Type

R(on) 34 mOhm Typ
@ 3.6V

Current

Power FETs

Apple Inc.

PP3V3_G3SSW_SNS

3

SLGAP1569V

Load Switch

46 mOhm Max

1A Max

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

82 OF 200

SHEET

79 OF 131

116

SIZE

D

SYNC_DATE=06/27/2017

B

A

8

67

35 4

2

1

678

3 245

1

D

C

B

PPVDDCPU_AWAKE

75 122

PMIC Buck1 - SoC VDD_CPU_SRAM

PPVDDCPUSRAM_AWAKE

75 122

PMIC Buck2 - SoC VDD_SOC

PP0V82_SLPDDR

75

PMIC BUCK3 - SoC AOP/SMC/VDD1

PP1V8_SLPS2R

75 122 131

PMIC BUCK3 SW 1

PP1V8_AWAKE

75 131

PMIC BUCK3 SW 3

PPVDDCPU_AWAKE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.06V
MAKE_BASE=TRUE

PPVDDCPU_AWAKE

PPVDDCPUSRAM_AWAKE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.06V
MAKE_BASE=TRUE

PPVDDCPUSRAM_AWAKE

PP0V82_SLPDDR

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.82V
MAKE_BASE=TRUE

PP0V82_SLPDDR

PP1V8_SLPS2R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

PP1V8_AWAKE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE

PMIC Buck4 - SDRAM VDD2PMIC Buck0 - SoC VDD_CPU

PP1V1_SLPS2R

119 119

42 80

119

42

75 122

PP1V1_SLPS2R

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPS2R
PP1V1_SLPS2R
PP1V1_SLPS2R
PP1V1_SLPS2R

76

76

43

44

Buck 4 Ext. SW U7901 - VDDIO_DDR & PLL

119

42 80

119

PP1V1_SLPDDR

76

PP1V1_SLPDDR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR

119

38

43

43

44

PMIC Buck5 - VDD_FIXED

75

79

76

46

77

64

46

38 47

44

44

44

44

68

51

51

51

47

29 107

67

126 131

107

119

77

46

44

44

44

44

44

41 46 47

46

66

126

PP0V9_SLPDDR

75 122

PMIC LDO0 - VDD_LOW

PP0V8_SLPS2R

76

PMIC LDO2 - PCIE_REFBUF/PLL

PP1V2_AWAKE

76

PMIC V3P3 SW 1 - USB

PP3V3_AWAKE

76

PP0V9_SLPDDR

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V
MAKE_BASE=TRUE

PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR

PP0V8_SLPS2R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.8V
MAKE_BASE=TRUE

PP0V8_SLPS2R

PP1V2_AWAKE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.2V
MAKE_BASE=TRUE

PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE

PP3V3_AWAKE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_AWAKE

119

43

43

43

43

43

119

43

119

44

44

44

44

44

NC Aliases

77

77

77

77

77

77

77

NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD
NC_PEARL_P2V7NAND_EN
NC_NAND_DISCHARGE_HDD_PWR_EN
NC_NAND_RESET_L_SD_PWR_EN
NC_NAND_WP_L_ENET_PWR_EN
NC_P3V3G3W_PGOOD
NC_P3V3G3W_EN

Alternate Feedback Sesne

75

75

75

OUT

OUT

OUT

PVDDCPUAWAKE_FB
Buck0 - Remote

P0V8SLPDDR_FB
Buck2 - Remote

PVCCPRIMCORE_FB PVCCPRIMCORE_FB_R
Buck8 - Remote

NOSTUFF

R8320

0

21

PVDDCPUAWAKE_FB_R

5%
1/16W
MF-LF

PLACE_NEAR=R7806.1:5MM

402

NOSTUFF

R8321

0

21

P0V8SLPDDR_FB_R

5%
1/16W
MF-LF

PLACE_NEAR=R7812.1:5MM

402

R8322

0

21

5%
1/16W
MF-LF

PLACE_NEAR=R7820.2:5MM

402

MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD
NC_PEARL_P2V7NAND_EN
NC_NAND_DISCHARGE_HDD_PWR_EN
NC_NAND_RESET_L_SD_PWR_EN
NC_NAND_WP_L_ENET_PWR_EN
NC_P3V3G3W_PGOOD
NC_P3V3G3W_EN

XW8320

SM

21

PPVDDCPU_AWAKE

PLACE_NEAR=U3900.AA12:4MM

XW8321

SM

21

PP0V82_SLPDDR

PLACE_NEAR=U3900.AA20:6MM

XW8322

SM

21

PP1V05_PRIM

PLACE_NEAR=U1200.AB12:4MM

D

42 80

42 80

C

16 17 115

B

A

PP1V8_S5

75

75

75

PMIC BUCK3 SW 4/5

NC_PP1V8_S3
NC_PP1V8_S0

PP1V8_S5

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

PP1V8_S5
PP1V8_S5

PP1V8_S5

PP1V8_S5

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

NC_PP1V8_S3

MAKE_BASE=TRUE

NC_PP1V8_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

119

46

16 17

39

12 16

12 13 15 16 19 20 52

15

126

17

12 36 77

51

51

51

46

94

69 74 78

93

79

74

16

57

57

57

46

18

PMIC V3P3 SW 2 (Internal) -

PP3V3_S5

76

PMIC LDO 1 - PCH VCCRTC

PP3V0_G3H_RTC

76

PP3V3_S5

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

PP3V0_G3H_RTC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.0V
MAKE_BASE=TRUE

PP3V0_G3H_RTC

119

12 16 17

46

78

15 16 19

14 16

15 16

18

20

12 16 17

79

12

93 124

126 131

16

119

12 16 17

119 18

119 77

46 8

77

77

NC_CHGR_AUX_OK
PM_PWRBTN_L
CPUVR_PGOOD
CPU_VCCST_PWRGD

NC_PMU_CLK32K
NC_PMU_AMUX_BY
NC_PMU_AMUX_AY

GND
GND

NO_TEST=1

MAKE_BASE
MAKE_BASE
MAKE_BASE
MAKE_BASE

NO_TEST=1

MAKE_BASE

NO_TEST=1

MAKE_BASE

NO_TEST=1

MAKE_BASE

MAKE_BASE
MAKE_BASE

NC_CHGR_AUX_OK
PM_PWRBTN_L
CPUVR_PGOOD

CPU_VCCST_PWRGD

NC_PMU_CLK32K
NC_PMU_AMUX_BY
NC_PMU_AMUX_AY

68

12 77

69

69

77

77

77

PAGE TITLE

SOC/PMIC Aliases

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

83 OF 200

SHEET

80 OF 131

SYNC_DATE=08/09/2017SYNC_MASTER=SILU

SIZE

D

A

8

67

35 4

2

1

Page Notes

678

PBUS LINE WIDTHS

3 245

1

D

C

B

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_G3S_BKLT (5V BACKLIGHT DRIVER INPUT)

PPBUS_G3H

115

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

740S0159

CRITICAL

F8400

3AMP-32V

81

0603-COMBO

121 53

121 53

CRITICAL

SENSOR ON PAGE 54 USES R8400 TO MEASURE THE

POWER GOING TO LCD BACKLIGHT

R8400

0.025

1%
1W
MF

IN

0612-1

21
43

EDP_BKLT_EN

PPVIN_S0SW_LCDBKLT_FET

21

VOLTAGE=12.6V VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

ISNS_LCDBKLT_P

OUT

ISNS_LCDBKLT_N

OUT

107S00034

93

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

PPVIN_S0SW_LCDBKLT_R

1

2

C8400

1000PF

10%
16V
X7R-1
0201

GND_BKLT_SGND

81

1

R8401

80.6K

1%
1/16W
MF-LF
402

2

1

R8402

63.4K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U8400.5:5MM
PLACE_NEAR=U8400.5:5MM

81

R8442

0

5%

1/20W

MF

0201

CRITICAL

Q8400

FDC638APZ_SBMS001

SSOT6-HF

4

3

LCDBKLT_EN_L

PP5V_G3S

81 116

C8440

GND_BKLT_SGND

1

R8440

1M

5%
1/20W

2

21

MF
201

1

2

BKLT_SD LCDBKLT_SW

BKLT_SENSE_OUT

BKLT_EN_R

NO STUFF

C8442

33PF

5%
25V
NP0-C0G
0201

BKLT_PWM_KEYB

1

R8447

10K

5%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

6
5
2
1

R8444

1/16W
MF-LF

402

1UF

10%
10V
X5R

402-1

NOSTUFF

1

C8401

2

1

0

5%

2

81

1

2

0.001UF

10%
50V
CERM
402

1

R8445

0

5%
1/16W
MF-LF
402

2

PP5V_G3S_BKLT_A

81

PP5V_G3S_BKLT_D

C8441

1

1UF

10%
10V

2

X5R
402-1

LP8548B1SQ_-03

11

SD

9

VSENSE_N

10

VSENSE_P
SENSE_OUT

19
17

EN
PWM_KEYB

12

SCL

15

SDA

16

GND_SW
24

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=12.6V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

5

18

Ben IC - V3

VDDA

VDDD

U8400

QFN

2

SW

81

SW

1
21

FB

ISET_KEYB

KEYB1

(IPU)

(IPU)

KEYB2

CRITICAL

GND_SW
23

XW8400

GNDA

GNDD

GND_SW2

3

7

22

SM

21

81

GD

SW2

FB2

THRM

PAD

25

LCDBKLT_FB
LCDBKLT_FET_DRV

4
20

NC

13

NC

14

NC

6

NC

8

NC

PLACE_NEAR=L8410.1:5MM
PLACE_NEAR=L8410.1:5MM
PLACE_NEAR=L8410.1:5MM

CRITICAL

C8410

1

4.7UF

10%
25V

2

X6S-CERM
0603

PLACEMENT_NOTE:

SANDWICH C8210 AND C8211

SANDWICH C8410 AND C8411

DIDT=TRUE
SWITCH_NODE=TRUE

VOLTAGE=59V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.3000

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

C8411

1

4.7UF

10%
25V

2

X6S-CERM
0603

LCDBKLT_FET_DRV_R

81

PLACE_NEAR=Q8401.5:3MM

CRITICAL

L8410

15UH-20%-1.9A-0.24OHM

21

PIME062D-SM

152S00253

C8412

1

0.1UF

10%
25V

2

X5R
402

1

R8433

10

5%
1/16W
MF-LF
402

2

81

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=59V

MAKE_BASE=TRUE

PPVIN_SW_LCDBKLT_SW

4

371S00077

D8410

SOD123-COMBO

KA

PMEG10020ELR-DFLS2100

CRITICAL

5

376S0678

CRITICAL

Q8401

SI7812DN

PWRPK-1212-8

321

PLACE_NEAR=U8400.1:5MM

PLACE_NEAR=D8410.K:4MM

XW8410

2

SM

1

1

R8431

LCDBKLT_TB_XWR

28.7K

1%
1/16W
MF-LF
402

2

1

R8432

150K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM

CRITICAL

C8460

1

2.2UF

10%

2

100V
X5R
1206

PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM

CRITICAL

1

C8465

2.2UF

10%

2

100V
X5R
1206

PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM
PLACE_NEAR=D8410.K:8MM

CRITICAL

1

C8470

2.2UF

10%

2

100V
X5R
1206

R8431:

28.7K FOR J80 DISPLAY.

NOSTUFF

C8430

1

100PF

5%

2

100V
C0G-CERM
0603

PP5V_G3S_BKLT_D

81

PP5V_G3S_BKLT_A

81

BKLT_EN_R

81

122 120 82 81

PPVOUT_S0_LCDBKLT
LCDBKLT_FB

81

LCDBKLT_FET_DRV_R

81

LCDBKLT_SW

81

BKLT_SD

81

LCDBKLT_EN_L

81

PPVIN_S0SW_LCDBKLT

81

PPVIN_S0SW_LCDBKLT_FET

81

PPVIN_SW_LCDBKLT_SW

81

CRITICAL

C8461

1

2.2UF

10%

2

100V
X5R
1206

CRITICAL

1

C8466

2.2UF

10%

2

100V
X5R
1206

CRITICAL

1

C8471

2.2UF

10%

2

100V
X5R
1206

VOUT = 52V TYP, 59V MAX
IOUT = 0.135A TYP, 0.15A MAX
FS = 625KHZ TYP (+/- 7%)

CRITICAL

C8462

1

2.2UF

10%

2

100V
X5R
1206

CRITICAL

1

C8467

2.2UF

10%

2

100V
X5R
1206

CRITICAL

1

C8472

2.2UF

10%

2

100V
X5R
1206

TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5

TP-P5
TP-P5
TP-P5

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=59V

MAKE_BASE=TRUE

CRITICAL

C8463

1

2.2UF

10%

2

100V
X5R
1206

1

2

CRITICAL

1

C8468

2.2UF

10%

2

100V
X5R
1206

1

2

CRITICAL

1

C8473

2.2UF

10%

2

100V
X5R
1206

1

TP

TPA8400

1

TP

TPA8401

1

TP

TPA8402

1

TP

TPA8403

1

TP

TPA8404

1

TP

TPA8405

1

TP

TPA8406

1

TP

TPA8407

1

TP

TPA8408

1

TP

TPA8410

1

TP

TPA8411

1

TP

TPA8412

CRITICAL

C8464

2.2UF

10%
100V
X5R
1206

CRITICAL

C8469

2.2UF

10%
100V
X5R
1206

122 120 82 81

D

C

B

PP5V_G3S

81 116

120 82

120 82

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

IN

BI

I2C_BKLT_SCL

I2C_BKLT_SDA

1

R8452

5%
1/20W
MF
201

2

1

R8453

1.8K1.8K

5%
1/20W
MF
201

2

PLACE_NEAR=U8400.16:10MM

PLACE_NEAR=U8400.15:10MM

R8450

0

21

5%

R8451

0

5%

1/20W

MF

0201

1/20W

MF

0201

21

BKLT_SCL

BKLT_SDA

GND_BKLT_SGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=0V

81

LCD BKLT LINE WIDTHS

A

8

SYNC_MASTER=RAYMOND SYNC_DATE=08/07/2017

PAGE TITLE

A

LCD Backlight Driver

122 120 82 81

IN

67

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=59V

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DISPLAY

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

84 OF 200

SHEET

81 OF 131

1

678

3 245

1

D

C

B

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

PP5V_G3S

116

1

VDD

U8500

TDFN

GND

8

51

D8518

K A

DSF01S30SCAP

BYPASS=U8510::2mm

1

C8570

0.1UF

10%
10V

2

X5R-CERM
0201

3

912
6
10

5
11

PP3V3_G3S_X

D

SC2

EDP_PANEL_PWR_BUF_EN

37
52

1

C8511

0.1UF

10%
10V

2

0201

NC
NC
NC

NC
NC

R8544

0

21

5%

1/20W

MF

0201

1

C8512

10UF

20%
10V

2

X5R-CERMX5R-CERM
0402-7

LCD_PWR_SLEW_3V3

1

C8516

0.47UF

10%

6.3V

2

0201

120 82

HOST SIDE

NOSTUFF

1

R8505

100K

5%
1/20W
MF
201

2

SEP_CAM_DISABLE_DFF_R_L

PP5V_S0SW_LCD

82 116

1

2

PP3V3_G3S_X

82 116

47 40

47 40

47 40

47 40

52

52

MIPI_FTCAM_CLK_P

MIPI_FTCAM_CLK_N

MIPI_FTCAM_DATA_P<0>

MIPI_FTCAM_DATA_N<0>

I2C_FTCAM_SDA

I2C_FTCAM_SCL

S OUTPUT
L Camera Disable

H Camera Enable

R8517

330

5% 201
1/20W

PP3V3_G3H_RTC_X

82 116

93

IN

EDP_PANEL_PWR_EN

MF

R8515

150K

5%

1/20W

MF

201

21

PANEL_P5V_EN_D

1

2

SMCRST_TIEOFF

21

PANEL_P5V_EN

DSF01S30SCAP

R8570

100K

5%
1/20W
MF
201

LCD_PWR_SLEW

1

D8517

SC2

KA

C8515

0.1UF

10%
10V

2

X5R-CERM
0201

R8518

330

5% 201
1/20W

MF

EDP_PANEL_PWR_DLY_EN

1

R8571

100K

5%
1/20W
MF
201

2

PM_SLP_TIEOFF

2

EDP_PANEL_PWR_EN

4 8

PM_SLP_S3_L
SMC_RESET_INPUT_L

64

IN

21

PANEL_P3V3_EN_D

SLG4AP4998

SEP_CAM_DISABLE_DFF_L

CRITICAL

CAP
ON S

1

C8509

4700PF

10%
10V

2

X7R
201

R8516

200K

1/20W

1

VDD

STQFN

GND

7

21

1%
MF

201

U8510

PANEL_FET_EN_DLY

PANEL_PWR_EN_CONN

SMC_RESET_OUTPUT_L

X604_DISP_PWR_EN

X604_DISP_SMC_RST_L

SLG5AP1443V

PANEL_P3V3_EN

NC0
NC1

82 116

VOLTAGE=5V

PP3V3_G3H_RTC_X

CRITICAL

U8501

SLG5AP1443V

CAP
ON S

C8513

4700PF

10%
10VCERM-X5R
X7R
201

1

VDD

TDFN

GND

8

BYPASS=U8502::2mm

1

C8502

0.1UF

10%
10V

2

X5R-CERM
0201

D

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

MIPIC FILTERING

L8502

3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM

SYM_VER-1

MIPI_FTCAM_DATA_ISOL_P<0>

82

MIPI_FTCAM_DATA_ISOL_N<0>

82

120 82

MIPI_FTCAM_CLK_ISOL_P

82

MIPI_FTCAM_CLK_ISOL_N

82

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

1

L8503

3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM

SYM_VER-1

1

L8504

FERR-120-OHM-1.5A

21

SENSOR:DEV

116

PP5V_G3S

0402A

R8520

0.01

1%

37

VOLTAGE=3.3V

52

1

2

PP3V3_S0SW_LCD_R

C8510

1.0UF

X5R

CRITICAL

6.3V20%

0201-1

10

VCC

121 55

ISNS_LCDPANEL_P

55
121

ISNS_LCDPANEL_N

1

R8551

100K

5%
1/20W
MF
201

2

1/3W

MF

0306

U8502

11

NX3DV642GU

QFN-COMBO

CLK1+

CLK+

1

CLK2+

CLK1-

CLK-

2

CLK2-

1D1+

1D+

3

1D2+

1D1-

1D-

4

1D2-

2D1+

2D+

5

2D2+

2D1-

2D-

6

2D2-

8

OE*

CONTROL

S

LOGIC

GND

9

Alternate: OnSemi FSA642 (353S01346)

NC
NC

17

22

GND_VOID=TRUE

16

23

GND_VOID=TRUE

15

20

GND_VOID=TRUE

14

21

GND_VOID=TRUE

13

19

12

18

7
24

Resistor needed?

MIPI_FTCAM_CLK_ISOL_P

MIPI_FTCAM_CLK_ISOL_N

MIPI_FTCAM_DATA_ISOL_P<0>

MIPI_FTCAM_DATA_ISOL_N<0>

NC

120 82

NC

120 82

I2C_CAM_ISOL_SDA

I2C_CAM_ISOL_SCL

NC
NC

NO_XNET_CONNECTION=1

21
43

PP3V3_S0SW_LCD

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V

DP_INT_HPD

120 93 82

82

82

82

82

120 82 51

PP1V8_G3S

52 116

120 82 51

120 82

122 120 82 81

120 93 82

120 93 82

120 93

120 93

120 93

120 93

120 93

120 93

120 93

120 93

PP3V3_S0SW_LCD

BKLT_PWM_MLB2TCON

PPVOUT_S0_LCDBKLT

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

120 82

120 82

120 82

120 82

120 82

1

2

EDP_INT_AUX_N
EDP_INT_AUX_P

EDP_INT_ML_N<0>
EDP_INT_ML_P<0>

EDP_INT_ML_N<1>
EDP_INT_ML_P<1>

EDP_INT_ML_N<2>
EDP_INT_ML_P<2>

EDP_INT_ML_N<3>
EDP_INT_ML_P<3>

MIPI_FTCAM_DATA_CONN_N<0>
MIPI_FTCAM_DATA_CONN_P<0>

MIPI_FTCAM_CLK_CONN_N
MIPI_FTCAM_CLK_CONN_P

PP5V_S0SW_LCD

R8510

100K

5%
1/20W
MF
201

PLACE_NEAR=J8500.33:5mm

GND_VOID=TRUE

4

MIPI_FTCAM_DATA_CONN_P<0>

GND_VOID=TRUE

32

MIPI_FTCAM_DATA_CONN_N<0>

PLACE_NEAR=J8500.39:5mm

GND_VOID=TRUE

4

MIPI_FTCAM_CLK_CONN_P

GND_VOID=TRUE

32

MIPI_FTCAM_CLK_CONN_N

PP5V_S0_ALSCAM_F

VOLTAGE=5V

1

C8504

0.1UF

10%
10V

2

X5R-CERM
0201

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

1

R8511

100K

5%
1/20W
MF
201

2

NOSTUFF

1

R8508

10K

5%
1/20W
MF
201

2

1

R8507

10K

5%
1/20W
MF
201

2

20759-042E-02

PPVOUT_S0_LCDBKLT

120 82

10%

100V
0603

1

2

PP3V3_G3H_RTC_X

82 116

C8500

82
120

82
120

1000PF

X7R-CERM

LCD Panel HPD & AUX strapping

120 82

NO_XNET_CONNECTION=1

NOSTUFF

120 82

120 93 82

120 93 82

EDP_INT_AUX_N

EDP_INT_AUX_P

NO_XNET_CONNECTION=1

NOSTUFF

J8500

F-ST-SM

PWR

SIGNAL

PWR

GND

4443

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

4847
5049
5251
5453
5655
5857
6059
6261
6463
6665
6867

PP3V3_S0SW_LCD

EDP_PANEL_PWR_BUF_EN
DP_INT_HPD
LCD_FSS
TP_LCD_IRQ_L

NC

TCON PWM is NCed

BKLT_PWM_MLB2TCON

I2C_BKLT_SDA
I2C_BKLT_SCL
I2C_TCON_SDA
I2C_TCON_SCL

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

I2C_ALS_SDA

I2C_ALS_SCL
I2C_CAM_ISOL_SCL
I2C_CAM_ISOL_SDA

PP5V_S0_ALSCAM_F

122 120 82 81

1

R8503

1M

5%
1/20W
MF
201

2

1

R8502

1M

5%
1/20W
MF
201

2

120 82 51

120 82

120 93 82

120 93

120

120 82

BI

120

BI

120

BI
BI

52

BI

52

BI

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

120 82

120 82

120 82

D

C

82 81

82 81

120 51

120 51

B

A

8

I2C pulls needed on both sides???

PP3V3_S0SW_LCD
PP5V_S0SW_LCD
PP5V_S0_ALSCAM_F
I2C_BKLT_SDA
I2C_BKLT_SCL

NOSTUFF

1

C8554

12PF

5%
25V

2

NP0-C0G
0201

1

C8550

12PF

5%
25V

2

NP0-C0G
0201

1

C8551

12PF

5%
25V

2

NP0-C0G
0201

1

C8552

12PF

5%
25V

2

NP0-C0G
0201

NOSTUFF

1

C8553

12PF

5%
25V

2

NP0-C0G
0201

BOM_COST_GROUP=DISPLAY

67

35 4

120 82 51

120 82

120 82

120 82 81

120 82 81

PAGE TITLE

eDP Display Connector

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

A

SYNC_DATE=08/09/2017SYNC_MASTER=SEAN

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

85 OF 200

SHEET

82 OF 131

1

678

3 245

1

D

C

124 119 87 86 85 84 83

124

119 87 86 85 84

PP1V8_SSD0

PP2V5_NAND_SSD0

C8648

1

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

1

C8632

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

C8636

4.3UF

1

C8649

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

20%

432

4V

CERM

0402-THICKSTNCL

CRITICAL

1

C8650

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8637

2.2UF

20%

2

6.3V
X5R-CERM
0201

124 87 86 85 84 83

119

NOSTUFF

1

R8630

0

5%
1/20W
MF
201

2

PP0V9_SSD0

SSD0_S4E0_VPP

F3

VPP

R2

VDD_PLL

S4E0

L12G4E12

VCC

P9T5N2K9J2

D3

VDDIO

E10

E2R4R8R6L8L6G8

VDD

G6

J4

ANI1_VREF

J8

L2

G12

ANI0_VREF

PCI_VDD_2

AVDD18_PLL

TP_SSD0_S4E0_ANI1_VREF
TP_SSD0_S4E0_ANI0_VREF

PP1V8_SSD0_S4E0_AVDD18_PLL
PP1V8_SSD0_S4E0_PCI_AVDD_H

PP0V9_SSD0

N8H7J6

PCI_VDD_1

PCI_AVDD_H

M9

N6

D

PP0V9_SSD0

1

1

C8610

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

C8646

1

1.0UF

20%

2

10V
X5R-CERM
0201-1

124 119 87 86 85 84 83

1

C8644

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C8611

2.2UF

20%

2

6.3V
X5R-CERM
0201

C8647

1

0.1UF

10%

2

16V
X5R-CERM
0201

1

C8645

0.1UF

10%
16V

2

X5R-CERM
0201

C8612

2.2UF

20%

2

6.3V
X5R-CERM
0201

C8613

1

0.1UF

10%

2

16V
X5R-CERM
0201

R8601

0

5%

1/20W

MF

0201

R8699

0

5%

1/20W

MF

0201

C8614

1

0.1UF

10%

2

16V
X5R-CERM
0201

21

21

C8615

1

0.1UF

10%

2

16V
X5R-CERM
0201

PP1V8_SSD0

124

124

119 87 86 85 84 83

119 87 86 85 84 83

C

B

119 87 86 85 84 83

124

PP1V8_SSD0

1

R8602

47K

1%
1/20W
MF
201

2

NOSTUFF

1

R8603

47K

1%
1/20W
MF
201

2

SSD0_OCARINA_PFN

SSD0_S4E0_DROOP_L

PCI_AVDD_CLK_1

U8600

KLAFGAKWCM-E0T2

B3

87 86 85 84

91 90 89 88 86 85 84 38

86 85 84 83

86 85 84

87 86 85 84 83

86 85 84 47 41

121 86 85 84 39

121 86 85 84 39

121 84

TPA8601

121 86 85 84

121 83

87 86 85 84 47

87 86 85 84 83

121 83

121

121

IN
IN
IN

IN

OUT

IN

IN

BI

OUT

OUT

TP

TP-P6

IN

BI

IN

SSD0_OCARINA_LPB_L
SSD_BFH
SSD0_S4E_BOOT2

83

SSD0_S4E0_SWD_UID0
SSD0_S4E_UART_RX

83

SSD0_S4E0_SWD_UID1
SSD0_S4E0_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E0_JTAG_TDO

1

SSD0_S4E0_JTAG_TDI
SSD0_S4E_JTAG_SEL
SSD0_S4E0_DROOP_L
SSD0_OCARINA_WP_L

EXT_D0/BOOT0

C4

EXT_D1/BOOT1

B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX

C8

EXT_D5/SWD_UID1/SPINAND_MOSI

B9

EXT_D6/UART_TX

B11

EXT_D7/SPF

E8

EXT_NCE/PERST*

D7

EXT_NRE/JTAG_TMS

E6

EXT_NWE/JTAG_TCK

E4

EXT_RNB/JTAG_TDO

D5

EXT_CLE/JTAG_TDI

D9

EXT_ALE/JTAG_SEL

T3

DROOP_N

G2

WP_N

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

ULGA-COMBO

OMIT_TABLE

CRITICAL

VSS

K7K5K1

L10

K13

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

GND_VOID=TRUE

GND_VOID=TRUE

D13

D11D1C12

PCI_AVDD_CLK_2

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

C2

B13B1A12

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

A8A6A4

A10

CLK_IN

RESET*

TRST*

ZQ_C
ZQ_N

A2

M3
K11

J12
P5

M11
N12

118

R12
T11

118

L4
G10
K3

C10

SSD0_CLK24M_01

84

PCIE_CLK100M_SSD0_01_P

PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L

SSD0_S4E0_PCIE_RESREF

PCIE_SSD0_R2D_P<0>

118

PCIE_SSD0_R2D_N<0>

GND_VOID=TRUE

PCIE_SSD0_D2R_C_P<0>

PCIE_SSD0_D2R_C_N<0>

118

SSD0_OCARINA_RESET_L

GND_VOID=TRUE

SSD0_S4E_JTAG_TRST_L
SSD0_S4E0_ZQ_C

SSD0_S4E0_ZQ_L

PLACE_NEAR=U8600.C10:5mm

1

R8605

300

1%
1/20W
MF
201

2

IN
IN

OUT

41 47

GND_VOID=TRUE

C8604

0.22UF

2 1

10%0201

X5R-CERM

C8602

0.22UF

2 1

0201

X5R-CERM

R8640

100

MF

1%

1/20W 201

C8603

0.22UF

2 1

0201 10%

X5R-CERM

C8601

6.3V

6.3V10%

1

R8606

100

1%
1/20W
MF
201

2

0.22UF

2 1

10%0201

X5R-CERM

SSD0_CLK24M

21

PCIE_SSD0_R2D_C_P<0>

GND_VOID=TRUE

6.3V

PCIE_SSD0_R2D_C_N<0>

GND_VOID=TRUE

PCIE_SSD0_D2R_P<0>

GND_VOID=TRUEGND_VOID=TRUE

6.3V

PCIE_SSD0_D2R_N<0>

GND_VOID=TRUE

IN

86 85 84

87 86 85 84

1

R8600

100K

1%
1/20W
MF
201

2

47 85

IN

IN

OUT

OUT

118 41

IN

118 41

118 41

118 41

1

R8604

3.01K

1%
1/20W
MF
201

2

B

A

1

R8620

100K

1%
1/20W
MF
201

2

1

R8608

100K

1%
1/20W
MF

2

201

SSD0_S4E_BOOT2
SSD0_S4E0_SWD_UID0
SSD0_S4E0_SWD_UID1

1

R8609

100K

1%
1/20W
MF

2

201

83

83

86 85 84 83

SYNC_DATE=01/26/2017SYNC_MASTER=j137_gs5_redhead

PAGE TITLE

A

SSD0 S4E 0

SIZE

D

BOM_COST_GROUP=SDD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

86 OF 200

SHEET

83 OF 131

8

67

35 4

2

1

678

3 245

1

S4E1

D

C

87 86 85 83

91 90 89 88 86 85 83 38

86 85 83

86 85 83

121

87 86 85 83

86 85 83 47 41

121 86 85 83 39

121 86 85 83 39

121 85

121 83

121 86 85 83

121 84

87 86 85 83 47

IN
IN
IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

124 119 87 86 85 84 83 124 119 87 86 85 84 83

PP1V8_SSD0 PP0V9_SSD0

D

124 119 87 86 85 84 83

124 119 87 86 85 84 83

PP2V5_NAND_SSD0

PP0V9_SSD0

PP1V8_SSD0_S4E1_AVDD18_PLL

SSD0_S4E1_VPP

NOSTUFF

1

R8730

0

5%
1/20W
MF
201

2

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

VDDIO

E10

E2R4R8R6L8L6G8

VDD

G6

J4

ANI1_VREF

J8

L2

G12

ANI0_VREF

PCI_VDD_2

AVDD18_PLL

N8H7J6

PCI_VDD_1

PCI_AVDD_H

U8700

KLAFGAKWCM-E0T2

B3

SSD0_OCARINA_LPB_L
SSD_BFH

SSD0_S4E_BOOT2

84

SSD0_S4E1_SWD_UID0
SSD0_S4E_UART_RX

84

SSD0_S4E1_SWD_UID1
SSD0_S4E1_UART_TX

SSD0_OCARINA_PFN
SSD0_PCIE_RESET_L

SSD0_SWDIO_UART_D2R

BI

SSD0_SWCLK_UART_R2D
SSD0_S4E1_JTAG_TDO
SSD0_S4E0_JTAG_TDO
SSD0_S4E_JTAG_SEL
SSD0_S4E1_DROOP_L

BI

SSD0_OCARINA_WP_L

EXT_D0/BOOT0

C4

EXT_D1/BOOT1

B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX

C8

EXT_D5/SWD_UID1/SPINAND_MOSI

B9

EXT_D6/UART_TX

B11

EXT_D7/SPF

E8

EXT_NCE/PERST*

D7

EXT_NRE/JTAG_TMS

E6

EXT_NWE/JTAG_TCK

E4

EXT_RNB/JTAG_TDO

D5

EXT_CLE/JTAG_TDI

D9

EXT_ALE/JTAG_SEL

T3

DROOP_N

G2

WP_N

ULGA-COMBO

OMIT_TABLE

CRITICAL

GND_VOID=TRUE

TP_SSD0_S4E1_ANI1_VREF

TP_SSD0_S4E1_ANI0_VREF

84

PP1V8_SSD0_S4E1_PCI_AVDD_H

84

PP0V9_SSD0

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

SSD0_CLK24M_01

118

118

M3
K11

PCIE_CLK100M_SSD0_01_P

J12

PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ1_L

P5

SSD0_S4E1_PCIE_RESREF

PCIE_SSD0_R2D_P<1>

M11
N12

PCIE_SSD0_R2D_N<1>

R12
T11

118

L4
G10
K3

C10

PCIE_SSD0_D2R_C_P<1>

118

PCIE_SSD0_D2R_C_N<1>

SSD0_OCARINA_RESET_L
SSD0_S4E_JTAG_TRST_L

SSD0_S4E1_ZQ_C
SSD0_S4E1_ZQ_L

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CLK_IN

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

RESET*

TRST*

ZQ_C
ZQ_N

124 119 87 86 85 84 83

83

IN

IN
IN

47 41

83 41

83 41

1

R8704

3.01K

1%
1/20W
MF
201

2

C8703

C8704

0.22UF

2 1

GND_VOID=TRUE

6.3V
X5R-CERM

10% 0201

0.22UF

2 1

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

6.3V

10%

X5R-CERM

C8702

0.22UF

2 1

0201

C8701

0.22UF

2 1

6.3V
X5R-CERM

GND_VOID=TRUE

6.3V020110%X5R-CERM

PCIE_SSD0_R2D_C_P<1>

PCIE_SSD0_R2D_C_N<1>

GND_VOID=TRUE

10% 0201

PCIE_SSD0_D2R_P<1>

PCIE_SSD0_D2R_N<1>

87 86 85 83

86 85 83

41

IN

118

IN

118 41

OUT

OUT

118 41

118 41

C

B

87 86 85 84 83

124 119

PP1V8_SSD0

1

R8702

47K

1%
1/20W
MF
201

2

1

R8709

100K

1%
1/20W
MF
201

2

1

R8708

100K

1%
1/20W
MF

2

201

SSD0_S4E1_SWD_UID0

SSD0_S4E1_DROOP_L

SSD0_S4E1_SWD_UID1

84

84

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

L10

K7K5K1

K13

VSS

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

D13

D11D1C12

C2

B13B1A12

A8A6A4

A10

A2

1

R8705

300

1%
1/20W
MF
201

2

1

R8706

100

1%
1/20W
MF
201

2

B

S4E VDDIO

S4E VDD

124 119 87 86 85 84 83

121 84

PP0V9_SSD0

1

C8710

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8711

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8712

2.2UF

20%

2

6.3V
X5R-CERM
0201

C8713

1

0.1UF

10%

16V
X5R-CERM

2

0201

C8714

1

10%16V
X5R-CERM

2

0201

C8715

1

0.1UF0.1UF

10%16V
X5R-CERM

2

0201

124 119 87 86 85 84 83

124 119 87 86 85 84 83

PP1V8_SSD0

VCC CAP

PP1V8_SSD0

C8732

1

10UF

20%6.3V
CERM-X6S

2

0402

CRITICAL

R8700

0

5%

1/20W

MF

0201

C8736

4.3UF

432

21

1

2

1

C8737

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

2.2UF

20%

6.3V

2

X5R-CERM
0201

PP1V8_SSD0_S4E1_PCI_AVDD_H

C8744

1.0UF

10V20%
X5R-CERM
0201-1

C8745

1

0.1UF

16V10%
X5R-CERM

2

0201

A

8

124 119 87 86 85 84 83

67

PP2V5_NAND_SSD0

1

C8748

1

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

C8749

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8750

2.2UF

20%

2

6.3V
X5R-CERM
0201

R8701

0

5%

1/20W

MF

0201

SYNC_MASTER=j137_gs5_redhead SYNC_DATE=01/26/2017

21

PP1V8_SSD0_S4E1_AVDD18_PLL

C8746

1

1.0UF

10V20%

2

X5R-CERM
0201-1

C8747

1

0.1UF

10%16V

2

X5R-CERM
0201

BOM_COST_GROUP=SDD

35 4

PAGE TITLE

SSD0 S4E 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

87 OF 200

SHEET

84 OF 131

1

SIZE

A

D

678

3 245

1

S4E2

D

C

87 86 84 83

91 90 89 88 86 84 83 38

86 84 83

86 84 83

121

87 86 84 83

86 84 83 47 41

121 86 84

121 86 84 83 39

87 86 84 83 47

83 39

121 86

121 84

121 86 84 83

121 85

BI

OUT

OUT

IN

IN
IN
IN

IN

OUT
IN

IN

IN

BI

IN

SSD0_OCARINA_LPB_L
SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E2_SWD_UID0

85

SSD0_S4E_UART_RX
SSD0_S4E2_SWD_UID1

85

SSD0_S4E2_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L

SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D

SSD0_S4E2_JTAG_TDO
SSD0_S4E1_JTAG_TDO
SSD0_S4E_JTAG_SEL
SSD0_S4E2_DROOP_L
SSD0_OCARINA_WP_L

124 119 87 86 85 84 83

124 119 87 86 85 84 83

NOSTUFF

1

R8830

0

5%
1/20W
MF
201

2

B3

EXT_D0/BOOT0

C4

EXT_D1/BOOT1

B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX

C8

EXT_D5/SWD_UID1/SPINAND_MOSI

B9

EXT_D6/UART_TX

B11

EXT_D7/SPF

E8

EXT_NCE/PERST*

D7

EXT_NRE/JTAG_TMS

E6

EXT_NWE/JTAG_TCK

E4

EXT_RNB/JTAG_TDO

D5

EXT_CLE/JTAG_TDI

D9

EXT_ALE/JTAG_SEL

T3

DROOP_N

G2

WP_N

124 119 87 86 85 84 83 124 119 87 86 85 84 83

PP1V8_SSD0 PP0V9_SSD0

PP2V5_NAND_SSD0

PP0V9_SSD0

PP1V8_SSD0_S4E2_AVDD18_PLL
PP1V8_SSD0_S4E2_PCI_AVDD_H

SSD0_S4E2_VPP

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

VDDIO

E10

E2R4R8R6L8L6G8

VDD

G6

J4

ANI1_VREF

L2

G12

ANI0_VREF

PCI_VDD_2

AVDD18_PLL

J8

N8H7J6

PCI_VDD_1

PCI_AVDD_H

U8800

KLAFGAKWCM-E0T2

ULGA-COMBO

OMIT_TABLE

CRITICAL

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

TP_SSD0_S4E2_ANI1_VREF
TP_SSD0_S4E2_ANI0_VREF

PP0V9_SSD0

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

M3
K11

J12
P5

M11
N12

R12
T11

L4
G10

GND_VOID=TRUE

GND_VOID=TRUE

CLK_IN

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

RESET*

TRST*

124 119 87 86 85 84 83

SSD0_CLK24M_23

86

PCIE_CLK100M_SSD0_23_P
PCIE_CLK100M_SSD0_23_N

SSD0_CLKREQ2_L
SSD0_S4E2_PCIE_RESREF
PCIE_SSD0_R2D_P<2>

118

PCIE_SSD0_R2D_N<2>

118

PCIE_SSD0_D2R_C_P<2>

118

118

PCIE_SSD0_D2R_C_N<2>

SSD0_OCARINA_RESET_L
SSD0_S4E_JTAG_TRST_L

R8840

100

C8803
C8804

C8801
C8802

21

SSD0_CLK24M

MF

201 1/20W

0.22UF

GND_VOID=TRUE GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE GND_VOID=TRUE

10% 6.3V 0201 X5R-CERM

0.22UF

2 1

X5R-CERM

2 1

6.3V020110%

2 1

2 1

X5R-CERM

6.3V10% 0201

IN

1%

GND_VOID=TRUE

X5R-CERM

GND_VOID=TRUEGND_VOID=TRUE

86 84 83

IN

IN
IN

OUT

83 47

86 41

86 41

121 47 41

PCIE_SSD0_R2D_C_P<2>

02016.3V10%

PCIE_SSD0_R2D_C_N<2>

PCIE_SSD0_D2R_P<2>

PCIE_SSD0_D2R_N<2>

87 86 84 83

IN

IN

OUT

OUT

D

118 41

118 41

1

R8804

3.01K

1%
1/20W
MF
201

2

C

118 41

118 41

B

119 87 86 85 84 83

124

PP1V8_SSD0

1

R8802

47K

1%
1/20W
MF
201

2

1

R8809

100K

1%
1/20W
MF

2

201

SSD0_S4E2_SWD_UID1

85

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

L10

K7K5K1

K13

VSS

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

D13

D11D1C12

C2

B13B1A12

A8A6A4

A10

ZQ_C
ZQ_N

A2

K3
C10

SSD0_S4E2_ZQ_C
SSD0_S4E2_ZQ_L

1

R8805

300

1%
1/20W
MF
201

2

1

R8806

100

1%
1/20W
MF
201

2

B

1

R8808

100K

1%
1/20W
MF
201

2

SSD0_S4E2_DROOP_L

SSD0_S4E2_SWD_UID0

85

121 85

S4E VDDIO

S4E VDD

PP1V8_SSD0

1

C8832

10UF

20%

6.3V
CERM-X6S

2

0402

CRITICAL

R8800

0

5%

1/20W

MF

0201

C8836

4.3UF

432

21

1

2

1

C8837

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

PP1V8_SSD0_S4E2_PCI_AVDD_H

C8844

1.0UF

20%
10V
X5R-CERM
0201-1

1

2

2.2UF

20%

2

6.3V
X5R-CERM

85

C8845

0.1UF

10%
16V
X5R-CERM
0201

124 119 87 86 85 84 83

PP0V9_SSD0

1

C8810

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

124 119 87 86 85 84 83

1

C8811

2.2UF

20%

2

6.3V
X5R-CERM 0201
0201

1

C8812

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8813

0.1UF

10%
16V
X5R-CERM

2

0201

1

C8814

0.1UF

10%
16V
X5R-CERM

2

0201

1

C8815

0.1UF

10%
16V
X5R-CERM

2

0201

124 119 87 86 85 84 83

PP1V8_SSD0

VCC CAP

A

8

124 119 87 86 85 84 83

67

PP2V5_NAND_SSD0

1

C8848

1

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

C8849

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8850

2.2UF

20%

2

6.3V
X5R-CERM
0201

R8801

0

5%

1/20W

MF

0201

SYNC_MASTER=j137_gs5_redhead SYNC_DATE=01/26/2017

PAGE TITLE

PP1V8_SSD0_S4E2_AVDD18_PLL

85

21

SSD0 S4E 2

DRAWING NUMBER

SIZE

051-02643

1

C8846

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C8847

0.1UF

10%
16V

2

X5R-CERM
0201

35 4

BOM_COST_GROUP=SDD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

REVISION

4.0.0

BRANCH

evt-0

PAGE

88 OF 200

SHEET

85 OF 131

1

A

D

678

3 245

1

S4E3

D

C

86 85 84 83

124 119 87

PP1V8_SSD0

1

R8902

47K

1%
1/20W
MF

2

201

1

R8908

100K

1%
1/20W
MF
201

2

87 85 84 83

91 90 89 88 85 84 83 38

87 85 84 83

85 84 83 47 41

121 85 84 83 39

121 85 84 83 39

TPA8901

121 85 84 83

87 85 84 83 47

1

R8909

100K

1%
1/20W
MF
201

2

85 84 83

85 84 83

121

121 85

121 86

IN
IN
IN

86

IN

86

OUT

IN

IN

BI

OUT

TP

TP-P6

IN

IN

BI

IN

SSD0_OCARINA_LPB_L

SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E3_SWD_UID0
SSD0_S4E_UART_RX
SSD0_S4E3_SWD_UID1
SSD0_S4E3_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D

121

SSD0_S4E3_JTAG_TDO

1

SSD0_S4E2_JTAG_TDO
SSD0_S4E_JTAG_SEL
SSD0_S4E3_DROOP_L
SSD0_OCARINA_WP_L

124 119 87 86 85 84 83

124 119 87 86 85 84 83

NOSTUFF

1

R8930

0

5%
1/20W
MF
201

2

B3

EXT_D0/BOOT0

C4

EXT_D1/BOOT1

B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX

C8

EXT_D5/SWD_UID1/SPINAND_MOSI

B9

EXT_D6/UART_TX

B11

EXT_D7/SPF

E8

EXT_NCE/PERST*

D7

EXT_NRE/JTAG_TMS

E6

EXT_NWE/JTAG_TCK

E4

EXT_RNB/JTAG_TDO

D5

EXT_CLE/JTAG_TDI

D9

EXT_ALE/JTAG_SEL

T3

DROOP_N

G2

WP_N

U12

U8U6U4

U10

124 119 87 86 85 84 83 124 119 87 86 85 84 83

PP1V8_SSD0

PP0V9_SSD0

PP2V5_NAND_SSD0

PP0V9_SSD0

SSD0_S4E3_VPP

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

VDDIO

E10

E2R4R8R6L8L6G8

VDD

G6

J4

ANI1_VREF

J8

L2

G12

ANI0_VREF

PCI_VDD_2

AVDD18_PLL

N8H7J6

PCI_VDD_1

PCI_AVDD_H

U8900

KLAFGAKWCM-E0T2

ULGA-COMBO

OMIT_TABLE

CRITICAL

VSS

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

L10

K7K5K1

K13

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

D13

D11D1C12

TP_SSD0_S4E3_ANI1_VREF
TP_SSD0_S4E3_ANI0_VREF

PP1V8_SSD0_S4E3_AVDD18_PLL
PP1V8_SSD0_S4E3_PCI_AVDD_H

86

PP0V9_SSD0

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

SSD0_CLK24M_23

118

118

A2

M3

PCIE_CLK100M_SSD0_23_P

K11
J12

PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ3_L

P5

SSD0_S4E3_PCIE_RESREF
PCIE_SSD0_R2D_P<3>

M11
N12

PCIE_SSD0_R2D_N<3>

R12
T11

L4
G10
K3

C10

SSD0_OCARINA_RESET_L
SSD0_S4E_JTAG_TRST_L
SSD0_S4E3_ZQ_C

SSD0_S4E3_ZQ_L

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

C2

B13B1A12

CLK_IN

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

RESET*

TRST*

ZQ_C
ZQ_N

A8A6A4

A10

D

124 119 87 86 85 84 83

85

IN

85 41

85 41

121 47 41

PCIE_SSD0_R2D_C_P<3>

GND_VOID=TRUE

PCIE_SSD0_R2D_C_N<3>

GND_VOID=TRUE

PCIE_SSD0_D2R_P<3>

GND_VOID=TRUE

PCIE_SSD0_D2R_N<3>

OUT

OUT

1

R8904

118 41

118 41

3.01K

1%
1/20W

MF

2

201

C

IN

41

IN

118

GND_VOID=TRUE

C8904

GND_VOID=TRUE

PCIE_SSD0_D2R_C_P<3>

PCIE_SSD0_D2R_C_N<3>

GND_VOID=TRUE GND_VOID=TRUE

1

R8905

300

1%
1/20W
MF
201

2

0.22UF

6.3V

GND_VOID=TRUE

C8902

0.22UF

1

2

2 1

10% 0201

X5R-CERM

2 1

10% 02016.3V

X5R-CERM

R8906

100

1%
1/20W
MF
201

C8903

0.22UF

2 1

6.3V 10%
X5R-CERM

C8901

0.22UF

2 1

6.3V

10% 0201

X5R-CERM

IN
IN

OUT

0201

87 85 84 83

85 84 83

B

SSD0_S4E3_SWD_UID0

SSD0_S4E3_SWD_UID1

86

86

SSD0_S4E3_DROOP_L

B

121 86

S4E VDDIO

S4E VDD

PP1V8_SSD0

1

C8932

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

R8900

0

5%

1/20W

MF

0201

C8936

4.3UF

432

21

1

2

1

C8937

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

PP1V8_SSD0_S4E3_PCI_AVDD_H

C8944

1.0UF

20%
10V
X5R-CERM
0201-1

1

2

2.2UF

20%

2

6.3V
X5R-CERM
0201

86

C8945

0.1UF

10%
16V
X5R-CERM
0201

124 119 87 86 85 84 83

PP0V9_SSD0

1

C8910

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8911

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C8912

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8913

10%
16V

2

X5R-CERM
0201

VCC CAP

PP2V5_NAND_SSD0

1

C8914

0.1UF0.1UF

10%
16V

2

X5R-CERM
0201

1

C8915

0.1UF

10%
16V

2

X5R-CERM
0201

124 119 87 86 85 84 83

124 119 87 86 85 84 83

PP1V8_SSD0

124 119 87 86 85 84 83

A

8

1

C8948

10UF

20%

6.3V
CERM-X6S

2

0402

CRITICAL

1

C8949

2.2UF

20%

2

6.3V
X5R-CERM
0201

1

C8950

2.2UF

20%

2

6.3V
X5R-CERM
0201

R8901

0

5%

1/20W

MF

0201

86

21

PP1V8_SSD0_S4E3_AVDD18_PLL

1

C8946

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C8947

0.1UF

10%
16V

2

X5R-CERM
0201

SYNC_MASTER=j137_gs5_redhead SYNC_DATE=01/26/2017

PAGE TITLE

SSD0 S4E 3

SIZE

Apple Inc.

DRAWING NUMBER

051-02643

REVISION

A

D

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

BOM_COST_GROUP=SDD

67

35 4

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

89 OF 200

SHEET

86 OF 131

1

678

3 245

1

D

PPBUS_G3H_SSD0_SNS

116

SSD0_VR_P2V5_EN

87

1

C9073

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

R9098

0

5%

1/20W

MF

0201

1

C9074

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

21

SSD0_VR_P2V5_EN_R

1

C9080

2

CRITICAL

10UF

20%
25V
X5R-CERM
0603

CRITICAL

1

C9081

10UF

20%
25V

2

X5R-CERM
0603

87

SSD0_VR_P2V5_EN_R

87

SSD0_TPS62180_SS

1

C9082

1000PF

10%

2

25V
X7R
0201

PLACE_NEAR=U9080.C4:5MM

87

P2V5_SSD0_AGND

U9080

TPS62180

A1

VIN1

B1

VIN1

C1

VIN1

D1

VIN2

E1

VIN2

F1

VIN2
EN VO

E4
D4

SS/TR

AGND
C4

BGA

CRITICAL

PGND

PGND

PGND

B3

A3

C3

SM

PGND
D3

21

XW9000

PGND

PGND
F3

E3

SW1
SW1
SW1

SW2
SW2
SW2

PG

FB

A2
B2
C2

D2
E2
F2

A4
F4
B4

P2V5_SW1_TPS62180_SSD0

DIDT=TRUE

SWITCH_NODE=TRUE

P2V5_SW2_TPS62180_SSD0

DIDT=TRUE

SWITCH_NODE=TRUE

87

SSD0_VR_P2V5_PGOOD

SSD0_TPS62180_FB

L9080

1UH-20%-3.8A-0.035OHM

PIFE32251B-SM

CRITICAL

L9081

1UH-20%-3.8A-0.035OHM

CRITICAL

PP2V5_NAND_SSD0

1

R9088

100K

1%
1/20W
MF
201

2

PIFE32251B-SM

SSD0_TPS62180_FB_R

21

21

P2V5_SSD0_AGND

87

1

R9083

10.2

1%
1/20W
MF

2

201

1

C9085

22PF

2%
50V

2

C0G-CERM
0201

124 119 87 86 85 84 83

1

R9080

475K

1%
1/20W
MF
201

2

OMIT_TABLE

1

R9081

200K

0.1%
1/20W
TF

2

0201

C9086

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9087

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9088

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9089

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9090

1

20UF

20%

2

10V
X5R
0402

CRITICAL

PP2V5_NAND_SSD0

C9091

1

20UF 20UF

20%

2

10V
X5R
0402

CRITICAL

C9092

1

2

CRITICAL CRITICAL

VOLTAGE=2.5V

20%
10V
X5R
0402

C9093

1

20UF

20%

2

10V
X5R
0402

124 119 87 86 85 84 83

D

C

B

PP3V3_G3H_SSD0_SNS

87 116

CRITICAL

PP3V3_G3H_SSD0_SNS

87 116

PLACE C2000-C2002 NEAR OCARINA PINS E7/E8
PLACE C2003-C2005 NEAR OCARINA PINS A7/A8
PLACE C2006 NEAR OCARINA PIN B4

C9000

1

2

87 116

1

R9010

100K

1%
1/20W
MF
201

2

C9001

1

10UF

20%

6.3V
CERM-X6S
0402

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

PP3V3_G3H_SSD0_SNS

1

2

1

R9011

100K

1%
1/20W
MF
201

2

1

R9012

0

5%
1/20W
MF
0201

2

119 93 92 77 39 38

C9002

1

0.1UF

20%

2

16V
X6S-CERM
0201

This sets the addres to 0xF2 for STG0

R9006

10K

5%
1/20W
MF
201

51

51

86 85 84 83

85 83

86 84

119 92 47 38

87

86 85 84 83

NO_TEST=1

86 85 84 83 47

87

C9003

1

4.7UF

20%

2

6.3V
X6S
0402

CRITICAL

C9004

1

4.7UF

20%

2

6.3V
X6S
0402

CRITICAL

SSD0_STG01_ADDR
SSD0_OCARINA_FORCE_EN
I2C_SSD0_SCL

I2C_SSD0_SDA
SSD0_OCARINA_LPB_L

SSD0_OCARINA_PFN

SSD0_OCARINA_PGOOD
SSD_PMU_RESET_L
SSD0_VR_P2V5_PGOOD

SSD0_OCARINA_POK2
SSD0_OCARINA_RESET_L
PMU_SYS_ALIVE
SSD0_VR_P2V5_EN

NC_SSD0_OCARINA_VEN2
SSD0_OCARINA_WP_L

C9005

1

0.1UF

20%

2

16V
X6S-CERM
0201

CAPDERATE

1

C9006

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

CRITICAL

F3

ATM

D2

ADDR
FORCE_EN

E1

G2

I2C_SCL
I2C_SDA

G3

LPBN

F4

PFN*

G5

PGOOD

G6

D1

PMIC_RESET*

D3

POK1

F1

POK2

E5

RESET*
SYS_ALIVE

F2
F5

VEN1
VEN2

E4

WP*

G4

OCARINA I2C BASE ADDRESS

STG0: F2
STG1: F0

A8

E7

E8

VDD_BUCK0

VDD_BUCK1

VDD_BUCK0

B4

A7

VDD_MAIN

VDD_BUCK1

B5

VDD_LDO

U9000

D2499A0

WLCSP

CRITICAL

OMIT_TABLE

R2081:200K->2.7V, 221K->2.519V NAND VCC

SSD0_OCARINA_VDD_LDO

SSD0_OCARINA_NAND_VCC_DET

PP1V8_SSD0

G1

C1

VCC_DET

V_BUF_1.8V

TCAL

VREF

IREF

TDEV1
TDEV2

VR1_DISCHG
VR2_DISCHG

BUCK0_FB_DIS
BUCK1_FB_DIS

BUCK0_LX0
BUCK0_LX0

BUCK0_LX1
BUCK0_LX1

BUCK1_LX0
BUCK1_LX0

1

C9009

0.1UF

10%
16V

2

X5R-CERM
0201

SSD0_OCARINA_TCAL

A4

SSD0_OCARINA_VREF

B3

SSD0_OCARINA_IREF

B2

SSD0_OCARINA_TDEV1

B1
C2

SSD0_OCARINA_TDEV2
PP2V5_NAND_SSD0

A3
A1

NC_SSD0_OCARINA_VR2_DIS
PP0V9_SSD0_FB_DIS

D5

PP1V8_SSD0_FB_DIS

C5

P0V9_LX0_SSD0

F8
F7

P0V9_LX1_SSD0

D8
D7

B8

P1V8_LX0_SSD0

B7

124 119 87 86 85 84 83

SWITCH_NODE=TRUE
DIDT=TRUE

SWITCH_NODE=TRUE
DIDT=TRUE

SWITCH_NODE=TRUE
DIDT=TRUE

C9007

1

0.22UF

20%

2

6.3V
X6S-CERM
0201

TPA9000

1

A

TP-P6

NO_TEST=1

CRITICAL

87

87

124

118S0738

103S00049

87

SSD0_OCARINA_TDEV1

1

1
1 R9081

R9002

100KOHM

0201

CRITICAL

2

1

R9005

200K

0.1%
TF

0201

2

85 84 83
119 87 86

1UH-20%-3.8A-0.035OHM

L9020

L9021

PIFE32251B-SM

0.47UH-20%-5.1A-0.03OHM

CRITICAL

PIFE32251B-SM

L9030

0.47UH-20%-5.1A-0.03OHM

PIFE32251B-SM

C9008

1

0.1UF

20%16V
X6S-CERM1/20W

2

0201

21

21

21

RES,THICKFILM,200KOHM,0.1%,1/20W,0201

RES,THICKFILM,221KOHM,0.1%,1/20W,0201

87

1

1

R9001

18.2K

0.1%
1/20W
TK
0201

2

2

R9020

1

R9000

8.06K

0.1%
1/20W
TK
0201

2

C9020

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9021

1

2

CRITICAL

20UF

20%
10V
X5R
0402

1/20W

0201

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R9081

SSD0_OCARINA_TDEV2

1

R9004

100KOHM

0201

CRITICAL

0

21

5%
MF

C9022

1

20UF

20%

2

10V
X5R
0402

CRITICAL

R9030

0

5%

1/20W

MF

0201

CRITICAL

R9003

18.2K

0.1%
1/20W
TK
0201

2

21

C9023

1

20UF

20%

2

10V
X5R
0402

CRITICAL

BOM OPTIONCRITICAL

CRITICAL SSD0_NAND_VCC:2.7V
CRITICAL

SSD0_NAND_VCC:2.5V

PP0V9_SSD0

PP1V8_SSD0

PP0V9_SSD0

C9024

1

20UF

20%

2

10V
X5R
0402

C9025

1

20UF

20%

2

10V
X5R
0402

CRITICAL

PP1V8_SSD0

124

124

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

C

124 119 87 86 85 84 83

124 119 87 86 85 84 83

119 87 86 85 84 83

B

119 87 86 85 84 83

A

VSS
A6

VSS
A5

VSS
B6

VSS
A2

VSS
C3

VSS
C4

VSS
D6

VSS
D4

VSS
E6

VSS
E2

VSS
F6

VSS(VSS_BUCK0)

VSS(VSS_BUCK0)

VSS
E3

G8

G7

VSS(VSS_BUCK01)

VSS(VSS_BUCK01)

VSS(VSS_BUCK01)

C6

C7

C8

CRITICAL

C9030

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9031

1

20%

2

10V
X5R
0402

CRITICAL

C9032

1

20UF20UF

20%

2

10V
X5R
0402

CRITICAL

PAGE TITLE

C9033

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9034

1

20UF

20%

2

10V
X5R
0402

CRITICAL

C9035

1

20UF

20%

2

10V
X5R
0402

CRITICAL

SYNC_DATE=01/26/2017SYNC_MASTER=j137_gs5_redhead

A

8

SSD0 PMIC & VR

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

BOM_COST_GROUP=SDD

67

35 4

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

90 OF 200

SHEET

87 OF 131

1

SIZE

D

678

3 245

1

D

C

B

90 89 88

124 119 92 91

124 119 92 91 90 89 88

124 119 92 91 90 89

PP1V8_SSD1

S4E_L5

VCC CAP

PP1V8_SSD1

CRITICAL

PP2V5_NAND_SSD1

S4E_L5

C9148

1

10UF

20%

2

6.3V
CERM-X6S
0402

NOSTUFF

1

R9102

47K

1%
1/20W
MF
201

2

1

R9103

47K

1%
1/20W
MF
201

2

S4E_L5

S4E_L5

1

C9132

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

C9136

4.3UF

S4E_L5

1

C9149

2.2UF

20%

2

6.3V
X5R-CERM
0201

432

SSD1_OCARINA_PFN
SSD1_S4E0_DROOP_L

88

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

S4E_L5

1

C9150

2.2UF

20%

2

6.3V
X5R-CERM
0201

91 90 89 86 85 84 83 38

92 91 90 89 88

91 90 89 47 41

121 91 90 89 39

121 91 90 89 39

TPA9101

92 91 90 89 47

92 91 90 89 88

S4E_L5

1

C9137

2.2UF

20%

2

6.3V
X5R-CERM
0201

92 91 90 89

91 90 89 88

91 90 89

121

121 89

121

121 91 90 89

IN
IN
IN

IN

OUT

IN

IN

BI

OUT

OUT

TP

TP-P6

IN

IN

SSD1_OCARINA_LPB_L
SSD_BFH
SSD1_S4E_BOOT2
SSD1_S4E0_SWD_UID0

88

SSD1_S4E_UART_RX
SSD1_S4E0_SWD_UID1

88

SSD1_S4E0_UART_TX
SSD1_OCARINA_PFN

SSD1_PCIE_RESET_L
SSD1_SWDIO_UART_D2R
SSD1_SWCLK_UART_R2D
SSD1_S4E0_JTAG_TDO

1

SSD1_S4E0_JTAG_TDI
SSD1_S4E_JTAG_SEL
SSD1_S4E0_DROOP_L

88

SSD1_OCARINA_WP_L

124 119 91

NOSTUFF

1

R9130

0

5%
1/20W
MF
201

2

B3
C4
B5
C6
B7
C8
B9

B11

E8
D7
E6
E4
D5
D9

T3

G2

92 90 89 88

PP0V9_SSD1

SSD1_S4E0_VPP

EXT_D0/BOOT0
EXT_D1/BOOT1
EXT_D2/BOOT2/SPINAND_SCLK
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D4/UART_RX
EXT_D5/SWD_UID1/SPINAND_MOSI
EXT_D6/UART_TX
EXT_D7/SPF

EXT_NCE/PERST*
EXT_NRE/JTAG_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
DROOP_N
WP_N

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

S4E0

P13

F3

VPP

P7P3P1

P11

R2

VDD_PLL

N10

L12G4E12

VCC

N4

M7M5M1

M13

P9T5N2K9J2

D3

VDDIO

OMIT_TABLE

U9100

KLAFGAKWCM-E0T2

ULGA

CRITICAL

VSS

K7K5K1

L10

K13

E10

E2R4R8R6L8L6G8

VDD

H13

H9H5H3

H11

J10

H1

G6

J4

ANI0_VREF

ANI1_VREF

F9F7F5

F13

F11

L2

G12

PCI_VDD_2

AVDD18_PLL

F1

J8

N8H7J6

PCI_VDD_1

PCI_AVDD_H

D13

D11D1C12

TP_SSD1_S4E0_ANI1_VREF
TP_SSD1_S4E0_ANI0_VREF

PP1V8_SSD1_S4E0_AVDD18_PLL
PP1V8_SSD1_S4E0_PCI_AVDD_H

PP0V9_SSD1

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

CLK_IN

M3

SSD1_CLK24M_01

89

PCIE_CLK100M_SSD1_01_P

GND_VOID=TRUE

GND_VOID=TRUE

PCIE_REFCLK_P

PCIE_REFCLK_M

K11
J12

PCIE_CLK100M_SSD1_01_N
SSD1_CLKREQ0_L

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

C2

B13B1A12

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

RESET*

TRST*

ZQ_C
ZQ_N

A8A6A4

A10

118

P5

M11
N12

R12
T11

118

L4

91 90 89

G10
K3

C10

A2

PCIE_SSD1_R2D_P<0>

118

PCIE_SSD1_R2D_N<0>

PCIE_SSD1_D2R_C_P<0>

118

PCIE_SSD1_D2R_C_N<0>

SSD1_OCARINA_RESET_L
SSD1_S4E_JTAG_TRST_L

SSD1_S4E0_ZQ_C
SSD1_S4E0_ZQ_L

124 119 92 91 90 89 88

S4E_L5

GND_VOID=TRUE

S4E_L5

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

PLACE_NEAR=U9100.C10:5mm

S4E_L5

1

C9110

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

S4E_L5

C9146

1

1.0UF

20%10V

2

X5R-CERM
0201-1

S4E_L5

1

C9144

1.0UF

20%
10V

2

X5R-CERM
0201-1

GND_VOID=TRUE

0201

S4E_L5

0201

S4E_L5

1

R9105

300

1%
1/20W
MF
201

2

1

2

S4E_L5

R9140

1/20W 201MF

IN
IN

OUT

S4E_L5

C9104

0.22UF

2 1

6.3V

10%

X5R-CERM

C9102

0.22UF

2 1

6.3V10%

X5R-CERM

1

2

S4E_L5

C9111

2.2UF

6.3V
X5R-CERM
0201

S4E_L5

C9147

1

0.1UF

10%16V

2

X5R-CERM
0201

S4E_L5

1

C9145

0.1UF

10%
16V

2

X5R-CERM
0201

100

21

1%

89 41

89 41

47 41

C9103

0.22UF

2 1

0201 10%

X5R-CERM

C9101

0.22UF

2 1

10% 6.3V

0201

X5R-CERM

S4E_L5

R9106

100

1%
1/20W
MF
201

S4E_L5

1

C9112

2.2UF

20%20%

2

6.3V
X5R-CERM
0201

R9101

1/20W

0201

R9199

0

5%

MF

1/20W

0201

1

2

0

5%

MF

S4E_L5

C9113

0.1UF

10%
16V
X5R-CERM
0201

21

21

SSD1_CLK24M

IN

SSD1_S4E0_PCIE_RESREF

PCIE_SSD1_R2D_C_P<0>

6.3V

GND_VOID=TRUE

PCIE_SSD1_R2D_C_N<0>

GND_VOID=TRUE

PCIE_SSD1_D2R_P<0>

GND_VOID=TRUE

PCIE_SSD1_D2R_N<0>

S4E_L5

R9100

1

100K

1%
1/20W
MF
201

2

S4E_L5

1

C9114

0.1UF

10%
16V
X5R-CERM

2

0201

90 47

1

C9115

0.1UF

10%
16V
X5R-CERM

2

0201

IN

IN

OUT

OUT

IN

S4E_L5

S4E_L5

1

R9104

3.01K

1%
1/20W
MF
201

2

118 41

118 41

118 41

118 41

D

PP0V9_SSD1

124

PP1V8_SSD1

124

119 92 91 90 89 88

119 92 91 90 89 88

C

B

92 91 90 89

A

S4E_L5

1

R9120

100K

1%
1/20W
MF
201

2

1

2

S4E_L5

R9108

100K

1%
1/20W
MF
201

SSD1_S4E_BOOT2

SSD1_S4E0_SWD_UID0
SSD1_S4E0_SWD_UID1

1

R9109

100K

1%
1/20W
MF

2

201

S4E_L5

88

88

91 90 89 88

SYNC_MASTER=j137_gs5_redhead SYNC_DATE=01/26/2017

PAGE TITLE

A

SSD1 S4E 0

SIZE

D

BOM_COST_GROUP=SDD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

91 OF 200

SHEET

88 OF 131

8

67

35 4

2

1

678

3 245

1

S4E1

D

C

88 90 91 92

38 83 84 85 86 88 90 91

88 90 91

88 90 91

121

88 90 91 92

41 47 88 90 91

39 88 90 91 121

39 88 90 91 121

89 90 121

88 121

47 88 90 91 92

88 89 90 91 92 119 124

PP1V8_SSD1

PP0V9_SSD1

88 89 90 91 92 119 124

D

119

88 89 90 91 92 124

88 89 90 91 92 119 124

PP2V5_NAND_SSD1

PP0V9_SSD1

SSD1_S4E1_VPP

NOSTUFF

1

R9230

0

5%
1/20W
MF
201

2

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

OMIT_TABLE

VDDIO

E10

E2R4R8R6L8L6G8

VDD

G6

ANI1_VREF

U9200

B3

IN
IN
IN

89

IN

89

OUT
IN

SSD1_OCARINA_LPB_L
SSD_BFH

SSD1_S4E_BOOT2
SSD1_S4E1_SWD_UID0

SSD1_S4E_UART_RX
SSD1_S4E1_SWD_UID1
SSD1_S4E1_UART_TX

SSD1_OCARINA_PFN
SSD1_PCIE_RESET_L

IN

SSD1_SWDIO_UART_D2R

BI

SSD1_SWCLK_UART_R2D

OUT

SSD1_S4E1_JTAG_TDO

OUT

SSD1_S4E0_JTAG_TDO

IN

88 90 91 121

IN

89

SSD1_S4E_JTAG_SEL
SSD1_S4E1_DROOP_L

SSD1_OCARINA_WP_L

IN

EXT_D0/BOOT0

C4

EXT_D1/BOOT1

B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX

C8

EXT_D5/SWD_UID1/SPINAND_MOSI

B9

EXT_D6/UART_TX

B11

EXT_D7/SPF

E8

EXT_NCE/PERST*

D7

EXT_NRE/JTAG_TMS

E6

EXT_NWE/JTAG_TCK

E4

EXT_RNB/JTAG_TDO

D5

EXT_CLE/JTAG_TDI

D9

EXT_ALE/JTAG_SEL

T3

DROOP_N

G2

WP_N

U12

U10

U8U6U4

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

KLAFGAKWCM-E0T2

L10

K13

ULGA

CRITICAL

VSS

K7K5K1

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

TP_SSD1_S4E1_ANI1_VREF

TP_SSD1_S4E1_ANI0_VREF

PP1V8_SSD1_S4E1_AVDD18_PLL

PP1V8_SSD1_S4E1_PCI_AVDD_H

J8

J4

L2

G12

ANI0_VREF

AVDD18_PLL

F1

N8H7J6

PCI_VDD_1

PCI_VDD_2

D13

D11D1C12

M9

N6

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

C2

B13B1A12

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

A10

PP0V9_SSD1

CLK_IN

RESET*

TRST*

ZQ_C
ZQ_N

A8A6A4

A2

89

M3
K11

J12
P5

M11
N12

R12
T11

L4
G10
K3

C10

89

88 89 90 91 92 119 124

SSD1_CLK24M_01
PCIE_CLK100M_SSD1_01_P

PCIE_CLK100M_SSD1_01_N
SSD1_CLKREQ1_L

SSD1_S4E1_PCIE_RESREF
PCIE_SSD1_R2D_P<1>

118

PCIE_SSD1_R2D_N<1>

118

118

PCIE_SSD1_D2R_C_P<1>

PCIE_SSD1_D2R_C_N<1>

118

SSD1_OCARINA_RESET_L
SSD1_S4E_JTAG_TRST_L

SSD1_S4E1_ZQ_C
SSD1_S4E1_ZQ_L

41 88

S4E_L6

GND_VOID=TRUE

GND_VOID=TRUE

88

IN

41 47

S4E_L6

C9204

0.22UF

2 1

6.3V
X5R-CERM

S4E_L6

X5R-CERM 10% 0201 6.3V

1

S4E_L6

R9205

300

1%
1/20W
MF
201

2

GND_VOID=TRUE

10% 0201

GND_VOID=TRUE

C9202

0.22UF

2

1

2

S4E_L6

R9206

100

1%
1/20W
MF
201

C9203

0.22UF

2 1

10%

X5R-CERM

S4E_L6

1

GND_VOID=TRUE

GND_VOID=TRUEGND_VOID=TRUE

02016.3V

C9201

0.22UF

2 1

10%6.3V 0201

X5R-CERM

88 90 91

PCIE_SSD1_R2D_C_P<1>

PCIE_SSD1_R2D_C_N<1>

PCIE_SSD1_D2R_P<1>

GND_VOID=TRUE

PCIE_SSD1_D2R_N<1>

IN

IN

OUT

OUT

IN

S4E_L6

1

R9204

3.01K

1%
1/20W
MF
201

2

41 118

41 118

41 118

41 118

88 90 91 92

C

B

PP1V8_SSD1

88 89 90 91 92
119 124

S4E_L6

1

R9202

47K

1%
1/20W
MF
201

2

S4E_L6

1

R9209

100K

1%
1/20W
MF
201

2

S4E_X6

R9231

89 90 121 91 121

SSD1_S4E1_JTAG_TDO

S4E_L6

1

R9208

100K

1%
1/20W
MF

2

201

SSD1_S4E1_SWD_UID0

SSD1_S4E1_DROOP_L

SSD1_S4E1_SWD_UID1

89

89

89

0

5%

1/20W

MF

0201

21

SSD1_S4E3_JTAG_TDO

OUTIN

88 89 90 91 92 119 124

S4E VDD

PP0V9_SSD1

S4E_L6

1

C9210

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

88 89 90 91 92 119 124

PP2V5_NAND_SSD1

S4E_L6

1

C9211

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L6

1

C9212

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L6

C9213

1

0.1UF

10%
16V

2

X5R-CERM
0201

VCC CAP

S4E_L6

C9214

1

0.1UF

10%
16V

2

X5R-CERM
0201

S4E_L6

C9215

1

0.1UF

16V
10%

2

X5R-CERM
0201

PP1V8_SSD1

88 89 90 91 92 119 124

S4E VDDIO

PP1V8_SSD1

88 89 90 91 92 119 124

1

2

S4E_L6

C9232

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

R9200

0

5%

1/20W

MF

0201

S4E_L6

C9236

4.3UF

432

21

1

2

S4E_L6

1

C9237

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

2.2UF

20%

2

6.3V
X5R-CERM
0201

PP1V8_SSD1_S4E1_PCI_AVDD_H

S4E_L6

C9244

1.0UF

20%10V
X5R-CERM
0201-1

S4E_L6

C9245

1

0.1UF

16V10%

2

X5R-CERM
0201

B

A

8

S4E_L6

C9248

1

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

67

S4E_L6

1

C9249

2.2UF

20%

2

6.3V
X5R-CERM
0201 X5R-CERM

S4E_L6

1

C9250

2.2UF

20%

2

6.3V
0201

R9201

0

5%

1/20W

MF

0201

SYNC_DATE=01/26/2017SYNC_MASTER=j137_gs5_redhead

21

PP1V8_SSD1_S4E1_AVDD18_PLL

S4E_L6

C9246

1

1.0UF

20%

2

10V
X5R-CERM
0201-1

S4E_L6

C9247

1

0.1UF

10%

2

16V
X5R-CERM
0201

BOM_COST_GROUP=SDD

35 4

PAGE TITLE

SSD1 S4E 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

92 OF 200

SHEET

89 OF 131

1

SIZE

A

D

678

3 245

1

S4E2

D

92 91 89 88

91 89 88 86 85 84 83 38

91 89 88

91 89 88

121

92 91 89 88

91 89 88 47 41

121 91 89 88 39

IN
IN
IN

IN

OUT
IN

IN

BI

SSD1_OCARINA_LPB_L
SSD_BFH
SSD1_S4E_BOOT2

90

SSD1_S4E2_SWD_UID0
SSD1_S4E_UART_RX

90

SSD1_S4E2_SWD_UID1
SSD1_S4E2_UART_TX
SSD1_OCARINA_PFN

SSD1_PCIE_RESET_L
SSD1_SWDIO_UART_D2R

124 119 92 91 90 89 88

124 119 92 91 90 89 88

NOSTUFF

1

R9330

0

5%
1/20W
MF
201

2

EXT_D0/BOOT0

B3

EXT_D1/BOOT1

C4
B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX
EXT_D5/SWD_UID1/SPINAND_MOSI

C8

EXT_D6/UART_TX

B9

EXT_D7/SPF

B11

EXT_NCE/PERST*

E8

EXT_NRE/JTAG_TMS

D7

124 119 92 91 90 89 88 124 119 92 91 90 89 88

PP1V8_SSD1

PP0V9_SSD1

PP2V5_NAND_SSD1

PP0V9_SSD1

SSD1_S4E2_VPP

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

E10

E2R4R8R6L8L6G8

VDDIO

OMIT_TABLE

VDD

G6

J4

ANI0_VREF

ANI1_VREF

L2

G12

PCI_VDD_2

AVDD18_PLL

J8

N8H7J6

PCI_VDD_1

PCI_AVDD_H

U9300

KLAFGAKWCM-E0T2

ULGA

CRITICAL

TP_SSD1_S4E2_ANI1_VREF
TP_SSD1_S4E2_ANI0_VREF

PP1V8_SSD1_S4E2_AVDD18_PLL
PP1V8_SSD1_S4E2_PCI_AVDD_H

PP0V9_SSD1

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

SSD1_CLK24M_23 SSD1_CLK24M

91

PCIE_CLK100M_SSD1_23_P
PCIE_CLK100M_SSD1_23_N

SSD1_CLKREQ2_L
SSD1_S4E2_PCIE_RESREF

PCIE_SSD1_R2D_P<2>

118

118

PCIE_SSD1_R2D_N<2>

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CLK_IN

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

M3
K11

J12
P5

M11
N12

D

124 119 92 91 90 89 88

S4E_L7

21

GND_VOID=TRUE

2011/20W MF

1%

C9303

0.22UF

2 1

X5R-CERM

GND_VOID=TRUE

10%6.3V

IN
IN

OUT

GND_VOID=TRUE

0201

IN

91 41

91 41

47 41

88 47

PCIE_SSD1_R2D_C_P<2>

PCIE_SSD1_R2D_C_N<2>

S4E_L7

1

R9304

3.01K

1%
1/20W
MF
201

2

IN

IN

118 41

118 41

S4E_L7

R9340

100

S4E_L7

C9304

0.22UF

GND_VOID=TRUE

2 1

C

124 119 92 91 90 89 88

PP1V8_SSD1

S4E_L7

1

R9302

47K

1% MF
1/20W
MF
201

2

S4E_L7

1

R9309

100K

1%
1/20W

201

2

121 91 89 88 39

121 91

121 89

121 91 89 88

92 91 89 88 47

OUT

OUT

IN

IN

IN

SSD1_SWCLK_UART_R2D
SSD1_S4E2_JTAG_TDO
SSD1_S4E1_JTAG_TDO
SSD1_S4E_JTAG_SEL

90

SSD1_S4E2_DROOP_L
SSD1_OCARINA_WP_L

EXT_NWE/JTAG_TCK

E6

EXT_RNB/JTAG_TDO

E4

EXT_CLE/JTAG_TDI

D5

EXT_ALE/JTAG_SEL

D9

DROOP_N

T3

WP_N

G2

U8U6U4

U12

U10

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

L10

K7K5K1

K13

VSS

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

D13

D11D1C12

GND_VOID=TRUE

GND_VOID=TRUE

C2

B13B1A12

PCIE_TX0_P

PCIE_TX0_M

RESET*

TRST*

A8A6A4

A10

ZQ_C
ZQ_N

A2

R12
T11

L4
G10
K3

C10

118

PCIE_SSD1_D2R_C_P<2>

118

PCIE_SSD1_D2R_C_N<2>
SSD1_OCARINA_RESET_L

SSD1_S4E_JTAG_TRST_L
SSD1_S4E2_ZQ_C

SSD1_S4E2_ZQ_L

6.3V

S4E_L7

1

R9305

300

1%
1/20W
MF
201

2

10%

X5R-CERM

0201

S4E_L7

1

2

S4E_L7

C9302

0.22UF

GND_VOID=TRUE

2 1

X5R-CERM

S4E_L7

10%6.3V

R9306

100

1%
1/20W
MF
201

C9301

0.22UF

GND_VOID=TRUE

GND_VOID=TRUE

0201

2 1

6.3V
X5R-CERM

91 89 88

PCIE_SSD1_D2R_P<2>

GND_VOID=TRUE

020110%

PCIE_SSD1_D2R_N<2>

OUT

OUT

C

118 41

118 41

IN

92 91 89 88

B

S4E_L7

1

R9308

100K

1%
1/20W
MF
201

2

SSD1_S4E2_SWD_UID1
SSD1_S4E2_DROOP_L

SSD1_S4E2_SWD_UID0

90

90

90

124 119 92 91 90 89 88

S4E VDD

PP0V9_SSD1

S4E_L7

1

C9310

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

S4E_L7

1

C9311

2.2UF

20%

2

6.3V
X5R-CERM
0201

VCC CAP

S4E_L7

1

C9312

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L7

C9313

1

0.1UF

10%
16V
X5R-CERM

2

0201

S4E_L7

C9314

1

0.1UF

10%
16V
X5R-CERM

2

0201

S4E_L7

C9315

1

0.1UF

10%
16V
X5R-CERM

2

0201

124 119 92 91 90 89 88

124 119 92 91 90 89 88

PP1V8_SSD1

S4E VDDIO

PP1V8_SSD1

S4E_L7

C9332

1

10UF

20%

6.3V
CERM-X6S

2

0402

CRITICAL

R9300

0

5%

1/20W

MF

0201

S4E_L7

C9336

4.3UF

432

21

S4E_L7

1

C9337

1

20%

4V

CERM

0402-THICKSTNCL

CRITICAL

PP1V8_SSD1_S4E2_PCI_AVDD_H

S4E_L7

1

C9344

1.0UF

20%
10V
X5R-CERM

2

0201-1

1

C9345

2

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L7

0.1UF

10%
16V
X5R-CERM
0201

B

A

8

124 119 92 91 90 89 88

67

PP2V5_NAND_SSD1

S4E_L7

C9348

1

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

S4E_L7

1

C9349

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L7

1

C9350

2.2UF

20%

2

6.3V
X5R-CERM
0201

R9301

0

5%

1/20W

MF

0201

SYNC_DATE=01/26/2017SYNC_MASTER=j137_gs5_redhead

PAGE TITLE

A

SSD1 S4E 2

21

PP1V8_SSD1_S4E2_AVDD18_PLL

S4E_L7

C9346

1

1.0UF

20%
10V
X5R-CERM

2

0201-1

S4E_L7

C9347

1

0.1UF

10%
16V

2

X5R-CERM
0201

35 4

BOM_COST_GROUP=SDD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

93 OF 200

SHEET

90 OF 131

1

SIZE

D

678

3 245

1

S4E3

D

C

92 90 89 88

90 89 88 86 85 84 83 38

90 89 88

90 89 88

121

92 90 89 88

90 89 88 47 41

121 90 89 88 39

121 90 89 88 39

TPA9401

121 90 89 88

121 89

121 90

IN
IN
IN

IN

OUT

IN

IN

BI

OUT

TP

TP-P6

IN

IN

SSD1_OCARINA_LPB_L
SSD_BFH

SSD1_S4E_BOOT2

91

SSD1_S4E3_SWD_UID0
SSD1_S4E_UART_RX

91

SSD1_S4E3_SWD_UID1
SSD1_S4E3_UART_TX
SSD1_OCARINA_PFN

SSD1_PCIE_RESET_L

SSD1_SWDIO_UART_D2R

SSD1_SWCLK_UART_R2D

1

SSD1_S4E3_JTAG_TDO
SSD1_S4E2_JTAG_TDO
SSD1_S4E_JTAG_SEL

124 119 92 91 90 89 88

124 119 92 91 90 89 88

NOSTUFF

1

R9430

0

5%
1/20W
MF
201

2

EXT_D0/BOOT0

B3

EXT_D1/BOOT1

C4
B5

EXT_D2/BOOT2/SPINAND_SCLK

C6

EXT_D3/SWD_UID0/SPINAND_MISO

B7

EXT_D4/UART_RX
EXT_D5/SWD_UID1/SPINAND_MOSI

C8

EXT_D6/UART_TX

B9

EXT_D7/SPF

B11

EXT_NCE/PERST*

E8

EXT_NRE/JTAG_TMS

D7

EXT_NWE/JTAG_TCK

E6

EXT_RNB/JTAG_TDO

E4

EXT_CLE/JTAG_TDI

D5

EXT_ALE/JTAG_SEL

D9

124 119 92 91 90 89 88

PP2V5_NAND_SSD1

PP0V9_SSD1

SSD1_S4E3_VPP

PP1V8_SSD1

F3

VPP

R2

VDD_PLL

L12G4E12

VCC

P9T5N2K9J2

D3

VDDIO

U9400

KLAFGAKWCM-E0T2

ULGA

OMIT_TABLE

CRITICAL

E10

E2R4R8R6L8L6G8

VDD

G6

J4

ANI0_VREF

ANI1_VREF

PP0V9_SSD1

J8

L2

G12

AVDD18_PLL

N8H7J6

PCI_VDD_1

PCI_VDD_2

M9

N6

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

124 119 92 91 90 89 88

TP_SSD1_S4E3_ANI1_VREF
TP_SSD1_S4E3_ANI0_VREF

PP1V8_SSD1_S4E3_AVDD18_PLL
PP1V8_SSD1_S4E3_PCI_AVDD_H

PP0V9_SSD1

CLK_IN

PCIE_REFCLK_P

PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P

PCIE_RX0_M

PCIE_TX0_P

PCIE_TX0_M

M3
K11

J12
P5

M11
N12

R12
T11

SSD1_CLK24M_23

PCIE_CLK100M_SSD1_23_P
PCIE_CLK100M_SSD1_23_N

SSD1_CLKREQ3_L
SSD1_S4E3_PCIE_RESREF
PCIE_SSD1_R2D_P<3>

118

118

PCIE_SSD1_R2D_N<3>

118

PCIE_SSD1_D2R_C_P<3>

118

PCIE_SSD1_D2R_C_N<3>

91

91

D

124 119 92 91 90 89 88

90

IN

90 41

90 41

47 41

0.22UF

0.22UF

0.22UF

0.22UF

020110%X5R-CERM6.3V

PCIE_SSD1_R2D_C_P<3>

PCIE_SSD1_R2D_C_N<3>

PCIE_SSD1_D2R_P<3>

PCIE_SSD1_D2R_N<3>

IN

IN

OUT

OUT

S4E_L8

1

118 41

118 41

118 41

118 41

R9404

3.01K

1%
1/20W
MF
201

2

C

S4E_L8

S4E_L8

S4E_L8

S4E_L8

IN
IN

OUT

C9403
C9404

GND_VOID=TRUE

C9401

GND_VOID=TRUE GND_VOID=TRUE

6.3V 020110%X5R-CERM

C9402

GND_VOID=TRUE

2 1

6.3V X5R-CERM 10% 0201

GND_VOID=TRUEGND_VOID=TRUE

2 1

GND_VOID=TRUE

6.3V 10%
X5R-CERM

2 1

2 1

GND_VOID=TRUE

0201

119 92 91 90 89 88

124

B

PP1V8_SSD1

S4E_L8

1

R9402

47K

1%
1/20W
MF
201

2

S4E_L8

1

R9408

100K

1%
1/20W
MF
201

2

92 90 89 88 47

S4E_L8

1

R9409

100K

1%
1/20W
MF

2

201

SSD1_S4E3_SWD_UID0

SSD1_S4E3_SWD_UID1

DROOP_N

91

SSD1_S4E3_DROOP_L

IN

SSD1_OCARINA_WP_L

91

91

T3

G2

WP_N

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

P7P3P1

P11

N10

N4

M7M5M1

M13

L10

K7K5K1

K13

VSS

J10

H13

H9H5H3

H11

H1

F13

F9F7F5

F11

F1

D13

D11D1C12

C2

B13B1A12

A8A6A4

A10

RESET*

TRST*

ZQ_C
ZQ_N

A2

L4
G10
K3

C10

SSD1_OCARINA_RESET_L

SSD1_S4E_JTAG_TRST_L

SSD1_S4E3_ZQ_C
SSD1_S4E3_ZQ_L

S4E_L8

1

R9405

300

1%
1/20W
MF
201

2

S4E_L8

1

R9406

100

1%
1/20W
MF
201

2

IN

90 89 88

92 90 89 88

B

A

SSD1_S4E3_DROOP_L

91

124 119 92 91 90 89 88

S4E VDD

PP0V9_SSD1

S4E_L8

1

C9410

10UF

20%

2

6.3V
CERM-X6S
0402

CRITICAL

PP2V5_NAND_SSD1

1

2

S4E_L8

1

C9411

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L8

1

C9412

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L8

C9413

1

0.1UF

10%
16V

2

X5R-CERM
0201

VCC CAP

S4E_L8

C9448

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

S4E_L8

1

C9449

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L8

1

C9450

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E_L8 S4E_L8

C9414

1

0.1UF

10%
16V

2

X5R-CERM
0201

S4E_L8

1

C9451

2.2UF

20%

2

6.3V
X5R-CERM
0201

C9415

1

0.1UF

10%
16V

2

X5R-CERM
0201

S4E_L8

1

C9452

2.2UF

20%

2

6.3V
X5R-CERM
0201

S4E VDDIO

124 119 92 91 90 89 88

124 119 92 91 90 89 88 91

124 119 92 91 90 89 88

PP1V8_SSD1

PP1V8_SSD1

CRITICAL

R9401

1

2

R9400

0

5%

1/20W

MF

0201

S4E_L8

C9432

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

0

5%

21

1/20W

MF

0201

21

S4E_L8

S4E_L8

C9436

4.3UF

1

4V

432

CERM

20%

0402-THICKSTNCL

1

C9437

2.2UF

20%

2

6.3V
X5R-CERM
0201

PP1V8_SSD1_S4E3_PCI_AVDD_H

S4E_L8

C9444

1

1.0UF

20%
10V

2

X5R-CERM
0201-1

PP1V8_SSD1_S4E3_AVDD18_PLL

S4E_L8

C9446

1

1.0UF

20%
10V

2

X5R-CERM
0201-1

S4E_L8

C9445

1

0.1UF

10%
16V
X5R-CERM

2

0201

S4E_L8

C9447

1

0.1UF

10%
16V

2

X5R-CERM
0201

91

BOM_COST_GROUP=SDD

PAGE TITLE

SSD1 S4E 3

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

94 OF 200

SHEET

91 OF 131

A

SIZE

D

8

67

35 4

2

1

D

C

B

116

PPBUS_G3H_SSD1_SNS

OCARINA_2

C9573

1

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

SSD1_VR_P2V5_EN

92

OCARINA_2

C9574

1

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

OCARINA_2

C9580

1

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

OCARINA_2

R9598

0

5%
1/20W
MF

0201

OCARINA_2

C9581

1

10UF

20%
25V

2

X5R-CERM
0603

SSD1_VR_P2V5_EN_R

92

SSD1_TPS62180_SS

1

2

21

SSD1_VR_P2V5_EN_R

92 116

CRITICAL

OCARINA_2

C9582

1000PF

10%
25V
X7R
0201

P2V5_SSD1_AGND

92

92

PP3V3_G3H_SSD1_SNS

92 116

PP3V3_G3H_SSD1_SNS

PLACE_NEAR=U9580.C4:5MM

OCARINA_2

1

R9510

100K

1%
1/20W
MF
201

2

678

OCARINA_2

U9580

TPS62180

A1

VIN1

B1

VIN1

C1

VIN1

D1

VIN2

E1

VIN2

F1

VIN2

E4

EN VO

D4

SS/TR

C4

PLACE C2000-C2002 NEAR OCARINA PINS E7/E8
PLACE C2003-C2005 NEAR OCARINA PINS A7/A8
PLACE C2006 NEAR OCARINA PIN B4

OCARINA_2

1

C9500

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

2

OCARINA_2

R9511

100K

1%
1/20W
MF
201

OCARINA_2

1

C9501

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

This sets the addres to 0xF0 for STG1

119 87 47 38

1

2

92

OCARINA_2

1

R9512

0

5%
1/20W
MF
201

2

BGA

CRITICAL

AGND

PGND

PGND

PGND

PGND

PGND

F3

C3

D3

E3

21

A3

B3

SM

XW9500

OCARINA_2

C9502

0.1UF

20%
16V
X6S-CERM
0201

91 90 89 88

91 90 89 88

SSD_PMU_RESET_L
SSD1_VR_P2V5_PGOOD

SSD1_OCARINA_POK2

91 90 89 88

NO_TEST=1

91 90 89 88 47

OCARINA_2

1

C9503

4.7UF

20%

6.3V

2

X6S
0402

CRITICAL

SSD1_OCARINA_FORCE_EN
I2C_SSD1_SCL

51

I2C_SSD1_SDA

51

SSD1_OCARINA_LPB_L
SSD1_OCARINA_PFN
SSD1_OCARINA_PGOOD

SSD1_OCARINA_RESET_L

119
93
77

PMU_SYS_ALIVE

38
39
87

92

SSD1_VR_P2V5_EN

NC_SSD1_OCARINA_VEN2

SSD1_OCARINA_WP_L

SW1
SW1
SW1

SW2
SW2
SW2

PGND

92

PG

FB

A2
B2
C2

D2
E2
F2

A4
F4
B4

1

2

CRITICAL

P2V5_SW1_TPS62180_SSD1

DIDT=TRUE

SWITCH_NODE=TRUE

P2V5_SW2_TPS62180_SSD1

SSD1_VR_P2V5_PGOOD
SSD1_TPS62180_FB

OCARINA_2

C9504

4.7UF

20%

6.3V
X6S
0402

DIDT=TRUE

SWITCH_NODE=TRUE

OCARINA_2

1

C9505

0.1UF

20%
16V

2

X6S-CERM
0201

CRITICAL

CAPDERATE

OCARINA_2

1

2

CRITICAL

F3

ATM

D2

ADDR

E1

FORCE_EN

G2

I2C_SCL

G3

I2C_SDA

F4

LPBN

G5

PFN*

G6

PGOOD

D1

PMIC_RESET*

D3

POK1

F1

POK2

E5

RESET*

F2

SYS_ALIVE

F5

VEN1

E4

VEN2

G4

WP*

OCARINA_2

1

R9588

2

OCARINA I2C BASE ADDRESS

C9506

150UF

20%

6.3V
TANT-POLY
CASE-B3

OCARINA_2

1UH-20%-3.8A-0.035OHM

1UH-20%-3.8A-0.035OHM

L9580

PIFE32251B-SM

OCARINA_2CRITICAL

L9581

PIFE32251B-SM

21

VOLTAGE=2.5V

21

PP2V5_NAND_SSD1

100K

1%
1/20W
MF
201

STG0: F2
STG1: F0

A8

E7

E8

VDD_BUCK0

VDD_BUCK0

A7

VDD_BUCK1

VDD_BUCK1

OMIT_TABLE

P2V5_SSD1_AGND

92

B4

B5

G1

VCC_DET

VDD_LDO

VDD_MAIN

U9500

D2499A0

WLCSP

CRITICAL

OCARINA_2

1

R9583

10.2

1%
1/20W
MF
201

SSD1_TPS62180_FB_R

OCARINA_2

C9585

1

22PF

2%
50V

2

C0G-CERM
0201

124 119 92 91 90 89 88

OMIT_TABLE

2

OCARINA_2

1

R9580

475K

1%
1/20W
MF

2

201

1

R9581

200K

0.1%
1/20W
TF
0201

2

R2081:200K->2.7V, 221K->2.519V NAND VCC

SSD1_OCARINA_NAND_VCC_DET

PP1V8_SSD1

OCARINA_2

C1

V_BUF_1.8V

VR1_DISCHG
VR2_DISCHG

BUCK0_FB_DIS
BUCK1_FB_DIS

BUCK0_LX0
BUCK0_LX0

BUCK0_LX1
BUCK0_LX1

BUCK1_LX0
BUCK1_LX0

TCAL

VREF

IREF

TDEV1
TDEV2

A4
B3

B2
B1

C2

A3
A1

D5
C5

F8
F7

D8
D7

B8
B7

C9509

1

0.1UF

10%16V

2

X5R-CERM
0201

SSD1_OCARINA_TCAL
SSD1_OCARINA_VREF

SSD1_OCARINA_IREF
SSD1_OCARINA_TDEV1

PP2V5_NAND_SSD1
NC_SSD1_OCARINA_VR2_DIS

PP0V9_SSD1_FB_DIS
PP1V8_SSD1_FB_DIS

P0V9_LX0_SSD1

P0V9_LX1_SSD1

P1V8_LX0_SSD1

OCARINA_2

1

C9586

20UF

20%
10V

2

X5R
0402

CRITICAL

OCARINA_2

1

C9587

20UF

20%
10V

2

X5R
0402

CRITICAL

OCARINA_2

1

C9588

20UF

20%
10V

2

X5R
0402

CRITICAL

SSD1_OCARINA_VDD_LDO

OCARINA_2

1

TPA9500

1

124 119 92 91 90 89 88

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

TP-P6

92

92

A

NO_TEST=1

C9507

0.22UF

20%

2

6.3V
X6S-CERM
0201

OCARINA_2

OCARINA_2

OCARINA_2

3 245

OCARINA_2

1

C9589

20UF

20%
10V

2

X5R
0402

CRITICAL

L9521

CRITICAL

0.47UH-20%-5.1A-0.03OHM

L9520

0.47UH-20%-5.1A-0.03OHM

L9530

1

2

124 119 92 91 90 89 88

OCARINA_2

C9590

20UF

20%
10V
X5R
0402

CRITICAL

118S0738 SSD1_NAND_VCC:2.7V

103S00049 SSD1_NAND_VCC:2.5V

1

2

SSD1_OCARINA_TDEV1

1

OCARINA_2
I26

R9502

100KOHM

0201

2

CRITICAL

PIFE32251B-SM

PIFE32251B-SM

PIFE32251B-SM

CRITICAL

OCARINA_2

C9591

20UF

20%
10V
X5R
0402

CRITICAL

1

RES,THICKFILM,200KOHM,0.1%,1/20W,0201

1

RES,THICKFILM,221KOHM,0.1%,1/20W,0201

21

21

21

1UH-20%-3.8A-0.035OHM

CRITICAL

1

2

1

2

CRITICAL

OCARINA_2

1

R9501

18.2K

0.1%
1/20W
TK

2

0201

OCARINA_2

1

R9505

200K

0.1%
1/20W
TF
0201

2

1

2

CRITICAL

OCARINA_2

C9530

20UF

20%
10V
X5R
0402

CRITICAL

PP2V5_NAND_SSD1

OCARINA_2

C9592

20UF

20%
10V
X5R
0402

OCARINA_2

C9520

20UF

20%
10V
X5R
0402

OCARINA_2

1

C9531

20UF

20%
10V
X5R

2

0402

CRITICAL

OCARINA_2

1

C9593

20UF

20%
10V

2

X5R
0402

CRITICAL

92

OCARINA_2

1

C9508

0.1UF

20%
16V

2

X6S-CERM
0201

OCARINA_2

1

C9521

20UF

20%
10V
X5R

2

0402

CRITICAL

1

2

CRITICAL

SSD1_OCARINA_TDEV2

1

2

OCARINA_2

C9532

20UF

20%
10V
X5R
0402

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

OCARINA_2
I22

R9504

100KOHM

0201

CRITICAL

OCARINA_2

1

R9500

8.06K

0.1%
1/20W
TK

2

0201

OCARINA_2

1

C9522

20UF

20%
10V
X5R

2

0402

CRITICAL

1

2

R9581
R9581

1

2

OCARINA_2

C9533

20UF

20%
10V
X5R
0402

CRITICAL

124 119 92 91 90 89 88

OCARINA_2

1

R9503

18.2K

0.1%
1/20W
TK

2

0201

OCARINA_2

C9523

20UF

20%
10V
X5R
0402

CRITICAL

OCARINA_2

1

C9534

20UF

20%
10V
X5R

2

0402

CRITICAL

CRITICAL
CRITICAL

OCARINA_2

R9520

0

1

5%

1/20W

MF

0201

OCARINA_2

1

C9524

20UF

20%
10V
X5R

2

0402

CRITICAL

PP1V8_SSD1

OCARINA_2

1

C9535

20UF

20%
10V
X5R

2

0402

CRITICAL

BOM OPTIONCRITICAL

92

PP0V9_SSD1

2

OCARINA_2

R9530

PP0V9_SSD1

OCARINA_2

1

C9525

20UF

20%
10V
X5R

2

0402

CRITICAL

0

5%

1/20W

MF

0201

1

D

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

C

124 119 92 91 90 89 88

PP1V8_SSD1SSD1_OCARINA_TDEV2

21

124

119 92 91 90 89 88

B

124 119 92 91 90 89 88

124 119 92 91 90 89 88

A

A6

VSS

A5

VSS

B6

VSS

A2

VSS

C3

VSS

C4

VSS

D6

VSS

D4

VSS

E6

VSS

E2

VSS

F6

VSS

E3

VSS(VSS_BUCK0)

VSS(VSS_BUCK0)

VSS

G7

G8

VSS(VSS_BUCK01)

VSS(VSS_BUCK01)

VSS(VSS_BUCK01)

C6

C7

C8

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

IV ALL RIGHTS RESERVED

SSD1 PMIC & VR

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

95 OF 200

SHEET

92 OF 131

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

80 93 124

80 93

PP3V3_S5

PP1V8_S5

80 93

PP1V8_S5

R9802

21

MF-LF 5%01/16W 402

R9803

21

402 MF-LF05% 1/16W

39

OUT

51

51

IN
BI

119 93

GMUX GPIO Expander

PP3V3_S5_GPIOX_R

PP1V8_S5_GPIOX_R

DISP_GCON_INT_L

I2C_DISP_SCL
I2C_DISP_SDA
DISP_GCON_RESET_L

NOSTUFF

1

R9804

10K

5%
1/20W
MF
201

2

GMUX_IOEXP_ADDR_SEL

1

R9805

0

5%
1/20W
MF
0201

2

VOLTAGE=3.3V

VOLTAGE=1.8V

NOSTUFF

1

R9801

10K

5%
1/20W
MF
201

2

1

C9801

0.1UF

2

NC
NC
NC
NC

10%

6.3V

CERM-X5R
0201

C4
A5
A3

A2
B4

B2
B3
C2
C3

INT*
ADDR
SCL

SDA
RESET*

NC

A4

A1

VDD(P)

VDD(I2C-BUS)

U9801

PCAL6524

VFBGA

I2C Addr:
Read: 45h
Write: 44h

VSS

A6

P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7

P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7

P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7

B1
D4
C1
D2
D1
E1
D3
F1

E2
F2
E3
F3
F4
E4
F5
E5

F6
E6
D5
D6
C5
C6
B5
B6

1

C9802

0.1UF

10%

6.3V

2

CERM-X5R
0201

EG_VR0_PGOOD
P1V8GPU_PGOOD
PVDDCI_PGOOD
GPUVCORE_PGOOD
GPUFB_PGOOD

DP_INT_HPD_R

USBC_HPD_DET

TP_BKLT_FAULT_L

DP_INT_EG_HPD

DP_INT_IG_HPD

EDP_MUXSEL_OVR

EDP_IG_PANEL_PWR
EDP_IG_BKLT_EN

EG_LCD_PWR_EN
EG_BKLT_EN

TP_BKLT_BOOST_EN

EG_VR0_EN
EG_VR1_EN
EG_VR2_EN
EG_VR3_EN
EG_VR4_EN

EG_RESET_L_BUFF

EDP_PANEL_PWR_EN
EDP_BKLT_EN

PP3V3_S5

80 93 124

1

2

C9860

0.1UF

10%

6.3V

CERM-X5R
0201

93

93

93

93

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

DP 2:1 ANALOG MUX

PP3V3_S5

80 93 124

C9850

1

0.1UF

20%

10V

2

X7R-CERM

J4

A2

118 103

118 103

118 103

118

118 103

118 103

118 103

118 103 120 82

118 103

118 103

IN
IN

IN

103

IN

IN
IN

IN
IN OUT

BI
BI

R9850

IN
IN
IN
IN
IN

95 93

95

95

95

93 19

LAST RAIL PGOOD HAS TO BE VR4_PGOOD

95

103 93

DP_INT_EG_HPD

402 MF-LF

R9806

200

103 93

93 15

15

IN

15

IN

103

IN

103

IN

95 93

95 93

95 93

95 93

93 82

93 81

1/16W
MF-LF

120 82

1%

402

93 15

21

DP_INT_HPD

OUT

IN

R9807

DP_INT_IG_HPD

LCD_FSS

100K

5%

1/20W

MF

201

82

120 93

4.7K

2.26K

1

PP3V3_S5

80 93 124

2

4.7K

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

R9851
R9819

MF-LF402 1% 1/16W

21

1% 1/16W

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

21

1/16W1%402 MF-LF

21

1

R9852

100K

5%
1/20W
MF
201

2

DP_INT_EG_ML_P<0>
DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<2>
DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<3>
DP_INT_EG_ML_N<3>

DP_INT_EG_AUX_P
DP_INT_EG_AUX_N

NC
NC

DP_INT_EG_HPD_R

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_N<0>

DP_INT_IG_ML_P<1>
DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<2>
DP_INT_IG_ML_N<2>

DP_INT_IG_ML_P<3>
DP_INT_IG_ML_N<3>

DP_INT_IG_AUX_P
DP_INT_IG_AUX_N

NC
NC

DP_INT_IG_HPD_R

EDP_MUXSEL_OVR
LCD_MUX_EN

B4
A4

B5
A5

B6
A6

A8
A9

H9

J9

H8

J8
J2

B8
B9

D8
D9

E8
E9

F8
F9

H6

J6

H5

J5

H3

A1
B7

DIN1_0+
DIN1_0-

DIN1_1+
DIN1_1-

DIN1_2+
DIN1_2-

DIN1_3+
DIN1_3-

DAUX1+
DAUX1-

DDC_CLK1
DDC_DAT1

HPD_1

DIN2_0+
DIN2_0-

DIN2_1+
DIN2_1-

DIN2_2+
DIN2_2-

DIN2_3+
DIN2_3-

DAUX2+
DAUX2-

DDC_CLK2
DDC_DAT2

HPD_2

GPU_SEL
XSD*

VDD

VDD

U9850

CBTL06142EEE

TFBGA

CRITICAL

DDC_AUX_SEL

GND

H4

GND

GND

H7

B3

GND

C8

GND

G8

DOUT_0+

DOUT_0-

DOUT_1+

DOUT_1-

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

AUX+

AUX-

HPDIN

GND

G2

MUXSEL is default low.
EG is the default option

B2
B1

D2
D1

E2
E1

F2
F1

H2
H1

J1

C2

0402

EDP_INT_ML_P<0>
EDP_INT_ML_N<0>

EDP_INT_ML_P<1>
EDP_INT_ML_N<1>

EDP_INT_ML_P<2>
EDP_INT_ML_N<2>

EDP_INT_ML_P<3>
EDP_INT_ML_N<3>

EDP_INT_AUX_P
EDP_INT_AUX_N

DP_INT_HPD

Pull down on eDP connector page

C9851

1

0.1UF

20%

10V

2

X7R-CERM
0402

OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

D

120 82

120 82

120 82

120 82

120 82

120 82

120 82

120 82

120 82

C

IN

120 93 82

B

A

R9820
R9821
R9822
R9823
R9824
R9825
R9826
R9827
R9828
R9830
R9832
R9833

47K
47K
47K
47K

47K
100K
100K
100K
100K
100K

47K

47K

21

21

21

21

21

21

1/20W MF 201 5%

21

1/20W 5%201MF

21

1/20W MF 201 5%

21

1/20W MF 201 5%

21

1/20W MF 201 5%

21

21

201

201

201

201

201

MF 5%1/20W

MF 5%1/20W

201

MF1/20W

U9860

74LVC1G11GW-S500

5

93

95 93

20

IN

5%MF1/20W

5%MF1/20W

5%MF1/20W

5%MF1/20W

EG_VR0_EN
EG_VR1_EN
EG_VR2_EN
EG_VR3_EN
EG_VR4_EN

DP_INT_EG_HPD
DP_X_SNK0_HPD_EG
DP_X_SNK1_HPD_EG
DP_T_SNK0_HPD_EG
DP_T_SNK1_HPD_EG

EDP_PANEL_PWR_EN
EDP_BKLT_EN

5%201

93

95 93

95 93

95 93

95 93

103 93

103 93

103 93

103 93

103 93

93 82

93 81

27

27

105

105

95 93 19

IN
IN

IN
IN

IN

DP_X_SNK0_HPD
DP_X_SNK1_HPD

DP_T_SNK0_HPD
DP_T_SNK1_HPD

GPUFB_PGOOD

EG_RESET_L_BUFF

EG_VR0_PGOOD

PLT3V3_RST_L

PP3V3_S5

80 93 124

1

C9840

0.1UF

10%

6.3V

2

CERM-X5R
0201

HPD_X_SNK0
HPD_X_SNK1

HPD_T_SNK0
HPD_T_SNK1

GPU_RESET_L HPD_DET_ANY

1

A

3

B

6

C

1

VDD

U9840

SLG4AP41422

STQFN

GND

7

SOT363

VCC

4

Y

GND

2

HPD_X_SNK0_ISO
HPD_X_SNK1_ISO

HPD_T_SNK0_ISO
HPD_T_SNK1_ISO

GPU_RESET_L

1

R9860

100K

5%
1/20W
MF
201

2

122

DP_X_SNK0_HPD_EG

113

DP_X_SNK1_HPD_EG

104

DP_T_SNK0_HPD_EG

95

DP_T_SNK1_HPD_EG

86

USBC_HPD_DET

OUT

117

93

OUT
OUT

OUT
OUT

PP1V8_S5

80 93

103 93

103 93

103 93

103 93

1

R9810

100K

5%
1/20W
MF
201

2

119 92 87 77 39 38

C9810

1

0.1UF

10%

2

6.3V

CERM-X5R
0201

P1V8S5_VALID

IN

PMU_SYS_ALIVE

SOT353

74LVC1G08GW

BOM_COST_GROUP=GRAPHICS

1

B

U9810

2

A

B

5

R9812

4

Y

3

DISP_GCON_RESET_L_R

1

R9811

0

NOSTUFF

5%
1/16W
MF-LF
402

2

SYNC_MASTER=SEAN

PAGE TITLE

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

0

21

DISP_GCON_RESET_L

5%
1/16W
MF-LF

402

EDP Mux

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

98 OF 200

SHEET

93 OF 131

119 93

SYNC_DATE=05/01/2017

SIZE

D

A

8

67

35 4

2

1

678

3 245

1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

D

C

101 98

101 98

101 98

101

101

98

NO_XNET_CONNECTION=1

IN

IN

IN

IN

IN

IN

GFXIMVP_ISNS1_N

NO_XNET_CONNECTION=1

GFXIMVP_ISNS2_N

NO_XNET_CONNECTION=1

GFXIMVP_ISNS3_N

GFXIMVP_ISNS1_P

GFXIMVP_ISNS2_P

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

GFXIMVP_ISNS3_P

104 95 94

NO_XNET_CONNECTION=1

R9943

2.43K

R9944

2.43K

R9945

2.43K

PP5V_S0_GPUFET

R9940

2.43K

0.1%

1/20W

0201

R9941

2.43K

0.1%

1/20W

0201

R9942

2.43K

1/20W

0.1%

1/20W

TK

0201

0.1%

1/20W

TK

0201

0.1%

1/20W

TK

0201

TK

TK

21

21

21

02010.1%
TK

21

21

21

GFXIMVP_ISNS_R_N

GFXIMVP_ISNS_R_P

R9900

1

21

5%
1/16W
MF-LF

402

R9946

3.09K

R9947

3.09K

1

C9900

10UF

20%

2

10V
X6S-CERM
0603

21

0.1%

1/20W

TK

0201

NO_XNET_CONNECTION=1

0.1%

1/20W

TK

0201

PLACE_NEAR=U9900.3:2.54MM

PLACE_NEAR=U9900.1:2.54MM

21

High Speed Summing AMP

1

C9901

0.1UF

10%

2

6.3V
X6S
0201

GFXIMVP_ISNS_N

NOSTUFF

GFXIMVP_ISNS_P

1

C9902

2

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

PP5V_S0_PCCAMP

0.01UF

10%
10V
X7R-CERM
0201

604K

0.1%

1/20W

TK

0201

1

2

R9903

R9904

604K

2 1

0.1%

1/20W

TK

NO_XNET_CONNECTION=1

0201

3

1

GPUVR_ISUM_IOUT

U9900

6

LMV693

UQFN

4

SD*

2

5

R9905

0

5%1/20W

NOSTUFF

21

GPUVR_ISUM_IOUT_R

0201 MF

1

2

C9903

0.1UF

10%

6.3V
X6S
0201

TP-P6

1

A

TP9900

R9906

GPU_VCORE_IOUT_REF_R

VCC+

GND

A

5

2

TP9901

3

1

TP-P6

1

1

PCC:YES

1M

21

1/20W

PLACE_NEAR=U9901.5:2.54MM

PP5V_S0_GPUFET

PCC:YES

1%

PCC:YES

C9904

1

0.1UF

10%

6.3V

2

X6S
0201

MF201

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

104 95 94

U9901

LMV331

SC70-5

GPUVDDC_PCC_ALERT_R_L GPUVDDC_PCC_ALERT_L

4

Comparator

R9907

1/20W

PCC:YES

0

5%

21

0201

R9961

R9960

10K

21

0.1%

1/20W

MF

0201-1

PLACE_NEAR=U7800.A14:5MM

PP3V3_S0_GPU

ALWAYS STUFF ME

NOSTUFF

1

C9905

0.22UF

20%

6.3V

2

X6S-CERM
0201

MF

1

R9908

10K

5%
1/20W
MF
201

2

R9961

5.49K

LOADRC:YES

LOADRC:NO117S0008

PLACE_NEAR=U7800.A14:5MM

PMU_GPU_CORE_ISENSE

PLACE_NEAR=U7800.A14:5MM

0.1%

1/20W

TK

0201

1

2

1

C9960

2.2UF

20%

2

6.3V

X5R-CERM
0201

OUT

59

GND_CALPE_AVSS

IG0C to Calpe

94 115

PCC flag to GPU

OUT

Active LOW

TP-P6

1

A

TP9902

103 94

D

121 76 58 55 54 53

C

B

104 95 94

Trip Point Voltage Gen

PCC:YES

PCC:YES

R9909

PP5V_S0_GPUFET PP3V3_VREF_PCC

2.2

5%

1/20W

MF

201

VOLTAGE=5V VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

21

PP5V_VREF_PCC

PCC:YES

1

C9906

1UF

20%

6.3V

2

X6S-CERM
0201

U9902

SC4437

SOT23-3

IN OUT

GND

3

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

21

PCC:YES

1

C9907

1UF

20%

6.3V

2

X6S-CERM
0201

R9910

1/20W

PCC:YES

1K

0.1%

R9911

PCC:YES

21

0201

R9912

11.8K

10K

0.1%

1/20W

0201-1

TK

0.1%

1/20W

0201

PCC:YES

1

MF

2

GPU_VCORE_IOUT_REF

1

TK

2

B

A

103 94

PP3V3_S0_GPU

94 115

1

R9913

0

5%
1/20W
MF
0201

2

PCC:YESPCC:YES PCC:YES

1

R9914

0

5%
1/20W
MF
0201

2

PCC:YES

A2

VCC

U9903

PCC_CLR_L

PCC:YES

1

C9908

0.1UF

10%

2

6.3V
X6S
0201

SN74LVC1G123

A1

A*

B1

B

C1 C2

CLR*

BGA

REXT_CEXT

GND

D1

Q

CEXT

1

C9909

2

D2
B2

PCC:YES

0.1UF

10%

6.3V
X6S
0201

PCC_CEXTPCC_B

1

2

200K

1%

1/20W

MF

201

1

2

1

2

PCC:YES

PCC:YES

C9910

1UF

20%

6.3V

X6S-CERM
0201

PCC:YES

5

U9904

74LVC1G17DRL

SOT-553

2

NC

1 3

NC

4

R9915

PCC_EVENT_3V3GPUVDDC_PCC_ALERT_L

PP1V8_S5

C9911

0.1UF

10%

6.3V
X6S
0201

80

R9916

1/20W 5%

PCC:YES

33

21

201

MF

1

PCC:NO

1

R9917

100K

5%
1/20W
MF
201

2

TP-P6

PCC_EVENTPCC_EVENT_R

A

TP9903

PCC flag to H9M

39

OUT

to H9M

Active HIGH

PAGE TITLE

SYNC_DATE=11/09/2017SYNC_MASTER=SEAN

A

8

GPU PCC

Pulse Stretcher

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

BOM_COST_GROUP=GRAPHICS

67

35 4

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

99 OF 200

SHEET

94 OF 131

1

SIZE

D

678

3 245

1

D

C

93

EG_VR0_EN

EG_VR1_EN

93

EG_VR3_EN

93

93

EG_VR4_EN

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

117

117

119 117 46

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

115 103

IN

PEG_GPU_R2D_C_P<0>

PEG_GPU_R2D_C_N<0>

PEG_GPU_R2D_C_P<1>

PEG_GPU_R2D_C_N<1>

PEG_GPU_R2D_C_P<2>

PEG_GPU_R2D_C_N<2>

PEG_GPU_R2D_C_P<3>

PEG_GPU_R2D_C_N<3>

PEG_GPU_R2D_C_P<4>

PEG_GPU_R2D_C_N<4>

PEG_GPU_R2D_C_P<5>

PEG_GPU_R2D_C_N<5>

PEG_GPU_R2D_C_P<6>

PEG_GPU_R2D_C_N<6>

PEG_GPU_R2D_C_P<7>

PEG_GPU_R2D_C_N<7>

EG_PEG_CLK100M_P
EG_PEG_CLK100M_N

PP1V8_S0_GPU

GPU_RESET_L

0

0

0

5%

0

21

0201 MF

21

0201

21

0201 MF

21

0201

RA010

1/20W 5%

RA011

1/20WMF5%

RA012

1/20W

RA014

1/20WMF5%

CA020

GND_VOID=TRUE

CA021

GND_VOID=TRUE

CA022

GND_VOID=TRUE

CA023

GND_VOID=TRUE

CA024

GND_VOID=TRUE

CA025

GND_VOID=TRUE

CA026

GND_VOID=TRUE

CA027

GND_VOID=TRUE

CA028

GND_VOID=TRUE

CA029

GND_VOID=TRUE

CA039

GND_VOID=TRUE

CA047

GND_VOID=TRUE

CA048

GND_VOID=TRUE

CA059

GND_VOID=TRUE

CA060

GND_VOID=TRUE

CA061

GND_VOID=TRUE

1K

1%

1/20W

MF

201

0

1/20W

MF

0201

GPUVCORE_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

0.22UF

21

PLACE_NEAR=UA000.AY13:5MM

21

5%

P1V35FB_EN

RA000

RA002

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

6.3V20% X6S-CERM

21

20%

6.3V X6S-CERM 0201

21

20%

6.3V X6S-CERM 0201

21

20%

6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

0201

GPU_TEST_PG

GPU_RESET_R_L

P3V3GPU_EN

P3V3GPU_EN

MAKE_BASE=TRUE

P1V8GPU_EN

GPUVCORE_EN

P1V35FB_EN

118

118

118

OUT

OUT

OUT

OUT

OUT

PEG_GPU_R2D_P<0>

PEG_GPU_R2D_N<0>

PEG_GPU_R2D_P<1>

PEG_GPU_R2D_N<1>

PEG_GPU_R2D_P<2>

PEG_GPU_R2D_N<2>

PEG_GPU_R2D_P<3>

PEG_GPU_R2D_N<3>

PEG_GPU_R2D_P<4>

PEG_GPU_R2D_N<4>

PEG_GPU_R2D_P<5>

PEG_GPU_R2D_N<5>

PEG_GPU_R2D_P<6>

PEG_GPU_R2D_N<6>

PEG_GPU_R2D_P<7>

PEG_GPU_R2D_N<7>

104

104

104

101

98

BOMOPTION=OMIT_TABLE

AT41

PCIE_RX0+

AT40

PCIE_RX0-

AR41

PCIE_RX1+

AR40

PCIE_RX1-

AP41

PCIE_RX2+

AP40

PCIE_RX2-

AM41

PCIE_RX3+

AM40

PCIE_RX3-

AL41

PCIE_RX4+

AL40

PCIE_RX4-

AK41

PCIE_RX5+

AK40

PCIE_RX5-

AJ41

PCIE_RX6+

AJ40

PCIE_RX6-

AH41

PCIE_RX7+

AH40

PCIE_RX7­PCIE_REFCLK+

AV33

PCIE_REFCLK-

AU33
AY13

TEST_PG

AV41

PERST*

SPARE

DBGLED

QA000

DMN5L06VK-7

SOT563

VER 3

UA000

100-CK4803-ES

BGA

SYM 1 OF 7

NC

D

6

2

G S

NC

1

PCIE_TX0+

PCIE_TX1+

PCIE_TX2+

PCIE_TX3+

PCIE_TX4+

PCIE_TX5+

PCIE_TX6+

PCIE_TX7+

118

118

PCIE_TX0-

118

118

PCIE_TX1-

118

118

PCIE_TX2-

118

118

PCIE_TX3-

118

118

PCIE_TX4-

118

118

PCIE_TX5-

118

PCIE_TX6-

PCIE_TX7-

118

118

118

PEG_GPU_D2R_C_P<0>

AV35

PEG_GPU_D2R_C_N<0>

AU35

PEG_GPU_D2R_C_P<1>

AU38

PEG_GPU_D2R_C_N<1>

AU39

PEG_GPU_D2R_C_P<2>

AR37

PEG_GPU_D2R_C_N<2>

AR38

PEG_GPU_D2R_C_P<3>

AN37

PEG_GPU_D2R_C_N<3>

AN38

PEG_GPU_D2R_C_P<4>

AL37

PEG_GPU_D2R_C_N<4>

AL38

PEG_GPU_D2R_C_P<5>

AJ37

PEG_GPU_D2R_C_N<5>

AJ38

PEG_GPU_D2R_C_P<6>

AG37

PEG_GPU_D2R_C_N<6>

AG38

PEG_GPU_D2R_C_P<7>

AE37

PEG_GPU_D2R_C_N<7>

AE38

CA077

GND_VOID=TRUE

CA062

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CA076

0.22UF

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

0.22UF

0.22UF

CA063

0.22UF

CA064

0.22UF

CA065

0.22UF

21

21

20% 6.3V X6S-CERM 0201

20% 6.3V X6S-CERM 0201

CA066

0.22UF

CA067

0.22UF

CA075

0.22UF

21

CA068

0.22UF

21

CA069

0.22UF

CA070

0.22UF

21

20%6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

CA071

0.22UF

CA072

0.22UF

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

21

20% 6.3V X6S-CERM 0201

CA073

0.22UF

21

20%6.3V X6S-CERM 0201

CA074

0.22UF

21

20%6.3V X6S-CERM 0201

0201X6S-CERM6.3V20%

0201X6S-CERM6.3V20%

21

21

21

21

20%6.3V X6S-CERM 0201

21

20%6.3V X6S-CERM 0201

0201X6S-CERM6.3V20%

0201X6S-CERM6.3V20%

0201X6S-CERM6.3V20%

PEG_GPU_D2R_P<0>

PEG_GPU_D2R_N<0>

PEG_GPU_D2R_P<1>

PEG_GPU_D2R_N<1>

PEG_GPU_D2R_P<2>

PEG_GPU_D2R_N<2>

PEG_GPU_D2R_P<3>

PEG_GPU_D2R_N<3>

PEG_GPU_D2R_P<4>

PEG_GPU_D2R_N<4>

PEG_GPU_D2R_P<5>

PEG_GPU_D2R_N<5>

PEG_GPU_D2R_P<6>

PEG_GPU_D2R_N<6>

PEG_GPU_D2R_P<7>

PEG_GPU_D2R_N<7>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

118 117

118 117

118 117

118 117

D

118 117

118 117

118 117

118 117

118 117

118 117

118 117

C

118 117

118 117

118 117

118 117

118 117

B

A

PP3V3_S0_GPU

115

104 94

PP5V_S0_GPUFET

DBGLED

RA021

21

180K

201

RA015

21

100K

100K

201

RA016

21

RA017

21

100K

201

201

RA018

21

100K

100K

201

RA099

RA019

21

21

100K

201

201

RA022

NOSTUFF

20K

5%

1/20W

MF

201

1

2

DBGLED_GPU

DBGLED

A

DA000

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM

SILK_PART=S0_ON

P5_S0GPU_PGOOD

MAKE_BASE=TRUE

P3V3_S0GPU_PGOOD

MAKE_BASE=TRUE

104 93

101

101

98

P1V8GPU_PGOOD

IN

IN

IN

IN

MAKE_BASE=TRUE

PVDDCI_PGOOD

MAKE_BASE=TRUE

GPUVCORE_PGOOD

MAKE_BASE=TRUE

GPUFB_PGOOD

MAKE_BASE=TRUE

21

330K

201

DBGLED

QA000

DMN5L06VK-7

SOT563

VER 3

5

G S

DBGLED_GPU_D

3

D

4

P1V8GPU_PGOOD
PVDDCI_PGOOD

GPUVCORE_PGOOD

GPUFB_PGOOD

SOT353

OUT

74LVC1G08GW

93

OUT

93

OUT

OUT

95 93 19

RA023

RA020

GPUFB_PGOOD

19 93 95

0

5%

1/20W

MF

0201

21

51

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

OUT

101

1

B

UA090

2

A

1

CA090

0.1UF

10%

6.3V

2

CERM-X5R
0201

5

4

Y

3

EG_VR0_PGOOD

OUT

93

PP3V3_S0SW_TBT_T_SNS

106 107 116 122

28 29 116 122

PP3V3_S0SW_TBT_X_SNS

21

100K

201

RA03121RA033

21

100K

201

100K

100K

201

201

Tieing off Ridge GPIOs
Both SNK0 and SNK1 shown
as always available

TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK
TBT_T_HDMI_DDC_DATA
TBT_T_HDMI_DDC_CLK

PCH pins mirror
TBT_X hookup

PAGE TITLE

BI

IN

BI

IN

120 29

120 29

120 107

120 107

SYNC_DATE=11/09/2017SYNC_MASTER=SEAN

B

A

GPU Baffin PCIe

RA03021RA032

BOM_COST_GROUP=GRAPHICS

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

100 OF 200

SHEET

95 OF 131

SIZE

D

8

67

35 4

2

1

0.24UH-20%-10A-0.012OHM

PP1V8_S0_GPU_LC_IC

LA100

1210

678

PP1V8_S0_GPU

21

115

BOMOPTION=OMIT_TABLE

3 245

1

D

C

B

CA100

1

12PF

5%
25V

2

NP0-C0G
0201

CA10A

1

4.7UF

20%

6.3V

2

X6S
0402

PP3V3_S0_GPU

1

CA104

0.1UF

10%

2

6.3V
X6S
0201

98

119 115 98 96

PP1V5R1V35_S0_GPU_MEM P1V5R1V35_GPU_FB_SNS_P

PPVCORE_S0_GPU

58 96 115
124

58 96 115

PPVDDCI_S0_GPU

124

P1V5R1V35_GPU_FB_SNS_N

OUT

101

OUT

101 98

RA110

10

1%

1/20W

MF

201

RA112

10

1%

1/20W

MF

201

124 96

98 96

101 96

98 96

PVCORE_GPU_FB_SNS_N

OUT

21

RA111

21

RA113

PP1V8_S0_GPU_LC_IC

PP3V3_S0_GPU

96 115

P1V5R1V35_GPU_FB_SNS_P

OUT

PVCORE_GPU_FB_SNS_P

OUT

PVDDCI_GPU_FB_SNS_P

OUT

PVDDCI_GPU_FB_SNS_N

NO_XNET_CONNECTION=1

10

1%

1/20W

MF

201

10

1%

1/20W

MF

201

CA101

1

12PF

5%
25V

2

NP0-C0G
0201

CA10B

1

4.7UF

20%

6.3V

2

X6S
0402

VOLTAGE=1.8V

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

PVCORE_GPU_FB_SNS_P

21

NO_XNET_CONNECTION=1

PVDDCI_GPU_FB_SNS_P

NO_XNET_CONNECTION=1

21

NO_XNET_CONNECTION=1

CA102

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA10C

1

10UF

20%
4V

2

X6S-CERM
0402-2

96 115

SM

21

XWA100

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

CA103

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA10D

1

10UF

20%
4V

2

X6S-CERM
0402-2

21

PP1V5R1V35_S0_GPU_IC

CA105

1

0.1UF

10%

6.3V

2

X6S
0201

CA106

1

0.1UF

10%

6.3V

2

X6S
0201

CA107

1

0.1UF

10%

6.3V

2

X6S
0201

CA108

1

0.1UF

10%

6.3V

2

X6S
0201

CA109

1

0.1UF

10%

6.3V

2

X6S
0201

CA110

1

12PF

5%
25V

2

NP0-C0G

CA111

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
02010201

96 115

XWA101

SHORT-14L-0.1MM-SM

101 96

98 96

CA199

1

2

21

3.0PF

+/-0.1PF
25V
NP0-C0G
0201

96 115

PP1V5R1V35_S0_GPU_IC

PPVDDCI_S0_GPU

GPU_AUX_ZVSS

GPU_FB_SNS_COMMON_NEG

XWA102

96 115

GPU_PCIE_ZVSS

1

RA102

200

1%
1/20W
MF
201 201

2

1

RA100

150

1%
1/20W
MF

2

AC10

AG10

K11
K13
K19
K23
K27
K31

L10

N10

W10

AC32
AG32
AG35

AJ34
AJ32

W32

AL34

AM15

AP15

AR15
AM31

BA12

C3
AR13
AV13
AU13

AU41

VMEMIO

VDD_08

VDD_18

VDD_33

AUX_ZVSS

FB_VMEMIO
FB_VDDC
FB_VDDCI
FB_VSS

PCIE_ZVSS

UA000

100-CK4803-ES

BGA

SYM 5 OF 7

VDDC

VDDC

VDDC

AA13
AA15
AA21
AA23
AA29
AA31
AC13
AC15
AC21
AC23
AC29
AC31
AE13
AE15
AE21
AE23
AE29
AE31
AG13
AG15
AG21
AG23
AG29
AG31
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25

AJ27
AJ29
AL13
AL15
AL17
AL19
AL21
AL23

AL25
AL27
AL29
N13
N15
N21
N23
N29
N31
R13
R15
R21
R23
R29
R31
U13
U15
U21
U23
U29
U31
W13
W15
W21
W23
W29
W31
AJ31
AL31

PPVCORE_S0_GPU

58 96 115 124

96 115

PPVDDCI_S0_GPU

PPVDDCI_S0_GPU

58 96 115 124

PPVCORE_S0_GPU

58 96 115 124

CA11A

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA11B

1

1UF

20%

2

6.3V
X6S-CERM
0201

1

CA125

220UF

3 2

20%
2V
ELEC
SM-COMBO

CA189

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA129

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA136

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA146

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA11C

1

4.7UF

20%

2

6.3V
X6S
0402

CA155

1

1UF

20%

2

6.3V
X6S-CERM
0201

CA160

1

0.1UF

10%

6.3V

2

X6S
0201

CA180

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA130

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA137

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA147

1

20%

2

4V
X6S-CERM
0201

CA11D

1

4.7UF

20%

2

6.3V
X6S
0402

CA156

1

1UF

20%

2

6.3V
X6S-CERM
0201

CA161

1

0.1UF

10%

6.3V

2

X6S
0201

1

CA126

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

CA127

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

CA128

220UF

20%

3 2

2V
ELEC
SM-COMBO SM-COMBO

These caps should be mirrored to CA13X

CA181

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA131

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA138

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA148

1

2.2UF2.2UF

20%

2

4V
X6S-CERM
0201

CA11E

1

10UF

20%

2

4V
X6S-CERM
0402-2

CA157

1

1UF

20%

2

6.3V
X6S-CERM
0201

CA162

1

0.1UF

10%

6.3V

2

X6S
0201

CA182

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA132

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA139

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA150

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA11F

1

10UF

20%

2

4V
X6S-CERM
0402-2

CA158

1

12PF

5%

2

25V
NP0-C0G
0201

CA163

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA183

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA133

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA140

1

2.2UF

20%

2

4V
X6S-CERM
0201

CA151

1

12PF

5%

2

25V
NP0-C0G
0201

CA159

1

3.0PF

+/-0.1PF

2

25V
NP0-C0G
0201

CA164

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA184

1

20UF

20% 20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA134

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA141

1

2.2UF

2

4V
X6S-CERM
0201

CA152

1

3.0PF

+/-0.1PF

2

25V
NP0-C0G
0201

CA165

1

1UF

20%

6.3V

2

X6S-CERM
0201

CA185

1

20UF

2.5V

2

X6S-CERM
0402-1

NOSTUFF

CA135

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA142

1

20%20%

2

4V
X6S-CERM
0201

CA153

1

12PF

5%

2

25V
NP0-C0G
0201 0201

CA166

1

12PF

5%
25V

2

NP0-C0G
0201

1

CA186

2

1

CA177

220UF

3 2

CA143

1

2.2UF2.2UF

20%

2

4V
X6S-CERM
0201

CA154

1

3.0PF

+/-0.1PF

2

25V
NP0-C0G

CA167

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

CA176

220UF

3 2

20UF

20%

2.5V
X6S-CERM
0402-1

20%
2V
ELEC
SM-COMBO

20%
2V
ELEC

CA144

1

2.2UF

20%

2

4V
X6S-CERM
0201

1

CA178

220UF

3 2

20%
2V
ELEC
SM-COMBO

CA145

1

2.2UF

20%

2

4V
X6S-CERM
0201

D

C

B

A

CA112

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

CA117

1

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

CA122

1

10UF

20%

2

10V
X6S-CERM
0603

1

2

CA118

1

2.2UF

20%
4V

2

X6S-CERM
0201

CA113

10UF

20%
4V
X6S-CERM
0402-2

CA119

1

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

CA123

1

10UF

20%

2

10V
X6S-CERM
0603

CA114

1

1000PF

5%

2

25V
CERM
0402

CA120

1

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

CA124

1

10UF

20%

2

10V
X6S-CERM
0603

1

2

CA121

1

12PF

5%
25V

2

NP0-C0G
0201

CA115

1000PF

5%
25V
CERM
0402

CA149

1

12PF

5%
25V

2

NP0-C0G
0201

CA116

1

1000PF

5%

2

25V
CERM
0402

VDDCI

AA11
AE11
L13
L17
L21
L25
L29
N11
U11

PPVDDCI_S0_GPU

58 96 115
124

1

CA168

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

CA169

220UF

20%

3 2

2V
ELEC
SM-COMBO

CA172

1

1000PF

5%

2

25V
CERM
0402

1

CA170

220UF

20%

3 2

2V
ELEC
SM-COMBO

CRITICAL

CA173

1

10UF

20%

2

10V
X6S-CERM
0603

CRITICAL

CA174

1

10UF

20%

2

10V
X6S-CERM
0603

BOM_COST_GROUP=GRAPHICS

1

CA171

220UF

20%

3 2

2V
ELEC
SM-COMBO

SYNC_MASTER=SEAN SYNC_DATE=06/21/2017

PAGE TITLE

1

CA175

220UF

20%

3 2

2V
ELEC
SM-COMBO

GPU Baffin Core/FB Power

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

101 OF 200

SHEET

96 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

C

B

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118 99

BOMOPTION=OMIT_TABLE

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
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BI

FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<2>
FB_A0_DQ<3>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<7>
FB_A0_DQ<8>
FB_A0_DQ<9>
FB_A0_DQ<10>
FB_A0_DQ<11>
FB_A0_DQ<12>
FB_A0_DQ<13>
FB_A0_DQ<14>
FB_A0_DQ<15>
FB_A0_DQ<16>
FB_A0_DQ<17>
FB_A0_DQ<18>
FB_A0_DQ<19>
FB_A0_DQ<20>
FB_A0_DQ<21>
FB_A0_DQ<22>
FB_A0_DQ<23>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<26>
FB_A0_DQ<27>
FB_A0_DQ<28>
FB_A0_DQ<29>
FB_A0_DQ<30>
FB_A0_DQ<31>

FB_A1_DQ<0>
FB_A1_DQ<1>
FB_A1_DQ<2>
FB_A1_DQ<3>
FB_A1_DQ<4>
FB_A1_DQ<5>
FB_A1_DQ<6>
FB_A1_DQ<7>
FB_A1_DQ<8>
FB_A1_DQ<9>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<12>
FB_A1_DQ<13>
FB_A1_DQ<14>
FB_A1_DQ<15>
FB_A1_DQ<16>
FB_A1_DQ<17>
FB_A1_DQ<18>
FB_A1_DQ<19>
FB_A1_DQ<20>
FB_A1_DQ<21>
FB_A1_DQ<22>
FB_A1_DQ<23>
FB_A1_DQ<24>
FB_A1_DQ<25>
FB_A1_DQ<26>
FB_A1_DQ<27>
FB_A1_DQ<28>
FB_A1_DQ<29>
FB_A1_DQ<30>
FB_A1_DQ<31>

L34

DQA0_0 MAA0_0

L37

DQA0_1

L38

DQA0_2

J35

DQA0_3

G37

DQA0_4

E38

DQA0_5

E35

DQA0_6

D35

DQA0_7

H41

DQA0_8

H40

DQA0_9

G41

DQA0_10

G40

DQA0_11

E40

DQA0_12

D41

DQA0_13

D40

DQA0_14

C41

DQA0_15

C40

DQA0_16

B39

DQA0_17

A39

DQA0_18

B38

DQA0_19

B36

DQA0_20

A36

DQA0_21

B35

DQA0_22

A35

DQA0_23

B33

DQA0_24

B32

DQA0_25

A32

DQA0_26

B31

DQA0_27

A30

DQA0_28

B29

DQA0_29

B28

DQA0_30

A28

DQA0_31

B27

DQA1_0

A27

DQA1_1

B26

DQA1_2

A26

DQA1_3

A24

DQA1_4

B23

DQA1_5

A23

DQA1_6

B22

DQA1_7

B20

DQA1_8

A20

DQA1_9

B19

DQA1_10

A19

DQA1_11

B17

DQA1_12

A16

DQA1_13

B16

DQA1_14

A15

DQA1_15
DQA1_16

B15

DQA1_17

A14

DQA1_18

B14

DQA1_19

B13

DQA1_20

A11

DQA1_21

B11

DQA1_22

A10

DQA1_23

B10

DQA1_24

B8

DQA1_25

A7

DQA1_26

B7

DQA1_27

A6

DQA1_28

A4

DQA1_29

B4

DQA1_30

A3

DQA1_31

B3

UA000

100-CK4803-ES

BGA

SYM 3 OF 7

WCKA0_0*

WCKA0_1*

WCKA1_0*

WCKA1_1*

MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7

MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7

WCKA0_0

WCKA0_1

WCKA1_0

WCKA1_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA0
ADBIA1

CLKA0

CLKA0*

CLKA1

CLKA1*

RASA0*
RASA1*

CASA0*
CASA1*

CSA0_0*

CSA1_0*

CKEA0
CKEA1

G25
H25
E27
D27
D29
H27
H23
E23

E15
H15
G13
D13
H11
H13
H17
G17

D33
E33

A34
B34

A22
B21

A8
B9

G38
F41
B37
A31

B24
A18
B12
B6

J38
F40
A38
B30

B25
B18
A12
B5

H21
H19

E31
D31

D7
D9

D21
D19

D23
D17

H31

E7

G21
E19

FB_A0_A<0>
FB_A0_A<1>
FB_A0_A<2>
FB_A0_A<3>
FB_A0_A<4>
FB_A0_A<5>
FB_A0_A<6>
FB_A0_A<7>

FB_A1_A<0>
FB_A1_A<1>
FB_A1_A<2>
FB_A1_A<3>
FB_A1_A<4>
FB_A1_A<5>
FB_A1_A<6>
FB_A1_A<7>

FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>

FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>

FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>

FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>

FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>

FB_A0_ABI_L
FB_A1_ABI_L

FB_A0_CLK_P
FB_A0_CLK_N

FB_A1_CLK_P
FB_A1_CLK_N

FB_A0_RAS_L
FB_A1_RAS_L

FB_A0_CAS_L
FB_A1_CAS_L

FB_A0_CS_L

FB_A1_CS_L

FB_A0_CKE_L
FB_A1_CKE_L

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

118 99

118 99

118 99

118 99

118 99

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118 99

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118 99

118 99

118 99

BI
BI
BI
BI

BI
BI
BI
BI

118 99

118 99

118 99

118 99

118 99

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118 99

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118 99

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118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<12>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<18>
FB_B0_DQ<19>
FB_B0_DQ<20>
FB_B0_DQ<21>
FB_B0_DQ<22>
FB_B0_DQ<23>
FB_B0_DQ<24>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<28>
FB_B0_DQ<29>
FB_B0_DQ<30>
FB_B0_DQ<31>

FB_B1_DQ<0>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<5>
FB_B1_DQ<6>
FB_B1_DQ<7>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<18>
FB_B1_DQ<19>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<22>
FB_B1_DQ<23>
FB_B1_DQ<24>
FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<30>
FB_B1_DQ<31>

BOMOPTION=OMIT_TABLE

C2

DQB0_0

C1

DQB0_1

D2

DQB0_2

D1

DQB0_3

F1

DQB0_4

G2

DQB0_5

G1

DQB0_6

H2

DQB0_7

K2

DQB0_8

K1

DQB0_9

L2

DQB0_10

L1

DQB0_11

N2

DQB0_12

P2

DQB0_13

P1

DQB0_14

R2

DQB0_15

R1

DQB0_16

T2

DQB0_17

T1

DQB0_18

U2

DQB0_19

W1

DQB0_20

W2

DQB0_21

Y1

DQB0_22

Y2

DQB0_23

AB2

DQB0_24

AC1

DQB0_25

AC2

DQB0_26

AD1

DQB0_27

AF1

DQB0_28

AF2

DQB0_29

AG1

DQB0_30

AG2

DQB0_31

AH1

DQB1_0

AH2

DQB1_1

AJ2

DQB1_2

AK1

DQB1_3

AL2

DQB1_4

AM1

DQB1_5

AM2

DQB1_6

AN2

DQB1_7

AR1

DQB1_8

AR2

DQB1_9

AT1

DQB1_10

AT2

DQB1_11

AV2

DQB1_12

AW1

DQB1_13

AW2

DQB1_14

AY3

DQB1_15

BA3

DQB1_16

AY4

DQB1_17

BA4

DQB1_18

AY5

DQB1_19

BA7

DQB1_20

AY7

DQB1_21

AY8

DQB1_22

BA8

DQB1_23

AR4

DQB1_24

AR5

DQB1_25

AU4

DQB1_26

AU7

DQB1_27

AN8

DQB1_28

AV11

DQB1_29

AU11

DQB1_30

AP11

DQB1_31

UA000

100-CK4803-ES

BGA

SYM 4 OF 7

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7

MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7

WCKB0_0

WCKB0_0*

WCKB0_1

WCKB0_1*

WCKB1_0

WCKB1_0*

WCKB1_1

WCKB1_1*

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB0
ADBIB1

CLKB0

CLKB0*

CLKB1

CLKB1*

RASB0*
RASB1*

CASB0*
CASB1*

CSB0_0*

CSB1_0*

CKEB0
CKEB1

R5
R8
N7
N4
L8
N8
U8
U7

AE7
AE8
AG5
AG4
AJ4
AG8
AC8
AC5

H1
J2

AB1
AA2

AP1
AP2

AN4
AN5

F2
M2
V1
AD2

AL1
AU2
BA6
AV7

E2
M1
V2
AE2

AK2
AV1
AY6
AV9

W8
AA8

G4
J4

AL5
AL4

W4
AA4

U4
AC4

G5

AL8

W5
AA7

FB_B0_A<0>
FB_B0_A<1>
FB_B0_A<2>
FB_B0_A<3>
FB_B0_A<4>
FB_B0_A<5>
FB_B0_A<6>
FB_B0_A<7>

FB_B1_A<0>
FB_B1_A<1>
FB_B1_A<2>
FB_B1_A<3>
FB_B1_A<4>
FB_B1_A<5>
FB_B1_A<6>
FB_B1_A<7>

FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>

FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>

FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>

FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>

FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>

FB_B0_ABI_L
FB_B1_ABI_L

FB_B0_CLK_P
FB_B0_CLK_N

FB_B1_CLK_P
FB_B1_CLK_N

FB_B0_RAS_L
FB_B1_RAS_L

FB_B0_CAS_L
FB_B1_CAS_L

FB_B0_CS_L

FB_B1_CS_L

FB_B0_CKE_L
FB_B1_CKE_L

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

118 100

118 100

118 100

118 100

118 100

118 100

118 100

100

118

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

BI
BI
BI
BI

BI
BI
BI
BI

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

118 100

D

C

B

118 100

118 100

A

MVREFDA

FB_A_MVREFD

97 97

FB_A_CALR

1

RA202

120

1%
1/20W
MF
201

NOSTUFF

2

K17

MEM_CALRA

K15

WEA0*
WEA1*

MAA0_8
MAA0_9

MAA1_8
MAA1_9

DRAM_RSTA

G29
D11

D25
H29

D15
E11

L32

NC

NC

PLACE_NEAR=UA000.K15:2.54MM

124 115 97

PP1V5R1V35_S0_GPU_IC

PLACE_NEAR=UA000.K17:2.54MM

PLACE_NEAR=UA000.K17:2.54MM

1

RA204

40.2

1%
1/20W
MF
201

2

NOSTUFF

1

RA206

100

1%
1/20W
MF
201

NOSTUFF

2

note: to be unstuffed after

initial baffin bringup

FB_A_MVREFD

97

PLACE_NEAR=UA000.K17:2.54MM

CA200

1

1UF

20%

2

6.3V
X6S-CERM

NOSTUFF

0201

FB_A0_WE_L
FB_A1_WE_L

FB_A0_A<8>

FB_A1_A<8>

RA291

FB_A_RESET_PIN_L

1

RA290

5.1K

1%
1/20W
MF
201

2

10

1%

1/20W

MF

201

OUT
OUT

OUT

OUT

FB_A_RESET_R_L

21

118 99

118 99

118 99

118 99

RA293

49.9

CA290

1

120PF

10%

2

25V
X7R
0201

1%

1/20W

MF

201

RA200

115 103

21

FB_A_RESET_L

PP3V3_S0_GPU

OUT

99

NOSTUFF

10K

2 1

5%

1/20W

MF

201

RA201

10K

1/20W

5%
MF

201

GPU_TEST_EN

1

2

FB_B_MVREFD

FB_B_CALR

1

RA203

120

1%
1/20W
MF
201

NOSTUFF

2

PLACE_NEAR=UA000.R10:2.54MM

124 115 97

MVREFDB

U10

WEB0*
WEB1*

AE40

TESTEN

MAB0_8
MAB0_9

MAB1_8

MEM_CALRB

R10 AJ8

MAB1_9

DRAM_RSTB

PP1V5R1V35_S0_GPU_IC

1

RA205

PLACE_NEAR=UA000.U10:2.54MM

40.2

1%
1/20W
MF
201

2

NOSTUFF

note: to be unstuffed after

initial baffin bringup

FB_B_MVREFD

PLACE_NEAR=UA000.U10:2.54MM

1

RA207

100

1%
1/20W
MF
201

NOSTUFF

2

PLACE_NEAR=UA000.U10:2.54MM

CA201

1

1UF

20%

2

6.3V
X6S-CERM

NOSTUFF

0201

BOM_COST_GROUP=GRAPHICS

L4
AJ7

R4
L5

AE4

AM11

97

FB_B0_WE_L
FB_B1_WE_L

FB_B0_A<8>

NC

FB_B1_A<8>

NC

FB_B_RESET_PIN_L

1

RA295

5.1K

1%
1/20W
MF
201

2

SYNC_MASTER=SEAN SYNC_DATE=04/19/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

RA296

10

1%

1/20W

MF

201

OUT
OUT

OUT

OUT

FB_B_RESET_R_L

21

1

2

118 100

100

118 100

118 100

RA297

49.9

1%

1/20W

MF

201

CA295

120PF

10%
25V
X7R
0201

GPU Baffin FB

Apple Inc.

21

FB_B_RESET_L

OUT

100

A

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

102 OF 200

SHEET

97 OF 131

SIZE

D

8

67

35 4

2

1

D

C

96

96

101 115

P1V5R1V35_GPU_FB_SNS_P

IN

P1V5R1V35_GPU_FB_SNS_N

IN

CA303

10PF

5%
50V
C0G

0201

PP3V3_S0_GPU

NO_XNET_CONNECTION=1

RA301

1.62K

1/20W

NO_XNET_CONNECTION=1

RA302

1.62K

1%

1/20W

MF

201

1%
MF

201

21

21

NOSTUFF

1

1

2

RA303

4.64K

0.1%

1/20W

MF

0201

RA304

2

1

RA330

10K

5%
1/20W
MF
201

2

NOSTUFF

1

4.64K

0.1%

1/20W

MF

0201

2

FBVDD_ALTVO

CA304

10PF

5%
50V
C0G

0201

1

2

98

CA305

1

0.01UF

10%
10V

2

X7R-CERM
0201

GPUFB_AGND

98

1

RA305

191K

0.1%
1/20W
MF
0201

2

1

RA306

95.3K

0.1%
1/20W
MF
0201

2

1

CA306

22PF

5%
50V
C0G

2

0201

GPUFB_SET_R

1

RA307

16.9K

0.1%
1/20W
MF
0201

2

GPUFB_AGND

678

116

PP5V_G3S

PP5V_S0GPU_P1V35_GPU

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1

CA310

2.2UF

10%

2

16V
X6S-CERM
0603

95

IN

95

OUT

NOSTUFF

RA309

RA308

0

5%

1/20W

MF

0201

VOLTAGE=5V

P1V35FB_EN
GPUFB_SENSE_DIV
GPUFB_SREF
GPUFB_VO

GPUFB_OCSET
GPUFB_PGOOD
GPUFB_RTN_DIV
GPUFB_FSEL
GPUFB_SET0

1

GPUFB_SET1

0

5%

1/20W

MF

201

21

2

98

FBVDD_ALTVO

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

98

CA318

20

1

10UF2.2

20%

2

10V
X6S-CERM
0603

RA310

5%
1/16W
MF-LF

402

1

2

19

PVCCVCC

UA300

ISL95870AH

EN

15 18

FB

10
7

SREF
VO

12

OCSET

11

PGOOD

14

RTN

4

FSEL

13

SET0

8

SET1

9

VID0

6

VID1

5

XWA300

PLACE_NEAR=UA300.3:1mm

UTQFN

CRITICAL

PGNDGND

3

SM

21

BOOT
UGATE
PHASE

LGATE

2

17
16
1

PPBUS_HS_GPU

115

GPUFB_BOOT_RC

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850
DIDT=TRUE

RA311

GPUFB_VBST

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850
DIDT=TRUE

GPUFB_DRVH_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

GPUFB_LL

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850
SWITCH_NODE=TRUE

DIDT=TRUE

GPUFB_DRVL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

0

5%
1/16W
MF-LF

402

1

2

REG_BOOT_GPU_VDDCI_RC

1

CA311

0.1UF

10%

2

16V
X7R-CERM
0402

RA312

2 1

1/16W
MF-LF

GPUFB_DRVH

1

5%

402

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

1

CA320

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

1

6

CRITICAL

1

CA321

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

376S0959

732

POWERPAK-6X3.7

QA300

SIZ710DT

CRITICAL

8

54

3 245

CRITICAL

1

CA322

33UF

20%

2

16V
TANT-POLY
CASE-B3

CAPDERATE

0.68UH-20%-14A

CAPDERATE

CRITICAL

LA300

PILE063T-COMBO

CRITICAL

1

2

121 58

121 58

CA323

33UF

20%
16V
TANT-POLY
CASE-B3

21

PP1V5R1V35_GPU_REG_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=1.35V

OUT

OUT

1

2

GPUFB_CS_P

XWA301

NO_XNET_CONNECTION=1

GPUFB_GPU_OCSET_R

RA315

RA316

4.53K

1/20W

1%
MF

201

21

CA324

2.2UF

20%
25V
X6S-CERM
0402

GPUFB_CS_N

2

SM

1

1

4.53K

1%

1/20W

MF

201

2

CA325

1

2.2UF

20%

2

25V
X6S-CERM
0402

CA319

2200PF

2 1

10%

16V
CERM
0201

CA326

1

1000PF

5%

2

25V
CERM
0402

CRITICAL

RA300

0.002

1%

1/2W

MF

0306

2

NO_XNET_CONNECTION=1

1

21
43

XWA302

SM

GPUFB_GPU_VO_R

NO_XNET_CONNECTION=1

VID1 VID0 FBVDD

1

GPU FB SUPPLY
VOUT = 1.5V / 1.35V

10.7A MAX OUTPUT
F = 500 KHZ

PP1V5R1V35_S0_GPU_MEM

20%

2V

ELEC

1

1

32

32

CA330

220UF

20%

ELEC

SM-COMBO

20%

2V

ELEC

1

CA332

220UF

SM-COMBO

2V

1

32

32

CA331

220UF

SM-COMBO

CA333

220UF

20%

2V

ELEC

SM-COMBO

0 0 1.5V
1 0 1.35V

CA334

1000PF

5%

25V
CERM
0402

CA335

220UF

20%

2V

ELEC

SM-COMBO

D

115
122

1

2

1

32

C

B

A

101

101 96

101 116

PP5V_G3S

IN

GFXIMVP_PWM3

96

PVDDCI_GPU_FB_SNS_P

IN

PVDDCI_GPU_FB_SNS_N

IN

101

101

RA344

1/16W
MF-LF

402

REG_GPU_VDDCI_VSEN

OUT

OUT

101

OUT

1

0

5%

2

NO_XNET_CONNECTION=1

REG_GPU_VDDCI_FB

REG_GPU_VDDCI_COMP

1

CA344

1UF

10%

2

10V
CER-X6S
0402

3

PWM

7

FCCM UGATE

UA340

ISL6208F

NOSTUFF

CA380

1

2

6

VCC

DFN

NO_XNET_CONNECTION=1

1%
MF

201

1

2

1

2

1

2

1

2

1

RA345

0.1UF

10%
16V
X5R-CERM
0201

RA385

41.2K

1/20W

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

DIDT=TRUE

GFXIMVP_BOOT

0

2

BOOT

2

1

GFXIMVP_FCCM

PHASE

THRM

GND

376S00174 1 CRITICALQA340

MOSFET,CTRL+SYNC,25V,4.1/1.4MO,QFN32,6x6

PAD

9

4

LGATE

8

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000

5

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

RA380

0

5%
1/20W
MF
0201

RA382

499

1%
1/20W
MF
201

CA382

100PF

5%
25V
C0G
0201

5%
1/16W
MF-LF
402

124 98

CA381

3300PF

10%
10V

X7R-CERM

0201

CA383

3300PF

10%
10V

X7R-CERM

0201

21

21

NOSTUFF

RA383

RA384

30

1/20W

201

9.09K

1/20W

201

REG_GPU_VDDCI_FB_R

GFXIMVP_BOOT_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

1

CA345

0.22UF

10%
16V

2

MIN_LINE_WIDTH=0.2000

CERM

MIN_NECK_WIDTH=0.1200

402

GATE_NODE=TRUE
DIDT=TRUE

GFXIMVP_UGATE3
GFXIMVP_PHASE3

GFXIMVP_Q1S3

GFXIMVP_LGATE3

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

REG_GPU_VDDCI_FB2_R

1

1%
MF

1%
MF

OMIT_TABLE

2

1

2

NOSTUFF

18

21

20

QA340

IRF3575

CRITICAL

GATEH

25

SW

6
7

26

Q1S
GATEL

5

32

4

28

16

PPBUS_HS_GPU

23

22

VIN

PQFN

1

NC

2

NC

3

NC

24

NC

27

NC

29

NC

30

NC

PGND

376S1136

31

101

101

101

101

101

101

101

124 98

NC

DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000

IN

IN

IN

IN

OUT
OUT
OUT

REG_BOOT_GPU_VDDCI

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

REG_UGATE_GPU_VDDCI_R

DIDT=TRUE
SWITCH_NODE=TRUE

REG_PHASE_GPU_VDDCI
REG_LGATE_GPU_VDDCI

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000

REG_GPU_VDDCI_FCCM
REG_GPU_VDDCI_IMON
REG_GPU_VDDCI_ISEN1

101 115

GFXIMVP_PHASE3

SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE

2.2

5%
1/16W
MF-LF

402

1

5%
1/16W
MF-LF

402

1

2

21

RA366

RA365

GATE_NODE=TRUEDIDT=TRUE

GATE_NODE=TRUE
DIDT=TRUE

1

RA386

10K

1%
1/20W

201

2

CRITICAL

LA340

0.2UH-20%-28A-0.0011OHM

21

PILA63T-SM

94

NO_XNET_CONNECTION

NO_XNET_CONNECTION=1

GFXIMVP_ISEN3

101

NO_XNET_CONNECTION=1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

PPVCORE_S0_GFX_PH3

VOLTAGE=1.1V

GFXIMVP_ISNS3_P

CA365

1

0.1UF

10%

2

16V
X7R-CERM
0402

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000

REG_UGATE_GPU_VDDCI

DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000

115

APN376S1005

1

RA387

365K

1%
1/20W
MFMF
201

2

CA384

1

1000PF

10%
16V
X7R-1

2

0201

CRITICAL

RA346

0.00075

0612-1

RA347

10K

1%

1/20W

MF

201

1

RA348

2

CA346

0.22UF

20%

6.3V

X6S-CERM

0201

1

1K

1%

1/20W

MF

201

2

21

NO_XNET_CONNECTION=1

PPBUS_HS_GPU

CRITICAL

QA350

CSD58873Q3D

TG

3

TGR

4

BG

5

1

RA389

121K

1%
1/20W
MF
201

2

1%
1W
MF

21
43

GFXIMVP_ISNS3_N

NO_XNET_CONNECTION=1

1

RA349

1.00

1%
1/20W
MF-LF
0201

2

GFXIMVP_ISUMN
GFXIMVP_ISUMP

Q3D

PPVCORE_S0_GPU

RA350

10K

1/20W

MF

201

RA351

10K

1/20W

MF

201

1%

21

1%

NO_XNET_CONNECTION=1

VIN

1

6

VSW

PGND

9

101

OUT

101

OUT

NO_XNET_CONNECTION=1

21

7

VR_PHASE_GPU_VDDCI VRVDDCI_R

8

REG_GPU_VDDCI_ISUMP
REG_GPU_VDDCI_ISUMN

101 94

101

101

GFXIMVP_ISNS2_N

GFXIMVP_ISNS1_N

CAPDERATE

CAPDERATE

CRITICAL

1

CA350

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

1

CA356

33UF

20%

2

16V
TANT-POLY
CASE-B3

CRITICAL

LA350

0.2UH-20%-28A-0.0011OHM

NOSTUFF

CA366

1

0.001UF

10%
50V

2

X7R-CERM
0402

REG_SNUBBER_GPU_VDDCI
NOSTUFF

1

RA367

2.2

5%
1/10W
MF-LF
603

2

PILA63T-SM

NO_XNET_CONNECTION=1

CA390

5600PF

CERM

RA390

101 94

101 94

3.09K

1%

1/20W

MF

201

BOM_COST_GROUP=GRAPHICS

101 115

NO_XNET_CONNECTION=1

CAPDERATE

CRITICAL

1

CA357

33UF

2

1

10%
10V

2

201

21

CAPDERATE

CRITICAL

1

CA358

33UF

20%
16V
TANT-POLY
CASE-B3

21

20%

2

16V
TANT-POLY
CASE-B3

REG_GPU_VDDCI_VSUMP

NO_XNET_CONNECTION=1

RA391

1K

1%

1/20W

MF

201

REG_GPU_VDDCI_VSUMN

RA392

1.00

1%

CA391

1

0.1UF

10%

2

16V
X5R-CERM
0201

1/20W
MF-LF

0201

REG_GPU_VDDCI_VSUMN_R

CRITICAL

CA351

1

12PF

5%

2

NP0-C0G
0201
25V

CRITICAL

RA368

0.002

1%

1/2W

MF

0306

2 1
4 3

21

21

NO_XNET_CONNECTION=1

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

CA352

1

3.0PF

+/-0.1PF

2

25V
NP0-C0G
0201

1

2

Note:

Regulator requires
a minimum load to
prevent noise in the
audio frequencies

XWA353

SM

2 1

XWA354

SM

2 1

VDDCIS0_CS_P

VDDCIS0_CS_N

VR 1.05V GPU & 1.35V FB

Apple Inc.

PLACE_NEAR=QA350.1:4mm

CA353

1000PF

5%
25V
CERM
0402

CA354

1

2.2UF

20%

2

25V
X6S-CERM
0402

PLACE_NEAR=QA350.1:4mm

PPVDDCI_S0_GPU

GPU VDDCI SUPPLY

VOUT = 0.8V-0.9V
?9.7A? MAX OUTPUT
F = 450 KHZ

OUT

OUT

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

EMC

CA355

1

2.2UF

20%

2

25V
X6S-CERM
0402

115

121 58

121 58

051-02643

4.0.0
evt-0

103 OF 200

98 OF 131

EMC

SIZE

D

B

A

SYNC_DATE=04/27/2017SYNC_MASTER=SILU

8

67

35 4

2

1

678

3 245

1

D

C

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

99 97 118 99 97

118

PLACE_NEAR=UA400.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

FB_A1_CLK_P

PLACE_NEAR=UA450.J12:8.4MM

CK TERMINATION - A0

FB_A0_CLK_P

RA400

CK TERMINATION - A1

RA451

RA401

60.4

1%

1/20W

MF

201

1

120

1%

1/20W

MF

201

2

60.4

1/20W

1%
MF

201

21

21

RA404

120

1%

1/20W

MF

201

PLACE_NEAR=UA400.J11:8.4MM

RA402

60.4

1%

1/20W

MF

201

1

2

PLACE_NEAR=UA450.J11:8.4MM

RA452

60.4

1%

1/20W

MF

201

FB_A0_CLK_N

21

120

1%

1/20W

MF

201

1

2

RA403

FB_A1_CLK_N

21

97
99
118

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 99 97

118 99 97

118 97

118 97

118 97

118 97

99 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

UA400

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

IN
IN
IN
IN

IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN

FB_A0_A<2>
FB_A0_A<5>
FB_A0_A<4>
FB_A0_A<3>

FB_A0_A<7>
FB_A0_A<1>
FB_A0_A<0>
FB_A0_A<6>
FB_A0_CKE_L

FB_A0_CLK_P
FB_A0_CLK_N
FB_A0_CS_L
FB_A0_WE_L
FB_A0_CAS_L
FB_A0_RAS_L
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN

IN

IN

BI
BI
BI
BI

IN
IN

IN
IN

FB_A_RESET_L

FB_A0_ABI_L

FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>

FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>

H11
K10
K11
H10

K4
H5
H4
K5

J3

J12
J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2
C13
R13

R2

D4

D5

P4

P5

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A8/A7
A9/A1
A10/A0
A11/A6
CKE*

CK
CK*
CS*
WE*
CAS*
RAS*
ZQ

(MF=0)

MF
SEN
RESET*

ABI*

EDC0
EDC1
EDC2
EDC3

WCK01
WCK01*

WCK23
WCK23*

(1 OF 2)

OMIT_TABLE

DBI0*
DBI1*
DBI2*
DBI3*

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>

FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<2>
FB_A0_DQ<3>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<7>
FB_A0_DQ<8>
FB_A0_DQ<9>
FB_A0_DQ<10>
FB_A0_DQ<11>
FB_A0_DQ<12>
FB_A0_DQ<13>
FB_A0_DQ<14>
FB_A0_DQ<15>
FB_A0_DQ<16>
FB_A0_DQ<17>
FB_A0_DQ<18>
FB_A0_DQ<19>
FB_A0_DQ<20>
FB_A0_DQ<21>
FB_A0_DQ<22>
FB_A0_DQ<23>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<26>
FB_A0_DQ<27>
FB_A0_DQ<28>
FB_A0_DQ<29>
FB_A0_DQ<30>
FB_A0_DQ<31>

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

120

1%

1/20W

MF

201

1

2

RA454

120

1%

1/20W

MF

201

1

RA453

2

120

1%

1/20W

MF

201

1

2

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

RA450

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 99 97

118 99 97

118 97

118 97

118 97

118 97

99 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

IN
IN
IN
IN

IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN

IN

IN

BI
BI
BI
BI

IN
IN

IN
IN

FB_A1_A<2>
FB_A1_A<5>
FB_A1_A<4>
FB_A1_A<3>

FB_A1_A<7>
FB_A1_A<1>
FB_A1_A<0>
FB_A1_A<6>
FB_A1_CKE_L

FB_A1_CLK_P
FB_A1_CLK_N
FB_A1_CS_L
FB_A1_WE_L
FB_A1_CAS_L

FB_A1_RAS_L
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN

FB_A_RESET_L

FB_A1_ABI_L

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A1_WCLK_P<0>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

H11

K10
K11

H10

K4
H5
H4
K5

J3

J12
J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2
C13
R13

R2

D4

D5

P4
P5

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A8/A7
A9/A1
A10/A0
A11/A6
CKE*

CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF
SEN
RESET*

ABI*

EDC0
EDC1
EDC2
EDC3

WCK01
WCK01*

WCK23
WCK23*

32MX32-1.25GHZ-MFL

(MF=0)

UA450

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

DBI0*
DBI1*
DBI2*
DBI3*

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>

FB_A1_DQ<0>
FB_A1_DQ<1>
FB_A1_DQ<2>
FB_A1_DQ<3>
FB_A1_DQ<4>
FB_A1_DQ<5>
FB_A1_DQ<6>
FB_A1_DQ<7>
FB_A1_DQ<8>
FB_A1_DQ<9>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<12>
FB_A1_DQ<13>
FB_A1_DQ<14>
FB_A1_DQ<15>
FB_A1_DQ<16>
FB_A1_DQ<17>
FB_A1_DQ<18>
FB_A1_DQ<19>
FB_A1_DQ<20>
FB_A1_DQ<21>
FB_A1_DQ<22>
FB_A1_DQ<23>
FB_A1_DQ<24>
FB_A1_DQ<25>
FB_A1_DQ<26>
FB_A1_DQ<27>
FB_A1_DQ<28>
FB_A1_DQ<29>
FB_A1_DQ<30>
FB_A1_DQ<31>

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

D

C

B

A

99 100 115 124

PP1V5R1V35_S0_GPU_MEM

CA400

1

4.7UF

20%

2

6.3V
X6S
0402

CA403

1

4.7UF

20%

6.3V

2

X6S
0402

CA406

1

1UF

20%

2

4V
CERM-X6S
0201

CA410

1

1UF

20%
4V

2

CERM-X6S
0201

CA414

1

1UF

20%

2

4V
CERM-X6S
0201

CA418

1

0.1UF

10%

6.3V

2

X6S
0201

CA422

1

0.1UF

10%

6.3V

2

X6S
0201

CA401

1

2

CA404

1

2

CA407

1

2

CA411

1

2

CA415

1

2

CA419

1

2

CA423

1

2

4.7UF

20%

6.3V
X6S
0402

4.7UF

20%

6.3V
X6S
0402

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

0.1UF

10%

6.3V
X6S
0201

0.1UF

10%

6.3V
X6S
0201

CA402

1

4.7UF

20%

2

6.3V
X6S
0402

CA405

1

4.7UF

20%

6.3V

2

X6S
0402

CA408

1

1UF

20%

2

4V
CERM-X6S
0201

CA412

1

1UF

20%
4V

2

CERM-X6S
0201

CA416

1

0.1UF

10%

2

6.3V
X6S
0201

CA420

1

0.1UF

10%

6.3V

2

X6S
0201

CA424

1

0.1UF

10%

6.3V

2

X6S
0201

FB_A0_VREFC

99

FB_A0_VREFD

99

NOSTUFF

CA496

1

12PF

5%
25V

2

NP0-C0G
0201

CA497

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CA409

1

1UF

20%

2

4V
CERM-X6S
0201

CA413

1

1UF

20%
4V

2

CERM-X6S
0201

CA417

1

0.1UF

10%

2

6.3V
X6S
0201

CA421

1

0.1UF

10%

6.3V

2

X6S
0201

CA425

1

0.1UF

10%

6.3V

2

X6S
0201

C5
C10
D11

G1

G4

G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3
K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3
T12
T14

J14

A10

U10

VDD

VDDQ

VREFC

VREFD

UA400

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSS

VSSQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_A0_VREFC

99

PLACE_NEAR=UA400.J14:8.4MM

PLACE CLOSE TO U9000

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_A0_VREFD

99

PLACE_NEAR=UA400.U10:8.4MM

PLACE_NEAR=UA400.U10:8.4MM

NOSTUFF

CA432

1

820PF

10%

2

25V
X7R-CERM
0201

CA431

1

820PF

10%
25V

2

X7R-CERM
0201

PLACE_NEAR=UA400.U10:12.4MM

NOSTUFF

CA433

1

820PF

10%

2

25V
X7R-CERM
0201

A5

NC

J5

NC

U5

1

RA430

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA400.J14:8.4MM

PLACE_NEAR=UA400.J14:8.4MM

1

RA431

1.33K

1%
1/20W
MF
201

2

FB_A0_ZQ1

RA460

120

1%

1/20W

MF

201

PLACE_NEAR=UA400.J14:8.4MM

1

RA434

931

1%
1/20W
MF
201

2

1

2

FB_SW_LEG

1

RA432

NOSTUFF

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA400.U10:8.4MM

PLACE_NEAR=UA400.U10:8.4MM

NOSTUFF

1

RA433

1.33K

1%
1/20W
MF
201

2

NOSTUFF

1

RA435

931

1%
1/20W
MF
201

2

FB_SW_LEG

FB_A0_A<8>

NOSTUFF

IN

UA450

IN

99 100 115 124

100 99

100 99

118 97

PP1V5R1V35_S0_GPU_MEM

CA450

1

4.7UF

20%

2

6.3V
X6S
0402

CA453

1

4.7UF

20%

6.3V

2

X6S
0402

CA456

1

1UF

20%

2

4V
CERM-X6S
0201

CA460

1

1UF

20%
4V

2

CERM-X6S
0201

CA464

1

1UF

20%
4V

2

CERM-X6S
0201

CA468

1

0.1UF

10%

6.3V

2

X6S
0201

CA472

1

0.1UF

10%

6.3V

2

X6S
0201

CA451

1

4.7UF

20%

2

6.3V
X6S
0402

CA454

1

4.7UF

20%

6.3V

2

X6S
0402

CA457

1

1UF

20%

2

4V
CERM-X6S
0201

CA461

1

1UF

20%
4V

2

CERM-X6S
0201

CA465

1

1UF

20%
4V

2

CERM-X6S
0201

CA469

1

0.1UF

10%

6.3V

2

X6S
0201

CA473

1

0.1UF

10%

6.3V

2

X6S
0201

CA452

1

4.7UF

20%

2

6.3V
X6S
0402

CA455

1

4.7UF

20%

6.3V

2

X6S
0402

CA458

1

1UF

20%

2

4V
CERM-X6S
0201

CA462

1

1UF

20%
4V

2

CERM-X6S
0201

CA466

1

0.1UF

10%

6.3V

2

X6S
0201

CA470

1

0.1UF

10%

6.3V

2

X6S
0201

CA474

1

0.1UF

10%

6.3V

2

X6S
0201

FB_A1_VREFC

99

FB_A1_VREFD

99

CA459

1

1UF

20%

2

4V
CERM-X6S
0201

CA463

1

1UF

20%
4V

2

CERM-X6S
0201

CA467

1

0.1UF

10%

6.3V

2

X6S
0201

CA471

1

0.1UF

10%

6.3V

2

X6S
0201

CA475

1

0.1UF

10%

6.3V

2

X6S
0201

C5
C10
D11

G1

G4
G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3

T12
T14

J14
A10
U10

VDD

VDDQ

VREFC

VREFD

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

B5
B10
D10
G5
G10
H1

VSS

VSSQ

H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

PLACE_NEAR=UA450.J14:8.4MM

BOM_COST_GROUP=GRAPHICS

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_A1_VREFD

99

PLACE_NEAR=UA450.U10:8.4MM

PLACE_NEAR=UA450.A10:8.4MM

SYNC_MASTER=SEAN SYNC_DATE=04/19/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

A5

NC

J5

NC

U5

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

FB_A1_VREFC

99

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

NOSTUFF

CA482

1

820PF

10%
25V

2

X7R-CERM
0201

CA481

1

820PF

10%
25V

2

X7R-CERM
0201

NOSTUFF

CA483

1

2

Apple Inc.

FB_A1_A<8>

IN

FB_A1_ZQ1

120

1%

1/20W

MF

201

1

2

NOSTUFF

PLACE_NEAR=UA450.J14:8.4MM

1

RA484

931

1%
1/20W
MF
201

2

RA461

1

RA480

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA450.J14:8.4MM

PLACE_NEAR=UA450.J14:8.4MM

1

RA481

1.33K

1%
1/20W
MF
201

2

FB_SW_LEG

PLACE CLOSE TO U9050

1

RA482

NOSTUFF

549

1%
1/20W
MF
201

PLACE_NEAR=UA450.U10:8.4MM

PLACE_NEAR=UA450.U10:8.4MM

PLACE_NEAR=UA450.U10:8.4MM

NOSTUFF

RA483

1.33K

1%
1/20W
MF
201

1

RA485

931

1%
1/20W
MF
201

2

820PF

10%
25V
X7R-CERM
0201

2

1

2

FB_SW_LEG

GDDR5 VRAM FB 1 [104]

118 97

NOSTUFF

DRAWING NUMBER

051-02643

REVISION

BRANCH

PAGE

104 OF 200

SHEET

99 OF 131

ININ

IN

100 99

100 99

4.0.0
evt-0

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

CK TERMINATION - B0

FB_B0_CLK_P

PLACE_NEAR=UA500.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

CK TERMINATION - B1

FB_B1_CLK_P

PLACE_NEAR=UA550.J12:8.4MM

RA501

60.4

1%

1/20W

MF

201

RA500

120

1%

1/20W

MF

201

RA551

60.4

1%

1/20W

MF

201

21

1

2

21

RA504

120

1%

1/20W

MF

201

RA502

60.4

1/20W

201

1

2

RA552

60.4

1%

1/20W

MF

201

FB_B0_CLK_N

21

1%

PLACE_NEAR=UA500.J11:8.4MM

MF

118 100 97

118 100 97

120

1%

1/20W

MF

201

1

2

97
100
118

RA503

FB_B1_CLK_N

21

PLACE_NEAR=UA550.J11:8.4MM

118 97

118 97

118 97

118 97

118 97

118 97

118 100 97 118 100 97

118 97

118 97

118 97

118 97

118 97

100 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

UA500

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

IN
IN
IN
IN

IN
IN
IN
IN
IN

FB_B0_A<2>
FB_B0_A<5>
FB_B0_A<4>
FB_B0_A<3>

FB_B0_A<7>
FB_B0_A<1>
FB_B0_A<0>
FB_B0_A<6>
FB_B0_CKE_L

H11
K10
K11
H10

K4
H5
H4
K5

J3

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A8/A7
A9/A1
A10/A0
A11/A6
CKE*

(1 OF 2)

DBI0*
DBI1*
DBI2*
DBI3*

OMIT_TABLE

IN
IN
IN
IN
IN
IN

FB_B0_CLK_P
FB_B0_CLK_N
FB_B0_CS_L
FB_B0_WE_L
FB_B0_CAS_L
FB_B0_RAS_L
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN

IN

IN

BI
BI
BI
BI

IN
IN

IN
IN

FB_B_RESET_L

FB_B0_ABI_L

FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>

FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>

J12
J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2
C13
R13

R2

D4

D5

P4

P5

CK
CK*
CS*
WE*
CAS*
RAS*
ZQ

(MF=0)

MF
SEN
RESET*

ABI*

EDC0
EDC1
EDC2
EDC3

WCK01
WCK01*

WCK23
WCK23*

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>

FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<12>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<18>
FB_B0_DQ<19>
FB_B0_DQ<20>
FB_B0_DQ<21>
FB_B0_DQ<22>
FB_B0_DQ<23>
FB_B0_DQ<24>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<28>
FB_B0_DQ<29>
FB_B0_DQ<30>
FB_B0_DQ<31>

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

120

1%

1/20W

MF

201

1

2

RA554

120

1%

1/20W

MF

201

1

RA553

2

120

1%

1/20W

MF

201

1

2

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

RA550

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 100 97

118 100 97

118 97

118 97

118 97

100 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

97

IN
IN
IN
IN

IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN

IN

IN

BI
BI
BI
BI

IN
IN

IN
IN

FB_B1_A<2>
FB_B1_A<5>
FB_B1_A<4>
FB_B1_A<3>

FB_B1_A<7>
FB_B1_A<1>
FB_B1_A<0>
FB_B1_A<6>
FB_B1_CKE_L

FB_B1_CLK_P
FB_B1_CLK_N

FB_B1_CS_L
FB_B1_WE_L
FB_B1_CAS_L
FB_B1_RAS_L
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
FB_B_RESET_L

FB_B1_ABI_L

FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>

FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>

H11

K10
K11

H10

K4
H5
H4
K5

J3

J12
J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2
C13
R13

R2

D4

D5

P4

P5

BA0/A2
BA1/A5
BA2/A4
BA3/A3

A8/A7
A9/A1
A10/A0
A11/A6
CKE*

CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF
SEN
RESET*

ABI*

EDC0
EDC1
EDC2
EDC3

WCK01
WCK01*

WCK23
WCK23*

32MX32-1.25GHZ-MFL

(MF=0)

UA550

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

DBI0*
DBI1*
DBI2*
DBI3*

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>

FB_B1_DQ<0>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<5>
FB_B1_DQ<6>
FB_B1_DQ<7>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<18>
FB_B1_DQ<19>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<22>
FB_B1_DQ<23>
FB_B1_DQ<24>
FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<30>
FB_B1_DQ<31>

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

118 97

D

C

B

A

99 100 115 124

PP1V5R1V35_S0_GPU_MEM

CA500

1

4.7UF

20%

2

6.3V
X6S
0402

CA503

1

4.7UF

20%

6.3V

2

X6S
0402

CA506

1

1UF

20%

2

4V
CERM-X6S
0201

CA510

1

1UF

20%
4V

2

CERM-X6S
0201

CA514

1

1UF

20%

2

4V
CERM-X6S
0201

CA518

1

0.1UF

10%

6.3V

2

X6S
0201

CA522

1

0.1UF

10%

6.3V

2

X6S
0201

CA501

1

2

CA504

1

2

CA507

1

2

CA511

1

2

CA515

1

2

CA519

1

2

CA523

1

2

4.7UF

20%

6.3V
X6S
0402

4.7UF

20%

6.3V
X6S
0402

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

0.1UF

10%

6.3V
X6S
0201

0.1UF

10%

6.3V
X6S
0201

CA502

1

4.7UF

20%

2

6.3V
X6S
0402

CA505

1

4.7UF

20%

6.3V

2

X6S
0402

CA508

1

20%

2

4V
CERM-X6S
0201

CA512

1

1UF

20%
4V

2

CERM-X6S
0201

CA516

1

10%

2

6.3V
X6S
0201

CA520

1

0.1UF

10%

6.3V

2

X6S
0201

CA524

1

0.1UF

10%

6.3V

2

X6S
0201

FB_B0_VREFC

100

FB_B0_VREFD

100

NOSTUFF

CA598

1

12PF

5%

2

25V
NP0-C0G
0201

CA599

1

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CA509

1

1UF1UF

20%

2

4V
CERM-X6S
0201

CA513

1

1UF

20%
4V

2

CERM-X6S
0201

CA517

1

0.1UF0.1UF

10%

2

6.3V
X6S
0201

CA521

1

0.1UF

10%

6.3V

2

X6S
0201

CA525

1

0.1UF

10%

6.3V

2

X6S
0201

C5
C10
D11

G1

G4

G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3
K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3
T12
T14

J14

A10

U10

VDD

VDDQ

VREFC

VREFD

UA500

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSS

VSSQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

99 100 115 124

PP1V5R1V35_S0_GPU_MEM

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_B0_VREFC

100

PLACE_NEAR=UA500.J14:8.4MM

CA531

1

820PF

10%
25V

2

X7R-CERM
0201

PLACE CLOSE TO U9000

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_B0_VREFD

100

NOSTUFF

CA532

1

820PF

10%
25V

2

X7R-CERM
0201

PLACE_NEAR=UA500.A10:8.4MM

PLACE_NEAR=UA500.U10:8.4MM

NOSTUFF

CA533

1

820PF

10%
25V

2

X7R-CERM
0201

A5

NC

J5

NC

U5

1

RA530

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA500.J14:8.4MM

PLACE_NEAR=UA500.J14:8.4MM

1

RA531

1.33K

1%
1/20W
MF
201

2

FB_B0_ZQ1

RA560

120

1%

1/20W

MF

201

PLACE_NEAR=UA500.J14:8.4MM

1

RA534

931

1%
1/20W
MF
201

2

1

2

FB_SW_LEG

NOSTUFF

1

RA532

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA500.U10:8.4MM

PLACE_NEAR=UA500.U10:8.4MM

NOSTUFF

1

RA533

1.33K

1%
1/20W
MF
201

2

PLACE_NEAR=UA500.U10:8.4MM

NOSTUFF

1

RA535

931

1%
1/20W
MF
201

2

FB_SW_LEG

FB_B0_A<8>

NOSTUFF

IN

IN

UA550

IN

99 100 115 124

100 99

100 99

118 97

PP1V5R1V35_S0_GPU_MEM

CA550

1

4.7UF

20%

2

6.3V
X6S
0402

CA553

1

4.7UF

20%

6.3V

2

X6S
0402

CA556

1

1UF

20%

2

4V
CERM-X6S
0201

CA560

1

1UF

20%
4V

2

CERM-X6S
0201

CA564

1

1UF

20%
4V

2

CERM-X6S
0201

CA568

1

0.1UF

10%

6.3V

2

X6S
0201

CA572

1

0.1UF

10%

6.3V

2

X6S
0201

CA551

1

4.7UF

20%

2

6.3V
X6S
0402

CA554

1

4.7UF

20%

6.3V

2

X6S
0402

CA557

1

1UF

20%

2

4V
CERM-X6S
0201

CA561

1

1UF

20%
4V

2

CERM-X6S
0201

CA565

1

1UF

20%
4V

2

CERM-X6S
0201

CA569

1

0.1UF

10%

6.3V

2

X6S
0201

CA573

1

0.1UF

10%

6.3V

2

X6S
0201

CA552

1

4.7UF

20%

2

6.3V
X6S
0402

CA555

1

4.7UF

20%

6.3V

2

X6S
0402

CA558

1

1UF

20%

2

4V
CERM-X6S
0201

CA562

1

1UF

20%
4V

2

CERM-X6S
0201

CA566

1

0.1UF

10%

6.3V

2

X6S
0201

CA570

1

0.1UF

10%

6.3V

2

X6S
0201

CA574

1

0.1UF

10%

6.3V

2

X6S
0201

FB_B1_VREFC

100

FB_B1_VREFD

100

CA559

1

1UF

20%

2

4V
CERM-X6S
0201

CA563

1

1UF

20%
4V

2

CERM-X6S
0201

CA567

1

0.1UF

10%

6.3V

2

X6S
0201

CA571

1

0.1UF

10%

6.3V

2

X6S
0201

CA575

1

0.1UF

10%

6.3V

2

X6S
0201

C5
C10
D11

G1

G4
G11
G14

L1

L4
L11
L14

P11

R5

R10

B1

B3
B12
B14

D1

D3
D12
D14

E5

E10

F1

F3
F12
F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3
M12
M14

N5

N10

P1

P3
P12
P14

T1

T3

T12
T14

J14
A10
U10

VDD

VDDQ

VREFC

VREFD

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

OMIT_TABLE

VSS

VSSQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

PLACE_NEAR=UA550.U10:8.4MM

PLACE_NEAR=UA550.A10:8.4MM

PLACE_NEAR=UA550.J14:8.4MM

BOM_COST_GROUP=GRAPHICS

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

MIN_LINE_WIDTH=0.0920
MIN_NECK_WIDTH=0.0850

FB_B1_VREFD

100

SYNC_MASTER=SEAN SYNC_DATE=04/19/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

A5

NC

J5

NC

U5

PP1V5R1V35_S0_GPU_MEM

99 100 115 124

FB_B1_VREFC

100

99 100 115 124

NOSTUFF

CA582

1

820PF

10%
25V

2

X7R-CERM
0201

FB_B1_A<8>

FB_B1_ZQ1

120

1%

1/20W

MF

201

1

2

CA581

1

820PF

10%

2

25V
X7R-CERM
0201

PLACE CLOSE TO U9050

RA561

1

RA580

549

1%
1/20W
MF
201

2

PLACE_NEAR=UA550.J14:8.4MM

PLACE_NEAR=UA550.J14:8.4MM

1

RA581

1.33K

1%
1/20W
MF
201

2

PP1V5R1V35_S0_GPU_MEM

NOSTUFF

1

RA582

549

1%
1/20W
MF
201

NOSTUFF

CA583

1

820PF

10%
25V

2

X7R-CERM
0201

2

1

2

PLACE_NEAR=UA550.U10:8.4MM

PLACE_NEAR=UA550.U10:8.4MM

NOSTUFF

RA583

1.33K

1%
1/20W
MF
201

GDDR5 VRAM FB 2

Apple Inc.

IN

118 97

NOSTUFF

PLACE_NEAR=UA550.J14:8.4MM

1

RA584

931

1%
1/20W
MF
201

2

FB_SW_LEG

NOSTUFF

PLACE_NEAR=UA550.U10:8.4MM

1

RA585

931

1%
1/20W
MF
201

2

IN

FB_SW_LEG

DRAWING NUMBER

100 99

IN

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

105 OF 200

SHEET

100 OF 131

B

100 99

A

SIZE

D

8

67

35 4

2

1