Apple X1190 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

SCHEM,MLB,X1190

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2018-01-2600110840694 ENGINEERING RELEASED

D

C

B

CSAPAGE

1
2
3
4 PD Parts
5
6
7
8

1
2
3
4
5
6
7

8
9
10

10

CONTENTS

Table of Contents 05/24/2017
BOM Configuration 1
BOM Configuration 2

CPU DMI/PEG/FDI/RSVD
CPU Clock/Misc/JTAG/CFG
CPU DDR4 Interfaces
CPU Power
CPU Ground

CPU Decoupling 1
11 11 CPU Decoupling 2
12
13
14
15
16
17
18
19
20
21
22
23
24
25

27
28
29
30
31
32
33

35

12

PCH RTC/CLK/ESPI/PM

13
14
15
16
17
18
19
20
22
23
24
25
26
27

PCH PCI-E/USB

PCH GPIO/MISC/NCTF

PCH Power

PCH Decoupling

CPU/PCH Merged XDP

Chipset Support 1

Chipset Support 2

DDR4 VREF Margining

DDR4 SDRAM Channel A 1 02/09/2017

DDR4 SDRAM Channel A 2

DDR4 SDRAM Channel B 1

DDR4 SDRAM Channel B 2

DDR4 Termination26

28 USB-C HIGH SPEED 1
29
30
31
32
33
34
35
36

USB-C HIGH SPEED 2

USB-C X Support

USB-C PORT CONTROLLER A

USB-C PORT CONTROLLER B

USB-C CONNECTOR A

USBC X Connector Support

TBT 5V REGULATOR

WIFI/BT: Support
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

38
39
40
41
42
43
44
45
46
47
48
49
50
51

AP & BT Conn

SoC GPIO/SEP/USB/DDR/Test

SoC AOP/AON/SMC

SoC ISP/I2C/UART/SPI/I2S

SoC PCIe

SoC Power 1

SoC Power 2

SoC Power 3

SoC Ground

SoC Project Support

MESA

Secure Element

DFR & T208 Support

SILU
SEAN
SEAN

ZIFENG_CONSTRAINTS

ZIFENG
j380_mlb
j380_mlb

ZIFENG_CONSTRAINTS

j380_mlb
SILU
SILU
ZIFENG
SILU
ZIFENG
ZIFENG
ZIFENG
ZIFENG
ZIFENG
SILU
ZIFENG
j380_mlb
j380_mlb
j380_mlb
j380_mlb
j380_mlb
j380_mlb

J132

ADITYA

ADITYA
ZIFENG
ZIFENG
SILU_J680
ADITYA

J132
J132

METE
METE
SILU
SILU

H9M and PMIC

SILU
SILU

H9M and PMIC

SILU

H9M and PMIC

SILU

SILU
SILU
SILU

SILU

DATESYNC

11/29/2017
11/29/2017
03/03/2017
09/07/2017
02/09/2017
02/09/2017
02/24/2017
02/09/20179
03/29/2017
05/24/2017
05/18/2017
07/27/2017PCH DMI/JTAG/SPI/HDA
05/18/2017
05/18/2017
05/18/2017
05/18/2017
05/24/2017
08/09/2017
05/18/2017
02/09/2017

02/09/2017
02/09/2017
02/09/2017
02/10/2017
05/11/2017
03/30/2017
04/19/2017
05/26/2017
05/26/2017
08/09/2017
04/05/2017
04/05/201734
03/29/2017
05/10/2017WIFI/BT: MODULE 137
08/11/2017
05/26/2017
03/22/2017
03/02/2017
03/15/2017
04/04/2017
03/02/2017
05/26/2017
03/02/2017
08/09/2017SoC Shared Support
07/27/2017
05/26/2017
05/05/2017
07/27/2017

CSAPAGE DATESYNC

51
52
53

52
53
54

55
55
56
57
58
59
60
61
62
63
64
65

56

57

58

59

60

62

63 07/24/2017Audio Jack Codec

64

65

66

67

68
67 VR 3.3V G3H & Battery Conn
68
69
70
71
72
73
74
75
76
77
78
79

69

70

71

72

73 05/10/2017

74

76

77

78

79 PMIC LDOs

80

81

82
80 83
81
82
83

84

85

86
84
85
86 SSD0 S4E 3
87
88
89

88

89

90

91

92

9390
91
92
93

94

95

98
94
95
96
97
98
99

101

102

103

104

105100

CONTENTS

I2C Connections 1
I2C Connections 2
Power Sensors High Side
Power Sensors Load Side54
Power Sensors Extended 1
Power Sensors Extended 2
Thermal Sensors
Power Sensor Extended 3
Fans/SMC/AMUX Support
Audio Placeholder

Audio Right Amplifiers
Audio Flex Connectors TROY
Keyboard & Trackpad 1
Keyboard & Trackpad 266

PBUS Supply & Battery Charger
IMVP IC
IMVP VCC Block 05/24/2017
IMVP SA Block
IMVP GT Block
Power - 5V 3.3V Supply
VR 2.5V & 1.2V/VTT
PMIC BUCKS AND SWs

PMIC GPIOs & Control
VR VCCIO
Power FETs
SOC/PMIC Aliases
LCD Backlight Driver
eDP Display Connector

SSD0 S4E 187
SSD0 S4E 2

SSD0 PMIC & VR
SSD1 S4E 0
SSD1 S4E 1
SSD1 S4E 2
SSD1 S4E 3
SSD1 PMIC & VR
EDP Mux
GPU PCC
GPU Baffin PCIe
GPU Baffin Core/FB Power
GPU Baffin FB
VR 1.05V GPU & 1.35V FB
GDDR5 VRAM FB 1 [104]
GDDR5 VRAM FB 2

RAYMOND

RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
RAYMOND
j132-audio
TROY
TROY
TROY

j132

j132
SILU
ZIFENG
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
SILU
RAYMOND

SEAN

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

j137_gs5_redhead

SEAN
SEAN
SEAN
SEAN
SEAN

SILU

SEAN

SEAN

DATESYNC

10/02/2017
10/02/2017
10/09/2017
10/13/2017
10/13/2017
10/13/2017
06/28/2017
10/13/2017
06/13/2017
03/15/2017

12/11/2017Audio Left Amplifiers
12/11/2017
03/22/2017
03/23/2017
03/23/2017
04/27/2017
05/24/2017
05/24/2017

05/24/2017
05/16/2017
05/01/2017
06/06/2017
07/10/2017
07/27/2017
05/10/2017
06/27/2017
08/09/2017
08/07/2017
08/09/2017
01/26/2017SSD0 S4E 0
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017
01/26/2017

05/01/2017
11/09/201799
11/09/2017100
06/21/2017
04/19/2017
04/27/2017
04/19/2017
04/19/2017

CSAPAGE

101
102
103
104

106
107
108
109

110105
106
107
108
109
110

111

112

113

114

115

116
112
113
114
115
116
117
118
119
120
121
122
123
124
125 Memory Bite/Byte Swizzle
126
127

117

118

119 GDDR5 VRAM FB 4

120

121

122

123

124

125

126

127

128

129

130

140

141
128 143
129

144

147

CONTENTS

VR GPU Core
GPU Baffin GPIO/CLK/Straps
GPU Baffin DP/GPIO
GPU Baffin VSS/Misc
USB-C HIGH SPEED 1 05/11/2017
USB-C HIGH SPEED 2
USB-C T Support
USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR A
USBC T Connector Support111
USB-C T 5V VR
GDDR5 VRAM FB 3

Power Alias 1
Power Alias 2
Signal Alias
High speed No Testpoints
DFU TEST POINTS
FCT TESTPOINTS 2
ICT, MAC-1 ,EE Testpoints
Desense Caps 1
Desense Caps 2
Desense Caps 3

Dev Support
BOM-639 2.2GHz
BOM-639 2.6GHz
BOM-639 2.9GHz
BOM Alt Table

SILU
SEAN
SILU
SEAN
J132
ADITYA
ADITYA
ZIFENG
ZIFENG
SILU_J680
ADITYA
SILU
j680_copy
j680_copy
SILU
SILU
METE
RAYMOND
RAYMOND
RAYMOND
RAYMOND
SEAN
j380_mlb
blah
j380_mlb

Debug
SEAN
j380_mlb
j380_mlb
SEAN

05/24/2017
04/19/2017
07/27/2017
11/09/2017

04/03/2017
04/19/2017
05/26/2017
05/26/2017
08/09/2017
04/05/2017
05/11/2017
02/01/2017
02/01/2017
05/01/2017
06/27/2017
05/10/2017
06/02/2017
08/07/2017
08/07/2017
08/31/2017
06/27/2017
02/09/2017
06/27/2017
02/09/2017

05/03/2017
11/29/2017
02/09/2017
02/09/2017
11/29/2017130
03/22/2017ADITYA200131 Dev Support

D

C

B

A

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Fri Jan 26 13:24:05 2018

Schematic / PCB #'s

8

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

3

LAST_MODIFICATION=Fri Jan 26 13:24:05 2018

DRAWING TITLE

SCHEM,MLB,X1190

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

1 OF 200

SHEET

1 OF 131

124567

A

SIZEDRAWING NUMBER

D

D

X1190 BOM Groups

BOM GROUP BOM OPTIONS

X1190_8L
X1190_6L
X1190_COMMON
X1190_COMMON1
X1190_COMMON2
X1190_PROGPARTS
X1190_SNS
X1190_DEVEL:ENG
X1190_DEVEL:DVT
X1190_DEVEL:PVT

ALTERNATE,S4E_L5,S4E_L6,S4E_L7,S4E_L8,OCARINA_2,S4E_X4PLUS,S4E_X8
ALTERNATE,S4E_L5,S4E_L6,OCARINA_2,S4E_X4PLUS,S4E_X6
SCH,PCB,COMMON,ALTERNATE,X1190_COMMON1,X1190_COMMON2,X1190_PROGPARTS,VRAM_ALTS
CPUPEG:X8X4X4,EDP:YES,BOARD_ID,BOARD_REV:011,SE:PROD_2017,EN_VP0R_LPS:YES

SKIP_5V3V3:AUDIBLE,XDP:YES,SYSDET:FET,VCCSPI:3V3,OCARINA_I2C:1K,SVID_PU:CORE,RF_TUNING,PBUS:3S

UPCROM_PROG:P1,WIFI_ROM:P0,BT_ROM:P2

LOADISNS,LOADRC:YES,SENSOR:DEV

ALTERNATE,X1190_SNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,WIFI_DBG,DBG_FAN,GPUROM:BLANK,VITAMIN-C:YES,PCC:YES,GPU_ROM:YES,BOOTCFG0

ALTERNATE,LOADRC:NO

ALTERNATE,LOADRC:NO

678

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

3 245

1

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00179

685-00198
985-00362

1 CRITICAL

685-00193 CRITICAL BOM_8L1

985-00362 CRITICAL DEVEL_BOM

685-00198 BOM_6L

1 CRITICAL

COMMON PARTS,MLB,X1190
S4E 8L Parts,MLB,X1190685-00193
S4E 6L Parts,MLB,X1190

DEV,MLB,X1190

COMMON PARTS, MLB, X1190

S4E 8L PARTS (8L),MLB,X1190

DEV PARTS,MLB,X1190

S4E 6L PARTS (6L),MLB,X1190

BASE

8L

DEVEL1

6L

X1190_COMMON
X1190_8L
X1190_6L
X1190_DEVEL:ENG

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BASE_BOM685-00179

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

B

DRAM Options

BOM GROUP BOM OPTIONS

MC_32G
HY_32G
HY_16G
MC_16G

S4E Options

BOM GROUP BOM OPTIONS

TS_256_PMLC
WD_256_PMLC
TS_512_PMLC
WD_512_PMLC
TS_1TB_PMLC
WD_1TB_PMLC
TS_2TB_PMLC
WD_2TB_PMLC
SM_2TB_3DV4
SM_4TB_3DV4

TS_2TB_TLC
WD_2TB_TLC

32G_MICRON_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L

32G_HYNIX_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

16G_HYNIX_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG1:L,RAMCFG0:L

16G_MICRON_2400,RAMCFG4:L,RAMCFG3:L,RAMCFG1:L

S4E_256_TB,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_256_WD,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_512_TB,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_512_WD,SOC:1GB,SSD0_NAND_VCC:2.5V

S4E_1TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_1TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_2TB_SM,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

S4E_4TB_SM,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TLC_2TB_TB,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TLC_2TB_WD,SOC:2GB,SSD0_NAND_VCC:2.5V,SSD1_NAND_VCC:2.5V

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

A

BOARD ID

BOM GROUP BOM OPTIONS

BOARD_ID BOARDID0,BOARDID1,BOARDID3

VRAM ALT BOM GROUPS

BOM NUMBER BOM NAME BOM OPTIONS

685-00221
685-00222
685-00223
685-00224

VRAM PARTS,HYNIX,2X,MLB,X1190

VRAM PARTS,MICRON,2X,MLB,X1190

VRAM PARTS,SAMSUNG,2X,MLB,X1190

VRAM PARTS,HYNIX,1Z,MLB,X1190

685-00225 VRAM PARTS,MICRON,1Z,MLB,X1190

VRAM SUB-BOM

1 CRITICAL VRAM_ALTS685-00221

VRAM PARTS,HYNIX,2X,MLB,X1190

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

VRAMSSSS

FB_4GB_HYNIX

FB_4GB_MICRON

FB_4GB_SAMSUNG

FB_4GB_HYNIX_1Z

FB_4GB_MICRON_1Z

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

2 OF 200

SHEET

2 OF 131

SYNC_DATE=11/29/2017SYNC_MASTER=SEAN

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

GPU Baffin

337S00493 1 CRITICALUA000
337S00494 UA000 CRITICAL1
998-04866 UA000
998-04867

1
1

GPU,AMD,BAFFIN,ULX,A3,0.83,QS,BGA769

GPU,AMD,BAFFIN,PROX,A3,0.83,QS,BGA769

INTERPOSER,AMD,C989,BGA769,VDDCI/MVDD

INTERPOSER,AMD,C988,BGA769,VDDC

UA000

FB VDRAM Parts

333S00074
333S00075
333S00100

4
4

4
333S00173 4
333S00175

4

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,1ZNM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,1ZNM,A,170 BGA

CPU Parts CFL (Needs to be updated)

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

BAFFIN_ULX

BAFFIN_PROX

STARDUST:VDDCI_MVDD

STARDUST:VDDC

FB_4GB_SAMSUNG

FB_4GB_MICRON

FB_4GB_HYNIX

FB_4GB_MICRON_1Z

FB_4GB_HYNIX_1Z

Programmable Parts

335S00199
341S01017

1 CRITICALUB090341S01018
341S01025 1 U3750 CRITICAL
341S00725 1

IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

T29,TR1(V2.1),NEW-PROTO-2,X1190

T29,TR2(V2.1),NEW-PROTO-2,X1190

IC, BT ROM, EVT,VXX, X1190

IC, WIFI ROM, PROTO0, X1190

H9M

POP,GIBRALTAR+2GB 21NM,H,B0,SCK,CSP1406

PART NUMBER

339S00372339S00373 ALL

339S00378

339S00377

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

UA7011 CRITICAL
U2890 CRITICAL1

U3710 CRITICAL

GPUROM:BLANK

UPCROM_PROG:P1

UPCROM_PROG:P1

BT_ROM:P2

WIFI_ROM:P0

Updated-P1

Updated-P1

Updated

Updated

D

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 SOC:2GBU3900339S00373

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

2GB,20NM,M,B0,SCK,CSP1406

TABLE_ALT_ITEM

ALL339S00372

ALL339S00372

2GB,21NM,H,B0,ATK,CSP1406

TABLE_ALT_ITEM

2GB,20NM,M,B0,ATK,CSP1406

C

337S00509
337S00510
337S00513

1 CRITICALU0500

CPU,CFLH,QP87,QS,U0,2.2,45W,1.1,LGA1440

CPU,CFL-H,QP86,QS,U0,2.6,6C,45W,1.15,BGA1440

CPU,CFL-H,QPQG,QS,U0,2.9,6C,45W,1.2,BGA1440

998-12472

Main DRAM Parts

333S00131 16
333S00134
333S00147
333S00163 16

16
16

INTERPOSER,CFH-H,BGA1440

IC,SDRAM,DDR4-2400,16GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,16GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,8GBIT,20NM,BGA78

IC,SDRAM,DDR4-2400,8GBIT,20NM,BGA78

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 U0500

U05001 CRITICAL

CRITICALU05001

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430,U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630

CRITICAL
CRITICAL
CRITICAL
CRITICAL

CPU_CFL:2.2
CPU_CFL:2.6
CPU_CFL:2.9

CPU_SKL:SOCKET

32G_MICRON_2400

32G_HYNIX_2400

16G_HYNIX_2400

16G_MICRON_2400

PART NUMBER

339S00375

339S00371 339S00376

339S00370

339S00376 ALL

339S00376 ALL

S4E Parts
256GB

998-12418

998-12418998-12419

4335S00324
4

POP,GIBRALTAR+1GB 21NM,H,B0,ATK,CSP1406

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

1GB,20NM,M,B0,ATK,CSP1406

ALL

NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,85GBP,S4E,170G,T,SUBX,ULGA110

ALL

1GB,21NM,H,B0,SCK,CSP1406

1GB,21NM,M,B0,SCK,CSP1406

SUBW

U3900 SOC:1GBCRITICAL1339S00376

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900

U8600,U8700,U8800,U8900

TABLE_ALT_ITEM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL

C

S4E_256_WD
S4E_256_TB

B

PCH CNL-H (Needs to be updated)

337S00523

IC,CNL,PCH-H,USFF,QNYP,QS,B0,BGA499

ACE & Ridges (Needs to Be Updated)

353S01442

338S00408

4 CRITICAL

IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96

IC,TBT,TITAN RIDGE DP,QUJK,QS,C1,CSP337

U3100,U3200,UB300,UB400

Hall Effect AMR

677-10608 CRITICALJ4800,J48012

SUBASSY T&00 PCBA, AMR, INTERPOSER, X1190

Power Controllers

353S01525 1 CRITICALU7000

IC,ISL9240HIB1Z,PMU,SOUNA,WCSP40,2.1X3.3MM

512GB

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALU12001

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALU2800,UB0002

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

335S00325
998-12420

998-12421 998-12420

1TB

998-12422

998-12422998-12423

2TB

335S00327 8
335S00321

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-12424 8

998-12426

998-12424

4
4

6335S00326
6

8

NAND,3DV3,128GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,128GBP,S4E,170G,T,SUBX,ULGA110

ALL

NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,170GBP,S4E,170G,T,SUBX,ULGA110

ALL

NAND,3DV3,256GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV4,256GBP,XXX,S4E,256G,SS,ULGA110

NAND,3DV3,256GBP,S4E,170G,T,SUBX,ULGA110

ALL

SUBW

SUBW

SUBW

U8600,U8700,U8800,U8900

U8600,U8700,U8800,U8900

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900,U9100,U9200

U8600,U8700,U8800,U8900,U9100,U9200

TABLE_ALT_ITEM

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

TABLE_ALT_ITEM

CRITICAL S4E_512_WD

S4E_512_TBCRITICAL

CRITICAL
CRITICAL

CRITICAL
CRITICAL

S4E_1TB_WD
S4E_1TB_TB

S4E_2TB_WD
S4E_2TB_SM

CRITICAL S4E_2TB_TB

B

338S00267 U7800 CRITICAL1

IC,SUPPLY,INTERSIL,ISL6277AHRZ,SVI2.0,QFN48

Harpoon

1339S00458 U3730

PART NUMBER

339S00428 ALL339S00458

IC,MODULE,WIFI/BT,MURATA,HARPOON,M,ES7.7,LGA385

USB-C Connector

IC,PMU,P650839,7X7MM.BGA168

IC,ISL95828A,IMVP8 CPU REG,QFN48,6X6MM

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IC,MODULE,WIFI/BT,HARPOON,USI,ES7.5,LGA385

TABLE_ALT_HEAD

TABLE_ALT_ITEM

4TB

CRITICALUA6001353S01229

335S00322 8

U7100 CRITICAL1353S00928

NAND,3DV4,512GBP,S4E,256G,SS,ULGA110

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

CRITICAL

S4E_4TB_SM

2TB TLC

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

335S00228
335S00247

8
8

NAND,3DV3,256GBT,S4E,256G,T,SLGA110

NAND,3DV3,256GBT,S4E,256G,SD,SLGA110

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400

CRITICAL
CRITICAL

TLC_2TB_TB
TLC_2TB_WD

A

Ocarina

8

2998-12556

1338S00410 CRITICAL
1338S00410 CRITICAL

CONN,RCPT,56+4,P=0.35,H=0.7,SHLD,THKR

IC,PMU,OCARINA,D2499A0,OTP-AG,WLCSP56

IC,PMU,OCARINA,D2499A0,OTP-AG,WLCSP56

U9000

CRITICALJ3300,JB500

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

A

SYNC_DATE=11/29/2017SYNC_MASTER=SEAN

PAGE TITLE

BOM Configuration 2

DRAWING NUMBER

051-02643

OCARINA_2U9500

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-0

PAGE

3 OF 200

SHEET

3 OF 131

1

SIZE

D

678

3 245

1

D

C

B

A

Pogo Pins

APN 870-01771

PG0410

POGO-2.3OD-4.63H-SM

SM

1

PG0411

POGO-2.3OD-4.63H-SM

SM

1

PG0420

POGO-2.3OD-4.63H-SM

SM

1

PG0421

POGO-2.3OD-4.63H-SM

SM

1

PG0430

POGO-2.3OD-4.63H-SM

SM

1

PG0471

POGO-2.3OD-4.63H-SM

SM

1

PG0470

POGO-2.3OD-4.63H-SM

APN 870-01772

SM

1

PG0400

POGO-2.3OD-4.06H-SM

SM

1

PG0401

POGO-2.3OD-4.63H-SM

Dummy Parts to act as bumpers

SM

1

C0402

1UF

21

10%

6.3V CERM 402

CKPLUS_WAIVE=TERMSHORTED

C0403

1UF

21

10% 6.3V CERM

CKPLUS_WAIVE=TERMSHORTED

402

C0404

1UF

21

10% 6.3V CERM

CKPLUS_WAIVE=TERMSHORTED

402

C0405

1UF

21

402

CERM

6.3V10%

CKPLUS_WAIVE=TERMSHORTED

C0406

1UF

21

6.3V10% CERM

CKPLUS_WAIVE=TERMSHORTED

402

APN 860-00392

3.4OD1.75ID-1.12H-SM 3.4OD1.75ID-1.12H-SM

3.4OD1.75ID-1.12H-SM

APN 806-06520

3.4OD1.75ID-1.45H-SM

APN 806-06521

APN 860-00469

Bumpers

860-00986

SMT Bosses

BS0400

1

USB-C Left
BOT side - North

BS0410

1

USB-C Right
BOT side - North

BS0420

1

DFR Touch
BOT side

BS0430

3.4OD1.75ID-1.9H-SM

1

DFR Display
BOT side - Left

BS0450

3.4OD1.75ID-1.9H-SM

1

Trackpad
BOT side - Left

BS0470

2.7X1.8R-1.4ID-0.91H-SM

1

APN 806-07958

TOUCH-COWLING-HOOK-X378

BS0472

1

SM

DFR Touch - TOP side

1 BM0400860-00948
5

11

eDP
TOP side - Left

bumper 1

bumper 2

bumper 3

bumper 4

BS0401

1

USB-C Left
BOT side - South

BS0411

3.4OD1.75ID-1.12H-SM

1

APN 806-06600

USB-C Right
BOT side - South

BS0480

3.4OD1.75ID-2.12H-SM

1

BS0431

3.4OD1.75ID-1.9H-SM

1

DFR Display
BOT side - Right

BS0441

3.4OD1.75ID-1.9H-SM

1

Keyboard
BOT side - Right

BS0471

2.7X1.8R-1.4ID-0.91H-SM

1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1 BM0411
CRITICAL

BM0484,BM0485,BM0486,BM0487,BM0488

BM0401,BM0402,BM0403,BM0406,BM0410,BM0407,BM0408,BM0483,BM0405,BM0409,BM0404

CRITICAL860-00954
CRITICAL860-00949

USB-C Right

BOT side - Left

OMIT_TABLE

APN 860-00500

BM0488

2.8OD1.2ID-3.5H-SM

1

2

eDP
TOP side - Right

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

2.8OD1.2ID-1.55H-SM

Rubber Mount

Standoffs

APN 860-00452

BM0400

3.09OD1.4ID-3.25H-SM

1
2

APN 860-00435

OMIT_TABLE

BM0401

2.8OD1.2ID-1.55H-SM

1
2

BM0402

2.8OD1.2ID-1.55H-SM

1
2

BM0403

2.8OD1.2ID-1.55H-SM

1
2

BM0404

2.8OD1.2ID-1.55H-SM

1
2

BM0405

2.8OD1.2ID-1.55H-SM

1
2

BM0483

2.8OD1.2ID-1.55H-SM

1
2

APN 860-00500

BM0484

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

BM0411

1

2

OMIT_TABLE

Shield Cans

806-11170

806-13328
806-13329
806-13324

1 SH0400 CRITICAL
2 CRITICAL806-13323 SH0401,SH0402
4

1806-13326

2

BM0406

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0407

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0408

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

BM0409

2.8OD1.2ID-1.55H-SM

1

2

OMIT_TABLE

BM0410

2.8OD1.2ID-1.55H-SM

1
2

OMIT_TABLE

OMIT_TABLE

APN 860-00500

BM0485

2.8OD1.2ID-3.5H-SM

1
2

BM0486

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

BM0487

2.8OD1.2ID-3.5H-SM

1
2

OMIT_TABLE

SHIELD,FENCE,DIPLEX,X1181

SHIELD,FENCE,NAND_L5_L6,X1181

SHIELD,FENCE,NAND_L5_L6_L7_L8,X1181

SHIELD,FENCE,H9M,X1181

SHIELD,FENCE,VRAM,X1181

SHIELD,FENCE,TR,RT,X1181

SHIELD,FENCE,NAND_L1_L2_L3_L4,X1181

SHIELD,FENCE,TR,LT,X1181

SHIELD,FENCE,DRAM,X1181

SHIELD,SLED,GPU,X1181

SHIELD,SLED,CPU,X1181

Diplexer Can

OMIT_TABLE

1

SH0400

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

NAND L5/L6

OMIT_TABLE

1

OMIT_TABLE

1

SH0402

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

NAND L7/L8

OMIT_TABLE

1

1

SH0404

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

H9M

1

OMIT_TABLE

SH0405

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

VRAM

1

OMIT_TABLE

SH0406

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

TR RT

1

OMIT_TABLE

SH0407

SM

SHIELD-DIPLEX-BLACK-X378A-X1099

NAND Right

OMIT_TABLE

1

1

SH0408

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

TR LT

1

SH0410

SM

OMIT_TABLE

SHIELD-DIPLEX-BLACK-X378A-X1099

DRAM

OMIT_TABLE

1

SH0411

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

CPU/GPU Sleds

OMIT_TABLE

1

SH0413

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SH0401,SH0402,SH0403,SH0404

SH0405
SH0406
SH0407

SH0408,SH0409

SH0410

SH0411,SH04122 CRITICAL
SH0413,SH0415
SH0414,SH0416

CRITICAL
CRITICAL806-13325 1
CRITICAL
CRITICAL806-13327 1
CRITICAL
CRITICAL1

CRITICAL806-13996 2
CRITICAL806-13997 2

BOM_COST_GROUP=MECHANICALS

SH0401

SM

SH0403

SM

OMIT_TABLE

SH0409

SM

OMIT_TABLE

1

SH0412

OMIT_TABLE

1

SH0414

SM

OMIT_TABLE

SM

S4E_X6
S4E_X8806-13323

Shield Can TH

APN 998-2691

DRAM

VRAM

SSD Right

TH0402

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0403

1

SL-1.2X0.4-1.5X0.7

TH0450

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0451

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0400

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0401

TH-NSPTH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0460

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0461

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0440

TH-NSP

1

SL-1.2X0.4-1.5X0.7

TH0441

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SSD Left

1

1

1

1

TH0407

TH-NSP

TH0416

TH-NSP

TH0415

TH-NSP

TH0406

TH-NSP

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

1

1

1

1

TH0413

TH-NSP

TH0412

TH-NSP

TH0417

TH-NSP

TH0414

TH-NSP

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

SL-1.2X0.4-1.5X0.7

H9M

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

TH0409

TH-NSP

TH0408

TH-NSP

TBT Left

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

TH0410

TH-NSP

TH0411

TH-NSP

TBT Right

1

SL-1.2X0.4-1.5X0.7

1

SL-1.2X0.4-1.5X0.7

OMIT_TABLE

1

SH0415

SM

OMIT_TABLE

1

SH0416

SM

SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099

SYNC_MASTER=ZIFENG_CONSTRAINTS SYNC_DATE=03/03/2017

PAGE TITLE

TH0420

TH-NSP

TH0421

TH-NSP

PD Parts

DRAWING NUMBER

051-02643

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

4.0.0

BRANCH

evt-0

PAGE

4 OF 200

SHEET

4 OF 131

D

C

B

A

SIZE

D

8

67

35 4

2

1

D

C

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

118 13

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

E8

F6

E5

J9

D8
E6
D5

J8

A8
B6
A5
B4

B8
C6
B5
D4

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 1 OF 13

CRITICAL

OMIT_TABLE

DMI

PEG_RCOMP

PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

678

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9

G2

D25
F24
D23
F22
D21
F20
D19
F18
E17
E16
E15
E14
E13
E12
E11
E10

E25
E24
E23
E22
E21
E20
E19
E18
D17
F16
D15
F14
D13
F12
D11
F10

CPU_PEG_RCOMP

PEG_GPU_D2R_N<0>
PEG_GPU_D2R_N<1>
PEG_GPU_D2R_N<2>
PEG_GPU_D2R_N<3>
PEG_GPU_D2R_N<4>
PEG_GPU_D2R_N<5>
PEG_GPU_D2R_N<6>
PEG_GPU_D2R_N<7>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_T_D2R_N<0>
PCIE_TBT_T_D2R_N<1>
PCIE_TBT_T_D2R_N<2>
PCIE_TBT_T_D2R_N<3>

PEG_GPU_D2R_P<0>
PEG_GPU_D2R_P<1>
PEG_GPU_D2R_P<2>
PEG_GPU_D2R_P<3>
PEG_GPU_D2R_P<4>
PEG_GPU_D2R_P<5>
PEG_GPU_D2R_P<6>
PEG_GPU_D2R_P<7>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_T_D2R_P<0>
PCIE_TBT_T_D2R_P<1>
PCIE_TBT_T_D2R_P<2>
PCIE_TBT_T_D2R_P<3>

From Intel EDS
PEG RCOMP Range = 24.76,25.25

Voltage = VCCIO (Page 121, Note 3)

PPVCCIO_S0_CPU

1

R0510

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.G2:5mm

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

117

IN

5 8 10 115

117

NC_DDI1_ML_C_N<0>

NC_DDI1_ML_C_P<0>

117

117

NC_DDI1_ML_C_N<1>
NC_DDI1_ML_C_P<1>

117

117

NC_DDI1_ML_C_N<2>
NC_DDI1_ML_C_P<2>

117

117

NC_DDI1_ML_C_N<3>
NC_DDI1_ML_C_P<3>

117

NC_DDI2_ML_C_N<0>

117

NC_DDI2_ML_C_P<0>

117

117

NC_DDI2_ML_C_N<1>

117

NC_DDI2_ML_C_P<1>
NC_DDI2_ML_C_N<2>

117

NC_DDI2_ML_C_P<2>

117

117

NC_DDI2_ML_C_N<3>

117

NC_DDI2_ML_C_P<3>

117

NC_DDI3_ML_N<2>
NC_DDI3_ML_P<2>

117

117

NC_DDI3_ML_N<3>
NC_DDI3_ML_P<3>

117

NC_DDI3_ML_N<0>

117

117

NC_DDI3_ML_P<0>

117

NC_DDI3_ML_N<1>
NC_DDI3_ML_P<1>

117

Port D pins out of order
to match Intel symbol.

K37
K36

J34

J35
H36
H37

J38

J37

H33
H34

G38

F37
F35

F34
E36
E37

E33

F33
B33
C33

D34
C34
B34
B36

3 245

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

DDI3_TXN2
DDI3_TXP2
DDI3_TXN3
DDI3_TXP3

DDI3_TXN0
DDI3_TXP0
DDI3_TXN1
DDI3_TXP1

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 11 OF 13

CRITICAL

OMIT_TABLE

EDP

DIGITAL DISPLAY INTERFACES

DISP_RCOMP

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

DDI1_AUXN
DDI1_AUXP

DDI2_AUXN
DDI2_AUXP

DDI3_AUXN
DDI3_AUXP

B26
C26

E29
E28
B29
B28

D29
F28
A29
C28

D37
A33

E27
D27

E26
F26

B27
A27

NC

DP_INT_IG_AUX_N
DP_INT_IG_AUX_P

DP_INT_IG_ML_N<0>
DP_INT_IG_ML_N<1>
DP_INT_IG_ML_N<2>
DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_P<1>
DP_INT_IG_ML_P<2>
DP_INT_IG_ML_P<3>

CPU_EDP_RCOMP

NC_DDI1_AUXCH_C_N
NC_DDI1_AUXCH_C_P

NC_DDI2_AUXCH_C_N
NC_DDI2_AUXCH_C_P

NC_DDI3_AUXCH_N
NC_DDI3_AUXCH_P

117

117

117

117

117

117

1

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

118 93

PPVCCIO_S0_CPU

1

R0530

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.D37:5mm

D

5 8 10

115

C

B

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TXN6
PEG_TXN7
PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0

PEG_TXP1

PEG_TXP2

PEG_TXP3

PEG_TXP4

PEG_TXP5

PEG_TXP6

PEG_TXP7

PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

A25
C24
A23
C22
A21
C20
A19
C18
B17
B16
B15
B14
B13
B12
B11
B10

B25
B24
B23
B22
B21
B20
B19
B18
A17
C16
A15
C14
A13
C12
A11
C10

PEG_GPU_R2D_C_N<0>
PEG_GPU_R2D_C_N<1>
PEG_GPU_R2D_C_N<2>
PEG_GPU_R2D_C_N<3>
PEG_GPU_R2D_C_N<4>
PEG_GPU_R2D_C_N<5>
PEG_GPU_R2D_C_N<6>
PEG_GPU_R2D_C_N<7>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_T_R2D_C_N<0>
PCIE_TBT_T_R2D_C_N<1>
PCIE_TBT_T_R2D_C_N<2>
PCIE_TBT_T_R2D_C_N<3>

PEG_GPU_R2D_C_P<0>
PEG_GPU_R2D_C_P<1>
PEG_GPU_R2D_C_P<2>
PEG_GPU_R2D_C_P<3>
PEG_GPU_R2D_C_P<4>
PEG_GPU_R2D_C_P<5>
PEG_GPU_R2D_C_P<6>
PEG_GPU_R2D_C_P<7>
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_R2D_C_P<1>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_R2D_C_P<3>
PCIE_TBT_T_R2D_C_P<0>
PCIE_TBT_T_R2D_C_P<1>
PCIE_TBT_T_R2D_C_P<2>
PCIE_TBT_T_R2D_C_P<3>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

117

TP-P5
TP-P5

TP-P5
TP-P5
TP-P5

TP0501
TP0502

TP0503
TP0504
TP0505

TP
TP

TP
TP
TP

U0500

CFL-H-DDR4-IL

BGA

1
1

1
1
1

CPU_DC_B2_C1
CPU_DC_B38_C38

CPU_DC_BR2_BR1
CPU_DC_C1_B2
CPU_DC_C38_B38

NC

NC

NC

NC

BR33

AT13

AW13

RSVD IST_TRIG

B2

RSVD

B38

RSVD

BP1

RSVD

BR2

RSVD

C1

RSVD

C38

SKTOCC*
ZVM*

MSM*

45W

SYM 13 OF 13

PROC_TRIGIN

PROC_TRIGOUT

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDR_VTT_CNTL

PM_DOWN

Impedance Spectrum Tool

E3

H23
J23

G27
G25
G29

BT13
BP31

CPU_IST_TRIG

PCH_CPU_TRIGGER
CPU_PCH_TRIGGER_R

PCH_DISPA_BCLK
PCH_DISPA_SDO
CPU_PROC_AUD_SDO_R

PM_MEMVTT_EN
CPU_PCH_PM_DOWN_R

Each corner of CPU has two testpoints.

5

5

IN

IN
IN

5

OUT

13

20

20

1

TP-P6

1

TP-P6

PLACE_NEAR=TP0506.1:5mm

119 74

A

TP0506

A

TP0507

B

Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP's on each corner.

R0524

5

CPU_PCH_TRIGGER_R

30

5%

1/20W

MF

201

CPU_PCH_TRIGGER

21

OUT

13

A

5

5

BOM_COST_GROUP=CPU & CHIPSET

CPU_PCH_PM_DOWN_R

CPU_PROC_AUD_SDO_R

SYNC_MASTER=ZIFENG SYNC_DATE=09/07/2017

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R0525

20

5%

1/20W

MF

201

R0526

20

5%

1/20W

MF

201

CPU_PCH_PM_DOWN

21

21

PCH_DISPA_SDI

Apple Inc.

13

OUT

20

OUT

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

5 OF 200

SHEET

5 OF 131

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

8 11 115

8 11 46 115

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

PP1V05_S0SW
PP1V05_S3

46

CPU_PROCHOT_L

IN

119 46

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1K

5%

1/20W

MF

201

NOSTUFF

R0647

1K

5%

1/20W

MF

201

CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1K

5%

1/20W

MF

201

1

2

1

2

R0648

NOSTUFF

1

R0643

1K

5%
1/20W
MF
201

2

NOSTUFF

R0641

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0640

1K

5%
1/20W
MF
201

2

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>

CPUCFG5_PDCPUCFG6_PD

1

R0645

1K

5%
1/20W
MF
201

2

EDP:YES

R0644

1K

5%

1/20W

MF

201

1

2

1

2

R0646

1K

5%

1/20W

MF

201

1

2

CPU_CFG<2>

NOSTUFF

1

R0642

1K

5%
1/20W
MF
201

2

18 6

18 6

18 6

18 6

18 6

PP0600
PP0601

PP0602
PP0603

18 6

18 6

18 6

18 6

18 6

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

OUT

1

CPU_RSVD_R14

1

CPU_RSVD_N29

1

CPU_RSVD_AE29

1

CPU_RSVD_AA14

TP0619

1

R0605

1K

1%
1/16W
MF-LF
402

2

A

TP-P6

NOSTUFF

1

R0604

1K

1%
1/16W
MF-LF
402

2

1

TP_CPU_RSVD_TP_D1

PPVCC_S0_CPU

8 58 115

6

6

6

6

1

R0601

1K

1%
1/16W
MF-LF
402

2

6

6

6

6

CPU_RSVD_R14
CPU_RSVD_N29
CPU_RSVD_AE29
CPU_RSVD_AA14

77

OUT

PLACE_NEAR=U0500.BR30:5mm

R0603

499

201

1%
1/20W

MF

46 13

21

13

13

121 119 13

118 12

118 12

118 12

118 12

118 12

118 12

BI

IN
IN
IN

IN
IN

IN
IN

IN
IN

D1

V30
V12
V29
Y35

R14

N29
AE29
AA14

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC
CPU_RESET_L
CPU_PWRGD

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

CRITICAL
OMIT_TABLE

RSVD_TP

VSS
VSS
VSS
VCC

RSVD
RSVD
RSVD
RSVD

PLACE_NEAR=U0500.BT31:157mm

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 12 OF 13

RESERVED

CFG_RCOMP

(IPU)

(IPU)

R0611

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD
RSVD
RSVD

RSVD

10K

5%
1/16W
MF-LF

402

BT25
BP23

BN22
BN23
BP22

AU13
AY13
J24
J3

BN33

U0500

CFL-H-DDR4-IL

BN1

NC

BM30

BT34

BR30

BM34

BP35
BT31

1

2

PROC_SELECT*

CATERR*

PECI

PROCHOT*

J31

THERMTRIP*

PM_SYNC
RESET*
PROCPWRGD

D31

CLK24N

E31

CLK24P

C36

PCI_BCLKN

D35

PCI_BCLKP

A32

BCLKN

B31

BCLKP

CRITICAL
OMIT_TABLE

CPU_CFG_RCOMP
CPU_CFG<16>

CPU_CFG<18>
CPU_CFG<17>
CPU_CFG<19>

NC
NC
NC
NC

NC

BGA
45W

SYM 2 OF 13

THERMALPWRCLOCK

18 6

18

1

TP-P5

1

TP-P5

DDR3

(IPU)
(IPU)

(IPD)
(IPU)

(IPU)

(IPU)

JTAG

TP

TP0617

TP

TP0618

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

PROC_PRDY*

PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

(IPU)
(IPU)
(IPU)
(IPU)

BPM0*
BPM1*
BPM2*
BPM3*

G1
H1
J2

BP27
BL30

BR28
BP28
BP30

BL32
BT28

BR27
BT27
BM31
BT30

1

R0690

49.9

1%
1/16W
MF-LF
402

2

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

OUT

IN

IN
IN
IN

IN

OUT

BI
BI
BI
BI

18

18

18

18

1

R0614

100

2

1%
1/16W
MF-LF
402

121 18 13

121 18 13

121 18

121 18

121 18 13

121 18

121 18

1

R0613

121

1%
1/16W
MF-LF
402

2

1

R0612

121

1%
1/16W
MF-LF
402

2

D

C

B

TP0601
TP0602
TP0603
TP0604
TP0605
TP0606
TP0607
TP0608
TP0609
TP0610
TP0611
TP0612
TP0613
TP0614
TP0615
TP0616

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

1

CPU_CFG<0>

1

CPU_CFG<1>

1

CPU_CFG<2>

1

CPU_CFG<3>

1

CPU_CFG<4>

1

CPU_CFG<5>

1

CPU_CFG<6>

1

CPU_CFG<7>

1

CPU_CFG<8>

1

CPU_CFG<9>

1

CPU_CFG<10>

1

CPU_CFG<11>

1

CPU_CFG<12>

1

CPU_CFG<13>

1

CPU_CFG<14>

1

CPU_CFG<15>

NC
NC

BN25
BN27
BN26
BN28
BR20

BM20

BT20
BP20
BR23
BR22

BT23

BT22

BM19

BR19

BP19

BT19

G3

G13

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD
RSVD

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

RSVD
RSVD

RSVD

RSVD

RSVD_TP
RSVD_TP

VSS
VSS

VSS
VSS

RSVD
RSVD
RSVD

BR35
BR31

BN35

C30

BT2
BR1

W3
W2

V6
W1

H24
E30
F30

NC
NC

NC

NC

TP_CPU_RSVD_TP_BT2
CPU_DC_BR1_BR2

NC
NC
NC

TP-P5

TP-P5

B

1

TP

1

TP0620

TP

TP0600

A

8

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM

CPUPEG:X8X8 CPUCFG5_PD

CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD

TABLE_BOMGROUP_ITEM

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

PAGE TITLE

A

CPU Clock/Misc/JTAG/CFG

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

6 OF 200

SHEET

6 OF 131

1

SIZE

D

D

C

B

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

26 23 22

26 23 22

21

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT

IN

OUT

MEM_A_DQ<45>
MEM_A_DQ<41>
MEM_A_DQ<44>
MEM_A_DQ<40>
MEM_A_DQ<47>
MEM_A_DQ<43>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<53>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<48>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<35>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<26>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<0>
MEM_A_DQ<5>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<13>
MEM_A_DQ<8>
MEM_A_DQ<14>
MEM_A_DQ<9>
MEM_A_DQ<15>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<16>
MEM_A_DQ<19>

MEM_A_PAR
MEM_A_ALERT_L
CPU_DIMM_VREFCA
MEM_A_ACT_L

BR6

DDR0_DQ0

BT6

DDR0_DQ1

BP3

DDR0_DQ2

BR3

DDR0_DQ3

BN5

DDR0_DQ4

BP6

DDR0_DQ5

BP2

DDR0_DQ6

BN3

DDR0_DQ7

BL4

DDR0_DQ8

BL5

DDR0_DQ9

BL2

DDR0_DQ10

BM1

DDR0_DQ11

BK4

DDR0_DQ12

BK5

DDR0_DQ13

BK1

DDR0_DQ14

BK2

DDR0_DQ15

BG4

DDR0_DQ16

BG5

DDR0_DQ17

BF4

DDR0_DQ18

BF5

DDR0_DQ19

BG2

DDR0_DQ20

BG1

DDR0_DQ21

BF1

DDR0_DQ22

BF2

DDR0_DQ23

BD2

DDR0_DQ24

BD1

DDR0_DQ25

BC4

DDR0_DQ26

BC5

DDR0_DQ27

BD5

DDR0_DQ28

BD4

DDR0_DQ29

BC1

DDR0_DQ30

BC2

DDR0_DQ31

AB1

DDR0_DQ32

AB2

DDR0_DQ33

AA4

DDR0_DQ34

AA5

DDR0_DQ35

AB5

DDR0_DQ36

AB4

DDR0_DQ37

AA2

DDR0_DQ38

AA1

DDR0_DQ39

V5

DDR0_DQ40

V2

DDR0_DQ41

U1

DDR0_DQ42

U2

DDR0_DQ43

V1

DDR0_DQ44

V4

DDR0_DQ45

U5

DDR0_DQ46

U4

DDR0_DQ47

R2

DDR0_DQ48

P5

DDR0_DQ49

R4

DDR0_DQ50

P4

DDR0_DQ51

R5

DDR0_DQ52

P2

DDR0_DQ53

R1

DDR0_DQ54

P1

DDR0_DQ55

M4

DDR0_DQ56

M1

DDR0_DQ57

L4

DDR0_DQ58

L2

DDR0_DQ59

M5

DDR0_DQ60

M2

DDR0_DQ61

L5

DDR0_DQ62

L1

DDR0_DQ63

DDR0_PAR

AG3
AU5

DDR0_ALERT*
DDR_VREF_CA

BN13

AU3

DDR0_ACT*

U0500

BGA

SYM 3 OF 13

45W

CFL-H-DDR4-IL

CRITICAL
OMIT_TABLE

DDR0_CKN0
DDR0_CKP0
DDR0_CKE0

DDR0_CKN1
DDR0_CKP1
DDR0_CKE1

DDR0_CKN2
DDR0_CKP2
DDR0_CKE2

DDR0_CKN3
DDR0_CKP3
DDR0_CKE3

DDR0_CS0*
DDR0_CS1*
DDR0_CS2*
DDR0_CS3*

DDR0_ODT0
DDR0_ODT1
DDR0_ODT2
DDR0_ODT3

MEMORY CHANNEL DDR0

DDR0_ECC0
DDR0_ECC1
DDR0_ECC2
DDR0_ECC3
DDR0_ECC4
DDR0_ECC5
DDR0_ECC6
DDR0_ECC7

DDR0_DQSN0
DDR0_DQSN1
DDR0_DQSN2
DDR0_DQSN3
DDR0_DQSN4
DDR0_DQSN5
DDR0_DQSN6
DDR0_DQSN7
DDR0_DQSN8

DDR0_DQSP0
DDR0_DQSP1
DDR0_DQSP2
DDR0_DQSP3
DDR0_DQSP4
DDR0_DQSP5
DDR0_DQSP6
DDR0_DQSP7
DDR0_DQSP8

VSS

AG2
AG1
AT1

AK1
AK2
AT2

AK3
AL3
AT3

AL1
AL2
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

U38

BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2

BR5
BL3
BG3
BD3
AA3
U3
P3
L3
BA3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3
AY3

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC

NC

678

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
MEM_A_CKE<1>

NC_MEM_A_CKE<2>

NC_MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>

MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_P<4>
MEM_A_DQS_P<3>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

26

26

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

3 245

BT11

125

118 26 23 22

118 26 23 22

26 23 22

118 26

118 26

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 25 24

26 25 24 26 23 22

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT

INOUT

MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<23>
MEM_B_DQ<19>
MEM_B_DQ<21>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<12>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<8>
MEM_B_DQ<10>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<7>
MEM_B_DQ<1>
MEM_B_DQ<4>
MEM_B_DQ<0>
MEM_B_DQ<25>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<26>
MEM_B_DQ<31>
MEM_B_DQ<24>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<35>
MEM_B_DQ<32>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<60>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<53>
MEM_B_DQ<41>
MEM_B_DQ<46>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<42>
MEM_B_DQ<47>
MEM_B_DQ<40>
MEM_B_DQ<45>

MEM_B_PAR
MEM_B_ALERT_L

DDR1_DQ0

BR11

DDR1_DQ1

BT9

DDR1_DQ2

BR8

DDR1_DQ3

BP11

DDR1_DQ4

BN11

DDR1_DQ5

BP8

DDR1_DQ6

BN8

DDR1_DQ7

BL12

DDR1_DQ8

BL11

DDR1_DQ9

BL8

DDR1_DQ10

BJ8

DDR1_DQ11

BJ11

DDR1_DQ12

BJ10

DDR1_DQ13

BL7

DDR1_DQ14

BJ7

DDR1_DQ15

BG11

DDR1_DQ16

BG10

DDR1_DQ17

BG8

DDR1_DQ18

BF8

DDR1_DQ19

BF11

DDR1_DQ20

BF10

DDR1_DQ21

BG7

DDR1_DQ22

BF7

DDR1_DQ23

BB11

DDR1_DQ24

BC11

DDR1_DQ25

BB8

DDR1_DQ26

BC8

DDR1_DQ27

BC10

DDR1_DQ28

BB10

DDR1_DQ29

BC7

DDR1_DQ30

BB7

DDR1_DQ31

AA11

DDR1_DQ32

AA10

DDR1_DQ33

AC11

DDR1_DQ34

AC10

DDR1_DQ35

AA7

DDR1_DQ36

AA8

DDR1_DQ37

AC8

DDR1_DQ38

AC7

DDR1_DQ39

W8

DDR1_DQ40

W7

DDR1_DQ41

V10

DDR1_DQ42

V11

DDR1_DQ43

W11

DDR1_DQ44

W10

DDR1_DQ45

V7

DDR1_DQ46

V8

DDR1_DQ47

R11

DDR1_DQ48

P11

DDR1_DQ49

P7

DDR1_DQ50

R8

DDR1_DQ51

R10

DDR1_DQ52

P10

DDR1_DQ53

R7

DDR1_DQ54

P8

DDR1_DQ55

L11

DDR1_DQ56

M11

DDR1_DQ57

L7

DDR1_DQ58

M8

DDR1_DQ59

L10

DDR1_DQ60

M10

DDR1_DQ61

M7

DDR1_DQ62

L8

DDR1_DQ63

AJ7

DDR1_PAR

AR8

DDR1_ALERT*

U0500

BGA

SYM 4 OF 13

45W

CFL-H-DDR4-IL

CRITICAL

OMIT_TABLE

DDR1_CKN0
DDR1_CKP0
DDR1_CKE0

DDR1_CKN1
DDR1_CKP1
DDR1_CKE1

DDR1_CKN2
DDR1_CKP2
DDR1_CKE2

DDR1_CKN3
DDR1_CKP3
DDR1_CKE3

DDR1_CS0*
DDR1_CS1*
DDR1_CS2*
DDR1_CS3*

DDR1_ODT0
DDR1_ODT1
DDR1_ODT2
DDR1_ODT3

MEMORY CHANNEL DDR1

DDR1_ECC0
DDR1_ECC1
DDR1_ECC2
DDR1_ECC3
DDR1_ECC4
DDR1_ECC5
DDR1_ECC6
DDR1_ECC7

DDR1_DQSN0
DDR1_DQSN1
DDR1_DQSN2
DDR1_DQSN3
DDR1_DQSN4
DDR1_DQSN5
DDR1_DQSN6
DDR1_DQSN7
DDR1_DQSN8

DDR1_DQSP0
DDR1_DQSP1
DDR1_DQSP2
DDR1_DQSP3
DDR1_DQSP4
DDR1_DQSP5
DDR1_DQSP6
DDR1_DQSP7
DDR1_DQSP8

VSS

AN9
AM9
AT8

AM8
AM7
AT10

AM10
AM11
AT7

AJ11
AJ10
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

Y38

AW11
AY11
AY8
AW8

AY10
AW10
AY7
AW7

BN9
BL9
BG9
BC9
AC9

W9

R9

M9
AY9

BP9

BJ9
BF9
BB9
AA9
V9

P9

L9
AW9

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC
NC

NC

NC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>

NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
MEM_B_CKE<1>

NC_MEM_B_CKE<2>

NC_MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

NC
NC
NC
NC

MEM_B_DQS_N<2>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>

MEM_B_DQS_P<2>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
MEM_B_DQS_P<5>

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

118 26 25 24

118 26 25 24

26 25 24

118 26

118 26

26 25 24

26

26

26 25 24

26 25 24

26 25 24

26 25 24

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

125

1

D

C

B

A

21

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

26 23 22

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CPU_DIMMB_VREFDQ

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

NC

DDR0_VREF_DQ

BP13

DDR1_VREF_DQ

BR13

AH3

DDR0_MA0

AP4

DDR0_MA1
DDR0_MA2

AN4

DDR0_MA3

AP5

DDR0_MA4

AP2

DDR0_MA5

AP1

DDR0_MA6

AP3

DDR0_MA7

AN1

DDR0_MA8

AN3

DDR0_MA9

AT4

DDR0_MA10

AH2

DDR0_MA11

AN2

DDR0_MA12

AU4

DDR0_MA13

AE3

DDR0_MA14

AG4

DDR0_MA15

AD1

DDR0_MA16

AH4

RSVD
RSVD
RSVD

DDR0_BA0

DDR0_BA1
DDR0_BG0
DDR0_BG1

AJ8
B30
BH30

AH5
AH1
AU1
AU2

NC
NC
NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

OUT
OUT
OUT
OUT

26 25 24

26 23 22

26 23 22

26 23 22

26 23 22

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

26 25 24

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

MEM_B_ACT_L

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

AT9

AJ9
AK6
AK5

AL5
AL6

AM6

AN7

AN10

AN8

AR11

AH7

AN11
AR10

AF9

AH11

AF8

AH10

DDR1_ACT*

DDR1_MA0
DDR1_MA1
DDR1_MA2
DDR1_MA3
DDR1_MA4
DDR1_MA5
DDR1_MA6
DDR1_MA7
DDR1_MA8
DDR1_MA9
DDR1_MA10
DDR1_MA11
DDR1_MA12
DDR1_MA13
DDR1_MA14
DDR1_MA15
DDR1_MA16

RSVD

RSVD

DDR1_BA0

DDR1_BA1
DDR1_BG0
DDR1_BG1

BK28

BJ28

AH8
AH9
AR9
AR7

NC

NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

BOM_COST_GROUP=CPU & CHIPSET

OUT
OUT
OUT
OUT

26 25 24

26 25 24

26 25 24

26 25 24

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

A

CPU DDR4 Interfaces

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

051-02643

REVISION

4.0.0

4.0.0

BRANCH

evt-0

evt-0

PAGE

7 OF 200

7 OF 200

SHEET

7 OF 131

7 OF 131

8

67

35 4

2

1

678

3 245

1

D

C

B

A

6 8 58 115

PP1V05_S3

6 8 11

46 115

8

CPU_VCCST_PWRGD_R

6 11 115

PP1V05_S0SW

PULL-UPS FOR SENSE LINES

1

R0864

100

5%
1/20W
MF
201

2

PPVCC_S0_CPU

1

1

R0865

100

5%
1/20W
MF

2

201

R0866

100

5%
1/20W
MF

2

201

VCC
AP37
AP36
AP35
AP32
AP31
AP30
AP13

AN38
AN37
AN36
AN35
AN34
AN33
AN32
AN31
AN14

AN13
AM36
AM35
AM34
AM33
AM32
AM31
AM30
AM29
AM14
AM13

AL38
AL37
AL36
AL35
AL32
AL31
AL30
AL29

AL13
AK38
AK37
AK36
AK35
AK34
AK33
AK32
AK31

AJ36
AJ35
AJ34
AJ33
AJ32
AJ31
AJ30
AJ29

AJ14
AH32
AH31
AH30
AH29
AH14
AH13

AG36
AG35
AG34
AG33
AG32
AG31
AG14

AF34
AF33
AF32
AF31
AF30
AF29

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

H30

VCCST

H13

VCCST_PWRGD

G30

VCCSTG

H29

VCCSTG

PPVCCGT_S0_CPU
PPVCCSA_S0_CPU

PPVCCIO_S0_CPU

1

R0861

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.H14:50.8mm
PLACE_NEAR=U0500.AG37:50.8mm
PLACE_NEAR=U0500.AH38:50.8mm
PLACE_NEAR=U0500.M38:50.4mm

CPU_VCCIOSENSE_P
CPU_VCCSASENSE_P

CPU_VCCGTSENSE_P

CPU_VCCSENSE_P

U0500

BGA

SYM 6 OF 13

POWER

45W

CFL-H-DDR4-IL

CRITICAL

OMIT_TABLE

VCCSA_SENSE
VSSSA_SENSE

PPVCC_S0_CPU

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCIO_SENSE

VSSIO_SENSE

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCPLL
VCCPLL

VCCPLL_OC
VCCPLL_OC
VCCPLL_OC

6 8 58 115

8 58 115

8 58 115

5 8 10 115

78 8

69 8

69 8

69 8

PPVCCIO_S0_CPU

AG12AP38
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27

H14
J14

J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36

M38
M37

H28
J28

BH13
G11
BJ13

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

PPVCCSA_S0_CPU

CPU_VCCSASENSE_P

CPU_VCCSASENSE_N

PP1V05_S3

Place C0802 on bottom side of U0500
Place C0803 on bottom side of U0500
PP1V2_S0SW

80 46

IN

6 8 11 46 115

PP1V05_S3

69

BI

6 8 11 46 115

5 8 10 115

OUT
OUT

8 58 115

OUT
OUT

69 8

69 9

11 115

CPU_VIDSOUT

1

C0802

1UF

20%

2

6.3V
X6S-CERM
0201

PP1V05_S3

78 8

78 9

1

C0803

1UF

20%

2

6.3V
X6S-CERM
0201

NOSTUFF

NOSTUFF

1

R0802

100

5%
1/20W
MF
201

2

69

69

CPU_VIDALERT_L

IN

CPU_VIDSCLK

OUT

R0812

0

5%
1/16W
MF-LF

402

115

PLACE_NEAR=U0500.H13:1MM

1

R0840

1K

1%
1/16W
MF-LF
402

2

1

R0842

100

5%
1/20W
MF
201

2

PP1V2_S3_CPUDDR

115

6 8 58 115

PPVCC_S0_CPU

69 8

OUT

69 9

OUT

1

R0800

56.2

1%
1/20W
MF
201

2

R0810

220

1/20W

R0811

0

5%
1/16W
MF-LF

402

21

PLACE_NEAR=U0500.H13:1MM

R0841

60.4

1/20W

5%
MF

201

21

1%
MF

201

21

TP0800
TP0801

6 8 58 115

21

PPVCC_S0_CPU

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

1

TP
TP

TP_CPU_RSVD_TP75

TP-P5

1

TP_CPU_RSVD_TP76

TP-P5

CPU_VCCST_PWRGD_RCPU_VCCST_PWRGD

NC
NC
NC
NC

BL31
BL34
AP14
AP29

AA6

AE12

AF5

AF6
AG5
AG9

AJ12

AL11

AP6

AP7

AR12

AR6

AT12

AW6

AY6

J5
J6

K12

K6

L12

L6
R6
T6

W6

Y12

U36

V13

AG37
AG38

BH31
BH32
BH29

Y7

Y8
E2
E1

Y9

Y13

W4

W34

Y10

W5

Y14

W12

Y37

W33

Y11

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AB30
AB31
AA38
AB29

V14
V31
V32
V33
V34
V35
V36
V37

V38
W13
W14

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
VCC

VCC_SENSE
VSS_SENSE

VIDALERT*
VIDSCK
VIDSOUT

VSS

VSS
RSVD_TP
RSVD_TP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 5 OF 13

CRITICAL

OMIT_TABLE

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PPVCC_S0_CPU

AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y36

6 8 58 115

BOM_COST_GROUP=CPU & CHIPSET

PPVCCGT_S0_CPU

8
58 115

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37

AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36

AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE33

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

PAGE TITLE

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 7 OF 13

POWER

CRITICAL

OMIT_TABLE

VCCGT_SENSE

VSSGT_SENSE

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

CPU Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BP37
BP38
BR15
BR16
BR17
BR37
BT15
BT16
BT17
BT37

AH38

CPU_VCCGTSENSE_P

AH37

CPU_VCCGTSENSE_N

DRAWING NUMBER

051-02643

REVISION

BRANCH

PAGE

8 OF 200

SHEET

8 OF 131

4.0.0
evt-0

D

C

B

OUT
OUT

SYNC_DATE=02/24/2017SYNC_MASTER=ZIFENG_CONSTRAINTS

69 8

69 9

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

A3
A4
A6

A9
A10
A12
A14
A16
A18
A20
A22
A24
A26
A34
A36
A37

AA12
AA29
AA30

AB6
AB33
AB34

AC1
AC2
AC3
AC4
AC5

AC6
AC12
AC37
AC38

AD6

AD7

AD8

AD9
AD10
AD11
AD12
AD29
AD30

AE6
AE33
AE34

AF1
AF2
AF3

AF4
AF12
AF13
AF14

AG6
AG7

AG8
AG10
AG11
AG13
AG29
AG30

AH6
AH12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 8 OF 13

GROUND

CRITICAL
OMIT_TABLE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH33
AH34
AH35
AH36
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ13
AJ37
AJ38
AK4
AK29
AK30
AL4
AL7
AL8
AL9
AL10
AL12
AL14
AL33
AL34
AM1
AM2
AM3
AM4
AM5
AM12
AM37
AM38
AN5
AN6
AN12
AN29
AN30
AP8
AP9
AP10
AP11
AP12
AP33
AP34
AR1
AR2
AR3
AR4
AR5
AR13
AR14
AR29
AR30
AR31
AR32
AR33
AR34
AR35

AR36
AR37
AR38

AT6
AT29
AT30

AU6
AU7
AU8

AU9
AU10
AU11
AU12
AU33
AU34

AV37
AV38

AW1
AW2
AW3
AW4

AW5
AW12
AW29
AW30

AY12
AY14
AY33
AY34

B3

B9
B37
BA6
BA7
BA8
BA9

BA10
BA11
BA12
BA37
BA38

BB1
BB2
BB3
BB4
BB5
BB6

BB12
BB29
BB30

BC6
BC12
BC13
BC14
BC33
BC34

BD6

BD7

BD8

BD9
BD10
BD11
BD12
BD37
BD38

BE1
BE2
BE3
BE4
BE5

BE6
BE29
BE30

BF6
BF12
BF33
BF34

BG6
BG12
BG13
BG14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA
45W

SYM 9 OF 13

GROUND

CRITICAL

OMIT_TABLE

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BG37
BG38
BH1
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
BH10
BH11
BH12
BH14
BJ12
BJ14
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK6
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BL6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BM2
BM3
BM5
BM6
BM7
BM8
BM9
BM11
BM12
BM13
BM14
BM18
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM33
BM35
BM38
BN2
BN19
C37
D3
D28
D30
D33
L33

A28

A30
BN4
BN7

BN12
BN14
BN18
BN20
BN21
BN24
BN29
BN30
BN31
BN34

BP7

BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BR7
BR9

BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36
BR38

BT3

BT4

BT5

BT8

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32
BT35
BT36

C2
C5
C8

C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31

D6

D9
D10
D12
D14
D16
D18
D20
D22
D24
D26
D38

E4

E9
E34
E35
E38

F2

F3

F4

F5

F8

F9
F11
F13
F15
F17
F19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

CFL-H-DDR4-IL

BGA

45W

SYM 10 OF 13

GROUND

CRITICAL
OMIT_TABLE

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F21
F23
F25
F27
F29
F31
F36
G4
G5
G6
G8
G9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
H11
H12
H18
H22
H25
H32
H35
J4
J7
J10
J18
J22
J25
J32
J33
J36
K1
K2
K3
K4
K5
K7
K8
K9
K10
K11
K38
L29
L30
L34
M6
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N33
N34
P6
P12
P37
P38
R12
R29
R30
T1
T2
T3
T4
T5
T7
T8
T9
T10
T11
T12
T13
T14
T33
T34
U6
U37

CPU_VCCGTSENSE_N
CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N
CPU_VCCSENSE_N

1

R0961

5%
1/20W
MF
201

2

8 69

OUT

8 78

OUT

8 69

OUT

8 69

OUT

1

R0963

100100

5%
1/20W
MF
201

2

1

R0965

5%
1/20W
MF
201

2

1

R0966

100100

5%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

CPU Ground

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

9 OF 200

SHEET

9 OF 131

D

C

B

A

8

67

35 4

2

1

678

3 245

1

D

PPVCC_S0_CPU

115

CPU VCORE Decoupling

Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side
Apple Implementation:

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1000

1

1UF

20%
4V

2

CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1023

1UF

20%

2

4V
CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1001

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1024

1UF

20%

2

4V
CERM-X6S
0201

C1002

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1025

1UF

20%

2

4V
CERM-X6S
0201

C1003

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1026

1UF 1UF

20%

2

4V
CERM-X6S
0201

1

2

1

2

C1004

1UF

20%
4V
CERM-X6S
0201

C1027

20%
4V
CERM-X6S
0201

C1005

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1028

1UF

20%

2

4V
CERM-X6S
0201

C1006

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1029

1UF

20%

2

4V
CERM-X6S
0201

C1007

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1030

1UF

20%

2

4V
CERM-X6S
0201

Vcc CPU Core Decoupling from 20140905 BOM

C1008

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1031

1UF

20%

2

4V
CERM-X6S
0201

C1009

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1032

1UF

20%

2

4V
CERM-X6S
0201

C1010

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1033

1UF

20%

2

4V
CERM-X6S
0201

C1011

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1034

1UF

20%

2

4V
CERM-X6S
0201

C1012

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1035

1UF

20%

2

4V
CERM-X6S
0201

C1013

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1036

1UF

20%

2

4V
CERM-X6S
0201

C1014

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1037

1UF

20%

2

4V
CERM-X6S
0201

C1015

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1038

1UF

20%

2

4V
CERM-X6S
0201

C1016

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1039

1UF

20%

2

4V
CERM-X6S
0201

C1017

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1040

1UF

20%

2

4V
CERM-X6S
0201

C1018

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1041

1UF

20%

2

4V
CERM-X6S
0201

C1019

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1042

1UF

20%

2

4V
CERM-X6S
0201

C1020

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1043

1UF

20%

2

4V
CERM-X6S
0201

C1021

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1044

1UF

20%

2

4V
CERM-X6S
0201

C1022

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1045

1UF

20%

2

4V
CERM-X6S
0201

D

C

C1046

1

1UF

20%
4V

2

CERM-X6S
0201

1

C10A0

20%

2

2.5V
X6S-CERM
0402-1

C1047

1

1UF

20%
4V

2

CERM-X6S
0201 0201

1

C10A3

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

1

C10A4

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1048

1UF

20%
4V
CERM-X6S

1

2

1

2

C1049

1

2

C10Z4

20UF

20%

2.5V
X6S-CERM
0402-1

C10D2

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

1

C10A6

2

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C10D3

20UF

20%

2.5V
X6S-CERM
0402-1

C1050

1UF

20%
4V
CERM-X6S
0201

C10A7

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1051

1

1UF

20%
4V

2

CERM-X6S
0201

C1052

1

1UF

20%
4V

2

CERM-X6S
0201

C1053

1

1UF

20%
4V

2

CERM-X6S
0201

Place near inductors on bottom side.

1

C10A8

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D5

1

20%

2

2.5V
X6S-CERM
0402-1

1

C10ZB

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10D6

1

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C10B0

20UF

20%

2

2.5V
X6S-CERM

C10E2

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1054

1

1UF

20%
4V

2

CERM-X6S
0201

C10B1

20UF

20%

2.5V
X6S-CERM
0402-10402-1

C10E3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10B4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1055

1

1UF

20%
4V

2

CERM-X6S
0201

C10C0

1

2

C10N1

12PF

5%
25V
NP0-C0G
0201

20UF

20%

2.5V
X6S-CERM
0402-1

C10N2

1

2

C1056

1

1UF

20%
4V

2

CERM-X6S
0201

12PF

5%
25V
NP0-C0G

C10C1

20UF

1

20%

2.5V
X6S-CERM

2

0402-1

1

2

C1057

1

1UF

20%
4V

2

CERM-X6S
0201

1

2

C10N3

12PF

5%
25V
NP0-C0G0201
0201

C10C4

20UF

20%

2.5V
X6S-CERM
0402-1

C10N4

1

12PF

5%

2

25V
NP0-C0G
0201

C1058

1

1UF

20%
4V

2

CERM-X6S
0201

1

C10C5

20%

2

2.5V
X6S-CERM
0402-1

C10N5

1

12PF

5%

2

25V
NP0-C0G
0201

C1059

1

2

1

C10C6

20UF20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

C1060

1

1UF

20%
4V
CERM-X6S
0201

1

2

C10C7

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V

2

CERM-X6S
0201

Noise Floor caps

C10N6

5%
25V
NP0-C0G
0201

C10N7

1

12PF12PF

5%

2

25V
NP0-C0G
0201

C1061

1

1UF

20%
4V

2

CERM-X6S
0201

C1062

1

1UF

20%
4V

2

CERM-X6S
0201

C

B

115 122

PP1V2_S3_CPUDDR

1

3 2

C1068

220UF

20%
2V
ELEC

C10F0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C1069

3 2

Place on bottom side of U0500.

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500

20%
2V
ELEC
SM-COMBOSM-COMBO

C10F1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10F2

1

2

1

C1070

220UF220UF

3 2

20UF

20%

2.5V
X6S-CERM
0402-1

20%
2V
ELEC
SM-COMBO

C10F3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C10F4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1 0402-1

C10F5

1

2

1

C1072

3 2

20UF

20%

2.5V
X6S-CERM

20%
2V
ELEC
SM-COMBO

1

C10F6

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

3 2

C1073

220UF220UF

20%
2V
ELEC
SM-COMBO

1

C10F7

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

C10F8

20UF

20%

2

2.5V
0402-1

1

C10F9

20UF

20%

2

2.5V
X6S-CERMX6S-CERM

1

C10G0

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

B

C1080

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1090

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1081

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1091

1

20UF

20%

2

2.5V
X6S-CERM

C1082

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1092

1

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

C1083

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1093

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1084

1

20UF 20UF

20%

2.5V

2

X6S-CERM
0402-1

C1094

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1085

1

2

C1095

1

2

20%

2.5V
X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

CPU VDDQ Decoupling

Intel recommendation: 10x 10uF 0402, 4x 22uF 0602
Apple Implementation:

1

C1096

220UF

20%

3 2

2V
ELEC
SM-COMBO

CPU VCCIO Decoupling

Intel recommendation: 3x 10uF 0402 (opposite CPU)
Apple Implementation:

Place near U0500 on bottom side

A

PPVCCIO_S0_CPU

5 8 115

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

8

67

C1086

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1087

1

20UF

20%

2

2.5V
X6S-CERM

C1088

1

20UF

20%

2

2.5V
X6S-CERM
0402-10402-1

C1089

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108A

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108B

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C108C

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

BOM_COST_GROUP=CPU & CHIPSET

35 4

C108D

20UF

20%

2.5V
X6S-CERM
0402-1

PAGE TITLE

CPU Decoupling 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

10 OF 200

SHEET

10 OF 131

1

SYNC_DATE=03/29/2017SYNC_MASTER=SILU

SIZE

A

D

678

3 245

1

D

PPVCCGT_S0_CPU

115 122

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1100

1UF

20%
4V
CERM-X6S
0201

C1124

1UF

20% 20%
4V
CERM-X6S
0201

C1101

1

2

1

C1125

2

CPU VGTSlice Decoupling

Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201
Apple Implementation:

1UF

20%
4V
CERM-X6S
0201

1UF

4V
CERM-X6S
0201

C1102

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1126

1UF

20%

2

4V
CERM-X6S
0201

C1103

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1127

1UF 1UF

20%

2

4V
CERM-X6S
0201

1

2

1

2

C1104

1UF

20%
4V
CERM-X6S
0201

C1128

20%
4V
CERM-X6S
0201

C1105

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1129

1UF

20%

2

4V
CERM-X6S
0201

C1106

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1130

1UF

20%

2

4V
CERM-X6S
0201

C1107

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1131

1UF

20%

2

4V
CERM-X6S
0201

C1108

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1132

1UF

20%

2

4V
CERM-X6S
0201

Vcc GT Slice Core Decoupling from 20140905 BOM

Board Edge: 4x220uF, 7x 47uF rest on back side

C1109

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1133

1UF

20%

2

4V
CERM-X6S
0201

C1110

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1134

1UF

20%

2

4V
CERM-X6S
0201

C1111

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1135

1UF

20%

2

4V
CERM-X6S
0201

C1112

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1136

1UF

20%

2

4V
CERM-X6S
0201

C1113

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1137

1UF

20%

2

4V
CERM-X6S
0201

C1114

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1138

1UF

20%

2

4V
CERM-X6S
0201

C1115

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1139

1UF

20%

2

4V
CERM-X6S
0201

C1116

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1140

1UF

20%

2

4V
CERM-X6S
0201

C1117

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1141

1UF

20%

2

4V
CERM-X6S
0201

C1118

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1142

1UF

20%

2

4V
CERM-X6S
0201

C1119

1

2

1

C1143

2

1UF

20%
4V
CERM-X6S
0201

1UF

20%
4V
CERM-X6S
0201

C1120

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1144

1UF

20%

2

4V
CERM-X6S
0201

C1121

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1145

1UF

20%

2

4V
CERM-X6S
0201

C1122

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1146

1UF

20%

2

4V
CERM-X6S
0201

C1123

1

1UF

20%
4V

2

CERM-X6S
0201

1

C1147

1UF

20%

2

4V
CERM-X6S
0201

D

C

C1148

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11F0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1149

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A1

1

20UF

20%

2.5V

2

X6S-CERM

C11F1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

NOSTUFF

C11A2

1

20UF

20%

2.5V

2

X6S-CERM
0402-10402-1

1

2

C1150

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F2

20UF

20%

2.5V
X6S-CERM
0402-1

C1151

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11F3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1152

1

1UF

20%
4V

2

CERM-X6S
0201

C11A5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F4

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

1

2

NOSTUFFNOSTUFF

C11A6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F5

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1153

1UF

20%
4V
CERM-X6S
0201

C11A7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C1154

1

2

NOSTUFF

C11F6

20UF

20%

2.5V
X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

C11A8

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11F7

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C1155

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11A9

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11B0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E0

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1156

1

1UF

20%
4V

2

CERM-X6S
0201

1

2

C11B1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E1

20UF

20%

2.5V
X6S-CERM
0402-1

C1157

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11E2

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1158

1

1UF

20%
4V

2

CERM-X6S
0201

C11B3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11E3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C1159

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11E4

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

C1160

1

2

NOSTUFF

C11B5

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11E5

1

2

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

C11B6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

C1161

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11B7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1162

1

1UF

20%
4V

2

CERM-X6S
0201

C11B8

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C11B9

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1163

1UF

20%
4V
CERM-X6S
0201

C11C0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1164

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11C1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1165

1

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

C11C2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1166

1

2

NOSTUFF

C11C3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1UF

20%
4V
CERM-X6S
0201

1

2

1

2

C11C4

20UF

20%

2.5V
X6S-CERM
0402-1

C1167

1UF

20%
4V
CERM-X6S
0201

C11C5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11C6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11C7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11D4

1

2

1

2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11C8

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11D3

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C11C9

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C11D0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11D2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

C11D1

1

20UF

20%

2

2.5V
X6S-CERM
0402-1

C

B

1

C1168

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

3 2

C1170

220UF

20%
2V
ELEC
SM-COMBO

1

C1171

220UF

3 2

20%
2V
ELEC
SM-COMBO

1

C1172

220UF

3 2

20%
2V
ELEC
SM-COMBO

B

A

PPVCCSA_S0_CPU

115

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

C11H0

1

1UF

20%

2

4V
0201

C11H1

1

1UF

20%

2

4V
CERM-X6S
0201

1

C11K9

220UF

3 2

C11H2

1

1UF

20%

2

4V
CERM-X6S
0201

20%
2V
ELEC
SM-COMBO

NOSTUFF

C11I0

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11I1

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I2

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11I3

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I4

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I5

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11I6

1

20UF

20%

2.5V

2

X6S-CERM
0402-1CERM-X6S

NOSTUFF

C11I7

1

20UF

20%

2.5V

2

X6S-CERM
0402-1

CPU VCCSA Decoupling

Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_

Apple Implementation:

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

CPU VCCSTG Decoupling

PP1V05_S0SW

6 8 115

Place near U0500 on bottom side

Place near U0500 on bottom side

2x 220uF, 1x 22uF on board edge, everything else on back side

C11L1

1

1UF

20%
4V

2

CERM-X6S
0201

C11L2

1

1UF

20%
4V

2

CERM-X6S
0201

CPU VCCPLL and VCCST Decoupling

8 115

PP1V05_S3

BOM_COST_GROUP=CPU & CHIPSET

6 8 46

PP1V05_S3

115

C11M1

1

1UF

20%
4V

2

CERM-X6S
0201

Place near U0500 on bottom side

Place near U0500 on bottom side

PAGE TITLE

C11M2

1

1UF

20%
4V

2

CERM-X6S
0201

CPU Decoupling 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

11 OF 200

SHEET

11 OF 131

SYNC_DATE=05/24/2017SYNC_MASTER=SILU

SIZE

D

A

8

67

35 4

2

1

D

121 119 46 18 12

119 46

121 119 46 35

119 46 20

119 112 46 34 18 12

80 77 12

IN

IN

IN

OUT

IN

IN

12

PM_SYSRST_L
PM_PCH_SYS_PWROK

PM_PCH_PWROK

PLT_RST_L
PM_RSMRST_L

PM_PWRBTN_L
SPIROM_USE_MLB

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 4 OF 11

SYSTEM POWER MANAGEMENT

AL17

AK16

H23

U25

J24

L22

SYS_RESET*
SYS_PWROK
PCH_PWROK

GPP_B13/PLTRST*
RSMRST*

GPD3/PWRBTN*
GPD1/ACPRESENT

(IPU)

DRAM_RESET*

(OD)

(IPD-DeepSx)

GPP_A14/SUS_STAT*/ESPI_RESET*

(IPU-RSMRST#)

DSW_PWROK

WAKE*

GPD10/SLP_S5*

GPD5/SLP_S4*
GPD4/SLP_S3*

K25
H25
K23

P23

H22
J21
K20K22

PCH_DRAM_RESET_L

PM_RSMRST_L

PCIE_WAKE_L

ESPI_RESET_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

IN

OUT

OUT

OUT

OUT

OUT

26

119 112 46 34 18 12

19 12

119 39 20

PCH_STRP_GPD7

119 12

119 12

131 119 105 27 14 12

12

SPIROM_USE_MLB

12

PCIE_WAKE_L

19 12

PCH_BATLOW_L

12

PP3V3_S5

16 17 80

13 15 16 19 20 52 80

PP1V8_S5
PP1V8_S5

16 80

PP3V3_S5

16 17 80

R1204
R1205

R1206
R1208

100K
100K

100K

10K

21

21

NOSTUFF

21

5%

21

D

201MF5% 1/20W

2011/20W MF5%

1/20W MF 201

MF5% 1/20W 201

C

77

IN

PP3V0_G3H_RTC

PMU_CLK32K_PCH

1

R1201

1M

5%
1/20W
MF
201

2

PCH_INTRUDER_L

16 17 80

12

R1220

100K

21

1/20W

201

MF

5%

131 77 39 12

1

R1221

127K

1%
1/20W
MF
201

2

121 41

121 41

121 36

121 36

121 117

121 117

PCH_BATLOW_L
PM_SLP_S0_L

119

12

OUT

PCH_CLK32K_RTCX1

20

OUT

12

119 77

PCIE_CLK100M_SOC_N

OUT

PCIE_CLK100M_SOC_P

OUT

PCH_PCIE_CLK100M_WLAN_N

OUT

PCH_PCIE_CLK100M_WLAN_P

OUT

EG_PEG_CLK100M_N

OUT

EG_PEG_CLK100M_P

OUT

IN

NC_PCH_CLK32K_RTCX2
PCH_INTRUDER_L

PCH_RTC_RESET_L

L24

U23

G24
G22

H20

F25
F23

AR10
AN10

AP9

AM9

AR8
AN8

GPD0/BATLOW*
GPP_B12/SLP_S0*

RTCX1
RTCX2

INTRUDER*
SRTCRST*
RTCRST*

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

GPP_A0/RCIN*/ESPI_ALERT1*

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1

RTC

ESPI/LPC

GPP_A7/PIRQA*/ESPI_ALERT0*

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME*/ESPI_CS0*

GPP_A6/SERIRQ/ESPI_CS1*

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 2 OF 11

SLP_SUS*

GPD7

XTAL_IN

XTAL_OUT

CLKIN_XTAL

J25

R24
N20
N21
M20
M22
M25
N25
N24

J20

AN3
AN1

AR4

TP_PCH_SLP_SUS_L

PCH_GPP_A0_PU
ESPI_IO_PCH<0>
ESPI_IO_PCH<1>

ESPI_IO_PCH<2>
ESPI_IO_PCH<3>
ESPI_CS_L
PCH_SOC_SYNC
PCH_ESPI_ALERT0_L

PCH_STRP_GPD7

PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT

118

PCH_CLKIN_XTAL

12

12

OUT

PCH_ESPI_ALERT0_L

12

PCH_GPP_A0_PU

12

SOC_CLKREQ_L

41 12

DEBUG_CLKREQ_L

12

12

22

21

1%

22

21

1%

22

21

1% 1/20W MF 201

22

21

BI

39 20

38 12

R1260

201MF1/20W

R1261

201MF1/20W

R1262
R1263

201MF1/20W1%

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>

121 119 46 18 12

PM_SYSRST_L

BI
BI
BI
BI

118 39 20

118 39 20

118 39 20

118 39 20

R1209
R1210

R1211
R1213

R1214

100K
100K

47K

47K

3.0K

NEED TO CHANGE PER INTEL SPEC

21
21

21

201

21

201

21

5% 1/20W 201MF

MF1/20W

2015%

201MF5% 1/20W

C

CRITICAL

C1250

12

1

R1251

200K

1%
1/20W
MF
201

2

R1250

1/20W

0201

0

5%
MF

Y1250

24MHZ-10PPM-8PF-30OHM

2.5X2.0-SM

4 2

3 1

21

CRITICAL

PCH_CLK24M_XTALOUT_R

10PF

21

5%
50V
C0G

0201

CRITICAL

C1251

10PF

21

5%
50V
C0G

0201

Ce1=Ce2=2*(C_L - C_S - C_I) = 2*(8-0.7)=14.6pF
C_L = Load Capacitance = 8pF
C_S = Trace Capacitace + XTAL Pad Capacitance = 0.7pF
C_I= PCH Pin Capacitance = 0

B

121

121

121 27

121 27

121 105

121 105

PCIE_CLK100M_DEBUG_N

OUT

PCIE_CLK100M_DEBUG_P

OUT

PCIE_CLK100M_TBT_X_N

OUT

PCIE_CLK100M_TBT_X_P

OUT

PCIE_CLK100M_TBT_T_N

OUT

PCIE_CLK100M_TBT_T_P

OUT

NC
NC

NC
NC

AM6

CLKOUT_PCIE_N3

AK6

CLKOUT_PCIE_P3

AM8

CLKOUT_PCIE_N4

AK8

CLKOUT_PCIE_P4

AL7

CLKOUT_PCIE_N5

AJ7

CLKOUT_PCIE_P5

AK1

CLKOUT_PCIE_N6

AK3

CLKOUT_PCIE_P6

AJ5

CLKOUT_PCIE_N7

AK4

CLKOUT_PCIE_P7

CLOCK SIGNALS

GPP_A9/CLKOUT_LPC0

CLKOUT_CPUBCLK_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N

CLKOUT_CPUNSSC_P

XCLK_BIASREF

/ESPI_CLK

AP2

M23

AR7
AP7

AR6
AN6

PCH_XCLK_BIASREF

ESPI_CLK60M_PCH_R

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

12

R1237

22

PLACE_NEAR=U1200.M23:4mm

21

OUT
OUT

OUT
OUT

ESPI_CLK60M_PCH

MF 2011/20W1%

118 6

118 6

118 6

118 6

OUT

20

131 119 105 27 14 12

131 119 77 39 12

131 119 77 39 12

119 12

119 12

38 12

12

12

PM_SLP_S0_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
PCH_SOC_SYNC

PCH_CLKIN_XTAL
PCH_XCLK_BIASREF

R1236

R1230
R1231
R1232
R1233
R1215

R1235

R1234

PLACE_NEAR=U1200.AP2:2.54mm

100K

100K
100K
100K
100K

100K

10K

60.4

PP1V8_S5

36 77 80

21

NOSTUFF

1/20W MF 2015%

21
21

5% MF1/20W 201

21
21

21

21
21

1/20W5% MF

5% 201MF1/20W

1%

1/20W MF

MF1/20W5%

MF1/20W5%

B

201

201

201

2015% 1/20W MF

201

A

PP3V3_S5

R1207

10K

80

21

1/20W MF5%

201

PM_PWRBTN_L

12 77 80

PCI EXPRESS

CLOCKS & CONTROL

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

GPP_B5/SRCCLKREQ0*
GPP_B6/SRCCLKREQ1*
GPP_B7/SRCCLKREQ2*
GPP_B8/SRCCLKREQ3*
GPP_B9/SRCCLKREQ4*

GPP_B10/SRCCLKREQ5*

GPP_H0/SRCCLKREQ6*
GPP_H1/SRCCLKREQ7*

AP5
AM5

W22
AB22
U20
V20
W20
V21

D12
A10

NC
NC

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

SOC_CLKREQ_L
PCH_WLAN_CLKREQ_L

PCH_GPU_CLKREQ_L
DEBUG_CLKREQ_L

TBT_X_CLKREQ_L
TBT_T_CLKREQ_L

12

OUT
OUT

BI
BI
BI

IN
IN

19

118 6

118 6

41 12

37 19

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PAGE TITLE

27 19

105 19

PCH RTC/CLK/ESPI/PM

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-0

PAGE

12 OF 200

SHEET

12 OF 131

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

C

Intel Spec: 1k Pull-up for IO2 and IO3

PP1V8_S5

PPVCCSPI_PRIM_PCH

R1330
R1331
R1332

R1318
R1303

R1317

100K
100K
100K

1K

1K

100K

21

VCCSPI:3V3

21

VCCSPI:3V3

21

VCCSPI:3V3

5% MF 201

21

NOSTUFF

21

21

12 15 16 19 20 52 80

16

1/20W5% MF 201

1/20W5%

1/20W

1/20W MF 2015%

201MF

MF 2011/20W5%

MF1/20W 2015%

SPI_MOSI_R

SPI_IO<2>
SPI_IO<3>

PCH_STRP_BSSB_SEL_GPIO

PCH_STRP_NO_REBOOT

18 13

13

13

13

PCH_WLAN_DEV_WAKE

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

118 5

18 13

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN
IN

DMI_S2N_N<0>
DMI_S2N_P<0>

DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_S2N_N<2>
DMI_S2N_P<2>

DMI_S2N_N<3>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_P<0>

DMI_N2S_N<1>
DMI_N2S_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>

DMI_N2S_N<3>
DMI_N2S_P<3>

H3
H1

J2
J1

K3
K1

L4
L2

C3

B2

C1

E1
E2

F1
F4

F3

DMI0_TXN
DMI0_TXP

DMI1_TXN
DMI1_TXP

DMI2_TXN
DMI2_TXP

DMI3_TXN
DMI3_TXP

DMI0_RXN
DMI0_RXP

DMI1_RXN
DMI1_RXP

DMI2_RXN
DMI2_RXP

DMI3_RXN
DMI3_RXP

DMI

SYM 5 OF 11

(IPD)

CPU/MISC

GPP_B23/SML1ALERT*/PCHHOT*

OMIT_TABLE

CPUPWRGD

THRMTRIP*

PECI

GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1

CPU_TRST*

PLTRST_CPU*

PRDY*

PREQ*

TRIGGER_IN

TRIGGER_OUT

PM_DOWN

PM_SYNC

AR16
AP12
AR12
V25

V24
B12
C13
U22

AR17
AM14
AJ16
AP14
AR13

AN13
AL12

AJ12

PCH_PROCPWRGD
PCH_PM_THRMTRIP_L_R

PCH_PECI
PCH_WLAN_PERST_L

PCH_WLAN_DEV_WAKE
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_B2
PCH_STRP_BSSB_SEL_GPIO

XDP_CPU_TRST_L
CPU_RESET_L

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_PCH_TRIGGER
PCH_CPU_TRIGGER_R

PLACE_NEAR=U1200.AN13:5mm

CPU_PCH_PM_DOWN
PM_SYNC_R

PLACE_NEAR=U1200.AJ12:10mm

R1319

R1308

R1309
R1315

R1314

PM_SYNC

21

1/20W MF 2015%

33

0

620

13

13

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

21

21
21

37 36 20

18

18

6

5

37 36 13

BSS GPIO 0=BSSB CLK/DI on USB-SS

121 18 6

121 18 6

121 18 6

33

21

5% MF 2011/20W

OUT

IN

1/20W

5%
MF

5% 1/20W
MF 201

1/20W

5%
MF

6

CPU_PWRGD

0201

PCH_PMTHRMTRIP_L
CPU_PECI

201

PCH_CPU_TRIGGER

NOSTUFF

1

R1326

150K

5%
1/20W
MF
201

2

OUT

IN

OUT

IN

BI

121 119 6

46

46 6

D

5

5

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

A24

NC
NC
NC
NC
NC
NC
NC

37 36 13

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

NC
NC
NC
NC
NC
NC
NC
NC

AJ10

AK10

AM10

AR24

AB1

AJ2
AJ4
AJ8

G2
G4
M1
M3

V1
V2

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

SYM 1 OF 11

HDA_BCLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD

(IPD)

RSVD & TP PINS

AUDIO

GPP_D5/I2S2_SFRM/CNV_RF_RESET*

GPP_D6/I2S2_TXD/MODEM_CLKREQ

HDA_SDO/I2S0_TXD

HDA_RST*/I2S1_SCLK

HDACPU_SCLK

HDACPU_SDI

HDACPU_SDO

AC24

NC

AD23

NC

AD25

NC

AD22

TP_HDA_SDI1

AC25

TP_HDA_SDO

AD20

TP_HDA_RST

AJ13

PCH_DISPA_BCLK_R

AK13
AM13

PCH_DISPA_SDO_R

L21
AJ21

NC
NC

TP-P5

TP-P5

TP-P5

1

TP

TP1306

1

TP

TP1307

1

TP

TP1308

R1320

5%

R1321

1/20W

5%

C

33

21

201

MF1/20W

33

21

201MF

PCH_DISPA_BCLK
PCH_DISPA_SDI

PCH_DISPA_SDO

OUT

IN

OUT

20

20

20

B

117S0134 3

R1330,R1331,R1332

VCCSPI:1V8RES,MF,5%,1/20W,201,75K

TP1300

TP1301

121 18

121 18

121 18

121 18

121 18

121 18

TP
TP

IN

IN

IN

OUT

IN

IN

1

TP-P5

1

TP-P5

TP_PCH_TP1_F22
TP_PCH_TP3_B24

PCH_ITP_PMODE
XDP_PCH_TCK

XDP_PCH_TDI
XDP_PCH_TDO

XDP_PCH_TMS
XDP_PCH_JTAGX

(IPD)

(IPU)

(Undriven)

(IPU)

F22
B24

AN16
AP17
AR18

AM16

AL14

AN18

TP1

TP2

ITP_PMODE
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_JTAGX

JTAG

B

OMIT_TABLE

A

18 13

18 13

13

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 3 OF 11

C23
E25
C25

D21
A20
E22
B21

SPI0_CLK
SPI0_CS0*
SPI0_CS1*

SPI0_MOSI
SPI0_MISO
SPI0_IO2
SPI0_IO3

(IPU 20K)

(IPU 20K)
(IPU 20K)

SPI

GSPI

(IPD)

(IPD)

GPP_B18/GSPI0_MOSI

GPP_B22/GSPI1_MOSI

P20

P22

PCH_STRP_NO_REBOOT

TP_PCH_STRP_BOOT_SPI_L

13

No Rebort: 0=Disable; 1=Enable

BootBIOS Strap: 0=SPI; 1=LPC

PAGE TITLE

A

SYNC_DATE=07/27/2017SYNC_MASTER=SILU

NC
NC
NC

BI

BI

BI

SPI_MOSI_R

NC

SPI_IO<2>
SPI_IO<3>

8

PCH DMI/JTAG/SPI/HDA

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

13 OF 200

SHEET

13 OF 131

1

SIZE

D

678

3 245

1

D

29

29

29

29

119

119

119

119

IN
IN

OUT
OUT

IN
IN

OUT
OUT

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_TEST_D2R_N
USB3_TEST_D2R_P

USB3_TEST_R2D_N
USB3_TEST_R2D_P

AA4

USB31_1_RXN

AA2

USB31_1_RXP

AD3

USB31_1_TXN

AD1

USB31_1_TXP

W3

USB31_2_RXN

W1

USB31_2_RXP

AC2

USB31_2_TXN

AC1

USB31_2_TXP

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 7 OF 11

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

AG1
AG2

AF1
AF3

AH1
AH3

AF4
AE5

USB2_UPC_TA_N
USB2_UPC_TA_P

USB2_UPC_TB_N
USB2_UPC_TB_P

USB2_UPC_XA_N
USB2_UPC_XA_P

USB2_UPC_XB_N
USB2_UPC_XB_P

OMIT_TABLE

U1200

961822

BGA

SYM 8 OF 11

PCIE/SATA/USB3

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

PCIE19_RXN/SATA6_RXN

PCIE19_RXP/SATA6_RXP

PCIE19_TXN/SATA6_TXN

PCIE19_TXP/SATA6_TXP

F6
D6

B4
A4

G8
G7

B5
A5

F8
D8

C6
A6

PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>

PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>

PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<1>

PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>

PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>

PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

118 41

118 41

118 47

118 47

118 41

118 41

118 47

118 47

118 41

118 41

118 47

118 47

D

29

29

29

29

119 107

119 107

119 107

119 107

118 36

118 36

118 36

118 36

126

126

126

126

119

119

119

119

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

PCH_PCIE_WLAN_D2R_N
PCH_PCIE_WLAN_D2R_P

PCH_PCIE_WLAN_R2D_C_N
PCH_PCIE_WLAN_R2D_C_P

USB3_TEST2_D2R_N
USB3_TEST2_D2R_P

USB3_TEST2_R2D_N
USB3_TEST2_R2D_P

USB3_SOCDEBUG_D2R_N
USB3_SOCDEBUG_D2R_P

USB3_SOCDEBUG_R2D_C_N

USB3_SOCDEBUG_R2D_C_P

W4

PCIE1_RXN/USB31_7_RXN

W6

PCIE1_RXP/USB31_7_RXP

U1

PCIE1_TXN/USB31_7_TXN

U3

PCIE1_TXP/USB31_7_TXP

U6

PCIE2_RXN/USB31_8_RXN

V5

PCIE2_RXP/USB31_8_RXP

R2

PCIE2_TXN/USB31_8_TXN

R1

PCIE2_TXP/USB31_8_TXP

P4

PCIE3_RXN/USB31_9_RXN

R5

PCIE3_RXP/USB31_9_RXP

P3

PCIE3_TXN/USB31_9_TXN

P1

PCIE3_TXP/USB31_9_TXP

CNL-PCH-H-USFF-QNYP

BI
BI

BI
BI

BI
BI

BI
BI

C

USB3

USB2

GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*

E12
G10
D10
F10

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

P6

NC
NC

NC
NC

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

107 14

107 14

107 14

109 108 107 105 14

29 27 14

105 14

29 14

29 14

107 14

107 14

OUT
OUT
OUT

OUT
OUT
OUT

XDP_PCH_OBSFN_C0
XDP_PCH_OBSDATA_A0

XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_D0

XDP_PCH_OBSDATA_D1
XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TDO

TBT_T_USB_PWR_EN
TBT_X_PLUG_EVENT_L

TBT_T_PLUG_EVENT_L

NC

PCH_PCIE_RCOMPP
PCH_PCIE_RCOMPN

PCIE4_RXN/USB31_10_RXN

N5

PCIE4_RXP/USB31_10_RXP

N2

PCIE4_TXN/USB31_10_TXN

N1

PCIE4_TXP/USB31_10_TXP

D16

GPP_E0/SATAXPCIE0/SATAGP0

F16

GPP_E1/SATAXPCIE1/SATAGP1

G14

GPP_E2/SATAXPCIE2/SATAGP2

C20

GPP_F0/SATAXPCIE3/SATAGP3

A19

GPP_F1/SATAXPCIE4/SATAGP4

B19

GPP_F2/SATAXPCIE5/SATAGP5

A22

GPP_F3/SATAXPCIE6/SATAGP6

G18

GPP_F4/SATAXPCIE7/SATAGP7

D18

GPP_F10/SATA_SCLOCK

C18

GPP_F11/SATA_SLOAD

G16

GPP_F12/SATA_SDATAOUT1

E17

GPP_F13/SATA_SDATAOUT0

L5

PCIE_RCOMPP

K4

PCIE_RCOMPN

PCIE20_RXN/SATA7_RXN

PCIE20_RXP/SATA7_RXP

PCIE20_TXN/SATA7_TXN

PCIE20_TXP/SATA7_TXP

GPP_E4/SATA_DEVSLP0
GPP_E5/SATA_DEVSLP1
GPP_E6/SATA_DEVSLP2

GPP_F5/SATA_DEVSLP3
GPP_F6/SATA_DEVSLP4
GPP_F7/SATA_DEVSLP5
GPP_F8/SATA_DEVSLP6
GPP_F9/SATA_DEVSLP7

GPP_E8/SATALED*

G9
E9

B7
A7

E14
F13
D13

F20
G19
D20
E19
F18

G13

PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>

PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>

XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1

TBT_X_PCI_RESET_L
TBT_T_PCI_RESET_L
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_CIO_PWR_EN

XDP_PCH_OBSDATA_B3

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT

OUT

18

18

18

18

118 41

118 41

118 47

118 47

29 27 20

105 20

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

C

IN
IN

B

PP3V3_S5

PM_SLP_S3_L
PP3V3_S0SW_TBT_T_SNS
PP3V3_S0SW_TBT_X_SNS

PM_SLP_S3_L

16 80

116

116

GPP_F15/USB2_OC4*
GPP_F16/USB2_OC5*

USB2_COMP

USB2_ID

USB2_VBUSSENSE

131 119 105 27 14 12

B17
D17

AB6
AE4
AE2

NC
NC

USB2_COMP
USB2_ID
USB2_VBUSSENSE

PLACE_NEAR=U1200.AB6:10.0mm

1

R1410

1K

5%
1/20W
MF
201

2

1

R1411

1K

5%
1/20W
MF
201

2

1

R1470

113

1%
1/20W
MF
201

2

1

R1400

100

1%
1/20W
MF
201

2

B

131 119 105 27 14 12

A

R1441
R1442

R1443
R1444

R1446

R1445
R1447

R1460
R1461
R1420
R1421

R1448

R1491
R1492
R1493
R1494

100K
100K

100K
100K

100K

100K

10K
10K

10K
10K
10K

100K

100K
100K
100K
100K

21

21

21

5% MF1/20W

21

5% 1/20W MF

21
21

21
21

5% 1/20W MF 201

21
21

21

21
21
21
21

21

1/20W MF5%
1/20W5% MF

5% MF 2011/20W

1/20W MF5% 201

5%

1/20W5%

5%

MF

MF

MF 201

MF5% 1/20W

MF1/20W

MF5% 1/20W 201

201
201

2011/20W MF5%

2011/20W

2011/20W5%

2011/20W5% MF

201

201

2011/20W MF5%

201

201

NOSTUFF
NOSTUFF

NOSTUFF
NOSTUFF

107 14

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_CIO_PWR_EN
TBT_T_USB_PWR_EN

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

TBT_T_CIO_PWR_EN
TBT_T_USB_PWR_EN

TBT_T_PLUG_EVENT_L
TBT_X_PLUG_EVENT_L

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDO

107 14

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

29 14

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

29 14

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

107 14

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

107 14

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

109 108 107 105 14

31 30 29 27 14

31 30 29 27 14

109 108 107 105 14

109 108 107 105 14

105 14

29 27 14

XDP_JTAG_ISP_TDO
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

18

18

18

18

18

SYNC_MASTER=ZIFENG SYNC_DATE=05/18/2017

PAGE TITLE

A

PCH PCI-E/USB

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

18

18

BOM_COST_GROUP=CPU & CHIPSET

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

14 OF 200

SHEET

14 OF 131

SIZE

D

8

67

35 4

2

1

D

C

RAMCFG0:L

1K

5%

1/20W

MF

201

1

2

R1530

RAMCFG1:L

1

R1531

1K

5%
1/20W
MF
201

2

RAMCFG2:L

R1532

1K

5%

1/20W

MF

201

SPEED

2400MHZ
2133MHZ

1

2

CONGIF3

0

1

RAMCFG3:L

1

R1533

1K

5%
1/20W
MF
201

2

STORAGE

16GB
32GB

1

R1534

1K

5%
1/20W
MF
201

2

RAMCFG4:L

CONGIF2

1
0

VENDOR

SAMSUNG

MICRON
HYNIX

CONGIF1

1
0

MLB_RAMCFG0
MLB_RAMCFG1

MLB_RAMCFG2
MLB_RAMCFG3

MLB_RAMCFG4

CONGIF0

0
1
00

15

15

15

15

15

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

93 15

93 15

J680 Display Port DDPF Disabled

PDG recommends to NC the HPD
lines not being used

93 15

J680 Display Port DDPB/C/D Disabled

107 29 15

eSPI Flash Mode: 0=MAF; 1=SAF

OUT
OUT

NC
NC
NC
NC

IN

OUT

EDP_IG_PANEL_PWR
EDP_IG_BKLT_EN

DP_INT_IG_HPD

TBT_POC_RESET

PCH_STRP_SPIROM_SAF

15

PCH_STRP_GPP_H15

15

NC

NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

A18
A16
C16
A14
B14
A13

AN23
AN25

AP24
AP22

AR22

AP19
AM19
AR20
AN20

AP21
AR21

AL24
AL25

AK25

A9

B9

GPP_F14/PS_ON*
GPP_F19/EDP_VDDEN
GPP_F20/EDP_BKLTEN
GPP_F21/EDP_BKLTCTL
GPP_F22/DDPF_CTRLCLK
GPP_F23/DDPF_CTRLDATA

GPP_I0/DDPB_HPD0/DISP_MISC0
GPP_I1/DDPC_HPD1/DISP_MISC1
GPP_I2/DDPD_HPD2_DISP_MISC2
GPP_I3/DDPF_HPD3_DISP_MISC3
GPP_I4/EDP_HPD/DISP_MISC4
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2

GPP_H12/SML2ALERT*

GPP_H15/SML3ALERT*

(IPD)

GPPF/

BACKLIGHT

GPPG

GPPI/DISPLAY

/SMLINK

BGA

SYM 9 OF 11

(IPD)

(IPD)

GPP_J0/CNV_PA_BLANKING

GPP_J1/CPU_C10_GATE*

GPP_J2
GPP_J3

GPP_J4/CNV_BRI_DT/UART0B_RTS*

GPP_J5/CNV_BRI_RSP/UART0B_RXD

GPP_J6/CNV_RGI_DT/UART0B_TXD

GPP_J7/CNV_RGI_RSP/UART0B_CTS*

GPP_J8/CNV_MFUART2_RXD

GPP_J9/CNV_MFUART2_TXD

GPP_J10

GPP_J11/A4WP_PRESENT

GPP_K20
GPP_K21

GPPJ_RCOMP_1P8

CNV_WR_CLKP

CNV_WR_CLKN

CNV_WR_D0P

CNV_WR_D0N

CNV_WR_D1P

CNV_WR_D1N

CNV_WT_CLKP
CNV_WT_CLKN

CNV_WT_D0P
CNV_WT_D0N

CNV_WT_D1P
CNV_WT_D1N

CNV_WT_RCOMP

AM18
AK18
AL19
AJ18
AJ22
AH23
AJ25
AH25
AK22
AK23
AM20
AK20

A8
C8

AJ17

AG24
AG25

AF23
AF25

AE22
AE24

AH22
AH20

AG21
AG20

AF22
AF20

AE21

SOC_SWD_MUX_SEL_PCH
CPU_C10_GATE_L
PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO
PCH_STRP_XTAL_24MHZ
MLB_RAMCFG2
PCH_STRP_CNV_L
MLB_RAMCFG3
MLB_RAMCFG4
PCH_STRP_VCCPSPI_1V8
PCH_BT_ROM_BOOT_L
PCH_BT_DEV_WAKE

MLB_RAMCFG0
MLB_RAMCFG1

PCH_GPPJ_RCOMP_1P8

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

15

OUT

GPP_J2:Unused

15

GPP_J3:Unused

15

GPP_J4: 0=38.4MHz 1=24MHz XTAL

15

15

15

GPP_J6: 0=ENABLE 1=DISABLE

15

15

15

GPP_J9: 0=3.3V; 1=1.8V

36 15

36 15

15

15

15

131 79 78 76 15

D

C

B

PP1V8_S5

PP3V3_S5
PP1V8_S5
PP3V3_S5

R1501
R1502

R1503
R1505

R1506
R1507
R1508
R1509
R1510

R1511
R1512

R1526
R1543

R1514
R1515
R1516

R1517
R1518

10K
10K

1K

47K

47K
47K
47K
47K
47K

1K

100K

20K

1K
100K
100K
100K

1K

1K

VCCSPI:1V8

VCCSPI:3V3

80

16 19 80

12 13 16 19 20 52 80

16 80

21

21

21

21

21
21
21
21
21

21
21

21

21

21
21
21

21

21

1/20W5% MF 201

1/20W MF5% 201

1/20W5% MF 201

1/20W MF5%

1/20W5%

1/20W

1/20W 201

1% 2011/20W

1/20W5% 201MF

1/20W 201

5% MF

5% 201MF

1/20W

1/20W5%

MF5% 2011/20W

MF5% 1/20W

201

201

201MF

MF5% 201

MF5%

MF5% 1/20W 201

MF 2015% 1/20W

MF

201MF1/20W5%

MF5% 1/20W

201MF

201

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

PCH_STRP_ESPI

PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

PCH_STRP_SPIROM_SAF
PCH_STRP_GPP_H15

PCH_STRP_CNV_L
PCH_STRP_XTAL_24MHZ

PCH_SWD_SOC_CLK
PCH_SWD_SOC_IO
CPU_C10_GATE_L

PCH_STRP_VCCPSPI_1V8

15

15

15

15

15

15

15

15

GPPH/I2C/INTEGRATED SENSOR

19 15

IN

WLAN_AUDIO_SYNC_LS3V3

C10

GPP_H23/TIME_SYNC0

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

121 27 15

121 105 15

35 15

39 20

35 15

35 15

35 15

126 119 29 15

126 119 29 15

TP1501

121 27 15

121 105 15

131 79 78 76 15

39

TP-P5

TP

OUT
IN

1

OUT
OUT

SOC_PERST_L
PCH_GCON_INT_L

TP_PCH_STRP_TOPBLK_SWP_L

PLACE_SIDE=BOTTOM

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

NC

R22

P25

R21

AC20
AC21

AB20

GPP_A20/ISH_GP2
GPP_A21/ISH_GP3

GPP_B14/SPKR

GPP_D0/SPI1_CS*/SBK0/BK0
GPP_D1/SPI1_CLK/SBK1/BK1

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

(IPD)

961822

BGA

SYM 6 OF 11

GPPA/

INTEGRATED SENSOR

GPPC/SMLINK/I2C/UART

(IPD)

(IPD)

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_C5/SML0ALERT*

GPP_C8/UART0A_RXD

GPP_C9/UART0A_TXD

GPP_C10/UART0A_RTS*

GPP_C11/UART0A_CTS*

GPP_C20/UART2_RXD

GPP_C21/UART2_TXD

W23
W25
AA22

AB19

AA24
AA21
AA18
Y19

AB25
AB23

SMBUS_PCH_CLK
SMBUS_PCH_DATA
TP_PCH_STRP_TLSCONF

PCH_STRP_ESPI

PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

15

OUT

BI

OUT
OUT

OUT

52

52

IN

IN

IN

PROJ-SPECIFIC PULLUP

TLS: 0=Disbale; 1=Enable

GPP_C5: 0=LPC; 1=eSPI

35 15

35 15

35 15

35 15

126 119 29 15

126 119 29 15

B

A

R1522
R1523

R1524
R1525

R1527
R1528

R1529
R1540
R1542

100K

100K
100K
100K

100K
100K

100K
100K

200

21

21

5% MF1/20W 201

21
21

NOSTUFF

21
21
21

21
21

1/20W MF 201

5%

1/20W

NOSTUFF

5% 1/20W 201MF

201MF1/20W5%

201MF1/20W5%

2015% 1/20W MF

201MF1/20W5%

MF5% 201

MF

GPPD/INTEGRATED SENSOR/UART/I2C GPPB

DP_INT_IG_HPD
TBT_POC_RESET

WLAN_AUDIO_SYNC_LS3V3
PCH_BT_DEV_WAKE

EDP_IG_PANEL_PWR
EDP_IG_BKLT_EN

SOC_SWD_MUX_SEL_PCH
PCH_BT_ROM_BOOT_L
PCH_GPPJ_RCOMP_1P8

2011/20W1%

15

15

93 15

107 29 15

19 15

36 15

93 15

93 15

PAGE TITLE

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PCH GPIO/MISC/NCTF

36 15

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

SIZE

D

4.0.0

BRANCH

evt-0

PAGE

15 OF 200

SHEET

15 OF 131

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

C

B

115 80 17

80 17 12

17

115

115

115

17

PP1V05_PRIM

PP3V3_S5

PP1V05_PRIM_PCH_VCCAPLL_F

PP1V05_PRIM

PP1V05_PRIM

PP1V05_PRIM

PP1V05_PRIM_PCH_VCCAXTAL_F

AB12
AB14
AB17

AB7

AB9
AD12
AD14

AD9
AE11

AF7

H7
H9

J15
K14
K17

K7

K9
M7
M9

P12
P14
P17

P7

P9

T12
T14
T17

T7

T9
V12
V14
V17

V9
Y12
Y14
Y17

Y7

Y9

AD17

AE15
AE18

M17

V7

AF6

AG8

AC5

AJ6

AG5

AD7

PRIMARY WELL

VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05

PRIMARY WELL HVCMOS

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

VCCAPLL_1P05
VCCAPLL_1P05

VCCDUSB_1P05

VCCA_BCLK_1P05

VCCA_SRC_1P05

VCCA_XTAL_1P05

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 10 OF 11

POWER

AUDIO PLL

MOD PHY PRIMARY

DEEP SX WELL

VCCAMPHYPLL_1P05

LDO

GPPA PRIMARY WELL

GPPB/GPPC
PRIMARY WELL

GPPD PRIMARY WELL

GPPE/GPPEF
PRIMARY WELL

GPPH/GPPK PRIMARY WELL

RTC WELL SUPPLY

RTC LOGIC PW/VRM

SPI

VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24
VCCDPHY_1P24

VCCDSW_3P3

VCCDSW_1P05

VCCPHVLDO_1P8
VCCPHVLDO_1P8

VCCPGPPA

VCCPGPPBC

VCCPGPPD

VCCPGPPEF
VCCPGPPEF

VCCPGPPHK

DCPRTC

VCCRTC
VCCRTC

VCCSPI

AF19
AG18
AH17
AH19

M19
N18

M6

AF12
AF14

P19

T19

V19

M12
M14

K12

H17

G20
H19

K19

678

3 245

1

OMIT_TABLE

U1200

CNL-PCH-H-USFF-QNYP

961822

BGA

SYM 11 OF 11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L8
L11
L13
L15
L18
L25
M4
N4
N6
N8
N11
N13
N22
U4
U8
R11
R13
R15
R18
R20
R25
U15
U11
W13
W18
U18
V4
V6
V22
W8
W11
W15
A25
AA1
AA5
A17
A21
AA25
AB3
AA6
AA8
AA11
AA13
AA15
AC4
AC6
AB4
AC8
AE1
AE6
AE8
AE13
AC11
AC13
AC15
AC18
AD4
AD6
AE20
AE25
AF9
AF17
AG6
AG15
AG22
AH4
AH6
AH7
B22

D

C

B

PP1V24_S5_PCH_VCCDPHY

PP3V3_S5

PP1V05_S5_PCH_VCCDSW

PP1V_PRIM_PCH_VCCAMPHYPLL_F

PP1V8_PCH_VCCPHYLDO

Internal Supply

17

17

17

PP1V8_S5

PP1V8_S5

PP3V3_S5

PP3V3_S5

PP3V3_S5

PPDCPRTC_PCH

17

PP3V0_G3H_RTC

VOLTAGE=3.3V

0201

R1601

VCCSPI:3V3

R1602

PPVCCSPI_PRIM_PCH

0201

VCCSPI:1V8

17

80 17 12

Internal LDO, leave this pin as NC

80 12

80 52 20 19 15 13 12

80 15

80 14

80 19 15

80 17 12

21

0

0

1/20W 5%MF

21

1/20W 5%MF

PP3V3_S5

PP1V8_S5

80

80

R6
U13
A12

A1

A2

AJ24

AP4

D5
G17

J11

L20

AL1

AA20
AC22

AG4
AH9

AJ1

AJ9
AJ14
AJ19
AJ20

AL2
AR14
AR19

AL4

AL9

AL22

AM7
AM12
AM17
AM21

AP1

AP25

AR1
AR2
AR5
AR9

E24

G1

AR25

B1

B25

D7

D9
D14
D19

E4

E7

J5
J8

G5
G12
G21
G25

H4

H6
H12
H14

J4

J6
J13
J22
J18

N15

R4
R8

L1
L6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A

PP1V8_S5

80 17

Share with GPIO J Group Power

PP1V05_PRIM

115 17

PP1V8_S0_PCH_VCCHDA_F

17

AG11
AG13
AH12
AH14

K6

AD19

VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8

VCCPRIM_MPHY_1P05

HD AUDIO POWER

VCCHDA

ANALOG PLL USB2/VRM

Current data from LPT EDS (doc #486708, Rev 1.0).

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

PCH Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

16 OF 200

SHEET

16 OF 131

SIZE

D

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

8

67

35 4

2

1

678

3 245

1

D

PP1V05_PRIM

16 80 115

C1750

NP0-C0G

PP3V3_S5

12 16 80

PP1V8_S5

16 80

PLACE_NEAR=U1200.K14:1MM

1

12PF

5%

25V

2

0201

PLACE_NEAR=U1200.AB14:5MM

PLACE_NEAR=U1200.K14:1MM

1

C1715

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.AE15:1MM

C1751

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1200.AG13:2MM

1

C1716

0.1UF

10%

16V

2

X5R-CERM
0201

1

2

1

C1752

12PF

5%

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.V9:3MM

C1700

22UF

X5R-CERM-1

PLACE_NEAR=U1200.AE15:1MM

1

2

PLACE_NEAR=U1200.AG13:2MM

1

2

1

20%

6.3V

2

603

C1703

0.1UF

10%

16V

X5R-CERM
0201

C1705

1UF

20%

6.3V

X6S-CERM
0201

PLACE_NEAR=U1200.P9:1MM

1

C1701

1UF

10%

6.3V

2

CERM
402

PLACE_NEAR=U1200.AE15:1MM

1

C1702

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.AH12:2MM

1

C1704

0.1UF

10%

16V

2

X5R-CERM
0201

PP1V05_S5_PCH_VCCDSW

17 16

PP3V0_G3H_RTC

12 16 80

PP1V05_PRIM

16 115

1

C1714

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.N18:1MM
PLACE_NEAR=U1200.N18:1MM

1

C1709

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.G19:1MM
PLACE_NEAR=U1200.H20:1MM

1

C1711

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.K6:1MM
PLACE_NEAR=U1200.K6:5MM
PLACE_NEAR=U1200.K6:1MM

1

C1713

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C1708

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1710

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1712

1UF

20%

6.3V

2

X6S-CERM
0201

VOLTAGE=1.05V

PP1V05_S5_PCH_VCCDSW

17 16

VOLTAGE=3V

PPDCPRTC_PCH

16

PP1V24_S5_PCH_VCCDPHY

16

PLACE_NEAR=U1200.N18:1MM

1

C1742

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.H17:1MM

1

C1743

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1200.AH19:3MM

NOSTUFF

1

C1740

4.7UF

20%

6.3V

2

X6S
0402

D

C

B

PP1V05_PRIM

115

C1721

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

L1703

220-OHM-0.7A-0.28-OHM

PLACE_NEAR=U1200.AG8:3MM

1

2

PP3V3_S5

12 16 17 80

21

PP1V05_PRIM_PCH_VCCAPLL_F

0402-1

PLACE_NEAR=U1200.AG8:3MM

MAKE_BASE=TRUE

PLACE_NEAR=U1200.AG8:1MM

1

C1722

3.0PF

+/-0.1PF

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.M19:1MM
PLACE_NEAR=U1200.M19:1MM
PLACE_NEAR=U1200.M19:1MM

C1753

12PF

NP0-C0G

PLACE_NEAR=U1200.AG8:1MM

1

2

1

5%

25V

2

0201

C1720

4.7UF

20%

6.3V

X6S
0402

C1707

0.1UF

20%

10V

CERM

402

PP1V05_PRIM_PCH_VCCAPLL_F

C

1

2

1

C1706

0.1UF

20%

10V

2

CERM
402

16

PP1V05_PRIM

115

PP3V3_S5

12 16 17 80

C1755

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1200.AD7:3MM

1

PLACE_NEAR=U1200.AD7:5MM

2

PLACE_NEAR=U1200.M19:2MM

1

C1741

1UF

20%

6.3V

2

X6S-CERM
0201

OMIT_TABLE

L1701

2.2UH-20%-0.19A-0.221OHM

21

0603

1

C1726

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1200.AD7:3MM

PP1V8_PCH_VCCPHYLDO

MAKE_BASE=TRUE

16

VOLTAGE=1.05V

PP1V05_PRIM_PCH_VCCAXTAL_F

1

C1727

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.AD7:3MM
PLACE_NEAR=U1200.AD7:3MM

1

2

C1728

1UF

20%

6.3V

X6S-CERM
0201

NOSTUFF

1

C1744

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V05_PRIM_PCH_VCCAXTAL_F

16

B

PP1V8_S5

80

C1724

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

L1704

75OHM-25%-0.2A-1.3OHM

21

PLACE_NEAR=U1200.AD19:3MM

1

2

0402

PLACE_NEAR=U1200.AD19:3MM

MAKE_BASE=TRUE

PP1V8_S0_PCH_VCCHDA_F

PLACE_NEAR=U1200.AD19:1MM

1

C1725

3.0PF

+/-0.1PF

25V

2

NP0-C0G
0201

PLACE_NEAR=U1200.AD19:1MM

1

C1723

4.7UF

20%

6.3V

2

X6S
0402

PP1V8_S0_PCH_VCCHDA_F

16

PP1V05_PRIM

115

C1756

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

PLACE_NEAR=U1200.M6:3MM

OMIT_TABLE

L1702

2.2UH-20%-0.19A-0.221OHM

21

PLACE_NEAR=U1200.M6:3MM

0603

MAKE_BASE=TRUE

1

C1729

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1200.M6.3MM

VOLTAGE=1V

PP1V_PRIM_PCH_VCCAMPHYPLL_F

1

C1730

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M6:3MM

1

C1731

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V_PRIM_PCH_VCCAMPHYPLL_F

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

16

A

Current data from LPT EDS (doc #486708, Rev 1.0).

8

L1701,L1702RES,MF,1A MAX,0OHM,5%,0603113S0022 2

SYNC_MASTER=ZIFENG SYNC_DATE=05/18/2017

PAGE TITLE

A

PCH Decoupling

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

17 OF 200

SHEET

17 OF 131

1

SIZE

D

D

C

6

IN

6

IN

6

IN

6

IN

119 112 46 34 12

119 80

121 18 6

121 13

Extra BPM Testpoints

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

IN

OUT

13

OUT

OUT

PM_RSMRST_L

PM_PWRBTN_L

SPI_MOSI_R

IN

XDP_CPU_TCK

XDP_PCH_JTAGX

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1800
TP1801
TP1802
TP1803

PP3V3_S5

80

PLACE_NEAR=J1800.48:2.54MM

R1800

PLACE_NEAR=U1200.H25:2.54MM

PLACE_NEAR=U1200.K22:5MM

R1802
R1803

PLACE_NEAR=U1200.D21:10MM

R1835

PLACE_NEAR=J1800.58:28MM

1K

10

1.5K

0

XDP:YES

21

XDP:YES

21

XDP:YES

XDP:YES

21

XDP:YES

1K

5%

1/20W

MF

201

1

2

MF 2011/20W5%

R1804

21

5% MF 2011/20W

1/20W

5% MF 0201

678

3 245

1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V05_PRIM

115

NOTE: This is not the standard XDP pinout.

XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49
52 51
54 53
56 55
58 57
60 59

64 63

61

518S0847

1.5K

5%

1/20W

MF

201

1

XDP:YES

NO_XNET_CONNECTION

2

XDP_PIN_1

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

NC
NC

NC

NC
NC

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

HOOK0
HOOK1

VCC_OBS_AB

HOOK2
HOOK3

XDP:YES

C1800

0.1UF

CERM-X5R

PLACE_NEAR=J1800.42:28MM

PLACE_NEAR=J1800.44:28MM

SDA TDO
SCL

TCK1

1

10%

6.3V

2

0201

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

PLACE_NEAR=J1800.2:5MM

XDP_PRESENT_CPU

121 13 6

121 13 6

6

6

6

6

6

6

6

6

XDP_CPU_PREQ_L

BI

XDP_CPU_PRDY_L

IN

CPU_CFG<0>

IN

CPU_CFG<1>

IN

CPU_CFG<2>

IN

CPU_CFG<3>

IN

CPU_CFG<4>

IN

CPU_CFG<5>

IN

CPU_CFG<6>

IN

CPU_CFG<7>

IN

XDP_PM_RSMRST_L
XDP_CPU_PWRBTN_L

2011/20W5% MF

SPI_MOSI_R_CONN

121 18 13

OUT

XDP_PCH_TCK

XDP:YES

10%

6.3V
0201

1

2

C1804

0.1UF

CERM-X5R

Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TRSTn
TDI
TMSTCK0
XDP_PRESENT#

XDP:YES

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.43:28MM

PLACE_NEAR=J1800.47:28MM

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC_ITPXDP_CLK100MP
NC_ITPXDP_CLK100MN

PCH_ITP_PMODE
XDP_DBRESET_L

XDP:YES

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

121 18 13

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

IN
IN

118 20

118 20

1

R1830

1K

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.E8:2.54MM

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

121 18 13

121 18 13

121 18 13

IN

0

0

0

0

121 18 6

121 18 6

121 13

XDP:YES

XDP:YES

XDP:YES

XDP_PCH_TDO

PLACE_NEAR=U1200.AM16:28MM

XDP_PCH_TDI

PLACE_NEAR=U1200.AR18:28MM

XDP_PCH_TMS

PLACE_NEAR=U1200.AL14:28MM

XDP_CPU_TDO

PLACE_NEAR=U0500.BT28:28MM

XDP_CPU_TCK

PLACE_NEAR=U0500.BR28:28MM

XDP_PCH_TCK

PLACE_NEAR=U1200.AP17:28MM

XDP_PCH_TRST_L

18

PROPER WAY TO TERMINATE?

21

5%

1/20W 0201MF

21

21

21

1/20W

5% MF 0201

5% 1/20W MF 0201

5% 1/20W

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

MF

XDP:YES

R1890
R1891
R1892
R1810

R1813
R1897

R1898

R1806

0

21

5%

1/20W

MF

0201

0201

PM_SYSRST_L

XDP:YES

PP1V05_S0SW

115

XDP:YES

100

XDP:YES

51

XDP:YES

51

100

XDP:YES

XDP:YES

51

NOSTUFF

51

NOSTUFF

51

IN

OUT

OUT

OUT

12

5% 201

1/20W MF

12

5%

MF 2011/20W

D

12

12

12

12

12

BI

1/20W MF

5%

1/20W MF

5%

5% 201

1/20W

MF

MF1/20W5%

121 119 46 12

201

201

201

2015% 1/20W MF

C

121 18 6

121 13 6

121 6

121 6

B

14

14

13

14

14

14

13

14

14

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PCH/XDP Signals

XDP_PCH_OBSDATA_A0

BI

XDP_PCH_OBSDATA_A1

BI

XDP_PCH_OBSDATA_A2

BI

XDP_PCH_OBSDATA_A3

BI

XDP_PCH_OBSDATA_B0

BI

XDP_PCH_OBSDATA_B1

BI

XDP_PCH_OBSDATA_B2

BI

XDP_PCH_OBSDATA_B3

BI

XDP_PCH_OBSFN_C0

BI

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1810
TP1811
TP1812
TP1813
TP1814
TP1815
TP1816
TP1817
TP1818

14

14

14

Non-XDP Signals

XDP_JTAG_ISP_TDO

BI

XDP_JTAG_ISP_TCK

BI

XDP_JTAG_ISP_TDI

BI

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1819
TP1826
TP1827

PP1V8_S5

18 80

XDP:YES

1

R1850

100K

5%
1/20W
MF
201

2

PP1V8_S5

18 80

XDP:YES

2
1

6

VCC

U1830

74AUP1G07GF

SOT891

YA

(OD)

NCNC

GND

3

XDP:YES

1

C1830

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U1830.4:7.54MM

SPI_IO2_STRAP_L

4
5

NCNC

PLACE_NEAR=U1830.4:2.54MM

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

XDP_PCH_TDO
XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

R1831

1.5K

MF

XDP:YES

NO_XNET_CONNECTION

21

R1832

49.9

MF

NO_XNET_CONNECTION

NOSTUFF

XDP_PRESENT_L

21

SPI_IO<2>

5%

1/20W

201

(STRAP TO PCH)

1/20W1%

201

18

IN

OUT
OUT

OUT

OUT

121 18 13

121 18 13

121 18 13

13

B

39

A

14

14

14

14

14

14

XDP_USB_EXTA_OC_L

BI

XDP_USB_EXTB_OC_L

BI

XDP_USB_EXTC_OC_L

BI

XDP_USB_EXTD_OC_L

BI

XDP_PCH_OBSDATA_D0

BI

XDP_PCH_OBSDATA_D1

BI

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP1820
TP1821
TP1822
TP1823
TP1824
TP1825

BOM_COST_GROUP=DEBUG

DESIGN: X502/MLB
LAST CHANGE: Mon Jun 15 22:04:28 2015

SYNC_MASTER=ZIFENG SYNC_DATE=05/24/2017

PAGE TITLE

CPU/PCH Merged XDP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

18 OF 200

SHEET

18 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

PP1V8_G3S_WLANBT_VDDIO

35 36 37 116 122

10%
16V

0201

1

2

NC

WLAN_AUDIO_SYNC

100K

5%

1/20W

MF

201

1

2

R1900

C1900

0.1UF

X5R-CERM

1

VCCA VCCB

U1900

SLSV1T34AMU-COMBO

2

CRITICAL

5

NC

UDFN

GND

3

PP3V3_S5

6

4

BA

10%
16V

0201

1

2

C1901

0.1UF

X5R-CERM

WLAN_AUDIO_SYNC_LS3V3

15 16 19 80

OUTIN

D

15 38 36

C

PCIE CLKREQS

PP1V8_S5
PP3V3_S5

R1940
R1941

R1942

R1944

100K

100K

47K

47K

21

5% 1/20W MF 201

21

21

21

PCH_WLAN_CLKREQ_L

5% 1/20W

PCH_GPU_CLKREQ_L

1/20W5%

12

1/20W MF5%

37 12

MF 201

MF 201

12 13 15 16 20 52 80

15 16 19 80

TBT_X_CLKREQ_L

TBT_T_CLKREQ_L

5% MF1/20W 201

1/20W 201MF

5%201

R1943

R1945

1K

1K

27 12

105 12

PCH_WLAN_CLKREQ_R_L

21

21

GPU_CLKREQ_L_R

MAKE_BASE=TRUE

GPU_CLKREQ_L_R

36

19

Will be reomved

NOSTUFF

R1910

MF 5%1/20W

0201

21

PCIE_WAKE_LAP_PCIE_WAKE_L

0

12 37 36

OUTIN

C

B

95 93

PP1V8_G3S

116

PLACE_NEAR=U1950.1:2mm

19

1

C1950

0.1UF

10%

6.3V

2

CERM-X5R
0201

2
3

NLSX4402

UDFN-COMBO

IO/VL1
IO/VL2

1

8

VCCVL

U1950

IO/VCC1
IO/VCC2

PP3V3_S0_GPU

1

C1951

0.1UF

10%

6.3V

2

CERM-X5R
0201

7
6

GPU_CLKREQ_LGPU_CLKREQ_L_R

NCNC

PLACE_NEAR=U1950.8:2mm

1

R1952

47K

5%
1/20W
MF
201

2

115

B

103

BI

R1950

0

IN

GPUFB_PGOOD

MF

21

5%1/20W0201

GPU_CLKREQ_EN

5

EN

GND

4

A

8

SYNC_MASTER=SILU SYNC_DATE=08/09/2017

PAGE TITLE

A

Chipset Support 1

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

19 OF 200

SHEET

19 OF 131

1

SIZE

D

678

3 245

1

NC ALIASES 3

MAKE_BASE=TRUE

NC_PCH_CLK32K_RTCX2

12

SIGNAL ALIASES

NC_PCH_CLK32K_RTCX2

D

12 13 15 16 19 52 80

119 46 12

PP1V8_S5

IN

PLACE_NEAR=U2072.1:5MM

C2072

0.1UF

10%
16V

X5R-CERM

0201

13

PCH_DISPA_BCLK

13

PCH_DISPA_SDI

13

Platform Reset Connections

PP3V3_S5

10%
16V

0201

1

PLACE_NEAR=U2072.6:5MM

2

1

C2073

0.1UF

2

1

VCCA VCCB

6

X5R-CERM

80

Placement study first

PCH_DISPA_SDO

18 118

NC_ITPXDP_CLK100MN

18 118

NC_ITPXDP_CLK100MP

eSPI Analyzer

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCH_DISPA_BCLK
PCH_DISPA_SDI
PCH_DISPA_SDO

TRUE

TRUE

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP

5

5

5

D

U2072

NC

SLSV1T34AMU-COMBO

2

5

NC

UDFN

GND

3

93

4

BA

PLT3V3_RST_LPLT_RST_L

R2061

100K

5%

1/20W

MF

201

ESPI_DBG
ESPI_DBG

1

118 39 12

118 39 12

100K

2

2 1

100K

2 1

R2000

5% 2011/20W MF

R2001

5% 2011/20W MF

TBT_X_PCI_RESET_L

TBT_T_PCI_RESET_L

OUT

OUT

29 27 14

105 14

118 39 12

118 39 12

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3> ESPI_IO_DBG<3>

R2050
R2051
R2052
R2053

0
0

ESPI_DBG
ESPI_DBG

21

5%

21

5%

1/20W MF

21

5%01/20W MF

21

5%01/20W MF

0201
0201
0201
0201

ESPI_IO_DBG<0>

MF1/20W

ESPI_IO_DBG<1>

ESPI_IO_DBG<2>

39 12

ESPI_CS_L

ESPI_DBG

NC

J2001

M-ST-SM

1413

21
43
65
87
109
1211

505070-1222

ESPI_RESET_L

NC

ESPI_CLK60M_DBG

NC
NC
NC

119 39 12

0201 1/20WMF

R2055

ESPI_DBG

0

21

ESPI_CLK60M_PCH

5%

20 12

C

R2060

100K

5%

1/20W

MF

201

15

100K

2 1

1

2

100K

2 1

R2002

5% 2011/20W MF

R2005

5% 2011/20W MF

PCH_WLAN_PERST_L

SOC_PERST_L

OUT

OUT

37 36 13

39 15

ESPI_CLK60M_PCH

20 12

0201 1/20WMF

R2054

16

0

21

ESPI_CLK60M

5%

OUT

39

C

B

B

A

8

A

SYNC_DATE=05/18/2017SYNC_MASTER=ZIFENG

PAGE TITLE

Chipset Support 2

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

20 OF 200

SHEET

20 OF 131

1

SIZE

D

678

3 245

1

D

DDR4 VDDQ = 1.2V

----------------­ MIMINUM Step Size = 0.50% * VDDQ = 6.0mV per step

TYPICAL Step Size = 0.65% * VDDQ = 7.8mV per step
MAXIMUM Step Size = 0.80% * VDDQ = 9.6mV per step

KBL PLATFORM GUIDE Page.102 FOR DDR4 X8 MEMORY DOWN

-------------------------------------------------­ DDR0_VREF_DQ = Not Used
DDR1_VREF_DQ = Reference For Channel B

DDR_VREF_CA = Reference For Channel A

D

CPU-Based Margining

VRef Dividers

C

B

PP1V2_S3

115

C

1

R2241

1.8K

1%
1/20W
MF
201

R2243

7

IN

7

IN

CPU_DIMMB_VREFDQ

1

2

CPU_DIMM_VREFCA

1

2

2.7

1/20W

5%
MF

201

21

PLACE_NEAR=R2241.2:1mm

C2240

0.022UF

10%

6.3V
X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

2.7

1/20W

5%
MF

201

21

PLACE_NEAR=R2261.2:1mm

C2260

0.022UF

10%

6.3V
X5R-CERM
0201

MEM_VREFCA_A_RC

R2242

1.8K

1/20W

R2240

24.9

1%

1/20W

MF

201

R2262

1.8K

1/20W

R2260

24.9

1%

1/20W

MF

201

1%
MF

201

21

1%
MF

201

21

1

2

1

2

2

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

1

R2261

1.8K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

115

115

B

A

8

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

A

DDR4 VREF Margining

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

BOM_COST_GROUP=DRAM

67

35 4

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

22 OF 200

SHEET

21 OF 131

1

SIZE

D

678

RepairLap.com

3 245

1

D

23 22 7

26

C

C2307

0.47UF

CERM-X5R-1

26
23
22
7

MEM_A_A<0>

23
7

MEM_A_A<1>

22
26

MEM_A_A<2>

23
7

MEM_A_A<3>

22
26

7

MEM_A_A<4>

22
23

MEM_A_A<5>

26

23
7

MEM_A_A<6>

22
26

7

MEM_A_A<7>

22
23

MEM_A_A<8>

26

23
7

MEM_A_A<9>

22
26

MEM_A_A<10>

23
7

MEM_A_A<11>

22
26

7

MEM_A_A<12>

22
23

MEM_A_A<13>

26

23
7

MEM_A_A<14>

22
26

MEM_A_A<15>

23
7

MEM_A_A<16>

22
26

23
7

MEM_A_BA<0>

22
26

MEM_A_BA<1>

23
7

MEM_A_BG<0>

22
26

7

MEM_A_BG<1>

22
23
26

23
7

MEM_A_PAR

22
26

MEM_A_ACT_L

26
23
22
7

MEM_A_CKE<0>

23
7

MEM_A_CS_L<0>

22
26

7

MEM_A_ODT<0>

22
23
26

23

MEM_A_CKE<1>

7
22
26

MEM_A_CS_L<1>

23
7

MEM_A_ODT<1>

22
26

26
24
22

MEM_RESET_L

23
25

118
23
7

MEM_A_CLK_P<0>

22
26

7

MEM_A_CLK_N<0>

22
23
26
118

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

H1

F9

F1

C7

VDD

VDD

VDD

VDD

OMIT_TABLE

16GB-64X8X2-2400

VSS

E9

VSS

G1

VSS

C8

VSS

E1

N9

M1

J9

VDD

VDD

VDD

U2300

MT40A2G8-NRE

FBGA

VSS

VSS

VSS

K9

K1

H9

A1

N1

B2

VDD

VSS

22 23 26 115

E8

E2

C9

C1

B8

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

PP1V2_S3

C2317

0.47UF

CERM-X5R-1

C2

MEM_A_DQ<0>

B7

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

D7

MEM_A_DQ<3>

D2

MEM_A_DQ<4>

D8

MEM_A_DQ<5>

E3

MEM_A_DQ<6>

E7

MEM_A_DQ<7>

C3

MEM_A_DQS_P<0>

B3

MEM_A_DQS_N<0>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

MEM_A_TEN MEM_A_TENMEM_A_TENMEM_A_TEN

B9

MEM_A_ZQ<0>

240

1%

1/20W

MF

201

2

1

R2300

C2308

0.047UF

10%

6.3V
X5R
201

1

25 24 23 22

2

22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26

26 23 22

115

26 23 22 7

26 23 22 7

26 23 22

26 23 22 7

22 23 115

26 23 22

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26

26 23 22 7

26 23 22 7

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

7

MEM_A_PAR
MEM_A_ACT_L

7

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

16GB-64X8X2-2400

OMIT_TABLE

VSS

VSS

VSS
E9

E1

C8

U2310

MT40A2G8-NRE

VSS

VSS

VSS

K1

H9

G1

FBGA

VSS
K9

22 23 26 115

C9

C1

B8

B2

A1

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

VSS

A2

N1

VDDQ

VDDQ

VSSQ
A8

VDDQ

NF/TDQS_C

VSSQ

VSSQ
D9

D1

E8

E2

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

ALERT*

VPP0
VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

C2

MEM_A_DQ<8>

B7

MEM_A_DQ<9>

D3

MEM_A_DQ<10>

D7

MEM_A_DQ<11>

D2

MEM_A_DQ<12>

D8
E3

MEM_A_DQ<14>

E7

MEM_A_DQ<15>

C3

MEM_A_DQS_P<1>

B3

MEM_A_DQS_N<1>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

B9

MEM_A_ZQ<1> MEM_A_ZQ<2>

R2310

1/20W

240

1%
MF

201

C2318

0.047UF

2

1

10%

6.3V
X5R
201

125 118

26 23 22 7

125 118

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22 7

26 23 22 7

23 22 7

26

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

26 23 22 7

26 23 22 7

22 23 26 115

26 23 22 7

7

26 23 22 7

26 23 22

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

1

26 23 22 7

2

26 25 24 23 22

118 26 23 22 7

118 26 23 22 7

A1

N1

B2

VDD

VSS

22 23 26 115

E8

E2

C9

C1

B8

VDDQ

VDDQ

VSSQ

A8

VDDQ

VDDQ

NF/TDQS_C

VSSQ

VSSQ

D9

D1

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

A9

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

A2

ZQ

C2
B7

MEM_A_DQ<17>

D3

MEM_A_DQ<18>

D7
D2

MEM_A_DQ<20>

D8

MEM_A_DQ<21>

E3

MEM_A_DQ<22>

E7

MEM_A_DQ<23>

C3

MEM_A_DQS_P<2>

B3

MEM_A_DQS_N<2>

A7

PP1V2_S3

A3

NC

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

G9

B9

R2320

240

1%

1/20W

MF

201

PP1V2_S3

C2327

0.47UF

CERM-X5R-1

22 7

MEM_A_A<0> MEM_A_DQ<16>

26 23

MEM_A_A<1>

22 7

MEM_A_A<2>

26 23

MEM_A_A<3> MEM_A_DQ<19>
MEM_A_A<4>
MEM_A_A<5>MEM_A_DQ<13>

22 7 125 118
26 23

MEM_A_A<6>

22 7
26 23

MEM_A_A<7>

22 7
26 23

MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

20%

4V

201

1

2

NC

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

U2320

16GB-64X8X2-2400

MT40A2G8-NRE

OMIT_TABLE

VSS

VSS

VSS

VSS

VSS

K9

G1

H9

K1

E1

E9

VDD

FBGA

VSS

C2328

0.047UF

2

1

10%

6.3V
X5R
201

1

2

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26
115

26 23 22

26 23 22 7

26 23 22 7

26 23 22

26 23 22 7

22 23 115

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

26 23 22 7

25 24 23 22

26 23 22 7

26 23 22 7

26

C2337

0.47UF

20%

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

MEM_A_PAR

7

MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>

26

MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

201

4V

1

2

NC

PP1V2_S3

C7

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2330

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

VSS

VSS

VSS

K1

K9

VSS
N1

VSS
E1

VSS
E9

VSS
G1

H9

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

C2
B7
D3
D7
D2
D8
E3
E7

C3
B3

A7
A3

L9

B1
M9

J1

G9

B9

MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

PP1V2_S3

NC

MEM_A_ALERT_L

PP2V5_S3

C2338

0.047UF

MEM_A_ZQ<3>

240

1%

1/20W

MF

201

2

1

R2330

10%

6.3V
X5R
201

D

118
125

125 118

125 118

125 118

125 118

125 118

125 118

125 118

118
125

118
125

26
22
23
115

23
7
22
26

C

115
22
23

1

2

B

PP2V5_S3

C2350

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2300

2.2UF

20%

6.3V

X5R-CERM

0201

22 23 115

1

2

1

C2351

1.0UF

0201-1

C2301

2.2UF

2

X5R-CERM

20%

6.3V
X5R

20%

6.3V

0201

1

2

C2352

1.0UF

22 23 26 115

1

C2302

2.2UF

2

X5R-CERM

20%

6.3V
X5R

0201-1

20%

6.3V

0201

1

2

1

C2353

1.0UF

0201-1

C2303

2.2UF

2

X5R-CERM

20%

6.3V
X5R

20%

6.3V

0201

1

2

1

C2354

1.0UF

C2310

2.2UF

2

X5R-CERM

20%

6.3V
X5R

0201-1

20%

6.3V

0201

1

2

1

C2355

1.0UF

6.3V

0201-1

C2311

2.2UF

2

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2356

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2357

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2358

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2359

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2360

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2361

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2362

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

20%

1

2

C2312

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2313

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2304

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2305

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2306

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1.0UF

20%

6.3V
X5R

0201-1

C2370

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2363

1.0UF

0201-1

C2309

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2364

1.0UF

0201-1

C2314

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2365

1.0UF

0201-1

C2315

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2316

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2371

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2319

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

PP1V2_S3

C2320

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

PP1V2_S3

C2321

2.2UF

20%

6.3V

X5R-CERM

0201

C2380

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

22 23 26 115

1

2

C2322

22 23 26 115

1

2

1

2.2UF

20%

6.3V

X5R-CERM

2

0201

C2381

0.1UF

10%

6.3V
CERM-X5R
0201

C2323

2.2UF

20%

6.3V

X5R-CERM

0201

C2382

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2330

2.2UF

2

X5R-CERM

C2383

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

6.3V
0201

1

2

C2331

2.2UF

20%

6.3V

X5R-CERM

0201

C2384

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2332

2.2UF

20%

6.3V

X5R-CERM

0201

C2385

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2333

2.2UF

20%

6.3V

X5R-CERM

0201

C2386

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2324

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2325

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

5x 0.1uF per chip

C2387

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2388

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2326

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2389

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2390

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2372

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2391

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2329

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2392

0.1UF

10%

6.3V

2

CERM-X5R
0201 0201

C2334

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2393

0.1UF

10%

6.3V

2

CERM-X5R

C2335

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2394

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

1

C2395

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2336

0.1UF

10%

6.3V
CERM-X5R
0201

1

C2396

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2397

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2373

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2398

0.1UF

10%

6.3V
CERM-X5R
0201

C2339

1

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2399

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

BOM_COST_GROUP=DRAM

PAGE TITLE

DDR4 SDRAM Channel A 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

23 OF 200

SHEET

22 OF 131

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

C2407

0.47UF

20%

CERM-X5R-1

4V

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7

N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2400

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

C2

MEM_A_DQ<32>

B7

MEM_A_DQ<33>

D3

MEM_A_DQ<34>

D7

MEM_A_DQ<35>

D2

MEM_A_DQ<36>

D8

MEM_A_DQ<37>

E3

MEM_A_DQ<38>

E7

MEM_A_DQ<39>

C3

MEM_A_DQS_P<4>

B3

MEM_A_DQS_N<4>

A7
A3

NC

125 118

22 7
26 23

125 118

22 7
26 23

22 7

125 118

26 23

26 23 22 7

22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23
22 7

125 118

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

22 7
26 23

26 23 22 7

22 23 26 115

26 23 22 7

C2417

0.47UF

20%

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

4V

201

1

2

NC

PP1V2_S3

C7

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

H1

F9

F1

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

N9

M1

J9

VDD

VDD

VDD

U2410

MT40A2G8-NRE

FBGA

22 23 26 115

C9

C1

B8

B2

A1

VDD

VDDQ

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

E8

E2

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

NF/TDQS_C

C2

MEM_A_DQ<40>

B7

MEM_A_DQ<41>

D3

MEM_A_DQ<42>

D7

MEM_A_DQ<43>

D2

MEM_A_DQ<44>

D8

MEM_A_DQ<45>

E3

MEM_A_DQ<46>

E7

MEM_A_DQ<47>

C3

MEM_A_DQS_P<5>

B3

MEM_A_DQS_N<5>

A7

PP1V2_S3

A3

NC

125 118

22 7
26 23

125 118

22 7
26 23

22 7

125 118

26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

125 118

22 7
26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

125 118

26 23 22

26 23 22 7

22 23 26

26 23 22

115

26 23 22 7

C2427

0.47UF

CERM-X5R-1

MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

7

MEM_A_BA<0>
MEM_A_BA<1>

7

MEM_A_BG<0>
MEM_A_BG<1>

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

H1

F9

F1

C7

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

A1

N9

M1

J9

VDD

VDD

VDD

VDD

U2420

MT40A2G8-NRE

FBGA

22 23 26 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

NF/TDQS_C

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

C2

MEM_A_DQ<48>MEM_A_A<0>

B7

MEM_A_DQ<49>

D3

MEM_A_DQ<50>

D7

MEM_A_DQ<51>

D2

MEM_A_DQ<52>

D8

MEM_A_DQ<53>

E3

MEM_A_DQ<54>

E7

MEM_A_DQ<55>

C3

MEM_A_DQS_P<6>

B3

MEM_A_DQS_N<6>

A7

PP1V2_S3PP1V2_S3

A3

NC

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

125 118

23 22 7

26

26 23 22 7

23 22 7

26

26 23 22 7

C2437

0.47UF

CERM-X5R-1

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<16>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>
MEM_A_BG<1>

20%

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3
N2

J7
N8

H2

H7

H8

N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

U2430

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

22 23 26 115

E2

C9

C1

B8

B2

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

VDDQ

NF/TDQS_C

E8

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2

MEM_A_DQ<56>

B7

MEM_A_DQ<57>

D3

MEM_A_DQ<58>

D7

MEM_A_DQ<59>

D2

MEM_A_DQ<60>

D8

MEM_A_DQ<61>

E3

MEM_A_DQ<62>

E7

MEM_A_DQ<63>

C3

MEM_A_DQS_P<7>

B3

MEM_A_DQS_N<7>

A7

PP1V2_S3

A3

NC

D

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

22 23
26 115

22 7
26 23

22 7

C

26 23

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

26
24
22
23
25

26 23 22 7

22 7

118 26 23

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_A

G9

MEM_A_TEN

MEM_A_ZQ<4>

B9

R2400

240

1/20W

201

1%
MF

2

1

C2408

0.047UF

10%

6.3V
X5R
201

7

26 23 22 7

26 23 22 7

22 23 115

26 23 22 7

26 23 22 7

26 23 22 7

26 23 22 7

1

25 24 23 22

2

26 23 22 7

26 23 22 7

26 23 22

7

26 23 22

23 22

115

26

118

118

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A2

VSSQ

A8

VSSQ

D1

RFU/TEN

VSSQ

A9

D9

ALERT*

VPP0
VPP1

VREFCA

ZQ

VSSQ

L9

MEM_A_ALERT_L

B1
M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

MEM_A_TEN MEM_A_TEN MEM_A_TEN

B9

MEM_A_ZQ<5>

R2410

240

1/20W

201

2

1%
MF

1

C2418

0.047UF

10%

6.3V
X5R
201

1

2

26 23 22 7

7

26 23 22

26 23 22 7

22 23 115

26 23 22

26 23 22 7

26 23 22 7

115 23 22

26 23 22

26 23 22 7

26 23 22 7

25 24 23 22

26 23 22 7

26 23 22 7

26

MEM_A_PAR
MEM_A_ACT_L

7

MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_ODT<0>

7

MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<1>

MEM_RESET_L

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ
A9

ZQ

L9

MEM_A_ALERT_L

B1

PP2V5_S3PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

B9

MEM_A_ZQ<6>

R2420

240

1/20W

201

2

1%
MF

1

C2428

0.047UF

10%

6.3V
X5R
201

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

26 23 22 7

23 22 7

26 23 22 7

1

23 22 7

2

25 24 23 22

26 23 22 7

26 23 22 7

MEM_A_PAR
MEM_A_ACT_L

MEM_A_CKE<0>

26

MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_CKE<1>

26

MEM_A_CS_L<1>
MEM_A_ODT<1>

26

MEM_RESET_L

26

MEM_A_CLK_P<0>

118

MEM_A_CLK_N<0>

118

N3

H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A8

A2

VSSQ

VSSQ

D1

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

A9

D9

VPP0

VPP1

ZQ

L9

MEM_A_ALERT_L

B1

PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_A

J1

G9

MEM_A_ZQ<7>

B9

R2430

240

1/20W

1%
MF

201

C2438

0.047UF

2

1

10%

6.3V
X5R
201

23
7
22
26

C

22 23
115

1

2

B

PP2V5_S3

C2450

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2400

2.2UF

20%

6.3V

X5R-CERM

0201

22 23 115

1

2

1

2

C2451

1.0UF

0201-1

C2401

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

C2452

1.0UF

22 23 26 115

1

2

C2402

20%

6.3V
X5R

0201-1

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2453

1.0UF

0201-1

C2403

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

1

2

C2454

1.0UF

0201-1

C2410

2.2UF

X5R-CERM

20%

6.3V
X5R

20%

6.3V
0201

1

2

1

2

C2455

1.0UF

6.3V

0201-1

C2411

2.2UF

X5R-CERM

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2456

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2457

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2458

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2459

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2460

1.0UF

0201-1

20%

6.3V
X5R

1

2

C2461

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

C2406

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
0201

1

C2404

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
0201

1

2

C2413

2.2UF

X5R-CERM

1

2

C2412

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2405

0.1UF

10%

6.3V
CERM-X5R

2

0201

1.0UF

20%

6.3V
X5R

0201-1

C2470

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2462

1.0UF

0201-1

1

C2414

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2463

1.0UF

1

C2409

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
X5R

0201-1

1

2

C2464

1.0UF

0201-1

C2416

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

6.3V
X5R

1

2

C2465

1.0UF

1

C2415

0.1UF

10%

6.3V
CERM-X5R

2

0201

20%

6.3V
X5R

0201-1

1

B

2

1

C2419

0.1UF

10%

6.3V
CERM-X5R

2

0201

C2471

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

A

PP1V2_S3

C2420

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

22 23 26 115

1

C2473

1

C2424

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2487

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

22 23 26 115

1

2

C2422

2.2UF

X5R-CERM

C2481

0.1UF

10%

6.3V
CERM-X5R
0201

1

2

C2421

2.2UF

X5R-CERM

1

C2480

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2423

2.2UF

X5R-CERM

1

C2482

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2430

2.2UF

X5R-CERM

1

C2483

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2431

2.2UF

X5R-CERM

1

C2484

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2432

2.2UF

X5R-CERM

1

C2485

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2433

2.2UF

X5R-CERM

1

C2486

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

5x 0.1uF per chip

1

C2425

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2488

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2426

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2489

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2490

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2472

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2491

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2429

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2492

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2493

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2434

0.1UF

10%

6.3V
CERM-X5R
0201

1

2

C2494

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2435

0.1UF

10%

6.3V
CERM-X5R
0201

C2495

1

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2436

0.1UF

10%

6.3V
CERM-X5R
0201

C2496

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2439

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2497

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2498

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2499

0.1UF

10%

6.3V

2

CERM-X5R
0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

DDR4 SDRAM Channel A 2

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

24 OF 200

SHEET

23 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

25 24 7

26

25 24 7

26

25 24 7

26

C

25 24 7

26

25 24 7

26

C2507

0.47UF

CERM-X5R-1

25

MEM_B_A<0>

7
24
26

MEM_B_A<1>

25

MEM_B_A<2>

7
24
26

MEM_B_A<3>

7
24
25

MEM_B_A<4>

26

25

MEM_B_A<5>

7
24
26

MEM_B_A<6>

7
24
25

MEM_B_A<7>

26

25

MEM_B_A<8>

7
24
26

MEM_B_A<9>

25

MEM_B_A<10>

7
24
26

MEM_B_A<11>

7
24
25

MEM_B_A<12>

26

25

MEM_B_A<13>

7
24
26

MEM_B_A<14>

25

MEM_B_A<15>

7
24
26

MEM_B_A<16>

7
24
25
26

25

MEM_B_BA<0>

7
24
26

MEM_B_BA<1>

7
24
25

MEM_B_BG<0>

26

25

MEM_B_BG<1>

7
24
26

MEM_B_PAR

25

MEM_B_ACT_L

7
24
26

25

MEM_B_CKE<0>

7
24
26

MEM_B_CS_L<0>

7
24
25

MEM_B_ODT<0>

26

25

MEM_B_CKE<1>

7
24
26

MEM_B_CS_L<1>

7
24
25

MEM_B_ODT<1>

26

26
24

MEM_RESET_L

22
23
25

118
25

MEM_B_CLK_P<0>

7
24
26

7

MEM_B_CLK_N<0>

24
25
26
118

20%

4V

201

NC

PP1V2_S3

1

2

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

H1

F9

F1

C7

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

VSS

E9

VSS

G1

VSS

C8

VSS

E1

N9

M1

J9

VDD

VDD

VDD

U2500

MT40A2G8-NRE

FBGA

VSS

VSS

VSS

K9

K1

H9

A1

VDD

VSS

N1

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

VDDQ

DQ0
DQ1
DQ2
DQ3

VPP0

VPP1

ZQ

1

2

NC

PP1V2_S3

C7

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2530

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

VSS

VSS

VSS

K1

K9

VSS
N1

VSS
E1

VSS
E9

VSS
G1

H9

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

D1

D9

A9

A2

A8

ZQ

C2

MEM_B_DQ<24>

B7

MEM_B_DQ<25>

D3

MEM_B_DQ<26>

D7

MEM_B_DQ<27>

D2

MEM_B_DQ<28>

D8

MEM_B_DQ<29>

E3

MEM_B_DQ<30>

E7

MEM_B_DQ<31>

C3

MEM_B_DQS_P<3>

B3

MEM_B_DQS_N<3>

A7
A3

NC

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

MEM_B_TENMEM_B_TENMEM_B_TEN

B9

MEM_B_ZQ<3>

R2530

1/20W

PP1V2_S3

C2517

0.47UF

CERM-X5R-1

C2

MEM_B_DQ<0>

B7

MEM_B_DQ<1>

D3

MEM_B_DQ<2>

D7

MEM_B_DQ<3>

D2

MEM_B_DQ<4>

D8

MEM_B_DQ<5>

E3

MEM_B_DQ<6>

E7

MEM_B_DQ<7>

C3

MEM_B_DQS_P<0>

B3

MEM_B_DQS_N<0>

A7

PP1V2_S3

A3

NC

L9

MEM_B_ALERT_L

B1

PP2V5_S3 PP2V5_S3 PP2V5_S3 PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

MEM_B_TEN

B9

MEM_B_ZQ<0> MEM_B_ZQ<1>

R2500

240

1%

1/20W

MF

201

C2508

0.047UF

2

1

10%

6.3V
X5R
201

24 25 115

1

25 24 23 22

2

24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

125 118

26 25 24

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 7

26 25 24 7

26 25 24 7

26

26 25 24 7

26 25 24 7

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

7

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>

7

MEM_B_BG<1>

7

MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>

26

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

16GB-64X8X2-2400

OMIT_TABLE

VSS

VSS

VSS
E9

E1

C8

U2510

MT40A2G8-NRE

VSS

VSS

VSS

K1

H9

G1

FBGA

VSS
K9

24 25 115

C9

C1

B8

B2

A1

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

VSS

A2

N1

VDDQ

VDDQ

VSSQ
A8

VDDQ

NF/TDQS_C

VSSQ

VSSQ
D9

D1

E8

E2

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

ALERT*

VPP0
VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

C2527

0.47UF

20%

CERM-X5R-1

C2

MEM_B_DQ<8>

B7

MEM_B_DQ<9>

D3

MEM_B_DQ<10>

D7

MEM_B_DQ<11>

D2

MEM_B_DQ<12>

D8

MEM_B_DQ<13>

E3

MEM_B_DQ<14>

E7

MEM_B_DQ<15>

C3

MEM_B_DQS_P<1>

B3

MEM_B_DQS_N<1>

A7

PP1V2_S3 PP1V2_S3

A3

NC

L9

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

B9

R2510

1/20W

240

201

2

1%
MF

1

C2518

0.047UF

10%

6.3V
X5R
201

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7 26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

7 26 25 24 7

MEM_B_PARMEM_B_ALERT_LMEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>

26 25 24 7

1

26 25 24 7

2

26 25 24 23 22

118 26 25 24 7

118 26 25 24 7

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

U2520

16GB-64X8X2-2400

MT40A2G8-NRE

OMIT_TABLE

VSS

VSS

VSS

VSS

VSS

G1

H9

K1

E1

E9

N9

VDD

FBGA

VSS

K9

A1

VDD

VSS

N1

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VSSQ

A8

VDDQ

VDDQ

NF/TDQS_C

VSSQ

VSSQ

D9

D1

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

ALERT*

VREFCA

RFU/TEN

VSSQ

A9

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VSSQ

A2

VDDQ

DQ0
DQ1
DQ2
DQ3

VPP0

VPP1

ZQ

C2

MEM_B_DQ<16>

B7

MEM_B_DQ<17>

D3

MEM_B_DQ<18>

D7

MEM_B_DQ<19>

D2

MEM_B_DQ<20>

D8

MEM_B_DQ<21>

E3

MEM_B_DQ<22>

E7

MEM_B_DQ<23>

C3

MEM_B_DQS_P<2>

B3

MEM_B_DQS_N<2>

A7

PP1V2_S3

A3

NC

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_B

G9

B9

MEM_B_ZQ<2>

R2520

240

1/20W

201

2

1%
MF

1

C2528

0.047UF

10%

6.3V
X5R
201

1

2

24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

26 25 24 7

24 25 115

26 25 24

26 25 24 7

26 25 24 7

7

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 23 22

26 25 24 7

26 25 24 7

26

C2537

0.47UF

20%

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>

7

MEM_B_BG<0>
MEM_B_BG<1>

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

201

4V

240

1%
MF

201

C2538

0.047UF

2

1

10%

6.3V
X5R
201

D

118
125

125 118

125 118

125 118

125 118

125 118

125 118

125 118

118
125

118
125

115
24
25

25
7
24
26

C

115
24
25

1

2

B

PP2V5_S3

C2550

PP1V2_S3

C2500

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2501

2.2UF

20%

6.3V

X5R-CERM

0201

C2551

1.0UF

20%

6.3V
X5R

0201-1

24 25 115

1

2

C2502

24 25 115

24 25 115

1

2

2.2UF

20%

6.3V

X5R-CERM

0201

C2552

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2503

2.2UF

X5R-CERM

C2553

20%

6.3V
0201

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2510

2.2UF

X5R-CERM

C2554

20%

6.3V
0201

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2511

2.2UF

20%

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

C2555

1.0UF

20%

6.3V
X5R

0201-1

1

C2556

1.0UF

2

0201-1

20%

6.3V
X5R

1

2

C2557

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2558

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2559

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2560

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2561

1.0UF

20%

6.3V
X5R

0201-1

1

2

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

2

C2512

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2513

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2504

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2505

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2506

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2570

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2509

0.1UF

10%

6.3V

2

CERM-X5R
0201

VDD/VDDQ Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

C2562

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

C2514

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2563

1.0UF

20%

6.3V
X5R

0201-1

1

2

1

2

C2515

0.1UF

10%

6.3V
CERM-X5R
0201

C2564

1.0UF

20%

6.3V
X5R

0201-1

1

C2516

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2565

1.0UF

20%

6.3V
X5R

0201-1

1

C2571

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

1

C2519

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

C2520

2.2UF

6.3V

X5R-CERM

0201

PP1V2_S3

20%

1

2

1

2

C2521

2.2UF

X5R-CERM

C2580

0.1UF

10%

6.3V
CERM-X5R
0201

1

20%

2

6.3V
0201

24 25 115

1

C2581

2

C2522

0.1UF

10%

6.3V
CERM-X5R
0201

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2582

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2523

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2583

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2530

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2584

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2531

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2585

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2532

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

C2586

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2533

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

C2524

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

5x 0.1uF per chip

1

C2587

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2588

2

1

2

0.1UF

10%

6.3V
CERM-X5R
0201

C2525

0.1UF

10%

6.3V
CERM-X5R
0201

C2589

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2526

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2590

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2572

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2591

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2529

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2592

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2534

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2593

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2535

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2594

0.1UF

10%

6.3V
CERM-X5R
0201

C2536

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2595

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2573

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2596

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2539

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2597

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2598

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2599

0.1UF

10%

6.3V

2

CERM-X5R
0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017

PAGE TITLE

DDR4 SDRAM Channel B 1

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

25 OF 200

SHEET

24 OF 131

A

8

67

35 4

2

1

678

3 245

1

D

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

C2607

0.47UF

20%

CERM-X5R-1

4V

201

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3

N2

J7

N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

U2600

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ0
DQ1
DQ2

DQ3
DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

C2

MEM_B_DQ<32>

B7

MEM_B_DQ<33>

D3

MEM_B_DQ<34>

D7

MEM_B_DQ<35>

D2

MEM_B_DQ<36>

D8

MEM_B_DQ<37>

E3

MEM_B_DQ<38>

E7

MEM_B_DQ<39>

C3

MEM_B_DQS_P<4>

B3

MEM_B_DQS_N<4>

A7

PP1V2_S3

A3

NC

26 25 24 7

26 25 24 7

26 25 24 7

24 7

125 118

26 25
24 7

125 118

26 25
24 7

125 118

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25

24 7

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

C2617

0.47UF

20%

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

4V

201

1

2

NC

PP1V2_S3

C7

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

16GB-64X8X2-2400

OMIT_TABLE

A1

N9

M1

VDD

VDD

VDD

VDD

U2610

MT40A2G8-NRE

FBGA

24 25 115

E8

E2

C9

C1

B8

B2

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T
DQS_C

NF/DM*/DBI*/TDQS_T

NF/TDQS_C

VDDQ

DQ0
DQ1
DQ2
DQ3

PP1V2_S3

C2627

0.47UF 0.47UF

CERM-X5R-1

C2

MEM_B_DQ<40>

B7

MEM_B_DQ<41>

D3

MEM_B_DQ<42>

D7

MEM_B_DQ<43>

D2

MEM_B_DQ<44>

D8

MEM_B_DQ<45>

E3

MEM_B_DQ<46>

E7

MEM_B_DQ<47>

C3

MEM_B_DQS_P<5>

B3

MEM_B_DQS_N<5> MEM_B_DQS_N<6>

A7

PP1V2_S3 PP1V2_S3

A3

NC

26 25 24 7 125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

125 118 125 118

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

MEM_B_A<0> MEM_B_DQ<48>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

7

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>
MEM_B_BG<1>

20%

4V

201

NC

1

2

N9

M1

J9

H1

F9

F1

C7

VDD

VDD

VDD

VDD

VDD

VDD

VDD

L3

A0

L7

A1

M3

A2

K7

A3

K3

A4

L8

A5

L2

A6

M8

A7

M2

A8

M7

A9

J3

A10/AP

N2

A11

J7

A12/BC*

N8

A13

H2

WE*/A14

H7

CAS*/A15

H8

RAS*/A16

N7

A17/NC

K2

BA0

K8

BA1

J2

BG0

J8

BG1

16GB-64X8X2-2400

OMIT_TABLE

U2620

MT40A2G8-NRE

FBGA

24 25 115

C9

C1

B8

B2

A1

VDD

VDDQ

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

NF/TDQS_C

E8

E2

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2
B7

MEM_B_DQ<49>

D3

MEM_B_DQ<50>

D7

MEM_B_DQ<51>

D2

MEM_B_DQ<52>

D8

MEM_B_DQ<53>

E3

MEM_B_DQ<54>

E7

MEM_B_DQ<55>

C3

MEM_B_DQS_P<6>

B3

A7
A3

NC

125 118

125 118

125 118

125 118

125 118

125 118

125 118

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

125 118

26 25 24 7

24 25 115

26 25 24

26 25 24 7

MEM_B_A<0>

24 7
26 25

MEM_B_A<1>

24 7
26 25

MEM_B_A<2>

24 7
26 25

MEM_B_A<3>

24 7
26 25

MEM_B_A<4>

24 7
26 25

MEM_B_A<5>

24 7
26 25

MEM_B_A<6>

24 7
26 25

MEM_B_A<7>

24 7
26 25

MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<16>

MEM_B_BA<0>

24 7
26 25

MEM_B_BA<1>
MEM_B_BG<0>

7

MEM_B_BG<1>

C2637

20%

CERM-X5R-1

4V

201

NC

PP1V2_S3

1

2

L3
L7

M3

K7
K3

L8

L2
M8
M2
M7

J3
N2

J7
N8
H2
H7
H8
N7

K2
K8

J2

J8

C7

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
WE*/A14
CAS*/A15
RAS*/A16
A17/NC

BA0
BA1
BG0
BG1

A1

N9

M1

J9

H1

F9

F1

VDD

VDD

VDD

VDD

VDD

VDD

U2630

16GB-64X8X2-2400

MT40A2G8-NRE

FBGA

OMIT_TABLE

24 25 115

E2

C9

C1

B8

B2

VDD

VDDQ

NF/DM*/DBI*/TDQS_T

VDDQ

VDDQ

VDDQ

NF/TDQS_C

E8

VDDQ

VDDQ

DQ4/NC
DQ5/NC
DQ6/NC
DQ7/NC

DQS_T

DQS_C

DQ0
DQ1
DQ2
DQ3

C2

MEM_B_DQ<56>

B7

MEM_B_DQ<57>

D3

MEM_B_DQ<58>

D7

MEM_B_DQ<59>

D2

MEM_B_DQ<60>

D8

MEM_B_DQ<61>

E3

MEM_B_DQ<62>

E7

MEM_B_DQ<63>

C3

MEM_B_DQS_P<7>

B3

MEM_B_DQS_N<7>

A7

PP1V2_S3

A3

NC

D

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

125 118

24 25 115

24 7
26 25

24 7

C

26 25

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26
24
22
23
25

26 25 24 7

24 7

118 26 25

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>

118

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

ZQ

VSSQ
A9

L9

MEM_B_ALERT_L

B1

PP2V5_S3

M9

J1

PP0V6_S3_MEM_VREFCA_B

MEM_B_TEN

G9

B9

MEM_B_ZQ<4>

26

25 24

R2600

240

1%

1/20W

MF

201

C2608

0.047UF

2

1

10%

6.3V
X5R
201

7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

1

2

25 24 23 22

26 25 24 7

26 25 24 7

ZQ

L9

MEM_B_ALERT_L

26 25 24 7

B1

PP2V5_S3 PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_B

J1

MEM_B_TEN MEM_B_TEN MEM_B_TEN

G9

B9

24
25
26

MEM_B_ZQ<5> MEM_B_ZQ<6>

R2610

240

1/20W

201

2

1%
MF

1

C2618

0.047UF

10%

6.3V
X5R
201

1

2

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

26 25 24 7

25 24 23 22

26 25 24 7

26 25 24 7

7

26 25 24 7

26 25 24

26

118

118

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

N3

PAR

H3

ACT*

G3

CKE

G7

CS*

F3

ODT

G2

C0/CKE1

G8

C1/CS1*

F2

C2/ODT1

L1

RESET*

F7

CK_T

F8

CK_C

VSS
C8

VSS
E1

VSS
E9

VSS
G1

VSS
H9

VSS
K1

VSS
K9

VSS
N1

VSSQ

VSSQ
A8

A2

VSSQ

VSSQ
D9

D1

ALERT*

VPP0

VPP1

VREFCA

RFU/TEN

VSSQ
A9

26 25 24

MEM_B_PAR
MEM_B_ACT_L

MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_ODT<0>

115 25 24

MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

26

MEM_B_CLK_P<0>

118

MEM_B_CLK_N<0>

118

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A2

VSSQ

A8

VSSQ

D1

RFU/TEN

VSSQ

A9

D9

ALERT*

VPP0
VPP1

VREFCA

VSSQ

ZQ

L9

MEM_B_ALERT_L

B1
M9

J1

PP0V6_S3_MEM_VREFCA_BMEM_B_CKE<1>

G9

B9

R2620

1/20W

24
25
26

240

1%
MF

201

C2628

0.047UF

2

1

10%

6.3V
X5R
201

26 25 24

26 25 24 7

24 25 115

26 25 24

26 25 24 7

26 25 24 7

26 25 24 7

1

26 25 24 7

2

26 25 24 23 22

118 26 25 24 7

118 26 25 24 7

1

2

25
7
24
26

C

24 25 115

25 24

115

ZQ

L9

MEM_B_ALERT_L

B1

PP2V5_S3

M9

PP0V6_S3_MEM_VREFCA_B

J1

G9

B9

MEM_B_ZQ<7>

R2630

24
25
26

240

1%

1/20W

MF

201

C2638

0.047UF

2

1

10%

6.3V
X5R
201

MEM_B_PAR

7

26 25 24 7

MEM_B_ACT_L

MEM_B_CKE<0>

7

MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_ODT<1>

MEM_RESET_L

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>MEM_B_CLK_N<0>

N3
H3

G3
G7

F3

G2
G8

F2

L1

F7
F8

PAR
ACT*

CKE
CS*
ODT

C0/CKE1
C1/CS1*
C2/ODT1

RESET*

CK_T
CK_C

VSS

C8

E1

VSS

E9

VSS

G1

VSS

H9

VSS

K1

VSS

K9

VSS

N1

VSS

VSSQ

A8

A2

VSSQ

VSSQ

D1

ALERT*

VREFCA

RFU/TEN

VSSQ

VSSQ

A9

D9

VPP0

VPP1

B

PP2V5_S3

C2650

1.0UF

20%

6.3V
X5R

0201-1

PP1V2_S3

C2600

2.2UF

20%

6.3V

X5R-CERM

0201

PP1V2_S3

24 25 115

1

2

1

2

C2651

1.0UF

20%

6.3V
X5R

0201-1

C2601

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

24 25 115

1

2

24 25 115

C2652

1.0UF

20%

6.3V
X5R

0201-1

C2602

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2653

1.0UF

20%

6.3V
X5R

0201-1

C2603

2.2UF

20%

6.3V

X5R-CERM

0201

1

2

1

2

C2654

1.0UF

20%

6.3V
X5R

0201-1

C2610

2.2UF

20%

6.3V

X5R-CERM

0201

1

C2655

1.0UF

2

1

2

C2611

6.3V

0201-1

2.2UF

20%

6.3V

X5R-CERM

0201

Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)

20%
X5R

1

2

C2656

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2657

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2658

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2659

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2660

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2661

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2662

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1

C2604

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
0201

1

2

C2613

2.2UF

X5R-CERM

1

2

C2612

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2605

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2606

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2670

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2609

0.1UF

10%

6.3V

2

CERM-X5R
0201

VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2663

1.0UF

20%

6.3V
X5R

0201-1

1

C2614

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

C2664

1.0UF

0201-1

1

C2615

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

C2665

1.0UF

0201-1

1

C2616

0.1UF

10%

6.3V

2

CERM-X5R
0201

20%

6.3V
X5R

1

2

1

C2671

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2619

0.1UF

10%

6.3V

2

CERM-X5R
0201

B

A

C2620

PP1V2_S3

2.2UF

20%

6.3V

X5R-CERM

0201

C2680

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

2

C2621

2.2UF

6.3V

X5R-CERM

0201

24 25 115

C2681

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

20%

1

2

C2622

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2623

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2630

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2631

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2632

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

C2633

2.2UF

X5R-CERM

20%

6.3V
0201

1

2

1

C2624

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2625

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2626

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2672

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2629

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2634

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2635

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2636

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2673

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2639

0.1UF

10%

6.3V

2

CERM-X5R
0201

5x 0.1uF per chip

A

D

C2682

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2683

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2684

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2685

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2686

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2687

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2688

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2689

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2690

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2691

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

1

C2692

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2693

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2694

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2695

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2696

0.1UF

10%

6.3V

2

CERM-X5R
0201

C2697

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2698

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

C2699

1

0.1UF

10%

2

6.3V
CERM-X5R
0201

BOM_COST_GROUP=DRAM

PAGE TITLE

DDR4 SDRAM Channel B 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02643

REVISION

4.0.0

BRANCH

evt-0

PAGE

26 OF 200

SHEET

25 OF 131

SYNC_DATE=02/09/2017SYNC_MASTER=j380_mlb

SIZE

8

67

35 4

2

1

678

3 245

1

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

D

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

PP0V6_S0_DDRVTT

26 115

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>

MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

R2700
R2701
R2702
R2703

R2704
R2705
R2706
R2707

R2708
R2709
R2710
R2711

R2712
R2713
R2714
R2715

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

C2701,C2721 FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

1

1

C2700

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2702

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2704

2.2UF

20%

2

4V
X5R-CERM
0201

C2701

12PF

5%
NP0-C0G

2

0201
25V

1

C2703

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2705

0.47UF

20%

2

4V
CERM-X5R-1
201

D

C

MEM_A_TEN

23 22

MEM_B_TEN

25 24

1

R2753

100

5%
1/20W
MF
201

2

1

R2755

100

5%
1/20W
MF
201

2

R2752

0

5%

1/20W

MF

0201

R2754

0

5%

1/20W

MF

0201

23 22 7

23 22 7

21

21

MEM_A_TEN_R

NOSTUFF

1

C2752

0.47UF

20%

2

4V
CERM-X5R-1
201

MEM_B_TEN_R

NOSTUFF

1

C2753

0.47UF

20%

2

4V
CERM-X5R-1
201

TP2700

1

TP

TP2701

1

TP

TP-P5

TP-P5

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

23 22 7

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN

MEM_A_A<16>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BG<0>

MEM_A_BG<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CKE<0>

MEM_A_CKE<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_ACT_L

MEM_A_PAR

R2716
R2717
R2718
R2719

R2720
R2721
R2722
R2723

R2724
R2725
R2726
R2727

R2728

36
36
36
36

36
36
36
36

36
36
36
36

36

21
21
21
21

21
21
21
21

21
21
21
21

21

26 115

PP0V6_S0_DDRVTT

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF

1

C2706

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2708

0.47UF

20%

2

4V
CERM-X5R-1
201

C2710

1

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2707

0.47UF

20%

2

4V
CERM-X5R-1
201

C

B

118 23 22 7

118 23 22 7

118 25 24 7

118 25 24 7

7 118

7 118

7

7

7 118

7 118

7

7

MEM Clock Termination

Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM

IN

IN

IN

IN

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>

MEM_A_CLK_N<0>

C2750

NOSTUFF

MEM_A_CLK_P<0>

NOSTUFF

MEM_B_CLK_P<0>

3300PF

10%
10V
X7R-CERM
0201

C2760

3300PF

10%
10V
X7R-CERM
0201

1

PLACE_NEAR=U2430.F8:10mm

2

PLACE_NEAR=U2630.F8:10mm

1

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK_N<1>
NC_MEM_A_CLK_P<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3> MEM_B_ACT_L
NC_MEM_B_CLK_N<1>
NC_MEM_B_CLK_P<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>

PLACE_NEAR=U2430.F8:8mm

PLACE_NEAR=U2430.F7:8mm

PLACE_NEAR=U2630.F8:8mm

PLACE_NEAR=U2630.F7:8mm

R2750

30

5%

1/20W

MF

201

R2751

30

5%

1/20W

MF

201

R2760

30

5%

1/20W

MF

201

R2761

30

5%

1/20W

MF

201

21

MEM_A_CLK0_TERM_R

21

MEM_B_CLK0_TERM_RMEM_B_CLK_N<0>

21

21

C2751

0.01UF

21

10%
25V

X5R-CERM

0201

C2761

0.01UF

21

10%
25V

X5R-CERM

0201

PP0V6_S0_DDRVTT

PP0V6_S0_DDRVTT

26 115

26 115

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

25 24 7

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN
IN
IN
IN

IN

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>

MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_A<16>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BG<0>

MEM_B_BG<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CKE<0>

MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_PAR

R2770
R2771
R2772
R2773

R2774
R2775
R2776
R2777

R2778
R2779
R2780
R2781

R2782
R2783
R2784
R2785

R2786
R2787
R2788
R2789

R2790
R2791
R2792
R2793

R2794
R2795
R2796
R2797

R2798

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21
21
21
21

21

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF
5% 2011/20W MF

5% 2011/20W MF

C2720

1

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2722

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2724

2.2UF

20%

2

4V
X5R-CERM
0201

C2726

1

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2728

0.47UF

20%

2

4V
CERM-X5R-1
201

1

C2730

0.47UF

20%

2

4V
CERM-X5R-1
201

C2721

1

12PF

5%
NP0-C0G

2

0201
25V

1

C2723

2.2UF

20%

2

4V
X5R-CERM
0201

1

C2725

0.47UF

20%

2

4V
CERM-X5R-1
201

C2727

1

0.47UF

20%

2

4V
CERM-X5R-1
201

B

A

8

PP1V2_S3

470

1%

1/20W

MF

201

1

2

23 22 7

25 24 7

12

R2730

IN
IN

IN

MEM_A_ALERT_L
MEM_B_ALERT_L

PCH_DRAM_RESET_L

1

51

1%

1/20W

MF

201

2

R2732

0

5%

1/20W

MF

0201

R2731

21

51

1%

1/20W

MF

201

1

2

R2733

BOM_COST_GROUP=DRAM

67

35 4

22 23 115

MEM_RESET_L

NOSTUFF

1

C2732

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_DATE=02/10/2017SYNC_MASTER=j380_mlb

PAGE TITLE

A

DDR4 Termination

DRAWING NUMBER

25 24 23 22

Apple Inc.

051-02643

REVISION

4.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

evt-0

PAGE

27 OF 200

SHEET

26 OF 131

1

SIZE

D

678

3 245

1

D

C

B

A

1

R2890

3.3K

5%
1/20W
MF
201

2

TBT_X_SPI_CS_L

29

121 27

TBT_X_ROM_WP_L

TBT_X_ROM_HOLD_L

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

118 103

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

DP_X_SNK0_ML_C_P<0>

DP_X_SNK0_ML_C_N<0>

DP_X_SNK0_ML_C_P<1>

DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<2>

DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<3>

DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

DP_X_SNK1_ML_C_N<0>

DP_X_SNK1_ML_C_P<1>

DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<2>

DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<3>

DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

100K

10K

NOSTUFF

100K

100K

100K

100K

100K

100K

R2891

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

21

21

21

21

21

21

21

21

R2864

MF 2011/20W5%

R2839

PU for NVM

MF1/20W5%

R2863

5% 1/20W MF 201

R2873

5% MF1/20W

R2862

MF1/20W5% 201

R2872

1/20W5% MF

R2860

1/20W5% MF

R2861

1/20W 201

MF5%

1

3.3K

5%

1/20W

MF

201

1

2

R2893

3.3K

5%
1/20W
MF
201

2

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

SNK0 AC Coupling

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

C2828

0.1UF

C2829

0.1UF

SNK1 AC Coupling

C2830

0.22UF

C2831

0.22UF

C2832

0.22UF

C2833

0.22UF

C2834

0.22UF

C2835

0.22UF

C2836

0.22UF

C2837

0.22UF

C2838

0.1UF

C2839

0.1UF

PP3V3_TBT_X_SX

TBT_X_BATLOW_L

201

TBT_X_TMU_CLK_IN

201

201

201

TBT_X_TMU_CLK_OUT

DP_XA_HPD

DP_XB_HPD

TBT_XA_USB2_MXCTL

TBT_XB_USB2_MXCTL

PP3V3_UPC_XB_LDO

8

VCC

U2890

8MBIT-3.0V

W25Q80DVUXIE

USON

OMIT_TABLE

CRITICAL

GND EPAD

9

4

21

20%

6.3V

X5R

21

20%
X5R

21

20% 6.3V 0201
X5R

21

20% 0201

6.3V

X5R

21

6.3V

20%
X5R

21

20% 6.3V 0201
X5R

21

20%
X5R

21

20% 6.3V 0201
X5R

21

6.3V

10%
CERM-X5R

21

10%
CERM-X5R

21

20% 0201

6.3V

X5R

21

20%

6.3V 0201

X5R

21

20%

6.3V 0201

X5R

21

20% 0201

6.3V

X5R

21

20% 0201

6.3V

X5R

21

20%

6.3V 0201

X5R

21

20% 02016.3V
X5R

21

20% 02016.3V
X5R

21

10%

6.3V

CERM-X5R

21

10%
CERM-X5R

28 29

1

2

TBT_X_SPI_MOSITBT_X_SPI_CLK
TBT_X_SPI_MISO

R2892

3.3K

1/20W

DI(IO0)

DO(IO1)

5%
MF

201

5
2

1

2

DP_X_SNK0_ML_P<0>

0201

DP_X_SNK0_ML_N<0>

02016.3V

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>

0201

DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>

02016.3V

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

02016.3V

DP_X_SNK1_ML_P<0>

DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>

DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>

DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>

DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P

0201

DP_X_SNK1_AUXCH_N

02016.3V

27

27

27

30 27

31 27

27

27

29

C2890

1UF

10%

6.3V
CERM
402

118 29

118 29

118 29

118 29

29 29

29

R2828

5%
MF

201

5%

1/20W

MF

201

1K

5%

1/20W

MF

201

1

2

1

2

1

R2829

100

5%
1/20W
MF
201

2

NOSTUFF

1

R2836

2.2K

5%
1/20W
MF
201

2

19 12

118 27

118 27

118 27

118 27

118 27

118 27

118 27

OUT

TBT_X_CLKREQ_L

93

OUT

R2830

93

100K

1/20W

OUT

118 27

118 27

118 27

118 27

118 27

R2831

100K

118 27

118 27

118 27

118 27

1

118 27

118 27

118 27

118 27

79 29 27

PP3V3_TBT_X_SX

R2825

100

5%
1/20W
MF
201

2

29

IN

118 29

118 29

118 29

118 29

121 12

121 12

21

121 107 105

121 15

121 107 105

121 107 105

118 32

32

32

32

32

118 32

118 32

30

30

30 27

PCIE_TBT_X_R2D_P<0>

IN

PCIE_TBT_X_R2D_N<0>

IN

PCIE_TBT_X_R2D_P<1>

IN

PCIE_TBT_X_R2D_N<1>

IN

PCIE_TBT_X_R2D_P<2>

IN

PCIE_TBT_X_R2D_N<2>

IN

PCIE_TBT_X_R2D_P<3>

IN

PCIE_TBT_X_R2D_N<3>

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_R_L

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>
DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P
DP_X_SNK0_AUXCH_N

DP_X_SNK0_HPD

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

DP_X_SNK1_ML_P<0>
DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_N

DP_X_SNK1_HPD

IN
IN
IN

OUT

JTAG_ISP_TDI
JTAG_TBT_X_TMS
JTAG_ISP_TCK
XDP_JTAG_ISP_TDO

TBT_X_TEST_EN

121

TBT_X_TEST_PWR_GOOD

USBC_XA_D2R_P<2>

IN

USBC_XA_D2R_N<2>

IN

USBC_XA_R2D_CR_P<2>

OUT

USBC_XA_R2D_CR_N<2>

OUT

USBC_XA_R2D_CR_P<1>

OUT
OUT

BI
BI

USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>

IN

USBC_XA_D2R_N<1>

IN

USBC_XA_AUXLSX1

USBC_XA_AUXLSX2

IN

DP_XA_HPD

I2C_TBT_XA_INT_L

TBT_XA_USB2_MXCTL

27

NC
NC
NC
NC

NC
NC

TBT_XA_USB2_RBIAS

PLACE_NEAR=U2800.H19:3MM

1

Y23
Y22

T23
T22

M23
M22

H23
H22

V19
T19

AC7

AB7
AB9

AC9

AC11

AB11
AB13

AC13

N1
N2

AA2

A5
B5

B3
A3

C2
C1

E2
E1

P1
P2
Y4

AC5

AB5

AC3

AB3

W20

Y20

W19

Y19

R4

W5

A15
B15

A17
B17

A19
B19

B21
A21

H4

J4

E20

D20

T2

M4

R2

H19

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*

DPSNK1_ML0_P
DPSNK1_ML0_N

DPSNK1_ML1_P
DPSNK1_ML1_N

DPSNK1_ML2_P
DPSNK1_ML2_N

DPSNK1_ML3_P
DPSNK1_ML3_N

DPSNK1_AUX_P
DPSNK1_AUX_N

SNK1_HPD

DPSNK2_ML0_P
DPSNK2_ML0_N

DPSNK2_ML1_P
DPSNK2_ML1_N

DPSNK2_ML2_P
DPSNK2_ML2_N

DPSNK2_ML3_P
DPSNK2_ML3_N

DPSNK2_AUX_P
DPSNK2_AUX_N

SNK2_HPD

U0_SSTXP1
U0_SSTXN1
U0_SSRXP1
U0_SSRXN1

TDI
TMS
TCK
TDO

TEST_EN
TEST_PWR_GOOD

ASSRXP2
ASSRXN2

ASSTXP2
ASSTXN2

ASSTXP1
ASSTXN1

ASSRXP1
ASSRXN1

ASBU1
ASBU2

PA_USB2_D_P
PA_USB2_D_N

PA_HPD

PA_I2C_INT

PA_USB2_MXCTL
PA_USB2_RBIAS

U2800

TITAN-RIDGE-DP

CSP

SYM 1 OF 2

OMIT_TABLE

CRITICAL

PCIE GEN3

SOURCE PORT

SINK PORT 2 SINK PORT 1

JTAG USBSS

TBT PORT A

FLASH POC GPIO LC GPIO

TBT PORT B

PCIE_TX0_P
PCIE_TX0_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_TX3_P
PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P

DPSRC_ML0_N

DPSRC_ML1_P

DPSRC_ML1_N

DPSRC_ML2_P

DPSRC_ML2_N

DPSRC_ML3_P

DPSRC_ML3_N
DPSRC_AUX_P

DPSRC_AUX_N

DPSRC_HPD

GPIO_0
GPIO_1

EE_WP*

TMU_CLKOUT

WAKE*

CIO_PLUG_EVENT*

TMU_CLKIN

I2C_SCL

I2C_SDA

USB_FORCE_PWR

FORCE_PWR

BATLOW*

SLP_S3*

RTD3_PWR_EN

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO

EE_CS*

EE_CLK

BSSRXp2
BSSRXn2

BSSTXp2
BSSTXn2

BSSTXp1
BSSTXn1

BSSRXp1
BSSRXn1

BSBU1
BSBU2

PB_USB2_D_P
PB_USB2_D_N

PB_HPD

PB_I2C_INT

PB_USB2_MXCTL

PB_USB2_RBIAS

R2854

200

1%

1/20W

MF

2

201

PLACE_NEAR=U2800.H6:2MM
PLACE_NEAR=U2800.J6:2MM

TF

1/20W

R2855

21

4.75K

0.5%
0201

TBT_X_RBIAS
TBT_X_RSENSE

J6
J5

A23

A1

AC23

AC1

D4

L8

RBIAS

RSENSE
PA_MONDC
PB_MONDC
PC_MONDC
USB_MONDC
TEST_EDM

FUSE_VQPS_64

DEBUG

USB2_ATEST

PCIE_ATEST

MONDC_SVR

VGA_RES

ATEST_P
ATEST_N

THERMDA

V23
V22

P23
P22

K23
K22

F23
F22

T4
N16Y6

AB21
AC21

AC19
AB19

AB17
AC17

AC15
AB15

N4
N5

R5

W1
W2

W4
Y1
Y2
AA1
W6

V2
V1
V5
V4
U2
U1
T5

E5
D22

D23
Y18

W16
W18
Y16

B7
A7

A9
B9

A11
B11

A13
B13

L4
L5

E19
D19

T1

M5

R1
F19

B23
AB23
D5

H5
J9

J11
V8

PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS

NC_DP_X_SRC_ML_P<0>
NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1>

NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2>

NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3>

NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

TBT_X_HDMI_DDC_DATA

TBT_X_HDMI_DDC_CLK
TBT_X_ROM_WP_L

TBT_X_TMU_CLK_OUT
TBT_WAKE_3V3_L
TBT_X_PLUG_EVENT_L

TBT_X_TMU_CLK_IN

I2C_TBT_X_SCL
I2C_TBT_X_SDA

TBT_X_USB_PWR_EN

TBT_X_CIO_PWR_EN

TBT_X_BATLOW_L

PM_SLP_S3_L

TBT_X_RTD3_PWR_EN

USBC_X_RESET_L

TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT

UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK

USBC_XB_D2R_P<2>

USBC_XB_D2R_N<2>

USBC_XB_R2D_CR_P<2>

USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<1>
USBC_XB_R2D_CR_N<1>

USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>

USBC_XB_AUXLSX1

USBC_XB_AUXLSX2

NC
NC

DP_XB_HPD

I2C_TBT_XB_INT_L

TBT_XB_USB2_MXCTL
TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:3MM

1

R2853

200

1%

NC
NC

NC
NC

NC

1/20W
MF
201

2

TBTTHMSNS_X_D1_P

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

IN

BOM_COST_GROUP=TBT

29

29

29

29

27

27

To SPI Flash

31

BI
BI

31

31 27

27

OUT

NOSTUFF

1

R2837

2.2K

5%
1/20W
MF
201

2

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

118 29

118 29

118 29

118 29

118 29

118 29

118 29

118 29

PLACE_NEAR=U2800.N16:2MM

29 20 14

R2851

3.01K

1%

1/20W

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

29

OUT
OUT

OUT
OUT

IN
IN

IN

IN

IN

OUT

IN
IN

OUT
OUT

OUT
OUT

IN
IN

29

29

29

29

29

29

29

29

29

29

29

29

121 27

29

32

32

32

32

105 29

29 14

31 30 29 14

PU at PCH

31 30 29 14

118 29

118 29

118 32

118 32

118 32

118 32

MF

201

131 119 105 14 12

PP3V3_TBT_X_SX

29

IN

PAGE TITLE

57

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

21

PP3V3_TBT_X_SX

29

1

R2835

2.2K

5%
1/20W
MF
201

2

BI

29

1

R2834

2.2K

5%
1/20W
MF

2

201

BI

27

79 29 27

USB-C HIGH SPEED 1

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

BRANCH

PAGE

28 OF 200

SHEET

27 OF 131

1

R2827

100K

5%
1/20W
MF
201

2

SYNC_DATE=05/11/2017SYNC_MASTER=J132

4.0.0
evt-0

D

C

79 29 27

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2931

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2932

1.0UF1.0UF

20%

2

X5R
0201-1

1

C2968

10UF

20%

6.3V

2

CERM-X5R
0402-4

1

C2984

1.0UF 1.0UF

20%

6.3V

2

X5R
0201-1

1

C2933

20%

6.3V6.3V

2

X5R
0201-1

1

C2964

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2985

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2934

1.0UF1.0UF

20%

6.3V

2

X5R
0201-1

1

C2965

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2935

1.0UF

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2966

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1

2

VOLTAGE=3.3V

C2920

1.0UF

20%

6.3V
X5R
0201-1

122 28

1

C2936

1.0UF

20%20%

6.3V

2

X5R
0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R
0201-1

29

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

PP0V9_TBT_X_PCIE

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

PP3V3_TBT_X_ANA
PP3V3_TBT_X_ANA_PCIE
PP3V3_TBT_X_ANA_USB2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY
INTERNAL SWITCH

H11

H9
H12
H13
H15
H16

T12
T13
T15

N6
T11

T9

E8

J18

L19

M19

L18
M18
M16

E16

L16

H18

W11

Y11

Y5

W12

Y12

Y8
AB4
AC4

C23
C22

W13

AB2

D6

W15

Y15

A4

B4

F2

D2

F1

D1

B1

B2

E18
V11
V12
V13

M6
N19
N18
E12
E13
F11
F12
F13
F15

J16

A2
F8
A6
A8
B8

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC6

AC8

B10
AC10
AC12
AC14
AC16
AC18
AC20
AC22

B12

B14
B16
B18
B20
B22

D8
D9

A10
D11
D12

VCC0P9_SVR_PAB_ANA

VCC0P9_SVR_PC_ANA

VCC0P9_SVR_DPAUX_ANA

VCC0P9_SVR_USB_ANA

VCC0P9_SVR_BRD_SENSE
VCC0P9_PCIE

VCC0P9_ANA_PCIE_1

VCC0P9_ANA_PCIE_2

VCC3P3_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

N15

VSS

L15

VSS

V18

F4

VSS

R9

VSS

R12

U2800

TITAN-RIDGE-DP

CSP

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

L12

M15

L9

M9

R15

M1

M2

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VCC0P9_LC

VCC0P9_LVR

VCC0P9_LVR_SENSE

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

VSS

VSS

VSS

VSS

T6

V16

M12

N9

N12

T18

V6
F18

R6
L6
E6
G1

G2
H2

R8
R11
L11
M8
M13
R16
R13
J13
L13
N8
N11
N13
T8
T16
M11

L1
L2
K1
K2

J1
J2
H1

J8
H8
H6

D13

D15
D16
D18
E9
E11
E15
A12
E22
E23
F9
F20
F16
G22
G23
A14
H20
J19
J20
J22
A16
J23
L20
L22
L23
A18
M20
N20
N22
N23
R18
A20
R19
R20
R22
R23
T20
U23
U22
A22
V9
V15
V20
W8
B6
W9
W22
W23
Y9
Y13
AA22
AA23
AB6
E4
J15
AB1
AC2
F5
F6
J12

PP3V3_TBT_X_LC
PP3V3_TBT_X_SX

1

C2991

2

1

C2975

10UF

20%

6.3V

2

CERM-X5R
0402-4

122 28

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

DIDT=TRUE
SWITCH_NODE=TRUE

VR0V9_IND_TBT_X

PP0V9_TBT_X_LC

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

Add XW or alias on
support page

XW

XW2900

SM

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

1.0UF

20%

6.3V
X5R
0201-1

1

C2976

10UF

20%

6.3V

2

CERM-X5R
0402-4

C2992

1.0UF

6.3V

0201-1

21

29

PP3V3_TBT_X_F

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C2990

1

C2977

20%

6.3V

2

CERM-X5R
0402-4

CRITICAL

1

C2978

10UF10UF

20%

6.3V

2

CERM-X5R
0402-4

L2950

0.68UH-20%-6.1A-0.020OHM

21

1210

SOURCED BY

20%
X5R

29

1

2

C2993

TBTTHMSNS_X_D1_N

INTERNAL SWITCH

1

1.0UF

20%

6.3V

2

X5R

0201-1

C2954

10UF

CERM-X5R

0402-4

OUT

NOSTUFF

1

C2995

2

1

C2910

1.0UF

20%

6.3V

2

X5R
0201-1

C2951

47UF

20%

6.3V
CER-X5R
0603

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

1

2

1.0UF

20%

6.3V
X5R

0201-1

1

C2950

47UF

20%

6.3V

2

CER-X5R
0603

1

20%

6.3V

2

NOSTUFF

1

C2994

47UF

20%

2

1

C2917

12PF

5%
25V

2

NP0-C0G
0201

6.3V

CER-X5R

0603

1

2

C2955

10UF

20%

6.3V

CERM-X5R

0402-4

2x 10uF outside BGA area

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0V

57

BOM_COST_GROUP=TBT

47UF

20%

6.3V

CER-X5R

0603

1

2

1

2

1

2

L2990

1/10W
MF-LF

C2911

1.0UF

20%

6.3V
X5R
0201-1

C2952

47UF

20%

6.3V
CER-X5R
0603

0

5%

603

FROM USB-C PORT
CONTROLLER (UPC)

21

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

PP3V3_S0SW_TBT_X_SNS

1

C2912

1.0UF

20%

6.3V

2

X5R
0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2982

1.0UF

2

1

C2913

1.0UF

20%

6.3V

2

X5R
0201-1

20%

6.3V
X5R
0201-1

SYNC_MASTER=ADITYA SYNC_DATE=03/30/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

27 29

1

C2980

1.0UF

2

1

C2983

1.0UF

20%

6.3V

2

X5R
0201-1

29 95 116 122

1

C2914

1.0UF

20%

6.3V

2

X5R
0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

1

C2915

1.0UF

20%

6.3V

2

X5R
0201-1

29

20%

6.3V
X5R
0201-1

1

2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

C2916

1.0UF

20%

6.3V
X5R
0201-1

SOURCED BY
INTERNAL SWITCH

USB-C HIGH SPEED 2

DRAWING NUMBER

051-02643

Apple Inc.

REVISION

BRANCH

PAGE

29 OF 200

SHEET

28 OF 131

D

C

B

A

SIZE

D

4.0.0
evt-0

8

67

35 4

2

1

678

3 245

1

D

C

TBT WAKE LEVEL SHIFTER

PP1V8_SLPS2R

29 80
107

SMC HAS IPU

39

TBT_WAKE_L

DP SRC OPTIONS

IF DP SRC NOT USED

27

=DP_X_SRC_ML_P<3..0>
=DP_X_SRC_ML_N<3..0>

27

NC_DP_X_SRC_AUX_P

27

NC_DP_X_SRC_AUX_N

27

FUSES FOR UPC

PP20V_USBC_XA_VBUS

29 30

29 31

PP20V_USBC_XB_VBUS

PP3V3_G3H_RTC_X29 116

Q3001

1

S G

2

PLACE_NEAR=Q3100:5MM

CRITICAL

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

D

TBT_WAKE_3V3_L

3

27

DP_X_SRC_HPD

NC_DP_X_SRC_ML_P<3..0>
NC_DP_X_SRC_ML_N<3..0>
NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

0603

F3000

6AMP-32V-0.0095OHM

PP20V_USBC_XA_VBUS_F

21

PLACE_NEAR=Q3200:5MM

CRITICAL

0603

740S0135

F3001

6AMP-32V-0.0095OHM

PP20V_USBC_XB_VBUS_F

21

1

R3065

100K

5%
1/20W
MF

2

201

INOUT

R3040

100K

1/20W 5% MF 201

MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1

21

29

31

Ridge and ACE PDs

USBC_XA_CC1

30

USBC_XA_CC2

30

29 30

105 29 27

UPC_X_5V_EN

30

TBT_XA_LSTX

30

TBT_XA_LSRX

31

TBT_XB_LSTX

31

TBT_XB_LSRX

USB_UPC_XA_P

30

30

USB_UPC_XA_N

R3032

MF5% 1/20W

R3020
R3021
R3022

1/20W

R3023

1/20W1MMF

R3024
R3025

5% 201

100K

201

2015% MF1/20W

2015% MF1/20W

2015% MF

2015%

MF1/20W5% 201

MF1/20W

1M

1M

1M

1M

1M

21

21

21

21

21

21

21

GND ALIASES

GND

31

30

GND

30

30

30

30

GND

30

GND

31

30

GND

RIDGE 0.9V SVR XW

28

RIDGE ARKANOID CONN

Place on bottom

J3001

M-ST-SM

1413

21
43
65
87
109
1211

1615

505070-1222

TBT_X_PCI_RESET_LTBT_X_PLUG_EVENT_L

USBC_X_RESET_L

PP3V3_TBT_T_ANA_PCIE
PP3V3_TBT_X_ANA
PP3V3_TBT_X_LC

105 29

27

30 27 14

TBT_WAKE_3V3_L

27

TBT_X_CIO_PWR_EN

14 30 30
31

TBT_X_USB_PWR_EN

31
29 30 31

TBT_POC_RESET

28

PP3V3_TBT_X_F

USBC_DBG

ACE A RPD STRAPPING ACE B RPD STRAPPING

MAKE_BASE=TRUE

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

33 30

33 30

USBC_XB_CC1

31

USBC_XB_CC2

31

SIGNAL ALIASES

34

GND
GND
GND
GND

P0V9_TBT_X_SVR_AGND

NO_XNET_CONNECTION=1

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

XW3000

27 20 14 27 14

29 27

79 29 27

106

28

28

SM

29 30

UPC_X_5V_EN
UPC_X_5V_EN

31

USB2_UPC_XB_P

31

USB2_UPC_XB_P

14

USB2_UPC_XB_N

31

14

USB2_UPC_XB_N

USB2_UPC_XA_P29
USB2_UPC_XA_P

14

29

USB2_UPC_XA_N
USB2_UPC_XA_N

14

21

30

UPC_PMU_RESET
UPC_PMU_RESET

31

31

27 29

27 29

27 29

27 29

105 107

105 107

105 107

105 107

USBC_X_RESET_L

UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_T_SPI_CLK
UPC_T_SPI_CS_L
UPC_T_SPI_MOSI
UPC_T_SPI_MISO

UPC_X_5V_EN

MAKE_BASE=TRUE

USB2_UPC_XB_P

MAKE_BASE=TRUE

USB2_UPC_XB_N

MAKE_BASE=TRUE

USB2_UPC_XA_P

MAKE_BASE=TRUE

USB2_UPC_XA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

UPC_PMU_RESET

MAKE_BASE=TRUE

USBC_X_RESET_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

29

27

I2C_UPC_X_SDA2

33 31

33 31

119 107 77 67

30

I2C_UPC_X_SDA2

31

29

30

31

29

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2
I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

30 29

PP20V_USBC_XA_VBUS_F

TBT

Alpine Ridge U2800

(MASTER)

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

27
29

27
29

27
29

I2C SERIES R'S

PLACE_NEAR=U3900.J4:5mm

201

33

33

R3080

I2C_UPC_SDA

21

PLACE_NEAR=U3900.M3:10mm

I2C_UPC_SCL

21

30K

5%

1/20W

MF

201

R3041

5% MF

1/20W

R3042

5% 1/20W MF 201

TBT to ACE

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L
I2C_TBT_XB_INT_L

I2C_UPC_SDA

I2C_UPC_SCL

21

SOC_USB_VBUS

K

DFN1006

BZT52C3V0LP

A

D3080

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L

Sec ACE

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XB_INT_L

Pri ACE

U3100

U3200

51

51

51

51

D

126 119 38

30

30

30

31

31

31

C

IN

TBT_X_XTAL25M_OUT

to/from Ridge

OUT

TBT_X_XTAL25M_IN

TR/ACE SPI BUS SERIES R'S

TBT_X_SPI_CLK

27

B

TBT_X_SPI_CS_L

27

27

TBT_X_SPI_MOSI

27

TBT_X_SPI_MISO

ROM

14

USB3_EXTA_R2D_C_P

IN

DCI

PCH USB3

14

USB3_EXTA_R2D_C_N

IN

A

25MHz xtal

31

42

R3094
R3095
R3096
R3097
R3098
R3090
R3091
R3092
R3093

C3020

0.1UF

21

10%
16V

X5R-CERM

0201

C3021

0.1UF

21

10%
16V

X5R-CERM

0201

14

14

USB3_EXTA_R2D_P
USB3_EXTA_R2D_N

126 119

126 119

47 29

47 29

30

30

C3002

CRITICAL

Y3000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG
UPC_XB_SPI_CLK

1/20W

UPC_XB_SPI_CS_L
UPC_XB_SPI_MOSI

1/20W

UPC_XB_SPI_MISO

1/20W

UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO

MF

2015% 1/20W MF

201

MF 2011/20W5%

MF5% 1/20W 201

OUT
OUT

BI
BI

OUT

BI

BI
BI

100

15
15
15
15
15
15
15
15

21

5% 1/20W MF 201

21

5% MF 201

21

5% 1/20W 201MF

21

5% 201

21

5% MF 201

21
21

5% 1/20W MF

21
21

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

USB_SOC_TYPEC_P
USB_SOC_TYPEC_N

SWD_SOC_SWCLK
SWD_SOC_SWDIO

USBC_XA_USB_TOP_P
USBC_XA_USB_TOP_N

20PF

21

5%
25V
C0G

0201

C3003

20PF

21

5%
25V
C0G

0201

29 116

107 51 39

31

31

Ace

31

31

29 27

AR

29 27

29 27

29 27

29 27

29

29

29

31 30

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

29

IN

IN

IN

OUT

IN

IN

IN

OUT

PP3V3_G3H_RTC_X

PI3USB32324

PCH_USB3_RX_P

3

PCH_USB3_RX_N

4

PCH_USB3_TX_P

6

PCH_USB3_TX_N

7

USB2_EP_P

1

USB2_EP_N

2

SWCLK

24 10

SWDIO

23

ANALOG1

11

ANALOG2

12

ACE ARKANOID CONN

USBC_DBG

I2C_TBT_XB_INT_L
I2C_UPC_X_SCL2
I2C_UPC_X_SDA2

UPC_I2C_INT_L

TBT_X_SPI_CLK_DBG
UPC_XA_UART_TX

NC ALIASES / NO TEST

31

IN

NC_USBC_XA_USB_BOTP30

30

NC_USBC_XA_USB_BOTN

C3022

20

VDD

U3000

QFN-1

5

GND

14

17

USB2_RP_P

USB2_RP_N

USB2_B_P
USB2_B_N

USB2_T_N

USB2_T_P

SDA

SCL

DEBUG1
DEBUG2

EPAD

25

8
9

16
15

18
19

13
22

21

Place on bottom

31

30

IN

IN

J3000

505070-1222

M-ST-SM

NO_TEST=1

1413

21
43
65
87
109
1211

1615

I2C_TBT_XA_INT_L
I2C_TBT_X_SDA

I2C_TBT_X_SCL
I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL
UPC_XA_UART_RX

29 27

29 27

29 27

30 29

30 29

31 30

NC_UPC_XB_I2C_ADDR PCIE_TBT_X_D2R_P<0>

MAKE_BASE=TRUE

NC_USBC_XA_USB_BOTP

MAKE_BASE=TRUE

NC_USBC_XA_USB_BOTN

NO_TEST=1

TBT_POC_RESET

UPC_XA_FAULT_L

UPC_XB_FAULT_L

30

TP_USBC_XA_RESET_L

TBT_X_HDMI_DDC_DATA

27

TBT_X_HDMI_DDC_CLK

27

R3079

5%

POWER ALIASES

27

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XB_LDO
PP3V3_UPC_XA_LDO

30

29 30

PP20V_USBC_XA_VBUS
PP20V_USBC_XB_VBUS

29 31

30 31 107 108

PPDCIN_G3H

109

PP5V_S4_X_USBC

30

31

PP5V_S4_X_USBC
PP5V_S4_X_USBC

34 122

PP3V3_S0SW_TBT_X_SNS

28 95 116 122

30

PP3V3_TBT_X_SX
PP3V3_TBT_X_SX31

PP3V3_TBT_X_SX27 28

PP1V8_SLPS2R30
PP1V8_SLPS2R

31

0

1/20W

0201MF

R3078

0

5% 1/20W
MF 0201

21

DEBUG ALIASES

0.1UF

21

10%
16V

X5R-CERM

0201

USB_DBG_PCH_XA_F_P
USB_DBG_PCH_XA_F_N

USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_BOT_N

USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_TOP_P

I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL

UPC_XA_DBG1
UPC_XA_DBG2

L3000

90-OHM-0.1A

EXCX4CE

SYM_VER-1

4

3 2

PLACE_NEAR=U3000:5mm

BI
BI

BI
BI

BI
BI

BI
BI

USB2_UPC_XA_P

1

USB2_UPC_XA_N

32 29

32 29

32

29

32 29

30 29

30

29

30

30

29

29

Diodes for USB2

USBC_XA_USB_DBG_BOT_P

32 29

USBC_XA_USB_DBG_BOT_N

32

29

USBC_XA_USB_DBG_TOP_N

32 29

USBC_XA_USB_DBG_TOP_P

32 29

PLACE_NEAR=U3000.19:10mm

PLACE_NEAR=U3000.18:10mm

PLACE_NEAR=U3000.15:10mm

PCH_UART_DEBUG_R2D31
PCH_UART_DEBUG_D2R31
SOC_DFU_STATUS30
SOC_FORCE_DFU30

SWD_SOC_SWCLK29 47

PLACE_NEAR=U3000.24:5mm

SWD_SOC_SWDIO29 47

PLACE_NEAR=U3000.23:5mm

PLACE_NEAR=U3000.16:10mm

R3076

5%
MF 0201

R3077

5% 1/20W

K

BAS70LP

DFN1006-2 DFN1006-2

A

D3001

TBT_POC_RESET

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

21

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

TP_USBC_XA_RESET_L

MAKE_BASE=TRUE

TBT_X_HDMI_DDC_DATA

MAKE_BASE=TRUE

TBT_X_HDMI_DDC_CLK

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PPDCIN_G3H

MAKE_BASE=TRUE

PP5V_S4_X_USBC

MAKE_BASE=TRUE

PP3V3_S0SW_TBT_X_SNS

MAKE_BASE=TRUE

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

PP1V8_SLPS2R

PCH_UART_DEBUG_R2D

MAKE_BASE=TRUE

PCH_UART_DEBUG_D2R

MAKE_BASE=TRUE

SOC_DFU_STATUS

MAKE_BASE=TRUE

SOC_FORCE_DFU

MAKE_BASE=TRUE

0

21

1/20W

21

0201MF

K

UPC_XB_DBG3

0

UPC_XB_DBG4

K

BAS70LP BAS70LP

DFN1006-2

A

D3002

A

D3003

OUTIN

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000

K

107 15 31 30 29

14

14

120 95

120 95

31

30

38

BAS70LP

DFN1006-2

A

D3004

122 120 32

79 29 27

126 119 15

126 119 15

131 119 38

BI

BI

122 120 119 32

122 119 68 55 53

29 80 107

131 119 77

31

119

119

31

117
118

117
118

117
118

117
118

117
118

117
118

117
118

118 117

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

IN

IN

IN

IN

IN

IN

IN

PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_R2D_C_N<0>

PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_R2D_C_N<1>

PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_R2D_C_N<2>

PCIE_TBT_X_R2D_C_P<3>

PCIE_TBT_X_R2D_C_N<3>

IN

PCIE_TBT_X_D2R_C_P<0>

IN

PCIE_TBT_X_D2R_C_N<0>

IN

IN

PCIE_TBT_X_D2R_C_N<1>

IN

PCIE_TBT_X_D2R_C_P<2>

IN

PCIE_TBT_X_D2R_C_N<2>

IN

IN

PCIE_TBT_X_D2R_C_N<3>

IN

BOM_COST_GROUP=TBT

Ridge PCIE Caps

GND_VOID=TRUE

0201 X5R 6.3V 20%

GND_VOID=TRUE

0201

GND_VOID=TRUE

GND_VOID=TRUE

0201 X5R 6.3V 20%

GND_VOID=TRUE

0201 6.3V 20%

GND_VOID=TRUE

GND_VOID=TRUE

0201

GND_VOID=TRUE

0201

0201

0201

0201

0201

0201 X5R 6.3V 20%

0201 X5R 6.3V 20%

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6.3VX5R 20%

6.3V 20%

X5R0201

X5R

X5R 6.3V

X5R 20%6.3V

X5R 6.3V 20%

X5R 6.3V 20%

X5R

6.3V0201 20%

X5R

X5R 6.3V 20%

X5R 6.3V 20%

X5R 6.3V 20%

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

20%0201

2 1

0.22UF

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

20%6.3V0201

2 1

0.22UF

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

2 1

0.22UF

USB-C X Support

Apple Inc.

C3040
C3041
C3042
C3043
C3044
C3045
C3046
C3047

GND_VOID=TRUE

C3050

GND_VOID=TRUE

C3051
C3052
C3053
C3054
C3055
C3056
C3057

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2>

PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>

PCIE_TBT_X_R2D_N<3>

PCIE_TBT_X_D2R_N<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<1>PCIE_TBT_X_D2R_C_P<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>

PCIE_TBT_X_D2R_N<3>

GND_VOID=TRUE

DRAWING NUMBER

051-02643

REVISION

BRANCH

PAGE

30 OF 200

SHEET

29 OF 131

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

4.0.0
evt-0

118 27

118 27

118 27

118 27

118 27

118 27

118 27

118 27

SIZE

D

B

118 117

118 117

118 117

118 117

118 117

118 117

118 117

118 117

A

SYNC_DATE=04/19/2017SYNC_MASTER=ADITYA

8

67

35 4

2

1

D

678

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

3 245

1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

29

PP1V8_SLPS2R

1

C3115

1.0UF

20%

6.3V

2

X5R
0201-1

PP20V_USBC_XA_VBUS

29

PP3V3_G3H_RTC_X

116

PP5V_S4_X_USBC

29

CAP FOR PP_5V0 ON VR PAGE

FUSE

Add on
support page

R3169

5%

1

C3100

10UF

20%

6.3V

2

CERM-X5R
0402-1

100K

201MF1/20W

29

21

PHV_INT_XA_G3H

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

C11

B11

A11

PP_5V0

PP_5V0

D11

PP_5V0

PP_5V0

1

C3101

1UF

10%
35V

2

X5R
0402

A8

A7

A6

PP_HV

PP_HV

PP_HV

B7

H10

PP_HV

J10

H11

VBUS

VBUS

PP_CABLE

S2
5

K11

J11

VBUS

G2
4

H1

VBUS

B1

VDDIO

VIN_3V3

3

2

NC

TP_Q3100_DRAIN

UPC_XA_GATE2

G1

H2

LDO_3V3

VOUT_3V3

A2

K1

LDO_1V8A

LDO_1V8D

G1

S1

1

8

UPC_XA_GATE1

E1

LDO_BMC

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20%
4V

2

X5R-CERM
0201

29 31 107 108 109

PP3V3_TBT_X_SX

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R
0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R
0402-1

29

C

B

PP3V3_UPC_XA_LDO

1M

1M

R3109

21

5% 201MF1/20W

R3108

21

5% 1/20W

21

R3105

5%1M1/20W 201MF

29

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

201MF

UPC_XA_UART_RX

31 29

TESTPOINTS MUST BE

30 29

30 29

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

119 77 38

131

31 29 27 14

31 29 27 14

119 39 31

GND I2C_ADDR
PRIMARY ONLY

29

121

27

29

29

29

29

IN
OUT

IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT

IN

TBT_POC_RESET
TP_USBC_XA_RESET_L

UPC_XA_GPIO0

PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

DP_XA_HPD

UPC_PMU_RESET

UPC_X_5V_EN

SOC_DOCK_CONNECT

UPC_XA_FAULT_L

GND

GND

UPC_XA_R_OSC

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

TO SMC

1

2

R3103

31 30 29

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

29

29

29

29

29

51

29

29

29

29

30 29

30 29

BI
BI
OUT

BI
BI
OUT

OUT
OUT
IN
OUT

I2C_UPC_XA_DBG_CTL_SCL
I2C_UPC_XA_DBG_CTL_SDA

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XA_INT_L

I2C_UPC_X_SCL2

UPC_I2C_INT_L
GND

GND
GND
GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL
OMIT_TABLE

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1
C_SBU2

NC

H7
B10

A10
B9

A9

L9
L10

K9
K10

K6
L6

K7
L7

K8
L8

L11

UPC_XA_SS

USBC_XA_CC1
USBC_XA_CC2

USBC_XA_CC1

USBC_XA_CC2
USBC_XA_USB_TOP_P

USBC_XA_USB_TOP_N
NC_USBC_XA_USB_BOTP

NC_USBC_XA_USB_BOTNI2C_UPC_X_SDA2
USBC_XA_SBU1

USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R
0201

BI

BI

BI
BI

29

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

BI

BI

1

C3114

29

BI

29

BI

29

BI

29

BI

120 32

120 32

220PF

10%
16V

2

CER-X7R
0201

1

C3113

220PF

10%
16V

2

CER-X7R
0201

33 29

33 29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

B

A

31 30 29

31 29

27

27

29

29

29

29

TP_UPC_XA_SWD_DATA

TP_UPC_XA_SWD_CLK

IN
OUT

BI
BI

BI
BI
BI
BI

UPC_XA_UART_RX
UPC_XA_UART_TX

TBT_XA_LSTX

29

TBT_XA_LSRX

29

USB_UPC_XA_P

29

USB_UPC_XA_N

29

USBC_XA_AUXLSX1

USBC_XA_AUXLSX2

UPC_XA_DBG1

UPC_XA_DBG2

SOC_DFU_STATUS
SOC_FORCE_DFU

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

L1

B8

H4

H5

G8

H8

D8

GND

E8

GND

F6

GND

F7

GND

F8

GND

G6

GND

G7

PAGE TITLE

SYNC_DATE=05/26/2017SYNC_MASTER=ZIFENG

A

8

USB-C PORT CONTROLLER A

DRAWING NUMBER

051-02643

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

67

29

BOM_COST_GROUP=USB-C

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

4.0.0

BRANCH

evt-0

PAGE

31 OF 200

SHEET

30 OF 131

1

SIZE

D