Apple X1032 Book
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
X1032 MLB BTTF
LAST_MODIFICATION=Thu Aug 9 14:09:34 2018
LAST_MODIFICATION=Thu Aug 9 14:09:34 2018
2 1
ECNREV DESCRIPTION OF REVISION
CK
APPD
DATE
2018-08-0900134733492 ENGINEERING RELEASED
D
1
2
3
1
2
3
44
5
5
6 6
7
8
9
10
11
12
13
8
9
10 03/30/2018
11
12
13
Table of Contents
BOM Configuration
BOM Configuration
PD Parts
CPU GFX
CPU Misc/JTAG/CFG/RSVD
CPU LPDDR3 Interface7
CPU Power
PCH Power
CPU & PCH Grounds
CPU Decoupling 1
CPU Decoupling 2
PCH Decoupling
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
DATESYNCCONTENTSCSAPAGE
03/30/2018
03/30/2018
03/30/2018
03/30/2018
03/30/2018
03/30/2018
03/30/2018
03/30/2018
51
52
60
61
Fans
RIO Connector
Audio Speaker Amplifiers
54 66 Audio Connectors
67
68 02/16/2017
57
58
59
60
61
69
70
71
72
74
62 76
63
78 PMIC BUCKS AND SWs
Keyboard & Trackpad 155
Keyboard & Trackpad 256
DC-In & Battery Connectors
PBUS Supply & Battery Charger
CPU IMVP8 Regulator IC
CPU VCore/VccSA Power Stage
CPU VccGT Power Stage
VR - 5V, 3V3
X1032_MLB_P4BP
AHAAGE_AUD53 64
AHAAGE_AUD
X260_MLB
X589_CARD_IPD
X589_BIGSUR
X1032_MLB_P4BP
J122_MLB
J122_MLB
J122_MLB
X589_BIGSUR
X589_BIGSUR
DATESYNCCONTENTSCSAPAGE
02/13/2017
05/23/2017
04/19/2017
02/16/2017
02/15/2017
02/13/2017
03/30/2018
03/30/2018
03/30/2018
03/01/2017
03/16/2017
D
C
14
15
16
17
19
21
22
23
24
25
26
27
14 PCH Audio/LPC/SPI/SMBus
15 PCH Power Management
16
17
1818
19
2020
22
23
25
27
28
29
30
PCH PCIe/USB/CLK
PCH GPIO/LPSS
CPU/PCH Merged XDP
Chipset Shared Support
Chipset Project Support
LPDDR3 VREF MARGINING 03/30/2018
LPDDR3 DRAM Channel A (0-63)
LPDDR3 DRAM Channel B (0-63)
LPDDR3 DRAM Termination
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2
USB-C SUPPORT
J122_MLB
J122_MLB
J122_MLB 03/30/2018
J122_MLB
X589_CPU_CNL_Y
X589_CPU_CNL_Y
X589_CPU_CNL_Y
J122_MLB
J122_MLB
J122_MLB
T290_CARD_CPU_U
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
03/30/2018
03/30/2018
03/30/2018
03/13/2017
03/27/2017
03/07/2017
03/30/2018
03/30/2018
04/06/2018
02/13/2017
02/13/2017
02/13/2017
64
65
79
PMIC LDOs
PMIC GPIOs & Control80
POWER - VDDQ, VCCIO81
Power FETs
LCD Backlight Driver84
eDP Display Connector
68
69
8267
85
S4E<0>86
71
72 S4E<2>
73 02/13/2017
74
75 02/21/2017
76
77
87 S4E<1>
88
90
91
NAND VCC VR
SSD Support
Power Aliases - 1120
121
122
Power Aliases - 2
Signal Aliases
X589_BIGSUR
X589_BIGSUR
X589_CPU_CNL_Y66
X589_CPU_CNL_Y
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032
X589_CPU_CNL_Y
X589_CPU_CNL_Y
03/16/2017
03/16/2017
03/08/2017
02/22/2017
02/13/2017
02/13/2017
02/13/201770
02/13/2017
02/14/2017
02/21/2017
C
B
28
29
30
31
32
33
34
35
36
37
38
39
31
32
33
34
37
38
39
40
41
42 X589_BIGSUR
43
44
40 45
41
46
USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR
USB-C SUPPORT 2
WIFI/BT MODULE
WIFI/BT Module Support
SoC GPIO/SEP/USB/DDR/Test
SoC AOP/AON/SMC
SoC ISP/I2C/UART/SPI/I2S
SoC PCIe
SoC Power 1
SoC Power 2
SoC Power 3
SoC Ground
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
MKARAKUCUK
X1032_MLB_P4BP
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
02/13/2017
02/13/2017
02/13/2017
03/22/2017
03/03/2017
03/15/2017
03/16/2017
03/15/2017
03/15/2017
02/13/2017
02/13/2017
02/13/2017
02/13/2017
78
79
80
81
123
124
127 Desense Caps 1
128
82 140 04/12/2017
83 BOM Variants 1
84
141
142
85 145
Memory Signal Swaps
ICT FCT
Desense Caps 2
Dev Support
BOM Variants 2
BOM Alternates
J122_MLB
X589_BIGSUR
04/13/2018
B
A
1 SCH CRITICAL SCHEM051-04039 SCH,MLB_BTTF,X1032
1 MLB CRITICAL PCBF820-01521 PCBF,MLB_BTTF,X1032
42
43
44
45
46
47
48
49
50
47
48
50
53
54
55
56
58
SoC Shared Support
SoC Project Support
Secure Element
I2C Connections 152
Power Sensors High Side
Power Sensors Load Side
Power Sensors Extended
Thermal Sensors
X589_BIGSUR
X589_BIGSUR
X941_MLB
X589_BIGSUR
X589_BIGSUR
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
03/16/2017
02/13/2017
03/10/2017
02/13/2017
02/13/2017I2C Connections 2
02/14/2017
02/14/2017
02/14/2017
DRAWING TITLE
A
SYNC_DATE=07/25/2017SYNC_MASTER=CONSTRAINTS_ML
SCHEM,MLB-BTTF,X1032
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
051-04039
REVISION
2.0.0
BRANCH
PAGE
1 OF 145
SHEET
1 OF 85
SIZEDRAWING NUMBER
D
8
3
124567
678
3 245
1
D
C
Module Parts
CPU TBT ROMNAND
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
1
CPU,AML-Y,QQQE,PQS,1.8,1.15,BGA1515
337S00593 CPU_AMLY:QQQF
337S00614
337S00615 CRITICAL
998-15364 CRITICAL1
CPU,AML-Y,QQQF,PQS,1.6,1.05,BGA1515
CPU,AML-Y,QQQG,PQS,1.6,1.05,BGA1515
CPU,AML-Y,QQQM,PQS,H0,1.8,7W,1.15,B1515
CPU,AML-Y,QQQN,PQS,H0,1.6,7W,1.1,B1515
CPU,AML-Y,QQQP,PQS,H0,1.6,7W,1.05,B1515
1 U0500 CPU_AMLY:QQQQ337S00621 CRITICAL
CPU,AML-Y,QQQQ,PQS,H0,1.8,7W,1.15,B1515
1 U0500 CRITICAL337S00622
CPU,AML-Y,QQQR,PQS,H0,1.6,7W,1.1,B1515
CPU,AML-Y,QQQS,PQS,H0,1.6,7W,1.05,B1515
1 CRITICALU0500337S00623
CPU,AML-Y,SREKN,PRQ,1.8,7W,1.15,BGA1515
1 CRITICALU0500337S00624
CPU,AML-Y,SREKP,PRQ,1.6,7W,1.1,BGA1515
1 CRITICALU0500337S00625
CPU,AML-Y,SREKQ,PRQ,1.6,7W,1.05,BGA1515
INTERPOSER,VRTT ADAPTER,KBL-Y,BGA1515
CRITICALU05001
CRITICAL1337S00626 U0500
TBT Titan Ridge
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
338S00305
338S00356 TBT_TR:B01
338S00408 CRITICAL1 U2800
IC,TBT,TITAN RIDGE,QTJE,P-ES,A0,CSP337
IC,TBT,TITAN RIDGE DP,QTZZ,ES2,B0,CSP337
IC,TBT,TITAN RIDGE DP,QTZZ,ES2,C0,CSP337
1 U2800 TBT_TR:C0338S00399 CRITICAL
IC,TBT,TITAN RIDGE DP,QUJK,QS,C1,CSP337
IC,TBT,TITANRIDGE DP,SLMHS,PRQ,C1,CSP337
1338S00441
U28001 TBT_TR:A0CRITICAL
U2800 CRITICAL
U2800 CRITICAL TBT_TR:PRQ
Ace
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96
IC,CD3215,ACE,C00,USB PWRSW,BLNK,NFBGA96
CRITICAL
CRITICAL353S01442 U3100,U32002
Wireless
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
MODULE,WIFI,YEBISU CIDRE,U,ES4.8,LGA160
PART NUMBER
339S00446 339S00448 Murata ModuleALL
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
CRITICAL WIRELESS:USI1 U3700339S00448
TABLE_ALT_HEAD
TABLE_ALT_ITEM
BOM OPTIONCRITICAL
CPU_AMLY:QQQECRITICALU0500337S00592
CPU_AMLY:QQQG337S00594 CRITICALU05001
CPU_AMLY:QQQMCRITICALU05001337S00613
CPU_AMLY:QQQNCRITICALU05001
CPU_AMLY:QQQP1 U0500
CPU_AMLY:QQQR
CPU_AMLY:QQQS
CPU_AMLY:SREKN
CPU_AMLY:SREKP
CPU_AMLY:SREKQ
CPU_AMLY:INTERPOSERU0500
BOM OPTIONCRITICAL
TBT_TR:C1
BOM OPTIONCRITICAL
ACE:C0_BGA353S00961 2 U3100,U3200
ACE:C0_NFBGA
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
335S00273 2 CRITICAL
335S00289 NAND:PMLC_128G_TO
335S00301 U8600,U8700,U88003 NAND:PMLC_128G_SD
335S00302 U8600,U8700,U8800 CRITICAL3
335S00292 NAND:PMLC_512G_TO3 U8600,U8700,U8800 CRITICAL
998-12416
335S00323 3 CRITICALU8600,U8700,U8800 NAND:PMLC_128G_SD_NM
998-12418 U8600,U8700,U8800 NAND:PMLC_256G_TO_NM
998-12423 ALL998-12422 TO 512G Substrate 2
335S00326 3 CRITICAL
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
NAND,1Z,128GBM,S4E,128G,SD,HPN1,ULGA110
NAND,3DV3,42GBP,XXX,S4E,170G,T,ULGA110
3 CRITICALU8600,U8700,U8800
NAND,3DV3,42GBP,XXX,S4E,170G,SD,ULGA110
NAND,3DV3,85GBP,XXX,S4E,170G,T,ULGA110
NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110
NAND,3DV3,170GBP,XXX,S4E,170G,T,ULGA110
NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110
NAND,3DV3,42GBP,S4E,170G,T,SUB X,ULGA110
PART NUMBER
NAND:PMLC_128G_TO_NM
NAND,3DV3,42GBP,XXX,S4E,170G,SD,ULGA110
3 CRITICAL
NAND,3DV3,85GBP,S4E,170G,T,SUB X,ULGA110
PART NUMBER
NAND:PMLC_256G_TO_NM
3335S00324 CRITICALU8600,U8700,U8800 NAND:PMLC_256G_SD_NM
NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110
NAND,3DV3,170GBP,S4E,170G,T,SUBX,ULGA110
3998-12422 CRITICAL
PART NUMBER
NAND:PMLC_512G_TO_NM
NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110
NAND,3DV4,512GBM,S4E,256G,SS,ULGA110
3 CRITICAL335S00322
NAND,3DV4,512GBM,S4E,256G,MG3,SS,ULGA110
U8600,U8700 NAND:HPN1_256G_2L
CRITICAL
U8600,U8700,U8800335S00290 3 CRITICAL
U8600,U8700,U8800 NAND:PMLC_512G_SD
CRITICAL3335S00304
U8600,U8700,U88003 CRITICAL NAND:PMLC_128G_TO_NM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
TO 128G Substrate 2ALL998-12417 998-12416
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ALL998-12418998-12419
TO 256G Substrate 2
U8600,U8700,U8800 NAND:PMLC_512G_TO_NM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
U8600,U8700,U8800 NAND:PMLC_512G_SD_NM
BOM OPTIONCRITICAL
NAND:PMLC_256G_TO
NAND:PMLC_256G_SD
NAND:3DV4_1P5T_SSU8600,U8700,U8800
NAND:3DV4_1P5T_SS_MG3U8600,U8700,U8800 CRITICAL3335S00373
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
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Programmables
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8
IC,NVM (V5.7) PROTO-0,X1032
1
IC,NVM (V1.1) NEW,PROTO-0,X1032
IC,NVM (V5.1) PROTO-1,X1032
1
341S00982 1 CRITICALU2890
IC,NVM (VXXX) PROTO-2,X1032
IC,NVM (VXXX) EVT,X1032
1
IC,NVM (VXXX) PROTO-3,X1032
IC,NVM (VXXX) EVT-2,X1032
U2890335S00133 1 CRITICAL TBT_ROM:BLANK
U2890341S00905 CRITICAL TBT_ROM:P0
U28901 CRITICAL341S00922 TBT_ROM:P0_B0
U2890 CRITICAL341S00942 TBT_ROM:P1
U2890
U28901341S01177
BT ROM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,SPI SERIAL FLASH,2MBIT,1.8V,DFN8
341S00745 BT_ROM:P0CRITICAL1
341S00939 U37701 CRITICAL BT_ROM:P1
341S01176
IC,BT ROM (V4) PROTO-0,X1032
BT SFLASH ROM (V22.33.40) PROTO-1,X1032
1341S00983
BT SFLASH ROM (VXXX) PROTO-2,X1032
1
BT SFLASH ROM (VXXX) EVT,X1032
BT SFLASH ROM (VXXX) EVT-2,X1032
1 U3770 CRITICAL BT_ROM:EVT2
PART NUMBER
U37701
U3770
U3770 CRITICAL341S01042 BT_ROM:EVT
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
CRITICAL335S00256 BT_ROM:BLANK
CRITICALU3770 BT_ROM:P2
TABLE_ALT_HEAD
TABLE_ALT_ITEM
ALL MacronixBT_ROM:BLANK335S00256335S00248
TABLE_ALT_ITEM
335S00256 BT_ROM:BLANK ALL335S00255 Adesto
Wifi ROM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
335S00145 1
341S00744
IC,EEPROM,4KBIT,1.8V,SELECT ORG,TDFN8
WIFI ROM (P101) PROTO-0,WW1,X1032
PART NUMBER
CRITICALU3780 WIFI_ROM:P01
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ALL335S00236 Rohm335S00145 WIFI_ROM:BLANK
SOC ROM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,FLASH,SERIAL,SPI,4MX8,1.8V,4X3MM,DFN8
U4770 SOC_ROM:BLANKCRITICAL1335S00203
BOM OPTIONCRITICAL
TBT_ROM:P2
TBT_ROM:EVT1 CRITICAL341S01046
TBT_ROM:P3U2890341S01150 CRITICAL
TBT_ROM:EVT2CRITICAL
BOM OPTIONCRITICAL
BOM OPTIONCRITICAL
WIFI_ROM:BLANKU3780 CRITICAL
BOM OPTIONCRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
D
C
B
SOC
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
339S00370 1 U3900 SOC:B0_1GCRITICAL
POP,GIBRALTAR+1GB 20NM,M,B0,SCK,CSP1406
PART NUMBER
339S00370 ALL339S00375 Micron 1GB SCKSOC:B0_1G
339S00370 Hynix 1GB ATK339S00376 ALLSOC:B0_1G
POP,GIBRALTAR+2GB 20NM,M,B0,SCK,CSP1406
PART NUMBER
339S00372 SOC:B0_2G339S00378 Hynix 2GB ATKALL
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
ALLSOC:B0_1G Hynix 1GB SCK339S00370339S00371
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
ALL339S00372 Hynix 2GB SCKSOC:B0_2G339S00373
Micron 2GB ATK339S00372339S00377 SOC:B0_2G ALL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
EFI ROM
TABLE_5_HEAD
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
IC,SERIAL FLASH,128MBIT,1.8V,QE=1,WSON8
1 U2100 EFI_ROM:BLANK335S00371
PART NUMBER
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
CRITICAL
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
MacronixALL335S00370 335S00371
TABLE_ALT_ITEM
335S00371335S00376 AdestoALL
TABLE_5_ITEM
SOC:B0_2G339S00372 CRITICALU39001
BOM OPTIONCRITICAL
TABLE_5_ITEM
B
A
PMU
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P
DRAM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,SDRAM,LPDDR3-1866,32GBIT,20NM,BGA253
2 CRITICAL333S00052 DRAM:SAMSUNG_8GBU2300,U2500
2 CRITICALU2300,U2500333S00130 DRAM:SAMSUNG_16GB
IC,LPDDR3-1866,64GBIT,18NM,S,BGA253
2 U2300,U2500333S00110 CRITICAL DRAM:HYNIX_8GB
IC,LPDDR3-1866,32GBIT,21NM,BGA253
IC,LPDDR3-1866,64GBIT,21NM,BGA253
333S00082 CRITICAL2 DRAM:MICRON_8GB_1866U2300,U2500
IC,LPDDR3-1866,32GBIT,20NM,BGA253
IC,LPDDR3-1866,64GBIT,20NM,M,BGA253
2 CRITICAL333S00113 U2300,U2500 DRAM:MICRON_16GB
IC,LPDDR3-2133,32GBIT,20NM,BGA253
U2300,U25002 CRITICAL333S00111
U2300,U25002 CRITICAL333S00199 DRAM:MICRON_8GB
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
CRITICALU78001 PMU:A0_A338S00267
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
DRAM:HYNIX_16GB
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PAGE TITLE
A
BOM Configuration
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04039
REVISION
2.0.0
BRANCH
PAGE
2 OF 145
SHEET
2 OF 85
8
67
35 4
2
1
678
3 245
1
D
BOM Groups
BOM GROUP BOM OPTIONS
MLB_COMMON
MLB_USBC
MLB_PROGPARTS
SCHEM,PCBF,ALTERNATE,COMMON,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH1,MLB_MECH2,MLB_MISC,PVT
TBT_PCIE_4LANES,TBT_TR:PRQ,ACE:C0_BGA
BT_ROM:EVT2,SOC_ROM:BLANK,TBT_ROM:EVT2,WIFI_ROM:P0,SE:PROD_2017
MLB_POWER PMU:A0_A
WIRELESS:USIMLB_WIRELESS
MLB_MECH1
MLB_MECH2
MLB_MISC
BRACKET,BUSBARLONG,BUSBARTOP,BUSBARBOTTOM
SHLD_CAN_DRAM,SHLD_FNC_NAND,SHLD_CAN_TR,SHLD_FNC_SOC,SHLD_CAN_DPLXR
BOARDID0,BOARDID1,BOARDID2,BOARDID4,SYSDET:FET,NAND_VCC:2V5,BOOTCFG0
See <rdar://problem/39661910> for BOARDID straps
Build Specific Groups
BOM GROUP BOM OPTIONS
PROTO3
PREEVT2
PVT
MAF,EFI_ROM:BLANK
BOARDREV0,SAF,PCHFLTR:FERRITE
BOARDREV1,SAF,PCHFLTR:FERRITE
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
DEV PARTS,MLB_BTTF,X1032 DEV_PARTS_BOMDEV11 CRITICAL985-00733
BOM OPTIONCRITICAL
TABLE_5_ITEM
CMN_PARTS_BOMCOMMON PARTS,MLB_BTTF,X10321 CRITICALCBOM685-00251
TABLE_5_ITEM
D
C
NAND Configs
BOM GROUP BOM OPTIONS
NANDCFG:HPN1_256G_2L
NANDCFG:PMLC_128G_TO
NANDCFG:PMLC_128G_SD
NANDCFG:PMLC_256G_TO
NANDCFG:PMLC_256G_SD
NANDCFG:PMLC_512G_TO
NANDCFG:PMLC_512G_SD
NANDCFG:3DV4_1P5T_SS
C
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
NAND:HPN1_256G_2L,SSDJTAG:2L,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_128G_TO_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_128G_SD_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_256G_TO_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_256G_SD_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_512G_TO_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:PMLC_512G_SD_NM,SOC:B0_1G
TABLE_BOMGROUP_ITEM
NAND:3DV4_1P5T_SS_MG3,SOC:B0_2G
B
CPU DRAM SPD Straps
BOM GROUP BOM OPTIONS
DRAMCFG:SAMSUNG_8GB
DRAMCFG:SAMSUNG_16GB
DRAMCFG:HYNIX_8GB
DRAMCFG:HYNIX_16GB
DRAMCFG:MICRON_8GB
DRAMCFG:MICRON_16GB
DRAM:SAMSUNG_8GB,RAMCFG0_L
DRAM:SAMSUNG_16GB,RAMCFG0_L,RAMCFG2_L,RAM_16GB
DRAM:HYNIX_8GB,RAMCFG0_L,RAMCFG1_L
DRAM:HYNIX_16GB,RAMCFG0_L,RAMCFG1_L,RAMCFG2_L,RAM_16GB
DRAM:MICRON_8GB
DRAM:MICRON_16GB,RAMCFG2_L,RAM_16GB
B
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
A
RAMCFGx strap is low if in table.
CPU DRAM CFG Chart
Vendor
Hynix
Samsung
Unused
Micron
CFG 1
0
1
0
1
8
CFG 0
0
0
1
1
Vendor
8GB
16GB
CFG 2
1
0
A
PAGE TITLE
BOM Configuration
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
67
35 4
2
BRANCH
PAGE
3 OF 145
SHEET
3 OF 85
1
SIZE
D
678
3 245
1
Shield Cans
D
Mounting Bracket
806-12895 CRITICAL1
BRKT,MOUNTING,MLB,X1030
DRAM Shield Can
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
SHIELD CAN,DRAM,X1030
BRACKETBRKT1
806-12387
1 CRITICALSHLD1 SHLD_CAN_DRAM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
NAND Shield Fence
D
SHIELD FENCE,MEMORY,SINGLE,X1030
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
SHLD_FNC_NANDSHLD2806-12384 1 CRITICAL
TR Shield Can
TABLE_5_HEAD
SHIELD CAN,TITAN RIDGE,X1030
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
SHLD3806-12386 1 CRITICAL
BOM OPTIONCRITICAL
TABLE_5_ITEM
SHLD_CAN_TR
C
Mounting Holes
998-03823
SH0400
TH-NSP
1
SL-3.36X2.1-5.86X4.6
SH0401
TH-NSP
1
SL-3.36X2.1-5.86X4.6
Heatsink Mounting Bosses
860-01043
SH0410
5.0OD1.85ID-1.5H-SM1
1
SH0411
5.0OD1.85ID-1.5H-SM1
1
SH0412
5.0OD1.85ID-1.5H-SM1
1
SH0413
5.0OD1.85ID-1.5H-SM1
1
SOC/NAND Shield Fence
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
806-12385 SHLD4 SHLD_FNC_SOCCRITICAL1
SHIELD FENCE,GIBRALTOR AND MEMORY,X1030
Diplexer Shield Can
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
SHIELD CAN,DIPLEX,SUS,X1030
CRITICAL1 SHLD_CAN_DPLXRSHLD5806-12650
Bus Bars
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
806-16920 2 BUSBARLONGCRITICAL
BUSBAR,MLB,LONG,BOTTOM,X1032
BUSBAR,MLB,TOP,X1032
BUSBAR,MLB,LONG,BOTTOM,X1032
BB0400,BB0403
CRITICAL
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
C
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
BUSBARTOPBB04011806-16921 CRITICAL
TABLE_5_ITEM
BUSBARBOTTOMBB04021806-16922
B
998-11113 998-11114
SH0402
4.6R1.7-NSP 4.6X5.2R1.7X2.3-NSP
1
SH0403
1
Antenna Cowling Bosses
860-00974
SH0420
2.7X1.8R-1.4ID-0.91H-SM-X1030
1
SH0421
2.7X1.8R-1.4ID-0.91H-SM-X1030
1
B
A
8
A
PAGE TITLE
PD Parts
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=MECHANICALS
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
4 OF 145
SHEET
4 OF 85
1
SIZE
D
D
DDI Port Assignments:
USBC Sink 0
USBC Sink 1
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
678
3 245
1
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
947915
DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_ML_C_P<3>
DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<2> DP_X_SNK0_AUXCH_C_N
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_ML_C_P<3>
A46
C46
C48
A48
B45
D45
B47
D47
A42
C42
A44
C44
B41
D41
B43
D43
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
SYM 1 OF 20
DDI
DISPLAY
EDP
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
H45
F45
J44
G44
J46
G46
H43
F43
J42
G42
A40
H41
F41
J40
G40
DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>
DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P
TP_EDP_DISP_UTIL
DP_X_SNK0_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
DP_X_SNK1_AUXCH_C_P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
69
69
69
69
69
69
69
69
69
69
27
27
27
27
eDP Port Assignment:
D
Internal panel
C
PPVCCIO_S0_CPU
8 11 76
PLACE_NEAR=U0500.A50:15.24mm
R0520
24.9
1%
1/20W
MF
201
DISPLAY SIDEBANDS
TP_PCH_GPP_E18
20
OUT
1
20
OUT
PCH_DDPB_CTRLDATA
TP_PCH_GPP_E20
PCH_DDPC_CTRLDATA
TP_PCH_GPP_E22
2
TP_PCH_GPP_E23
MCP_EDP_RCOMP
L6
GPP_E18/DDPB_CTRLCLK
H6
GPP_E19/DDPB_CTRLDATA
H4
GPP_E20/DDPC_CTRLCLK
F4
GPP_E21/DDPC_CTRLDATA
M5
GPP_E22
L4
GPP_E23
A50
EDP_RCOMP
(IPD-PLTRST#)
(IPD-PLTRST#)
(IPD-PLTRST#)
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLEN
EDP_BKLCTL
EDP_VDDEN
C11
L10
M7
F6
A7
D4
B6
D3
DP_X_SNK0_HPD
DP_X_SNK1_HPD
TP_PCH_GPP_E15
TBT_X_PLUG_EVENT_L
DP_INT_HPD
EDP_BKLT_EN
EDP_BKLT_PWM
EDP_PANEL_PWR_EN
OUT
OUT
OUT
IN
IN
IN
IN
27
27
27 25 5
69 5
79 68 5
79 69
69 5
C
B
B
A
PM_SLP_S3_L
R0530
R0560
R0562
R0563
100K
100K
100K
100K
8
21
21
21
21
1/20W
5% 2011/20W MF
5% MF
1/20W 201
79 25 20 15 14
PAGE TITLE
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
A
CPU GFX
DRAWING NUMBER
051-04039
Apple Inc.
TBT_X_PLUG_EVENT_L
2015% MF
EDP_BKLT_EN
EDP_PANEL_PWR_EN
DP_INT_HPD
MF5%
2011/20W
27 25 5
79 68 5
69 5
69 5
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
REVISION
2.0.0
BRANCH
PAGE
5 OF 145
SHEET
5 OF 85
1
SIZE
D
D
PP1V_S0SW
8 12 18 75
42
79 42 20 17 15
33 32
BI
OUT
678
PP1V_S3
8 12 15 59 75
R0610
1/20W
CPU_PROCHOT_L
IN
1K
5%
MF
201
1
2
1
R0614
100K
5%
1/20W
MF
201
2
R0611
499
2 1
1%
1/20W
MF
201
R0612
65 42
1K
5%
1/20W
MF
201
OUT
3 245
1
CRITICAL
OMIT_TABLE
U0500
1
65
2
42
OUT
BI
CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
42
PM_THRMTRIP_L
NC
18
18
18
18
18
18
BI
BI
BI
BI
OUT
BI
(IFDIM trigger)
XDP_BPM_L<0>PLT_RST_L
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_PCH_OBSFN_C1
XDP_PCH_OBSDATA_A3
PCH_WLAN_PERST_L
33 32
OUT
PCH_WLAN_DEV_WAKE
IPD in module
CPU_OPI_RCOMP
PCH_OPI_COMP
H49
F49
J48
H47
B62
H51
J50
F51
G50
E11
M9
BD8
BC11
BN17
BP16
CATERR*
PECI
PROCHOT*
THERMTRIP*
SKTOCC*
BPM0*
BPM1*
BPM2*
BPM3*
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
KBL-PCH-Y-QKKR
BGA
947915
SYM 4 OF 20
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
JTAG
(IPU)
CPU MISC
(IPD)
(IPD)
(IPU)
(IPU)
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST*
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST*
JTAGX
D53
C54
G48
C59
F47
B53
C50
B51
A52
C52
B49
XDP_CPUPCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L
TP_XDP_PCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TCK
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
BI
18
18
18
18
18
18
18
18
18
18
18
D
C
B
A
R0620
49.9
PLACE_NEAR=U0500.BN17:2.54mm
PLACE_NEAR=U0500.BP16:2.54mm
1
1%
1/20W
MF
201
2
18
BI
R0634
1K
5%
1/20W
MF
201
R0680
49.9
1%
1/20W
MF
201
1
2
1
2
R0621
49.9
1%
1/20W
MF
201
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1
2
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<18>
CPU_CFG<19>
CPU_CFG_RCOMP
ITP_PMODE
TP_MCP_RSVD_D49
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G52
F53
J52
H53
H55
D55
C56
F55
D61
G58
D57
F61
J60
J58
H61
H59
J54
G54
G56
J56
A54
A60
B4
B3
F3
F1
L36
L38
BA19
BB18
BC19
BD18
D49
M21
L20
M19
L26
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
(IPU)
BL64
BG47
BA17
AY18
BF18
BE19
BA23
AY22
R12
P13
M15
L16
L18
M17
AH7
K12
H12
BN3
BP3
L22
M23
BN1
AY20
BA21
BB14
M25
L24
L28
M27
BJ15
BJ17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TP_MCP_RSVD_BL64
TP_MCP_RSVD_BG47
TP_MCP_RSVD_BA17
TP_MCP_RSVD_AY18
TP_MCP_RSVD_BF18
TP_MCP_RSVD_BE19
TP_MCP_RSVD_BA23
TP_MCP_RSVD_AY22
TP_MCP_RSVD_BN1
TP_MCP_RSVD_M25
TP_MCP_RSVD_L24
TP_MCP_RSVD_L28
TP_MCP_RSVD_M27
TP_MCP_RSVD_BJ15
TP_MCP_RSVD_BJ17
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
CPU Misc/JTAG/CFG/RSVD
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
BRANCH
PAGE
6 OF 145
SHEET
6 OF 85
C
B
A
SIZE
D
8
67
35 4
2
.
1
678
3 245
1
D
C
B
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
AG61
AH60
AK62
AK60
AH62
AG63
AL61
AL63
AM60
AM62
AT60
AR61
AN61
AN63
AR63
AT62
AT56
AR55
AN57
AN55
AR57
AT58
AM58
AM56
AL55
AL57
AH58
AH56
AK58
AK56
AG55
AG57
BE55
BC55
BG53
BE53
BC53
BG55
BD52
BF52
BC51
BE51
BC49
BE49
BG51
BG49
BF48
BD48
BJ55
BL55
BJ53
BL53
BN55
BN53
BM52
BK52
BL51
BJ51
BL49
BJ49
BN49
BN51
BK48
BM48
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR1_DQ0/DDR0_DQ16
DDR1_DQ1/DDR0_DQ17
DDR1_DQ2/DDR0_DQ18
DDR1_DQ3/DDR0_DQ19
DDR1_DQ4/DDR0_DQ20
DDR1_DQ5/DDR0_DQ21
DDR1_DQ6/DDR0_DQ22
DDR1_DQ7/DDR0_DQ23
DDR1_DQ8/DDR0_DQ24
DDR1_DQ9/DDR0_DQ25
DDR1_DQ10/DDR0_DQ26
DDR1_DQ11/DDR0_DQ27
DDR1_DQ12/DDR0_DQ28
DDR1_DQ13/DDR0_DQ29
DDR1_DQ14/DDR0_DQ30
DDR1_DQ15/DDR0_DQ31
DDR0_DQ16/DDR0_DQ32
DDR0_DQ17/DDR0_DQ33
DDR0_DQ18/DDR0_DQ34
DDR0_DQ19/DDR0_DQ35
DDR0_DQ20/DDR0_DQ36
DDR0_DQ21/DDR0_DQ37
DDR0_DQ22/DDR0_DQ38
DDR0_DQ23/DDR0_DQ39
DDR0_DQ24/DDR0_DQ40
DDR0_DQ25/DDR0_DQ41
DDR0_DQ26/DDR0_DQ42
DDR0_DQ27/DDR0_DQ43
DDR0_DQ28/DDR0_DQ44
DDR0_DQ29/DDR0_DQ45
DDR0_DQ30/DDR0_DQ46
DDR0_DQ31/DDR0_DQ47
DDR1_DQ16/DDR0_DQ48
DDR1_DQ17/DDR0_DQ49
DDR1_DQ18/DDR0_DQ50
DDR1_DQ19/DDR0_DQ51
DDR1_DQ20/DDR0_DQ52
DDR1_DQ21/DDR0_DQ53
DDR1_DQ22/DDR0_DQ54
DDR1_DQ23/DDR0_DQ55
DDR1_DQ24/DDR0_DQ56
DDR1_DQ25/DDR0_DQ57
DDR1_DQ26/DDR0_DQ58
DDR1_DQ27/DDR0_DQ59
DDR1_DQ28/DDR0_DQ60
DDR1_DQ29/DDR0_DQ61
DDR1_DQ30/DDR0_DQ62
DDR1_DQ31/DDR0_DQ63
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 2 OF 20
DDR CH - A
DDR0_CKN0
DDR0_CKP0
DDR0_CKN1
DDR0_CKP1
DDR0_CKE0
DDR0_CKE1
DDR0_CKE2
DDR0_CKE3
DDR0_CS0*
DDR0_CS1*
DDR0_ODT0
DDR0_CAA0
DDR0_CAA1
DDR0_CAA2
DDR0_CAA3
DDR0_CAA4
DDR0_CAA5
DDR0_CAA6
DDR0_CAA7
DDR0_CAA8
DDR0_CAA9
DDR0_CAB0
DDR0_CAB1
DDR0_CAB2
DDR0_CAB3
DDR0_CAB4
DDR0_CAB5
DDR0_CAB6
DDR0_CAB7
DDR0_CAB8
DDR0_CAB9
DDR0_MA3
DDR0_MA4
DDR0_DQSN0
DDR0_DQSP0
DDR0_DQSN1
DDR0_DQSP1
DDR1_DQSN0/DDR0_DQSN2
DDR1_DQSP0/DDR0_DQSP2
DDR1_DQSN1/DDR0_DQSN3
DDR1_DQSP1/DDR0_DQSP3
DDR0_DQSN2/DDR0_DQSN4
DDR0_DQSP2/DDR0_DQSP4
DDR0_DQSN3/DDR0_DQSN5
DDR0_DQSP3/DDR0_DQSP5
DDR1_DQSN2/DDR0_DQSN6
DDR1_DQSP2/DDR0_DQSP6
DDR1_DQSN3/DDR0_DQSN7
DDR1_DQSP3/DDR0_DQSP7
DDR0_ALERT*
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
BC62
BC60
BA60
BA62
BB57
BC58
BE57
AW61
AW63
BJ57
BN61
AW59
AW55
BF62
AV56
AW57
AV58
BA56
BD59
BD61
BG61
BK59
BL62
BJ61
AV60
BN62
BB61
BL61
BM59
BN58
AV62
BB63
BL57
AJ61
AJ63
AP62
AP60
AP56
AP58
AJ57
AJ55
BD54
BF54
BF50
BD50
BM54
BK54
BK50
BM50
BG57
BM56
AR53
AN53
AW53
BN47
NC
NC
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>
MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
PM_MEMVTT_EN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
21
21
21
66
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
CRITICAL
OMIT_TABLE
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
24 22
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
BC41
BC39
BG41
BE39
BF42
BD42
BG39
BE41
BC43
BD46
BG43
BG45
BC45
BE43
BE45
BF46
BM28
BN27
BK28
BL25
BN25
BL27
BJ25
BJ27
BM24
BK24
BN21
BJ23
BL23
BN23
BJ21
BL21
BN45
BM46
BL43
BK46
BN43
BL45
BJ45
BJ43
BM42
BN41
BJ41
BN39
BK42
BL41
BL39
BJ39
BF28
BD28
BG25
BC27
BG27
BE27
BE25
BC25
BF24
BD24
BG21
BC23
BE23
BG23
BC21
BE21
DDR0_DQ32/DDR1_DQ0
DDR0_DQ33/DDR1_DQ1
DDR0_DQ34/DDR1_DQ2
DDR0_DQ35/DDR1_DQ3
DDR0_DQ36/DDR1_DQ4
DDR0_DQ37/DDR1_DQ5
DDR0_DQ38/DDR1_DQ6
DDR0_DQ39/DDR1_DQ7
DDR0_DQ40/DDR1_DQ8
DDR0_DQ41/DDR1_DQ9
DDR0_DQ42/DDR1_DQ10
DDR0_DQ43/DDR1_DQ11
DDR0_DQ44/DDR1_DQ12
DDR0_DQ45/DDR1_DQ13
DDR0_DQ46/DDR1_DQ14
DDR0_DQ47/DDR1_DQ15
DDR1_DQ32/DDR1_DQ16
DDR1_DQ33/DDR1_DQ17
DDR1_DQ34/DDR1_DQ18
DDR1_DQ35/DDR1_DQ19
DDR1_DQ36/DDR1_DQ20
DDR1_DQ37/DDR1_DQ21
DDR1_DQ38/DDR1_DQ22
DDR1_DQ39/DDR1_DQ23
DDR1_DQ40/DDR1_DQ24
DDR1_DQ41/DDR1_DQ25
DDR1_DQ42/DDR1_DQ26
DDR1_DQ43/DDR1_DQ27
DDR1_DQ44/DDR1_DQ28
DDR1_DQ45/DDR1_DQ29
DDR1_DQ46/DDR1_DQ30
DDR1_DQ47/DDR1_DQ31
DDR0_DQ48/DDR1_DQ32
DDR0_DQ49/DDR1_DQ33
DDR0_DQ50/DDR1_DQ34
DDR0_DQ51/DDR1_DQ35
DDR0_DQ52/DDR1_DQ36
DDR0_DQ53/DDR1_DQ37
DDR0_DQ54/DDR1_DQ38
DDR0_DQ55/DDR1_DQ39
DDR0_DQ56/DDR1_DQ40
DDR0_DQ57/DDR1_DQ41
DDR0_DQ58/DDR1_DQ42
DDR0_DQ59/DDR1_DQ43
DDR0_DQ60/DDR1_DQ44
DDR0_DQ61/DDR1_DQ45
DDR0_DQ62/DDR1_DQ46
DDR0_DQ63/DDR1_DQ47
DDR1_DQ48
DDR1_DQ49
DDR1_DQ50
DDR1_DQ51
DDR1_DQ52
DDR1_DQ53
DDR1_DQ54
DDR1_DQ55
DDR1_DQ56
DDR1_DQ57
DDR1_DQ58
DDR1_DQ59
DDR1_DQ60
DDR1_DQ61
DDR1_DQ62
DDR1_DQ63
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 3 OF 20
DDR CH - B
DDR1_CKN0
DDR1_CKP0
DDR1_CKN1
DDR1_CKP1
DDR1_CKE0
DDR1_CKE1
DDR1_CKE2
DDR1_CKE3
DDR1_CS0*
DDR1_CS1*
DDR1_ODT0
DDR1_CAA0
DDR1_CAA1
DDR1_CAA2
DDR1_CAA3
DDR1_CAA4
DDR1_CAA5
DDR1_CAA6
DDR1_CAA7
DDR1_CAA8
DDR1_CAA9
DDR1_CAB0
DDR1_CAB1
DDR1_CAB2
DDR1_CAB3
DDR1_CAB4
DDR1_CAB5
DDR1_CAB6
DDR1_CAB7
DDR1_CAB8
DDR1_CAB9
DDR1_MA3
DDR1_MA4
DDR0_DQSN4/DDR1_DQSN0
DDR0_DQSP4/DDR1_DQSP0
DDR0_DQSN5/DDR1_DQSN1
DDR0_DQSP5/DDR1_DQSP1
DDR1_DQSN4/DDR1_DQSN2
DDR1_DQSP4/DDR1_DQSP2
DDR1_DQSN5/DDR1_DQSN3
DDR1_DQSP5/DDR1_DQSP3
DDR0_DQSN6/DDR1_DQSN4
DDR0_DQSP6/DDR1_DQSP4
DDR0_DQSN7/DDR1_DQSN5
DDR0_DQSP7/DDR1_DQSP5
DDR1_DQSN6
DDR1_DQSP6
DDR1_DQSN7
DDR1_DQSP7
DDR1_ALERT*
DDR1_PAR
DRAM_RESET*
DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2
BK36
BM36
BD32
BF32
BN33
BK32
BG33
BH30
BM30
BJ33
BC35
BK30
BN31
BM32
BL37
BG31
BN37
BJ37
BJ35
BM34
BN35
BG37
BE37
BC37
BF34
BC33
BF30
BD36
BG35
BC31
BF36
BJ31
BK34
BD40
BF40
BD44
BF44
BK26
BM26
BM22
BK22
BK44
BM44
BM40
BK40
BD26
BF26
BF22
BD22
BD34
BD30
BP20
BF64
BJ64
BC64
NC
NC
NCNC
NC
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>
MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
R0752
162
1%
1/20W
MF
201
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
24 23
D
C
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
B
1%
1/20W
MF
201
1
2
R0750
1
R0751
80.6
2
200
1%
1/20W
MF
201
1
2
A
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
PLACE_NEAR=U0500.BC64:12.7mm
PLACE_NEAR=U0500.BJ64:12.7mm
PLACE_NEAR=U0500.BF64:12.7mm
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
CPU LPDDR3 Interface
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
BRANCH
PAGE
7 OF 145
SHEET
7 OF 85
A
SIZE
D
8
67
35 4
2
1
678
3 245
1
D
C
B
A
SKL-ULX current estimates from Skylake Processor EDS vol 1, doc #544924, v0.94
VCCIO breakdown per 4/20/15 email from Srini
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
PPVCCGT_S0_CPU
8 12 76
24A Max
AA53
AB62
AC47
AC55
AD54
AD64
AE61
AF47
AJ53
AK49
AN46
AT43
AT50
N50
T46
T54
U61
V60
W57
Y44
Y51
Y62
AB54
AB64
AC49
AC57
AD56
AE53
AE63
AF49
AK43
AK50
AN47
AT44
AT51
R51
T47
U53
U63
V62
W59
Y46
Y54
Y64
AB58
AC44
AC51
AC61
AD60
AE57
AF44
AF51
AK46
AB60
AC46
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
947915
SYM 14 OF 20
CPU POWER 2 OF 4
VCCGT_SENSE
VSSGT_SENSE
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
AC53
AC63
AD62
AE59
AF46
AG53
AK47
AN44
AN51
AT49
N48
T44
T51
U59
V58
W55
Y43
Y50
Y60
AB56
AC43
AC50
AC59
AD58
AE55
AF43
AF50
AK44
AK51
AN49
AT46
N44
R53
T49
U55
V54
V64
W61
Y47
Y56
AN50
AT47
N46
T43
T50
U57
V56
W53
W63
Y49
Y58
AN43
N52
P52
PPVCCGT_S0_CPU
PLACE_NEAR=U0500.N52:50.8mm
1
R0830
100
5%
1/20W
MF
201
2
CPU_VCCGTSENSE_P
CPU_VCCGTSENSE_N
PLACE_NEAR=U0500.P52:50.8mm
1
R0831
100
5%
1/20W
MF
201
2
8 12 76
OUT
OUT
PPVCCSA_S0_CPU
11 76
3.78A Max
PLACE_NEAR=U0500.N30:50.8mm
VCCSA & VCCSA_DDR must
be isolated from VR
output to BGA pads
PPVCCSA_S0_CPUDDR
11 76
320mA Max
59
59
OUT
OUT
CPU_VCCSASENSE_P
CPU_VCCSASENSE_N
PLACE_NEAR=U0500.R30:50.8mm
24A Max
PPVCC_S0_CPU
8 11 49 76
TP_MCP_DC_A64
TP_MCP_DC_B64
59
59
R0860
100
5%
1/20W
MF
201
R0861
100
5%
1/20W
MF
201
NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 16 OF 20
AA29
AF30
AN29
AC29
AH29
AN30
AC30
AK29
AR29
1
2
1
2
AE29
AK30
AF29
AL29
AT29
AT30
VCCSA
VCCSA
VCCSA
L30
VCCSA
T30
VCCSA
VCCSA
VCCSA
VCCSA
M31
VCCSA
V29
VCCSA
VCCSA
VCCSA
VCCSA
N30
VCCSA
Y29
VCCSA
VCCSA
VCCSA
R29
VCCSA
Y30
VCCSA
VCCSA
VCCSA
T29
VCCSA
VCCSA_DDR
VCCSA_DDR
M29
VCCSA_SENSE
N28
VSSSA_SENSE
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
CPU POWER 4 OF 4
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
AA35
R38
Y35
AA38
T35
Y38
AC35
T38
AC38
V35
R35
V38
AF35
AK38
AR35
AF38
AL35
AR38
AH35
AL38
AH38
AN35
AK35
AN38
CRITICAL
OMIT_TABLE
A64
AE32
AE40
AH41
AN32
AT33
AT41
J64
L48
M33
M43
M53
M64
N40
N59
P60
R57
T41
AA32
AE33
AE41
AK32
AN41
AT35
B64
L40
L50
M35
M45
M56
N32
N42
N61
P62
R59
V32
AA41
AE35
AF32
AK41
AR32
AT36
D64
L42
L52
M37
M47
R63
P56
R32
Y32
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 13 OF 20
CPU POWER 1 OF 4
VCC_SENSE
VSS_SENSE
VIDALERT*
VIDSCK
VIDSOUT
VCCSTG
VCCSTG
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M58
N34
N54
N63
P64
R61
V41
AC41
AE38
AH32
AL41
AT32
AT40
H63
L46
L63
M41
M51
M62
N38
N57
P58
R41
T32
Y41
AC32
AE36
AF41
AL32
AR41
AT38
F64
L44
L54
M39
M49
M60
N36
N55
L34
L32
B58
A56
A58
AA26
AC26
PPVCCG0_S0_CPU
MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.1500
VOLTAGE=1.5V
PPVCCG1_S0_CPU
MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.1500
VOLTAGE=1.5V
PPVCC_S0_CPU
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R
PP1V_S0SW
11
11
8 11 49 76
VDDQC must implement
1nH trace filter
BYPASS=U0500.BA39::0.59mm
C0850
0.1UF
X5R-CERM
PLACE_NEAR=U0500.L34:50.8mm
100
5%
1/20W
MF
201
100
5%
1/20W
MF
201
1
2
1
2
R0820
6 8 12 18
75
PLACE_NEAR=U0500.L32:50.8mm
R0821
10%
10V
0201
1
2
OUT
OUT
59
59
PP1V2_S3
12 76
2A Max
TP_MCP_DC_BN64
TP_MCP_DC_BP64
XW0850
SM
21
PP1V2_S0_CPU_VDDQC
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.2V
PP1V_S3
6 8 12 15
59 75
PP1V_S0SW
6 8 12 18 75
PP1V2_S0SW
12 76
PP1V_S3
12 75
R0800
56
1%
1/20W
MF
R0810
220
21
1%
1/20W
MF
201
R0812
0
21
5%
1/20W
MF
0201
201
R0811
0
5%
1/20W
MF
0201
R0800.2:
R0802.2:
R0811.1:
AH64
BA27
BA37
BA49
BP32
BP50
AK64
BA29
BA41
BA51
BP34
BP56
AT64
BA31
BA43
BN64
BP40
BP58
AV64
BA33
BA45
BP24
BP42
BP64
BA25
BA35
BA47
BP26
BP48
BA39
V26
Y26
R26
T26
AE27
AF27
R27
T27
PP1V_S3
1
2
1
R0802
100
1%
1/20W
MF
201
2
CPU_VIDALERT_L
21
CPU_VIDSCLK
CPU_VIDSOUT
PLACE_NEAR=U0500.B58:12.7mm
PLACE_NEAR=U0500.A58:12.7mm
PLACE_NEAR=U0500.A56:12.7mm
BOM_COST_GROUP=CPU & CHIPSET
KBL-PCH-Y-QKKR
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCST
VCCST
VCCSTG
VCCSTG
VCCPLL_OC
VCCPLL_OC
VCCPLL
VCCPLL
IN
OUT
BI
CRITICAL
OMIT_TABLE
U0500
BGA
947915
SYM 15 OF 20
CPU POWER 3 OF 4
VCCIO_SENSE
VSSIO_SENSE
6 8 12 15 59 75
59
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
59
59
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
PPVCCIO_S0_CPU
AC23
AF24
AN26
AC24
AF26
AR26
AE23
AH26
AT26
AE24
AK26
AE26
AL26
AV26
AV36
AV46
AW31
AW41
AW51
AV28
AV38
AV48
AW33
AW43
AV30
AV40
AV50
AW35
AW45
AV32
AV42
AW27
AW37
AW47
AV34
AV44
AW29
AW39
AW49
AT24
AR24
VCCIO & VCCIO_DDR must
be isolated from local
plane to BGA pads
PPVCCIO_S0_CPU
PLACE_NEAR=U0500.AT26:50.8mm
1
R0840
100
5%
1/20W
MF
201
2
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
PLACE_NEAR=U0500.AN24:50.8mm
1
R0841
100
5%
1/20W
MF
201
2
CPU Power
Apple Inc.
1.185A Max
1.75A Max
5 11 76
76
OUT
OUT
DRAWING NUMBER
051-04039
REVISION
2.0.0
BRANCH
PAGE
8 OF 145
SHEET
8 OF 85
D
C
B
66
66
A
SIZE
D
8
67
35 4
2
1
D
C
VCCAMPHYPLL_1P0 and VCCPRIM_1P0 / VCCPRIM_3P3 breakdowns from Srini email 4/13/15
BYPASS=U0500.AL2::5.32mm
20%
6.3V
X5R
1
2
C0920
1.0UF
0201-1
678
PP1V_PRIM
75
370mA Max
PPVCC_PRIM_CORE
75
1.1A Max
PP1V_S5_PCH_DCPDSW
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.0V
PP1V_PRIM
13 75
22mA Max
PP1V_PRIM
13 75
See EDS Table 10-5
PP1V_SUSSW_PCH_VCCAMPHYPLL
13
88mA Max
PP1V_SUS_PCH_VCCAPLL
13
26mA Max
PP1V_PRIM
13 75
168mA Max
PP3V3_S5
13 75
71mA Max
PP3V3R1V8R1V5_S0_PCH_VCCHDA
13
68/36/33mA @ 3.3/1.8/1.5V Max
PP1V8_S5
13 75
11/7mA @ 3.3/1.8V Max
PP1V_PRIM
75
0.565A Max
AH18
AH19
AK18
AL18
AE18
AE19
AF18
AF19
AR16
AT16
AL2
AM1
V1
W2
T1
T15
T16
U2
V15
V16
AA18
AA19
AH13
AH15
AL15
AM13
AT23
AV22
AT15
AV15
AA21
AA23
AK23
AL23
AN23
AR23
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCDSW_3P3
VCCDSW_3P3
VCCHDA
VCCHDA
VCCSPI
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 17 OF 20
PCH POWER
VCCPGPPA
VCCPGPPA
VCCPGPPB
VCCPGPPB
VCCPGPPC
VCCPGPPC
VCCPGPPD
VCCPGPPD
VCCPGPPE
VCCPGPPE
VCCPGPPF
VCCPGPPF
VCCPGPPG
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_1P0
VCCPRIM_1P0
VCCATS
VCCATS
VCCRTCPRIM_3P3
VCCRTCPRIM_3P3
VCCRTC
VCCRTC
DCPRTC
DCPRTC
VCCCLK1
VCCCLK1
VCCCLK2
VCCCLK2
VCCCLK3
VCCCLK3
VCCCLK4
VCCCLK4
VCCCLK5
VCCCLK5
AT1
AU2
AV1
AW2
AH1
AJ2
AF1
AG2
AA2
AB1
AN2
AP1
AN15
AP13
AC2
AD1
AA15
AA16
AE15
AE16
AK19
AL19
AR19
AT19
AT18
AV18
V18
Y18
V19
Y19
V23
Y23
V21
Y21
R21
R23
PP1V8_S5
20/9mA @ 3.3/1.8V Max
PP1V8_S5
4/2mA @ 3.3/1.8V Max
PP1V8_S5
6/3mA @ 3.3/1.8V Max
PP1V8_S5
8/3mA @ 3.3/1.8V Max
PP3V3_S5
6/2mA @ 3.3/1.8V Max
PP1V8_S5
33/161mA @ 3.3/1.8V Max
PP3V3_S5
41/56mA @ 3.3/1.8V Max
PP3V3_S5
PP1V_PRIM
PP1V8_S5
PP3V3_S5
PPVOUT_S0_PCH_DCPRTC
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.0V
PP1V_PRIM
PP1V_PRIM
PP1V_SUS_PCH_VCCCLK3
PP1V_SUS_PCH_VCCCLK4
PP1V_SUS_PCH_VCCCLK5
3 245
1mA Max
6mA Max
6mA Max
<1mA Max
<1mA Max
35mA Max
29mA Max
24mA Max
33mA Max
4mA Max
75
17 75
14 17 75
75
13 75
17 75
14 75
75
75
13 75
13 75
75
75
13
13
13
Must not exceed
PP3V_G3H
1
C0901
1.0UF
20%
6.3V
2
X5R
0201-1
BYPASS=U0500.AR19::2.10mm
BYPASS=U0500.AT19::2.10mm
10%
10V
0201
1
2
C0900
0.1UF
X5R-CERM
1
C0910
0.1UF
10%
10V
2
X5R-CERM
0201
BYPASS=U0500.AT18::1.08mm
1
NOTE: Aliases not used on CPU supply outputsSPT-LP current estimates from Sunrise Point-LP PCH EDS vol 1, doc #545659, v1.2.
to avoid any extraneous connections.
D
3.2V max
15 75
C
B
PP3V3_S5
75
74mA Max
PP1V_PRIM
75
55mA Max
PP1V_PRIM
13 75
33mA Max
AH21
AK21
AR21
AT21
R15
R16
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_1P0
VCCPRIM_1P0
VCCAPLLEBB_1P0
VCCAPLLEBB_1P0
VCCCLK6
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
R19
T19
BA13
BB12
PP1V_PRIM
TP_PCH_CORE_VID<0>
TP_PCH_CORE_VID<1>
75
10mA Max
B
A
8
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
PAGE TITLE
A
PCH Power
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
9 OF 145
SHEET
9 OF 85
1
SIZE
D
678
3 245
1
D
C
B
A14
AA36
AA47
AA57
AC15
AC27
AE10
AE43
AE50
AF16
AF40
AF62
AH24
AH40
AH49
AK1
AK24
AK40
AL16
AL33
AL46
AL53
AN18
AN33
AP64
AR2
AR4
AR47
AR6
AU55
AV16
AW17
AY16
AY32
AY42
AY52
BA5
BA9
BB28
BB38
BB48
BC17
BD56
BE33
BF56
BG2
BG8
BH28
BH40
BH50
BJ29
BK56
BL35
BM16
BP36
BP54
D10
E14
E24
E34
E44
E54
J14
J9
AH47
AJ59
AK16
AK36
AK9
V24
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
K23
K33
K43
K53
L61
N20
R10
R24
R40
R49
T13
T33
T60
V27
V43
V50
Y15
Y33
Y9
AA24
AA40
AA49
AA59
AC16
AC33
AE2
AE44
AE51
AF21
AF54
AF64
AH27
AH43
AH50
AK11
AK27
AK5
AL21
AL36
AL47
AL59
AN19
AN36
AR10
AR27
AR40
AR49
AR8
AU57
AV20
AW19
AY24
AY34
AY44
BA53
BB20
BB30
BB40
BB50
BC29
BD63
BE35
BF59
BG29
AL30
AL44
AL51
AN16
AN27
BA7
BH20
BH32
BH42
BH52
BJ47
BL1
BL47
BM18
BN6
BP38
BP60
E16
E26
E36
R43
E46
E56
J3
K15
K25
K35
K45
K55
M3
N22
R30
R50
T18
T36
T62
V30
V44
V51
Y16
Y36
Y7
AA27
AA43
AA50
AA61
AC18
AC36
AE21
AE46
AE8
AF23
AF56
AG59
AH30
AH44
AH51
AK13
AK3
AK54
AL24
AL40
AL49
AM54
AN21
AN40
AR12
AR30
AR43
AP54
AR18
AR36
AR46
AR59
BA3
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 19 OF 20
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR50
AT27
AU59
AV24
AY26
AW21
AY36
AY46
BA1
BB22
BA58
BB32
BB42
BB52
BE12
BC47
BE47
BG12
BG4
BH34
BH22
BH44
BH54
BJ62
BL29
BM20
BL8
BP22
BP44
E18
E28
D6
E38
E48
E59
K17
J5
K27
K37
K47
N14
L14
N24
R33
R44
T21
R55
T40
T64
V33
Y1
V46
Y24
Y40
AA30
AA51
AA44
AA63
AC19
AC40
AE47
AE30
AF13
AU53
AU63
AV54
AW25
AY30
AY50
AF33
AF58
AH16
AH33
AH46
AH54
AK15
AK33
AK7
AL27
AL43
AL50
AM64
AN24
AN59
AR15
AR33
AR44
AR51
AT54
AU61
AV52
AW23
AY28
AY38
AY48
BA11
BA64
BB24
BB34
BB44
BB54
BD20
BE29
BF20
BG15
BG6
BH24
BH36
BH46
BH56
BK20
BL31
BM11
BM38
BP28
BP46
C14
D62
E20
E30
E40
E50
F62
J62
K19
K29
K39
K49
L57
N16
N26
R18
R36
AY40
V49
Y13
AH36
V40
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 20 OF 20
GND 3 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R46
R6
T23
T56
V13
V36
V47
Y11
Y27
Y5
BB26
BB36
BB46
BB59
BD38
BE31
BF38
BG17
BG63
BH26
BH38
BH48
BH59
BK38
BL33
BM14
BN29
BP30
BP52
C40
D8
E22
E32
E42
E52
G14
J7
K21
K31
K41
K51
L59
N18
P54
R2
R4
R47
R8
T24
T58
Y3
AA33
AA46
AA55
AB13
AC21
AD13
AE4
AE49
AF15
AF36
AF60
AH23
BP1
A5
D1
BP62
D
C
B
TP_MCP_DC_BP1
TP_MCP_DC_A5
TP_MCP_DC_D1
TP_MCP_DC_BP62
A
8
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
A
CPU & PCH Grounds
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
10 OF 145
SHEET
10 OF 85
1
SIZE
D
678
All Intel recommendations from Intel doc #561280 KBL-UY PDG and #594883 KBL-YR PDG addendum
CPU VCORE Decoupling
Intel implementation (#561280, Table 49-2): 20x 0.1uF 0201, 8x 10uF 0402, 6x 47uF 0805
PPVCC_S0_CPU
8 49 76
Intel implementation (#594883, AML): 20x 0.1uF 0201, 10x 1uF 0201, 9x 10uF 0402, 6x 100uF 0805
Apple implementation: 9x 0.1uF 0201, 21x 1uF 0201, 12x 20uF 0402 STUFF (6x NOSTUFF), 2x 220uF D1 STUFF (1x NOSTUFF)
3 245
1
D
CRITICAL
1
C1100
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1116
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1120
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1101
0.1UF
10%
6.3V
2
X6S
0201
1
C1117
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1121
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1102
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1118
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1122
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1103
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1119
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1123
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1104
1UF
20%
6.3V
2
X6S-CERM
0201
1
C111A
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1124
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1105
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
CRITICAL
1
C111B
1UF 1UF
20%
6.3V
2
X6S-CERM
0201
1
2
CRITICAL
1
C1125
20UF
20%
2.5V
2
X6S-CERM
0402
1
2
CRITICAL
C1106
1UF
20%
6.3V
X6S-CERM
0201
CRITICAL
C111C
20%
6.3V
X6S-CERM
0201
CRITICAL
C1126
20UF
20%
2.5V
X6S-CERM
0402
CRITICAL
1
C1107
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C111D
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1127
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1108
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1128
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1109
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1129
20UF
20%
2.5V
2
X6S-CERM
0402
1
C110A
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C112A
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C110B
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C112B
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C110C
1UF
20%
6.3V
2
X6S-CERM
0201
1
C110D
0.1UF
10%
6.3V
2
X6S
0201
NO STUFF NO STUFF
CRITICAL
1
C112C
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C112D
20UF
20%
2.5V
2
X6S-CERM
0402
1
C110E
0.1UF
10%
6.3V
2
X6S
0201
NO STUFF
CRITICAL
1
C112E
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C110F
1UF
20%
6.3V
2
X6S-CERM
0201
NO STUFF
CRITICAL
1
C112F
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1110
1UF
20%
6.3V
2
X6S-CERM
0201
NO STUFF
CRITICAL
1
C112G
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1111
1UF
20%
6.3V
2
X6S-CERM
0201
NO STUFF
CRITICAL
1
C112H
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1112
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1130
220UF
20%
2V
2
ELEC
SM
CRITICAL
1
C1113
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1131
220UF
20%
2V
2
ELEC
SM
CRITICAL
1
C1114
1UF
20%
6.3V
2
X6S-CERM
0201
NO STUFF
CRITICAL
1
C1134
220UF
20%
2V
2
ELEC
SM
1
C1115
0.1UF
10%
6.3V
2
X6S
0201
D
C
PPVCCG0_S0_CPU
8
PPVCCG1_S0_CPU
8
CPU VCORE G0 Decoupling
Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201
Intel implementation (#594883, AML): 10x 0.1uF 0201, 2x 1uF 0201
Apple implementation : 10x 0.1uF 0201, 2x 1uF 0201
1
C1140
0.1UF
10%
6.3V
2
X6S
0201
1
C1141
0.1UF
10%
6.3V
2
X6S
0201
1
C1142
0.1UF
10%
6.3V
2
X6S
0201
1
C1143
0.1UF
10%
6.3V
2
X6S
0201
1
C1146
0.1UF
10%
6.3V
2
X6S
0201
1
C1147
0.1UF
10%
6.3V
2
X6S
0201
CPU VCORE G1 Decoupling
Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201
Intel implementation (#594883, AML): 10x 0.1uF 0201, 2x 1uF 0201
Apple implementation : 10x 0.1uF 0201, 2x 1uF 0201
1
C1150
0.1UF
10%
6.3V
2
X6S
0201
1
C1151
0.1UF
10%
6.3V
2
X6S
0201
1
C1152
0.1UF
10%
6.3V
2
X6S
0201
1
C1153
0.1UF
10%
6.3V
2
X6S
0201
1
C1154
0.1UF
10%
6.3V
2
X6S
0201
1
C1157
0.1UF
10%
6.3V
2
X6S
0201
1
C1148
0.1UF
10%
6.3V
2
X6S
0201
1
C1158
0.1UF
10%
6.3V
2
X6S
0201
1
C1149
0.1UF
10%
6.3V
2
X6S
0201
1
C1159
0.1UF
10%
6.3V
2
X6S
0201
1
C114A
0.1UF
10%
6.3V
2
X6S
0201
1
C115A
0.1UF
10%
6.3V
2
X6S
0201
1
C114B
0.1UF
10%
6.3V
2
X6S
0201
1
C115B
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1144
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1155
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1145
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1156
1UF
20%
6.3V
2
X6S-CERM
0201
C
B
PPVCCIO_S0_CPU
5 8 76
CPU VCCIO Decoupling
Intel implementation (#561280, Table 49-2): 13x 0.1uF 0201, 1x 1uF 0402
Apple implementation : 13x 0.1uF 0201, 1x 1uF 0402, 7x 20uF 0402 (2x 20uF on VR page), 1x 220uF D1
1
C1160
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1177
1.0UF
20%
6.3V
2
X5R
0201-1
1
C1161
0.1UF
10%
6.3V
2
X6S
0201
1
C1162
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1178
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1163
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1179
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1164
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117A
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1165
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117B
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1166
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117C
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1167
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117D
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1168
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117E
20UF
20%
2.5V
2
X6S-CERM
0402-1
1
C1169
0.1UF
10%
6.3V
2
X6S
0201
1
C116A
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C117G
220UF
20%
2V
2
ELEC
SM
1
C116B
0.1UF
10%
6.3V
2
X6S
0201
1
C116C
0.1UF
10%
6.3V
2
X6S
0201
B
A
PPVCCSA_S0_CPU
8 76
PPVCCSA_S0_CPUDDR
8 76
CPU VCCSA Decoupling
Intel implementation (#561280, Table 49-2): 1x 1uF 0201, 4x 22uF 0603
Apple implementation : 6x 1uF 0201, 2x 2.2uF 0402, 3x 10uF 0402, 1x 120uF D1
CRITICAL
1
C1180
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1181
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1182
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL CRITICAL
1
C1183
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1184
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C118A
1UF
20%
6.3V
2
X6S-CERM
0201
CPU VCCSA DDR Decoupling
Intel implementation (#561280, Table 49-2): 1x 0.1uF 0201, 1x 22uF 0603
Apple implementation : 1x 1uF 0201, 1x 10uF 0402
CRITICAL
1
C1195
1UF
20%
6.3V
2
X6S-CERM
0201
CRITICAL
1
C1197
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C118B
2.2UF
20%
25V
2
X6S-CERM
0402
1
C118C
2.2UF
20%
25V
2
X6S-CERM
0402
CRITICAL
1
C118D
10UF
20%
6.3V
2
CER-X6S
0402
CRITICALCRITICAL
1
C118E
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C118F
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C1190
120UF
20%
2.5V
2
TANT-POLY
CASE-B2-SM
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
CPU Decoupling 1
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
BRANCH
PAGE
11 OF 145
SHEET
11 OF 85
A
SIZE
D
2.0.0
8
67
35 4
2
1
678
All Intel recommendations from Intel doc #561280 KBL-UY PDG and #594883 KBL-YR PDG addendum
CPU GT Decoupling
Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201, 2x 1uF 0402, 9x 47uF 0805
PPVCCGT_S0_CPU
8 76
Apple implementation: 24x 0.1uF 0201, 2x 1uF 0201, 10x 20uF 0402 STUFF (6x NOSTUFF), 2x 220uF D1 STUFF
3 245
1
D
1
C1200
0.1UF
10%
6.3V
2
X6S
0201
1
C1213
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1254
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1201
0.1UF
10%
6.3V
2
X6S
0201
1
C1214
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1255
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1202
0.1UF
10%
6.3V
2
X6S
0201
1
C1215
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1256
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1203
0.1UF
10%
2
X6S
0201
1
C1216
0.1UF
10%
6.3V
2
X6S
0201
1
C1257
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1204
0.1UF
10%
6.3V6.3V
2
X6S
0201
1
C1217
0.1UF
10%
6.3V
2
X6S
0201
CRITICALCRITICAL
1
C1258
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1205
0.1UF
6.3V
2
X6S
0201
1
C1218
0.1UF
10% 10%
6.3V
2
X6S
0201
CRITICAL
1
C1259
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1206
0.1UF
10%10%
6.3V
2
X6S
0201
1
C1219
1
2
1
0.1UF
6.3V 6.3V
2
X6S
0201
2
CRITICAL
1
C125A
20UF
20%
2.5V
2
X6S-CERM
0402
1
2
CRITICAL
C1207
1UF
20%
6.3V
X6S-CERM
0201
C1220
0.1UF
10%
X6S
0201
CRITICAL
C125B
20UF
20%
2.5V
X6S-CERM
0402
1
C1208
0.1UF
10%
6.3V
2
X6S
0201
1
C1221
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C125C
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1209
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1222
0.1UF
10%
6.3V 6.3V
2
X6S
0201
1
2
1
2
CRITICAL
1
C125D
20UF
20%
2.5V
2
X6S-CERM
0402
1
2
C1210
0.1UF
10%
6.3V
X6S
0201
C1223
0.1UF
10%
X6S
0201
CRITICAL
C125E
20UF
20%
2.5V
X6S-CERM
0402
1
C1211
0.1UF
10%
2
X6S
0201
1
C1224
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C125F
20UF
20%
2.5V
2
X6S-CERM
0402
1
C1212
0.1UF
10%
6.3V6.3V
2
X6S
0201
1
C1225
0.1UF
10%
6.3V
2
X6S
0201
NO STUFF
CRITICAL
1
C125G
20UF
20%
2.5V
2
X6S-CERM
0402
D
C
PP1V2_S3
8 76
NO STUFF
CRITICAL
1
C125H
20UF
20%
2.5V
2
X6S-CERM
0402
CPU VDDQ DECOUPLING
NO STUFF
CRITICAL
1
C125I
20UF
20%
2.5V
2
X6S-CERM
0402
NO STUFF
CRITICAL
1
C125J
20UF
20%
2.5V
2
X6S-CERM
0402
CRITICAL
1
C1264
220UF
20%
2V
2
ELEC
SM
Intel implementation (#561280, Table 49-2): 18x 0.1uF 0201
Apple implementation: 18x 0.1uF 0201
1
C1270
0.1UF
10%
6.3V
2
X6S
0201
1
C1271
0.1UF
10%
6.3V
2
X6S
0201
1
C1272
0.1UF
10%
6.3V
2
X6S
0201
1
C1273
0.1UF
10%
6.3V
2
X6S
0201
1
C1274
0.1UF
10%
6.3V
2
X6S
0201
CRITICAL
1
C1265
220UF
20%
2V
2
ELEC
SM
1
C1275
0.1UF
10%
6.3V
2
X6S
0201
1
C1276
0.1UF
10%
6.3V
2
X6S
0201
1
C1277
0.1UF
10%
6.3V
2
X6S
0201
1
C1278
0.1UF
10%
6.3V
2
X6S
0201
1
C1279
0.1UF
10%
6.3V
2
X6S
0201
CPU VCCST BYPASS
(CPU 1.0V SUSTAIN PWR)
PP1V_S3
6 8 15 59 75
C
B
1
C1280
0.1UF
10%
6.3V
2
X6S
0201
1
C1281
0.1UF
10%
6.3V
2
X6S
0201
1
C1282
0.1UF
10%
6.3V
2
X6S
0201
1
C1283
0.1UF
10%
6.3V
2
X6S
0201
1
C1284
0.1UF
10%
6.3V
2
X6S
0201
1
C1285
0.1UF
10%
6.3V
2
X6S
0201
1
C1286
0.1UF
10%
6.3V
2
X6S
0201
1
C1287
0.1UF
10%
6.3V
2
X6S
0201
C1290
0.1UF
10%
6.3V
X6S
0201
BYPASS=U0500.V26::2.38mm
CPU VCCSTG BYPASS
(CPU 1.0V SUSTAIN GATED PWR)
PP1V_S0SW
6 8 18 75
C1292
0.1UF
10%
6.3V
X6S
0201
BYPASS=U0500.R26::4.20mm
CPU VCCPLL_OC BYPASS
(CPU 1.2V PLL PWR)
PP1V2_S0SW
8 76
1
2
1
2
B
A
PAGE TITLE
C1294
0.1UF
6.3V
0201
BYPASS=U0500.AE27::2.07mm
CPU VCCPLL BYPASS
(CPU 1.0V DIGITAL PLL PWR)
PP1V_S3
8 75
C1296
0.1UF
6.3V
0201
BYPASS=U0500.R27::1.99mm
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
10%
X6S
10%
X6S
1
2
1
2
A
Bypass calcs based on 0.1mm trace width NOTE:
with worst case stackup and 500pH added
for power/ground via pair.
8
CPU Decoupling 2
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
12 OF 145
SHEET
12 OF 85
1
SIZE
D
D
(PCH 3.3V DSW PWR)
PP3V3_S5
9 75
10%
6.3V
X6S
0201
1
2
C1300
0.1UF
BYPASS=U0500.AL15::1.96mm
PCH VCCPRIM_1P0 BYPASSPCH VCCDSW_3P3 BYPASS
(PCH 1.0V USB PWR)
PP1V_PRIM
9 75
BYPASS=U0500.AH13::1.39mm
678
3 245
1
PCH VCCAMPHYPLL_1P0 FILTER/BYPASS
(PCH 1.0V USB3/PCIE/SATA/MIPI PLL PWR)
C1336
0.1UF
10%
6.3V
X6S
0201
PP1V_PRIM
75
1
2
R1370
0
21
5%
1/16W
MF-LF
402
NOSTUFF
C1370
20UF
20%
6.3V
CERM-X5R
0402
BYPASS=U0500.V15::12.82mm
BYPASS=U0500.V15::12.82mm
BYPASS=U0500.V15::3.91mm
NOSTUFF
1
2
C1371
20UF
6.3V
CERM-X5R
0402
1
20%
2
PP1V_SUSSW_PCH_VCCAMPHYPLL
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V
NOSTUFF
1
C1372
0.1UF
10%
6.3V
2
X6S
0201
9
D
C
(PCH 3.3V/1.8V SPI PWR)
PP1V8_S5
9 75
BYPASS=U0500.AT15::2.38mm
PCH VCCRTCPRIM BYPASS
(PCH 3.3V SUSPEND RTC PWR)
PP3V3_S5
9 75
BYPASS=U0500.AK19::1.68mm
C1302
0.1UF
10%
6.3V
X6S
0201
C1306
1.0UF
20%
6.3V
X5R
0201-1
PCH VCCCLK3 FILTER/BYPASS
(PCH 1.0V CLOCK 3 PWR)
PCH VCCMPHYAON_1P0 BYPASSPCH VCCSPI BYPASS
PP1V_PRIM
75
(PCH 1.0V MPHY ALWAYS ON PWR)
PP1V_PRIM
9 75
10%
6.3V
X6S
0201
1
2
1
C1340
0.1UF
2
BYPASS=U0500.V1::1.68mm
R1380
0
21
5%
1/16W
MF-LF
402
NOSTUFF
C1380
20UF
20%
6.3V
CERM-X5R
0402
BYPASS=U0500.V19::10.17mm
BYPASS=U0500.V19::10.17mm
NOSTUFF
1
2
C1381
20UF
6.3V
CERM-X5R
0402
1
20%
2
PP1V_SUS_PCH_VCCCLK3
MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.0V
9
PCH VCCCLK4 FILTER/BYPASS
(PCH 1.0V CLOCK 4 PWR)
PCH VCCAPLLEBB BYPASS
PP1V_PRIM
75
(PCH 1.0V APLL EBB PWR)
PP1V_PRIM
9 75
1
C1307
0.1UF
2
BYPASS=U0500.AK19::1.68mm
10%
6.3V
X6S
0201
1
C1344
0.1UF
2
BYPASS=U0500.R15::1.54mm
10%
6.3V
X6S
0201
1
2
R1385
0
21
5%
1/16W
MF-LF
402
NOSTUFF
C1385
20UF
20%
6.3V
CERM-X5R
0402
BYPASS=U0500.V21::10.17mm
BYPASS=U0500.V21::10.17mm
NOSTUFF
1
2
C1386
20UF
6.3V
CERM-X5R
0402
1
20%
2
PP1V_SUS_PCH_VCCCLK4
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V
9
C
B
PCH VCCPGPPE BYPASS
(PCH 3.3V/1.8V GPIO GROUP E PWR)
PP3V3_S5
9 75
C1318
0.1UF
BYPASS=U0500.AA2::0.84mm
PCH VCCATS BYPASS
(PCH 1.8V THERMAL PWR)
PP1V8_S5
9 75
C1330
1.0UF
BYPASS=U0500.AE15::1.76mm
10%
6.3V
X6S
0201
20%
6.3V
X5R
0201-1
PCH VCCCLK5 FILTER/BYPASS
(PCH 1.0V CLOCK 5 PWR)
PCH VCCMPHYGT_1P0 BYPASS
PP1V_PRIM
75
(PCH 1.0V MPHY GATED PWR)
PP1V_PRIM
9 75
10%
6.3V
X6S
0201
1
C1347
1.0UF
2
0201-1
BYPASS=U0500.T15::4.18mm
1
C1346
0.1UF
2
BYPASS=U0500.T15::3.07mm
20%
6.3V
X5R
1
C1348
20UF
2
CERM-X5R
BYPASS=U0500.T15::4.18mm
20%
6.3V
0402
1
2
R1390
0
21
5%
1/16W
MF-LF
402
OMIT_TABLE
NOSTUFF
C1390
20UF
20%
6.3V
CERM-X5R
0402
BYPASS=U0500.R21::10.17mm
BYPASS=U0500.R21::10.17mm
BYPASS=U0500.R21::0.92mm
NOSTUFF
1
2
C1391
20UF
6.3V
CERM-X5R
0402
1
20%
2
L1309
PP1V8_S5
75
PLACE_NEAR=L1309.1:1mm
1
1
2
C1308
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
220-OHM-0.7A-0.28-OHM
PLACE_NEAR=U0500.AT23:1mm
21
0402-1
NOSTUFF
1
C1304
0.1UF
10%
6.3V
2
X6S
0201
PP1V_SUS_PCH_VCCCLK5
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V
1
C1392
0.1UF
10%
6.3V
2
X6S
0201
PCH VCCHDA FILTER/BYPASS
(PCH 3.3V/1.8V/1.5V HDA PWR)
PP3V3R1V8R1V5_S0_PCH_VCCHDA
MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.5V
1
C1309
2.9PF
+/-0.05PF
25V
2
C0G-CERM
0201
BYPASS=U0500.AT23::1.23mm
9
9
B
A
PP1V_PRIM
75
PART# DESCRIPTIONQTY
155S0391 L1309,L13952
155S00480 L1309,L13952
PLACE_NEAR=L1395.1:1mm
1
C1393
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
FERR BD,220 OHM,25%,700MA,0.28 DCR,0402
RES,MTL FILM,0 OHM,1A MAX,0402,SMD
FERR BD,30 OHMZ,25%,0.6A,0.449 OHM,0402
OMIT_TABLE
L1395
220-OHM-0.7A-0.28-OHM
PLACE_NEAR=U0500.AA18:1mm
21
0402-1
BYPASS=U0500.AT23::1.23mm
NOSTUFF
1
C1394
0.1UF
10%
6.3V
2
X6S
0201
BYPASS=U0500.AA18::1.23mm
TABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
PCHFLTR:FERRITE
TABLE_5_ITEM
PCHFLTR:BYPASS2 L1309,L1395116S0004
TABLE_5_ITEM
PCHFLTR:FERRITE30
PCH VCCAPLL FILTER/BYPASS
(PCH 1.0V APLL PWR)
PP1V_SUS_PCH_VCCAPLL
MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.0V
1
C1395
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
BYPASS=U0500.AA18::1.23mm
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
9
A
8
PCH Decoupling
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
13 OF 145
SHEET
13 OF 85
1
SIZE
D
D
678
3 245
1
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
20
18
IN
OUT
TP_HDA_SYNC
TP_HDA_BIT_CLK
HDA_SDOUT
TP_HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_RST_L
SPT_XDP_PCH_OBSDATA_D0
TP_PCH_I2S1_SFRM
TP_PCH_I2S1_TXD
TP_PCH_GPP_F1
TP_PCH_GPP_F0
TP_PCH_GPP_F2
TP_PCH_GPP_F3
BJ19
BK18
BK16
BL15
BL17
BL19
V5
BL12
BK14
AT13
AT11
AP11
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST*/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
(IPD-PLTRST#)
(IPD-PLTRST#)
(IPD)
BGA
947915
SYM 7 OF 20
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
(IPD)
AUDIO
GPP_A17/SD_PWR_EN*/ISH_GP7
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD*
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AH9
AH11
AG12
AF9
AF11
AG8
AG10
AE12
BL4
BN4
BF1
AJ8AT5
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_POC_RESET
JTAG_TBT_X_TMS
TBT_X_PCI_RESET_L
JTAG_ISP_TCK
JTAG_ISP_TDI
JTAG_ISP_TDO
TP_PCH_GPP_A17
TP_PCH_GPP_A16
TP_PCH_SD_RCOMP
TP_PCH_GPP_F23
OUT
OUT
OUT
OUT
OUT
OUT
OUT
29
29
PLT_RST_3V3_L
1
R1424
28 27 25 14
28 27 25 14
27 14
27 25 14
25 14
25 14
25 14
100K
5%
1/20W
MF
201
2
OUT
27 25
IN
20
D
C
18
18
18
18
OUT
OUT
OUT
OUT
SPT_XDP_PCH_OBSDATA_C2
SPT_XDP_PCH_OBSDATA_C3
SPT_XDP_PCH_OBSDATA_C0
SPT_XDP_PCH_OBSDATA_C1
NC_PCH_STRP_TOPBLK_SWP_L
77
77
77
77
77
20
77
OUT
BI
BI
BI
BI
OUT
NC_SPI_PCHROM_CLK
NC_SPI_PCHROM_MISO
NC_SPI_PCHROM_MOSI
NC_SPI_PCHROM_IO<2>
SPI_PCHROM_IO<3>
NC_SPI_PCHROM_CS_L
TP_SPI_CS1_L
TP_SPI_CS2_L
TP_PCH_GPP_D1
TP_PCH_GPP_D2
TP_PCH_GPP_D3
17
MLB_RAMCFG4
IN
TP_PCH_GPP_D22
TP_PCH_GPP_D0
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
PCH_GPP_A0_PU
14
TP_PCH_GPP_A6
V3
V11
U12
U8
AV3
CKPLUS_WAIVE=CLK_DATA_CONCKPLUS_WAIVE=CLK_DATA_CON
CKPLUS_WAIVE=CLK_DATA_CON
U0500.V5, U0500.V3, U0500.U12
AU10
AU12
AV11
AV13
BL10
SPI0_CLK
SPI0_MISO
AT3
SPI0_MOSI
SPI0_IO2
SPI0_IO3
AU4
SPI0_CS0*
AU6
SPI0_CS1*
AU8
SPI0_CS2*
P9
GPP_D1
N8
GPP_D2
P3
GPP_D3
W12
GPP_D21
V7
GPP_D22
N6
GPP_D0
F12
CL_CLK
D12
CL_DATA
B12
CL_RST*
GPP_A0/RCIN*
BN8
GPP_A6/SERIRQ
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
(IPD-PLTRST#)
CRITICAL
OMIT_TABLE
KBL-PCH-Y-QKKR
(IPU-RSMRST#)
(IPU)
(IPU-RSMRST#)
(IPU)
(IPU)
(IPU-RSMRST#)
(IPU-RSMRST#)
(IPU-RSMRST#)
(IPU/IPD)
(IPU/IPD)
(IPU-eSPI)
(IPU-eSPI)
SPI - FLASHC LINK
U0500
BGA
947915
SYM 5 OF 20
(IPU)
LPC SMBUS, SMLINK
(IPU-eSPI)
GPP_A14/SUS_STAT*/ESPI_RESET*
SDIO/SDXC
GPP_C0/SMBCLK
GPP_C1/SMBDATA
(IPD-RSMRST#)
(IPD-RSMRST#)
GPP_B23/SML1ALERT*/PCHHOT*
(IPD-PLTRST#)
GPP_A5/LFRAME*/ESPI_CS*
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C2/SMBALERT*
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT*
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN*
AC12
W6
W8
W4
AC10
AA6
AA4
W10
BB6
BK11
BJ8
BG10
BP5
BP7
BJ6
BJ10
BF5
BH11
SMBUS_PCH_CLK
SMBUS_PCH_DATA
TP_PCH_STRP_TLSCONF
SML_PCH_0_CLK
SML_PCH_0_DATA
PCH_STRP_ESPI
I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA
TP_PCH_STRP_BSSB_SEL_GPIO
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
ESPI_RESET_L
ESPI_CLK60M_R
R1476
TP_PCH_GPP_A10
TP_PCH_GPP_A8
OUT
OUT
14
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
45
45
45
45
45
45
35
35
35
35
35
35
22
LPC strap sampled at RSMRST# rising (0 = LPC, 1 = eSPI)
21
1% MF1/20W
201
ESPI_CLK60M
OUT
35
C
B
PP1V8_S5
PP3V3_S5
PM_SLP_S3_L
B
9 17 75
9 75
79 25 20 15 5
A
R1420
R1421
R1422
R1423
R1468
R1475
R1425
R1426
R1427
8
100K
100K
10K
10K
100K
1K
100K
100K
100K
21
5%
21
21
21
21
21
21
21
21
1/20W MF5% 201
5% 201
5% 2011/20W
1/20W
1/20W MF
5% 201
MF 2011/20W
MF1/20W 2015%
MF1/20W
MF
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
JTAG_TBT_X_TMS
2015% MF1/20W
JTAG_ISP_TDO
2011/20W MF5%
PCH_GPP_A0_PU
PCH_STRP_ESPI
TBT_POC_RESET
JTAG_ISP_TCK
2015% MF
JTAG_ISP_TDI
14
14
29 28 27 25 14
29 28 27 25 14
27 25 14
25 14
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
PCH Audio/LPC/SPI/SMBus
DRAWING NUMBER
SIZE
051-04039
Apple Inc.
27 14
25 14
25 14
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
REVISION
2.0.0
BRANCH
PAGE
14 OF 145
SHEET
14 OF 85
1
A
D
D
PP1V_S3
6 8 12 59 75
19
IN
R1523
CPU_VCCST_PWRGD
1K
5%
1/20W
MF
201
678
3 245
1
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 11 OF 20
1
2
R1522
60.4
1%
1/20W
MF
201
79 42 20 17 15 6
42 20
21
PLACE_NEAR=U0500.B61:7.62mm
79 42
42 33
42
OUT
IN
IN
IN
IN
PLT_RST_L
PM_SYSRST_L
PM_RSMRST_L
TP_CPU_PWRGD
CPU_VCCST_PWRGD_R
PM_PCH_SYS_PWROK
PM_PCH_PWROK
TP_PCH_GPP_A13
TP_PCH_GPP_A15
PCIE_WAKE_L
15
TP_PCH_LAN_WAKE_L
15
TP_PCH_LANPHYPC
TP_PCH_GPD7
BB8 BC9
GPP_B13/PLTRST*
H2
SYS_RESET*
BJ12
BP14
BN15
BE15
BC15
BB16
RSMRST*
A62
PROCPWRGD
B61
VCCST_PWRGD
J1
SYS_PWROK
PCH_PWROK
DSW_PWROK
BL6
GPP_A13/SUSWARN*/
SUSPWRDNACK
BF9
GPP_A15/SUSACK*
BP9
WAKE*
GPD2/LAN_WAKE*
GPD11/LANPHYPC
GPD7/RSVD
(IPD-DeepSx)
SYSTEM POWER MANAGEMENT
(IPU)
(IPU)
(IPD-DeepSx)
(IPD-DeepSx)
(IPU)
GPP_B11/EXT_PWR_GATE*
GPP_B12/SLP_S0*
GPD4/SLP_S3*
GPD5/SLP_S4*
GPD10/SLP_S5*
SLP_SUS*
SLP_LAN*
GPD9/SLP_WLAN*
GPD6/SLP_A*
GPD3/PWRBTN*
GPD1/ACPRESENT
GPD0/BATLOW*
GPP_A11/PME*
INTRUDER*
GPP_B2/VRALERT*
AY14
BF16
BH14
BN10
BP11
BH16
BE17
BF14
BD14
BD16
BF7
BG19
BC7
BD6
PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
TP_PCH_SLP_SUS_L
TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L
TP_PCH_SLP_A_L
PCH_PWRBTN_L
NC_SPIROM_USE_MLB
PCH_BATLOW_L
TP_PCH_GPP_A11
PCH_INTRUDER_L
TP_HSIO_PWR_EN
TP_PCH_GPP_B2
15
OUT
OUT
OUT
OUT
IN
BI
77
82 79 66 65 35 15
79 25 20 15 14 5
79 15
79 15
PP3V_G3H
65 15
1
R1580
1M
5%
1/20W
MF
201
2
9 75
D
C
C
B
PP3V3_S5
B
75
A
R1520
R1521
R1538
R1540
R1510
R1530
R1531
R1532
R1533
8
10K
100K
1K
100K
100K
100K
100K
100K
100K
21
21
21
21
21
21
21
21
21
1/20W 201
5% 1/20W MF 201
5%
1/20W 201MF
1/20W5% 201
1/20W5% MF 201
1/20W 201
5% MF
MF5%
MF5%
MF5% 1/20W
MF1/20W5%
MF
PCIE_WAKE_L
TP_PCH_LAN_WAKE_L
2011/20W
PCH_PWRBTN_L
201
PCH_BATLOW_L
PLT_RST_L
PM_SLP_S0_L
201
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
15
15
15
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
65 15
PCH Power Management
DRAWING NUMBER
SIZE
051-04039
79 42 20 17 15 6
82 79 66 65 35 15
79 25 20 15 14 5
79 15
79 15
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
Apple Inc.
REVISION
2.0.0
BRANCH
PAGE
15 OF 145
SHEET
15 OF 85
1
A
D
D
C
PCIe Port Assignments:
SOC BDF: 0/28/0
SOC lane 0
SOC lane 1
SOC lane 2
SOC lane 3
TBT BDF: 0/28/4
Thunderbolt X lane 0
Thunderbolt X lane 1
Thunderbolt X lane 2
Thunderbolt X lane 3
WLAN BDF: 0/29/0
WLAN
ENET/SD BDF: 0/29/1
Reserved: ENET/SD
R1610
100
1%
1/20W
MF
201
678
3 245
1
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
37
37
43
43
37
37
43
43
37
37
43
43
37
37
43
43
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
33
33
33
33
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>
PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>
PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>
PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>
PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_P<1>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_X_R2D_C_P<3>
PCIE_PCH_WLAN_D2R_N
PCIE_PCH_WLAN_D2R_P
PCIE_PCH_WLAN_R2D_C_N
PCIE_PCH_WLAN_R2D_C_P
TP_PCIE_PCH_ENETSD_D2RN
TP_PCIE_PCH_ENETSD_D2RP
TP_PCIE_PCH_ENETSD_R2D_CN
TP_PCIE_PCH_ENETSD_R2D_CP
1
PCH_PCIE_RCOMP_N
PCH_PCIE_RCOMP_P
PLACE_NEAR=U0500.B10:2.54mm
18
18
OUT
IN
2
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
TP_PCH_GPP_A7
C20
PCIE1_RXN/USB3_5_RXN
A20
PCIE1_RXP/USB3_5_RXP
G20
PCIE1_TXN/USB3_5_TXN
J20
PCIE1_TXP/USB3_5_TXP
B19
PCIE2_RXN/USB3_6_RXN
D19
PCIE2_RXP/USB3_6_RXP
F19
PCIE2_TXN/USB3_6_TXN
H19
PCIE2_TXP/USB3_6_TXP
C22
PCIE3_RXN
A22
PCIE3_RXP
G22
PCIE3_TXN
J22
PCIE3_TXP
B21
PCIE4_RXN
D21
PCIE4_RXP
F21
PCIE4_TXN
H21
PCIE4_TXP
C24
PCIE5_RXN
A24
PCIE5_RXP
G24
PCIE5_TXN
J24
PCIE5_TXP
B23
PCIE6_RXN
D23
PCIE6_RXP
F23
PCIE6_TXN
H23
PCIE6_TXP
C26
PCIE7_RXN/SATA0_RXN
A26
PCIE7_RXP/SATA0_RXP
G26
PCIE7_TXN/SATA0_TXN
J26
PCIE7_TXP/SATA0_TXP
B25
PCIE8_RXN/SATA1A_RXN
D25
PCIE8_RXP/SATA1A_RXP
F25
PCIE8_TXN/SATA1A_TXN
H25
PCIE8_TXP/SATA1A_TXP
C28
PCIE9_RXN
A28
PCIE9_RXP
G28
PCIE9_TXN
J28
PCIE9_TXP
B27
PCIE10_RXN
D27
PCIE10_RXP
F27
PCIE10_TXN
H27
PCIE10_TXP
A9
PCIE_RCOMPN
B10
PCIE_RCOMPP
D51
PROC_PRDY*
B55
PROC_PREQ*
BF3
GPP_A7/PIRQA*
(IPU)
(IPU)
947915
SYM 8 OF 20
SSIC / USB3
PCIE/USB3/SATA
USB2
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_5
USB2P_5
USB2N_7
USB2P_7
USB2N_3
USB2P_3
USB2N_9
USB2P_9
USB2N_2
USB2P_2
(IPD)
USB2_COMP
(IPU)
USB2_VBUSSENSE
GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*
(IPD-RSMRST#)
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED*
USB2_ID
C16
A16
G16
J16
B15
D15
F15
H15
C18
A18
G18
J18
B17
D17
F17
H17
AJ6
AJ4
AH5
AH3
AF5
AF3
AL6
AL4
AG6
AG4
AM3
AM5
N2
AF7
AE6
N12
M11
F8
B8
F10
H10
L8
G11
J11
N10
H8
USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P
TP_USB3_EXTB_D2R_N
TP_USB3_EXTB_D2R_P
TP_USB3_EXTB_R2D_C_N
TP_USB3_EXTB_R2D_C_P
NC_USB3_EXTC_D2RN
NC_USB3_EXTC_D2RP
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTC_R2D_CP
NC_USB3_EXTD_D2RN
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_R2D_CN
NC_USB3_EXTD_R2D_CP
USB_UPC_PCH_XA_N
USB_UPC_PCH_XA_P
TP_USB_5N
TP_USB_5P
TP_USB_7N
TP_USB_7P
TP_USB_EXTC_N
TP_USB_EXTC_P
TP_USB_9N
TP_USB_9P
USB_UPC_PCH_XB_N
USB_UPC_PCH_XB_P
PCH_USB2_COMP
USB2_VBUSSENSE
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
UPC_XA_FAULT_L
UPC_XB_FAULT_L
XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSDATA_B0
27
IN
27
IN
27
OUT
27
OUT
79
IN
79
IN
79
OUT
79
OUT
77
IN
77
IN
77
OUT
77
OUT
77
IN
77
IN
77
OUT
77
OUT
27
BI
27
BI
79
BI
79
BI
27
BI
27
BI
Grounded per SKL MOW 2015WW10
18
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
18
18 16
18 16
18
18
18
18
18
18
18
1
R1620
1K
2
USB3 Port Assignments:
Ext A (SS, DCI)
Ext B (SS)
Unused
Unused
USB Port Assignments:
Ext A (LS/FS/HS)
Unused
Unused
Ext C (LS/FS/HS)
Unused
Ext B (LS/FS/HS)
5%
1/20W
MF
201
PLACE_NEAR=U0500.N2:2.54mm
1
R1622
113
1%
1/20W
MF
201
2
D
C
B
37
37
37 16
25
25
20
33
33
33 16
OUT
OUT
BI
OUT
OUT
IN
OUT
OUT
PCIE_CLK100M_SOC_N
PCIE_CLK100M_SOC_P
SOC_CLKREQ_L
PCIE_CLK100M_TBT_X_N
PCIE_CLK100M_TBT_X_P
TBT_X_CLKREQ_PCH_L
TP_PCIE_CLK100M3N
TP_PCIE_CLK100M3P
TP_PCH_SRCCLKREQ3_L
PCIE_CLK100M_PCH_WLAN_N
PCIE_CLK100M_PCH_WLAN_P
PCH_WLAN_CLKREQ_L
NC_PCIE_CLK100M_DEBUGN
77
NC_PCIE_CLK100M_DEBUGP
77
PU_DEBUG_CLKREQ_L
16 77
H35
F35
AV9
J36
G36
BD10
J38
G38
AV5
H37
F37
AV7
H39
F39
BC5
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
SYM 10 OF 20
CLOCK SIGNALS
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1*
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2*
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3*
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4*
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5*
BGA
947915
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST*
RTCRST*
J34
G34
BA15
M1
L2
P1
BN19
BP18
BH18
BN12
NC
PP1V_PRIM
PLACE_NEAR=U0500.P1:2.54mm
1
TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP
TP_PCH_CLK32K_SUS
PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT
OUT
IN
19
19
PCH_DIFFCLK_BIASREF
PMU_CLK32K_PCH_1V0 PMU_CLK32K_PCH
PCH_RTC_RESET_L
IN
65
R1662
2.7K
1%
1/20W
MF
201
2
R1672
127K
1%
1/20W
MF
201
R1673
100K
1%
1/20W
MF
1
2
201
PLACE_NEAR=U0500.B19:2.54mm
PLACE_NEAR=U0500.B19:2.54mm
75
21
IN
B
65
A
PP1V8_S5
PP3V3_S5
R1630
R1631
R1650
R1656
R1660
8
100K
100K
47K
47K
47K
21
5%
21
5%
21
5% MF1/20W
21
21
TP_PCH_SRCCLKREQ0_L
75
75
BB10
GPP_B5/SRCCLKREQ0*
SYNC_MASTER=J122_MLB
PAGE TITLE
SYNC_DATE=03/30/2018
A
PCH PCIe/USB/CLK
DRAWING NUMBER
051-04039
MF1/20W 201
MF1/20W 201
1/20W MF5%
1/20W MF5%
UPC_XB_FAULT_L
SOC_CLKREQ_L
201
PCH_WLAN_CLKREQ_L
201
PU_DEBUG_CLKREQ_L
201
UPC_XA_FAULT_L
16 18
16 18
37 16
33 16
16 77
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
Apple Inc.
REVISION
2.0.0
BRANCH
PAGE
16 OF 145
SHEET
16 OF 85
1
SIZE
D
79 42 20 15 6
IN
PLT_RST_L
678
3 245
1
CRITICAL
OMIT_TABLE
D
C
35
OUT
1
R1702
100K
5%
1/20W
MF
201
2
79 27 17
79 27 17
34 17
OUT
PCH_SOC_SYNC
SOC_PERST_L
TP_PCH_GPP_B17
PCH_STRP_NO_REBOOT
17
TP_PCH_GPP_B19
TP_PCH_GPP_B20
TP_PCH_GPP_B21
TP_PCH_STRP_BOOT_SPI_L
33 17
33 17
33 17
33 17
IN
OUT
OUT
IN
IN
OUT
PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
TP_PCH_GPP_C22
PCH_UART2_CTS_L
17
TP_PCH_GPP_C16
TP_PCH_GPP_C17
TP_PCH_GPP_C18
TP_PCH_GPP_C19
TP_PCH_GPP_F4
TP_PCH_GPP_F5
TP_PCH_GPP_F6
TP_PCH_GPP_F7
TP_PCH_GPP_F8
TP_PCH_GPP_F9
BC3
AW10
AW6
BB4
BB2
AW12
AW4
AW8
AC8
AA8
AA10
AA12
AD5
AD7
AD3
AD9
AD11
AB3
AB9
AB11
AP3
AP7
AP5
AT7
AN4
AN6
LPSS
GPP_B15/GSPI0_CS*
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS*
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS*
GPP_C11/UART0_CTS*
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS*
GPP_C23/UART2_CTS*
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
(IPD-PLTRST#)
(IPD-PLTRST#)
U0500
KBL-PCH-Y-QKKR
BGA
947915
SYM 6 OF 20
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA
GPP_D14/ISH_UART0_TXD/SML0BCLK
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C15/UART1_CTS*/ISH_UART1_CTS*
ISH
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_D15/ISH_UART0_RTS*
GPP_D16/ISH_UART0_CTS*
/SML0BALERT*
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
SX_EXIT_HOLDOFF/GPP_A12
/BM_BUSY*/ISH_GP6
P11
T7
T5
T11
P7
P5
T9
T3
AM7
AT9
U10
U4
U6
V9
AC6
AC4
AB7
AB5
BF11
BD2
BJ1
BL3
BJ3
BD4
BJ4
TP_PCH_GPP_D9
TP_PCH_GPP_D10
TP_PCH_GPP_D11
TP_PCH_GPP_D12
TP_PCH_GPP_D5
TP_PCH_GPP_D6
TP_PCH_GPP_D7
TP_PCH_GPP_D8
TP_PCH_GPP_F10
TP_PCH_GPP_F11
MLB_RAMCFG0
MLB_RAMCFG1
MLB_RAMCFG2
MLB_RAMCFG3
TP_PCH_GPP_C12
TP_PCH_GPP_C13
TP_PCH_GPP_C14
TP_PCH_GPP_C15
TP_PCH_GPP_A18
TP_PCH_GPP_A19
TP_PCH_GPP_A20
TP_PCH_GPP_A21
TP_PCH_GPP_A22
TP_PCH_GPP_A23
TP_PCH_GPP_A12
D
17
17
17
17
C
B
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
H29
F29
F33
H33
J30
G30
J32
G32
D29
B29
C32
A32
C30
A30
D33
B33
D35
B35
C36
A36
D37
B37
C38
A38
CRITICAL
OMIT_TABLE
U0500
KBL-PCH-Y-QKKR
BGA
947915
H31
F31
D31
B31
C34
A34
D39
B39
A11
N4
AN12
AP9
AN10
AJ10
AM9
AL12
AJ12
AN8
AL10
AL8
AM11
BC1
NC
NC
NC
NC
NC
NC
NC
NC
TP_PCH_CSI2_COMP
TP_PCH_GPP_D4
TP_PCH_GPP_F13
TP_PCH_GPP_F14
PCH_WLAN_AUDIO_SYNC
TP_PCH_GPP_F16
TP_PCH_GPP_F17
TP_PCH_GPP_F18
TP_PCH_GPP_F19
TP_PCH_GPP_F20
TP_PCH_GPP_F21
PCH_BT_ROM_BOOT_L
TP_PCH_GPP_F12
TP_PCH_EMMC_RCOMP
OUT
IN
20 17
32 17
B
A
PP1V8_S5
PP1V8_S5
PP1V8_S5
R1704
R1710
R1711
R1712
R1713
R1714
R1715
R1740
R1700
R1717
R1783
1K
47K
47K
47K
47K
47K
47K
10K
100K
47K
100K
21
21
21
21
21
21
21
21
21
21
21
1/20W
1/20W 2015% MF
1/20W 2015% MF
1/20W
5% 1/20W
5% 1/20W
5% MF
1/20W MF
1/20W
9 75
9 14 75
9 75
MF 2015% 1/20W
2015% MF
2015% MF
MF 201
MF 201
2011/20W
2015%
MF5% 201
MF5% 1/20W 201
PCH_STRP_NO_REBOOT
PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
PCH_BT_ROM_BOOT_L
PCH_SOC_SYNC
PCH_UART2_CTS_L
PCH_WLAN_AUDIO_SYNC
17
17
RAM Configuration Straps
MLB_RAMCFG0
33 17
33 17
33 17
33 17
79 27 17
79 27 17
32 17
34 17
20 17
17
MLB_RAMCFG1
17
MLB_RAMCFG2
17
MLB_RAMCFG3
17
MLB_RAMCFG4
14
RAMCFG4_L
R1794
1K
5%
1/20W
MF
201
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
A
PCH GPIO/LPSS
RAMCFG3_L
1
2
R1793
1K
5%
1/20W
MF
201
1
2
R1792
1K
5%
1/20W
MF
201
1
2
RAMCFG1_LRAMCFG2_L
R1791
1K
5%
1/20W
MF
201
RAMCFG0_L
1
2
1K
5%
1/20W
MF
201
1
2
R1790
BOM_COST_GROUP=CPU & CHIPSET
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04039
REVISION
2.0.0
BRANCH
PAGE
17 OF 145
SHEET
17 OF 85
SIZE
D
8
67
35 4
2
1
678
3 245
1
D
C
CPU_CFG<0>
6
CPU_CFG<1>
6
CPU_CFG<2>
6
CPU_CFG<3>
6
CPU_CFG<4>
6
CPU_CFG<5>
6
CPU_CFG<6>
6
CPU_CFG<7>
6
CPU_CFG<8>
6
CPU_CFG<9>
6
CPU_CFG<10>
6
CPU_CFG<11>
6
CPU_CFG<12>
6
CPU_CFG<13>
6
CPU_CFG<14>
6
CPU_CFG<15>
6
CPU_CFG<16>
6
CPU_CFG<17>
6
CPU_CFG<18>
6
CPU_CFG<19>
6
D
TP XDP Signals
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PP1800
PP
0.50MM
PP1801
PP
0.50MM
PP1802
PP
0.50MM
PP1803
PP
0.50MM
PP1804
PP
0.50MM
PP1805
PP
0.50MM
PP1806
PP
0.50MM
PP1807
PP
0.50MM
PP1808
PP
0.50MM
PP1809
PP
0.50MM
PP1810
PP
0.50MM
PP1811
PP
0.50MM
PP1812
PP
0.50MM
PP1813
PP
0.50MM
PP1814
PP
0.50MM
PP1815
PP
0.50MM
PP1816
PP
0.50MM
PP1817
PP
0.50MM
PP1818
PP
0.50MM
PP1819
PP
0.50MM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
XDP_CPU_PREQ_L
16
XDP_CPU_PRDY_L
16
ITP_PMODE
6
XDP_BPM_L<0>
6
IFDIM Trigger for DCDC
XDP_BPM_L<1>
6
XDP_BPM_L<2>
6
XDP_BPM_L<3>
6
XDP_PRESENT_L
35
NOSTUFF
R1895
100K
5%
1/20W
MF
201
NOSTUFF
R1894
100K
5%
1/20W
MF
201
1
1
1
1
1
2
1
1
1
PP1820
PP
0.50MM
PP1821
PP
0.50MM
PP1822
PP
0.50MM
PP1823
PP
0.50MM
PP1824
PP
0.50MM
PP1825
PP
0.50MM
PP1826
PP
0.50MM
SM
SM
SM
SM
SM
SM
SM
C
1
2
B
A
PCH XDP Signals
These signals do not connect to the Primary (Merged) XDP connector in this architecture because it does not exist.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation, but also does not exist.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
Unused GPIOs have TPs.
PCH/XDP Signals Non-XDP Signals
16 6
BI OUT
16
BI
16
BI
6
BI
16
BI
16
BI
16
BI
14
BI
14
BI
14
BI
14
BI
16
BI
16
BI
16
BI
14
BI
6
BI
16
BI
XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
SPT_XDP_PCH_OBSDATA_C0
SPT_XDP_PCH_OBSDATA_C1
SPT_XDP_PCH_OBSDATA_C2
SPT_XDP_PCH_OBSDATA_C3
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
SPT_XDP_PCH_OBSDATA_D0
XDP_PCH_OBSFN_C1
UPC_XA_FAULT_L
UPC_XB_FAULT_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PP1868
PP
PP1869
PP
PP1870
PP
PP1871
PP
PP1872
PP
PP1873
PP
PP1874
PP
PP1880
PP
PP1881
PP
PP1882
PP
PP1883
PP
PP1875
PP
PP1876
PP
PP1877
PP
PP1878
PP
PP1884
PP
MAKE_BASE=TRUE
PP1885
PP
MAKE_BASE=TRUE
PP1886
PP
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
0.50MM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
SM
UPC_XA_FAULT_L
UPC_XB_FAULT_L
IN
INBI
28
29 16
PP1V_S0SW
JTAG Chain for DCI Only Connectivity
6
6
6
XDP_CPUPCH_TDO
IN
XDP_CPUPCH_TDO
OUT
XDP_CPUPCH_TCK
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
XDP_CPUPCH_TDO
XDP_CPUPCH_TCK
PLACE_NEAR=U0500.B51:28MM
PLACE_NEAR=U0500.D53:28MM
1
R1890
51
5%
1/20W
MF
201
2
6 8 12
75
XDP_CPUPCH_TCK
1
R1892
6
6
6
6
6
6
6
XDP_CPUPCH_TRST_L
OUT
XDP_CPUPCH_TRST_L
OUT
XDP_CPUPCH_TMS
OUT
XDP_CPUPCH_TMS
OUT
XDP_CPUPCH_TDI
OUT
XDP_CPUPCH_TDI
OUT
TP_XDP_PCH_TCK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TMS
XDP_CPUPCH_TDI
TP_XDP_PCH_TCK
SYNC_MASTER=X589_CPU_CNL_Y
PAGE TITLE
2
51
5%
1/20W
MF
201
SYNC_DATE=03/13/2017
B
A
CPU/PCH Merged XDP
SIZE
D
BOM_COST_GROUP=DEBUG
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04039
REVISION
2.0.0
BRANCH
PAGE
18 OF 145
SHEET
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8
67
35 4
2
1
678
3 245
1
D
CRITICAL
C1900
7PF
21
+/-0.1PF
25V
CERM
0201
2
4
CRITICAL
C1901
7PF
21
+/-0.1PF
25V
CERM
0201
24MHz Crystal
PCH_CLK24M_XTALOUT_R
CRITICAL
1
Y1900
2.5X2.0MM-SM
24MHZ-10PPM-8PF-40OHM
3
R1900
0
21
5%
1/20W
MF
0201
PCH_CLK24M_XTALOUT
1
R1901
1M
5%
1/20W
MF
201
2
PCH_CLK24M_XTALIN
OUT
IN
16
D
16
C
59 19
IN
PP1V8_S5
75
ALL_SYS_PWRGD_R
VCCST_PWRGD Generation
BYPASS=U1920::5mm
C1920
0.1UF
10%
6.3V
CERM-X5R
0201
C
1
2
2
1
6
VCC
U1920
74AUP1G07GF
SOT891
GND
3
4
YA
NCNC
CPU_VCCST_PWRGD
5
NC
OUT
15
B
PP1V8_S5
75
42 35
65
IN
IN
ALL_SYS_PWRGD Qualifier
BYPASS=U1910::2MM
SMC_RSMRST_L
ALL_SYS_PWRGD
C1910
0.1UF
10%
6.3V
CERM-X5R
0201
B
1
U1910
2
VCC
2
A Y
1
B
5
NC
NC
GND
74AUP1G08GF
6
SOT891
3
4
ALL_SYS_PWRGD_R
1
R1911
1M
5%
1/20W
MF
201
2
OUT
59 19
A
8
NOSTUFF
R1910
0
21
5%
1/20W
MF
0201
SYNC_MASTER=X589_CPU_CNL_Y
PAGE TITLE
SYNC_DATE=03/27/2017
A
Chipset Shared Support
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
19 OF 145
SHEET
19 OF 85
1
SIZE
D
678
3 245
1
D
PP3V3_S5
75
PLTRST# 3.3V Level Shifter
BYPASS=U2030::2MM
10%
6.3V
0201
1
2
1
2
U2030
SN74AUP1T97
5
SON
4
6
3
1
R2030
100K
5%
1/20W
MF
201
2
OUTIN
C2030
0.1UF
CERM-X5R
PLT_RST_L
DP DDP Straps
PP3V3_S5
75
1
R2001
2.2K
5%
1/20W
MF
201
2
D
5%
1/20W
MF
201
1
2
R2000
2.2K
14 79 42 20 17 15 6
79 35
79 35
BI
DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO
IN
BI
27
27
5
OUT
5
OUT
PCH_DDPB_CTRLDATAPLT_RST_3V3_L
PCH_DDPC_CTRLDATA
C
16
79 25 15 14 5
OUT
IN
TBT X CLKREQ Level Shifter
PP1V8_S5
75
BYPASS=U2040::2MM
C2040
0.1UF
10%
6.3V
CERM-X5R
0201
TBT_X_CLKREQ_PCH_L
PM_SLP_S3_L
SAF Selector
NO_XNET_CONNECTION=1
R2092
0
5%
MF
0201
SAF
NC
21
Q2090
3
D
C
DMN32D2LFB4
DFN1006H4-3
SYM_VER_2
1
4
Y
PM_RSMRST
51
NCNC
R2093
100K
5%
1/20W
MF
201
1
2
SG
2
1
R2091
1K
5%
1/20W
MF
201
2
14
PP3V3_S5
BYPASS=U2040::2MM
1
1
2
8
VCCVL
1
C2041
0.1UF
10%
6.3V
2
CERM-X5R
0201
75
IN
75
U2040
NLSX4402
2
3
5
IO/VL1
IO/VL2
EN
UDFN
IO/VCC1
IO/VCC2
(10k IPUs)
GND
4
7
TBT_X_CLKREQ_L
6
NCNC
IN
25
42 15
IN
R2090
PM_RSMRST_L PM_RSMRST_RC_L SAF_SEL_S
5.6K
1/20W
5%
MF
201
21
SPI_PCHROM_IO<3> SPI_IO3_D
1/20W
PP3V3_S5
BYPASS=U2090::2MM
10%
6.3V
0201
1
2
2
A
NC
U2090
74AUP1G14
6
X2-DFN1010-6
VCC
GND
3
C2094
C2090
1000PF
10%
16V
X7R-1
0201
0.1UF
CERM-X5R
1
2
B
PP1V8_S5
75
79 34 32 17
79 42 20 17 15 6
WLAN_AUDIO_SYNC Isolation
BYPASS=U2050::5mm
10%
6.3V
0201
5%
MF
201
1
2
2
A
NOSTUFF
1
2
R2051
U2050
74AUP1G126GX
5
X2SON5
4
Y
OE
1
3
0
21
5%
1/20W
MF
0201
PCH_WLAN_AUDIO_SYNC
C2050
0.1UF
CERM-X5R
IN OUT
IN
WLAN_AUDIO_SYNC
PLT_RST_L
R2050
100K
1/20W
HDA_SDOUT
1
C2095
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
OUT
B
14
A
8
SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=03/07/2017
PAGE TITLE
A
Chipset Project Support
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
20 OF 145
SHEET
20 OF 85
1
SIZE
D
678
3 245
1
D
C
B
D
CPU-Based Margining
PP1V2_S3
VRef Dividers
R2223
10
1%
MF
201
10
1%
MF
201
5.1
1%
MF
0201
21
PLACE_NEAR=R2221.2:1mm
1%
1/20W
MF
201
1
2
R2222
8.2K
R2220
24.9
1/20W
21
PLACE_NEAR=R2241.2:1mm
21
1%
MF
201
R2242
8.2K
1%
1/20W
MF
201
1
2
R2240
24.9
1/20W
21
PLACE_NEAR=R2261.2:1mm
21
1%
MF
201
R2262
8.2K
1%
1/20W
MF
201
1
2
R2260
24.9
1/20W
1%
MF
201
21
7
CPU_DIMMA_VREFDQ
1/20W
1
C2220
0.022UF
10%
6.3V
2
X5R-CERM
0201
MEM_VREFDQ_A_RC
R2243
7
IN
CPU_DIMMB_VREFDQ
1/20W
1
C2240
0.022UF
10%
6.3V
2
X5R-CERM
0201
MEM_VREFDQ_B_RC
R2263
7
IN
CPU_DIMM_VREFCA
1/20W
1
C2260
0.022UF
10%
6.3V
2
X5R-CERM
0201
MEM_VREFCA_A_RC
1
R2221
8.2K
1%
1/20W
MF
201
2
PPVREF_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
1
R2241
8.2K
1%
1/20W
MF
201
2
PPVREF_S3_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
1
R2261
8.2K
1%
1/20W
MF
201
2
PPVREF_S3_MEM_VREFCA
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
76
76
C
76
76
B
A
8
SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018
PAGE TITLE
A
LPDDR3 VREF MARGINING
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
22 OF 145
SHEET
21 OF 85
1
SIZE
D
678
3 245
1
D
C
B
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 22 7
24 22 7
24 7
24 7
24 22 7
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_ODT<0>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<10>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
CRITICAL
CA0_A
CA1_A
CA2_A
CA3_A
OMIT_TABLE
U2300
BGA
SYM 1 OF 2
CA4_A
CA5_A
CA6_A
CA7_A CA7_B
ELPIDA
CA8_A
CA9_A
CK_T_A
CK_C_A CK_C_B
32GB-LPDDR3X64
CS0_A*
CS1_A*
CKE0_A
CKE1_A
ODT_A
DM0_A
DM1_A
DM2_A
DM3_A
DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DDR B
DQ9_A
DDR A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DQ16_A
DQ17_A
DQ18_A
DQ19_A
DQ20_A
DQ21_A
DQ22_A
DQ23_A
DQ24_A
DQ25_A
DQ26_A
DQ27_A
DQ28_A
DQ29_A
DQ30_A
DQ31_A
DQS0_T_A
DQS0_C_A
DQS1_T_A
DQS1_C_A
DQS2_T_A
DQS2_C_A
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
CA6_B
CA8_B
CA9_B
CK_T_B
CS0_B*
CS1_B*
CKE0_B
CKE1_B
ODT_B
DM0_B
DM1_B
DM2_B
DM3_B
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DQ16_B
DQ17_B
DQ18_B
DQ19_B
DQ20_B
DQ21_B
DQ22_B
DQ23_B
DQ24_B
DQ25_B
DQ26_B
DQ27_B
DQ28_B
DQ29_B
DQ30_B
DQ31_B
DQS0_T_B
DQS0_C_B
DQS1_T_B
DQS1_C_B
DQS2_T_B
DQS2_C_B
BYPASS=U2300.A15::5mm
PP1V8_S3
23 66 75
L2B5
L3C5
L4D5
K2B6
K3C6
G3C9
G4D9
F2B10
F3C10
F4D10
H3B8
H2C8
K4D6
J2B7
J3C7
J4D7
H13N8
MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>MEM_A_CAB<9>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_ODT<0>
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
24 7
24 7
20%
6.3V
CERM
0402
20%
6.3V
CERM
0402
1
2
C2341
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.B17::5mm
1
2
C2351
10UF
20%
6.3V
CERM
0402
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 22 7
24 22 7
PP1V2_S3
23 76
C2340
10UF
C2350
10UF
24 7
24 7
24 22 7
H14N6
F13P8
L14P4
D14P11
L15N4
L16T5
K13R5
K14P5
K15N5
K16T6
J15R6
J16P6
F14T9
F15R9
F16T10
E13R10
E14P10
E15N10
E16T11
D13R11
P15T2
P16R2
N14P2
N15N2
N16T3
M13R3
M14P3
L13N3
C13N11
C14N12
C15P12
C16T13
B13R13
B14P13
B15T14
B16R14
J14P7
J13N7
G14P9
G13N9
M16T4
M15R4
MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<43>
MEM_A_DQ<45>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<57>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQ<63>
MEM_A_DQ<59>
MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<58>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
PP1V2_S3
23 76
PP1V2_S3
23 76
C2370
10UF
20%
6.3V
CERM
0402
C2380
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.A9::5mm
1
2
C2371
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.A13::5mm
1
2
C2385
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.T16::5mm
1
2
C2342
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.U2::5mm
1
2
C2352
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.G2::5mm
1
2
C2372
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.K17::5mm
1
2
C2390
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.B2::5mm
1
2
BYPASS=U2300.A11::5mm
1
2
BYPASS=U2300.K1::5mm
1
2
BYPASS=U2300.U10::5mm
1
2
C2343
10UF
20%
6.3V
CERM
0402
C2353
10UF
20%
6.3V
CERM
0402
BYPASS=U2300.T1::5mm
1
2
BYPASS=U2300.R15::5mm
1
2
CRITICAL
R1
VDD1_A/B VSS_A/B
T1
VDD1_A/B
B2
VDD1_A/B
A15
VDD1_A/B
A16
VDD1_A/B
T16
VDD1_A/B
OMIT_TABLE
U2300
BGA
SYM 2 OF 2
ELPIDA
32GB-LPDDR3X64
H1
VDD2_A/B
L1
VDD2_A/B
U2
VDD2_A/B
C3
VDD2_A/B
U3
VDD2_A/B
R15
VDD2_A/B
H16
VDD2_A/B
B17
VDD2_A/B
C17
VDD2_A/B
A7
VDD2_A/B
T8
VDD2_A/B
A11
VDD2_A/B
A6
VDDCA_A/B
E1
VDDCA_A/B
K1
VDDCA_A/B
G2
VDDCA_A/B
A9
VDDCA_A/B
B9
VDDCA_A/B
N1
VDDQ_A/B
M2
VDDQ_A/B
M3
VDDQ_A/B
U5
VDDQ_A/B
B12
VDDQ_A/B
C12
VDDQ_A/B
G12
VDDQ_A/B
K12
VDDQ_A/B
M12
VDDQ_A/B
A13
VDDQ_A/B
U14
VDDQ_A/B
E17
VDDQ_A/B
G17
VDDQ_A/B
K17
VDDQ_A/B
L17
VDDQ_A/B
P17
VDDQ_A/B
M7
VDDQ_A/B
U7
VDDQ_A/B
M10
VDDQ_A/B
U10
VDDQ_A/B
U11
VDDQ_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
B1
C1
D1
F1
G1
M1
P1
A2
C2
D2
A3
B3
D3
A4
B4
C4
D4
M4
U4
A5
E5
F5
G5
H5
J5
K5
L5
M5
A12
D12
E12
F12
H12
L12
U12
N13
U13
A14
P14
G15
H15
T15
U15
G16
R16
U16
D17
F17
J17
M17
N17
R17
T17
E6
M6
U6
E7
R7
T7
A8
E8
M8
R8
E9
U9
E10
E11
M11
D
C
B
A
PPVREF_S3_MEM_VREFCA
22 76
PPVREF_S3_MEM_VREFDQ_A
22 76
78
78
R2300
243
1%
1/20W
MF
201
NC
NC
NC
NC
NC
NC
1
2
D16T12
D15R12
E2B11
J1A10
H17U8
A17A1
U17U1
D8
M9
C11
D11
C2331
0.047UF
NC
NC
NC
NC
NC
6.3V
BI
BI
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_ZQ_B MEM_A_ZQ_A
DQS3_T_A
DQS3_C_A
ZQ_A
VREFCA_A
VREFDQ_A
E3
E4
H4
J12
NC
NC
NC
NC
NC
NC
1
C2312
0.1UF
10%
2
CERM-X5R
0201
NC
NC
MEM_A_ZQ1_A
NC
NC
RAM_16GB
1
2
1
R2321
243
1%
1/20W
MF
201
2
C2310
0.047UF
10%
6.3V
X5R
201
1
2
1
2
NC
C2311
0.047UF
10%
6.3V
X5R
201
DQS3_T_B
DQS3_C_B
ZQ_B
VREFCA_B
VREFDQ_B
C2332
0.1UF
10%
6.3V6.3V
CERM-X5R
0201
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
1
C2330
0.047UF
10%
6.3V
2
X5R
201
10%
X5R
201
1
2
MEM_A_ZQ1_B
RAM_16GB
R2301
243
1%
1/20W
MF
201
78
BI
78
BI
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ_A
1
2
1
R2320
243
1%
1/20W
MF
201
2
22 76
22 76
PAGE TITLE
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
LPDDR3 DRAM Channel A (0-63)
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04039
REVISION
A
2.0.0
BRANCH
PAGE
23 OF 145
SHEET
22 OF 85
BOM_COST_GROUP=DRAM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
67
35 4
2
1
678
3 245
1
D
C
B
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 23 7
24 23 7
24 7
24 7
24 23 7
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CRITICAL
MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>
MEM_B_CLK_P<1>
CA0_A
CA1_A
CA2_A
CA3_A
OMIT_TABLE
U2500
BGA
SYM 1 OF 2
CA4_A
CA5_A
CA6_A
CA7_A CA7_B
ELPIDA
CA8_A
CA9_A
CK_T_A
CK_C_A CK_C_B
32GB-LPDDR3X64
CS0_A*
MEM_B_CS_L<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_ODT<0> MEM_B_ODT<0>
CS1_A*
CKE0_A
CKE1_A
ODT_A
DM0_A
DM1_A
DM2_A
DM3_A
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<4>
MEM_B_DQ<1>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<7>
MEM_B_DQ<3>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<8>
MEM_B_DQ<12>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<41>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<40>
MEM_B_DQ<44>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DQ16_A
DQ17_A
DQ18_A
DQ19_A
DQ20_A
DQ21_A
DQ22_A
DQ23_A
DQ24_A
DQ25_A
DQ26_A
DQ27_A
DQ28_A
DQ29_A
DQ30_A
DQ31_A
DQS0_T_A
DQS0_C_A
DQS1_T_A
DQS1_C_A
DQS2_T_A
DQS2_C_A
DDR B
DDR A
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
CA6_B
CA8_B
CA9_B
CK_T_B
CS0_B*
CS1_B*
CKE0_B
CKE1_B
ODT_B
DM0_B
DM1_B
DM2_B
DM3_B
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DQ16_B
DQ17_B
DQ18_B
DQ19_B
DQ20_B
DQ21_B
DQ22_B
DQ23_B
DQ24_B
DQ25_B
DQ26_B
DQ27_B
DQ28_B
DQ29_B
DQ30_B
DQ31_B
DQS0_T_B
DQS0_C_B
DQS1_T_B
DQS1_C_B
DQS2_T_B
DQS2_C_B
L2B5
L3C5
L4D5
K2B6
K3C6
G3C9
G4D9
F2B10
F3C10
F4D10
H3B8
H2C8
K4D6
J2B7
J3C7
J4D7
MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>MEM_B_CLK_N<1>
MEM_B_CS_L<0>MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
H13N8
H14N6
F13P8
L14P4
D14P11
L15N4
L16T5
K13R5
K14P5
K15N5
K16T6
J15R6
J16P6
F14T9
F15R9
F16T10
E13R10
E14P10
E15N10
E16T11
D13R11
P15T2
P16R2
N14P2
N15N2
N16T3
M13R3
M14P3
L13N3
C13N11
C14N12
C15P12
C16T13
B13R13
B14P13
B15T14
B16R14
J14P7
J13N7
G14P9
G13N9
M16T4
M15R4
MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<58>
MEM_B_DQ<63>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BYPASS=U2500.A15::5mm
PP1V8_S3
22 66 75
24 7
24 7
20%
6.3V
CERM
0402
1
2
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
C2540
10UF
C2541
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.T16::5mm
1
2
C2542
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.B2::5mm
1
2
C2543
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.T1::5mm
1
2
R1
T1
B2
A15
A16
T16
CRITICAL
OMIT_TABLE
U2500
BGA
ELPIDA
B1
C1
D1
F1
G1
M1
P1
A2
C2
D2
D
A3
24 7
24 7
24 23 7
24 23 7
24 7
24 7
PP1V2_S3
22 76
C2550
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.B17::5mm
1
2
C2551
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.U2::5mm
1
2
C2552
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.A11::5mm
1
2
C2553
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.R15::5mm
1
2
H1
L1
U2
C3
U3
R15
32GB-LPDDR3X64
H16
24 23 7
B17
C17
A7
T8
A11
B3
D3
A4
B4
C4
D4
M4
U4
A5
E5
F5
G5
H5
J5
K5
L5
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
PP1V2_S3
22 76
PP1V2_S3
22 76
C2570
10UF
20%
6.3V
CERM
0402
C2580
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.A9::5mm
1
2
C2571
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.A13::5mm
1
2
C2585
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.G2::5mm
1
2
BYPASS=U2500.K17::5mm
1
2
C2572
10UF
20%
6.3V
CERM
0402
C2590
10UF
20%
6.3V
CERM
0402
BYPASS=U2500.E1::5mm
1
2
BYPASS=U2500.U10::5mm
1
2
A6
E1
K1
G2
A9
B9
N1
M2
M3
U5
B12
C12
G12
K12
M12
A13
U14
E17
G17
K17
L17
P17
M7
U7
M10
U10
U11
M5
A12
D12
E12
F12
H12
L12
U12
N13
U13
A14
P14
G15
H15
T15
U15
G16
R16
U16
D17
F17
J17
M17
N17
R17
T17
E6
M6
U6
E7
R7
T7
A8
E8
M8
R8
E9
U9
E10
E11
M11
C
B
A
PPVREF_S3_MEM_VREFCA
23 76
PPVREF_S3_MEM_VREFDQ_B
23 76
78
78
R2500
243
1%
1/20W
MF
201
NC
NC
NC
NC
NC
NC
1
2
D16T12
D15R12
E2B11
J1A10
H17U8
A17A1
U17U1
D8
M9
C11
D11
C2531
0.047UF
NC
NC
NC
NC
NC
6.3V
BI
BI
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_ZQ_B MEM_B_ZQ_A
DQS3_T_A
DQS3_C_A
ZQ_A
VREFCA_A
VREFDQ_A
E3
E4
H4
J12
NC
NC
NC
NC
NC
NC
1
C2512
0.1UF
10%
6.3V
2
CERM-X5R
0201
NC
NC
MEM_B_ZQ1_A
NC
NC
RAM_16GB
1
2
1
R2521
243
1%
1/20W
MF
201
2
C2510
0.047UF
10%
6.3V
X5R
201
1
2
1
2
NC
C2511
0.047UF
10%
6.3V
X5R
201
DQS3_T_B
DQS3_C_B
ZQ_B
VREFCA_B
VREFDQ_B
C2532
0.1UF
10%
6.3V
CERM-X5R
0201
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
1
C2530
0.047UF
10%
6.3V
2
X5R
201
10%
X5R
201
1
2
MEM_B_ZQ1_B
RAM_16GB
R2501
243
1/20W
1%
MF
201
78
BI
78
BI
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ_B
1
2
1
R2520
243
1%
1/20W
MF
201
2
23 76
23 76
PAGE TITLE
SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB
LPDDR3 DRAM Channel B (0-63)
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04039
REVISION
A
2.0.0
BRANCH
PAGE
25 OF 145
SHEET
23 OF 85
BOM_COST_GROUP=DRAM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
67
35 4
2
1
678
3 245
1
D
C
Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK
PP0V6_S0_DDRVTT
76
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
22 7
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
MEM_A_CAA<9>
MEM_A_CAA<8>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<5>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_CAA<4>
MEM_A_CAA<3>
MEM_A_CAA<2>
MEM_A_CAA<1>
MEM_A_CAA<0>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<5>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_CAB<4>
MEM_A_CAB<2>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730
68
68
68
68
68
38.3
38.3
80.6
80.6
68
68
68
68
68
68
68
68
68
68
38.3
38.3
80.6
80.6
68
68
68
68
68
80.6
80.6
80.6
21
21
21
21
21
21
1% 1/32W TK01005
21
1% 1/32W TK01005
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
1% 1/32W MF
21
21
TK010051/32W1%
TK010051/32W1%
TK1% 010051/32W
TK010051/32W1%
TK1/32W 010051%
010051% 1/32W MF
MF010051% 1/32W
TK010051% 1/32W
TK010051% 1/32W
TK1% 1/32W 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
01005 TK1/32W1%
01005 TK1/32W1%
MF1/32W1% 01005
010051% 1/32W MF
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
01005
010051% 1/32W MF
010051% 1/32W MF
1
C2700
0.47UF
2
1
C2701
0.47UF
2
1
C2703
0.47UF
2
1
C2705
0.47UF
2
1
C2707
0.47UF
2
1
C2709
0.47UF
2
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
1
C2730
12PF
5%
25V
2
NP0-C0G
0201
1
C2702
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2704
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2706
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2708
0.47UF
20%
4V
2
CERM-X5R-1
201
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
23 7
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<4>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_CAB<4>
MEM_B_CAB<2>
MEM_B_CAB<3>MEM_A_CAB<3>
MEM_B_CAB<1>
MEM_B_CAB<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770
68
68
68
68
68
38.3
38.3
80.6
80.6
68
68
68
68
68
68
68
68
68
68
38.3
38.3
80.6
80.6
68
68
68
68
68
80.6
80.6
80.6
PP0V6_S0_DDRVTT
76
21
21
21
21
21
21
1% 1/32W TK01005
21
1% 1/32W TK01005
21
21
21
21
21
21
21
21
21
21
21
21
21
1% 1/32W TK01005
21
1% 1/32W TK01005
21
21
21
21
21
21
21
21
21
21
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK010051% 1/32W
010051% 1/32W MF
010051% 1/32W MF
TK010051% 1/32W
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
010051% 1/32W MF
010051% 1/32W MF
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
MF1/32W1% 01005
MF1/32W1% 01005
010051% 1/32W MF
1
C2710
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2711
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2713
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2715
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2717
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2719
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2731
12PF
5%
25V
2
NP0-C0G
0201
1
C2712
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2714
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2716
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C2718
0.47UF
20%
4V
2
CERM-X5R-1
201
D
C
B
CRITICAL
1
C2720
20UF
20%
6.3V
2
CERM-X5R
0402
1
C2722
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
CRITICAL
1
C2740
20UF
20%
6.3V
2
CERM-X5R
0402
1
C2742
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
B
A
8
SYNC_MASTER=T290_CARD_CPU_U SYNC_DATE=04/06/2018
PAGE TITLE
A
LPDDR3 DRAM Termination
DRAWING NUMBER
051-04039
Apple Inc.
REVISION
2.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DRAM
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
27 OF 145
SHEET
24 OF 85
1
SIZE
D
678
3 245
1
D
C
B
A
1
R2890
3.3K
5%
1/20W
MF
201
2
PP3V3_TBT_X_SX
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
TBT_X_SPI_CLK
27
TBT_X_SPI_CS_L
27
TBT_X_ROM_WP_L
25
TBT_X_ROM_HOLD_L
DP_X_SNK1_ML_C_P<0>
IN
DP_X_SNK1_ML_C_N<0>
IN
DP_X_SNK1_ML_C_P<1>
IN
DP_X_SNK1_ML_C_N<1>
IN
DP_X_SNK1_ML_C_P<2>
IN
DP_X_SNK1_ML_C_N<2>
IN
DP_X_SNK1_ML_C_P<3>
IN
DP_X_SNK1_ML_C_N<3>
IN
BI
BI
BI
BI
DP_X_SNK1_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
DP_X_SNK0_ML_C_P<0>
IN
DP_X_SNK0_ML_C_N<0>
IN
DP_X_SNK0_ML_C_P<1>
IN
DP_X_SNK0_ML_C_N<1>
IN
DP_X_SNK0_ML_C_P<2>
IN
DP_X_SNK0_ML_C_N<2>
IN
DP_X_SNK0_ML_C_P<3>
IN
DP_X_SNK0_ML_C_N<3>
IN
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N
100K
10K
100K
100K
100K
100K
100K
100K
21
21
21
21
21
21
21
21
R2866
R2864
R2863
R2865
R2860
R2870
R2862
R2872
R2891
3.3K
MF
1
5%
1/20W
MF
201
2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
2011/20W5%
NOSTUFF
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
PP3V3_UPC_XB_LDO
1
R2893
3.3K
5%
1/20W
MF
201
2
8
VCC
U2890
8MBIT-3.0V
W25Q80DVUXIE
6
CLK
1
CS*
3
WP*(IO2)
7
HOLD*(IO3)
USON
OMIT_TABLE
CRITICAL
GND EPAD
9
4
SNK1 AC Coupling
C2820
0.22UF
C2821
0.22UF
C2822
0.22UF
C2823
0.22UF
C2824
0.22UF
C2825
0.22UF
C2826
0.22UF
C2827
0.22UF
C2828
0.1UF
C2829
0.1UF
SNK0 AC Coupling
C2830
0.22UF
C2831
0.22UF
C2832
0.22UF
C2833
0.22UF
C2834
0.22UF
C2835
0.22UF
C2836
0.22UF
C2837
0.22UF
C2838
0.1UF
C2839
0.1UF
67 27 26 25
TBT_X_BATLOW_L
TBT_X_TMU_CLK_IN
TBT_X_TMU_CLK_OUT
TBT_XA_USB2_MXCTL
TBT_XB_USB2_MXCTL
DP_XA_HPD
DP_XB_HPD
R2892
3.3K
5%
1/20W
MF
201
DI(IO0)
DO(IO1)
21
21
20%
X5R
21
X5R 0201
21
21
20%
21
21
21
X5R
21
0201 CERM-X5R
21
0201
21
X5R
21
20%
X5R
21
20%
X5R
21
20%
X5R
21
20%
X5R
21
X5R
21
X5R
21
21
0201 CERM-X5R
21
0201
25
25
25
25
25
25 28
25 29
5
2
6.3V20%
0201X5R
6.3V
0201
6.3V20%
6.3V20%
0201X5R
6.3V
0201X5R
6.3V20%
0201X5R
6.3V20%
0201X5R
6.3V20%
0201
6.3V10%
6.3V10%
CERM-X5R
6.3V20%
0201
6.3V
0201
6.3V
0201
6.3V
0201
6.3V
0201
6.3V20%
0201
6.3V20%
0201
6.3V20%
0201X5R
6.3V10%
6.3V10%
CERM-X5R
27
1
2
1
C2890
1UF
10%
10V
2
X5R
402-1
TBT_X_SPI_MOSI
TBT_X_SPI_MISO
DP_X_SNK1_ML_P<0>
DP_X_SNK1_ML_N<0>
DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<1>
DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<3>
DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_N
DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_N<0>
DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_P<2>
DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<3>
DP_X_SNK0_AUXCH_P
DP_X_SNK0_AUXCH_N
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
27
27
PCIE_TBT_X_R2D_P<0>
IN
PCIE_TBT_X_R2D_N<0>
IN
PCIE_TBT_X_R2D_P<1>
IN
PCIE_TBT_X_R2D_N<1>
IN
PCIE_TBT_X_R2D_P<2>
IN
PCIE_TBT_X_R2D_N<2>
IN
PCIE_TBT_X_R2D_P<3>
IN
PCIE_TBT_X_R2D_N<3>
IN
PCIE_CLK100M_TBT_X_P
IN
PCIE_CLK100M_TBT_X_N
IN
TBT_X_CLKREQ_R_L
DP_X_SNK0_ML_P<0>
25
DP_X_SNK0_ML_N<0>
25
DP_X_SNK0_ML_P<1>
25
DP_X_SNK0_ML_N<1>
25
DP_X_SNK0_ML_P<2>
25
DP_X_SNK0_ML_N<2>
25
DP_X_SNK0_ML_P<3>
25
DP_X_SNK0_ML_N<3>
25
DP_X_SNK0_AUXCH_P
25
DP_X_SNK0_AUXCH_N
25
DP_X_SNK0_HPD
DP_X_SNK1_ML_P<0>
25
DP_X_SNK1_ML_N<0>
25
DP_X_SNK1_ML_P<1>
25
DP_X_SNK1_ML_N<1>
25
DP_X_SNK1_ML_P<2>
25
DP_X_SNK1_ML_N<2>
25
DP_X_SNK1_ML_P<3>
25
DP_X_SNK1_ML_N<3>
25
DP_X_SNK1_AUXCH_P
25
DP_X_SNK1_AUXCH_N
25
DP_X_SNK1_HPD
IN
IN
IN
OUT
JTAG_ISP_TDI
JTAG_TBT_X_TMS
JTAG_ISP_TCK
JTAG_ISP_TDO
NC
NC
NC
NC
20
TBT_X_CLKREQ_L
OUT
<rdar://problem/42880020>
27
OUT
R2830
100K
1/20W
201
27
OUT
R2831
100K
1/20W
201
5%
MF
5%
MF
R2828
1
2
1
2
100
5%
1/20W
MF
201
27
27
27
27
27
27
27
27
16
16
21
14
14 27
14
14
TBT_X_TEST_EN
TBT_X_TEST_PWR_GOOD
100
5%
1/20W
MF
201
5%
1/20W
MF
201
1
2
1
2
30
30
30
30
30
30
30
30
28
28
25 28
IN
IN
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
USBC_XA_D2R_P<2>
USBC_XA_D2R_N<2>
USBC_XA_R2D_CR_P<2>
USBC_XA_R2D_CR_N<2>
USBC_XA_R2D_CR_P<1>
USBC_XA_R2D_CR_N<1>
USBC_XA_D2R_P<1>
USBC_XA_D2R_N<1>
USBC_XA_AUXLSX1
USBC_XA_AUXLSX2
NC
NC
DP_XA_HPD
I2C_TBT_XA_INT_L
TBT_XA_USB2_MXCTL
25
67 27 26 25
100
5%
1/20W
MF
201
1
2
R2825
PP3V3_TBT_X_SX
NOSTUFF
R2829
R2836
2.2K
27 27
TBT_XA_USB2_RBIAS
PLACE_NEAR=U2800.H19:2MM
200
1%
1/20W
MF
201
1
TBT_X_RBIAS
2
TF 1/20W
R2855
PLACE_NEAR=U2800.H6:2MM
PLACE_NEAR=U2800.J6:2MM
21
TBT_X_RSENSE
4.75K
0.5%
0201
R2854
Y23
Y22
T23
T22
M23
M22
H23
H22
V19
T19
AC7
AB7
AB9
AC9
AC11
AB11
AB13
AC13
N1
N2
AA2
A5
B5
B3
A3
C2
C1
E2
E1
P1
P2
Y4
AC5
AB5
AC3
AB3
W20
Y20
W19
Y19
R4
W5
A15
B15
A17
B17
A19
B19
B21
A21
H4
J4
E20
D20
T2
M4
R2
H19
J6
J5
A23
A1
AC23
AC1
D4
L8
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*
DPSNK1_ML0_P
DPSNK1_ML0_N
DPSNK1_ML1_P
DPSNK1_ML1_N
DPSNK1_ML2_P
DPSNK1_ML2_N
DPSNK1_ML3_P
DPSNK1_ML3_N
DPSNK1_AUX_P
DPSNK1_AUX_N
SNK1_HPD
DPSNK2_ML0_P
DPSNK2_ML0_N
DPSNK2_ML1_P
DPSNK2_ML1_N
DPSNK2_ML2_P
DPSNK2_ML2_N
DPSNK2_ML3_P
DPSNK2_ML3_N
DPSNK2_AUX_P
DPSNK2_AUX_N
SNK2_HPD
U0_SSTXP1
U0_SSTXN1
U0_SSRXP1
U0_SSRXN1
TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD
ASSRXP2
ASSRXN2
ASSTXP2
ASSTXN2
ASSTXP1
ASSTXN1
ASSRXP1
ASSRXN1
ASBU1
ASBU2
PA_USB2_D_P
PA_USB2_D_N
PA_HPD
PA_I2C_INT
PA_USB2_MXCTL
PA_USB2_RBIAS
RBIAS
RSENSE
PA_MONDC
PB_MONDC
PC_MONDC
USB_MONDC
TEST_EDM
FUSE_VQPS_64
U2800
TITAN-RIDGE-DP
CSP
SYM 1 OF 2
OMIT_TABLE
CRITICAL
PCIE GEN3
SINK PORT 1SINK PORT 2
USBSSJTAG
TBT PORT A
DEBUG
SOURCE PORT
LC GPIOPOC GPIOFLASH
TBT PORT B
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PERST*
PCIE_RBIAS
DPSRC_ML0_P
DPSRC_ML0_N
DPSRC_ML1_P
DPSRC_ML1_N
DPSRC_ML2_P
DPSRC_ML2_N
DPSRC_ML3_P
DPSRC_ML3_N
DPSRC_AUX_P
DPSRC_AUX_N
DPSRC_HPD
GPIO_0
GPIO_1
EE_WP*
TMU_CLKOUT
WAKE*
CIO_PLUG_EVENT*
TMU_CLKIN
I2C_SCL
I2C_SDA
USB_FORCE_PWR
FORCE_PWR
BATLOW*
SLP_S3*
RTD3_PWR_EN
RESET*
XTAL_25_IN
XTAL_25_OUT
EE_DI
EE_DO
EE_CS*
EE_CLK
BSSRXp2
BSSRXn2
BSSTXp2
BSSTXn2
BSSTXp1
BSSTXn1
BSSRXp1
BSSRXn1
BSBU1
BSBU2
PB_USB2_D_P
PB_USB2_D_N
PB_HPD
PB_I2C_INT
PB_USB2_MXCTL
PB_USB2_RBIAS
USB2_ATEST
PCIE_ATEST
MONDC_SVR
VGA_RES
ATEST_P
ATEST_N
THERMDA
V23
V22
P23
P22
K23
K22
F23
F22
T4
N16Y6
AB21
AC21
AC19
AB19
AB17
AC17
AC15
AB15
N4
N5
R5
W1
W2
W4
Y1
Y2
AA1
W6
V2
V1
V5
V4
U2
U1
T5
E5
D22
D23
Y18
W16
W18
Y16
B7
A7
A9
B9
A11
B11
A13
B13
L4
L5
E19
D19
T1
M5
R1
F19
B23
AB23
D5
H5
J9
J11
V8
PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>
PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>
TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS
NC_DP_X_SRC_MLP<0>
NC_DP_X_SRC_MLN<0>
NC_DP_X_SRC_MLP<1>
NC_DP_X_SRC_MLN<1>
NC_DP_X_SRC_MLP<2>
NC_DP_X_SRC_MLN<2>
NC_DP_X_SRC_MLP<3>
NC_DP_X_SRC_MLN<3>
NC_DP_X_SRC_AUXP
NC_DP_X_SRC_AUXN
PD_DP_X_SRC_HPD
PD_TBT_X_GPIO_0
PU_TBT_X_GPIO_1
TBT_X_ROM_WP_L
TBT_X_TMU_CLK_OUT
TBT_WAKE_3V3_L
TBT_X_PLUG_EVENT_L
TBT_X_TMU_CLK_IN
I2C_TBT_X_SCL
I2C_TBT_X_SDA
TBT_X_USB_PWR_EN
TBT_X_CIO_PWR_EN
TBT_X_BATLOW_L
PM_SLP_S3_L
RTD3_PWR_EN
USBC_X_RESET_L
TBT_X_XTAL25M_IN
TBT_X_XTAL25M_OUT
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK
USBC_XB_D2R_P<2>
USBC_XB_D2R_N<2>
USBC_XB_R2D_CR_P<2>
USBC_XB_R2D_CR_N<2>
USBC_XB_R2D_CR_P<1>
USBC_XB_R2D_CR_N<1>
USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>
USBC_XB_AUXLSX1
USBC_XB_AUXLSX2
NC
NC
DP_XB_HPD
I2C_TBT_XB_INT_L
TBT_XB_USB2_MXCTL
TBT_XB_USB2_RBIAS
NC
NC
NC
NC
NC
TBT_X_THERM_D_P
USE NEAREST GND BALL
(XXXX) FOR THERM_D_N
PU at PCH
PU at PCH
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
27
OUT
OUT
25
25
OUT
OUT
25
IN
IN
25
IN
IN
IN
OUT
27
27
27
27
IN
IN
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
25
OUT
27
27
27
27
27
27
27
27
14 27
1
27
27
27
27
27
27
27
27
27
27
27
27
27
5 27
14 27 28 29
14 27 28 29
5 14 15 20 79
27
27
27
To SPI Flash
30
30
30
30
30
30
30
30
29
29
25 29
SYNC_MASTER=X1032_MLB_P4BP
PAGE TITLE
50
2
1
2
PP3V3_TBT_X_SX
1
2
1
2
R2851
3.01K
1%
1/20W
MF
201
PP3V3_TBT_X_SX
R2834
2.2K
5%
1/20W
MF
201
27
BI
R2837
2.2K
5%
1/20W
MF
201
PLACE_NEAR=U2800.F19:2MM
1
R2835
2.2K
5%
1/20W
MF
201
2
BI
NOSTUFF
27
ININ
R2853
200
1%
1/20W
MF
201
USB-C HIGH SPEED 1
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TBT
IV ALL RIGHTS RESERVED
1
R2827
100K
5%
1/20W
MF
201
2
67 27 26 25
DRAWING NUMBER
051-04039
REVISION
BRANCH
PAGE
28 OF 145
SHEET
25 OF 85
67 27 26 25
SYNC_DATE=02/13/2017
2.0.0
D
C
B
A
SIZE
D
8
67
35 4
2
1
678
3 245
1
D
C
B
A
26
PP0V9_TBT_X_SVR
1
C2930
1.0UF
20%
6.3V
2
X5R
0201-1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
SOURCED BY
INTERNAL SWITCH INTERNAL SWITCH INTERNAL SWITCH
1
C2984
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2931
1.0UF
20%
6.3V
2
X5R
1
C2932
1.0UF
20%
6.3V
2
X5R
0201-10201-1
1
C2964
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2985
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2933
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2965
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2934
1.0UF
20%
6.3V
2
X5R
0201-1
SOURCED BY INTERNAL SWITCH
1
C2966
1.0UF
20%
6.3V
2
X5R
0201-1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
1
C2920
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2935
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2967
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2936
1.0UF
20%
6.3V
2
X5R
0201-1
PP0V9_TBT_X_PCIE
1
C2968
10UF
20%
6.3V
2
CERM
0402
PP3V3_TBT_X_ANA
27
27
PP3V3_TBT_X_ANA_PCIE
PP3V3_TBT_X_ANA_USB2
SOURCED BYSOURCED BY
1
C2921
1.0UF
20%
6.3V
2
X5R
0201-1
MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
H11
H9
H12
H13
H15
H16
T12
T13
T15
N6
T11
T9
E8
J18
L19
M19
L18
M18
M16
E16
L16
H18
W11
Y11
Y5
W12
Y12
Y8
AB4
AC4
C23
C22
W13
AB2
D6
W15
Y15
A4
B4
F2
D2
F1
D1
B1
B2
E18
V11
V12
V13
M6
N19
N18
E12
E13
F11
F12
F13
F15
J16
A2
F8
A6
A8
B8
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
B10
AC10
AC12
AC14
AC16
AC18
AC20
AC22
B12
B14
B16
B18
B20
B22
D8
D9
A10
D11
D12
VCC0P9_SVR_PAB_ANA
VCC0P9_SVR_PC_ANA
VCC0P9_SVR_DPAUX_ANA
VCC0P9_SVR_USB_ANA
VCC0P9_SVR_BRD_SENSE
VCC0P9_PCIE
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_2
VCC3P3_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS
N15
VSS
L15
V18
VSS
VSS
F4
VSS
R9
U2800
TITAN-RIDGE-DP
CSP
SYM 2 OF 2
OMIT_TABLE
CRITICAL
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M9
L9
R12
L12
M15
R15
VSS
M1
VCC3P3_SVR
VCC0P9_SVR
VCC0P9_LVR_SENSE
VSS
VSS
VSS
VSS
V16
M12
N9
N12
M2
VCC3P3_LC
VCC3P3_SX
VCC3P3_S0
VCC3P3A
SVR_IND
SVR_VSS
VCC0P9_LC
VCC0P9_LVR
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
T6
T18
V6
F18
R6
L6
E6
G1
G2
H2
R8
R11
L11
M8
M13
R16
R13
J13
L13
N8
N11
N13
T8
T16
M11
L1
L2
K1
K2
J1
J2
H1
J8
H8
H6
D13
D15
D16
D18
E9
E11
E15
A12
E22
E23
F9
F20
F16
G22
G23
A14
H20
J19
J20
J22
A16
J23
L20
L22
L23
A18
M20
N20
N22
N23
R18
A20
R19
R20
R22
R23
T20
U23
U22
A22
V9
V15
V20
W8
B6
W9
W22
W23
Y9
Y13
AA22
AA23
AB6
E4
J15
AB1
AC2
F5
F6
J12
PP3V3_TBT_X_LC
PP3V3_TBT_X_SX
27
PP3V3_TBT_X_F
CRITICAL
1
C2975
10UF
20%
6.3V
2
CERM
0402
BYPASS=U2800.G2:J1:3MM
26
PP0V9_TBT_X_SVR
MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.9V
DIDT=TRUE
SWITCH_NODE=TRUE
VR0V9_IND_TBT_X
PP0V9_TBT_X_LC
PP0V9_TBT_X_LVR
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.9V
on support page
XW2900
SM
PLACE_NEAR=U2800.V9:2MM
NO_XNET_CONNECTION=1
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
1
C2991
1.0UF
20%
6.3V
2
X5R 0201-1
0201-1
CRITICAL
1
C2976
10UF
20%
6.3V
2
CERM
0402
CRITICAL
1
C2977
10UF
20%
6.3V
2
CERM
0402
CRITICAL
L2950
0.68UH-20%-6.1A-0.020OHM
21
1210
27
XW
21
TBT_X_THERM_D_N
NOSTUFF
C2990
1.0UF
20%
6.3V
X5R
1
2
C2994
CER-X5R
CRITICAL
1
C2978
10UF
20%
6.3V
2
CERM
0402
1
C2917
12PF
5%
25V
2
CERM
0201
INTERNAL SWITCHING VR OUTPUT
CRITICAL
1
C2950
47UF
20%
6.3V
2
CER-X5R
0603
SOURCED BY INTERNAL SWITCH
1
C2992
1.0UF
20%
6.3V
2
X5R
0201-1
P0V9_TBT_X_SVR_AGND
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V
50
OUT
NOSTUFF
47UF
20%
6.3V
0603
1
2
1
C2910
1.0UF
20%
6.3V
2
X5R
0201-1
C2995
47UF
20%
6.3V
CER-X5R
0603
1
2
CRITICAL
1
C2951
47UF
20%
6.3V
2
CER-X5R
0603
1
C2993
1.0UF
20%
6.3V
2
X5R
0201-1
2x 10uF outside BGA area
1
2
1
2
BOM_COST_GROUP=TBT
1
2
C2911
1.0UF
20%
6.3V
X5R
0201-1
CRITICAL
C2952
47UF
20%
6.3V
CER-X5R
0603
CRITICAL
C2954
10UF
20%
6.3V
CERM
0402
0
21
5%
1/10W
MF-LF
603
L2990
1
C2912
1.0UF
20%
6.3V
2
X5R
0201-1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.9V
CRITICAL
1
C2955
10UF
20%
6.3V
2
CERM
0402
1
2
VOLTAGE=3.3V
1
C2981
1.0UF
20%
6.3V
2
X5R
0201-1
PP3V3_TBT_X_S0
C2913
1.0UF
20%
6.3V
X5R
0201-1
SYNC_MASTER=X1032_MLB_P4BP
PAGE TITLE
1
2
1
2
MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000
FROM USB-C PORT
CONTROLLER (UPC)
1
C2983
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2914
1.0UF
20%
6.3V
X5R
0201-1
C2915
1.0UF
20%
6.3V
2
X5R
0201-1
C2982
1.0UF
20%
6.3V
X5R
0201-1
ISOLATE GND OF SVR_IND CAPS
AND GND OF VCC3P3_SVR CAPS
FROM SYSTEM GND IN LAYOUT
(SEE INTEL LAYOUT GUIDELINES)
27 76
USB-C HIGH SPEED 2
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
25 27 67
1
C2916
1.0UF
20%
6.3V
2
X5R
0201-1
1
C2980
1.0UF
20%
6.3V
2
X5R
0201-1
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
SOURCED BYSOURCED BY INTERNAL SWITCH
INTERNAL SWITCH
27
SYNC_DATE=02/13/2017
051-04039
2.0.0
29 OF 145
26 OF 85
D
C
B
A
SIZE
D
8
67
35 4
2
1
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