Apple X1032 Book

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X1032 MLB BTTF

LAST_MODIFICATION=Thu Aug 9 14:09:34 2018

LAST_MODIFICATION=Thu Aug 9 14:09:34 2018

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2018-08-0900134733492 ENGINEERING RELEASED

D

1
2
3

1
2
3
44

5

5

6 6

7
8
9
10
11
12
13

8

9

10 03/30/2018

11

12

13

Table of Contents
BOM Configuration
BOM Configuration
PD Parts
CPU GFX
CPU Misc/JTAG/CFG/RSVD
CPU LPDDR3 Interface7
CPU Power
PCH Power
CPU & PCH Grounds
CPU Decoupling 1
CPU Decoupling 2
PCH Decoupling

J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB
J122_MLB

DATESYNCCONTENTSCSAPAGE

03/30/2018
03/30/2018
03/30/2018
03/30/2018
03/30/2018

03/30/2018
03/30/2018
03/30/2018

51
52

60
61

Fans
RIO Connector
Audio Speaker Amplifiers

54 66 Audio Connectors

67

68 02/16/2017
57
58
59
60
61

69

70

71

72

74
62 76
63

78 PMIC BUCKS AND SWs

Keyboard & Trackpad 155
Keyboard & Trackpad 256
DC-In & Battery Connectors
PBUS Supply & Battery Charger
CPU IMVP8 Regulator IC
CPU VCore/VccSA Power Stage
CPU VccGT Power Stage
VR - 5V, 3V3

X1032_MLB_P4BP

AHAAGE_AUD53 64
AHAAGE_AUD
X260_MLB
X589_CARD_IPD
X589_BIGSUR
X1032_MLB_P4BP
J122_MLB
J122_MLB
J122_MLB
X589_BIGSUR
X589_BIGSUR

DATESYNCCONTENTSCSAPAGE

02/13/2017

05/23/2017
04/19/2017
02/16/2017

02/15/2017
02/13/2017
03/30/2018
03/30/2018
03/30/2018
03/01/2017
03/16/2017

D

C

14
15
16
17

19

21
22
23
24
25
26
27

14 PCH Audio/LPC/SPI/SMBus
15 PCH Power Management
16
17
1818
19
2020
22
23
25
27
28
29
30

PCH PCIe/USB/CLK
PCH GPIO/LPSS
CPU/PCH Merged XDP
Chipset Shared Support
Chipset Project Support
LPDDR3 VREF MARGINING 03/30/2018
LPDDR3 DRAM Channel A (0-63)
LPDDR3 DRAM Channel B (0-63)
LPDDR3 DRAM Termination
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2
USB-C SUPPORT

J122_MLB
J122_MLB
J122_MLB 03/30/2018
J122_MLB
X589_CPU_CNL_Y
X589_CPU_CNL_Y
X589_CPU_CNL_Y
J122_MLB
J122_MLB
J122_MLB
T290_CARD_CPU_U
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP

03/30/2018
03/30/2018

03/30/2018
03/13/2017
03/27/2017
03/07/2017

03/30/2018
03/30/2018
04/06/2018
02/13/2017
02/13/2017
02/13/2017

64
65

79

PMIC LDOs
PMIC GPIOs & Control80
POWER - VDDQ, VCCIO81
Power FETs
LCD Backlight Driver84
eDP Display Connector

68
69

8267

85

S4E<0>86
71
72 S4E<2>
73 02/13/2017
74
75 02/21/2017
76
77

87 S4E<1>
88
90
91

NAND VCC VR

SSD Support

Power Aliases - 1120

121
122

Power Aliases - 2

Signal Aliases

X589_BIGSUR
X589_BIGSUR
X589_CPU_CNL_Y66
X589_CPU_CNL_Y
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032_MLB_P4BP
X1032

X589_CPU_CNL_Y
X589_CPU_CNL_Y

03/16/2017
03/16/2017
03/08/2017
02/22/2017
02/13/2017
02/13/2017
02/13/201770
02/13/2017
02/14/2017

02/21/2017

C

B

28
29
30
31
32
33
34
35
36
37
38
39

31
32
33
34
37
38
39
40
41
42 X589_BIGSUR
43

44
40 45
41

46

USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR
USB-C SUPPORT 2
WIFI/BT MODULE
WIFI/BT Module Support
SoC GPIO/SEP/USB/DDR/Test
SoC AOP/AON/SMC
SoC ISP/I2C/UART/SPI/I2S
SoC PCIe
SoC Power 1
SoC Power 2
SoC Power 3
SoC Ground

X1032_MLB_P4BP

X1032_MLB_P4BP
X1032_MLB_P4BP
MKARAKUCUK
X1032_MLB_P4BP
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR

X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR

02/13/2017

02/13/2017
02/13/2017
03/22/2017
03/03/2017
03/15/2017
03/16/2017
03/15/2017
03/15/2017
02/13/2017
02/13/2017
02/13/2017
02/13/2017

78
79
80
81

123
124
127 Desense Caps 1

128
82 140 04/12/2017
83 BOM Variants 1
84

141

142
85 145

Memory Signal Swaps
ICT FCT

Desense Caps 2
Dev Support

BOM Variants 2
BOM Alternates

J122_MLB

X589_BIGSUR

04/13/2018

B

A

1 SCH CRITICAL SCHEM051-04039 SCH,MLB_BTTF,X1032

1 MLB CRITICAL PCBF820-01521 PCBF,MLB_BTTF,X1032

42
43
44
45
46
47
48
49
50

47
48
50

53
54
55
56
58

SoC Shared Support
SoC Project Support
Secure Element
I2C Connections 152

Power Sensors High Side
Power Sensors Load Side
Power Sensors Extended
Thermal Sensors

X589_BIGSUR
X589_BIGSUR
X941_MLB
X589_BIGSUR
X589_BIGSUR
X1032_MLB_P4BP
X1032_MLB_P4BP

X1032_MLB_P4BP

03/16/2017
02/13/2017
03/10/2017
02/13/2017
02/13/2017I2C Connections 2
02/14/2017
02/14/2017

02/14/2017

DRAWING TITLE

A

SYNC_DATE=07/25/2017SYNC_MASTER=CONSTRAINTS_ML

SCHEM,MLB-BTTF,X1032

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

051-04039

REVISION

2.0.0

BRANCH

PAGE

1 OF 145

SHEET

1 OF 85

SIZEDRAWING NUMBER

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3

124567

678

3 245

1

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Module Parts

CPU TBT ROMNAND

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REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1

CPU,AML-Y,QQQE,PQS,1.8,1.15,BGA1515

337S00593 CPU_AMLY:QQQF

337S00614

337S00615 CRITICAL

998-15364 CRITICAL1

CPU,AML-Y,QQQF,PQS,1.6,1.05,BGA1515

CPU,AML-Y,QQQG,PQS,1.6,1.05,BGA1515

CPU,AML-Y,QQQM,PQS,H0,1.8,7W,1.15,B1515

CPU,AML-Y,QQQN,PQS,H0,1.6,7W,1.1,B1515

CPU,AML-Y,QQQP,PQS,H0,1.6,7W,1.05,B1515

1 U0500 CPU_AMLY:QQQQ337S00621 CRITICAL

CPU,AML-Y,QQQQ,PQS,H0,1.8,7W,1.15,B1515

1 U0500 CRITICAL337S00622

CPU,AML-Y,QQQR,PQS,H0,1.6,7W,1.1,B1515

CPU,AML-Y,QQQS,PQS,H0,1.6,7W,1.05,B1515

1 CRITICALU0500337S00623

CPU,AML-Y,SREKN,PRQ,1.8,7W,1.15,BGA1515

1 CRITICALU0500337S00624

CPU,AML-Y,SREKP,PRQ,1.6,7W,1.1,BGA1515

1 CRITICALU0500337S00625

CPU,AML-Y,SREKQ,PRQ,1.6,7W,1.05,BGA1515

INTERPOSER,VRTT ADAPTER,KBL-Y,BGA1515

CRITICALU05001

CRITICAL1337S00626 U0500

TBT Titan Ridge

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

338S00305

338S00356 TBT_TR:B01

338S00408 CRITICAL1 U2800

IC,TBT,TITAN RIDGE,QTJE,P-ES,A0,CSP337

IC,TBT,TITAN RIDGE DP,QTZZ,ES2,B0,CSP337

IC,TBT,TITAN RIDGE DP,QTZZ,ES2,C0,CSP337

1 U2800 TBT_TR:C0338S00399 CRITICAL

IC,TBT,TITAN RIDGE DP,QUJK,QS,C1,CSP337

IC,TBT,TITANRIDGE DP,SLMHS,PRQ,C1,CSP337

1338S00441

U28001 TBT_TR:A0CRITICAL

U2800 CRITICAL

U2800 CRITICAL TBT_TR:PRQ

Ace

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96

IC,CD3215,ACE,C00,USB PWRSW,BLNK,NFBGA96

CRITICAL

CRITICAL353S01442 U3100,U32002

Wireless

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

MODULE,WIFI,YEBISU CIDRE,U,ES4.8,LGA160

PART NUMBER

339S00446 339S00448 Murata ModuleALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CRITICAL WIRELESS:USI1 U3700339S00448

TABLE_ALT_HEAD

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

CPU_AMLY:QQQECRITICALU0500337S00592

CPU_AMLY:QQQG337S00594 CRITICALU05001

CPU_AMLY:QQQMCRITICALU05001337S00613

CPU_AMLY:QQQNCRITICALU05001

CPU_AMLY:QQQP1 U0500

CPU_AMLY:QQQR

CPU_AMLY:QQQS

CPU_AMLY:SREKN

CPU_AMLY:SREKP

CPU_AMLY:SREKQ

CPU_AMLY:INTERPOSERU0500

BOM OPTIONCRITICAL

TBT_TR:C1

BOM OPTIONCRITICAL

ACE:C0_BGA353S00961 2 U3100,U3200

ACE:C0_NFBGA

BOM OPTIONCRITICAL

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335S00273 2 CRITICAL

335S00289 NAND:PMLC_128G_TO

335S00301 U8600,U8700,U88003 NAND:PMLC_128G_SD

335S00302 U8600,U8700,U8800 CRITICAL3

335S00292 NAND:PMLC_512G_TO3 U8600,U8700,U8800 CRITICAL

998-12416

335S00323 3 CRITICALU8600,U8700,U8800 NAND:PMLC_128G_SD_NM

998-12418 U8600,U8700,U8800 NAND:PMLC_256G_TO_NM

998-12423 ALL998-12422 TO 512G Substrate 2

335S00326 3 CRITICAL

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,1Z,128GBM,S4E,128G,SD,HPN1,ULGA110

NAND,3DV3,42GBP,XXX,S4E,170G,T,ULGA110

3 CRITICALU8600,U8700,U8800

NAND,3DV3,42GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,85GBP,XXX,S4E,170G,T,ULGA110

NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,170GBP,XXX,S4E,170G,T,ULGA110

NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,42GBP,S4E,170G,T,SUB X,ULGA110

PART NUMBER

NAND:PMLC_128G_TO_NM

NAND,3DV3,42GBP,XXX,S4E,170G,SD,ULGA110

3 CRITICAL

NAND,3DV3,85GBP,S4E,170G,T,SUB X,ULGA110

PART NUMBER

NAND:PMLC_256G_TO_NM

3335S00324 CRITICALU8600,U8700,U8800 NAND:PMLC_256G_SD_NM

NAND,3DV3,85GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV3,170GBP,S4E,170G,T,SUBX,ULGA110

3998-12422 CRITICAL

PART NUMBER

NAND:PMLC_512G_TO_NM

NAND,3DV3,170GBP,XXX,S4E,170G,SD,ULGA110

NAND,3DV4,512GBM,S4E,256G,SS,ULGA110

3 CRITICAL335S00322

NAND,3DV4,512GBM,S4E,256G,MG3,SS,ULGA110

U8600,U8700 NAND:HPN1_256G_2L

CRITICAL

U8600,U8700,U8800335S00290 3 CRITICAL

U8600,U8700,U8800 NAND:PMLC_512G_SD

CRITICAL3335S00304

U8600,U8700,U88003 CRITICAL NAND:PMLC_128G_TO_NM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 128G Substrate 2ALL998-12417 998-12416

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

ALL998-12418998-12419

TO 256G Substrate 2

U8600,U8700,U8800 NAND:PMLC_512G_TO_NM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

U8600,U8700,U8800 NAND:PMLC_512G_SD_NM

BOM OPTIONCRITICAL

NAND:PMLC_256G_TO

NAND:PMLC_256G_SD

NAND:3DV4_1P5T_SSU8600,U8700,U8800

NAND:3DV4_1P5T_SS_MG3U8600,U8700,U8800 CRITICAL3335S00373

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Programmables

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8

IC,NVM (V5.7) PROTO-0,X1032

1

IC,NVM (V1.1) NEW,PROTO-0,X1032

IC,NVM (V5.1) PROTO-1,X1032

1

341S00982 1 CRITICALU2890

IC,NVM (VXXX) PROTO-2,X1032

IC,NVM (VXXX) EVT,X1032

1

IC,NVM (VXXX) PROTO-3,X1032

IC,NVM (VXXX) EVT-2,X1032

U2890335S00133 1 CRITICAL TBT_ROM:BLANK

U2890341S00905 CRITICAL TBT_ROM:P0

U28901 CRITICAL341S00922 TBT_ROM:P0_B0

U2890 CRITICAL341S00942 TBT_ROM:P1

U2890

U28901341S01177

BT ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,SPI SERIAL FLASH,2MBIT,1.8V,DFN8

341S00745 BT_ROM:P0CRITICAL1

341S00939 U37701 CRITICAL BT_ROM:P1

341S01176

IC,BT ROM (V4) PROTO-0,X1032

BT SFLASH ROM (V22.33.40) PROTO-1,X1032

1341S00983

BT SFLASH ROM (VXXX) PROTO-2,X1032

1

BT SFLASH ROM (VXXX) EVT,X1032

BT SFLASH ROM (VXXX) EVT-2,X1032

1 U3770 CRITICAL BT_ROM:EVT2

PART NUMBER

U37701

U3770

U3770 CRITICAL341S01042 BT_ROM:EVT

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CRITICAL335S00256 BT_ROM:BLANK

CRITICALU3770 BT_ROM:P2

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ALL MacronixBT_ROM:BLANK335S00256335S00248

TABLE_ALT_ITEM

335S00256 BT_ROM:BLANK ALL335S00255 Adesto

Wifi ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

335S00145 1

341S00744

IC,EEPROM,4KBIT,1.8V,SELECT ORG,TDFN8

WIFI ROM (P101) PROTO-0,WW1,X1032

PART NUMBER

CRITICALU3780 WIFI_ROM:P01

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

ALL335S00236 Rohm335S00145 WIFI_ROM:BLANK

SOC ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,FLASH,SERIAL,SPI,4MX8,1.8V,4X3MM,DFN8

U4770 SOC_ROM:BLANKCRITICAL1335S00203

BOM OPTIONCRITICAL

TBT_ROM:P2

TBT_ROM:EVT1 CRITICAL341S01046

TBT_ROM:P3U2890341S01150 CRITICAL

TBT_ROM:EVT2CRITICAL

BOM OPTIONCRITICAL

BOM OPTIONCRITICAL

WIFI_ROM:BLANKU3780 CRITICAL

BOM OPTIONCRITICAL

TABLE_5_HEAD

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D

C

B

SOC

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

339S00370 1 U3900 SOC:B0_1GCRITICAL

POP,GIBRALTAR+1GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

339S00370 ALL339S00375 Micron 1GB SCKSOC:B0_1G

339S00370 Hynix 1GB ATK339S00376 ALLSOC:B0_1G

POP,GIBRALTAR+2GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

339S00372 SOC:B0_2G339S00378 Hynix 2GB ATKALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ALLSOC:B0_1G Hynix 1GB SCK339S00370339S00371

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ALL339S00372 Hynix 2GB SCKSOC:B0_2G339S00373

Micron 2GB ATK339S00372339S00377 SOC:B0_2G ALL

TABLE_ALT_HEAD

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TABLE_ALT_HEAD

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EFI ROM

TABLE_5_HEAD

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

IC,SERIAL FLASH,128MBIT,1.8V,QE=1,WSON8

1 U2100 EFI_ROM:BLANK335S00371

PART NUMBER

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

MacronixALL335S00370 335S00371

TABLE_ALT_ITEM

335S00371335S00376 AdestoALL

TABLE_5_ITEM

SOC:B0_2G339S00372 CRITICALU39001

BOM OPTIONCRITICAL

TABLE_5_ITEM

B

A

PMU

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P

DRAM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,SDRAM,LPDDR3-1866,32GBIT,20NM,BGA253

2 CRITICAL333S00052 DRAM:SAMSUNG_8GBU2300,U2500

2 CRITICALU2300,U2500333S00130 DRAM:SAMSUNG_16GB

IC,LPDDR3-1866,64GBIT,18NM,S,BGA253

2 U2300,U2500333S00110 CRITICAL DRAM:HYNIX_8GB

IC,LPDDR3-1866,32GBIT,21NM,BGA253

IC,LPDDR3-1866,64GBIT,21NM,BGA253

333S00082 CRITICAL2 DRAM:MICRON_8GB_1866U2300,U2500

IC,LPDDR3-1866,32GBIT,20NM,BGA253

IC,LPDDR3-1866,64GBIT,20NM,M,BGA253

2 CRITICAL333S00113 U2300,U2500 DRAM:MICRON_16GB

IC,LPDDR3-2133,32GBIT,20NM,BGA253

U2300,U25002 CRITICAL333S00111

U2300,U25002 CRITICAL333S00199 DRAM:MICRON_8GB

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

CRITICALU78001 PMU:A0_A338S00267

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BOM OPTIONCRITICAL

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DRAM:HYNIX_16GB

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PAGE TITLE

A

BOM Configuration

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

2 OF 145

SHEET

2 OF 85

8

67

35 4

2

1

678

3 245

1

D

BOM Groups

BOM GROUP BOM OPTIONS

MLB_COMMON

MLB_USBC

MLB_PROGPARTS

SCHEM,PCBF,ALTERNATE,COMMON,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH1,MLB_MECH2,MLB_MISC,PVT

TBT_PCIE_4LANES,TBT_TR:PRQ,ACE:C0_BGA
BT_ROM:EVT2,SOC_ROM:BLANK,TBT_ROM:EVT2,WIFI_ROM:P0,SE:PROD_2017

MLB_POWER PMU:A0_A

WIRELESS:USIMLB_WIRELESS
MLB_MECH1
MLB_MECH2

MLB_MISC

BRACKET,BUSBARLONG,BUSBARTOP,BUSBARBOTTOM

SHLD_CAN_DRAM,SHLD_FNC_NAND,SHLD_CAN_TR,SHLD_FNC_SOC,SHLD_CAN_DPLXR

BOARDID0,BOARDID1,BOARDID2,BOARDID4,SYSDET:FET,NAND_VCC:2V5,BOOTCFG0

See <rdar://problem/39661910> for BOARDID straps

Build Specific Groups

BOM GROUP BOM OPTIONS

PROTO3

PREEVT2

PVT

MAF,EFI_ROM:BLANK

BOARDREV0,SAF,PCHFLTR:FERRITE

BOARDREV1,SAF,PCHFLTR:FERRITE

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

DEV PARTS,MLB_BTTF,X1032 DEV_PARTS_BOMDEV11 CRITICAL985-00733

BOM OPTIONCRITICAL

TABLE_5_ITEM

CMN_PARTS_BOMCOMMON PARTS,MLB_BTTF,X10321 CRITICALCBOM685-00251

TABLE_5_ITEM

D

C

NAND Configs

BOM GROUP BOM OPTIONS

NANDCFG:HPN1_256G_2L
NANDCFG:PMLC_128G_TO
NANDCFG:PMLC_128G_SD
NANDCFG:PMLC_256G_TO
NANDCFG:PMLC_256G_SD
NANDCFG:PMLC_512G_TO
NANDCFG:PMLC_512G_SD
NANDCFG:3DV4_1P5T_SS

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

NAND:HPN1_256G_2L,SSDJTAG:2L,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_128G_TO_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_128G_SD_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_256G_TO_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_256G_SD_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_512G_TO_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:PMLC_512G_SD_NM,SOC:B0_1G

TABLE_BOMGROUP_ITEM

NAND:3DV4_1P5T_SS_MG3,SOC:B0_2G

B

CPU DRAM SPD Straps

BOM GROUP BOM OPTIONS

DRAMCFG:SAMSUNG_8GB

DRAMCFG:SAMSUNG_16GB

DRAMCFG:HYNIX_8GB
DRAMCFG:HYNIX_16GB
DRAMCFG:MICRON_8GB

DRAMCFG:MICRON_16GB

DRAM:SAMSUNG_8GB,RAMCFG0_L
DRAM:SAMSUNG_16GB,RAMCFG0_L,RAMCFG2_L,RAM_16GB
DRAM:HYNIX_8GB,RAMCFG0_L,RAMCFG1_L
DRAM:HYNIX_16GB,RAMCFG0_L,RAMCFG1_L,RAMCFG2_L,RAM_16GB
DRAM:MICRON_8GB
DRAM:MICRON_16GB,RAMCFG2_L,RAM_16GB

B

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

A

RAMCFGx strap is low if in table.

CPU DRAM CFG Chart

Vendor

Hynix
Samsung
Unused
Micron

CFG 1

0
1
0
1

8

CFG 0

0
0
1
1

Vendor

8GB
16GB

CFG 2

1
0

A

PAGE TITLE

BOM Configuration

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

PAGE

3 OF 145

SHEET

3 OF 85

1

SIZE

D

678

3 245

1

Shield Cans

D

Mounting Bracket

806-12895 CRITICAL1

BRKT,MOUNTING,MLB,X1030

DRAM Shield Can

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHIELD CAN,DRAM,X1030

BRACKETBRKT1

806-12387

1 CRITICALSHLD1 SHLD_CAN_DRAM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

NAND Shield Fence

D

SHIELD FENCE,MEMORY,SINGLE,X1030

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHLD_FNC_NANDSHLD2806-12384 1 CRITICAL

TR Shield Can

TABLE_5_HEAD

SHIELD CAN,TITAN RIDGE,X1030

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SHLD3806-12386 1 CRITICAL

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHLD_CAN_TR

C

Mounting Holes

998-03823

SH0400

TH-NSP

1

SL-3.36X2.1-5.86X4.6

SH0401

TH-NSP

1

SL-3.36X2.1-5.86X4.6

Heatsink Mounting Bosses

860-01043

SH0410

5.0OD1.85ID-1.5H-SM1

1

SH0411

5.0OD1.85ID-1.5H-SM1

1

SH0412

5.0OD1.85ID-1.5H-SM1

1

SH0413

5.0OD1.85ID-1.5H-SM1

1

SOC/NAND Shield Fence

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

806-12385 SHLD4 SHLD_FNC_SOCCRITICAL1

SHIELD FENCE,GIBRALTOR AND MEMORY,X1030

Diplexer Shield Can

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SHIELD CAN,DIPLEX,SUS,X1030

CRITICAL1 SHLD_CAN_DPLXRSHLD5806-12650

Bus Bars

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

806-16920 2 BUSBARLONGCRITICAL

BUSBAR,MLB,LONG,BOTTOM,X1032

BUSBAR,MLB,TOP,X1032

BUSBAR,MLB,LONG,BOTTOM,X1032

BB0400,BB0403

CRITICAL

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

C

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

BUSBARTOPBB04011806-16921 CRITICAL

TABLE_5_ITEM

BUSBARBOTTOMBB04021806-16922

B

998-11113 998-11114

SH0402

4.6R1.7-NSP 4.6X5.2R1.7X2.3-NSP

1

SH0403

1

Antenna Cowling Bosses

860-00974

SH0420

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

SH0421

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

B

A

8

A

PAGE TITLE

PD Parts

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=MECHANICALS

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

4 OF 145

SHEET

4 OF 85

1

SIZE

D

D

DDI Port Assignments:

USBC Sink 0

USBC Sink 1

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

678

3 245

1

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

947915

DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_ML_C_P<3>

DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<2> DP_X_SNK0_AUXCH_C_N
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_ML_C_P<3>

A46
C46
C48
A48
B45
D45
B47
D47

A42
C42
A44
C44
B41
D41
B43
D43

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

SYM 1 OF 20

DDI

DISPLAY

EDP

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

H45
F45
J44
G44
J46
G46
H43
F43

J42
G42

A40

H41
F41
J40
G40

DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>

DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P

TP_EDP_DISP_UTIL

DP_X_SNK0_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
DP_X_SNK1_AUXCH_C_P

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI

BI
BI
BI
BI

69

69

69

69

69

69

69

69

69

69

27

27

27

27

eDP Port Assignment:

D

Internal panel

C

PPVCCIO_S0_CPU

8 11 76

PLACE_NEAR=U0500.A50:15.24mm

R0520

24.9

1%

1/20W

MF

201

DISPLAY SIDEBANDS

TP_PCH_GPP_E18

20

OUT

1

20

OUT

PCH_DDPB_CTRLDATA
TP_PCH_GPP_E20

PCH_DDPC_CTRLDATA
TP_PCH_GPP_E22

2

TP_PCH_GPP_E23
MCP_EDP_RCOMP

L6

GPP_E18/DDPB_CTRLCLK

H6

GPP_E19/DDPB_CTRLDATA

H4

GPP_E20/DDPC_CTRLCLK

F4

GPP_E21/DDPC_CTRLDATA

M5

GPP_E22

L4

GPP_E23

A50

EDP_RCOMP

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLEN

EDP_BKLCTL

EDP_VDDEN

C11
L10
M7
F6
A7

D4
B6
D3

DP_X_SNK0_HPD
DP_X_SNK1_HPD
TP_PCH_GPP_E15
TBT_X_PLUG_EVENT_L
DP_INT_HPD

EDP_BKLT_EN
EDP_BKLT_PWM
EDP_PANEL_PWR_EN

OUT
OUT
OUT

IN
IN

IN
IN

27

27

27 25 5

69 5

79 68 5

79 69

69 5

C

B

B

A

PM_SLP_S3_L

R0530
R0560
R0562
R0563

100K
100K
100K
100K

8

21
21
21
21

1/20W
5% 2011/20W MF
5% MF

1/20W 201

79 25 20 15 14

PAGE TITLE

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

A

CPU GFX

DRAWING NUMBER

051-04039

Apple Inc.

TBT_X_PLUG_EVENT_L

2015% MF

EDP_BKLT_EN
EDP_PANEL_PWR_EN
DP_INT_HPD

MF5%

2011/20W

27 25 5

79 68 5

69 5

69 5

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

REVISION

2.0.0

BRANCH

PAGE

5 OF 145

SHEET

5 OF 85

1

SIZE

D

D

PP1V_S0SW

8 12 18 75

42

79 42 20 17 15

33 32

BI

OUT

678

PP1V_S3

8 12 15 59 75

R0610

1/20W

CPU_PROCHOT_L

IN

1K

5%
MF

201

1

2

1

R0614

100K

5%
1/20W
MF
201

2

R0611

499

2 1

1%

1/20W

MF

201

R0612

65 42

1K

5%

1/20W

MF

201

OUT

3 245

1

CRITICAL

OMIT_TABLE

U0500

1

65

2

42

OUT
BI

CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L

42

PM_THRMTRIP_L

NC

18

18

18

18

18

18

BI
BI
BI
BI

OUT
BI

(IFDIM trigger)

XDP_BPM_L<0>PLT_RST_L
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

XDP_PCH_OBSFN_C1
XDP_PCH_OBSDATA_A3
PCH_WLAN_PERST_L

33 32

OUT

PCH_WLAN_DEV_WAKE

IPD in module

CPU_OPI_RCOMP
PCH_OPI_COMP

H49
F49
J48
H47
B62

H51
J50
F51
G50

E11

M9

BD8

BC11

BN17
BP16

CATERR*
PECI
PROCHOT*
THERMTRIP*
SKTOCC*

BPM0*
BPM1*
BPM2*
BPM3*

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP

KBL-PCH-Y-QKKR

BGA

947915

SYM 4 OF 20

(IPU)

(IPU)
(IPU)
(IPU)
(IPU)

(IPD)
(IPU)

JTAG

(IPU)

CPU MISC

(IPD)

(IPD)
(IPU)

(IPU)

PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST*

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST*

JTAGX

D53
C54
G48
C59
F47

B53
C50
B51
A52
C52
B49

XDP_CPUPCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L

TP_XDP_PCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TCK

OUT

OUT

IN
IN

IN
IN

IN
IN

IN
IN

BI

18

18

18

18

18

18

18

18

18

18

18

D

C

B

A

R0620

49.9

PLACE_NEAR=U0500.BN17:2.54mm

PLACE_NEAR=U0500.BP16:2.54mm

1

1%

1/20W

MF

201

2

18

BI

R0634

1K

5%

1/20W

MF

201

R0680

49.9

1%

1/20W

MF

201

1

2

1

2

R0621

49.9

1%

1/20W

MF

201

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

1

2

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

OUT

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>

CPU_CFG<16>
CPU_CFG<17>

CPU_CFG<18>
CPU_CFG<19>

CPU_CFG_RCOMP
ITP_PMODE

TP_MCP_RSVD_D49

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC

NC

G52
F53
J52
H53
H55
D55
C56
F55
D61
G58
D57
F61
J60
J58
H61
H59

J54
G54

G56
J56

A54

A60

B4
B3

F3
F1

L36
L38

BA19
BB18

BC19
BD18

D49
M21
L20
M19

L26

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

(IPU)

BL64
BG47

BA17
AY18

BF18
BE19

BA23
AY22

R12
P13
M15
L16

L18
M17

AH7

K12
H12

BN3
BP3

L22
M23

BN1

AY20
BA21

BB14

M25
L24

L28
M27

BJ15
BJ17

NC
NC
NC
NC

NC
NC

NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

TP_MCP_RSVD_BL64
TP_MCP_RSVD_BG47

TP_MCP_RSVD_BA17
TP_MCP_RSVD_AY18

TP_MCP_RSVD_BF18
TP_MCP_RSVD_BE19

TP_MCP_RSVD_BA23
TP_MCP_RSVD_AY22

TP_MCP_RSVD_BN1

TP_MCP_RSVD_M25
TP_MCP_RSVD_L24

TP_MCP_RSVD_L28
TP_MCP_RSVD_M27

TP_MCP_RSVD_BJ15
TP_MCP_RSVD_BJ17

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

CPU Misc/JTAG/CFG/RSVD

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

6 OF 145

SHEET

6 OF 85

C

B

A

SIZE

D

8

67

35 4

2

.

1

678

3 245

1

D

C

B

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

AG61
AH60
AK62
AK60
AH62
AG63
AL61
AL63
AM60
AM62
AT60
AR61
AN61
AN63
AR63
AT62
AT56
AR55
AN57
AN55
AR57
AT58
AM58
AM56
AL55
AL57
AH58
AH56
AK58
AK56
AG55
AG57
BE55
BC55
BG53
BE53
BC53
BG55
BD52
BF52
BC51
BE51
BC49
BE49
BG51
BG49
BF48
BD48
BJ55
BL55
BJ53
BL53
BN55
BN53
BM52
BK52
BL51
BJ51
BL49
BJ49
BN49
BN51
BK48
BM48

DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR1_DQ0/DDR0_DQ16
DDR1_DQ1/DDR0_DQ17
DDR1_DQ2/DDR0_DQ18
DDR1_DQ3/DDR0_DQ19
DDR1_DQ4/DDR0_DQ20
DDR1_DQ5/DDR0_DQ21
DDR1_DQ6/DDR0_DQ22
DDR1_DQ7/DDR0_DQ23
DDR1_DQ8/DDR0_DQ24
DDR1_DQ9/DDR0_DQ25
DDR1_DQ10/DDR0_DQ26
DDR1_DQ11/DDR0_DQ27
DDR1_DQ12/DDR0_DQ28
DDR1_DQ13/DDR0_DQ29
DDR1_DQ14/DDR0_DQ30
DDR1_DQ15/DDR0_DQ31
DDR0_DQ16/DDR0_DQ32
DDR0_DQ17/DDR0_DQ33
DDR0_DQ18/DDR0_DQ34
DDR0_DQ19/DDR0_DQ35
DDR0_DQ20/DDR0_DQ36
DDR0_DQ21/DDR0_DQ37
DDR0_DQ22/DDR0_DQ38
DDR0_DQ23/DDR0_DQ39
DDR0_DQ24/DDR0_DQ40
DDR0_DQ25/DDR0_DQ41
DDR0_DQ26/DDR0_DQ42
DDR0_DQ27/DDR0_DQ43
DDR0_DQ28/DDR0_DQ44
DDR0_DQ29/DDR0_DQ45
DDR0_DQ30/DDR0_DQ46
DDR0_DQ31/DDR0_DQ47
DDR1_DQ16/DDR0_DQ48
DDR1_DQ17/DDR0_DQ49
DDR1_DQ18/DDR0_DQ50
DDR1_DQ19/DDR0_DQ51
DDR1_DQ20/DDR0_DQ52
DDR1_DQ21/DDR0_DQ53
DDR1_DQ22/DDR0_DQ54
DDR1_DQ23/DDR0_DQ55
DDR1_DQ24/DDR0_DQ56
DDR1_DQ25/DDR0_DQ57
DDR1_DQ26/DDR0_DQ58
DDR1_DQ27/DDR0_DQ59
DDR1_DQ28/DDR0_DQ60
DDR1_DQ29/DDR0_DQ61
DDR1_DQ30/DDR0_DQ62
DDR1_DQ31/DDR0_DQ63

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 2 OF 20

DDR CH - A

DDR0_CKN0
DDR0_CKP0
DDR0_CKN1
DDR0_CKP1

DDR0_CKE0
DDR0_CKE1
DDR0_CKE2
DDR0_CKE3

DDR0_CS0*
DDR0_CS1*
DDR0_ODT0

DDR0_CAA0
DDR0_CAA1
DDR0_CAA2
DDR0_CAA3
DDR0_CAA4
DDR0_CAA5
DDR0_CAA6
DDR0_CAA7
DDR0_CAA8
DDR0_CAA9

DDR0_CAB0
DDR0_CAB1
DDR0_CAB2
DDR0_CAB3
DDR0_CAB4
DDR0_CAB5
DDR0_CAB6
DDR0_CAB7
DDR0_CAB8
DDR0_CAB9

DDR0_MA3
DDR0_MA4

DDR0_DQSN0
DDR0_DQSP0
DDR0_DQSN1

DDR0_DQSP1
DDR1_DQSN0/DDR0_DQSN2
DDR1_DQSP0/DDR0_DQSP2
DDR1_DQSN1/DDR0_DQSN3
DDR1_DQSP1/DDR0_DQSP3
DDR0_DQSN2/DDR0_DQSN4
DDR0_DQSP2/DDR0_DQSP4
DDR0_DQSN3/DDR0_DQSN5
DDR0_DQSP3/DDR0_DQSP5
DDR1_DQSN2/DDR0_DQSN6
DDR1_DQSP2/DDR0_DQSP6
DDR1_DQSN3/DDR0_DQSN7
DDR1_DQSP3/DDR0_DQSP7

DDR0_ALERT*

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

BC62
BC60
BA60
BA62

BB57
BC58
BE57
AW61

AW63
BJ57
BN61

AW59
AW55
BF62
AV56
AW57
AV58
BA56
BD59
BD61
BG61

BK59
BL62
BJ61
AV60
BN62
BB61
BL61
BM59
BN58
AV62

BB63
BL57

AJ61
AJ63
AP62
AP60
AP56
AP58
AJ57
AJ55
BD54
BF54
BF50
BD50
BM54
BK54
BK50
BM50

BG57
BM56

AR53
AN53
AW53

BN47

NC
NC

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ

PM_MEMVTT_EN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

21

21

21

66

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

CRITICAL

OMIT_TABLE

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

24 22

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

BC41
BC39
BG41
BE39
BF42
BD42
BG39
BE41
BC43
BD46
BG43
BG45
BC45
BE43
BE45
BF46
BM28
BN27
BK28
BL25
BN25
BL27
BJ25
BJ27
BM24
BK24
BN21
BJ23
BL23
BN23
BJ21
BL21
BN45
BM46
BL43
BK46
BN43
BL45
BJ45
BJ43
BM42
BN41
BJ41
BN39
BK42
BL41
BL39
BJ39
BF28
BD28
BG25
BC27
BG27
BE27
BE25
BC25
BF24
BD24
BG21
BC23
BE23
BG23
BC21
BE21

DDR0_DQ32/DDR1_DQ0
DDR0_DQ33/DDR1_DQ1
DDR0_DQ34/DDR1_DQ2
DDR0_DQ35/DDR1_DQ3
DDR0_DQ36/DDR1_DQ4
DDR0_DQ37/DDR1_DQ5
DDR0_DQ38/DDR1_DQ6
DDR0_DQ39/DDR1_DQ7
DDR0_DQ40/DDR1_DQ8
DDR0_DQ41/DDR1_DQ9
DDR0_DQ42/DDR1_DQ10
DDR0_DQ43/DDR1_DQ11
DDR0_DQ44/DDR1_DQ12
DDR0_DQ45/DDR1_DQ13
DDR0_DQ46/DDR1_DQ14
DDR0_DQ47/DDR1_DQ15
DDR1_DQ32/DDR1_DQ16
DDR1_DQ33/DDR1_DQ17
DDR1_DQ34/DDR1_DQ18
DDR1_DQ35/DDR1_DQ19
DDR1_DQ36/DDR1_DQ20
DDR1_DQ37/DDR1_DQ21
DDR1_DQ38/DDR1_DQ22
DDR1_DQ39/DDR1_DQ23
DDR1_DQ40/DDR1_DQ24
DDR1_DQ41/DDR1_DQ25
DDR1_DQ42/DDR1_DQ26
DDR1_DQ43/DDR1_DQ27
DDR1_DQ44/DDR1_DQ28
DDR1_DQ45/DDR1_DQ29
DDR1_DQ46/DDR1_DQ30
DDR1_DQ47/DDR1_DQ31
DDR0_DQ48/DDR1_DQ32
DDR0_DQ49/DDR1_DQ33
DDR0_DQ50/DDR1_DQ34
DDR0_DQ51/DDR1_DQ35
DDR0_DQ52/DDR1_DQ36
DDR0_DQ53/DDR1_DQ37
DDR0_DQ54/DDR1_DQ38
DDR0_DQ55/DDR1_DQ39
DDR0_DQ56/DDR1_DQ40
DDR0_DQ57/DDR1_DQ41
DDR0_DQ58/DDR1_DQ42
DDR0_DQ59/DDR1_DQ43
DDR0_DQ60/DDR1_DQ44
DDR0_DQ61/DDR1_DQ45
DDR0_DQ62/DDR1_DQ46
DDR0_DQ63/DDR1_DQ47
DDR1_DQ48
DDR1_DQ49
DDR1_DQ50
DDR1_DQ51
DDR1_DQ52
DDR1_DQ53
DDR1_DQ54
DDR1_DQ55
DDR1_DQ56
DDR1_DQ57
DDR1_DQ58
DDR1_DQ59
DDR1_DQ60
DDR1_DQ61
DDR1_DQ62
DDR1_DQ63

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 3 OF 20

DDR CH - B

DDR1_CKN0
DDR1_CKP0
DDR1_CKN1
DDR1_CKP1

DDR1_CKE0
DDR1_CKE1
DDR1_CKE2
DDR1_CKE3

DDR1_CS0*
DDR1_CS1*
DDR1_ODT0

DDR1_CAA0
DDR1_CAA1
DDR1_CAA2
DDR1_CAA3
DDR1_CAA4
DDR1_CAA5
DDR1_CAA6
DDR1_CAA7
DDR1_CAA8
DDR1_CAA9

DDR1_CAB0
DDR1_CAB1
DDR1_CAB2
DDR1_CAB3
DDR1_CAB4
DDR1_CAB5
DDR1_CAB6
DDR1_CAB7
DDR1_CAB8
DDR1_CAB9

DDR1_MA3
DDR1_MA4

DDR0_DQSN4/DDR1_DQSN0
DDR0_DQSP4/DDR1_DQSP0
DDR0_DQSN5/DDR1_DQSN1
DDR0_DQSP5/DDR1_DQSP1
DDR1_DQSN4/DDR1_DQSN2
DDR1_DQSP4/DDR1_DQSP2
DDR1_DQSN5/DDR1_DQSN3
DDR1_DQSP5/DDR1_DQSP3
DDR0_DQSN6/DDR1_DQSN4
DDR0_DQSP6/DDR1_DQSP4
DDR0_DQSN7/DDR1_DQSN5
DDR0_DQSP7/DDR1_DQSP5

DDR1_DQSN6
DDR1_DQSP6
DDR1_DQSN7
DDR1_DQSP7

DDR1_ALERT*

DDR1_PAR

DRAM_RESET*

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

BK36
BM36
BD32
BF32

BN33
BK32
BG33
BH30

BM30
BJ33
BC35

BK30
BN31
BM32
BL37
BG31
BN37
BJ37
BJ35
BM34
BN35

BG37
BE37
BC37
BF34
BC33
BF30
BD36
BG35
BC31
BF36

BJ31
BK34

BD40
BF40
BD44
BF44
BK26
BM26
BM22
BK22
BK44
BM44
BM40
BK40
BD26
BF26
BF22
BD22

BD34
BD30
BP20

BF64
BJ64
BC64

NC
NC

NCNC
NC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>

MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

R0752

162

1%

1/20W

MF

201

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

24 23

D

C

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

B

1%

1/20W

MF

201

1

2

R0750

1

R0751

80.6

2

200

1%

1/20W

MF

201

1

2

A

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

PLACE_NEAR=U0500.BC64:12.7mm

PLACE_NEAR=U0500.BJ64:12.7mm

PLACE_NEAR=U0500.BF64:12.7mm

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

CPU LPDDR3 Interface

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

7 OF 145

SHEET

7 OF 85

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

SKL-ULX current estimates from Skylake Processor EDS vol 1, doc #544924, v0.94
VCCIO breakdown per 4/20/15 email from Srini

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

PPVCCGT_S0_CPU

8 12 76

24A Max

AA53
AB62
AC47
AC55
AD54
AD64
AE61
AF47
AJ53
AK49
AN46
AT43
AT50

N50
T46
T54
U61
V60
W57
Y44
Y51

Y62
AB54
AB64
AC49
AC57
AD56
AE53
AE63
AF49
AK43
AK50
AN47
AT44
AT51

R51

T47

U53

U63

V62

W59

Y46

Y54

Y64
AB58
AC44
AC51
AC61
AD60
AE57
AF44
AF51
AK46
AB60
AC46

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

947915

SYM 14 OF 20

CPU POWER 2 OF 4

VCCGT_SENSE
VSSGT_SENSE

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

AC53
AC63
AD62
AE59
AF46
AG53
AK47
AN44
AN51
AT49
N48
T44
T51
U59
V58
W55
Y43
Y50
Y60
AB56
AC43
AC50
AC59
AD58
AE55
AF43
AF50
AK44
AK51
AN49
AT46
N44
R53
T49
U55
V54
V64
W61
Y47
Y56
AN50
AT47
N46
T43
T50
U57
V56
W53
W63
Y49
Y58
AN43

N52
P52

PPVCCGT_S0_CPU

PLACE_NEAR=U0500.N52:50.8mm

1

R0830

100

5%
1/20W
MF
201

2

CPU_VCCGTSENSE_P
CPU_VCCGTSENSE_N

PLACE_NEAR=U0500.P52:50.8mm

1

R0831

100

5%
1/20W
MF
201

2

8 12 76

OUT
OUT

PPVCCSA_S0_CPU

11 76

3.78A Max

PLACE_NEAR=U0500.N30:50.8mm

VCCSA & VCCSA_DDR must
be isolated from VR
output to BGA pads

PPVCCSA_S0_CPUDDR

11 76

320mA Max

59

59

OUT
OUT

CPU_VCCSASENSE_P
CPU_VCCSASENSE_N

PLACE_NEAR=U0500.R30:50.8mm

24A Max

PPVCC_S0_CPU

8 11 49 76

TP_MCP_DC_A64

TP_MCP_DC_B64

59

59

R0860

100

5%

1/20W

MF

201

R0861

100

5%

1/20W

MF

201

NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 16 OF 20

AA29
AF30
AN29

AC29
AH29
AN30

AC30
AK29
AR29

1

2

1

2

AE29
AK30

AF29
AL29

AT29
AT30

VCCSA
VCCSA
VCCSA

L30

VCCSA

T30

VCCSA
VCCSA
VCCSA
VCCSA

M31

VCCSA

V29

VCCSA
VCCSA
VCCSA
VCCSA

N30

VCCSA

Y29

VCCSA
VCCSA
VCCSA

R29

VCCSA

Y30

VCCSA
VCCSA
VCCSA

T29

VCCSA

VCCSA_DDR
VCCSA_DDR

M29

VCCSA_SENSE

N28

VSSSA_SENSE

VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0
VCCG0

CPU POWER 4 OF 4

VCCG0
VCCG0
VCCG0
VCCG0
VCCG0

VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1
VCCG1

AA35
R38
Y35
AA38
T35
Y38
AC35
T38
AC38
V35
R35
V38

AF35
AK38
AR35
AF38
AL35
AR38
AH35
AL38
AH38
AN35
AK35
AN38

CRITICAL

OMIT_TABLE

A64
AE32
AE40
AH41
AN32
AT33
AT41

J64

L48

M33

M43

M53

M64

N40

N59

P60

R57

T41
AA32
AE33
AE41
AK32
AN41
AT35

B64

L40

L50

M35

M45

M56

N32

N42

N61

P62

R59

V32
AA41
AE35
AF32
AK41
AR32
AT36

D64

L42

L52

M37

M47

R63

P56

R32

Y32

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 13 OF 20

CPU POWER 1 OF 4

VCC_SENSE
VSS_SENSE

VIDALERT*

VIDSCK

VIDSOUT

VCCSTG
VCCSTG

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

M58
N34
N54
N63
P64
R61
V41
AC41
AE38
AH32
AL41
AT32
AT40
H63
L46
L63
M41
M51
M62
N38
N57
P58
R41
T32
Y41
AC32
AE36
AF41
AL32
AR41
AT38
F64
L44
L54
M39
M49
M60
N36
N55

L34
L32

B58
A56
A58

AA26
AC26

PPVCCG0_S0_CPU

MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.1500
VOLTAGE=1.5V

PPVCCG1_S0_CPU

MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.1500
VOLTAGE=1.5V

PPVCC_S0_CPU

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

PP1V_S0SW

11

11

8 11 49 76

VDDQC must implement

1nH trace filter

BYPASS=U0500.BA39::0.59mm

C0850

0.1UF

X5R-CERM

PLACE_NEAR=U0500.L34:50.8mm

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

1

2

1

2

R0820

6 8 12 18
75

PLACE_NEAR=U0500.L32:50.8mm

R0821

10%
10V

0201

1

2

OUT
OUT

59

59

PP1V2_S3

12 76

2A Max

TP_MCP_DC_BN64

TP_MCP_DC_BP64

XW0850

SM

21

PP1V2_S0_CPU_VDDQC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.2V

PP1V_S3

6 8 12 15
59 75

PP1V_S0SW

6 8 12 18 75

PP1V2_S0SW

12 76

PP1V_S3

12 75

R0800

56

1%

1/20W

MF

R0810

220

21

1%

1/20W

MF

201

R0812

0

21

5%

1/20W

MF

0201

201

R0811

0

5%

1/20W

MF

0201

R0800.2:
R0802.2:
R0811.1:

AH64
BA27
BA37
BA49
BP32
BP50
AK64
BA29
BA41
BA51
BP34
BP56
AT64
BA31
BA43
BN64
BP40
BP58
AV64
BA33
BA45
BP24
BP42
BP64
BA25
BA35
BA47
BP26
BP48
BA39

V26
Y26

R26
T26

AE27
AF27

R27
T27

PP1V_S3

1

2

1

R0802

100

1%
1/20W
MF
201

2

CPU_VIDALERT_L

21

CPU_VIDSCLK

CPU_VIDSOUT

PLACE_NEAR=U0500.B58:12.7mm
PLACE_NEAR=U0500.A58:12.7mm
PLACE_NEAR=U0500.A56:12.7mm

BOM_COST_GROUP=CPU & CHIPSET

KBL-PCH-Y-QKKR

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC

VCCST
VCCST

VCCSTG
VCCSTG

VCCPLL_OC
VCCPLL_OC

VCCPLL
VCCPLL

IN

OUT

BI

CRITICAL

OMIT_TABLE

U0500

BGA

947915

SYM 15 OF 20

CPU POWER 3 OF 4

VCCIO_SENSE
VSSIO_SENSE

6 8 12 15 59 75

59

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

59

59

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR
VCCIO_DDR

PPVCCIO_S0_CPU

AC23
AF24
AN26
AC24
AF26
AR26
AE23
AH26
AT26
AE24
AK26
AE26
AL26

AV26
AV36
AV46
AW31
AW41
AW51
AV28
AV38
AV48
AW33
AW43
AV30
AV40
AV50
AW35
AW45
AV32
AV42
AW27
AW37
AW47
AV34
AV44
AW29
AW39
AW49

AT24
AR24

VCCIO & VCCIO_DDR must
be isolated from local
plane to BGA pads

PPVCCIO_S0_CPU

PLACE_NEAR=U0500.AT26:50.8mm

1

R0840

100

5%
1/20W
MF
201

2

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

PLACE_NEAR=U0500.AN24:50.8mm

1

R0841

100

5%
1/20W
MF
201

2

CPU Power

Apple Inc.

1.185A Max

1.75A Max

5 11 76

76

OUT
OUT

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

8 OF 145

SHEET

8 OF 85

D

C

B

66

66

A

SIZE

D

8

67

35 4

2

1

D

C

VCCAMPHYPLL_1P0 and VCCPRIM_1P0 / VCCPRIM_3P3 breakdowns from Srini email 4/13/15

BYPASS=U0500.AL2::5.32mm

20%

6.3V
X5R

1

2

C0920

1.0UF

0201-1

678

PP1V_PRIM

75

370mA Max

PPVCC_PRIM_CORE

75

1.1A Max

PP1V_S5_PCH_DCPDSW

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.0V

PP1V_PRIM

13 75

22mA Max

PP1V_PRIM

13 75

See EDS Table 10-5

PP1V_SUSSW_PCH_VCCAMPHYPLL

13

88mA Max

PP1V_SUS_PCH_VCCAPLL

13

26mA Max

PP1V_PRIM

13 75

168mA Max

PP3V3_S5

13 75

71mA Max

PP3V3R1V8R1V5_S0_PCH_VCCHDA

13

68/36/33mA @ 3.3/1.8/1.5V Max

PP1V8_S5

13 75

11/7mA @ 3.3/1.8V Max

PP1V_PRIM

75

0.565A Max

AH18
AH19
AK18
AL18

AE18
AE19
AF18
AF19
AR16
AT16

AL2
AM1

V1
W2

T1
T15
T16

U2

V15
V16

AA18
AA19

AH13
AH15

AL15
AM13

AT23
AV22

AT15
AV15

AA21
AA23
AK23
AL23
AN23
AR23

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0
DCPDSW_1P0

VCCMPHYAON_1P0
VCCMPHYAON_1P0

VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0
VCCAPLL_1P0

VCCPRIM_1P0
VCCPRIM_1P0

VCCDSW_3P3
VCCDSW_3P3

VCCHDA
VCCHDA

VCCSPI
VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 17 OF 20

PCH POWER

VCCPGPPA
VCCPGPPA
VCCPGPPB
VCCPGPPB
VCCPGPPC
VCCPGPPC
VCCPGPPD
VCCPGPPD
VCCPGPPE
VCCPGPPE
VCCPGPPF
VCCPGPPF
VCCPGPPG
VCCPGPPG

VCCPRIM_3P3
VCCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0

VCCATS
VCCATS

VCCRTCPRIM_3P3
VCCRTCPRIM_3P3

VCCRTC
VCCRTC

DCPRTC
DCPRTC

VCCCLK1
VCCCLK1

VCCCLK2
VCCCLK2

VCCCLK3
VCCCLK3

VCCCLK4
VCCCLK4

VCCCLK5
VCCCLK5

AT1
AU2
AV1
AW2
AH1
AJ2
AF1
AG2
AA2
AB1
AN2
AP1
AN15
AP13

AC2
AD1

AA15
AA16

AE15
AE16

AK19
AL19

AR19
AT19

AT18
AV18

V18
Y18

V19
Y19

V23
Y23

V21
Y21

R21
R23

PP1V8_S5

20/9mA @ 3.3/1.8V Max

PP1V8_S5

4/2mA @ 3.3/1.8V Max

PP1V8_S5

6/3mA @ 3.3/1.8V Max

PP1V8_S5

8/3mA @ 3.3/1.8V Max

PP3V3_S5

6/2mA @ 3.3/1.8V Max

PP1V8_S5

33/161mA @ 3.3/1.8V Max

PP3V3_S5

41/56mA @ 3.3/1.8V Max

PP3V3_S5

PP1V_PRIM

PP1V8_S5

PP3V3_S5

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.0V

PP1V_PRIM

PP1V_PRIM

PP1V_SUS_PCH_VCCCLK3

PP1V_SUS_PCH_VCCCLK4

PP1V_SUS_PCH_VCCCLK5

3 245

1mA Max

6mA Max

6mA Max

<1mA Max

<1mA Max

35mA Max

29mA Max

24mA Max

33mA Max

4mA Max

75

17 75

14 17 75

75

13 75

17 75

14 75

75

75

13 75

13 75

75

75

13

13

13

Must not exceed

PP3V_G3H

1

C0901

1.0UF

20%

6.3V

2

X5R
0201-1

BYPASS=U0500.AR19::2.10mm

BYPASS=U0500.AT19::2.10mm

10%
10V

0201

1

2

C0900

0.1UF

X5R-CERM

1

C0910

0.1UF

10%
10V

2

X5R-CERM
0201

BYPASS=U0500.AT18::1.08mm

1

NOTE: Aliases not used on CPU supply outputsSPT-LP current estimates from Sunrise Point-LP PCH EDS vol 1, doc #545659, v1.2.
to avoid any extraneous connections.

D

3.2V max

15 75

C

B

PP3V3_S5

75

74mA Max

PP1V_PRIM

75

55mA Max

PP1V_PRIM

13 75

33mA Max

AH21
AK21

AR21
AT21

R15
R16

VCCPRIM_3P3
VCCPRIM_3P3

VCCPRIM_1P0
VCCPRIM_1P0

VCCAPLLEBB_1P0
VCCAPLLEBB_1P0

VCCCLK6
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

R19
T19

BA13
BB12

PP1V_PRIM

TP_PCH_CORE_VID<0>
TP_PCH_CORE_VID<1>

75

10mA Max

B

A

8

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

PAGE TITLE

A

PCH Power

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

9 OF 145

SHEET

9 OF 85

1

SIZE

D

678

3 245

1

D

C

B

A14
AA36
AA47
AA57
AC15
AC27
AE10
AE43
AE50
AF16
AF40
AF62
AH24
AH40
AH49

AK1
AK24
AK40
AL16
AL33
AL46
AL53
AN18
AN33
AP64

AR2

AR4
AR47

AR6
AU55
AV16
AW17
AY16
AY32
AY42
AY52

BA5

BA9
BB28
BB38
BB48
BC17
BD56
BE33
BF56

BG2

BG8
BH28
BH40
BH50
BJ29
BK56
BL35
BM16
BP36
BP54

D10

E14

E24

E34

E44

E54

J14

J9
AH47
AJ59
AK16
AK36

AK9
V24

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

K23
K33
K43
K53
L61
N20
R10
R24
R40
R49
T13
T33
T60
V27
V43
V50
Y15
Y33
Y9
AA24
AA40
AA49
AA59
AC16
AC33
AE2
AE44
AE51
AF21
AF54
AF64
AH27
AH43
AH50
AK11
AK27
AK5
AL21
AL36
AL47
AL59
AN19
AN36
AR10
AR27
AR40
AR49
AR8
AU57
AV20
AW19
AY24
AY34
AY44
BA53
BB20
BB30
BB40
BB50
BC29
BD63
BE35
BF59
BG29
AL30
AL44
AL51
AN16
AN27
BA7

BH20
BH32
BH42
BH52
BJ47

BL1
BL47
BM18

BN6
BP38
BP60

E16

E26

E36

R43

E46

E56

J3
K15
K25
K35
K45
K55

M3
N22
R30
R50
T18
T36
T62
V30
V44
V51
Y16
Y36

Y7

AA27
AA43
AA50
AA61
AC18
AC36
AE21
AE46

AE8

AF23
AF56
AG59
AH30
AH44
AH51
AK13

AK3

AK54
AL24
AL40
AL49
AM54
AN21
AN40
AR12
AR30
AR43
AP54
AR18
AR36
AR46
AR59

BA3

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 19 OF 20

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AR50
AT27
AU59
AV24
AY26
AW21
AY36
AY46
BA1
BB22
BA58
BB32
BB42
BB52
BE12
BC47
BE47
BG12
BG4
BH34
BH22
BH44
BH54
BJ62
BL29
BM20
BL8
BP22
BP44
E18
E28
D6
E38
E48
E59
K17
J5
K27
K37
K47
N14
L14
N24
R33
R44
T21
R55
T40
T64
V33
Y1
V46
Y24
Y40
AA30
AA51
AA44
AA63
AC19
AC40
AE47
AE30
AF13
AU53
AU63
AV54
AW25
AY30
AY50

AF33
AF58
AH16
AH33
AH46
AH54
AK15
AK33

AK7
AL27
AL43
AL50
AM64
AN24
AN59
AR15
AR33
AR44
AR51
AT54
AU61
AV52
AW23
AY28
AY38
AY48
BA11
BA64
BB24
BB34
BB44
BB54
BD20
BE29
BF20
BG15

BG6
BH24
BH36
BH46
BH56
BK20
BL31
BM11
BM38
BP28
BP46

C14

D62

E20

E30

E40

E50

F62

J62

K19

K29

K39

K49

L57

N16

N26

R18

R36
AY40

V49

Y13
AH36

V40

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 20 OF 20

GND 3 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

R46
R6
T23
T56
V13
V36
V47
Y11
Y27
Y5
BB26
BB36
BB46
BB59
BD38
BE31
BF38
BG17
BG63
BH26
BH38
BH48
BH59
BK38
BL33
BM14
BN29
BP30
BP52
C40
D8
E22
E32
E42
E52
G14
J7
K21
K31
K41
K51
L59
N18
P54
R2
R4
R47
R8
T24
T58
Y3
AA33
AA46
AA55
AB13
AC21
AD13
AE4
AE49
AF15
AF36
AF60
AH23
BP1
A5
D1

BP62

D

C

B

TP_MCP_DC_BP1
TP_MCP_DC_A5
TP_MCP_DC_D1

TP_MCP_DC_BP62

A

8

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

A

CPU & PCH Grounds

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

10 OF 145

SHEET

10 OF 85

1

SIZE

D

678

All Intel recommendations from Intel doc #561280 KBL-UY PDG and #594883 KBL-YR PDG addendum

CPU VCORE Decoupling

Intel implementation (#561280, Table 49-2): 20x 0.1uF 0201, 8x 10uF 0402, 6x 47uF 0805

PPVCC_S0_CPU

8 49 76

Intel implementation (#594883, AML): 20x 0.1uF 0201, 10x 1uF 0201, 9x 10uF 0402, 6x 100uF 0805
Apple implementation: 9x 0.1uF 0201, 21x 1uF 0201, 12x 20uF 0402 STUFF (6x NOSTUFF), 2x 220uF D1 STUFF (1x NOSTUFF)

3 245

1

D

CRITICAL

1

C1100

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1116

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1120

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1101

0.1UF

10%

6.3V

2

X6S
0201

1

C1117

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1121

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1102

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1118

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1122

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1103

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1119

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1123

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1104

1UF

20%

6.3V

2

X6S-CERM
0201

1

C111A

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1124

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1105

1UF

20%

6.3V

2

X6S-CERM
0201

1

2

CRITICAL

1

C111B

1UF 1UF

20%

6.3V

2

X6S-CERM
0201

1

2

CRITICAL

1

C1125

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

CRITICAL

C1106

1UF

20%

6.3V
X6S-CERM
0201

CRITICAL

C111C

20%

6.3V
X6S-CERM
0201

CRITICAL

C1126

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

1

C1107

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C111D

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1127

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1108

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1128

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1109

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1129

20UF

20%

2.5V

2

X6S-CERM
0402

1

C110A

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C112A

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C110B

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C112B

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C110C

1UF

20%

6.3V

2

X6S-CERM
0201

1

C110D

0.1UF

10%

6.3V

2

X6S
0201

NO STUFF NO STUFF
CRITICAL

1

C112C

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C112D

20UF

20%

2.5V

2

X6S-CERM
0402

1

C110E

0.1UF

10%

6.3V

2

X6S
0201

NO STUFF
CRITICAL

1

C112E

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C110F

1UF

20%

6.3V

2

X6S-CERM
0201

NO STUFF
CRITICAL

1

C112F

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1110

1UF

20%

6.3V

2

X6S-CERM
0201

NO STUFF
CRITICAL

1

C112G

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1111

1UF

20%

6.3V

2

X6S-CERM
0201

NO STUFF
CRITICAL

1

C112H

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1112

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1130

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C1113

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1131

220UF

20%
2V

2

ELEC
SM

CRITICAL

1

C1114

1UF

20%

6.3V

2

X6S-CERM
0201

NO STUFF
CRITICAL

1

C1134

220UF

20%
2V

2

ELEC
SM

1

C1115

0.1UF

10%

6.3V

2

X6S
0201

D

C

PPVCCG0_S0_CPU

8

PPVCCG1_S0_CPU

8

CPU VCORE G0 Decoupling

Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201
Intel implementation (#594883, AML): 10x 0.1uF 0201, 2x 1uF 0201
Apple implementation : 10x 0.1uF 0201, 2x 1uF 0201

1

C1140

0.1UF

10%

6.3V

2

X6S
0201

1

C1141

0.1UF

10%

6.3V

2

X6S
0201

1

C1142

0.1UF

10%

6.3V

2

X6S
0201

1

C1143

0.1UF

10%

6.3V

2

X6S
0201

1

C1146

0.1UF

10%

6.3V

2

X6S
0201

1

C1147

0.1UF

10%

6.3V

2

X6S
0201

CPU VCORE G1 Decoupling

Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201
Intel implementation (#594883, AML): 10x 0.1uF 0201, 2x 1uF 0201
Apple implementation : 10x 0.1uF 0201, 2x 1uF 0201

1

C1150

0.1UF

10%

6.3V

2

X6S
0201

1

C1151

0.1UF

10%

6.3V

2

X6S
0201

1

C1152

0.1UF

10%

6.3V

2

X6S
0201

1

C1153

0.1UF

10%

6.3V

2

X6S
0201

1

C1154

0.1UF

10%

6.3V

2

X6S
0201

1

C1157

0.1UF

10%

6.3V

2

X6S
0201

1

C1148

0.1UF

10%

6.3V

2

X6S
0201

1

C1158

0.1UF

10%

6.3V

2

X6S
0201

1

C1149

0.1UF

10%

6.3V

2

X6S
0201

1

C1159

0.1UF

10%

6.3V

2

X6S
0201

1

C114A

0.1UF

10%

6.3V

2

X6S
0201

1

C115A

0.1UF

10%

6.3V

2

X6S
0201

1

C114B

0.1UF

10%

6.3V

2

X6S
0201

1

C115B

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1144

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1155

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1145

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1156

1UF

20%

6.3V

2

X6S-CERM
0201

C

B

PPVCCIO_S0_CPU

5 8 76

CPU VCCIO Decoupling

Intel implementation (#561280, Table 49-2): 13x 0.1uF 0201, 1x 1uF 0402
Apple implementation : 13x 0.1uF 0201, 1x 1uF 0402, 7x 20uF 0402 (2x 20uF on VR page), 1x 220uF D1

1

C1160

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1177

1.0UF

20%

6.3V

2

X5R
0201-1

1

C1161

0.1UF

10%

6.3V

2

X6S
0201

1

C1162

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1178

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1163

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1179

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1164

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117A

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1165

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117B

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1166

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117C

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1167

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117D

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1168

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117E

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1169

0.1UF

10%

6.3V

2

X6S
0201

1

C116A

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C117G

220UF

20%
2V

2

ELEC
SM

1

C116B

0.1UF

10%

6.3V

2

X6S
0201

1

C116C

0.1UF

10%

6.3V

2

X6S
0201

B

A

PPVCCSA_S0_CPU

8 76

PPVCCSA_S0_CPUDDR

8 76

CPU VCCSA Decoupling

Intel implementation (#561280, Table 49-2): 1x 1uF 0201, 4x 22uF 0603
Apple implementation : 6x 1uF 0201, 2x 2.2uF 0402, 3x 10uF 0402, 1x 120uF D1

CRITICAL

1

C1180

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1181

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1182

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL CRITICAL

1

C1183

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1184

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C118A

1UF

20%

6.3V

2

X6S-CERM
0201

CPU VCCSA DDR Decoupling

Intel implementation (#561280, Table 49-2): 1x 0.1uF 0201, 1x 22uF 0603
Apple implementation : 1x 1uF 0201, 1x 10uF 0402

CRITICAL

1

C1195

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1197

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C118B

2.2UF

20%
25V

2

X6S-CERM
0402

1

C118C

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C118D

10UF

20%

6.3V

2

CER-X6S
0402

CRITICALCRITICAL

1

C118E

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C118F

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1190

120UF

20%

2.5V

2

TANT-POLY
CASE-B2-SM

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

CPU Decoupling 1

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

BRANCH

PAGE

11 OF 145

SHEET

11 OF 85

A

SIZE

D

2.0.0

8

67

35 4

2

1

678

All Intel recommendations from Intel doc #561280 KBL-UY PDG and #594883 KBL-YR PDG addendum

CPU GT Decoupling

Intel implementation (#561280, Table 49-2): 12x 0.1uF 0201, 2x 1uF 0402, 9x 47uF 0805

PPVCCGT_S0_CPU

8 76

Apple implementation: 24x 0.1uF 0201, 2x 1uF 0201, 10x 20uF 0402 STUFF (6x NOSTUFF), 2x 220uF D1 STUFF

3 245

1

D

1

C1200

0.1UF

10%

6.3V

2

X6S
0201

1

C1213

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1254

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1201

0.1UF

10%

6.3V

2

X6S
0201

1

C1214

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1255

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1202

0.1UF

10%

6.3V

2

X6S
0201

1

C1215

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1256

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1203

0.1UF

10%

2

X6S
0201

1

C1216

0.1UF

10%

6.3V

2

X6S
0201

1

C1257

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1204

0.1UF

10%

6.3V6.3V

2

X6S
0201

1

C1217

0.1UF

10%

6.3V

2

X6S
0201

CRITICALCRITICAL

1

C1258

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1205

0.1UF

6.3V

2

X6S
0201

1

C1218

0.1UF

10% 10%

6.3V

2

X6S
0201

CRITICAL

1

C1259

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1206

0.1UF

10%10%

6.3V

2

X6S
0201

1

C1219

1

2

1

0.1UF

6.3V 6.3V

2

X6S
0201

2

CRITICAL

1

C125A

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

CRITICAL

C1207

1UF

20%

6.3V
X6S-CERM
0201

C1220

0.1UF

10%
X6S

0201

CRITICAL

C125B

20UF

20%

2.5V
X6S-CERM
0402

1

C1208

0.1UF

10%

6.3V

2

X6S
0201

1

C1221

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C125C

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1209

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1222

0.1UF

10%

6.3V 6.3V

2

X6S
0201

1

2

1

2

CRITICAL

1

C125D

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

C1210

0.1UF

10%

6.3V
X6S
0201

C1223

0.1UF

10%
X6S

0201

CRITICAL

C125E

20UF

20%

2.5V
X6S-CERM
0402

1

C1211

0.1UF

10%

2

X6S
0201

1

C1224

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C125F

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1212

0.1UF

10%

6.3V6.3V

2

X6S
0201

1

C1225

0.1UF

10%

6.3V

2

X6S
0201

NO STUFF
CRITICAL

1

C125G

20UF

20%

2.5V

2

X6S-CERM
0402

D

C

PP1V2_S3

8 76

NO STUFF
CRITICAL

1

C125H

20UF

20%

2.5V

2

X6S-CERM
0402

CPU VDDQ DECOUPLING

NO STUFF
CRITICAL

1

C125I

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF
CRITICAL

1

C125J

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1264

220UF

20%
2V

2

ELEC
SM

Intel implementation (#561280, Table 49-2): 18x 0.1uF 0201
Apple implementation: 18x 0.1uF 0201

1

C1270

0.1UF

10%

6.3V

2

X6S
0201

1

C1271

0.1UF

10%

6.3V

2

X6S
0201

1

C1272

0.1UF

10%

6.3V

2

X6S
0201

1

C1273

0.1UF

10%

6.3V

2

X6S
0201

1

C1274

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C1265

220UF

20%
2V

2

ELEC
SM

1

C1275

0.1UF

10%

6.3V

2

X6S
0201

1

C1276

0.1UF

10%

6.3V

2

X6S
0201

1

C1277

0.1UF

10%

6.3V

2

X6S
0201

1

C1278

0.1UF

10%

6.3V

2

X6S
0201

1

C1279

0.1UF

10%

6.3V

2

X6S
0201

CPU VCCST BYPASS
(CPU 1.0V SUSTAIN PWR)

PP1V_S3

6 8 15 59 75

C

B

1

C1280

0.1UF

10%

6.3V

2

X6S
0201

1

C1281

0.1UF

10%

6.3V

2

X6S
0201

1

C1282

0.1UF

10%

6.3V

2

X6S
0201

1

C1283

0.1UF

10%

6.3V

2

X6S
0201

1

C1284

0.1UF

10%

6.3V

2

X6S
0201

1

C1285

0.1UF

10%

6.3V

2

X6S
0201

1

C1286

0.1UF

10%

6.3V

2

X6S
0201

1

C1287

0.1UF

10%

6.3V

2

X6S
0201

C1290

0.1UF

10%

6.3V
X6S

0201

BYPASS=U0500.V26::2.38mm

CPU VCCSTG BYPASS
(CPU 1.0V SUSTAIN GATED PWR)

PP1V_S0SW

6 8 18 75

C1292

0.1UF

10%

6.3V
X6S

0201

BYPASS=U0500.R26::4.20mm

CPU VCCPLL_OC BYPASS
(CPU 1.2V PLL PWR)

PP1V2_S0SW

8 76

1

2

1

2

B

A

PAGE TITLE

C1294

0.1UF

6.3V

0201

BYPASS=U0500.AE27::2.07mm

CPU VCCPLL BYPASS
(CPU 1.0V DIGITAL PLL PWR)

PP1V_S3

8 75

C1296

0.1UF

6.3V

0201

BYPASS=U0500.R27::1.99mm

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

10%
X6S

10%
X6S

1

2

1

2

A

Bypass calcs based on 0.1mm trace width NOTE:
with worst case stackup and 500pH added
for power/ground via pair.

8

CPU Decoupling 2

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

12 OF 145

SHEET

12 OF 85

1

SIZE

D

D

(PCH 3.3V DSW PWR)

PP3V3_S5

9 75

10%

6.3V
X6S

0201

1

2

C1300

0.1UF

BYPASS=U0500.AL15::1.96mm

PCH VCCPRIM_1P0 BYPASSPCH VCCDSW_3P3 BYPASS
(PCH 1.0V USB PWR)

PP1V_PRIM

9 75

BYPASS=U0500.AH13::1.39mm

678

3 245

1

PCH VCCAMPHYPLL_1P0 FILTER/BYPASS
(PCH 1.0V USB3/PCIE/SATA/MIPI PLL PWR)

C1336

0.1UF

10%

6.3V
X6S

0201

PP1V_PRIM

75

1

2

R1370

0

21

5%
1/16W
MF-LF

402

NOSTUFF

C1370

20UF

20%

6.3V

CERM-X5R

0402

BYPASS=U0500.V15::12.82mm

BYPASS=U0500.V15::12.82mm

BYPASS=U0500.V15::3.91mm

NOSTUFF

1

2

C1371

20UF

6.3V

CERM-X5R

0402

1

20%

2

PP1V_SUSSW_PCH_VCCAMPHYPLL

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V

NOSTUFF

1

C1372

0.1UF

10%

6.3V

2

X6S
0201

9

D

C

(PCH 3.3V/1.8V SPI PWR)

PP1V8_S5

9 75

BYPASS=U0500.AT15::2.38mm

PCH VCCRTCPRIM BYPASS
(PCH 3.3V SUSPEND RTC PWR)

PP3V3_S5

9 75

BYPASS=U0500.AK19::1.68mm

C1302

0.1UF

10%

6.3V
X6S

0201

C1306

1.0UF

20%

6.3V
X5R

0201-1

PCH VCCCLK3 FILTER/BYPASS
(PCH 1.0V CLOCK 3 PWR)

PCH VCCMPHYAON_1P0 BYPASSPCH VCCSPI BYPASS

PP1V_PRIM

75

(PCH 1.0V MPHY ALWAYS ON PWR)

PP1V_PRIM

9 75

10%

6.3V
X6S

0201

1

2

1

C1340

0.1UF

2

BYPASS=U0500.V1::1.68mm

R1380

0

21

5%
1/16W
MF-LF

402

NOSTUFF

C1380

20UF

20%

6.3V

CERM-X5R

0402

BYPASS=U0500.V19::10.17mm

BYPASS=U0500.V19::10.17mm

NOSTUFF

1

2

C1381

20UF

6.3V

CERM-X5R

0402

1

20%

2

PP1V_SUS_PCH_VCCCLK3

MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.0V

9

PCH VCCCLK4 FILTER/BYPASS
(PCH 1.0V CLOCK 4 PWR)

PCH VCCAPLLEBB BYPASS

PP1V_PRIM

75

(PCH 1.0V APLL EBB PWR)

PP1V_PRIM

9 75

1

C1307

0.1UF

2

BYPASS=U0500.AK19::1.68mm

10%

6.3V
X6S

0201

1

C1344

0.1UF

2

BYPASS=U0500.R15::1.54mm

10%

6.3V
X6S

0201

1

2

R1385

0

21

5%
1/16W
MF-LF

402

NOSTUFF

C1385

20UF

20%

6.3V

CERM-X5R

0402

BYPASS=U0500.V21::10.17mm

BYPASS=U0500.V21::10.17mm

NOSTUFF

1

2

C1386

20UF

6.3V

CERM-X5R

0402

1

20%

2

PP1V_SUS_PCH_VCCCLK4

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V

9

C

B

PCH VCCPGPPE BYPASS
(PCH 3.3V/1.8V GPIO GROUP E PWR)

PP3V3_S5

9 75

C1318

0.1UF

BYPASS=U0500.AA2::0.84mm

PCH VCCATS BYPASS
(PCH 1.8V THERMAL PWR)

PP1V8_S5

9 75

C1330

1.0UF

BYPASS=U0500.AE15::1.76mm

10%

6.3V
X6S

0201

20%

6.3V
X5R

0201-1

PCH VCCCLK5 FILTER/BYPASS
(PCH 1.0V CLOCK 5 PWR)

PCH VCCMPHYGT_1P0 BYPASS

PP1V_PRIM

75

(PCH 1.0V MPHY GATED PWR)

PP1V_PRIM

9 75

10%

6.3V
X6S

0201

1

C1347

1.0UF

2

0201-1

BYPASS=U0500.T15::4.18mm

1

C1346

0.1UF

2

BYPASS=U0500.T15::3.07mm

20%

6.3V
X5R

1

C1348

20UF

2

CERM-X5R

BYPASS=U0500.T15::4.18mm

20%

6.3V
0402

1

2

R1390

0

21

5%
1/16W
MF-LF

402

OMIT_TABLE

NOSTUFF

C1390

20UF

20%

6.3V

CERM-X5R

0402

BYPASS=U0500.R21::10.17mm

BYPASS=U0500.R21::10.17mm

BYPASS=U0500.R21::0.92mm

NOSTUFF

1

2

C1391

20UF

6.3V

CERM-X5R

0402

1

20%

2

L1309

PP1V8_S5

75

PLACE_NEAR=L1309.1:1mm

1

1

2

C1308

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

220-OHM-0.7A-0.28-OHM

PLACE_NEAR=U0500.AT23:1mm

21

0402-1

NOSTUFF

1

C1304

0.1UF

10%

6.3V

2

X6S
0201

PP1V_SUS_PCH_VCCCLK5

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V

1

C1392

0.1UF

10%

6.3V

2

X6S
0201

PCH VCCHDA FILTER/BYPASS

(PCH 3.3V/1.8V/1.5V HDA PWR)

PP3V3R1V8R1V5_S0_PCH_VCCHDA

MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.5V

1

C1309

2.9PF

+/-0.05PF
25V

2

C0G-CERM
0201

BYPASS=U0500.AT23::1.23mm

9

9

B

A

PP1V_PRIM

75

PART# DESCRIPTIONQTY

155S0391 L1309,L13952

155S00480 L1309,L13952

PLACE_NEAR=L1395.1:1mm

1

C1393

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

FERR BD,220 OHM,25%,700MA,0.28 DCR,0402

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

FERR BD,30 OHMZ,25%,0.6A,0.449 OHM,0402

OMIT_TABLE

L1395

220-OHM-0.7A-0.28-OHM

PLACE_NEAR=U0500.AA18:1mm

21

0402-1

BYPASS=U0500.AT23::1.23mm

NOSTUFF

1

C1394

0.1UF

10%

6.3V

2

X6S
0201

BYPASS=U0500.AA18::1.23mm

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PCHFLTR:FERRITE

TABLE_5_ITEM

PCHFLTR:BYPASS2 L1309,L1395116S0004

TABLE_5_ITEM

PCHFLTR:FERRITE30

PCH VCCAPLL FILTER/BYPASS
(PCH 1.0V APLL PWR)

PP1V_SUS_PCH_VCCAPLL

MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700
VOLTAGE=1.0V

1

C1395

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

BYPASS=U0500.AA18::1.23mm

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

9

A

8

PCH Decoupling

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

13 OF 145

SHEET

13 OF 85

1

SIZE

D

D

678

3 245

1

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

20

18

IN

OUT

TP_HDA_SYNC
TP_HDA_BIT_CLK
HDA_SDOUT
TP_HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_RST_L
SPT_XDP_PCH_OBSDATA_D0
TP_PCH_I2S1_SFRM
TP_PCH_I2S1_TXD

TP_PCH_GPP_F1
TP_PCH_GPP_F0
TP_PCH_GPP_F2
TP_PCH_GPP_F3

BJ19
BK18
BK16
BL15
BL17
BL19

V5
BL12
BK14

AT13
AT11
AP11

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST*/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD)

BGA

947915

SYM 7 OF 20

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1

(IPD)

AUDIO

GPP_A17/SD_PWR_EN*/ISH_GP7

GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD*

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AH9
AH11
AG12
AF9
AF11
AG8
AG10
AE12

BL4
BN4

BF1

AJ8AT5

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_POC_RESET
JTAG_TBT_X_TMS
TBT_X_PCI_RESET_L
JTAG_ISP_TCK
JTAG_ISP_TDI
JTAG_ISP_TDO

TP_PCH_GPP_A17
TP_PCH_GPP_A16

TP_PCH_SD_RCOMP
TP_PCH_GPP_F23

OUT
OUT
OUT
OUT

OUT
OUT
OUT

29

29

PLT_RST_3V3_L

1

R1424

28 27 25 14

28 27 25 14

27 14

27 25 14

25 14

25 14

25 14

100K

5%
1/20W
MF
201

2

OUT

27 25

IN

20

D

C

18

18

18

18

OUT
OUT

OUT
OUT

SPT_XDP_PCH_OBSDATA_C2
SPT_XDP_PCH_OBSDATA_C3

SPT_XDP_PCH_OBSDATA_C0
SPT_XDP_PCH_OBSDATA_C1

NC_PCH_STRP_TOPBLK_SWP_L

77

77

77

77

77

20

77

OUT
BI
BI
BI
BI
OUT

NC_SPI_PCHROM_CLK
NC_SPI_PCHROM_MISO
NC_SPI_PCHROM_MOSI
NC_SPI_PCHROM_IO<2>
SPI_PCHROM_IO<3>
NC_SPI_PCHROM_CS_L
TP_SPI_CS1_L
TP_SPI_CS2_L

TP_PCH_GPP_D1
TP_PCH_GPP_D2
TP_PCH_GPP_D3

17

MLB_RAMCFG4

IN

TP_PCH_GPP_D22
TP_PCH_GPP_D0

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

PCH_GPP_A0_PU

14

TP_PCH_GPP_A6

V3

V11

U12

U8

AV3

CKPLUS_WAIVE=CLK_DATA_CONCKPLUS_WAIVE=CLK_DATA_CON

CKPLUS_WAIVE=CLK_DATA_CON

U0500.V5, U0500.V3, U0500.U12

AU10
AU12

AV11
AV13

BL10

SPI0_CLK
SPI0_MISO

AT3

SPI0_MOSI
SPI0_IO2
SPI0_IO3

AU4

SPI0_CS0*

AU6

SPI0_CS1*

AU8

SPI0_CS2*

P9

GPP_D1

N8

GPP_D2

P3

GPP_D3

W12

GPP_D21

V7

GPP_D22

N6

GPP_D0

F12

CL_CLK

D12

CL_DATA

B12

CL_RST*

GPP_A0/RCIN*

BN8

GPP_A6/SERIRQ

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

(IPD-PLTRST#)

CRITICAL

OMIT_TABLE

KBL-PCH-Y-QKKR

(IPU-RSMRST#)
(IPU)
(IPU-RSMRST#)
(IPU)
(IPU)
(IPU-RSMRST#)
(IPU-RSMRST#)
(IPU-RSMRST#)

(IPU/IPD)
(IPU/IPD)

(IPU-eSPI)
(IPU-eSPI)

SPI - FLASHC LINK

U0500

BGA

947915

SYM 5 OF 20

(IPU)

LPC SMBUS, SMLINK

(IPU-eSPI)

GPP_A14/SUS_STAT*/ESPI_RESET*

SDIO/SDXC

GPP_C0/SMBCLK

GPP_C1/SMBDATA

(IPD-RSMRST#)

(IPD-RSMRST#)

GPP_B23/SML1ALERT*/PCHHOT*

(IPD-PLTRST#)

GPP_A5/LFRAME*/ESPI_CS*

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN*

AC12
W6
W8

W4
AC10
AA6

AA4
W10
BB6

BK11
BJ8
BG10
BP5
BP7
BJ6

BJ10
BF5
BH11

SMBUS_PCH_CLK
SMBUS_PCH_DATA
TP_PCH_STRP_TLSCONF

SML_PCH_0_CLK
SML_PCH_0_DATA
PCH_STRP_ESPI

I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA
TP_PCH_STRP_BSSB_SEL_GPIO

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
ESPI_RESET_L

ESPI_CLK60M_R

R1476

TP_PCH_GPP_A10
TP_PCH_GPP_A8

OUT

OUT

14

OUT

OUT
OUT

BI

BI

BI

BI
BI
BI

45

45

45

45

45

45

35

35

35

35

35

35

22

LPC strap sampled at RSMRST# rising (0 = LPC, 1 = eSPI)

21

1% MF1/20W

201

ESPI_CLK60M

OUT

35

C

B

PP1V8_S5
PP3V3_S5
PM_SLP_S3_L

B

9 17 75

9 75

79 25 20 15 5

A

R1420
R1421
R1422
R1423
R1468
R1475

R1425
R1426
R1427

8

100K
100K

10K
10K

100K

1K

100K
100K
100K

21

5%

21
21
21
21
21

21
21
21

1/20W MF5% 201

5% 201

5% 2011/20W

1/20W
1/20W MF

5% 201

MF 2011/20W

MF1/20W 2015%
MF1/20W

MF

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
JTAG_TBT_X_TMS

2015% MF1/20W

JTAG_ISP_TDO

2011/20W MF5%

PCH_GPP_A0_PU
PCH_STRP_ESPI

TBT_POC_RESET
JTAG_ISP_TCK

2015% MF

JTAG_ISP_TDI

14

14

29 28 27 25 14

29 28 27 25 14

27 25 14

25 14

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

PCH Audio/LPC/SPI/SMBus

DRAWING NUMBER

SIZE

051-04039

Apple Inc.

27 14

25 14

25 14

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

REVISION

2.0.0

BRANCH

PAGE

14 OF 145

SHEET

14 OF 85

1

A

D

D

PP1V_S3

6 8 12 59 75

19

IN

R1523

CPU_VCCST_PWRGD

1K

5%

1/20W

MF

201

678

3 245

1

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 11 OF 20

1

2

R1522

60.4

1%

1/20W

MF

201

79 42 20 17 15 6

42 20

21

PLACE_NEAR=U0500.B61:7.62mm

79 42

42 33

42

OUT

IN
IN

IN
IN

PLT_RST_L
PM_SYSRST_L
PM_RSMRST_L

TP_CPU_PWRGD
CPU_VCCST_PWRGD_R

PM_PCH_SYS_PWROK
PM_PCH_PWROK

TP_PCH_GPP_A13
TP_PCH_GPP_A15

PCIE_WAKE_L

15

TP_PCH_LAN_WAKE_L

15

TP_PCH_LANPHYPC
TP_PCH_GPD7

BB8 BC9

GPP_B13/PLTRST*

H2

SYS_RESET*

BJ12

BP14
BN15

BE15
BC15
BB16

RSMRST*

A62

PROCPWRGD

B61

VCCST_PWRGD

J1

SYS_PWROK
PCH_PWROK
DSW_PWROK

BL6

GPP_A13/SUSWARN*/

SUSPWRDNACK

BF9

GPP_A15/SUSACK*

BP9

WAKE*
GPD2/LAN_WAKE*
GPD11/LANPHYPC
GPD7/RSVD

(IPD-DeepSx)

SYSTEM POWER MANAGEMENT

(IPU)

(IPU)

(IPD-DeepSx)

(IPD-DeepSx)

(IPU)

GPP_B11/EXT_PWR_GATE*

GPP_B12/SLP_S0*

GPD4/SLP_S3*
GPD5/SLP_S4*

GPD10/SLP_S5*

SLP_SUS*
SLP_LAN*

GPD9/SLP_WLAN*

GPD6/SLP_A*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD0/BATLOW*

GPP_A11/PME*

INTRUDER*

GPP_B2/VRALERT*

AY14
BF16
BH14

BN10
BP11
BH16
BE17

BF14
BD14
BD16

BF7
BG19

BC7
BD6

PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L

TP_PCH_SLP_SUS_L
TP_PCH_SLP_LAN_L
TP_PCH_SLP_WLAN_L
TP_PCH_SLP_A_L

PCH_PWRBTN_L
NC_SPIROM_USE_MLB
PCH_BATLOW_L

TP_PCH_GPP_A11
PCH_INTRUDER_L

TP_HSIO_PWR_EN
TP_PCH_GPP_B2

15

OUT
OUT
OUT
OUT

IN

BI

77

82 79 66 65 35 15

79 25 20 15 14 5

79 15

79 15

PP3V_G3H

65 15

1

R1580

1M

5%
1/20W
MF
201

2

9 75

D

C

C

B

PP3V3_S5

B

75

A

R1520
R1521
R1538
R1540

R1510
R1530
R1531
R1532
R1533

8

10K

100K

1K

100K
100K

100K
100K
100K
100K

21

21

21
21

21
21
21
21
21

1/20W 201

5% 1/20W MF 201

5%

1/20W 201MF

1/20W5% 201
1/20W5% MF 201
1/20W 201

5% MF

MF5%

MF5%

MF5% 1/20W

MF1/20W5%
MF

PCIE_WAKE_L
TP_PCH_LAN_WAKE_L

2011/20W

PCH_PWRBTN_L

201

PCH_BATLOW_L
PLT_RST_L

PM_SLP_S0_L

201

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L

15

15

15

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

65 15

PCH Power Management

DRAWING NUMBER

SIZE

051-04039

79 42 20 17 15 6

82 79 66 65 35 15

79 25 20 15 14 5

79 15

79 15

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

15 OF 145

SHEET

15 OF 85

1

A

D

D

C

PCIe Port Assignments:

SOC BDF: 0/28/0
SOC lane 0

SOC lane 1

SOC lane 2

SOC lane 3

TBT BDF: 0/28/4
Thunderbolt X lane 0

Thunderbolt X lane 1

Thunderbolt X lane 2

Thunderbolt X lane 3

WLAN BDF: 0/29/0
WLAN

ENET/SD BDF: 0/29/1
Reserved: ENET/SD

R1610

100

1%

1/20W

MF

201

678

3 245

1

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

37

37

43

43

37

37

43

43

37

37

43

43

37

37

43

43

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

33

33

33

33

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>

PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>

PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>
PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>

PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>

PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_X_R2D_C_P<3>

PCIE_PCH_WLAN_D2R_N
PCIE_PCH_WLAN_D2R_P
PCIE_PCH_WLAN_R2D_C_N
PCIE_PCH_WLAN_R2D_C_P

TP_PCIE_PCH_ENETSD_D2RN
TP_PCIE_PCH_ENETSD_D2RP
TP_PCIE_PCH_ENETSD_R2D_CN
TP_PCIE_PCH_ENETSD_R2D_CP

1

PCH_PCIE_RCOMP_N
PCH_PCIE_RCOMP_P

PLACE_NEAR=U0500.B10:2.54mm

18

18

OUT

IN

2

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
TP_PCH_GPP_A7

C20

PCIE1_RXN/USB3_5_RXN

A20

PCIE1_RXP/USB3_5_RXP

G20

PCIE1_TXN/USB3_5_TXN

J20

PCIE1_TXP/USB3_5_TXP

B19

PCIE2_RXN/USB3_6_RXN

D19

PCIE2_RXP/USB3_6_RXP

F19

PCIE2_TXN/USB3_6_TXN

H19

PCIE2_TXP/USB3_6_TXP

C22

PCIE3_RXN

A22

PCIE3_RXP

G22

PCIE3_TXN

J22

PCIE3_TXP

B21

PCIE4_RXN

D21

PCIE4_RXP

F21

PCIE4_TXN

H21

PCIE4_TXP

C24

PCIE5_RXN

A24

PCIE5_RXP

G24

PCIE5_TXN

J24

PCIE5_TXP

B23

PCIE6_RXN

D23

PCIE6_RXP

F23

PCIE6_TXN

H23

PCIE6_TXP

C26

PCIE7_RXN/SATA0_RXN

A26

PCIE7_RXP/SATA0_RXP

G26

PCIE7_TXN/SATA0_TXN

J26

PCIE7_TXP/SATA0_TXP

B25

PCIE8_RXN/SATA1A_RXN

D25

PCIE8_RXP/SATA1A_RXP

F25

PCIE8_TXN/SATA1A_TXN

H25

PCIE8_TXP/SATA1A_TXP

C28

PCIE9_RXN

A28

PCIE9_RXP

G28

PCIE9_TXN

J28

PCIE9_TXP

B27

PCIE10_RXN

D27

PCIE10_RXP

F27

PCIE10_TXN

H27

PCIE10_TXP

A9

PCIE_RCOMPN

B10

PCIE_RCOMPP

D51

PROC_PRDY*

B55

PROC_PREQ*

BF3

GPP_A7/PIRQA*

(IPU)
(IPU)

947915

SYM 8 OF 20

SSIC / USB3

PCIE/USB3/SATA

USB2

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_5
USB2P_5

USB2N_7
USB2P_7

USB2N_3
USB2P_3

USB2N_9
USB2P_9

USB2N_2
USB2P_2

(IPD)

USB2_COMP

(IPU)

USB2_VBUSSENSE

GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*

(IPD-RSMRST#)

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED*

USB2_ID

C16
A16
G16
J16

B15
D15
F15
H15

C18
A18
G18
J18

B17
D17
F17
H17

AJ6
AJ4

AH5
AH3

AF5
AF3

AL6
AL4

AG6
AG4

AM3
AM5

N2
AF7
AE6

N12
M11
F8
B8

F10
H10
L8

G11
J11
N10

H8

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

TP_USB3_EXTB_D2R_N
TP_USB3_EXTB_D2R_P
TP_USB3_EXTB_R2D_C_N
TP_USB3_EXTB_R2D_C_P

NC_USB3_EXTC_D2RN
NC_USB3_EXTC_D2RP
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_D2RN
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_R2D_CN
NC_USB3_EXTD_R2D_CP

USB_UPC_PCH_XA_N
USB_UPC_PCH_XA_P

TP_USB_5N
TP_USB_5P

TP_USB_7N
TP_USB_7P

TP_USB_EXTC_N
TP_USB_EXTC_P

TP_USB_9N
TP_USB_9P

USB_UPC_PCH_XB_N
USB_UPC_PCH_XB_P

PCH_USB2_COMP

USB2_VBUSSENSE
XDP_PCH_OBSDATA_B1

XDP_PCH_OBSDATA_B2
UPC_XA_FAULT_L
UPC_XB_FAULT_L

XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3

XDP_PCH_OBSDATA_B0

27

IN

27

IN

27

OUT

27

OUT

79

IN

79

IN

79

OUT

79

OUT

77

IN

77

IN

77

OUT

77

OUT

77

IN

77

IN

77

OUT

77

OUT

27

BI

27

BI

79

BI

79

BI

27

BI

27

BI

Grounded per SKL MOW 2015WW10

18

IN
IN

BI
BI

BI
BI
BI

BI
BI
BI

BI

18

18 16

18 16

18

18

18

18

18

18

18

1

R1620

1K

2

USB3 Port Assignments:

Ext A (SS, DCI)

Ext B (SS)

Unused

Unused
USB Port Assignments:

Ext A (LS/FS/HS)

Unused

Unused

Ext C (LS/FS/HS)

Unused

Ext B (LS/FS/HS)

5%
1/20W
MF
201

PLACE_NEAR=U0500.N2:2.54mm

1

R1622

113

1%
1/20W
MF
201

2

D

C

B

37

37

37 16

25

25

20

33

33

33 16

OUT
OUT
BI

OUT
OUT

IN

OUT
OUT

PCIE_CLK100M_SOC_N
PCIE_CLK100M_SOC_P
SOC_CLKREQ_L

PCIE_CLK100M_TBT_X_N
PCIE_CLK100M_TBT_X_P
TBT_X_CLKREQ_PCH_L

TP_PCIE_CLK100M3N
TP_PCIE_CLK100M3P
TP_PCH_SRCCLKREQ3_L

PCIE_CLK100M_PCH_WLAN_N
PCIE_CLK100M_PCH_WLAN_P
PCH_WLAN_CLKREQ_L

NC_PCIE_CLK100M_DEBUGN

77

NC_PCIE_CLK100M_DEBUGP

77

PU_DEBUG_CLKREQ_L

16 77

H35
F35
AV9

J36
G36

BD10

J38
G38
AV5

H37
F37
AV7

H39
F39
BC5

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

SYM 10 OF 20

CLOCK SIGNALS

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5*

BGA

947915

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST*

RTCRST*

J34
G34

BA15

M1
L2

P1

BN19
BP18

BH18
BN12

NC

PP1V_PRIM

PLACE_NEAR=U0500.P1:2.54mm

1

TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP

TP_PCH_CLK32K_SUS
PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT

OUT

IN

19

19

PCH_DIFFCLK_BIASREF
PMU_CLK32K_PCH_1V0 PMU_CLK32K_PCH

PCH_RTC_RESET_L

IN

65

R1662

2.7K

1%
1/20W
MF
201

2

R1672

127K

1%

1/20W

MF

201

R1673

100K

1%

1/20W

MF

1

2

201

PLACE_NEAR=U0500.B19:2.54mm
PLACE_NEAR=U0500.B19:2.54mm

75

21

IN

B

65

A

PP1V8_S5
PP3V3_S5

R1630
R1631
R1650
R1656
R1660

8

100K
100K

47K
47K
47K

21

5%

21

5%

21

5% MF1/20W

21
21

TP_PCH_SRCCLKREQ0_L

75

75

BB10

GPP_B5/SRCCLKREQ0*

SYNC_MASTER=J122_MLB

PAGE TITLE

SYNC_DATE=03/30/2018

A

PCH PCIe/USB/CLK

DRAWING NUMBER

051-04039

MF1/20W 201
MF1/20W 201

1/20W MF5%
1/20W MF5%

UPC_XB_FAULT_L
SOC_CLKREQ_L

201

PCH_WLAN_CLKREQ_L

201

PU_DEBUG_CLKREQ_L

201

UPC_XA_FAULT_L

16 18

16 18

37 16

33 16

16 77

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

16 OF 145

SHEET

16 OF 85

1

SIZE

D

79 42 20 15 6

IN

PLT_RST_L

678

3 245

1

CRITICAL

OMIT_TABLE

D

C

35

OUT

1

R1702

100K

5%
1/20W
MF
201

2

79 27 17

79 27 17

34 17

OUT

PCH_SOC_SYNC
SOC_PERST_L
TP_PCH_GPP_B17
PCH_STRP_NO_REBOOT

17

TP_PCH_GPP_B19
TP_PCH_GPP_B20
TP_PCH_GPP_B21

TP_PCH_STRP_BOOT_SPI_L

33 17

33 17

33 17

33 17

IN
OUT
OUT

IN

IN
OUT

PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
TP_PCH_GPP_C22
PCH_UART2_CTS_L

17

TP_PCH_GPP_C16
TP_PCH_GPP_C17

TP_PCH_GPP_C18
TP_PCH_GPP_C19

TP_PCH_GPP_F4
TP_PCH_GPP_F5

TP_PCH_GPP_F6
TP_PCH_GPP_F7

TP_PCH_GPP_F8
TP_PCH_GPP_F9

BC3

AW10

AW6
BB4

BB2

AW12

AW4
AW8

AC8

AA8
AA10
AA12

AD5

AD7

AD3

AD9

AD11

AB3

AB9
AB11

AP3

AP7

AP5

AT7

AN4

AN6

LPSS

GPP_B15/GSPI0_CS*
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS*
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS*
GPP_C11/UART0_CTS*

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS*
GPP_C23/UART2_CTS*

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

(IPD-PLTRST#)

(IPD-PLTRST#)

U0500

KBL-PCH-Y-QKKR

BGA

947915

SYM 6 OF 20

GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C15/UART1_CTS*/ISH_UART1_CTS*

ISH

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS*
GPP_D16/ISH_UART0_CTS*

/SML0BALERT*

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

SX_EXIT_HOLDOFF/GPP_A12

/BM_BUSY*/ISH_GP6

P11
T7
T5
T11

P7
P5

T9
T3

AM7
AT9

U10
U4
U6
V9

AC6
AC4
AB7
AB5

BF11
BD2
BJ1
BL3
BJ3
BD4
BJ4

TP_PCH_GPP_D9
TP_PCH_GPP_D10
TP_PCH_GPP_D11
TP_PCH_GPP_D12

TP_PCH_GPP_D5
TP_PCH_GPP_D6

TP_PCH_GPP_D7
TP_PCH_GPP_D8

TP_PCH_GPP_F10
TP_PCH_GPP_F11

MLB_RAMCFG0
MLB_RAMCFG1
MLB_RAMCFG2
MLB_RAMCFG3

TP_PCH_GPP_C12
TP_PCH_GPP_C13
TP_PCH_GPP_C14
TP_PCH_GPP_C15

TP_PCH_GPP_A18
TP_PCH_GPP_A19
TP_PCH_GPP_A20
TP_PCH_GPP_A21
TP_PCH_GPP_A22
TP_PCH_GPP_A23
TP_PCH_GPP_A12

D

17

17

17

17

C

B

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

H29
F29
F33
H33
J30
G30
J32
G32

D29
B29
C32
A32
C30
A30
D33
B33

D35
B35
C36
A36
D37
B37
C38
A38

CRITICAL

OMIT_TABLE

U0500

KBL-PCH-Y-QKKR

BGA

947915

H31
F31
D31
B31
C34
A34
D39
B39
A11
N4

AN12
AP9
AN10
AJ10
AM9
AL12
AJ12
AN8

AL10
AL8
AM11

BC1

NC
NC
NC
NC
NC
NC
NC
NC

TP_PCH_CSI2_COMP
TP_PCH_GPP_D4

TP_PCH_GPP_F13
TP_PCH_GPP_F14
PCH_WLAN_AUDIO_SYNC
TP_PCH_GPP_F16
TP_PCH_GPP_F17
TP_PCH_GPP_F18
TP_PCH_GPP_F19
TP_PCH_GPP_F20

TP_PCH_GPP_F21
PCH_BT_ROM_BOOT_L
TP_PCH_GPP_F12

TP_PCH_EMMC_RCOMP

OUT

IN

20 17

32 17

B

A

PP1V8_S5
PP1V8_S5
PP1V8_S5

R1704
R1710
R1711
R1712
R1713
R1714
R1715
R1740

R1700
R1717
R1783

1K
47K
47K
47K
47K
47K
47K

10K

100K

47K

100K

21
21
21
21
21
21
21
21

21
21
21

1/20W
1/20W 2015% MF
1/20W 2015% MF

1/20W
5% 1/20W
5% 1/20W

5% MF

1/20W MF

1/20W

9 75

9 14 75

9 75

MF 2015% 1/20W

2015% MF

2015% MF
MF 201
MF 201

2011/20W

2015%
MF5% 201
MF5% 1/20W 201

PCH_STRP_NO_REBOOT
PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
PCH_BT_ROM_BOOT_L

PCH_SOC_SYNC
PCH_UART2_CTS_L
PCH_WLAN_AUDIO_SYNC

17

17

RAM Configuration Straps

MLB_RAMCFG0

33 17

33 17

33 17

33 17

79 27 17

79 27 17

32 17

34 17

20 17

17

MLB_RAMCFG1

17

MLB_RAMCFG2

17

MLB_RAMCFG3

17

MLB_RAMCFG4

14

RAMCFG4_L

R1794

1K

5%

1/20W

MF

201

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

A

PCH GPIO/LPSS

RAMCFG3_L

1

2

R1793

1K

5%

1/20W

MF

201

1

2

R1792

1K

5%

1/20W

MF

201

1

2

RAMCFG1_LRAMCFG2_L

R1791

1K

5%

1/20W

MF

201

RAMCFG0_L

1

2

1K

5%

1/20W

MF

201

1

2

R1790

BOM_COST_GROUP=CPU & CHIPSET

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

17 OF 145

SHEET

17 OF 85

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

CPU_CFG<0>

6

CPU_CFG<1>

6

CPU_CFG<2>

6

CPU_CFG<3>

6

CPU_CFG<4>

6

CPU_CFG<5>

6

CPU_CFG<6>

6

CPU_CFG<7>

6

CPU_CFG<8>

6

CPU_CFG<9>

6

CPU_CFG<10>

6

CPU_CFG<11>

6

CPU_CFG<12>

6

CPU_CFG<13>

6

CPU_CFG<14>

6

CPU_CFG<15>

6

CPU_CFG<16>

6

CPU_CFG<17>

6

CPU_CFG<18>

6

CPU_CFG<19>

6

D

TP XDP Signals

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1800

PP

0.50MM

PP1801

PP

0.50MM

PP1802

PP

0.50MM

PP1803

PP

0.50MM

PP1804

PP

0.50MM

PP1805

PP

0.50MM

PP1806

PP

0.50MM

PP1807

PP

0.50MM

PP1808

PP

0.50MM

PP1809

PP

0.50MM

PP1810

PP

0.50MM

PP1811

PP

0.50MM

PP1812

PP

0.50MM

PP1813

PP

0.50MM

PP1814

PP

0.50MM

PP1815

PP

0.50MM

PP1816

PP

0.50MM

PP1817

PP

0.50MM

PP1818

PP

0.50MM

PP1819

PP

0.50MM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

XDP_CPU_PREQ_L

16

XDP_CPU_PRDY_L

16

ITP_PMODE

6

XDP_BPM_L<0>

6

IFDIM Trigger for DCDC

XDP_BPM_L<1>

6

XDP_BPM_L<2>

6

XDP_BPM_L<3>

6

XDP_PRESENT_L

35

NOSTUFF

R1895

100K

5%

1/20W

MF

201

NOSTUFF

R1894

100K

5%

1/20W

MF

201

1

1

1

1

1

2

1

1

1

PP1820

PP

0.50MM

PP1821

PP

0.50MM

PP1822

PP

0.50MM

PP1823

PP

0.50MM

PP1824

PP

0.50MM

PP1825

PP

0.50MM

PP1826

PP

0.50MM

SM

SM

SM

SM

SM

SM

SM

C

1

2

B

A

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture because it does not exist.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation, but also does not exist.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
Unused GPIOs have TPs.

PCH/XDP Signals Non-XDP Signals

16 6

BI OUT

16

BI

16

BI

6

BI

16

BI

16

BI

16

BI

14

BI

14

BI

14

BI

14

BI

16

BI

16

BI

16

BI

14

BI

6

BI

16

BI

XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
SPT_XDP_PCH_OBSDATA_C0
SPT_XDP_PCH_OBSDATA_C1
SPT_XDP_PCH_OBSDATA_C2
SPT_XDP_PCH_OBSDATA_C3
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
SPT_XDP_PCH_OBSDATA_D0
XDP_PCH_OBSFN_C1
UPC_XA_FAULT_L

UPC_XB_FAULT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1868

PP

PP1869

PP

PP1870

PP

PP1871

PP

PP1872

PP

PP1873

PP

PP1874

PP

PP1880

PP

PP1881

PP

PP1882

PP

PP1883

PP

PP1875

PP

PP1876

PP

PP1877

PP

PP1878

PP

PP1884

PP

MAKE_BASE=TRUE

PP1885

PP

MAKE_BASE=TRUE

PP1886

PP

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

0.50MM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

UPC_XA_FAULT_L

UPC_XB_FAULT_L

IN

INBI

28

29 16

PP1V_S0SW

JTAG Chain for DCI Only Connectivity

6

6

6

XDP_CPUPCH_TDO

IN

XDP_CPUPCH_TDO

OUT

XDP_CPUPCH_TCK

OUT

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TDO

XDP_CPUPCH_TCK

PLACE_NEAR=U0500.B51:28MM

PLACE_NEAR=U0500.D53:28MM

1

R1890

51

5%
1/20W
MF
201

2

6 8 12
75

XDP_CPUPCH_TCK

1

R1892

6

6

6

6

6

6

6

XDP_CPUPCH_TRST_L

OUT

XDP_CPUPCH_TRST_L

OUT

XDP_CPUPCH_TMS

OUT

XDP_CPUPCH_TMS

OUT

XDP_CPUPCH_TDI

OUT

XDP_CPUPCH_TDI

OUT

TP_XDP_PCH_TCK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS

XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

SYNC_MASTER=X589_CPU_CNL_Y

PAGE TITLE

2

51

5%
1/20W
MF
201

SYNC_DATE=03/13/2017

B

A

CPU/PCH Merged XDP

SIZE

D

BOM_COST_GROUP=DEBUG

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

18 OF 145

SHEET

18 OF 85

8

67

35 4

2

1

678

3 245

1

D

CRITICAL

C1900

7PF

21

+/-0.1PF

25V
CERM
0201

2
4

CRITICAL

C1901

7PF

21

+/-0.1PF

25V
CERM
0201

24MHz Crystal

PCH_CLK24M_XTALOUT_R

CRITICAL

1

Y1900

2.5X2.0MM-SM

24MHZ-10PPM-8PF-40OHM

3

R1900

0

21

5%

1/20W

MF

0201

PCH_CLK24M_XTALOUT

1

R1901

1M

5%
1/20W
MF
201

2

PCH_CLK24M_XTALIN

OUT

IN

16

D

16

C

59 19

IN

PP1V8_S5

75

ALL_SYS_PWRGD_R

VCCST_PWRGD Generation

BYPASS=U1920::5mm

C1920

0.1UF

10%

6.3V

CERM-X5R

0201

C

1

2

2

1

6

VCC

U1920

74AUP1G07GF

SOT891

GND

3

4

YA

NCNC

CPU_VCCST_PWRGD

5

NC

OUT

15

B

PP1V8_S5

75

42 35

65

IN

IN

ALL_SYS_PWRGD Qualifier

BYPASS=U1910::2MM

SMC_RSMRST_L
ALL_SYS_PWRGD

C1910

0.1UF

10%

6.3V

CERM-X5R

0201

B

1

U1910

2

VCC

2

A Y

1

B

5

NC

NC

GND

74AUP1G08GF

6

SOT891

3

4

ALL_SYS_PWRGD_R

1

R1911

1M

5%
1/20W
MF
201

2

OUT

59 19

A

8

NOSTUFF

R1910

0

21

5%

1/20W

MF

0201

SYNC_MASTER=X589_CPU_CNL_Y

PAGE TITLE

SYNC_DATE=03/27/2017

A

Chipset Shared Support

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

19 OF 145

SHEET

19 OF 85

1

SIZE

D

678

3 245

1

D

PP3V3_S5

75

PLTRST# 3.3V Level Shifter

BYPASS=U2030::2MM

10%

6.3V
0201

1

2

1

2

U2030

SN74AUP1T97

5

SON

4

6

3

1

R2030

100K

5%
1/20W
MF
201

2

OUTIN

C2030

0.1UF

CERM-X5R

PLT_RST_L

DP DDP Straps

PP3V3_S5

75

1

R2001

2.2K

5%
1/20W
MF
201

2

D

5%

1/20W

MF

201

1

2

R2000

2.2K

14 79 42 20 17 15 6

79 35

79 35

BI

DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO

MAKE_BASE=TRUE
MAKE_BASE=TRUE

DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO

IN

BI

27

27

5

OUT

5

OUT

PCH_DDPB_CTRLDATAPLT_RST_3V3_L
PCH_DDPC_CTRLDATA

C

16

79 25 15 14 5

OUT

IN

TBT X CLKREQ Level Shifter

PP1V8_S5

75

BYPASS=U2040::2MM

C2040

0.1UF

10%

6.3V

CERM-X5R

0201

TBT_X_CLKREQ_PCH_L

PM_SLP_S3_L

SAF Selector

NO_XNET_CONNECTION=1

R2092

0

5%
MF

0201

SAF

NC

21

Q2090

3

D

C

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

4

Y

PM_RSMRST

51

NCNC

R2093

100K

5%

1/20W

MF

201

1

2

SG

2

1

R2091

1K

5%
1/20W
MF
201

2

14

PP3V3_S5

BYPASS=U2040::2MM

1

1

2

8

VCCVL

1

C2041

0.1UF

10%

6.3V

2

CERM-X5R
0201

75

IN

75

U2040

NLSX4402

2
3

5

IO/VL1
IO/VL2

EN

UDFN

IO/VCC1
IO/VCC2

(10k IPUs)

GND

4

7

TBT_X_CLKREQ_L

6

NCNC

IN

25

42 15

IN

R2090

PM_RSMRST_L PM_RSMRST_RC_L SAF_SEL_S

5.6K

1/20W

5%
MF

201

21

SPI_PCHROM_IO<3> SPI_IO3_D

1/20W

PP3V3_S5

BYPASS=U2090::2MM

10%

6.3V
0201

1

2

2

A

NC

U2090
74AUP1G14

6

X2-DFN1010-6

VCC

GND

3

C2094

C2090

1000PF

10%
16V

X7R-1

0201

0.1UF

CERM-X5R

1

2

B

PP1V8_S5

75

79 34 32 17

79 42 20 17 15 6

WLAN_AUDIO_SYNC Isolation

BYPASS=U2050::5mm

10%

6.3V
0201

5%
MF

201

1

2

2

A

NOSTUFF

1

2

R2051

U2050

74AUP1G126GX

5

X2SON5

4

Y

OE

1

3

0

21

5%

1/20W

MF

0201

PCH_WLAN_AUDIO_SYNC

C2050

0.1UF

CERM-X5R

IN OUT

IN

WLAN_AUDIO_SYNC

PLT_RST_L

R2050

100K

1/20W

HDA_SDOUT

1

C2095

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

OUT

B

14

A

8

SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=03/07/2017

PAGE TITLE

A

Chipset Project Support

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

20 OF 145

SHEET

20 OF 85

1

SIZE

D

678

3 245

1

D

C

B

D

CPU-Based Margining

PP1V2_S3

VRef Dividers

R2223

10

1%
MF

201

10

1%
MF

201

5.1

1%
MF

0201

21

PLACE_NEAR=R2221.2:1mm

1%

1/20W

MF

201

1

2

R2222

8.2K

R2220

24.9

1/20W

21

PLACE_NEAR=R2241.2:1mm

21
1%
MF

201

R2242

8.2K

1%

1/20W

MF

201

1

2

R2240

24.9

1/20W

21

PLACE_NEAR=R2261.2:1mm

21
1%
MF

201

R2262

8.2K

1%

1/20W

MF

201

1

2

R2260

24.9

1/20W

1%
MF

201

21

7

CPU_DIMMA_VREFDQ

1/20W

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

7

IN

CPU_DIMMB_VREFDQ

1/20W

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

7

IN

CPU_DIMM_VREFCA

1/20W

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_A_RC

1

R2221

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

1

R2241

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

1

R2261

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

76

76

C

76

76

B

A

8

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

A

LPDDR3 VREF MARGINING

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

22 OF 145

SHEET

21 OF 85

1

SIZE

D

678

3 245

1

D

C

B

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 22 7

24 22 7

24 7

24 7

24 22 7

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

BI
BI

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

IN

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_ODT<0>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<10>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_DQS_P<1>
MEM_A_DQS_N<1>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>

CRITICAL

CA0_A
CA1_A
CA2_A
CA3_A

OMIT_TABLE

U2300

BGA

SYM 1 OF 2

CA4_A
CA5_A
CA6_A
CA7_A CA7_B

ELPIDA

CA8_A
CA9_A

CK_T_A
CK_C_A CK_C_B

32GB-LPDDR3X64

CS0_A*
CS1_A*

CKE0_A
CKE1_A

ODT_A

DM0_A
DM1_A
DM2_A
DM3_A

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A

DDR B

DQ9_A

DDR A

DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DQ16_A
DQ17_A
DQ18_A
DQ19_A
DQ20_A
DQ21_A
DQ22_A
DQ23_A
DQ24_A
DQ25_A
DQ26_A
DQ27_A
DQ28_A
DQ29_A
DQ30_A
DQ31_A

DQS0_T_A
DQS0_C_A

DQS1_T_A
DQS1_C_A

DQS2_T_A
DQS2_C_A

CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
CA6_B

CA8_B
CA9_B

CK_T_B

CS0_B*
CS1_B*

CKE0_B
CKE1_B

ODT_B

DM0_B
DM1_B
DM2_B
DM3_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B

DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DQ16_B
DQ17_B
DQ18_B
DQ19_B
DQ20_B
DQ21_B
DQ22_B
DQ23_B
DQ24_B
DQ25_B
DQ26_B
DQ27_B
DQ28_B
DQ29_B
DQ30_B
DQ31_B

DQS0_T_B
DQS0_C_B

DQS1_T_B
DQS1_C_B

DQS2_T_B
DQS2_C_B

BYPASS=U2300.A15::5mm

PP1V8_S3

23 66 75

L2B5
L3C5
L4D5
K2B6
K3C6
G3C9
G4D9
F2B10
F3C10
F4D10

H3B8
H2C8

K4D6
J2B7

J3C7
J4D7

H13N8

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>MEM_A_CAB<9>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_ODT<0>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

24 7

24 7

20%

6.3V
CERM
0402

20%

6.3V
CERM
0402

1

2

C2341

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.B17::5mm

1

2

C2351

10UF

20%

6.3V
CERM
0402

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 22 7

24 22 7

PP1V2_S3

23 76

C2340

10UF

C2350

10UF

24 7

24 7

24 22 7

H14N6
F13P8
L14P4
D14P11

L15N4
L16T5
K13R5
K14P5
K15N5
K16T6
J15R6
J16P6
F14T9
F15R9
F16T10
E13R10
E14P10
E15N10
E16T11
D13R11
P15T2
P16R2
N14P2
N15N2
N16T3
M13R3
M14P3
L13N3
C13N11
C14N12
C15P12
C16T13
B13R13
B14P13
B15T14
B16R14

J14P7
J13N7

G14P9
G13N9

M16T4
M15R4

MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<43>
MEM_A_DQ<45>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<57>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQ<63>
MEM_A_DQ<59>
MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<58>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

MEM_A_DQS_P<5>
MEM_A_DQS_N<5>

MEM_A_DQS_P<6>
MEM_A_DQS_N<6>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

BI
BI

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

PP1V2_S3

23 76

PP1V2_S3

23 76

C2370

10UF

20%

6.3V
CERM
0402

C2380

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.A9::5mm

1

2

C2371

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.A13::5mm

1

2

C2385

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.T16::5mm

1

2

C2342

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.U2::5mm

1

2

C2352

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.G2::5mm

1

2

C2372

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.K17::5mm

1

2

C2390

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.B2::5mm

1

2

BYPASS=U2300.A11::5mm

1

2

BYPASS=U2300.K1::5mm

1

2

BYPASS=U2300.U10::5mm

1

2

C2343

10UF

20%

6.3V
CERM
0402

C2353

10UF

20%

6.3V
CERM
0402

BYPASS=U2300.T1::5mm

1

2

BYPASS=U2300.R15::5mm

1

2

CRITICAL

R1

VDD1_A/B VSS_A/B

T1

VDD1_A/B

B2

VDD1_A/B

A15

VDD1_A/B

A16

VDD1_A/B

T16

VDD1_A/B

OMIT_TABLE

U2300

BGA

SYM 2 OF 2

ELPIDA

32GB-LPDDR3X64

H1

VDD2_A/B

L1

VDD2_A/B

U2

VDD2_A/B

C3

VDD2_A/B

U3

VDD2_A/B

R15

VDD2_A/B

H16

VDD2_A/B

B17

VDD2_A/B

C17

VDD2_A/B

A7

VDD2_A/B

T8

VDD2_A/B

A11

VDD2_A/B

A6

VDDCA_A/B

E1

VDDCA_A/B

K1

VDDCA_A/B

G2

VDDCA_A/B

A9

VDDCA_A/B

B9

VDDCA_A/B

N1

VDDQ_A/B

M2

VDDQ_A/B

M3

VDDQ_A/B

U5

VDDQ_A/B

B12

VDDQ_A/B

C12

VDDQ_A/B

G12

VDDQ_A/B

K12

VDDQ_A/B

M12

VDDQ_A/B

A13

VDDQ_A/B

U14

VDDQ_A/B

E17

VDDQ_A/B

G17

VDDQ_A/B

K17

VDDQ_A/B

L17

VDDQ_A/B

P17

VDDQ_A/B

M7

VDDQ_A/B

U7

VDDQ_A/B

M10

VDDQ_A/B

U10

VDDQ_A/B

U11

VDDQ_A/B

VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B
VSS_A/B

B1
C1
D1
F1
G1
M1
P1
A2
C2
D2
A3
B3
D3
A4
B4
C4
D4
M4
U4
A5
E5
F5
G5
H5
J5
K5
L5
M5
A12
D12
E12
F12
H12
L12
U12
N13
U13
A14
P14
G15
H15
T15
U15
G16
R16
U16
D17
F17
J17
M17
N17
R17
T17
E6
M6
U6
E7
R7
T7
A8
E8
M8
R8
E9
U9
E10
E11
M11

D

C

B

A

PPVREF_S3_MEM_VREFCA

22 76

PPVREF_S3_MEM_VREFDQ_A

22 76

78

78

R2300

243

1%

1/20W

MF

201

NC
NC
NC
NC
NC
NC

1

2

D16T12
D15R12

E2B11

J1A10
H17U8

A17A1
U17U1
D8
M9
C11
D11

C2331

0.047UF

NC
NC
NC
NC

NC

6.3V

BI
BI

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

MEM_A_ZQ_B MEM_A_ZQ_A

DQS3_T_A
DQS3_C_A

ZQ_A

VREFCA_A
VREFDQ_A

E3
E4
H4

J12

NC
NC
NC
NC
NC
NC

1

C2312

0.1UF

10%

2

CERM-X5R
0201

NC
NC

MEM_A_ZQ1_A

NC
NC

RAM_16GB

1

2

1

R2321

243

1%
1/20W
MF
201

2

C2310

0.047UF

10%

6.3V
X5R
201

1

2

1

2

NC

C2311

0.047UF

10%

6.3V
X5R
201

DQS3_T_B
DQS3_C_B

ZQ_B

VREFCA_B
VREFDQ_B

C2332

0.1UF

10%

6.3V6.3V

CERM-X5R

0201

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

1

C2330

0.047UF

10%

6.3V

2

X5R
201

10%
X5R

201

1

2

MEM_A_ZQ1_B

RAM_16GB

R2301

243

1%

1/20W

MF

201

78

BI

78

BI

PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ_A

1

2

1

R2320

243

1%
1/20W
MF
201

2

22 76

22 76

PAGE TITLE

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

LPDDR3 DRAM Channel A (0-63)

SIZE

D

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

A

2.0.0

BRANCH

PAGE

23 OF 145

SHEET

22 OF 85

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

C

B

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 23 7

24 23 7

24 7

24 7

24 23 7

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

BI
BI

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

CRITICAL

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

MEM_B_CLK_P<1>

CA0_A
CA1_A
CA2_A
CA3_A

OMIT_TABLE

U2500

BGA

SYM 1 OF 2

CA4_A
CA5_A
CA6_A
CA7_A CA7_B

ELPIDA

CA8_A
CA9_A

CK_T_A
CK_C_A CK_C_B

32GB-LPDDR3X64

CS0_A*

MEM_B_CS_L<1>

MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_ODT<0> MEM_B_ODT<0>

CS1_A*

CKE0_A
CKE1_A

ODT_A

DM0_A
DM1_A
DM2_A
DM3_A

MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<4>
MEM_B_DQ<1>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<7>
MEM_B_DQ<3>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<8>
MEM_B_DQ<12>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<41>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<40>
MEM_B_DQ<44>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_DQS_P<1>
MEM_B_DQS_N<1>

MEM_B_DQS_P<4>
MEM_B_DQS_N<4>

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DQ16_A
DQ17_A
DQ18_A
DQ19_A
DQ20_A
DQ21_A
DQ22_A
DQ23_A
DQ24_A
DQ25_A
DQ26_A
DQ27_A
DQ28_A
DQ29_A
DQ30_A
DQ31_A

DQS0_T_A
DQS0_C_A

DQS1_T_A
DQS1_C_A

DQS2_T_A
DQS2_C_A

DDR B

DDR A

CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
CA6_B

CA8_B
CA9_B

CK_T_B

CS0_B*
CS1_B*

CKE0_B
CKE1_B

ODT_B

DM0_B
DM1_B
DM2_B
DM3_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B

DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DQ16_B
DQ17_B
DQ18_B
DQ19_B
DQ20_B
DQ21_B
DQ22_B
DQ23_B
DQ24_B
DQ25_B
DQ26_B
DQ27_B
DQ28_B
DQ29_B
DQ30_B
DQ31_B

DQS0_T_B
DQS0_C_B

DQS1_T_B
DQS1_C_B

DQS2_T_B
DQS2_C_B

L2B5
L3C5
L4D5
K2B6
K3C6
G3C9
G4D9
F2B10
F3C10
F4D10

H3B8
H2C8

K4D6
J2B7

J3C7
J4D7

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>MEM_B_CLK_N<1>

MEM_B_CS_L<0>MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_CKE<0>
MEM_B_CKE<1>

H13N8

H14N6
F13P8
L14P4
D14P11

L15N4
L16T5
K13R5
K14P5
K15N5
K16T6
J15R6
J16P6
F14T9
F15R9
F16T10
E13R10
E14P10
E15N10
E16T11
D13R11
P15T2
P16R2
N14P2
N15N2
N16T3
M13R3
M14P3
L13N3
C13N11
C14N12
C15P12
C16T13
B13R13
B14P13
B15T14
B16R14

J14P7
J13N7

G14P9
G13N9

M16T4
M15R4

MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<58>
MEM_B_DQ<63>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>

MEM_B_DQS_P<6>
MEM_B_DQS_N<6>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

BI
BI

BI
BI

BYPASS=U2500.A15::5mm

PP1V8_S3

22 66 75

24 7

24 7

20%

6.3V
CERM
0402

1

2

24 7

24 7

24 7

24 7

24 7

24 7

24 7

24 7

C2540

10UF

C2541

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.T16::5mm

1

2

C2542

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.B2::5mm

1

2

C2543

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.T1::5mm

1

2

R1
T1

B2
A15
A16
T16

CRITICAL

OMIT_TABLE

U2500

BGA

ELPIDA

B1
C1
D1
F1
G1
M1
P1
A2
C2
D2

D

A3

24 7

24 7

24 23 7

24 23 7

24 7

24 7

PP1V2_S3

22 76

C2550

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.B17::5mm

1

2

C2551

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.U2::5mm

1

2

C2552

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.A11::5mm

1

2

C2553

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.R15::5mm

1

2

H1

L1

U2

C3

U3
R15

32GB-LPDDR3X64

H16

24 23 7

B17
C17

A7

T8
A11

B3
D3
A4
B4
C4
D4
M4
U4
A5
E5
F5
G5
H5
J5
K5
L5

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

PP1V2_S3

22 76

PP1V2_S3

22 76

C2570

10UF

20%

6.3V
CERM
0402

C2580

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.A9::5mm

1

2

C2571

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.A13::5mm

1

2

C2585

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.G2::5mm

1

2

BYPASS=U2500.K17::5mm

1

2

C2572

10UF

20%

6.3V
CERM
0402

C2590

10UF

20%

6.3V
CERM
0402

BYPASS=U2500.E1::5mm

1

2

BYPASS=U2500.U10::5mm

1

2

A6

E1

K1

G2

A9

B9

N1
M2
M3

U5
B12
C12
G12
K12
M12
A13
U14
E17
G17
K17
L17
P17

M7

U7
M10
U10
U11

M5
A12
D12
E12
F12
H12
L12
U12
N13
U13
A14
P14
G15
H15
T15
U15
G16
R16
U16
D17
F17
J17
M17
N17
R17
T17
E6
M6
U6
E7
R7
T7
A8
E8
M8
R8
E9
U9
E10
E11
M11

C

B

A

PPVREF_S3_MEM_VREFCA

23 76

PPVREF_S3_MEM_VREFDQ_B

23 76

78

78

R2500

243

1%

1/20W

MF

201

NC
NC
NC
NC
NC
NC

1

2

D16T12
D15R12

E2B11

J1A10
H17U8

A17A1
U17U1
D8
M9
C11
D11

C2531

0.047UF

NC
NC
NC
NC

NC

6.3V

BI
BI

MEM_B_DQS_P<5>
MEM_B_DQS_N<5>

MEM_B_ZQ_B MEM_B_ZQ_A

DQS3_T_A
DQS3_C_A

ZQ_A

VREFCA_A
VREFDQ_A

E3
E4
H4

J12

NC
NC
NC
NC
NC
NC

1

C2512

0.1UF

10%

6.3V

2

CERM-X5R
0201

NC
NC

MEM_B_ZQ1_A

NC
NC

RAM_16GB

1

2

1

R2521

243

1%
1/20W
MF
201

2

C2510

0.047UF

10%

6.3V
X5R
201

1

2

1

2

NC

C2511

0.047UF

10%

6.3V
X5R
201

DQS3_T_B
DQS3_C_B

ZQ_B

VREFCA_B
VREFDQ_B

C2532

0.1UF

10%

6.3V

CERM-X5R

0201

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

1

C2530

0.047UF

10%

6.3V

2

X5R
201

10%
X5R

201

1

2

MEM_B_ZQ1_B

RAM_16GB

R2501

243

1/20W

1%
MF

201

78

BI

78

BI

PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ_B

1

2

1

R2520

243

1%
1/20W
MF
201

2

23 76

23 76

PAGE TITLE

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

LPDDR3 DRAM Channel B (0-63)

SIZE

D

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

A

2.0.0

BRANCH

PAGE

25 OF 145

SHEET

23 OF 85

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

C

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

76

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

22 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_A_CAA<9>
MEM_A_CAA<8>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<5>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_CAA<4>
MEM_A_CAA<3>
MEM_A_CAA<2>
MEM_A_CAA<1>
MEM_A_CAA<0>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<5>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_CAB<4>
MEM_A_CAB<2>

MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>

R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730

68
68
68
68
68

38.3

38.3

80.6

80.6
68
68
68
68
68
68
68
68
68
68

38.3

38.3

80.6

80.6
68
68
68
68
68

80.6

80.6

80.6

21
21
21
21
21

21

1% 1/32W TK01005

21

1% 1/32W TK01005

21
21
21
21
21
21
21
21
21
21
21
21

21
21

21
21
21
21
21
21
21
21

1% 1/32W MF

21
21

TK010051/32W1%
TK010051/32W1%
TK1% 010051/32W
TK010051/32W1%
TK1/32W 010051%

010051% 1/32W MF

MF010051% 1/32W
TK010051% 1/32W
TK010051% 1/32W
TK1% 1/32W 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005

TK1/32W1% 01005
01005 TK1/32W1%
01005 TK1/32W1%

MF1/32W1% 01005
010051% 1/32W MF

TK010051% 1/32W

TK1/32W1% 01005

TK1/32W1% 01005

TK1/32W1% 01005

TK1/32W1% 01005
01005
010051% 1/32W MF
010051% 1/32W MF

1

C2700

0.47UF

2

1

C2701

0.47UF

2

1

C2703

0.47UF

2

1

C2705

0.47UF

2

1

C2707

0.47UF

2

1

C2709

0.47UF

2

20%
4V
CERM-X5R-1
201

20%
4V
CERM-X5R-1
201

20%
4V
CERM-X5R-1
201

20%
4V
CERM-X5R-1
201

20%
4V
CERM-X5R-1
201

20%
4V
CERM-X5R-1
201

1

C2730

12PF

5%
25V

2

NP0-C0G
0201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

23 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<4>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_CAB<4>
MEM_B_CAB<2>
MEM_B_CAB<3>MEM_A_CAB<3>
MEM_B_CAB<1>
MEM_B_CAB<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>

R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770

68
68
68
68
68

38.3

38.3

80.6

80.6
68
68
68
68
68
68
68
68
68
68

38.3

38.3

80.6

80.6
68
68
68
68
68

80.6

80.6

80.6

PP0V6_S0_DDRVTT

76

21
21
21
21
21

21

1% 1/32W TK01005

21

1% 1/32W TK01005

21
21
21
21
21
21
21
21
21
21
21
21

21

1% 1/32W TK01005

21

1% 1/32W TK01005

21
21
21
21
21
21
21
21
21
21

TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK010051% 1/32W

010051% 1/32W MF
010051% 1/32W MF

TK010051% 1/32W
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005

010051% 1/32W MF
010051% 1/32W MF

TK010051% 1/32W
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
TK1/32W1% 01005
MF1/32W1% 01005
MF1/32W1% 01005

010051% 1/32W MF

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2711

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2713

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2715

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2717

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2719

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2731

12PF

5%
25V

2

NP0-C0G
0201

1

C2712

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2714

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2716

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2718

0.47UF

20%
4V

2

CERM-X5R-1
201

D

C

B

CRITICAL

1

C2720

20UF

20%

6.3V

2

CERM-X5R
0402

1

C2722

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

1

C2740

20UF

20%

6.3V

2

CERM-X5R
0402

1

C2742

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

B

A

8

SYNC_MASTER=T290_CARD_CPU_U SYNC_DATE=04/06/2018

PAGE TITLE

A

LPDDR3 DRAM Termination

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

27 OF 145

SHEET

24 OF 85

1

SIZE

D

678

3 245

1

D

C

B

A

1

R2890

3.3K

5%
1/20W
MF
201

2

PP3V3_TBT_X_SX

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

TBT_X_SPI_CLK

27

TBT_X_SPI_CS_L

27

TBT_X_ROM_WP_L

25

TBT_X_ROM_HOLD_L

DP_X_SNK1_ML_C_P<0>

IN

DP_X_SNK1_ML_C_N<0>

IN

DP_X_SNK1_ML_C_P<1>

IN

DP_X_SNK1_ML_C_N<1>

IN

DP_X_SNK1_ML_C_P<2>

IN

DP_X_SNK1_ML_C_N<2>

IN

DP_X_SNK1_ML_C_P<3>

IN

DP_X_SNK1_ML_C_N<3>

IN

BI

BI

BI

BI

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

DP_X_SNK0_ML_C_P<0>

IN

DP_X_SNK0_ML_C_N<0>

IN

DP_X_SNK0_ML_C_P<1>

IN

DP_X_SNK0_ML_C_N<1>

IN

DP_X_SNK0_ML_C_P<2>

IN

DP_X_SNK0_ML_C_N<2>

IN

DP_X_SNK0_ML_C_P<3>

IN

DP_X_SNK0_ML_C_N<3>

IN

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

100K

10K

100K

100K

100K

100K

100K

100K

21

21

21

21

21

21

21

21

R2866
R2864
R2863
R2865
R2860
R2870
R2862
R2872

R2891

3.3K

MF

1

5%

1/20W

MF

201

2

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

2011/20W5%

NOSTUFF

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

PP3V3_UPC_XB_LDO

1

R2893

3.3K

5%
1/20W
MF
201

2

8

VCC

U2890

8MBIT-3.0V

W25Q80DVUXIE

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

USON

OMIT_TABLE

CRITICAL

GND EPAD

9

4

SNK1 AC Coupling

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

C2828

0.1UF

C2829

0.1UF

SNK0 AC Coupling

C2830

0.22UF

C2831

0.22UF

C2832

0.22UF

C2833

0.22UF

C2834

0.22UF

C2835

0.22UF

C2836

0.22UF

C2837

0.22UF

C2838

0.1UF

C2839

0.1UF

67 27 26 25

TBT_X_BATLOW_L

TBT_X_TMU_CLK_IN

TBT_X_TMU_CLK_OUT

TBT_XA_USB2_MXCTL

TBT_XB_USB2_MXCTL

DP_XA_HPD

DP_XB_HPD

R2892

3.3K

5%

1/20W

MF

201

DI(IO0)
DO(IO1)

21

21

20%
X5R

21

X5R 0201

21

21

20%

21

21

21

X5R

21

0201 CERM-X5R

21

0201

21

X5R

21

20%
X5R

21

20%
X5R

21

20%
X5R

21

20%
X5R

21

X5R

21

X5R

21

21

0201 CERM-X5R

21

0201

25

25

25

25

25

25 28

25 29

5
2

6.3V20%
0201X5R

6.3V
0201

6.3V20%

6.3V20%
0201X5R

6.3V
0201X5R

6.3V20%
0201X5R

6.3V20%
0201X5R

6.3V20%
0201

6.3V10%

6.3V10%
CERM-X5R

6.3V20%

0201

6.3V

0201

6.3V

0201

6.3V

0201

6.3V

0201

6.3V20%

0201

6.3V20%

0201

6.3V20%

0201X5R

6.3V10%

6.3V10%
CERM-X5R

27

1

2

1

C2890

1UF

10%
10V

2

X5R
402-1

TBT_X_SPI_MOSI
TBT_X_SPI_MISO

DP_X_SNK1_ML_P<0>

DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>

DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>

DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>

DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P

DP_X_SNK1_AUXCH_N

DP_X_SNK0_ML_P<0>

DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

DP_X_SNK0_AUXCH_N

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

27

27

PCIE_TBT_X_R2D_P<0>

IN

PCIE_TBT_X_R2D_N<0>

IN

PCIE_TBT_X_R2D_P<1>

IN

PCIE_TBT_X_R2D_N<1>

IN

PCIE_TBT_X_R2D_P<2>

IN

PCIE_TBT_X_R2D_N<2>

IN

PCIE_TBT_X_R2D_P<3>

IN

PCIE_TBT_X_R2D_N<3>

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_R_L

DP_X_SNK0_ML_P<0>

25

DP_X_SNK0_ML_N<0>

25

DP_X_SNK0_ML_P<1>

25

DP_X_SNK0_ML_N<1>

25

DP_X_SNK0_ML_P<2>

25

DP_X_SNK0_ML_N<2>

25

DP_X_SNK0_ML_P<3>

25

DP_X_SNK0_ML_N<3>

25

DP_X_SNK0_AUXCH_P

25

DP_X_SNK0_AUXCH_N

25

DP_X_SNK0_HPD
DP_X_SNK1_ML_P<0>

25

DP_X_SNK1_ML_N<0>

25

DP_X_SNK1_ML_P<1>

25

DP_X_SNK1_ML_N<1>

25

DP_X_SNK1_ML_P<2>

25

DP_X_SNK1_ML_N<2>

25

DP_X_SNK1_ML_P<3>

25

DP_X_SNK1_ML_N<3>

25

DP_X_SNK1_AUXCH_P

25

DP_X_SNK1_AUXCH_N

25

DP_X_SNK1_HPD

IN
IN
IN

OUT

JTAG_ISP_TDI
JTAG_TBT_X_TMS
JTAG_ISP_TCK
JTAG_ISP_TDO

NC
NC
NC
NC

20

TBT_X_CLKREQ_L

OUT

<rdar://problem/42880020>

27

OUT

R2830

100K

1/20W

201

27

OUT

R2831

100K

1/20W

201

5%
MF

5%
MF

R2828

1

2

1

2

100

5%

1/20W

MF

201

27

27

27

27

27

27

27

27

16

16

21

14

14 27

14

14

TBT_X_TEST_EN

TBT_X_TEST_PWR_GOOD

100

5%

1/20W

MF

201

5%

1/20W

MF

201

1

2

1

2

30

30

30

30

30

30

30

30

28

28

25 28

IN
IN

OUT
OUT

OUT
OUT

IN
IN

BI
BI

IN

USBC_XA_D2R_P<2>
USBC_XA_D2R_N<2>

USBC_XA_R2D_CR_P<2>
USBC_XA_R2D_CR_N<2>

USBC_XA_R2D_CR_P<1>
USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>
USBC_XA_D2R_N<1>

USBC_XA_AUXLSX1
USBC_XA_AUXLSX2

NC
NC

DP_XA_HPD

I2C_TBT_XA_INT_L

TBT_XA_USB2_MXCTL

25

67 27 26 25

100

5%

1/20W

MF

201

1

2

R2825

PP3V3_TBT_X_SX

NOSTUFF

R2829

R2836

2.2K

27 27

TBT_XA_USB2_RBIAS

PLACE_NEAR=U2800.H19:2MM

200

1%

1/20W

MF

201

1

TBT_X_RBIAS

2

TF 1/20W

R2855

PLACE_NEAR=U2800.H6:2MM

PLACE_NEAR=U2800.J6:2MM

21

TBT_X_RSENSE

4.75K

0.5%
0201

R2854

Y23
Y22

T23
T22

M23
M22

H23
H22

V19
T19

AC7
AB7

AB9
AC9

AC11
AB11

AB13
AC13

N1
N2

AA2

A5
B5

B3
A3

C2
C1

E2
E1

P1
P2

Y4

AC5
AB5
AC3
AB3

W20
Y20
W19
Y19

R4
W5

A15
B15

A17
B17

A19
B19

B21
A21

H4
J4

E20
D20

T2

M4

R2

H19

J6
J5

A23

A1

AC23

AC1

D4

L8

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*

DPSNK1_ML0_P
DPSNK1_ML0_N

DPSNK1_ML1_P
DPSNK1_ML1_N

DPSNK1_ML2_P
DPSNK1_ML2_N

DPSNK1_ML3_P
DPSNK1_ML3_N

DPSNK1_AUX_P
DPSNK1_AUX_N

SNK1_HPD

DPSNK2_ML0_P
DPSNK2_ML0_N

DPSNK2_ML1_P
DPSNK2_ML1_N

DPSNK2_ML2_P
DPSNK2_ML2_N

DPSNK2_ML3_P
DPSNK2_ML3_N

DPSNK2_AUX_P
DPSNK2_AUX_N

SNK2_HPD

U0_SSTXP1
U0_SSTXN1
U0_SSRXP1
U0_SSRXN1

TDI
TMS
TCK
TDO

TEST_EN
TEST_PWR_GOOD

ASSRXP2
ASSRXN2

ASSTXP2
ASSTXN2

ASSTXP1
ASSTXN1

ASSRXP1
ASSRXN1

ASBU1
ASBU2

PA_USB2_D_P
PA_USB2_D_N

PA_HPD

PA_I2C_INT

PA_USB2_MXCTL
PA_USB2_RBIAS

RBIAS
RSENSE

PA_MONDC

PB_MONDC

PC_MONDC

USB_MONDC

TEST_EDM

FUSE_VQPS_64

U2800

TITAN-RIDGE-DP

CSP

SYM 1 OF 2

OMIT_TABLE

CRITICAL

PCIE GEN3

SINK PORT 1SINK PORT 2

USBSSJTAG

TBT PORT A

DEBUG

SOURCE PORT

LC GPIOPOC GPIOFLASH

TBT PORT B

PCIE_TX0_P
PCIE_TX0_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_TX3_P
PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P
DPSRC_ML0_N

DPSRC_ML1_P
DPSRC_ML1_N

DPSRC_ML2_P
DPSRC_ML2_N

DPSRC_ML3_P
DPSRC_ML3_N

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD

GPIO_0
GPIO_1

EE_WP*

TMU_CLKOUT

WAKE*

CIO_PLUG_EVENT*

TMU_CLKIN

I2C_SCL
I2C_SDA

USB_FORCE_PWR

FORCE_PWR

BATLOW*
SLP_S3*

RTD3_PWR_EN

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI
EE_DO

EE_CS*

EE_CLK

BSSRXp2
BSSRXn2

BSSTXp2
BSSTXn2

BSSTXp1
BSSTXn1

BSSRXp1
BSSRXn1

BSBU1
BSBU2

PB_USB2_D_P
PB_USB2_D_N

PB_HPD

PB_I2C_INT
PB_USB2_MXCTL
PB_USB2_RBIAS

USB2_ATEST

PCIE_ATEST

MONDC_SVR

VGA_RES

ATEST_P
ATEST_N

THERMDA

V23
V22

P23
P22

K23
K22

F23
F22

T4

N16Y6

AB21
AC21

AC19
AB19

AB17
AC17

AC15
AB15

N4
N5

R5

W1
W2

W4
Y1
Y2
AA1
W6

V2
V1
V5
V4
U2
U1
T5

E5

D22
D23

Y18
W16
W18
Y16

B7
A7

A9
B9

A11
B11

A13
B13

L4
L5

E19
D19

T1

M5

R1
F19

B23

AB23

D5

H5

J9
J11

V8

PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS

NC_DP_X_SRC_MLP<0>
NC_DP_X_SRC_MLN<0>

NC_DP_X_SRC_MLP<1>
NC_DP_X_SRC_MLN<1>

NC_DP_X_SRC_MLP<2>
NC_DP_X_SRC_MLN<2>

NC_DP_X_SRC_MLP<3>
NC_DP_X_SRC_MLN<3>

NC_DP_X_SRC_AUXP
NC_DP_X_SRC_AUXN

PD_DP_X_SRC_HPD
PD_TBT_X_GPIO_0

PU_TBT_X_GPIO_1
TBT_X_ROM_WP_L
TBT_X_TMU_CLK_OUT
TBT_WAKE_3V3_L
TBT_X_PLUG_EVENT_L
TBT_X_TMU_CLK_IN

I2C_TBT_X_SCL
I2C_TBT_X_SDA
TBT_X_USB_PWR_EN
TBT_X_CIO_PWR_EN
TBT_X_BATLOW_L
PM_SLP_S3_L
RTD3_PWR_EN

USBC_X_RESET_L
TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT
UPC_X_SPI_MOSI

UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK

USBC_XB_D2R_P<2>
USBC_XB_D2R_N<2>

USBC_XB_R2D_CR_P<2>
USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<1>
USBC_XB_R2D_CR_N<1>

USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>

USBC_XB_AUXLSX1
USBC_XB_AUXLSX2

NC
NC

DP_XB_HPD
I2C_TBT_XB_INT_L
TBT_XB_USB2_MXCTL
TBT_XB_USB2_RBIAS

NC

NC

NC

NC
NC

TBT_X_THERM_D_P

USE NEAREST GND BALL

(XXXX) FOR THERM_D_N

PU at PCH
PU at PCH

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

27

OUT
OUT

25

25

OUT
OUT

25

IN
IN

25

IN

IN

IN

OUT

27

27

27

27

IN
IN

OUT
OUT

OUT
OUT

IN
IN

BI
BI

IN

25

OUT

27

27

27

27

27

27

27

27

14 27

1

27

27

27

27

27

27

27

27

27

27

27

27

27

5 27

14 27 28 29

14 27 28 29

5 14 15 20 79

27

27

27

To SPI Flash

30

30

30

30

30

30

30

30

29

29

25 29

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

50

2

1

2

PP3V3_TBT_X_SX

1

2

1

2

R2851

3.01K

1%
1/20W
MF
201

PP3V3_TBT_X_SX

R2834

2.2K

5%
1/20W
MF
201

27

BI

R2837

2.2K

5%
1/20W
MF
201

PLACE_NEAR=U2800.F19:2MM

1

R2835

2.2K

5%
1/20W
MF
201

2

BI

NOSTUFF

27

ININ

R2853

200

1%
1/20W
MF
201

USB-C HIGH SPEED 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=TBT

IV ALL RIGHTS RESERVED

1

R2827

100K

5%
1/20W
MF
201

2

67 27 26 25

DRAWING NUMBER

051-04039

REVISION

BRANCH

PAGE

28 OF 145

SHEET

25 OF 85

67 27 26 25

SYNC_DATE=02/13/2017

2.0.0

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

B

A

26

PP0V9_TBT_X_SVR

1

C2930

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

SOURCED BY

INTERNAL SWITCH INTERNAL SWITCH INTERNAL SWITCH

1

C2984

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2931

1.0UF

20%

6.3V

2

X5R

1

C2932

1.0UF

20%

6.3V

2

X5R
0201-10201-1

1

C2964

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2933

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2965

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2934

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

1

C2966

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

1

C2920

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2935

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2936

1.0UF

20%

6.3V

2

X5R
0201-1

PP0V9_TBT_X_PCIE

1

C2968

10UF

20%

6.3V

2

CERM
0402

PP3V3_TBT_X_ANA

27

27

PP3V3_TBT_X_ANA_PCIE
PP3V3_TBT_X_ANA_USB2

SOURCED BYSOURCED BY

1

C2921

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.0750

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

H11

H9
H12
H13
H15
H16

T12
T13
T15

N6

T11

T9

E8

J18

L19
M19

L18
M18
M16

E16
L16
H18

W11
Y11

Y5
W12
Y12

Y8
AB4
AC4
C23
C22
W13
AB2

D6
W15
Y15

A4

B4

F2

D2

F1

D1

B1

B2
E18
V11
V12
V13

M6
N19
N18
E12
E13
F11
F12
F13
F15
J16

A2

F8

A6

A8

B8
AB8

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC6
AC8
B10

AC10
AC12
AC14
AC16
AC18
AC20
AC22

B12

B14
B16
B18
B20
B22

D8

D9
A10
D11
D12

VCC0P9_SVR_PAB_ANA

VCC0P9_SVR_PC_ANA

VCC0P9_SVR_DPAUX_ANA

VCC0P9_SVR_USB_ANA

VCC0P9_SVR_BRD_SENSE

VCC0P9_PCIE

VCC0P9_ANA_PCIE_1

VCC0P9_ANA_PCIE_2

VCC3P3_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

N15

VSS

L15

V18

VSS

VSS

F4

VSS

R9

U2800

TITAN-RIDGE-DP

CSP

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M9

L9

R12

L12

M15

R15

VSS

M1

VCC3P3_SVR

VCC0P9_SVR

VCC0P9_LVR_SENSE

VSS

VSS

VSS

VSS

V16

M12

N9

N12

M2

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

SVR_IND

SVR_VSS

VCC0P9_LC

VCC0P9_LVR

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS

VSS

VSS

T6

T18

V6

F18
R6

L6

E6

G1
G2
H2

R8
R11
L11
M8
M13
R16
R13
J13
L13
N8
N11
N13
T8
T16
M11

L1
L2
K1
K2

J1
J2
H1

J8
H8
H6

D13

D15
D16
D18
E9
E11
E15
A12
E22
E23
F9
F20
F16
G22
G23
A14
H20
J19
J20
J22
A16
J23
L20
L22
L23
A18
M20
N20
N22
N23
R18
A20
R19
R20
R22
R23
T20
U23
U22
A22
V9
V15
V20
W8
B6
W9
W22
W23
Y9
Y13
AA22
AA23
AB6
E4
J15
AB1
AC2
F5
F6
J12

PP3V3_TBT_X_LC
PP3V3_TBT_X_SX

27

PP3V3_TBT_X_F

CRITICAL

1

C2975

10UF

20%

6.3V

2

CERM
0402

BYPASS=U2800.G2:J1:3MM

26

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.9V

DIDT=TRUE
SWITCH_NODE=TRUE

VR0V9_IND_TBT_X

PP0V9_TBT_X_LC

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.9V

on support page

XW2900

SM

PLACE_NEAR=U2800.V9:2MM

NO_XNET_CONNECTION=1

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

1

C2991

1.0UF

20%

6.3V

2

X5R 0201-1
0201-1

CRITICAL

1

C2976

10UF

20%

6.3V

2

CERM
0402

CRITICAL

1

C2977

10UF

20%

6.3V

2

CERM
0402

CRITICAL

L2950

0.68UH-20%-6.1A-0.020OHM

21

1210

27

XW

21

TBT_X_THERM_D_N

NOSTUFF

C2990

1.0UF

20%

6.3V
X5R

1

2

C2994

CER-X5R

CRITICAL

1

C2978

10UF

20%

6.3V

2

CERM
0402

1

C2917

12PF

5%
25V

2

CERM
0201

INTERNAL SWITCHING VR OUTPUT

CRITICAL

1

C2950

47UF

20%

6.3V

2

CER-X5R
0603

SOURCED BY INTERNAL SWITCH

1

C2992

1.0UF

20%

6.3V

2

X5R
0201-1

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0V

50

OUT

NOSTUFF

47UF

20%

6.3V
0603

1

2

1

C2910

1.0UF

20%

6.3V

2

X5R
0201-1

C2995

47UF

20%

6.3V

CER-X5R

0603

1

2

CRITICAL

1

C2951

47UF

20%

6.3V

2

CER-X5R
0603

1

C2993

1.0UF

20%

6.3V

2

X5R
0201-1

2x 10uF outside BGA area

1

2

1

2

BOM_COST_GROUP=TBT

1

2

C2911

1.0UF

20%

6.3V
X5R
0201-1

CRITICAL

C2952

47UF

20%

6.3V
CER-X5R
0603

CRITICAL

C2954

10UF

20%

6.3V
CERM
0402

0

21

5%
1/10W
MF-LF

603

L2990

1

C2912

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.9V

CRITICAL

1

C2955

10UF

20%

6.3V

2

CERM
0402

1

2

VOLTAGE=3.3V

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

PP3V3_TBT_X_S0

C2913

1.0UF

20%

6.3V
X5R
0201-1

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

1

2

1

2

MIN_LINE_WIDTH=0.1800
MIN_NECK_WIDTH=0.2000

FROM USB-C PORT
CONTROLLER (UPC)

1

C2983

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2914

1.0UF

20%

6.3V
X5R
0201-1

C2915

1.0UF

20%

6.3V

2

X5R
0201-1

C2982

1.0UF

20%

6.3V
X5R
0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

27 76

USB-C HIGH SPEED 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

25 27 67

1

C2916

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2980

1.0UF

20%

6.3V

2

X5R
0201-1

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

SOURCED BYSOURCED BY INTERNAL SWITCH
INTERNAL SWITCH

27

SYNC_DATE=02/13/2017

051-04039

2.0.0

29 OF 145

26 OF 85

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

GND_VOID=TRUE

16

16

16

16

16

D

16

16

16

25

25

25

25

25

25

25

25

PCIE_TBT_X_R2D_C_P<0>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<0>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<1>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<1>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<2>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<2>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<3>

IN

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<3>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_P<0>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_N<0>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_P<1>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_N<1>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_P<2>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_N<2>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_P<3>

IN

GND_VOID=TRUE

PCIE_TBT_X_D2R_C_N<3>

IN

ACE ARKANOID CONN

C

27 25

45 28

45 28

45 35

29 28

OUT
BI
BI
BI

IN

RIDGE ARKANOID CONN

27 25

27 14

BI

29 28 25 14

29 28 25 14

BI

26

IN

I2C_TBT_XB_INT_L
I2C_UPC_SCL
I2C_UPC_SDA
UPC_I2C_INT_L
TBT_X_SPI_CLK_DBG

27

UPC_XA_UART_TX

TBT_X_PLUG_EVENT_L
TBT_WAKE_3V3_L
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_POC_RESET
PP3V3_TBT_X_F

B

PP3V3_TBT_X_S0

A

100K

1M

1M

1M

1M

100K

100K

100K

100K

100K

100K

30 27

30 27

30 27

30 27

USBC_XA_USB_DBG_BOT_N
USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_TOP_P

Debug Mux 2
Schottky Diodes

R3075

21

21

R3045

21

R3046

1/20W 201MF5%

21

R3047

1/20W

21

R3048
R3076

21

5% 1/20W MF 201

R3020

21

5% 1/20W MF 201

R3057

21

R3058

21

5% 1/20W MF 201

R3042

21

1/20W MF 2015%

R3043

21

5% 1/20W MF 201

RIDGE AC COUPLING

Primary UPC (XA)

U3100

(WRITE: 0X70 READ: 0X71)

I2C_TBT_X_SDA

I2C_TBT_X_SCL

I2C_TBT_XA_INT_L

Secondary UPC (XB)

U3200

(WRITE: 0X7E READ: 0X7F)

I2C_TBT_X_SDA

I2C_TBT_X_SCL

I2C_TBT_XB_INT_L

TBT_X_SPI_CLK_DBG

UPC_XB_SPI_CLK

UPC_XB_SPI_CS_L

UPC_XB_SPI_MOSI

UPC_XB_SPI_MISO

UPC_X_SPI_CLK

UPC_X_SPI_CS_L

UPC_X_SPI_MOSI

UPC_X_SPI_MISO

5%

1/20W

MF

201

1

2

R3044

100K

PP3V3_G3H

76

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

USB3_EXTA_R2D_P
USB3_EXTA_R2D_N

USB_SOC_P
USB_SOC_N

DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO

USBC_XA_USB_TOP_P

USBC_XA_USB_TOP_N

28

28

28

29

29

29

27

29

29

29

29

25 27

25 27

25 27

25 27

USB VBUS Detect

<rdar://25149752>

INOUT

27 28

27 29

27 25 35

PP20V_USBC_XA_VBUS

PP20V_USBC_XB_VBUS

1

C3022

0.1UF

10%
10V

2

X5R-CERM
0201

24 10
23

11
12

XW3001

SM

21

PLACE_NEAR=U2800.F1:5MM
NO_XNET_CONNECTION=1

TBT_X_XTAL25M_OUT

25

NOSTUFF

1M

5%

1/20W

MF

201

1

2

R3006

TBT_X_XTAL25M_IN

25

F3000

6A-32V

0603-1

F3010

6A-32V

0603-1

353S01188

20

VDD

U3000

PI3USB32324

3

PCH_USB3_RX_P

4

PCH_USB3_RX_N

6

PCH_USB3_TX_P

7

PCH_USB3_TX_N

1

USB2_EP_P

2

USB2_EP_N

SWCLK
SWDIO

ANALOG1
ANALOG2

QFN-1

GND

5

14

USB2_RP_P
USB2_RP_N

USB2_B_P
USB2_B_N

USB2_T_N
USB2_T_P

EPAD

17

31

SDA
SCL

DEBUG1
DEBUG2

25

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0V

C3002

CRITICAL

Y3000

42

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

C3003

R3080

30K

1/20W

CRITICAL

21

PP20V_USBC_XA_VBUS_F

CRITICAL

21

PP20V_USBC_XB_VBUS_F

8
9

16
15

18
19

13

22
21

21

SOC_USB_VBUSPP20V_USBC_XA_VBUS_F

5%
MF

201

K

D3001

DFN1006

A

BZT52C3V0LP-COMBO

USB_DBG_PCH_XA_F_P
USB_DBG_PCH_XA_F_N

USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_BOT_N

USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_TOP_P

I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL

UPC_XA_DBG1
UPC_XA_DBG2

20PF

21

25V5%
0201C0G

20PF

21

25V5%
0201C0G

CRITICAL

26

79 34 28 27

29

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

BI

5

OUT

16

BI

27

BI

16

BI

27

BI

16

BI

29

BI

16

BI

29

BI

28

BI

28

BI

29

OUT

29

IN

29 27 20

OUT OUT

29 27 20

IN IN

28

28

29

29

25 27

25 27

25 27

25 27

29

28 27

28 29

28

29

28

28

28

28

28

28

29

28

29

28

L3000

90-OHM-0.1A

1

BI
BI

BI
BI

BI
BI

BI
BI

C3040
C3041
C3042
C3043
C3044
C3045
C3046
C3047

R2D

21

21

21

21

21

21

21

21

0.22UF

20% 6.3VX5R0201

0.22UF

6.3V20%X5R0201

0.22UF

20% 6.3VX5R0201

0.22UF

20% 6.3V0201 X5R

0.22UF

20% 6.3VX5R0201

0.22UF

20%X5R0201

6.3V

0.22UF

20% 6.3VX5R0201

0.22UF

20% 6.3VX5R0201

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

TBT_PCIE_4LANES

PCIE_TBT_X_R2D_P<2>

TBT_PCIE_4LANES

PCIE_TBT_X_R2D_N<2>

TBT_PCIE_4LANES

PCIE_TBT_X_R2D_P<3>

TBT_PCIE_4LANES

PCIE_TBT_X_R2D_N<3>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

25

25

25

25

25

25

25

25

TITAN RIDGE - U2800

27 25

I2C_TBT_X_SDA
I2C_TBT_X_SCL

27 25

27 25

I2C_TBT_XA_INT_L

27 25

I2C_TBT_XB_INT_L

TBT

(MASTER)

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

D2R

0.22UF

M-ST-SM

M-ST-SM

21

20% 6.3VX5R0201

0.22UF

21

20% 6.3VX5R0201

0.22UF

21

0.22UF

21

20% 6.3VX5R0201

0.22UF

21

20%X5R0201

0.22UF

21

20% 6.3VX5R

0.22UF

21

20%

0.22UF

21

1413

21
43
65
87
109
1211

16

1413

21
43
65
87
109
1211

16

K

D3092

DFN1006

BAS40LP

A

PCIE_TBT_X_D2R_P<0>

PCIE_TBT_X_D2R_N<0>

PCIE_TBT_X_D2R_P<1>

PCIE_TBT_X_D2R_N<1>

TBT_PCIE_4LANES

PCIE_TBT_X_D2R_P<2>

6.3V

TBT_PCIE_4LANES

PCIE_TBT_X_D2R_N<2>

TBT_PCIE_4LANES

PCIE_TBT_X_D2R_P<3>

6.3VX5R0201

TBT_PCIE_4LANES

PCIE_TBT_X_D2R_N<3>

6.3V20%X5R0201

UPC_DBG_HDR

I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL

UPC_DBG_HDR

I2C_TBT_XA_INT_L

I2C_TBT_X_SDA

I2C_TBT_X_SCL

UPC_XA_UART_RX

TBT_X_PCI_RESET_L

USBC_X_RESET_L
PP3V3_TBT_X_SX

PP3V3_TBT_X_ANA_PCIE

PP3V3_TBT_X_ANA

PP3V3_TBT_X_LC

PU_TBT_X_GPIO_1

PD_TBT_XA_LSTX

PD_TBT_XA_LSRX

PD_TBT_XB_LSTX

PD_TBT_XB_LSRX

PD_TBT_X_GPIO_0

PD_DP_X_SRC_HPD

25

28

28

29

29

25

25

PD_USB_UPC_XA_FP

PD_USB_UPC_XA_FN

UPC_XA_5V_EN

UPC_XB_5V_EN

K

D3091

DFN1006

BAS40LP

A

K

D3090

DFN1006

BAS40LP

A

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI
BI

OUT

28 27

OUT

OUTOUT

BI

25 26 27 67

26

26

26

28

OUT

28

OUT

28

OUT

29

OUT

27 25

28 27

29 28

25 14 25 5

16

16

16

16

16

16

16

16

27 25

27 25

27 25

100

TBT_X_SPI_CLK

25

TBT_X_SPI_CS_L

25

TBT_X_SPI_MOSI

25

TBT_X_SPI_MISO

25

TBT Wake Level Shifter

PP1V8_SLPS2R

75

SMC has IPU

TBT_WAKE_L

Sacrificial Components

0

21

402MF-LF1/16W5%

CKPLUS_WAIVE=TERMSHORTED

0

21

402MF-LF1/16W5%

CKPLUS_WAIVE=TERMSHORTED

0

21

402MF-LF1/16W5%

CKPLUS_WAIVE=TERMSHORTED

0

21

402MF-LF1/16W5%

CKPLUS_WAIVE=TERMSHORTED

GND_VOID=TRUE

C3020

X5R-CERM0201 16V10%

C3021

0201

X5R-CERM 16V10%

GND_VOID=TRUE

16

16

USB3_EXTA_R2D_C_P

BI

USB3_EXTA_R2D_C_N

BI

R3000

R3001

R3002

R3003

15

15

15

15

15

15

15

15

2

R3098

21

R3090

21

5%

R3091

21

R3092

21

R3093

21

R3094

21

R3095

21

R3096

21

R3097

21

PP3V3_G3H

76

1

GS

Q3001

DMN32D2LFB4

DFN1006H4-3

0.1UF

21

0.1UF

21

SYM_VER_3

D

3

201MF1/20W5%

201MF1/20W

MF 2011/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

201MF1/20W5%

MF1/20W5% 201

201MF1/20W5%

TBT_WAKE_3V3_L

16

OUT

16

OUT

79 34

79 34

27 20

27 20

28

28

BI
BI

OUT
BI

BI
BI

C3050
C3051
C3052

0201 20% 6.3VX5R

C3053
C3055
C3056

0201

C3057
C3054

J3098

505070-1222

15
516S00115

J3099

505070-1222

15
516S00115

26 27 76

PU_TBT_X_GPIO_1

201MF1/20W5%

201MF1/20W5%

201MF5%

201MF1/20W5%

201MF1/20W5%

MAKE_BASE=TRUE

PD_TBT_XA_LSTX

MAKE_BASE=TRUE

PD_TBT_XA_LSRX

MAKE_BASE=TRUE

PD_TBT_XB_LSTX

MAKE_BASE=TRUE

PD_TBT_XB_LSRX

MAKE_BASE=TRUE

PD_TBT_X_GPIO_0

MAKE_BASE=TRUE

PD_DP_X_SRC_HPD

MAKE_BASE=TRUE

PD_USB_UPC_XA_FP

MAKE_BASE=TRUE

PD_USB_UPC_XA_FN

MAKE_BASE=TRUE

K

D3093

DFN1006

BAS40LP

A

PP20V_USBC_XA_VBUS

27 28

PP20V_USBC_XB_VBUS

27 29

PP3V3_UPC_XA_LDO

28

PP3V3_UPC_XB_LDO

29

PP3V3_UPC_XB_LDO

25

PP3V3_TBT_X_SX

28

PP3V3_TBT_X_SX

29

PP3V3_TBT_X_S0

26 27 76

DP_X_SNK0_ML_C_N<3..0>
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N
DP_X_SNK1_ML_C_P<3..0>
DP_X_SNK1_ML_C_N<3..0>
DP_X_SNK1_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
NC_DP_X_SRC_MLP<0..3>

25

NC_DP_X_SRC_MLN<0..3>

25

NC_DP_X_SRC_AUXP

25

NC_DP_X_SRC_AUXN

25

DP_X_SNK0_HPD
DP_X_SNK1_HPD

USB_UPC_PCH_XA_P
USB_UPC_PCH_XA_P
USB_UPC_PCH_XA_N
USB_UPC_PCH_XA_N
USB_UPC_PCH_XB_P
USB_UPC_PCH_XB_P
USB_UPC_PCH_XB_N
USB_UPC_PCH_XB_N

SOC_DFU_STATUS
SOC_FORCE_DFU

PCH_UART_DEBUG_R2D

PCH_UART_DEBUG_D2R

UPC_XB_DBG3

UPC_XB_DBG4

JTAG_TBT_X_TMS

USBC_XA_CC1
USBC_XA_CC2
USBC_XB_CC1
USBC_XB_CC2
UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
USBC_X_RESET_L
TBT_POC_RESET
UPC_PMU_RESET
UPC_PMU_RESET
TP_USBC_XA_RESET_L
GND
GND
GND
GND
GND
GND
GND
GND
GND

EXCX4CE

SYM_VER-1

4

USB_UPC_PCH_XA_P

PLACE_NEAR=U3000:5MM

32

USB_UPC_PCH_XA_N

30 27

30 27

30 27

30 27

28 27

28 27

28

28

BOM_COST_GROUP=USB-C

POWER ALIASES

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

DP / USB SOURCE ALIASES

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1MAKE_BASE=TRUE
NO_TEST=1MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1

DP_X_SNK0_ML_C_P<3..0>DP_X_SNK0_ML_C_P<3..0>
DP_X_SNK0_ML_C_N<3..0>
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N
DP_X_SNK1_ML_C_P<3..0>
DP_X_SNK1_ML_C_N<3..0>
DP_X_SNK1_AUXCH_C_P
DP_X_SNK1_AUXCH_C_N
NC_DP_X_SRC_MLP<0..3>
NC_DP_X_SRC_MLN<0..3>
NC_DP_X_SRC_AUXP
NC_DP_X_SRC_AUXN
DP_X_SNK0_HPD
DP_X_SNK1_HPD

USB_UPC_PCH_XA_P

USB_UPC_PCH_XA_N

USB_UPC_PCH_XB_P

USB_UPC_PCH_XB_N

Debug Aliases

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

21

R3073
R3074

15

5% 1/20W MF 201

21

15

5% 1/20W MF 201

MAKE_BASE=TRUE

MISC ALIASES

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

27

27

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=U3000.24:5mm

PLACE_NEAR=U3000.23:5mm

USB-C SUPPORT

Apple Inc.

SOC_DFU_STATUS
SOC_FORCE_DFU

PCH_UART_DEBUG_R2D

PCH_UART_DEBUG_D2R

DBGMUX_SWD_SOC_CLK

DBGMUX_SWD_SOC_IO

JTAG_TBT_X_TMS

USBC_XA_CC1
USBC_XA_CC2
USBC_XB_CC1
USBC_XB_CC2
UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
USBC_X_RESET_L
TBT_POC_RESET
UPC_PMU_RESET

TP_USBC_XA_RESET_L

PP20V_USBC_XA_VBUS
PP20V_USBC_XB_VBUS
PP3V3_UPC_XA_LDO
PP3V3_UPC_XB_LDO

PP3V3_TBT_X_SX

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

25 26 27 67

PP3V3_TBT_X_S0

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

VOLTAGE=3.3V

DRAWING NUMBER

051-04039

REVISION

BRANCH

PAGE

30 OF 145

SHEET

27 OF 85

2.0.0

28

29

79

IN
INOUT

OUT

OUT

IN

BI
BIBI
BI
BI
BI
BI
BI
BI

BI

80 79 30

80 79 30

80 79

D

25

25 5

25

25

25

25

25

25

25

25 5

C

43 34
82 79

79 65 34

79 17

79 17

25 14

31 28

31 28

31 29

31 29

27 25

27 14

65 57

SIZE

D

SYNC_DATE=02/13/2017

B

A

8

67

35 4

2

1

678

3 245

1

D

C

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

75

C3115

1.0UF

20%

6.3V
X5R

0201-1

FUSE

27

Add on
support page

PP20V_USBC_XA_VBUS

PP1V8_SLPS2R

76

CRITICAL

20%

6.3V
CERM
0402

1

2

1

C3100

10UF

2

PP3V3_G3H_RTC

28

PP5V_G3S

76

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_XA_VBUS_F

27

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=20V

D11

C11

B11

A11

PP_5V0

PP_5V0

PP_5V0

PP_5V0

1

C3101

1UF

10%
35V

2

X5R
0402

A8

A7

A6

PP_HV

PP_HV

PP_HV

B7

PP_HV

J10

H11

H10

VBUS

PP_CABLE

PWR-CLIP-33

S2

5

K11

J11

VBUS

VBUS

VBUS

G2

4

H1

VIN_3V3

B1

VDDIO

CRITICAL

Q3100

FDPC4044

3

2

NC

TP_Q3100_DRAIN

G1

H2

K1

LDO_3V3

LDO_1V8A

VOUT_3V3

1

UPC_XA_GATE2

E1

A2

LDO_BMC

LDO_1V8D

G1

S1

8

UPC_XA_GATE1

79

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

PP1V8_UPC_XA_LDODPHV_INT_XA_G3H

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

1

C3104

2.2UF

20%

6.3V

2

X5R-CERM
0201

29 76

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

PP3V3_TBT_X_SX

PP1V8_UPC_XA_LDOA

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3106

0.47UF

20%
4V

2

CERM-X5R-1
201

PP3V3_UPC_XA_LDO

27

1

2

27

VOUT_3V3 FOR RIDGE,
OR FLOAT IF UNUSED

CRITICAL

C3108

10UF

20%

6.3V
CERM
0402

D

C

B

PP3V3_UPC_XA_LDO

1M

1M

100K

1M

R3109

21

R3108

21

21

5% MF1/20W

21

R3169
R3105

27

I2C_UPC_XA_DBG_CTL_SCL

201MF1/20W5%

I2C_UPC_XA_DBG_CTL_SDA

201MF1/20W5%

PHV_INT_XA_G3H

201

UPC_XA_UART_RX

MF 2015% 1/20W

28

29 27

TESTPOINTS MUST BE

28 27

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

28 27

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

GND I2C_ADDR
PRIMARY ONLY

ON BANSURI DESIGNS

29 27 25 14

29 27 25 14

79 35 29

27

82
79
34
65

25

27

27

18

27

IN
OUT

IN
BI
BI
OUT
OUT
OUT
OUT
OUT

IN

TBT_POC_RESET
TP_USBC_XA_RESET_L

TP_UPC_XA_DBG_UART_TX
PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
DP_XA_HPD
UPC_PMU_RESET
UPC_XA_5V_EN
SOC_DOCK_CONNECT
UPC_XA_FAULT_L

GND
GND

27

UPC_XA_R_OSC

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

TO SMC

1

2

R3103

29 28 27

NEED 0.1%

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

27

27

27

45 27

45 27

45

27

27

27

27

28 27

28 27

BI
BI
OUT

BI
BI
OUT

OUT
OUT
IN
OUT

I2C_UPC_XA_DBG_CTL_SCL
I2C_UPC_XA_DBG_CTL_SDA

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XA_INT_L

I2C_UPC_SDA

I2C_UPC_SCL

UPC_I2C_INT_L
GND

GND
GND
GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

PRIMARY ONLY

U3100

CD3215A10

BGA

HV FET/SENSE

TYPE-C

CRITICAL
OMIT_TABLE

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

NC

H7

B10
A10

B9
A9

L9

USBC_XA_CC1

L10

USBC_XA_CC2

K9

USBC_XA_CC1

K10

USBC_XA_CC2

K6

USBC_XA_USB_TOP_P

L6

USBC_XA_USB_TOP_N

K7

NC_USBC_XA_USB_BOTP

L7

NC_USBC_XA_USB_BOTN

K8

USBC_XA_SBU1

L8

USBC_XA_SBU2

L11

GROUND

NC or GND to dissipate heat

UPC_XA_SS

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R
0201

BI
BI

BI
BI

BI
BI

BI
BI

27

27

27

27

77

77

30

30

1

C3114

220PF

2%
50V

2

C0G
0201

1

C3113

220PF

2%
50V

2

C0G
0201

BI
BI

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

31 27

31 27

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

B

A

Add CMC on support page
for ridgeless design

CMC

27

27

BI
BI

29 28 27

29 27

27

27

25

25

27

27

27

27

IN
OUT

IN
OUT

BI
BI

BI
BI
BI
BI

TP_UPC_XA_SWD_DATA
TP_UPC_XA_SWD_CLK

UPC_XA_UART_RX
UPC_XA_UART_TX

PD_TBT_XA_LSTX
PD_TBT_XA_LSRX

PD_USB_UPC_XA_FP
PD_USB_UPC_XA_FN

USBC_XA_AUXLSX1
USBC_XA_AUXLSX2

UPC_XA_DBG1
UPC_XA_DBG2
SOC_DFU_STATUS
SOC_FORCE_DFU

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

E8

D8

B8

L1

H8

G8

H5

H4

GND

F6

GND

GND

F7

GND

F8

GND

G6

GND

G7

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

8

USB-C PORT CONTROLLER A

DRAWING NUMBER

051-04039

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

67

27

BOM_COST_GROUP=USB-C

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

31 OF 145

SHEET

28 OF 85

1

SIZE

D

678

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

PWR-CLIP-33

CRITICAL

Q3200

FDPC4044

3 245

1

D

C

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

75

C3219

1.0UF

20%

6.3V
X5R

0201-1

D

G2

S2

5

PP20V_USBC_XB_VBUS

27

FUSE

Add on
support page

PP20V_USBC_XB_VBUS_F

27

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=20V

1

2

C3201

1UF

10%
35V
X5R
0402

4

3

2

NC

TP_Q3200_DRAIN

PP1V8_SLPS2R

76

CRITICAL

20%

6.3V
CERM
0402

1

2

1

C3200

10UF

2

PP3V3_G3H_RTC
PHV_INT_XB_G3H

29

PP5V_G3S

76

CAP FOR PP_5V0 ON VR PAGE

B11

A11

PP_5V0

PP_5V0

D11

C11

PP_5V0

PP_5V0

A7

A6

PP_HV

PP_HV

B7

A8

PP_HV

PP_HV

J10

H11

H10

VBUS

PP_CABLE

J11

VBUS

VBUS

K11

VBUS

H1

B1

VDDIO

VIN_3V3

G1

H2

LDO_3V3

VOUT_3V3

K1

LDO_1V8A

G1

S1

1

8

UPC_XB_GATE1

UPC_XB_GATE2

E1

A2

LDO_BMC

LDO_1V8D

79

PP1V1_UPC_XB_LDO_BMC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

PP1V8_UPC_XB_LDOD

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

1

C3204

2.2UF

20%

6.3V

2

X5R-CERM
0201

28 76

PP3V3_TBT_X_SX

PP1V8_UPC_XB_LDOA

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

1

C3205

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

1

C3206

0.47UF

20%
4V

2

CERM-X5R-1
201

VOLTAGE=3.3V

PP3V3_UPC_XB_LDO

27

27

VOUT_3V3 FOR RIDGE,
OR FLOAT IF UNUSED

CRITICAL

1

C3208

10UF

20%

6.3V

2

CERM
0402

C

B

PP3V3_UPC_XB_LDO

1M

1M

100K

1M

1M

R3209

21

5% 1/20W MF 201

R3208

21

5% 1/20W MF 201

R3269

21

5% MF1/20W 201

R3272

21

5%

R3205

21

5% 1/20W MF 201

27

I2C_UPC_XB_DBG_CTL_SCL

I2C_UPC_XB_DBG_CTL_SDA

PHV_INT_XB_G3H

201MF1/20W

UPC_XB_GPIO1

UPC_XA_UART_TX

29

29

29

29

TBT_POC_RESET

27 28

USBC_X_RESET_L

27

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

28 27 25 14

28 27 25 14

25

27

79 35 28

18

27

NO_TEST=1

BI
BI
OUT

OUT
OUT
OUT

IN

TP_UPC_XB_DBG_UART_TX
UPC_XB_GPIO1

29

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
DP_XB_HPD
UPC_PMU_RESET

27

UPC_XB_5V_EN
SOC_DOCK_CONNECT
UPC_XB_FAULT_L

GND
NC_UPC_XB_I2C_ADDR

UPC_XB_R_OSC

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

TO SMC

1

27

2

27

27

45

45

45

27

27

27

27

BI
BI
OUT

BI
BI
OUT

OUT
OUT
IN
OUT

R3203

NEED 0.1%

29 28 27

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

I2C_UPC_XB_DBG_CTL_SCL

29

I2C_UPC_XB_DBG_CTL_SDA

29

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XB_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

UPC_XB_SPI_CLK
UPC_XB_SPI_MOSI
UPC_XB_SPI_MISO
UPC_XB_SPI_CS_L

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

U3200

CD3215A10

BGA

HV FET/SENSE

TYPE-C

CRITICAL
OMIT_TABLE

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

NC

H7

B10
A10

B9
A9

L9

USBC_XB_CC1

L10

USBC_XB_CC2

K9

USBC_XB_CC1

K10

USBC_XB_CC2

K6

USBC_XB_USB_TOP_P

L6

USBC_XB_USB_TOP_N

K7

USBC_XB_USB_BOT_P

L7

USBC_XB_USB_BOT_N

K8

USBC_XB_SBU1

L8

USBC_XB_SBU2

L11

UPC_XB_SS

GROUND

NC or GND to dissipate heat

1

C3209

0.47UF

10%

6.3V

2

CERM-X5R
0201

BI
BI

BI
BI

BI
BI

BI
BI

27

27

30

30

30

30

30

30

1

C3214

220PF

2%
50V

2

C0G
0201

1

C3213

220PF

2%
50V

2

C0G
0201

BI
BI

31 27

31 27

MIN_LINE_WIDTH=0.3500

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.3500
MIN_NECK_WIDTH=0.2000

B

A

27

27

BI

BI

USB_UPC_PCH_XB_P

USB_UPC_PCH_XB_N

CRITICAL

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

4

PLACE_NEAR=U3200.L5:5mm

32

PLACE_NEAR=U3200.K5:5mm

29 28 27

28 27

27

27

25

25

27

27

27

27

IN
OUT

IN

BI
BI

BI
BI
BI
BI

TP_UPC_XB_SWD_DATA
TP_UPC_XB_SWD_CLK

UPC_XA_UART_TX
UPC_XA_UART_RX

PD_TBT_XB_LSTX
PD_TBT_XB_LSRX

USB_UPC_XB_F_P
USB_UPC_XB_F_N

USBC_XB_AUXLSX1
USBC_XB_AUXLSX2

PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R
UPC_XB_DBG3
UPC_XB_DBG4

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

E8

D8

B8

L1

H8

G8

H5

H4

GND

F6

GND

GND

F7

GND

F8

GND

G6

GND

G7

A

PAGE TITLE

8

USB-C PORT CONTROLLER B

DRAWING NUMBER

051-04039

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

67

27

BOM_COST_GROUP=USB-C

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

32 OF 145

SHEET

29 OF 85

1

SIZE

D

D

678

3 245

1

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.57::10MM

BYPASS=J3300.57::10MM

CRITICAL

1

C3320

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3321

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3322

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3323

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

K

D3320

X3-WLB1608-1

SDM2U40CSP

A

PP20V_USBC_XB_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

VOLTAGE=20V

K

D3321

ESDA25P35-1U1M-COMBO

1610-COMBO

A

80 79 27

D

C

B

25

25

25

25

25

25

25

25

USBC_XB_CC1_CONN

31

USBC_XB_R2D_CR_N<1>

IN

USBC_XB_R2D_CR_P<1>

IN

USBC_XB_D2R_N<1>

OUT

USBC_XB_D2R_P<1>

OUT

USBC_XB_SBU2

29

USBC_XB_USB_BOT_N

29

USBC_XB_USB_BOT_P

29

DSN2

CRITICAL

2

1

USBC_XA_USB_DBG_BOT_N

27

USBC_XA_USB_DBG_BOT_P

27

USBC_XA_SBU1

28

USBC_XA_R2D_CR_P<2>

IN

USBC_XA_R2D_CR_N<2>

IN

USBC_XA_D2R_P<2>

OUT

USBC_XA_D2R_N<2>

OUT

USBC_XA_CC2_CONN

31

2

1

2

SESDL2011

1

D3362

DSN2

CRITICAL

2

SESDL2011

1

D3383

DSN2

CRITICAL

2

SESDL2011

1

D3363

DSN2

CRITICAL

2

SESDL2011

1

D3382

GND_VOID=TRUE

R3361

1/20W

5% MF 201

R3360

5% MF 201

1/20W

GND_VOID=TRUE
GND_VOID=TRUE

R3363

5% 1/20W MF 201

R3362

5% 1/20W MF 201

DSN2

CRITICAL

SESDL2011

D3360

GND_VOID=TRUE

CRITICAL

2

1

D3361

GND_VOID=TRUE

DSN2

SESDL2011

R3380

1/20W MF 2015%

R3381

5% 1/20W MF 201

GND_VOID=TRUE
GND_VOID=TRUE

R3382

5% MF 2011/20W

R3383

5% MF 2011/20W

DSN2

CRITICAL

SESDL2011

D3381

GND_VOID=TRUE

CRITICAL

2

1

D3380

DSN2

SESDL2011

21

USBC_XB_R2D_C_N<1>

2

21

USBC_XB_R2D_C_P<1>

2

21

USBC_XB_D2R_R_N<1>

2

21

USBC_XB_D2R_R_P<1>

2

CRITICAL

GND_VOID=TRUE

2

1

2

X3DFN2

D3364

ESD8011-COMBO

21

USBC_XA_R2D_C_P<2>

2

21

USBC_XA_R2D_C_N<2>

2

21

USBC_XA_D2R_R_P<2>

2

21

USBC_XA_D2R_R_N<2>

2

CRITICAL

GND_VOID=TRUE

2

1

2

5.5V-6.2PF

0201-THICKSTNCL

D3386

CRITICAL

GND_VOID=TRUE

1

1

D3365

CRITICAL

GND_VOID=TRUE

D3387

ESD8011-COMBO

5.5V-6.2PF

CRITICAL

GND_VOID=TRUE

2

X3DFN2

1

GND_VOID=TRUE

2

0201-THICKSTNCL

1

2

5.5V-6.2PF

0201-THICKSTNCL

1

D3367

CRITICAL

2

X3DFN2

1

D3384

ESD8011-COMBO

GND_VOID=TRUE

C3361

10% 25VX5R 0201

C3360

10%X5R 0201

GND_VOID=TRUE
GND_VOID=TRUE

C3363

CER-X5R 25V

10% 0201

C3362

CER-X5R 10%

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

5.5V-6.2PF

0201-THICKSTNCL

D3366

GND_VOID=TRUE

C3380

10% 25VX5R 0201

C3381

10%

GND_VOID=TRUE
GND_VOID=TRUE

C3382

10% 25VCER-X5R 0201

C3383

10% 25VCER-X5R 0201

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

X3DFN2

D3385

ESD8011-COMBO

0.22UF

21

0.22UF

21

25V

0.33UF

21

0.33UF

21

25V

0.22UF

21

0.22UF

21

25VX5R 0201

0.33UF

21

0.33UF

21

0201

R3365

R3384

201MF1/20W5%

220K

1

2

220K

1

1/20W5% 201MF

2

201MF5%

220K

1

2

R3364

220K

1

2

R3385

220K

1/20W

R3367

220K

1/20W5% 201MF

R3386

USBC_XB_R2D_N<1>

USBC_XB_R2D_P<1>

USBC_XB_D2R_CR_N<1>

USBC_XB_D2R_CR_P<1>

201MF1/20W5%

1

2

201MF1/20W

220K

1

2

R3366

USBC_XA_R2D_P<2>

USBC_XA_R2D_N<2>

USBC_XA_D2R_CR_P<2>

USBC_XA_D2R_CR_N<2>

220K

1

2

1

1/20W5% 201MF

2

R3387

1/20W5% 201MF 5%

(NO LANE REVERSALS ALLOWED)

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

516S00457

Mates with:

x on y

J3300

20875-056E-01

F-ST-SM

PWR

SIGNAL

PWR

GND

5857

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645
4847
5049
5251
5453
5655

6059

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

BYPASS=J3300.57::10MM

CRITICAL

1

C3326

0.01UF

10%
25V

2

X5R-CERM
0201

TP_USBC_PP20V_XB

USBC_XB_R2D_N<2>

USBC_XB_R2D_P<2>

USBC_XB_D2R_CR_N<2>

USBC_XB_D2R_CR_P<2>

USBC_XA_R2D_P<1>

USBC_XA_R2D_N<1>

USBC_XA_D2R_CR_P<1>

USBC_XA_D2R_CR_N<1>

TP_USBC_PP20V_XA

BYPASS=J3300.57::10MM

BYPASS=J3300.57::10MM

CRITICAL

1

C3327

0.01UF

10%
25V

2

X5R-CERM
0201

201MF5% 1/20W

220K220K

1

2

R3396

220K

R3397

220K

1

1/20W5% 201MF

2

R3377

R3376

1

2

1

2

1

2

201MF5% 1/20W

220K

1

2

R3394

220K

1

1/20W5% 201MF

2

R3375

CRITICAL

C3328

0.01UF

10%
25V
X5R-CERM
0201

201MF5% 1/20W

1/20W5% 201MF

0.22UF

X5R

0.22UF

0.33UF

0.33UF

CER-X5R

220K

1

5% 1/20W MF 201

2

R3395

0.22UF

0.22UF

0.33UF

0.33UF

220K

1

1/20W 201MF
5%

2

R3374

BYPASS=J3300.57::10MM

CRITICAL

1

C3325

0.01UF

10%
25V

2

X5R-CERM
0201

GND_VOID=TRUE

21

C3391

10% 25V 0201

C3390

21

10% 25VX5R 0201

GND_VOID=TRUE

GND_VOID=TRUE

21

C3393

10% 25VCER-X5R 0201

C3392

21

10% 25V 0201

GND_VOID=TRUE

GND_VOID=TRUE

21

C3370

10% 25VX5R 0201

21

C3371

10% 25VX5R 0201

GND_VOID=TRUE

GND_VOID=TRUE

C3372

21

10% 25VCER-X5R 0201

C3373

21

25VCER-X5R 020110%

GND_VOID=TRUE

USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<2>

USBC_XB_D2R_R_N<2>

USBC_XB_D2R_R_P<2>

GND_VOID=TRUE

1

CRITICAL

D3396

2

5.5V-6.2PF

GND_VOID=TRUE

CRITICAL

2

0201-THICKSTNCL

1

2

X3DFN2

1

D3394

ESD8011-COMBO

USBC_XA_R2D_C_P<1>

USBC_XA_R2D_C_N<1>

USBC_XA_D2R_R_P<1>

USBC_XA_D2R_R_N<1>

CRITICAL

GND_VOID=TRUE

2

1

D3377

5.5V-6.2PF

0201-THICKSTNCL

CRITICAL

GND_VOID=TRUE

2

1

D3374

2

X3DFN2

1

ESD8011-COMBO

GND_VOID=TRUE

2

5% 1/20W 201

2

5% 1/20W MF 201

5% 1/20W MF 201

5%

GND_VOID=TRUE

CRITICAL

D3395

GND_VOID=TRUE

GND_VOID=TRUE

2

2

1/20W MF 201

GND_VOID=TRUE

GND_VOID=TRUE

1

CRITICAL

5.5V-6.2PF

D3397

2

X3DFN2

ESD8011-COMBO

GND_VOID=TRUE

2

5% 1/20W MF 201

2

5% 1/20W MF 201

5% 1/20W 201MF

5% 1/20W MF 201

CRITICAL

GND_VOID=TRUE

D3375

GND_VOID=TRUE

GND_VOID=TRUE

2

2

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

2

X3DFN2

1

D3376

5.5V-6.2PF

ESD8011-COMBO

R3391

21

MF

R3390

21

R3393

21

R3392

21

2

0201-THICKSTNCL

R3370

21

R3371

21

R3372

21

R3373

21

2

0201-THICKSTNCL

CRITICAL

1

CRITICAL

1

DSN2

2

SESDL2011

1

D3391

USBC_XA_USB_DBG_TOP_P
USBC_XA_USB_DBG_TOP_N

DSN2

2

SESDL2011

1

D3370

USBC_XB_CC2_CONN

USBC_XB_R2D_CR_N<2>

USBC_XB_R2D_CR_P<2>

USBC_XB_USB_TOP_P
USBC_XB_USB_TOP_N

USBC_XB_D2R_N<2>

USBC_XB_D2R_P<2>

USBC_XB_SBU1

DSN2

CRITICAL

2

SESDL2011

1

D3390

DSN2

CRITICAL

2

SESDL2011

1

D3393

USBC_XA_SBU2

USBC_XA_R2D_CR_P<1>

USBC_XA_R2D_CR_N<1>

USBC_XA_D2R_P<1>

USBC_XA_D2R_N<1>

USBC_XA_CC1_CONN

DSN2

CRITICAL

2

SESDL2011

1

D3371

DSN2

CRITICAL

2

SESDL2011

1

D3372

31

IN

IN

29

29

OUT

OUT

29

DSN2

CRITICAL

SESDL2011

D3392

28

IN

IN

27

27

OUT

OUT

31

DSN2

CRITICAL

SESDL2011

D3373

25

25

25

25

C

25

25

25

25

B

A

80 79 27

PP20V_USBC_XA_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

D3301

ESDA25P35-1U1M-COMBO

1610-COMBO

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.59::10MM

K

CRITICAL

D3300

X3-WLB1608-1

K

SDM2U40CSP

A

A

CRITICAL

1

C3300

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3306

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3301

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3307

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3302

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3308

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3303

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3305

0.01UF

10%
25V

2

X5R-CERM
0201

Cowling Bosses

860-00973

SH3300

3.4OD1.75ID-1.12H-SM-X10303.4OD1.75ID-1.12H-SM-X1030

1

SH3301

1

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

PAGE TITLE

USB-C CONNECTOR

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

SYNC_DATE=02/13/2017SYNC_MASTER=X1032_MLB_P4BP

A

SIZE

D

2.0.0

BRANCH

PAGE

33 OF 145

SHEET

30 OF 85

BOM_COST_GROUP=USB-C

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

3 245

1

D

USBC_XA_CC1_CONN

30

C3432

1

680PF

10%
25V

X7R-CERM

2

0201

GDZ5V6LP3-55

1%

1/20W

MF

201

1

2

R3432

4.02K

SAVE_CC1A_Z

CRITICAL

K

D3432

DFN0201

R3433

4.99K

1%

1/20W

MF

201

A

1

2

DMT5015LFDF

76521

D

5.6V

SAVE_CC1A_B

100OHM-20%-24V-0.3A

CRITICAL

Q3430

UDFN202-6

G

3

7 6

2

1

CRITICAL

R3430

0603

84

S

SAVE_CC1A_G

Q3431

NSS60101DMT

WDFN6

21

R3431

10K

5%

1/20W

MF

201

USBC_XA_CC1

21

PPBUS_G3H

BI

CRITICAL

R3440

100OHM-20%-24V-0.3A

CRITICAL

0603

21

Q3440

DMT5015LFDF

76521

28 27

31 76

USBC_XA_CC2_CONN

30

C3442

680PF

10%
25V

X7R-CERM

0201

1%

1/20W

MF

201

1

2

1

2

R3442

4.02K

SAVE_CC2A_Z

CRITICAL

K

D3442

GDZ5V6LP3-55

DFN0201

R3443

4.99K

1%

1/20W

MF

201

A

SAVE_CC2A_B

1

2

UDFN202-6

D

5

G

3

8 3

84

S

SAVE_CC2A_G

Q3431

NSS60101DMT

WDFN6

4

R3441

10K

21

5%

1/20W

MF

201

USBC_XA_CC2

PPBUS_G3H

BI

28 27

D

31 76

C

USBC_XB_CC1_CONN

30

C3452

680PF

10%
25V

X7R-CERM

0201

1

2

R3452

4.02K

1/20W

201

SAVE_CC1B_Z

CRITICAL

D3452

GDZ5V6LP3-55

DFN0201

1%
MF

CRITICAL

R3450

100OHM-20%-24V-0.3A

0603

21

CRITICAL

Q3450

DMT5015LFDF

76521

1

2

K

UDFN202-6

D

84

S

G

3

R3451

10K

5%

1/20W

MF

201

USBC_XB_CC1

21

PPBUS_G3H

BI

29 27

31 76

USBC_XB_CC2_CONN

30

C3462

680PF

10%
25V

X7R-CERM

0201

1%

1/20W

MF

201

1

2

1

2

R3462

4.02K

SAVE_CC2B_Z

CRITICAL

K

D3462

CRITICAL

Q3460

DMT5015LFDF

76521

UDFN202-6

D

100OHM-20%-24V-0.3A

S

G

3

SAVE_CC2B_GSAVE_CC1B_G

CRITICAL

R3460

0603

84

21

R3461

10K

5%

1/20W

MF

201

USBC_XB_CC2

21

PPBUS_G3H

BI

29 27

31 76

C

GDZ5V6LP3-55

A

7 6

DFN0201

A

8 3

B

R3453

4.99K

1%

1/20W

MF

201

SAVE_CC1B_B

2

Q3451

SAVE_CC2B_B

NSS60101DMT

1

WDFN6

R3463

4.99K

1%

1/20W

MF

201

1

2

1

2

5

Q3451

NSS60101DMT

WDFN6

4

B

A

8

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_DATE=02/13/2017SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

A

USB-C SUPPORT 2

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=USB-C

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

.

BRANCH

PAGE

34 OF 145

SHEET

31 OF 85

1

SIZE

D

678

3 245

1

D

C

12
18
21
23
27
29
35
36
38
54
56
57
64
66

77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94

99
100
101
102
103
104
105
106
107
108
109
110

1
3
6
9

GND

THRM_PAD

U3700

2103-601607-30

LGA-1

SYM 2 OF 2

THRM_PAD

111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

PP1V8_G3S

32 76

PP1V8_G3S

32 76

SPI_BT_MOSI

79 32

SPI_BT_MISO

79 32

1

R3703

10K

5%
1/20W
MF
201

2

WLAN_ROM_MOSI

32

WLAN_ROM_CS

32

WLAN_ROM_CLK

32

5

DI(IO0)

2

DO(IO1)

WIFI ROM

10%

10V

0201

1

2

C3780

0.1UF

X5R-CERM

BT ROM

8

VCC

U3770

2MBIT

USON

CLK

W25Q20EWUXIE

OMIT_TABLE

HOLD*(IO3)

EPAD

GND

9

4

CS*

WP*(IO2)

OMIT_TABLE

U3780

AT93C66B-MAHM

DI

1

CS

2

SK

CRITICAL

GND

1

2

6

1
3
7

8

VCC

UDFN

5

THRM

PAD

9

DO

ORG

NC

43

6

7

C3770

0.1UF

10%

10V

X5R-CERM
0201

SPI_BT_CLK

SPI_BT_CS_L
BTROM_WP_L
BTROM_HOLD_L

PP1V8_G3S

32 76

1

R3704

10K

5%
1/20W
MF
201

2

R3780

WLAN_ROM_MISO
WLAN_ROM_ORG

NC

R3773

4.7K

5%

1/20W

MF

201

1

2

1

2

R3751

100K

1/20W

36

OUT

36

OUT

1

10K

5%

1/20W

MF

201

2

R3771

100K

5%
1/20W
MF
201

79 32

79 32

1

5%
MF

201

2

32

1

R3772

100K

5%
1/20W
MF
201

2

79 34 20

R3750

100K

5%

1/20W

MF

201

1

2

36

IN

OUT

WLAN_THROTTLE
WLAN_AUDIO_SYNC

R3700

1/20W

48 76

PP1V8_G3S

32 76

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

10K

5%
MF

201

2

PP3V3_G3S_WLANBT

33

65 33

65 33

IN

IN

PMU_CLK32K_WLANBT

WLAN_PWR_EN

BT_PWR_EN

JTAG_WLAN_SEL
TP_JTAG_WLAN_TCK

79

TP_JTAG_WLAN_TMS

79

TP_JTAG_WLAN_TRST

79

UART_WLAN_D2R

36

IN

UART_WLAN_R2D

UART_WLAN_D2R_CTS_L

36

33 6

IN

IN

UART_WLAN_R2D_RTS_L
PCH_WLAN_DEV_WAKE

CRITICAL CRITICAL

1

C3702

10UF

20%

6.3V

2

X5R
603

79

WLAN_THROTTLE

79

WLAN_AUDIO_SYNC

1

C3703

10UF

20%

6.3V

2

X5R
603

NC
NC

CRITICAL

1

C3700

4.7UF

20%

6.3V

2

X5R
402

39

LPO_IN

43

SECI_RX

44

SECI_TX

25

WL_REG_ON

17

BT_REG_ON

63

JTAG_SEL

48

JTAG_TCK

47

JTAG_TMS

53

JTAG_TRST*

60

ANT_SWITCH_CORE1

61

ANT_SWITCH_CORE0

49

FAST_UART_TX

51

FAST_UART_RX

52

FAST_UART_RTS_OUT

50

FAST_UART_CTS_IN

WL_DEV_WAKE

CRITICAL

1

C3701

4.7UF

20%

6.3V

2

X5R
402

62

VDDIO_1P8V

2103-601607-30

OMIT_TABLE

1

C3704

2

19

U3700

LGA-1

SYM 1 OF 2

3PF

+/-0.1PF

25V

C0G
0201

20

VBAT_VCC

1

C3705

3PF

+/-0.1PF

25V

2

C0G
0201

70

69

VIN_3P3V

1

C3706

3PF

+/-0.1PF

25V

2

C0G
0201

BT_GPIO_2
BT_GPIO_4

BT_DEV_WAKE

BT_I2S_DI
BT_I2S_DO

BT_I2S_CLK

BT_I2S_WS

BT_UART_RXD

BT_UART_TXD
BT_UART_CTS*
BT_UART_RTS*

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

GPIO17

WL_HOST_WAKE

76
42

34

95
96
97
98

31
30
26
32

15
14
13
16

71

5958

1

C3707

3PF

+/-0.1PF

25V

2

C0G
0201

1

C3708

12PF

5%

25V

2

CERM
0201

MOD_BT_ROM_BOOT_L
TP_BT_GPIO4

BT_DEV_WAKE

NC
NC

UART_BT_LH_D2R
UART_BT_LH_R2D

UART_BT_MUX_R2D
UART_BT_MUX_D2R
UART_BT_MUX_CTS_L
UART_BT_MUX_RTS_L

SPI_BT_CLK
SPI_BT_CS_L
SPI_BT_MOSI
SPI_BT_MISO

WIFI_SROM_STRAP

WLAN_HOST_WAKE

1

C3709

5%

25V

2

CERM
0201

NOSTUFF

R3790

0

R3791

0

R3702

10K

2 1

5%

1/20W

MF

201

1

C3710

12PF12PF

5%

25V

2

CERM
0201

NOSTUFF

R3701

10K

1/20W

201

21

BT_ROM_BOOT_L

21

PCH_BT_ROM_BOOT_L

1/20W MF 0201

5%

79

35

33

33

IN

OUT

IN

OUT

OUT

79 33

79 33

79 33

79 33

79 32

79 32

79 32

79 32

79 35

02015% 1/20W MF

1

2

1

5%
MF

2

C3711

12PF

5%

25V

CERM
0201

IN

IN

D

34

17

C

B

RF Diplexers & Matching

2X 518S00033

CRITICAL

J3710

IR050D15010C

F-ST-SM

1

4

3

2

CRITICAL

J3720

IR050D15010C

F-ST-SM

1

4

3

2

OMIT_TABLE

C3718

0.3PF

+/-0.05PF

25V

C0G-CERM

0201

RF_1_ANT

OMIT_TABLE

C3727

0.4PF

+/-0.05PF

25V

C0G
201

OMIT_TABLE

1

2

OMIT_TABLE

1

2

R3710

0

21

5%

1/20W

MF

0201

R3723

0

21

5%

1/20W

MF

0201

RF_0_ANT_MATCH_TRF_0_ANT

OMIT_TABLE

1

C3719

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

OMIT_TABLE

1

C3726

0.2PF

+/-0.05PF

25V

2

COG-CERM
0201

CRITICAL

U3710

LFD212G45MJBD899

LLP

2

P3 P1

GND

5

3

4

6

P2

1

CRITICAL

U3720

LFD212G45MJCD900

LLP

2

P3 P1

GND

5

3

4

6

P2

1

OMIT_TABLE

R3714

0

5%
MF

0201

21

OMIT_TABLE

1

C3721

2.0PF

+/-0.1PF

25V

2

C0G-CERM
0201

RF_G_0_DIPLEXER RF_G_0_MATCH

OMIT_TABLE

C3729

2.0PF

+/-0.1PF

25V

C0G-CERM

0201

1

2

1/20W

OMIT_TABLE

R3712

0

5%

MF

0201

21

RF_A_0_MATCH

OMIT_TABLE

1

C3730

2.0PF

+/-0.1PF

25V

2

C0G-CERM
0201

RF_A_0_DIPLEXER

OMIT_TABLE

C3720

2.0PF

+/-0.1PF
C0G-CERM

0201

25V

1/20W

1

2

OMIT_TABLE

R3724

0

5%
MF

0201

21

RF_G_1_MATCH

OMIT_TABLE

1

C3725

0.3PF

+/-0.05PF

25V

2

C0G-CERM
0201

RF_G_1_DIPLEXERRF_1_ANT_MATCH_T

OMIT_TABLE

C3728

2.0PF

+/-0.1PF

25V

C0G-CERM

0201

1

2

1/20W

35 33

IN

BT_HOST_WAKE

WLAN_ROM_CLK

32

WLAN_ROM_CS

32

WLAN_ROM_MISO

32

WLAN_ROM_MOSI

32

NC
NC

33

BT_HOST_WAKE

28

2G_ANT_CORE0

65

2G_ANT_CORE1

37

5G_ANT_CORE0

55

5G_ANT_CORE1

41

BT_GPIO_3

40

BT_GPIO_5

74

SPROM_CLK

73

SPROM_CS

72

SPROM_MISO

75

SPROM_MOSI

PCIE_CLKREQ*

PCIE_PERST*

PCI_PME*

PCIE_RDP
PCIE_RDN

PCIE_TDP0
PCIE_TDN0

PCIE_REFCLK_P
PCIE_REFCLK_N

CXT_A_JTAG_TDI
CXT_B_JTAG_TDO

SR_VLX

VIN_LDO

68
67

2

4
5

7
8

10
11

46
45

22

24

PCH_WLAN_CLKREQ_R_L
PCH_WLAN_PERST_L

NC

PCIE_PCH_WLAN_R2D_P
PCIE_PCH_WLAN_R2D_N

PCIE_PCH_WLAN_D2R_C_P
PCIE_PCH_WLAN_D2R_C_N

PCIE_CLK100M_PCH_WLAN_C_P
PCIE_CLK100M_PCH_WLAN_C_N

WLAN_CONTEXT_A
WLAN_CONTEXT_B

PVIN_LDO_WLAN_L

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0700
SWITCH_NODE=TRUE

0805

2.2UH-20%-1.6A-0.2OHM

L3790

PPVIN_LDO_WLAN

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.35V

33

OUT

33 6

IN

33

IN

33

IN

33

OUT

33

OUT

33

IN

33

IN

IN
IN

21

PVIN_LDO_WLAN_LC

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0700

79 35

79 35

C3790

7.5UF

20%

4V

CERM
0402

1

3

4

2

B

A

8

RF_A_1_DIPLEXER

OMIT_TABLE

C3723

2.0PF

+/-0.1PF
C0G-CERM

0201

67

25V

OMIT_TABLE

R3725

1

2

1/20W

0

5%
MF

0201

SYNC_DATE=03/22/2017SYNC_MASTER=MKARAKUCUK

PAGE TITLE

21

RF_A_1_MATCH

OMIT_TABLE

1

C3724

2.0PF

+/-0.1PF

25V

2

C0G-CERM
0201

WIFI/BT MODULE

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=WIRELESS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

37 OF 145

SHEET

32 OF 85

1

SIZE

A

D

678

3 245

1

D

C

PP1V8_G3S

R3810

1/20W

R3811

5% 201MF1/20W

R3812

5% 201MF1/20W

R3813

5%

65 32

65 32

100K

2 1

100K

2 1

100K

2 1

100K

2 1

MF5% 201

MF 2011/20W

BT_HOST_WAKE

IN

IN

WLAN_PWR_EN

BT_PWR_EN

33 76

SPI_AOP_SENSOR_CLK

SPI_AOP_SENSOR_MOSI

SPI_AOP_SENSOR_MISO

SPI_ACCEL_CS_L

SPI_ACCEL_CS_L

ACCEL_INT1
ACCEL_INT2

1

C3821

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3825

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3835

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3820

12PF

5%
25V

2

CERM
0201

1

C3824

12PF

5%
25V

2

CERM
0201

1

C3834

12PF

5%
25V

2

CERM
0201

35

35

35

IN

IN
IN

33

NOSTUFF

L3810

FERR-240OHM-25%-350MA

21

43 33

43 33

35 33

PLACE_NEAR=U3810.8:2MM

NOSTUFF

1

C3811

0.22UF

20%
10V

2

CERM-X5R
0201

8

VDD

PP1V8_ACCEL_FILT

VOLTAGE=1.8V

7

VDDIO

NOSTUFF

C3810

0.22UF

CERM-X5R

20%
10V

0201

0201

1

2

PLACE_NEAR=U3810.7:2MM

PP1V8_G3S

33 76

33 76

U3810

BMA282

33

79

79

SPI_ACCEL_CS_L

ACCEL_INT1
ACCEL_INT2

32 6 35 32

ININ

PCH_WLAN_DEV_WAKE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

1

C3822

12PF

5%
25V

2

CERM
0201

4

CS*

6

INT1

5

INT2

1

C3823

3PF

+/-0.1PF
25V

2

C0G
0201

9

11

LGA

NOSTUFF

GND

14

12

GNDIO

10

SCX
SDX
SDO

PS

1

SPI_AOP_SENSOR_CLK

2

SPI_AOP_SENSOR_MOSI

3

SPI_AOP_SENSOR_MISO

13

OUT

OUT

IN

36

IN

43 33

43 33

35 33

35 33

BTUARTMUX_SEL_PCH

36 32

OUT IN

SoC

5%

1/20W

MF

201

1

PCH

2

3

D

R3801

100K

Q3850

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

UART_BT_LH_R2D
UART_BT_LH_D2R

PP3V3_G3S_WLANBT

33 76

PP1V8_G3S

33 76

36

36

17

17

IN

OUT

IN

OUT

UART_BT_R2D
UART_BT_D2R

PCH_UART_BT_R2D
PCH_UART_BT_D2R

BTUARTMUX_OE_L

Software
Gen1 (macOS)
Gen1 (Bootcamp)
Gen2

PP1V8_G3S

MAKE_BASE=TRUE

UART_BT_LH_R2D
UART_BT_LH_D2R

MAKE_BASE=TRUE

47K

5%

1/20W

MF

201

1

2

R3845

R3805

47K

5%

1/20W

MF

201

5
4

7
6

8

I2S_SEL UART_SEL

0
1
X

1

2

BYPASS=U3440::5mm

9

VCC

M+
M-

D+
D-

OE* SEL

U3840

PI3USB102J

X2QFN

CRITICAL

GND
3

SEL OUTPUT

Y+
Y-

1
2

10

1
1 I2S (PCH)
0

C3840

0.1UF

X5R-CERM

UART_BT_MUX_R2D
UART_BT_MUX_D2R

BTUARTMUX_SEL_PCH

10%
10V

0201

1

2

I2S I/F UART I/F

UART (PCH)

UART (PCH)
UART (PCH)
UART (SOC)X

32

OUT

Module

OUT

IN

IN

D

79 32

79 32

35 33

L SOC (M)

33 32

32 6

PCH_WLAN_CLKREQ_R_L

OUT

1

C3832

12PF

5%
25V

2

CERM
0201

PCH_WLAN_PERST_L

IN

1

C3836

12PF

5%
25V

2

CERM
0201

1

C3833

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3837

3PF

+/-0.1PF
25V

2

C0G
0201

42 15

IN

PM_PCH_PWROK

1

SG

2

PP3V3_G3S_WLANBT

33 76

PP1V8_G3S

33 76

47K

5%

1/20W

MF

201

1

9

2

5

M+

4

M-

VCC

U3850

SoC

36

36

IN

OUT

R3855

UART_BT_R2D_RTS_L
UART_BT_D2R_CTS_L UART_BT_MUX_RTS_L

PI3USB102J

X2QFN

CRITICAL

PCH

17

17

IN

OUT

PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L

7

D+

6

D-

H PCH (D)

BYPASS=U3450::5mm

C3850

0.1UF

X5R-CERM

1

Y+
Y-

UART_BT_MUX_CTS_L

2

10%
10V

0201

C

1

2

Module

OUT

IN

79 32

79 32

B

32

16

16

PMU_CLK32K_WLANBT

OUT IN

PCH_WLAN_CLKREQ_L

OUT IN

IN

PCIE_PCH_WLAN_R2D_C_P

R3829

R3828

C3857

0.1UF

16

IN

PCIE_PCH_WLAN_R2D_C_N

C3854

0.1UF

16

OUT

PCIE_PCH_WLAN_D2R_P

C3852

0.1UF

16

OUT

PCIE_PCH_WLAN_D2R_N

C3853

0.1UF

16

IN

PCIE_CLK100M_PCH_WLAN_P

C3858

100PF

33

1K

21

201MF1/20W5%

21

201MF5% 1/20W

21

21

21

21

21

PMU_CLK32K_WLANBT_R

PCH_WLAN_CLKREQ_R_L

PCIE_PCH_WLAN_R2D_CC_P

0201X5R-CERM16V10%

PCIE_PCH_WLAN_R2D_CC_N

X5R-CERM 020116V10%

PCIE_PCH_WLAN_D2R_CC_P

0201X5R-CERM16V10%

PCIE_PCH_WLAN_D2R_CC_N

0201X5R-CERM16V10%

PCIE_CLK100M_PCH_WLAN_CC_P

0201C0G25V5%

65

33 32

CRITICAL

L3854

2.4GHZ

0.65X0.5X0.3MM-SM

SYM_VER-1

1

CRITICAL

L3852

2.4GHZ

0.65X0.5X0.3MM-SM

SYM_VER-1

1

CRITICAL

L3858

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

8

OE* SEL

GND
3

10

BTUARTMUX_SEL_PCH

IN

35 33

SEL OUTPUT

L SOC (M)
H PCH (D)

4

32

4

32

4

PCIE_PCH_WLAN_R2D_P

PCIE_PCH_WLAN_R2D_N

PCIE_PCH_WLAN_D2R_C_P

PCIE_PCH_WLAN_D2R_C_N

PCIE_CLK100M_PCH_WLAN_C_P

OUT

OUT

OUT

IN

IN

32

32

32

32

32

B

A

16

IN

PCIE_CLK100M_PCH_WLAN_N

C3859

21

PCIE_CLK100M_PCH_WLAN_CC_N

100PF

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

152S2053 C37191

131S0428 CRITICALR37101

152S2021 1 R3714 CRITICAL

152S00157 1 R3712 CRITICAL

152S2053 C37261

131S0428 1 R3723 CRITICAL

152S2021 1 R3724 CRITICAL

152S00157 1 CRITICAL

IND,FILM,4.7NH,+/-3%,400MA,UH-Q,0201

CAP,CER,10PF,5%,25V,C0H,0201,HQ

IND,FILM,1.5NH,+/-0.1NH,1000MA,UH-Q,0201

IND,FILM,1.2NH,+/-0.05NH,1.1A,UH-Q,0201

IND,FILM,4.7NH,+/-3%,400MA,UH-Q,0201

CAP,CER,10PF,5%,25V,C0H,0201,HQ

IND,FILM,1.5NH,+/-0.1NH,1000MA,UH-Q,0201

IND,FILM,1.2NH,+/-0.05NH,1.1A,UH-Q,0201

R3725

CRITICAL

CRITICAL

32

0201C0G25V5%

CAP,CER,COG,0.2PF,+/-0.05PF,25V,0201,H-Q

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

131S0319 1 C3729 RFTUNING:NOSTUFF

131S0319 C37211 RFTUNING:NOSTUFF

131S0319 C37201 RFTUNING:NOSTUFF

131S0319 1 C3730 RFTUNING:NOSTUFF

131S0431 1 RFTUNING:NOSTUFF

131S0319 C37281 RFTUNING:NOSTUFF

131S0319 1 C3725 RFTUNING:NOSTUFF

131S0319 1 C3723 RFTUNING:NOSTUFF

131S0319 C37241 RFTUNING:NOSTUFF

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,COG,0.2PF,+/-0.05PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

CAP,CER,C0G,2.0PF,+/-0.1PF,25V,0201,H-Q

PCIE_CLK100M_PCH_WLAN_C_N

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

C3727

OUT

32

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

RFTUNING:NOSTUFFC3718131S0431 1

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

WIFI/BT Module Support

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

SYNC_DATE=03/03/2017

SIZE

A

D

2.0.0

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

BOM_COST_GROUP=WIRELESS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

38 OF 145

SHEET

33 OF 85

8

67

35 4

2

1

Note 1) IPU represents SW configured state, not HW default

678

3 245

1

D

C

77

77

77

79 54 52

44

17

79 52

79 52 43

77

42

79 53 52

79 53 52

42

56

72 71 70

44

42

42

42

43

77

OUT
OUT
OUT

IN

OUT

IN

IN
OUT
OUT

IN

IN
OUT

IN
OUT
OUT
OUT

IN

IN

IN
OUT

IN

NC_PLCAM_TX_THROTTLE
NC_GNSS_HOST_TIME
NC_GNSS_DEV_WAKE
CODEC_INT_L
SE_CTLR_FW_DWLD
PCH_SOC_SYNC
MESA_INT
MESA_PWR_EN
NC_WLAN_DEV_WAKE
BOARD_REV0
SPKRAMP_INT_L
SPKRAMP_RESET_L
BOARD_REV1
TPAD_SPI_EN
SSD_BFH
SE_DEV_WAKE
BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2
SSD_PMU_RESET_L
NC_DFR_DISP_INT

A13
A12
B12

AJ36

R36
AB36
AC36

V34

V36
AA36

U36

U35

V32

R32

L36

M33

J33

P33

K32

J32
AA34

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

(IPD)
(IPD)

(IPU)

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 3 OF 18

GPIO/TEST/MISC

(IPD)

(IPD)

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

CFSB

FORCE_DFU

DFU_STATUS

HOLD_RESET

ANALOGMUX_OUT

TST_CLKOUT

TESTMODE

DROOP

SOCHOT

XO0
XI0

L33
L35
K36

K34

W32
V33

J34

AN36
P32
C12

L32
L34

AV23
AV24

WLAN_AUDIO_SYNC
NC_DFR_PWR_EN
BT_ROM_BOOT_L

PMU_ACTIVE_READY
SOC_FORCE_DFU

SOC_DFU_STATUS
SOC_HOLD_RESET
TP_SOC_AMUXOUT

TP_SOC_TST_CLKOUT
SOC_TESTMODE

PMU_DROOP_L
SOC_SOCHOT_L

SOC_XTAL24M_OUT
SOC_XTAL24M_IN

IN
OUT
OUT

IN

IN
OUT

IN

IN

IN
OUT

1

R3940

2

77

32

43

43

65

511K

1%
1/20W
MF
201

D

79 32 20

82 79 65 28

79 65 27

82 79 43 27

79 65 34

R3941

0

21

SOC_XTAL24M_OUT_R

5%

1/20W

MF

0201

Y3940

1.60X1.20MM-SM

24MHZ-30PPM-9.5PF-60OHM

C

B

42

42

43

43

43

79 27

79 27

79 27

OUT

OUT
OUT
OUT

BI
BI

IN

I2C_SEP_SDA
I2C_SEP_SCL

SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE

USB_SOC_P
USB_SOC_N

TP_SOC_USB_ID
SOC_USB_VBUS
SOC_USB_REXT

1

R3960

200

1%
1/20W
MF
201

2

AV8

SEP_I2C0_SDA

AT7

SEP_I2C0_SCL

AU9

SEP_SPI0_MISO

AV9

SEP_SPI0_MOSI

AT8

SEP_SPI0_SCLK

B23

USB_DP

A23

USB_DM

D23

USB_ID

E23

USB_VBUS

F22

USB_REXT

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 7 OF 18
SEP/USB/DDR

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

H3
H35
AL3
AL35

N2
AF36

H4
H34
AL4
AL34

G3
G35
AM3
AM35

240

1%

1/20W

MF

201

1

2

R3970

SOC_DDR0_RREF
SOC_DDR1_RREF
SOC_DDR2_RREF
SOC_DDR3_RREF

SOC_DDR0_ZQ
SOC_DDR3_ZQ

AON_SLEEP1_RESET_L

PMU_SYS_ALIVE

R3971

240

1%

1/20W

MF

201

IN

IN

NC GND

1%
MF

201

4312

1

2

1

C3941

12PF

5%
25V

2

CERM
0201

R3974

240

1%

1/20W

MF

201

PP1V1_SLPDDR

240

1%

1/20W

MF

201

1

2

1

2

R3975

75

B

C3940

12PF

240

1%

1/20W

MF

201

1

2

1

2

R3972

35

74 65 35

1

5%

25V

2

CERM
0201

R3973

240

1/20W

A

PP1V8_SLPS2R

R3939

47K

8

43 75

21

5% 201

MF1/20W

SOC_SOCHOT_L

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=03/15/2017

A

SoC GPIO/SEP/USB/DDR/Test

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

79 65 34

BOM_COST_GROUP=T290

67

35 4

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

39 OF 145

SHEET

34 OF 85

1

SIZE

D

D

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 6 OF 18

AOP

(IPU)
(IPU)
(IPU)

(IPD)
(IPD)

AOP_PDM_CLK0
AOP_PDM_CLK1
AOP_PDM_CLK2
AOP_PDM_CLK3
AOP_PDM_CLK4

AOP_PDM_DATA0
AOP_PDM_DATA1

AOP_SPI_MOSI
AOP_SPI_SCLK
AOP_SPI_MISO

P6
K2
J6
L6
L5

J5
K4

D2
F2
E2

PDM_DMIC_CLK0_R
PDM_DMIC_CLK1_R
TP_SMC_FIXTURE_MODE_L
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT

PDM_DMIC_DATA0
PDM_DMIC_DATA1

SPI_AOP_SENSOR_MOSI_R
SPI_AOP_SENSOR_CLK_R
SPI_AOP_SENSOR_MISO

OUT
OUT

OUT
OUT

IN
IN
IN

IN
IN

IN

43

43

79

77

77

54

54

43

43

33

D

79 32

79 32

33

33

33

17

77

33

77

46

46

OUT
OUT

IN
IN

OUT

IN

IN
OUT
OUT

OUT
BI

WLAN_CONTEXT_A
WLAN_CONTEXT_B
ACCEL_INT1
ACCEL_INT2
BTUARTMUX_SEL_PCH
SOC_PERST_L
NC_ALTIMETER_INT
SPI_ACCEL_CS_L
NC_SPI_ALTIMETER_CS_L

NC_I2C_AOP_SCL
NC_I2C_AOP_SDA

D3

AOP_FUNC[0]

F4

AOP_FUNC[1]

M6

AOP_FUNC[2]

D4

AOP_FUNC[3]

F3

AOP_FUNC[4]

K6

AOP_FUNC[5]

E4

AOP_FUNC[6]

J3

AOP_FUNC[7]

H6

AOP_FUNC[8]

N6

AOP_I2C0_SCL

G5

AOP_I2C0_SDA

(IPD)
(IPD)

(IPD)

C

65

65

OUT
BI

SPMI_CLK
SPMI_DATA

R4036
R4037

PLACE_NEAR=U3900.AD6:5MM
PLACE_NEAR=U7800.M7:5MM

20
20

21

5% MF1/20W

21

5% MF

201

1/20W 201

77

42

77

77

18

79 52

32

77

77

43

77

77

65

65

65 43

IN
IN
IN

OUT

IN
OUT
OUT

IN
OUT

IN

IN

IN

IN

IN

IN

NC_DFR_TOUCH_INT_L
CPU_SMC_THRMTRIP_L
NC_SMC_GFX_SELF_THROTTLE
NC_SMC_TOPBLK_SWP_L
XDP_PRESENT_L
CODEC_RESET_L
BT_DEV_WAKE
NC_PCIEDN_WAKE_L
NC_ENET_LOW_PWR
TPAD_SPI_INT_L
NC_SDCONN_STATE_CHANGE_L
NC_ENET_MEDIA_SENSE
PMU_INT_L

SPMI_CLK_R
SPMI_DATA_R

PMU_CLK32K_SOC

79

SOC_COLD_RESET_L

4.7K

R4039

1/20W MF 201

5%

21

PMU_COLD_RESET_L

AL6

AON_GPIO0

AE6

AON_GPIO1

AT5

AON_GPIO2

AN4

AON_GPIO3

AK4

AON_GPIO4

AV5

AON_GPIO5

AR3

AON_GPIO6

AG6

AON_GPIO7

AU5

AON_GPIO8

AP2

AON_GPIO9

AR4

AON_GPIO10

AN3

AON_GPIO11

AT6

AON_GPIO12

AD6

AON_SPMI_SCLK

AR2

AON_SPMI_SDATA

AR5

RT_CLK32768

AK2

COLD_RESET*

AK3

CFSB_AON

(IPD)

(IPU)

(IPU)
(IPD)
(IPU)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 5 OF 18

AON

(IPU)
(IPU)
(IPU)

(IPD)

(IPU)

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

JTAG_TRST*

JTAG_SEL

DOCK_CONNECT

AON_SWD0_TMS
AON_SWD1_TMS

AON_SWD01_TCK

WDOG

AON_SLEEP1_RESET*

AK6
AN5
AH6
AP4
AJ6
AC6

AN2

AJ4
AH4
AJ2

AJ5

AF6

DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
TP_JTAG_SOC_TRST_L
SOC_JTAG_SEL

(DAP=0, TAP=1)

SOC_DOCK_CONNECT
TP_SWD_WLAN_SWDIO

NC_MESA_MENUKEY_L
TP_SWD_WLAN_SWCLK

SOC_WDOG
AON_SLEEP1_RESET_L

79

79

35

OUT

OUT

OUT

IN

IN

IN

BI

BI

77

77

77

65

34

79 20

79 20

79 35 29 28

C

B

A

PP1V8_S5

R4054
R4055
R4056
R4057
R4059

R4046
R4047

100K
100K
100K
100K
100K

10K

100K

OMIT_TABLE

CRITICAL

PLACE_NEAR=U3900.V2:5MM
PLACE_NEAR=U3900.U3:5MM
PLACE_NEAR=U3900.U4:5MM
PLACE_NEAR=U3900.V8:5MM

35 14

35 14

35 14

35 14

75

21
21
21
21
21

21
21

1/20W 2015% MF
1/20W 2015% MF
1/20W 2015% MF
1/20W 2015% MF

BI
BI
BI
BI

MF 2011/20W5%

MF1/20W5% 201
MF 2011/20W5%

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3> ESPI_IO_R<3>

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

SOC_JTAG_SEL
SOC_DOCK_CONNECT

R4050
R4051
R4052
R4053

20

20

35 14

35 14

35 14

35 14

35 14

35

79 35 29 28

21
21

5% MF1/20W

21
21

MF5%201/20W 201

201
1/20W5% MF20201
1/20W5%

82 79 66 65 15

201MF

35 14

79 42

42 19

59 43 42

74 65 34

79 45

79 45

14

14

42

42

42

42

45

45

45

45

45

45

45

45

45

45

45

45

IN
IN
IN

IN

OUT

OUT
OUT

OUT
OUT

IN

BI

IN

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

ESPI_IO_R<0>
ESPI_IO_R<1>
ESPI_IO_R<2>

ESPI_CLK60M
ESPI_CS_L
ESPI_RESET_L

SMC_PECI_RX
SMC_PECI_TX

SMC_PCH_PWROK
SMC_PCH_SYS_PWROK

SMC_RSMRST_L
SMC_SYSRST_L

PM_SLP_S0_L
SMC_PROCHOT_L

PMU_SYS_ALIVE
I2C_UPC_SCL

I2C_UPC_SDA
NC_I2C_SNS0_S0_SCL

NC_I2C_SNS0_S0_SDA
I2C_SNS1_S0_SCL

I2C_SNS1_S0_SDA
I2C_DISP_SCL

I2C_DISP_SDA
I2C_PWR_SCL

I2C_PWR_SDA
I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA
NC_I2C_SSD0_SCL

NC_I2C_SSD0_SDA

V2

SMC_ESPI_IO0

U3

SMC_ESPI_IO1

U4

SMC_ESPI_IO2

V8

SMC_ESPI_IO3

U2

SMC_ESPI_CLK

V7

SMC_ESPI_CS*

V6

SMC_ESPI_RESET*

M5

SMC_PECI_IN

T6

SMC_PECI_OUT

W7

PCH_PWROK

W8

SYS_PWROK

W6

RSMRST*

W4

SYS_RESET*

AA4

SLP_S0B

R5

PROCHOT*

AA6

SYS_ALIVE

M3

SMC_I2C0_SCL

J4

SMC_I2C0_SDA

N4

SMC_I2C1_SCL

P4

SMC_I2C1_SDA

U5

SMC_I2C2_SCL

M2

SMC_I2C2_SDA

U6

SMC_I2C3_SCL

R4

SMC_I2C3_SDA

P3

SMC_I2C4_SCL

T4

SMC_I2C4_SDA

R2

SMC_I2C5_SCL

P2

SMC_I2C5_SDA

R3

SMC_I2C6_SCL

T2

SMC_I2C6_SDA

(IPD)

(IPD)

(IPD)

U3900

H9M

BGA

SYM 9 OF 18

SMC

(IPU)

(IPD)
(IPD)

(IPD)

(IPU)

(IPU)
(IPU)
(IPD)

SMC_GPIO0
SMC_GPIO1
SMC_GPIO2
SMC_GPIO3
SMC_GPIO4
SMC_GPIO5
SMC_GPIO6
SMC_GPIO7
SMC_GPIO8

SMC_GPIO9
SMC_GPIO10
SMC_GPIO11
SMC_GPIO12
SMC_GPIO13
SMC_GPIO14
SMC_GPIO15

SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7

REFP_ADC
REFM_ADC

SMC_PWM0

SMC_TACH0

SMC_PWM1

SMC_TACH1

SMC_PWM2

SMC_UART0_RXD
SMC_UART0_TXD

SWD_OUT0_TCK
SWD_OUT0_TMS

SWD_OUT1_TCK
SWD_OUT1_TMS

Y4
Y8
Y5
AA2
Y7
Y6
AB2
AD5
AD2
AB4
AC2
AC3
AA8
AB3
AE2
L4

AG2
AC4
AH3
AD4
AB6
AH2
AG4
AC5

AF4
AG3

J2
L3

R6
L2

M4

V4
V5

AE3
AA5

AF2
AA7

CODEC_WAKE_L
BT_HOST_WAKE
WLAN_HOST_WAKE
NC_SMC_GFX_THROTTLE_L
LID_OPEN_RIGHT
NC_PCC_EVENT
NC_TPAD_VIBE_L
TPAD_KBD_WAKE_L
LID_OPEN_LEFT
NC_SPI_DESCRIPTOR_OVERRIDE_L
NC_DISP_GCON_INT_L
NC_PCH_GCON_INT_L
TPAD_ACTUATOR_DISABLE_L
TBT_WAKE_L
UPC_I2C_INT_L
NC_GNSS_HOST_WAKE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HS_ISENSE
SMC_3V3G3HMAIN_ISENSE
SMC_5VG3S_ISENSE
SMC_SSD0_ISENSE

PP1V25_SLPS2R_SMC_AVREF
GND_SMC_AVSS

SMC_FAN_0_PWM
SMC_FAN_0_TACH

NC_SMC_FAN_1_PWM
NC_SMC_FAN_1_TACH

NC_SMC_LED_ONEWIRE
TP_SMC_DEBUGPRT_RX

TP_SMC_DEBUGPRT_TX
SSD0_SWCLK_UART_R2D

SSD0_SWDIO_UART_D2R
NC_SSD1_SWCLK_UART_R2D

NC_SSD1_SWDIO_UART_D2R

IN
IN
IN

77

OUT

43

IN

77

IN

77

OUT

43

IN

BI

77

OUT

77

IN

77

OUT

BI

27

IN
IN

77

IN

43

IN

43

IN

43

IN

43

IN

43

IN

43

IN

43

IN

43

IN

42

PLACE_NEAR=U3900.AG3:4MM

51

OUT

51

IN

77

OUT

77

IN

BI

79

IN

79

OUT

OUT

BI

77

OUT

BI

79 54 52

33 32

79 32

43

43

45 27

XW4089

SM

21

77

72 71 70

72 71 70

77

BOM_COST_GROUP=T290

PAGE TITLE

SoC AOP/AON/SMC

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/16/2017SYNC_MASTER=X589_BIGSUR

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

40 OF 145

SHEET

35 OF 85

B

A

SIZE

D

8

67

35 4

2

1

D

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 4 OF 18

ISP

(IPD)

(IPD)

ISP_I2C0_SDA
ISP_I2C0_SCL

ISP_I2C1_SDA
ISP_I2C1_SCL

SENSOR0_CLK
SENSOR0_RST

SENSOR0_ISTRB

SENSOR1_CLK
SENSOR1_RST

SENSOR1_ISTRB

SENSOR2_CLK
SENSOR2_RST

SENSOR_INT

DISP_TE

DISP_VSYNC

CLK32K_OUT

AF32
AH36

AB32
AG32

AK35
AK34
AJ33

AD33
AC32
AC34

AD32
AJ32
AA33

H32

T36

AK33

I2C_FTCAM_SDA
I2C_FTCAM_SCL

NC_I2C_PLCAM_SDA
NC_I2C_PLCAM_SCL

NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
NC_DFR_TOUCH_RESET_L

NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
NC_DFR_DISP_RESET_L

NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_INT

NC_DFR_DISP_TE
BOARD_REV2
NC_DFR_TOUCH_CLK32K_RESET_L

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT

IN

IN

IN

BI

BI

46

46

77

77

77

77

77

77

77

77

77

77

42

77

46

46

D

69

69

77

77

69

69

77

77

77

77

77

77

77

77

77

77

IN
IN
IN

IN
IN

IN
IN
IN
IN

IN
IN

OUT
OUT

OUT
OUT

MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
GND
GND

MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N

GND
GND
GND
GND

GND
GND

NC_MIPI_DFR_DATAP
NC_MIPI_DFR_DATAN

NC_MIPI_DFR_CLKP
NC_MIPI_DFR_CLKN

SOC_MIPI0C_REXT
SOC_MIPI1C_REXT
SOC_MIPID_REXT

B27

MIPI0C_DATA0_P

A27

MIPI0C_DATA0_N

B25

MIPI0C_DATA1_P

A25

MIPI0C_DATA1_N

B26

MIPI0C_CLK_P

A26

MIPI0C_CLK_N

B28

MIPI1C_DATA0_P

A28

MIPI1C_DATA0_N

B30

MIPI1C_DATA1_P

A30

MIPI1C_DATA1_N

B29

MIPI1C_CLK_P

A29

MIPI1C_CLK_N

B33

MIPID_DATA0_P

A33

MIPID_DATA0_N

B32

MIPID_CLK_P

A32

MIPID_CLK_N

F23

MIPI0C_REXT

F26

MIPI1C_REXT

F27

MIPID_REXT

C

B

1

R4100

4.02K

1%
1/20W
MF
201

2

1

R4101

4.02K

1%
1/20W
MF
201

2

79 46

79 46

79 54 52

79 54

46

46

46

46

46

46

46

46

46

46

79

79

44

44

44

44

33

33

33

33

33

33

77

77

32

32

32

32

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

IN
IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

1

R4102

4.02K

1%
1/20W
MF
201

2

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL

TP_I2C_CODEC_SDA
TP_I2C_CODEC_SCL

I2C_ALS_SDA
I2C_ALS_SCL

NC_I2C_DFR_SDA
NC_I2C_DFR_SCL

NC_I2C_SOC_5_SDA
NC_I2C_SOC_5_SCL

SPKR_ID1
SPKR_ID0

TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX

UART_SE_D2R
UART_SE_R2D
UART_SE_D2R_CTS_L
UART_SE_R2D_RTS_L

UART_BT_D2R
UART_BT_R2D
UART_BT_D2R_CTS_L
UART_BT_R2D_RTS_L

UART_BT_LH_D2R
UART_BT_LH_R2D
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L

UART_WLAN_D2R
UART_WLAN_R2D
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L

AE35
AD35

AF34
AG35

M34
R33

Y32

AE34

T34
U32

R35
U33

P34
R34

Y33
Y34

B15
A15
C15
D15

J36
J35
N32
M32

M36
N36
M35
U34

B14
A14
C14
C13

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

I2C2_SDA
I2C2_SCL

I2C3_SDA
I2C3_SCL

I2C4_SDA
I2C4_SCL

I2C5_SDA
I2C5_SCL

I2C6_SDA
I2C6_SCL

UART0_RXD
UART0_TXD

UART1_RXD
UART1_TXD
UART1_CTS*
UART1_RTS*

UART2_RXD
UART2_TXD
UART2_CTS*
UART2_RTS*

UART3_RXD
UART3_TXD
UART3_CTS*
UART3_RTS*

UART4_RXD
UART4_TXD
UART4_CTS*
UART4_RTS*

(IPU)
(IPU)

(IPU)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 2 OF 18

I2C/UART/SPI/I2S

(IPU)

(IPD)

(IPD)

(IPD)

(IPD)

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

I2S0_DIN
I2S0_DOUT
I2S0_BCLK
I2S0_LRCK

I2S0_MCK

I2S1_DIN
I2S1_DOUT
I2S1_BCLK
I2S1_LRCK

I2S1_MCK

I2S2_DIN
I2S2_DOUT
I2S2_BCLK
I2S2_LRCK

I2S2_MCK

I2S3_DIN
I2S3_DOUT
I2S3_BCLK
I2S3_LRCK

I2S3_MCK

AR9
AR7
AU7
AT9

P36
N34
P35
T32

A19
A20
C19
A18

C17
C18
B18
A17

AC33
AG34
AA32
AG33
AR35

B20
C20
C21
A21
D21

AH34
AB34
AF33
AH35
AR33

AD36
AB35
AE36
W34
AG36

SPI_SOCROM_MISO

IN

SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R SPI_SOCROM_CLK
SPI_SOCROM_CS_L

SPI_TPAD_MISO
SPI_TPAD_MOSI_R
SPI_TPAD_CLK_R
SPI_TPAD_CS_L

SPI_MESA_MISO
SPI_MESA_MOSI_R
SPI_MESA_CLK_R
WLAN_THROTTLE

NC_SPI_DFR_MISO
NC_SPI_DFR_MOSI_R
NC_SPI_DFR_CLK_R
NC_SPI_DFR_CS_L

I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_L_R2D_R
I2S_SPKRAMP_L_BCLK_R
I2S_SPKRAMP_L_LRCLK
NC_DFR_TOUCH_RSVD

I2S_SPKRAMP_R_D2R
I2S_SPKRAMP_R_R2D_R
I2S_SPKRAMP_R_BCLK_R
I2S_SPKRAMP_R_LRCLK
NC_PCHROM_SW_EN

I2S_CODEC_D2R
I2S_CODEC_R2D_R
I2S_CODEC_BCLK_R
I2S_CODEC_LRCLK
NC_I2S_CODEC_MCLK

NC_I2S_HAWKING_D2R
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK_R
NC_I2S_HAWKING_LRCLK
NC_I2S_CODEC1_MCLK

OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

BI

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

43 42

R4171
R4172

42

56 42

43

43

56

79 52

43

43

32

77

77

77

77

79 53 52

43

43

43

77

54

43

43

43

77

79 52

43

43

79 52

77

77

77

77

77

77

PLACE_NEAR=U3900.AR7:5MM
PLACE_NEAR=U3900.AU7:5MM

20
20

21
21

SPI_SOCROM_MOSI

2015% 1/20W MF

1/20W MF5%

201

OUT
OUT

C

43 42

43 42

B

A

8

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=03/15/2017

A

SoC ISP/I2C/UART/SPI/I2S

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

41 OF 145

SHEET

36 OF 85

1

SIZE

D

678

3 245

1

OMIT_TABLE

CRITICAL

D

16

16

16

16

16

16

16

16

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

16

PCIE_SOC_D2R_P<0>
PCIE_SOC_D2R_N<0>

PCIE_SOC_D2R_P<1>
PCIE_SOC_D2R_N<1>

PCIE_SOC_D2R_P<2>
PCIE_SOC_D2R_N<2>

PCIE_SOC_D2R_P<3>
PCIE_SOC_D2R_N<3>

OUT

SOC_CLKREQ_L

(All Caps)

GND_VOID=TRUE

C4210

0.22UF

C4211

0.22UF

C4212

0.22UF

C4213

0.22UF

C4214

0.22UF

C4215

0.22UF

C4216

0.22UF

C4217

0.22UF

R4218

21

6.3V X5R 0201

20%

21

X5R6.3V20% 0201

21
20% X5R6.3V 0201

21

20% 6.3V X5R 0201

21

X5R20% 02016.3V

21

X5R 02016.3V20%

21

6.3V20% X5R 0201

21

020120% X5R6.3V

21

5%1K1/20W MF 201

43

43

43

43

43

43

43

43

16

16

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

PCIE_SOC_D2R_C_P<0>
PCIE_SOC_D2R_C_N<0>
PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

PCIE_SOC_D2R_C_P<1>
PCIE_SOC_D2R_C_N<1>
PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

PCIE_SOC_D2R_C_P<2>
PCIE_SOC_D2R_C_N<2>
PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_D2R_C_P<3>
PCIE_SOC_D2R_C_N<3>
PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

SOC_CLKREQ_R_L
PCIE_CLK100M_SOC_P

PCIE_CLK100M_SOC_N
SOC_PCIE_UP_REXT

1

R4200

3.01K

1%
1/20W
MF
201

2

B10

PCIE_UP_TX0_P

C10

PCIE_UP_TX0_N

E10

PCIE_UP_RX0_P

F10

PCIE_UP_RX0_N

A9

PCIE_UP_TX1_P

B9

PCIE_UP_TX1_N

D9

PCIE_UP_RX1_P

E9

PCIE_UP_RX1_N

B8

PCIE_UP_TX2_P

C8

PCIE_UP_TX2_N

E8

PCIE_UP_RX2_P

F8

PCIE_UP_RX2_N

A7

PCIE_UP_TX3_P

B7

PCIE_UP_TX3_N

D7

PCIE_UP_RX3_P

E7

PCIE_UP_RX3_N

B21

PCIE_UP_CLKREQ*

G13

PCIE_UP_EXT_REFCLK_P

G12

PCIE_UP_EXT_REFCLK_N

G11

PCIE_UP_REXT

U3900

H9M

BGA

SYM 1 OF 18

PCIE UP/DN

PCIE_DN_TX0_P
PCIE_DN_TX0_N
PCIE_DN_RX0_P
PCIE_DN_RX0_N

PCIE_DN_TX1_P
PCIE_DN_TX1_N
PCIE_DN_RX1_P
PCIE_DN_RX1_N

PCIE_DN_TX2_P
PCIE_DN_TX2_N
PCIE_DN_RX2_P
PCIE_DN_RX2_N

PCIE_DN_TX3_P
PCIE_DN_TX3_N
PCIE_DN_RX3_P
PCIE_DN_RX3_N

PCIE_DN_REFCLK0_P
PCIE_DN_REFCLK0_N

PCIE_DN_CLKREQ0*

PCIE_DN_PERST0*

PCIE_DN_REFCLK1_P
PCIE_DN_REFCLK1_N

PCIE_DN_CLKREQ1*

PCIE_DN_PERST1*

PCIE_DN_REFCLK2_P
PCIE_DN_REFCLK2_N

PCIE_DN_CLKREQ2*

PCIE_DN_PERST2*

AV31
AU31
AR31
AP31

AU30
AT30
AP30
AN30

AV29
AU29
AR29
AP29

AU28
AT28
AP28
AN28

AP26
AR26
AM33
AN34

AN25
AP25
AN35
AK32

AU26
AV26
AH32
AE32

NC_PCIE_WLAN_R2D_CP
NC_PCIE_WLAN_R2D_CN
NC_PCIE_WLAN_D2RP
NC_PCIE_WLAN_D2RN

NC_PCIE_ENET_R2D_CP
NC_PCIE_ENET_R2D_CN
NC_PCIE_ENET_D2RP
NC_PCIE_ENET_D2RN

TP_PCIE_DN2_R2D_CP
TP_PCIE_DN2_R2D_CN
TP_PCIE_DN2_D2RP
TP_PCIE_DN2_D2RN

TP_PCIE_DN3_R2D_CP
TP_PCIE_DN3_R2D_CN
TP_PCIE_DN3_D2RP
TP_PCIE_DN3_D2RN

NC_PCIE_CLK100M_WLANP
NC_PCIE_CLK100M_WLANN
NC_WLAN_CLKREQ_L
NC_WLAN_PERST_L

NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_ENETN
ENET_CLKREQ_L
NC_ENET_RESET_L

TP_PCIE_CLK100M_DN2P
TP_PCIE_CLK100M_DN2N
TP_PCIEDN2_CLKREQ_L
TP_PCIEDN2_RESET_L

37

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN

OUT

OUT
OUT

OUT

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

D

(UID_MODE strap on A00)

C

B

74

74

70

70

74

74

71

71

74

74

72

72

74

74

74

74

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

PCIE_SSD0_R2D_C_P<0>
PCIE_SSD0_R2D_C_N<0>
PCIE_SSD0_D2R_P<0>
PCIE_SSD0_D2R_N<0>

PCIE_SSD0_R2D_C_P<1>
PCIE_SSD0_R2D_C_N<1>
PCIE_SSD0_D2R_P<1>
PCIE_SSD0_D2R_N<1>

PCIE_SSD0_R2D_C_P<2>
PCIE_SSD0_R2D_C_N<2>
PCIE_SSD0_D2R_P<2>
PCIE_SSD0_D2R_N<2>

NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>

AU11
AT11
AP11
AN11

AV12
AU12
AR12
AP12

AU13
AT13
AP13
AN13

AV14
AU14
AR14
AP14

PCIE_STG0_TX0_P
PCIE_STG0_TX0_N
PCIE_STG0_RX0_P
PCIE_STG0_RX0_N

PCIE_STG0_TX1_P
PCIE_STG0_TX1_N
PCIE_STG0_RX1_P
PCIE_STG0_RX1_N

PCIE_STG0_TX2_P
PCIE_STG0_TX2_N
PCIE_STG0_RX2_P
PCIE_STG0_RX2_N

PCIE_STG0_TX3_P
PCIE_STG0_TX3_N
PCIE_STG0_RX3_P
PCIE_STG0_RX3_N

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 8 OF 18

PCIE STG 0/1

PCIE_DN_REFCLK3_P
PCIE_DN_REFCLK3_N

PCIE_DN_CLKREQ3*

PCIE_DN_PERST3*

PCIE_DN_EXT_REFCLK_P
PCIE_DN_EXT_REFCLK_N

PCIE_DN_REXT

PCIE_STG1_TX0_P
PCIE_STG1_TX0_N
PCIE_STG1_RX0_P
PCIE_STG1_RX0_N

PCIE_STG1_TX1_P
PCIE_STG1_TX1_N
PCIE_STG1_RX1_P
PCIE_STG1_RX1_N

PCIE_STG1_TX2_P
PCIE_STG1_TX2_N
PCIE_STG1_RX2_P
PCIE_STG1_RX2_N

PCIE_STG1_TX3_P
PCIE_STG1_TX3_N
PCIE_STG1_RX3_P
PCIE_STG1_RX3_N

AT25
AU25
AJ34
AK36

AM27
AM26

AM25

AU16
AT16
AP16
AN16

AV17
AU17
AR17
AP17

AU18
AT18
AP18
AN18

AV19
AU19
AR19
AP19

TP_PCIE_CLK100M_DN3P
TP_PCIE_CLK100M_DN3N
TP_PCIEDN3_CLKREQ_L
TP_PCIEDN3_RESET_L

SOC_PCIE_DN_REXT

R4201

3.01K

1%

1/20W

MF

201

NC_PCIE_SSD1_R2D_CP<0>
NC_PCIE_SSD1_R2D_CN<0>
NC_PCIE_SSD1_D2RP<0>
NC_PCIE_SSD1_D2RN<0>

NC_PCIE_SSD1_R2D_CP<1>
NC_PCIE_SSD1_R2D_CN<1>
NC_PCIE_SSD1_D2RP<1>
NC_PCIE_SSD1_D2RN<1>

NC_PCIE_SSD1_R2D_CP<2>
NC_PCIE_SSD1_R2D_CN<2>
NC_PCIE_SSD1_D2RP<2>
NC_PCIE_SSD1_D2RN<2>

NC_PCIE_SSD1_R2D_CP<3>
NC_PCIE_SSD1_R2D_CN<3>
NC_PCIE_SSD1_D2RP<3>
NC_PCIE_SSD1_D2RN<3>

C

1

2

77

OUT

77

OUT

77

IN

77

IN

77

OUT

77

OUT

B

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

77

77

77

77

77

77

77

77

77

77

A

PP1V8_AWAKE

R4232

47K

71 70

71 70

70 43

71 43

72

72

72 43

43

72 71 70 43

43

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT

OUT

PCIE_CLK100M_SSD0_01_P
PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_CLKREQ1_L

PCIE_CLK100M_SSD0_23_P
PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ2_L
SSD0_CLKREQ3_L

SSD0_PCIE_RESET_L

SSD0_CLK24M_R

AP21
AR21
AT33
AR34

AN22
AP22
AP34
AN33

AR36

AP7

AM14
AM15

PCIE_STG0_REFCLK01_P
PCIE_STG0_REFCLK01_N
PCIE_STG0_CLKREQ0*
PCIE_STG0_CLKREQ1*

PCIE_STG0_REFCLK23_P
PCIE_STG0_REFCLK23_N
PCIE_STG0_CLKREQ2*
PCIE_STG0_CLKREQ3*

PCIE_STG0_PERST*

PCIE_STG0_NANDCLK

PCIE_STG0_EXT_REFCLK_P
PCIE_STG0_EXT_REFCLK_N

PCIE_STG1_REFCLK01_P
PCIE_STG1_REFCLK01_N

PCIE_STG1_CLKREQ0*
PCIE_STG1_CLKREQ1*

PCIE_STG1_REFCLK23_P
PCIE_STG1_REFCLK23_N

PCIE_STG1_CLKREQ2*
PCIE_STG1_CLKREQ3*

PCIE_STG1_PERST*

PCIE_STG1_NANDCLK

PCIE_STG1_EXT_REFCLK_P
PCIE_STG1_EXT_REFCLK_N

AU21
AV21
B17
D18

AT22
AU22
C16
A16

AP36

AV7

AM19
AM20

NC_PCIE_CLK100M_SSD1_01P
NC_PCIE_CLK100M_SSD1_01N
NC_SSD1_CLKREQ0_L
NC_SSD1_CLKREQ1_L

NC_PCIE_CLK100M_SSD1_23P
NC_PCIE_CLK100M_SSD1_23N
NC_SSD1_CLKREQ2_L
NC_SSD1_CLKREQ3_L

NC_SSD1_PCIE_RESET_L

NC_SSD1_CLK24M_R

OUT
OUT

OUT
OUT

OUT

OUT

IN
IN

IN
IN

77

77

77

77

77

77

77

77

77

77

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=03/15/2017

A

SoC PCIe

SOC_PCIE_STG0_REXT

1

R4250

3.01K

1%

2

1/20W
MF
201

42 43 75

21

1/20W

ENET_CLKREQ_L

201MF5%

37

AM16

PCIE_STG0_REXT

PCIE_STG1_REXT

AM21

SOC_PCIE_STG1_REXT

R4251

3.01K

1%

1/20W

MF

201

DRAWING NUMBER

051-04039

1

Apple Inc.

REVISION

SIZE

D

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

2

BOM_COST_GROUP=T290

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

42 OF 145

SHEET

37 OF 85

8

67

35 4

2

1

678

3 245

1

D

C

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

PPVDDCPU_AWAKE

75

0.625V - 1.06V

11.6A Max

CRITICAL

C4300

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4305

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4320

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4330

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4301

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4306

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4321

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4331

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4302

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4307

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4322

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4332

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4303

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4308

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4323

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4333

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4304

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4309

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4324

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4334

4.3UF

20%

4V
CERM
0402

1

3

AA12
AA14
AA16
AB11
AB13
AB15
AC12
AC14
AC16
AD11
AD13
AD15
AD17
AE10
AE12
AE14
AE16
AE18

P11
P13
P15
P17
R12
R14
R16
T11
T13
T15
U12
U14
U16
V17
W12
W14
W16
Y17

VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU

OMIT_TABLE
CRITICAL

U3900

H9M

BGA

SYM 10 OF 18

VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM

VDD_CPU_SENSE

VSS_CPU_SENSE

AA10
AB17
AC10
R10
T17
U10
V11
V13
V15
W10
Y11
Y13
Y15

N18

N17

CRITICAL

C4350

9.1UF

20%

4V
CERM
0402

1

4

2

CRITICAL

C4355

4.3UF

20%

4V
CERM
0402

1

4

2

3

3

CRITICAL

C4351

1

CRITICAL

C4356

1

CRITICAL

C4360

4.3UF

20%

4V
CERM
0402

1

SOC_VDDCPU_SENSE
TP_SOC_VSSCPU_SENSE

3

4

2

9.1UF

20%

4V
CERM
0402

4

2

4.3UF

20%

4V
CERM
0402

4

2

3

3

OUT

CRITICAL

C4352

9.1UF

20%

4V
CERM
0402

1

65

3

4

2

CRITICAL

C4353

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4354

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4357

9.1UF

20%

4V
CERM
0402

1

3

4

2

PPVDDCPUSRAM_AWAKE

0.8V - 1.06V

0.9A Max

75

D

C

B

A

PP0V82_SLPDDR

75

5.6A Max

4

4

4

4

4

2

2

2

2

2

OMIT_TABLE
CRITICAL

U3900

H9M

BGA

SYM 11 OF 18

VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

VDD_SOC_SENSE

VSS_SENSE

J22
J24
J26
J28
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
N10
N12
N14
N16
N20
N22
N24
N26
N28
R18
R20
R22
R24
R26
R28
U18
U20
U22
U24
U26
U28
W20
W22
W24
W26
W28

AD27

AD28

TP_SOC_VDDSOC_SENSE
TP_SOC_VSSSOC_SENSE

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

IV ALL RIGHTS RESERVED

SoC Power 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SYNC_DATE=02/13/2017

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

43 OF 145

SHEET

38 OF 85

B

A

SIZE

D

CRITICAL

C4370

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4380

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4385

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4371

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4381

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4386

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4372

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4373

9.1UF

20%

4V
CERM
0402

1

3

4

2

AA20
AA22
AA24
AA26
AA28
AC18
AC20
AC22
AC24
AC26
AC28
AE20
AE22
AE24
AE26
AE28
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28

J10
J12
J14
J16
J18
J20

VDD_SOC VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

8

67

35 4

2

1

678

3 245

1

D

C

B

A

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

PP1V1_SLPDDR

75

0.86A Max
CRITICAL

1

2

C4451

X6S-CERM

CRITICAL

1

2

C4455

X6S-CERM

2.2UF

20%

4V

0201

2.2UF

20%

4V

0201

PP0V9_SLPDDR

75

1.9A Max

9mA Max

PP0V9_SLPDDR

75

PP0V9_SLPDDR

75

5mA Max

PP0V9_SLPDDR

75

25mA Max

PP0V8_SLPS2R

75

102mA Max

PP0V9_SLPDDR

39 75

330mA Max

CRITICAL

C4400

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4405

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4410

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4401

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4406

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4411

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

CRITICAL

C4425

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4402

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4420

4.3UF

20%

4V
CERM
0402

1

3

4

2

C4423

2.2UF

20%

4V

X6S-CERM

0201

CRITICAL

C4426

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4450

2.2UF

20%

4V

X6S-CERM

0201

CRITICAL

C4454

2.2UF

20%

4V

X6S-CERM

0201

U3900

H9M

AB19
AB21
AB23
AB25
AB27
AD19
AD21
AD23
AD25
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AF27
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AK11

K11
K13
K15
K17

W18

G22

H23
H25
H27

AB9
AD9

1

2

H11
H13
H15

J15
J11
J13

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

VDD_FIXED_CPU

VDD_FIXED_USB

VDD_FIXED_MIPI
VDD_FIXED_MIPI
VDD_FIXED_MIPI

VDD_LOW
VDD_LOW

P9

VDD_LOW

T9

VDD_LOW

V9

VDD_LOW

Y9

VDD_LOW

VDD_FIXED_UP_PCIE_ANA
VDD_FIXED_UP_PCIE_ANA
VDD_FIXED_UP_PCIE_ANA

VDD_FIXED_UP_PCIE_CLK
VDD_FIXED_UP_PCIE_CLK
VDD_FIXED_UP_PCIE_CLK

BGA

SYM 12 OF 18

OMIT_TABLE
CRITICAL

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA

VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK

VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA

VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK

VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA

VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK

VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF

K19
K21
K23
K25
K27
M11
M13
M15
M17
M19
M21
M23
M25
M27
P19
P21
P23
P25
P27
T19
T21
T23
T25
T27
V19
V21
V23
V25
V27
Y19
Y21
Y23
Y25
Y27

AL14
AL16
AL12

AK13
AK15
AK17

AL18
AL20
AL22

AK19
AK21
AL17

AL26
AL28

AL30

AK25
AK27
AK29

AK23
AJ15

AL24
AJ21
AJ27

CRITICAL

1

C4452

2.2UF

2

X6S-CERM

CRITICAL

1

C4456

2.2UF

2

X6S-CERM

CRITICAL

C4430

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4435

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4440

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4445

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

20%

4V

0201

1

C4453

2.2UF

2

X6S-CERM

20%

4V

0201

1

2

CRITICAL

20%

4V

0201

1

C4457

2.2UF

2

X6S-CERM

20%

4V

0201

1

2

C36
E37
G37
H30
J29
K30
L29
M30
N29
P37
R37
U37

AB1
AD1
AE1
AF9
AG8
AH9
AJ8
AK9
AL8
AM1
AP1
AT2

AB37
AD30
AD37
AE29
AE37
AF30
AG29
AH30
AJ29
AM37
AP37
AT36

PP0V9_SLPDDR

CRITICAL

C4431

4.3UF

20%

4V
CERM
0402

1

3

4

2

PP0V9_SLPDDR

CRITICAL

C4436

4.3UF

20%

4V
CERM
0402

1

3

4

2

PP0V9_SLPDDR

CRITICAL

C4441

4.3UF

20%

4V
CERM
0402

1

PP0V9_SLPDDR_SOC_PCIEREFBUF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V

3

4

2

C2
E1
G1
H8
J9
K8
L9
M8
N9
P1
R1
U1

OMIT_TABLE
CRITICAL

330mA Max

330mA Max

330mA Max

R4445

0

2 1

5%

1/20W

MF

0201

U3900

H9M

BGA

39 75

39 75

39 75

PP0V9_SLPDDR

G9
G29
AM9
AK30

G4
G34
AM4
AM34

CRITICAL

1

C4460

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C4470

2.2UF

20%
4V

2

X6S-CERM
0201

45mA Max

PP1V1_SLPDDR

75

8mA Max

CRITICAL

1

C4461

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C4471

2.2UF

20%
4V

2

X6S-CERM
0201

39 75

BOM_COST_GROUP=T290

CRITICAL

1

C4462

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C4472

2.2UF

20%
4V

2

X6S-CERM
0201

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F

CRITICAL

1

C4463

0.22UF

20%

6.3V

2

X6S-CERM
0201

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.1V

Current included in VDD2

PP1V1_SLPS2R

CRITICAL

1

C4473

2.2UF

20%
4V

2

X6S-CERM
0201

SoC Power 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

R4460

5.1

21

1% MF1/20W

0201

L4460

120-OHM-25%-0.48A-0.21DCR

21

0201

75

SYNC_DATE=02/13/2017

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

44 OF 145

SHEET

39 OF 85

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

3 245

1

D

C

B

A

PP1V8_AWAKE

75

40mA Max

PP1V8_AWAKE

75

2mA Max

1mA Max

PP1V8_SLPS2R

75

PP1V8_SLPS2R

75

1mA Max

CRITICAL

PP1V8_SLPS2R

75

20mA Max

C4521

2.2UF

20%

4V

X6S-CERM

0201

PP1V8_SLPS2R

75

134mA Max

CRITICAL

1

C4522

2.2UF

2

X6S-CERM

0201

R4530

0

5%

1/20W

MF

0201

R4515

1% MF 2011/20W

R4519

1% 1/20W MF 201

CRITICAL

1

20%

4V

2

21

CRITICAL

C4530

X6S-CERM

75

CRITICAL

C4500

2.2UF

X6S-CERM

CRITICAL

C4510

2.2UF

20%

4V

X6S-CERM

0201

49.9

49.9

C4523

1UF

20%

6.3V
0201

PP1V8_AWAKE

20mA Max

21

21

2.2UF

20%

4V

X6S-CERM

0201

PP1V8_AWAKE_SOC_TSADC_RC

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750

1

2

PP1V8_SLPS2R_SOC_LPADC_RC

PP1V8_SLPS2R_SOC_LPOSC_RC

1

2

CRITICAL

20%

4V

0201

1

2

C4501

2.2UF

20%

4V

X6S-CERM

0201

CRITICAL

1

2

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

75

C4511

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4524

4.3UF

20%

4V
CERM
0402

1

PP1V8_AWAKE

3

4

2

C4525

4.3UF

CERM
0402

1

2

7mA Max

CRITICAL

10%

6.3V
X6S

0201

1

2

C4540

0.1UF

CRITICAL

1

2

C4502

2.2UF

20%

4V

X6S-CERM

0201

CRITICAL

1

2

CRITICAL

C4512

4.3UF

20%

4V
CERM
0402

1

4

2

CRITICAL

C4519

CRITICAL

C4513

3

1

2.2UF

20%

4V

X6S-CERM

CRITICAL

2

0201

0.1UF

10%

6.3V
X6S

0201

CRITICAL

CRITICAL

C4526

20%

4V

3

4

CRITICAL

PP1V8_AWAKE_SOC_FMON_F

4.3UF

20%

4V
CERM
0402

1

3

4

2

1

CRITICAL

20%

4V

0201

1

2

C4535

2.2UF

X6S-CERM

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

C4503

2.2UF

20%

4V

X6S-CERM

0201

1

2

C4515

20UF

20%

2.5V

X6S-CERM

0402

C4527

4.3UF

20%

4V
CERM
0402

3

4

2

C4536

0.1UF

10%

6.3V
X6S

0201

D

OMIT_TABLE
CRITICAL

U3900

H9M

A4

VDD1 VDD12_CPU_UVD

1

2

1

2

1

2

AV34

AV4
B35

W1

W37

Y1

Y37

AA9

P8
R9
T8
U9
W9

AC9
AD8
AE9

AB8

AB10

AA29
AB30
AC29

P30
R29
T30

U29
V30
W29
Y30

G16

G18

G20
H17
H19
H21

AK31
AM31

AL11
AM10

AA18

P16

AD16
AF18

H28

G23
G25
G27

H22

AF12

AM30
AK12

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1

VDDIO18_AOP2
VDDIO18_AOP2
VDDIO18_AOP2

VDD18_LPADC

VDD18_LPOSC

VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1

VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2

VDDIO18_GRP3
VDDIO18_GRP3

VDDIO18_GRP4
VDDIO18_GRP4

VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC

VDD18_MIPI
VDD18_MIPI
VDD18_MIPI

VDD18_USB

VDD18_FMON

VDD18_EFUSE1
VDD18_EFUSE2

SYM 14 OF 18

BGA

VDD12_PLL_CPU

VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF

VDD12_DN_PCIE
VDD12_UP_PCIE

VDD12_STG0_PCIE
VDD12_STG1_PCIE

VDD12_PLL_SOC
VDD12_PLL_SOC
VDD12_PLL_SOC

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

VDD11_XTAL

VDD33_USB

Y18

V18

AK24
AM23

AM29
G14

AM13
AM18

AC23
AD24
AE23

AG1
AG37
AJ1
AJ37
AK1
AK37
AU3
AU34
AU35
AU4
B3
B4
C34
D34
J1
J37
K1
K37
M1
M37
W3
W35
Y3
Y35

AN23

F21

PP1V2_AWAKE

10mA Max

CRITICAL

1

C4550

2.2UF

20%
4V

2

X6S-CERM
0201

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V2_AWAKE_SOC_PLLCPU_F
PP1V2_AWAKE_SOC_PCIEREFBUF_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V2_AWAKE_SOC_PCIEPLL_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V2_AWAKE_SOC_PLLSOC_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V1_SLPDDR_SOC_XTAL_F

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP3V3_AWAKE

75

12mA Max

CRITICAL

1

C4595

0.1UF

10%

6.3V

2

X6S
0201

75

C4560

0.1UF

10%

6.3V
X6S

0201

C4565

2.2UF

20%

4V

X6S-CERM

0201

C4570

0.1UF

10%

6.3V
X6S

0201

CRITICAL

C4590

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

C4580

2.2UF

20%
4V

2

X6S-CERM
0201

0.1UF

10%

6.3V
X6S

0201

R4555

0

21

5%

C4555

0.1UF

10%

6.3V
X6S

0201

1

2

1/20W

MF

0201

R4560

0

21

5%

1/20W

MF

0201

CRITICAL

1

C4561

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

20%

4V

0201

1

2

C4566

2.2UF

20%

4V

X6S-CERM

0201

1

C4567

2.2UF

2

X6S-CERM

R4570

0

21

5%

C4571

0.1UF

10%

6.3V
X6S

0201

1

2

1/20W

MF

0201

CRITICAL

1

C4581

2.2UF

20%
4V

2

X6S-CERM
0201

1

2

R4590

5.1

21

1%

1/20W MF 0201

L4590

FERR-240OHM-25%-350MA

21

0201

1

2

CRITICAL

1

2

PP1V2_AWAKE

PP1V2_AWAKE

CRITICAL

1

C4562

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

C4568

2.2UF

X6S-CERM

0201

PP1V2_AWAKE

CRITICAL

1

C4572

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

C4582

2.2UF

20%
4V
X6S-CERM
0201

PP1V1_SLPDDR

C4591

2.2UF

20%
4V
X6S-CERM
0201

1

20%

4V

2

PP1V1_SLPS2R

CRITICAL

1

C4583

2.2UF

20%
4V

2

X6S-CERM
0201

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

13mA Max

80mA Max

R4565

0

21

5%

1/20W

MF

0201

31mA Max

4mA Max

75

40 75

PP1V2_AWAKE

75

1.74A Max

75

75

60mA Max

40 75

SYNC_DATE=02/13/2017

C

B

A

8

PP1V8_AWAKE

75

1mA Max

R4545

49.9

1/20W

1%
MF

201

21

67

CRITICAL

1

C4545

1UF

20%

6.3V

2

X6S-CERM
0201

SoC Power 3

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

45 OF 145

SHEET

40 OF 85

1

SIZE

D

678

3 245

1

D

C

B

A1
A10
A11

A2
A22
A24

A3
A31
A34
A35
A36
A37

A5

A6

A8
AA1

AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27

AA3

AA30
AA31
AA35
AA37
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB29
AB31
AB33

AB5
AB7
AC1

AC11
AC13
AC15
AC17
AC19
AC21
AC25
AC27
AC30
AC31
AC35
AC37

AC7
AC8

AD10
AD12
AD14
AD18
AD20
AD22
AD26
AD29

AD3

AD31
AD34

AD7

AE11
AE13
AE15
AE17
AE19
AE21
AE25
AE27
AE30
AE31
AE33

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 15 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE4
AE5
AE7
AE8
AF1
AF10
AF14
AF16
AF20
AF22
AF24
AF26
AF28
AF29
AF3
AF31
AF35
AF37
AF5
AF7
AF8
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG30
AG31
AG5
AG7
AG9
AH1
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH29
AH31
AH33
AH37
AH5
AH7
AH8
AJ11
AJ13
AJ17
AJ19
AJ23
AJ25
AJ3
AJ30
AJ31
AJ35
AJ7
AJ9
AK10
AK14
AK16
AK18
AK20
AK22
AK26
AK28
AK5
AK7
AK8
AL1
AL10
AL13
AL15
AL19
AL2

AL21
AL23
AL25
AL27
AL29
AL31
AL32
AL33
AL36
AL37

AL5
AL7

AL9
AM11
AM12
AM17

AM2
AM22
AM24
AM28
AM32
AM36

AM5

AM6

AM7

AM8

AN1
AN10
AN12
AN14
AN15
AN17
AN19
AN20
AN21
AN24
AN26
AN27
AN29
AN31
AN32
AN37

AN6

AN7

AN8

AN9
AP10
AP15
AP20
AP23
AP24
AP27

AP3
AP32
AP33
AP35

AP5

AP6

AP8

AP9

AR1
AR10
AR11
AR13
AR15
AR16
AR18
AR20
AR22
AR23
AR24
AR25
AR27
AR28
AR30
AR32
AR37

AR6

AR8

AT1
AT10
AT12
AT14
AT15
AT17

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 16 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT19
AT20
AT21
AT23
AT24
AT26
AT27
AT29
AT3
AT31
AT32
AT34
AT35
AT37
AT4
AU1
AU10
AU15
AU2
AU20
AU23
AU24
AU27
AU32
AU33
AU36
AU37
AU6
AU8
AV1
AV10
AV11
AV13
AV15
AV16
AV18
AV2
AV20
AV22
AV25
AV27
AV28
AV3
AV30
AV32
AV33
AV35
AV36
AV37
AV6
B1
B11
B13
B16
B19
B2
B22
B24
B31
B34
B36
B37
B5
B6
C1
C11
C22
C23
C24
C25
C26
C27
C28
C29
C3
C30
C31
C32
C33
C35
C37
C4
C5
C6

C7
C9

D1
D10
D11
D12
D13
D14
D16
D17
D19
D20
D22
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D35
D36
D37

D5

D6

D8
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E24
E25
E26
E27
E28
E29

E3
E30
E31
E32
E33
E34
E35
E36

E5

E6

F1
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F24
F25
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37

F5

F6

F7

F9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 17 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G10
G15
G17
G19
G2
G21
G24
G26
G28
G30
G31
G32
G33
G36
G6
G7
G8
H1
H10
H12
H14
H16
H18
H2
H20
H24
H26
H29
H31
H33
H36
H37
H5
H7
H9
J17
J19
J21
J23
J25
J27
J30
J31
J7
J8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K29
K3
K31
K33
K35
K5
K7
K9
L1
L11
L13
L15
L17
L19
L21
L23
L25
L27
L30
L31
L37
L7
L8
M10
M12
M14
M16
M18
M20

M22
M24
M26
M28
M29
M31

M7
M9

N1
N11
N13
N15
N19
N21
N23
N25
N27

N3
N30
N31
N33
N35
N37

N5

N7

N8
P10
P12
P14
P18
P20
P22
P24
P26
P28
P29
P31

P5

P7
R11
R13
R15
R17
R19
R21
R23
R25
R27
R30
R31

R7

R8

T1
T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 18 OF 18

OMIT_TABLE
CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T3
T31
T33
T35
T37
T5
T7
U11
U13
U15
U17
U19
U21
U23
U25
U27
U30
U31
U7
U8

V1

V10
V12
V14
V16
V20
V22
V24
V26
V28
V29
V3
V31
V35
V37
W11
W13
W15
W17
W19
W2
W21
W23
W25
W27
W30
W31
W33
W36
W5
Y10
Y12
Y14
Y16
Y2
Y20
Y22
Y24
Y26
Y28
Y29
Y31
Y36

D

C

B

A

8

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=02/13/2017

A

SoC Ground

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

46 OF 145

SHEET

41 OF 85

1

SIZE

D

678

3 245

1

PECI Level Shifting

D

34

34

34

43 36

43 36

43 36

56 43

56 36

56 43

Boot Config

OUT
OUT
OUT

BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2

Board ID

OUT
OUT
OUT
OUT
OUT
OUT

SPI_SOCROM_CLK
SPI_SOCROM_MOSI
SPI_SOCROM_MISO
SPI_TPAD_MOSI
SPI_TPAD_MISO
SPI_TPAD_CLK

BOOTCFG0

1

R4700

1K

5%
1/20W
MF
201

2

1

R4710

3.0K

5%
1/20W
MF
201

2

BOOTCFG1

1

R4701

1K

5%
1/20W
MF
201

2

BOARDID1BOARDID0

1

R4711

3.0K

5%
1/20W
MF
201

2

PP1V8_AWAKE

BOOTCFG2

1

R4702

1K

5%
1/20W
MF
201

2

BOARDID2

1

R4712

3.0K

5%
1/20W
MF
201

2

BOARDID3

1

R4713

3.0K

5%
1/20W
MF
201

2

37 42 43 75

BOOTCFG2

BOARDID4

1

R4714

3.0K

5%
1/20W
MF
201

2

0
0
1
1

BOOTCFG0

0
1

BOOTCFG1

0
1
0
1

PP1V8_AWAKE

BOARDID5

1

R4715

3.0K

5%
1/20W
MF
201

2

Test Mode

Disabled

Enabled

Frequency

40 MHz

6 MHz

24 MHz

Invalid

37 42 43
75

35

IN

BYPASS=U4750::5MM

PLACE_NEAR=U3900.T6:5MM

R4750

0

21

5% 1/20W MF 0201

PP1V8_S5

75

BYPASS=U4755::5MM

SMC_PECI_TX_RSMC_PECI_TX

C4755

X5R-CERM

35

OUT

SMC_PECI_RX

C4750

0.1UF

10%
10V

X5R-CERM

0201

0.1UF

10%
10V

0201

PP1V_S3

75

U4750

A2

74AUC1G126

BGA-YZP

B1

A

126

OE

1

C1

2

1

2

1

U4755

74AVC1T45

SOT886

A

5

DIR

CRITICAL

GND

2

C2

Y

CRITICAL

A1

6

VCCBVCCA

B

D

BYPASS=U4755::5MM

1

C4756

0.1UF

10%
10V

2

X5R-CERM
0201

43

330

5%

1/20W

MF

201

1

2

R4755

CPU_PECI

BI

6

C

34

34

36

PP1V8_AWAKE

75

Board Revision

BOARDREV0

1

R4720

1K

5%
1/20W
MF
201

2

OUT
OUT
OUT

BOARD_REV0
BOARD_REV1
BOARD_REV2

SEP EEPROM

BOARDREV1

1

R4721

1K

5%
1/20W
MF
201

2

PP1V8_AWAKE

BOARDREV2

1

R4722

1K

5%
1/20W
MF
201

2

See <rdar://31841051> for J140 assignments

37 42 43 75

PCH PM Level Shifting

PP1V8_SLPS2R

75

BYPASS=U4760::5MM

PQFP

GND

10

2

11

VCCBVCCA

15

1B1

13

2B1

14

1B2

12

2B2

3

U4760

SN74AVC4T245RSV

CRITICAL

10%
10V

0201

1

2

1

2

6

1A1

8

2A1

4

1DIR

1

1OE*

7

1A2

9

2A2

5

2DIR

16

2OE*

C4760

0.1UF

X5R-CERM

35

IN

79 35 79 15

35 19

IN OUT

35

IN
IN

SMC_SYSRST_L
SMC_PCH_SYS_PWROK

SMC_PCH_PWROK

R4760

100K

5%

1/20W

MF

201

2

1

R4761

100K

5%

1/20W

MF

201

2

1

R4762

100K

5%

1/20W

MF

201

1

2

R4763

100K

5%

1/20W

MF

201

BYPASS=U4760::5MM

1

C4765

0.1UF

10%
10V

2

X5R-CERM
0201

1

R4765

100K

5%
1/20W
MF
201

2

1

R4767

100K

5%
1/20W
MF
201

2

1

R4766

100K

5%
1/20W
MF
201

2

PP3V3_S5

1

R4768

100K

5%
1/20W
MF
201

2

PM_SYSRST_R_L

5% 1/20W MF 201

75

R4769

2.2K

21

PM_SYSRST_L
PM_PCH_SYS_PWROK

PM_PCH_PWROK
PM_RSMRST_LSMC_RSMRST_L

OUT

OUT
OUT

15

C

33 15

20 15

B

A

5%

1/20W

MF

201

1

2

I2C_SEP_SCL

R4730

2.2K

34

IN BI

Swapped for non CSP package per

rdar://problem/33172008

SDA pull added per

rdar://problem/30924615

SMC AVREF Supply

Footprint supports 353S01042 alternate

PP1V8_SLPS2R

75

BYPASS=U4780::3MM

20%

6.3V
X5R

1

2

C4780

1.0UF

0201-1

VCC

U4730

M24128

EEPROM

3
2
1
7

E2
E1
E0
WC*

MLP

SCL SDA

VSS

4

U4780

REF3312AIRSE

UQFN-COMBO

5

IN

CRITICAL

4

8

THM_P

GND

9

OUT

NC0
NC1

NC2

NC3
NC4

BYPASS=U4730::3MM

1

C4730

0.1UF

10%
10V

2

X5R-CERM
0201

1

R4731

2.2K

5%
1/20W
MF
201

2

56

I2C_SEP_SDA

34

65 6

79 20 17 15 6

75

IN

IN

THRMTRIP# Isolation

PP1V_S3

BYPASS=U4740::3MM

10%
10V

0201

1

2

U4740

8

1

3

7

5

4

2

74AXP1T57

SOT833

6

CPU_SMC_THRMTRIP_L

rdar://problem/33171763

C4740

0.1UF

X5R-CERM

PM_THRMTRIP_L

PLT_RST_L

PP1V8_S5

BYPASS=U4740::3MM

1

C4741

0.1UF

10%
10V

2

X5R-CERM
0201

OUT

35

75

43

36

PP1V8_AWAKE

75

IN

SPI_SOCROM_CS_L
SPI_SOCROM_WP_L

R4770

100K

5%

1/20W

MF

201

SoC ROM

B

OMIT_TABLE

10K

5%

1/20W

MF

201

1

8

CRITICAL

VCC

U4770

2

SCLK SI/SIO0

4MX8-1.8V

USON

56

1

2

R4771

MX25U3235F

1

CS*

3

WP*/SIO2

7

RESET*/SIO3

VER 2

GND

4

SO/SIO1

EPAD

EPAD

10

9

2

BYPASS=U4770::5MM

1

C4770

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_SOCROM_MOSISPI_SOCROM_CLK

SPI_SOCROM_MUX_MISO_R

R4773

20

21

SPI_SOCROM_MISO

5% 2011/20WMF

PLACE_NEAR=U4770.2:5MM

OUT

IN

43

43

PROCHOT# Level Shifting

rdar://problem/34583713

PP1V8_S5

75

PP1V25_SLPS2R_SMC_AVREF

8

1

NC

2

NC

3

NC

6

NC

7

NC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.25V

BYPASS=U4780::3MM

1

C4781

1.0UF

20%

6.3V

2

X5R
0201-1

GND_SMC_AVSS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

49 48 47 35

35

59 43 35

R4790

10K

1/20W

201

SMC_PROCHOT_L

1

5%
MF

2

6

VCC

U4790

74LVC1G07FW5

DFN1010

2

A

NC NC

1

GND

3

4

Y

5

NCNC

CRITICAL

BYPASS=U4790::3MM

1

C4790

0.1UF

10%
10V

2

X5R-CERM
0201

CPU_PROCHOT_R_L

6

R4791

75

2 1

5%

1/20W

MF

201

CPU_PROCHOT_L

SYNC_DATE=03/16/2017SYNC_MASTER=X589_BIGSUR

PAGE TITLE

A

SoC Shared Support

6

OUTIN

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

47 OF 145

SHEET

42 OF 85

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

IV ALL RIGHTS RESERVED

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

47

47

47

47

47

47

47

49

IN

IN

IN

IN

IN

IN

IN

IN

SMC ADC Assignments

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HS_ISENSE

MAKE_BASE=TRUE

SMC_3V3G3HMAIN_ISENSE

MAKE_BASE=TRUE

SMC_5VG3S_ISENSE

MAKE_BASE=TRUE

SMC_SSD0_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HS_ISENSE
SMC_3V3G3HMAIN_ISENSE
SMC_5VG3S_ISENSE
SMC_SSD0_ISENSE

PCIe Up R2D AC Caps

(All Caps)

GND_VOID=TRUE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

35

35

35

35

35

35

35

35

79 55 43

79 52 43

From Mic Flex

SMC_LID_LEFT

SMC_LID_RIGHT

From RIO

R4804

5% 1/20W MF

R4805

5% 1/20W MF

10K

10K

Lid Detect Logic

LID_OPEN_LEFT

LID_OPEN_LEFT

MAKE_BASE=TRUE

PP1V8_SLPS2R

52 55 75

1

R4801

1M

5%
1/20W
MF
201

2

1M

5%

1/20W

MF

201

1

2

R4800

21

201

21

201

Clamshell Open = High

BYPASS=U4802::5MM

10%

6.3V
0201

1

2

2

1

C4802

0.1UF

CERM-X5R

6

NC

5 3

U4802

74LVC1G32

SOT891

4

IPD_LID_OPEN

Clamshell Closed = Low

NC

OUT

BI

35

D

79 55

C

B

21
20% X5R6.3V 0201

21

6.3V X5R20% 0201

21

6.3V 0201X5R20%

21

0201X5R20% 6.3V

21
20% X5R 02016.3V

21

6.3V

21

6.3V 020120%

21

X5R 020120%

X5R

02016.3V X5R20%

PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

16

16

16

16

16

16

16

IN
IN

IN
IN

IN
IN

IN

PCIE_SOC_R2D_C_P<0>
PCIE_SOC_R2D_C_N<0>

PCIE_SOC_R2D_C_P<1>
PCIE_SOC_R2D_C_N<1>

PCIE_SOC_R2D_C_P<2>
PCIE_SOC_R2D_C_N<2>

PCIE_SOC_R2D_C_P<3>
PCIE_SOC_R2D_C_N<3>

C4820

0.22UF

C4821

0.22UF

C4822

0.22UF

C4823

0.22UF

C4824

0.22UF

C4825

0.22UF

C4826

0.22UF

C4827

0.22UF

GPIO Source Termination

I2S_SPKRAMP_L_R2D_R

PLACE_NEAR=U3900.AG34:5MM

I2S_SPKRAMP_L_BCLK_R

PLACE_NEAR=U3900.AA32:5MM

36

IN OUT

36

IN OUT

36

IN

36

IN OUT

36

IN

36

IN

36 56 42

IN OUT

36

IN OUT

36

IN OUT

36

IN

37

IN OUT

35

IN

35

IN

35

IN

35

IN

I2S_SPKRAMP_L_LRCLK

PLACE_NEAR=U3900.AG33:5MM

I2S_SPKRAMP_R_R2D_R

PLACE_NEAR=U3900.C20:5MM

PLACE_NEAR=U3900.C21:5MM

I2S_SPKRAMP_R_LRCLK

PLACE_NEAR=U3900.A21:5MM

I2S_CODEC_R2D_R

PLACE_NEAR=U3900.AB34:5MM

I2S_CODEC_BCLK_R

PLACE_NEAR=U3900.AF33:5MM

SPI_TPAD_MOSI_R

PLACE_NEAR=U3900.N34:5MM

SPI_TPAD_CLK_R

PLACE_NEAR=U3900.P35:5MM

SPI_MESA_MOSI_R SPI_MESA_MOSI

PLACE_NEAR=U3900.A20:5MM

PLACE_NEAR=U3900.C19:5MM

SSD0_CLK24M_R

PLACE_NEAR=U3900.AP7:5MM

PDM_DMIC_CLK0_R

PLACE_NEAR=U3900.P6:5MM

PDM_DMIC_CLK1_R

PLACE_NEAR=U3900.K2:5MM

SPI_AOP_SENSOR_MOSI_R

PLACE_NEAR=U3900.D2:5MM

SPI_AOP_SENSOR_CLK_R

PLACE_NEAR=U3900.F2:5MM

R4843
R4844
R4841
R4845
R4846
R4842
R4847
R4848
R4851
R4852
R4853
R4854
R4857
R4859
R4860
R4861
R4862

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

21

I2S_SPKRAMP_L_R2D

5% 1/20W MF 201

21

I2S_SPKRAMP_L_BCLK

21

I2S_SPKRAMP_L_LRCLK_R

1/20W MF 2015%

21

I2S_SPKRAMP_R_R2D

1/20W 201MF5%

21

I2S_SPKRAMP_R_BCLKI2S_SPKRAMP_R_BCLK_R

1/20W MF 2015%

21

I2S_SPKRAMP_R_LRCLK_R

21

I2S_CODEC_R2D

1/20W

5% MF

21

I2S_CODEC_BCLK

5% 1/20W MF 201

21

SPI_TPAD_MOSI

5% 1/20W 201

21

SPI_TPAD_CLK

1/20W

5% MF 201

21

5% 1/20W MF 201

21

SPI_MESA_CLKSPI_MESA_CLK_R

5% 1/20W MF 201

21

SSD0_CLK24M

5% 1/20W 201

21

PDM_DMIC_CLK0

1/20W5%

21

PDM_DMIC_CLK1

5% 1/20W

21

SPI_AOP_SENSOR_MOSI

5% 1/20W MF 201

21

SPI_AOP_SENSOR_CLK

5% 1/20W MF 201

MF1/20W5% 201

2015% 1/20W MF

201

MF

MF

MF

MF 201

201

OUTIN

OUTIN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUTIN

53 36

53 36

53

33

33

37

37

37

37

37

37

37

37 16

LID_OPEN_RIGHT

OUT

35

LID_OPEN_RIGHT

MAKE_BASE=TRUE

Secure Disable

PP1V8_SLPS2R

75

BYPASS=U4850::5MM

10%

6.3V
0201

1

2

34

34

34

65 35

IN

IN

IN

IN

79 52 43

79 55 43

C4850

0.1UF

CERM-X5R

SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE
PMU_COLD_RESET_L
SMC_LID_RIGHT

SMC_LID_LEFT
LID_CTRL_DMIC

79 52

79 52

79 52

79 52

79 52

PP3V3_S5

43 75

56 42

79 52

79 52

72 70 43

79 55

79 55

77

IN

BYPASS=U4880::5MM

C4880

0.1UF

10%

6.3V

CERM-X5R

0201

UVP_DIS_L

1

2

1

R4880

100K

5%
1/20W
MF
201

2

NC
NC
NC

2 3

ENABLE

9

COMP_INPUT

5
8

NC

11

1

R4850

1K

5%
1/20W
MF
201

2

2

CAM_DIS*

3

DMIC_DIS*

4

DIS_STROBE

9

PMU_COLD_RST*

13

LID_RIGHT

14

LID_LEFT

6

SEL

1

VDD

U4880

SLG4AP41473

STQFN

DUMMY_OUTPU_COMP

THROTTLE*_TEST_OUTPUT

1

VDD

U4850

SLG4AP41496V

STQFN

GND

8

VREF_1V2

CPU_THROTTLE*

GPU_THROTTLE*

CAM_DIS_OUT*

DMIC_DIS_OUT*

CAM_DIS_OUT

DMIC_DIS_OUT

NC

10

12

6

4

NC

NC

12

SEP_CAM_DISABLE_OUT_L

7

SEP_DMIC_DISABLE_OUT_L

RFU

10

11

5

NC

NC

NC

PBUS_DIVIDER_REF
SMC_PROCHOT_L

OUT

OUT

OUT

69

54

C

B

59 42 35

1

C4881

0.1UF

10%

6.3V

2

CERM-X5R
0201

A

PP1V8_SLPS2R
PP1V8_AWAKE

R4883
R4884
R4887
R4888

R4885
R4886
R4895

47K
47K
47K
47K

100K

47K

100K

34 75

37 42 75

21

5% MF1/20W

21

5%

21
21

5% 1/20W 201

21

5% MF 2011/20W

21
21

1/20W
1/20W

MF 2011/20W
MF
MF

SSD0_CLKREQ0_L

201

SSD0_CLKREQ1_L
SSD0_CLKREQ2_L

2011/20W5%

SSD0_CLKREQ3_L

SSD0_PCIE_RESET_L
SSD0_CLK24M

201MF5%

SSD_PMU_RESET_L

201MF5%

37

34

GND

7

PP1V8_G3S

76

1

R4873

100K

5%
1/20W
MF
201

2

79 52 34

82 79 34 27

70 37

71 37

72 37

72 71 70 37

72 70 43

MESA_PWR_EN

SOC_DFU_STATUS

SOC_HOLD_RESET

34

SOC_TESTMODE

34

1

R4871

10K

5%
1/20W
MF
201

2

1

R4872

10K

5%
1/20W
MF
201

2

1

R4874

47K

5%
1/20W
MF
201

2

TPAD_KBD_WAKE_L

35

TPAD_SPI_INT_L

35

TPAD_ACTUATOR_DISABLE_L

35

Overloaded GPIOs

SPI_SOCROM_MOSI

42

SPI_SOCROM_CLK

42

SPI_SOCROM_MISO

42

PBUS_DIVIDER_OUT

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

TPAD_KBD_WAKE_L
TPAD_SPI_INT_L

TPAD_ACTUATOR_DISABLE_L

SPI_SOCROM_MOSI
SPI_SOCROM_CLK
SPI_SOCROM_MISO

BOM_COST_GROUP=T290

PP3V3_S5

43 75

BYPASS=U4885::5MM

C4885

0.1UF

CERM-X5R

56

56

56

10%

6.3V
0201

U4885

LMV331

42 36

42 36

42 36

1

2

4

SC70-5

5

VCC+

GND

2

3

1

PBUS_DIVIDER

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SoC Project Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PPBUS_G3H

1

R4881

665K

0.1%
1/20W
TK
0201

2

1

R4882

127K

0.1%
1/20W
MF
0201

2

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

76

SYNC_DATE=02/13/2017

SIZE

051-04039

D

2.0.0

48 OF 145

43 OF 85

A

8

67

35 4

2

1

678

3 245

1

STOCKHOLM 2017

D

PP3V3_G3S

76

BYPASS=U5000::3MM

C5014

4.7UF

PP1V8_G3S

76

20%

6.3V
X5R
402

BYPASS=U5000::3MM

1

2

BYPASS=U5000::3MM

C5019

4.7UF

20%

6.3V
X5R
402

C5018

1.0UF

20%

6.3V
X5R

0201-1

PP4V7_SE_TVDD

VOLTAGE=4.7V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

2

1

NCNC

2

C7

VDD

E8

VBAT

A4

A7

D2

PVDD

H3

VUP

G7

TVDD

D7

AVDD

B8

SVDD

C5

G1

ESE_VDD

GPIOVDD

A8

A5

SIM_VCC1

PP1V8_SE_AVDD

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

PP1V8_SE_ESE

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

SIM_VCC2

BYPASS=U5000::3MM

1

C5015

0.22UF

20%

6.3V

2

X5R
0201

1

C5016

2.2UF

20%
4V

2

X6S-CERM
0201

BYPASS=U5000::3MM

1

C5017

2.2UF

20%
4V

2

X6S-CERM
0201

BYPASS=U5000::3MM

1

2

BYPASS=U5000::3MM

C5025

2.2UF

20%

6.3V
X5R
0201

D

C

44 34

44 36

44 36

44 36

44 36

65

SE_CTLR_FW_DWLD

IN

UART_SE_R2D

IN

UART_SE_D2R

OUT

UART_SE_R2D_RTS_L

IN

UART_SE_D2R_CTS_L

OUT

SE_PWR_EN

IN

NC

NC

NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

E3

IRQ

D3

DWL

B1

CLK_REQ

C8

NFC_CLK_XTAL1

E1

UART_RX

D1

UART_TX

E2

UART_CTS

C3

UART_RTS

H1

VEN

B5

IC0

C4

IC1

D5

IC2

E4

IC3

E6

IC4

F4

IC5

F5

IC6

F6

IC7

F8

IC8

G4

IC9

B3

IC10

B6

IC11

D6

IC12

E7

IC13

F7

IC14

SIM_PMU_VCC_1

SIM_PMU_VCC_2

U5000

PN80VEU3-C004B013

UFLGA

OMIT_TABLE

SIM_SWIO_1

SIM_SWIO_2

ESE_GPIO

TX_PWR_REQ_P

ESE_DWPM_DBG
ESE_DWPS_DBG

RX+
RX-

TX1

TX2

WKUP_REQ

VMID

NFC_GPIO0
NFC_GPIO1
NFC_GPIO2
NFC_GPIO3
NFC_GPIO4
NFC_GPIO5
NFC_GPIO6

XTAL2

A3

A6

E5

A2

B7
D4

H5
H6

G8
H7

A1

H4

C2
B2
F3
F2
H2
G2
F1

D8

NC
NC

NC

NC

NC
NC

NC
NC

NC
NC

SE_DEV_WAKE
PP0V9_SE_VMID

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

NC
NC
NC
NC
NC
NC
NC

NCNC

IN

44 34

BYPASS=U5000::3MM

1

C5026

0.1UF

10%

6.3V

2

CERM-X5R
0201

C

B

AVSS

G3

AVSS

G5

AVSS

G6

DVSS

C6

TVSS

H8

C1

B4

ESE_VSS

PVSS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-11132 U5000 SE:DEV_20171 CRITICAL

1338S00253 CRITICAL SE:PROD_2017

IC,RTM4,ES2.1,PN80V,DEV KY,S/W-M,UFLGA64

MODULE,NFC,NXP,LGA64

U5000

B

A

PP1V8_G3S

R5001
R5002
R5003
R5004
R5000
R5006

8

100K
100K
100K
100K
100K
100K

76

SYNC_MASTER=X941_MLB

PAGE TITLE

SYNC_DATE=03/10/2017

A

Secure Element

DRAWING NUMBER

21
21
21
21
21
21

1/20W5% MF

1/20W5% MF
1/20W

UART_SE_R2D

201

UART_SE_D2R

201MF5% 1/20W

UART_SE_R2D_RTS_L

201MF5% 1/20W

UART_SE_D2R_CTS_L

201MF5% 1/20W

SE_CTLR_FW_DWLD

201

SE_DEV_WAKE

2015% MF

44 36

44 36

44 36

44 36

44 34

44 34

BOM_COST_GROUP=T151

67

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

051-04039

REVISION

2.0.0

BRANCH

PAGE

50 OF 145

SHEET

44 OF 85

1

SIZE

D

678

3 245

1

D

SPT-LP PCH S0 "SMBUS 0" Connections

PP1V8_S5

45 75

CNL-LP PCH

U0500

(MASTER)

SMBUS_PCH_CLK

14

MAKE_BASE=TRUE

SMBUS_PCH_DATA

14

MAKE_BASE=TRUE

SPT-LP PCH S0 "SMLINK 0" Connections

PP1V8_S5

45 75

R5202

2.2K

5%

1/20W

MF

201

SMC I2C "0" G3H Connections

PP1V8_SLPS2R

75

SMC I2C "4" G3H Connections

PP1V8_SLPS2R

57 75

UPC Port X

1

2

1

R5203

2.2K

5%
1/20W
MF
201

2

35

35

35 27

SMC (SoC)

U3900

(MASTER)

I2C_UPC_SCL

MAKE_BASE=TRUE

I2C_UPC_SDA

MAKE_BASE=TRUE

UPC_I2C_INT_L

MAKE_BASE=TRUE

(IPU)

R5200

2.2K

5%

1/20W

MF

201

1

2

1

R5201

2.2K

5%
1/20W
MF
201

2

J0500
(Ace XA W:0x70 R:0x71)
(Ace XB W:0x7E R:0x7F)
(All-Ace W:0xD6 R:0xD7)

I2C_UPC_SCL
I2C_UPC_SDA
UPC_I2C_INT_L

I2C_UPC_SCL
I2C_UPC_SDA
UPC_I2C_INT_L

27 28

27 28

28

29

29

29

79 35

79 35

SMC (SoC)

J3900

(MASTER)

I2C_PWR_SCL

MAKE_BASE=TRUE

I2C_PWR_SDA

MAKE_BASE=TRUE

R5240

4.7K

5%

1/20W

MF

201

1

2

1

R5241

4.7K

5%
1/20W
MF
201

2

Battery

J6950

(Write:0x16 Read:0x17)

I2C_PWR_SCL
I2C_PWR_SDA

57

57

D

Battery Charger

U7000

(Write:0x12 Read:0x13)

I2C_PWR_SCL

58

C

CNL-LP PCH

U0500

(MASTER)

SML_PCH_0_CLK

14

MAKE_BASE=TRUE

SML_PCH_0_DATA

14

MAKE_BASE=TRUE

R5204

2.2K

5%

1/20W

MF

201

I2C_PWR_SDA

1

2

1

R5205

2.2K

5%
1/20W
MF
201

2

SMC I2C "1" S0 Connections

PMU

58

J7800

(Write:0xE8 Read:0xE9)

SMC (SoC)

U3900

UNUSED

I2C_PWR_SCL
I2C_PWR_SDA

65

65

(MASTER)

NC_I2C_SNS0_S0_SCL

35

NC_I2C_SNS0_S0_SDA

35

NC_I2C_SNS0_S0_SCL

MAKE_BASE=TRUE

NO_TEST=1

NC_I2C_SNS0_S0_SDA

MAKE_BASE=TRUE

NO_TEST=1

C

SMC I2C "5" G3S Connections

PP1V8_G3S

76

B

SPT-LP PCH S0 "SMLINK 1" Connections

SPT-LP PCH

U0500

(Write: 0x88 Read: 0x89)

I2C_SNS1_S0_SCL

14

I2C_SNS1_S0_SDA

14

PP1V8_S5

75

SMC (SoC)

U3900

(MASTER)

I2C_SNS1_S0_SCL

35

MAKE_BASE=TRUE

I2C_SNS1_S0_SDA

35

MAKE_BASE=TRUE

SMC I2C "2" S0 Connections

R5220

2.2K

5%

1/20W

MF

201

1

2

1

R5221

2.2K

5%
1/20W
MF
201

2

SMC (SoC)

U3900

(MASTER)

I2C_SNS_G3S_SCL

35

MAKE_BASE=TRUE

I2C_SNS_G3S_SDA

35

MAKE_BASE=TRUE

R5250

2.2K

5%

1/20W

MF

201

1

2

1

R5251

2.2K

5%
1/20W
MF
201

2

Trackpad

J5200

(Write:0x98 Read:0x99)

I2C_SNS_G3S_SCL

(10K IPU)

I2C_SNS_G3S_SDA

(10K IPU)

56

56

Thermal Sensors

U5800

(See thermal sensor page)

I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA

50

50

B

A

SMC (SoC)

U3900

(MASTER)

I2C_DISP_SCL

35

I2C_DISP_SDA

35

PP1V8_S5

75

R5230

2.2K

5%

1/20W

MF

201

1

2

1

R5231

2.2K

5%
1/20W
MF
201

2

I2C_DISP_LS_EN

R5236

100K

5%

1/20W

MF

201

SMC I2C "3" S0 Connections

10%
16V

0201

1

1

2

8

VCCVL

C5230

1

0.1UF

X5R-CERM

U5200

2

2
3

5

NLSX4402

IO/VL1
IO/VL2

EN

UDFN

IO/VCC1
IO/VCC2

GND

4

1

C5231

0.1UF

10%
16V

2

X5R-CERM
0201

CKPLUS_WAIVE=I2C_PULLUP

7

I2C_TCON_SCL_R

6

I2C_TCON_SDA_R

CKPLUS_WAIVE=I2C_PULLUP

R5235

R5234

R5232

2.2K

1/20W

30

21

MF1/20W5% 201

30

21

5%
MF

201

SMC I2C "6" G3H Connections

SMC (SoC)

U3900

(MASTER)

NC_I2C_SSD0_SCL

35

NC_I2C_SSD0_SDA

35

PP3V3_S0SW_LCD

1

2

1

R5233

2.2K

5%
1/20W
MF
201

2

Internal Display

69

J8500
(Write: 0x-- Read: 0x--)

I2C_TCON_SCL

69

NC_I2C_SSD0_SCL

MAKE_BASE=TRUE

NC_I2C_SSD0_SDA

MAKE_BASE=TRUE

UNUSED

NO_TEST=1

NO_TEST=1

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=02/13/2017

A

I2C Connections 1

2015% 1/20W MF

I2C_TCON_SDA

69

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

52 OF 145

SHEET

45 OF 85

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SOC

IV ALL RIGHTS RESERVED

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

AP I2C "0" G3S Connections

PP1V8_G3S

76

U3900

(MASTER)

I2C_SPKRAMP_L_SCL

36

MAKE_BASE=TRUE

I2C_SPKRAMP_L_SDA

36

MAKE_BASE=TRUE

AP I2C "1" G3S Connections

PP1V8_G3S

76

R5300

2.2K

5%

1/20W

MF

201

ISP I2C "0" G3S Connections

PP1V8_G3S

69 76

1

2

1

R5301

2.2K

5%
1/20W
MF
201

2

Left Speaker AmpsAP (SoC)

U6400

(See speaker amp card)
I2C_SPKRAMP_L_SCL

I2C_SPKRAMP_L_SDA

53

53

ISP (SoC)

U3900 J8500

(MASTER)

I2C_FTCAM_SCL

36

MAKE_BASE=TRUE

I2C_FTCAM_SDA

36

MAKE_BASE=TRUE

R5335

1K

5%

1/20W

MF

201

1

2

1

R5336

1K

5%
1/20W
MF
201

2

FaceTime Camera

(See camera card)

I2C_FTCAM_SCL
I2C_FTCAM_SDA

69

69

AP (SoC) UNUSED

U3900

(MASTER)

TP_I2C_CODEC_SCL

36

TP_I2C_CODEC_SDA

36

AP I2C "2" Codec Connections

TP_I2C_CODEC_SCL

MAKE_BASE=TRUE

TP_I2C_CODEC_SDA

MAKE_BASE=TRUE

D

AP I2C "4" DFR Connections

C

79 36

79 36

36

36

5%

1/20W

MF

201

1

2

AP (SoC)

R5305

2.2K

U3900

(MASTER) (See RIO)

I2C_SPKRAMP_R_SCL

MAKE_BASE=TRUE

I2C_SPKRAMP_R_SDA

MAKE_BASE=TRUE

1

R5306

2.2K

5%
1/20W
MF
201

2

RIO Audio

Speaker Amp, Codec

I2C_SPKRAMP_R_SCL
I2C_SPKRAMP_R_SDA

AP I2C "3" G3S Connections

PP1V8_G3S

76

AP (SoC)

U3900

(MASTER)

I2C_ALS_SCL

MAKE_BASE=TRUE

I2C_ALS_SDA

MAKE_BASE=TRUE

R5315

1K

5%

1/20W

MF

201

1

2

1

R5316

1K

5%
1/20W
MF
201

2

ALS

J8500

(See camera flex)

I2C_ALS_SCL
I2C_ALS_SDA

52

52

69

69

AP (SoC)

U3900

(MASTER)

NC_I2C_DFR_SCL

36

NC_I2C_DFR_SDA

36

AP I2C "5" Awake Connections

AP (SoC)

U3900

(MASTER)

NC_I2C_SOC_5_SCL

36

NC_I2C_SOC_5_SDA

36

UNUSED

NC_I2C_DFR_SCL

MAKE_BASE=TRUE

NC_I2C_DFR_SDA

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

UNUSED

NC_I2C_SOC_5_SCL

MAKE_BASE=TRUE

NC_I2C_SOC_5_SDA

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

C

B

ISP I2C "1" G3S Connections

ISP (SoC)

U3900

(MASTER)

NC_I2C_PLCAM_SCL

36

NC_I2C_PLCAM_SDA

36

NC_I2C_PLCAM_SCL

MAKE_BASE=TRUE

NC_I2C_PLCAM_SDA

MAKE_BASE=TRUE

AOP I2C G3H Connections

UNUSED

B

NO_TEST=1

NO_TEST=1

A

AOP (SoC)

U3900

(MASTER)

NC_I2C_AOP_SCL

35

NC_I2C_AOP_SDA

35

BOM_COST_GROUP=SOC

NC_I2C_AOP_SCL

MAKE_BASE=TRUE

NC_I2C_AOP_SDA

MAKE_BASE=TRUE

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

I2C Connections 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

UNUSED

NO_TEST=1

NO_TEST=1

DRAWING NUMBER

051-04039

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=02/13/2017

2.0.0

53 OF 145

46 OF 85

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

INA21X PARTS HAVE MINOR LEAKAGE PATH FROM INPUTS TO OUTPUT WHEN UNPOWERED.
PULL-DOWN RESISTERS ON INA OUTPUTS BLEED OFF THE LEAKAGE CURRENT TO PREVENT
SIGNAL PUMP-UP.

CPU High Side Current Sense (IC0R)

GAIN: 100X, EDP: 10.16 A
Rsense: 0.003 (R5400)
VSENSE: 30.475 mV, RANGE: 8.842 A
SMC ADC: 04

76

PPBUS_HS_CPU

CRITICAL

NO_XNET_CONNECTION=1

76

PPBUS_G3H

R5400

0.003

1%
1W

CYN

0612

PLACE_NEAR=U5400.5:10MM

1

ISNS_HS_COMPUTING_N

ISNS_HS_COMPUTING_P

432

PLACE_NEAR=U5400.4:10MM

PP3V3_G3SSW_SNS

47 48 49 76

3

V+

U5400

5

IN-

4

IN+ REF

INA214

SC70

100X

CRITICAL

GND

2

OUT

PBUS Voltage Sense & Enable (VP0R)

Gain: 0.089x
Vnominal: 13.05 V, Range: 14.05 V
SMC ADC: 02

Enables PBUS VSense
divider when sensor
rail is enabled.

PP3V3_G3SSW_SNS

BYPASS=U5400.3:2:5MM

1

C5401

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AB6:5.2MM

76

IN

R5409

6

1

ISNS_HS_COMPUTING_IOUT

PLACE_NEAR=U5400.6:5MM

1

R5405

15K

5%

2

1/20W
MF
201

PLACE_NEAR=U3900.AB6:5.2MM

10.2K

1%

1/20W

MF

201

21

SMC_CPU_HS_ISENSE

R5408

7.68K

1%

1/20W

MF

201

1

2

1

2

GND_SMC_AVSS

43

OUT

PLACE_NEAR=U3900.AB6:6.2MM

C5409

0.022UF

10%

6.3V
X5R-CERM
0201

PPBUS_G3H

76

49 48 47 42 35

XW5480

SM

21

PBUS_S0_VSENSE_IN

R5481

100K

1/20W

1%
MF

201

1

2

CRITICAL

Q5480

NTUD3169CZ

SOT-963

N-CHANNEL

2

1

5

4

G

G

P-CHANNEL

PBUSVSENS_EN_L_DIV

6

PBUSVSENS_EN_L

D

R5482

100K

S

3

PBUS_S0_VSENSE

D

S

1%

1/20W

MF

201

1

D

2

PLACE_NEAR=U3900.AH3:5MM

1%

1/20W

MF

201

1

Rthevenin = 4573 Ohms

2

R5488

51.1K

SMC_PBUS_VSENSE

PLACE_NEAR=U3900.AH3:5MM

1

C5489

0.022UF

10%

6.3V

2

X5R-CERM
0201

R5489

4.99K

1%

1/20W

MF

201

1

2

GND_SMC_AVSS

OUT

43

49 48 47 42 35

C

B

5V G3S (IO5R)

GAIN: 100X, EDP: 4.2 A
Rsense: 0.005 (R5410)
VSENSE: 21 mV, RANGE: 5 A
SMC ADC: 06

62 76

PPVIN_G3H_P5VG3S

CRITICAL

R5410

NO_XNET_CONNECTION=1

76

PPBUS_G3H

3V3 G3H MAIN (IO3R)

GAIN: 100X, EDP: 4.702 A
Rsense: 0.005 (R5420)
VSENSE: 23.510 mV, RANGE: 5 A
SMC ADC: 05

62 76

76

PPVIN_G3H_P3V3G3H

CRITICAL

R5420

NO_XNET_CONNECTION=1

PPBUS_G3H

0.005

1%
1W
MF

0612-8

0.005

1%
1W
MF

0612-8

PLACE_NEAR=U5410.5:10MM

2

ISNS_5VG3S_N

ISNS_5VG3S_P

341

PLACE_NEAR=U5410.4:10MM

PLACE_NEAR=U5420.5:10MM

1

ISNS_3V3G3HMAIN_N

ISNS_3V3G3HMAIN_P

432

PLACE_NEAR=U5420.4:10MM

PP3V3_G3SSW_SNS

47 48 49 76

PP3V3_G3SSW_SNS

47 48 49 76

3

V+

U5410

5

IN-

4

IN+ REF

INA214

SC70

100X

CRITICAL

GND

2

3

V+

U5420

5

IN-

4

IN+ REF

INA214

SC70

100X

CRITICAL

GND

2

OUT

OUT

PLACE_NEAR=U3900.AH3:5MM

BYPASS=U5410.3:2:5MM

1

C5411

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AG4:5.2MM

R5419

6

1

ISNS_5VG3S_IOUT

PLACE_NEAR=U5410.6:5MM

1

R5415

15K

5%
1/20W
MF
201

2

BYPASS=U5420.3:2:5MM

1

C5421

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AG4:5.2MM

9.09K

1/20W

PLACE_NEAR=U3900.AH2:5.2MM

1%
MF

201

21

SMC_5VG3S_ISENSE

1%

1/20W

MF

201

1

2

R5418

9.09K

43

OUT

PLACE_NEAR=U3900.AG4:6.2MM

1

C5419

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

49 48 47 42 35

R5429

6

1

ISNS_3V3G3HMAIN_IOUT

PLACE_NEAR=U5420.6:5MM

1

R5425

15K

2

5%
1/20W
MF
201

PLACE_NEAR=U3900.AH2:5.2MM

9.09K

1%

1/20W

MF

201

21

SMC_3V3G3HMAIN_ISENSE

PLACE_NEAR=U3900.AH2:6.2MM

R5428

9.09K

1%

1/20W

MF

201

1

2

1

C5429

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

43

49 48 47 42 35

DC In Voltage Sense & Enable (VD0R)

Gain: 0.148x
Vnominal: 16.5 V, Range: 22.29 V
SMC ADC: 00

PPDCIN_G3H

76

PLACE_NEAR=U3900.AG2:5MM

1%

1/20W

MF

201

1

Rthevenin = 4586 Ohms

2

R5498

78.7K

SMC_DCIN_VSENSE

PLACE_NEAR=U3900.AG2:5MM

1

C5499

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

R5499

4.87K

1/20W

PLACE_NEAR=U3900.AG2:5MM

1%
MF

201

1

2

DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 3.0 A
RSENSE: 0.010 (R7020)
SMC ADC: 01

PLACE_NEAR=U3900.AC4:5MM

R5472

58

CHGR_AMON

4.53K

1/20W

1%
MF

201

21

SMC_DCIN_ISENSE

PLACE_NEAR=U3900.AC4:5MM

1

C5473

0.022UF

10%

6.3V

2

X5R-CERM
0201

DCIN sensing no longer gated.

FETs removed to avoid power
draw on PU on CHGR_AUX_OK.

OUT

OUT

C

43

49 48 47 42 35

43

B

3V3 G3H RTC (xxxx)

GAIN: X, EDP: 0.753 A
Rsense: 0.005 (R5430)
VSENSE: 3.767 mV, RANGE: 0.756 A
PMU AMUX: x

57 76

76

PPVIN_G3H_P3V3G3HRTC

CRITICAL

NO_XNET_CONNECTION=1

PPBUS_G3H

R5430

0.005

1%

1/3W

LF

0306

GND_SMC_AVSS

49 48 47 42 35

Charger (BMON) Current Sense (IPBR)

Charger Gain: 7.9x, EDP: 6.5 A
RSENSE: 0.005 (R7060)
SMC ADC: 03

R5470

79 58

1

ISNS_3V3G3HRTC_N

ISNS_3V3G3HRTC_P

432

1

1

PP5431

PP

P3MM

SM

PP5430

PP

P3MM

SM

IN

CHGR_BMON SMC_BMON_ISENSE

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U3900.AD4:5MM

21

PLACE_NEAR=U3900.AD4:5MM

1

C5471

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

43

49 48 47 42 35

DESIGN: X1032/MLB

A

8

LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/14/2017

A

Power Sensors High Side

SIZE

D

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SENSORS

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

54 OF 145

SHEET

47 OF 85

1

D

VDDMAIN (ISLC)

GAIN: 200X, EDP: 10.90 A
Rsense: 0.001 (R5500)
VSENSE: 10.90 mV, RANGE: 10.988 A
PMU AMUX: A0

63 76

76

PP3V3_G3H_PMU_VDDMAIN

CRITICAL

NO_XNET_CONNECTION=1

PP3V3_G3H

R5500

0.001

1%

1W
MF-3
0612

PLACE_NEAR=U5500.5:10MM

1

ISNS_VDDMAIN_N

ISNS_VDDMAIN_P

432

PLACE_NEAR=U5500.4:10MM

PP3V3_G3SSW_SNS

47 48 49 76

3

V+

U5500

5

IN-

4

IN+ REF

INA210

SC70

200X

CRITICAL

GND

2

OUT

678

3 245

1

D

BYPASS=U5500.3:2:5MM

1

C5501

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_VDDMAIN_IOUT

PLACE_NEAR=U5500.6:5MM

1

R5505

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.A16:5.2MM

PLACE_NEAR=U7800.A16:5.2MM

R5509

6.65K

1/20W

1%
MF

201

21

PMU_VDDMAIN_ISENSE

1%

1/20W

MF

201

1

2

R5508

14.3K

49

PLACE_NEAR=U7800.A16:5.2MM

1

C5509

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

49 48 47 42 35

C

Wireless (IAPC)

GAIN: 200X, EDP: 1.5 A
Rsense: 0.010 (R5510)
VSENSE: 15 mV, RANGE: 1.5 A
PMU AMUX: A2

32 76

76

PP3V3_G3S_WLANBT

NO_XNET_CONNECTION=1

PP3V3_G3S

CRITICAL

R5510

0.01

0.5%

0612-1-COMBO

1W

MF

PLACE_NEAR=U5510.5:10MM

1

ISNS_WLANBT_N

ISNS_WLANBT_P

432

PLACE_NEAR=U5510.4:10MM

PP3V3_G3SSW_SNS

47 48 49 76

3

V+

U5510

5

IN-

4

IN+ REF

INA210

SC70

200X

CRITICAL

GND

2

OUT

BYPASS=U5510.3:2:5MM

1

C5511

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_WLANBT_IOUT PMU_WLANBT_ISENSE

PLACE_NEAR=U5510.6:5MM

1

R5515

15K

2

5%
1/20W
MF
201

PLACE_NEAR=U7800.A14:5.2MM

PLACE_NEAR=U7800.A14:5.2MM

R5519

10.2K

1/20W

1%
MF

201

21

R5518

9.09K

1%

1/20W

MF

201

1

2

49

OUT

PLACE_NEAR=U7800.A14:5.2MM

1

C5519

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

C

49 48 47 42 35

B

B

A

8

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/14/2017

A

Power Sensors Load Side

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SENSORS

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

55 OF 145

SHEET

48 OF 85

1

SIZE

D

D

SSD (IH0R)

GAIN: 500X, EDP: 0.654 A
Rsense: 0.010 (R5600)
VSENSE: 6.536 mV, RANGE: 1.8 A
SMC ADC: 07

73 76

76

PPBUS_G3H_SSD0

NO_XNET_CONNECTION=1

PPBUS_G3H

CRITICAL

R5600

0.01

0.5%

0.5W
0306

MA

PLACE_NEAR=U5400.5:10MM

2

ISNS_SSD0_N

ISNS_SSD0_P

341

PLACE_NEAR=U5400.4:10MM

PP3V3_G3SSW_SNS

47 48 49 76

3

V+

U5600

5

IN-

4

IN+ REF

INA211

SC70

500X

CRITICAL

GND

2

OUT

678

3 245

1

CPU CORE VOLTAGE SENSE (VCAC)

PMU AMUX: A5

PPVCC_S0_CPU

8 11 76

BYPASS=U5600.3:2:5MM

1

C5601

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_SSD0_IOUT SMC_SSD0_ISENSE

PLACE_NEAR=U5600.6:5MM

1

R5605

15K

5%

2

1/20W
MF
201

PLACE_NEAR=U3900.AC5:5.2MM

PLACE_NEAR=U3900.AC5:5.2MM

R5609

12.1K

1/20W

1%
MF

201

21

R5608

7.32K

1%

1/20W

MF

201

1

2

43

OUT

PLACE_NEAR=U3900.AC5:6.2MM

1

C5609

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

NAND 2V7 VOLTAGE SENSE (VHNC)

PMU AMUX: A6

PP2V7_NAND

70 71 72 76

49 48 47 42 35

XW5680

SM

21

CPUVSENSE_IN

PLACE_NEAR=R7210.1:7 MM

PLACE_NEAR=U7800.D15:5MM
PLACE_NEAR=U7800.D15:5MM

XW5660

SM

21

NANDVSENSE_IN

PLACE_NEAR=R7210.1:7 MM

PLACE_NEAR=U7800.E14:5MM
PLACE_NEAR=U7800.E14:5MM

R5680

5.76K

1/20W

1%
MF

201

21

R5660

8.25K

1/20W

1%
MF

201

21

1

R5681

22.1K

1%
1/20W
MF
201

2

1

R5661

10.2K

1%
1/20W
MF
201

2

PMU_CPU_VSENSE

PLACE_NEAR=U7800.D15:5MM

1

C5680

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

PMU_NAND_VSENSE

PLACE_NEAR=U7800.E14:5MM

1

C5660

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

49

49

49 48 47 42 35

49 48 47 42 35

D

C

Trackpad (xxxx)

GAIN: x, EDP: 2.3 A
Rsense: 0.010 (R5610)
VSENSE: 23 mV, RANGE: 2.344 A
PMU AMUX: x

55 76

76

PPBUS_G3H_TPAD

NO_XNET_CONNECTION=1

PPBUS_G3H

CRITICAL

R5610

0.01

0.5%

0612-1-COMBO

1W
MF

4

ISNS_TPAD_N

ISNS_TPAD_P

3

1 2

VCCIO VOLTAGE SENSE (VCIC)

PMU AMUX: A7

PPVCCIO_S0_CPU VCCIOVSENSE_IN PMU_VCCIO_VSENSE

76 49

1

1

PP5611

PP

P3MM

SM

PP5610

PP

P3MM

SM

XW5670

SM

21

PLACE_NEAR=R7210.1:7 MM

PLACE_NEAR=U7800.F14:5MM

R5670

4.53K

1/20W

1%
MF

201

21

PLACE_NEAR=U7800.F14:5MM

1

C5670

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

C

49 48 47 42 35

B

LCD Backlight (IBLR)

GAIN: 100X, EDP: 0.902 A
Rsense: 0.025 (R8400)
VSENSE: 22.549 mV, RANGE: 0.902 A
PMU AMUX: A4

68

IN

68

IN

PP3V3_G3SSW_SNS

47 48 49 76

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

3

V+

U5620

5

IN-

4

IN+ REF

INA214

SC70

100X

CRITICAL

GND

2

OUT

BYPASS=U5620.3:2:5MM

1

C5621

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_LCDBKLT_IOUT

PLACE_NEAR=U5620.6:5MM

1

R5625

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.C14:5.2MM

PLACE_NEAR=U7800.C14:5.2MM

R5629

7.15K

1/20W

1%
MF

201

21

PMU_LCDBKLT_ISENSE

1%

1/20W

MF

201

1

2

R5628

12.7K

49

PLACE_NEAR=U7800.C14:5.2MM

1

C5629

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

48

IN

48

IN

49

49 48 47 42 35

49

49

49

PMU ADC Assignments

PMU_VDDMAIN_ISENSE

MAKE_BASE=TRUE

NC_PMU_AMUX_A1

MAKE_BASE=TRUE

NO_TEST=1

PMU_WLANBT_ISENSE

MAKE_BASE=TRUE

NC_PMU_AMUX_A3

MAKE_BASE=TRUE

NO_TEST=1

PMU_LCDBKLT_ISENSE

MAKE_BASE=TRUE

PMU_CPU_VSENSE

MAKE_BASE=TRUE

PMU_NAND_VSENSE

MAKE_BASE=TRUE

PMU_VCCIO_VSENSE

MAKE_BASE=TRUE

PMU_VDDMAIN_ISENSE
NC_PMU_AMUX_A1
PMU_WLANBT_ISENSE
NC_PMU_AMUX_A3
PMU_LCDBKLT_ISENSE
PMU_CPU_VSENSE
PMU_NAND_VSENSE
PMU_VCCIO_VSENSE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

65

65

65

65

65

65

65

65

B

A

8

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

A

PAGE TITLE

Power Sensors Extended

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=SENSORS

67

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

56 OF 145

SHEET

49 OF 85

1

SIZE

D

678

3 245

1

D

(TC0P)

CPU SENSOR

Location:

Top, Opposite CPU

(TM0P)

DRAM SENSOR

Location:

Bottom, Opposite U2300

Q5810

BC846BMB

SOT883

CRITICAL

Q5820

BC846BMB

SOT883

CRITICAL

THMSNS_CPU_D1_P

3

1

2

NO_XNET_CONNECTION=1

C5810

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.A1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_CPU_D1_N

NO_XNET_CONNECTION=1

THMSNS_DRAM_D2_P

3

1

2

NO_XNET_CONNECTION=1

C5820

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.B1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_DRAM_D2_N

NO_XNET_CONNECTION=1

50

XW5810

SM

21

50

XW5820

SM

21

PLACE_NEAR=U5800.A3:5MM

D

PLACE_NEAR=U5800.A3:5MM

C

(TSMP)

SoC SENSOR

Location:

Top, Opposite SOC

(TCaP)

PMIC SENSOR

Location:

Top, Opposite PMIC

(TH0a)

NAND SENSOR

Location:

Top, Opposite U8700

Q5830

BC846BMB

SOT883

CRITICAL

Q5840

BC846BMB

SOT883

CRITICAL

Q5850

BC846BMB

SOT883

CRITICAL

THMSNS_SOC_D3_P

3

1

2

NO_XNET_CONNECTION=1

C5830

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.C1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_SOC_D3_N

NO_XNET_CONNECTION=1

THMSNS_PMIC_D4_P

3

1

2

NO_XNET_CONNECTION=1

C5840

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.D1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_PMIC_D4_N

NO_XNET_CONNECTION=1

THMSNS_NAND_D5_P

3

1

2

C5850

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.A2:5MMNO_XNET_CONNECTION=1

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_NAND_D5_N

NO_XNET_CONNECTION=1

50

XW5830

SM

21

50

XW5840

SM

21

50

XW5850

SM

21

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

PP1V8_G3S

76

THMSNS_CPU_D1_P

50

THMSNS_DRAM_D2_P

50

THMSNS_SOC_D3_P

50

THMSNS_PMIC_D4_P

50

THMSNS_NAND_D5_P

50

THMSNS_CHGR_D6_P

50

THMSNS_WLAN_D7_P

50

50 25

TBT_X_THERM_D_P
THMSNS_DN

R5810

100K

1%

1/20W

MF

201

THMSNS_ADDR

1

2

R5800

0

21

5%

1/20W

MF

0201

PP1V8_G3S_THMSNS_R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1500

VOLTAGE=1.8V

D3

V+

U5800

TMP468

A1
B1
C1
D1
A2
B2
C2
D2

A3

B4

D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+

D-

ADD

DSBGA

CRITICAL

THERM2*

GND

A4

SCL

SDA

THERM*

D4

C4

C3

B3

1

C5800

2

NC

NC

0.1UF

10%
16V
X7R-CERM
0402

I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA

IN

BI

C

45

45

B

(TCHP)

Charger SENSOR

Location:

Bottom, Between Q7030 and Q7040

(TW0P)

Wireless SENSOR

Location:

Top, Near wireless module

Q5860

BC846BMB

SOT883

CRITICAL

Q5870

BC846BMB

SOT883

CRITICAL

THMSNS_CHGR_D6_P

3

1

2

NO_XNET_CONNECTION=1

5%
25V
C0G

0201

1

2

C5860

100PF

PLACE_NEAR=U5800.B2:5MM

PLACE_NEAR=U5800.A3:5MM

THMSNS_CHGR_D6_N

NO_XNET_CONNECTION=1

THMSNS_WLAN_D7_P

3

1

2

NO_XNET_CONNECTION=1

5%
25V
C0G

0201

1

2

C5870

100PF

PLACE_NEAR=U5800.C2:5MM

PLACE_NEAR=U5800.A3:5MM

THMSNS_WLAN_D7_N

50

XW5860

SM

21

50

XW5870

SM

21

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

U5800 I2C Address:

Write: 0x90
Read: 0x91

(Tm0P)

Ambient SENSOR

INTERNAL (U5800)

B

A

(TUDD)

TITAN RIDGE SENSOR

INTERNAL (U2800)

50 25

26

IN

IN

NO_XNET_CONNECTION=1

5%
25V
C0G

0201

1

2

C5880

100PF

TBT_X_THERM_D_P

PLACE_NEAR=U5800.D2:5MM

PLACE_NEAR=U5800.A3:5MM

TBT_X_THERM_D_N

NO_XNET_CONNECTION=1

XW5880

SM

NO_XNET_CONNECTION=1

PLACE_NEAR=U5800.A3:5MM

21

BOM_COST_GROUP=SENSORS

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

Thermal Sensors

DRAWING NUMBER

051-04039

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

58 OF 145

SHEET

50 OF 85

2.0.0

SIZE

D

SYNC_DATE=02/14/2017

A

8

67

35 4

2

1

678

3 245

1

D

51 76

79 51

79 51

PP5V_G3S
FAN_LT_PWM

FAN_LT_TACH
TP_FAN_OTP1
TP_FAN_OTP2

518S0818

J6000

FF14A-6C-R11DL-B-3H

F-RT-SM

7

1
2
3
4
5
6

8

D

C

PP5V_G3S

51 76

10%
16V

0402

1

2

C6070

0.1UF 12PF

X7R-CERM

1

C6071

5%
25V

2

CERM
0201

CRITICAL

DZ6005

ESD8472MUT5G

21

X3DFN2-1

CRITICAL

DZ6007

ESD8472MUT5G

21

1

C6072

3PF

+/-0.1PF
25V

2

C0G
0201

FAN_LT_PWM

FAN_LT_TACH

C

79 51

79 51

B

35

OUT

X3DFN2-1

PP1V8_G3S

76

SMC_FAN_0_TACH

FAN SUPPORT

R6005

47K

21

FAN_LT_TACH

5%

1/20W

MF

201

R6000

47K

5%

1/20W

MF

201

B

1

2

79 51

A

35

IN

NOSTUFF

R6001

SMC_FAN_0_PWM

R6002

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

1

1

GS

2

2

1

Q6000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

FAN_LT_PWM

3

79 51

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

Fans

2

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

60 OF 145

SHEET

51 OF 85

BOM_COST_GROUP=FAN

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

8

67

35 4

2

1

D

678

3 245

1

On RIO Board:

AMR
CODEC
MESA
SPKR AMP

J6100

502250-8045

F-RT-SM

48
46

D

52

53 54 76

79 54 52 34

79 54 36

46

79 43

79 43

79 36

82 79 65 57

79 43

79 43

79 43

79 43

79 53 52 34

52 76

52 76

52 76

PP3V3_G3S_G3H_RIO
PP1V8_G3S
CODEC_INT_L
SPKR_ID1
I2C_SPKRAMP_R_SCL
I2S_CODEC_BCLK
I2S_CODEC_R2D
SPI_MESA_MISO
PMU_ONOFF_L
SPI_MESA_CLK
SMC_LID_RIGHT
I2S_SPKRAMP_R_BCLK
I2S_SPKRAMP_R_LRCLK_R
SPKRAMP_RESET_L
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

1
3
5
7
9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PP1V8_SLPS2R
PP3V3_G3S_G3H_RIO
CODEC_RESET_L
CODEC_WAKE_L
I2C_SPKRAMP_R_SDA
I2S_CODEC_D2R
AUD_PWR_EN
I2S_CODEC_LRCLK
MESA_INT
SPI_MESA_MOSI
MESA_PWR_EN
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_R2D
SPKRAMP_INT_L

NC

PPBUS_G3H
PPBUS_G3H

43 55 75

52

79 35

79 54 52 35

46

79 36

79 65

79 36

79 52 34

79 43

79 43 34

79 53 36

79 43

79 53 52 34

52 76

52 76

C

PP3V3_G3S

76

47
49

518S00155
Mates with 998-11285

on X1032 RIO Flex J0200

NOSTUFF

R6100

0

21

5%

1/20W

MF

0201

PP3V3_G3S_G3H_RIO

VOLTAGE=3.3V

C

52

B

PP3V3_G3H

76

R6101

0

21

5%

1/20W

MF

0201

B

A

1

C6100

100PF

5%
25V

2

C0G
0201

1

C6101

100PF

5%
25V

2

C0G
0201

1

C6102

100PF

5%
25V

2

C0G
0201

1

C6103

100PF

5%
25V

2

C0G
0201

1

C6104

100PF

5%
25V

2

C0G
0201

MESA_INT
CODEC_INT_L
CODEC_WAKE_L
SPKRAMP_INT_L
SPKRAMP_RESET_L

79 52 34

79 54 52 34

79 54 52 35

79 53 52 34

79 53 52 34

A

PAGE TITLE

RIO Connector

SIZE

D

BOM_COST_GROUP=AUDIO

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

61 OF 145

SHEET

52 OF 85

8

67

35 4

2

1

1X MONO SPEAKER AMPLIFIER

APN: 353S01629
GAIN: 0DBFS = 6.31 VRMS

678

3 245

1

D

C

LEFT AMPLIFIER

79 52 34

43

79 52 36

43

43

PP1V8_G3S

52 54 76

SPKRAMP_INT_L

OUT

I2S_SPKRAMP_L_R2D

IN

I2S_SPKRAMP_L_D2R

OUT

I2S_SPKRAMP_L_LRCLK_R

IN

IN

I2S_SPKRAMP_L_BCLK

NOSTUFF

1

R6400

47K

5%
1/20W
MF
201

2

R6401

5% 1/20W

33

21

SHORT-8L-0.25MM-SM

XW6410

79 53 52 34

21

I2S_SPKRAMP_L_D2R_R

201MF

46

46

IN

BI

IN

SPKRAMP_RESET_L

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

SPKRAMP_L_MODE

53

PLACE_NEAR=U6400.D2:5 MM

CRITICAL

1

C6402

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.C1:5 MM

VOLTAGE=1.8V

PLACE_NEAR=U6400.D2:3 MM

CRITICAL

1

C6403

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C1:3 MM

PP1V8_S0_SPKRAMP_AVDD

CRITICAL

1

C6400

1UF

10%

10V

2

X5R
402-1

CRITICAL

1

C6401

0.1UF

10%

25V

2

X5R
0201

C3

F3
F4

D4

F2
E1

E2

F1

E4
E3

E5
F5

SDZ*

SDA
SCL

IRQZ

MODE

SDIN
SDOUT

FSYNC

SBCLK

PDMD0
PDMCK0

PDMD1
PDMCK1

C1

D2

IOVDDAVDD

U6400

PTAS5770LB2

CSP

GND

C2

PGND

A4

B4

C4

VBAT

C5

BST_P
OUT_P
OUT_P

VSNS_P

BST_N
OUT_N
OUT_N

VSNS_N

AREG

DREG

PLACE_NEAR=U6400.C4:3 MM

CRITICAL

1

C6404

0.1UF

10%

25V

2

X5R
0201

B2

SPKRAMP_L_BSTP

A3

SPKRAMP_L_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_L_SNSP

A2

SPKRAMP_L_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_L_OUTN

B1

SPKRAMP_L_SNSN

D5

D1

SPKRAMP_L_AREG

SPKRAMP_L_DREG

PLACE_NEAR=U6400.D1:3 MM

CRITICAL

1

C6407

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6405

10UF

20%

25V

2

X5R-CERM
0603

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6406

10UF

20%

25V

2

X5R-CERM
0603

C6411

0.1UF

10%

25V

X5R

0201

C6412

0.1UF

10%

25V

X5R

0201

PLACE_NEAR=U6400.D1:5 MM

CRITICAL

1

C6408

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.D5:3 MM

CRITICAL

1

C6409

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6415

10UF

20%

25V

2

X5R-CERM
0603

CRITICAL

BYPASS=U6400.B2:B3:5 MM
NO_XNET_CONNECTION=1

21

L6400

180OHM-3.4A

CRITICAL

BYPASS=U6400.A2:A5:5 MM
NO_XNET_CONNECTION=1

21

L6401

180OHM-3.4A

PLACE_NEAR=U6400.D5:5 MM

CRITICAL

1

C6410

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6416

10UF

20%

25V

2

X5R-CERM
0603

CRITICAL

PLACE_NEAR=U6400.A3:10 MM

21

0806

21

SHORT-8L-0.25MM-SM

XW6400

PLACE_NEAR=J6620.1:3 MM

CRITICAL

PLACE_NEAR=U6400.A5:10 MM

21

0806

SHORT-8L-0.25MM-SM

PLACE_NEAR=J6620.4:3 MM

XW6401

21

NOSTUFF

CRITICAL

C6413

220PF

10%

25V

X7R-CERM

201

D

PPBUS_G3H

SPKRCONN_L_OUTP

OUT

53 76

79 54

C

SPKRCONN_L_OUTN

NOSTUFF

OUT

CRITICAL

1

2

1

C6414

220PF

10%

25V

2

X7R-CERM
201

79 54

B

A

LEFT BULK CAPACITANCE

CRITICAL

1

C6480

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C6481

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C6482

68UF

20%
16V

2

AL
CASE-D2-SM

CRITICAL

1

C6483

68UF

20%
16V

2

AL
CASE-D2-SM

PPBUS_G3H

53 76

79 53 52 34

53

SPKRAMP_RESET_L

SPKRAMP_L_MODE

R6402

100K

1/20W

5%
MF

201

21

R6480

0

21

5%

1/20W

MF

0201

MODE PIN
GND
470 to GND
470 to IOVDD
2k2 to GND
2k2 to IOVDD
10k to GND
10k to IOVDD
47k to IOVDD

I2C ADDR

0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38

CHANNEL

LEFT

RIGHT

BOM_COST_GROUP=AUDIO

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_MASTER=AHAAGE_AUD

PAGE TITLE

Audio Speaker Amplifiers

DRAWING NUMBER

051-04039

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

64 OF 145

SHEET

53 OF 85

2.0.0

SIZE

D

SYNC_DATE=05/23/2017

B

A

8

67

35 4

2

1

D

678

3 245

1

DMIC Secure Disable

PP1V8_G3S

54 55 76

CRITICAL

U6615

74AUP1G08GF

6

43

SEP_DMIC_DISABLE_OUT_L

IN

79 55

IN

PDM_DMIC_DATA0_ISOL

BYPASS=U8515::2MM

C6615

0.1UF

CERM-X5R

10%

6.3V
0201

SOT891

VCC

2

A Y

AND

1

B

5

1

NC

2

NC

GND

3

4

PDM_DMIC_DATA0_R

R6615

33

21

5%

1/20W

MF

201

PDM_DMIC_DATA0

35

D

C

79 55

PP1V8_G3S

54 55 76

IN

PDM_DMIC_DATA1_ISOL

BYPASS=U8518::2MM

C6618

0.1UF

10%

6.3V

CERM-X5R

0201

CRITICAL

U6618

74AUP1G08GF

6

SOT891

VCC

2

A Y

AND

1

B

5

NC

1

2

NC

GND

3

4

PDM_DMIC_DATA1_R PDM_DMIC_DATA1

R6618

33

21

5%

1/20W

MF

201

OUT

35

C

R6650

0

21

5%

1/20W

MF

0201

I2S_SPKRAMP_R_D2R

36

79 36

PP1V8_G3S

52 53 54 76

SPKR_ID0

OUT

LEFT SPEAKER CONNECTOR

APN: 518S0521

NOSTUFF

47K

5%

1/20W

MF

201

1

2

79 53

79 53

SPKRCONN_L_OUTP

IN

SPKRCONN_L_OUTN

IN

R6620

1

C6620

3PF

+/-0.1PF
25V

2

C0G
0201

1

C6621

3PF

+/-0.1PF
25V

2

C0G
0201

J6620

78171-0004

M-RT-SM

5

1
2
3
4

6

B

AUDIO JACK CODEC PULL-UPS

PP1V8_G3S

1

R6640

47K

5%
1/20W
MF
201

2

1

R6641

47K

5%
1/20W
MF
201

2

52 53 54 76

RIGHT SPEAKER ID

PP1V8_G3S

52 53 54 76

NOSTUFF

47K

5%
MF

201

1

2

R6630

1/20W

B

DESIGN: X1032/MLB

A

8

CODEC_WAKE_L SPKR_ID1
CODEC_INT_L

IN OUT
IN

79 52 35

79 52 34

79 52 36

67

LAST CHANGE: Fri Sep 15 15:09:18 2017

A

SYNC_DATE=04/19/2017SYNC_MASTER=AHAAGE_AUD

PAGE TITLE

Audio Connectors

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=AUDIO

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

66 OF 145

SHEET

54 OF 85

1

SIZE

D

678

3 245

1

IPD B2B CONNECTOR

Bottom side contacts used
Pinout reversed from flex

D

C

PPBUS_G3H_TPAD

49 76

CRITICAL

F6700

3AMP-32V

0603

CRITICAL

L6700

30-OHM-5A

21

PPBUS_G3H_TPAD_FUSED PPBUS_G3H_TPAD_FLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000

VOLTAGE=13.1V

0603

21

C6700

0.1UF

10%
25V
X5R

0201

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000

1

2

VOLTAGE=13.1V

516S0784

CRITICAL

J6700

AA03-S042VA1

F-ST-SM

79 43

79 43

79 54

79 55

82 79 65 57 55

79 55

79 55

79 56

79 56

79 56

79 56

79 56

79 55

SMC_LID_LEFT
PDM_DMIC_CLK0
PDM_DMIC_DATA0_ISOL
PP5V_G3S_IPD_F
PMU_RSLOC_RST_L
PP3V3_G3H_IPD_F
PP3V3_G3S_IPD_F
I2C_TPAD_3V3_SCL

SPI_TPAD_3V3_MISO
SPI_TPAD_3V3_CS_L
TPAD_SPI_3V3_INT_L
TPAD_KBD_3V3_WAKE_L
TP_USB_TPADP
TP_USB_TPAD_VBUS_ENABLE
PP5V_G3S_IPD_F

79

D

4443

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

PDM_DMIC_CLK1
PDM_DMIC_DATA1_ISOL

PP1V8_G3S
PP1V8_SLPS2R
PP5V_G3S_IPD_F

I2C_TPAD_3V3_SDA
SPI_TPAD_3V3_CLK

SPI_TPAD_3V3_MOSI
TPAD_SPI_3V3_EN

TP_USB_TPADN

IPD_LID_OPEN

79 43

79 54

54 76

43 52 75

79 55

79 56

79 56

79 56

79 56

79 55 43

79 55

79 55

PP3V3_G3H_IPD_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

C6701

0.1UF

X5R-CERM

PP3V3_G3S_IPD_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

C6702

0.1UF

X5R-CERM

10%
10V

0201

10%
10V

0201

FERR-120-OHM-1.5A

1

2

FERR-120-OHM-1.5A

1

2

CRITICAL

L6701

2 1

0402-LF

CRITICAL

L6702

2 1

0402-LF

PP3V3_G3H

PP3V3_G3S

55 76

C

55 76

B

4645

CRITICAL

L6703

FERR-120-OHM-1.5A

79 55

PP5V_G3S_IPD_F

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

VOLTAGE=5V

C6703

0.1UF

X5R-CERM

10%
10V

0201

2 1

1

2

0402-LF

PP5V_G3S

76

B

A

BYPASS=J6700.2::1.5MM

1

C6710

100PF

5%
25V

2

C0G
0201

PMU_RSLOC_RST_L

IPD_LID_OPEN

BYPASS=J6700.30::1.5MM

1

C6712

100PF

5%
25V

2

C0G
0201

IPD Connector

PP3V3_G3S

55 76

PP3V3_G3H

55 76

82 79 65 57 55

79 55 43

C6775

12PF

5%

25V
CERM
0201

1

2

1

C6776

3PF

+/-0.1PF
25V

2

C0G
0201

C6777

12PF

5%

25V
CERM
0201

1

2

1

C6778

3PF

+/-0.1PF
25V

2

C0G
0201

Cowling Bosses

SH6700

STDOFF-2.7SQ1.15ID-H1.11-SM

1

SH6701

STDOFF-2.7SQ1.15ID-H1.11-SM

1

BOM_COST_GROUP=TRACKPAD

SYNC_MASTER=X260_MLB

PAGE TITLE

Keyboard & Trackpad 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/16/2017

DRAWING NUMBER

051-04039

REVISION

BRANCH

PAGE

67 OF 145

SHEET

55 OF 85

A

SIZE

D

2.0.0

8

67

35 4

2

1

678

3 245

1

Trackpad Level Shifting

D

PP1V8_AWAKE

75

42 36

OUT

SPI_TPAD_MISO

R6803

36

43 42

43 42

R6804

1/20W

100K

5%

1/20W

MF

201

IN

IN

IN

20

5%
MF

201

1

2

SPI_TPAD_CS_L

SPI_TPAD_CLK

SPI_TPAD_MOSI

21

SPI_TPAD_MISO_R SPI_TPAD_3V3_MISO

PLACE_NEAR=U6860.5:2MM

BYPASS=U6860::5MM

C6860

0.1UF

X5R-CERM

10%
10V

0201

PP3V3_G3S

1

2

NOSTUFF

R6872

100K

5%

1/20W

MF

201

1

2

R6873

100K

5%

1/20W

MF

R6875

PLACE_NEAR=U6860.9:2MM

R6876

PLACE_NEAR=U6860.8:2MM

1

2

79 55

SPI_TPAD_3V3_CLK

SPI_TPAD_3V3_MOSI

20

20

OUT

21

1/20W5%

201MF

21

1/20W5%

MF

201

BYPASS=U6860::5MM

1

14

2

13

VCCBVCCA

U6860

SN74AVC4T774-COMBO

15

16

1

A1
DIR1

2

A2
DIR2

3

A3

5

DIR3

4

A4

6

DIR4

7

OE*

QFN

GND

8

B1

B2

B3

B4

12

11

10

9

1

C6861

0.1UF

10%
10V

2

X5R-CERM
0201

R6874

100K

1/20W

SPI_TPAD_3V3_CS_L

SPI_TPAD_3V3_CLK_R

SPI_TPAD_3V3_MOSI_R

NOSTUFF

R6870

100K

1/20W

201

5%
MF

201

5%
MF

1

R6871

100K

2

IN

1

2

R6880

1

5%

1/20W

MF

201 201

2

79 55

100K

5%

1/20W

MF

201

56 76

OUT

OUT

D

79 55

79 55

C

B

45

45

IN

BI

PP1V8_G3S

56 76

I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA

PLACE_NEAR=Q6861.4:2MM

R6879

30

5%

1/20W

MF

201

CKPLUS_WAIVE=I2C_PULLUP

21

I2C_TPAD_SDA_R

2

GS

1

5

GS

4

Q6861

SOT563

SSM6N15AFEAP

D

I2C_TPAD_3V3_SCL_R

6

Q6861

SOT563

SSM6N15AFEAP

D

I2C_TPAD_3V3_SDA_R

3

376S0855 DQed for Q6961
per rdar://37241842

R6812

4.7K

5%

1/20W

MF

201

NC

PP1V8_G3S

56 76

PP3V3_G3S

1

2

1

R6813

4.7K

5%
1/20W
MF
201

2

PLACE_NEAR=Q6861.6:2MM

56 76

43

OUT

10K

5%

1/20W

MF

201

1

2

R6863

TPAD_SPI_INT_L TPAD_SPI_3V3_INT_L

2

GS

1

5

GS

4

Q6862

SOT563

SSM6N15AFEAP

D

6

Q6862

SOT563

NCNC

SSM6N15AFEAP

D

3

PP3V3_G3S

56 76

1

R6864

100K

5%
1/20W
MF
201

2

IN

C

79 55

R6877

30

21

I2C_TPAD_3V3_SCL

5%

1/20W

MF

201

PLACE_NEAR=Q6861.3:2MM

CKPLUS_WAIVE=I2C_PULLUP

R6878

30

21

I2C_TPAD_3V3_SDA

5%

1/20W

MF

201

CKPLUS_WAIVE=I2C_PULLUP

OUT

BI

79 55

PP1V8_G3S

56 76

10K

5%

1/20W

MF

201

1

2

GS

2

1

Q6865

SOT563

SSM6N15AFEAP

D

6

R6865

79 55

43

OUT

TPAD_KBD_WAKE_L TPAD_KBD_3V3_WAKE_L

PP1V8_G3S

56 76

PP3V3_G3S

56 76

PP3V3_G3S

56 76

1

R6866

100K

5%
1/20W
MF
201

2

IN

79 55

NOSTUFF

1

R6868

100K

5%
1/20W
MF
201

2

BI

B

79

43

BI

10K

5%

1/20W

MF

201

1

5

GS

2

4

Q6865

SOT563

SSM6N15AFEAP

D

3

Pull-Up on IPD module

R6867

TPAD_ACTUATOR_DISABLE_L TPAD_3V3_ACTUATOR_DISABLE_L

A

PP1V8_G3S

56 76

BYPASS=U6855::5MM

10%
10V

0201

1

2

NC

VCC_A

U6855

SN74AUP1T34-COMBO

A

5

NC

6

1

VCC_B

SON

42

B

GND

3

C6855

0.1UF

X5R-CERM

34

TPAD_SPI_EN TPAD_SPI_3V3_EN

IN OUT

5%

1/20W

MF

201

1

2

R6852

100K

BYPASS=U6855::5MM

1

C6856

0.1UF

10%
10V

2

X5R-CERM
0201

1

2

PP3V3_G3S

NOSTUFF

1

R6854

100K

5%
1/20W
MF
201

2

R6853

100K

5%
1/20W
MF
201

56 76

79 55

SYNC_MASTER=X589_CARD_IPD

PAGE TITLE

SYNC_DATE=02/16/2017

A

Keyboard & Trackpad 2

SIZE

D

BOM_COST_GROUP=TRACKPAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

68 OF 145

SHEET

56 OF 85

8

67

35 4

2

1

D

518-00030

Mates with x

CRITICAL

J6950

RCPT-BMU

F-RT-TH-1

10
8

1
2
3
4
5
6
7

9
11

1

C6950

0.1UF

10%
25V

2

X7R-CERM-1
0402

1

C6951

1UF

10%

16V

2

CER-X6S
0402

R6951

4.7K

1/20W

1

3

PP3V3_G3H

1

R6952

4.7K

5%
1/20W
MF
201

2

5%
MF

201

2

1

2

D6950

SC-75

RCLAMP2402B

PPVBAT_G3H_CONN

79

SMBUS_3V3_BATT_SCL

79

SMBUS_3V3_BATT_SDA
SYS_DETECT_L

SYSDET:AON

1

R6950

10K

5%
1/20W
MF
201

2

3

2

678

76

79 58

79

SYSDET:FET

D

Q6955

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

S G

1

79

376S0855 DQed for Q6950
per rdar://37241842

Q6950

SSM6N15AFEAP

SOT563

D

6

Q6950

SSM6N15AFEAP

SOT563

D

3

PP3V3_G3H_RTC

SYSDET:FET

1

R6955

10K

2

SYS_DETECT

SW6955

SOX-152HNT

SM

21

5%
1/20W
MF
201

3 245

PP1V8_SLPS2R

2

GS

45 75

PP3V3_G3H_RTC

76

1

R6941

1K

21

I2C_PWR_SCL

1

5

GS

I2C_PWR_SDA

4

76

1

R6959

1M

5%
1/20W
MF
201

2

Copied from J212:
DIM LED always lit
when AON is energeized

IN

BI

45

45

82 79 65 52

82 79 65 55

IN
IN

BYPASS=U6940::3MM

C6940

0.1UF

0201

PMU_ONOFF_L
PMU_RSLOC_RST_L

10%

25V

X5R

1

2

3
4

SLG4AP41183

BTN1
BTN2

1

VDD

U6940

STQFN

CRITICAL

GND

7

RESET

NC
NC
NC
NC
NC
NC
NC

10

2
5
6
8
9
11
12

CHGR_RST_IN_R

NC
NC
NC
NC
NC
NC
NC

5%

1/20W

MF

201

R6940

1K

5%

1/20W

MF

201

UPC_PMU_RESET

21

CHGR_RST_IN

OUT

OUT

65 27

58

D

SYS_DETECT_LED

A

D6959

WHITE-140MCD-0.005A-2.7V

0402

K

C

SYSDET:FET

C

B

A

PPVIN_G3H_P3V3G3HRTC

47 76

58

IN

CRITICAL

1

C6960

68UF

20%
16V

2

AL
CASE-D2-SM

CRITICAL

1

C6961

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C6962

2.2UF

20%
25V

2

X6S-CERM
0402

2

R6965

10

5%
1/20W
MF
201

1

P3V3G3H_AVIN

R6960

0

5%
MF

0201

21

CRITICAL

1

C6965

0.1UF

10%
25V

2

X6S-CERM
0201

GND_P3V3G3H_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CHGR_EN_MVR CHGR_EN_MVR_R

1/20W

3.3V G3H RTC VR

12

11

PVIN

PVIN

10

AVIN

8

DEF

13

EN

7

FSW

XW6960

SM

21

U6960

TPS62130B-S

VQFN

CRITICAL

353S00897

PAD

THRM

PGND

16

AGND

6

17

PGND

15

SS/TR

SW
SW
SW

VOS

FB

PG

1
2
3

14

5

4

9

P3V3G3H_PHASE

DIDT=TRUE

P3V3G3H_VOS
P3V3G3H_FB
P3V3G3H_PGOOD
P3V3G3H_SS

CRITICAL

C6968

0.01UF

10%
25V

X5R-CERM

0201

PP3V3_G3H_RTC_R

57

B

1

R6967

100K

5%
1/20W
MF
201

2

2.2UH-20%-3.4A-0.066OHM

152S00477

CRITICAL

L6960

1210

21

XW6970

SM

P3V3G3H_FB_TOP

10

5%

1/20W

MF

201

1%

1/20W

MF

201

0.1%

1/20W

MF

1

2

R6970

1

2

CRITICAL

1

C6969

27PF

5%

25V

2

C0G
0201

R6971

2.8K

<Ra>

R6973

82.5K

0201-1

R6972

27.4K

0.1%

1/20W

<Rb>

MF

0201

Vout = 3.3V
Iout Max = 1.95A
f = 1.25 MHZ

2

1

1

2

P3V3G3H_FB_R

1

CRITICAL

2

1

CRITICAL

2

CRITICAL

1

C6970

10UF

20%

6.3V

2

CER-X6S
0402

Vout = 0.8 * (1 + <Ra>/<Rb>) = 3.299V

CRITICAL

1

C6971

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C6972

150UF

20%

6.3V

2

TANT
CASE-B-SM

BOM_COST_GROUP=PLATFORM POWER

PP3V3_G3H_RTC_R

57

VOLTAGE=3.3V

R6979

0

0%

1/4W

MF

0603

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

21

PP3V3_G3H_RTC

DC-In & Battery Connectors

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

76

SYNC_DATE=02/15/2017

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

69 OF 145

SHEET

57 OF 85

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

80 79

PPDCIN_G3H_CHGR_AMON

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1800

VOLTAGE=20V

FROM USB-C SOURCE

PPDCIN_G3H

76

CRITICAL

1

C7025

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7026

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7024

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7027

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

PLACE_NEAR=C7036.1:3MM

CRITICAL

1

C7034

2.2UF

20%

35V

2

X5R-CERM
0402

CRITICAL

1

C7035

2.2UF

20%

35V

2

X5R-CERM
0402

(AMON)

CRITICAL

R7020

0.01

0.5%
1W
MF

0612-1-COMBO

PLACE_NEAR=Q7030.2:2MM

CRITICAL

1

C7036

2.2UF

20%

35V

2

X5R-CERM
0402

21
43

CRITICAL

1

C7037

2.2UF

20%

35V

2

X5R-CERM
0402

TO SYSTEM

PPBUS_G3H

152S00730

CRITICAL

1

C7050

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7053

2.2UF

20%

25V

2

X5R-CERM
0402-1

CRITICAL

1

C7054

2.2UF

20%

25V

2

X5R-CERM
0402-1

1

C7055

1000PF

10%
25V

2

X7R
0201

CRITICAL

L7030

2.7UH-20%-8.7A-0.025OHM

CHGR_PHASE1 CHGR_PHASE2

DIDT=TRUE
SWITCH_NODE=TRUE

7

6

10

4

3

2

5

PIMA062D

80

21

DIDT=TRUE
SWITCH_NODE=TRUE

7

6

CRITICAL

1

C7056

33UF

20%
16V

2

TANT
CASED12-SM

5

1043

2

58 76

D

C

CHGR_CSI_P

R7021

1.00

1/20W
MF-LF

0201

CRITICAL

10%

50V

0402

1

2

C7021

0.047UF

CER-X7R

1%

1

2

CRITICAL

C7023

0.47UF

CHGR_CSI_N

1

R7022

1.00

1%
1/20W
MF-LF
0201

2

CHGR_CSIR_NCHGR_CSIR_P

CRITICAL

1

C7022

0.047UF

10%

50V

2

CER-X7R
0402

D1

Q7030

SIZ342DT

PWRPAIR-3X3-COMBO

CHGR_GATE_Q1

DIDT=TRUE
GATE_NODE=TRUE

CRITICAL

S1/D2G1G2

9

1

CHGR_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

CRITICAL

1

C7030

0.1UF

10%

25V

2

X7R-CERM-1
0402

CHGR_BOOT1_RC

DIDT=TRUE
SWITCH_NODE=TRUE

1

R7030

0

5%
1/16W
MF-LF
402

2

8

CHGR_GATE_Q2

DIDT=TRUE
GATE_NODE=TRUE

S2

XW7030

SM

CHGR_GATE_Q3

GATE_NODE=TRUE

2

1

2

XW7031

SM

1

CHGR_BOOT1

DIDT=TRUE
SWITCH_NODE=TRUE

21

S2

DIDT=TRUE

CRITICAL

G2

CHGR_LX2

SWITCH_NODE=TRUE

DIDT=TRUE

CRITICAL

C7040

0.1UF

10%

X7R-CERM-1

25V

0402

CHGR_BOOT2_RC

SWITCH_NODE=TRUE

DIDT=TRUE

R7040

0

5%
1/16W
MF-LF

402

CHGR_BOOT2

SWITCH_NODE=TRUE

DIDT=TRUE

S1/D2

981

1

2

1

2

G1

CHGR_GATE_Q4

DIDT=TRUE
GATE_NODE=TRUE

D1

(PBUS)

Q7040

SIZ342DT

PWRPAIR-3X3-COMBO

CHGR_CSO_P

(BMON)

CRITICAL

R7060

0.005

1%
1W
MF

0612-8

12
34

CHGR_CSO_N

CRITICAL

C7065

2.2UF

20%

25V

X5R-CERM

0402-1

79

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CRITICAL

1

2

C7066

2.2UF

20%

25V

X5R-CERM

0402-1

CRITICAL

1

2

C7067

0.1UF

10%

25V

X5R

0201

CRITICAL

Q7065

SI7655DN-COMBO

PWRPK-1212-8

SYM-VER-2

S

3
2
1

G

4

CRITICAL

1

C7068

0.01UF

2

D

80

5

1

10%

25V

X5R-CERM

2

0201

PPVBAT_G3H_FUSE

MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CRITICAL

F7000

12A-32V-0.0045OHM

21

1206

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6000MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

57
79

C

B

A

NOSTUFF

C7016

0.01UF

10%

25V

X5R-CERM

0201

PP1V8_SLPS2R

75

1

R7015

750K

1%
1/20W
MF
201

2

1

2

PPBUS_G3H

58 76

CHGR_AUX_DET

1

R7016

255K

1%
1/20W
MF
201

2

CRITICAL

20%

6.3V
X5R

1

2

C7080

1.0UF

0201-1

R7073

1/20W

0201

CRITICAL

C7078

1

0

5%
MF

2

1

2.2UF

20%

35V

X5R-CERM

2

0402

CRITICAL

C7070

0.12UF

10%
10V
X5R

0402

20%

4V

CERM-X5R-1

201

NO_XNET_CONNECTION=1

VOLTAGE=5V

PPCHGR_VDDA

CRITICAL

1

C7075

20%

25V

2

X5R-CERM
0402-1

B5

P_IN

C5

CSIN

D5

CSIP

A5

PBUS_PWR

D3

AUX_DET

F5

VDDIO1P8

45

45

57

BI

I2C_PWR_SDA
I2C_PWR_SCL

IN

CHGR_RST_IN

IN

79

CHGR_HPWR_EN_L

NOSTUFF

CHGR_COMP

H: 3-CELL
L: 2-CELL

G5

SDA

H5

SCL

G2

SMC_RST_IN

G3

HPWR_EN*

E5

COMP

G4

CELL

B2

NC0

C2

NC1

E4

CRITICAL

10%
10V
X5R

0402

1

2

1

C7071

0.12UF

2

R7075

4.7

1/20W

A2

VDDA

21

5%
MF

VOLTAGE=5V

201

PPCHGR_VDDP

CRITICAL

D2

VDDP

U7000

ISL9240HI

WCSP

CRITICAL

353S01525

AGND

PGND

E2

E3

C7077

10UF2.2UF

20%

10V

X5R

0603-1

GATE_Q1

BOOT1

LX1
GATE_Q2
GATE_Q3

LX2

BOOT2

GATE_Q4

PBUS
CSOP
CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ*
CBC_ON
EN_MVR
AUX_OK

AMON

BMONNC2

1

C7064

1000PF

10%

25V

2

X7R
0201

1

R7061

2

PLACE_NEAR=U7000.A4:2mm PLACE_NEAR=U7000.B4:2mm

CHGR_CSOR_P

CRITICAL

1.00

C7061

H1
F1
G1
E1
D1
B1
C1
A1
A3
A4
B4
B3
C3
F2
H4
H3
H2
F4
F3
D4
C4

CHGR_BGATE
CHGR_VBAT
NC_CHGR_EN_VR1
TP_CHGR_SMC_RST_L
CHGR_INT_L
CHGR_CBC_ON
CHGR_EN_MVR
NC_CHGR_AUX_OK
CHGR_AMON
CHGR_BMON

OUT

OUT
OUT
OUT
OUT
OUT
OUT

0.047UF

77

65

65

57

77

47

79 47

10%

50V

CER-X7R

0402

1%
1/20W
MF-LF

0201

1

2

1

R7062

1.00

1%
1/20W
MF-LF
0201

2

CHGR_CSOR_N

1

2

CRITICAL

C7020

0.47UF

21

20%

CERM-X5R-1

NO_XNET_CONNECTION=1

4V

201

CRITICAL

1

C7062

0.047UF

10%

50V

2

CER-X7R
0402

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

R7063

1K

1%
1/20W
MF
201

2

1

C7063

4700PF

10%

25V

2

CER-X5R
0201

3

2

1

C7060

0.1UF

10%

25V

2

X5R
0201

D

Q7070

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

S G

1

R7070

24K

1%
1/20W
MF
201

2

1

R7071

SAVE_BAT_GSAVE_BAT_S PPDCIN_G3H

KA

200K

1/20W

D7070

DFN0201

GDZ5V6LP3-55

1%
MF

201

21

B

80 79 76

DESIGN: X1032/MLB
LAST CHANGE: Fri Sep 15 15:09:18 2017

SYNC_DATE=02/13/2017SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

A

PBUS Supply & Battery Charger

SIZE

D

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=PLATFORM POWER

IV ALL RIGHTS RESERVED

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

70 OF 145

SHEET

58 OF 85

8

67

35 4

2

1

678

3 245

1

D

61 59

61

61 59

61 59

NO_XNET_CONNECTION=1

R7142

0

8

IN

8

IN

CPU_VCCGTSENSE_P

C7141

CPU_VCCGTSENSE_N

330PF

10%
16V
X7R

0201

1

2

2 1

5%

1/20W

MF

0201

XW7140

SM

21

CPUGT_SENSE_P_R

C7144

470PF

21

CPUGT_SENSE_P_RC

10%
16V

X5R-X7R-CERM

0201

CPUGT_RTN

R7143

2.15K

1%

1/20W

MF

201

59

R7123

21

R7144

2K

21

1%

1/20W

MF

201

R7145

560

2 1

1%

1/20W

MF

201

CPUGT_FB_RC

1

C7143

820PF

10%
25V

2

X7R-CERM
0201

C7123

680PF

10%
25V

X7R-CERM

0201

CPUCORE_FBCPUGT_FB

59 59

CPUCORE_FB_RC

1

2

R7125

560

2 1

1%

1/20W

MF

201

R7124

2K

21

1%

1/20W

MF

201

CPUCORE_SENSE_P_RC

2.32K

1%

1/20W

MF

201

21

CPUCORE_SENSE_P_R

C7124

470PF

10%

16V

X5R-X7R-CERM

0201

CPUCORE_RTN

59

21

NO_XNET_CONNECTION=1

R7122

0

2 1

5%

1/20W

MF

0201

XW7120

SM

21

1

C7121

330PF

10%
16V

2

X7R
0201

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IN

IN

8

8

D

NO_XNET_CONNECTION=1

R7150

R7151

1K

2 1

1%

1/20W

MF

201

CPUGT_ISUMN_RC

255

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

PPBUS_HS_CPU

76

21

CPUGT_ISUMN_RCPUGT_ISUMN

C7150

3300PF

2 1

R7101

10

21

5%

1/20W

MF

201

C7101

0.22UF

10%
25V
X7R

0402

PPVIN_S0_CPUVR_VIN

MIN_NECK_WIDTH=0.2000
VOLTAGE=12.9V

1

2

41

VIN

PP5V_S3_CPUVR_VCC

MIN_LINE_WIDTH=0.0900MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

42

VCC

U7100

10%
10V

X7R-CERM

0201

61

61

61

OUT

OUT
OUT

61 59

59

CPUGT_FCCM
CPUGT_PWM1

CPUGT_PWM2

CPUGT_ISUMP
CPUGT_ISUMN_R

11 24

FCCM_B

12 25

PWM1_B

13 26

PWM2_B

7 19

ISUMP_B

8 20

ISUMN_B

ISL95828

TQFN

353S00928

FCCM_A

PWM1_A
PWM2_A
PWM3_A

ISUMP_A
ISUMN_A

27

CPUCORE_FCCM
CPUCORE_PWM1

CPUCORE_PWM2

NC

CPUCORE_ISUMP
CPUCORE_ISUMN_R

R7100

1/20W

201

1

C7100

1UF

10%
10V

2

X5R
402-1

5%
MF

1

21

PP5V_G3S

76

R7130

59

OUT

OUT
OUT

CPUCORE_ISUMN_R

59 59

301

1/20W

C7130

3300PF

2 1

10%
10V

60

60

60

60 59

X7R-CERM

0201

CPUCORE_ISUMN_RC

1%
MF

201

21

R7131

1K

2 1

1%

1/20W

MF

201

1

C7122

330PF

10%
16V

2

X7R
0201

C7131

220PF

2 1

C7133

0.01UF

2 1

C7134

0.01UF

2 1

1

C7132

0.01UF

10%
10V

2

X7R-CERM
0201

CPUCORE_ISUMP

50V C0G 02012%

CPUCORE_ISUMN

CPUCORE_ISEN1

10V10% 0201

X7R-CERM

CPUCORE_ISEN2

10V10% 0201

X7R-CERM

IN

IN

IN

IN

60 59

60

60 59

60 59

IN

IN

IN

IN

CPUGT_ISUMP

CPUGT_ISEN1

0201 10%10VX7R-CERM

CPUGT_ISEN2

0201 10%10V

X7R-CERM

10%
16V
X7R

0201

1

2

C7142

330PF

C7151

220PF

21

50VC0G 2%0201

C7153

0.01UF

2 1

C7154

0.01UF

2 1

10%
10V

0201

1

2

C7152

0.01UF

X7R-CERM

C

B

C7156

0.01UF

21

CPUGT_COMP_RC

10%
10V

X7R-CERM

0201

R7157

69.8K

1/20W

1

1%
MF

201

21

C7157

220PF

R7159

220KOHM-3%

0201

2

CPUGT_NTC_XW

2%
50V
C0G

0201

21

C7155

82PF

21

5%
25V
C0G

0201

R7155

CPUGT_IMON

R7158

12.1K

1/20W

Alert, min = 99C
Hot, min = 105C

XW7159

1%
MF

201

SM

21

CPUGT_NTCCPUGT_NTC_R

21

3.40K

1%

1/20W

MF

201

61 59

60

60

61 59

OUT

60 59

CPUGT_COMP

21

59

59

59

CPUGT_ISEN1
CPUGT_ISEN2

CPUGT_COMP

59

CPUGT_FB

59

CPUGT_RTN

59

CPUGT_IMON

59

CPUGT_NTC

59

CPUSA_FCCM
CPUSA_PWM
CPUSA_ISUMP

CPUSA_ISUMN_R

59

CPUSA_COMP

59

CPUSA_FB

59

CPUSA_RTN

59

CPUSA_IMON

59

CPUVR_PROG1
CPUVR_PROG2

CPUVR_PROG3
CPUVR_PROG4
CPUVR_PROG5

1

R7111

110K 63.4K

1%
1/20W
MF
201

2

1

R7112

1%
1/20W
MF
201

2

1

R7113

1.87K

1%
1/20W
MF
201

2

1

R7114

182K

1%
1/20W
MF
201

2

1

R7115

100K

1%
1/20W
MF
201

2

9 21

ISEN1_B

10 22

ISEN2_B

4 16

COMP_B

5 17

FB_B

6 18

RTN_B

2 14

IMON_B

3 15

NTC_B

34

FCCM_C

35

PWM_C

32

ISUMP_C

33

ISUMN_C

29

COMP_C

30

FB_C

RTN_C

28

IMON_C

40

PROG1

39

PROG2

38

PROG3

37

PROG4

36

PROG5

THRM_PAD

49

ISEN1_A
ISEN2_A
ISEN3_A

COMP_A

FB_A

RTN_A

IMON_A

NTC_A

VR_HOT*

VR_READY

VR_ENABLE

SDA

ALERT*

SCLK

PSYS

23

46

47

48

43

44

4531

1

CPUCORE_ISEN1
CPUCORE_ISEN2

CPUCORE_COMP
CPUCORE_FB
CPUCORE_RTN
CPUCORE_IMON
CPUCORE_NTC

CPU_VR_PROCHOT_L
CPUVR_PGOOD
CPU_VR_EN

CPUVR_VIDSOUT
CPU_VIDALERT_L
CPUVR_VIDSCLK

59

59

59

59

59

60 59

60 59

CPUCORE_COMP

59

R7135

3.40K

R7106

100

1/20W

59

OUTOUT

R7107

1/20W

1%
MF

201

0

5%
MF

0201

21

21

SMC_PROCHOT_L

ALL_SYS_PWRGD_R

R7103

100

1/20W

R7102

1% 1/20W

R7104

1% 201
R7103.2:
R7105.2:

10

49.9

PLACE_NEAR=U7100.43:5.08mm
PLACE_NEAR=U7100.45:5.08mm

1

1%
MF

201

2

21

MF 201

21

MF1/20W

OUT

19

IN

PP1V_S3

1

R7105

45.3

1%
1/20W
MF
201

2

CPU_VIDSOUT

CPU_VIDSCLK

43 42 35

59

6 8 12 15 75

CPUCORE_NTC

59

8

BI

8

OUT

8

IN

1/20W

CPUCORE_IMON

21

CPUCORE_COMP_RC

1%
MF

201

Alert, min = 99C

Hot, min = 105C

XW7139

C7135

82PF

0201

R7138

12.1K

1/20W

1%
MF

201

SM

21

21

21

5%
25V
C0G

C7136

0.01UF

X7R-CERM

R7137

84.5K

C7137

1/20W

150PF

21

5%

50V

CER-C0G

0201

CPUCORE_NTC_R

R7139

220KOHM-3%

CPUCORE_NTC_XW

0201

1%
MF

201

0201

10%
10V

C

21

21

1

2

B

A

C7175

82PF

5%
25V
C0G

0201

21

C7177

150PF

21

5%

50V

CER-C0G

0201

C7176

0.01UF

21

10%
10V

X7R-CERM

0201

R7177

95.3K

1/20W

DRAWING NUMBER

1%
MF

201

21

SYNC_DATE=03/30/2018

051-04039

REVISION

2.0.0

BRANCH

PAGE

71 OF 145

SHEET

59 OF 85

A

SIZE

D

CPUSA_COMP

59

PP1V8_S5

75

1%
MF

5%
MF

201

1

2

R7170

402

1%

1/20W

MF

201

CPUSA_ISUMN_RC

21

CPUSA_ISUMN_RCPUSA_ISUMN

59

C7170

3300PF

2 1

10%
10V

X7R-CERM

0201

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=J122_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R7108

BJT: Still applicable?
rdar://problem/31759230

CPUVR_PGOOD

65

NO_XNET_CONNECTION=1

R7162

0

8

IN

8

IN

CPU_VCCSASENSE_P

C7161

CPU_VCCSASENSE_N

330PF

10%
16V
X7R

0201

1

2

1

2

2 1

5%

1/20W

MF

0201

NO_XNET_CONNECTION=1

XW7160

SM

21

C7162

330PF

10%
16V
X7R
0201

CPUSA_SENSE_P_R

C7164

470PF

2 1

10%
16V

X5R-X7R-CERM

0201

CPUSA_RTN

CPUSA_SENSE_P_RC

R7163

1.87K

2 1

1%

1/20W

MF

201

59

R7164

1K

21

1%

1/20W

MF

201

R7165

560

2 1

1%

1/20W

MF

201

CPUSA_FB

CPUSA_FB_RC

59

1

C7163

1000PF

10%
16V

2

X7R-1
0201

60 59

60

IN

IN

MAKE_BASE=TRUE

CPUSA_ISUMP

0201

59

CPUVR_PGOOD

C7171

220PF

50VC0G 2%

C7172

0.01UF

X7R-CERM

0201

21

10%
10V

1

2

100K

1/20W

R7171

1K

2 1

1/20W

201

R7175

2.74K

1/20W

CPUSA_IMON

59

1%
MF

201

21

CPUSA_COMP_RC

CPU IMVP8 Regulator IC

Apple Inc.

8

67

35 4

2

1

678

3 245

1

D

Note:Vcore design requires 4x POSCAPs

3x shared from other VRs

PPBUS_HS_CPU

60 76

Phase 1

CRITICAL

20%
16V

TANT

1

2

C7210

33UF

CASED12-SM

CPU VCORE

C7214

2.2UF

20%
25V

X6S-CERM

0402

60 59

59

R7217

PP5V_S0_CPUCORE1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

1

C7217

2.2UF

20%
25V

2

X6S-CERM
0402

20%
25V

0402

1

2

6

VIN

1

ZCD_EN*

12

PWM

3

NC

NC

XW7210

SM

21

1

C7215

2.2UF

2

X6S-CERM

CPUCORE_FCCM

IN

CPUCORE_PWM1

IN

2.2

1/20W

2

VCIN

U7210

SIC535CD

MLP4535

CRITICAL

PGND

7

1%
MF

201

PGND

10

21

11

VDRV

BOOT

PHASE

VSWH

GL
GL

CGND

13

PP5V_G3S

1

C7216

2.2UF

20%
25V

2

X6S-CERM
0402

4

5

8

9
14

NC

CPUCORE_BOOT1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_BOOT1_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_PHASE1

80

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_GL1

60 76

CPUCORE_BOOT1_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

0

5%
1/16W
MF-LF

402

1

2

P3MM

1

SM

PP

R7219

PP7210

1

C7219

0.22UF

10%
25V

2

X7R
0402

CRITICAL

L7210

0.22UH-20%-25A-0.0045OHM

21

PPVCORE_S0_CPU_PH1

80

PILE052T-SM1-COMBO

152S01013

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7211

1K

1/20W

201

1

1%
MF

2

CRITICAL

R7210

0.001

1%

1W
MF-3
0612

1 2
3 4

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

1

R7212

200K

1%
1/20W
MF
201

2

CPUCORE_ISEN1
CPUCORE_ISUMP

CPUCORE_ISNS1_P
CPUCORE_ISNS1_N

R7214

2.2

1/20W

1%
MF

201

21

CPUCORE_ISUMN

OUT

60

OUT

OUT

60 59

R7213

200K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

CPUCORE_ISNS2_N

59

OUT
OUT

60 59

60

PPVCC_S0_CPU

D

76

Vout Max = 1.52V

C

PPBUS_HS_CPU

60 76

CRITICAL

C7230

33UF

20%
16V

TANT

CASED12-SM

Phase 2

1

2

C7234

2.2UF

20%
25V

X6S-CERM

0402

60 59

59

GND_CPUCORE1_CGND

Iout Max = 28A

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

R7237

PP5V_S0_CPUCORE2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

1

C7237

2.2UF

20% 20%
25V

2

X6S-CERM
0402

20%
25V

0402

1

2

6

VIN

1

ZCD_EN*

12

PWM

3

NC

NC

XW7230

SM

21

1

C7235

2.2UF

2

X6S-CERM

CPUCORE_FCCM

IN

CPUCORE_PWM2

IN

2.2

1/20W

2

VCIN

U7230

SIC535CD

MLP4535

CRITICAL

PGND

7

1%
MF

201

PGND

10

21

11

VDRV

BOOT

PHASE

VSWH

GL
GL

CGND

13

PP5V_G3S

1

C7236

2.2UF

25V

2

X6S-CERM
0402

4

5

8

9
14

NC

CPUCORE_BOOT2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_BOOT2_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_PHASE2

80

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_GL2

60 76

CPUCORE_BOOT2_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

0

5%
1/16W
MF-LF

402

1

2

P3MM

1

SM

PP

R7239

PP7230

1

C7239

0.22UF

10%
25V

2

X7R
0402

CRITICAL

L7230

0.22UH-20%-25A-0.0045OHM

21

PPVCORE_S0_CPU_PH2

80

PILE052T-SM1-COMBO

152S01013

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7231

1K

1/20W

201

1

1%
MF

2

CRITICAL

R7230

0.001

1%

1W
MF-3
0612

2 1
4 3

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

1

R7232

200K

1%
1/20W
MF
201

2

CPUCORE_ISEN2
CPUCORE_ISUMP

CPUCORE_ISNS2_P
CPUCORE_ISNS2_N

R7234

2.2

1/20W

1%
MF

201

21

CPUCORE_ISUMN

OUT

60

OUT

OUT

60 59

R7233

200K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

CPUCORE_ISNS1_N

59

OUT
OUT

60 59

60

f = 750kHz

C

B

A

CPU VCCSA

PP5V_G3S

76

59

59

IN

IN

CPUSA_PWM

CPUSA_FCCM

6

VCC

U7290

ISL6208F

3

PWM

7

FCCM UGATE

CRITICAL

GND

DFN

THRM

PAD

9

4

C7296

2.2UF

X6S-CERM

BOOT

PHASE

LGATE

20%
25V

0402

2

1

8

5

GND_CPUCORE2_CGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

PPBUS_HS_CPU

76

1

2

CPUSA_BOOT

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE

CPUSA_PHASE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

CPUSA_LGATE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE

CRITICAL

C7290

33UF

20%
16V

TANT

CASED12-SM

1

2

C7294

CPUSA_BOOT_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

1

5%
1/16W
MF-LF

402

1

2

R7299

R7297

2.2

1/16W
MF-LF

5%

402

21

CPUSA_UGATE_RCPUSA_UGATE

R7298

1

21

CPUSA_LGATE_R

5%
1/16W
MF-LF

402

2.2UF

20%
25V

X6S-CERM

0402

1

C7299

0.22UF

10%
25V

2

X7R
0402

B

20%
25V

0402

1

2

1

C7295

2.2UF

2

X6S-CERM

CRITICAL

Q7291

CSD58873Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

1

6

81

CPUSA_SW_LL

MIN_LINE_WIDTH=0.4000

7

MIN_NECK_WIDTH=0.2000
DIDT=TRUE

8

SWITCH_NODE=TRUE

1

R7293

2.2

5%
1/16W
MF-LF
402

2

CPUSA_SNUBR

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
DIDT=TRUE
SWITCH_NODE=TRUE

1

C7293

100PF

5%
50V

2

C0G
0402

0.47UH-20%-8.5A-0.035OHM

152S00356

CRITICAL

L7290

MHCI03020-SM

21

PPVCCSA_S0_CPU_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7291

1K

1%

1/20W

MF

201

CRITICAL

R7290

0.003

1%
1W

CYN

0612

2 1
4 3

NO_XNET_CONNECTION=1

1

2

1

2

CPUSA_ISNS_P
CPUSA_ISNS_N

R7292

0

5%
1/20W
MF
0201

CPUSA_ISUMN
CPUSA_ISUMP

XW7290

SHORT-12L-1.25MM-SM

21

PLACE_NEAR=R7290:5MM

OUT
OUT

PAGE TITLE

59

OUT

59

OUT

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PPVCCSA_S0_CPUDDR

PPVCCSA_S0_CPU

76

76

Vout Max = 1.52V
Iout Max = 4.1A
f = 750kHz

SYNC_DATE=03/30/2018SYNC_MASTER=J122_MLB

CPU VCore/VccSA Power Stage

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

BRANCH

PAGE

72 OF 145

SHEET

60 OF 85

A

SIZE

D

8

67

35 4

2

.

1

678

3 245

1

D

PPBUS_HS_CPU

61 76

CRITICAL

C7410

33UF

20%
16V

TANT

CASED12-SM

CPU VGT

Phase 1

1

2

C7414

2.2UF

20%
25V

X6S-CERM

0402

61 59

59

R7417

PP5V_S0_CPUGT1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

1

C7417

2.2UF

20%
25V

2

X6S-CERM
0402

20%
25V

0402

1

2

6

VIN

1

ZCD_EN*

12

PWM

3

NC

NC

XW7410

SM

21

1

C7415

2.2UF

2

X6S-CERM

CPUGT_FCCM

IN

CPUGT_PWM1

IN

2.2

1/20W

2

VCIN

U7410

SIC535CD

MLP4535

CRITICAL

PGND

7

1%
MF

201

PGND

10

21

11

VDRV

BOOT

PHASE

VSWH

GL
GL

CGND

13

PP5V_G3S

1

C7416

2.2UF

20%
25V

2

X6S-CERM
0402

4

5

8

9
14

NC

CPUGT_BOOT1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUGT_BOOT1_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUGT_PHASE1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

CPUGT_GL1

61 76

CPUGT_BOOT1_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

0

5%
1/16W
MF-LF

402

1

2

P3MM

1

SM

PP

R7419

PP7410

1

C7419

0.22UF

10%
25V

2

X7R
0402

CRITICAL

L7410

0.22UH-20%-25A-0.0045OHM

21

PPVCCGT_S0_CPU_PH1

PILE052T-SM1-COMBO

152S01013

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7411

1K

1/20W

201

1

1%
MF

2

CRITICAL

R7410

0.001

1%

1W
MF-3
0612

2 1
4 3

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

1

R7412

200K

1%
1/20W
MF
201

2

CPUGT_ISEN1
CPUGT_ISUMP

CPUGT_ISNS1_P
CPUGT_ISNS1_N

R7414

2.2

1/20W

1%
MF

201

21

CPUGT_ISUMN

OUT

61

OUT

OUT

61 59

R7413

200K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

CPUGT_ISNS2_N

59

OUT
OUT

61 59

61

PPVCCGT_S0_CPU

D

76

Vout Max = 1.52V

C

PPBUS_HS_CPU

61 76

CRITICAL

C7430

33UF

20%
16V

TANT

CASED12-SM

Phase 2

1

2

C7434

2.2UF

20%
25V

X6S-CERM

0402

61 59

59

GND_CPUGT1_CGND

Iout Max = 24A

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

R7437

PP5V_S0_CPUGT2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=5V

1

C7437

2.2UF

20%
25V

2

X6S-CERM
0402

20%
25V

0402

1

2

6

VIN

1

ZCD_EN*

12

PWM

3

NC

NC

XW7430

SM

21

1

C7435

2.2UF

2

X6S-CERM

CPUGT_FCCM

IN

CPUGT_PWM2

IN

2.2

1/20W

2

VCIN

U7430

SIC535CD

MLP4535

CRITICAL

PGND

7

1%
MF

201

PGND

10

21

11

VDRV

BOOT

PHASE

VSWH

GL
GL

CGND

13

PP5V_G3S

1

C7436

2.2UF

20%
25V

2

X6S-CERM
0402

4

5

8

9
14

NC

CPUGT_BOOT2

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUGT_BOOT2_RC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUGT_PHASE2

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

CPUGT_GL2

61 76

CPUGT_BOOT2_R

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

0

5%
1/16W
MF-LF

402

1

2

P3MM

1

SM

PP

R7439

PP7430

1

C7439

0.22UF

10%
25V

2

X7R
0402

CRITICAL

L7430

0.22UH-20%-25A-0.0045OHM

21

PPVCCGT_S0_CPU_PH2

PILE052T-SM1-COMBO

152S01013

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7431

1K

1/20W

201

1

1%
MF

2

CRITICAL

R7430

0.001

1%

1W
MF-3
0612

2 1
4 3

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

1

R7432

200K

1%
1/20W
MF
201

2

CPUGT_ISEN2
CPUGT_ISUMP

CPUGT_ISNS2_P
CPUGT_ISNS2_N

R7434

2.2

1/20W

1%
MF

201

21

CPUGT_ISUMN

OUT

61

OUT

OUT

61 59

R7433

200K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

CPUGT_ISNS1_N

59

OUT
OUT

61 59

61

f = 750kHz

C

B

GND_CPUGT2_CGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

B

A

8

SYNC_MASTER=J122_MLB SYNC_DATE=03/30/2018

PAGE TITLE

A

CPU VccGT Power Stage

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

67

35 4

IV ALL RIGHTS RESERVED

2

.

BRANCH

PAGE

74 OF 145

SHEET

61 OF 85

1

SIZE

D

678

3 245

1

D

5V G3S

76 62

CRITICAL

C7671

PP5V_G3S

1

2.2UF

20%
25V

X6S-CERM

2

0402

CRITICAL

1

C7675

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

CRITICAL

1

C7677

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

Vout = 5.1V
Iout Max = 6.3A
F = 500 KHZ

CRITICAL

1

C7670

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7676

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

PPVIN_G3H_P5VG3S

76 47

CRITICAL

1

C7665

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7666

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7660

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7661

2.2UF

20%
25V

2

X6S-CERM
0402

PP5V_G3S

76 62

100MA MAX OUTPUT

PP5V_S5_LDO

CRITICAL

1

C7651

10UF

20%
16V

2

X6S-CERM
0603

VOUT = 5V

76

PPVIN_G3H_P3V3G3H

76 47

CRITICAL

1

C7650

2.2UF

20%
25V

2

X6S-CERM
0402

1

2

CRITICAL

C7680

2.2UF

20%
25V
X6S-CERM
0402

CRITICAL

1

C7681

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7685

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7686

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

C7690

2.2UF

20%
25V

X6S-CERM

0402

CRITICAL

C7695

150UF

20%

6.3V
TANT

CASE-B-SM

CRITICAL

C7611

150UF

20%

6.3V
TANT

CASE-B-SM

3V3 G3H

Vout = 3.3V
Iout Max = 10.9A
F = 500 KHZ

CRITICAL

1

2

1

2

1

2

C7691

2.2UF

X6S-CERM

CRITICAL

C7696

150UF

CASE-B-SM

CRITICAL

C7697

150UF

CASE-B-SM

20%
25V

0402

20%

6.3V
TANT

20%

6.3V
TANT

PP3V3_G3H

1

2

62
76

D

CRITICAL

1

C7613

150UF

2

CASE-B-SM

20%

6.3V
TANT

1

2

CRITICAL

20%

6.3V
TANT

1

2

1

C7612

150UF

2

CASE-B-SM

C

B

A

76

76 62

PLACE_NEAR=C7675.1:5.3MM

2

XW7675

SM

1

P5VG3S_VFB1_R

NO_XNET_CONNECTION=1

1

R7671

10

5%
1/20W
MF
201

2

P5VG3S_VFB1_R2

1

R7677

6.34K

1%
1/20W
MF
201

2

P5VG3S_VFB1_RR

1

R7678

34.8K

0.1%
1/20W
MF
0201-1

2

1

R7679

10K

0.1%
1/20W
MF
0201-1

2

PP1V8_G3S

PP3V3_G3H

1.5UH-20%-12.5A-0.017OHM

2

XW7671

SM

1

CRITICAL

CRITICAL

CRITICAL

L7670

21

80

P5VG3S_VSW

PIMB062D-SM

152S00268

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600

PLACE_NEAR=L7670.1:3MM

PLACE_NEAR=L7670.2:3MM

2

XW7670

SM

NO_XNET_CONNECTION=1

1

DIDT=TRUE

P5VG3S_CS1_L_P

P5VG3S_CS1_L_N

1

R7600

100K

5%
1/20W
MF
201

2

P5VG3S_PGOOD

1

R7601

100K

5%
1/20W
MF
201

2

P3V3MAIN_PGOOD

1

6
7
8

NOSTUFF

1

R7674

2.2

5%
1/10W
MF-LF
603

2

P5VG3S_SNUBR

DIDT=TRUE
SWITCH_NODE=TRUE

NOSTUFF

1

C7674

0.001UF

10%
50V

2

CERM
402

62 65

62 65

CRITICAL

Q7660

CSD58873Q3D

Q3D

VIN

VSW

PGND

9

376S1038

PP5V_G3S

76 79 80

P5VG3S_DSCHRG_EN

P5VG3S_EN

62 65

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

3

TG

TGR

BG

P5VG3S_DRVH

4

5

P5VG3S_DRVL

R7664

2 1

DIDT=TRUE

GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

R7672

3.92K

2 1

1%

1/20W

MF

NO_XNET_CONNECTION=1

201

R7620

D7620

DLLFSD01LP3

X3-DFN0603-2

Q7620

SSM6N15AFEAP

SOT563

2

R7666

2 1

0

5%
1/16W
MF-LF

402

220K

5%

1/20W

MF

201

G S

P5VG3S_VBST_R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE

DIDT=TRUE

CRITICAL

1

C7669

0.1UF

1

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000 GATE_NODE=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.2000

10%
25V

2

X7R-CERM-1
0402

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

CRITICAL

NO_XNET_CONNECTION=1

C7673

0.1UF

21

10%
25V

X6S-CERM

0201

R7673

1.27K

1/20W

NO_XNET_CONNECTION=1

1

2

K A

1%
MF

201

21

R7621

10

21

5%

6

D

1

1/20W

MF

201

AUDIBLE SKIPPING INAUDIBLE SKIPPING

R7651

1/20W

0201

R7665

1

0

5%
1/16W
MF-LF

402

2

SWITCH_NODE=TRUE DIDT=TRUE

CRITICAL

5%
25V
C0G

0201

1

2

R7623

620

1/16W
MF-LF

C7678

560PF

R7622

620

5%
1/16W
MF-LF

402

1

2

Q7620

SSM6N15AFEAP

P5VG3S_DSCHRG_RC

1

C7620

0.047UF

10%
16V

2

X5R
0201

P5VP3V3_VREG3

P5VP3V3_VREF2

NOSTUFF

1

0

5%
MF

2

62 65

OUT

NOSTUFF

1

R7676

10K

1%
1/20W
MF
201

2

1

R7650

0

5%
1/20W
MF
0201

2

P5VP3V3_SKIPSEL

P5VG3S_VBST

P5VG3S_SW
P5VG3S_DRVL_R
P5VG3S_CSP1

DIDT=TRUE

P5VG3S_VFB1

P5VG3S_EN_DLY

62

R7675

5.49K

1%

1/20W

MF

201

P5VG3S_COMP1_R

CRITICAL

2

23

29

22

13

C7652

0.22UF

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

VBST1 VBST2

1

DRVH1 DRVH2

32

SW1 SW2

30

DRVL1

7

CSP1

8

CSN1 CSN2

11

MODE

9

10

COMP1 COMP2

4

EN1 EN2

5

PGOOD1 PGOOD2

1

2

VIN

CRITICAL

U7650

353S3905

GND

28

VREG5

QFN

VREG3

TPS51980A

THRM_PAD

33

VREF2

EN

DRVL2

CSP2

RF

VFB2VFB1

12

26

24

25

27

18
17

3
16
15

21
20

P5VXX_EN

P3V3G3H_VBST

DIDT=TRUESWITCH_NODE=TRUEDIDT=TRUE

P3V3G3H_DRVH_RP5VG3S_DRVH_R

DIDT=TRUE

P3V3G3H_SW
P3V3G3H_DRVL_R
P3V3G3H_CSP2

DIDT=TRUE

P3V3G3H_RF
P3V3G3H_VFB2
P3V3G3H_COMP2P5VG3S_COMP1

TP_P3V3G3H_EN2
P3V3MAIN_PGOODP5VG3S_PGOOD

1

2

1

10%
16V

2

CERM

402

SWITCH_NODE=TRUE

R7695

5.49K

1%
1/20W
MF
201

P3V3G3H_COMP2_R

CRITICAL

1

C7679

4700PF

10%
10V

2

X7R
201

(P5VP3V3_VREF2) (P5VP3V3_VREF2)

PLACE_NEAR=U7650.28:1MM

2

XW7650

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

VOLTAGE=0V

SM

1

GND_5V3V3_AGND

5%

402

620

5%
1/16W
MF-LF

402

1

2

R7625

1

2

R7624

620

5%
1/16W
MF-LF

402

1

2

P5V_G3S_DISCHARGEP5VG3S_DSCHRG_R

3

D

SOT563

5

G S

62

4

65

IN

P5VG3S_EN P5VG3S_EN_R P5VG3S_EN_DLY

CRITICAL

1

C7653

2.2UF

20%
25V

2

X6S-CERM
0402

SWITCH_NODE=TRUE

GATE_NODE=TRUE

NOSTUFF

R7696

CRITICAL

C7699

2700PF

0201

R7613

0

21

5%

1/20W

MF

0201

62

10%
16V
X7R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

1

R7685

2

62 65

OUT

1

10K

1%

1/20W

MF

201

2

1

2

PP3V3_G3H

76

BYPASS=U7610::5mm

1

2

P3V3G3H_VBST_R

SWITCH_NODE=TRUE

C7689

0

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6000GATE_NODE=TRUEGATE_NODE=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000DIDT=TRUE
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000DIDT=TRUE
MIN_NECK_WIDTH=0.2000

R7655

200K

1%

1/20W

MF

201

CRITICAL

1

2

0.1UF

X7R-CERM-1

CRITICAL

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

C7698

270PF

10%
16V
X7R-CERM
0201-1

10%
10V

0201

47K

5%

1/20W

MF

201

1

2

1

2

C7610

0.1UF

X5R-CERM

R7610

1

10%
25V

2

0402

CRITICAL

C7693

0.1UF

21

10%
25V

X6S-CERM

0201

R7693

1.37K

1%

1/20W

MF

201

5

1

3

2

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

R7686

1

2 1

5%
1/16W
MF-LF

402

P3V3G3H_DRVH

P3V3G3H_DRVL

R7684

0

2 1

5%
1/16W
MF-LF

402

21

R7692

3.83K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

U7610

SN74AUP1T97

SON

4

6

1

R7611

47K

5%
1/20W
MF
201

2

BOM_COST_GROUP=PLATFORM POWER

CRITICAL

Q7680

CSD58873Q3D

3

TG

4

TGR

5

BG

DIDT=TRUE

GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

62

Q3D

1

VIN

1.0UH-20%-14A-0.0107OHM

6

80

VSW

P3V3G3H_VSW

7
8

NOSTUFF

2.2

5%
1/10W
MF-LF

603

1

2

PGND

9

376S1038

R7694

P3V3G3H_SNUBR

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

NOSTUFF

10%
50V

CERM

402

1

2

DIDT=TRUE

C7694

0.001UF

P3V3G3H_CS2_L_P

P3V3G3H_CS2_L_N

65

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

PMU_PVDDMAIN_EN P5VXX_EN

IN

47K

5%

1/20W

MF

201

1

2

R7661

VR - 5V, 3V3

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

L7690

2 1

PIMB062D-SM

152S00269

NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1

2

XW7690

SM

1

R7660

3.3K

1/20W

5%
MF

201

21

2

XW7691

SM

1

PLACE_NEAR=L7690.1:3MM

PLACE_NEAR=L7690.2:3MM

XW7695

SM

P3V3G3H_VFB2_R

R7691

10

5%

1/20W

MF

201

P3V3G3H_VFB2_R2

R7697

3.09K

1%

1/20W

MF

201

P3V3G3H_VFB2_RR

CRITICAL

R7698

105K

0.1%

1/20W

MF

0201-1

CRITICAL

R7699

47K

0.1%

1/20W

MF

0201

1

C7664

1000PF

10%
16V

2

X7R-1
0201

SYNC_DATE=03/01/2017

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

76 OF 145

SHEET

62 OF 85

C

PLACE_NEAR=C7695.1:6.6MM

2

1

1

2

1

2

1

2

1

2

62

B

A

SIZE

D

8

67

35 4

2

1

D

C

75

B

75

75

Vout = 0.9V
Iout Max = 1.4A
F = 3MHz

A

Vout = 1.8V
Iout Max = 1.3A
F = 3MHz

PP1V8_SSD

75

Note : Design based on Calpe ERS - D2449-A0-110-00_0v3.pdf (Radar# 24696002)
System Block Diagram - T290 Power System Architecture . v9
Optimize componentS for individual projects based on EDP(A)

PP3V3_G3H_PMU_VDDMAIN

48 76

CRITICAL

1

C7801

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7810

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B0

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B9

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.D10::5mm

CRITICAL

1

C78BA

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7802

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7809

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B1

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B8

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.K14::5mm

CRITICAL

1

C78BB

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7803

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7808

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B2

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B7

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.P5::5mm

CRITICAL

1

C78BC

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7804

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7807

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B3

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL CRITICAL

1

C78B6

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.P9::5mm

CRITICAL

1

C78BD

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7805

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7806

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B4

1UF

20%

6.3V

2

X6S-CERM
0201

1

C78B5

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78BG

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C78BE

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78BF

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78AE

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78AF

10UF

20%

6.3V

2

CER-X6S
0402

1

C78BH

0.1UF

10%

6.3V

2

X6S
0201

Note : All Bucks are default Local Sense

Buck 0,2,7,9 and 10 need to have option for Remote Sense for Future Use.

Vout = 1V (0.7V in LPM)
Iout Max = 1.1A
F = 3MHz

PPVCC_PRIM_CORE

Vout = 1V

CRITICAL

1

C7865

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7862

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7866

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7861

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7867

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7860

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

CRITICAL

1

C7858

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7868

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7889

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

CRITICAL

1

C7857

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7869

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7890

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7864

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7870

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7871

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7863

20UF

20%

2.5V

2

X6S-CERM
0402

Iout Max = 3.05A
F = 3MHz

PP1V_PRIM

PP0V9_SSD

CRITICAL

1

C78A0

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7872

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7878

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C78A2

20UF

20%

2.5V 2.5V

2

X6S-CERM
0402

CRITICAL

1

C7891

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C78A1

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

1

2

1

2

1

2

1

2

CRITICAL

C7873

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C7879

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL CRITICAL

C78A3

20UF

20%
X6S-CERM

0402

CRITICAL

C7820

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C7894

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

1

C7874

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7880

20UF

20%

2.5V

2

X6S-CERM
0402

1

C7897

20UF

20%

2.5V

2

X6S-CERM
0402

1

C7882

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7895

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7875

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7881

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7859

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICALCRITICAL

1

C7883

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7886

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7876

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7898

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7832

20UF

20%

2.5V

2

X6S-CERM X6S-CERM
0402

CRITICAL

1

C7884

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7896

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7887

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7877

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7899

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7831

20UF

20%

2.5V

2

0402

CRITICAL

1

C7885

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7892

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7888

20UF

20%

2.5V

2

X6S-CERM
0402

678

65

IN

CRITICALCRITICAL

1

C78BJ

100PF

5%
25V

2

C0G
0201

0.47UH-20%-4.8A-0.034OHM

CRITICAL

0.47UH-20%-4.8A-0.034OHM

CRITICAL

PLACE_NEAR=L7819.1:5MM

PLACE_NEAR=U7800.N15:5MM

CRITICAL

CRITICAL

PLACE_NEAR=L7822.1:5MM

CRITICAL

PLACE_NEAR=L7823.1:5MM

PLACE_NEAR=U7800.N15:10MM

CRITICAL

CRITICAL

1

C7893

20UF

20%

2.5V

2

X6S-CERM
0402

PLACE_NEAR=L7824.1:5MM

PMU_VDD_HI
PP1V8_SLPS2R_PMUVDDGPIO

63

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0800

VOLTAGE=1.8V

CRITICAL

1

C78BK

100PF

5%
25V

2

C0G
0201

L7819

0806-COMBO

L7820

0806-COMBO

R7819
R7821

0201 MF 1/20W

5%

0806-COMBO

0.47UH-20%-4.8A-0.034OHM

L7821
L7822

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7820

L7823

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7822
R7824

L7824

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

Resistor Divider from PBUS
VDD_HI < 3.1V

1

10%

6.3V

2

X6S

0201

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

02011/20W5% MF

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MF5% 0201

0201MF1/20W5%

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

0
0

NOSTUFF

0

0
0

C7800

0.1UF

CRITICAL

21

PVCCPCOREPRIM_SW0

21

PVCCPCOREPRIM_SW1

NOSTUFF

21

PVCCPCOREPRIM_FB_P

5% 1/20W MF 0201

21

PVCCPCOREPRIM_FB_N

NOSTUFF

21

P1VPRIM_SW0

21

P1VPRIM_SW1

21

P1VPRIM_FB

PP1V_PRIM

75

21

P0V9SSD_SW0

21

P0V9SSD_FB_P

1/20W

21

P0V9SSD_FB_N

21

P1V8SSD_SW0

R7823

0

21

P1V8SSD_FB

0201MF1/20W5%

NC
NC

NC

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

P5

D10

P9

K14

K13

J11

C1
C2
C3

G1
G2
G3

R1
R2

L1
L2
L3

B16
B17
B18

A7
B7

A11
B11

F17
F18

K16
K17
K18

P16
P17
P18

T1
T2

R7

T4

E17
E18

G17
G18

F15

G15

L16
L17
L18

J16
J17
J18

L14

P12
R12
T12
U12
V12

N16
N17
N18

P14

N14

R16
R17
R18

R14

VDD_MAIN_E
VDD_MAIN_N
VDD_MAIN_S
VDD_MAIN_W

VDD_HI

VDD_GPIO

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK16

VDD_BUCK2

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

VDD_BUCK7

VDD_BUCK8

VDD_BUCK910

BUCK6_LX0

BUCK6_IN

BUCK6_FB

BUCK7_LX0

BUCK7_LX1

BUCK7_RTP

BUCK7_RTN

BUCK8_LX0

BUCK8_LX1

BUCK8_FB

BUCK8_IN

BUCK9_LX0

BUCK9_RTP

BUCK9_RTN

BUCK10_LX0

BUCK10_FB

U7800

CALPE-PMU

BGA

SYM 2 OF 4

CRITICAL
OMIT_TABLE

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

BUCK3_LX0

BUCK3_FB

BUCK3_IN

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

BUCK4_IN

BUCK5_LX0

BUCK5_LX1

BUCK5_FB

BUCK3_SW1
BUCK3_SW2
BUCK3_SW3
BUCK3_SW4
BUCK3_SW5

BUCK4_SW1

BUCK6_SW1

BUCK8_SW1
BUCK8_SW2

82

B1
B2
B3

D1
D2
D3

F1
F2
F3

H1
H2
H3

G5

P1
P2

R4

K1
K2
K3

M1
M2
M3

L5

C16
C17
C18

D14

R9
T10
T9
U10
U9
V10
V9

A8
B8

A6
B6

D7

P7

A10
B10

A12
B12

D12

T8
T11
V11
V8
R8

P6

R6

P13
R13

PVDDCPUAWAKE_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUAWAKE_SW1

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUAWAKE_SW2

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUAWAKE_SW3

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUAWAKE_FB

PVDDCPUSRAMAWAKE_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUSRAMAWAKE_FB

P0V8SLPDDR_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P0V8SLPDDR_SW1

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P0V8SLPDDR_FB

82

P1V8SLPS2R_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P1V8SLPS2R_FB

PP1V8_SLPS2R

P1V1SLPS2R_SW0

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
SWITCH_NODE=TRUE
DIDT=TRUE

P1V1SLPS2R_SW1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P1V1SLPS2R_FB

P0V9SLPDDR_SW0

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P0V9SLPDDR_SW1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P0V9SLPDDR_FB

3 245

L7806

1UH-20%-3.8A-0.055OHM

CRITICAL

21

2016-COMBO

L7807

0.22UH-20%-6.7A-0.023OHM

CRITICAL

21

PINA20121T-SM

L7808

0.22UH-20%-6.7A-0.023OHM

CRITICAL

21

PINA20121T-SM

L7809

0.22UH-20%-6.7A-0.023OHM

CRITICAL

21

PINA20121T-SM

R7806
R7807

NOSTUFF

L7810

1.0UH-20%-2.6A-0.095OHM

0805-COMBO

R7811

0

L7811

1UH-20%-4.7A-0.04OHM

2520

L7812

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7812

0

L7813

1UH-20%-3.8A-0.055OHM

2016-COMBO

R7813

0

PLACE_NEAR=L7813.2:5MM

75

L7814

1UH-20%-3.8A-0.055OHM

2016-COMBO

L7815

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7814

0

L7816

2016-COMBO

1UH-20%-3.8A-0.055OHM

L7817

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7816

0

NOSTUFF

PP1V8_AWAKE
PP1V8_SLPS2R_PMUVDDGPIO
PP1V8_S5
PP1V8_S3
TP_PMU_BUCK3SW5

TP_PP1V1_PMU_BUCK4SW1
TP_PMU_BUCK6SW1
PP1V_S0SW

PP1V_S3

0

0

PLACE_NEAR=L7810.2:5MM

21

NOSTUFF

PLACE_NEAR=L7812.2:5MM

21

5% MF 02011/20W

21

5% 1/20W MF 0201

PLACE_NEAR=L7815.2:5MM

21

1/20W5% MF

PLACE_NEAR=L7816.2:5MM

21

5% MF 02011/20W

PLACE_NEAR=L7806.2:5MM

21

5% 1/20W

21

CRITICAL

21

MF5% 02011/20W

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

C7821

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7812

20UF

20%

2.5V

X6S-CERM

0402

MF 0201

PVDDCPUAWAKE_FB_XW

1/20W5%

MF 0201

CRITICAL

C7829

10UF

20%

6.3V

CER-X6S

0402

CRITICAL

C7833

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7814

20UF

20%

2.5V

X6S-CERM

0402 0402

CRITICAL

C7839

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7845

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7846

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7816

20UF

0201

CRITICAL

20%

2.5V

X6S-CERM

0402

C7852

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7819

20UF

20%

2.5V

X6S-CERM

0402

Supplied Current

75 82

63

75

75

75

75

0.3A

0.3A

1.0A

1.0A

0.3A

BOM_COST_GROUP=T290

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CRITICAL

C7822

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7811

20UF

20%

2.5V

X6S-CERM

0402

SM

CRITICAL

C7830

10UF

20%

6.3V

CER-X6S

0402

CRITICAL

C7834

20%

2.5V

X6S-CERM

0402

CRITICAL

C7815

20UF

20%

2.5V

X6S-CERM

CRITICAL

C7840

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C2

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7847

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7817

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7853

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C1

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

1

2

CRITICAL

1

2

XW7807

21

1

2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

1

2

CRITICAL

1

2

1

2

CRITICAL

1

2

1

2

CRITICAL

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

C7855

C7823

20UF

X6S-CERM

C7827

20UF

X6S-CERM

C7835

20UF20UF

X6S-CERM

C78C3

20UF

X6S-CERM

C7841

20UF

X6S-CERM

C7848

20UF

X6S-CERM

C7854

20UF 20UF

X6S-CERM

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C7824

20UF

20%

2.5V

X6S-CERM

0402

C7828

20UF

20%

2.5V

X6S-CERM

0402

C7836

20UF

20%

2.5V

X6S-CERM

0402

C78C4

20UF

20%

2.5V

X6S-CERM

0402

C7842

20UF

20%

2.5V

X6S-CERM

0402

C7849

20UF

20%

2.5V

X6S-CERM

0402

20%

2.5V

X6S-CERM

0402

PMIC BUCKS AND SWs

Vout = 0.625V - 1.06V
Iout Max = 12.5A
F = 2MHz & 4MHz

PPVDDCPU_AWAKE

CRITICAL

1

2

1

2

C7825

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7813

20UF

20%

2.5V

X6S-CERM

0402

1

2

1

2

CRITICAL

C7826

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C0

20UF

20%

2.5V

X6S-CERM

0402

Vout = 0.8V - 1.06V
Iout Max = 0.923A
F = 3MHz

PPVDDCPUSRAM_AWAKE

Vout = 0.82V
Iout Max = 3.93A
F = 3MHz

PP0V82_SLPDDR

CRITICAL

1

2

1

2

C7837

20UF

20%

2.5V

X6S-CERM

0402

PP1V8_SLPS2R

CRITICAL

1

2

C7843

20UF

20%

2.5V

X6S-CERM

0402

1

2

1

2

CRITICAL

C7838

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7844

20UF

20%

2.5V

X6S-CERM

0402

Vout = 1.8V
Iout Max = 1.5A
F = 3MHz

Vout = 1.1V
Iout Max = 1.4A
F = 3MHz

PP1V1_SLPS2R

CRITICAL

1

2

C7850

20UF

20%

2.5V

X6S-CERM

0402

1

2

CRITICAL

C7851

20UF

20%

2.5V

X6S-CERM

0402

Vout = 0.9V
Iout Max = 2.64A
F = 3MHz

PP0V9_SLPDDR

CRITICAL

1

2

C7856

20UF

20%

2.5V

X6S-CERM

0402

1

2

CRITICAL

C7818

20UF

20%

2.5V

X6S-CERM

0402

Apple Inc.

1

1

2

1

2

1

2

1

2

1

2

1

2

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

75

75

75

75 82

75

75

SYNC_DATE=03/16/2017

SIZE

051-04039

D

2.0.0

78 OF 145

63 OF 85

D

C

B

A

8

67

35 4

2

1

D

PP3V3_G3H

76

PP1V1_SLPS2R

75

PP3V3_G3H

76

PP1V8_SLPS2R

75

CRITICAL

1

C7903

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C7904

0.1UF

10%

6.3V

2

X6S
0201

678

3 245

1

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

D

CRITICAL

1

C7909

0.1UF

10%

6.3V

2

X6S
0201

N11
N12

V3P3

LDO1_IN
LDO2_IN

SYM 1 OF 4

LDO_CORE

LDO0
LDO1LDO0_IN
LDO2
LDO3

HIO_SW_EN

HIO_SW

L8

V15
U15V14
U17U14
P8U16

N6

T13
U13
V13

LDO_CORE

PMU_LDO3_OUT

PD_HIO_PWR_EN

NC
NC
NC

PP0V8_SLPS2R
PP3V_G3H
PP1V2_AWAKE

1

C7914

2.2UF

10%

10V

2

X6S-CERM
0402

CRITICAL

1

C7906

2.2UF

10%

10V

2

X6S-CERM
0402

CRITICAL

1

C7905

2.2UF

10%

10V

2

X6S-CERM
0402

CRITICAL

75

Max Current = 150mA
Max Current = 10mA

75

Max Current = 300mA

75

C

B

A

PLACE_NEAR=U7800.V5:1MM

XW7903

SHORT-12L-0.1MM-SM

21

GND_PMU_VSS_RTC

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PLACE_NEAR=U7800.E4:1MM

XW7902

SHORT-12L-0.1MM-SM

21

GND_PMU_AVSS_B0

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PLACE_NEAR=U7800.J15:1MM

XW7901

SHORT-12L-0.1MM-SM

21

GND_PMU_AVSS_B8

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PP3V3_G3H_RTC

76

VIN RTC implementation
may change between
Desktops and Portables

A1
E1
E2

VSS_BUCK0

E3
A2
A3
J1
J2

VSS_BUCK02

J3
B5
A5

VSS_BUCK4
A13
B13

T16
T17
T18

D16
D17
D18

H16
H17
H18
M16
M17
M18

R11

E11
U11

V16

C13
C10

H15
J15
M15
T14

VSS_BUCK5

U1
U2

VSS_BUCK6

VSS_BUCK10

N1
N2

VSS_BUCK21

N3

VSS_BUCK37

B9
A9

VSS_BUCK45

VSS_BUCK78

VSS_BUCK89

V5

VSS_RTC

M9

AVSS_C
AVSS_S

PVSS_N
PVSS_S

T5

PVSS_SE
PVSS_SW

E4

VSSA_BUCK0

R5

VSSA_BUCK1_6/AVSS_SE

M4

VSSA_BUCK2
VSSA_BUCK3
VSSA_BUCK4_5
VSSA_BUCK7
VSSA_BUCK8/AVSS_W
VSSA_BUCK9
VSSA_BUCK10/AVSS_SW

1

2

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

SYM 4 OF 4

CRITICAL

C7907

10UF

20%

6.3V

CER-X6S
0402

VSS

CRITICAL

1

C7908

10UF

20%

6.3V

2

CER-X6S
0402

A4
A17
A18
B4
B15
C4
C5
C6
C7
C8
C9
C12
C15
D4
E15
E16
F4
F12
F16
G4
G12
G16
H4
H12
J4
J12
K4
K15
L15
N4
N15
P3
P4
P11
P15
R3
R15
T3
T15
U18
U3
U4
U5
U8
V1
V2
V17
V18

CRITICAL

1

C7912

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7913

1UF

20%

6.3V

2

X6S-CERM
0201

T6
U6

H5
D11
P10
M14

82 79 65

VIN_RTC

VIN_RTC_E
VIN_RTC_N
VIN_RTC_S
VIN_RTC_W

IN

1

C7920

1500PF

10%

10V

2

X7R
0201

LDO_RTC

VOUT_RTC

VPUMP

V3P3_SW1
V3P3_SW2

PP3V3_G3H

76

1

C7921

0.1UF

10%

6.3V

2

X6S
0201

P1V1SLPDDR_RAMP
P1V1_SLPDDR_SOCFET_EN

V7

T7
U7

R10

N13
N10

LDO_RTC

PMU_VPUMP

SLG5AP1668V

CAP

ON S

1

2

1

VDD

U7901

TDFN8

GND

8

NOSTUFF

R7900

100K

5%
1/20W
MF
201

CRITICAL

1

C7902

0.01UF

10%

10V

2

X5R-CERM
0201

1.1V SLPDDR SWITCH

37

D

PP1V1_SLPS2R

52

Part : SLG5AP1668V
R(ON) : 7.8 mohm (Typical) , 9.6 mohm (max)
Current: 5.3A Max

CRITICAL

1

C7901

0.1UF

10%

6.3V

2

X6S
0201

PP1V1_SLPDDR

CRITICAL

1

C7911

0.1UF

10%

6.3V

2

X6S
0201

75

75

PP3V3_G3H

PP3V3_AWAKE
PP3V3_S5

CRITICAL

1

C7910

0.1UF

10%

6.3V

2

X6S
0201

BOM_COST_GROUP=T290

76

Max Current = 300mA

75

Max Current = 500mA

75

PAGE TITLE

PMIC LDOs

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/16/2017SYNC_MASTER=X589_BIGSUR

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

79 OF 145

SHEET

64 OF 85

C

B

A

SIZE

D

8

67

35 4

2

1

D

C

B

35

16

79 34 27

45

45

OUT

OUT

OUT

IN

BI

PMU_CLK32K_SOC
PMU_CLK32K_PCH

SOC_FORCE_DFU

I2C_PWR_SCL
I2C_PWR_SDA

Caution : AMUX programmed with Gain 1
should not have inputs greater than 1.5V

PP1V_S3

1

R8012

R8010

33

5%

1/20W

MF

201

2.2K

1

R8011

33

5%
1/20W
MF

2

201

2

82 79 65 34 28

21

1/20W 5% MF201

Use SOC's Internal Pull Up

R8080
R8081

0

21

1/20W

21

CRITICAL

Y8001

75

32.768KHZ-20PPM-12.5PF

1

C8002

27PF

5%
25V

2

C0G
0201

1.60X1.00-SM

21

35

79 34

57 27

42 6

77

65 43 35

82 79 66 35 15

33

77

74 65 35 34

35

0201 5% MF

35

35

65 19

15

R8013

0

5%

1/20W

MF

0201

1

C8003

27PF

5%
25V

2

C0G
0201

678

IN
IN
IN
IN
IN

OUT

IN

OUT

OUT
OUT

OUT

OUT

5% MF1/20W00201

IN
BI
OUT
OUT

49

49

49

49

49

49

49

49

21

NOSTUFF

SOC_WDOG
SOC_SOCHOT_L
UPC_PMU_RESET
PM_THRMTRIP_L
NC_GPU_THRMTRIP
PMU_COLD_RESET_L

PM_SLP_S0_L
PMU_ACTIVE_READY
PMU_CLK32K_SOC_R

PMU_CLK32K_PCH_R
PMU_CLK32K_WLANBT_R
NC_PMU_CLK32K_GNSS_R
TP_PMU_CLK32K

PMU_SYS_ALIVE
PMU_FORCE_DFU

PMU_INT_L
I2C_PMU_SCL_R

I2C_PMU_SDA_R

SPMI_CLK
SPMI_DATA
ALL_SYS_PWRGD
PCH_PWRBTN_L

PMU_VDDMAIN_ISENSE
NC_PMU_AMUX_A1
PMU_WLANBT_ISENSE
NC_PMU_AMUX_A3
PMU_LCDBKLT_ISENSE
PMU_CPU_VSENSE
PMU_NAND_VSENSE
PMU_VCCIO_VSENSE
TP_PMU_AMUX_AY

TP_PMU_AMUX_B0
TP_PMU_AMUX_B1
TP_PMU_AMUX_B2
TP_PMU_AMUX_B3
TP_PMU_AMUX_B4
TP_PMU_AMUX_B5
TP_PMU_AMUX_B6
TP_PMU_AMUX_B7
TP_PMU_AMUX_BY

1

R8018

1M

5%
1/20W
MF
201

2

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

PMU_XTAL1PMU_XTAL1_R
PMU_XTAL2

65 6

IN

PMU_VDD_MAX

CRITICAL

1

C8004

0.1UF

10%

6.3V

2

X6S
0201

CPU_CATERR_L

NC
NC

F5

RESET_IN1

E5

RESET_IN2

K5

RESET_IN3

K6

RESET_IN4

N5

RESET_IN5

L13

RESET*

M12

SYS_SLEEP*

J5

ACTIVE_RDY

H6

CLKOUT0_32K

H7

CLKOUT1_32K

J7

CLKOUT2_32K

K7

CLKOUT3_32K

K8

CLKOUT4_32K

L11

SYS_ALIVE

D6

FORCE_DFU

L9

IRQ*

M11

SCL

L10

SDA

M8

SCLK

M7

SDATA

K11

SYS_ACTIVE

C11

SYS_BTN

A16

AMUX_A0

A15

AMUX_A1

A14

AMUX_A2

B14

AMUX_A3

C14

AMUX_A4

D15

AMUX_A5

E14

AMUX_A6

F14

AMUX_A7

J14

AMUX_AY

D13

AMUX_B0

E13

AMUX_B1

E12

AMUX_B2

F13

AMUX_B3

G13

AMUX_B4

G14

AMUX_B5

H14

AMUX_B6

H13

AMUX_B7

J13

AMUX_BY

N9

LS_BID1

M10

LS_BID2

V3

XTAL1

V4

XTAL2

L6

SYS_ERR*

N8

VDD_MAX

E6

VDD_OTP

(IPD)

(IPD)

(IPD)

(IPU)
(IPU)

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

SYM 3 OF 4

(IPU)
(IPU)

IREF

VREF

VDROOP

VDROOP_DET

CHG_CBC_ON

NCHG_INT

CHG_POK

VPWR_EN

LDO1_POK

PFN

VIN_BBAT

BUTTON1
BUTTON2

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25

L12

K12

L7

M5

D9
J6
L4

D5

M13

D8

V6

N7
M6

E9
E8
E7
F6
F7
F8
F9
F10
G10
G9
G8
G7
G6
H8
H9
J9
J8
K9
K10
J10
H10
H11
G11
F11
E10

PMU_IREF

PMU_VREF

CRITICAL

1

C8001

0.1UF

10%

6.3V

2

X6S
0201

PMU_DROOP_L

SOC_VDDCPU_SENSE
CHGR_CBC_ON

CHGR_INT_L
GND

PMU_PVDDMAIN_EN
PCH_RTC_RESET_L

NC

GND

PMU_ONOFF_L
PMU_RSLOC_RST_L

P3V3MAIN_PGOOD
NC_P3V3G3W_EN
NC_P3V3G3W_PGOOD
P5VG3S_EN
P5VG3S_PGOOD
P3V3G3S_EN
P1V8G3S_EN
CPUVR_PGOOD
PVCCIO_EN
PVCCIO_PGOOD
PVDDQ_EN
PVDDQ_PGOOD
AUD_PWR_EN
WLAN_PWR_EN
BT_PWR_EN
SE_PWR_EN
SENSOR_PWR_EN
PVCCPLLOC_EN
P2V7NAND_PGOOD
P2V7NAND_EN
NAND_DISCHARGE_EN
NAND_RESET_L
UVP_DIS_L
TBT_PWR_EN
P1V1_SLPDDR_SOCFET_EN

1

R8001

200K

1%
1/20W
MF
201

2

OUT

IN

IN
IN
IN

OUT

OUT

76

IN
IN

3 245

65 34

38

58

58

77

62

16

To be Grounded on Portables Only, RC on Coin Cell on Desktops

82 79 65 57 52

82 79 65 57 55

62

IN

77

77

IN

62

OUT

62

IN

59

66

66

44

67

77

77

77

77

77

67 65

82 79 67 65

82 79 66 65

79 66

79 52

33 32

33 32

67 65

67 65

67 65

82 79 64

PVCCPLLOC_EN

IN

OUT
OUT

IN

OUT

IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT
OUT
OUT

67 65

NOSTUFF

TBT_PWR_EN

IN

R8065

47K

5%

1/20W

MF

201

1

2

67 65

P3V3G3S_EN

IN

R8060

47K

5%

1/20W

MF

201

1

1

2

R8061

47K

5%

1/20W

MF

201

D

C

B

1

2

A

PP3V3_G3H_RTC

PP1V8_AWAKE
PP1V8_S5

PP1V8_SLPS2R

R8002
R8003

R8005
R8006
R8015
R8014
R8017

10K
10K

1K

10K
10K
10K

51

76

75

75

75

21

21

1/20W 5%201

21

21

21

1/20W

21

21

PMU_COLD_RESET_L

201 5%1/20W

201 MF1/20W 5%

201 5% MF

201 5%1/20W MF

MF

PMU_SYS_ALIVE

MF

ALL_SYS_PWRGD
PMU_DROOP_L

MF

5%2011/20W

PMU_ONOFF_L
PMU_RSLOC_RST_L
CPU_CATERR_L

5%201 1/20W MF

82 79 67 65

82 79 65 34 28

82 79 66 65

IN

PVDDQ_EN

NOSTUFF

R8062

PPBUS_G3H

76

0.1%

1/20W

TK

0201

0.1%

1/20W

MF

0201

1

2

PMU_VDD_HI

1

2

OUT

63

BOM_COST_GROUP=T290

SYNC_MASTER=X589_BIGSUR SYNC_DATE=03/16/2017

PAGE TITLE

PMIC GPIOs & Control

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R8050

65 43 35

74 65 35 34

65 19

65 34

82 79 65 57 52

82 79 65 57 55

65 6

NOSTUFF

C8051

220PF

0201

2%
50V
C0G

1

2

887K

R8051

357K

PMU_ACTIVE_READY

IN

NOSTUFF

1

47K

5%

1/20W

MF

201

2

P1V8G3S_EN

IN

R8063

47K

5%

1/20W

MF

201

NOSTUFF

1

R8064

47K

1/20W

2

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

80 OF 145

SHEET

65 OF 85

5%
MF

201

1

2

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

76

82 79 65

BYPASS=U8100.6::1mm

CRITICAL

10%
25V

0201

1

2

C8115

0.1UF

X6S-CERM

PP5V_G3S

MEMVTT_EN

66

PVDDQ_EN

IN

1

R8111

3.57K

1%
1/20W
MF
201

2

PLACE_NEAR=U8100.19:3mm

P1V1REG_VREF_R

1

R8117

21K

0.1%
1/20W
MF
0201

2

CRITICAL

PLACE_NEAR=U8100.8:5mm

1

R8112

48.7K

0.1%
1/20W
MF
0201

2

CRITICAL

R8103

2.2

21

5%
1/16W
MF-LF

402

CRITICAL

C8103

X6S-CERM

R8155

0

21

MF1/20W5%

0201

R8104

0

1/20W 02015%

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600

1

C8116

0.01UF

10%

10V

2

X7R-CERM
0201

P1V1REG_AGND

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

VOLTAGE=0V

21

MF

BYPASS=U8100.8::1mm

CRITICAL

PP1V2_S3

66 76

2.2UF

20%
25V

0402

VOLTAGE=5V

PP5V_G3S_P1V1REG

BYPASS=U8100.12::1mm

1

2

PD_P1V2_S3_EN
PVDDQ_EN_R

P1V2REG_VREF

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600

PVCCEDRAM_REFIN
P1V2REG_MODE

P1V2REG_TRIP

PLACE_NEAR=U8100.19:3mm

1

R8113

200K

1%
1/20W
MF
201

2

PLACE_NEAR=U8100.18:3mm

CRITICAL

BYPASS=U8100.2::1mm

C8102

17
16

19
18

1

R8114

40.2K

1%
1/20W
MF
201

2

10UF

20%

6.3V

CER-X6S

0402

V5IN

S3
S5

6

VREF

8

REFIN

MODE
TRIP

1

2

VLDOIN

U8100

TPS51916

CRITICAL

PGND GND

7

10

CRITICAL

BYPASS=U8100.2::1mm

1

C8108

10UF

20%

6.3V

2

CER-X6S
0402

2

VBST
DRVH

QFN

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

VTT THRM

GND PAD

4

21

PLACE_NEAR=U8100.21:1mm

1512
14
13

SW

11
20
9
3

VTT

1

5

2

XW8100

SM

1

R8130

2.2

1/20W

P1V2_VBST

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
DIDT=TRUE

PPVTT_VTTREF

VOLTAGE=0.6V

P1V2_BOOT_RC

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
DIDT=TRUE

1

5%
MF

201

2

P1V2_DRVH

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

DIDT=TRUE

P1V2_SW

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P1V2_DRVL

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
GATE_NODE=TRUE
DIDT=TRUE

PVDDQ_PGOOD

PP0V6_S0_DDRVTT
PVTT_VTTSNS

CRITICAL

1

C8140

0.22UF

10%

16V

2

CERM
402

R8157

1/20W MF 02015%

CRITICAL

1

C8131

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C8130

0.1UF

10%

25V

2

X6S-CERM
0201

R8133

R8132

79 66 65

0

1

5%
1/16W
MF-LF

402

1

5%
1/16W
MF-LF

402

21

P1V2_DRVH_R

21

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
GATE_NODE=TRUEGATE_NODE=TRUE
DIDT=TRUE

21

P1V2_DRVL_R

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
GATE_NODE=TRUE
DIDT=TRUE

PVTT_VTTSNS_R

CRITICAL

1

C8132

15UF

20%
2V

2

X6S
0402

VT 0.6V LDO

VDDQ 1.2V S3 VR

PPBUS_HS_CPU

76

CRITICAL

Q8100

CSD58873Q3D

Q3D

1

VIN

3

TG

6

CRITICAL

1

C8133

15UF

20%
2V

2

X6S
0402

XW8105

SM

21

CRITICAL

1

C8134

15UF

20%
2V

2

X6S
0402

4

TGR

5

BG

VSW

PGND

9

P1V2_SNS

CRITICAL

1

C8135

15UF

20%
2V

2

X6S
0402

Vout = 0.6V

0.512A MAX OUTPUT

7
8

P1V2_PHASE

1

2

P1V2_LL_SNUB

1

2

CRITICAL

1

C8136

15UF

20%
2V

2

X6S
0402

CRITICAL

1

C8100

33UF

20%
16V

2

TANT
CASED12-SM

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.1V

R8110

2.2

5%
1/10W
MF-LF
603

C8110

0.001UF

10%

50V

X7R-CERM
0402

NOSTUFF

DIDT=TRUE

NOSTUFF

R8141

10

21

5%

1/20W

IN

MF

201

75

PM_MEMVTT_EN

76

7

CRITICAL

1

C8101

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C8104

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

L8100

0.68UH-20%-14.5A-0.009OHM

21

PILA052D-SM

152S00239

XW8110

SM

P1V2_SNS_R

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600

PP1V_PRIM

C8190

10%

X6S-CERM

0201

5%

1/20W

MF

201

1

2

R8191

100K

25V

1

2

NC

21

PLACE_NEAR=C8107.1:1mm

VCC_A

SN74AUP1T34-COMBO

A

5

NC

6

1

VCC_B

U8190

SON

GND

3

PP1V2_S3

76

42

B

CRITICAL

1

C8105

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

PP1V8_S5

1

C8191

0.1UF0.1UF

10%

25V

2

X6S-CERM
0201

MEMVTT_EN

1

2

K

A

1

2

22 23 66 75

R8192

100K

5%
1/20W
MF
201

CRITICAL

D8100

SOD523

PMEG3010EB/S500

CRITICAL

C8106

330UF

20%

2.5V

TANT
CASE-B2-SM1

CRITICAL

1

C8107

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

PP1V8_S3

75

66

PP1V8_S3

CRITICAL

K

D8101

SOD523

PMEG3010EB/S500

A

Higher voltage rails
must remain above
lower voltage rails

Vout = 1.2V

6.5A MAX OUTPUT
F = 400 KHZ

PP1V2_S3

CRITICAL

1

C8112

10UF

20%

6.3V

2

CER-X6S
0402

1

R8190

100K

5%
1/20W
MF
201

2

PVDDQ_PGOOD

22 23 66 75

66 76

CRITICAL

1

C8113

10UF

20%

6.3V

2

CER-X6S
0402

OUT

D

79 66 65

C

B

A

8

8

65 35 15

82 79

65

CPU_VCCIOSENSE_P

IN

CPU_VCCIOSENSE_N

IN

PLACE_NEAR=R8150.1:1mm

PP3V3_S5

66 75

C8176

0.1UF

CERM-X5R

IN

IN

PM_SLP_S0_L

PVCCIO_EN

10%

6.3V
0201

PP5V_G3S

76

R8150

10

21

CPU_VCCIOSENSE_R

5%

1/20W

MF

201

XW8102

SM

21

CPU_VCCIOSENSE_XW

NO_XNET_CONNECTION=1

1%

1/20W

MF

201

1

2

R8160

4.42K

<Ra> <Ra>

1%

1/20W

MF

201

1

2

R8162

4.99K

<Rb>

5%
50V
C0G

0201

1

2

C8160

10PF

1

VCCIO EN LOGIC

2

U8111

5

6

132

74AUP1T97GM

SOT886

4

PVCCIOS0_EN

R8159

NO_XNET_CONNECTION=1

1

R8151

64.9

1%
1/20W
MF
201

2

PVCCIOS0_FB_R

NO_XNET_CONNECTION=1

1

R8161

4.42K

0.1%
1/20W
MF
0201

2

Vout = 0.5V * (1 + Ra/Rb)

1

R8163

4.99K

0.1%
1/20W
MF
0201

2

<Rb>

1

C8161

10PF

5%
50V

2

C0G
0201

66 75

R8158

3.92K

100K

5%

1/20W

MF

201

2 1

1

NOSTUFF

2

PVCCIOS0_EN_R PVCCIOS0_EN_FILT

1/20W1%201 MF

66

66 65

OUT

C8170

3300PF

21

5.0%
50V

CERM
0603

1

C8163

270PF

5%
50V

2

C0G
0402

PP3V3_S5

C8177

1

C8178

330PF

5%
25V

2

C0G
0201

R8165

0201 5%MF

MIN_LINE_WIDTH=0.0900

C8162

2.2UF

20%
25V

X6S-CERM

0402

1

2

MIN_NECK_WIDTH=0.0500

VOLTAGE=5V

PVCCIOS0_AGND

PVCCIOS0_EN_FILT_BUF_R
PVCCIOS0_FB
PVCCIOS0_SREF
PVCCIOS0_VO
PVCCOIOS0_OCSET
PVCCIO_PGOOD
PVCCIOS0_RTN

PVCCIOS0_FSEL

1

R8164

100K

1%
1/20W
MF
201

2

PVCCIOS0_AGND

66

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500

VOLTAGE=0V

1

0.1UF

10%

6.3V

CERM-X5R

0201

0

2 1

2

1

NOSTUFF

1/20W

U8112

52

74AUP2G17GM/S500-COMBO-1

SOT886

6

C8179

100PF

R8144

1/20W

3 12

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

PLACE_NEAR=U8110.1:1mm

XW8101

21

0201C0G25V5%

1

2.2

5%
MF

201

2

66

13

U8110

ISL95870HRUZ

UTQFN

-TR5720

353S01077

CRITICAL

1

SM

21

1

R8147

2

14

PVCCVCC

PGNDGND

16

2.2

5%
1/20W
MF
201

PP5V_G3S_VCCIOPVCCPP5V_G3S_VCCIOVCC

BOOT

UGATE

PHASE

LGATE

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0500

VOLTAGE=5V

1

C8143

10UF

20%
10V

2

X5R-CERM
0402-7

PVCCIO_VBST

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE

PVCCIO_DRVH

11

10

15

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE

PVCCIO_LL

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE

PVCCIO_DRVL

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
GATE_NODE=TRUE

(PCHVCCIOS0_OCSET)
(PCHVCCIOS0_VO)

52

3

0.95V VCCIO

PVCCIO_BOOT_RC

1

R8145

2.2

5%
1/20W
MF
201

2

U8112

74AUP2G17GM/S500-COMBO-1

SOT886

4

PVCCIOS0_EN_FILT_BUF

1

R8166

47K

5%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

1

C8144

0.1UF

10%
25V

2

X6S-CERM
0201

R8146

5%

1/20W

MF

201

R8148

5%

1/20W

MF

201

PPBUS_HS_CPU

76

CRITICAL

1

C8152

33UF

20%
16V

2

TANT
CASED12-SM

1

C8151

2.2UF

20%
25V

2

X6S-CERM
0402

1

C8150

2.2UF

20%
25V

2

X6S-CERM
0402

Q8102

CSD58889Q3D

Q3D

1

VIN

1

21

PVCCIO_DRVH_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

1

21

PVCCIO_DRVL_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE

3

TG

6

4

TGR

5

BG

VSW

PGND

9

7
8

PVCCIO_PHASE

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

SWITCH_NODE=TRUE

1

R8116

2.2

5%
1/10W
MF-LF
603

2

PVCCIO_LL_SNUB

NOSTUFF

1

C8120

0.001UF

10%
50V

2

X7R-CERM
0402

0.68UH-20%-6.7A-0.0194OHM

NOSTUFF

SWITCH_NODE=TRUE
DIDT=TRUE

152S00260

L8102

21

81

PIMS042T-SM-COMBO

NO_XNET_CONNECTION=1

1

R8142

4.42K

1%
1/20W
MF
201

2

PP0V95_S0_CPUVCCIO_REG_R

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0.95V

PVCCIOS0_CS_P

PVCCIOS0_CS_N

NO_XNET_CONNECTION=1

CRITICAL

R8102

0.003

1%

1/3W

MF

0306

21
43

Vout = 0.95V
3A MAX OUTPUT
F = 600kHz

PPVCCIO_S0_CPU

CRITICAL

1

C8174

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C8175

20UF

20%

2.5V

2

X6S-CERM
0402

B

76

C8142

470PF

21

NO_XNET_CONNECTION=1

1

R8143

4.42K

1%
1/20W
MF
201

2

SYNC_MASTER=X589_CPU_CNL_Y

PAGE TITLE

POWER - VDDQ, VCCIO

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

66 65

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/08/2017

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

81 OF 145

SHEET

66 OF 85

A

SIZE

D

R8167

0

2 1

5%

1/20W

MF

0201

PVCCIOS0_EN_FILT_BUF_R

PP1V8_S5

75

66

BOM_COST_GROUP=PLATFORM POWER

R8152

100K

5%

1/20W

MF

201

1

2

PVCCIO_PGOOD

10%
16V

X5R-X7R-CERM

0201

OUT

8

67

35 4

2

1

1.2V S0SW VCCPLL_OC Switch

678

3 245

1

D

75

C8242

100PF

5%
25V
C0G

0201

PP3V3_S5

65

IN

1

2

BYPASS=U8240::2MM

C8240

0.1UF

10%

6.3V

CERM-X5R

0201

P1V2S0SW_RAMP
PVCCPLLOC_EN

PP1V2_S3

1

1

2

VDD

U8240

BYPASS=U8240::2MM

1

C8241

1.0UF

20%

6.3V

2

X5R
0201-1

76

SLG5AP1635V

CAP

ON

STDFN

CRITICAL

GND

8

Part
Type
R(on)

@ 3.3V
Current

37

D

52

S

PP1V2_S0SW

EDP: 120mA

76

SLG5AP1635V
Load Switch

27.5 mOhm Typ

VCCPLL_OC had turn-on requirement of
11us min and 240us max
from EN to 1.2V

31 mOhm Max

2.5A Max

D

C

C8210

4700PF

10%
10V
X7R
201

3.3V G3 Standby Switch

PP3V3_G3H

PP3V3_G3H

76

BYPASS=U8210::5mm

1

C8211

1

VDD

U8210

0.1UF

10%
10V

2

X5R-CERM
0201

SLG5AP1445V

P3V3G3S_SS

65

1

2

P3V3G3S_EN

IN

CAP

ON S

TDFN8

GND

8

Part
R(on)

@ 3.6V
Current

37

D

52

PP3V3_G3H_RTC
PP3V3_G3S

76

76

C8220

4700PF

10%

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max
4A Max

10V
X7R
201

76

82 79 65

1

2

IN

P1V8G3S_SS
P1V8G3S_EN

1.8V G3 Standby Switch

BYPASS=U8220::5mm

1

C8221

1

VDD

U8220

SLG5AP1445V

CAP

ON S

TDFN8

GND

8

Part SLG5AP1445V
R(on)

@ 3.6V
Current

37

D

52

7.8 mOhm Typ

8.5 mOhm Max
4A Max

0.1UF

10%
10V

2

X5R-CERM
0201

PP1V8_SLPS2R
PP1V8_G3S

C

75

76

B

C8225

4700PF

10%
10V
X7R
201

EG: Check load current & shrink switch?

3.3V Sensors Switch

PP3V3_G3H

76

BYPASS=U8225::5mm

1

C8226

1

VDD

U8225

SLG5AP1445V

P3V3SEN_SS

65

IN

1

2

SENSOR_PWR_EN

CAP

ON S

TDFN8

GND

8

Part
R(on)

@ 3.6V
Current 4A Max

37

D

52

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_G3H
PP3V3_G3SSW_SNS

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max

76

76

27 26 25

65

IN

IN

PP3V3_TBT_X_SX

TBT_PWR_EN

PP3V3_G3H

67 76

R8200

33

21

BYPASS=U8201::2MM

20%

6.3V
X5R

1

2

C8202

1.0UF

0201-1

P3V3_TBT_X_SX_EN

201MF1/20W5%

67 76

U8201

5

6

132

74AUP1T97GM

SOT886

4

TBT_PWR_AND_SX_EN

3.3V S0SW TBT Switch

PP3V3_G3H

BYPASS=U8200::2MM

20%

6.3V
X5R

10%
10V
X7R
201

1

2

1

VDD

U8200

SLG5AP1445V

CAP

ON S

1

2

TDFN8

CRITICAL

GND

8

Part
Type

37

D

52

PP3V3_TBT_X_S0

U8200

SLG5AP1445V
Load Switch

R8201

100K

5%

1/20W

MF

201

C8200

1.0UF

0201-1

P3V3TBT_RAMP

1

C8201

4700PF

2

B

76

CPU/PCH State: Off (RTC Only)

PP*_S2R (0.8,1.1,1.8V)
PP*_DDR (0.8,0.9,1.1V)
PP*_AWAKE

(CPU,SRAM,1.2,1.8,3.3V)

A

PP3V3_G3H (VR1)
PP1S_G3H

PP*_G3S (1.8,3.3,5V)
PP*_S5 (1.8,3.3V)
CPU/PCH VRs

* System: Shutdown Awake is a transition state only.
* SoC: SLP_DDR is a transition state only.
* CPU/PCH: S4 is only used by desktops for USB wakes.
* CPU/PCH: S5 is a transition state. May also be used for RTC wakes.

System State:

System Power States

Shutdown (G3H)

S2R
On

Off
Off

Off On
Off
Off

On
On
On

OnOn
OnOn

Off
Off

Standby (G3S)
Off (RTC Only) Sleep

On
Off

On
On
OnOff

On
On

On
Off
Off

On
On

On
Off
Off

Standby (S4)
Standby

On
Off
Off

On
On

On

On
On
On

On
On

On
OnOn

Off/On

Off/On

Sleep (S0i/S3) Run (S0)

On
Off
Off

On
On

Off/On

On
On
On

On
On

OnOn
OnOn
Off/On

Run
AwakeS2R AwakeS2R AwakeS2R AwakeAwakeSoC State:Rails
On

On
On

On
On

On
On
On

R8202

0

5%

1/20W

MF

0201

NOSTUFF

R(on)
@ 4A

21

Current

SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=02/22/2017

PAGE TITLE

7.8 mOhm Typ
TBD mOhm Max

4A Max

A

Power FETs

SIZE

D

BOM_COST_GROUP=PLATFORM POWER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

82 OF 145

SHEET

67 OF 85

8

67

35 4

2

1

678

3 245

1

D

C

Page Notes

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

CRITICAL

F8400

3AMP-32V

PPBUS_G3H

76

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

740S0159

68

0603

21

PPVIN_S0SW_LCDBKLT_F

49

49

OUT

OUT

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

79 5

IN

107S00034

R8400

0.025

1%
1W
MF

0612-1

2 1

4

3

79
68

PPVIN_S0SW_LCDBKLT_R

1

C8400

1000PF

10%

16V

2

X7R-1
0201

1

R8401

80.6K

1%
1/16W
MF-LF
402

2

1

R8402

63.4K

1%
1/16W
MF-LF
402

2

R8442

0

5%

1/20W

MF

0201

GND_BKLT_SGND

68

CRITICAL

Q8400

FDC638APZ_SBMS001

SSOT6-HF

4

3

LCDBKLT_EN_L

PP5V_G3S

68 76

PLACE_NEAR=U8400.5:5MM

68

GND_BKLT_SGND

1

R8440

1M

5%
1/20W
MF
201

2

BKLT_SD LCDBKLT_SW

BKLT_SENSE_OUT

21

BKLT_EN_REDP_BKLT_EN

NO STUFF

1

C8442

33PF

5%

25V

2

NP0-C0G
0201

6
5
2
1

R8444

10

1%
1/16W
MF-LF

402

C8440

1UF

10%

10V

X5R

402-1

NOSTUFF

1

C8401

0.001UF

10%

50V

2

CERM
402

1

2

1

2

68

68

68

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

MAKE_BASE=TRUE

1

R8445

10

1%
1/16W
MF-LF
402

2

PP5V_S0_BKLT_A
PP5V_S0_BKLT_D

PLACE_NEAR=U8400.18:5MM

1

C8441

1UF

10%

10V

2

X5R
402-1

5

18

VDDA

VDDD

U8400

LLP

LP8548B1SQ_-04

11

SD

9

VSENSE_N

10

VSENSE_P

19

SENSE_OUT

17
12

15
16

EN
PWM_KEYB

SCL

(IPU)

SDA

(IPU)

CRITICAL

ISET_KEYB

KEYB1
KEYB2

353S4160

SW
SW
FB
GD

SW2
FB2

1

C8413

12PF

5%

25V

2

CERM
0201

CRITICAL

1

C8410

4.7UF

10%

25V

2

X6S-CERM
0603

PLACEMENT_NOTE:

SANDWICH C8410 AND C8411

PLACE_NEAR=L8410.1:5MM

SANDWICH C8410 AND C8411

PLACE_NEAR=L8410.1:5MM

R8410

DIDT=TRUE
SWITCH_NODE=TRUE

VOLTAGE=55V

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000

2
1
21

LCDBKLT_FB

4

LCDBKLT_FET_DRV

20

13
14

6
8

GATE_NODE=TRUE
DIDT=TRUE

NC

NC
NC

NC
NC

10

5%
1/16W
MF-LF

402

1

C8414

3PF

+/-0.1PF

25V

2

C0G
0201

152S00253

CRITICAL

15UH-20%-1.9A-0.24OHM

CRITICAL

1

C8411

4.7UF

10%

25V

2

X6S-CERM
0603

PLACE_NEAR=L8410.1:5MM

21

LCDBKLT_FET_DRV_R

GATE_NODE=TRUE
DIDT=TRUE

68

1

C8412

0.1UF

10%

25V

2

X5R
402

L8410

PIME062D-SM

PLACE_NEAR=Q8401.5:3MM

21

68

PPVIN_SW_LCDBKLT_SW

NOSTUFF

1

C8402

12PF

5%

100V

2

C0G
0201

5

CRITICAL

Q8401

4

SI7812DN

PWRPK-1212-8

PLACE_NEAR=U8400.1:3MM

321

PLACE_NEAR=L8410.2:3MM

371S00077

CRITICAL

D8410

SOD123-COMBO

KA

PMEG10020ELR-DFLS2100

XW8410

PLACE_NEAR=D8410::2MM

SM

68

PPVOUT_S0_LCDBKLT_F

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8460

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8465

2.2UF

10%
100V

2

X5R-CERM
1206

2

PLACE_NEAR=D8410.K:5MM

1

CRITICAL

1

C8470

2.2UF

10%
100V

2

X5R-CERM
1206

LCDBKLT_TB_XWR

1

R8431

18.2K

1%
1/16W
MF-LF
402

2

1

R8432

150K

1%
1/16W
MF-LF
402

2

FERR-470-OHM-0.2A

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8461

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8466

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8471

2.2UF

10%
100V

2

X5R-CERM
1206

1

C8476

3PF

+/-0.1PF

100V

2

C0G
0201

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8462

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8467

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8472

2.2UF

10%
100V

2

X5R-CERM
1206

1

C8477

12PF

5%

100V

2

C0G
0201

NOSTUFF

1

C8432

100PF

5%

100V

2

C0G-CERM
0603

L8420

21

0402

OMIT_TABLE

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8463

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5.1MM

CRITICAL

1

C8468

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8473

2.2UF

10%
100V

2

X5R-CERM
1206

1

C8478

3PF

+/-0.1PF

100V

2

C0G
0201

PPVOUT_S0_LCDBKLT

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8464

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5.1MM

CRITICAL

1

C8469

2.2UF

10%
100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:6.1MM

1

C8474

12PF

5%

100V

2

CERM
0402

1

C8479

12PF

5%

100V

2

C0G
0201

PLACE_NEAR=D8410.K:6.1MM

1

C8475

12PF

5%

100V

2

CERM
0402

Vout = 46V Typ, 55V Max
Iout = 0.12A Typ, 0.15A Max
Fs = 625kHz Typ (+/- 7%)

79 69 68

D

C

B

68

PP5V_G3S

68 76

1

R8452

1.8K

5%
1/20W
MF
201

2

79 69

79 69

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

IN

BI

I2C_BKLT_SCL

I2C_BKLT_SDA

GND_BKLT_SGND

1

R8453

1.8K

5%
1/20W
MF
201

2

R8451

0

5%

1/20W

MF

0201

KBD_BKLT_PWM

1

R8447

10K

5%
1/20W
MF
201

2

PLACE_NEAR=U8400.15:10MM

R8450

0

5%

1/20W

MF

0201

21

PLACE_NEAR=U8400.16:10MM

CKPLUS_WAIVE=I2C_PULLUP

I2C_BKLT_SCL_R

21

CKPLUS_WAIVE=I2C_PULLUP

I2C_BKLT_SDA_R

GND_SW

GND_SW

GND_SW2

7

24

23

XW8400

3

SM

GNDA

GNDD

22

21

THRM

PAD

25

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0V

68

116S0004

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

B

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

L84201

BOM OPTIONCRITICAL

TABLE_5_ITEM

A

8

LINE WIDTHS PBUS LINE WIDTHS

PP5V_S0_BKLT_A

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

68

PPVIN_S0SW_LCDBKLT_F LCDBKLT_FET_DRV

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_R

MIN_LINE_WIDTH=2.0000

PP5V_S0_BKLT_D

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

68

MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

67

68

68

LCD BKLT LINE WIDTHS

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

79 68

GATE_NODE=TRUE

DIDT=TRUE

68

I351

PPVIN_SW_LCDBKLT_SW

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.1200

VOLTAGE=55V

SWITCH_NODE=TRUE

DIDT=TRUE

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

VOLTAGE=55V

PPVOUT_S0_LCDBKLT_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

VOLTAGE=55V

68

68

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

LCD Backlight Driver

79 69 68

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DISPLAY

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

84 OF 145

SHEET

68 OF 85

1

SIZE

A

D

678

3 245

1

D

C

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

1%
MF

201

1%
MF

201

C8518

0.1UF

10%
10V

X5R-CERM

0201

3

912

NC

6

NC

10

NC

5

NC

11

NC

21

21

21

D8517

SM-0201

KA

DSF01S30SCAP

D8518

SM-0201

K A

DSF01S30SCAP

EDP_PANEL_PWR_BUF_EN

PP5V_G3S

76

LCD_PWR_SLEW

PANEL_P5V_EN

1

C8515

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_G3H

69 76

LCD_PWR_SLEW_3V3

PANEL_P3V3_EN

1

C8516

0.47UF

10%

6.3V

2

CERM-X5R
0201

69

CRITICAL

CAP

ON S

1

C8509

2200PF

10%
10V

2

X7R-CERM
0201

CRITICAL

CAP

ON S

1

C8513

2200PF

10%
10V

2

X7R-CERM
0201

1

VDD

U8500

SLG5AP1443V

TDFN

GND

8

1

VDD

U8501

SLG5AP1443V

TDFN

GND

8

5

IN

PP3V3_G3H

69 76

R8510

2 1

R8511

2 1

PP3V3_G3H

69 76

EDP_PANEL_PWR_EN

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

PU_U8510_4

PU_U8510_12

EDP_PANEL_PWR_DLY_EN

1

VDD

SLG4AP4998

2

EDP_PANEL_PWR_EN

4 8

PM_SLP_S3_L

SMC_RESET_INPUT_L

STQFN

U8510

PANEL_FET_EN_DLY

PANEL_PWR_EN_CONN

SMC_RESET_OUTPUT_L

X604_DISP_PWR_EN

X604_DISP_SMC_RST_L

NC0
NC1

GND

7

R8517

330

21

PANEL_P5V_EN_D

5%

1/20W

MF

201

R8515

150K

1/20W

R8516

200K

1/20W

R8518

330

21

PANEL_P3V3_EN_D

5%

1/20W

MF

201

CRITICAL

L8509

2.4GHZ

0.65X0.5X0.3MM-SM

4

SYM_VER-1

1

MIPI_FTCAM_CLK_CONN_N

69

MIPI_FTCAM_CLK_ISOL_N

69

L8580

27NH-3%-0.140A-2.3OHM

2 1

0201

MIPI_FTCAM_CLK_F_N

L8581

27NH-3%-0.140A-2.3OHM

MIPI_FTCAM_CLK_ISOL_P

69

1

C8582

7PF

+/-0.1PF
25V

2

CERM

MUX

37

D

52

1

2

37

D

52

VOLTAGE=5V

PP5V_S0SW_LCD

C8511

0.1UF

10%
10V
X5R-CERM
0201

1

C8510

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

C8512

10UF

20%
10V

2

X5R-CERM
0402-7

1

C8560

12PF

5%
25V

2

CERM
0201

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.1000

VOLTAGE=3.3V

1

C8561

3PF

+/-0.1PF
25V

2

C0G
0201

PP3V3_S0SW_LCD

1

C8562

12PF

5%
25V

2

CERM
0201

1

C8563

3PF

+/-0.1PF
25V

2

C0G
0201

69

MIPI_FTCAM_DATA_ISOL_N<0>

69

MIPI_FTCAM_DATA_ISOL_P<0>

69

PP5V_G3S

76

77.2 mA nominal max

69 45

96.2 mA peak

0201

1

C8586

7PF

+/-0.1PF
25V

2

CERM
0201

1

C8583

7PF

+/-0.1PF
25V

2

CERM
0201

1

C8587

7PF

+/-0.1PF
25V

2

CERM
0201

2 1

0201

MIPI_FTCAM_CLK_F_P

C8581

7PF

+/-0.1PF

25V
CERM
0201

L8584

27NH-3%-0.140A-2.3OHM

2 1

0201

MIPI_FTCAM_DATA_F_N<0>

L8585

27NH-3%-0.140A-2.3OHM

2 1

0201

MIPI_FTCAM_DATA_F_P<0>

C8585

7PF

+/-0.1PF

25V
CERM
0201

L8570

FERR-120-OHM-1.5A

21

0402A

CRITICAL

1

2

1

2

1

2

C8580

7PF

+/-0.1PF

25V
CERM
0201

C8584

7PF

+/-0.1PF

25V
CERM
0201

C8577

0.1UF

10%
16V
X7R-CERM
0402

1

2

1

2

PP5V_MAIN_ALSCAM_F

CRITICAL

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

J8500

20759-042E-02

F-ST-SM

PWR

4443

3 2

PLACE_NEAR=J8500.37:2.54MM

MIPI_FTCAM_CLK_CONN_P

CRITICAL

L8507

2.4GHZ

0.65X0.5X0.3MM-SM

4

3 2

SYM_VER-1

1

MIPI_FTCAM_DATA_CONN_N<0>

MIPI_FTCAM_DATA_CONN_P<0>

PLACE_NEAR=J8500.33:2.54MM

69

VOLTAGE=5V

516S00266

PP3V3_S0SW_LCDPPVOUT_S0_LCDBKLT

CONNECTOR

69 45 79 69 68

69

D

69

69

C

B

A

FTCAM Secure Disable

PP3V3_G3S

76

MIPI_FTCAM_CLK_P

36

MIPI_FTCAM_CLK_N

36

MIPI_FTCAM_DATA_P<0>

36

MIPI_FTCAM_DATA_N<0>

36

I2C_FTCAM_SDA

I2C_FTCAM_SCL

SEP_CAM_DISABLE_OE_L
SEP_CAM_DISABLE_OUT_L

IN

Output

S

Cam Enable

H

Cam Disable

L

PLACE_NEAR=J8500:5MM

5%

100V

C0G

0201

1

2

C8501

12PF

69

79 69 68

79 69 68

EDP_PANEL_PWR_BUF_EN
I2C_BKLT_SDA

PPVOUT_S0_LCDBKLT

3PF

100V

C0G

0201

1

C8503

12PF

2

100V

C0G

0201

C8504

+/-0.1PF

5%

46

BI

46

BI

43

PLACE_NEAR=J8500:5MM

1

2

C8502

+/-0.1PF

3PF

100V

C0G

0201

1

2

BYPASS=U8570::3MM

C8595

0.1UF

X5R-CERM

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

R8589

100K

1/20W

201

PLACE_NEAR=J8500:5MM

10%

100V

X7R

0402

1

2

C8500

1000PF

10%
10V

0201

5%
MF

1

2

1

2

NOSTUFF

CLKP

1

CLKN

2

D1P

3

D1N

4

D2P

5

D2N

6

8

OE*

11

SEL

C8573

12PF

5%

25V
CERM
0201

10

VCC

U8595

FSA642S

UMLP-COMBO

CLKAP

CLKBP
CLKAN

CLKBN

SWITCH

CONTROL

GND

9

1

2

C8570

DA1P

DB1P
DA1N

DB1N
DA2P

DB2P
DA2N

DB2N

NC
NC

12PF

25V
CERM
0201

17

22

GND_VOID=TRUE

16

23

GND_VOID=TRUE

15

20

GND_VOID=TRUE

14

21

GND_VOID=TRUE

13

19

12

18

7
24

1

5%

2

MIPI_FTCAM_CLK_ISOL_P

MIPI_FTCAM_CLK_ISOL_N

MIPI_FTCAM_DATA_ISOL_P<0>

MIPI_FTCAM_DATA_ISOL_N<0>

NC

I2C_FTCAM_ISOL_SDA

NC

I2C_FTCAM_ISOL_SCL

NC
NC

46

46

45

45

BI

BI

BI

BI

I2C_ALS_SDA

I2C_ALS_SCL

I2C_FTCAM_ISOL_SDA

69

I2C_FTCAM_ISOL_SCL

69

I2C_TCON_SDA

I2C_TCON_SCL

69

69

69

69

R8595

100K

5%

1/20W

MF

201

R8556

R8558

R8560

R8562

R8572

R8568

PP1V8_G3S

1

2

1

R8596

100K

5%
1/20W
MF
201

2

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

33

33

33

33

33

33

69

69

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

21

1/20W5%

201MF

PLACE_NEAR=J8500:5MM

21

1/20W5%

201MF

1

C8550

12PF

5%
25V

2

CERM
0201

46 76

1

C8551

12PF

5%
25V

2

CERM
0201

1

C8552

12PF

5%
25V

2

CERM
0201

1

C8553

12PF

5%
25V

2

CERM
0201

69 5

69 5

5

5

5

5

5

5

5

5

69

69

69

69

69

1

C8554

12PF

5%
25V

2

CERM
0201

DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P

DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>
DP_INT_ML_C_P<1>

DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>

DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>

MIPI_FTCAM_DATA_CONN_N<0>
MIPI_FTCAM_DATA_CONN_P<0>

MIPI_FTCAM_CLK_CONN_N
MIPI_FTCAM_CLK_CONN_P

PP5V_S0SW_LCD

COWLING BOSES

860-00974

SH8501

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

SH8502

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

CKPLUS_WAIVE=I2C_PULLUP

I2C_ALS_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_ALS_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_FTCAM_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_FTCAM_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_TCON_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_TCON_SCL_CONN

1

C8555

12PF

5%
25V

2

CERM
0201

BOM_COST_GROUP=DISPLAY

69

69

69

69

69

69

SIGNAL

PWR

GND

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

4847
5049
5251
5453
5655
5857
6059
6261
6463
6665
6867

NC

NC

EDP_PANEL_PWR_BUF_EN
DP_INT_HPD

TP_LCD_IRQ_L

P0: J8500.14 was TCON_BKLT_PWM on J130

EDP_BKLT_PWM

I2C_BKLT_SDA
I2C_BKLT_SCL
I2C_TCON_SDA_CONN
I2C_TCON_SCL_CONN

I2C_ALS_SDA_CONN
I2C_ALS_SCL_CONN
I2C_FTCAM_SCL_CONN
I2C_FTCAM_SDA_CONN

PP5V_MAIN_ALSCAM_F

1

C8564

12PF

5%
25V

2

CERM
0201

LCD Panel AUX strapping

PP3V3_S0SW_LCD

R8503

R8502

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

eDP Display Connector

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1M

2 1

1M

2 1

69

5

OUT

IN

BI

BI

69

69

69

69

69

69

69

69 45

DP_INT_AUXCH_C_N

201MF1/20W5%

NO_XNET_CONNECTION=1

DP_INT_AUXCH_C_P

201MF1/20W5%

NO_XNET_CONNECTION=1

DRAWING NUMBER

PD on PCH page
(CSA5)

79 5

79 69 68

79 68

SYNC_DATE=02/13/2017

051-04039

REVISION

2.0.0

BRANCH

PAGE

85 OF 145

SHEET

69 OF 85

B

69 5

69 5

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

S4E0

D

C

72 43

IN

PCIE_SSD0_D2R_P<0>

37

PCIE_SSD0_D2R_N<0>

37

R8640

51

5%

1/20W

MF

201

R8604

3.01K

1%

1/20W

MF

201

GND_VOID=TRUE

C8601

10% X5R-CERM

C8602

10%

6.3V X5R-CERM 0201

GND_VOID=TRUE

21

21

21

21

0.22UF

0.22UF

71 37

71 37

43 37

74

74

02016.3V

SSD0_CLK24M_01SSD0_CLK24M

71

PCIE_CLK100M_SSD0_01_P
PCIE_CLK100M_SSD0_01_N

SSD0_CLKREQ0_L
SSD0_S4E0_PCIE_RESREF
PCIE_SSD0_R2D_P<0>

PCIE_SSD0_R2D_N<0>

PCIE_SSD0_D2R_C_P<0>
PCIE_SSD0_D2R_C_N<0>

PP0V9_SSD

70 71 72 75

TP_SSD0_S4E0_ANI1_VREF
TP_SSD0_S4E0_ANI0_VREF

SSD0_S4E0_AVDD18_PLL

70

SSD0_S4E0_PCI_AVDD_H

70

PP0V9_SSD

70 71 72 75

GND_VOID=TRUE

GND_VOID=TRUE

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_M

P5

PCIE_CLKREQ_N

H7

PCI_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_M

R12

PCIE_TX0_P

T11

PCIE_TX0_M

J6

M9

N6

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

GND_VOID=TRUE
GND_VOID=TRUE

J8

N8

PCI_VDD_1

L2J4G12

PCI_VDD_2

AVDD18_PLL

G8

G6

ANI0_VREF

ANI1_VREF

L6

L8

VDD

N2

K9

J2

E10

E2

R8

R6

VDDIO

U8600

KLAFGAKWCM-E0T2

ULGA-COMBO

OMIT_TABLE

T5

P9

D3

E12

G4

L12

VCC

R2

F3

R4

VPP

VDD_PLL

PP1V8_SSD

PP2V7_NAND

PP0V9_SSD

70 71 72 75

49 70 71 72 76

70 71 72 75

SSD0_S4E0_VPP

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/UART_RX

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/UART_TX

EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

B3
C4
B5
C6
B7
C8
B9
B11

E8

D7

E6

E4

D5

D9

NOSTUFF

1

R8630

0

5%
1/20W
MF
0201

2

SSD0_LPB_L
SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E0_SWD_UID0
SSD0_S4E_UART_RX
SSD0_S4E0_SWD_UID1
TP_SSD0_S4E0_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E0_JTAG_TDO
TP_SSD0_S4E0_JTAG_TDI
SSD0_S4E_JTAG_SEL

TP8604

1

TP

TP-P5

72 71

72 71 34

72 71

79

72 71 35

72 71 35

71

79

72 71

D

PP1V8_SSD

NOSTUFF

1

R8603

47K

1%
1/20W
MF
201

2

72 71

74 72 71

72 71 43 37

1

R8602

47K

1%
1/20W
MF
201

2

70 71 72 75

C

R8600

100K

1%

1/20W

MF

201

1

2

R8606

100

1%

1/20W

MF

201

1

2

R8605

300

1%

1/20W

MF

201

T3

DROOP_N

74 72 71

SSD0_RESET_L
SSD0_S4E_JTAG_TRST_L

72 71

SSD0_S4E0_ZQ_C
SSD0_S4E0_ZQ_L

1

2

L4

G10

K3

C10

RESET*

TRST*

ZQ_C
ZQ_N

A4

A2

A6

A8

A10

A12

B1

B13

C2

C12

D1

D11

D13

F1

F5

F7

F9

F11

F13

H1

H3

H5

H9

H11

H13

VSS

J10

K1

K5

K7

K13

L10

M1

M5

M7

M13

N4

N10

P1

P3

P7

P11

P13

R10

T1

T7

T9

T13

U2

U4

U6

U8

WP_N

U10

U12

SSD0_S4E0_DROOP_L

G2

SSD0_WP_L

74 72 71

1

R8609

100K

1%
1/20W
MF
201

2

1

R8608

100K

1%
1/20W
MF
201

2

1

R8620

100K

1%
1/20W
MF
201

2

B

A

S4E VDD

PP0V9_SSD

70 71 72 75

S4E VCC

PP2V7_NAND

49 70 71 72 76

CRITICAL

1

C8610

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8648

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8611

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8649

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8612

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8650

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8613

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8614

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8615

0.1UF

10%
16V

2

X5R-CERM
0201

S4E VDDIO

PP1V8_SSD

70 71 72 75

1

2

PP1V8_SSD

70 71 72 75

CRITICAL

C8632

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

C8636

4.3UF

20%

4V
CERM
0402

1

4

2

R8610

0

21

5%

1/20W

MF

0201

B

CRITICAL

1

C8635

2.2UF

20%

6.3V

2

X5R
0201

3

SSD0_S4E0_PCI_AVDD_H

CRITICAL

1

C8644

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8645

0.1UF

10%
16V

2

X5R-CERM
0201

70

X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

8

S4E<0>

R8611

0

21

5%

1/20W

MF

0201

67

SSD0_S4E0_AVDD18_PLL

CRITICAL

1

C8646

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8647

0.1UF

10%
16V

2

X5R-CERM
0201

70

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

35 4

IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

86 OF 145

SHEET

70 OF 85

1

SIZE

D

678

3 245

1

S4E1

D

C

PCIE_SSD0_D2R_P<1>

37

PCIE_SSD0_D2R_N<1>

37

GND_VOID=TRUE

C8701

6.3V 0201

C8702

GND_VOID=TRUE

70

IN

R8704

3.01K

1/20W

1%
MF

201

21

21

X5R-CERM10%

21

70 37

70 37

43 37

74

74

0.22UF

0.22UF

0201X5R-CERM6.3V10%

SSD0_CLK24M_01
PCIE_CLK100M_SSD0_01_P

PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ1_L
SSD0_S4E1_PCIE_RESREF
PCIE_SSD0_R2D_P<1>

PCIE_SSD0_R2D_N<1>

GND_VOID=TRUE

PCIE_SSD0_D2R_C_P<1>
PCIE_SSD0_D2R_C_N<1>

GND_VOID=TRUE

PP0V9_SSD

70 71 72 75

TP_SSD0_S4E1_ANI1_VREF
TP_SSD0_S4E1_ANI0_VREF

SSD0_S4E1_AVDD18_PLL

71

SSD0_S4E1_PCI_AVDD_H

71

PP0V9_SSD

70 71 72 75

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_M

P5

PCIE_CLKREQ_N

H7

PCI_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_M

R12

PCIE_TX0_P

T11

PCIE_TX0_M

J6

M9

N6

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

GND_VOID=TRUE
GND_VOID=TRUE

J8

N8

PCI_VDD_1

L2J4G12

PCI_VDD_2

AVDD18_PLL

G8

G6

ANI0_VREF

ANI1_VREF

L6

L8

VDD

N2

K9

J2

E10

E2

R8

R6

VDDIO

U8700

KLAFGAKWCM-E0T2

ULGA-COMBO

OMIT_TABLE

T5

P9

D3

E12

G4

L12

VCC

R2

F3

R4

VPP

VDD_PLL

PP1V8_SSD

PP2V7_NAND

PP0V9_SSD

70 71 72 75

49 70 71 72 76

70 71 72 75

SSD0_S4E1_VPP

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/UART_RX

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/UART_TX

EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

B3
C4
B5
C6
B7
C8
B9
B11

E8

D7

E6

E4

D5

D9

NOSTUFF

1

R8730

0

5%
1/20W
MF
0201

2

SSD0_LPB_L
SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E1_SWD_UID0
SSD0_S4E_UART_RX
SSD0_S4E1_SWD_UID1
TP_SSD0_S4E1_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E1_JTAG_TDO
SSD0_S4E0_JTAG_TDO
SSD0_S4E_JTAG_SEL

TP8704

1

TP

TP-P5

72 70

72 70 34

72 70

72 70

79

74 72 70

72 70 35

72 70 35

74 72

70

72 70

D

PP1V8_SSD

1

R8708

100K

1%
1/20W
MF
201

2

72 70 43 37

1

R8702

47K

1%
1/20W
MF
201

2

70 71 72 75

C

R8706

100

1%

1/20W

MF

201

1

2

R8705

300

1%

1/20W

MF

201

T3

DROOP_N

74 72 70

72 70

SSD0_RESET_L
SSD0_S4E_JTAG_TRST_L
SSD0_S4E1_ZQ_C

SSD0_S4E1_ZQ_L

1

2

L4

G10

K3

C10

RESET*

TRST*

ZQ_C
ZQ_N

A4

A2

A6

A8

A10

A12

B1

B13

C2

C12

D1

D11

D13

F1

F5

F7

F9

F11

F13

H1

H3

H5

H9

H11

H13

VSS

J10

K1

K5

K7

K13

L10

M1

M5

M7

M13

N4

N10

P1

P3

P7

P11

P13

R10

T1

T7

T9

T13

U2

U4

U6

U8

WP_N

U10

U12

SSD0_S4E1_DROOP_L

G2

SSD0_WP_L

74 72 70

1

R8709

100K

1%
1/20W
MF
201

2

B

A

S4E VDD

PP0V9_SSD

70 71 72 75

S4E VCC

PP2V7_NAND

49 70 71 72 76

CRITICAL

1

C8710

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8748

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8711

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8749

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8712

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8750

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8713

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8714

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8715

0.1UF

10%
16V

2

X5R-CERM
0201

S4E VDDIO

PP1V8_SSD

70 71 72 75

1

2

PP1V8_SSD

70 71 72 75

CRITICAL

C8732

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

C8736

4.3UF

20%

4V
CERM
0402

1

4

2

R8710

0

21

5%

1/20W

MF

0201

B

CRITICAL

1

C8735

2.2UF

20%

6.3V

2

X5R
0201

3

SSD0_S4E1_PCI_AVDD_H

CRITICAL

1

C8744

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8745

0.1UF

10%
16V

2

X5R-CERM
0201

71

X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

8

S4E<1>

R8711

0

21

5%

1/20W

MF

0201

67

SSD0_S4E1_AVDD18_PLL

CRITICAL

1

C8746

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8747

0.1UF

10%
16V

2

X5R-CERM
0201

71

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

35 4

IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

87 OF 145

SHEET

71 OF 85

1

SIZE

D

678

3 245

1

S4E2

D

C

70 43

IN

PCIE_SSD0_D2R_P<2>

37

PCIE_SSD0_D2R_N<2>

37

R8840

51

5%

1/20W

MF

201

R8804

3.01K

1%

1/20W

MF

201

GND_VOID=TRUE

C8801

6.3V 0201

10% X5R-CERM

C8802

GND_VOID=TRUE

21

21

21

21

0.22UF

0.22UF

37

37

43 37

74

74

0201X5R-CERM6.3V10%

SSD0_CLK24M_23SSD0_CLK24M
PCIE_CLK100M_SSD0_23_P

PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ2_L
SSD0_S4E2_PCIE_RESREF
PCIE_SSD0_R2D_P<2>

PCIE_SSD0_R2D_N<2>

GND_VOID=TRUE

PCIE_SSD0_D2R_C_P<2>
PCIE_SSD0_D2R_C_N<2>

GND_VOID=TRUE

PP0V9_SSD

70 71 72 75

TP_SSD0_S4E2_ANI1_VREF
TP_SSD0_S4E2_ANI0_VREF

SSD0_S4E2_AVDD18_PLL

72

SSD0_S4E2_PCI_AVDD_H

72

PP0V9_SSD

70 71 72 75

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_M

P5

PCIE_CLKREQ_N

H7

PCI_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_M

R12

PCIE_TX0_P

T11

PCIE_TX0_M

J6

M9

N6

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

GND_VOID=TRUE
GND_VOID=TRUE

J8

N8

PCI_VDD_1

L2J4G12

PCI_VDD_2

AVDD18_PLL

G8

G6

ANI0_VREF

ANI1_VREF

L6

L8

VDD

N2

K9

J2

E10

E2

R8

R6

VDDIO

U8800

KLAFGAKWCM-E0T2

ULGA-COMBO

OMIT_TABLE

T5

P9

D3

E12

G4

L12

VCC

R2

F3

R4

VPP

VDD_PLL

PP1V8_SSD

PP2V7_NAND

PP0V9_SSD

70 71 72 75

49 70 71 72 76

70 71 72 75

SSD0_S4E2_VPP

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/UART_RX

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/UART_TX

EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

B3
C4
B5
C6
B7
C8
B9
B11

E8

D7

E6

E4

D5

D9

NOSTUFF

1

R8830

0

5%
1/20W
MF
0201

2

SSD0_LPB_L
SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E2_SWD_UID0
SSD0_S4E_UART_RX
SSD0_S4E2_SWD_UID1
TP_SSD0_S4E2_UART_TX
SSD0_OCARINA_PFN

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E2_JTAG_TDO
SSD0_S4E1_JTAG_TDO
SSD0_S4E_JTAG_SEL

TP8804

1

TP

TP-P5

71 70

71 70 34

71 70

71 70

79

74 71 70

71 70 35

71 70 35

74

74 71

71 70

D

PP1V8_SSD

1

R8809

100K

1%
1/20W
MF
201

2

71 70 43 37

1

R8802

47K

1%
1/20W
MF
201

2

70 71 72 75

C

R8806

100

1%

1/20W

MF

201

1

2

R8805

300

1%

1/20W

MF

201

T3

DROOP_N

74 71 70

71 70

SSD0_RESET_L
SSD0_S4E_JTAG_TRST_L
SSD0_S4E2_ZQ_C

SSD0_S4E2_ZQ_L

1

2

L4

G10

K3

C10

RESET*

TRST*

ZQ_C
ZQ_N

A4

A2

A6

A8

A10

A12

B1

B13

C2

C12

D1

D11

D13

F1

F5

F7

F9

F11

F13

H1

H3

H5

H9

H11

H13

VSS

J10

K1

K5

K7

K13

L10

M1

M5

M7

M13

N4

N10

P1

P3

P7

P11

P13

R10

T1

T7

T9

T13

U2

U4

U6

U8

WP_N

U10

U12

SSD0_S4E2_DROOP_L

G2

SSD0_WP_L

74 71 70

1

R8808

100K

1%
1/20W
MF
201

2

B

A

S4E VDD

PP0V9_SSD

70 71 72 75

S4E VCC

PP2V7_NAND

49 70 71 72 76

CRITICAL

1

C8810

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8848

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C8811

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8849

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8812

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8850

2.2UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C8813

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8814

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C8815

0.1UF

10%
16V

2

X5R-CERM
0201

S4E VDDIO

PP1V8_SSD

70 71 72 75

1

2

PP1V8_SSD

70 71 72 75

CRITICAL

C8832

10UF

20%

6.3V
CERM-X6S
0402

CRITICAL

C8836

4.3UF

20%

4V
CERM
0402

1

4

2

R8810

0

21

5%

1/20W

MF

0201

B

CRITICAL

1

C8835

2.2UF

20%

6.3V

2

X5R
0201

3

SSD0_S4E2_PCI_AVDD_H

CRITICAL

1

C8844

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8845

0.1UF

10%
16V

2

X5R-CERM
0201

72

X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/14/2017

A

8

S4E<2>

R8811

0

21

5%

1/20W

MF

0201

67

SSD0_S4E2_AVDD18_PLL

CRITICAL

1

C8846

1.0UF

20%
10V

2

X5R-CERM
0201-1

CRITICAL

1

C8847

0.1UF

10%
16V

2

X5R-CERM
0201

72

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

35 4

IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

88 OF 145

SHEET

72 OF 85

1

SIZE

D

678

3 245

1

D

C

PPBUS_G3H_SSD0

49 76

77

IN

CRITICAL

1

C9058

68UF

20%
16V

2

AL
CASE-D2-SM

R9060

0

21

5%

1/20W

MF

0201

CRITICAL

1

C9061

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C9062

2.2UF

20%
25V

2

X6S-CERM
0402

1

R9062

47K

5%
1/20W
MF
201

2

2

R9065

10

5%
1/20W
MF
201

1

P2V7SSD0_AVIN

P2V7SSD0_ENP2V7NAND_EN

CRITICAL

1

C9065

0.1UF

10%
25V

2

X6S-CERM
0201

GND_P2V7SSD0_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

12

11

PVIN

PVIN

U9060

10

AVIN

8

DEF

13

EN

7

FSW

XW9060

SM

118S0578 1 CRITICAL NAND_VCC:2V7R9071

103S00075

TPS62130B-S

VQFN

CRITICAL

353S00897

PGND

PGND

16

15

21

RES,MF,976OHM,1,1/20W,0201

RES,MF,590OHM,1,1/20W,0201

RES,MF,21KOHM,0.1%,50PPM,15V,1/20W,0201

RES,MF,23.2KOHM,0.1%,50PPM,1/20W,0201

1

AGND

6

PAD

THRM

17

SS/TR

SW
SW
SW

VOS

FB

PG

1
2
3

14

5

4

9

P2V7SSD0_PHASE

DIDT=TRUE

P2V7SSD0_VOS
P2V7SSD0_FB
P2V7NAND_PGOOD
P2V7SSD0_SS

R9067

100K

CRITICAL

C9068

1000PF

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

5%

1/20W

MF

201

10%
25V
X7R

0201

PP2V7_NAND

1

2

77

1

2

R9071118S0453 1

R9072 NAND_VCC:2V7CRITICAL1

73 76

152S00703

CRITICAL

L9060

2.2UH-20%-5.5A-0.043OHM

21

MHCI04020C-COMBO

XW9070

P2V7SSD0_FB_TOP

R9070

1/20W

R9071

CRITICAL

1

C9069

100PF

5%

25V

2

C0G
0201

<Ra>

CRITICAL

CRITICAL

1/20W

R9073

48.7K

1/20W

R9072

23.2K

<Rb>

BOM OPTIONCRITICAL

CRITICAL NAND_VCC:2V5

NAND_VCC:2V5103S00137 CRITICALR9072

1/20W

10

5%
MF

201

590

1%
MF

201

0.1%
MF

0201

0.1%
MF

0201

2

SM

1

1

2

1

OMIT_TABLE

2

P2V7SSD0_FB_R

1

2

1

OMIT_TABLE

2

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Vout = 2.5V
Iout Max = 1.8A
F = 1.25 MHZ

Vout = 0.8 * (1 + <Ra>/<Rb>) = 2.701V

NOSTUFF

CRITICAL

1

C9070

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9080

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9086

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9095

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

CRITICAL

1

C9071

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9081

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9087

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9096

150UF

20%

6.3V

2

TANT-POLY
CASE-B1S-1

CRITICAL

1

C9072

150UF

20%

6.3V

2

TANT
CASE-B-SM

NOSTUFF

1

C9082

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9088

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C9073

100UF

20%

6.3V

2

TANT-POLY
CASE-A3-LLP

NOSTUFF

1

C9083

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9089

10UF

20%

6.3V

2

CER-X6S
0402

PP2V7_NAND

NOSTUFF

1

C9084

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9090

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9085

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

1

C9091

10UF

20%

6.3V

2

CER-X6S
0402

73 76

D

C

B

B

A

8

X1032

PAGE TITLE

SYNC_DATE=02/13/2017

A

NAND VCC VR

SIZE

D

Apple Inc.

DRAWING NUMBER

051-04039

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

90 OF 145

SHEET

73 OF 85

1

(All Caps)

GND_VOID=TRUE

678

3 245

1

D

37

37

37

37

37

37

37

37

37

37

OUT
OUT
IN
IN

OUT

PCIE_SSD0_R2D_C_N<0>

OUT

OUT

OUT

OUT

PCIE_SSD0_R2D_C_P<1>

PCIE_SSD0_R2D_C_N<1>

PCIE_SSD0_R2D_C_P<2>

PCIE_SSD0_R2D_C_N<2>

NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>

C9110

0.22UF

C9111

0.22UF

C9112

0.22UF

C9113

0.22UF

C9114

0.22UF

C9115

0.22UF

21

X5R

21

X5R20% 02016.3V

21
20% 6.3V X5R

21

20% X5R6.3V
21

21

6.3V20% 0201X5R

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

020120% 6.3V

0201

0201

02016.3V X5R20%

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

PCIE_SSD0_R2D_P<0>PCIE_SSD0_R2D_C_P<0>

PCIE_SSD0_R2D_N<0>

PCIE_SSD0_R2D_P<1>

PCIE_SSD0_R2D_N<1>

PCIE_SSD0_R2D_P<2>

PCIE_SSD0_R2D_N<2>

NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>

70

70

71

71

72

72

R9193

SSDJTAG:2L

0

21

MF1/20W5%

SSD0_S4E1_JTAG_TDO

0201

SSD0_S4E2_JTAG_TDO

71 72

72

D

C

PP1V8_SSD

75 79 80

1

R9110

0

5%
1/20W
MF
0201

2

SSD0_WP_L

70 71 72

PP2V7_NAND

76

C

B

NAND_RESET_L

77

PMU_SYS_ALIVE

34 35 65

R9115

5% MF002011/20W

R9117

5% 0201

0

1/20W MF

1

R9120

24.9

1%
1/10W
MF-LF
603

21

SSD0_RESET_L

70 71 72

2

1

R9121

24.9

1%
1/10W
MF-LF
603

2

1

R9122

24.9

1%
1/10W
MF-LF
603

2

1

R9123

24.9

1%
1/10W
MF-LF
603

2

1

R9124

24.9

1%
1/10W
MF-LF
603

2

1

R9125

24.9

1%
1/10W
MF-LF
603

2

P2V7_SSD_DISCHARGE

4

21

SSD0_OCARINA_PFN

70 71

72

D

Q9120

1

G

S

32

DMN2044UCB4

BGA BGA

1

G

4

D

Q9121

B

DMN2044UCB4

S

32

A

NAND_DISCHARGE_EN

77

1

R9106

10K

5%
1/20W
MF
201

2

R9105

10K

1/20W

5%
MF

201

21

1

C9105

33000PF

10%

6.3V

2

X5R
201

NAND_DISCHARGE_EN_RC

BOM_COST_GROUP=SSD

PAGE TITLE

SSD Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

91 OF 145

SHEET

74 OF 85

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

PMIC Buck0 - SoC VDD_CPU

PPVDDCPU_AWAKE

63

Sourced from 3V3 G3H
Enabled by

PMIC Buck1 - SoC VDD_CPU_SRAM

PPVDDCPUSRAM_AWAKE

63

Sourced from 3V3 G3H
Enabled by

PMIC Buck2 - SoC VDD_SOC

PP0V82_SLPDDR

63

Sourced from 3V3 G3H
Enabled by

PMIC BUCK3 - SoC AOP/SMC/VDD1

PP1V8_SLPS2R

63 82

Sourced from 3V3 G3H
Enabled by

PPVDDCPU_AWAKE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.06V
MAKE_BASE=TRUE

PPVDDCPU_AWAKE

PPVDDCPUSRAM_AWAKE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.06V
MAKE_BASE=TRUE

PPVDDCPUSRAM_AWAKE

PP0V82_SLPDDR

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.82V
MAKE_BASE=TRUE

PP0V82_SLPDDR
PP0V82_SLPDDR

PP1V8_SLPS2R

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0740
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

79

38

38

79

38

82

80 79

63

67

64

42

65

43

42

34 43

40

40

40

40

27

58

45 57

45

43 52 55

28

29

PMIC BUCK3 SW 4 - VDD1

PP1V8_S3

63

Sourced from PP1V8_SLPS2R
Enabled by

PMIC Buck4 - SDRAM VDD2

PP1V1_SLPS2R

63

Sourced from 3V3_G3H
Enabled by

U7901 - VDDIO_DDR & PLL

PP1V1_SLPDDR

64

Sourced from
Enabled by

PMIC Buck5 - VDD_FIXED

PP0V9_SLPDDR

63

Sourced from 3V3_G3H
Enabled by

PP1V8_S3

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_S3

PP1V1_SLPS2R

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPS2R
PP1V1_SLPS2R

PP1V1_SLPS2R
PP1V1_SLPS2R

PP1V1_SLPDDR

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR

PP0V9_SLPDDR

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.9V
MAKE_BASE=TRUE

PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR

79

22 23 66

64

64

39

40

79

34

39

39

40

39

39

39

39

39

82

PMIC Buck8 SW 1 - VCCSTG

63

Sourced from PP1V05_PRIM
Enabled by

PP1V_S0SW

PMIC Buck8 SW 2 - VCCPLL, VCCSTPMIC BUCK3 SW 5 - UNUSED

PP1V_S3

63

Sourced from PP1V05_PRIM
Enabled by

PMIC Buck9 - 0V9 SSD

PP0V9_SSD

63

Sourced from 3V3 G3H
Enabled by

PMIC Buck10 - 1V8 SSD

PP1V8_SSD

63

Sourced from 3V3 G3H
Enabled by

PMIC LDO0 - VDD_LOW

PP0V8_SLPS2R

64

Sourced from PP1V1_SLP2R
Enabled by

PMIC LDO1 - PCH VCCRTC

PP3V_G3H

64

Sourced from PP3V3_G3H
Enabled by

PMIC LDO2 - PCIE_REFBUF/PLL

PP1V_S0SW

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1V
MAKE_BASE=TRUE

PP1V_S0SW

PP1V_S3

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0740
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V_S3
PP1V_S3
PP1V_S3
PP1V_S3
PP1V_S3

PP0V9_SSD

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.9V
MAKE_BASE=TRUE

PP0V9_SSD

PP1V8_SSD

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_SSD

PP0V8_SLPS2R

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.8V
MAKE_BASE=TRUE

PP0V8_SLPS2R

PP3V_G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3V
MAKE_BASE=TRUE

PP3V_G3H

6 8 12 18

D

8 12

6 8 12 15 59

65

42

42

80 79

70 71 72

80 79 74

70 71 72

C

39

79

9 15

B

A

PMIC BUCK3 SW 1

PP1V8_AWAKE

63 82

Sourced from PP1V8_SLPS2R
Enabled by

PMIC BUCK3 SW 3 - VCCPRIM_1P8

PP1V8_S5

63

Sourced from PP1V8_SLPS2R
Enabled by

PP1V8_AWAKE

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE

PP1V8_S5

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5
PP1V8_S5

79

65

42

40

40

40

40

40

37 42 43

42

56

80 79

35

13

19

19

59

66

9 13

65

45

9 13

66

16

45

42

42

20

42

9

9 17

9 14 17

9

9 17

20

45

PMIC Buck7 - VCCPRIM_CORE

63

PPVCC_PRIM_CORE

Sourced from 3V3_G3H
Enabled by

PMIC Buck8 - VCCPRIM_1P0

PP1V_PRIM

63

Sourced from 3V3_G3H
Enabled by

PPVCC_PRIM_CORE

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.0V
MAKE_BASE=TRUE

PPVCC_PRIM_CORE
PPVCC_PRIM_CORE

PP1V_PRIM

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1V
MAKE_BASE=TRUE

PP1V_PRIM

PP1V_PRIM

PP1V_PRIM

PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM
PP1V_PRIM

79

9

82

79

63

82

9

16

13

9

9

13

13

13

9

9

9

9 13

9 13

13

9 13

9 13

9

66

PP1V2_AWAKE

64

Sourced from PP1V8_SLPS2R
Enabled by

PP1V2_AWAKE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.2V
MAKE_BASE=TRUE

PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE

PMIC V3P3 SW 1 - USB

PP3V3_AWAKE

64

Sourced from 3V3_G3H
Enabled by

PP3V3_AWAKE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_AWAKE

PMIC V3P3 SW 2 - VCCDSW_3P3, VCCPRIM_3P3

PP3V3_S5

64

Sourced from 3V3_G3H
Enabled by

PP3V3_S5

MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.0800
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

79

40

40

40

40

40

9

9

16

20

20

9 13

15

67

13 9

42

66

9 13

9
14

20

SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=02/21/2017

43

PAGE TITLE

20

Power Aliases - 1

DRAWING NUMBER

051-04039

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

PAGE

120 OF 145

SHEET

75 OF 85

B

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

PBUS Rails

U7000 - PBUS

58

47

28 29

62

PPBUS_G3H

PPBUS_HS_CPU

PPDCIN_G3H

U7550 - 5V G3S

PP5V_G3S

Sourced from PBus
Enabled by P5VG3S_EN

3V3 Rails

U6960 - 3V3_G3H_RTC

PPBUS_G3H

MIN_LINE_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_HS_CPU

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.2500
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU

PPDCIN_G3H

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=20V
MAKE_BASE=TRUE

PPDCIN_G3H
PPDCIN_G3H

PP5V_G3S

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S

80 79 79

47

47

47

68

47

53

52

49

49

47

65

31

43

80

59

60

60

61

66

66

80 79 58

58

47

80 79 62

55

66

69

68

51

69

59

60

60

61

28

29

66

PP3V3_G3H_RTC

57

Sourced from PBus
Enabled by CHGR_EN_MVR

U7550 - 3V3_G3H VDD_MAIN

PP3V3_G3H

62

PP3V3_G3H

64

Sourced from PBus
Enabled by PMU_VDDMAIN_EN

VOUT_RTC sourced from

PP3V3_G3H_RTC input to PMIC

U8225 - 3V3 Sensors

PP3V3_G3SSW_SNS

67

Sourced from 3V3_G3H_RTC
Enabled by SENSOR_PWR_EN

PP3V3_G3H_RTC

MIN_NECK_WIDTH=0.0740
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3H_RTC
PP3V3_G3H_RTC

PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC

PP3V3_G3H

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H

PP3V3_G3H

PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H

PP3V3_G3SSW_SNS

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3SSW_SNS
PP3V3_G3SSW_SNS

67

64

57

65

57

28

29

80 79

48

67

64

64

67

64

67

67

67

62

27

82

57

55

52

27

69

47

47 48 49

1V8 Rails

U8220 - 1V8_G3S

PP1V8_G3S

67

Sourced from 1V8 SLEEPS2R
Enabled by P1V8G3S_EN

CPU/PCH Rails

U7210, U7230 - VCCCORE

PPVCC_S0_CPU

60

Sourced from PBus
Enabled by CPU_VR_EN

U7290 - VCCSA

PPVCCSA_S0_CPU

60

Sourced from PBus
Enabled by CPU_VR_EN

U7290 - VCCSA_DDR

PPVCCSA_S0_CPUDDR

60

Sourced from PBus
Enabled by CPU_VR_EN

U7410, U7430 - VCCGT

PPVCCGT_S0_CPU

61

Sourced from PBus
Enabled by CPU_VR_EN

PP1V8_G3S

MIN_LINE_WIDTH=0.0800
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S

PPVCC_S0_CPU

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.5V
MAKE_BASE=TRUE

PPVCC_S0_CPU

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.5V
MAKE_BASE=TRUE

PPVCCSA_S0_CPU

PPVCCSA_S0_CPUDDR

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.5V
MAKE_BASE=TRUE

PPVCCSA_S0_CPUDDR

PPVCCGT_S0_CPU

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.5V
MAKE_BASE=TRUE

PPVCCGT_S0_CPU

80 79

33

51

46

46 69

46

45

46

43

62

44

54 55

50

56

33

32

44

52 53 54

80 79

8 11 49

81

8 11

8 11

81

8 12

D

C

B

A

U7550 - 5V LDO - UNUSED

PP5V_S5_LDO

62

Sensed Rails

PPVIN_G3H_P5VG3S

47 62

PPVIN_G3H_P3V3G3H

47 62

PPVIN_G3H_P3V3G3HRTC

47 57

PP3V3_G3H_PMU_VDDMAIN

48 63

PP3V3_G3S_WLANBT

32 48

PPBUS_G3H_SSD0

49 73

PPBUS_G3H_TPAD

49 55

Digital Ground

GND

VOLTAGE=0V
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0700

PP5V_S5_LDO

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V
MAKE_BASE=TRUE

PPVIN_G3H_P5VG3S

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVIN_G3H_P3V3G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVIN_G3H_P3V3G3HRTC

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PP3V3_G3H_PMU_VDDMAIN

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3S_WLANBT

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3S_WLANBT

PPBUS_G3H_SSD0

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_G3H_TPAD

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

80

80

80

79

33

80

U8210 - 3V3_G3S

PP3V3_G3S

67

Sourced from 3V3_G3H_RTC
Enabled by P3V3G3S_EN

U8200 - 3V3_TBT_X_S0

PP3V3_TBT_X_S0

67

Sourced from 3V3_G3H
Enabled by TBT_PWR_EN

U9080 - NAND 2V7

PP2V7_NAND

73

Sourced from PBUS
Enabled by VR_P2V7_EN

GND

65

PP3V3_G3S

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.0740
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3S

PP3V3_G3S
PP3V3_G3S
PP3V3_G3S
PP3V3_G3S
PP3V3_G3S

PP3V3_TBT_X_S0

PP2V7_NAND

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=2.7V
MAKE_BASE=TRUE

PP2V7_NAND
PP2V7_NAND

80 79

52

55

44

69

56

48

26 27

80 79

49 70 71 72

74

U8110 - VCCIO

PPVCCIO_S0_CPU

66

Sourced from PBus
Enabled by CPU_VR_EN

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.95V
MAKE_BASE=TRUE

PPVCCIO_S0_CPU
PPVCCIO_S0_CPU

U8240 - VCCPLL OC SW

PP1V2_S0SW

67

Sourced from PP1V1_S3
Enabled by CPU_C10_GATE_L

&& PVCCPLLOC_EN

PP1V2_S0SW

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.2V
MAKE_BASE=TRUE

PP1V2_S0SW

Memory Rails

U8100 - Memory VDD2, VDDCA, VDDQ; CPU VDDQ

PP1V2_S3

66

Sourced from PBUS
Enabled by PVDDQ_EN

U8100 - Memory VTT

PP0V6_S0_DDRVTT

66

Sourced from PBUS
Enabled by PVDDQ_EN

PP1V2_S3

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.95V
MAKE_BASE=TRUE

PP1V2_S3

PP1V2_S3
PP1V2_S3
PP1V2_S3
PP1V2_S3
PP1V2_S3
PP1V2_S3

PP0V6_S0_DDRVTT

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.6V
MAKE_BASE=TRUE

PP0V6_S0_DDRVTT
PP0V6_S0_DDRVTT

49

5 8 11

8

79

8 12

80 79

67

8 12

66

21

22 23

22 23

22 23

81

24

24

Memory VRef

PPVREF_S3_MEM_VREFDQ_A

22

PPVREF_S3_MEM_VREFDQ_B

23

PPVREF_S3_MEM_VREFCA

22

PPVREF_S3_MEM_VREFCA

23

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.6V
MAKE_BASE=TRUE

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.6V
MAKE_BASE=TRUE

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0.6V
MAKE_BASE=TRUE

Power Aliases - 2

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

21

21

21

SIZE

2.0.0

121 OF 145

76 OF 85

D

B

A

SYNC_DATE=02/21/2017SYNC_MASTER=X589_CPU_CNL_Y

8

67

35 4

2

1

678

Unused CPU/PCH Signals Unused SoC Signals

3 245

1

D

C

B

A

NC_USB3_EXTC_D2RP

16

NC_USB3_EXTC_D2RN

16

NC_USB3_EXTC_R2D_CN

16

NC_USB3_EXTC_R2D_CP

16

NC_USB3_EXTD_D2RP

16

NC_USB3_EXTD_D2RN

16

NC_USB3_EXTD_R2D_CN

16

NC_USB3_EXTD_R2D_CP

16

NC_PCIE_CLK100M_DEBUGP

16

NC_PCIE_CLK100M_DEBUGN

16

Unused Misc Signals

NC_PMU_CLK32K_GNSS_R

65

NC_GPU_THRMTRIP

65

NC_P3V3G3W_EN

65

NC_P3V3G3W_PGOOD

65

NC_CHGR_EN_VR1

58

NC_CHGR_AUX_OK

58

NC_USBC_XA_USB_BOTP

28

NC_USBC_XA_USB_BOTN

28

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NC_USB3_EXTC_D2RP
NC_USB3_EXTC_D2RN
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTC_R2D_CP
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_D2RN
NC_USB3_EXTD_R2D_CN
NC_USB3_EXTD_R2D_CP
NC_PCIE_CLK100M_DEBUGP

NC_PMU_CLK32K_GNSS_R
NC_GPU_THRMTRIP
NC_P3V3G3W_EN
NC_P3V3G3W_PGOOD
NC_CHGR_EN_VR1
NC_CHGR_AUX_OK
NC_USBC_XA_USB_BOTP
NC_USBC_XA_USB_BOTN

NC_ALTIMETER_INT

35

NC_DFR_DISP_INT

34

NC_DFR_DISP_RESET_L

36

NC_DFR_DISP_TE

36

NC_DFR_PWR_EN

34

NC_DFR_TOUCH_CLK32K_RESET_L

36

NC_DFR_TOUCH_INT_L

35

NC_DFR_TOUCH_RESET_L

36

NC_DFR_TOUCH_RSVD

36

NC_DISP_GCON_INT_L

35

NC_ENET_LOW_PWR

35

NC_ENET_MEDIA_SENSE

35

NC_ENET_RESET_L

37

NC_FTCAM_CLK12M_R

36

NC_FTCAM_RESET_L

36

NC_GNSS_DEV_WAKE

34

NC_GNSS_HOST_TIME

34

NC_GNSS_HOST_WAKE

35

NC_I2S_CODEC_MCLK

36

NC_I2S_CODEC1_MCLK

36

NC_I2S_CODEC1_R2D_R

36

NC_I2S_HAWKING_BCLK_R

36

NC_I2S_HAWKING_D2R

36

NC_I2S_HAWKING_LRCLK

36

NC_MESA_MENUKEY_L

35

NC_MIPI_DFR_CLKN

36

NC_MIPI_DFR_CLKP

36

NC_MIPI_DFR_DATAN

36

NC_MIPI_DFR_DATAP

36

NC_PCC_EVENT

35

NC_PCH_GCON_INT_L

35

NC_PCIE_CLK100M_ENETN

37

NC_PCIE_CLK100M_ENETP

37

NC_PCIE_CLK100M_SSD1_01N

37

NC_PCIE_CLK100M_SSD1_01P

37

NC_PCIE_CLK100M_SSD1_23N

37

NC_PCIE_CLK100M_SSD1_23P

37

NC_PCIE_CLK100M_WLANN

37

NC_PCIE_CLK100M_WLANP

37

NC_PCIE_ENET_D2RN

37

NC_PCIE_ENET_D2RP

37

NC_PCIE_ENET_R2D_CN

37

NC_PCIE_ENET_R2D_CP

37

NC_PCIE_SSD1_D2RN<3..0>

37

NC_PCIE_SSD1_D2RP<3..0>

37

NC_PCIE_SSD1_R2D_CN<3..0>

37

NC_PCIE_SSD1_R2D_CP<3..0>

37

NC_PCIE_WLAN_D2RN

37

NC_PCIE_WLAN_D2RP

37

NC_PCIE_WLAN_R2D_CN

37

NC_PCIE_WLAN_R2D_CP

37

NC_PCIEDN_WAKE_L

35

NC_PLCAM_PROX_INT_L

35

NC_PLCAM_ROMEO_B2B_DETECT

35

NC_PLCAM_RX_CLK12M_R

36

NC_PLCAM_RX_RESET_L

36

NC_PLCAM_TX_CLK12M_R

36

NC_PLCAM_TX_INT

36

NC_PLCAM_TX_RESET_L

36

NC_PLCAM_TX_THROTTLE

34

NC_SDCONN_STATE_CHANGE_L

35

NC_SMC_FAN_1_PWM

35

NC_SMC_FAN_1_TACH

35

NC_SMC_GFX_SELF_THROTTLE

35

NC_SMC_GFX_THROTTLE_L

35

NC_SMC_LED_ONEWIRE

35

NC_SPI_ALTIMETER_CS_L

35

NC_SSD1_CLK24M_R

37

NC_SSD1_CLKREQ0_L

37

NC_SSD1_CLKREQ1_L

37

NC_SSD1_CLKREQ2_L

37

NC_SSD1_CLKREQ3_L

37

NC_SSD1_PCIE_RESET_L

37

NC_SSD1_SWCLK_UART_R2D

35

NC_SSD1_SWDIO_UART_D2R

35

NC_TPAD_VIBE_L

35

NC_UART_GNSS_D2R_CTS_L

36

NC_UART_GNSS_R2D_RTS_L

36

NC_WLAN_CLKREQ_L

37

NC_WLAN_DEV_WAKE

34

NC_WLAN_PERST_L

37

NC_SPIROM_USE_MLB

15

NC_SPI_PCHROM_MOSI

14

NC_SPI_PCHROM_MISO

14

NC_SPI_PCHROM_IO<2>

14

NC_SPI_PCHROM_CS_L

14

NC_SPI_PCHROM_CLK

14

NC_SPI_DFR_MOSI_R

36

NC_SPI_DFR_MISO

36

NC_SPI_DFR_CS_L

36

NC_SPI_DFR_CLK_R

36

NC_SPI_DESCRIPTOR_OVERRIDE_L

35

NC_SMC_TOPBLK_SWP_L

35

NC_PCHROM_SW_EN

36

NC_PCH_STRP_TOPBLK_SWP_L

14

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1MAKE_BASE=TRUE

NO_TEST=1MAKE_BASE=TRUE

NO_TEST=1MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NO_TEST=1

NC_ALTIMETER_INT
NC_DFR_DISP_INT
NC_DFR_DISP_RESET_L
NC_DFR_DISP_TE
NC_DFR_PWR_EN
NC_DFR_TOUCH_CLK32K_RESET_L
NC_DFR_TOUCH_INT_L
NC_DFR_TOUCH_RESET_L
NC_DFR_TOUCH_RSVD
NC_DISP_GCON_INT_LNC_PCIE_CLK100M_DEBUGN
NC_ENET_LOW_PWR
NC_ENET_MEDIA_SENSE
NC_ENET_RESET_L
NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
NC_GNSS_DEV_WAKE
NC_GNSS_HOST_TIME
NC_GNSS_HOST_WAKE
NC_I2S_CODEC_MCLK
NC_I2S_CODEC1_MCLK
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK_R
NC_I2S_HAWKING_D2R
NC_I2S_HAWKING_LRCLK
NC_MESA_MENUKEY_L
NC_MIPI_DFR_CLKN
NC_MIPI_DFR_CLKP
NC_MIPI_DFR_DATAN
NC_MIPI_DFR_DATAP
NC_PCC_EVENT
NC_PCH_GCON_INT_L
NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_SSD1_01N
NC_PCIE_CLK100M_SSD1_01P
NC_PCIE_CLK100M_SSD1_23N
NC_PCIE_CLK100M_SSD1_23P
NC_PCIE_CLK100M_WLANN
NC_PCIE_CLK100M_WLANP
NC_PCIE_ENET_D2RN
NC_PCIE_ENET_D2RP
NC_PCIE_ENET_R2D_CN
NC_PCIE_ENET_R2D_CP
NC_PCIE_SSD1_D2RN<3..0>
NC_PCIE_SSD1_D2RP<3..0>
NC_PCIE_SSD1_R2D_CN<3..0>
NC_PCIE_SSD1_R2D_CP<3..0>
NC_PCIE_WLAN_D2RN
NC_PCIE_WLAN_D2RP
NC_PCIE_WLAN_R2D_CN
NC_PCIE_WLAN_R2D_CP
NC_PCIEDN_WAKE_L
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT
NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_INT
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_THROTTLE
NC_SDCONN_STATE_CHANGE_L
NC_SMC_FAN_1_PWM
NC_SMC_FAN_1_TACH
NC_SMC_GFX_SELF_THROTTLE
NC_SMC_GFX_THROTTLE_L
NC_SMC_LED_ONEWIRE
NC_SPI_ALTIMETER_CS_L
NC_SSD1_CLK24M_R
NC_SSD1_CLKREQ0_L
NC_SSD1_CLKREQ1_L
NC_SSD1_CLKREQ2_L
NC_SSD1_CLKREQ3_L
NC_SSD1_PCIE_RESET_L
NC_SSD1_SWCLK_UART_R2D
NC_SSD1_SWDIO_UART_D2R
NC_TPAD_VIBE_L
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L
NC_WLAN_CLKREQ_L
NC_WLAN_DEV_WAKE
NC_WLAN_PERST_L
NC_SPIROM_USE_MLB
NC_SPI_PCHROM_MOSI
NC_SPI_PCHROM_MISO
NC_SPI_PCHROM_IO<2>
NC_SPI_PCHROM_CS_L
NC_SPI_PCHROM_CLK
NC_SPI_DFR_MOSI_R
NC_SPI_DFR_MISO
NC_SPI_DFR_CS_L
NC_SPI_DFR_CLK_R
NC_SPI_DESCRIPTOR_OVERRIDE_L
NC_SMC_TOPBLK_SWP_L
NC_PCHROM_SW_EN
NC_PCH_STRP_TOPBLK_SWP_L

PU_DEBUG_CLKREQ_L

16

TP_SWD_WLAN_SWDIO

35

TP_SWD_WLAN_SWCLK

35

Grounded Signals

GND

36

GND

36

GND

36

GND

36

GND

36

GND

36

GND

36

GND

36

GND

65

PMIC GPIO Config Select

P2V7NAND_PGOOD

65

P2V7NAND_EN

65

NAND_DISCHARGE_EN

65

NAND_RESET_L

65

UVP_DIS_L

65

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PU_DEBUG_CLKREQ_L
TP_SWD_WLAN_SWDIO
TP_SWD_WLAN_SWCLK

P2V7NAND_PGOOD
P2V7NAND_EN
NAND_DISCHARGE_EN
NAND_RESET_L
UVP_DIS_L

Signal Aliases

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

122 OF 145

SHEET

77 OF 85

D

C

B

73

73

74

74

43

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

Memory Bit/Byte Swizzle

D

C

B

MAKE_BASE

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

22

BI

MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<47>
MEM_A_DQ<46> MEM_B_DQ<24>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<43>
MEM_A_DQ<45>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<57>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQ<63>
MEM_A_DQ<59>
MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<58>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<10>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<33>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<43>
MEM_A_DQ<45>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<57>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQ<63>
MEM_A_DQ<59>
MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<58>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<10>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<29>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MAKE_BASE

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

23

BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<25>

MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<58>
MEM_B_DQ<63>
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<4>
MEM_B_DQ<1>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<7>
MEM_B_DQ<3>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<8>
MEM_B_DQ<12>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<41>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<40>
MEM_B_DQ<44>

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<18>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<55>
MEM_B_DQ<50>
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<58>
MEM_B_DQ<63>
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<4>
MEM_B_DQ<1>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<7>
MEM_B_DQ<3>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DQ<9>
MEM_B_DQ<15>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<8>
MEM_B_DQ<12>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<41>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<40>
MEM_B_DQ<44>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

D

C

B

A

22

BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

22 7

BI BI

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

BI

7

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

SYNC_MASTER=J122_MLB SYNC_DATE=04/13/2018

PAGE TITLE

A

8

Memory Signal Swaps

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

PAGE

123 OF 145

SHEET

78 OF 85

1

SIZE

D

678

3 245

1

D

C

B

16

16

16

16

16

16

34 27

65 34 27

34 27

34 27

82 43 34 27

35 29 28

35

27 17

27 17

35 20

35 20

36

36

35

35

45 35

45 35

35

35

DFU/SoC/SWDL

TP_USB3_EXTB_D2R_N

BI
BI
BI

BI
BI

TP_USB3_EXTB_D2R_P
TP_USB3_EXTB_R2D_C_N
TP_USB3_EXTB_R2D_C_P

TP_USB_EXTC_N
TP_USB_EXTC_P

BI
BI
BI
BI
BI
BI
BI

SOC_USB_VBUS
SOC_FORCE_DFU
USB_SOC_N
USB_SOC_P
SOC_DFU_STATUS
SOC_DOCK_CONNECT
SOC_COLD_RESET_L
GND

Debug

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
DBGMUX_SWD_SOC_CLK
DBGMUX_SWD_SOC_IO
TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
I2C_PWR_SCL
I2C_PWR_SDA
TP_SMC_DEBUGPRT_RX
TP_SMC_DEBUGPRT_TX

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

GND_VOID=TRUE

2

1

FUNC_TEST=TRUE
FUNC_TEST=TRUE

7x

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

TP_USB3_EXTB_D2R_N
TP_USB3_EXTB_D2R_P
TP_USB3_EXTB_R2D_C_N
TP_USB3_EXTB_R2D_C_P

DSN2

CRITICAL

DC4B0

GND_VOID=TRUE

2

SESDL2011

1

DSN2

CRITICAL

2

SESDL2011

1

DC4B1

DSN2

GND_VOID=TRUE

CRITICAL

SESDL2011

DC4B2

2

1

TP_USB_EXTC_N
TP_USB_EXTC_P

GND_VOID=TRUE

CRITICAL

2

1

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

DC450

2

X3DFN2

1

ESD8011-COMBO

TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX

TP_SMC_DEBUGPRT_RX
TP_SMC_DEBUGPRT_TX

TP-P5
TP-P5
TP-P5
TP-P5

DSN2

GND_VOID=TRUE

CRITICAL

SESDL2011

DC4B3

TP-P5
TP-P5

GND_VOID=TRUE

CRITICAL

X3DFN2

DC451

ESD8011-COMBO

TP-P5
TP-P5
TP-P5
TP-P5

RIO -

Display

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

TPDC4B3
TPDC4B2
TPDC4B1
TPDC4B0

TPDC450
TPDC451

68 5

69 5

68

69 68

69 68

69 68

To be probed at connector

Backlight

BI
BI
BI
BI

BI
BI

EDP_BKLT_EN
EDP_BKLT_PWM
PPVIN_S0SW_LCDBKLT_R
PPVOUT_S0_LCDBKLT

I2C_BKLT_SCL
I2C_BKLT_SDA
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

82 79 65 57 52

5x

Power

80 30 27

80 30 27

80 76 58

80 58

80 79 76

80 79 75

1

TP

1

TP

1

TP

1

TP

TPDC4B7
TPDC4B6
TPDC4B5
TPDC4B4

80 76

80 79 76 62

80 79 76

80 79 76

80 75

80 76

80 76

80 75 74

80 75

80 27

80 76

75

75

76

75

75

27

76

75

75

75

75

75

35

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI

BI
BI
BI
BI
BI
BI

PP20V_USBC_XA_VBUS
PP20V_USBC_XB_VBUS
PPDCIN_G3H
PPDCIN_G3H_CHGR_AMON
PPBUS_G3H
PP1V8_SLPS2R
PP1V1_SLPDDR
PP1V8_AWAKE
PP3V3_G3H_RTC
PP3V3_G3H
PP3V_G3H
PP5V_G3S
PP3V3_G3S
PP1V8_G3S
PP1V8_S5
PP1V8_S3
PP1V2_S3

PP2V7_NAND
PP1V8_SSD
PP0V9_SSD
PP3V3_TBT_X_S0
PP3V3_TBT_X_SX

PP1V2_S0SW
PP1V_PRIM

PP1V2_AWAKE
PP0V82_SLPDDR
PPVDDCPU_AWAKE
PPVCC_PRIM_CORE
PPVCC_S0_CPU ACCEL_INT2

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=TRUE

TP_SMC_FIXTURE_MODE_L

TP_SMC_FIXTURE_MODE_L

FUNC_TEST=TRUE

GND

MAKE_BASE=TRUE
FUNC_TEST=TRUE

52 43

52 36

52 43

52 34

52 43 34

65 52

52 36

52 43

52 36

52 43

54 52 34

54 52 35

52 35

53 52 34

53 52 34

46 36

46 36

52 43

53 52 36

52 43

52 43

54 52 36

52 43

80 79 76

80 79 76

80 79 76

80 79 75

55 43

55 54

55 43

55 54

55 43

80 79 76

80 79 75

54 53

54 53

54 36

Speaker (R), Mesa, Headphone

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

SPI_MESA_CLK
SPI_MESA_MISO
SPI_MESA_MOSI
MESA_INT
MESA_PWR_EN
PMU_ONOFF_L
AUD_PWR_EN
I2S_CODEC_LRCLK
I2S_CODEC_R2D
I2S_CODEC_D2R
I2S_CODEC_BCLK
CODEC_INT_L
CODEC_WAKE_L
CODEC_RESET_L
SPKRAMP_RESET_L
SPKRAMP_INT_L
I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL
I2S_SPKRAMP_R_R2D
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_LRCLK_R
I2S_SPKRAMP_R_BCLK
SPKR_ID1
SMC_LID_RIGHT
PPBUS_G3H
PP3V3_G3S
PP1V8_G3S
PP1V8_SLPS2R
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

AMR/Mic

BI
BI
BI
BI
BI
BI
BI

PDM_DMIC_CLK0
PDM_DMIC_DATA0_ISOL
PDM_DMIC_CLK1
PDM_DMIC_DATA1_ISOL
SMC_LID_LEFT
PP1V8_G3S
PP1V8_SLPS2R
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

Speaker (L)

BI
BI
BI

SPKRCONN_L_OUTP
SPKRCONN_L_OUTN
SPKR_ID0
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

x

1x

1x

28

29

82 79 65 57 52

55 43

82 65 57 55

56 55

56 55

56 55

56 55

56 55

56 55

56

56 55

56 55

56 55

55

55

55

55

34 32 20

33 32

33 32

33 32

33 32

32

32

32

32

35 32

35 32

35 32

32

32

32

32

32

32

33

33

76

USBC

BI

BI

TP_Q3100_DRAIN
TP_Q3200_DRAIN
GND

IPD

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

PMU_ONOFF_L
IPD_LID_OPEN
PMU_RSLOC_RST_L
I2C_TPAD_3V3_SCL
I2C_TPAD_3V3_SDA
SPI_TPAD_3V3_CLK
SPI_TPAD_3V3_CS_L
SPI_TPAD_3V3_MISO
SPI_TPAD_3V3_MOSI
TPAD_3V3_ACTUATOR_DISABLE_L
TPAD_SPI_3V3_EN
TPAD_SPI_3V3_INT_L
TPAD_KBD_3V3_WAKE_L
PPBUS_G3H_TPAD_FLT
PP5V_G3S_IPD_F
PP3V3_G3H_IPD_F
PP3V3_G3S_IPD_F
GND

Wireless

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

WLAN_AUDIO_SYNC
UART_BT_MUX_R2D
UART_BT_MUX_D2R
UART_BT_MUX_CTS_L
UART_BT_MUX_RTS_L
SPI_BT_CLK
SPI_BT_CS_L
SPI_BT_MOSI
SPI_BT_MISO
WLAN_HOST_WAKE
WLAN_CONTEXT_A
WLAN_CONTEXT_B
WLAN_THROTTLE
WLAN_AUDIO_SYNC
TP_JTAG_WLAN_TCK
TP_JTAG_WLAN_TMS
TP_JTAG_WLAN_TRST
TP_BT_GPIO4
ACCEL_INT1

PP3V3_G3S_WLANBT
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

5x

D

2x

C

Power Sequencing

PLT_RST_L
PM_PCH_SYS_PWROK
PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PVDDQ_PGOOD
PVDDQ_EN
PMU_ACTIVE_READY
P1V1_SLPDDR_SOCFET_EN

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

B

51

51

80 79 76 62

BI
BI
BI

Fan

FAN_LT_PWM
FAN_LT_TACH
PP5V_G3S
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

1x

42 20 17 15 6

42 15

82 66 65 35 15

25 20 15 14 5

15

15

66 65

82 66 65

82 65 34 28

82 65 64

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

A

71

72

70

70

BI
BI
BI
BI

SSD

TP_SSD0_S4E1_UART_TX
TP_SSD0_S4E2_UART_TX
TP_SSD0_S4E0_UART_TX
TP_SSD0_S4E0_JTAG_TDI

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

TP_SSD0_S4E1_UART_TX
TP_SSD0_S4E2_UART_TX
TP_SSD0_S4E0_UART_TX
TP_SSD0_S4E0_JTAG_TDI

58

57

57

57

57

58 47

58

58

57

BI
BI
BI
BI
BI
BI
BI
BI

Battery

CHGR_HPWR_EN_L
SMBUS_3V3_BATT_SCL
SMBUS_3V3_BATT_SDA
SYS_DETECT
SYS_DETECT_L
CHGR_BMON
PPVBAT_G3H_CHGR_R
PPVBAT_G3H_CONN
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

BOM_COST_GROUP=DEBUG

5x
5x

82 67 65

42 35

65 34

BI

BI

BI

PAGE TITLE

P1V8G3S_EN
SMC_PCH_SYS_PWROK
SOC_SOCHOT_L

ICT FCT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

DRAWING NUMBER

051-04039

REVISION

BRANCH

PAGE

124 OF 145

SHEET

79 OF 85

A

SIZE

D

2.0.0

8

67

35 4

2

1

678

3 245

1

D

79 76

PPVCC_S0_CPU

1

CC740

12PF

5%
100V

2

C0G C0G
0201

1

CC741

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7G0

12PF

5%
100V

2

C0G
0201

1

CC742

3PF

+/-0.1PF +/-0.1PF
100V

2

0201

1

CC743

12PF

5%
100V

2

C0G
0201 0201

NOSTUFF

1

CC7G2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC744

3PF

100V

2

C0G
0201

1

CC745

12PF

5%
100V

2

C0G

1

CC7G4

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC746

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC747

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC7G6

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC748

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC749

12PF

5%
100V

2

C0G
0201

1

CC7G8

12PF

5%
100V

2

C0G
0201

1

CC750

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC751

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC7H0

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC752

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC753

12PF

5%
100V

2

C0G
0201

1

CC7H2

3.3PF

+/-0.1PF
16V

2

CERM
01005

1

CC754

12PF

5%
100V

2

C0G
0201

1

CC755

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC756

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC757

12PF

5%
100V

2

C0G
0201

1

CC758

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC759

12PF

5%
100V

2

C0G
0201

79 27

76

PP3V3_TBT_X_S0

1

CC720

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC721

12PF

5%
100V

2

C0G
0201

PPVIN_G3H_P3V3G3H

1

CC786

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC762

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC763

12PF

5%
100V

2

C0G
0201

1

CC7D4

3PF

+/-0.1PF
100V

2

C0G
0201

80 79 75

76

PP1V8_S5

1

CC722

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC723

12PF

5%
100V

2

C0G
0201

PPVIN_G3H_P5VG3S

1

CC788

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC724

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC725

12PF

5%
100V

2

C0G
0201

1

CC7D6

3PF

+/-0.1PF
100V

2

C0G
0201

79 76

PP3V3_G3H

1

CC730

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC731

12PF

5%
100V

2

C0G
0201

1

CC760

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC761

12PF

5%
100V

2

C0G
0201

D

C

79 75 74

PP1V8_SSD

1

CC7G1

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7A8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7A9

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC7G3

12PF

5%
100V

2

C0G
0201

1

CC7B0

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B1

12PF

5%
100V

2

C0G
0201

1

CC7G5

12PF

5%
100V

2

C0G
0201

1

CC7B2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B3

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC7G7

12PF

5%
100V

2

C0G
0201

1

CC7B4

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B5

12PF

5%
100V

2

C0G
0201

1

CC7G9

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B6

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B7

12PF

5%
100V

2

C0G
0201

79 76

NOSTUFF

1

CC7H1

12PF

5%
100V

2

C0G
0201

PPBUS_G3H

1

CC7H3

12PF

5%
16V

2

CER
01005

1

CC700

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC701

12PF

5%
100V

2

C0G
0201

1

CC702

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC703

12PF

5%
100V

2

C0G
0201

1

CC704

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC705

12PF

5%
100V

2

C0G
0201

1

CC706

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC707

12PF

5%
100V

2

C0G
0201

1

CC772

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC773

12PF

5%
100V

2

C0G
0201

1

CC778

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC779

12PF

5%
100V

2

C0G
0201

79 30 27

79 30 27

1

CC787

12PF

5%
100V

2

C0G
0201

PP20V_USBC_XA_VBUS

1

CC710

3PF

+/-0.1PF
100V

2

C0G
0201

PP20V_USBC_XB_VBUS

1

CC712

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D5

12PF

5%
100V

2

C0G
0201

1

CC711

12PF

5%
100V

2

C0G
0201

1

CC713

12PF

5%
100V

2

C0G
0201

1

2

PPBUS_G3H_TPAD

76

1

2

PPVCORE_S0_CPU_PH1

60

1

2

CC789

12PF

5%
100V
C0G
0201

CC776

3PF

+/-0.1PF
100V
C0G
0201

CC780

3PF

+/-0.1PF
100V
C0G
0201

1

CC7D7

12PF

5%
100V

2

C0G
0201

1

CC777

12PF

5%
100V

2

C0G
0201

1

CC781

12PF

5%
100V

2

C0G
0201

CHGR_PHASE1

58

CHGR_PHASE2

58

1

CC794

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC796

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC795

12PF

5%
100V

2

C0G
0201

1

CC797

12PF

5%
100V

2

C0G
0201

C

B

79 76 79 75

PP2V7_NAND PP0V9_SSD

1

CC7B8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7B9

12PF

5%
100V

2

C0G
0201

1

CC7A2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C0

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C1

12PF

5%
100V

2

C0G
0201

1

CC7A4

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C3

12PF

5%
100V

2

C0G
0201

1

CC7A6

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C4

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C5

12PF

5%
100V

2

C0G
0201

1

CC732

3PF

+/-0.1PF
100V

2

C0G
0201

79 76 62

PP5V_G3S

1

CC7C6

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C7

12PF

5%
100V

2

C0G
0201

1

CC714

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7C9

12PF

5%
100V

2

C0G
0201

1

CC716

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D0

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D1

12PF

5%
100V

2

C0G
0201

1

CC774

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D3

12PF

5%
100V

2

C0G
0201

80 79 76

79 76

79 75 76 60

PP1V2_S3

1

CC726

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC727

12PF

5%
100V

2

C0G
0201

PP1V8_G3S

1

CC766

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC767

12PF

5%
100V

2

C0G
0201

PP1V8_SLPS2RPPBUS_HS_CPU CPUCORE_PHASE1

1

CC768

3PF

+/-0.1PF
100V 100V

2

C0G
0201

1

CC769

12PF

5%

2

C0G
0201

60

80 58

PPVCORE_S0_CPU_PH2

1

CC782

3PF

+/-0.1PF
100V

2

C0G
0201

PPVBAT_G3H_FUSE

1

CC784

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC790

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC783

12PF

5%
100V

2

C0G
0201

1

CC785

12PF

5%
100V

2

C0G
0201

1

CC791

12PF

5%
100V

2

C0G
0201

62

62

79 58

P3V3G3H_VSW

1

CC798

3PF

+/-0.1PF
100V

2

C0G
0201

P5VG3S_VSW

1

CC7A0

3PF

+/-0.1PF
100V

2

C0G
0201

PPDCIN_G3H_CHGR_AMON

1

CC7D8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC799

12PF

5%
100V

2

C0G
0201

1

CC8A1

12PF

5%
100V

2

C0G
0201

1

CC7D9

12PF

5%
100V

2

C0G
0201

B

A

80 79 76

PP1V2_S3

1

CC7A3

12PF

5%
100V

2

C0G
0201

1

CC728

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC729

12PF

5%
100V

2

C0G
0201

1

CC7A5

12PF

5%
100V

2

C0G
0201

1

CC7E2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7E3

12PF

5%
100V

2

C0G
0201

1

CC7A7

12PF

5%
100V

2

C0G
0201

1

CC7E4

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7E5

12PF

5%
100V

2

C0G
0201

1

CC733

12PF

5%
100V

2

C0G
0201

1

CC7E6

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7E7

12PF

5%
100V

2

C0G
0201

1

CC7E8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7E9

12PF

5%
100V

2

C0G
0201

1

CC7F0

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7F1

12PF

5%
100V

2

C0G
0201

1

CC715

12PF

5%
100V

2

C0G
0201

1

CC7F2

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7F3

12PF

5%
100V

2

C0G
0201 0201

1

2

1

2

1

2

CC717

12PF

5%
100V
C0G
0201

CC7F4

3PF

+/-0.1PF
100V
C0G
0201

CC7F5

12PF

5%
100V
C0G

1

CC775

12PF

5%
100V

2

C0G
0201

1

CC7F6

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7F7

12PF

5%
100V

2

C0G
0201

80 58

79 76

PPVBAT_G3H_FUSE

1

CC770

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC708

3PF

+/-0.1PF
100V

2

C0G
0201

PP3V3_G3S

1

CC765

12PF

5%
100V

2

C0G
0201

1

CC771

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC709

12PF

5%
100V

2

C0G
0201

CPUCORE_PHASE2

60

PP3V3_G3H_PMU_VDDMAINPPDCIN_G3H

76 79 76 58

BOM_COST_GROUP=DESENSE

1

CC792

3PF

+/-0.1PF
100V

2

C0G
0201

NOSTUFF

1

CC718

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC793

12PF

5%
100V

2

C0G
0201

NOSTUFF

1

CC719

12PF

5%
100V

2

C0G
0201

80 79 75

PAGE TITLE

PP1V8_S5

1

CC7E0

3PF

+/-0.1PF
100V

2

C0G
0201

Desense Caps 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

CC7E1

12PF

5%
100V

2

C0G
0201

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

051-04039

2.0.0

127 OF 145

80 OF 85

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

PPVCCGT_S0_CPU

76

1

CC800

12PF

5%
100V

2

C0G
0201

1

CC801

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC820

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC802

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC803

12PF

5%
100V

2

C0G
0201

1

CC822

3.3PF

+/-0.1PF
16V

2

CERM
01005

1

CC804

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC805

12PF

5%
100V

2

C0G
0201

1

CC806

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC807

12PF

5%
100V

2

C0G
0201

1

CC808

3PF

+/-0.1PF
100V

2

0201

1

CC809

12PF

5%
100V

2

C0G
0201

1

CC810

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC811

12PF

5%
100V

2

C0G
0201

1

CC812

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC813

12PF

5%
100V

2

C0G
0201

1

CC814

12PF

5%
100V

2

C0G
0201

1

CC815

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC816

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC817

12PF

5%
100V

2

C0G
0201

1

CC818

3PF

+/-0.1PF
100V

2

C0GC0G
0201

1

CC819

12PF

5%
100V

2

C0G
0201

CPUSA_SW_LL

60

1

CC880

3PF

+/-0.1PF
100V

2

C0G
0201

PPVCCSA_S0_CPU

76

1

CC882

3PF

+/-0.1PF
100V

2

C0G
0201

PP0V95_S0_CPUVCCIO_REG_R

66

1

CC884

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC881

12PF

5%
100V

2

C0G
0201

1

CC883

12PF

5%
100V

2

C0G
0201

1

CC885

12PF

5%
100V

2

C0G
0201

D

C

PP0V6_S0_DDRVTT

76

1

CC821

12PF

5%
100V

2

C0G
0201

1

CC830

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC831

12PF 12PF

5%
100V

2

C0G
0201

1

2

1

2

1

2

CC823

12PF

5%
16V
CER
01005

CC832

3PF

+/-0.1PF
100V
C0G
0201

CC833

5%
100V
C0G
0201

1

CC834

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC835

12PF

5%
100V

2

C0G
0201

1

CC836

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC837

12PF

5%
100V

2

C0G
0201

1

CC838

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC839

12PF

5%
100V

2

C0G
0201

1

CC840

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC841

12PF

5%
100V

2

C0G
0201

1

CC842

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC843

12PF

5%
100V

2

C0G
0201

1

CC844

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC845

12PF

5%
100V

2

C0G
0201

C

B

B

A

8

A

PAGE TITLE

Desense Caps 2

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DESENSE

67

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

PAGE

128 OF 145

SHEET

81 OF 85

1

SIZE

D

678

3 245

DBG_LED

1

D

C

PP0V9_SLPDDR

75

PP0V82_SLPDDR

75

PPVCC_PRIM_CORE

75

PP1V_PRIM

75

Remote Sense Support

XWE095

SHORT-12L-0.1MM-SM

2 1

XWE096

SHORT-12L-0.1MM-SM

2 1

P0V8SLPDDR_FB_R P0V8SLPDDR_FB

XWE097

SHORT-12L-0.1MM-SM

2 1

PVCCPCOREPRIM_FB_R_P

XWE098

SHORT-12L-0.1MM-SM

2 1

PVCCPCOREPRIM_FB_R_N

XWE099

SHORT-12L-0.1MM-SM

2 1

P1VPRIM_FB_R

RE095

0

21

5%

1/20W

MF

0201

RE096

0

21

5%

1/20W

MF

0201

RE097

0

21

5%

1/20W

MF

0201

RE098

0

21

5%

1/20W

MF

0201

RE099

0

21

5%

1/20W

MF

0201

P0V9SLPDDR_FBP0V9SLPDDR_FB_R

NO_XNET_CONNECTION=1

NO_XNET_CONNECTION=1

PVCCPCOREPRIM_FB_P

NO_XNET_CONNECTION=1

PVCCPCOREPRIM_FB_N

NO_XNET_CONNECTION=1

P1VPRIM_FB

NO_XNET_CONNECTION=1

OUT

OUT

OUT

OUT

OUT

63

63

63

63

63

63 75

82 79 65 64

63 75

79 43 34 27

SOC State LEDs

PP1V8_SLPS2R

DBG_LED

P1V1_SLPDDR_SOCFET_EN

DBG_LED

PP1V8_AWAKE

DBG_LED

SOC_DFU_STATUS

DBG_LED

PP3V3_G3H

76 82

RE009

0

VOLTAGE=3.3V

21

PP3V3_G3H_DEBUGLED_SOC

0201MF5% 1/20W

DBG_LED

DE000

LTST-C32JBGEW

SM

4

1

R

G

3

B

2

DBG_LED

A

DE001

AMBER-605NM-35-56MCD
LTST-C281KFKT-SM

K

D

QE000

2

G

DMN5L06VK-7

SOT563

VER 5

DBG_LED

RE000

DS

SOC_SLPS2R_RED

1

6

QE000

5

G

DMN5L06VK-7

SOT563

VER 5

2.1K

1%

1/20W

MF

201

DBG_LED

21

SOC_SLPS2R_RED_R

RE001

DS

3

4

SOC_SLPDDR_GREEN

QE001

2

G

DMN5L06VK-7

SOT563

VER 5

4.75K

1%

1/20W

MF

201

DBG_LED

21

SOC_SLPDDR_GREEN_R

RE002

DS

SOC_AWAKE_BLUE

1

6

QE001

5

G

4

DMN5L06VK-7

SOT563

VER 5

DS

3

SOC_DFU_AMBER

4.75K

1%

1/20W

MF

201

DBG_LED

RE003

5.1K

1%

1/20W

MF

201

21

SOC_AWAKE_BLUE_R

21

SOC_DFU_AMBER_R

C

B

PP3V3_G3H

76 82

79 65 34 28

82 79 65 64

79 66 65 35 15

79 66 65

79 67 65

IN

IN

IN

IN

IN

RE059

DBG_LED

VOLTAGE=3.3V

21

PP3V3_G3H_DEBUGLED_R PP3V3_G3H_DEBUGLED_RR

02011/20W0MF5%

BYPASS=UE050::5mm

PMU_ACTIVE_READY
P1V1_SLPDDR_SOCFET_EN
PM_SLP_S0_L
PVDDQ_EN
P1V8G3S_EN

System State LED

RE063

0

21

0201MF1/20W

SYS_STATE_RED_R
SYS_STATE_GREEN_R
SYS_STATE_BLUE_R

NC
NC
NC
NC

CE050

0.1UF

10%

10V

X5R-CERM

0201

DBG_LED

1

2

SLG4AP41990

2

PMU_ACTIVE_READY

3

P1V1_SLPDDR_SCFET_EN

4

PM_SLP_S0*

5

PVDDQ_EN

6

P1V8G3S_EN

1

VDD

UE050

STQFN

DBG_LED

GND

8

5%

R
G
B

RFU1
RFU2
RFU3
RFU4

DBG_LED

12
11
10

7
9
13
14

VOLTAGE=3.3V

DBG_LED

RE060

DBG_LED

RE061

DBG_LED

RE062

2.1K

1% 1/20W MF 201

5.1K

1/20W1%

4.75K

1%

21

21

201MF

21

201MF1/20W

DBG_LED

DE050

LTST-C32JBGEW

SM

SYS_STATE_RED

SYS_STATE_GREEN

SYS_STATE_BLUE

1

R

4

G

3

B

2

B

Dev Buttons

SWE010

SOX-152HNT

SM

21

PMU_ONOFF_L

79 65 57 52

SWE001

SOX-152HNT

SM

21

PMU_RSLOC_RST_L

79 65 57 55

A

PMU

ACT RDY

0
0
1
0
1
1
1

P1V1_SLPDDR

SOCFET_EN

0
0
1
0
1
1
1

Inputs

PM_SLP

S0_L

0
0
0
0
0
1
0

PVDDQ P1V8G3S

EN

0
0
0
1
1
1
0

EN

0
1
1
1
1
1
0

BLINK

ON
ON
ON
OFF
OFF

BLINK

Outputs

G BR

OFF
OFF
ON
ON
OFF
ON
ON

OFF
OFF
OFF
ON
ON
OFF
OFF

Color

Blinking

Red
Red
Yellow
White
Blue
Green
Blinking

Yellow

&

Green

All other states are magenta

State

System CPUSoC

Shutdown (G3H)
Standby (G3S)
Standby (G3S)
Sleep
Sleep
Run

SLPS2R
AWAKE
SLPS2R
AWAKE
AWAKE

OFFOFF
OFF
OFF
S0i
S0i
S0

DBG_BTN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

IV ALL RIGHTS RESERVED

DBG_BTN

Dev Support

Apple Inc.

SYNC_DATE=04/12/2017SYNC_MASTER=X589_BIGSUR

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

140 OF 145

SHEET

82 OF 85

A

SIZE

D

8

67

35 4

2

1

678

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00251 MLB_COMMONCOMMON PARTS,MLB_BTTF,X1032

DBG_BTN,DBG_LED,UPC_DBG_HDR985-00733 DEV PARTS,MLB_BTTF,X1032

939-06596 PCBA,MLB-BTTF,DCDC,X1032

ALTERNATE,COMMON,DEV_PARTS_BOM,SCHEM,PCBF,CPU_AMLY:INTERPOSER,MLB_POWER,MLB_MISC,MLB_MECH1,PREEVT2

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

3 245

1

D

C

B

EEEE
K6GN
KLTM
KLV0
KLVD
KLVV
KLW7
KLWL
KLWY
KLX9
KLXN
KLY1
KLYD
KLYQ
KM04
KM0L
KM10
KM1F
KM1R
KM24
KM2H
KM2V
KM39
KM3Q
KM47
KM4Q
KM55
KM5J
KM5W
KM67
KM6L
KM6Y
KM79
KM7N
KM81
KM8D
KM8Q
KM93
KM9G
KM9T
KMC5
KMCJ
KMCW

BOM NUMBER BOM NAME BOM OPTIONS

639-06259

639-06565 PCBA,MLB,BEST,SS-8G,TO-128G,X1032

639-06572 PCBA,MLB,BEST,HY-8G,SD-256G,X1032

639-06583 PCBA,MLB,BEST,SS-16G,TO-256G,X1032

PCBA,MLB,BEST,HY-8G,SD-128G,X1032 PCBA,MLB,BTTR,HY-8G,SD-128G,X1032639-06602
PCBA,MLB,BEST,HY-8G,TO-128G,X1032639-06561
PCBA,MLB,BEST,MI-8G,SD-128G,X1032639-06562
PCBA,MLB,BEST,MI-8G,TO-128G,X1032639-06563
PCBA,MLB,BEST,SS-8G,SD-128G,X1032639-06564

PCBA,MLB,BEST,HY-16G,SD-128G,X1032639-06566
PCBA,MLB,BEST,HY-16G,TO-128G,X1032639-06567
PCBA,MLB,BEST,MI-16G,SD-128G,X1032639-06568
PCBA,MLB,BEST,MI-16G,TO-128G,X1032639-06569
PCBA,MLB,BEST,SS-16G,SD-128G,X1032639-06570
PCBA,MLB,BEST,SS-16G,TO-128G,X1032639-06571

PCBA,MLB,BEST,HY-8G,TO-256G,X1032639-06573
PCBA,MLB,BEST,MI-8G,SD-256G,X1032639-06574
PCBA,MLB,BEST,MI-8G,TO-256G,X1032639-06575
PCBA,MLB,BEST,SS-8G,SD-256G,X1032639-06576
PCBA,MLB,BEST,SS-8G,TO-256G,X1032639-06577
PCBA,MLB,BEST,HY-16G,SD-256G,X1032639-06578
PCBA,MLB,BEST,HY-16G,TO-256G,X1032639-06579
PCBA,MLB,BEST,MI-16G,SD-256G,X1032639-06580
PCBA,MLB,BEST,MI-16G,TO-256G,X1032639-06581
PCBA,MLB,BEST,SS-16G,SD-256G,X1032639-06582

PCBA,MLB,BEST,HY-8G,SD-512G,X1032639-06584
PCBA,MLB,BEST,HY-8G,TO-512G,X1032639-06585
PCBA,MLB,BEST,MI-8G,SD-512G,X1032639-06586
PCBA,MLB,BEST,MI-8G,TO-512G,X1032639-06587
PCBA,MLB,BEST,SS-8G,SD-512G,X1032639-06588
PCBA,MLB,BEST,SS-8G,TO-512G,X1032639-06589
PCBA,MLB,BEST,HY-16G,SD-512G,X1032639-06590
PCBA,MLB,BEST,HY-16G,TO-512G,X1032639-06591
PCBA,MLB,BEST,MI-16G,SD-512G,X1032639-06592
PCBA,MLB,BEST,MI-16G,TO-512G,X1032639-06593
PCBA,MLB,BEST,SS-16G,SD-512G,X1032639-06594
PCBA,MLB,BEST,SS-16G,TO-512G,X1032639-06595
PCBA,MLB,BEST,HY-8G,SS-1.5T,X1032639-06596
PCBA,MLB,BEST,MI-8G,SS-1.5T,X1032639-06597
PCBA,MLB,BEST,SS-8G,SS-1.5T,X1032639-06598
PCBA,MLB,BEST,HY-16G,SS-1.5T,X1032639-06599
PCBA,MLB,BEST,MI-16G,SS-1.5T,X1032639-06600
PCBA,MLB,BEST,SS-16G,SS-1.5T,X1032639-06601

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:HYNIX_16GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:MICRON_16GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKN,DRAMCFG:SAMSUNG_16GB,NANDCFG:3DV4_1P5T_SS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated

Deactivated
Deactivated

EEEE
KMD7
KMDL
KMDY
KMF9
KMFN
KMG1
KMGD
KMGQ
KMH3
KMHG
KMHT
KMJ5
KMJK
KMJX
KMK8
KMKM
KML0
KMLC
KMLP
KMM2
KMMF
KMMR
KMN4
KMNH
KMNV
KMP6
KMPK
KMPX
KMQ8
KMQM
KMR0
KMRC
KMRP
KMT2
KMTF
KMTR
KMV4
KMVL
KMVY
KMW9
KMWN
KMX1

BOM NUMBER BOM NAME BOM OPTIONS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_SD

PCBA,MLB,BTTR,HY-8G,TO-128G,X1032639-06603
PCBA,MLB,BTTR,MI-8G,SD-128G,X1032639-06604
PCBA,MLB,BTTR,MI-8G,TO-128G,X1032639-06605
PCBA,MLB,BTTR,SS-8G,SD-128G,X1032639-06606
PCBA,MLB,BTTR,SS-8G,TO-128G,X1032639-06607
PCBA,MLB,BTTR,HY-16G,SD-128G,X1032639-06608
PCBA,MLB,BTTR,HY-16G,TO-128G,X1032639-06609
PCBA,MLB,BTTR,MI-16G,SD-128G,X1032639-06610
PCBA,MLB,BTTR,MI-16G,TO-128G,X1032639-06611
PCBA,MLB,BTTR,SS-16G,SD-128G,X1032639-06612
PCBA,MLB,BTTR,SS-16G,TO-128G,X1032639-06613
PCBA,MLB,BTTR,HY-8G,SD-256G,X1032639-06614
PCBA,MLB,BTTR,HY-8G,TO-256G,X1032639-06615
PCBA,MLB,BTTR,MI-8G,SD-256G,X1032639-06616
PCBA,MLB,BTTR,MI-8G,TO-256G,X1032639-06617
PCBA,MLB,BTTR,SS-8G,SD-256G,X1032639-06618
PCBA,MLB,BTTR,SS-8G,TO-256G,X1032639-06619
PCBA,MLB,BTTR,HY-16G,SD-256G,X1032639-06620
PCBA,MLB,BTTR,HY-16G,TO-256G,X1032639-06621
PCBA,MLB,BTTR,MI-16G,SD-256G,X1032639-06622
PCBA,MLB,BTTR,MI-16G,TO-256G,X1032639-06623
PCBA,MLB,BTTR,SS-16G,SD-256G,X1032639-06624
PCBA,MLB,BTTR,SS-16G,TO-256G,X1032639-06625
PCBA,MLB,BTTR,HY-8G,SD-512G,X1032639-06626
PCBA,MLB,BTTR,HY-8G,TO-512G,X1032639-06627
PCBA,MLB,BTTR,MI-8G,SD-512G,X1032639-06628
PCBA,MLB,BTTR,MI-8G,TO-512G,X1032639-06629
PCBA,MLB,BTTR,SS-8G,SD-512G,X1032639-06630
PCBA,MLB,BTTR,SS-8G,TO-512G,X1032639-06631
PCBA,MLB,BTTR,HY-16G,SD-512G,X1032639-06632
PCBA,MLB,BTTR,HY-16G,TO-512G,X1032639-06633
PCBA,MLB,BTTR,MI-16G,SD-512G,X1032639-06634
PCBA,MLB,BTTR,MI-16G,TO-512G,X1032639-06635
PCBA,MLB,BTTR,SS-16G,SD-512G,X1032639-06636

PCBA,MLB,BTTR,SS-16G,TO-512G,X1032639-06637
639-06638 PCBA,MLB,BTTR,HY-8G,SS-1.5T,X1032
639-06639 PCBA,MLB,BTTR,MI-8G,SS-1.5T,X1032

PCBA,MLB,BTTR,SS-8G,SS-1.5T,X1032639-06640
639-06641 PCBA,MLB,BTTR,HY-16G,SS-1.5T,X1032

PCBA,MLB,BTTR,MI-16G,SS-1.5T,X1032639-06642

PCBA,MLB,BTTR,SS-16G,SS-1.5T,X1032639-06643

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:HYNIX_16GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:MICRON_16GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKP,DRAMCFG:SAMSUNG_16GB,NANDCFG:3DV4_1P5T_SS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

C

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated
Deactivated

B

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated

Deactivated
Deactivated

A

8

A

PAGE TITLE

BOM Variants 1

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

PAGE

141 OF 145

SHEET

83 OF 85

1

SIZE

D

BOM Variants

678

3 245

1

D

C

B

EEEE
KMXD
KMXQ
KMY4
KMYH
KMYV
KN06
KN0L
KN0Y
KN19
KN1N
KN22
KN2F
KN2R
KN34
KN3J
KN3Y
KN4F
KN4X
KN5C
KN5P
KN62
KN6F
KN6R
KN74
KN7H
KN7V
KN86
KN8M
KN90
KN9C
KN9P
KNC2
KNCF
KNCR
KND4
KNDJ
KNDX
KNF8
KNFM
KNG0
KNGC

BOM NUMBER BOM NAME BOM OPTIONS

639-06644 PCBA,MLB,GOOD,HY-8G,SD-128G,X1032
639-06645 PCBA,MLB,GOOD,HY-8G,TO-128G,X1032
639-06646 PCBA,MLB,GOOD,MI-8G,SD-128G,X1032
639-06647 PCBA,MLB,GOOD,MI-8G,TO-128G,X1032
639-06648 PCBA,MLB,GOOD,SS-8G,SD-128G,X1032
639-06649 PCBA,MLB,GOOD,SS-8G,TO-128G,X1032
639-06650 PCBA,MLB,GOOD,HY-16G,SD-128G,X1032
639-06651 PCBA,MLB,GOOD,HY-16G,TO-128G,X1032

PCBA,MLB,GOOD,MI-16G,SD-128G,X1032639-06652
PCBA,MLB,GOOD,MI-16G,TO-128G,X1032639-06653
PCBA,MLB,GOOD,SS-16G,SD-128G,X1032639-06654
PCBA,MLB,GOOD,SS-16G,TO-128G,X1032639-06655
PCBA,MLB,GOOD,HY-8G,SD-256G,X1032639-06656
PCBA,MLB,GOOD,HY-8G,TO-256G,X1032639-06657
PCBA,MLB,GOOD,MI-8G,SD-256G,X1032639-06658
PCBA,MLB,GOOD,MI-8G,TO-256G,X1032639-06659
PCBA,MLB,GOOD,SS-8G,SD-256G,X1032639-06660
PCBA,MLB,GOOD,SS-8G,TO-256G,X1032639-06661
PCBA,MLB,GOOD,HY-16G,SD-256G,X1032639-06662
PCBA,MLB,GOOD,HY-16G,TO-256G,X1032639-06663
PCBA,MLB,GOOD,MI-16G,SD-256G,X1032639-06664
PCBA,MLB,GOOD,MI-16G,TO-256G,X1032639-06665
PCBA,MLB,GOOD,SS-16G,SD-256G,X1032639-06666
PCBA,MLB,GOOD,SS-16G,TO-256G,X1032639-06667
PCBA,MLB,GOOD,HY-8G,SD-512G,X1032639-06668
PCBA,MLB,GOOD,HY-8G,TO-512G,X1032639-06669
PCBA,MLB,GOOD,MI-8G,SD-512G,X1032639-06670
PCBA,MLB,GOOD,MI-8G,TO-512G,X1032639-06671
PCBA,MLB,GOOD,SS-8G,SD-512G,X1032639-06672
PCBA,MLB,GOOD,SS-8G,TO-512G,X1032639-06673
PCBA,MLB,GOOD,HY-16G,SD-512G,X1032639-06674
PCBA,MLB,GOOD,HY-16G,TO-512G,X1032639-06675
PCBA,MLB,GOOD,MI-16G,SD-512G,X1032639-06676
PCBA,MLB,GOOD,MI-16G,TO-512G,X1032639-06677
PCBA,MLB,GOOD,SS-16G,SD-512G,X1032639-06678
PCBA,MLB,GOOD,SS-16G,TO-512G,X1032639-06679
PCBA,MLB,GOOD,HY-8G,SS-1.5T,X1032639-06680
PCBA,MLB,GOOD,MI-8G,SS-1.5T,X1032639-06681
PCBA,MLB,GOOD,SS-8G,SS-1.5T,X1032639-06682
PCBA,MLB,GOOD,HY-16G,SS-1.5T,X1032639-06683
PCBA,MLB,GOOD,MI-16G,SS-1.5T,X1032639-06684

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:PMLC_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_8GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:HYNIX_16GB,NANDCFG:3DV4_1P5T_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:MICRON_16GB,NANDCFG:3DV4_1P5T_SS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

C

Deactivated
Deactivated

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated
Deactivated

B

Deactivated
Deactivated
Deactivated
Deactivated

Deactivated

Deactivated

A

KNGP

PCBA,MLB,GOOD,SS-16G,SS-1.5T,X1032639-06685

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_AMLY:SREKQ,DRAMCFG:SAMSUNG_16GB,NANDCFG:3DV4_1P5T_SS

Deactivated

A

PAGE TITLE

BOM Variants 2

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-04039

REVISION

2.0.0

BRANCH

PAGE

142 OF 145

SHEET

84 OF 85

8

67

35 4

2

1

Alternates

678

3 245

1

D

C

B

PART NUMBER

107S00033

128S00087 ALL

152S00785 152S00477 ALL

152S00182 152S00703 ALL

128S00062 128S00067 ALL

128S00065 ALL

128S00039 ALL128S00038

128S0302

128S0631 ALL128S0352

152S00807

152S00734 ALL

107S00015 ALL107S00011

128S0392 128S0436 ALL

128S00043

128S00058 ALL

311S00060 ALL311S0273

138S1101

107S00034 ALL

107S00044

107S0085 ALL107S00070

107S0178

128S00011

128S00011

128S00011

197S00118197S00120 ALL

152S00265152S00708 ALL

128S00081128S0264 ALL

128S00081128S0364 ALL

128S00067 ALL128S00069

128S00067

152S00730

376S00012376S00303

107S00087107S00029 ALL

376S1038376S00302 ALL

376S00203 ALL376S00227

376S00203 ALL376S00204

376S00203376S00226 ALL

152S00268 ALL152S00800

128S0436128S0445

128S0311

128S0311128S0329 ALL

128S00018

376S1179376S00007 ALL 107S00005 ALL

376S1179376S00228 ALL

138S00073 ALL138S00047

138S00060138S00084 ALL

138S0648 ALL138S0703

353S00796 ALL353S00497

197S00036197S00047 ALL

197S00036197S00048 ALL

197S00036 ALL197S00046

371S00077 ALL371S00180

138S0884 ALL138S00086

ALL107S00076

ALL107S00139

ALL107S0248 107S0250

ALL128S00026

ALL128S00031

ALL152S00269152S00368

ALL152S00786 152S00344

ALL128S00038

ALL152S00837

ALL

ALL

ALL128S00042

ALL128S0311

ALL138S0738

ALL138S0831138S00049

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/31026333

rdar://problem/31026474

rdar://problem/31026832

rdar://problem/31026896

rdar://problem/31026938

rdar://problem/31104542

rdar://problem/31104542

rdar://problem/31104542

rdar://problem/32474316

rdar://problem/32986667

rdar://problem/32986857

rdar://problem/32988704

rdar://problem/32988930

rdar://problem/32989310

rdar://problem/32981497

rdar://problem/32981497

rdar://problem/31160233

rdar://problem/31160233

rdar://problem/31160233

rdar://problem/32984088

rdar://problem/32984088

rdar://problem/32984967

rdar://problem/33018005

rdar://problem/32986265

Per Peter H

rdar://problem/33006397

rdar://problem/33006830

rdar://problem/33008171

rdar://problem/32990227

rdar://problem/32990227

rdar://problem/32990227

rdar://problem/32986455

rdar://problem/32981936

rdar://problem/32981936

rdar://problem/32982452

rdar://problem/32982452

rdar://problem/32982452

rdar://problem/32983704

rdar://problem/33006121

rdar://problem/33006121

rdar://problem/31227780

rdar://problem/31227858

rdar://problem/31228419

rdar://problem/31285876

rdar://problem/31509365

rdar://problem/31509365

rdar://problem/31509365

rdar://problem/31512477

rdar://problem/31491081

rdar://problem/31927114

rdar://problem/31284882

rdar://problem/31285557

TABLE_ALT_HEAD

Vendor

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Yageo

TABLE_ALT_ITEM

TDK

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Rohm

TABLE_ALT_ITEM

Epson

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

Rohm

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

Chilisin Cyntec

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Rohm

TABLE_ALT_ITEM TABLE_ALT_ITEM

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Epson

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

PrimaryAlternate
Vendor

Cyntec
Cyntec
Murata
Murata
Cyntec
Kemet
Kemet
Kemet
TXC
Cyntec
Cyntec
Murata
Murata
Chilisin
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Kemet
Kemet
Panasonic
NEC

TIDiodes
Cyntec
Yageo
TI
Vishay
Vishay
Vishay
Cyntec
Kemet
Panasonic
NEC
NEC
NEC
NEC
VishayAOS
Vishay
Murata
Murata
Taiyo
Fairchild
TXC
TXC
TXC
Philips
Samsung
NXP
Murata

PART NUMBER

138S00077

138S00093 ALL138S00035

132S00012 132S0401

138S00015 138S0777 ALL

138S0847138S0786 ALL

152S00204152S00398 ALL

152S00311152S00724 ALL

152S00592152S00726 ALL

152S00590152S00725

371S00089 ALL

155S00007 ALL

376S00219 ALL376S00079

311S00013 ALL311S0508

155S00067

311S00121 ALL

371S00127 ALL

138S00056

353S01041 ALL

311S00156 311S00129

138S0846

376S1106 ALL376S0678

371S00074

311S0426 ALL311S00007

138S0945 ALL138S0706

311S00138

335S00270 335S00203

335S00213 335S0888

378S00029 ALL378S00002

197S00053

197S00054 ALL

197S00055 ALL

371S00085

155S0914155S00190

155S0667

155S0894155S00203 ALL

740S00002 ALL740S00033

740S00028740S0118 ALL

138S0986 ALL138S00024

155S0391 ALL155S00166

311S0398

371S00182

311S00091311S00104

353S01042

107S00086107S00056 ALL

138S0860138S0775 ALL

376S0604 ALL376S1053

152S00253

740S0159740S00041

371S0602 ALL

132S0640

155S00232155S0665

197S00050

197S00050

138S0942138S0754 ALL

ALL138S00035

ALL

ALL

ALL

ALL155S00401

ALL155S0361155S0741

ALL138S1100

ALL

ALL

ALL138S0811

ALL152S00359

ALL

ALL132S00176

ALL138S0706138S0739

ALL

ALL311S0436

ALL

ALL311S00029311S00175

ALL

ALL197S00050

ALL311S00178 311S00177

ALL132S0238 132S00181

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/31167038

rdar://problem/31167038

rdar://problem/31180314

rdar://problem/31254330

rdar://problem/31253709

rdar://problem/33011314

rdar://problem/33011211

rdar://problem/33011437

rdar://problem/33011526

rdar://problem/31927389

rdar://problem/32364855

rdar://problem/32415629

rdar://problem/32435328

rdar://problem/32435733

rdar://problem/32476985

rdar://problem/32477535

rdar://problem/32477706

rdar://problem/31410587

Per CE

rdar://problem/32406745

rdar://problem/32407296

rdar://problem/32474809

rdar://problem/36311626

rdar://problem/31411109

rdar://problem/31509861

rdar://problem/31816775

rdar://problem/31941459

rdar://problem/39511087

Per Peter Hazucha

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/33675478

rdar://problem/33924830

rdar://problem/31253813

rdar://problem/31253813

rdar://problem/32364084

rdar://problem/32474939

rdar://problem/33516617

rdar://problem/33857884

rdar://problem/33927828

rdar://problem/33932183

rdar://problem/33931383

rdar://problem/33931383

rdar://problem/33931383

rdar://problem/39513462

Per Peter H

rdar://problem/34016553

TABLE_ALT_HEAD

Alternate
Vendor

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Murata/TDK

TABLE_ALT_ITEM

Samsung/Taiyo

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

TI

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Thinking

TABLE_ALT_ITEM

Polytronics

TABLE_ALT_ITEM

Taiyo/TDK

TABLE_ALT_ITEM

TDK

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

TDK

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

Taiyo/TDK

TABLE_ALT_ITEM

TI

TABLE_ALT_ITEM

ST

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Bourns

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Infineon

TABLE_ALT_ITEM

Yageo

TABLE_ALT_ITEM

NXP

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

Adesto

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

On Semi

TABLE_ALT_ITEM

Lite-On

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

NDK

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Murata

Primary
Vendor

Murata
Murata
Taiyo
Murata

Murata/Taiyo

Cyntec
Cyntec
Cyntec
Cyntec
ON Semi

Panasonic

Panasonic
Murata
Fairchild

NXP/Nexperia

Murata
Bussman
Murata
Murata
TDK
Murata

NXP/Nexperia

Diodes
Murata
ON Semi
TI
TI
TFT
Murata
Murata
Fairchild
Cyntec
Littlefuse
Vishay
NXP
Murata
Diodes
Murata
Murata
TDK
TI
Macronix
Diodes
STMicro
Everlight
TXC
TXC
TXC
TIOn Semi
Murata
Yageo

PART NUMBER

ALL138S00073 138S0942

138S00047 ALL138S0942

152S00403 ALL152S00322

ALL372S00015372S00016

376S1080 ALL376S0820

ALL376S00074 376S0855

353S01320

107S0240 ALL107S0255

152S00765 ALL152S00239

377S00123

376S1137 ALL

353S00711 ALL

353S00712

311S0372 311S0562 ALL

376S00282 376S1128 ALL

152S00735 152S01013

152S00731 152S01013 ALL

152S00394

131S00308

353S00832

311S00193

311S00004

376S00146 ALL

371S00085

376S00309

138S00022 ALL138S0801

377S00031 ALL

376S00019

155S0302155S0706 ALL

311S0593311S0596 ALL

131S00041131S00134

353S2073

353S2216 ALL

371S00197371S0689 ALL

132S0312 ALL131S00142

152S00356152S00280 ALL

152S00260 ALL

131S00037 ALL

103S0276103S0321

138S0853

107S00071

107S00101

311S0370 ALL

376S1061

371S00190 ALL

138S00036138S00111

376S00161376S00343 ALL

376S00161 ALL376S00344

ALL353S01346

ALL377S0077 377S0183

ALL377S0155377S0184

ALL740S0190740S00005

ALL

ALL132S00202 132S00175

ALL138S00109 138S0914

ALL

ALL152S00348 152S01013

ALL353S00525 353S4471

ALL353S4471

ALL311S00192

ALL

ALL371S00193 371S00015

ALL138S0863

ALL107S00053

ALL

ALL377S00077377S00079

ALL376S00074

ALL353S2208353S01824

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

rdar://problem/34812612

TABLE_ALT_ITEM

rdar://problem/34812612

TABLE_ALT_ITEM

rdar://problem/34319209

TABLE_ALT_ITEM

rdar://problem/34320842

TABLE_ALT_ITEM

rdar://problem/34320959

TABLE_ALT_ITEM

rdar://problem/34321106

TABLE_ALT_ITEM

rdar://problem/33903814

TABLE_ALT_ITEM

rdar://problem/33930580

Per Peter H

TABLE_ALT_ITEM

rdar://problem/35399063

TABLE_ALT_ITEM

rdar://problem/35403837

TABLE_ALT_ITEM

rdar://problem/35404095

TABLE_ALT_ITEM

rdar://problem/35404496

TABLE_ALT_ITEM

rdar://problem/33955940

TABLE_ALT_ITEM

rdar://problem/32364222

TABLE_ALT_ITEM

rdar://problem/35040623

TABLE_ALT_ITEM

rdar://problem/36353852

TABLE_ALT_ITEM

rdar://problem/36563522

TABLE_ALT_ITEM

rdar://problem/36563854

TABLE_ALT_ITEM

rdar://problem/33930952

TABLE_ALT_ITEM

rdar://problem/36674713

TABLE_ALT_ITEM

rdar://problem/36484938

TABLE_ALT_ITEM

rdar://problem/35404697

TABLE_ALT_ITEM

rdar://problem/33904000

TABLE_ALT_ITEM

rdar://problem/36993892

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

rdar://problem/39510566

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

rdar://problem/39513670

TABLE_ALT_ITEM

rdar://problem/39513670

TABLE_ALT_ITEM

rdar://problem/39512882

TABLE_ALT_ITEM

Email per Peter H

TABLE_ALT_ITEM

Email per CE

TABLE_ALT_ITEM

rdar://problem/40634165

TABLE_ALT_ITEM

rdar://problem/40145084

rdar://problem/40145309

TABLE_ALT_ITEM

rdar://problem/40179470

TABLE_ALT_ITEM

rdar://problem/40315007

TABLE_ALT_ITEM

rdar://problem/40314867

TABLE_ALT_ITEM

Per Peter H

TABLE_ALT_ITEM

TABLE_ALT_ITEM

rdar://problem/40181869

TABLE_ALT_ITEM

rdar://problem/40667960

TABLE_ALT_ITEM

rdar://problem/40468973

TABLE_ALT_ITEM

rdar://problem/42347938

TABLE_ALT_ITEM

Per Eric Lee

MurataTaiyo

Alternate
Vendor

Primary
Vendor

MurataMurata
Taiyo
Chilisin
Diodes
Diodes
Toshiba
NXP

Murata

Murata

On Semi

On Semi

Diodes

On Semi
TFT Cyntec
Chilisin

Cyntec

ON SemiSemtech
ST
Infineon
Littelfuse
Vishay
Taiyo
TI
Murata

Infineon

ON Semi

Wayon

Diodes

Murata

NXP/Nexperia

Taiyo
ON Semi TI
ON Semi TI
NXP

Murata/Taiyo

Diodes

Kyocera/Samsung

MurataKyocera

NXP/Nexperia

Nexperia
Samsung
Chilisin
Cyntec
Vishay
Cyntec
Vishay
Yageo
Vishay
Fairchild
TI
Yageo
Rohm

TI

Diodes

Murata

Cyntec

Cyntec

Cyntec

Chilisin

Cyntec

Murata

Vishay

Vishay

NXP

Cyntec

Toshiba

MurataTaiyo
Cyntec Yageo
Cyntec Yageo
ON Semi
Rohm
ON Semi
Taiyo
Diodes

NXP/Nexperia

Diodes

Diodes

Murata

ST Micro
Diodes Toshiba
Taiyo
On Semi
On Semi

Murata, Samsung

TI

Diodes
Alpha Omega Diodes

D

C

B

A

8

A

PAGE TITLE

BOM Alternates

DRAWING NUMBER

051-04039

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

PAGE

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