Apple Macbook Pro 15 Retina A1398 Schematic

8

VENUS2, PROTO1A : PRELIMINARY
TEST / FAB_ADM1110

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

C

B

Page

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

7

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

1
2
3
4
5
6
7
8
9

TABLE_TABLEOFCONTENTS_ITEM

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(.csa)

1

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU DMI/PEG/FDI/RSVD

6

CPU Clock/Misc/JTAG/CFG

7

CPU DDR3 Interfaces

8

CPU Power

9

CPU Ground

10

CPU Decoupling

11

PCH RTC/HDA/JTAG/SATA/CLK

12

PCH DMI/FDI/PM/GFX/PCI

13

PCH PCI-E/USB

14

PCH GPIO/MISC/NCTF

15

PCH Power

16

PCH Grounds

17

PCH DECOUPLING

18

CPU & PCH XDP

19

Chipset Support

20

Project Chipset Support

21

CPU Memory S3 Support

22

DDR3 VREF MARGINING

23

DDR3 SDRAM Bank A (1 OF 2)

24

DDR3 SDRAM Bank A (2 OF 2)

25

DDR3 SDRAM Bank B (1 OF 2)

26

DDR3 SDRAM Bank B (2 OF 2)

27

DDR3 Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

35

X87 CONNECTOR

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

46

USB 3.0 CONNECTORS

48

KEYBOARD/TRACKPAD (1 OF 2)

49

KEYBOARD/TRACKPAD (2 OF 2)

50

SMC

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Voltage and Current Sensing

55

Load Side Voltage and Current Sensing

56

Debug Sensors

57

GPU V/I Sensors

58

Thermal Sensors

60

Fan Connectors

Contents

SCHEM,MLB,VENUS2, PROTO1A

ENG 06/04/2014

50
51
52
53
54
55
56
57
58
59
60
61
62

TABLE_TABLEOFCONTENTS_ITEM

63
64
65
66
67
68
69

TABLE_TABLEOFCONTENTS_ITEM

70
71
72

TABLE_TABLEOFCONTENTS_ITEM

73
74
75

TABLE_TABLEOFCONTENTS_ITEM

76
77
78

TABLE_TABLEOFCONTENTS_ITEM

79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97

(.csa)

61

SPI Debug Connector

62

AUDIO:CODEC, ANALOG

63

AUDIO:CODEC, DIGITAL

64

AUDIO: SPEAKER AMP

65

AUDIO: JACK

66

AUDIO: JACK TRANSLATORS

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.5 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

1.35V DDR3L SUPPLY

75

5V / 3.3V Power Supply

76

1V05V POWER SUPPLY

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

79

X249 POWER SUPPLY

80

Power FETs

81

Power Control 1/ENABLE

82

Power Sequencing EG/PGOOD

83

eDP Display Connector

84

VENUS PCI-E

85

VENUS CORE/FB POWER

86

VENUS FRAME BUFFER I/F

87

0V95 GPU / 1V35 FB Power Supply

88

GDDR5 Frame Buffer A

89

GDDR5 Frame Buffer B

90

VENUS HDMI/DP/GPIO

91

VENUS GPIOs & STRAPs

92

VENUS DP PWR/GNDs

93

GFX IMVP VCore Regulator

94

VREG GPU VDDCI

95

RIO Connectors

96

eDP Mux

97

eDP Muxed Graphics Support

100

Power Aliases

102

Signal Aliases

104

Functional Test Points

105

NC & No Test

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

GPU (AMD VENUS) Constraints

Contents

Sync

MASTER

CLEAN_X305

J15_MLB

CLEAN_X305G

CLEAN_X305_PEG

J15_REFERENCE

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

CLEAN_X305G

J15_REFERENCE

J15_REFERENCE

J15_REFERENCE

CLEAN_X425

J15_REFERENCE

J15_REFERENCE

CLEAN_X425

J15_MLB

CLEAN_X425

J15_REFERENCE

CLEAN_MAXWELL

CLEAN_X425

J15_MLB

J15_MLB

J15_MLB

J15_MLB

CLEAN_X425

T29_RR

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X425

CLEAN_X425

CLEAN_X425

CLEAN_X425

CLEAN_X425

CLEAN_X425

CLEAN_X425G

CLEAN_MAXWELL

CLEAN_X305

CLEAN_X305

CLEAN_X305G

CLEAN_X305G

CLEAN_X305_PEG

CLEAN_X425G

CLEAN_X305

J45G_AMD

CHANG_J45

J15_MLB

Date

MASTER

05/30/2014

10/31/2012

08/08/2014

02/18/2014

12/18/2012

12/18/2012

10/31/2014

12/18/2012

08/11/2014

12/18/2012

12/18/2012

12/18/2012

10/31/2014

12/18/2012

12/18/2012

10/30/2014

10/31/2012

10/31/2014

01/14/2013

07/02/2014

08/11/2014

10/31/2012

10/31/2012

10/31/2012

10/31/2012

10/30/2014

01/14/2013

10/30/2014

06/24/2014

10/30/2014

10/30/2014

10/30/2014

08/15/2014

10/30/2014

10/30/2014

10/30/2014

09/10/2014

07/02/2014

01/15/2014

06/24/2014

08/11/2014

08/11/2014

02/18/2014

09/10/2014

01/14/2014

07/01/2014

11/26/2012

10/31/2012

Page

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

3456

REV ECN

DESCRIPTION OF REVISION

12

CK
APPD

DATE

06/04/2014

D

C

B

Sync

CLEAN_X425

JOE_J45

JOE_J45

JOE_J45

CLEAN_X305

CLEAN_X305

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X425

CLEAN_X305

CLEAN_X425

CLEAN_X305_PEG

CLEAN_X425

CLEAN_X305

CLEAN_MAXWELL

J45_IG

J45_IG

MARY_X425G

MARY_X425G

MARY_X425G

MARY_X425G

J45G_AMD

ADITYA_X425G

MARY_X425G

MARY_X425G

MARY_X425G

MARY_X425G

MARY_X425G

ADITYA_X425G

ADITYA_X425G

CLEAN_MAXWELL

MARY_X425G

MARY_X425G

CLEAN_X305

J15_MLB

J15_MLB

J15_MLB

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

CLEAN_X305_PEG

SIDLE_J45

SIDLE_J45

SIDLE_J45

SIDLE_J45

SIDLE_J45

J45G_AMD

Date

08/15/2014

07/30/2013

07/30/2013

07/30/2013

06/24/2014

06/24/2014

11/04/2014

01/15/2014

01/09/2015

01/09/2015

01/15/2014

11/04/2014

02/18/2014

10/30/2014

01/15/2014

07/02/2014

07/01/2014

07/01/2014

09/11/2014

12/11/2014

08/22/2014

09/22/2014

06/30/2014

09/16/2014

09/22/2014

09/22/2014

09/22/2014

11/07/2014

09/22/2014

09/15/2014

09/16/2014

07/01/2014

09/22/2014

10/15/2014

05/30/2014

10/31/2012

10/31/2012

10/31/2012

12/10/2012

02/18/2014

12/10/2012

02/18/2014

12/10/2012

12/10/2012

12/10/2012

12/10/2012

12/10/2012

07/01/2014

00109324590.1

ENGINEERING RELEASED

A

Schematic / PCB #’s

PART NUMBER

051-00388

820-00426

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Mon Jan 12 16:34:40 2015

QTY

1 SCH

1 PCB

8 7 6 5 4 2 1

DESCRIPTION

SCHEM,MLB,VENUS2,PROTO1A

PCBF,MLB,VENUS2,PROTO1A

REFERENCE DES

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

<PART_DESCRIPTION>

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

1 OF 119

SHEET

1 OF 97

3

8 7 6 5 4 3

VENUS2, PROTO1A : PRELIMINARY
TEST / FAB_ADM1110

BOM Variants

BOM NUMBER

685-00042
985-00050
639-00682
639-00703
639-00739
639-00740

D

639-00798
639-00799
639-00800
639-00801

639-00803

639-00974

COMMON PARTS,MLB,VENUS2

DEV BOM,MLB,VENUS2
PCBA,MLB,VENUS2,CTO,16GHYN,VR-4GHYN,X425G
PCBA,MLB,VENUS2,CTO,16GMIC,VR-4GMIC,X425G
PCBA,MLB,VENUS2,CTO,16GHYN,VR-4GMIC,X425G
PCBA,MLB,VENUS2,CTO,16GMIC,VR-4GHYN,X425G

PCBA,MLB,VENUS2,BEST,16GHYN,VR-4GHYN,X425G
PCBA,MLB,VENUS2,BEST,16GMIC,VR-4GMIC,X425G
PCBA,MLB,VENUS2,BEST,16GHYN,VR-4GMIC,X425G
PCBA,MLB,VENUS2,BEST,16GMIC,VR-4GHYN,X425G

PCBA,MLB,VENUS2,NOCPU,16GMIC,VR-4GHYN,X425G

PCBA,MLB,NOGPU,CTO,16GMIC,VR-4GHYN,X425G

BOM NAME

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_HYNIX

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_MICRON

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:HYNIX_1600,FB_4G_MICRON

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_HYNIX

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_MICRON

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:HYNIX_1600,FB_4G_MICRON

BASE_BOM,DEVEL_BOM,GFX_BOM,CPU_CRW:BEST,RAM:MICRON_1600,FB_4G_HYNIX

BASE_BOM,DEVEL_BOM,GFX_BOM,RAM:MICRON_1600,FB_4G_HYNIX

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600,FB_4G_HYNIX

BOM OPTIONS
X425_COMMON

X425_DEVEL:ENG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

X425 BOM Groups

BOM GROUP

X425_COMMON
X425_COMMON1
X425_COMMON2

X425_PVT
X425_PROGPARTS
X425_DEVEL:ENG
X425_DEVEL:DVT
X425_DEVEL:PVT

GFX_BOM

XDP_DEBUG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,DPMUX_DEBUG,GPU_ROM:YES,SENSOR_GPU_NONPROD:Y

BOM OPTIONS

ALTERNATE,COMMON,X425_COMMON1,X425_COMMON2,X425_PROGPARTS,ACAPS:A2

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CPUPEG:X8X4X4,S2_PWR:S0,SMC_SUSACK:YES

EDP:YES,XDP,SSD_PWR_EN:GPIO,CAM_WAKE:NO,SAMCONN,APCLKRQ:ISOL,CRW_SPRT,WLAN_SW:SIL

BKLT:PROD,SENSOR_NONPROD:N

SMC_PROG:BASE,BOOTROM_PROG:EVT,TBTROM:PROG,DPMUXMCU:PROG

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED

XDP_DEBUG

VENUS:XTA

XDP_CONN,XDP_PCH

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

12

D

Module Parts

C

PART NUMBER

337S00058
337S00059

337S4542
338S1247
338S1264
333S0700

333S00032

333S0660 CRITICAL

337S00116

333S00027

333S0766

QTY

1
1
1
1
1

1
32
32

1

4

4

DESCRIPTION

CRW,SR1ZX,PRQ,C0,2.5,47W,4+3E,1.2,6M,BGA

CRW,SR1ZY,PRQ,C0,2.8,47W,4+3E,1.2,6M,BGA

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

IC,SDRAM,DDR3L-1600,4GBIT,78B FBGA

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

IC,GPU,VENUS XTAA1,QS,29X29MM,FCBGA962

IC,GDDR5,4GBIT,6GBPS,1.5V,25NM,BGA170

IC,GDDR5,4GBIT,6GBPS,128MX32,25NM,170BGA

REFERENCE DES

U0500
U0500
U1100
U2800
U3900
U4000

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

U8400

U8800,U8850,U8900,U8950

U8800,U8850,U8900,U8950

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

CPU_CRW:BEST

CPU_CRW:CTO

HYNIX_1600

MICRON_1600

VENUS:XTA

FB_4G_HYNIX

FB_4G_MICRON

DRAM SPD Straps

BOM GROUP

RAM:HYNIX_1600

RAM:MICRON_1600

BOM OPTIONS

HYNIX_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

MICRON_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

A

COMMON/DEVEL BOM

PART NUMBER

685-00042
985-00050

QTY

1
1

DESCRIPTION

COMMON PARTS,MLB,VENUS,X425G

DEV,MLB,VENUS,X425G

REFERENCE DES

BASE

DEVEL

6 3

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

BASE_BOM

DEVEL_BOM

SYNC_MASTER=CLEAN_X305

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

2 OF 119

SHEET

2 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

VENUS2, PROTO1A : PRELIMINARY
TEST / FAB_ADM1110

Programmables - All builds

335S0915 CRITICAL

341S00166

335S0724
341S3565

D

337S4313

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

1

T29,FALCON RIDGE(V27.1)PROTO0,X425G

1

1MBIT SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

1

1

IC,EDP MUX-95C,(RENESAS) V3.2.8,DVB,D2

1

IC,MCU,H8S/2113,9X9MM,TLP-145V

SMC

338S1214

341S00157

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

1

IC,SMC-B1,EXT (V2.25A9) PROTO 0,X425G

1

EFI ROM

335S00007
335S00006
341S00239

1

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM

1
1

IC,EFI ROM (V0145) EVT,X425

C

B

U2890
U2890

U9101
U9600
U9600

U5000
U5000

U6100
U6100
U6100

CRITICAL

CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL

TBTROM:BLANK

TBTROM:PROG

GPUROM:BLANK

DPMUXMCU:PROG

DPMUXMCU:BLANK

SMC_PROG:BLANK

SMC_PROG:BASE

BOOTROM_BLANK:WIN

BOOTROM_BLANK:MAC

BOOTROM_PROG:EVT

Alternate Parts

PART NUMBER

128S0311
138S0739
197S0481
197S0478 197S0479
371S0713 371S0558
152S0461
376S1080 376S0820
155S0667
376S00074

376S1089 376S1128
128S0371
138S0803
138S0843
138S0846 138S0811
127S0164 127S0162
138S0732
128S0364

311S0649
376S00014
740S00003
740S00004
107S00029 107S00030 ALL
128S0398

311S00008 ALL

371S00017
107S00033
107S0240

128S00008 ALL
311S00060 ALL
353S00133 ALL
353S00394 ALL
376S00086
112S00001
353S00095

311S00004

ALTERNATE FOR
PART NUMBER

376S0604376S1053
128S0329
138S0706
197S0480

152S1645

155S00008
376S0855
376S0855376S1129

128S0376
138S0639
138S0674

138S0715
128S0264
333S0700333S0704
311S0541
376S0761
740S0135
740S0134

128S0220
128S0284128S0386
311S0271
128S0334128S0393
311S0426
371S0749

107S0255
107S0250107S0248
107S00032107S00031
107S0251107S0249
107S00038107S00037

128S0380
311S0273
353S2741
353S2162
376S0761
112S0254
353S3328
128S0325128S0397
311S0370

BOM OPTION

REF DES

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ALL
ALL

ALL
ALL311S00007
ALL
ALL107S00034
ALL
ALL
ALL
ALL
ALL
ALL107S00011107S00015

ALL
ALL
ALL

ALL
ALL

COMMENTS:

Diodes alt to Fairchild

NEC alt to Sanyo

Samsung alt to Murata

Epson Alt to NDK

NDK Alt to Epson

DDS alt to ST

Cyntec alt to Vishay

Diodes alt to On Semi

Panasonic alt to TDK

Toshiba alt to Diodes

NXP alt to Diodes

NXP alt to Diodes

Kemet alt to Sanyo

Samsung alt to Murata

Samsung alt to Murata

Samsung alt to Murata

Rohm alt to Vishay

Rohm alt to Vishay

Kemet alt to Sanyo

ELPIDA to HYNIX U4000

ON alt to Toshiba

Toshiba alt to Vishay

AEM alt to Tyco

AEM alt to Littlefuse

TFT alt to Cyntec

Kemet alt to Sanyo

Kemet alt to Sanyo

Diodes alt to NXP

Kemet alt to Sanyo

Diodes alt to NXP

Diodes alt to Onsemi

TFT alt to Cyntec

TFT alt to Cyntec

TFT alt to Cyntec

TFT alt to Cyntec

TFT alt to Cyntec

TFT alt to Cyntec

TFT alt to Cyntec

NEC alt to Sanyo

Diodes alt to NXP

ON Semi alt to TI

ON Semi alt to TI

Diodes alt to Vishay

Yageo alt to Cyntec

Pericom alt to TI

Kemet alt to Sanyo

ON Semi alt to NXP

12

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

D

C

B

A

6 3

SYNC_MASTER=J15_MLB

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

3 OF 119

SHEET

3 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

ZT0415

2.8R2.3

1

GND

ZT0450

TH-NSP

1

SL-2.3X3.9-2.9X4.5

GND

D

SH0430

4.5OD1.85ID-1.95H

1

SH0428

4.5OD1.85ID-1.95H

C

1

Frame Holes

GPU BOSS APN 860-4772

GPU BOSS APN 817-4517

GND

GND

GND

GND

SH0427

4.5OD1.85ID-1.95H

1

ZT0470

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0471

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0472

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0473

TH-NSP

1

SL-1.1X0.45-1.4x0.75

X305G THERMAL MODULE STANDOFF

APN 860-3690

SH0424

STDOFF-4.5OD1.9H-SM-1

1

2.1SM2.0MM-CIR

APN 817-0688

SH0446

STDOFF-4.9OD2.38H-SM-2

1

APN 817-0741

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

SH0445

1

ZT0490

SMT-PAD-NSP

1

SMT GND TEST PONTS

ZT0491

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

ZT0492

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

CPU BOSS APN 860-2931

SH0429

5.0OD1.85ID-2.35H

1

SH0422

5.0OD1.85ID-2.35H

1

APN 806-2247

BR0401

MLB-MTG-BRKT-J5

TH

1

SH0420

5.0OD1.85ID-2.35H

1

SH0426

5.0OD1.85ID-2.35H

1

D

C

SH0421

4.5OD1.85ID-1.95H-1

1

FAN BOSS APN 860-3428

SH0425

STDOFF-4.5OD1.8H-SM-1

B

1

APN 806-9391

1

SH0450

SHLD-MLB-USB-J45

SM

SHLD-FENCE-MLB-T29-X305

SH0423

STDOFF-4.5OD1.8H-SM-1

1

806-00452

1

SH0451

SM

--------------------------------------------------------

Thermal Module gaskets APN 875-9290

OMIT

CG0400

6.0OD3.9H-SM

1

OMIT

CG0401

6.0OD3.9H-SM

1

X305G POGO PINS

OMIT

CG0402

6.0OD3.9H-SM

1

OMIT

CG0403

6.0OD3.9H-SM

1

APN 870-2451

SH0431

POGO-2.3OD-5.5H-X304

SM

1

SH0432

POGO-2.3OD-5.5H-X304

SM

1

SH0433

POGO-2.3OD-5.5H-X304

SM

1

SH0434

POGO-2.3OD-5.5H-X304

SM

1

SH0435

POGO-2.3OD-5.5H-X304

SM

1

PD parts

PART NUMBER

SH0437

POGO-2.3OD-5.5H-X304

SM

1

QTY

1

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

DESCRIPTION

REFERENCE DES

EDGE_BOND

CRITICAL

CRITICAL946-3819

RIO FLEX BRACKET BOSS (860-00166)

SH0480

3.5OD1.85ID-2.0H

1

SH0481

3.5OD1.85ID-2.0H

1

IPD FLEX BRACKET BOSS (860-00166)

SH0482

3.5OD1.85ID-2.0H

1

SH0483

3.5OD1.85ID-2.0H

1

BOM OPTION

B

X305G STANDOFF

APN 860-1448

--------------------------------------------------------

SH0440

A

2.9OD1.2ID-1.35H-SM

1

2

SH0442

2.9OD1.2ID-1.35H-SM

1

2

SH0441

2.9OD1.2ID-1.35H-SM

1

2

SH0443

2.9OD1.2ID-1.35H-SM

1

2

SH0444

2.9OD1.2ID-1.35H-SM

1

2

SH0462

2.9OD1.2ID-1.35H-SM

1

2

SH0460

2.9OD1.2ID-1.35H-SM

1

2

SH0465

2.9OD1.2ID-1.35H-SM

1

2

SH0461

2.9OD1.2ID-1.35H-SM

1

2

SH0466

2.9OD1.2ID-1.35H-SM

1

2

SH0463

2.9OD1.2ID-1.35H-SM

1

2

SH0467

2.9OD1.2ID-1.35H-SM

1

2

6 3

SH0464

2.9OD1.2ID-1.35H-SM

1

2

SYNC_MASTER=CLEAN_X305G

PAGE TITLE

PD Parts

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/08/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

4 OF 119

SHEET

4 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

Vinafix.com

12

PPVCOMP_S0_CPU

OMIT_TABLE

U0500

HASWELL

BGA

DMI_S2N_N<0>

12 89

IN

DMI_S2N_N<1>

12 87 89

IN

DMI_S2N_N<2>

12 87 89

IN

DMI_S2N_N<3>

12 87 89

IN

DMI_S2N_P<0>

12 89

D

IN

12 87 89

IN

12 87 89

IN

12 87 89

IN

12 89

OUT

12 87 89

OUT

12 87 89

OUT

12 87 89

OUT

12 89

OUT

12 87 89

OUT

12 87 89

OUT

12 87 89

OUT

12 89

IN

12 89

IN

DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

FDI_CSYNC

FDI_INT

AB2
AB3
AC3
AC1

AB1
AB4
AC4
AC2

AF2
AF4
AG4
AG2

AF1
AF3
AG3
AG1

F11

F12

DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI_CSYNC

DISP_INT

C

SYM 1 OF 12

PEG_RCOMP

PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*

DMI

PEG_RX8*

PEG_RX9*
PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*

FDI

PEG_RX10

PEG_RX11

PEG_RX12

PEG_RX13

PEG_RX14

PEG_RX15

PEG_TX0*

PEG_TX1*

PEG_TX2*

PEG_TX3*

PEG_TX4*

PEG_TX5*

PEG_TX6*

PEG_TX7*

PEG_TX8*

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TX9*
PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*

B

PEG_TX10

PEG_TX11

PEG_TX12

PEG_TX13

PEG_TX14

PEG_TX15

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9

AH6

E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2

F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1

B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1

C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2

CPU_PEG_RCOMP

89

=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_N<1>
PCIE_TBT_D2R_N<2>
PCIE_TBT_D2R_N<3>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_N<3>

=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_P<3>
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_P<3>

=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_N<3>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_N<3>

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_P<3>
PCIE_SSD_R2D_C_P<0>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_C_P<3>

1

R0510

24.9

1%
1/16W
MF-LF
402

2

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

28 85 89

IN

28 85 89

IN

28 85 89

IN

28 85 89

IN

34 85 89

IN

34 85 89

IN

34 85 89

IN

34 85 89

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

28 85 89

IN

28 85 89

IN

28 85 89

IN

28 85 89

IN

34 85 89

IN

34 85 89

IN

34 85 89

IN

34 85 89

IN

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

28 85 89

OUT

28 85 89

OUT

28 85 89

OUT

28 85 89

OUT

34 85 89

OUT

34 85 89

OUT

34 85 89

OUT

34 85 89

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

85

OUT

28 85 89

OUT

28 85 89

OUT

28 85 89

OUT

28 85 89

OUT

34 85 89

OUT

34 85 89

OUT

34 85 89

OUT

34 85 89

OUT

5 8

OMIT_TABLE

U0500

HASWELL

BGA

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
Port D pins out of order
to match Intel symbol.

C25
D25
A25
B25
C24
D24
A24
B24

C21
D21
A21
B21
C20
D20
A20
B20

C16
D16
A16
B16

C17
D17
A17
B17

DDIB_TXN0
DDIB_TXP0
DDIB_TXN1
DDIB_TXP1
DDIB_TXN2
DDIB_TXP2
DDIB_TXN3
DDIB_TXP3

DDIC_TXN0
DDIC_TXP0
DDIC_TXN1
DDIC_TXP1
DDIC_TXN2
DDIC_TXP2
DDIC_TXN3
DDIC_TXP3

DDID_TXN2
DDID_TXP2
DDID_TXN3
DDID_TXP3

DDID_TXN0
DDID_TXP0
DDID_TXN1
DDID_TXP1

SYM 10 OF 12

EDP_AUXN
EDP_AUXP

EDP_TXN0

EDP

EDP_TXN1

EDP_TXP0
EDP_TXP1

EDP_RCOMP

EDP_DISP_UTIL

DIGITAL DISPLAY INTERFACES

FDI_TXN0
FDI_TXP0

FDI

FDI_TXN1
FDI_TXP1

EDP_HPD

F15
F14
E14

C14
A12

D14
B12

AG6
E12

C12
D12
A14
B14

OMIT_TABLE

U0500

HASWELL

TP0500
TP0510

TP0520
TP0530

TP0521

TP

TP-P6

TP

TP-P6

TP

TP-P6

TP

TP-P6

TP

TP-P6

BGA

CPU_DC_A3_B3

5

CPU_DC_A4

1

CPU_DC_A51

1

CPU_DC_A52_B52

5

CPU_DC_A53_B53

5

CPU_DC_B2_C3

5

CPU_DC_A3_B3

5 5

CPU_DC_A52_B52

5

CPU_DC_A53_B53

5

CPU_DC_B54_C54

5

1

CPU_DC_BC1
CPU_DC_BC54

1

CPU_DC_BD1_BE1

5

CPU_DC_BD54_BE54

5

CPU_DC_BD1_BE1

5

CPU_DC_BE2_BF2

5

CPU_DC_BE3_BF3

5

CPU_DC_BE52_BF52

5

CPU_DC_BE53_BF53

5

CPU_DC_BD54_BE54

5

CPU_DC_BE2_BF2

5

CPU_DC_BE3_BF3

5

CPU_DC_BF4

1

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

A51
A52
A53

B52
B53
B54

BC1

BC54

BD1

BD54

BE1
BE2

BE3
BE52
BE53
BE54

BF2

BF3

BF4

A3
A4

B2
B3

SYM 12 OF 12

RESERVED

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

RSVD132
RSVD133
RSVD134
RSVD135
RSVD136
RSVD137
RSVD138
RSVD139

NO_TESTNO_TEST

BF51
BF52
BF53

C1
C2
C3

C54
D1

D54

CPU Daisy-Chain Strategy:

Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.

AN35
AN37
AF9
AE9
G14
G17
AD45
AG45

PPVCCIO_S0_CPU

1

R0531

10k

5%
1/16W
MF-LF
402

2

DP_INT_IG_AUX_N
DP_INT_IG_AUX_P
DP_IG_A_HPD_L

DP_INT_IG_ML_N<0>
DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_P<1>

CPU_EDP_RCOMP

89

TP_EDP_DISP_UTIL

DP_INT_IG_ML_N<2>
DP_INT_IG_ML_P<2>
DP_INT_IG_ML_N<3>
DP_INT_IG_ML_P<3>

CPU_DC_BF51
CPU_DC_BE52_BF52

TRUE

CPU_DC_BE53_BF53

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_B54_C54

TRUE

CPU_DC_D1

CPU_DC_D54

NC
NC
NC
NC
NC
NC
NC
NC

6 8

10 18 58

82 85 97

82 85 97

20

82 85 97

82 85 97

82 85 97

82 85 97

PPVCOMP_S0_CPU

1

R0530

24.9

1%
1/16W
MF-LF
402

2

82 85 97

82 85 97

82 85 97

82 85 97

5

5

5

5

5

1

TP-P6

1

TP-P6

1

TP-P6

TP

TP

TP

D

5 8

C

TP0531

TP0501
TP0511

B

A

6 3

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

5 OF 119

SHEET

5 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

OMIT_TABLE

D

PPVCCIO_S0_CPU

5 8

10 18 58

1

R0601

62

5%
1/16W
MF-LF

402

2

R0603

56

1%
1/16W
MF-LF

402

3.32K

1/16W
MF-LF

2 1

5%
1/16W
MF-LF

402

1

2

1

1%

402

2

CPU_PROCHOT_L

40 41 58 89

BI

PP1V35_S3RS0_CPUDDR

8

10 21 66 67 84 96

R0620

PLACE_NEAR=R0621.2:1mm

PM_MEM_PWRGD

12 21 89

IN

PLACE_NEAR=U0500.AP48:51.562mm

1.82K

R0621

C

CPU_CATERR_L

40 89

OUT

CPU_PECI

14 41 89

BI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

14 41 89

OUT

PM_SYNC

12 89

IN

CPU_PWRGD

14 18 89

IN

CPU_RESET_L

14

IN

CPU_CLK135M_DPLLREF_N

11 89

IN

CPU_CLK135M_DPLLREF_P

11 89

IN

CPU_CLK135M_DPLLSS_N

11 89

IN

CPU_CLK135M_DPLLSS_P

11 89

IN

DMI_CLK100M_CPU_N

11 89

IN

DMI_CLK100M_CPU_P

11 89

IN

PLACE_NEAR=U0500.F50:157mm

R0611

10K

1/16W
MF-LF

1

5%

402

2

C51

NC

PROC_DETECT*

G50

CATERR*

G51

PECI

E50

PROCHOT*

D53

THERMTRIP*

D52

PM_SYNC

F50

PWRGOOD

AP48

SM_DRAMPWROK

L54

PLTRSTIN*

AC6

DPLL_REF_CLKN

AE6

DPLL_REF_CLKP

V6

SSC_DPLL_REF_CLKN

Y6

SSC_DPLL_REF_CLKP

AB6

BCLKN

AA6

BCLKP

U0500

HASWELL

BGA

SYM 2 OF 12

THERMAL

PWR

CLOCK

DDR3

JTAG

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_DRAMRST*

PRDY*

(IPU)

PREQ*

(IPU)

(IPD)
(IPU)

TRST*

(IPU)

(IPU)

DBR*

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

TCK
TMS

TDI
TDO

BB51
BB53
BB52

BE51

N53
N52

N54
M51
M53

N49
M49

F53

R51
R50
P49
N50
R49
P53
U51
P51

CPU_SM_RCOMP<0>

89

CPU_SM_RCOMP<1>

89

CPU_SM_RCOMP<2>

89

CPU_MEM_RESET_L

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPUPCH_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

PLACE_NEAR=U0500.BB52:12.7mm

21

OUT

18 86 89

OUT

18 86 89

IN

18 86 89

IN

18 86 89

IN

18 86 89

IN

18 86 89

IN

18 86 89

OUT

18 19 89

OUT

18 89

BI

18 89

BI

18 89

BI

18 89

BI

18 89

BI

18 89

BI

18 89

BI

18 89

BI

PLACE_NEAR=U0500.BB53:12.7mm

PLACE_NEAR=U0500.BB51:12.7mm

1

R0614

100

1%
1/16W
MF-LF
402

2

1

R0613

75

1%
1/16W
MF-LF
402

2

1

R0612

100

1%
1/16W
MF-LF
402

2

D

C

B

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1/16W
MF-LF

NOSTUFF

1

1K

5%

402

R0648

1/16W

2

MF-LF

NOSTUFF

1

1

R0643

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

NOSTUFF

R0641

1/16W
MF-LF

A

NOSTUFF

R0647

1/16W
MF-LF

1

1K

5%

402

2

CPUCFG6_PD

R0646

1/16W
MF-LF

1K

402

5%

1

2

CPUCFG5_PD

1

R0645

1K

5%
1/16W
MF-LF
402

2

EDP:YES

R0644

1/16W
MF-LF

1K

5%

402

1K

5%

402

1

2

1

2

CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1

R0640

1K

5%
1/16W
MF-LF
402

2

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>

NOSTUFF

1

R0642

1K

5%
1/16W
MF-LF
402

2

6

18 89

6

18 89

6

18 86 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

6

18 89

BOM GROUP

CPUPEG:X8X8

CPUPEG:X8X4X4

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

OMIT_TABLE

U0500

HASWELL

BGA

R0680

49.9

1/16W
MF-LF

R0685

49.9

1/16W
MF-LF

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

SYM 11 OF 12

RESERVED

CFG_RCOMP

(IPU)

(IPU)

RSVD_TP17
RSVD_TP18

RSVD_TP1
RSVD_TP2
RSVD_TP3
RSVD_TP4

TP_CPU_RSVD_TP23
TP_CPU_RSVD_TP24

TP_CPU_RSVD_TP25
TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP27
TP_CPU_RSVD_TP28
CPU_TESTLO_F21

1

1%

402

2

PPVCC_S0_CPU

8

10 45 59 84 86

TP_CPU_RSVD_TP35
TP_CPU_RSVD_TP36

TP_CPU_RSVD_TP37
TP_CPU_RSVD_TP38

TP_CPU_RSVD_TP39
CPU_TESTLO_F20

1

1%

402

2

CPU_CFG<0>

6

18 89

CPU_CFG<1>

6

18 89

CPU_CFG<2>

6

18 89

CPU_CFG<3>

6

18 86 89

CPU_CFG<4>

6

18 89

CPU_CFG<5>

6

18 89

CPU_CFG<6>

6

18 89

CPU_CFG<7>

6

18 89

CPU_CFG<8>

18 89

CPU_CFG<9>

6

18 89

CPU_CFG<10>

18 89

CPU_CFG<11>

18 89

CPU_CFG<12>

18 89

CPU_CFG<13>

18 89

CPU_CFG<14>

18 89

CPU_CFG<15>

18 89

BE4

RSVD_TP23

BD3

RSVD_TP24

F6

RSVD_TP25

G6

RSVD_TP26

G21

RSVD_TP27

G24

RSVD_TP28

F21

TESTLO_F21

G19

VSS_G19

F51

VSS_F51

F52

VSS_F52

F22

VCC_F22

L52

RSVD_TP35

L53

RSVD_TP36

L51

RSVD_TP37

F24

RSVD_TP38

F25

RSVD_TP39

F20

TESTLO_F20

AG49

CFG0

AD49

CFG1

AC49

CFG2

AE49

CFG3

Y50

CFG4

AB49

CFG5

V51

CFG6

W51

CFG7

Y49

CFG8

Y54

CFG9

Y53

CFG10

W53

CFG11

U53

CFG12

V54

CFG13

R53

CFG14

R52

CFG15

L49

RSVD50
RSVD51

E5

RSVD52

NC
NC
NC

BOM OPTIONS

CPUCFG5_PD

CPUCFG6_PD,CPUCFG5_PD

CFG16
CFG18
CFG17
CFG19

RSVD92
RSVD93
RSVD94
RSVD95

RSVD9
RSVD10
RSVD11

RSVD41
RSVD42

RSVD16

VSS_H54
VSS_H53

VSS_H51
VSS_H52

RSVD47
RSVD48
RSVD49

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

F1
E1
A5
A6

R54

Y52
V53
Y51
V52

B50
AH49
AM48
AU27

AU26
BD4
BC4

AL6
F8

F16

G12
G10

H54
H53

H51
H52

N51L50
G53
H50

TP_CPU_RSVD_TP1
TP_CPU_RSVD_TP2
TP_CPU_RSVD_TP3
TP_CPU_RSVD_TP4

CPU_CFG_RCOMP
CPU_CFG<16>

CPU_CFG<18>
CPU_CFG<17>
CPU_CFG<19>

NC
NC
NC
NC

NC
NC
NC

NC
NC

NC

TP_CPU_RSVD_TP17
TP_CPU_RSVD_TP18

TP_CPU_RSVD_TP47
TP_CPU_RSVD_TP48
TP_CPU_RSVD_TP49

6 3

6

18 89

18 89

18 89

18 89

1

R0690

49.9

1%
1/16W
MF-LF
402

2

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU Clock/Misc/JTAG/CFG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

<SCH_NUM>

<E4LABEL>

<BRANCH>
6 OF 119

6 OF 97

SIZE

B

A

D

8 7 6 5 4 3

12

MEM_A_DQ<0>

23 24 92

BI

MEM_A_DQ<1>

23 24 92

BI

MEM_A_DQ<2>

23 24 92

BI

MEM_A_DQ<3>

23 24 92

BI

MEM_A_DQ<4>

23 24 92

BI

MEM_A_DQ<5>

23 24 92

BI

MEM_A_DQ<6>

23 24 92

BI

MEM_A_DQ<7>

23 24 92

BI

MEM_A_DQ<8>

23 24 92

D

C

B

BI

MEM_A_DQ<9>

23 24 92

BI

MEM_A_DQ<10>

23 24 92

BI

MEM_A_DQ<11>

23 24 92

BI

MEM_A_DQ<12>

23 24 92

BI

MEM_A_DQ<13>

23 24 92

BI

MEM_A_DQ<14>

23 24 92

BI

MEM_A_DQ<15>

23 24 92

BI

MEM_A_DQ<16>

23 24 92

BI

MEM_A_DQ<17>

23 24 92

BI

MEM_A_DQ<18>

23 24 92

BI

MEM_A_DQ<19>

23 24 92

BI

MEM_A_DQ<20>

23 24 92

BI

MEM_A_DQ<21>

23 24 92

BI

MEM_A_DQ<22>

23 24 92

BI

MEM_A_DQ<23>

23 24 92

BI

MEM_A_DQ<24>

23 24 92

BI

MEM_A_DQ<25>

23 24 92

BI

MEM_A_DQ<26>

23 24 92

BI

MEM_A_DQ<27>

23 24 92

BI

MEM_A_DQ<28>

23 24 92

BI

MEM_A_DQ<29>

23 24 92

BI

MEM_A_DQ<30>

23 24 92

BI

MEM_A_DQ<31>

23 24 92

BI

MEM_A_DQ<32>

23 24 92

BI

MEM_A_DQ<33>

23 24 92

BI

MEM_A_DQ<34>

23 24 92

BI

MEM_A_DQ<35>

23 24 92

BI

MEM_A_DQ<36>

23 24 92

BI

MEM_A_DQ<37>

23 24 92

BI

MEM_A_DQ<38>

23 24 92

BI

MEM_A_DQ<39>

23 24 92

BI

MEM_A_DQ<40>

23 24 92

BI

MEM_A_DQ<41>

23 24 92

BI

MEM_A_DQ<42>

23 24 92

BI

MEM_A_DQ<43>

23 24 92

BI

MEM_A_DQ<44>

23 24 92

BI

MEM_A_DQ<45>

23 24 92

BI

MEM_A_DQ<46>

23 24 92

BI

MEM_A_DQ<47>

23 24 92

BI

MEM_A_DQ<48>

23 24 92

BI

MEM_A_DQ<49>

23 24 92

BI

MEM_A_DQ<50>

23 24 92

BI

MEM_A_DQ<51>

23 24 92

BI

MEM_A_DQ<52>

23 24 92

BI

MEM_A_DQ<53>

23 24 92

BI

MEM_A_DQ<54>

23 24 92

BI

MEM_A_DQ<55>

23 24 92

BI

MEM_A_DQ<56>

23 24 92

BI

MEM_A_DQ<57>

23 24 92

BI

MEM_A_DQ<58>

23 24 92

BI

MEM_A_DQ<59>

23 24 92

BI

MEM_A_DQ<60>

23 24 92

BI

MEM_A_DQ<61>

23 24 92

BI

MEM_A_DQ<62>

23 24 92

BI

MEM_A_DQ<63>

23 24 92

BI

CPU_DIMM_VREFCA

22

OUT

CPU_DIMMA_VREFDQ

22 89

OUT

CPU_DIMMB_VREFDQ

22 89

OUT

AH54

SA_DQ0

AH52

SA_DQ1

AK51

SA_DQ2

AK54

SA_DQ3

AH53

SA_DQ4

AH51

SA_DQ5

AK52

SA_DQ6

AK53

SA_DQ7

AN54

SA_DQ8

AN52

SA_DQ9

AR51

SA_DQ10

AR53

SA_DQ11

AN53

SA_DQ12

AN51

SA_DQ13

AR52

SA_DQ14

AR54

SA_DQ15

AV52

SA_DQ16

AV53

SA_DQ17

AY52

SA_DQ18

AY51

SA_DQ19

AV51

SA_DQ20

AV54

SA_DQ21

AY54

SA_DQ22

AY53

SA_DQ23

AY47

SA_DQ24

AY49

SA_DQ25

BA47

SA_DQ26

BA45

SA_DQ27

AY45

SA_DQ28

AY43

SA_DQ29

BA49

SA_DQ30

BA43

SA_DQ31

BF14

SA_DQ32

BC14

SA_DQ33

BC11

SA_DQ34

BF11

SA_DQ35

BE14

SA_DQ36

BD14

SA_DQ37

BD11

SA_DQ38

BE11

SA_DQ39

BC9

SA_DQ40

BE9

SA_DQ41

BE6

SA_DQ42

BC6

SA_DQ43

BD9

SA_DQ44

BF9

SA_DQ45

BE5

SA_DQ46

BD6

SA_DQ47

BB4

SA_DQ48

BC2

SA_DQ49

AW3

SA_DQ50

AW2

SA_DQ51

BB3

SA_DQ52

BB2

SA_DQ53

AW4

SA_DQ54

AW1

SA_DQ55

AU3

SA_DQ56

AU1

SA_DQ57

AR1

SA_DQ58

AR4

SA_DQ59

AU2

SA_DQ60

AU4

SA_DQ61

AR2

SA_DQ62

AR3

SA_DQ63

AM6

SM_VREF

AR6

SA_DIMM_VREFDQ

AN6

SB_DIMM_VREFDQ

BC53

NC

RSVD25

U0500

HASWELL

BGA

SYM 3 OF 12

MEMORY CHANNEL A

VSS_BC21

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

RSVD160

SA_CKN0
SA_CKP0
SA_CKE0

SA_CKN1
SA_CKP1
SA_CKE1

SA_CKN2
SA_CKP2
SA_CKE2

SA_CKN3
SA_CKP3
SA_CKE3

SA_CS0*
SA_CS1*
SA_CS2*
SA_CS3*

SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3

SA_BS0
SA_BS1
SA_BS2

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

RSVD161

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD162

RSVD163
RSVD164
RSVD165
RSVD166
RSVD167
RSVD168
RSVD169
RSVD170

BD31

BE25
BF25
BE34

BD25
BC25
BF34

BE23
BF23
BC34

BD23
BC23
BD34

BE16
BC17
BE17
BD16

BC16
BF16
BF17
BD17

BC20
BD21
BD32

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>

MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_CKE<1>

NC
NC
NC

NC
NC
NC

MEM_A_CS_L<0>
MEM_A_CS_L<1>

NC
NC

MEM_A_ODT<0>
MEM_A_ODT<1>

NC
NC

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT

23 27 92

23 27 92

23 27 92

24 27 92

24 27 92

24 27 92

23 27 92

24 27 92

23 27 92

24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

BC21

BF20
BF21
BE21

BD28
BD27
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BD20
BF31
BC31
BE20
BE32
BE31

AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
AW39

AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AW40

BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39

MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CAS_L

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

NC

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

NC

NC
NC NC
NC
NC
NC
NC
NC
NC

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

23 24 92

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

25 26 92

BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10

AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3

OMIT_TABLE

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13

SB_DQ15

SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

OMIT_TABLE

U0500

HASWELL

BGA

SYM 4 OF 12

MEMORY CHANNEL B

RSVD171

SB_CKN0
SB_CKP0
SB_CKE0

SB_CKN1
SB_CKP1
SB_CKE1

SB_CKN2
SB_CKP2
SB_CKE2

SB_CKN3
SB_CKP3
SB_CKE3SB_DQ14

SB_CS0*SB_DQ16
SB_CS1*SB_DQ17
SB_CS2*SB_DQ18
SB_CS3*SB_DQ19

SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3

SB_BS0
SB_BS1
SB_BS2

VSS_AU30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

RSVD172

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD173

RSVD174
RSVD175
RSVD176
RSVD177
RSVD178
RSVD179
RSVD180
RSVD181

AY36

AW27
AV27
AU36

AW26
AV26
AU35

BA26
AY26
AV35

BA27
AY27
AV36

BA20
AY19
AU19
AW20

AY20
BA19
AV19
AW19

AY23
BA23
BA36

AU30

AV23
AW23
AV20

BA30
AW30
AY30
AV30
AW32
AY32
AT30
AV32
BA32
AU32
AU23
AY35
AW35
AU20
AW36
BA35

AD52
AU46
BD48
BD43
AW16
AW10
AW8
AL2
BE38

AD53
AV46
BE48
BE43
AW15
AW12
AW6
AL3
BD38

BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37

NCNC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>

MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<1>

NC
NC
NC

NC
NC
NC

MEM_B_CS_L<0>
MEM_B_CS_L<1>

NC
NC

MEM_B_ODT<0>
MEM_B_ODT<1>

NC
NC

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CAS_L

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

NC

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

NC

NC

NC
NC
NC
NC
NC
NC

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

25 27 92

25 27 92

25 27 92

26 27 92

26 27 92

26 27 92

25 27 92

26 27 92

25 27 92

26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 27 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

D

C

B

A

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU DDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

<SCH_NUM>

REVISION

<E4LABEL>

<E4LABEL>

BRANCH

<BRANCH>

<BRANCH>

PAGE

7 OF 119

7 OF 119

SHEET

7 OF 977 OF 97

124578

SIZE

A

D

D

C

B

A

H37

H36

H34

H33

BGA

U0500

HASWELL

SYM 6 OF 12

OMIT_TABLE

AB8

AC46

AB46

AB45

8 7 6 5 4 3

PP1V35_S3RS0_CPUDDR

6

10 21 66 67 84 96

PPVCC_S0_CPU

6 8

10 45 59 84 86

1

R0860

H38

POWER

AC47

H39

AC8

H40

AC9

H42

AD46

H43

AD8

H45

AE46

H46

AE47

AE8

AF8

H9H8H48

AG46

J10

AG8

J14

AH46

J19

AH47

J24

AH8

J29

AJ45

J33

AJ46

J36

AK46

J37

AK47

J38

AK8

J39

AL45

J40

AL46

J42

AL8

NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.

Max load: 300mA

58 89

IN

58 89

OUT

58 89

BI

K45

K44

K43

K40

K38

J9J8J48

J46

J45

J43

AM9

AM8

AL9

AM46

AM47

AN10

AN12

AN13

AN14

AN15

AN16

PPVCCIO_S0_CPU

5 6

10 18 58

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

L39

L38

L37

K9K8K48

K46

AN25

AN24

AN23

AN21

AN20

AN19

AN17

L40

AN26

L42

AN27

R0800

L44

L43

AN30

AN29

75

1/16W
MF-LF

402

R0811

0

5%
1/16W
MF-LF

402

L47

L46

AN34

AN32

1%

L8

AN36

1

2

21

M37

AN38

R0810

R0812

M39

M38

AN40

AN39

43

5%
1/16W
MF-LF

402

5%
1/16W
MF-LF

402

M40

VCCVCC

AN41

0

M42

AN42

21

21

M43

AN43

M44

AN44

1

R0802

110

1%
1/16W
MF-LF
402

2

M45

AN46

AN45

AN8

R0802.2:
R0810.2:
R0800.2:

N37

M9M8M46

AN9

AP10

N38

AP12

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

58 89

OUT

5

Max load: 300mA

PLACE_NEAR=U0500.J50:2.54mm
PLACE_NEAR=U0500.J53:38mm
PLACE_NEAR=R0810.1:2.54mm

N46

N44

N43

N42

N40

N39

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

R46

P8

P46

P45

N9N8N47

AP25

AP24

AP23

AP22

AP21

CPU_VCCSENSE_P

PPVCOMP_S0_CPU

R9

R8

R47

AP29

AP27

AP26

T45

AP30

T46

AP31

U46

AP32

1/16W
MF-LF

U47

AP33

100

U8

AP34

5%

402

2

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

CPU_PWR_DEBUG

18

IN

TP_CPU_RSVD_TP75
TP_CPU_RSVD_TP76
TP_CPU_IVR_ERROR
TP_CPU_RSVD_TP78

Y8

Y46

Y45

W8

W47

W46

V8

V46

V45

U9

AP35

AP36

AP37

AP38

AP39

AP40

AP41

AP42

AP43

AP44

A27

AP46

A28

AP47

A31

AP8

A32

AP9

A34

AR35

B27

AR37

B28

AR39

B31

AR41

B32

AR43

B34

AR45

B36

AR46

B38

H30

B39

H31

6 3

B42

H32

12

PPVCC_S0_CPU

VCC

FC_D5
FC_D3

B43
B45
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29

D5
D3

Connections are required
for BDW CPU support.

PP1V05_S0_CPU_VCCST
CPU_VCCST_PWRGD

SYNC_MASTER=CLEAN_X425

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

J17

AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33

AN31

AN22
AN18

AN33

AR49

AM49

AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50

AA46
AA47

J21
J26
J31

C50
AH9
D51
F17
AK6

J12

J53
J52
J50

B51
F19
E52
V49
U49

W49
V50

A36
A38
A39
A42
A43
A45
A46
A48

AA8
AA9

L6
M6

W9

RSVD64
RSVD65
RSVD66
RSVD67

VDDQ

RSVD68
VCC_L6
VCC_M6
RSVD69
RSVD70

VCC_SENSE
RSVD71
VCCIO_OUT
FC_F17
VCOMP_OUT
RSVD72
RSVD73
RSVD79(VSS)
RSVD74

VIDALERT*
VIDSCLK
VIDSOUT

VSS_B51
PWR_DEBUG*
VSS_E52
RSVD75
RSVD76
IVR_ERROR
IST_TRIGGER
VSS_V50(RSVD)
VSS_AN49(RSVD)
VSS_AJ49(RSVD)
VSS_AG50(RSVD)
VSS_AK49(RSVD)
VSS_AJ50(RSVD)
VSS_AP49(RSVD)
VSS_AB50(RSVD)
VSS_AP50(RSVD)
VSS_AD50(RSVD)
VSS_AM50(RSVD)

VCC

NC
NC
NC
NC

NC

NC
NC

NC

NC

NC
NC
NC
NC

U0500

HASWELL

BGA

SYM 5 OF 12

OMIT_TABLE

6 8

10 45 59 84 86

CPU Power

Apple Inc.

10 19

19

IN

SYNC_DATE=10/31/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

8 OF 119

SHEET

8 OF 97

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

OMIT_TABLE

A11
A15
A19
A22
A26

D

C

B

A30
A33
A37
A40
A44
AA1
AA2
AA3
AA4

AA48

AA5
AA7

AB5
AB51
AB52
AB53
AB54

AB7

AB9
AC48

AC5
AC50

AC7
AD48
AD51
AD54

AD7

AD9

AE1

AE2

AE3

AE4
AE48

AE5
AE50

AE7

AF5

AF6

AF7
AG48

AG5
AG51
AG52
AG53
AG54

AG7

AG9

AH1

AH2

AH3

AH4
AH48

AH5
AH50

AH7

U0500

HASWELL

BGA

SYM 7 OF 12

GROUND

AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7

VSSVSS

AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4

AT40
AT42
AT43
AT45
AT46
AT47
AT49

AT50
AT51
AT52
AT53
AT54

AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42

AV13
AV18

AV22
AV25
AV29

AV33

AV42

AV50

AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49

AW50
AW51
AW54

AY13
AY22
AY25
AY29
AY33
AY37
AY42

AT5

AT6
AT8
AT9

AU5
AU9
AV1

AV2

AV3

AV4

AV5

AV9

AW5

AW9

OMIT_TABLE

U0500

HASWELL

BGA

SYM 8 OF 12

GROUND

VSS VSS

AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9

D

C

B

CPU_VCCSENSE_N

Y9Y7Y48

W7

W54

W52

W50

W48

V9

V7

V48

U7U6U54

U52

U50

U5

U48

C33

VSS

C37

U4U3U2U1T48

C40

C44

C49

C52

C8

D15

D11

D19

D22

D26

D30

D33

C4

D37

D40

D44

D49

D8

E11

E15

E16

E17

E19

G18

AR22

AB48

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AB48(RSVD)

VSS_AR22(RSVD)

E24

E22

E21

E20

E25

E26

E30

A49

E33

E37

E40

B4A8A50

E44

BA1

E49

BA54

E51

BB1

E53

BB54

E8

BD2

F2

BF49

BD53

VSS_NCTF

F3

F26

BF5

F30

BF50

F33

BF6

F37

C53

G1

F54

E54

D2

F5

F4

F40

F44

F49

G11

G13

G26

G25

G23

G20

BGA

U0500

HASWELL

SYM 9 OF 12

OMIT_TABLE

G30

G33

G37

G40

G44

G49

G52

G54

J51

J49

J44

H7

H49

H44

G9G8G7

K7K6K5K4K3K2K1J7J54

VSS

R7

R48P9P7P6P54

P52

P50

P5

P48

P4P3P2

P1

N7

N48

M7

M54

M52

M50

M48

L9L7L48

A

C30

C26

C22

C19

C15

C11

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC30

BC33

BC36

BC38

BC41

BC43

BC46

BC48

BC5

BC50

BC52

BC7

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF12

BF15

BF18

BF22

BF26

BF30

BF33

BF36

BF38

BF41

BF43

BF46

BF48

BF7

D50

VSS_SENSE

G16

1

R0960

100

PLACE_NEAR=U0500.D50:50.8mm

5%
1/16W

PLACE_SIDE=BOTTOM

MF-LF
402

2

6 3

58 89

OUT

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

CPU Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

9 OF 119

SHEET

9 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU VCORE Decoupling

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)
Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

PPVCC_S0_CPU

6 8

45 59 84 86

D

C

PP1V35_S3RS0_CPUDDR

6 8

21 66 67

84 96

B

PLACEMENT_NOTE (C1000-C1019):

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1000

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

PLACEMENT_NOTE (C1020-C1023):

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

1

C1020

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

PLACEMENT_NOTE (C1024-C1045):

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

CRITICAL

1

C1024

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1001

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C1021

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1025

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

1

2

NO STUFF

1

2

PLACEMENT_NOTE (C1046-C1067):

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

CRITICAL

1

C1046

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

PLACEMENT_NOTE (C1068-C1076:

CRITICAL

1

C1047

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

1

2

C1002

1UF

10%
10V
X6S-CERM
0402

NO STUFF

C1022

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C1026

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C1048

20UF

20%

2.5V
X6S-CERM
0402

NO STUFF

1

C1003

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

1

C1023

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1027

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1049

20UF

20%

2.5V

2

X6S-CERM
0402

Place near inductors on bottom side.

CRITICAL

1

C1068

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1069

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1070

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CRITICAL

1

C1071

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

CPU VDDQ Decoupling

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 3x 270uF, 8x 10uF 0603, 10x 1uF 0402

PLACEMENT_NOTE (C1080-C1089):

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

1

2

C1080

1UF

10%
10V
X6S-CERM
0402

1

2

C1081

1UF

10%
10V
X6S-CERM
0402

PLACEMENT_NOTE (C1090-C1097):

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

1

2

C1090

10UF

20%
4V
X6S
0402

1

2

C1091

10UF

20%
4V
X6S
0402

PLACEMENT_NOTE (C1098-C1099):

1

C1082

2

1

C1092

2

1UF

10%
10V
X6S-CERM
0402

10UF

20%
4V
X6S
0402

1

2

1

2

C1083

1UF

C1093

10UF

10%
10V
X6S-CERM
0402

20%
4V
X6S
0402

1

C1004

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1028

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C1050

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1072

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

1

2

1

2

NO STUFF

CRITICAL

1

C109A

20UF

20%

2.5V

2

X6S-CERM
0402

C1084

1UF

10%
10V
X6S-CERM
0402

C1094

10UF

20%
4V
X6S
0402

C1085

1UF

10%
10V
X6S-CERM
0402

C1095

10UF

20%
4V
X6S
0402

ACAPS:A2

CRITICAL

1

C109B

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1006

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1030

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1052

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1074

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

1

2

1

2

1

C1005

1UF

10%
10V

2

X6S-CERM
0402

CAPS for Acoustic Control (C109A to C102D)

NO STUFF

CRITICAL

1

C1029

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1051

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1073

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

1

2

1

2

C1086

1UF

10%
10V
X6S-CERM
0402

C1096

10UF

20%
4V
X6S
0402

NO STUFF

CRITICAL

1

C109C

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1007

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1031

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1053

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1075

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

ACAPS:A2

1

C1087

1UF

10%
10V

2

X6S-CERM
0402

1

C1097

10UF

20%
4V

2

X6S
0402

3 2

CRITICAL

C108B

12PF

5%
NP0-C0G
0201
25V

1

C1009

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C109E

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1033

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1055

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1077

330UF-9MOHM

20%

2.5V
POLY-TANT
D15T-1

1

2

NO STUFF

C1089

1UF

10%
10V
X6S-CERM
0402

CRITICAL

1

C108C

12PF

5%
NP0-C0G

2

0201
25V

1

C1008

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C109D

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1032

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C1054

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1076

210UF

20%

2.5V

2

POLY-TANT
CASE-B2S

1

C1088

1UF

10%
10V

2

X6S-CERM
0402

1

2

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

1

C1010

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C109F

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1034

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C1056

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

CRITICAL

C107B

3.0PF

+/-0.1PF
25V
NP0-C0G
0201

CRITICAL

C102F

20UF

20%

2.5V
X6S-CERM
0402

1

C1013

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C101C

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1037

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C1059

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

1

C1011

1UF

10%
10V

2

X6S-CERM
0402

CRITICAL

1

C101A

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1035

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

1

C1012

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C101B

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1036

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

ACAPS:A2

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

1

C1058

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

CRITICAL

1

C1057

20UF

20%

2.5V

2

X6S-CERM
0402

CAPS for Acoustic Control (C102E to C103F)

CRITICAL

1

C102E

2

CRITICAL

C103A

20UF

20%

2.5V
X6S-CERM
0402

1

C1014

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C101D

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1038

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C1060

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C103B

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1015

1UF

10%
10V

2

X6S-CERM
0402

CRITICAL

1

C101E

20UF

20%

2

NO STUFF

CRITICAL

1

C1039

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1061

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

2.5V
X6S-CERM
0402

NO STUFF

CRITICAL

1

C103C

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1016

1UF

10%
10V

2

X6S-CERM
0402

CRITICAL

1

C101F

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1040

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1062

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C103D

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1017

1UF

10%
10V

2

X6S-CERM
0402

CRITICAL

1

C102A

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1041

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1063

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C103E

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1018

1UF

10%
10V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C102B

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1042

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1064

20UF

20%

2.5V

2

X6S-CERM
0402

1

C1019

1UF

10%
10V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C102C

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1043

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C102D

20UF

20%

2.5V

2

X6S-CERM
0402

NO STUFF

CRITICAL

1

C1044

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A1

CRITICAL

1

C1065

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C103F

20UF

20%

2.5V

2

X6S-CERM
0402

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

CRITICAL

1

C108D

2

12PF

5%
NP0-C0G
0201
25V

CRITICAL

1

C1066

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

CRITICAL

C108E

12PF

5%
NP0-C0G
0201
25V

CRITICAL

1

C1045

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C1067

20UF

20%

2.5V

2

X6S-CERM
0402

ACAPS:A2

CRITICAL

1

C107A

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

D

C

B

CRITICAL

1

C1098

270UF

20%
2V

2

TANT
CASE-B2-SM

CRITICAL

1

C1099

270UF

20%
2V

2

TANT
CASE-B2-SM

(Z = 2mm, place on tall side next to CPU & under heat pipe)

CRITICAL

1

C108A

270UF

20%
2V

2

TANT
CASE-B2-SM

C1098, C1099 and C108A use B size caps due to EG board placement constraints.

CPU VCCIO Decoupling

A

PPVCCIO_S0_CPU

5 6 8

18 58

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)
Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

1

C1079

0.01UF

10%
16V

2

X7R-CERM
0402

6 3

PP1V05_S0

14 15 17 18 41 62 67 84 86

BDW_SPRT

R1080

0

5%
1/10W
MF-LF

603

CPU VCCST Decoupling

Intel recommendation: 1x 0.1uF 0402, 1x 4.7uF 0805
Apple Implementation: 1x 0.1uF 0201, 1x 4.7uF 0402

21

PP1V05_S0_CPU_VCCST

8

19

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

PLACE_NEAR=U0500.D5:12.7mm

BDW_SPRT

1

C106A

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=U0500.D5:25.4mm

BDW_SPRT

1

C106B

4.7UF

20%

6.3V

2

X5R
402

SYNC_MASTER=CLEAN_X305G

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/11/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

10 OF 119

SHEET

10 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

D

PPVRTC_G3H

1

R1101

1M

5%
1/20W
MF
201

2

R1102

C1102

1

R1100

330K

5%

1/20W

MF

201

2

C

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.
PEG-attached (CPU) PCIe devices must use one set,
while PCH-attached PCIe devices use the other set.
If 2 or less devices are attached to PEG the
CLKOUT_PEG outputs can be used for those devices.

20K

1/20W

201

1UF

10%
10V
X5R
402

12 15 19 84

1

1

R1103

20K

5%
MF

2

1

2

5%
1/20W
MF
201

2

PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
RTC_RESET_L

1

C1103

1UF

10%
10V

2

X5R
402

B

PP3V3_SUS
PP3V3_S0

R1177
R1176
R1178

R1134
R1133

R1143
R1142

A

R1169
R1144
R1145
R1147
R1114
R1115

R1146
R1148

R1179

4.7K
10K

4.7K
10K

10K
10K

10K
10K
10K
10K
10K
10K
10K

10K
10K

10K

12 13 14 15 17 50 64 66 67 84
67 68 69 82 83 84 86 96

12 13 14 15 17 19 20 29 34 43
44 45 46 47 48 49 51 52 55 66

21

5% 201

21
21

5% MF

21
21

5% 201MF

21

5% 201MF

21
21
21
21
21

12

21

5%

21

5% 201MF

21

5% 201MF

21

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

1/20W
1/20W
1/20W

1/20W
1/20W

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W
1/20W

1/20W

MF
MF 2015%

MF 2015%

MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 201

MF 2015%

HDA_BIT_CLK

52 91

OUT

HDA_SYNC

52 91

OUT

HDA_RST_L

52 91

OUT

HDA_SDOUT

52 91

OUT

11 91

11 91

11 91

11

PCH_SPKR
DP_TBT_SEL
PCH_SATALED_L

201

DP_AUXCH_ISOL_L
XDP_DC1_SATARDRVR_EN

SSD_CLKREQ_L
XDP_DD2_ENETSD_CLKREQ_L
AP_CLKREQ_L
CAMERA_CLKREQ_L
TBT_CLKREQ_L
PCH_CLKRQ5_L_GPIO44
PEG_CLKREQ_L
PCH_CLKRQ7_L_GPIO46

ENET_CLKREQ_L
PCH_PEGCLKRQB_L_GPIO56

ENET_MEDIA_SENSE_RDIV

R1110
R1111

R1112

R1113

11

11 85

11

18 85

11 18

11 34

11 18

18 33

11 35

11 28

11

11 82 85

11

11 85

11

11 85

12

OMIT_TABLE

SATALED*

TP9
TP8

BC8
BE8
AW8
AY8

BC10
BE10
AV10
AW10

BB9
BD9
AY13
AW13

BC12
BE12
AR13
AT13

BD13
BB13
AV15
AW15

BC14
BE14
AP15
AR15

AY5

AP3

AT1
AU2

BD4

BA2
BB2

NC_SATA_A_D2RN
NC_SATA_A_D2RP
NC_SATA_A_R2D_CN
NC_SATA_A_R2D_CP

NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP

NC_SATA_ODD_D2RN
NC_SATA_ODD_D2RP
NC_SATA_ODD_R2D_CN
NC_SATA_ODD_R2D_CP

NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP

TP_PCIE_ENET_D2RN
TP_PCIE_ENET_D2RP
TP_PCIE_ENET_R2D_CN
TP_PCIE_ENET_R2D_CP

NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

PCH_SATA_RCOMP

90

PCH_SATALED_L

XDP_DC0_DP_AUXCH_ISOL_L
XDP_DC1_SATARDRVR_EN

NC
NC

IN

IN
OUT
OUT

IN

IN
OUT
OUT

87

87

87

87

87

87

87

87

87

87

87

87

11

OUT
OUT

SYSCLK_CLK32K_RTC

19 90

IN

PCH_SRTCRST_L

11 91

PCH_INTRUDER_L

11 91

PCH_INTVRMEN_L

11 91

RTC_RESET_L

11

33

33

33

21

HDA_BIT_CLK_R

91

MF 2015%

1/20W

PLACE_NEAR=U1100.B25:1.27mm

21

HDA_SYNC_R

91

1/20W

5% 201MF

PLACE_NEAR=U1100.A22:1.27mm

PCH_SPKR

11

21

HDA_RST_R_L

91

MF 2015%

1/20W

PLACE_NEAR=U1100.C24:1.27mm

HDA_SDIN0

52 91

IN

NC_HDA_SDIN1

87

NC_HDA_SDIN2

87

NC_HDA_SDIN3

87

21

HDA_SDOUT_R

19 91

1/20W33MF

PLACE_NEAR=U1100.A24:1.27mm

DP_TBT_SEL

11 85

OUT

ENET_MEDIA_SENSE_RDIV

11 85

IN

XDP_PCH_TCK

18 86

IN

XDP_PCH_TMS

18 86

IN

XDP_PCH_TDI

18 86

IN

XDP_PCH_TDO

18 86

OUT

2015%

B5
B4

NC

B9

A8

G10

D9

B25

A22

AL10

C24

L22
K22
G22
F22

A24

B17
C22

AB3

AD1

AE2

AD3

F8

NC

C26

NC

AB6

NC

RTCX1
RTCX2

SRTCRST*

INTRUDER*

INTVRMEN

RTCRST*

HDA_BCLK

HDA_SYNC

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDI0
HDA_SDI1
HDA_SDI2
HDA_SDI3

HDA_SDO

(IPD-DOCKEN#?)

DOCKEN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TP25
TP22
TP20

LYNXPOINT

(1 OF 11)

(IPD-boot)

(IPD)
(IPD)
(IPD)
(IPD)

(IPD-boot)

(IPD)

(IPU)

(IPU)

U1100

MOBILE

FCBGA

RTC

SATA

SATA_RXN4/PERN1

AZALIA

SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1

SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2

SATA0GP/GPIO21
SATA1GP/GPIO19

(IPU-PLTRST#)

JTAG

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2

SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3

SATA_RCOMP

SATA_IREF

OMIT_TABLE

TP19
TP18

AB35
AB36

AF6

Y39
Y38

U4

AF39
AF40

AJ40
AJ39

AF35
AF36

AY24
AW24

AR24
AT24

H33
G33

BE6
BC6

F45

D17

AM43
AL44

C40
F38
F36
F39

AM45

AD39
AD38

AN44

NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP

ENET_CLKREQ_L

NC_PCIE_CLK100M_PEGBN
NC_PCIE_CLK100M_PEGBP

PCH_PEGCLKRQB_L_GPIO56

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

CPU_CLK135M_DPLLSS_N
CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLREF_N
CPU_CLK135M_DPLLREF_P

PCIE_CLK100M_PCH_N

91

PCIE_CLK100M_PCH_P

91

PCH_CLKIN_GNDN
PCH_CLKIN_GNDP

PCH_CLK96M_DOT_N

91

PCH_CLK96M_DOT_P

91

PCH_CLK100M_SATA_N

91

PCH_CLK100M_SATA_P

91

PCH_CLK14P3M_REFCLK

91

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

90

NC

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3
PP1V5_S0

NC
NC

PCH_DIFFCLK_BIASREF

PLACE_NEAR=U1100.AN44:2.54mm

R1190

7.5K

1/20W

201

PCIE_CLK100M_SSD_N

34 91

OUT

PCIE_CLK100M_SSD_P

34 91

OUT

SSD_CLKREQ_L

11 34

IN

NC_PCIE_CLK100M_ENETSDN

87

OUT

NC_PCIE_CLK100M_ENETSDP

87

OUT

XDP_DD2_ENETSD_CLKREQ_L

11 18

IN

PCIE_CLK100M_AP_N

33 91

OUT

PCIE_CLK100M_AP_P

33 91

OUT

XDP_DD3_AP_CLKREQ_L

18

IN

PCIE_CLK100M_CAMERA_N

36 91

OUT

PCIE_CLK100M_CAMERA_P

36 91

OUT

CAMERA_CLKREQ_L

11 35

IN

PEG_CLK100M_N

70 85 91

OUT

PEG_CLK100M_P

70 85 91

OUT

TBT_CLKREQ_L

11 28

IN

NC_PCIE_CLK100M_PE5N

87

NC_PCIE_CLK100M_PE5P

87

PCH_CLKRQ5_L_GPIO44

11

NC_PCIE_CLK100M_SWN

87

NC_PCIE_CLK100M_SWP

87

PEG_CLKREQ_L

11 82 85

IN

PCIE_CLK100M_TBT_N

28 91

OUT

PCIE_CLK100M_TBT_P

28 91

OUT

PCH_CLKRQ7_L_GPIO46

11

NC_ITPXDP_CLK100MN

87 89

OUT

NC_ITPXDP_CLK100MP

87 89

OUT

LPC_CLK33M_SMC_R

19 91

OUT

NC_LPC_CLK33M_LPCPLUS_R

87 91

OUT

LPC_CLK33M_DPMUX_UC_R

20

NC_PCI_CLK33M_OUT3

87

PCH_CLK33M_PCIOUT

19 91

OUT

Y43

CLKOUT_PCIE_N0

Y45

CLKOUT_PCIE_P0

AB1

PCIECLKRQ0*/GPIO73

AA44

CLKOUT_PCIE_N1

AA42

CLKOUT_PCIE_P1

AF1

PCIECLKRQ1*/GPIO18

AB43

CLKOUT_PCIE_N2

AB45

CLKOUT_PCIE_P2

AF3

PCIECLKRQ2*/GPIO20/SMI*

AD43

CLKOUT_PCIE_N3

AD45

CLKOUT_PCIE_P3

T3

PCIECLKRQ3*/GPIO25

AF43

CLKOUT_PCIE_N4

AF45

CLKOUT_PCIE_P4

V3

PCIECLKRQ4*/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P5

AA2

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AB40

CLKOUT_PCIE_N6

AB39

CLKOUT_PCIE_P6

AE4

PCIECLKRQ6*/GPIO45

AJ44

CLKOUT_PCIE_N7

AJ42

CLKOUT_PCIE_P7

Y3

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AH43

CLKOUT_ITPXDP_N

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

U1100

LYNXPOINT

MOBILE

FCBGA

(2 OF 11)

(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)

(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLOCKS

CLKIN_33MHZLOOPBACK

CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67

DIFFCLK_BIASREF

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKOUT_DPNS_N
CLKOUT_DPNS_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND_N
CLKIN_GND_P

CLKIN_DOT96_N
CLKIN_DOT96_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

ICLK_IREF

6 3

SATA Port assignments:

87 90

87 90

Primary HDD/SSD (SATA only)

87 90

87 90

87 90

87 90

Secondary HDD/SSD (SATA only)

87 90

87 90

Reserved: ODD

Unused

PCIe:
Reserved: Ethernet
(if not combo w/SD Card)

Unused

PLACE_NEAR=U1100.AY5:2.54mm

18

11 18

87

87

11 85

IN

87

87

11

6

89

OUT

6

89

OUT

6

89

OUT

6

89

OUT

6

89

OUT

6

89

OUT

R1196
R1195

R1171
R1170

R1192
R1191

R1194
R1193

R1197

IN

87

87

87

87

11 12 13 15 17 19 52 64 67 81
84 86

12
1%
MF

Unused clock terminations for FCIM Mode

10K
10K

10K
10K

10K
10K

10K
10K

10K

19 91

PP1V5_S0

R1130

7.5K

1/20W

201

PP1V5_S0

1

1%
MF

2

11 12 13 15 17 19 52 64 67 81
84 86

NOTE: ENET pair only used if SD Card Reader is USB3.

21
21

21
21

5% 201MF

21
21

21
21

21

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W
1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF5%

1/20W

MF 2015%

1/20W

1.5V -> 1.1V

R1173

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

201

R1172

340

1%

1/16W

1

MF-LF

402

1K

1%

1/20W

MF

201

2

11 12 13 15 17 19 52 64 67 81
84 86

21

SYSCLK_CLK25M_SB

PCH RTC/HDA/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

19 90

IN

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

11 OF 119

SHEET

11 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

DMI_N2S_N<0>

5

89

IN

DMI_N2S_N<1>

5

87 89

IN

DMI_N2S_N<2>

5

87 89

IN

DMI_N2S_N<3>

5

87 89

IN

DMI_N2S_P<0>

5

89

IN

DMI_N2S_P<1>

5

87 89

IN

DMI_N2S_P<2>

5

87 89

IN

DMI_N2S_P<3>

5

87 89

IN

DMI_S2N_N<0>

5

89

OUT

DMI_S2N_N<1>

5

87 89

D

PP1V5_S0

11 12 13 15 17 19 52 64 67 81
84 86

1

R1200

7.5K

1%

1/20W

MF

201

42

OUT

IN

R1286

1/20W

2

0201

1

0

5%
MF

2

PLACE_NEAR=U1100.AY17:12.7mm

PP3V3_SUS

11 13 14 15 17 50 64 66 67 84

NO STUFF

1

R1205

C

1/20W

10K

R1287

5%
MF

201

2

10K

1/20W

5%
MF

201

SMC_SUSACK:NO

1

42

2

OUT

5

87 89

OUT

5

87 89

OUT

5

89

OUT

5

87 89

OUT

5

87 89

OUT

5

87 89

OUT

19 40 86 91

IN

18 19 40 86 91

IN

12 19 86 91

IN

12 19 86 91

IN

6

21 89

OUT

67 86 91

IN

12 18 40 91

IN

40 41

IN

12 30 40 42

IN

DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

PCH_DMI_RCOMP

PCH_SUSACK_L
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_PWROK
PM_MEM_PWRGD
PM_RSMRST_L
PCH_SUSWARN_L
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L

PCH_RI_L

TP_PCH_SLP_S0_L
TP_PCH_SLP_WLAN_L

AW22

DMI_RXN0

AR20

DMI_RXN1

AP17

DMI_RXN2

AV20

DMI_RXN3

AY22

DMI_RXP0

AP20

DMI_RXP1

AR17

DMI_RXP2

AW20

DMI_RXP3

BD21

DMI_TXN0

BE20

DMI_TXN1

BD17

DMI_TXN2

BE18

DMI_TXN3

BB21

DMI_TXP0

BC20

DMI_TXP1

BB17

DMI_TXP2

BC18

DMI_TXP3

BE16

DMI_IREF

AW17

TP12

NC

AV17

TP7

NC

AY17

DMI_RCOMP

R6

SUSACK*

AM1

SYS_RESET*

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

(OD)

J2

RSMRST*

J4

SUSWARN*/SUSPWRNACK/GPIO30

K1

PWRBTN*

E6

ACPRESENT/GPIO31

(IPD-DeepSx)

K7

BATLOW*/GPIO72

N4

RI*

AB10

TP21

D2

SLP_WLAN*/GPIO29

(IPU)

(IPU)

U1100

LYNXPOINT

MOBILE

FCBGA

(4 OF 11)

DMI

MANAGEMENT

SYSTEM POWER

FDI_CSYNC

FDI

FDI_RCOMP

(IPD-DeepSx)

SUS_STAT*/GPIO61

SUSCLK/GPIO62

(IPU-RSMRST#)

SLP_S5*/GPIO63

FDI_RXN0
FDI_RXN1

FDI_RXP0
FDI_RXP1

TP16

TP15
TP10

FDI_INT

FDI_IREF

TP17
TP13

DSWVRMEN

DPWROK

WAKE*

CLKRUN*

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

SLP_LAN*

TP5

AJ35
AL35

AJ36
AL36

AV43
AY45
AV45
AW44

AL39
AL40

AT45

AU42
AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3
F1

AY3

G5

NC
NC

NC
NC

NC
NC
NC
NC

FDI_CSYNC
FDI_INT

NC
NC

PCH_FDI_RCOMP

PCH_DSWVRMEN

91

PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
PM_SYNC
TP_PCH_SLP_LAN_L

5

89

OUT

5

89

OUT

R1210

PLACE_NEAR=U1100.AR44:12.7mm

12 33 35 86 91

IN

12 40

BI

20 40

OUT

41

OUT

12 40 67

OUT

12 21 33 37 40 67 81 86

OUT

12 21 40 67 86

OUT

12 44 66 67

OUT

6

89

OUT

7.5K

1/20W

201

1

1%
MF

2

PP1V5_S0

PPVRTC_G3H

1

R1215

330K

5%
1/20W
MF
201

2

IN

1

R1209

100K

5%
1/20W
MF
201

2

40 86 91

11 12 13 15 17 19 52 64 67 81
84 86

11 15 19 84

D

C

T45

OMIT_TABLE

U44
V45

M43
M45

N42
N44

U40
U39

N36

K36

G36

H20
L20
K17
M20

A12
B13
C12

C10
A10
AL6

VGA_BLUE
VGA_GREEN
VGA_RED

VGA_DDC_CLK
VGA_DDC_DATA

VGA_HSYNC
VGA_VSYNC

DAC_IREF
VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA*
PIRQB*
PIRQC*
PIRQD*

GPIO50
GPIO52
GPIO54

GPIO51
GPIO53
GPIO55

NC
NC
NC

VGA DAC Disabled per SB
DG v1.0 (Table 12-18).

B

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

PP3V3_S5
PP3V3_S0

R1239
R1240
R1291
R1216

R1217
R1218

R1230
R1214

R1231

A

R1233
R1225
R1224

R1221
R1222
R1223

R1281
R1284

3.0K
10K
10K
10K

100K

10K
10K

100K

10K

10K

1K

100K
100K
100K
100K

100K
100K

NO STUFF

NO STUFF

14 15 17 18 19 21 31 32 33 61
64 66 67 82 84 85 86 96

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
68 69 82 83 84 86 96

21

5%

1/20W

12

5%

1/20W

21

5%

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

Redundant to pull-up on audio page

21

5% 201

1/20W

21

5% 201

1/20W

Redundant to pull-up on audio page

21

5% 201

1/20W

21

5%

1/20W

12

5%

1/20W

12

5%

1/20W

12

5%

1/20W

12

5%

1/20W

12

5%

1/20W

12

5%

1/20W

66 67

PM_PWRBTN_L

201

MF

PM_BATLOW_L

201

MF

PM_CLKRUN_L

201

MF

ENET_LOW_PWR_PCH

MF

AUD_IPHS_SWITCH_EN_PCH

MF

BT_PWRRST_L

MF

SDCONN_OC_L

MF

AUD_IP_PERIPHERAL_DET

MF

TBT_PWR_REQ_L

MF

AUD_I2C_INT_L

MF

PCIE_WAKE_L

201

MF

PM_SLP_S3_L

201

MF

PM_SLP_S4_L

201

MF

PM_SLP_S5_L

201

MF

PM_SLP_SUS_L

201

MF

EDP_IG_BKL_ON

201

MF

EDP_IG_PANEL_PWR

201

MF

R1260
R1261
R1262
R1263

10K
10K
10K
10K

12 18 40 91

12 30 40 42

12 40

12 85

12 85

12 85

12 85

12 85

12 29

12 85

12 33 35 86 91

12 21 40 67 86

12 21 33 37 40 67 81 86

12 40 67

12 44 66 67

12 82 85

12 82 85

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

21

5% 201

1/20W

NC_EDP_IG_BKL_PWM

87

OUT

EDP_IG_BKL_ON

12 82 85

OUT

EDP_IG_PANEL_PWR

12 82 85

OUT

PCI_INTA_L

MF

PCI_INTB_L

MF

PCI_INTC_L

MF

PCI_INTD_L

MF

ENET_LOW_PWR_PCH

12 85

OUT

AUD_IPHS_SWITCH_EN_PCH

12 85

OUT

BT_PWRRST_L

12 85

OUT

TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L

42

IN

NC
NC

NC
NC

6 3

U1100

LYNXPOINT

MOBILE

FCBGA

(5 OF 11)

CRT

EDP

PCI

(IPU-PWROK&PCIRST#)

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DISPLAY

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

DDPB_AUXN
DDPC_AUXN
DDPD_AUXN

DDPB_AUXP
DDPC_AUXP
DDPD_AUXP

DDPB_HPD
DDPC_HPD
DDPD_HPD

(IPU)

PLTRST*

PME*

R40
R39

R35
R36

N40
N38

H45
K43
J42

H43
K45
J44

K40
K38
H39

G17
F17
L15
M15

AD10

Y11

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

TP_DP_IG_D_DDC_CLK
TP_DP_IG_D_DDC_DATA

DPA_IG_AUX_CH_N
DPB_IG_AUX_CH_N
NC_DP_IG_D_AUXCHN

DPA_IG_AUX_CH_P
DPB_IG_AUX_CH_P
NC_DP_IG_D_AUXCHP

DP_TBTSNK0_HPD_IG
DP_TBTSNK1_HPD_IG
TP_DP_IG_D_HPD

SDCONN_OC_L
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

83 85

83 85

83 85

83 85

83 85 89

83 85 89

87

83 85 89

83 85 89

87

82 85

82 85

IN
IN
IN
IN

87

OUT

12 85

12 85

12 29

12 85

18 20 21 86

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

SYNC_DATE=12/18/2012

PCH DMI/FDI/PM/GFX/PCI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

12 OF 119

SHEET

12 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

FCBGA

USB3 Port Assignments:

Unused

D

PCIe/USB3 Port Assignments:

SD Card Reader
(& Ethernet if combo)

PCIe Port Assignments:

AirPort

Camera

SSD (Gumstick)
Lane 0
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)

C

B

Lane 1
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)
Lane 2
(PCIe-only)
Or PCIe switch if TBT/SSD

SSD (Gumstick)
Lane 3
(PCIe-only)
Or PCIe switch if TBT/SSD

PP1V5_S0

11 12 15 17 19 52 64 67 81 84
86

1

R1300

7.5K

1%
1/20W
MF
201

2

PLACE_NEAR=U1100.BD29:12.7mm

NC_USB3_SPARE_D2RN

87

NC_USB3_SPARE_D2RP

87

NC_USB3_SPARE_R2D_CN

87

NC_USB3_SPARE_R2D_CP

87

USB3_SD_D2R_N

20 81 86 91

IN

USB3_SD_D2R_P

20 81 86 91

IN

USB3_SD_R2D_C_N

20 81 86 91

OUT

USB3_SD_R2D_C_P

20 81 86 91

OUT

PCIE_AP_D2R_N

20 33 91

IN

PCIE_AP_D2R_P

20 33 91

IN

PCIE_AP_R2D_C_N

33 91

OUT

PCIE_AP_R2D_C_P

33 91

OUT

PCIE_CAMERA_D2R_N

20 36 91

IN

PCIE_CAMERA_D2R_P

20 36 91

IN

PCIE_CAMERA_R2D_C_N

36 91

OUT

PCIE_CAMERA_R2D_C_P

36 91

OUT

NC_PCIE_SSD_D2RN<0>

85

IN

NC_PCIE_SSD_D2RP<0>

85

IN

NC_PCIE_SSD_R2D_CN<0>

85

OUT

NC_PCIE_SSD_R2D_CP<0>

85

OUT

NC_PCIE_SSD_D2RN<1>

85

IN

NC_PCIE_SSD_D2RP<1>

85

IN

NC_PCIE_SSD_R2D_CN<1>

85

OUT

NC_PCIE_SSD_R2D_CP<1>

85

OUT

NC_PCIE_SSD_D2RN<2>

85

IN

NC_PCIE_SSD_D2RP<2>

85

IN

NC_PCIE_SSD_R2D_CN<2>

85

OUT

NC_PCIE_SSD_R2D_CP<2>

85

OUT

NC_PCIE_SSD_D2RN<3>

85

IN

NC_PCIE_SSD_D2RP<3>

85

IN

NC_PCIE_SSD_R2D_CN<3>

85

OUT

NC_PCIE_SSD_R2D_CP<3>

85

OUT

PCH_PCIE_RCOMP

AW31

PERN1_USB3RN3

AY31

PERP1_USB3RP3

BE32

PETN1_USB3TN3

BC32

PETP1_USB3TP3

AT31

PERN2_USB3RN4

AR31

PERP2_USB3RP4

BD33

PETN2_USB3TN4

BB33

PETP2_USB3TP4

AW33

PERN3

AY33

PERP3

BE34

PETN3

BC34

PETP3

AT33

PERN4

AR33

PERP4

BE36

PETN4

BC36

PETP4

AW36

PERN5

AV36

PERP5

BD37

PETN5

BB37

PETP5

AY38

PERN6

AW38

PERP6

BC38

PETN6

BE38

PETP6

AT40

PERN7

AT39

PERP7

BE40

PETN7

BC40

PETP7

AN38

PERN8

AN39

PERP8

BD42

PETN8

BD41

PETP8

BE30

PCIE_IREF

BC30

TP11

NC

BB29

TP6

NC

BD29

PCIE_RCOMP

(9 OF 11)

PCI-E

USB

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

USBRBIAS*

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB2N8
USB2P8

USB2N9
USB2P9

USB2N10
USB2P10

USB2N11
USB2P11

USB2N12
USB2P12

USB2N13
USB2P13

(IPD)

USB3RN1
USB3RP1
USB3TN1
USB3TP1

USB3RN2
USB3RP2
USB3TN2
USB3TP2

USB3RN5
USB3RP5
USB3TN5
USB3TP5

USB3RN6
USB3RP6
USB3TN6
USB3TP6

USBRBIAS

TP24
TP23

B37
D37

A38
C38

A36
C36

A34
C34

B33
D33

F31
G31

K31
L31

G29
H29

A32
C32

A30
C30

B29
D29

A28
C28

G26
F26

F24
G24

AR26
AP26
BE24
BD23

AW26
AV26
BD25
BC24

AW29
AV29
BE26
BC26

AR29
AP29
BD27
BE28

K24
K26

M33
L33

P3
V1
U2
P1
M3
T1
N2
M1

USB_EXTA_N
USB_EXTA_P

NC_USB_EXTCN
NC_USB_EXTCP

NC_USB_SDN
NC_USB_SDP

NC_USB_WLANN
NC_USB_WLANP

NC_USB_4N
NC_USB_4P

NC_USB_PSOCN
NC_USB_PSOCP

NC_USB_6N
NC_USB_6P

NC_USB_7N
NC_USB_7P

USB_EXTB_N
USB_EXTB_P

NC_USB_EXTDN
NC_USB_EXTDP

TP_USB_CAMERAN
TP_USB_CAMERAP

USB_BT_N
USB_BT_P

NC_USB_IRN
NC_USB_IRP

USB_TPAD_N
USB_TPAD_P

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P

NC_USB3_EXTC_D2RN
NC_USB3_EXTC_D2RP
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_D2RN
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_R2D_CN
NC_USB3_EXTD_R2D_CP

PCH_USB_RBIAS

90

NC
NC

XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTC_OC_L
XDP_DA2_SSD_PWR_EN
XDP_DA3_CAMERA_PWR_EN
XDP_DB0_USB_EXTB_OC_L
XDP_DB1_USB_EXTD_OC_L
XDP_DB2_SD_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L

87 90

87 90

87

87

87

87

87

87

87 90

87 90

87 90

87 90

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

37 90

BI

37 90

BI

87 90

BI

87 90

BI

81 86 90

BI

81 86 90

BI

87 90

BI

87 90

BI

33 90

BI

33 90

BI

87 90

BI

87 90

BI

38 86 90

BI

38 86 90

BI

37 90

IN

37 90

IN

37 90

37 90

81 86 90

IN

81 86 90

IN

81 90

81 90

87 90

IN

87 90

IN

87 90

87 90

87 90

IN

87 90

IN

87 90

87 90

OUT
OUT

OUT

USB Port Assignments:

Ext A (LS/FS/HS)

Ext C (LS/FS/HS)

Reserved: SD (HS)

Reserved: WiFi (HS)

Unused

Reserved: PSOC (Legacy Trackpad)

Unused

Unused

Ext B (LS/FS/HS)

Ext D (LS/FS/HS)

Reserved: Camera

BT

IR

Trackpad
USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

Ext C (SS)

Ext D (SS)

PLACE_NEAR=U1100.K24:11.4mm

1

R1370

22.6

1%
1/20W
MF
201

13 18

IN

13 18

IN

18

18

13 18

IN

13 18

IN

18

13 18

IN

2

12

D

C

B

OMIT_TABLE

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST*

TD_IREF

TP1
TP2
TP4
TP3

N7

R10
U11

N8

U8
R7

H6

K6
N11

AF11

AF10

AF7

BA45
BC45
BE43
BE44
AY43

PCH_SMBALERT_L
SMBUS_PCH_CLK

SMBUS_PCH_DATA

PCH_SML0ALERT_L
SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L
SML_PCH_1_CLK

SML_PCH_1_DATA

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

NC
NC
NC
NC

PCH_TD_IREF

13

OUT

BI

13

OUT

BI

13

IN
BI

87

87

87

1

R1380

8.2K

1%
1/20W
MF
201

2

18 43 81 85 86 91

18 43 81 85 86 91

43 91

43 91

43 91

43 91

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

PCH PCI-E/USB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

13 OF 119

SHEET

13 OF 97

124578

SIZE

A

D

LPC_AD<0>

40 82 91

BI

LPC_AD<1>

40 82 91

BI

LPC_AD<2>

40 82 91

BI

LPC_AD<3>

40 82 91

BI

LPC_FRAME_L

40 82 91

OUT

PP3V3_SUS
PP3V3_SUS
PP3V3_S3
PP3V3_S3RS0_CAMERA
PP3V3_S0

R1350
R1351
R1360

A

R1361
R1362
R1368
R1320
R1321
R1367
R1369

R1392
R1393

R1353
R1354
R1355

10K
10K
10K

10K
10K
10K
10K
10K
10K
10K

1K
1K

10K
10K
10K

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

20 21 43 45 46 66 81 82 84 86

20 35 46 84
67 68 69 82 83 84 86 96

11 12 14 15 17 19 20 29 34 43
44 45 46 47 48 49 51 52 55 66

21

1/20W

5% 201MF

21

1/20W

21

1/20W

5%

21

1/20W

21

1/20W

21

1/20W

21

1/20W

5% 201MF

21

1/20W

5% 201MF

12

1/20W

5% 201MF

21

1/20W

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

21

1/20W

5% 201MF

LPC_SERIRQ
TBT_PWR_EN_PCH

MF 2015%

XDP_DA0_USB_EXTA_OC_L

MF 201

XDP_DA1_USB_EXTC_OC_L

MF 2015%

SSD_PWR_EN

MF 2015%

CAMERA_PWR_EN_PCH

MF 2015%

XDP_DB0_USB_EXTB_OC_L
XDP_DB1_USB_EXTD_OC_L
SD_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L

MF 2015%

SPI_IO<2>
SPI_IO<3>

PCH_SMBALERT_L
PCH_SML0ALERT_L
PCH_SML1ALERT_L

R1340
R1341
R1342
R1343

R1344

33
33
33

33

13 40

13 20

13 18

13 18

18 66

18 20

13 18

13 18

18 81 86

13 18

13 50 91

13 50 91

13

13

13

21

1/20W

21

1/20W

21

5%

1/20W

21

21

5% 201MF

1/20W

201MF5%
MF 2015%
MF 201

2015%331/20W

MF

13 20

13 40

50 91

50 91

50 91

50 91

13 50 91

13 50 91

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_FRAME_R_L
NC_LPC_DREQ0_L

87

TBT_PWR_EN_PCH

OUT

LPC_SERIRQ

BI

SPI_CLK_R

OUT

SPI_CS0_R_L

OUT

TP_SPI_CS1_L
TP_SPI_CS2_L
SPI_MOSI_R

BI

SPI_MISO

BI

SPI_IO<2>

BI

SPI_IO<3>

BI

A20
C20
A18
C18

B21

D21
G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

LAD0

(IPU)

LAD1

(IPU)

LAD2

(IPU)

LAD3

(IPU)

LFRAME*

LDRQ0*

(IPU)

LDRQ1*/GPIO23

(IPU-LDRQ1#?)

SERIRQ

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_CS2*

SPI_MOSI

SPI_MISO

SPI_IO2

(IPU)

SPI_IO3

(IPU)

U1100

LYNXPOINT

MOBILE

(3 OF 11)

(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

SMBALERT*/GPIO11

FCBGA

SML0ALERT*/GPIO60

LPC

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

(IPU/IPD)

(IPU/IPD)

C-LINK

SPI

6 3

8 7 6 5 4 3

Pull-up/down on chipset support page (depends on TBT controller)
Falcon Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.
Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

D

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

10K

201

5%
MF

1

2

RAMCFG1:H

1

R1474

10K

5%
1/20W
MF
201

2

RAMCFG0:H

R1475

1/20W

18 20 20

C

IN IN

RAMCFG2:H

R1473

10K

1/20W

BOM GROUP

RAMCFG_SLOT

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.

RAMCFG3:H

1

1

R1472

10K

5%

5%

1/20W
MF

MF

201

201

2

2

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

BOM OPTIONS

TBT_CIO_PLUG_EVENT_L

20 28

IN

FW_PME_L

14 85

IN

DPMUX_UC_IRQ

14 82 85

IN

SMC_RUNTIME_SCI_L

14 40

IN

XDP_FC0_HDD_PWR_EN

18

OUT

WOL_EN

14 85

OUT

MEM_VDD_SEL_1V5_L

14 85

OUT

XDP_DD0_SSD_PCIE_SEL_L

14 18

IN

LPCPLUS_GPIO

14 85

BI

JTAG_TBT_TMS_PCH

14 20

OUT

TBT_GO2SX_BIDIR

14 85

BI

SMC_WAKE_SCI_L

14 40

ISOLATE_CPU_MEM_L

21

OUT

TBT_POC_RESET_L

29

OUT

XDP_FC1_GPU_GOOD

18

OUT

XDP_DC2_ODD_PWR_EN_L

14 18

OUT

XDP_DC3_JTAG_ISP_TCK

18

OUT

JTAG_ISP_TDO

14 20

IN

JTAG_ISP_TDI

14 20

OUT

FW_PWR_EN_PCH

14 85

OUT

XDP_DD1_MLB_RAMCFG1
SPIROM_USE_MLB

14 50 86

BI

MLB_RAMCFG3

20

MLB_RAMCFG2

20

SD_SEL_PCIE_L_USB_H
MLB_RAMCFG0

20

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

AT8

BMBUSY*/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

AB11

AN2

C14

BB4

Y10

R11

AD11

AN6

AP1

AT3

AK1

AT7

AM3

AN4

AK3

U12

C16

D13

G13

H15

BE41

BE5
C45

A5

(IPU-RSMRST#)

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

(IPU-Boot/SATA4GP?)

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

(IPU-DeepSx)

GPIO28

GPIO34

GPIO35/NMI*

SATA2GP/GPIO36

(IPD-PLTRST#)

SATA3GP/GPIO37

(IPD-PLTRST#)

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49

(IPU-Boot/SATA5GP?)

GPIO57

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

(IPU-Boot?)

TACH7/GPIO71

(IPU-Boot?)

VSS

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

(6 OF 11)

FCBGA

GPIO

(IPD)

PROCPWRGD

CPU/MISC

THRMTRIP*

PLTRST_PROC*

TP14

PECI

RCIN*

VSS

VSS

AN10

AY1

AT6

AV3

AV1

AU4

N10

A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

91

PM_THRMTRIP_L_R

41 42

CPU_RESET_L

PART NUMBER

117S0201

14

14 91

OUT

PP1V05_S0

BDW_SPRT

1

R1457

1K

5%
1/16W
MF-LF
402

2

R1470

R1440
R1456

6

QTY

1

DESCRIPTION

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

0

390

NO STUFF

CRW_SPRT

21

CPU_PECI

5%

1/20W

MF43201

21

CPU_PWRGD

1/20W

5%
MF

0201

21

PM_THRMTRIP_L

1/20W

5%

201

MF

REFERENCE DES

10 15 17 18 41 62 67 84 86

BI

OUT

ININ

R1456

6

41 89

6

18 89

6

41 89

CRITICAL

12

D

BOM OPTION

BDW_SPRT

C

SIZE

B

A

D

B

PP3V3_S5
PP3V3_SUS
PP3V3_S0

R1485
R1411
R1496
R1494
R1489
R1495
R1490
R1412
R1492

A

R1491
R1498
R1413
R1486
R1499
R1484
R1493

R1450
R1455

10K
20K
10K
10K

10K
100K
100K

10K

10K

10K

10K

10K

10K

10K

10K
100K

10K

10K

12 15 17 18 19 21 31 32 33 61
64 66 67 82 84 85 86 96

11 12 13 15 17 50 64 66 67 84
66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

NOTE: GPIO0 pull-up/down on project-specific page

21

5% 201

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W
1/20W

MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF

MF
MF

12

5% 201

21

5% 201

21

5% 201

21

5% 201

12

5% 201

21

5% 201

12

5% 201

21

5% 201

21

5% 201

12

5% 201

12

5% 201

21

5% 201

21

5% 201

21

5% 201

21

5% 201

NOTE: GPIO70 pull-up/down on project-specific page

21

5% 201

21

5% 201

FW_PME_L
DPMUX_UC_IRQ
SMC_RUNTIME_SCI_L
WOL_EN
MEM_VDD_SEL_1V5_L
XDP_DD0_SSD_PCIE_SEL_L
LPCPLUS_GPIO
JTAG_TBT_TMS_PCH
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
XDP_DC2_ODD_PWR_EN_L
JTAG_ISP_TCK
JTAG_ISP_TDO
JTAG_ISP_TDI
FW_PWR_EN_PCH
SPIROM_USE_MLB

PCH_A20GATE
PCH_RCIN_L

14 85

14 82 85

14 40

14 85

14 85

14 18

14 85

14 20

14 85

14 40

14 18

18 20

14 20

14 20

14 85

14 50 86

14

14 91

6 3

SYNC_MASTER=CLEAN_X425

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

14 OF 119

SHEET

14 OF 97

124578

8 7 6 5 4 3

12

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCC: 1.312 A Max, 130mA Idle

D

R1550

PLACE_NEAR=U1100.U14:2.54mm

5.11

21

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm

1%

MIN_NECK_WIDTH=0.2 mm

1/20W

VOLTAGE=1.05V

MF-LF

201

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCCASW: 670mA Max, 34mA Idle

Powered in DeepSx

C1550

1UF

6.3V
CERM

PLACE_NEAR=R1550.1:2.54mm

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

1

10%

2

402

C

Y26
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24

U14

U18

U20

U22

U24

V18

V20

V22

V24

Y18

Y20

Y22
AA18

VCC

DCPSUSBYP

VCCASW

FCBGA

(7 OF 11)

CORE

CRT

VCCADACBG3_3

FDI

HVCMOS

USB3

PCIE/DMI

SATA

VCCMPHY

VCCADAC1_5

VCCVRM

VCCIO

VCC3_3

DCPSUS1

VCCSUS3_3

DCPSUS3

VCCIO

VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

VCCIO

VSS

P45

P43

M31

BB44

AN34
AN35

R30
R32

Y12

AJ30
AJ32

AJ26
AJ28

AK20

AK26
AK28

BE22

AK18

AN11

AK22

AM18
AM20
AM22
AP22
AR22
AT22

CKPLUS_WAIVE=PwrTerm2Gnd

VGA DAC Disabled per SB
DG v1.0 (Table 12-18).

CKPLUS_WAIVE=PwrTerm2Gnd

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

NC

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

NC
NC

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

11 12 13 15 17 19 52 64 67 81

84 86

10 14 15 17 18 41 62 67 84 86

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 50 64 66 67

84

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

11 12 13 15 17 19 52 64 67 81

84 86

D

C

B

A

Current data from LPT EDS (doc #486708, Rev 1.0).

OMIT_TABLE

U1100

LYNXPOINT

MOBILE

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
84

VCCSUS3_3: 261mA Max, 6mA Idle

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

??mA Max, ??mA Idle

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

VCC3_3: 133mA Max, 3mA Idle

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0

11 12 13 15 17 19 52 64 67 81
84 86

VCCVRM: 183mA Max, 68mA Idle

PP1V05_S0_PCH_VCC_CLK_F

17

??mA Max, ??mA Idle

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCCCLK: 306mA Max, 89mA Idle

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

VCCCLK3_3: 55mA Max, 11mA Idle

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCCCLK: 306mA Max, 89mA Idle

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

VCCCLK: 306mA Max, 89mA Idle

R24

R26

VCCSUS3_3

R28

U26

M24

VSS

U35

VCCUSBPLL

L24

VCC3_3

V28

VCCIO

V30

Y30

Y35

AF34

AP45

Y32

M29

L29

L26

M26

U32

V32

AD34

AA30
AA32

AD35

AG30
AG32

AD36

AE30
AE32

DCPSUS2

VCCVRM

VCC

VCCCLK

VCCCLK3_3

VCCCLK

NC

FCBGA

(8 OF 11)

USB

CLK/MISC

GPIO/LPC

SPI CPU RTC HDA

THERMAL

VCCSUS3_3

VCCDSW3_3

DCPSST

VCC3_3

VCCIO

VCCSUSHDA

VCCSUS3_3

VCCRTC

DCPRTC

V_PROC_IO

VCCSPI

VCCASW

VCCVRM

VCC3_3

VCC

R20
R22

A16

AA14

AE14
AF12
AG14

U36U30

A26

K8

A6

P14
P16

AJ12
AJ14

AD12

P18
P20

L17

R18

AW40

AK30
AK32

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

PP3V3_S5
15 mA Max, 1mA Idle

PPVOUT_S0_PCH_DCPSST

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

PP1V05_S0
VCCIO: 3629mA Max, 264mA Idle

PP1V5_S0
10mA Max, 1mA Idle

PP3V3_SUS
VCCSUS3_3: 261mA Max, 6mA Idle

6uA Max (3.0V, room temperature)

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP1V05_S0
4mA Max, 2mA Idle

PP3V3_SUS
22mA Max, 1mA Idle

NOTE: Pin name is VCC but really is 3.3V
PP3V3_S0

??mA Max, ??mA Idle

PP1V05_S0
VCCASW: 670mA Max, 34mA Idle

PP1V05_S0
VCCASW: 670mA Max, 34mA Idle

PP1V5_S0
VCCVRM: 183mA Max, 68mA Idle

PP3V3_S0
VCC3_3: 133mA Max, 3mA Idle

6 3

11 12 13 14 15 17 50 64 66 67

84

12 14 17 18 19 21 31 32 33 61
64 66 67 82 84 85 86 96

BYPASS=U1100.AA14::6.35mm

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29
34 43 44 45 46 47 48 49 51 52
96

10 14 15 17 18 41 62 67 84

86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 14 15 17 50 64 66 67

84

BYPASS=U1100.P14::6.35mm

10 14 15 17 18 41 62 67 84 86

11 12 13 14 15 17 50 64 66 67
84

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

11 12 13 15 17 19 52 64 67 81

84 86

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

1

C1580

0.1UF

20%
10V

2

CERM
402

1

C1590

0.1UF

20%
10V

2

CERM
402

1

C1533

0.1UF

C1532

20%
10V

2

CERM

402

BYPASS=U1100.A6::6.35mm

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

0.1UF

20%
10V

2

CERM

402

BYPASS=U1100.A6::6.35mm

R

PPVRTC_G3H

1

C1531

1UF

10%

6.3V

2

CERM
402

BYPASS=U1100.A6::6.35mm

PCH Power

Apple Inc.

11 12 19 84

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

15 OF 119

SHEET

15 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

VSS

K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8

D

C

AL34
AL38

AL8
AM14
AM24
AM26
AM28
AM30
AM32
AM16
AN36

D

C

AN40
AN42

AP13
AP24
AP31
AP43

AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38

AV13
AV22
AV24
AV31
AV33
BB25
AV40

AY10
AY15
AY20
AY26
AY29

AN8

AR2

D42

AV6

AW2

F43

AY7

B11

B15

VSS

U1100

LYNXPOINT

MOBILE

FCBGA

(10 OF 11)

VSS

AA16
AA20
AA22
AA28

AA4
AB12
AB34
AB38

AB8

AC2
AC44
AD14
AD16

B

A

AD18
AD30
AD32
AD40

AE16
AE28
AF38

AG16

AG26
AG28
AG44
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38

AK14
AK24
AK43
AK45
AL12

BC22
BB42

AD6

AD8

AF8

AG2

AJ6

AJ8

AL2

U1100

LYNXPOINT

MOBILE

FCBGA

(11 OF 11)

VSS

VSS VSS

6 3

B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

PCH Grounds

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/18/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

16 OF 119

SHEET

16 OF 97

124578

SIZE

B

A

D

OMIT_TABLE

8 7 6 5 4 3

12

PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)

PP3V3_S5

12 14 15 18 19 21 31 32 33 61
64 66 67 82 84 85 86 96

BYPASS=U1100.A16::6.35mm

D

C

B

PCH VCCSPI BYPASS
(PCH 3.3V SPI PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
84

BYPASS=U1100.AD12::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
84

BYPASS=U1100.R20::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND USB PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
84

BYPASS=U1100.R26::6.35mm

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)

PP3V3_SUS

11 12 13 14 15 17 50 64 66 67
84

BYPASS=U1100.K8::6.35mm

PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)

PP1V5_S0

11 12 13 15 17 19 52 64 67 81
84 86

BYPASS=U1100.A26::6.35mm

C1700

0.1UF

10%
25V

X7R-CERM

0402

C1702

1.0UF

10%

6.3V
X6S

0402

C1704

0.1UF

10%
25V

X7R-CERM

0402

C1706

0.1UF

10%
25V

X7R-CERM

0402

C1708

1.0UF

10%

6.3V
X6S

0402

C1710

0.1UF

10%
25V

X7R-CERM

0402

1

2

BYPASS=U1100.L26::6.35mm

1

2

1

2

1

2

1

2

1

2

C1720

BYPASS=U1100.L29::6.35mm

PCH VCCCLK3_3 BYPASS
(PCH 3.3V CLK PWR)

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

1

C1721

1.0UF

6.3V
0402

1.0UF

10%
X6S

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

PCH VCCVRM BYPASS
(PCH 1.5V VCCVRM PWR)

11 12 13 15 17 19 52 64 67 81
84 86

183mA Max, 68mA Idle

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

10%

6.3V

2

X6S

0402

BYPASS=U1100.M29::6.35mm

PCH VCC3_3 BYPASS
(PCH 3.3V HVCMOS PWR)

PP3V3_S0

PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)

PP3V3_S0

PCH VCC3_3 BYPASS
(PCH 3.3V USB2 PWR)

PP3V3_S0

PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)

PP3V3_S0

PCH VCC BYPASS
(PCH 3.3V FUSE PWR)

PP3V3_S0

PP1V5_S0

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

C1722

1.0UF

10%

6.3V
X6S

0402

1

2

C1723

1.0UF

C1726

0.1UF

X7R-CERM

C1728

0.01UF

X7R-CERM

C1730

0.1UF

X7R-CERM

C1732

0.1UF

X7R-CERM

C1734

1.0UF

1

2

BYPASS=U1100.U32::6.35mm

BYPASS=U1100.R30::6.35mm

BYPASS=U1100.AE14::6.35mm

BYPASS=U1100.L24::6.35mm

BYPASS=U1100.AK30::6.35mm

BYPASS=U1100.P18::6.35mm

C1740

BYPASS=U1100.AF34::12.7mm

X6S-CERM

10%

6.3V
X6S

0402

10%
25V

0402

10%
16V

0402

10%
25V

0402

10%
25V

0402

10%

6.3V
X6S

0402

10UF

20%
16V

0603

1

2

1

2

1

2

1

2

1

2

1

2

1

2

PART NUMBER

QTY

1113S0022

PCH VCCASW BYPASS
(PCH 1.05V ME CORE PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

670mA Max, 34mA Idle

C1750

22UF

X5R-CERM-1

PLACE_NEAR=U1100.V20:2.54mm

PLACE_NEAR=U1100.V20:2.54mm

PCH VCC BYPASS
(PCH 1.05V CORE PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

BYPASS=U1100.AG18::12.7mm

PCH VCCIO BYPASS
(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

BYPASS=U1100.AK18::12.7mm

PCH VCCUSBPLL BYPASS
(PCH 1.05V USB2 PLL PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

PCH VCCIO BYPASS
(PCH 1.05V FDI PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

BYPASS=U1100.AN34::6.35mm

PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

PCH V_PROC_IO BYPASS
(PCH 1.05V CPU I/F PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

BYPASS=U1100.AJ12::12.7mm

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

??mA Max, ??mA Idle

PLACE_NEAR=U1100.V20:2.54mm

Not documented in EDS!

C1755

10UF

X6S-CERM

BYPASS=U1100.AA24::6.35mm

BYPASS=U1100.AK18::6.35mm

BYPASS=U1100.U35::6.35mm

BYPASS=U1100.U30::6.35mm

BYPASS=U1100.AJ12::6.35mm

BYPASS=U1100.AD20::6.35mm

C1760

10UF

X6S-CERM

BYPASS=U1100.AK22::6.35mm

C1785

1.0UF

BYPASS=U1100.AJ12::6.35mm

DESCRIPTION

RES,FF,0 OHM,(020OHM MAX),2A,0603

1

20%

6.3V
2

603

1

20%
16V

2

0603

BYPASS=U1100.AE18::6.35mm

1

20%
16V

2

0603

1

C1770

1.0UF

10%

6.3V

2

X6S

0402

1

C1772

1.0UF

10%

6.3V

2

X6S

0402

1

C1774

0.1UF

10%
25V

2

X7R-CERM

0402

1

10%

6.3V
2

X6S

0402

R1790

REFERENCE DES

L1790

1

C1751

1.0UF

10%

6.3V

2

X6S
0402

1

C1756

1.0UF

10%

6.3V

2

X6S
0402

1

C1761

1.0UF

10%

6.3V

2

X6S
0402

BYPASS=U1100.AK20::6.35mm

1

C1786

0.1UF

10%
25V

2

X7R-CERM
0402

1

5%
1/16W
MF-LF

402

1

C1752

1.0UF

10%

6.3V

2

X6S
0402

1

C1757

1.0UF

10%

6.3V

2

X6S
0402

1

C1762

1.0UF

10%

6.3V

2

X6S
0402

BYPASS=U1100.AM18::6.35mm

CRITICAL

1

C1775

12PF

5%
NP0-C0G

2

0201
25V

1

C1787

0.1UF

10%
25V

2

X7R-CERM
0402

21

PP1V05_S0_PCH_VCC_CLK_R

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

CRITICAL

CRITICAL

1

C1753

12PF

5%
NP0-C0G

2

0201
25V

1

C1758

1.0UF

10%

6.3V

2

X6S
0402

1

C1763

1.0UF

10%

6.3V

2

X6S
0402

4.7UH-170MA-0.321OHM

BOM OPTION

BYPASS=U1100.AP45::12.7mm

CRITICAL

1

C1759

12PF

5%
NP0-C0G

2

0201
25V

1

C1764

1.0UF

10%

6.3V

2

X6S
0402

OMIT_TABLE

BYPASS=U1100.AP45::6.35mm

CRITICAL

1

C1765

12PF

5%
NP0-C0G

2

0201
25V

PCH VCCCLK BYPASS
(PCH 1.05V SSC100 PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

BYPASS=U1100.AE30::6.35mm

PCH VCCCLK BYPASS
(PCH 1.05V DIFFCLK PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

PCH VCCCLK BYPASS
(PCH 1.05V DIFFCLK135 PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

PCH VCCCLK BYPASS
(PCH 1.05V SSC PWR)

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

CRITICAL

L1790

21

0603

NO STUFF

C1790

10UF

20%
16V

X6S-CERM

0603

C1776

1.0UF

10%

6.3V
X6S

0402

BYPASS=U1100.AG30::6.35mm

BYPASS=U1100.AD35::6.35mm

BYPASS=U1100.AD34::6.35mm

BYPASS=U1100.AA30::6.35mm

PCH CLK VCC BYPASS
(PCH 1.05V CLK PLL PWR)

PP1V05_S0_PCH_VCC_CLK_F

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1791

1UF

10%
10V

2

2

X6S-CERM
0402

1

2

C1777

1.0UF

10%

6.3V
X6S

0402

C1778

1.0UF

10%

6.3V
X6S

0402

C1780

1.0UF

10%

6.3V
X6S

0402

C1782

1.0UF

10%

6.3V
X6S

0402

D

1

2

1

2

1

2

C

B

1

2

15

A

Current data from LPT EDS (doc #486708, Rev 1.0).

6 3

SYNC_MASTER=CLEAN_X425

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

17 OF 119

SHEET

17 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

IN

IN

OUT
OUT

IN

6

18 86 89

OUT

OUT

OUT

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

51

51

51

12 20 21 86

11 18 86

11 18 86

11 18 86

6

18 86 89

6

18 86 89

6

86 89

6

86 89

PP1V05_SUS

64 84

51

51

51

51

XDP

21

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

XDP

12

5% 201

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

D

C

B

MF

MF

MF

MF

PPVCCIO_S0_CPU

5 6 8

XDP

C1804

0.1UF

6.3V

CERM-X5R

0201

10%

10 58

1

R1830

150

5%
1/16W
MF-LF
402

2

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

XDP

1

1

R1831

1K

5%

2

1/16W
MF-LF
402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

89

IN

XDP_BPM_L<3>

6

89

IN

XDP_BPM_L<4>

6

89

IN

XDP_BPM_L<5>

6

89

IN

XDP_BPM_L<6>

6

89

IN

XDP_BPM_L<7>

6

89

D

C

IN

6

14 89

IN

12 40 91

OUT

12 19 40 86 91

OUT

6

18 86 89

OUT

CPU_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

XDP_CPU_TCK

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.F50:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800

R1802

R1804

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

XDP_CPU_PREQ_L

6

86 89

BI

XDP_CPU_PRDY_L

6

86 89

IN

CPU_CFG<0>

6

89

IN

CPU_CFG<1>

6

89

IN

CPU_CFG<2>

6

89

IN

CPU_CFG<3>

6

86 89

IN

XDP_BPM_L<0>

6

89

IN

XDP_BPM_L<1>

6

89

IN

CPU_CFG<4>

6

89

IN

CPU_CFG<5>

6

89

IN

CPU_CFG<6>

6

89

XDP

1K

0

0

21

5% 201

XDP

21

5%

XDP

21

5%

1/20W

1/20W

MF

0201

MF

402

MF-LF1/16W

IN

CPU_CFG<7>

6

89

IN

XDP_CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG

8

OUT

XDP_SYS_PWROK

SMBUS_PCH_DATA

13 43 81 85 86 91

BI

SMBUS_PCH_CLK

13 43 81 85 86 91

IN

XDP_PCH_TCK

11 18 86

OUT

XDP_CPU_PRESENT_L

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

PCH/XDP Signals

XDP_DA0_USB_EXTA_OC_L

13 37

OUT

XDP_DA2_SSD_PWR_EN

IN

XDP_DA3_CAMERA_PWR_EN

IN

XDP_DB0_USB_EXTB_OC_L

13

OUT

XDP_DB2_SD_PWR_EN

13

B

IN

XDP_DB3_SDCONN_STATE_CHANGE_L

13

OUT

XDP_DC0_DP_AUXCH_ISOL_L

11

IN

XDP_DC1_SATARDRVR_EN

11 18

IN

XDP_DC2_ODD_PWR_EN_L

IN

XDP_DC3_JTAG_ISP_TCK

14

IN

XDP_DD0_SSD_PCIE_SEL_L

14 34

OUT

XDP_DD1_MLB_RAMCFG1

OUT

XDP_DD2_ENETSD_CLKREQ_L

11 18

OUT

XDP_DD3_AP_CLKREQ_L

11

OUT

R1890
R1895
R1893
R1894
R1896
R1897

R1872

MAKE_BASE=TRUE
MAKE_BASE=TRUE

R1875
R1876

MAKE_BASE=TRUE
MAKE_BASE=TRUE

R1879

(All 10 R’s)

SHORT
SHORT
SHORT
SHORT
SHORT
SHORT

SHORT

SHORT
SHORT

SHORT

OMIT

21

NONE

21
21

NONENONE NONE

21

NONE NONE NONE

21

NONE NONENONE

21

NONE NONENONE

21

NONE

NONE NONE

21

NONE

NONE NONE

21

21

NONE NONE NONE

Non-XDP Signals

NONENONE
NONENONENONE

NONENONENONE

SSD_PWR_EN

201

CAMERA_PWR_EN_PCH

201

USB_EXTB_OC_L

201

SD_PWR_EN

201

SDCONN_STATE_CHANGE_L

201

DP_AUXCH_ISOL_L

201

XDP_DC1_SATARDRVR_EN
XDP_DC2_ODD_PWR_EN_L
JTAG_ISP_TCK

201

SSD_PCIE_SEL_L

201

XDP_DD1_MLB_RAMCFG1
XDP_DD2_ENETSD_CLKREQ_L
AP_CLKREQ_L

201

USB_EXTA_OC_L

201

IN

13 66 13

OUT

13 20 13

OUT

96

81 86

IN

13 81 86

OUT

20

IN

11 85

OUT

11 18

OUT

14 18 14 18

OUT

14 20

OUT

IN

14 18 20 14 18 20

IN

11 18

IN

11 33

IN

PCH/XDP Signal Isolation Notes:
’Output’ non-XDP signals require pulls.

’Output’ PCH/XDP signals require pulls.

R187x and R189x should be placed where
signal path needs to split between route
from PCH to J1850 and path to non-XDP
signal destination (to minimize stub).

Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

SDA
SCL

XDP

6.3V
0201

10%

DF40RC-60DP-0.4V

1

2

CRITICAL
XDP_CONN

J1800

M-ST-SM1

62

61

1

8 7

9

10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
52 51
54 53
56 55
58 57
60659

64 63

518S0847

CPU JTAG Isolation

PP5V_S0

19 36 49 58 59 62 63 66
67 73 79 80 84 85 86

PP3V3_S5

12 14 15 17 19 21 31 32
33 61 64 66 67 82 84 85 86

1

C1845

0.1UF

10%
16V

2

19 40 58 67 86

IN

X5R-CERM

ALL_SYS_PWRGD

0201

74LVC1G07GF

2

A

1

NC NC

6

VCC

U1845

SOT891

GND

3

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC
NC

XDP_CPURST_L
XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

89

IN

6

19 89

OUT

R1805

XDP_TRST_L

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.51:28mm

CRITICAL

Q1840

DMN5L06VK-7

SOT563

XDP

VER 5

3

CRITICAL

Q1840

DMN5L06VK-7

SOT563

XDP

VER 5

PLACE_NEAR=J1800.53:28mm

6

CRITICAL

Q1842

DMN5L06VK-7

SOT563

XDP

VER 5

PLACE_NEAR=J1800.55:28mm

3

CRITICAL

Q1842

DMN5L06VK-7

SOT563

XDP

1

R1845

330K

5%
1/20W
MF
201

2

Y

4

5

NCNC

PLACE_NEAR=J1800.57:28mm

XDP_JTAG_CPU_ISOL_L

VER 5

6

XDP_CPU_TDO

6

18 86 89

XDP_CPU_TCK

6

18 86 89

XDP_CPUPCH_TRST_L

6

18 86 89

PLACE_NEAR=U0500.M49:28mm

PLACE_NEAR=U0500.N54:28mm

PLACE_NEAR=U0500.M53:28mm

R1820
R1823

R1824

TDI and TMS are terminated in CPU.

XDP

1K

21

PLT_RESET_L

5% 201

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

MF

XDP_PCH_TDO

XDP_PCH_TDI
XDP_PCH_TMS

5

G

SD

4

2

G

SD

1

5

G

SD

4

2

G

SD

1

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

XDP_PCH_TDO

11 18 86

XDP_PCH_TDI

11 18 86

XDP_PCH_TMS

11 18 86

XDP_PCH_TCK

11 18 86

PLACE_NEAR=U1100.AD3:28mm

PLACE_NEAR=U1100.AE2:28mm

PLACE_NEAR=U1100.AD1:28mm

PLACE_NEAR=U1100.AB3:28mm

R1860
R1861

R1862
R1866

Unused PCH/XDP Signals

XDP_DA1_USB_EXTC_OC_L

13

BI

XDP_DB1_USB_EXTD_OC_L

13

A

BI

XDP_FC0_HDD_PWR_EN

14

BI

XDP_FC1_GPU_GOOD

14

BI

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1810
TP1811
TP1812
TP1813

6 3

SYNC_MASTER=J15_MLB

PAGE TITLE

CPU & PCH XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

18 OF 119

SHEET

18 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH Reset Button

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

XDP

XDP_DBRESET_L

6

18 89

IN

D

R1996

1/16W
MF-LF

1

R1995

1K

5%
1/16W
MF-LF
402

2

0

21

5%

402

PM_SYSRST_L

OMIT

1

R1997

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

OUT

12 40 86 91

D

PP3V42_G3H

19 34 37 38 40 41 42 43 50
56 57 67 84 86

52 55 66 67 68 69 82 83 84

PP3V3_S0

11 12 13 14 15 17 19 20 29
34 43 44 45 46 47 48 49 51
86 96

ALL_SYS_PWRGD

18 40 58 67 86

IN

CPUVR_PGOOD

IN

SMC_DELAYED_PWRGD

29 30 40 41

C

IN

NOTE: ALL_SYS_PWRGD must remain low until at
least 5ms after all rails are valid.

R1950

2.0K

1/16W
MF-LF

1

5%

402

2

PCH PWROK Generation

BYPASS=U1950::5MM

1

C1950

0.1UF

20%

1

A

U1950

2

B

10V

2

CERM
402

74LVC2G08GT/S505

8

SOT833

7

Y

08

4

R1947

PM_S0_PGOOD

1/20W

0201

NO STUFF

2

1

R1948

0

0

5%

5%

1/20W
MF

MF

0201

1

2

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

8

SOT833

5

A

3

SYS_PWROK_R

Y

U1950

6

B

PLACE_NEAR=U1100.AD7:7MM

08

4

CKPLUS_WAIVE=UNCONNECTED_PINS

PCH 33MHz Clocks

R1955

22

LPC_CLK33M_SMC_R

11 91 40 91

IN

PCH_CLK33M_PCIOUT

11 91

IN

PLACE_NEAR=U1100.D44:6.35mm

PLACE_NEAR=U1100.A40:6.35mm

B

5%

1/20W

MF

201

R1959

22

5%

1/20W

MF

201

21

21

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Camera power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

85 86 96

GreenClk 25MHz Power

SB XTAL Power
Camera XTAL Power
TBT XTAL Power

NOTE: SLG3NB148A provides slow rising
edge on 25MHZ_B when powered from

1.2V VDDIO. Falcon Ridge also
complicates VDD_25M power, forcing
at least S4. Both issues to be
addressed in upcoming part
(SLG3NB148C).

A

PP3V3_S5

12 14 15 17 18 19 21
31 32 33 61 64 66 67 82 84

PP1V5_S0

11 12 13 15 17 19 52 64 67 81
84 86

PP1V2_CAM_XTALPCIEVDD

35

PP3V3_TBTLC

20 28 29 84

C1905

12PF

2 1

5%
50V
C0G

0402

C1906

12PF

5%
50V
C0G

0402

SYSCLK_CLK25M_X2

CRITICAL

31

42

NC
NC

21

SYSCLK_CLK25M_X1

NOTE: 30 PPM crystal required

1

C1924

0.1UF

20%
10V

2

CERM

402

Y1905

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

LPC_CLK33M_SMC

PCH_CLK33M_PCIIN

1

C1920

0.1UF

20%
10V

2

CERM

402

R1905

0

5%
1/16W
MF-LF

402

OUT

11 91

OUT

PP3V42_G3H

19 34 37 38 40 41 42 43 50 56
57 67 84 86

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
No bypass necessary

1

C1922

0.1UF

20%
10V

2

CERM

402

21

SYSCLK_CLK25M_X2_R

NO STUFF

1

R1906

1M

5%
1/16W
MF-LF
402

2

C1902

1UF

402-1

1

10%
10V

2

X5R

6 3

R1949

1K

5%
1/16W
MF-LF

402

11

VIOE_25M_A

6

VIOE_25M_B

14

VIOE_25M_C

3

X2

4

X1

PM_PCH_PWROK
PM_PCH_PWROK

MAKE_BASE=TRUE

21

PM_PCH_SYS_PWROK

5

NC

VDD

U1900

SLG3NB148CV

TQFN

CRITICAL

32.768K

THRM

GND

PAD

17216107

OUT
OUT

OUT

13

VBAT and +V3.3A are
internally ORed to

VG3HOT

create VDD_RTC_OUT.
+V3.3A should be first

available ~3.3V power
to reduce VBAT draw.

25M_A
25M_B
25M_C

VOUT

12

9
8
15

1

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
PPVRTC_G3H
For SB RTC Power

1

C1910

1UF

10%

6.3V

2

CERM
402

12 19 86 91

12 19 86 91

12 18 40 86 91 58

11 12 15 84

VCCST (1.05V S0) PWRGD

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

PM_PCH_PWROK

12 19 86 91

BDW_SPRT

C1930

0.1UF

10%
16V

X5R-CERM

0201

1

2

NC

BDW_SPRT

CRITICAL

U1930

74AUP1G09

6

SOT891

VCC

2

1

5

4

YA

B

NC

GND

3

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

Q1920

DMN5L06VK-7

PP1V5_S0

11 12 13 15 17 19 52 64 67 81
84 86

DMN5L06VK-7

SPI_DESCRIPTOR_OVERRIDE_L

40 41

11 90

OUT

11 90

OUT

36 90

OUT

28 90

OUT

IN

PP1V05_S0_CPU_VCCST

BDW_SPRT

1

R1930

10K

5%
1/20W
MF
201

2

CPU_VCCST_PWRGD

SOT563

VER 5

3

5

G

SD

4

Q1920

SOT563

VER 3

2

8

10

8

OUT

PP5V_S0

18 36 49 58 59 62 63 66 67 73
79 80 84 85 86

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

6

D

SG

1

SYNC_MASTER=CLEAN_X425

PAGE TITLE

Chipset Support

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

R1921

1K

5%
1/20W
MF
201

2

HDA_SDOUT_R

IPD = 9-50k

Apple Inc.

1

R1920

100K

5%
1/20W
MF
201

2

SYNC_DATE=10/31/2014

11 91

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

19 OF 119

SHEET

19 OF 97

SIZE

C

B

A

D

124578

8 7 6 5 4 3

12

D

C

B

PLACE_NEAR=U2050.1:3mm

A

RIO SD Card Reader Support

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

R2040

470K

5%

1/20W

MF

Q2040

DMN5L06VK-7

SMC_PME_S4_DARK_L

28 40 41 42

OUT

PP3V3_S3

13 21 43 45 46 66 81 82 84 86

SDCONN_STATE_CHANGE_L

18

OUT

To/From PCH

Flexible I/O Aliases

SD Card Reader is always USB3 in this implementaton.

USB3_SD_D2R_P

13 20 81 86 91 13 20 81 86 91

OUT

USB3_SD_D2R_N

13 20 81 86 91

OUT

USB3_SD_R2D_C_P

13 20 81 86 91

IN

USB3_SD_R2D_C_N

13 20 81 86 91

IN

Flexible I/O Configuration Strap

Must pull signal correctly even if always USB or PCIe

52 55 66 67 68 69 82 83 84

PP3V3_S0

11 12 13 14 15 17 19 20 29
34 43 44 45 46 47 48 49 51
86 96

SD_SEL_PCIE_L_USB_H

14

OUT

C2030

R2030

100K

1/20W

CERM-X5R

201

0.1UF

6.3V
0201

1

5%
MF

2

10%

SOT563

VER 5

3

1

2

USB3_SD_D2R_P

MAKE_BASE=TRUE

USB3_SD_D2R_N

MAKE_BASE=TRUE

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

4

5

Y

3

5

SMC_PME_SDCONN

G

SD

4

CRITICAL

U2030

TC7SZ08FEAPE

SOT665

2

A

1

B

RIO_SDCONN_STATE_CHANGE_L

IN

IN

OUT

OUT

201

13 20 81 86 91

13 20 81 86 91

13 20 81 86 91

GS3 Connector Support

DEVSLP not supported on LPT-H

SSD_DEVSLP

34

OUT

1

R2070

10K

5%

1/20W

MF

201

2

Camera power-up sequencing Support

R2052

10K

1/20W

PLACE_NEAR=U2050.1:3mm

C2054

0.1UF

10%
10V

X5R-CERM

0201

13 18

IN

PP3V3_S3RS0_CAMERA

1

5%
MF

201

2

CAMERA_PWR_EN_RC

1

2

CAMERA_PWR_EN_PCH

13 35 46 84

BYPASS=U2050::3mm

C2050

0.1UF

10%
10V

X5R-CERM

0201

1

2

1

2

PP3V3_S4

U2050

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

CAMERA_PWR_EN_R

R2050

0

5%

1/20W

MF

0201

NOSTUFF

1

Q2040

DMN5L06VK-7

SOT563

VER 5

2

6

2

G

SD

1

From RIO Connector

20 33 38 41 42 45 46 65 66 67
81 84 85 86

R2051

33

21

CAMERA_PWR_EN

5%

1/20W

MF

201

21

LCD HPD Inverter

Platform Reset Connections

(Pull-Up on CPU Page)

1

R2041

470K

5%
1/20W
MF
201

2

IN

81 86

DP_IG_A_HPD_L

3

D

82

IN

DP_INT_IG_HPD

G

1

Q2010

DMN32D2LFB4

S

DFN1006H4-3

SYM_VER_1

2

HDMI HPD pull-down

HDMI_HPD

81 82 86

OUT

1

R2010

100K

5%

1/20W

MF

201

2

5

OUT

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

12 18 21 86

IN

PP3V3_S0

PLT_RESET_L

MAKE_BASE=TRUE

C2080

0.1UF

20%
10V

CERM

402

1

2

Falcon Ridge Support

RR output is open-drain, no isolation necessary

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

TBT_CIO_PLUG_EVENT_L TBT_CIO_PLUG_EVENT_L

14 20 28 14 20 28

IN

MAKE_BASE=TRUE

R2075

10K

1/20W

1

5%
MF

201

2

OUT

Falcon Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

U2060 supports I/O’s powered when VCC=0V

PP3V3_TBTLC

19 28 29 84

55 66 67 68 69 82 83

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
84 86 96

C2060

JTAG_TBT_TMS_PCH

14

IN

JTAG_ISP_TDO

14

OUT

14

IN

To/From PCH
(Pull-ups on PCH page)

0.1UF

X5R-CERM

0201

16V

10%

1

2

1

2

3

R2061

8

VCC

U2060

SN74AUP3G07DQER

X2SON

1A

3Y 3A

2A 2Y

GND

4

1/20W

1Y

CRITICAL

10K

7

6

5

1

1

R2062

10K

5%

5%

1/20W
MF

MF

201

201

2

2

PCH 33MHz Clock for DPMUX

35

OUT

LPC_CLK33M_DPMUX_UC_R

11 20

MAKE_BASE=TRUE

LPC_CLK33M_DPMUX_UC_R

11 20

IN

PLACE_NEAR=U1100.B42:6.35MM

R2057

22

5%

1/20W

MF

201

21

LPC_CLK33M_DPMUX_UC

AP PCIE D2R test points

PCIE_AP_D2R_N

13 33 91

IN

PCIE_AP_D2R_P

13 33 91

IN

6 3

PLACE_NEAR=U1100.AW33:1mm

1

R2021

84.5

1%
1/20W
MF
201

2

NOSTUFF

1

R2063

10K

5%
1/20W
MF
201

2

Pull-up values TBD

JTAG_TBT_TMS

JTAG_TBT_TDO

JTAG_TBT_TDIJTAG_ISP_TDI

To/From RR

28

OUT

28

IN

28

OUT

82

OUT

Unbuffered

Buffered

CRITICAL

5

MC74VHC1G08

1

2

U2080

3

SC70-HF

4

69

PLT_RST_BUF_L

MAKE_BASE=TRUE

1

R2080

100K

5%
1/16W
MF-LF
402

2

RAM Configuration Straps

MLB_RAMCFG3

14

OUT

MLB_RAMCFG2

14

OUT

XDP_DD1_MLB_RAMCFG1

14 18

OUT

MLB_RAMCFG0

14

OUT

RAMCFG0:L

R2002

1K

1/20W

201

GPIO Glitch Prevention

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

TBT_PWR_EN must be high for JTAG Programming

TBT_PWR_EN

20 28

IN

JTAG_ISP_TCK

14 18

IN

TBT_PWR_EN_PCH

IN

LPC_PWRDWN_L

12 40

IN

Camera PCIE D2R test points

13 36 91

IN

13 36 91

IN

R2083

33

21

5%
1/16W
MF-LF

402

R2085

0

21

5%

21

21

U2000

1

A1

2

B1

5

A2

6

B2

SOT833

1/16W
MF-LF

402

R2088

0

21

5%
1/16W
MF-LF

402

R2072

0

21

5%
1/16W
MF-LF

402

RAMCFG2:L

R2012

8

VCC

08

7

Y1

3

Y2

GND

4

74LVC2G08GT/S505

5%
MF

1

2

R2091

0

5%
1/16W
MF-LF

402

R2087

0

5%
1/16W
MF-LF

402

RAMCFG1:L

1

R2011

1K

5%
1/20W
MF
201

2

CRITICAL

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

SYNC_MASTER=J15_REFERENCE

PAGE TITLE

Project Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SMC_LRESET_L

SSD_RESET_L

CAM_PCIE_RESET_L

AP_RESET_L

TBT_PCIE_RESET_L

DPMUX_LRESET_L

RAMCFG3:L

1

1

R2013

1K

1K

5%
MF

201

2

1

C2013

0.1UF

10%
16V

2

X5R-CERM
0201

2

5%
1/20W
MF
201

1/20W

JTAG_TBT_TCK

TBT_PWR_EN

PLACE_NEAR=U1100.AT33:1mm

1

R2020

84.5

1%
1/20W
MF
201

2

NOSTUFF

SYNC_DATE=01/14/2013

40

OUT

34

OUT

35

OUT

33

OUT

28

OUT

82

OUT

28

OUT

20 28 13

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

20 OF 119

SHEET

20 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

12 33 37 40 67 81 86

IN

CRITICAL

PP3V3_S3

13 20 43 45 46 66 81 82 84 86

DMN5L06VK-7

C

ISOLATE_CPU_MEM_L

14 12 40 67 86

IN IN

PP5V_S3

21 36 60 66 67 84 86

CPUMEM:S0

1

R2115

100K

5%
1/16W
MF-LF

402

2

CRITICAL

CPUMEM:S0

Q2115

DMN5L06VK-7

SOT563

VER 5

B

MEMRESET_ISOL_LS5V_L

22

CPU_MEM_RESET_L

6

21

IN

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1
2 0 0 1 1 1 1 0 1

to

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NO STUFF

C2117

0.047UF

10%

6.3V
X5R
201

CPU_MEM_RESET_L

MAKE_BASE=TRUE

6

1

2

2

G

SD

1

CRITICAL

CPUMEM:S0

Q2115

DMN5L06VK-7

5

G

S D

4

CPUMEM:S3

R2117

5%
1/16W
MF-LF

402

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2100

SOT563

VER 3

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2100

DMN5L06VK-7

SOT563

VER 3

SOT563

VER 5

3

0

21

R2101

100K

1/16W
MF-LF

402

5

R2102

100K

1/16W
MF-LF

402

2

CPUMEM:S0

1

R2116

1K

5%
1/16W
MF-LF
402

2

1

5%

2

3

D

SG

4

1

5%

2

6

D

SG

1

CPUVDDQ_EN_L

MEMVTT_EN_L

CPUMEM:S0

Q2105

DMN5L06VK-7

SOT563

VER 3

CRITICAL
CPUMEM:S0

Q2110

DMN5L06VK-7

SOT563

VER 3

PP1V35_S3

CPUMEM:S0

1

C2116

0.1UF

20%
10V

2

CERM
402

2

3

4

2

3

4

D

S G

D

S G

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

CPUMEM:S0

1

R2105

10K

5%
1/16W
MF-LF
402

2

CPUVDDQ_EN

6

D

SG

1

CRITICAL

5

PM_SLP_S3_L

CPUMEM:S0

1

R2110

10K

5%
1/16W
MF-LF
402

2

MEMVTT_EN

6

1

5

PLT_RESET_L

MEM_RESET_L

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2105

DMN5L06VK-7

SOT563

VER 3

D

SG

Q2110

DMN5L06VK-7

SOT563

VER 3

45 60 66 84 86

OUT

OUT

IN

OUT

66

21 60 85

12 18 20 86

23 24 25 26

PP1V35_S3RS0_CPUDDR

6 8

10 66 67 84 96

R2120

27.4K

1/16W
MF-LF

R2121

43.2K

1/16W
MF-LF

MEM S0 "PGOOD" for CPU

PP3V3_S5

12 14 15 17 18 19 31 32 33 61
64 66 67 82 84 85 86 96

1%

402

1%

402

1

2

MEMPWR_DIV

1

2

C2120

0.047UF

X5R-CERM

1

10%
10V

2

0402

5

1

R2122

10K

5%
1/16W
MF-LF
402

2

PM_MEM_PWRGD_L

3

CRITICAL

Q2120

DMB53D0UV

SOT-563

4

MEMVTT Clamp

Ensures CKE signals are held low in S3

PP5V_S3

21 36 60 66 67 84 86

DMN5L06VK-7

MEMVTT_EN

21 60 85

IN

CPUMEM:S0

CRITICAL

CPUMEM:S0

Q2150

SOT563

VER 3

R2151

100K

1/16W
MF-LF

5

5%

402

D

SG

1

2

VTTCLAMP_EN

3

4

DMN5L06VK-7

NO STUFF

0.001UF

27 60 84 86

CRITICAL

CPUMEM:S0

Q2150

C2151

20%
50V

CERM

402

PPVTT_S0_DDR

SOT563

VER 3

2

1

2

G

2

6

D

SG

1

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM:S0

VTTCLAMP_L

PM_MEM_PWRGD

6

CRITICAL

D

Q2120

DMB53D0UV

SOT-563

S

1

1

R2150

10

75mA max load @ 0.75V

5%

60mW max power

1/10W
MF-LF

603

2

SYNC_MASTER=CLEAN_MAXWELL

PAGE TITLE

6

12 89

OUT

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

SYNC_DATE=07/02/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

21 OF 119

SHEET

21 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

D

CPU-Based Margining

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
LPDDR3 (1.2V) ?.??mV per step

MEMRESET_ISOL_LS5V_L

21

IN

CPU_DIMMA_VREFDQ

7

89

IN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

C

CPU_DIMMB_VREFDQ

7

89

IN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

CPU_DIMM_VREFCA

7

IN

MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm

NOTE: CPU has single output for VREFCA.
Connected to 4 DRAMs.

MIN_NECK_WIDTH=0.2 mm

B

CRITICAL

Q2220

DMN5L06VK-7

2

SOT563

G

VER 5

S D

1

CRITICAL

Q2220

DMN5L06VK-7

5

G

S D

4

CRITICAL

Q2260

DMN5L06VK-7

2

G

S D

1

CRITICAL

Q2260

DMN5L06VK-7

5

G

S D

4

6

CPU_MEM_VREFDQ_A_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

3

CPU_MEM_VREFDQ_B_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

6

CPU_MEM_VREFCA_ISOL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SOT563

VER 5

3

VRef Dividers

Always used, regardless
of margining option.

R2223

2

21

1%

PLACE_NEAR=R2221.2:1mm

1/20W

MF

0201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

2

21

1%

PLACE_NEAR=R2241.2:1mm

1/20W

MF

0201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

2

21

1%

PLACE_NEAR=R2261.2:1mm

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_RC

R2222

1/20W

R2220

24.9

1%

1/20W

MF

201

R2242

1/20W

R2240

24.9

1%

1/20W

MF

201

R2262

1/20W

R2260

24.9

1%

1/20W

MF

201

201

201

201

1

1K

1%
MF

2

21

1

1K

1%
MF

2

21

1

1K

1%
MF

2

21

PP1V35_S3_MEM

1

R2221

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

R2241

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

R2261

1K

1%
1/20W
MF
201

2

PP0V75_S3_MEM_VREFCA

MIN_NECK_WIDTH=0.2 mm

23 24 25 26 27 45 84 92

23 24 85 89 92

C

25 26 85 89

23 24 25 26 85 89 92

B

A

SYNC_MASTER=CLEAN_X425

PAGE TITLE

DDR3 VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=08/11/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

22 OF 119

SHEET

22 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2300

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9

D2

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

1

1

C2308

0.047UF

10%

6.3V

J9

X5R
201

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<0>

C8

MEM_A_DQ<6>

C3

MEM_A_DQ<7>

C9

MEM_A_DQ<5>

E4

MEM_A_DQ<3>

E9

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

E8

MEM_A_DQ<4>

C4

MEM_A_DQS_P<0>

D4

MEM_A_DQS_N<0>

B8
A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC NC

A4

NC

A11

NC

F2

NC

F10

NC

C2309

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

23 24

7

24 92

7

24 92

23 24

23 24

23 24

23 24

23 24
27 92

23

23

23 24 27 92

23 24 27 92

23 24 27 92

23 24

23 24

23

92
7
23 27

23

23 24 27 92

23 24 27 92

23 27 92

D10

C2317

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
92

MEM_A_A<2>

7

MEM_A_A<3>

7
27 92

MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>

7
27 92

MEM_A_A<7>

7
27 92

MEM_A_A<8>

7
27 92

MEM_A_A<9>

7
27 92

MEM_A_A<10>

7
92

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
92

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 92

MEM_A_BA<1>

7
27 92

MEM_A_BA<2>

7
24 27
92

MEM_A_RAS_L

7
24 27 92

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<1>

2

R2310

240

1%
1/20W
MF
201

1

0.47UF

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

C2307

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 92

MEM_A_A<1>

7

23 24

D

27 92

MEM_A_A<2>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23 24

27 92

MEM_A_A<12>

7

23 24

27 92

MEM_A_A<13>

7

23 24

27 92

MEM_A_A<14>

7

23 24

27 92

MEM_A_A<15>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<2>

7

23 24

27 92

MEM_A_RAS_L

7

23 24

27 92

MEM_A_CAS_L

7

23 24

27 92

MEM_A_WE_L

7

23 24

27 92

MEM_A_ODT<0>

7

23 27

92

MEM_A_ZQ<0>

2

C

R2300

240

1%
1/20W
MF
201

1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2310

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

1

1

1

C2318

0.047UF

10%

6.3V
X5R
201

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<14>

C8

MEM_A_DQ<9>

C3

MEM_A_DQ<10>

C9

MEM_A_DQ<15>

E4

MEM_A_DQ<11>

E9

MEM_A_DQ<13>

D3

MEM_A_DQ<8>

E8

MEM_A_DQ<12>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8
A8

NC NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1
A4

NC

A11

NC

F2

NC

F10

NC

C2319

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 92

23

23

23 24 27 92

23 24 27 92

23 24 27 92

23 24

23 24

23

92
7
23 27

23

23 24 27 92

23 24 27 92

23 27 92

D10

C2327

CERM-X5R-1

MEM_A_A<0>

7

MEM_A_A<1>

7
92

MEM_A_A<2>

7

MEM_A_A<3>

7
27 92

MEM_A_A<4>

7
27 92

MEM_A_A<5>

7
27 92

MEM_A_A<6>

7
27 92

MEM_A_A<7>

7
27 92

MEM_A_A<8>

7
27 92

MEM_A_A<9>

7
27 92

MEM_A_A<10>

7
92

MEM_A_A<11>

7
24 27

MEM_A_A<12>

7
24 27
92

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<0>

7
27 92

MEM_A_BA<1>

7
27 92

MEM_A_BA<2>

7
24 27
92

MEM_A_RAS_L

7
24 27 92

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<0>

7

MEM_A_ZQ<2>

2

R2320

240

1%
1/20W
MF
201

1

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2320

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2328

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2329

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<23>
MEM_A_DQ<20>
MEM_A_DQ<19>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_A_A<0>

7

23 24 27 92

MEM_A_A<1>

7

23 24 27

92

MEM_A_A<2>

7

23 24 27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24
27 92

92

MEM_A_A<11>

7

23

24 27

MEM_A_A<12>

7

23

24 27
92

MEM_A_A<13>

7

23 24 27 92

MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

92
27

MEM_A_BA<2>

7

23

23

24 27

7

92

23 27 92

MEM_A_RAS_L

7

23

7

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<0>

7

23 27 92

MEM_A_ZQ<3>

2

R2330

240

1%
1/20W
MF
201

1

C2337

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2330

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2338

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<31>

C8

MEM_A_DQ<24>

C3

MEM_A_DQ<27>

C9

MEM_A_DQ<28>

E4

MEM_A_DQ<30>

E9

MEM_A_DQ<25>

D3

MEM_A_DQ<26>

E8

MEM_A_DQ<29>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8
A8

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2339

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

23 27

92
7

23 27

92

7

23 27

92
7

23 27

92

C

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2340

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9

D2

C10

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

C2348

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2349

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 92

23

23

7

23 24 27 92

23 24 27 92

23 24 27 92

23 24

23 24
92
27

23

23
7

23 27 92

23

7

23 24 27 92

23 24 27 92

23 27 92

7

7
92

7

7
27 92

7
27 92

7
27 92

7
27 92

7
27 92

7
27 92

7
27 92

7
92

7
24 27

7
24 27
92

7

7

7
27 92

7
27 92

7
24 27
92

7
24 27 92

7

7

7

2

R2350

240

1%
1/20W
MF
201

1

C2357

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ODT<0>
MEM_A_ZQ<5>

PP1V35_S3_MEM

1

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

J2

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2347

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 92

MEM_A_A<1>

7

23 24

27 92

MEM_A_A<2>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

B

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23 24

27 92

MEM_A_A<12>

7

23 24

27 92

MEM_A_A<13>

7

23 24

27 92

MEM_A_A<14>

7

23 24

27 92

MEM_A_A<15>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<2>

7

23 24

27 92

MEM_A_RAS_L

7

23 24

27 92

MEM_A_CAS_L

7

23 24

27 92

MEM_A_WE_L

7

23 24

27 92

MEM_A_ODT<0>

7

23 27

92

MEM_A_ZQ<4>

2

R2340

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2350

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2358

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

N1

1

1

C2359

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_A_DQ<40>

MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>

MEM_A_DQS_P<5>
MEM_A_DQS_N<5>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_A_A<0>

7

23 24 27 92

MEM_A_A<1>

7

23 24 27

92

MEM_A_A<2>

7

23 24 27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24
27 92

92

MEM_A_A<11>

7

23

24 27

7
24 92

MEM_A_A<12>

7

24 92

MEM_A_A<13>

7

23 24 27 92

MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

92
27

MEM_A_BA<2>

7

23

23

24 27

7

92

23 27 92

MEM_A_RAS_L

7

23

7

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<0>

7

23 27 92

MEM_A_ZQ<6>

2

R2360

240

1%
1/20W
MF
201

1

C2367

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

E3C2B10

M10

M2

K10

K2G3G9D8A10

OMIT_TABLE

U2360

DDR3-1333

(SYM VER 2)

VDDQ

FBGA

VSS

F9D9A9F3N2L2J2

J10

N10

L10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2368

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2369

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>

MEM_A_DQS_P<6>
MEM_A_DQS_N<6>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_A_A<0>

7

23 24 27 92

MEM_A_A<1>

7

23 24 27

92

MEM_A_A<2>

7

23 24 27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<5>

7

24 92

MEM_A_A<6>

7

24 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24
27 92

92

MEM_A_A<11>

7

23

24 27

MEM_A_A<12>

7

23

24 27
92

MEM_A_A<13>

7

23 24 27 92

MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

92
27

MEM_A_BA<2>

7

23

23

24 27

7

92

23 27 92

MEM_A_RAS_L

7

23

7

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<0>

7

23 27 92

MEM_A_ZQ<7>

2

R2370

240

1%
1/20W
MF
201

1

C2377

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

E3C2B10

M10

M2

K10

K2G3G9D8A10

OMIT_TABLE

U2370

DDR3-1333

(SYM VER 2)

VDDQ

FBGA

VSS

F9D9A9F3N2L2J2

J10

N10

L10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2378

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2379

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_A_DQ<56>

MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

NC

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

7

24 92

B

7

24 92

7

24 92

7

24 92

7

23 27

92
7

23 27

92

7

23 27

92
7

23 27

92

PP1V35_S3_MEM

22 23 24 25 26 27 45 84 92

A

C2300

2.2UF

X5R-CERM

C2340

2.2UF

X5R-CERM

1

C2301

20%
10V

2

402

1

C2341

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2310

20%
10V

2

402

1

C2350

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2311

20%
10V

2

402

1

C2351

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2320

2.2UF

X5R-CERM

C2360

2.2UF

X5R-CERM

1

C2321

20%
10V

2

X5R-CERM

402

1

C2361

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

2.2UF

1

20%
10V

2

402

1

20%
10V

2

402

C2330

2.2UF

X5R-CERM

C2370

2.2UF

X5R-CERM

1

C2331

2.2UF

2

1

2

X5R-CERM

C2371

2.2UF

X5R-CERM

20%
10V

402

20%
10V

402

20%
10V

402

20%
10V

402

1

1

C2303

0.1UF

10%

6.3V

2

2

1

2

CERM-X5R
0201

1

C2343

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2304

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2344

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2305

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2345

0.1UF

10%

6.3V

2

CERM-X5R
0201

6 3

1

C2313

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2353

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2314

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2354

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2315

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2355

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2323

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2363

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2324

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2364

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2325

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2365

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2333

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2373

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2334

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2374

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2335

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2375

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=J15_MLB

PAGE TITLE

DDR3 SDRAM Bank A (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

23 OF 119

SHEET

23 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2400

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9

D2

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2408

0.047UF

J9

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<6>

C8

MEM_A_DQ<0>

C3

MEM_A_DQ<5>

C9

MEM_A_DQ<7>

E4

MEM_A_DQ<4>

E9

MEM_A_DQ<2>

D3

MEM_A_DQ<1>

E8

MEM_A_DQ<3>

C4

MEM_A_DQS_P<0>

D4

MEM_A_DQS_N<0>

B8
A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

6.3V

MEM_A_A<0>

7

MEM_A_A<1>

7
92

MEM_A_A<2>

7

MEM_A_A<4>

7
27 92

MEM_A_A<3>

7
27 92

MEM_A_A<6>

7
27 92

MEM_A_A<5>

7
27 92

MEM_A_A<8>

7
27 92

MEM_A_A<7>

7
27 92

MEM_A_A<9>

7
27 92

MEM_A_A<10>

7
92

MEM_A_A<11>

7
24 27

MEM_A_A<12>

23 92

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>
MEM_A_BA<0>

7
27 92

MEM_A_BA<2>

7
24 27
92

MEM_A_RAS_L
MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

C2417

0.47UF

CERM-X5R-1

1

1

C2409

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24
27 92

23
7
23 92
7

23 24 27 92

23 24 27 92

23 24 27 92

7

24 27

92

23 24

23

92
7
24 27

7

24 27

92

23 24 27 92

23 24 27 92

24 27 92

MEM_A_ZQ<9>

2

R2410

240

1%
1/20W
MF
201

1

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2407

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 92

MEM_A_A<1>

7

23 24

D

27 92

MEM_A_A<2>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23 24

27 92

MEM_A_A<12>

7

23 24

27 92

MEM_A_A<13>

7

23 24

27 92

MEM_A_A<14>

7

23 24

27 92

MEM_A_A<15>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<2>

7

23 24

27 92

MEM_A_RAS_L

7

23 24

27 92

MEM_A_CAS_L

7

23 24

27 92

MEM_A_WE_L

7

23 24

27 92

MEM_A_ODT<1>

7

24 27

92

MEM_A_ZQ<8>

2

C

R2400

240

1%
1/20W
MF
201

1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2410

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

1

MEM_A_A<0>

7

MEM_A_A<1>

7
92

7

MEM_A_A<4>

7
27 92

MEM_A_A<3>

7
27 92

MEM_A_A<6>

7
27 92

MEM_A_A<5>

7
27 92

MEM_A_A<8>

7
27 92

MEM_A_A<7>

7
27 92

MEM_A_A<9>

7
27 92

MEM_A_A<10>

7
27 92

MEM_A_A<11>

23

92

MEM_A_A<12>

7
24 27

MEM_A_A<13>

7

MEM_A_A<14>

7

MEM_A_A<15>

7

MEM_A_BA<1>

7
27 92

MEM_A_BA<0>

7
92

MEM_A_BA<2>

7
24 27

MEM_A_RAS_L

7
24 27 92

MEM_A_CAS_L

7

MEM_A_WE_L

7

MEM_A_ODT<1>

7

MEM_A_ZQ<10>

2

R2420

240

1%
1/20W
MF
201

1

C2427

0.47UF

CERM-X5R-1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2418

0.047UF

10%

6.3V
X5R
201

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<9>

C8

MEM_A_DQ<14>

C3

MEM_A_DQ<15>

C9

MEM_A_DQ<10>

E4

MEM_A_DQ<12>

E9

MEM_A_DQ<8>

D3

MEM_A_DQ<13>

E8

MEM_A_DQ<11>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8
A8

NC NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C2419

0.047UF

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

23 24

23 24

23 24

23 24

23 24

23 24

23 24

23 24

92
7

23

23 24 27 92

23 24 27 92

23 24 27 92

23 24

23 24
27 92

23

24 27 92

23

7

23 24 27 92

23 24 27 92

24 27 92

D10

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92 22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2420

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2428

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2429

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<23>
MEM_A_DQ<18>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_A_A<0>

7

23 24 27 92

MEM_A_A<1>

7

23 24 27

92

MEM_A_A<2>MEM_A_A<2>

7

23 24 27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24
27 92

92

MEM_A_A<11>

7

23

24 27

MEM_A_A<12>

7

23

24 27
92

MEM_A_A<13>

7

23 24 27 92

MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<2>

7

23

92

24 27

7

92

24 27

MEM_A_RAS_L

7

23

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<1>

7

24 27 92

MEM_A_ZQ<11>

2

R2430

240

1%
1/20W
MF
201

1

C2437

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2430

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2438

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<24>

C8

MEM_A_DQ<31>

C3

MEM_A_DQ<28>

C9

MEM_A_DQ<27>

E4

MEM_A_DQ<29>

E9

MEM_A_DQ<26>

D3

MEM_A_DQ<25>

E8

MEM_A_DQ<30>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8
A8

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2439

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

24 27

92
7

24 27

92

7

24 27

92
7

24 27

92

C

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2440

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9

D2

C10

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

C2448

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2449

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

23 24 27 92

23 24 27

23 24 27 92

7

23 92

23 24

23 24

23 24

23 24

7

23 92

7

23 92

23 24
27 92

23

7
23 92

7

23 92

23 24 27 92

23 24 27 92

23 24 27 92

23 24

7

24 27

92

23
7
24 27 92
7

24 27
92

23 24 27 92

23 24 27 92

24 27 92

7

7
92

7

7
27 92

7
27 92

7
27 92

7
27 92

7
92

7
24 27

7

7

7

7
27 92

92
7
24 27

7

7

7

2

R2450

240

1%
1/20W
MF
201

1

C2457

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ODT<1>
MEM_A_ZQ<13>

PP1V35_S3_MEM

1

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

J2

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2447

CERM-X5R-1

MEM_A_A<0>

7

23 24

27 92

MEM_A_A<1>

7

23 24

27 92

MEM_A_A<2>

7

23 24

27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

B

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23 24

27 92

MEM_A_A<12>

7

23 24

27 92

MEM_A_A<13>

7

23 24

27 92

MEM_A_A<14>

7

23 24

27 92

MEM_A_A<15>

7

23 24

27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<2>

7

23 24

27 92

MEM_A_RAS_L

7

23 24

27 92

MEM_A_CAS_L

7

23 24

27 92

MEM_A_WE_L

7

23 24

27 92

MEM_A_ODT<1>

7

24 27

92

MEM_A_ZQ<12>

2

R2440

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92 22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2450

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

L10

N10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2458

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

N1

1

1

C2459

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_A_DQ<41>

MEM_A_DQ<40>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>

MEM_A_DQS_P<5>
MEM_A_DQS_N<5>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

23 24 27 92

25 26
21 23 24

7

7

27 92

7
23 92

7

92
27
24
7

24 27 92
7

MEM_A_A<0>

7

23 24 27 92

23 24 27 92

MEM_A_A<1>

7

MEM_A_A<2>

7

23 24 27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<6>

23 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<8>

23 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23
24

92

MEM_A_A<12>

7

23

24 27

MEM_A_A<13>
MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

MEM_A_BA<2>

7

23

24 27
92

MEM_A_RAS_L

7

23

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<1>

7

24 27 92

MEM_A_ZQ<14>

2

R2460

240

1%
1/20W
MF
201

1

C2467

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2460

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2468

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2469

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>

MEM_A_DQS_P<6>
MEM_A_DQS_N<6>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_A_A<0>

7

23 24 27 92

MEM_A_A<1>

7

23 24 27

92

MEM_A_A<2>

7

23 24 27 92

MEM_A_A<4>

7

23 24

27 92

MEM_A_A<3>

7

23 24

27 92

MEM_A_A<6>

7

23 24

27 92

MEM_A_A<5>

7

23 24

27 92

MEM_A_A<8>

7

23 24

27 92

MEM_A_A<7>

7

23 24

27 92

MEM_A_A<9>

7

23 24

27 92

MEM_A_A<10>

7

23 24

27 92

MEM_A_A<11>

7

23

24 27
92

MEM_A_A<12>

7

23

24 27
92

MEM_A_A<13>

7

23 24 27 92

MEM_A_A<14>

7

23 24 27 92

MEM_A_A<15>

7

23 24 27 92

MEM_A_BA<1>

7

23 24

27 92

MEM_A_BA<0>

7

23 24

27 92

92
27

MEM_A_BA<2>

7

23

24

24 27

7

92

24 27 92

MEM_A_RAS_L

7

23

7

24 27 92

MEM_A_CAS_L

7

23 24 27 92

MEM_A_WE_L

7

23 24 27 92

MEM_A_ODT<1>

7

24 27 92

MEM_A_ZQ<15>

2

R2470

240

1%
1/20W
MF
201

1

C2477

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2470

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2478

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2479

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_A_DQ<57>

MEM_A_DQ<56>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

NC

MEM_A_CS_L<1>
MEM_A_CKE<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

7

23 92

B

7

23 92

7

23 92

7

23 92

7

24 27

92
7

24 27

92

7

24 27

92
7

24 27

92

PP1V35_S3_MEM

22 23 24 25 26 27 45 84 92

A

C2400

2.2UF

X5R-CERM

C2440

2.2UF

X5R-CERM

1

C2401

20%
10V

2

402

1

C2441

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2410

20%
10V

2

402

1

C2450

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2411

20%
10V

2

402

1

C2451

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2420

2.2UF

X5R-CERM

C2460

2.2UF

X5R-CERM

1

C2421

20%
10V

2

X5R-CERM

402

1

C2461

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

2.2UF

1

20%
10V

2

402

1

20%
10V

2

402

C2430

2.2UF

X5R-CERM

C2470

2.2UF

X5R-CERM

1

C2431

20%
10V

2

402

1

C2471

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

1

C2403

20%
10V

2

402

1

20%
10V

2

402

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2443

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2404

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2444

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2405

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2445

0.1UF

10%

6.3V

2

CERM-X5R
0201

6 3

1

C2413

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2453

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2414

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2454

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2415

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2455

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2423

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2463

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2424

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2464

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2425

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2465

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2433

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2473

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2434

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2474

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2435

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2475

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=J15_MLB

PAGE TITLE

DDR3 SDRAM Bank A (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

24 OF 119

SHEET

24 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2500

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9

D2

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2508

0.047UF

J9

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<6>

C8

MEM_B_DQ<1>

C3

MEM_B_DQ<3>

C9

MEM_B_DQ<5>

E4

MEM_B_DQ<2>

E9

MEM_B_DQ<4>

D3

MEM_B_DQ<7>

E8

MEM_B_DQ<0>

C4

MEM_B_DQS_P<0>

D4

MEM_B_DQS_N<0>

B8
A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

6.3V

1

1

C2509

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

25 26 27 92

25 26 27

25 26 27 92

25 26

25 26

7

26 92

25 26

25 26

25 26

25 26

25 26

27 92

25
26

25

25 26 27 92

25 26 27 92

25 26 27 92

25 26

25 26
92
27

25

25
7

25 27 92

25

7

25 26 27 92

25 26 27 92

25 27 92

C2517

0.47UF

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
92

MEM_B_A<2>

7

MEM_B_A<3>

7
27 92

MEM_B_A<4>

7
27 92

MEM_B_A<5>
MEM_B_A<6>

7
27 92

MEM_B_A<7>

7
27 92

MEM_B_A<8>

7
27 92

MEM_B_A<9>

7
27 92

MEM_B_A<10>

7
27 92

MEM_B_A<11>

7
92

MEM_B_A<12>

7
26 27

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 92

MEM_B_BA<1>

7
27 92

MEM_B_BA<2>

7
26 27
92

MEM_B_RAS_L

7
26 27 92

MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<0>

7

MEM_B_ZQ<1>

2

R2510

240

1%
1/20W
MF
201

1

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2507

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 92

MEM_B_A<1>

7

25 26

D

27 92

MEM_B_A<2>

7

25 26

27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

MEM_B_A<10>

7

25 26

27 92

MEM_B_A<11>

7

25 26

27 92

MEM_B_A<12>

7

25 26

27 92

MEM_B_A<13>

7

25 26

27 92

MEM_B_A<14>

7

25 26

27 92

MEM_B_A<15>

7

25 26

27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

MEM_B_BA<2>

7

25 26

27 92

MEM_B_RAS_L

7

25 26

27 92

MEM_B_CAS_L

7

25 26

27 92

MEM_B_WE_L MEM_B_WE_L

7

25 26

27 92

MEM_B_ODT<0>

7

25 27

92

MEM_B_ZQ<0>

2

C

R2500

240

1%
1/20W
MF
201

1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2510

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP1V35_S3_MEM

1

1

1

C2518

0.047UF

10%

6.3V
X5R
201

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<14>

C8

MEM_B_DQ<9>

C3

MEM_B_DQ<11>

C9

MEM_B_DQ<13>

E4

MEM_B_DQ<10>

E9

MEM_B_DQ<12>

D3

MEM_B_DQ<15>

E8

MEM_B_DQ<8>

C4

MEM_B_DQS_P<1>

D4

MEM_B_DQS_N<1>

B8
A8

NC NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C2519

0.047UF

10%

6.3V

2

2

X5R
201

25 26 27 92

25 26 27

25 26 27 92

25 26

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 92

25

25

25 26 27 92

25 26 27 92

25 26 27 92

25 26

25 26
92
27

25

25
7

25 27 92

25

7

25 26 27 92

25 26 27 92

25 27 92

D10

C2527

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7
92

MEM_B_A<2>

7

MEM_B_A<3>

7
27 92

MEM_B_A<4>

7
27 92

MEM_B_A<5>

7
27 92

MEM_B_A<6>

7
27 92

MEM_B_A<7>

7
27 92

MEM_B_A<8>

7
27 92

MEM_B_A<9>

7
27 92

MEM_B_A<10>

7
92

MEM_B_A<11>

7
26 27

MEM_B_A<12>

7
26 27
92

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<0>

7
27 92

MEM_B_BA<1>

7
27 92

MEM_B_BA<2>

7
26 27
92

MEM_B_RAS_L

7
26 27 92

MEM_B_CAS_L

7

7

MEM_B_ODT<0>

7

MEM_B_ZQ<2>

2

R2520

240

1%
1/20W
MF
201

1

0.47UF

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2520

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2528

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2529

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<18>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<16>
MEM_B_DQ<23>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<17>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27

92

MEM_B_A<2>

7

25 26 27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<5>

7

26 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

MEM_B_A<10>

7

25 26
27 92

92

MEM_B_A<11>

7

25

26 27

MEM_B_A<12>

7

25

26 27
92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

MEM_B_BA<2>

7

25 27 92

MEM_B_RAS_L

7

25 27

92

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<0>

7

25 27 92

MEM_B_ZQ<3>

2

R2530

240

1%
1/20W
MF
201

1

C2537

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2530

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2538

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<27>

C8

MEM_B_DQ<25>

C3

MEM_B_DQ<26>

C9

MEM_B_DQ<29>

E4

MEM_B_DQ<30>

E9

MEM_B_DQ<28>

D3

MEM_B_DQ<31>

E8

MEM_B_DQ<24>

C4

MEM_B_DQS_P<3>

D4

MEM_B_DQS_N<3>

B8
A8

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2539

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

25 27

92
7

25 27

92

7

25 27

92
7

25 27

92

C

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2540

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9

D2

C10

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

C2548

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2549

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>

MEM_B_DQS_P<4>
MEM_B_DQS_N<4>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

25 26 27 92

25 26 27

25 26 27 92

7

26 92

25 26

25 26

25 26

25 26

25 26

25 26

25 26
27 92

25

25

7

25 26 27 92

25 26 27 92

25 26 27 92

25 26

25 26
92
27

25

25
7

25 27 92

25

7

25 26 27 92

25 26 27 92

25 27 92

7

7
92

7

7
27 92

7
27 92

7
27 92

7
27 92

7
27 92

7
27 92

7
92

7
26 27

7
26 27
92

7

7

7
27 92

7
27 92

7
26 27
92

7
26 27 92

7

7

7

2

R2550

240

1%
1/20W
MF
201

1

C2557

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_ODT<0>
MEM_B_ZQ<5>

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2547

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 92

MEM_B_A<1>

7

25 26

27 92

MEM_B_A<2>

7

25 26

27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

B

MEM_B_A<10>

7

25 26

27 92

MEM_B_A<11>

7

25 26

27 92

MEM_B_A<12>

7

25 26

27 92

MEM_B_A<13>

7

25 26

27 92

MEM_B_A<14>

7

25 26

27 92

MEM_B_A<15>

7

25 26

27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

MEM_B_BA<2>

7

25 26

27 92

MEM_B_RAS_L

7

25 26

27 92

MEM_B_CAS_L

7

25 26

27 92

MEM_B_WE_L

7

25 26

27 92

MEM_B_ODT<0>

7

25 27

92

MEM_B_ZQ<4>

2

R2540

240

1%
1/20W
MF
201

1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2550

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2558

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

N1

1

1

C2559

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_B_DQ<40>

MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>

MEM_B_DQS_P<5>
MEM_B_DQS_N<5>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27

92

MEM_B_A<2>

7

25 26 27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

MEM_B_A<10>

7

25 26
27 92

92

MEM_B_A<11>

7

25

26 27

MEM_B_A<12>

7

25

26 27
92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

92
27

MEM_B_BA<2>

7

25

25

26 27

7

92

25 27 92

MEM_B_RAS_L

7

25

7

26 27 92

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<0>

7

25 27 92

MEM_B_ZQ<6>

2

R2560

240

1%
1/20W
MF
201

1

C2567

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2560

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2568

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2569

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>

MEM_B_DQS_P<6>
MEM_B_DQS_N<6>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27

92

MEM_B_A<2>

7

25 26 27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

MEM_B_A<10>

7

25 26
27 92

92

MEM_B_A<11>

7

25

26 27

MEM_B_A<12>

7

25

26 27
92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

92
27

MEM_B_BA<2>

7

25

25

26 27

7

92

25 27 92

MEM_B_RAS_L

7

25

7

26 27 92

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<0>

7

25 27 92

MEM_B_ZQ<7>

2

R2570

240

1%
1/20W
MF
201

1

C2577

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2570

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2578

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2579

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_B_DQ<56>

MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

NC

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

7

26 92

B

7

26 92

7

26 92

7

26 92

7

25 27

92
7

25 27

92

7

25 27

92
7

25 27

92

PP1V35_S3_MEM

22 23 24 25 26 27 45 84 92

A

C2500

2.2UF

X5R-CERM

C2540

2.2UF

X5R-CERM

1

C2501

20%
10V

2

402

1

C2541

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2510

20%
10V

2

402

1

C2550

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2511

20%
10V

2

402

1

C2551

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2520

2.2UF

X5R-CERM

C2560

2.2UF

X5R-CERM

1

C2521

20%
10V

2

X5R-CERM

402

1

C2561

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

2.2UF

1

20%
10V

2

402

1

20%
10V

2

402

C2530

2.2UF

X5R-CERM

C2570

2.2UF

X5R-CERM

1

C2531

20%
10V

2

402

1

C2571

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

1

C2503

20%
10V

2

402

1

20%
10V

2

402

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2543

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2504

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2544

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2505

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2545

0.1UF

10%

6.3V

2

CERM-X5R
0201

6 3

1

C2513

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2553

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2514

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2554

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2515

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2555

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2523

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2563

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2524

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2564

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2525

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2565

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2533

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2573

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2534

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2574

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2535

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2575

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=J15_MLB

PAGE TITLE

DDR3 SDRAM Bank B (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

25 OF 119

SHEET

25 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2600

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9

D2

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

C2608

0.047UF

J9

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<1>

C8

MEM_B_DQ<6>

C3

MEM_B_DQ<5>

C9

MEM_B_DQ<3>

E4

MEM_B_DQ<0>

E9

MEM_B_DQ<7>

D3

MEM_B_DQ<4>

E8

MEM_B_DQ<2>

C4

MEM_B_DQS_P<0>

D4

MEM_B_DQS_N<0>

B8
A8

NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

6.3V

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

201

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

J2

B2

A2

1

1

C2609

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

25 26 27 92

25 26 27

92

21 23 24
25 26

7

25 92

25 26

7

25 92

25 26

7

25 92

7

25 92

7

25 92

25 26

7

7

25 26 27 92

25 26 27 92

25 26 27 92

7

26 27

92
7

26 27

92

7

26 27 92

7

26 27

92

25 26 27 92

25 26 27 92

26 27 92

C2617

CERM-X5R-1

MEM_B_A<0>

7

MEM_B_A<1>

7

MEM_B_A<2> MEM_B_A<2>

7
25 26 27 92

MEM_B_A<4>
MEM_B_A<3>

7
27 92

MEM_B_A<6>
MEM_B_A<5>

7
27 92

MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<9>
MEM_B_A<10>

7
27 92

MEM_B_A<11>

25 92

MEM_B_A<12>

25 92

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<1>

7

MEM_B_ZQ<9>

2

R2610

240

1%
1/20W
MF
201

1

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2607

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 92

MEM_B_A<1>

7

25 26

D

27 92

MEM_B_A<2>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

MEM_B_A<10>

7

25 26

27 92

MEM_B_A<11>

7

25 26

27 92

MEM_B_A<12>

7

25 26

27 92

MEM_B_A<13>

7

25 26

27 92

MEM_B_A<14>

7

25 26

27 92

MEM_B_A<15>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<2>

7

25 26

27 92

MEM_B_RAS_L

7

25 26

27 92

MEM_B_CAS_L

7

25 26

27 92

MEM_B_WE_L

7

25 26

27 92

MEM_B_ODT<1>

7

26 27

92

MEM_B_ZQ<8>

2

C

R2600

240

1%
1/20W
MF
201

1

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2610

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2

E10

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

J9

VREFDQ

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK

CK*

NC

C10

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

MEM_B_A<0>

7

MEM_B_A<1>

7

7
25 26 27 92

MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<9>
MEM_B_A<10>

26 27 92

MEM_B_A<11>

7

25 92

MEM_B_A<12>

25 92

MEM_B_A<13>

7

MEM_B_A<14>

7

MEM_B_A<15>

7

MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L

7

MEM_B_WE_L

7

MEM_B_ODT<1>

7

MEM_B_ZQ<10>

2

R2620

240

1%
1/20W
MF
201

1

C2627

0.47UF

CERM-X5R-1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

1

1

C2618

0.047UF

10%

6.3V
X5R
201

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<9>

C8

MEM_B_DQ<14>

C3

MEM_B_DQ<13>

C9

MEM_B_DQ<11>

E4

MEM_B_DQ<8>

E9

MEM_B_DQ<15>

D3

MEM_B_DQ<12>

E8

MEM_B_DQ<10>

C4

MEM_B_DQS_P<1>

D4

MEM_B_DQS_N<1>

B8
A8

NC NC

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C2619

0.047UF

10%

6.3V

2

2

X5R
201

25 26 27 92

25 26 27

92

21 23 24
25 26

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

25

7

7

25 26 27 92

25 26 27 92

25 26 27 92

7

26 27

92
7

26 27

92

7

26 27 92

7

26 27

92

25 26 27 92

25 26 27 92

26 27 92

D10

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2620

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2

E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

B9D2B3

DQ0
DQ1
DQ2
DQ3

DQS

DQS*

CS*
CKE

CK*

NC

C10

J9

VREFCA

CK

C2628

0.047UF

H2
H10

N1

NC

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

D10

1

1

C2629

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<20>
MEM_B_DQ<18>
MEM_B_DQ<16>
MEM_B_DQ<19>
MEM_B_DQ<17>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<23>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>

NC

MEM_B_CS_L<1>
MEM_B_CKE<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

92

21 23 24
25 26

7

7

7

7

7

7

7

7

7

7

7
92

7
92

7

7
92

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27

MEM_B_A<2>

7
25 26 27 92

MEM_B_A<4>

25 92

MEM_B_A<3>

25 92

MEM_B_A<6>

25 92

MEM_B_A<5>

25 92

MEM_B_A<8>

25 92

MEM_B_A<7>

25 92

MEM_B_A<9>

25 92

MEM_B_A<10>

25 92

26 27 92

MEM_B_A<11>

7

25

25 92

MEM_B_A<12>

25 92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<1>

26 27

MEM_B_BA<0>

26 27

MEM_B_BA<2>

26 27 92

MEM_B_RAS_L

26 27

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<1>

7

26 27 92

MEM_B_ZQ<11>

2

R2630

240

1%
1/20W
MF
201

1

C2637

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2630

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9F3N2L2J2

J10

N10

L10

VDDQ

E10

E3C2B10

E2

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

DQ0
DQ1
DQ2
DQ3

DQS

J9

CK

C2638

0.047UF

6.3V

H2

NC

H10

NC

N1

NC

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<25>

C8

MEM_B_DQ<27>

C3

MEM_B_DQ<29>

C9

MEM_B_DQ<26>

E4

MEM_B_DQ<24>

E9

MEM_B_DQ<31>

D3

MEM_B_DQ<28>

E8

MEM_B_DQ<30>

C4

MEM_B_DQS_P<3>

D4

MEM_B_DQS_N<3>

B8
A8

H3

MEM_B_CS_L<1>

G10

MEM_B_CKE<1>

F8

MEM_B_CLK_P<1>

G8

MEM_B_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

1

C2639

0.047UF

10%
X5R

201

10%

6.3V

2

2

X5R
201

D

21 23 24 25 26

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

26 27

92
7

26 27

92

7

26 27

92
7

26 27

92

C

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

J2

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2640

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9

D9A9F3N2L2

J10

L10

B10

N10

C2

VDDQ

E3

B3

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9

D2

C10

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

C2648

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2649

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>

MEM_B_DQS_P<4>
MEM_B_DQS_N<4>

NC

MEM_B_CS_L<1>
MEM_B_CKE<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

7

7

7

7

7

7

7

7

7

7

7
92

7
92

7

7
92

7

25 26 27 92

7

25 26 27

92
7

25 26 27 92

25 92

25 92

25 92

25 92

25 92

25 92

25 92

25 92

26 27 92
7

25

25 92

25 92

7

25 26 27 92

7

25 26 27 92

7

25 26 27 92

26 27

26 27

26 27 92

26 27

7

25 26 27 92

7

25 26 27 92

7

26 27 92

2

R2650

240

1%
1/20W
MF
201

1

C2657

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_ODT<1>
MEM_B_ZQ<13>

PP1V35_S3_MEM

0.47UF

1

20%

4V

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

C2647

CERM-X5R-1

MEM_B_A<0>

7

25 26

27 92

MEM_B_A<1>

7

25 26

27 92

MEM_B_A<2>

7

25 26

27 92

MEM_B_A<4>

7

25 26

27 92

MEM_B_A<3>

7

25 26

27 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<5>

7

25 26

27 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<7>

7

25 26

27 92

MEM_B_A<9>

7

25 26

27 92

B

MEM_B_A<10>

7

25 26

27 92

MEM_B_A<11>

7

25 26

27 92

MEM_B_A<12>

7

25 26

27 92

MEM_B_A<13>

7

25 26

27 92

MEM_B_A<14>

7

25 26

27 92

MEM_B_A<15>

7

25 26

27 92

MEM_B_BA<1>

7

25 26

27 92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<2>

7

25 26

27 92

MEM_B_RAS_L

7

25 26

27 92

MEM_B_CAS_L

7

25 26

27 92

MEM_B_WE_L

7

25 26

27 92

MEM_B_ODT<1>

7

26 27

92

MEM_B_ZQ<12>

2

R2640

240

1%
1/20W
MF
201

1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

J2

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

M10

M2

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2650

DDR3-1333

FBGA

(SYM VER 2)

VSS

F9D9A9

F3N2L2

J10

N10

L10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2658

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

N1

1

1

C2659

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_B_DQ<41>

MEM_B_DQ<40>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>

MEM_B_DQS_P<5>
MEM_B_DQS_N<5>

NC

MEM_B_CS_L<1>
MEM_B_CKE<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

1

C2667

0.47UF

20%

4V

CERM-X5R-1

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27

92

21 23 24
25 26

MEM_B_A<2> MEM_B_A<2>

7
25 26 27 92

MEM_B_A<4>

7

25 92

MEM_B_A<3>

7

25 92

MEM_B_A<6>

7

25 92

MEM_B_A<5>

7

25 92

MEM_B_A<8>

7

25 26

27 92

MEM_B_A<7>

7

25 92

MEM_B_A<9>

7

25 92

MEM_B_A<10>

7

25 92

26 27 92

MEM_B_A<11>

7

25

7

25 92

MEM_B_A<12>

7

25 92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<1>

7

26 27

92

MEM_B_BA<0>

7

26 27

92

MEM_B_BA<2>

7

26 27 92

MEM_B_RAS_L

7

26 27

92

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<1>

7

26 27 92

MEM_B_ZQ<14>

2

R2660

240

1%
1/20W
MF
201

1

2

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

A3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

201

22 23 24 25 26 85 89 92

K10

K2G3G9D8A10

VDD

OMIT_TABLE

U2660

DDR3-1333

(SYM VER 2)

VSS

22 23 24 25 26 27 45
84 92

M10

M2

FBGA

F9D9A9F3N2L2J2

J10

L10

N10

VDDQ

E3C2B10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2668

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2669

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L

MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>

MEM_B_DQS_P<6>
MEM_B_DQS_N<6>

NC

MEM_B_CS_L<1>
MEM_B_CKE<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

92

MEM_B_A<0>

7

25 26 27 92

MEM_B_A<1>

7

25 26 27
21 23 24
25 26

7
25 26 27 92

MEM_B_A<4>

7

25 92

MEM_B_A<3>

7

25 92

MEM_B_A<6>

7

25 26

27 92

MEM_B_A<5>

7

25 92

MEM_B_A<8>

7

25 92

MEM_B_A<7>

7

25 92

MEM_B_A<9>

7

25 92

MEM_B_A<10>

7

25 92

26 27 92

MEM_B_A<11>

7

25

7

25 92

MEM_B_A<12>

7

25 92

MEM_B_A<13>

7

25 26 27 92

MEM_B_A<14>

7

25 26 27 92

MEM_B_A<15>

7

25 26 27 92

MEM_B_BA<1>

7

26 27

92

MEM_B_BA<0>

7

25 26

27 92

MEM_B_BA<2>

7

26 27 92

26 27 92

MEM_B_RAS_L

7

25

7

26 27 92

MEM_B_CAS_L

7

25 26 27 92

MEM_B_WE_L

7

25 26 27 92

MEM_B_ODT<1>

7

26 27 92

MEM_B_ZQ<15>

2

R2670

240

1%
1/20W
MF
201

1

C2677

0.47UF

CERM-X5R-1

1

20%

4V

2

201

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8

J3
K9
J4

F4
G4
H4

G2

H9

PP1V35_S3_MEM

A3

VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*

ODT

ZQ

B2

A2

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

22 23 24 25 26 27 45
84 92

E3C2B10

M10

M2

K10

K2G3G9D8A10

OMIT_TABLE

U2670

DDR3-1333

(SYM VER 2)

VDDQ

FBGA

VSS

F9D9A9F3N2L2J2

J10

N10

L10

E2J9E10

VREFDQ

RESET*

NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS*
CKE

CK*

NC

VSSQ

B9D2B3

C10

C2678

0.047UF

NC

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

D10

H2
H10

N1

N11
N3

B4
C8
C3
C9
E4
E9
D3
E8

C4
D4

B8
A8

H3
G10

F8
G8

A1
A4
A11
F2
F10

1

1

C2679

0.047UF

10%

6.3V
X5R
201

NC
NC

NC
NC

MEM_RESET_L
MEM_B_DQ<57>

MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

NC

MEM_B_CS_L<1>
MEM_B_CKE<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

NC
NC
NC
NC
NC

10%

6.3V

2

2

X5R
201

21 23 24 25 26

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

7

25 92

B

7

25 92

7

25 92

7

25 92

7

26 27

92
7

26 27

92

7

26 27

92
7

26 27

92

PP1V35_S3_MEM

22 23 24 25 26 27 45 84 92

A

C2600

2.2UF

X5R-CERM

C2640

2.2UF

X5R-CERM

1

C2601

20%
10V

2

402

1

C2641

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2610

20%
10V

2

402

1

C2650

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2611

20%
10V

2

402

1

C2651

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20%
10V

2

402

1

20%
10V

2

402

C2620

2.2UF

X5R-CERM

C2660

2.2UF

X5R-CERM

1

C2621

20%
10V

2

X5R-CERM

402

1

C2661

20%
10V

2

X5R-CERM

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

2.2UF

1

20%
10V

2

402

1

20%
10V

2

402

C2630

2.2UF

X5R-CERM

C2670

2.2UF

X5R-CERM

1

C2631

20%
10V

2

402

1

C2671

20%
10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

1

C2603

20%
10V

2

402

1

20%
10V

2

402

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2643

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2604

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2644

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2605

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2645

0.1UF

10%

6.3V

2

CERM-X5R
0201

6 3

1

C2613

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2653

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2614

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2654

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2615

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2655

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2623

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2663

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2624

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2664

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2625

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2665

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2633

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2673

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2634

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2674

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2635

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C2675

0.1UF

10%

6.3V

2

CERM-X5R
0201

SYNC_MASTER=J15_MLB

PAGE TITLE

DDR3 SDRAM Bank B (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

26 OF 119

SHEET

26 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

PPVTT_S0_DDR

7

23 92

MEM_A_CS_L<0>

IN

MEM_A_ODT<0>

7

23 92

IN

7

23 24 92

MEM_A_CAS_L

IN

7

24 92

MEM_A_CKE<1>
FOR DESENSE IMPROVEMENT
PLACE ONE AT EACH DDR3L MEMORY MODULE.

PP1V35_S3_MEM

D

CRITICAL

C2740

12PF

5%

25V

NP0-C0G

0201

CRITICAL

C2770

12PF

5%

25V

NP0-C0G

0201

CRITICAL

1

C2741

2

CRITICAL

1

C2771

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

25V

25V

PP1V35_S3_MEM

CRITICAL

C2780

NP0-C0G

CRITICAL

C2790

C

NP0-C0G

12PF

0201

12PF

0201

25V

25V

5%

5%

CRITICAL

1

C2781

2

CRITICAL

1

C2791

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

25V

25V

5%

5%

5%

5%

1

2

CRITICAL

1

2

1

2

CRITICAL

1

2

22 23 24 25 26 27 45 84 92

CRITICAL

CRITICAL

1

C2742

12PF

5%

25V

2

NP0-C0G

0201

1

C2772

12PF

5%

25V

2

NP0-C0G

0201

22 23 24 25 26 27 45 84 92

1

C2782

12PF

5%

25V

2

NP0-C0G

0201

1

C2792

12PF

5%

25V

2

NP0-C0G

0201

CRITICAL

C2743

12PF

25V

NP0-C0G

0201

CRITICAL

C2773

12PF

25V

NP0-C0G

0201

CRITICAL

C2783

12PF

25V

NP0-C0G

0201

CRITICAL

C2793

12PF

25V

NP0-C0G

0201

5%

5%

5%

5%

CRITICAL

1

C2744

2

CRITICAL

1

C2774

2

CRITICAL

1

C2784

2

CRITICAL

1

C2794

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

25V

25V

25V

25V

5%

5%

5%

5%

CRITICAL

1

C2745

2

CRITICAL

1

C2775

2

CRITICAL

1

C2785

2

CRITICAL

1

C2795

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

5%

25V

5%

25V

5%

25V

5%

25V

CRITICAL

1

C2746

2

CRITICAL

1

C2776

2

CRITICAL

1

C2786

2

CRITICAL

1

C2796

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

25V

25V

25V

25V

5%

5%

5%

5%

CRITICAL

1

C2747

2

CRITICAL

1

C2777

2

CRITICAL

1

C2787

2

CRITICAL

1

C2797

2

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

12PF

NP0-C0G

0201

1

5%

25V

2

1

5%

25V

2

1

5%

25V

2

1

5%

25V

2

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 92

7

24 92

7

23 24 92

7

24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

7

23 24 92

IN

MEM_A_BA<0>

IN

MEM_A_A<0>

IN

MEM_A_BA<2>

IN

MEM_A_WE_L

IN

MEM_A_A<5>

IN

MEM_A_BA<1>

IN

MEM_A_A<6>

IN

MEM_A_A<4>

IN

MEM_A_RAS_L

IN

MEM_A_CKE<0>

IN

MEM_A_ODT<1>

IN

MEM_A_A<10>

IN

MEM_A_CS_L<1>

IN

MEM_A_A<15>

IN

MEM_A_A<12>

IN

MEM_A_A<3>

IN

MEM_A_A<8>

IN

MEM_A_A<7>

IN

MEM_A_A<11>

IN

MEM_A_A<9>

IN

MEM_A_A<2>

IN

MEM_A_A<1>

IN

MEM_A_A<14>

IN

MEM_A_A<13>

IN

RP2701
RP2701
RP2701
RP2701

RP2702
RP2702
RP2702
RP2702

RP2703
RP2703
RP2703
RP2703

RP2704
RP2704
RP2704
RP2704

RP2705
RP2705
RP2705
RP2705

RP2706
RP2706
RP2706
RP2706

RP2707
RP2707
RP2707
RP2707

21 27 60 84 86

36
36
36
36

36
36
36
36

36
36
36

36
36
36
36

36

36
36

36
36
36
36

36
36
36
36

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

5%

1/32W
1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%
5%

1/32W

5%

1/32W

5%361/32W
5%

1/32W
1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%
5%361/32W
5%

1/32W

5%

1/32W

1/32W

5%

1/32W

5%
5%

1/32W
1/32W

5%

1/32W

5%
5%

1/32W
1/32W

5%

1/32W

5%

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

4X0201
4X0201
4X0201
4X0201

C2701,C2721 FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

1

C2700

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2701

12PF

5%
NP0-C0G

2

0201
25V

1

C2703

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2705

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2707

0.47UF

20%
4V

2

CERM-X5R-1
201

D

C

PPVTT_S0_DDR

7

25 26 92

25 92

25 26 92

25 26 92

25 26 92

25 92

MEM Clock Termination

Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM

R2750

30

MEM_A_CLK_N<0>

7

23 92

IN

3.3PF

+/-0.25PF

0201

3.3PF

+/-0.25PF

0201

3.3PF

+/-0.25PF

0201

1

25V

2

C0G

1

25V

2

C0G

1

25V

2

C0G

C2750

PLACE_NEAR=U2370.F8:3.2mm

MEM_A_CLK_P<0>

7

23 92

B

IN

7

24 92

IN

MEM_A_CLK_N<1>

C2755

PLACE_NEAR=U2470.F8:3.2mm

MEM_A_CLK_P<1>

7

24 92

IN

MEM_B_CLK_N<0>

7

25 92

IN

C2760

PLACE_NEAR=U2500.F8:3.2mm

7

25 92

IN

MEM_B_CLK_P<0>

A

MEM_B_CLK_N<1>

7

26 92

IN

PLACE_NEAR=U2600.F8:3.2mm

MEM_B_CLK_P<1>

7

26 92

IN

C2765

3.3PF

+/-0.25PF

0201

1

25V

2

C0G

5%

1/20W

MF

201

R2751

30

5%

1/20W

MF

201

R2755

30

5%

1/20W

MF

201

R2756

30

5%

1/20W

MF

201

R2760

30

5%

1/20W

MF

201

R2761

30

5%

1/20W

MF

201

R2765

30

5%

1/20W

MF

201

R2766

30

5%

1/20W

MF

201

21

MEM_A_CLK0_TERM_R

21

21

MEM_A_CLK1_TERM_R

21

21

MEM_B_CLK0_TERM_R

21

21

MEM_B_CLK1_TERM_R

21

C2751

0.1UF

10%

6.3V

CERM-X5R

0201

C2756

0.1UF

10%

6.3V

CERM-X5R

0201

C2761

0.1UF

10%

6.3V

CERM-X5R

0201

C2766

0.1UF

10%

6.3V

CERM-X5R

0201

21

21

21

21

25 92

25 26 92

25 26 92

25 26 92

25 26 92

26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

25 26 92

26 92

26 92

25 26 92

25 26 92

25 26 92

25 26 92

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

MEM_B_A<10>
MEM_B_CS_L<0>
MEM_B_BA<2>
MEM_B_BA<0>

MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_CKE<0>
MEM_B_WE_L

MEM_B_A<12>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_CS_L<1>

MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<1>
MEM_B_A<8>

MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<9>
MEM_B_A<14>

MEM_B_A<15>
MEM_B_CAS_L
MEM_B_CKE<1>
MEM_B_ODT<1>

MEM_B_BA<1>
MEM_B_A<0>
MEM_B_A<4>
MEM_B_A<5>

RP2720
RP2720
RP2720
RP2720

RP2722
RP2722
RP2722
RP2722

RP2724
RP2724
RP2724
RP2724

RP2725
RP2725
RP2725
RP2725

RP2726
RP2726
RP2726
RP2726

RP2728
RP2728
RP2728
RP2728

RP2730
RP2730
RP2730
RP2730

6 3

21 27 60 84 86

36
36
36

36
36
36
36

36
36
36
36

36
36
36
36

36
36

36

36
36
36

36
36
36

81

5%

1/32W

72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

81
72
63
54

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

SYNC_MASTER=CLEAN_X425

PAGE TITLE

1

C2720

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2722

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2724

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2726

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2728

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2730

0.47UF

20%
4V

2

CERM-X5R-1
201

DDR3 Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C2721

12PF

5%
NP0-C0G

2

0201
25V

1

C2723

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2725

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2727

0.47UF

20%
4V

2

CERM-X5R-1
201

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

27 OF 119

SHEET

27 OF 97

SIZE

B

A

D

124578

8 7 6 5 4 3

12

5%
MF

1

2

R2830

R2831

21

10%

21

10%

21

10%

21

10%

21

10%

21

10%

21

10%

21

10%

R2815

NOSTUFF

1

R2825

100

5%
1/20W
MF
201

2

82

OUT

100K

1/20W

201

82

OUT

100K

1/20W

201

OMIT

NONE
NONE
NONE
0201

5%
MF

5%
MF

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

1

2

1

2

1

2

89

PCIE_TBT_R2D_P<0>

87

0201

PCIE_TBT_R2D_N<0>

87 89

0201

89

PCIE_TBT_R2D_P<1>

87

0201

PCIE_TBT_R2D_N<1>

87 89

0201

89

PCIE_TBT_R2D_P<2>

87

0201

PCIE_TBT_R2D_N<2>

87 89

0201

89

PCIE_TBT_R2D_P<3>

87

0201

PCIE_TBT_R2D_N<3>

87 89

0201

TBT_PCIE_RESET_L

20

IN

TBT_PWR_ON_POC_RST_L

29

IN

TP_TBT_MONDC0
TP_TBT_MONDC1

DEBUG: For monitoring current/voltage

TBT_MONOBSP
TBT_MONOBSN

DEBUG: For monitoring clock

TBT_THERMDP

48 96

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

93

TBT_SPI_MISO

93

TBT_SPI_CS_L

93

TBT_SPI_CLK

93

JTAG_TBT_TDI

20

IN

JTAG_TBT_TMS

20

IN

JTAG_TBT_TCK

20

IN

JTAG_TBT_TDO

20

OUT

TBT_TEST_EN
TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

28 89 97

DP_TBTSNK0_ML_N<3>

28 89 97

DP_TBTSNK0_ML_P<2>

28 89 97

DP_TBTSNK0_ML_N<2>

28 89 97

DP_TBTSNK0_ML_P<1>

28 89 97

DP_TBTSNK0_ML_N<1>

28 89 97

DP_TBTSNK0_ML_P<0>

28 89 97

DP_TBTSNK0_ML_N<0>

28 89 97

DP_TBTSNK0_AUXCH_P

28 89 97

DP_TBTSNK0_AUXCH_N

28 89 97

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

28 89 97

DP_TBTSNK1_ML_N<3>

28 89 97

DP_TBTSNK1_ML_P<2>

28 89 97

DP_TBTSNK1_ML_N<2>

28 89 97

DP_TBTSNK1_ML_P<1>

28 89 97

DP_TBTSNK1_ML_N<1>

28 89 97

DP_TBTSNK1_ML_P<0>

28 89 97

DP_TBTSNK1_ML_N<0>

28 89 97

DP_TBTSNK1_AUXCH_P

28 89 97

DP_TBTSNK1_AUXCH_N

28 89 97

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

31 93

OUT

TBT_A_R2D_C_N<0>

31 93

OUT

TBT_A_D2R_P<0>

31 93

IN

TBT_A_D2R_N<0>

31 93

IN

TBT_A_CONFIG1_BUF

31 82 32 82

IN IN

TBT_A_CONFIG2_RC

31

IN

TBT_A_R2D_C_P<1>

31 93

OUT

TBT_A_R2D_C_N<1>

31 93

OUT

TBT_A_D2R_P<1>

31 87 93

IN

TBT_A_D2R_N<1>

31 87 93

IN

TBT_A_LSTX

31

OUT

TBT_A_LSRX

31

IN

DP_TBTPA_ML_C_P<1>

31 93

OUT

DP_TBTPA_ML_C_N<1>

31 93

OUT

DP_TBTPA_ML_C_P<3>

31 93

OUT

DP_TBTPA_ML_C_N<3>

31 93

OUT

DP_TBTPA_AUXCH_C_P

31 93

BI

DP_TBTPA_AUXCH_C_N

31 93

BI

DP_TBTPA_HPD

31

IN

TBT_A_HV_EN

28 30 31

OUT

TBT_A_CIO_SEL

31

OUT

TBT_A_DP_PWRDN

28 31

OUT

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15

PERP_2

AA16

PERN_2

AA18

PERP_3

AB19

PERN_3

P5

PERST_OD_N

R4

PWR_ON_POC_RSTN

AD23

MONDC0

AC24

MONDC1

W18

MONOBSP

W16

MONOBSN

AB7

THERMDA

AA2

EE_DI

Y3

EE_DO

T5

EE_CS_N

U8

EE_CLK

W2

TDI

AB1

TMS

AA6

TCK

U6

TDO

R6

TEST_EN

W8

TEST_PWR_GOOD

E14

DPSNK0_3_P

D13

DPSNK0_3_N

E16

DPSNK0_2_P

D15

DPSNK0_2_N

E18

DPSNK0_1_P

D17

DPSNK0_1_N

E20

DPSNK0_0_P

D19

DPSNK0_0_N

G4

DPSNK0_AUX_P

G2

DPSNK0_AUX_N

AB5

DPSNK0_HPD

E6

DPSNK1_3_P

D5

DPSNK1_3_N

E8

DPSNK1_2_P

D7

DPSNK1_2_N

E10

DPSNK1_1_P

D9

DPSNK1_1_N

E12

DPSNK1_0_P

D11

DPSNK1_0_N

H3

DPSNK1_AUX_P

H1

DPSNK1_AUX_N

U4

DPSNK1_HPD

G24

PA_CIO0_TX_P/DPSRC_0_P

E24

PA_CIO0_TX_N/DPSRC_0_N

G22

PA_CIO0_RX_P

E22

PA_CIO0_RX_N

P1

PA_CONFIG1/CIO_0_LSEO

K5

PA_CONFIG2/CIO_0_LSOE

L24

PA_CIO1_TX_P/DPSRC_2_P

J24

PA_CIO1_TX_N/DPSRC_2_N

L22

PA_CIO1_RX_P

J22

PA_CIO1_RX_N

N8

PA_LSTX/CIO_1_LSEO

J6

PA_LSRX/CIO_1_LSOE

A16

PA_DPSRC_1_P

B17

PA_DPSRC_1_N

A18

PA_DPSRC_3_P

B19

PA_DPSRC_3_N

L4

PA_AUX_P

L2

PA_AUX_N

M3

PA_DPSRC_HPD

R8

GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2

U2800

FALCON RIDGE

FCBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

PCIE GEN2

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

MISC

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

DPSRC_3_P
DPSRC_3_N

DPSRC_2_P
DPSRC_2_N

DPSRC_1_P
DPSRC_1_N

DPSRC_0_P
DPSRC_0_N

DISPLAY PORT

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_8/EN_CIO_PWR_N_OD

PB_CIO2_TX_P/DPSRC_0_P
PB_CIO2_TX_N/DPSRC_0_N

PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DPSRC_2_P
PB_CIO3_TX_N/DPSRC_2_N

PORTS

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P
PB_CIO2_RX_N

PB_CIO3_RX_P
PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE

PB_DPSRC_1_P
PB_DPSRC_1_N

PB_DPSRC_3_P
PB_DPSRC_3_N

PB_DPSRC_HPD

GPIO_1/PB_HV_EN/BYP0

PB_AUX_P
PB_AUX_N

PETP_0
PETN_0

PETP_1
PETN_1

PETP_2
PETN_2

PETP_3
PETN_3

RSENSE

RBIAS

GPIO_17
GPIO_18
GPIO_19

GPIO_14
GPIO_15

AD5

PCIE_TBT_D2R_C_P<0>

87 89

AD7

PCIE_TBT_D2R_C_N<0>

87 89

AD9

PCIE_TBT_D2R_C_P<1>

87 89
89

AD11

PCIE_TBT_D2R_C_N<1>

87

89

AD13

PCIE_TBT_D2R_C_P<2>

87
89

AD15

PCIE_TBT_D2R_C_N<2>

87

89

AD17

PCIE_TBT_D2R_C_P<3>

87
89

AD19

PCIE_TBT_D2R_C_N<3>

87

U20

TBT_RSENSE

W20

TBT_RBIAS

AD1
L8

Used for straps in host mode

W6

TP_TBT_PCIE_RESET0_L

AB3

TBT_DFT_STRAP_1

AD3

TBT_ROM_SECURITY_XOR

V1

TBT_DFT_STRAP_3

V3

TBT_CLKREQ_L

AB21

PCIE_CLK100M_TBT_P

AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

90

AB23

NC_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

A14

NC_DP_TBTSRC_ML_CP<3>

B15

NC_DP_TBTSRC_ML_CN<3>

A12

NC_DP_TBTSRC_ML_CP<2>

B13

NC_DP_TBTSRC_ML_CN<2>

A10

NC_DP_TBTSRC_ML_CP<1>

B11

NC_DP_TBTSRC_ML_CN<1>

A8

NC_DP_TBTSRC_ML_CP<0>

B9

NC_DP_TBTSRC_ML_CN<0>

J4

NC_DP_TBTSRC_AUXCH_CP

J2

NC_DP_TBTSRC_AUXCH_CN

AC2

DP_TBTSRC_HPD

U2

TBT_GPIO2

L6

TBT_PWR_EN

H5

SMC_PME_S4_DARK_L

Y7

TBT_CIO_PLUG_EVENT_L

Y1

HDMITBTMUX_SEL_TBT

T7

TBT_GPIO7

V7

TBT_EN_CIO_PWR_L

M7

TBT_BATLOW_L

T1

TBTDP_AUXIO_EN

T3

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

D3

TBT_B_CONFIG1_BUF

M1

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

M5

TBT_B_LSTX

P7

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

K3

DP_TBTPB_AUXCH_C_P

K1

DP_TBTPB_AUXCH_C_N

N6

DP_TBTPB_HPD

F1

TBT_B_HV_EN

R2N2

TBT_B_CIO_SEL

F3P3

TBT_B_DP_PWRDN

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

C2840
C2841

C2842
C2843

C2844
C2845

C2846
C2847

1

R2855

1K

1%
1/20W
MF
201

2

11

OUT

11 91

IN

11 91

IN

87

87

87

87

87

87

87

87

87

87

87

28

20

IN

20 40 41 42

OUT

14 20

OUT

28 85

IN

28 29

OUT

28 30

IN

28 31 32

OUT

28 82

OUT

32 93

OUT

32 93

OUT

32 93

IN

32 93

IN

32

IN

32 93

OUT

32 93

OUT

32 93

IN

32 93

IN

32

OUT

32

IN

32 93

OUT

32 93

OUT

32 93

OUT

32 93

OUT

BI
BI

32

IN

28 30 32

OUT

32

OUT

28 32

OUT

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

32 93

32 93

PCIE_TBT_R2D_C_P<0>

5

85 89

IN

PCIE_TBT_R2D_C_N<0>

5

85 89

IN

PCIE_TBT_R2D_C_P<1>

5

85 89

IN

PCIE_TBT_R2D_C_N<1>

5

85 89

IN

PCIE_TBT_R2D_C_P<2>

5

85 89

D

BYPASS=U2890::2mm

1

201

1

R2891

3.3K

5%

5%
1/20W

MF

MF
201

2

2

R2890

3.3K

1/20W

(TBT_SPI_MOSI)
(TBT_SPI_CLK)
(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

C2890

1UF

6.3V
CERM

10%

402

1

2

DI/IO0

6

CLK

1

CS*

3

WP*

7

HOLD*

CRITICAL

8

OMIT_TABLE

VCC

DO/IO1

U2890

4MBIT

W25X40CLXIG

USON

GND

THRM_PAD

4

9

IN

PCIE_TBT_R2D_C_N<2>

5

85 89

IN

PCIE_TBT_R2D_C_P<3>

5

85 89

IN

PCIE_TBT_R2D_C_N<3>

5

85 89

IN

25

(TBT_SPI_MISO)

R2892

3.3K

1/20W

201

19 20 28 29 84

1

5%
MF

2

C2800
C2801

C2802
C2803

C2804
C2805

C2806
C2807

PP3V3_TBTLC

1

R2893

3.3K

5%
1/20W
MF
201

2

R2829

10K

1/20W

201

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

76 89 97

IN

DP_TBTSNK0_ML_C_N<0>

76 89 97

IN

DP_TBTSNK0_ML_C_P<1>

76 89 97

IN

DP_TBTSNK0_ML_C_N<1>

76 89 97

IN

B

DP_TBTSNK0_ML_C_P<2>

76 89 97

IN

DP_TBTSNK0_ML_C_N<2>

76 89 97

IN

DP_TBTSNK0_ML_C_P<3>

76 89 97

IN

DP_TBTSNK0_ML_C_N<3>

76 89 97

IN

DP_TBTSNK0_AUXCH_C_P

83 89 97

BI

DP_TBTSNK0_AUXCH_C_N

83 89 97

BI

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

21

DP_TBTSNK0_ML_P<0>

0201

16V10%

X5R-CERM

21

DP_TBTSNK0_ML_N<0>

0201

16V10%

X5R-CERM

21

DP_TBTSNK0_ML_P<1>

0201

10% 16V
X5R-CERM

21

DP_TBTSNK0_ML_N<1>

0201

16V10%

X5R-CERM

21

DP_TBTSNK0_ML_P<2>

0201

10% 16V
X5R-CERM

21

DP_TBTSNK0_ML_N<2>

0201

16V10%

X5R-CERM

21

DP_TBTSNK0_ML_P<3>

0201

10% 16V
X5R-CERM

21

DP_TBTSNK0_ML_N<3>

0201

16V10%

X5R-CERM

21

DP_TBTSNK0_AUXCH_P

0201

10% 16V
X5R-CERM

21

DP_TBTSNK0_AUXCH_N

0201

16V10%

X5R-CERM

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

76 89 97

IN

DP_TBTSNK1_ML_C_N<0>

76 89 97

IN

DP_TBTSNK1_ML_C_P<1>

76 89 97

IN

DP_TBTSNK1_ML_C_N<1>

76 89 97

IN

DP_TBTSNK1_ML_C_P<2>

76 89 97

A

IN

DP_TBTSNK1_ML_C_N<2>

76 89 97

IN

DP_TBTSNK1_ML_C_P<3>

76 89 97

IN

DP_TBTSNK1_ML_C_N<3>

76 89 97

IN

DP_TBTSNK1_AUXCH_C_P

83 89 97

BI

DP_TBTSNK1_AUXCH_C_N

83 89 97

BI

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

21

DP_TBTSNK1_ML_P<0>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_N<0>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_P<1>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_N<1>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_P<2>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_N<2>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_P<3>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_ML_N<3>

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_AUXCH_P

0201

16V10%

X5R-CERM

21

DP_TBTSNK1_AUXCH_N

0201

16V10%

X5R-CERM

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

28 89 97

6 3

21

PCIE_TBT_D2R_P<0>

16V

X5R-CERM

10%

21

PCIE_TBT_D2R_N<0>

16V10%

X5R-CERM

21

PCIE_TBT_D2R_P<1>

16V10%

X5R-CERM

21

PCIE_TBT_D2R_N<1>

16V10%

X5R-CERM

21

PCIE_TBT_D2R_P<2>

16V10%

X5R-CERM

21

PCIE_TBT_D2R_N<2>

16V10%

X5R-CERM

21

PCIE_TBT_D2R_P<3>

10% 16V

X5R-CERM

21

PCIE_TBT_D2R_N<3>

10% 16V

X5R-CERM

Security strap setting is XORed with
bit in the flash, so the active-level
depends on the code in the flash.

0201

0201

0201

0201

0201

0201

0201

0201

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

If strap != bit then security is enabled?

Divides 3.3V to 1.8V

R2895

806

21

SYSCLK_CLK25M_TBT

1%

NO STUFF

R2899

10K

1/20W

R2878

100K

1/20W

1/20W

MF

201

1

1

R2896

1K

5%

5%

1/20W
MF

MF

201

201

2

2

PP3V3_TBTLC

1

1

R2879

100K

5%

5%
1/20W

MF

MF

201

201

2

2

NOTE: The following pins require testpoints:
0 - GPIO_13
1 - GPIO_1
2 - GPIO_2
3 - GPIO_3
4 - GPIO_5
5 - PCIE_RST_1_N
6 - PCIE_RST_2_N
7 - PCIE_RST_3_N

SYNC_MASTER=T29_RR

PAGE TITLE

19 20 28 29 84

28 29 30 45 84

TBT_EN_CIO_PWR_L

28 29

TBT_DDC_XBAR_EN_L

28 82

HDMITBTMUX_SEL_TBT

28 85

TBTDP_AUXIO_EN

28 31 32

DP_TBTSRC_HPD

28

19 20 28 29 84

28 29 30 45 84

28 30

28 31

28 32

28 30 31

28 30 32

Thunderbolt Host (1 of 2)

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP3V3_TBTLC

19 20 28 29 84

1

R2861

10K

5%
1/20W
MF
201

2

PP3V3_TBTLC
PP3V3_S4_TBT

R2881

PP3V3_S4_TBT

R2884

TBT_BATLOW_L
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN

8 - GPIO_15
9 - GPIO_11
10 - GPIO_14
11 - GPIO_0
12 - GPIO_12
13 - GPIO_10
14 - PB_LSTX
15 - PB_LSRX

Apple Inc.

IN

100K

1/20W

100K

1/20W

201

201

NO STUFF

1

R2867

10K

5%
1/20W
MF
201

2

1

R2862

10K

5%
1/20W
MF
201

2

19 90

1

R2880

5%
MF

2

R2832

NO STUFF

1

R2885

5%
MF

2

R2888

SYNC_DATE=01/14/2013

1

100K

5%

1/20W

MF

201

2

1

100K

5%

1/20W

MF

201

2

1

10K

5%

1/20W

MF

201

2

1

10K

5%

1/20W

MF

201

2

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

28 OF 119

SHEET

28 OF 97

124578

1

R2863

10K

5%
1/20W
MF
201

2

1

R2882

100K

5%
1/20W
MF
201

2

1

R2883

100K

5%
1/20W
MF
201

2

NO STUFF

1

R2886

10K

5%
1/20W
MF
201

2

1

R2887

10K

5%
1/20W
MF
201

2

SIZE

D

C

B

A

D

D

Vinafix.com

C

B

A

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

8 7 6 5 4 3

U2950

1

C2900

1.0UF

0201-1

29

C2901

20%

6.3V
2

X5R

PP1V05_TBT

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V

1.0UF

20%

6.3V
X5R

0201-1

NOSTUFF

C2923

X5R-CERM

1

2

C2902

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2903

1.0UF

6.3V

0201-1

1900 mA EDP

C2922

20UF

20%

X5R-CERM

0402-2

1

C2921

4V

2

X5R-CERM

1

20UF

20%

4V

2

0402-2

J45 Implementation: 4 X 10uF
X425 Implementation: 3 X 20uF

20%
X5R

0402-2

1

2

20UF

20%

C2904

1

4V

2

1.0UF

6.3V

0201-1

C2920

X5R-CERM

CRITICAL

1

C2907

12PF

5%
NP0-C0G

2

0201
25V

1

C2905

1.0UF

20%
X5R

CRITICAL

1

C2912

12PF

5%
NP0-C0G

2

0201
25V

20%

6.3V

2

X5R

0201-1

680NH-30%-3.6A-35MOHM

1

20UF

20%

4V

2

0402-2

NSR1020MW2T1G

CRITICAL

1

C2908

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C2906

2

CRITICAL

1

C2913

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

L2920

SM

CRITICAL

D2920

1.0UF

6.3V

0201-1

SOD-323

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V

1

700 mA EDP

20%

2

X5R

C2910

1.0UF

20%

6.3V
X5R

0201-1

21

P1V05TBT_SW

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
DIDT=TRUE
SWITCH_NODE=TRUE

K

A

1

2

C2911

1.0UF

6.3V

0201-1

20%
X5R

CRITICAL

1

C2933

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C2934

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

OMIT_TABLE

G10
G12
G14
G16
G18
H19

H9
J18
K15
K17
K19

K7

VCC1P0_RDV_DECAP

L16
M19
P19
T19
U18
V15
V17
W12
W14

J8

1

2

K9
L14
M15

SVR_VCC1P0

M17
P17
V19

A4

A6

SVR_IND

B3

B5

AA14
AA20
AA22

AB11
AB17
AC10
AC12
AC14
AC16
AC18
AC20
AC22

A24

AC4
AC6
AC8

C10
C12
C14
C16
C18

C20
C22
C24

D21
D23

F11
F13
F15
F17
F19
F21
F23

A2

B1

B7

C2

C4

C6

C8

E4

F5

F7

F9

SVR_AMON

VSS

NC

U2800

FALCON RIDGE

FCBGA

SYM 2 OF 2

CRITICAL

VCC

VCC3P3_RDV_DECAP

GND

VCC1P0_CIO

VCC3P3_LC

VCC3P3

VSS

J10
J12
K11
L10
M11
N10
N14
P11
P15
R10
R14
T11
T15
U10
U14
V11

D1
E2
H11
N4
V5
W4

Y5

H13
H15
H17
H7
L18
N18
R18
W10

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

G20
G6
G8
H21
H23
J14AA8
J16
J20
K13
K21
K23
L12
L20
M13
M21
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9

1

6.3V

20%
X5R

2

C2931

1.0UF

20%

6.3V
X5R

0201-1

C2930

1.0UF

0201-1

SVR input to FR - 1100 mA EDP

POC input to FR - 150 mA EDP
Isolated to reduce noise from SVR

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=3.3V

100 mA EDP

1

C2970

1.0UF

20%

6.3V

2

X5R

0201-1

PP3V3_TBTRDV

25 mA EDP

19 30 40 41

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

14

1

2

IN

PP3V3_S0

IN

Part
Type
R(on)

@ 1.05V

Max Current = 4A (85C)

1.0UF

6.3V

0201-1

20%
X5R

1

2

19 20 28 29 84

C2932

1

C2980

1.0UF

20%

6.3V

2

X5R
0201-1

SMC_DELAYED_PWRGD

TBT_POC_RESET_L

TPS22920
Load Switch
8 mOhm Typ

11.5 mOhm Max

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

1200 mA EDP

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

28 29 30 45 84

1

R2995

100K

5%

1/20W

MF

201

2

C2950

10UF

CERM-X5R

0402-1

C2960

1.0UF

0201-1

PP3V3_S4_TBT

Q2995

DMN32D2LFB4

DFN1006H4-3

1

S G

2

6 3

1.05V TBT "CIO" Switch

Internal switch not functional on FR.

PP1V05_TBT

U2940

TPS22920

CSP

A1
B1
C1

VOUT

CRITICAL

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

VIN

ON

GND

D1

PP3V3_S0

12

OUT

A2
B2
C2

D2

TBT_EN_CIO_PWR

1

C2940

1.0UF

20%

6.3V

2

X5R
0201-1

TBT_PWR_REQ_L

Pull-up (S0) on PCH page

20%

6.3V

20%

6.3V
X5R

1

2

1

2

C2951

10UF

6.3V

CERM-X5R

0402-1

C2961

1.0UF

6.3V

0201-1

20%

20%
X5R

1

2

1

2

C2952

10UF

6.3V

CERM-X5R

0402-1

20%

1

2

C2953

10UF

CERM-X5R

0402-1

TBT "POC" Power-up Reset

SYM_VER_3

C2995

330PF

0201

1

R2990

100K

5%
1/20W
MF
201

2

D

3

10%
16V
X7R

TBTPOCRST_MR_L
TBTPOCRST_SENSE

1

R2991

1

24.9K

1%
1/20W

2

MF
201

2

Vth = 2.508V nominal

R2992

100K

1/20W

1

5%
MF

201

2

29

6

1

5

SOT563

G

VER 5

S D

4

1

1

20%

6.3V

2

2

PP3V3_S4_TBT_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

CRITICAL

U2990

TPS3895ADRY

1

3

USON

ENABLE SENSE_OUT

SENSE

GND

PP3V3_TBTLC

1

R2945

100K

5%
1/20W
MF
201

2

Q2945

DMN5L06VK-7

D

SOT563

VER 3

2

S G

3

Q2945

DMN5L06VK-7

CRITICAL

C2954

12PF

5%
NP0-C0G
0201
25V

6

VCC

2

19 20 28 29 84

TBT_EN_CIO_PWR_L

PP3V3_S4_TBT

CRITICAL

1

C2955

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C2990

0.1UF

10%
25V

2

X5R
402

Push-pull output

4

TBT_PWR_ON_POC_RST_L

5

TBTPOCRST_CT

CT

3.1 W (Dual-Port)

2.4 W (Single-Port)
EDP: 1.25 A

PLACE_NEAR=C2953.1:1mm

2

XW2960

SM

1

Delay = 4.04ms nominal

SYNC_MASTER=CLEAN_X425

PAGE TITLE

Thunderbolt Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

28

IN

28 29 30 45 84

OUT

1

C2991

0.001UF

10%
50V

2

X7R-CERM

0402

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

29 OF 119

SHEET

29 OF 97

124578

D

C

B

28

A

SIZE

D

8 7 6 5 4 3

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)
Signal aliases required by this page:

(NONE)
BOM options provided by this page:

(NONE)

12

D

SI8409DB:

C3080 USING 0603 PAKAGE IS FOR DFM TO PROTECT Q3080 (CSP)

PPBUS_G3H

44 47 56 57 63 65 84 86

8-13V Input
Changes required
for 2S.

C

Q3005

DMN5L06VK-7

SOT563

VER 3

28 31

IN

6

D

2

SG

1

R3080

470K

1/16W
MF-LF

R3081

330K

1/16W
MF-LF

28 32

IN

1

5%

402

2

1

5%

402

2

TBTBST_PWREN_L

DMN5L06VK-7

TBT_B_HV_ENTBT_A_HV_EN

1

C3080

0.1UF

10%
50V

2

X7R
603-1

TBTBST_PWREN_DIV_L

Q3005

SOT563

VER 3

5

D

SG

Q3080

SI8409DB

SGD

4

1

3

C3085

2.2UF

CER-X6S

4

1

R3092

73.2K

1%
1/16W
MF-LF
402

2

<R2>

UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)

CRITICAL

Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 46mOhm @ 4.5V Vgs
Id(max): 3.7A @ 70C

BGA

32

PPVIN_SW_TBTBST

84

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

Voltage not specified here,
add property on another page.

1

1

C3086

2.2UF

20%
10V

2

2

CER-X6S
0402

C3092

2.2UF

20%
10V

CER-X6S

0402

0402

20%
10V

1

C3087

68PF

5%
50V

2

CERM
0402

R3093

49.9K

TBTBST_VC_RC

1

1

2

C3093

0.0033UF

10%
50V

2

X7R-CERM
0402

B

Thunderbolt 15V Boost Regulator

CRITICAL

L3095

R3091

200K

1/16W
MF-LF

<R1>

1%
1/16W
MF-LF

402

R3094

26.7K

1/16W
MF-LF

3.3UH-6.5A

1

C3090

10UF

20%
25V

2

X5R-CERM

1

1%

402

2

0603

TBTBST_EN_UVLO

TBTBST_INTVCC

TBTBST_VC

1

2

1

1%

402

2

TBTBST_RT

TBTBST_SS

1

C3094

0.33UF

10%

6.3V

2

X6S-CERM
0402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

Q3088

DMN5L06VK-7

6

D

SOT563

VER 3

Max Vgs: 10V

2

S G

1

TBTBST_SHDN_DIV

1

R3087

330K

5%
1/16W
MF-LF
402

2

C3091

10UF

X5R-CERM

0603

1

20%
25V

2

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

1

R3088

330K

5%
1/16W
MF-LF
402

2

Q3088

DMN5L06VK-7

3

D

SOT563

VER 3

S G

4

PIMB063T-SM

27

VIN

CRITICAL

U3090

LT3957

SGND

37

24234

SGND shorted to
GND inside package,
no XW necessary.

5

SMC_DELAYED_PWRGD

QFN

21

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE

9

8

382120

SW

6

SNS1

3

SNS2

1
2
10

NC

35
36

31

FBX

GND

12

1716151413

NC

TBTBST_SNS1

TBTBST_SNS2

NO STUFF

1

C3089

100PF

5%
50V

2

CERM
402

Vout = 1.6V * (1 + Ra / Rb)

19 29 40 41

IN

R3089

1/20W

TBTBST_VSNS

1

C3088

10PF

5%
50V

2

CERM
0402

TBTBST_FBX

0201

1

0

5%
MF

2

R3097

10

5%
1/16W
MF-LF

402

R3095

137K

1/16W
MF-LF

<Ra>

R3096

15.8K

1/16W
MF-LF

<Rb>

402

402

2

1

CRITICAL

D3095

PDS540XF

3

PWRDI5

21

NOTE: Change R3097 to XW3095 at PVT

1

1%

2

1

1%

2

1

C3095

33UF-0.06OHM

20%
25V

2

POLY-TANT
CASE-D3L

C3096

X5R-CERM

10UF

PP15V_TBT

Vout = 15.47V
Max Current = 2A?
Freq = 480KHz

NO STUFF

1

1

C3097

10UF

10%
25V

2

2

X7R-CERM
1206

0603

20%
25V

1

2

PLACE_SIDE=BOTTOM

NOTE: MIRROR C3096 and C3098

31 32 84

C3099

0.001UF

10%
50V
X7R-CERM
0402

10UF

X5R-CERM

0603

1

20%
25V

2

C3098

PLACE_SIDE=TOP

D

C

B

BATLOW# Isolation

Q3000

A

12 40 42

IN

DMN32D2LFB4

PM_BATLOW_L

DFN1006H4-3

SYM_VER_3

D

3

PP3V3_S4_TBT

1

S G

2

Pull-up on RR page
TBT_BATLOW_L

TBT_BATLOW_L

MAKE_BASE=TRUE

6 3

28 29 45 84

28 30

SIZE

A

D

SYNC_MASTER=CLEAN_X305

PAGE TITLE

28 30

OUT

Thunderbolt Mobile Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/24/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

30 OF 119

SHEET

30 OF 97

124578

8 7 6 5 4 3

V3P3 must be S4 to support
wake from Thunderbolt devices.

67 82 84 85 86 96

PP3V3_S5

12 14 15 17 18 19
21 32 33 61 64 66

CRITICAL

POLY-TANT

D

C

CASE-B2-SM

For 12V systems:

PART NUMBER

Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

B

C3287

100UF

20%

6.3V

PP15V_TBT

30 32 84

15.75V Max

118S0145
118S0145

1

C3280

22UF

20%

6.3V

2

X5R-CERM-1

603

4.7UF

X5R-CERM

0603

32 66 67

28 30

32 44 67

10%
25V

1

2

IN

IN

IN

C3215

QTY

2
2

TBT_A_D2R_P<0>

28 93

OUT

TBT_A_D2R_N<0>

28 93

OUT

DP_TBTPA_ML_C_P<3>

28 93

IN

DP_TBTPA_ML_C_N<3>

28 93

IN

1

1

2

2

1

C3210

0.1UF

10%
25V

2

X5R
402

S4_PWR_EN
TBT_A_HV_EN
PM_SLP_S3_R_L

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

A

3.3V/HV Power MUX

Nominal Min Max
IV3P3 1100mA 1030mA 1200mA

C3281

0.1UF

10%
16V
X5R-CERM
0201

DESCRIPTION

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

CD3211A1RGP

ENHVU

5

EN

HV_EN

17

S0

TBTHV:P15V

R3213

U3210

QFN

ISET_V3P3

GND

321

13

22.6K

1/20W

V3P3OUT

FAULTZ

ISET_S0

ISET_S3

15

1%
MF

201

18

12

OUT

14

C3285

0.1UF

X5R-CERM

416

8

1011

9

THRM

PAD

21

TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R

TBTHV:P15V

1

1

R3214

22.6K

1%
1/20W
MF
201

2

2

<RHVS0><RHVS3>

REFERENCE DES

R3210,R3213
R3211,R3214

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3274

0.47UF

C3275

0.47UF

C3278

0.22UF

C3279

0.22UF

28

OUT

21

4V

20%
CERM-X5R-1

21
20%

CERM-X5R-1

21

6.3V

20%

0201

X5R
21

6.3V

20%

0201

X5R

TBT_A_HPD

31

TBT_A_CONFIG1_RC

31

TBT_A_CONFIG2_RC

201

2014V

R3252

1

1

C3286

10UF

20%

6.3V

2

2

CERM-X5R
0402

0201

10%
16V

TBTAPWRSW_ISET_V3P3
TBTAPWRSW_ISET_S0
TBTAPWRSW_ISET_S3

TBTHV:P15V

12V: See
below

R3210

22.6K

1/20W

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

TBT_A_D2R_C_P<0>

93

TBT_A_D2R_C_N<0>

93

NO_XNET_CONNECTION=TRUE

DP_TBTPA_ML_P<3>

93

DP_TBTPA_ML_N<3>

93

1

1M

5%

1/20W

MF

201

2

1

R3251

1M

5%
1/20W
MF
201

2

GND_VOID=TRUE

PP3V3_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PP3V3RHV_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

1

C3211

0.1UF

10%
25V

2

X5R
402

TBTHV:P15V

1

1

R3211

22.6K

1%

1%

1/20W
MF

MF

201

201

2

2

BOM OPTION

TBTHV:P12V
TBTHV:P12V

1

201

1

1K

5%
MF

2

2

R3294

1/20W

31

1

R3212

36.5K

1%
1/20W
MF
201

2

<RV3P3>

C3200

0.01UF

10%
50V

X7R-CERM

0402

GND_VOID=TRUE

R3295

1K

5%
1/20W
MF
201

NO_XNET_CONNECTION=TRUE

1

R3279

470K

1/20W

1

R3278

470K

5%

5%
1/20W

MF

201

MF
201

2

2

TBT_A_D2R1_AUXDDC_P

31 93

TBT_A_D2R1_AUXDDC_N

31 93

CRITICAL

L3200

FERR-120-OHM-3A

1

C3201

0.01UF

10%
50V

2

X7R-CERM
0402

0603

1

2

TBT_A_D2R_N<1>

28 87 93

OUT

TBT_A_D2R_P<1>

28 87 93

OUT

DP_TBTPA_AUXCH_C_N

28 93

BI

DP_TBTPA_AUXCH_C_P

28 93

BI

DP_TBTPA_ML_C_P<1>

28 93

IN

DP_TBTPA_ML_C_N<1>

28 93

IN

21

PP3V3RHV_S4_TBTAPWR_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT: RX_0

TBT: Unused

Thunderbolt Connector A

R3201

12

21

5%

1/20W

MF

201

B2
B4
B6

B8 B7
B10
B12
B14 B13
B16
B18
B20

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3277

0.47UF

C3276

0.47UF

C3230

0.1UF

C3231

0.1UF

C3232

0.22UF

C3233

0.22UF

CRITICAL

1

C3203

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

S16

SHIELD PINS

J3200

MDP-J44

F-RT-TH

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

PORT B

SHIELD PINS

S24

S22

S21

514-0876

S20

S15

S14

S19

21
20%

CERM-X5R-1
21
20%

CERM-X5R-1
21
10% 16V

X5R-CERM

0201

21
10% 16V

X5R-CERM

0201

21

6.3V

20%

0201

X5R
21

6.3V

20%

0201

X5R

CRITICAL

1

C3204

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

S13

S12

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S18

S17

2014V

2014V

B1
B3
B5

B9
B11

B15
B17
B19

TBT: RX_1

DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V

C3294

330PF

0201

10%
16V
X7R

1

C3202

0.01UF

10%
16V

2

X5R-CERM

1

1

1

C3295

330PF

10%
16V

2

2

X7R
0201

R3241

100K

5%
1/20W
MF
201

2

0201

6 3

31

TBT_A_D2R_C_N<1>

93

TBT_A_D2R_C_P<1>

93

DP_TBTPA_AUXCH_N

93

DP_TBTPA_AUXCH_P

93

DP_TBTPA_DDC_DATA

83

BI

DP_TBTPA_DDC_CLK

83

IN

TBT_A_CONFIG1_BUF

28 82

OUT

DP_TBTPA_ML_P<1>

93

DP_TBTPA_ML_N<1>

93

TBT_A_LSTX

28

IN

TBT_A_LSRX

28

OUT

DP_TBTPA_HPD

28

OUT

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

DP Dir

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

PP3V3_S4_TBTAPWR

C3220

0.1UF

X5R-CERM

(0-18.9V)

TBT Dir

TBT: TX_0

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

10%
16V

2

0201

7 15

TB-

8

TB+

1

AUX-

2

AUX+

4

DDC_DAT

5

DDC_CLK

16 18

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

12 17

HPDOUT

GND_VOID=TRUE

C3205

0.01UF

10%
25V

X5R-CERM

0201

TBT_A_R2D_P<0>

93

TBT_A_R2D_N<0>

93

GND_VOID=TRUE

C3206

0.01UF

10%
25V

X5R-CERM

0201

TBT_A_R2D_P<1>

93

TBT_A_R2D_N<1>

93

3

SIGNAL_MODEL=TBT_MUX

VDD

CRITICAL

U3220

CBTL05024

HVQFN24-COMBO

AUXIO_EN

(IPU)
(IPD)

(IPU)
(IPD)

THMPAD

GND
9

21

1

2

1

2

TB_ENA

DP_PD

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

25

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1

2

470k R’s for ESD protection
on AC-coupled signals.

SYNC_MASTER=CLEAN_X425

PAGE TITLE

TBT_A_CIO_SEL

24

TBTDP_AUXIO_EN

6

TBT_A_DP_PWRDN

23

TBT_A_D2R1_AUXDDC_N

22

TBT_A_D2R1_AUXDDC_P

TBT: RX_1

TBT_A_CONFIG1_RC

19

DP_A_LSX_ML_P<1>

20

DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

HPD

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3270

0.22UF

C3271

0.22UF

R3270

470K

5%
1/20W
MF
201

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3272

0.22UF

C3273

0.22UF

R3272

470K

5%
1/20W
MF
201

21
20%

6.3V

X5R

0201
21
20%

6.3V

X5R

0201

GND_VOID=TRUE

1

R3271

470K

5%
1/20W
MF
201

2

21
20%

6.3V

X5R

0201
21
20%

6.3V

X5R

0201

GND_VOID=TRUE

1

R3273

470K

5%
1/20W
MF
201

2

28

IN

28 32

IN

28

IN

31 93

31 93

31

31 93

31 93

31

TBT_A_R2D_C_P<0>
TBT_A_R2D_C_N<0>

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>

SYNC_DATE=10/30/2014

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

IN
IN

31 93

31 93

IN
IN

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

32 OF 119

SHEET

31 OF 97

124578

28 93

28 93

28 93

28 93

SIZE

D

C

B

A

D

8 7 6 5 4 3

V3P3 must be S4 to support
wake from Thunderbolt devices.

67 82 84 85 86 96

PP3V3_S5

12 14 15 17 18 19
21 31 33 61 64 66

CRITICAL

POLY-TANT

D

C

CASE-B2-SM

For 12V systems:

PART NUMBER

Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

B

C3387

100UF

20%

6.3V

PP15V_TBT

30 31 84

15.75V Max

118S0145
118S0145

1

C3380

22UF

20%

6.3V

2

X5R-CERM-1

603

4.7UF

X5R-CERM

0603

31 66 67

28 30

31 44 67

10%
25V

1

2

IN

IN

IN

C3315

QTY

2
2

TBT_B_D2R_P<0>

28 93

OUT

TBT_B_D2R_N<0>

28 93

OUT

DP_TBTPB_ML_C_P<3>

28 93

IN

DP_TBTPB_ML_C_N<3>

28 93

IN

1

1

2

2

1

C3310

0.1UF

10%
25V

2

X5R
402

S4_PWR_EN
TBT_B_HV_EN
PM_SLP_S3_R_L

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

A

3.3V/HV Power MUX

Nominal Min Max
IV3P3 1100mA 1030mA 1200mA

C3381

0.1UF

10%
16V
X5R-CERM
0201

DESCRIPTION

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

CD3211A1RGP

ENHVU

5

EN

HV_EN

17

S0

TBTHV:P15V

R3313

<RHVS3>

U3310

QFN

ISET_V3P3

GND

321

13

22.6K

1/20W

V3P3OUT

FAULTZ

ISET_S0

ISET_S3

15

1%
MF

201

18

12

OUT

14

C3385

0.1UF

X5R-CERM

416

8

1011

9

THRM

PAD

21

TBTBPWRSW_ISET_S3_R
TBTBPWRSW_ISET_S0_R

TBTHV:P15V

1

1

R3314

22.6K

1%
1/20W
MF
201

2

2

<RHVS0>

REFERENCE DES

R3310,R3313
R3311,R3314

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3374

0.47UF

C3375

0.47UF

C3378

0.22UF

C3379

0.22UF

28

OUT

21
20%

4V

CERM-X5R-1
21
20%

4V 201

CERM-X5R-1

21
20%

6.3V

X5R

0201
21
20%

6.3V

X5R

0201

TBT_B_HPD

32

TBT_B_CONFIG1_RC

32

TBT_B_CONFIG2_RC

201

R3352

1

1

C3386

10UF

20%

6.3V

2

2

CERM-X5R
0402

0201

10%
16V

TBTBPWRSW_ISET_V3P3
TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3

TBTHV:P15V

12V: See
below

R3310

22.6K

1/20W

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

TBT_B_D2R_C_P<0>

93

TBT_B_D2R_C_N<0>

93

NO_XNET_CONNECTION=TRUE

DP_TBTPB_ML_P<3>

93

DP_TBTPB_ML_N<3>

93

1

1M

5%

1/20W

MF

201

2

1

R3351

1M

5%
1/20W
MF
201

2

GND_VOID=TRUE

PP3V3_S4_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PP3V3RHV_S4_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

1

C3311

0.1UF

10%
25V

2

X5R
402

TBTHV:P15V

1

1

R3311

22.6K

1%

1%

1/20W
MF

MF

201

201

2

2

BOM OPTION

32

1

R3312

36.5K

1%
1/20W
MF
201

2

<RV3P3>

TBT_B_D2R_N<1>

28 93

OUT

TBT_B_D2R_P<1>

28 93

OUT

DP_TBTPB_AUXCH_C_N

28 93

BI

DP_TBTPB_AUXCH_C_P

28 93

BI

DP_TBTPB_ML_C_P<1>

28 93

IN

DP_TBTPB_ML_C_N<1>

28 93

IN

Thunderbolt Connector B

(Both C’s)

C3377

0.47UF

C3376

0.47UF

C3330

0.1UF

C3331

0.1UF

C3332

0.22UF

C3333

0.22UF

GND_VOID=TRUE

GND_VOID=TRUE

21
20%

CERM-X5R-1
21
20%

CERM-X5R-1
21
10% 16V

X5R-CERM
21
10% 16V

X5R-CERM

21
20%

X5R
21
20%

X5R

4V 201

4V 201

0201

0201

6.3V
0201

6.3V
0201

TBTHV:P12V
TBTHV:P12V

R3394

1K

5%

1/20W

MF

201

GND_VOID=TRUE

1

1

R3395

1K

5%
1/20W
MF
201

2

2

NO_XNET_CONNECTION=TRUE

R3379

470K

1/20W

C3300

0.01UF

10%
50V

X7R-CERM

0402

1

1

R3378

470K

5%

5%
1/20W

MF

201

MF
201

2

2

TBT_B_D2R1_AUXDDC_P

32 93

TBT_B_D2R1_AUXDDC_N

32 93

CRITICAL

L3300

FERR-120-OHM-3A

1

C3301

0.01UF

10%
50V

2

X7R-CERM
0402

0603

1

2

21

PP3V3RHV_S4_TBTBPWR_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT: RX_0

TBT: Unused

R3301

12

5%

1/20W

MF

201

CRITICAL

1

C3303

12PF

5%
NP0-C0G

2

0201

21

25V

CRITICAL

S5S4S3

SHIELD PINS

J3200

A2
A4
A6

A8 A7
A10
A12
A14 A13
A16
A18
A20

MDP-J44

F-RT-TH

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

PORT A

SHIELD PINS

S23S2S11

S10

S9S8S7

514-0876

CRITICAL

1

C3304

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

S1

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S6

A1
A3
A5

A9
A11

A15
A17
A19

TBT: RX_1

DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V

C3394

330PF

0201

10%
16V
X7R

1

C3302

0.01UF

10%
16V

2

X5R-CERM

1

1

1

C3395

330PF

10%
16V

2

2

X7R
0201

R3341

100K

5%
1/20W
MF
201

2

0201

6 3

32

TBT_B_D2R_C_N<1>

93

TBT_B_D2R_C_P<1>

93

DP_TBTPB_AUXCH_N

93

DP_TBTPB_AUXCH_P

93

DP_TBTPB_DDC_DATA

83

BI

DP_TBTPB_DDC_CLK

83

IN

TBT_B_CONFIG1_BUF

28 82

OUT

DP_TBTPB_ML_P<1>

93

DP_TBTPB_ML_N<1>

93

TBT_B_LSTX

28

IN

TBT_B_LSRX

28

OUT

DP_TBTPB_HPD

28

OUT

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

DP Dir

TBTBCONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

PP3V3_S4_TBTBPWR

C3320

0.1UF

X5R-CERM

(0-18.9V)

TBT Dir

TBT: TX_0

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

10%
16V

2

0201

7 15

TB-

8

TB+

1

AUX-

2

AUX+

4

DDC_DAT

5

DDC_CLK

16 18

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

12 17

HPDOUT

GND_VOID=TRUE

C3305

0.01UF

10%
25V

X5R-CERM

0201

TBT_B_R2D_P<0>

93

TBT_B_R2D_N<0>

93

GND_VOID=TRUE

C3306

0.01UF

10%
25V

X5R-CERM

0201

TBT_B_R2D_P<1>

93

TBT_B_R2D_N<1>

93

3

SIGNAL_MODEL=TBT_MUX

VDD

CRITICAL

U3320

CBTL05024

HVQFN24-COMBO

AUXIO_EN

(IPU)
(IPD)

(IPU)
(IPD)

THMPAD

GND
9

21

1

2

1

2

TB_ENA

DP_PD

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

25

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1

2

470k R’s for ESD protection
on AC-coupled signals.

SYNC_MASTER=CLEAN_X425

PAGE TITLE

TBT_B_CIO_SEL

24

TBTDP_AUXIO_EN

6

TBT_B_DP_PWRDN

23

TBT_B_D2R1_AUXDDC_N

22

TBT_B_D2R1_AUXDDC_P

TBT: RX_1

TBT_B_CONFIG1_RC

19

DP_B_LSX_ML_P<1>

20

DP_B_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_B_HPD

HPD

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3370

0.22UF

C3371

0.22UF

R3370

470K

5%
1/20W
MF
201

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3372

0.22UF

C3373

0.22UF

R3372

470K

5%
1/20W
MF
201

21

6.3V

20%

0201

X5R
21

6.3V

20%

0201

X5R

GND_VOID=TRUE

1

R3371

470K

5%
1/20W
MF
201

2

21

6.3V

20%

0201

X5R
21

6.3V

20%

0201

X5R

GND_VOID=TRUE

1

R3373

470K

5%
1/20W
MF
201

2

28

IN

28 31

IN

28

IN

32 93

32 93

32

32 93

32 93

32

TBT_B_R2D_C_P<0>
TBT_B_R2D_C_N<0>

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_R2D_C_P<1>
TBT_B_R2D_C_N<1>

SYNC_DATE=10/30/2014

Thunderbolt Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

IN
IN

32 93

32 93

IN
IN

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

33 OF 119

SHEET

32 OF 97

124578

28 93

28 93

28 93

28 93

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

CRITICAL

1

C3524

12PF

5%
NP0-C0G

2

0201
25V

D

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

CRITICAL

J3501

SSD-X29-D1

F-RT-SM

C

19

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15
16
17
18

20

21

516S1016

B

A

CRITICAL

1

C3525

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

WIFI_EVENT_L

PP3V3_S3RS4_BT_F

86

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

40 41 86

IN

CRITICAL

1

C3533

12PF

5%
NP0-C0G

2

0201
25V

PCIE_WAKE_L

CRITICAL

1

C3534

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

PCIE_AP_R2D_P

86 91

NOSTUFF

1

C3570

12PF

5%
25V

2

NP0-C0G
0201

PCIE_AP_R2D_N

86 91

NOSTUFF

1

C3572

12PF

5%
25V

2

NP0-C0G
0201

1

C3574

12PF

5%

NOSTUFF

25V

2

NP0-C0G
0201

1

C3576

12PF

5%
25V

2

NP0-C0G
0201

PCIE_CLK100M_AP_CONN_N

86 91

PCIE_CLK100M_AP_CONN_P

86 91

12 35 86 91

OUT

L3505

1

C3532

0.01UF

10%
16V

2

X7R-CERM
0402

2 1

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=J3501.18:2.54MM

6 3

NOSTUFF

PLACE_NEAR=J3501.7:2.54MM

CRITICAL

90-OHM-0.1A-0.7-2GHZ

1

PP3V3_S4

NOSTUFF

1

C3571

2

L3501

TAM0605

SYM_VER-1

0.1UF

10%
16V
X5R-CERM
0201

NOSTUFF

1

C3573

0.1UF

10%
16V

2

X5R-CERM
0201

PCIE_AP_D2R_P

NOSTUFF

1

C3575

0.1UF

10%
16V

2

X5R-CERM
0201

PCIE_AP_D2R_N

NOSTUFF

1

C3577

0.1UF

10%
16V

2

X5R-CERM
0201

4

PCIE_CLK100M_AP_N

32

PCIE_CLK100M_AP_P

USB_BT_CONN_N

86 90

USB_BT_CONN_P

86 90

20 33 38 41 42 45 46 65 66 67
81 84 85 86

C3531

21

0.1UF

10%

16V

PLACE_NEAR=J3501.5:2.54MM

C3530

PLACE_NEAR=J3501.4:2.54MM

OUT

OUT

0402

13 20 91

21

16V10%

13 20 91

X7R-CERM

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

0.1UF

X7R-CERM0402

AIRPORT

BLUETOOTH

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

PM_SLP_S4_L

12 21 37 40 67 81 86

IN

SIGNAL_MODEL=MOJO_MUX_USBONLY

AP_RESET_CONN_L

86

AP_CLKREQ_Q_L

86

IN

11 91

IN

11 91

IN

1
2

10

VCC

Y+
Y-

U3510

PI3USB102EZLE

TQFN

CRITICAL

SEL OE*

GND

13 91

13 91

IN

9

M+
M-

D+
D-

3

NO_XNET_CONNECTION=TRUE

1

C3510

0.1UF

10%

6.3V

2

CERM-X5R
0201

5

NC

4

7
6

8

USB_BT_WAKEN

USB_BT_P
USB_BT_N

SEL OUTPUT

L USB_BT_WAKE
H USB_BT

NOTE: Stuff non-zero value for R3557 to see which end is driving low

1A PEAK

PP3V3_WLAN

41 86

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PLACE_NEAR=J3501.1:2.54MM

3.3V TI WLAN Switch

Part
Type
R(on)

@ 2.5V

TPS22924C
Load Switch

18.5 mOhm Typ

25.8 mOhm Max

CURRENT SENSE

33 46

OUT

PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

Max Current = 2A (85C)

3.3V SIL WLAN Switch

Part
Type
R(on)

@ 2.5V

WLAN_SW:SIL

Q3510

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

13 90

BI

13 90

BI

C3555

4700PF

1

SLG5AP1443V
Load Switch
17 mOhm Typ

19 mOhm Max

PM_WLAN_CAP

1

10%
10V

2

X7R
201

SMC_PME_S4_WAKE_L

3

D

G S

2

1

R3512

15K

1%
1/20W
MF
201

2

33 40 67

1

R3553

100K

1%
1/16W
MF-LF
402

2

PM_WLAN_EN

OUT

Supervisor & CLKREQ # Isolation

L3504

FERR-120-OHM-3A

1

C3522

0.1uF

20%
10V

2

CERM

402

WLAN_SW:TI

U3550

TPS22924

A1

VOUTONVIN

B1

CRITICAL

WLAN_SW:SIL

U3551

SLG5AP1443V

CAP

CRITICAL

38 40 42 86

Delay = 130 ms +/- 20%

PP3V3_WLAN_F

1

R3554

232K

1%
1/16W
MF-LF
402

2

P3V3WLAN_VMON

1

R3555

100K

1%
1/16W
MF-LF
402

2

155S0367

0603

C3521

0.1uF

20%
10V

CERM

402

PLACE_NEAR=J3501.1:2.54MM

CSP

GND

C1

1

VDD

TDFN

GND

8

33 46

SLG4AP041V

2

SENSE
VREF

4

RESET*

7

IN

21

PP3V3_WLAN_F

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

2

A2
B2

C2

PP3V3_S5

CRITICAL

1

C3523

12PF

5%
NP0-C0G

2

0201
25V

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

PM_WLAN_EN

PP3V3_S5

CRITICAL

1

C3550

12PF

5%
NP0-C0G

2

0201
25V

FOR DESENSE IMPROVEMENT

37

D

52

SON

LOCATION DEPENDS ON DESENSE TEAM

PP3V3_WLAN_R

CRITICAL

1

C3551

12PF

5%
NP0-C0G

2

0201
25V

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

PP3V3_S5

1

CRITICAL

VDD

U3540

TDFN
+

-

DLY

MR*

EN

OUT

THRM

PAD

(OD)

GND

9

5

APCLKRQ:BIDIR

SYNC_MASTER=CLEAN_X425

PAGE TITLE

3

6
8

R3557

1/20W

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

1

C3540

0.1uF

20%
10V

2

CERM
402

AP_RESET_L

AP_CLKREQ_R_L

APCLKRQ:ISOL

1K

5%
MF

201

PM_WLAN_EN

R3556

21

1/20W

0201

AP_CLKREQ_L

X87 CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

33 46

IN

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

33 40 67

IN

33 40 67

1

0

5%
MF

2

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

33 46

20

IN

11 18

SYNC_DATE=10/30/2014

<E4LABEL>

<BRANCH>

35 OF 119

33 OF 97

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

FOR DESENSE IMPROVEMENT

D

PLACE_NEAR=J3700.1:3mm

CRITICAL

L3700

PP3V3_S0SW_SSD

34 45 84 86

1

C3701

0.1UF

10%
10V

2

X5R-CERM

PLACE_NEAR=L3700.1:1mm

0201

C

FERR-26-OHM-6A

PCIE_SSD_R2D_C_N<3>

5

85 89

IN

PCIE_SSD_R2D_C_P<3>

5

85 89

IN

PCIE_SSD_R2D_C_N<2>

5

85 89

IN

PCIE_SSD_R2D_C_P<2>

5

85 89

IN

PCIE_SSD_R2D_C_N<1>

5

85 89

IN

PCIE_SSD_R2D_C_P<1>

5

85 89

IN

PCIE_SSD_R2D_C_N<0>

5

85 89

IN

PCIE_SSD_R2D_C_P<0>

5

85 89

IN

C3710

0.22UF

C3711

0.22UF

C3712

0.22UF

C3713

0.22UF

C3714

0.22UF

C3715

0.22UF

C3716

0.22UF

C3717

0.22UF

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

21
20%

21
20%

21
20%

21
20%

21
20%

21
20%

21
20%

21
20%

21

0603

GND_VOID=TRUE

6.3V 0201

GND_VOID=TRUE

6.3V

GND_VOID=TRUE

6.3V

GND_VOID=TRUE

6.3V X6S-CERM 0201

GND_VOID=TRUE

GND_VOID=TRUE

6.3V

GND_VOID=TRUE

6.3V X6S-CERM

GND_VOID=TRUE

1

2

X6S-CERM

X6S-CERM 0201

X6S-CERM6.3V

X6S-CERM

X6S-CERM6.3V

PP3V3_S0SW_SSD_FLT

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.15mm

0201X6S-CERM

0201

0201

0201

0201

VOLTAGE=3.3V

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

SSD_RESET_CONN_L
NC_SSD_MFG_RSVD

PCIE_SSD_R2D_N<3>

89

PCIE_SSD_R2D_P<3>

89

PCIE_SSD_R2D_N<2>

89

PCIE_SSD_R2D_P<2>

89

PCIE_SSD_R2D_N<1>

89

PCIE_SSD_R2D_P<1>

89

PCIE_SSD_R2D_N<0>

89

PCIE_SSD_R2D_P<0>

89

SSD_CLKREQ_CONN_L

C3702

0.1UF

10%
10V
X5R-CERM
0201

PLACE_NEAR=L3700.1:1mm

NO_TEST=TRUE

1

C3722

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J3700.3:2mm

1

C3723

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J3700.4:2mm

GND_VOID

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

514S0449
CRITICAL

J3700

SSD-GS3

F-RT-SM
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26
27
28

1

C3724

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J3700.5:2mm

GND_VOID

53
52
51

50
49
48
47

46
45

TRUE

44

TRUE

43
42

TRUE

41

TRUE

40

39
38

TRUE

37

TRUE

36
35

TRUE

34

TRUE

33

32
31
30
29

NOSTUFF

R3700

SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L

SSD_PCIE_SEL_L
SSD_DEVSLP
SMC_PWRFAIL_WARN_L
SSD_PWR_FET_EN

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

100K

1/20W

201

1

1%
MF

2

18

OUT

20

IN

40

IN

34 66

IN

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

5

85 89

OUT

11 91

IN

11 91

IN

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

OOB Isolation

PP3V3_S0SW_SSD

34 45 84 86

CRITICAL

74LVC1G08

SOT891

BYPASS=U3711::5 mm

C3719

0.1UF

10%
10V

X5R-CERM

0201

1

R3701

100K

1%

1/20W

MF

201

2

4

U3710

1

2

2

1

NC

NC

6

08

U3711

08

5 3

BYPASS=U3710::5 mm

1

C3718

0.1UF

10%
10V

2

X5R-CERM
0201

2

1

NC

53

NC

CRITICAL

74LVC1G08

6

SOT891

4

SMC_OOB1_R2D_L

SMC_OOB1_D2R_L

40

IN

40

OUT

D

C

54
55

B

Supervisor & CLKREQ# Isolation

Delay = ~55ms

R3740

100K

1/20W

201

1

5%
MF

2

PP3V3_S0SW_SSD

1

R3741

232K

1%
1/20W
MF
201

2

P3V3SSD_VMON

1

R3742

100K

1%
1/20W
MF
201

2

34 45 84 86

CRITICAL

SLG4AP016V

2

SENSE

0.7V

4

RESET*

7

IN

THRM

1

VDD

U3740

TDFN
+

-

PAD

9

DLY

GND

PP3V42_G3H

1

C3740

0.1UF

10%

6.3V

2

CERM-X5R
0201

APN 343S0511

3

MR*

OUT

(OD)

5

6

EN

8

SSD_RESET_L

SSD_PWR_FET_EN
SSD_CLKREQ_L

19 37 38 40 41 42 43 50 56 57
67 84 86

20

IN

34 66

IN

11

OUT

Gumstick3 Connector

56
57
58

A

SSD_PWR_FET_EN

SSD_PWR_FET_EN

MAKE_BASE=TRUE

34 66 34 66

6 3

59
60
61
62
63

SYNC_MASTER=CLEAN_X425

PAGE TITLE

SSD Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

37 OF 119

SHEET

34 OF 97

SIZE

B

A

D

124578

D

35

35

C

B

A

GND_CAM_PVSSC

GND_CAM_PVSSD

35

35

8 7 6 5 4 3

L3902

1.0UH-1.6A-55MOHM

CRITICAL

1

C3976

12PF

5%
NP0-C0G

2

0201
25V

1

C3971

1000PF

10%
16V

2

X7R-1
0201

BYPASS=U3900.F6::2.54MM

BYPASS=U3900.F9::2.54MM

CRITICAL

1

C3978

12PF

5%
NP0-C0G

2

0201
25V

13 20 46 84

PP1V8_CAM

35 36

R3913

C3937

0.1UF

10%

6.3V
CERM-X5R
0201

12 33 86 91

OUT

35 36

35 36 86

35 36 86

PCIE_WAKE_L

PP1V8_CAM

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

BI

36 94

OUT

36 94

OUT

36 94

OUT

36

OUT

21

1008

PLACE_NEAR=U3900.K13:4MM

1K

5%

1/20W

MF

201

OUT

BI

P1V35_CAM_SRVLXD_PHASE

PP1V8_CAM

35 36

1

R3920

100K

5%
1/20W
MF
201

2

1

C3972

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.F9::2.54MM

1

R3914

2

1

2

BYPASS=U3900.L9::2.54MM

36 94

36 94

36 94

36 94

36 91

36 91

36 91

36 91

36 91

36 91

1

1K

5%

1/20W

MF

201

2

NO STUFF

R3991

0

21

5%

1/20W

MF

0201

1

R3990

100K

5%
1/20W
MF
201

2

NO STUFF

1

C3990

0.1UF

10%

6.3V

2

CERM-X5R
0201

PU on PCH page

CAM_XTAL_FREQ

35

PU = 25MHz

1

R3921

100K

5%
1/20W
MF
201

2

I2C_CAM_SMBDBG_CLK
I2C_CAM_SMBDBG_DAT

C3973

1000PF

10%
16V
X7R-1
0201

BYPASS=U3900.L9::2.54MM

MIPI_CLK_P

IN

MIPI_CLK_N

IN

MIPI_DATA_P

IN

MIPI_DATA_N

IN

PCIE_CAMERA_R2D_P

IN

PCIE_CAMERA_R2D_N

IN

PCIE_CLK100M_CAMERA_C_P

IN

PCIE_CLK100M_CAMERA_C_N

IN

PCIE_CAMERA_D2R_C_P

OUT

PCIE_CAMERA_D2R_C_N

OUT

36

OUT

36

IN

35

35

11

OUT

20

IN

36

IN

20

IN

N7
N8
N6

C10

C7

G14
M12

N13
P14
P15
R15

K15
L12
L13
L14
L15

A1
A6
B6
D1
D5
E5
G1
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K1
K5
K6
K7
K8
K9

A14

M9
N1
P5
R1
R5

E9

B12

CAM_UARTCTS
CAM_UARTRXD

MIPI_AGND

PCIE_GND

PMU_AVSS

SR_PVSSC

SR_PVSSD

VSSC

XTAL_AVSS

U3900

BCM15700

FBGA

SYM 3 OF 3

CRITICAL

OMIT_TABLE

DDR_VDDIO_CK

PCIE_PVDD1P2

MIPI_AVDD1P8

SR_VDD_3P3C

SR_VDD_3P3D

L3901:1
L3902:1

XTAL_AVDD1P2

CRITICAL

1

C3981

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

R3975

51K

5%
1/20W
MF
201

2

DDR_VDDIO

DDR_VREF

PCIE_VDD1P2

DDR_AVDD1P8

PLL_VDD1P8

OTP_VDD3P3

SR_VLXC_O

SR_VLXD_O

VDD_1P35A

VDD_3P3A

VDD1P2_O

VDD1P8_O

VDDC

VDDO18

VSENSE_C
VSENSE_D

1

2

1

R3976

51K

5%
1/20W
MF
201

2

A4
D4
G4
K4
N4

G5

N5

C8

D9

J1

L7

D6

D7

M14
M15
N15

H14
H15
J13
J14
J15

M13
N14

K13
K14

F14

J11

F15

G15

F6
F7
F8
F9
L6
L5
L8
L9

B15

R11

M11
K12

B13

CRITICAL

C3977

12PF

5%
NP0-C0G
0201
25V

PP1V35_CAM

35 36 94

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP1V35_DDR_CLK

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP0V675_CAM_VREF

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0.675V

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM_PCIE_PVDD_FLT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V8_CAM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

(=PP3V3_S3RS0_CAMERA)

1

C3928

4.7UF

20%

6.3V

2

X5R
402

(=PP3V3_S3RS0_CAMERA)

P1V2_CAM_SRVLXC_PHASE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

P1V35_CAM_SRVLXD_PHASE

PP1V35_CAM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

35 36 94

PP1V2_CAM_XTALPCIEVDD

PP1V8_CAM

PP1V2_CAM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM

PP1V35_CAM

PP1V2_CAM_XTALPCIEVDD

1

C3960

0.1UF

10%

6.3V

2

CERM-X5R
0201

35

35 36 94

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MAKE_BASE=TRUE

PP1V2_CAM_XTALPCIEVDD

1

C3900

0.1UF

10%

6.3V

2

CERM-X5R
0201

36 94

1

C3927

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.D7::2.54MM

GND_CAM_PVSSC

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

35

35

35

19 35

R3912

240

21

1%

1/20W

MF

201

L3906

22NH

21

0402

1

C3938

1000PF

10%
16V

2

X7R-1
0201

XW3900

SM

21

PLACE_NEAR=U3900.M14:2.54MM

1

C3926

4.7UF

20%

6.3V

2

X5R
402

1

C3941

2.2UF

20%

6.3V

2

CERM

1

C3939

1UF

10%
10V

2

X5R
402

BYPASS=U3900.G15::2.54MM

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

19 35

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

36 94

OUT

402-LF

BYPASS=U3900.F15::2.54MM

MEM_CAM_A<0>
MEM_CAM_A<1>
MEM_CAM_A<2>
MEM_CAM_A<3>
MEM_CAM_A<4>
MEM_CAM_A<5>
MEM_CAM_A<6>
MEM_CAM_A<7>
MEM_CAM_A<8>
MEM_CAM_A<9>
MEM_CAM_A<10>
MEM_CAM_A<11>
MEM_CAM_A<12>
MEM_CAM_A<13>
MEM_CAM_A<14>

MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_DM<0>
MEM_CAM_DM<1>

MEM_CAM_ZQ_S2
MEM_CAM_CKE
MEM_CAM_CS_L

1

C3921

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3930

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3932

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3919

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.J1::2.54MM

GND_CAM_PVSSD

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

1

2

1

2

1

2

1

2

BYPASS=U3900.J1::2.54MM

1

C3942

4.7UF

20%

6.3V

2

X5R
402

BYPASS=U3900::7mm

L3

DDR_AD00

M4

DDR_AD01

N3

DDR_AD02

M3

DDR_AD03

M1

DDR_AD04

M2

DDR_AD05

P4

DDR_AD06

N2

DDR_AD07

P3

DDR_AD08

P2

DDR_AD09

J4

DDR_AD10

R2

DDR_AD11

L1

DDR_AD12

P1

DDR_AD13

R4

DDR_AD14

K3

DDR_BA0

L2

DDR_BA1

K2

DDR_BA2

H2

DDR_CK_P0

G2

DDR_CK_N0

C1

DDR_DM0

C4

DDR_DM1

G3

DDR_ZQ

J3

DDR_CKE

L4

DDR_CS*

1

C3922

0.1UF

10%

6.3V
CERM-X5R
0201

C3931

10UF

20%
4V
X5R
402

C3933

10UF

20%
4V
X5R
402

C3918

1000PF

10%
16V
X7R-1
0201

BYPASS=U3900.L7::2.54MM

XW3901

BYPASS=U3900::5mm

C3923

2

L3903

220-OHM-1.4A

0603

L3904

220-OHM-1.4A

0603

1

C3916

2

BYPASS=U3900.L7::2.54MM

SM

21

1

C3940

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900::3mm

BCM15700

OMIT_TABLE

1.0UF

20%

6.3V
X5R
0201-1

GND_CAM_PVSSD

35

21

21

0.1UF

10%

6.3V
CERM-X5R
0201

BYPASS=U3900.D6::2.54MM

1

C3934

1000PF

10%
16V

2

X7R-1
0201

BYPASS=U3900::5mm

U3900

FBGA

SYM 2 OF 3

CRITICAL

BYPASS=U3900.K13::2.54MM

1

C3924

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C3912

4.7UF

20%

6.3V

2

X5R
402

PP1V2_CAM_XTALPCIEVDD

1

C3917

1000PF

10%
16V

2

X7R-1
0201

1

C3910

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.D6::2.54MM

PP3V3_S3RS0_CAMERA

1

C3935

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900::3mm

DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15

DDR_DQS_P0
DDR_DQS_N0

DDR_DQS_P1
DDR_DQS_N1

DDR_RAS*

DDR_WE*

DDR_CAS*

DDR_RESET*

1

C3913

4.7UF

20%

6.3V

2

X5R
402

PP1V2_CAM

35

BYPASS=U3900.F6::2.54MM

1

C3951

0.1UF

10%

6.3V

2

CERM-X5R
0201

CRITICAL

1

C3980

12PF

5%
NP0-C0G

2

0201
25V

1

C3936

1000PF

10%
16V

2

X7R-1
0201

BYPASS=U3900::5mm

C2

MEM_CAM_DQ<0>

E3

MEM_CAM_DQ<1>

E4

MEM_CAM_DQ<2>

D3

MEM_CAM_DQ<3>

F3

MEM_CAM_DQ<4>

F1

MEM_CAM_DQ<5>

F4

MEM_CAM_DQ<6>

F2

MEM_CAM_DQ<7>

B5

MEM_CAM_DQ<8>

C3

MEM_CAM_DQ<9>

B1

MEM_CAM_DQ<10>

B4

MEM_CAM_DQ<11>

A5

MEM_CAM_DQ<12>

C5

MEM_CAM_DQ<13>

B2

MEM_CAM_DQ<14>

B3

MEM_CAM_DQ<15>

E2

MEM_CAM_DQS_P<0>

D2

MEM_CAM_DQS_N<0>

A2

MEM_CAM_DQS_P<1>

A3

MEM_CAM_DQS_N<1>

H3

MEM_CAM_RAS_L

J2

MEM_CAM_WE_L

H4

MEM_CAM_CAS_L

R3

MEM_CAM_RESET_L

19 35

1

C3970

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

2

6 3

35

1

C3974

0.1UF

10%

6.3V

2

CERM-X5R
0201

CLK25M_CAM_CLKP
CLK25M_CAM_CLKN

I2C_CAM_SMBDBG_CLK
I2C_CAM_SCK
I2C_CAM_SMBDBG_DAT
I2C_CAM_SDA

TP_CAM_JTAG_TCK
TP_CAM_JTAG_TDI
TP_CAM_JTAG_TDO
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TRST_L
TP_CAM_JTAG_SRST_L

CAMERA_CLKREQ_L
CAM_PCIE_RESET_L
CAM_PCIE_WAKE_L

CAM_PWR_SEL
CAM_DEBUG_RESET_L

1

R3901

100K

5%
1/20W
MF
201

2

CAM_SENSOR_WAKE_L
CAMERA_PWR_EN

1

R3904

100K

5%
1/20W
MF
201

2

1

C3975

0.1UF

10%

6.3V

2

CERM-X5R
0201

PD = 1.35V

1

2

1

2

35

35

1

2

GND_CAM_PVSSC

35

NC
NC

B10
A10

NC
NC

A13
A12

D15
R10
C15

F13
E12
F12
D12
D11
C11

P13
R14
N12

G12
E15
R13
H12

PP1V8_CAM

NO STUFF

R3906

100K

5%
1/20W
MF
201

CAM_XTAL_SEL

R3907

100K

5%
1/20W
MF
201

PP1V8_CAM

NOSTUFF

1

R3930

100K

5%
1/20W
MF
201

2

1

R3931

330K

5%
1/20W
MF
201

2

CRITICAL

C3979

12PF

5%
NP0-C0G
0201
25V

P7

MIPI_CP_CLK

R7

MIPI_CM_CLK

P8

MIPI_DP0

R8

MIPI_DM0

P6

MIPI_DP1

R6

MIPI_DM1

B7

PCIE_RDP0

A7

PCIE_RDN0

PCIE_REFCLKP
PCIE_REFCLKN

A8

PCIE_TDP0

B8

PCIE_TDN0

B9

PCIE_TESTP

C9

PCIE_TESTN

XTAL_P
XTAL_N

I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG

R9

I2C_DATA_SENSOR

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_SRST*

PCIE_CLKREQ*
PCIE_RST*
PCIE_WAKE*

PWR_MODE
RESET*
SENSOR_WAKE*
SHUTDOWN*

I2C_CAM_SDA

35 36 86

35 36

35

35 36

NOSTUFF

1

R3932

100K

5%
1/20W
MF
201

2

1

R3933

330K

5%
1/20W
MF
201

2

1

C3914

4.7UF

20%

6.3V

2

X5R
402

I2C_CAM_SCK

35 36 86

NOSTUFF

1

R3934

100K

5%
1/20W
MF
201

2

CAM_RAMCFG2
CAM_RAMCFG1
CAM_RAMCFG0

1

R3935

330K

5%
1/20W
MF
201

2

L3901

1.0UH-1.6A-55MOHM

1

C3915

4.7UF

20%

PLACE_NEAR=U3900.M13:2.54MM

6.3V

2

X5R
402

U3900

BCM15700

FBGA

SYM 1 OF 3

CRITICAL

OMIT_TABLE

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

CRITICAL

1

C3982

12PF

5%
NP0-C0G

2

0201
25V

SYNC_MASTER=CLEAN_X425

PAGE TITLE

1

2

DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_06
DEBUG_07
DEBUG_08
DEBUG_09
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_14
DEBUG_15
DEBUG_16

TEST_OUT

TEST_MODE

35

CRITICAL

C3983

12PF

5%
NP0-C0G
0201
25V

21

1008

PLACE_NEAR=U3900.M13:4MM

B11
C14
B14
A15
E11
E10
F11
F10
G11
G10
H11
H10
J10
K11
K10
L11
L10

R12

GPIO_00

P12

GPIO_01

P11

GPIO_02

P10

GPIO_03

P9

GPIO_04

N11

GPIO_05

N10

GPIO_06

N9

GPIO_07

D13

UARTCTS

D14

UARTRTS

E13

UARTRXD

E14

UARTTXD

J12
M10

C13

C12

CAM_TEST_MODE

35

CAM_TEST_OUT

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC

Camera 1 of 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

35

35

35

P1V2_CAM_SRVLXC_PHASE

TP_CAM_TEST_MODE0
TP_CAM_TEST_MODE1
TP_CAM_TEST_MODE2
TP_CAM_LV_JTAG_TCK
TP_CAM_LV_JTAG_TDI
TP_CAM_LV_JTAG_TDO
TP_CAM_LV_JTAG_TMS
TP_CAM_LV_JTAG_TRSTN

PP1V8_CAM

35 36

NOSTUFF

R3936

CAM_RAMCFG0
CAM_RAMCFG1
CAM_RAMCFG2
CAM_GPIO3

35

35

35

NOSTUFF

R3937

CAM_UARTCTS
TP_CAM_UARTRTS

CAM_UARTRXD
TP_CAM_UARTTXD

CAM_TEST_OUT
CAM_TEST_MODE

CAM_XTAL_FREQ
CAM_XTAL_SEL

NO STUFF

1

R3910

100K

5%
1/20W
MF
201

2

35

35

35

35

35

35

1

R3911

100K

5%
1/20W
MF
201

2

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

39 OF 119

SHEET

35 OF 97

124578

100K

1/20W

201

100K

1/20W

201

D

35

C

1

5%
MF

2

1

5%
MF

2

B

A

SIZE

D

8 7 6 5 4 3

12

PP1V35_CAM

35 94

R4000

D

PP0V675_CAM_VREF

35 94

R4022

1/20W

R4023

1/20W

201

201

1

1K

1%
MF

2

1

1K

1%
MF

2

C

35 94

IN

35 94

IN

35 94

IN

MEM_CAM_CKE_R

NO STUFF

1

C4026

100PF

5%
25V

2

C0G
0201

B

0201

1/20W

0

5%

1

2

1

2

21

MF

R4002

1/20W

NOSTUFF

R4003

1/20W

R4020

84.5

1%
1/20W
MF
201

NO STUFF

R4021

82

1%
1/20W
MF
201

201

201

PP0V675_MEM_CAM_VREFDQ

94

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

PP0V675_MEM_CAM_VREFCA

94

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

C4010

0.1UF

10%

6.3V

CERM-X5R

0201

1

1K

5%
MF

2

1

1K

5%
MF

2

1

R4004

240

1%
1/20W
MF
201

2

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35 94

IN

35

IN

CRITICAL

1

C4017

12PF

5%
NP0-C0G

2

0201
25V

1

1

C4011

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

MEM_CAM_A<0>
MEM_CAM_A<1>
MEM_CAM_A<2>
MEM_CAM_A<3>
MEM_CAM_A<4>
MEM_CAM_A<5>
MEM_CAM_A<6>
MEM_CAM_A<7>
MEM_CAM_A<8>
MEM_CAM_A<9>
MEM_CAM_A<10>
MEM_CAM_A<11>
MEM_CAM_A<12>
MEM_CAM_A<13>
MEM_CAM_A<14>

MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>

MEM_CAM_RAS_L
MEM_CAM_CAS_L
MEM_CAM_WE_L

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_CKE
MEM_CAM_CS_L

MEM_CAM_ODT

94

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

BYPASS=U4000.A1::4mm

CRITICAL

1

C4018

12PF

5%
NP0-C0G

2

0201
25V

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M2
N8
M3

J3
K3
L3

J7
K7

K9
L2

K1

L8

T2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

BA0
BA1
BA2

RAS*
CAS*
WE*

CK
CK*

CKE
CS*

ODT

ZQ

RESET*

1

2

C4002

10UF

20%
4V
X5R
402

VDDQ

VSSQ

BYPASS=U4000.B2::4mm

1

C4003

10UF

20%
4V

2

X5R
402

H9H2F1E9D2C9C1A8A1

U4000

4GB-DDR3-256MX16

K4B4G1646B-HYK0

B2

FBGA

D9

BYPASS=U4000.H9::4mm

VDD

CRITICAL

OMIT_TABLE

VSS

G9G1F9E8E2D8D1B9B1

E1

B3

A9

1

C4004

0.47UF

20%
4V

2

CERM-X5R-1
201

BYPASS=U4000.D2::4mm

H1

J1

VREFDQ

NC

J9

NC

L1

NC

L9

NC

M7

NC

E3
F7
F2
F8
H3
H8
G2
H7

F3

MEM_CAM_DQS_P<0>

G3

MEM_CAM_DQS_N<0>

C7

MEM_CAM_DQS_P<1>

B7

MEM_CAM_DQS_N<1>

D7
C3
C8
C2
A7
A2
B8
A3

E7

DML

D3

DMU

1

C4006

2.2UF

20%
10V

2

X5R-CERM
402

MEM_CAM_DQ<0>
MEM_CAM_DQ<1>
MEM_CAM_DQ<2>
MEM_CAM_DQ<3>
MEM_CAM_DQ<4>
MEM_CAM_DQ<5>
MEM_CAM_DQ<6>
MEM_CAM_DQ<7>

MEM_CAM_DQ<8>
MEM_CAM_DQ<9>
MEM_CAM_DQ<10>
MEM_CAM_DQ<11>
MEM_CAM_DQ<12>
MEM_CAM_DQ<13>
MEM_CAM_DQ<14>
MEM_CAM_DQ<15>

MEM_CAM_DM<0>
MEM_CAM_DM<1>

1

C4005

0.1UF

10%

6.3V

2

CERM-X5R
0201

M8

R9R1N9N1K8K2G7

VREFCA

NC

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQSL

DQSL*

DQSU

DQSU*

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

P9P1M9M1J8J2G8

T9

T1

1

C4007

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U4000.R9::4mm

BYPASS=U4000.K2::4mm

1

C4008

2.2UF

20%
10V

2

X5R-CERM
402

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

BI

35 94

IN

35 94

IN

1

C4009

0.1UF

10%

6.3V

2

CERM-X5R
0201

CAM_SENSOR_WAKE_L_CONN

36 86

CAM_WAKE:NO

13 91

13 91

35 91

35 91

11 91

11 91

1

R4031

0

5%

1/20W

MF

0201

2

PCIE_CAMERA_R2D_C_P

IN

PCIE_CAMERA_R2D_C_N

IN

PCIE_CAMERA_D2R_C_P

IN

PCIE_CAMERA_D2R_C_N

IN

PCIE_CLK100M_CAMERA_P

IN

PCIE_CLK100M_CAMERA_N

IN

CAM_WAKE:YES

R4030

0

21

5%

0201

1/20W

MF

C4033
C4032

C4031
C4030

C4061
C4062

CAM_SENSOR_WAKE_L

35

21

PCIE_CAMERA_R2D_P

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

10%
21

PCIE_CAMERA_R2D_N

10%

21

PCIE_CAMERA_D2R_P

10%
21

PCIE_CAMERA_D2R_N

10%

21

PCIE_CLK100M_CAMERA_C_P

10%

21

PCIE_CLK100M_CAMERA_C_N

10%

X5R-CERM 0201

16V

X5R-CERM 0201

16V

16V

16V

X5R-CERM 0201

16V

X5R-CERM 0201

16V

PP1V8_CAM

1

R4005

100K

5%
1/20W
MF
201

2

0201X5R-CERM

0201X5R-CERM

D

35

C

35 91

OUT

35 91

OUT

13 20 91

OUT

13 20 91

OUT

35 91

OUT

35 91

OUT

B

remove DRAM SPD Straps

CRITICAL

L4009

CAMERA SENSOR

CRITICAL

J4002

CCR20-AK7100-1

F-RT-SM

14

1
2

MIPI_CLK_CONN_N

86 94

3

MIPI_CLK_CONN_P

86 94

4

CAM_SENSOR_WAKE_L_CONN

5

MIPI_DATA_CONN_N

86 94

6

MIPI_DATA_CONN_P

86 94

7
8

SMBUS_SMC_0_S0_SDA

9

A

ALS

SMBUS_SMC_0_S0_SCL

10

I2C_CAM_SCK

11

I2C_CAM_SDA

12

PP5V_S3RS0_ALSCAM_F

86

13

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

BI
IN
IN
BI

C4013

518S0892

36 86

40 43 48 69 76 85 86 95

40 43 48 69 76 85 86 95

35 86

35 86

1

0.1uF

20%
10V

2

CERM

402

1

C4012

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J4002.12:2mm

FERR-120-OHM-1.5A

2 1

FERR-120-OHM-1.5A

2 1

90-OHM-0.1A-0.7-2GHZ

PLACE_NEAR=J4002.2:2.54MM

90-OHM-0.1A-0.7-2GHZ

PLACE_NEAR=J4002.5:2.54MM

L4010

0402-LF

NOSTUFF

L4011

0402-LF

TAM0605

SYM_VER-1

1

CRITICAL

L4007

TAM0605

SYM_VER-1

1

PP5V_S0

PP5V_S3

4

MIPI_CLK_N

32

MIPI_CLK_P

4

MIPI_DATA_N

32

MIPI_DATA_P

18 19 49 58 59 62 63 66 67 73
79 80 84 85 86

77.2 mA nominal max

96.2 mA peak

35 94

IN

35 94

IN

35 94

BI

35 94

BI

21 60 66 67 84 86

NO STUFF

C4015

12PF

21

5%

25V
CERM
0201

C4014

12PF

21

5%

25V
CERM
0201

3 1

NO STUFF

SYSCLK_CLK25M_CAMERA

19 90

IN

CLK25M_CAM_XTALP

CRITICAL

Y4000

NC

SM-3.2X2.5MM

NC

4 2

25.000MHZ-12PF-20PPM
NO STUFF

NO STUFF

R4007

21

020105%

1/20W

MF

CLK25M_CAM_XTALP_R

NO STUFF

1

R4012

1M

1%
1/20W
MF
201

2

CLK25M_CAM_XTALN

NOTE: TBD PPM crystal required

020105%

R4009

NO STUFF

R4010

0

5%

1/20W

MF

0201

NO STUFF

R4008

1/20W

0

5%

1/20W

MF

0201

21

21

CLK25M_CAM_CLKP

MF

21

CLK25M_CAM_CLKN

1

C4016

100PF

5%
25V

2

C0G
0201

35

IN

SYNC_MASTER=CLEAN_X425

PAGE TITLE

Camera 2 of 2

35

OUT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

DRAM CFG Chart

VENDOR
HYNIX
SAMSUNG
MICRON
ELPIDA

DIE REV

A
B

Apple Inc.

R

CFG 110CFG 0

0
1

1

0
0

1

CFG 2

0
1

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

40 OF 119

SHEET

36 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

USB Port Power Switch

D

Left USB Port A

PP5V_S4

38 51 61 66 67 69 81 84 86

PM_SLP_S4_L

12 21 33 40 67 81 86

1

R4690

0

5%
1/16W
MF-LF

402

2

18

OUT

USB_EXTA_OC_L

USB_PWR_EN

1

220UF-35MOHM

2

CASE-B2-SM1

CRITICAL

C4696

20%

6.3V

POLY-TANT

1

1

1

2

C4690

10UF

20%

6.3V
X5R
603

C4691

0.1UF

20%
10V

2

2

CERM
402

NOSTUFF

C4692

0.47UF

10%
10V
X5R

0402

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

C

USB/SMC Debug Mux

PP3V42_G3H

19 34 38 40 41 42 43 50
56 57 67 84 86

C4650

SMC_DEBUGPRT_RX_L

40 41 90

IN

SMC_DEBUGPRT_TX_L

40 41 90

OUT

USB_EXTA_P

13 90

BI

USB_EXTA_N

13 90

BI

B

0.1UF

CERM

20%
10V

402

1

2

5
4

7
6

8

9

VCC

M+
M-

U4650

PI3USB102EZLE

TQFN

D+

CRITICAL

D-

GND

3

1

Y+

2

Y-

10

SELOE*

1

R4650

100K

5%
1/16W
MF-LF
402

2

SMC_DEBUGPRT_EN_L

SEL=0 Choose SMC
SEL=1 Choose USB

SIGNAL_MODEL=MOJO_MUX_USBONLY

NOSTUFF

R4651

0

21

5%

1/20W

MF

0201

NOSTUFF

R4652

0

5%

1/20W

MF

0201

21

CRITICAL

U4600

TPS2557DRB

SON

2

IN_0

3

IN_1

8

FAULT*

4

EN

GND

1

IN

OUT1

OUT2

ILIM

THRM

PAD

9

USB_ILIM_R

40

6
7

5

USB_ILIM

R4601

22.1K

1/20W

R4600

22.1K

1/16W
MF-LF

201

402

CRITICAL

L4605

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

1%
MF

2

1

1%

2

C4695

10UF

20%

6.3V
X5R
603

1

2

USB_EXTA_MUXED_N

90

USB_EXTA_MUXED_P

90

USB3_EXTA_D2R_N

13 90

OUT

USB3_EXTA_D2R_P

13 90

OUT

C4605

0.01UF

X7R-CERM

FERR-26-OHM-6A

1

20%
16V

2

0402

90-OHM-0.1A-0.7-2GHZ

CRITICAL

L4600

TAM0605

SYM_VER-1

1

0603

ESD112-B1-02ELS

PLACE_NEAR=J4600.1:5MM

21

PP5V_S3_LTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

4

32

CRITICAL

ESD112-B1-02ELS

D4601

0201-THICKSTNCL

GND_VOID=TRUE

CRITICAL

D4610

0201-THICKSTNCL

2

1

2

1

CRITICAL

1

C4606

12PF

5%
NP0-C0G

2

0201
25V

2

CRITICAL

D4600

ESD112-B1-02ELS

0201-THICKSTNCL

1

GND_VOID=TRUE

2

CRITICAL

D4611

ESD112-B1-02ELS

0201-THICKSTNCL

1

CRITICAL

1

C4607

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

USB3_EXTA_R2D_P

90

USB3_EXTA_R2D_N

90

USB_LT1_N

90

USB_LT1_P

90

CRITICAL

J4600

USB3.0-J44-ALT

F-RT-TH

1

VBUS

2

SSTX+

3

SSTX-

4

GND

5

D-

6

D+

7

GND

8

SXRX+

9

SSRX-

10

GND

11
12
13
14
15
16
17
18
19
20
21
22
23

514-0934

C

B

GND_VOID=TRUE

USB3_EXTA_R2D_C_N

13 90

IN

USB3_EXTA_R2D_C_P

13 90

IN

C4610

C4611

0.1UF

0.1UF

A

6 3

21
10%

21
10%

GND_VOID=TRUE

16V

X5R-CERM

16V

X5R-CERM

0201

0201

GND_VOID=TRUE

CRITICAL

ESD112-B1-02ELS

D4612

0201-THICKSTNCL

2

1

GND_VOID=TRUE

2

CRITICAL

D4613

ESD112-B1-02ELS

0201-THICKSTNCL

1

SYNC_MASTER=CLEAN_X425

PAGE TITLE

USB 3.0 CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

46 OF 119

SHEET

37 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

IPD CONNECTOR

CRITICAL

J4801

DF40CG1.5-48DS-0.4V

CRITICAL

F4809

PPVIN_S4_TPAD

45 84 86

2.5A-16V-0.1OHM

D

GND_ACTUATOR

38 86

PART WILL NOT WORK WITH BOOST.

SMC Manual Reset & Isolation

LEFT SHIFT, OPTION & CONTROL KEYS COMBINED WITH POWER BUTTON CAUSE SMC RESET# ASSERTION.

C

PP3V3_S4

20 33 38 41 42 45 46
65 66 67 81 84 85 86

WS_LEFT_SHIFT_KBD

38 86

WS_LEFT_OPTION_KBD

38 86

WS_CONTROL_KBD

38 86

B

PP3V3_S4

20 33 38 41 42 45 46 65 66
67 81 84 85 86

R4822

2.0K

1/20W

201

A

Keys ANDed with PSoC power to isolate when PSoC is not powered.

No IPD on OE input pin PP3V3_S4 (symbol error).

PP3V42_G3H

19 34 37 38 40 41 42 43 50 56
57 67 84 86

10

VDD

U4850

SLG4AP4103

GND

5

TQFN

THRM

PAD

11

4

OE

(IPD)

1

IN_1

(IPD)

2

IN_2

(IPD)

3

IN_3

(IPD)

IO EXPANDER / KEYBOARD INTERFACE

1

1

R4820

100K

5%
1/20W
MF

2

201

2

IOXP1_INT_L

I2C_IOXP_SCL

38 86

I2C_IOXP_SDA

38 86

IOXP1_RESET_L

1

2

5%
MF

1

R4823

2

2.0K

1/20W

201

5%
MF

1

2

R4821

1/20W

NOSTUFF

C4824

0.01UF

X5R-CERM

0201

10K

10%
10V

201

5%
MF

BYPASS=U4850.10:5:5 mm

BYPASS=U4820.B4:E2:5MM

1812

OUT_1

OUT_2

OUT_3

OUT_ALL#

1

C4820

1UF

10%

6.3V

2

CERM
402

B5

A5
A4

A2

21

CRITICAL

1

C4805

12PF

2%
100V

2

CERM
0402

1

C4850

0.1UF

10%
16V

2

X7R-CERM

0402

9

WS_LEFT_SHIFT_KEY

8

WS_LEFT_OPTION_KEY

7

WS_CONTROL_KEY

Pull-up in U5110.

6

SMC_TPAD_RST_L

B4

B3

VCCI

VCCP

U4820

PCAL6416A

INT*

VFBGA

ADDR

SCL
SDA

RESET*

GND

E2

C4808

1.0UF

CERM-X5R

PLACE_NEAR=J4801.7:5mm

BYPASS=U4820.B3:E2:2MM

1

2

A1A3

P0_0

C3

P0_1

B1

P0_2

C1

P0_3

C2

P0_4

D1

P0_5

E1

P0_6

D2

P0_7

E3

P1_0

E4

P1_1

D3

P1_2

E5

P1_3

D4

P1_4

D5

P1_5

C5

P1_6

C4

P1_7

311S0597

PPVIN_S4_TPAD_FUSE

1

10%
35V

2

0402

PLACE_NEAR=J4801.7:5mm

38

38

38

OUT

C4821

0.1UF

10%

6.3V
CERM-X5R
0201

WS_KBD23
WS_KBD2
WS_KBD1
WS_KBD3
WS_KBD4
WS_KBD20
WS_KBD22
WS_KBD21

TP_IOXP1_0
TP_IOXP1_1
TP_IOXP1_2
TP_IOXP1_3
TP_IOXP1_4
IOXP1_DEBUG SMC_ONOFF_L
WS_KBD16N
IOXP1_LED_DRV

1

C4806

0.1UF

10%
35V

2

CER-X5R
0201

NOSTUFF

1

R4891

0

5%
1/16W
MF-LF
402

2

41

BYPASS=U4820.B4:E2:2MM

1

C4822

0.1UF

10%

6.3V

2

CERM-X5R
0201

38 86

38 86

38 86

38 86

38 86

38 86

38 86

38 86

38

1

2

SMBUS_SMC_2_S3_SDA

40 43 86 95

SMBUS_SMC_2_S3_SCL

40 43 86 95

TPAD_NC3

SMC_PME_S4_WAKE_L

33 40 42

86

PP3V3_S4

20 33
38 41
42 45
46 65 66 67 81 84 85
86

TPAD_SPI_INT_L

85

TPAD_SPI_BUS_EN

85

TPAD_SPI_SCLK

85 91

TPAD_SPI_MISO

85 91

TPAD_SPI_CS_L

85 91

TPAD_SPI_MOSI

85 91

NOSTUFF

R4824

0

2 1

5%

1/20W

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=28V

C4807

0.1UF

10%
35V
CER-X5R
0201

PLACE_NEAR=J4801.7:5mm

MF

0201

CONNECT WITH 516S1037

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

DMN32D2LFB4

38 40 41 86

R4840

(Write: 0x40 Read: 0x41)

F-ST-SM

49

1
3
5

9

19

29

39

APN 516S1035

R4831

10K

5%

1/20W

MF

201

NOSTUFF

C4834

0.01UF

10%
10V

X5R-CERM

0201

Q4840

DFN1006H4-3

SYM_VER_2

100K

1/16W
MF-LF

402

D

1

G S

1

1%

2

50

2
4
6
87
10
1211
1413
1615

20

SMC_ACTUATOR_EN_R_L

2221

TPAD_VBUS_EN

2423

TPAD_ACTUATOR_THRMTRIP_L

2625
2827

SMC_LID

30
3231

3635

USB_TPAD_P

3837

USB_TPAD_N

40
4241

I2C_IOXP_SCL

4443

IOXP2_INT_L

4645

I2C_IOXP_SDA

4847

TPAD_NC4

5251

1

1

R4830

100K

5%
1/20W
MF
201

2

2

IOXP2_INT_L

38 86

38 86

38 86

1

2

WS_KBD15_C

3

2

2

XW4801

SM

PLACE_NEAR=J4801:3MM

1

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

GND_ACTUATOR

NOSTUFF

R4893

NOSTUFF

1

R4890

0

5%
1/16W
MF-LF
402

2

CRITICAL

1

C4833

12PF

5%
NP0-C0G

2

0201
25V

I2C_IOXP_SCL
I2C_IOXP_SDA

IOXP2_RESET_L

38

38 86

PP3V3_S4

1

100K

5%

1/20W

MF

201

2

R4808

0

1/20W

5% MF 0201

67 86

PP5V_S4_TPAD_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

C4801

100PF

13 86 90

13 86 90

38 86

38 86

38 86

BYPASS=U4830.B4:E2:5MM

1

C4830

1UF

10%

6.3V

2

CERM
402

25V
C0G

0201

B3

VCCI

5%

U4830

PCAL6416A

INT*

ADDR

SCL
SDA

RESET*

VFBGA

GND

E2

B5

A5
A4

A2

20 33 38 41 42 45 46 65 66 67
81 84 85 86

SMC_ACTUATOR_EN_L

21

65 86

VOLTAGE=5V

C4803

1

0.1uF

2

B4

VCCP

P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7

P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7

311S0597

(Write: 0x42 Read: 0x43)

1

20%
10V

2

CERM

402

BYPASS=U4830.B3:E2:2MM

1

C4831

0.1UF

10%

6.3V

2

CERM-X5R
0201

A1A3

WS_KBD5

38 86

C3

WS_KBD6

38 86

B1

WS_KBD7

38 86

C1

WS_KBD9

38 86

C2

WS_KBD12

38 86

D1

WS_KBD8

38 86

E1

WS_KBD17

38 86

D2

WS_KBD18

38 86

E3

WS_KBD19

38 86

E4

WS_KBD10

38 86

D3

WS_KBD14

38 86

E5

WS_KBD13

38 86

D4

WS_KBD11

38 86

D5
C5
C4

L4803

FERR-120-OHM-1.5A

2 1

1

C4804

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

BYPASS=U4830.B4:E2:2MM

1

C4832

0.1UF

10%

6.3V

2

CERM-X5R
0201

WS_CONTROL_KEY

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KEY

40 86

OUT

0402-LF

R4802

20 33 38 41 42 45 46 65 66 67
81 84 85 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

PP5V_S4

38

38

SMC_ONOFF_L

38 40 41 86

OUT

PLACE_NEAR=J4813.5:5MM

1

R4801

10K

1/20W

201

10K

5%

1/20W

MF

2

38

38

38

PP3V3_S4
PP3V42_G3H

1

C4811

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

WS_KBD15_C

WS_KBD16N

C4810

PP3V3_S4

1

R4852

5%
MF

201

2

6 3

Keyboard Connector

1

C4812

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

37 51 61 66 67 69 81 84 86

R4814

113

21

1%
1/16W
MF-LF

402

R4815

0

21

5%
1/16W
MF-LF

402

R4810

1K

21

5%
1/16W

1

MF-LF

0.1UF

20%
10V

CERM

402

10K

5%

1/20W

MF

201

SYNC_MASTER=CLEAN_X425G

PAGE TITLE

402

2

20 33 38 41 42 45 46 65 66 67
81 84 85 86

1

R4853

10K

5%

1/20W

MF

201

2

R4858

10K

5%

1/20W

MF

201

1

R4854

2

1

R4859

2

KEYBOARD/TRACKPAD (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

WS_KBD1

38 86

WS_KBD2

38 86

WS_KBD3

38 86

WS_KBD4

38 86

WS_KBD5

38 86

WS_KBD6

38 86

WS_KBD7

38 86

WS_KBD8

38 86

WS_KBD9

38 86

WS_KBD10

38 86

WS_KBD11

38 86

WS_KBD12

38 86

WS_KBD13

38 86

WS_KBD14

38 86

WS_KBD15_CAP

86

WS_KBD16_NUM

86

WS_KBD17

38 86

WS_KBD18

38 86

WS_KBD19

38 86

WS_KBD20

38 86

WS_KBD21

38 86

WS_KBD22

38 86

WS_KBD23

38 86

WS_KBD_ONOFF_L

86

WS_LEFT_SHIFT_KBD

38 86

WS_LEFT_OPTION_KBD

38 86

WS_CONTROL_KBD

38 86

1

R4855

10K

5%

201

1/20W

MF

2

1/20W

PP3V3_S4

1

R4860

10K

5%

1/20W

201

1/20W

MF

2

FF14A-30C-R11DL-B-3H

10K

201

10K

201

1

5%
MF

2

1

5%
MF

2

1

R4856

10K

5%

1/20W

MF

201

2

20 33 38 41 42 45 46 65 66 67
81 84 85 86

1

R4861

10K

5%

1/20W

MF

201

2

SYNC_DATE=09/10/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

48 OF 119

SHEET

38 OF 97

124578

518S0752

CRITICAL

J4813

32

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31

F-RT-SM

R4857

10K

1/20W

201

R4862

10K

1/20W

201

D

C

1

5%
MF

2

B

1

5%
MF

2

A

SIZE

D

8 7 6 5 4 3

12

Keyboard Backlight Connector

516S0899

D

KBDBKLT_RETURN1

63 86

KBDBKLT_RETURN2

63 86

PPVOUT_S0_KBDBKLT

63 86

CRITICAL

J4915

AA07A-S010-VA1

F-ST-SM

2

4 3

NC

6 5

8 7

10

12

11

1

NC

9

13

14

D

C

B

C

B

A

6 3

SYNC_MASTER=CLEAN_MAXWELL

PAGE TITLE

KEYBOARD/TRACKPAD (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=07/02/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

49 OF 119

SHEET

39 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

D

13 82 91

BI

13 82 91

BI

13 82 91

BI

13 82 91

BI

19 91

IN

13 82 91

IN

20

IN

13

BI

12

OUT

12 20

IN

14

OUT

14

OUT

36 43 48 69 76 85 86 95

BI

36 43 48 69 76 85 86 95

BI

43 48 95

BI

43 48 95

BI

38 43 86 95

BI

38 43 86 95

C

B

BI

42 95

BI

42 95

BI

42

BI

42

BI

43 56 57 86 95

BI

43 56 57 86 95

BI

49

OUT

49

IN

49

OUT

49

IN

42

OUT

63

OUT

65

BI

42 82

BI

56

BI

42

IN

42

OUT

41

BI

41

OUT

41

IN

42

IN

33 38 42 86

IN

20 28 41 42

IN

41 67

OUT

38 86

IN

38 41 42 86

IN

42

IN

41

IN

41 42 56 57

IN

41

IN

12 21 67 86

IN

12 21 33 37 67 81 86

IN

12 67

IN

38 41 86

IN

41

IN

41

OUT

34

OUT

33 67

OUT

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
NC_SMBUS_SMC_3_SCL
NC_SMBUS_SMC_3_SDA
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_TOPBLK_SWP_L
TP_SMC_MPM5_LED_CHG

SMC_SYS_KBDLED
SMC_ACTUATOR_DISABLE_L
SMC_GFX_SELF_THROTTLE
SYS_ONEWIRE
NC_HISIDE_ISENSE_OC
SMC_PCH_SUSACK_L

CPU_PECI_R
SMC_PECI_L

SMC_BIL_BUTTON_L
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN

SMC_ACTUATOR_EN_L
SMC_LID

SMC_PCH_SUSWARN_L
SMS_INT_L
SMC_BC_ACOK
G3_POWERON_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L

SMC_RX_L
SMC_TX_L

SMC_PWRFAIL_WARN_L
PM_WLAN_EN

(OD)
(OD)

(OD)

(OD)

(OD)
(OD)

(OD)

(OD)
(OD)

(OD)
(OD)

(OD)

(OD)
(OD)

NC

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1

A12

PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3

N12

PN5/FAN0TACH3

N11

PN6/FAN0PWM4

M11

PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116

L12

PP1/IRQ117

M5

PP2/IRQ118

J12

PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

U5000

LM4FSXAH5BB

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2­T3CCP0/PJ4/C2+

AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23

PC5/C1+

SSI0CLK/PA2
SSI0FSS/PA3

SSI0RX/PA4
SSI0TX/PA5

U1RX/B0

U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7

SSI1RX/PF0
SSI1TX/PF1

SSI1CLK/PF2
SSI1FSS/PF3

WT0CCP0/PG4
WT0CCP1/PG5

WT2CCP0/PH0
WT2CCP1/PH1

WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7

T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3

WT5CCP1/PM3

C0­C0+
C1-

PF4
PF5

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8

K2
K1
L2
L1
C5
D5

M2
M3
L4
N1

F11
E11
F4
F3

M9
N9
L10
K10
L9
K9

K7
L7

K3
K4

J3
H4
H3
G4

C9
B9
A9
C8

H10

SMC_CPUPKG_VSENSE
SMC_CPUPKG_ISENSE
SMC_TPAD_ISENSE
SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_SSD_ISENSE
SMC_CHGR_BMON_ISENSE
SMC_CPU_HI_ISENSE
SMC_OTHER3V3_HI_ISENSE
SMC_P1V35MEM_ISENSE
SMC_CPUDDR_ISENSE
SMC_LCDPANEL_ISENSE
SMC_OTHER5V_HI_ISENSE
SMC_GPU_HI_ISENSE
SMC_GPUCORE_ISENSE
SMC_GPUCORE_VSENSE
SMC_GPU_VDDCI_ISENSE
SMC_GPU0V95_ISENSE
SMC_PCH_CORE_ISENSE
SMC_GPU_FB_ISENSE
SMC_GPU_FB_VSENSE
SMC_X87_ISENSE
SMC_TBT_ISENSE

CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
SPI_DESCRIPTOR_OVERRIDE_L
CPU_CATERR_L
CPU_THRMTRIP_3V3

SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT

SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
NC_SMC_SYS_LED
SMC_GFX_PWR_LEVEL_L

(OD)

SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD
PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L
SMC_GFX_OVERTEMP

ALL_SYS_PWRGD
SMC_THRMTRIP

PM_PWRBTN_L
PM_SYSRST_L

(OD)

NC_MEM_EVENT_L

(OD)

SMC_ADAPTER_EN

SMC_OOB1_D2R_L
SMC_OOB1_R2D_L
NC_IR_RX_OUT_RC
NC_SMC_TPAD_BOOST_DISABLE_L

PM_BATLOW_L

12

L5001

M10

G13

F10

J10

B11
N13
M12

N10

G12

K12

K13

D7
E6
E8
E9

J7
J9

J1
J6

D6

30-OHM-1.7A

0402

OMIT_TABLE

U5000

LM4FSXAH5BB

(2 OF 2)

RST*

PK4/RTCCLK
WAKE*
HIB*

XOSC0
XOSC1

OSC0
OSC1

VBAT

VDD

VDDC

BGA

21

SWCLK/TCK
SWDIO/TMS

SWO/TDO

VDDA

VREFA+
VREFA-

GNDA

GND

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V

C10G10
A10
A11
B10

TDI

A2

NC

D3

D2
D1

C3

41 44 45 46 47

E3

A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
K11

1

C5001

0.1UF

10%

6.3V

2

CERM-X5R
0201

NC

PP3V3_S5_AVREF_SMC

41 86

GND_SMC_AVSS

SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI

PLACE_NEAR=U5000.A1:4MM

1

2

41 50 86

41 50 86

41

41

XW5000

2 1

C5020

0.01UF

10%
10V
X5R-CERM
0201

D

SM

1

C5021

1UF

10%

6.3V

2

CERM
402

C

B

PP3V42_G3H

19 34 37 38 41 42 43 50 56 57
67 84 86

1

2

1

C5009

0.1UF

10%
16V

2

X5R-CERM
0201

1

C5014

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5011

1UF

10%
25V

2

X5R
402

C5005

0.1UF

10%
16V
X5R-CERM
0201

1

C5008

0.1UF

10%
16V

2

X5R-CERM
0201

1

C5013

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5010

1UF

10%
25V

2

X5R
402

1

C5004

0.1UF

10%
16V

2

X5R-CERM
0201

1

C5002

1UF

10%

6.3V

2

CERM

402

42 45

IN

42 45

IN

42 45

IN

42 44

IN

42 44

IN

42 44

IN

42 45

IN

42 44

IN

42 44

IN

42 44

IN

42 45

IN

42 46

IN

42 46

IN

42 44

IN

42 47

IN

42 47

IN

42 47

IN

42 47

IN

42 47

IN

42 45

IN

42 47

IN

42 47

IN

42 46

IN

42 45

IN

6

41 58 89

41

41

IN

OUT

IN
IN

OUT
OUT
OUT
OUT

IN
OUT
OUT

BI

IN
OUT
OUT
OUT

IN

IN

OUT

IN

IN
OUT

OUT
OUT

BI

OUT

IN
OUT

IN
OUT

OUT

19 41

6

89

41

41 61 67

12 86 91

19 29 30 41

41

37 41 90

37 41 90

42

42 82

50 91

50 91

50 91

50 91

61 67

12 18 19 86 91

37

42 82

18 19 58 67 86

41

12 18 91

12 19 86 91

42

12 41

34

34

42

42

12 30 42

1

2

1

C5007

0.1UF

10%
16V

2

X5R-CERM
0201

C5003

0.1UF

10%
16V
X5R-CERM
0201

1

2

1

C5015

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5012

1UF

10%
25V

2

X5R
402

C5006

0.1UF

10%
16V
X5R-CERM
0201

1

C5016

0.1UF

10%

6.3V

2

CERM-X5R
0201

41 50 57 86

33 41 86

41

1

2

IN

BI

IN

C5017

0.1UF

10%

6.3V
CERM-X5R
0201

SMC_RESET_L

WIFI_EVENT_L

SMC_CLK32K

SMC_EXTAL

41

SMC_XTAL

41

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V

1

R5002

1M

5%
1/20W
MF
201

2

(OD)

SMC_WAKE_L

NC

NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

A

If SMS interrupt is not used, pull up to SMC rail.

6 3

SYNC_MASTER=CLEAN_X305

PAGE TITLE

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

50 OF 119

SHEET

40 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC Reset "Button", Supervisor & AVREF Supply

84 86
50 56
40 41
19 34
37 38
42 43
57 67

D

38

38 40 41 86

PLACE_SIDE=BOTTOM

R5127

0

21

PP3V42_G3H_SMC_SPVSRPP3V42_G3H

NO STUFF

10%

6.3V
402

10%
10V

0201

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V

1

2

VREF-3.3V-VDET-3.0V

6

MR1*

7

MR2*

4

DELAY

1

2

GND

1

2

V+

(IPU)
(IPU)

5%
1/16W
MF-LF

Mac Mini: 5V

Mobiles: 3.42V

SMC_TPAD_RST_L

IN

SMC_ONOFF_L

IN

SMC_MANUAL_RST_L
OMIT

1

R5101

0

5%
1/10W
MF-LF
603

2

SILK_PART=SMC_RST

MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.

1

C5127

2

19 34 37 38 40 41 42 43 50
56 57 67 84 86

C5120

C5101

4.7UF

20%

6.3V
X5R
402

PP3V42_G3H

0.47UF

CERM-X5R

0.01UF

X5R-CERM

402

NOTE: Internal pull-ups are to VIN, not V+.

U5110

DFN

SN0903049

CRITICAL

3

VIN

RESET*

REFOUT

THRM

PAD

9

5

8

C5125

10uF

6.3V

1

2

20%
X5R

603

R5100

100K

5%
1/20W
MF
201

SMC_RESET_L

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

1

1

C5126

2

2

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

0.01UF

10%
10V
X5R-CERM
0201

OUT

40 50 57 86

40 86

40 44 45 46 47

6

40 58 89

14 42 91

CPU_PROCHOT_L

BI

PM_THRMTRIP_L_R

OUT

6

1

3

D

S G

D

40

IN

From SMC

Q5159

DMN5L06VK-7

SOT563

VER 3

2

SMC_PROCHOT

Q5159

DMN5L06VK-7

SOT563

SMC_PECI_L

VER 3

Debug Power "Buttons"

SMC_ONOFF_L

OMIT

OMIT

1

C

PLACE_SIDE=TOP

SILK_PART=PWR_BTN

R5116

1/10W
MF-LF

1

0

5%

603

2

R5115

0

PLACE_SIDE=BOTTOM
5%
1/10W
MF-LF
603

2

SILK_PART=PWR_BTN

SMC Crystal Circuit

40

40

SMC_XTAL

SMC_EXTAL

21

1%

1/20W

MF

201

12.000MHZ-30PPM-10PF-85C

1

2

C5110

12PF

5%
25V
CERM
0201

SMC_XTAL_R

CRITICAL

Y5110

3.2X2.5MM-SM-1

R5110

2.49K

B

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

38 40 41 86

OUT

PP1V05_S0

10 14 15 17 18 41 62 67 84 86

1

R5197

100K

1%
1/20W
MF
201

SMC_VCCIO_CPU_DIV2

40

31

42

NC

NC

1

C5111

12PF

5%
25V

2

CERM
0201

2

1

R5196

100K

1%
1/20W
MF
201

2

CPU_THRMTRIP_3V3

40 41

OUT

12

CRITICAL

Q5158

MMBT3904LP-7

DFN1006-3

PM_CLK32K_SUSCLK_R

IN

PLACE_NEAR=U1100.Y6:5.1mm

3

2

PM_THRMTRIP_B_L

1

R5158

3.3K

5%

1/20W

MF

201

R5112

22

5%

1/20W

MF

201

21

PM_THRMTRIP_L

21

SMC_CLK32K

4

S G

IN

5

SMC_THRMTRIP

6

14 89

SMC12 PECI SUPPORT

CRITICAL

Q5130

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

R5132

0

21

SMC_PECI_L_R

5%

1/20W

MF

0201

40

IN

40 41

IN

40

OUT

SMC_PME_S4_DARK_L

20 28 40 42

SMC_ONOFF_L

38 40 41 86

G3_POWERON_L

40

SMC_LID

38 40 42 86

SMC_TX_L

40

SMC_RX_L

40

SMC_DEBUGPRT_TX_L

37 40 90

SMC_DEBUGPRT_RX_L

37 40 90

SMC_TMS

40 50 86

SMC_TDO

40

SMC_TDI

40

SMC_TCK

40 50 86

SMC_BIL_BUTTON_L

40

SMC_BC_ACOK

40 42 56 57

SMC_S5_PWRGD_VIN

40

SMS_INT_L

40

CPU_THRMTRIP_3V3

40 41

SPI_DESCRIPTOR_OVERRIDE_L

19 40

40

1

2

OUT

To SMC

OMIT

R5133

NOSTUFF

NONE
NONE
NONE
0201

NOSTUFF

D

1

G S

CPU_PECI_R

R5169
R5170
R5172
R5171
R5173
R5174
R5175
R5176
R5177
R5178
R5179
R5180
R5181
R5187
R5192
R5193
R5194
R5195

PP1V05_S0

3

2

1

R5131

330

5%
1/20W
MF
201

2

R5134

43

5%

1/20W

MF

201

20 33 38 42 45 46 65 66 67 81
84 85 86

100K

10K
10K

100K

10K

100K

20K
20K
10K
10K
10K
10K

10K
470K
100K

10K
100K

10K

10 14 15 17 18 41 62 67 84 86

21

CPU_PECI

From/To CPU/PCH

PP3V42_G3H

19 34 37 38 40 41 42 43 50 56
57 67 84 86

PP3V3_S4

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

D

6

14 89

BI

C

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

MF
MF

MF

MF
MF

MF

MF
MF

B

201
201

201

201
201

201

201
201

SMC_THRMTRIP

40 41

SMC_DELAYED_PWRGD

19 29 30 40

SMC_PM_G2_EN

40 61 67

SMC_ADAPTER_EN

12 40

SMC_S4_WAKESRC_EN

40 67

WIFI_EVENT_L

33 40 86

A

SYNC_MASTER=CLEAN_X305

PAGE TITLE

R5186

R5191
R5198
R5185
R5190

R5189

SMC Shared Support

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

10K

100K
100K

10K

100K

10K

Apple Inc.

R

21

21

21

21
21

PP3V3_WLAN

33 86

21

5%

1/20W

MF

5%

1/20W
1/20W

1/20W

1/20W

1/20W

MF
MF

MF

MF

MF

5%

5%

5%

5%

SYNC_DATE=06/24/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

51 OF 119

SHEET

41 OF 97

124578

201

201
201

201

201

201

A

SIZE

D

8 7 6 5 4 3

12

SMC_BC_ACOK

40 41 42 56 57

SMC_CPUPKG_VSENSE

40 42 45

SMC_CPUPKG_ISENSE

40 42 45

SMC_TPAD_ISENSE

40 42 45

SMC_DCIN_VSENSE

D

C

40 42 44

SMC_DCIN_ISENSE

40 42 44

SMC_PBUS_VSENSE

40 42 44

SMC_SSD_ISENSE

40 42 45

SMC_CHGR_BMON_ISENSE

40 42 44

SMC_CPU_HI_ISENSE

40 42 44

SMC_OTHER3V3_HI_ISENSE

40 42 44

SMC_P1V35MEM_ISENSE

40 42 45

SMC_CPUDDR_ISENSE

40 42 46

SMC_LCDPANEL_ISENSE

40 42 46

SMC_OTHER5V_HI_ISENSE

40 42 44

SMC_GPU_HI_ISENSE

40 42 47

SMC_GPUCORE_ISENSE

40 42 47

SMC_GPUCORE_VSENSE

40 42 47

SMC_GPU_VDDCI_ISENSE

40 42 47

SMC_GPU0V95_ISENSE

40 42 47

SMC_PCH_CORE_ISENSE

40 42 45

SMC_GPU_FB_ISENSE

40 42 47

SMC_GPU_FB_VSENSE

40 42 47

SMC_X87_ISENSE

40 42 46

SMC_TBT_ISENSE

40 42 45

NC_SMBUS_SMC_4_ASF_SCL

40 42

NC_SMBUS_SMC_4_ASF_SDA

40 42

NC_SMBUS_SMC_3_SCL

40 42 95

NC_SMBUS_SMC_3_SDA

40 42 95

NC_SMC_TPAD_BOOST_DISABLE_L

40 42

SMC_PME_S4_DARK_L

20 28 40 41 42

MAKE_BASE=TRUE

Spare S4 IRQ

B

SMC_DP_HPD_L

40

OUT

SMC_BC_ACOK

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OCNC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_CPUPKG_VSENSE

MAKE_BASE=TRUE

SMC_CPUPKG_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_CHGR_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_P1V35MEM_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_GPUCORE_ISENSE

MAKE_BASE=TRUE

SMC_GPUCORE_VSENSE

MAKE_BASE=TRUE

SMC_GPU_VDDCI_ISENSE

MAKE_BASE=TRUE

SMC_GPU0V95_ISENSE

MAKE_BASE=TRUE

SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUE

SMC_GPU_FB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_FB_VSENSE

MAKE_BASE=TRUE

SMC_X87_ISENSE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

NC_SMC_TPAD_BOOST_DISABLE_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SMC_PME_S4_DARK_L

PP3V3_S4

1

R5259

100K

5%
1/20W
MF
201

2

20 33 38 41 42 45 46 65 66 67
81 84 85 86

40 42 40 42

40 42 95

40 42 95

20 28 40 41 42

20 28 40 41 42

40 41 42 56 57

IN

40 42 45

IN

40 42 45

IN

40 42 45

IN

40 42 44

IN

40 42 44

IN

40 42 44

IN

40 42 45

IN

40 42 44

IN

40 42 44

IN

40 42 44

IN

40 42 45

IN

40 42 46

IN

40 42 46

IN

40 42 44

IN

40 42 47

IN

40 42 47

IN

40 42 47

IN

40 42 47

IN

40 42 47

IN

40 42 45

IN

40 42 47

IN

40 42 47

IN

40 42 46

IN

40 42 45

IN

40 42

40 42

NC_SMC_SYS_LED

40 42

NC_MEM_EVENT_L

40 42

NC_IR_RX_OUT_RC

40 42

SMC_GFX_SELF_THROTTLE

40 42
82

SMC_GFX_PWR_LEVEL_L

40 42
82

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

SMC_GFX_SELF_THROTTLE

MAKE_BASE=TRUE

SMC_GFX_PWR_LEVEL_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

40 42

40 42

40 42

IN

40 42 82

40 42 82

GPU HI ISENSE

40 42

SMC_SUSACK:YES

R5230

0

21

201

201

5%
MF

0

5%
MF

PCH_SUSWARN_L

21

PCH_SUSACK_L

SMC_PCH_SUSWARN_L

40 12

OUT

SMC_PCH_SUSACK_L

40

IN

1/20W

R5231

1/20W

SMC_SUSACK:YES

D

C

PM_THRMTRIP_L_R

14 41 91

OUT

CRITICAL

3

D

Q5260

2

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

GS

SMC_GFX_OVERTEMP

40 82

IN

IN

12

OUT

B

PP3V3_S4

1

R5282

100K

5%
1/20W
MF
201

Hall Effect pads

APN: 998-3029

OMIT_TABLE

HALL-SENSOR-MLB-PADS-K99

A

PART NUMBER

607-6811

J5250

SM

8

1

NC

2
3

NC

QTY

1

SUBASSY,PCBA HALL EFFECT,K99

NC

7

PP3V42_G3H

6

86

54

NC

DESCRIPTION

SMC_LID_R

50 56 57 67 84

R5250

19 34 37 38 40 41
43

86

0

21

5%

1/20W

MF

0201

REFERENCE DES

J5250

1

C5250

0.001UF

10%
50V

2

X7R-CERM
0402

SMC_LID

CRITICAL

CRITICAL

38 40 41 86

BOM OPTION

SMC_TOPBLK_SWP_L

40

IN

12 30 40 42

PM_BATLOW_L

IN

33 38 40 42 86

33 38 40 42 86

SMC_PME_S4_WAKE_L

IN

SMC_PME_S4_WAKE_L

IN

R5283

1K

5%

1/20W

MF

201

21

PCH_STRP_TOPBLK_SWP_L

PM_BATLOW_L

MAKE_BASE=TRUE

OUT

12 30 40 42

2

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

12

OUT

6 3

20 33 38 41 42 45 46 65 66 67
81 84 85 86

33 38 40 42 86

OUT

PAGE TITLE

SMC Project Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

52 OF 119

SHEET

42 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH SMBus "0" Connections

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

1

1

Lynx Point

U1100

(MASTER)

SMBUS_PCH_CLK

13 18 43 81
85 86 91

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

13 18 43 81
85 86 91

MAKE_BASE=TRUE

R5300

1/16W
MF-LF

R5301

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

U5000

(MASTER)

95

SMBUS_SMC_0_S0_SCL

36 40 43 48
69 76 85 86

95

SMBUS_SMC_0_S0_SDA

36 40 43 48
69 76 85 86

eDP Connector

J8300

(Write: 0x86 Read: 0x87)

95

SMBUS_SMC_0_S0_SCL

36 40 43 48
69 76 85 86

95

SMBUS_SMC_0_S0_SDA

36 40 43 48
69 76 85 86

XDP Connectors

J1800 & J1850

C

(MASTER)

SMBUS_PCH_CLK

13 18 43 81
85 86 91

SMBUS_PCH_DATA

13 18 43 81
85 86 91

HDMI Redriver (on RIO)

J9510 -> U9700

(WRITE: 0xCC READ: 0xCD)

SMBUS_PCH_CLK

SMBUS_PCH_DATA

91
13 18 43
81 85 86

91
13 18 43
81 85 86

SMC

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

13 20 21 45 46 66 81 82 84 86

SMC "0" SMBus Connections

85
40 43 48 69 76

SMBUS_SMC_0_S0_SCL

36

86 95

MAKE_BASE=TRUE

85 86 95

40 43 48 69 76

SMBUS_SMC_0_S0_SDA

36

MAKE_BASE=TRUE

SMC "2" SMBUS CONNECTIONS

NOTE: SMC RMT bus remains powered and may be active in S3 state

PP3V3_S3

R5350

2.0K

1/20W

Need to check with SMC team

1

1

R5351

2.0K

5%

5%

1/20W
MF

MF

201

201

2

2

L&R Fin Stack Temp

EMC1414-A: U5850

(Write: 0x98 Read: 0x99)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

J4002

ALS

(Write: 0x72 Read: 0x73)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

U8400

GPU

(Write: 0x?? Read: 0x??)

NEED CONFIRM FROM AMD

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

85 86 95
36 40 43
48 69 76

85 86 95
36 40 43
48 69 76

85 86 95
36 40 43
48 69 76

85 86 95
36 40 43
48 69 76

85 86 95
36 40 43
48 69 76

85 86 95
36 40 43
48 69 76

(MASTER)

SMBUS_SMC_5_G3_SCL

40 43 56 57
86 95

SMBUS_SMC_5_G3_SDA

40 43 56 57
86 95

(MASTER)

SMC

U5000

SMC

U5000

PP3V42_G3H

19 34 37 38 40 41 42 50 56 57
67 84 86

Unused

SMC "5" SMBUS CONNECTIONS

1

R5380

2.0K

5%

1/20W

MF

201

43 56 57 86 95

SMBUS_SMC_5_G3_SCL

40

MAKE_BASE=TRUE

43 56 57 86 95

SMBUS_SMC_5_G3_SDA

40

MAKE_BASE=TRUE

2

SMC "4" SMBUS CONNECTIONS

SMC "3" SMBUS CONNECTIONS

1

R5381

2.0K

5%
1/20W
MF
201

2

Battery Charger

ISL6258 - U7100

(Write: 0x12 Read: 0x13)

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

Battery

J7050

(Write: 0x16 Read: 0x17)

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

40 43 56
57 86 95

40 43 56
57 86 95

40 43 56
57 86 95

40 43 56
57 86 95

D

C

B

A

SMLink 1 is slave port to

access PCH & CPU via PECI.

Lynx Point

U1100

(MASTER)

SML_PCH_0_CLK

13 91

MAKE_BASE=TRUE

SML_PCH_0_DATA

13 91

MAKE_BASE=TRUE

Lynx Point

U1100

(Write: 0x88 Read: 0x89)

SML_PCH_1_CLK

13 91

MAKE_BASE=TRUE

SML_PCH_1_DATA

13 91

MAKE_BASE=TRUE

PCH "SMLink 0" Connections

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

R5310

PCH "SMLink 1" Connections

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

NO STUFF

R5320

8.2K

1/16W
MF-LF

8.2K

1/20W

1

1/20W

1

R5371

1K

1K

5%

5%
1/20W

MF

MF

201

201

2

2

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SDA

Trackpad

J4801

(Write: 0x98 Read: 0x99)

38 40 43
86 95

38 40 43
86 95

SMC

U5000

(MASTER)

Unused

SMC

U5000

(MASTER)

SMBUS_SMC_2_S3_SCL

38 40 43 86
95

SMBUS_SMC_2_S3_SDA

38 40 43 86
95

40 43 86 95

SMBUS_SMC_2_S3_SCL

38

MAKE_BASE=TRUE

40 43 86 95

SMBUS_SMC_2_S3_SDA

38

MAKE_BASE=TRUE

R5370

SMC "1" SMBUS CONNECTIONS

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

1

1

SMC

1

1

R5311

8.2K

5%

5%
1/16W
MF-LF

402

402

2

2

U5000

(MASTER)

SMBUS_SMC_1_S0_SCL

40 43 48 95

SMBUS_SMC_1_S0_SDA

40 43 48 95

95

SMBUS_SMC_1_S0_SCL

40 43 48

MAKE_BASE=TRUE

95

SMBUS_SMC_1_S0_SDA

40 43 48

MAKE_BASE=TRUE

R5360

1/20W

R5361

1K

1K

5%

5%

1/20W
MF

MF

201

201

2

2

CPU/DDR3/PCH/AIRFLOW TEMP

EMC1414-A: U5870

(Write: 0x98 Read: 0x99)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

40 43 48
95

40 43 48
95

X87 TEMP

TMP105: U5823

(WRITE: 0X92 READ: 0X93)

NO STUFF

1

1

R5321

8.2K

5%

5%

1/20W
MF

MF

201

201

2

2

R5323

0

5%

1/20W

MF

0201

R5322

0

5%

1/20W

MF

0201

21

21

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

40 43 48
95

40 43 48
95

6 3

DPMUX IC

U9100

(MASTER)

NC_I2C_DPMUX_A_SCL

43 82

NC_I2C_DPMUX_A_SDA

43 82 43 82

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

DPMUX IC

U9100

(MASTER)

I2C_DPMUX_UC_SCL

43 82

I2C_DPMUX_UC_SDA

43 82

R5334

2.0K

1/20W

1

5%

MF

201

2

NC_I2C_DPMUX_A_SCL

MAKE_BASE=TRUE

NC_I2C_DPMUX_A_SDA

MAKE_BASE=TRUE

1

R5335

2.0K

5%

1/20W

MF

201

2

I2C_DPMUX_UC_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SDA

MAKE_BASE=TRUE

SYNC_MASTER=CLEAN_X305G

PAGE TITLE

NO_TEST=TRUE

NO_TEST=TRUE

43 82

43 82

43 82

SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/11/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

53 OF 119

SHEET

43 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

C

EDP Current:21.6A

PPVIN_S5_HS_COMPUTING_ISNS

58 59 60 62 84

Power Drop across R5400 at EDP becomes 1.21W

PPBUS_G3H

30 44 47 56 57 63 65
84 86

DC-In Voltage Sense Enable & Filter

Q5410

DMC31D5UDJ

SOT963

D

D

N-CH

PPDCIN_G3H_ISOL

56 57 84

Enables DC-In VSense
divider when SUS present.

PM_SLP_SUS_L

12 66 67

IN

R5411

100K

1/16W
MF-LF

P-CH

G

5

S

4

2

G

S

1

1

1%

402

2

PDCINVSENS_EN_L_DIV

COMPUTING High Side Current Sense / Filter

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

3

V+

R5400

0612
MF-3

0.001

CRITICAL

432

ISNS_HS_COMPUTING_N

1

96

ISNS_HS_COMPUTING_P

96

1W
1%

Gain:100x

U5400

INA214

5

SC70

IN-

CRITICAL

4

IN+ REF

GND

2

3

DCIN_S5_VSENSE

6

DCINVSENS_EN_L

R5412

PLACE_NEAR=U5000.F1:5MM

6

HS_COMPUTING_IOUT

OUT

1

100K

1/16W
MF-LF

1

2

1%

402

C5401

0.1UF

20%
10V
CERM
402

1

2

R5413

R5414

1

2

1

30.9K

5.36K

R5409

20K

5%
1/16W
MF-LF
402

PLACE_NEAR=U5400.6:5MM

PLACE_NEAR=U5000.F1:5MM

1%

1/20W

Divider set for Vin max of 22.32V

MF

RTHEVENIN = 4567 Ohms

201

2

1

1

1%

1/20W

MF

201

2

PLACE_NEAR=U5000.B5:5MM

2

SMC_DCIN_VSENSE

PLACE_NEAR=U5000.F1:5MM

C5414

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

R5403

4.53K

21

SMC_CPU_HI_ISENSE

1%

1/20W

MF

1

201

2

SMC KEY VD0R

SMC_ADC3

OUT

40 41 44 45 46 47

SMC Key IC0R
SMC_ADC8

PLACE_NEAR=U5000.B5:5MM

C5403

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

40 42

40 42

OUT

40 41 44 45 46 47

PBUS Voltage Sense Enable & Filter

Enables PBUS VSense
divider when in S0.

PM_SLP_S3_R_L

31 32 67

IN

PPBUS_G3H

30 44 47 56 57 63 65 84 86

R5405

100K

1/16W
MF-LF

1

1%

402

2

CRITICAL

Q5400

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

2

1

5

4

PBUSVSENS_EN_L_DIV

G

P-CHANNEL

S

D

S

6

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

1

R5402

100K

1%
1/16W
MF-LF

402

2

R5401

R5404

PLACE_NEAR=U5000.A3:5MM

1

19.1K

1%

1/20W

PLACE_NEAR=U5000.A3:5MM

Divider set for Vin max of 13.98V

MF

RTHEVENIN = 4508 Ohms

201

2

SMC_PBUS_VSENSE

PLACE_NEAR=U5000.A3:5MM

1

1

5.90K

1/20W

C5404

0.22UF

1%

20%

6.3V

2

MF

X5R

201

0201

2

GND_SMC_AVSS

SMC Key VP0R

SMC_ADC5

40 42

OUT

40 41 44 45 46 47

D

C

B

EDP Current:5A

PPVIN_S5_HS_OTHER5V_ISNS

61 84

CRITICAL

PPBUS_G3H

30 44 47 56 57 63 65
84 86

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER

OTHERS (5V) High Side Current Sense / Filter

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

3

R5420

0612-6

0.005

432

96

MF
1W
1%

96

1

ISNS_HS_OTHER5V_N

ISNS_HS_OTHER5V_P

5

4

Gain:100x

V+

U5420

INA214

SC70

IN-

IN+ REF

CRITICAL

GND

2

OUT

6

1

C5422

1

0.1UF

20%
10V
CERM

2

402

HS_OTHER5V_IOUT

1

R5429

20K

5%
1/16W
MF-LF
402

2

PLACE_NEAR=U5420.6:5MM

SMC Key IO5R
SMC_ADC13

PLACE_NEAR=U5000.C2:5MM

R5426

4.53K

21

1%

1/20W

MF

201

SMC_OTHER5V_HI_ISENSE

PLACE_NEAR=U5000.C2:5MM

C5426

1

0.22UF

20%

6.3V
X5R

2

0201

GND_SMC_AVSS

40 41 44 45 46 47

EDP Current:5A

PPVIN_S5_HS_OTHER3V3_ISNS

61 84

40 42

OUT

PPBUS_G3H

30 44 47 56 57 63 65 84 86

DC-IN (AMON) Current Sense Filter

A

PLACE_NEAR=U5000.B3:5MM

R5441

45.3K

21

1%

1/20W

MF

201

From charger

57

IN

CHGR_BMON

R5423

45.3K

1%

1/20W

MF

201

21

PLACE_NEAR=U5000.A4:5MM

SMC_CHGR_BMON_ISENSE

C5421

1

0.022UF

10%

6.3V

PLACE_NEAR=U5000.A4:5MM

X5R-CERM

2

0201

GND_SMC_AVSS

IPBR

SMC_ADC7

40 41 44 45 46 47

EDP Current:4.6A

40 42

OUT

IN

CHGR_AMON

6 3

OTHERS (3.3V) High Side Current Sense / Filter

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

3

R5430

0612-6

0.005

CRITICAL

SMC_DCIN_ISENSE

PLACE_NEAR=U5000.B3:5MM

1

C5441

2200PF

10%
10V

2

X7R-CERM
0201

GND_SMC_AVSS

432

ISNS_HS_OTHER3V3_N

96

MF
1W
1%

ISNS_HS_OTHER3V3_P

96

1

SMC Key ID0R
SMC_ADC4

40 42 57

OUT

40 41 44 45 46 47

5

4

Gain:100x

V+

U5430

INA214

SC70

IN-

IN+ REF

CRITICAL

GND

2

OUT

6

1

C5431

1

0.1UF

20%
10V
CERM

2

402

HS_OTHER3V3_IOUT

1

R5439

20K

5%
1/16W
MF-LF
402

2

PLACE_NEAR=U5430.6:5MM

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

High Side Voltage and Current Sensing

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SMC Key IO3R
SMC_ADC9

PLACE_NEAR=U5000.A5:5MM

R5433

4.53K

21

1%

1/20W

MF

201

R

SMC_OTHER3V3_HI_ISENSE

PLACE_NEAR=U5000.A5:5MM

C5433

1

0.22UF

20%

6.3V
X5R

2

0201

GND_SMC_AVSS

40 41 44 45 46 47

Apple Inc.

40 42

OUT

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

54 OF 119

SHEET

44 OF 97

124578

SIZE

B

A

D

D

C

B

A

Sense Resistor 0.005 Ohm

EDP CURRENT: 5A

PP3V3_S0SW_SSD_R

66 84

PP3V3_S0SW_SSD

34 84
86

SENSE RESISTOR 0.010 OHM
EDP CURRENT: 0.94 A

66 67 81 84 85 86

PP3V3_S4

20 33 38 41
42 45 46 65

PP3V3_S4_TBT

28 29 30
84

8 7 6 5 4 3

NO_XNET_CONNECTION=TRUE

CRITICAL

R5549

0.005

0612-6

1%
1W
MF

21

96

CRITICAL

R5559

43

ISNS_SSD_P

ISNS_SSD_N

96

0.010

1%

1/2W

MF

1206-1

PP1V35_S3

PP1V35_S3_MEM

22 23 24 25 26 27 84 92

SENSOR_NONPROD:Y

R5505

5.23K

0.5%

1/16W

MF

402

R5508

5.23K

0.5%

1/16W

MF

402

R5500

5.23K

0.5%

1/16W

MF

402

R5570

5.23K

0.5%

1/16W

MF

402

R5571

5.23K

0.5%

1/16W

MF

402

R5572

5.23K

1/16W

DDR3L 1.35V DRAM ONLY CURRENT SENSE / FILTER

R5560

0.003

CRITICAL

0.5%

0612

21

21

21

MF

402

1%
1W

CYN

SSD CURRENT SENSE

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

R5504

6.04K

1/16W
MF-LF

402

R5561

6.04K

1/16W
MF-LF

402

21

ISNS_SSD_R_P

96

1%

21

ISNS_SSD_R_N

96

1%

1

R5562

1M

1%
1/16W
MF-LF
402

2

NO_XNET_CONNECTION=TRUE

1

3

R5563

1/16W
MF-LF

402

+

-

1M

21

1%

OMIT_TABLE

U5540
OPA333DCKG4

5

SC70-5

V+

4

V-

2

NO_XNET_CONNECTION=TRUE

ISNS_SSD_IOUT

TBT Router CURRENT SENSE

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

R5551

3.65K

ISNS_TBT_P

96

1

432

ISNS_TBT_N

96

1%

1/20W

MF

201

R5552

3.65K

1%

1/20W

MF

201

21

21

ISNS_TBT_R_P

ISNS_TBT_R_N

1

R5553

1M

1%
1/20W
MF
201

2

1

+

3

-

R5501

1M

1%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

GAIN: 165.56X

OMIT_TABLE

U5500

OPA333DCKG4

5

SC70-5

V+

V-

2

21

1

C5558

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U5000.B4:7MM

4

ISNS_TBT_IOUT

GAIN: 274X

R5564

4.53K

21

1%

1/20W

MF

201

1

C5551

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U5000.A8:5MM

SMC_SSD_ISENSE

1

C5540

0.22UF

20%

6.3V

2

X5R
0201

R5502

4.53K

1%

1/20W

MF

201

IHDC

SMC_ADC6

40 42

OUT

PLACE_NEAR=U5000.B4:5MM

GND_SMC_AVSS

21

40 41 44 45 46 47

SMC_TBT_ISENSE

1

2

IHSC

SMC_ADC23

OUT

PLACE_NEAR=U5000.A8:5MM

C5500

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

PLACE_NEAR=R7310.3:5MM

59 96

IN

PLACE_NEAR=R7320.3:5MM

59 96

IN

PLACE_NEAR=R7330.3:5MM

59 96

IN

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7310.4:5MM

59 96

IN

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

PLACE_NEAR=R7320.4:5MM

SENSOR_NONPROD:Y

59 96

IN

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7330.4:5MM

59 96

IN

NO_XNET_CONNECTION=TRUE

40 42

EDP CURRENT:8A

40 41 44 45 46 47

CPUVR_ISNS1_P

CPUVR_ISNS2_P

SENSOR_NONPROD:Y

CPUVR_ISNS3_P

CPUVR_ISNS1_N

CPUVR_ISNS2_N

SENSOR_NONPROD:Y

CPUVR_ISNS3_N

21 60 66 84 86

CPU PKG Load Side Current Sense / Filter

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

R5503

CPUVR_ISNS_P

96

SENSOR_NONPROD:Y

21

CPUVR_ISNS_N

21

21

1

96

96

432

ISNS_1V35_MEM_P

ISNS_1V35_MEM_N

3.57K

1%
1/16W
MF-LF

402

R5507

3.57K

1%
1/16W
MF-LF

402

NO_XNET_CONNECTION=TRUE

Individual Sense R is 0.75mOhm

EDP: 95A TDP :45A

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

CPU Vcore Voltage Sense / Filter

VC0C

SMC_ADC0

40 42

OUT

40 41 44 45 46 47

R5518

ISNS_TPAD_IOUT_FDBK

10K

1/20W

1%

MF

201

CRITICAL

U5511

OPA340NA

5

3

+

SOT-23

V+

1

SMC_TPAD_ISENSE_R

1

R5519

10K

1%
1/20W
MF
201

2

V-

4

-

2

Total Gain: 24.9 x 2 = 49.8x

Sense Resistor R7640 0.001 Ohm on PCH regulator page

P1V05S0_CS_P

62 96

IN

P1V05S0_CS_N

62 96

IN

21

ITPC

PLACE_NEAR=U5000.F2:5MM

R5514

4.53K

21

SMC_TPAD_ISENSE

1%

1/20W

MF

201

SMC_AD2

1

C5514

0.22UF

20%

6.3V

2

X5R

PLACE_NEAR=U5000.F2:5MM

0201

GND_SMC_AVSS

40 42

OUT

40 41 44 45 46 47

EDP CURRENT: 5A

PART NUMBER

353S00107

R5591

3.0K

0.1%

1/20W

MF

0201

R5592

3.0K

0.1%

1/20W

MF

0201

21

21

ISNS_PCH_R_P

96

ISNS_PCH_R_N

96

QTY

3

IC,OPAMP,NCS333QS3,SC70-5

PPVCC_S0_CPU

6 8

10 59 84 86

Gain: 24.9x, EDP: 2.61 A (Transient)
Rsense: 0.02 (R5510)
Vsense: 52.2 mV, Range: 5 A

PPBUS_S4_TPAD

65 84

IN

PLACE_NEAR=U5510.3:3MM

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

C5510

0.1UF

PLACE_NEAR=R7310.2:5 MM

ISNS_TPAD_P ISNS_TPAD_N

96 96

1

20%
10V

CERM

2

402

BYPASS=U5510.5::5MM

Gain: 1000uA/V * 24.9kOhm = 24.9x

XW5520

SM

21

CPUVSENSE_IN

PLACE_NEAR=U5000.E2:7MM

CRITICAL

R5510

0.02

1%
1W
MF

0612-2

21

PPVIN_S4_TPAD

43

PLACE_NEAR=U5510.4:3MM

43

VIN+ VIN-

U5510

INA139

SOT23-5

5 1

V+

OUT

CRITICAL

GND

2

R5520

4.53K

21

SMC_CPUPKG_VSENSE

PLACE_NEAR=U5000.E2:5MM

1

C5520

0.22UF

20%

6.3V

2

X5R
0201

1/20W

1%

MF
201

GND_SMC_AVSS

TRACKPAD CURRENT SENSE

20 33 38 41 42 45 46 65 66 67
81 84 85 86

BYPASS=U5511.5::5MM

1

R5511

2

PP3V3_S4

C5511

0.1UF

20%
10V

CERM

402

38 84 86

OUT

ISNS_TPAD_IOUT_BUF

24.9K

1%
1/16W
MF-LF
402

1

2

6 3

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

21

CPUVR_ISUM_R_P

96

21

CPUVR_ISUM_R_N

96

SENSOR_NONPROD:Y

1

R5554

732K

1%
1/16W
MF-LF
402

2

R5573

7.32K

1/16W
MF-LF

402

R5574

7.32K

1/16W
MF-LF

402

21

96

1%

21

ISNS_1V35_MEM_R_N

96

1%

13 20 21 43 46 66 81 82 84 86

ISNS_1V35_MEM_R_P

1

3

SENSOR_NONPROD:Y

PP3V3_S3

1

R5575

1M

1%
1/16W
MF-LF
402

2

+

-

R5555

732K

1%
1/16W
MF-LF

402

58

NO_XNET_CONNECTION=TRUE

PCH CORE CURRENT SENSE

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

GAIN: 333X

1

R5593

1M

1%
1/16W
MF-LF
402

2

NO_XNET_CONNECTION=TRUE

DESCRIPTION

5

1

+

V+

V-

3

-

2

R5594

1M

1%
1/16W
MF-LF

402

NO_XNET_CONNECTION=TRUE

1

2

U5590
OPA333DCKG4

SC70-5

4

ISNS_PCH_IOUT

21

REFERENCE DES

U5500,U5540,U5590

C5590

OMIT_TABLE

SENSOR_NONPROD:Y

CRITICAL

U5550

OPA333DCKG4

5

SC70-5

V+

4

V-

2

21

NO_XNET_CONNECTION=TRUE

CPUVR_ISUM_IOUT

Gain:137.77x

Scale: 29.03A / V
Max VOut: 3.3V at 95.8A

NOSTUFF

CPUVR_IMON

IN

PLACE_NEAR=U7200.3:5MM

U5560

OPA333DCKG4

5

1

+

SC70-5

V+

4

V-

3

-

2

R5576

1M

21

1%
1/16W
MF-LF

402

0.1UF

20%
10V
CERM
402

R5595

4.53K

21

1%

1/20W

MF

201

PLACE_NEAR=U5000.H2:7MM

CRITICAL

CRITICAL

SENSOR_NONPROD:Y

PLACE_NEAR=U5550.5:3MM

1

C5550

0.1UF

20%
10V

2

X7R-CERM
0402

SENSOR_NONPROD:Y

R5506

4.53K

21

1%

1/20W

MF

PLACE_NEAR=U5000.E1:5MM

201

SMC_CPUPKG_ISENSE

1

C5501

2

GND_SMC_AVSS

R5530

0

21

5%

1/20W

MF

0201

1

C5560

0.1UF

20%
10V

2

X7R-CERM
0402

IM0C

SMC_ADC10

R5577

4.53K

1/20W

21

1%

MF

201

ISENSE_P1V35MEM_IOUT

PLACE_NEAR=U5000.B6:7mm

GAIN:136.6X

IC1C

SMC_ADC19

SMC_PCH_CORE_ISENSE

1

C5591

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.H2:5MM

GND_SMC_AVSS

SYNC_MASTER=CLEAN_X425G

PAGE TITLE

Load Side Voltage and Current Sensing

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

40 42

40 41 44 45 46 47

BOM OPTION

Apple Inc.

R

12

IC0C

SMC_ADC1

PLACE_NEAR=U5000.E1:5MM

SENSOR_NONPROD:Y

0.22UF

20%

6.3V
X5R
0201

40 41 44 45 46 47

SMC_P1V35MEM_ISENSE

PLACE_NEAR=U5000.B6:5mm

1

C5577

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

SYNC_DATE=09/10/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

55 OF 119

SHEET

45 OF 97

124578

OUT

OUT

40 41 44 45 46 47

40 42

40 42

SIZE

D

D

C

B

A

8 7 6 5 4 3

Vinafix.com

12

X87 AIRPORT CURRENT SENSE

PP3V3_S4

20 33 38 41 42 45 65 66 67 81
84 85 86

Sense Resistor 0.005 Ohm
EDP Current: 1.06A

D

C

PP3V3_WLAN_R

33

CRITICAL

PP3V3_WLAN_F

33

MF

1W

1%

0.005

R5635

ISNS_AIRPORTP

0612-6

4 3

2 1

ISNS_AIRPORTN

PART NUMBER

117S0008

CPU DDR CURRENT SENSE

EDP CURRENT: 4.2A

SENSOR_NONPROD:Y

ISNS_CPUDDR_P

66 96

IN

ISNS_CPUDDR_N

66 96

IN

SENSOR_NONPROD:Y

SENSOR_NONPROD:Y

R5630

R5631

R5681

3.16K

1%

1/20W

MF

201

R5682

3.16K

1%

1/20W

MF

201

SENSOR_NONPROD:Y

620

21

ISNS_AIRPORT_R_P

96

1%

1/20W

MF

201

620

21

ISNS_AIRPORT_R_N

96

SENSOR_NONPROD:Y

1%

1/20W

MF

201

QTY

5

DESCRIPTION

RES,MTL FILM,100K,5,1/20W,0201,SMD,LF

PP3V3_S3

13 20 21 43 45 46 66 81 82 84
86

SENSOR_NONPROD:Y

21

ISNS_CPU_DDR_R_P

96

21

ISNS_CPU_DDR_R_N

96

1

R5683

1M

1%

1/20W

MF
201

2

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

1

R5632

510K

1%

1/20W

MF
201

2

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

5

1

+

V+

V-

3

­2

R5684

1M

NO_XNET_CONNECTION=TRUE

21

1%

1/20W

MF

201

SENSOR_NONPROD:Y

5

1

+

V+

V-

3

­2

GAIN: 822X

R5633

NO_XNET_CONNECTION=TRUE

510K

21

SENSOR_NONPROD:Y

1%

1/20W

MF

201

REFERENCE DES

C5601,C5631,C5600,C5681,C5671

SENSOR_NONPROD:Y

1

C5682

0.1UF

20%

10V

2

CERM

U5682

OPA333DCKG4

SC70-5

4

402

ISNS_CPU_DDR_IOUT

Gain: 316x

U5630

OPA333DCKG4

SC70-5

4

B

SENSOR_NONPROD:Y

1

C5630

0.1UF

10%

6.3V

2

CERM-X5R
0201

SENSOR_NONPROD:Y

ISNS_AIRPORT_IOUT

PLACE_NEAR=U5000.B8:7MM

R5685

4.53K

1%

1/20W

MF

201

BOM OPTION

SENSOR_NONPROD:N

21

CRITICAL

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.A6:7MM

R5634

4.53K

21

SMC_X87_ISENSE

1%

1/20W

201

MF

1

2

IC3C

SMC_ADC11

SMC_CPUDDR_ISENSE

SENSOR_NONPROD:Y

1

C5681

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

IAPC

SMC_ADC22

SENSOR_NONPROD:Y

C5631

0.22UF

20%

6.3V

PLACE_NEAR=U5000.B8:7MM

X5R
0201

GND_SMC_AVSS

40 42

OUT

PLACE_NEAR=U5000.A6:5MM

40 41 44 45 46 47

40 42

OUT

40 41 44 45 46 47

LCD PANEL CURRENT SENSE

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

EDP CURRENT: 1.0A

ISNS_LCD_PANEL_N

69 96

IN

ISNS_LCD_PANEL_P

69 96

IN

5

4

3

SENSOR_NONPROD:Y

V+

U5670

INA214

SC70

IN-

IN+ REF

GND

2

OUT

GAIN: 100X

SENSOR_NONPROD:Y

1

C5670

0.1UF

20%

10V

2

CERM
402

6

LCD_PANEL_IOUT

1

1

R5678

20K

5%
1/20W
MF
201

2

SENSOR_NONPROD:Y

PLACE_NEAR=U5670.6:5MM

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.C1:7MM

R5671

4.53K

21

1/20W

201

1%
MF

SMC_LCDPANEL_ISENSE

SENSOR_NONPROD:Y

1

C5671

0.22UF

20%

6.3V

2

X5R
0201

ILDC

SMC_ADC12

PLACE_NEAR=U5000.C1:7MM

GND_SMC_AVSS

40 42

OUT

40 41 44 45 46 47

D

C

B

A

S2 CAMERA CONTROLLER CURRENT SENSE

ICMC removed due to lack of channel on SMC

R5676

0

S2_PWR:S3

PP3V3_S3

13 20 21 43 45 46 66 81 82 84
86

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

MF-LF

MF-LF 1/16W

5%

1/16W

R5677

0

5%

21

402

S2_PWR:S0

21

402

PP3V3_S3RS0_CAMERA_R

2

XW5675

SM

Use 1206 package

1

PP3V3_S3RS0_CAMERA

13 20 35 84

SENSE RESISTOR 0.003 OHM
EDP CURRENT: 5A

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

6 3

SIZE

A

D

SYNC_MASTER=CLEAN_X305

PAGE TITLE

Debug Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/14/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

56 OF 119

SHEET

46 OF 97

124578

.

8 7 6 5 4 3

12

GPU FB Current Sense

55 66 67 68 69 82 83 84 86

GPUFB_CS_R_P

96

GPUFB_CS_R_N

96

1

R5772

1M

1%
1/16W
MF-LF
402

2

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

NO_XNET_CONNECTION=TRUE

1

3

R5773

1/16W
MF-LF

1

C5770

0.1UF

20%
10V

2

CERM
402

U5770

OPA333DCKG4

5

+

SC70-5

V+

4

V-

-

2

1M

21

1%

402

PLACE_NEAR=U5000.H2:5mm

SMC_GPU_FB_R

Gain: 100x

R5774

4.53K

1%

1/20W

MF

201

21

SMC_GPU_FB_ISENSE

1

C5771

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

IGMC

SMC_ADC20

OUT

PLACE_NEAR=U5000.H2:5mm

40 41 44 45 46 47

40 42

D

GRAPHICS High Side Current Sense

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

EDP Current: 13.9A

PPVIN_S5_HS_GPU_ISNS

73 79 80 84

D

OUT

PPBUS_G3H

30 44 56 57 63 65 84 86

IN

CRITICAL

R5701

0.002

1

ISNS_HS_GPU_N

96

0612

CYN

1W

ISNS_HS_GPU_P

96

1%

432

5

4

Gain:100x

3
V+

U5710

INA214

SC70

IN-

IN+ REF

CRITICAL

GND

2

OUT

C5711

1

0.1UF

20%
10V
CERM

2

402

6

HS_GPU_IOUT

1

PLACE_NEAR=U5000.F2:5mm

R5719

1

R5709

20K

5%
1/16W
MF-LF
402

2

4.53K

1%

1/20W

MF

201

21

IG0R

SMC_ADC14

SMC_GPU_HI_ISENSE

PLACE_NEAR=U5000.F2:5mm

C5719

1

0.22UF

20%

6.3V
X5R

2

0201

GND_SMC_AVSS

40 41 44 45 46 47

40 42

OUT

EDP Current: 13.5A

GPUFB_CS_P

73 96

GPUFB_CS_N

73 96

NO_XNET_CONNECTION=TRUE

R5770

1/20W

R5771

1/20W

10K

21

1%

MF

201

10K

21

1%

MF

201

GPU VCORE Voltage Sense

VG0C

SMC_ADC16

OUT

40 41 44 45 46 47

40 42

PP1V35_GPU_REG

71 72 73 74 75 84

XW5790

SM

PPVCORE_GPU

71 79 84

XW5735

SM

21

GPUVSENSE_IN

PLACE_NEAR=U5000.B3:5mm

R5735

4.53K

21

1%

1/20W

MF
201

SMC_GPUCORE_VSENSE

PLACE_NEAR=U5000.B3:5mm

1

C5735

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

C

GPU VCORE Current Sense

82 83 84
52 55 66
45 46 47
19 20 29

PP3V3_S0

11 12 13
14 15 17
34 43 44
48 49 51
67 68 69
86 96

GFXIMVP6_IMON

79

IN

EDP Current:49.5A

Vimon=3xIo*(0.2/R8915)*R8912

B

EDP Current: 7.317A

A

GPUVCORE_INV

SENSOR_NONPROD:Y

1

R5700

499K

1%
1/16W
MF-LF
402

2

SENSOR_GPU_NONPROD:Y

ISNS_PP0V95_S0GPU_P

73 96

ISNS_PP0V95_S0GPU_N

73 96

SENSOR_GPU_NONPROD:Y

NO_XNET_CONNECTION=TRUE

1

3

NO_XNET_CONNECTION=TRUE

R5740

7.15K

1/20W

201

R5741

7.15K

1%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U5700.1:5mm

R5710

0

5%

1/20W

MF

0201

OPAMP_OPA333_NONINV

SENSOR_NONPROD:Y

U5700

OPA333DCKG4

SC70-5

5

+

V+

4

V-

-

2

SENSOR_NONPROD:Y

R5717

1M

21

1%
1/16W
MF-LF

402

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

21

ISNS_PP0V95_S0GPU_R_P

96

1%

MF

21

ISNS_PP0V95_S0GPU_R_N

96

SENSOR_GPU_NONPROD:Y

1

R5742

1M

1%
1/16W
MF-LF
402

2

21

NO_XNET_CONNECTION=TRUE

GPUVCORE_IOUT

47

SENSOR_NONPROD:Y

CRITICAL

1

C5710

0.1UF

20%
10V

2

CERM
402

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.B2:5mm

R5718

4.53K

1/20W

Gain: 3.004x

GPU 0V95 Current Sense

PP3V3_S0

SENSOR_GPU_NONPROD:Y

U5740

OPA333DCKG4

5

1

+

SC70-5

V+

4

V-

3

-

2

SENSOR_GPU_NONPROD:Y

R5743

1M

21

1%

1/16W

NO_XNET_CONNECTION=TRUE

MF-LF

402

Gain: 139.86x

21

1%

MF

201

0V95_GPU_IOUT

SENSOR_NONPROD:Y

1

C5718

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

SENSOR_GPU_NONPROD:Y

1

C5743

0.1UF

20%
10V

2

X7R-CERM
0402

SENSOR_GPU_NONPROD:Y

R5744

4.53K

1%

1/20W

MF

PLACE_NEAR=U5000.G2:5MM

201

SMC_GPUCORE_ISENSE

PLACE_NEAR=U5000.B2:5mm

21

SMC_GPU0V95_ISENSE

SENSOR_GPU_NONPROD:Y

1

C5742

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

40 41 44 45 46 47

IG3C

SMC_ADC18

PLACE_NEAR=U5000.G2:5MM

40 41 44 45 46 47

IG0C

SMC_ADC15

OUT

40 42

40 42

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

80 96

80 96

C5750

0402-1

EDP Current: 13.5A

VDDCIS0_CS_P

VDDCIS0_CS_N

1

1UF

10%
25V

2

X5R

SENSOR_GPU_NONPROD:Y

R5795

8.06K

1/20W

SENSOR_GPU_NONPROD:Y

R5796

8.06K

1/20W

SENSOR_GPU_NONPROD:Y

NO_XNET_CONNECTION=TRUE

GPU VR OCP

U5750

REF3030

SOT23-3

1

IN

CRITICAL

2

OUT

GND

3

C5751

0.1UF

CERM-X5R

47

TRIP POINT: 61A

6.3V
0201

GPUVCORE_IOUT

1%

MF

201

1%

MF

201

10%

6 3

GPU FB Voltage Sense

PLACE_NEAR=U5000.H1:5mm

21

GPU_FB_VSENSE_IN

VDDCI Current Sense

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

VDDCIS0_CS_R_P

96

21

VDDCIS0_CS_R_N

96

21

1

R5793

1M

1%
1/16W
MF-LF
402

2

NO_XNET_CONNECTION=TRUE

SENSOR_GPU_NONPROD:Y

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

P3V0_GPU_VREF

R5752

40.2K

1/20W

201

IWARN_FB

21

1%

1

MF

2

1

2

R5790

4.53K

21

1/20W

1%

MF

201

PLACE_NEAR=U5000.H1:5mm

1

C5790

0.22UF

20%

6.3V

2

X5R
0201

SENSOR_GPU_NONPROD:Y

5

1

+

V+

V-

3

-

2

R5794

1M

21

1%
1/16W
MF-LF

402

U5760

LMV7275MG/NOPB

R5753

324K

1%

1/20W
MF
201

R5761

VG1C

SMC_ADC21

SMC_GPU_FB_VSENSE

GND_SMC_AVSS

SENSOR_GPU_NONPROD:Y

1

C5792

0.1UF

20%
10V

2

CERM
402

U5790

OPA333DCKG4

SC70-5

4

VDDCI_GPU_IOUT

OUT

40 41 44 45 46 47

PLACE_NEAR=U5000.A7:5mm

SENSOR_GPU_NONPROD:Y

R5791

4.53K

1%

1/20W

MF

201

Gain: 124.07x

1

C5760

10%

6.3V

0.1UF

0201

CERM-X5R

2

5

1

3

1/20W

SC70-5

V+

GND

2

CRITICAL

1M

GPU_VCORE_OC_L

21
1%
MF

201

SYNC_MASTER=J45G_AMD

PAGE TITLE

0

4

5%

1/20W

MF

201

R5762

GPU V/I Sensors

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

40 42

21

SMC_GPU_VDDCI_ISENSE

SENSOR_GPU_NONPROD:Y

PLACE_NEAR=U5000.A7:5mm

1

C5791

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

NO STUFF

1

R5763

2.2K

5%
1/20W
MF
201

2

GPUCORE_VR_ICCWARN_BUF_L

21

10%

6.3V
0201

Apple Inc.

IG2C

SMC_ADC17

40 42

40 41 44 45 46 47

NO STUFF

1

C5761

0.1UF

CERM-X5R

2

SYNC_DATE=07/01/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

77

OUT

<E4LABEL>

<BRANCH>

57 OF 119

47 OF 97

SIZE

C

B

A

D

.

8 7 6 5 4 3

12

GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK

R5850

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

76 96

BI

D

CRITICAL

Placement note:

PLACE Q5801 ON TOP SIDE
CLOSE TO THE LEFT FIN STACK

Q5801

BC846BMXXH

SOT732-3

2

1

Th2H

PLACE_NEAR=Q5803.3:2mm

3

LEFT FIN STACK TEMPERATURE

C5803

47PF

0201

NOSTUFF

CRITICAL

1

5%

25V

2

C0G

Q5803

BC846BMXXH

SOT732-3

Th1H

PLACE Q5803 ON BOTTOM SIDE NEAR RIGHT FIN STACK

Placement note:

TG0D

GPU DIE TEMPERATURE

76 96

BI

GPUTHMSNS_D_P

3

1

2

RIGHT FIN STACK TEMPERATURE

96

GPUTHMSNS_D_N

96

47

5%
1/16W
MF-LF

402

GPU_TDIODE_P

NO_XNET_CONNECTION=TRUE

GPU_TDIODE_N

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5850.5:5mm

21

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PLACE_NEAR=U5850.2:5mm

PLACE_NEAR=U5850.3:5mm

1

C5851

0.0022uF

10%
50V

2

CERM

402

1

C5852

0.0022uF

10%
50V

2

CERM

402

PLACE_NEAR=U5850.4:5mm

1

VDD

U5850

EMC1414-A-AIA

2

3 8

4

5

DFN

DP1

THERM*/ADDR

DN1

DP2/DN3

DN2/DP3

ALERT*

SMDATA

SMCLK

THRM_PAD

GND

11

6

R5851 10K gives:
Write Address: 0x98
Read Address: 0x99

1

C5850

0.1UF

20%
10V

2

X7R-CERM
0402

7

GPUTHMSNS_THM_L

R5851

10K

1/20W

201

1

5%
MF

2

GPUTHMSNS_ALERT_L

9

SMBUS_SMC_0_S0_SDA

10

SMBUS_SMC_0_S0_SCL

Placement note:

PLACE U5850 ON TOP SIDE UNDER THE GPU

1

R5852

10K

5%
1/20W
MF
201

2

BI

IN

D

36 40 43 69 76 85 86 95

36 40 43 69 76 85 86 95

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

R5870

C

TM0P

DDR3 PROXIMITY TEMPERATURE

CRITICAL

Placement note:

PLACE Q5803 ON TOP SIDE NEAR DDR3

AIRFLOW PROXIMITY TEMPERATURE

Ta0P

CRITICAL

Q5802

BC846BMXXH

SOT732-3

Placement note:

B

PLACE Q5802 ON TOP SIDE
CLOSE TO BOARD EDGE

2

1

3

Q5806

BC846BMXXH

SOT732-3

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

DDR3THMSNS_D1_P

96

3

1

2

DDR3THMSNS_D1_N

96

CRITICAL

Q5804

BC846BMXXH

SOT732-3

PCH PROXIMITY TEMPERATURE

TP0P

Placement note:

PLACE Q5804 ON TOP SIDE UNDER PCH

PLACE_NEAR=U5870.2:5mm

PLACE_NEAR=U5870.3:5mm

NO_XNET_CONNECTION=TRUE

3

1

2

47

21

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=3.3V

MF-LF

402

C5871

0.0022uF

CERM

CPUTHMSNS_D2_P

96

NO_XNET_CONNECTION=TRUE

0.0022uF

CPUTHMSNS_D2_N

96

PLACE_NEAR=U5870.4:5mm
PLACE_NEAR=U5870.5:5mm

PP3V3_S0_CPUTHMSNS_R

2

1

10%
50V

2

402

C5890

CERM

10%
50V

402

1

2

3 8

4

5

1

VDD

U5870

EMC1414-A-AIA

DFN

DP1

THERM*/ADDR

DN1

DP2/DN3

DN2/DP3

THRM_PAD

GND

11

6

Write Address: 0x98
Read Address: 0x99

1

C5870

0.1UF

20%
10V

2

X7R-CERM
0402

7

CPUTHMSNS_THM_L

ALERT*

SMDATA

SMCLK

CPUTHMSNS_ALERT_L

9

SMBUS_SMC_1_S0_SDA

10

SMBUS_SMC_1_S0_SCL

TC0P

CPU PROXIMITY TEMPERATURE

Placement note:

PLACE U5870 ON TOP SIDE UNDER CPU

R5871 10K gives:

R5871

10K

1/16W
MF-LF

402

1

1

R5872

10K

5%

5%
1/16W
MF-LF
402

2

2

40 43 48 95

BI

40 43 48 95

IN

C

B

X87 PROXIMITY

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

PLACE_NEAR=J3501:5MM

PLACE_SIDE=BOTTOM

TW0P

SMBUS_SMC_1_S0_SDA

40 43 48 95

BI

SMBUS_SMC_1_S0_SCL

40 43 48 95

BI

A

Placement note:

PLACE U5823 ON BOTTOM NEAR X87 CONN

HPA00330AI

6

SDA

1

SCL

5

V+

U5823

SOT563

CRITICAL

GND

2

ADD0

ALERT

6 3

4

3

X87THMSNS_A0

NC

1

2

1

C5823

R5822

0.1uF
10K

20%

5%

10V

1/16W

CERM

MF-LF

402

402

2

WRITE ADDRESS: 0X92
READ ADDRESS: 0X93

THSP

TBT_THERMDP

28 48 96

BI

PLACE_NEAR=U2800.AC6:2mm

XW5820

Use GND pin B1 on U2800 for N leg

21

SM

TBT DIE

TBT_THERMDP

28 48 96

MAKE_BASE=TRUE

TBT_THERMDN

96

PLACE_SIDE=TOP

NOSTUFF

1

R5820

10K

5%
1/16W
MF-LF
402

2

SYNC_MASTER=CHANG_J45

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

58 OF 119

SHEET

48 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

Left Fan

C

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

SMC_FAN_0_TACH

40

OUT

PP3V3_S3_FAN_CTL

49 85

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

SMC_FAN_0_CTL

40

IN

R6051

100K

1/20W

201

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52

1

R6050

47K

5%
1/16W
MF-LF

402

R6055

47K

21

FAN_LT_TACH

86

5%
1/16W
MF-LF

1

5%
MF

2

5

G

4

S

VER 1

402

Q6060

DMN5L06VK-7

SOT563

86

3

D

FAN_LT_PWM

2

CRITICAL

J6050

FF14A-5C-R11DL-B-3H

F-RT-SM
6

NC

1
2
3
4
5

NC NC

7

NC

518S0769

96

SMC_FAN_1_TACH

40

OUT

PP3V3_S3_FAN_CTL

49 85

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

SMC_FAN_1_CTL

40

IN

R6061

100K

1/20W

201

1

5%
MF

2

1

Right Fan

2

G

S

VER 1

R6065

47K

5%
1/16W
MF-LF

402

Q6060

DMN5L06VK-7

SOT563

FAN_RT_PWM

86

6

D

21

FAN_RT_TACH

86

R6060

47K

1/16W
MF-LF

402

1

5%

2

CRITICAL

J6060

FF14A-5C-R11DL-B-3H

F-RT-SM
6

NC

1
2
3
4
5

7

NC

518S0769

D

C

R6071

0

21

5%
1/16W
MF-LF

B

402

NOSTUFF

A

6 3

R6072

0

5%
1/16W
MF-LF

402

NOSTUFF

21

B

SIZE

A

D

SYNC_MASTER=J15_MLB

PAGE TITLE

Fan Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

60 OF 119

SHEET

49 OF 97

124578

8 7 6 5 4 3

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported.
SPI Frequency: 50MHz for CPU, 20MHz for SMC.

PP3V3_SUS

11 12 13 14 15 17 64 66 67 84

BYPASS=U6101::3mm

OE*

1

2

7

1

C6101

0.1UF

10%
16V
X5R-CERM
0201

SPI_MLBROM_CS_L

PLACE_NEAR=U6100.1:12MM

BYPASS=U6100::3mm

SPI_MLB_CLK

50 91

SPI_MLB_IO2_WP_L

50 91

SPI_MLB_IO3_HOLD_L

50 91

C6100

0.1UF

X5R-CERM

0201

10%
16V

1

2

6

1

3

7

8

CRITICAL

VCC

U6100

W25Q64FVZPIG

64MBIT

WSON

CLK

OMIT_TABLE

CS*

IO2

WP*(IO2)
HOLD*(IO3)

GND

4

IO3

THRM_PAD

DI(IO0)

DO(IO1)

9

IO0

5

IO1

2

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

50 91

50 91

19 34 37 38 40 41 42 43 56 57
67 84 86

50 91 50 91

50 91

50 91

50 91

40 41 57 86

D

8

VCC

U6101

74LVC1G99

2

SOT833

A Y

SPI_MLB_CS_L

50 91

SPIROM_USE_MLB

14 50 86

3

B

CRITICAL

5

C

6

D

GND

4

SPI+SWD SAM Connector

SAMCONN

CRITICAL

J6100

DF40PC-12DP-0.4V-51

M-ST-SM

PP3V42_G3H

SPI_MLB_IO0_MOSI
SPI_MLB_IO1_MISO
SPI_MLB_IO2_WP_L
SPI_MLB_IO3_HOLD_L

SMC_RESET_L

14 13

2
4 3
6 5

8 7
10
12 11

16

1

9

15

SPI_MLB_CLK
SPI_MLB_CS_L

SPIROM_USE_MLB
SMC_TMS
SMC_TCK

(SWDIO)
(SWCLK)

50 91

OUTOUT

14 50 86

BI

40 41 86

BI

40 41 86

12

D

516S00024

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles
in normal and Dual-IO modes.

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

C

C

SPI Bus Series Termination

SPI_MLB_IO3_HOLD_L
SPI_MLB_IO2_WP_L
SPI_MLB_IO1_MISO
SPI_MLB_IO0_MOSI
SPI_MLB_CLK
SPI_MLB_CS_L

R6110

11

SPI_CS0_R_L

13 91

IN

SPI_CLK_R

13 91

IN

B

A

PCH Master

SMC12 Master

13 91

BI

13 91

BI

13 91

BI

13 91

BI

PLACE_NEAR=U1100.AJ11:50MM

SPI_MOSI_R

(SPI_IO<0>)

SPI_MISO

PLACE_NEAR=U1100.AH3:50MM

(SPI_IO<1>)

SPI_IO<2>

SPI_IO<3>

PLACE_NEAR=U1100.AJ2:50MM

OVER/UNDER-SHOOT WAS OBSERVED ON IO2 AND IO3.
0HOM WERE ADDED FOR R6118&R6119 AS PLACEHOLDER.
FINAL VALUE NEEDS TO BE TUNED.

40 91

OUT

40 91

IN

40 91

IN

40 91

IN

PLACE_NEAR=U1100.AJ7:50MM

PLACE_NEAR=U1100.AH1:50MM

PLACE_NEAR=U1100.AJ4:50MM

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L

R6111

11

5%

1/20W

MF

201

R6113

11

5%

1/20W

MF

201

R6119

11

5%

1/20W

MF

201

NOSTUFF

R6114

0

5%

1/20W

MF

0201

21

21

21

21

PLACE_NEAR=U5000.M9:12MM

21

5%

1/20W

MF

201

R6112

11

21

5%

1/20W

MF

201

R6118

11

21

5%

1/20W

MF

201

NOSTUFF

R6115

0

21

PLACE_NEAR=U5000.N9:12MM

5%

1/20W

MF

0201

SPI_CS0_L

91

SPI_CLK

91

SPI_MOSI

91

SPI_MISO_R

91

SPI_IO2_R

SPI_IO3_R

NOSTUFF

R6116

0

5%

1/20W

MF

0201

21

PLACE_NEAR=U5000.L10:12MM

NOSTUFF

R6117

0

21

PLACE_NEAR=U5000.K10:12MM

5%

1/20W

MF

0201

R6121

R6123

R6120

1/20W

201

33

21

PLACE_NEAR=U6100.6:12MM

1%

1/20W

MF

R6122

201

1/20W

201

33

21

PLACE_NEAR=U6100.2:12MM

1%

1/20W

MF

201

R6131

33

21

1%

1/20W

MF

201

33

21

PLACE_NEAR=U6100.1:12MM

1%
MF

33

21

PLACE_NEAR=U6100.5:12MM

1%
MF

R6130

33

21

PLACE_NEAR=U6100.3:12MM

1%

1/20W

MF

201

PLACE_NEAR=U6100.7:12MM

SPI_MLB_CS_L

MAKE_BASE=TRUE

SPI_MLB_CLK

MAKE_BASE=TRUE

SPI_MLB_IO0_MOSI

MAKE_BASE=TRUE

SPI_MLB_IO1_MISO

MAKE_BASE=TRUE

SPI_MLB_IO2_WP_L

MAKE_BASE=TRUE

SPI_MLB_IO3_HOLD_L

MAKE_BASE=TRUE

SYNC_MASTER=CLEAN_X425

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

50 91

50 91

50 91

Sam Card ROM Slave

50 91

50 91

50 91

50 91

OUT

50 91

OUT

50 91

BI

SPI ROM Slave

50 91

BI

50 91

BI

50 91

BI

SYNC_DATE=08/15/2014

SPI Debug Connector

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

61 OF 119

SHEET

50 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

AUDIO CODEC, ANALOG BLOCKS

APPLE P/N 353S4080

PP3V3_S0_AUDIO_ANALOG

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

D

BYPASS=U6201.H12:L10:5 mm

CRITICAL

C6219

15UF

21

20%

4V

X5R

0402

CODEC_FLYP

CODEC_FLYN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

BYPASS=U6201.A8:B10:5 mm

CRITICAL

C6222

15UF

0402

51 55

1

20%

4V

2

X5R

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.07MM

51 55

TP_AUD_CODEC_MICBIAS1_L

TP_AUD_CODEC_MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

TP_AUD_CODEC_MICBIAS2_R

C

GND_AUDIO_CODEC

51 55

GND_AUDIO_CODEC

51 55

R6206

2.21K

21

1%

1/20W

MF

201

C6220

1UF

21

10%
25V
X5R
402

B

CRITICAL

BYPASS=U6201.H12:H13:5 mm

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

C6226

0.1UF

10%
16V
X5R-CERM
0201

AUD_HSBIAS_IN
AUD_HSBIAS

AUD_HSBIAS_REF

1

2

C6215

10UF

TANT-POLY

0805-LLP-1

21

C6221

4.7UF

20%
10V
X5R-CERM
0402

1

20%
16V

2

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

CODEC_MICIN2

AUD_HSBIAS_FILT

VREF_DAC

VHP_FILTN

H13

A11

B10
B11

N10
M10

L12
L13
M13
N11

A8

N9
M9

L8
L7

L5
L4

N8
M8

N7
M7

N5
M5

N4
M4

VREF_DAC

VHP_FILT-

FLYP
FLYN
FLYN

LINEIN_L+
LINEIN_L-

LINEIN_R+
LINEIN_R-

MICBIAS1_L
MICBIAS1_R

MICBIAS2_L
MICBIAS2_R

MICIN1_L+
MICIN1_L-

MICIN1_R+
MICIN1_R-

MICIN2_L+
MICIN2_L-

MICIN2_R+
MICIN2_R-

HSBIAS_IN
HSBIAS
HSBIAS_REF
HSBIAS_FILT

H12A1A9

VA_REF

U6201

CS4208-CRZR

ANALOG

SYM 1 OF 2

AGND

AGND

AGND

L9

L6

L10

M11

VFBGA

AGND

VA_HP

HPGND

A10

N13

VA

HPGND

C8

HPGND

C10

VA_PLL

D13

C6218

0.1UF

X7R-CERM

HSGND

PLLGND

A2

1

10%
16V

2

0402

HPOUT_L
HPOUT_R

SENSE_A1
SENSE_A2

HS3_REF
HS4_REF

HSIN+
HSIN-

SENSE_B1
SENSE_B2

SENSE_C
SENSE_D

LINEOUT1_L+
LINEOUT1_L-

LINEOUT1_R+
LINEOUT1_R-

LINEOUT2_L+
LINEOUT2_L-

LINEOUT2_R+
LINEOUT2_R-

LINEOUT3_L+
LINEOUT3_L-

LINEOUT3_R+
LINEOUT3_R-

LINEOUT4_L+
LINEOUT4_L-

LINEOUT4_R+
LINEOUT4_R-

VCOM

VREF_ADC

BYPASS=U6201.N13:M11:5 mm

A12
A13

C11
D12

C13

HS3

C12

HS4

B13
B12
N6

CODEC_HS_MIC_P

96

M6

CODEC_HS_MIC_N

96

E11
D11
M3
L3

E12
E13

F11
F12

F13
G11

G12
G13

H11
J11

J12
J13

K11
K12

K13
L11

M12

CODEC_VCOM

N12

CODEC_VREF_ADC

1UF-10OHM

C6216

0.1UF

10%
16V

X7R-CERM

0402

MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.5MM

CRITICAL

C6210

20%
25V

TANT

0603-LLP

1

2

1

2

PP4V5_AUDIO_ANALOG

1

C6217

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.07MM

MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

CRITICAL

1

C6211

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

51

51 55

MIN_NECK_WIDTH=0.07MM

MIN_NECK_WIDTH=0.07MM

C6224

1UF

21

10%
25V

402

X5R

GND_AUDIO_CODEC

C6214

C6212

0.1UF

X7R-CERM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.07MM

C6225

51 55

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

0.1UF

X7R-CERM

10%
16V

0402

1UF

10%
25V
X5R
402

10%
16V

0402

21

51 55

1

2

1

BYPASS=U6201.A1:A2:5 MM

2

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.07MM

CRITICAL

L6201

120-OHM-25%-1.3A

0402

CRITICAL

1

C6213

10UF

20%

6.3V

2

CERM-X6S
0402

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_TIPDET_1
AUD_TIPDET_2

AUD_US_HS_GND
AUD_CH_HS_GND
AUD_HP_PORT_REFUS
AUD_HP_PORT_REFCH

HS_MIC_P

HS_MIC_N

AUD_TYPEDET
NC_AUD_LO1_LP
NC_AUD_LO1_LN

NC_AUD_LO1_RP
NC_AUD_LO1_RN

AUD_LO2_L_P
AUD_LO2_L_N

AUD_LO2_R_P

AUD_LO2_R_N

AUD_LO3_L_P
AUD_LO3_L_N

AUD_LO3_R_P
AUD_LO3_R_N

NC_AUD_LO4_LP
NC_AUD_LO4_LN

NC_AUD_LO4_RP
NC_AUD_LO4_RN

PP3V3_S0

21

GND_AUDIO_CODEC

55

OUT

55

OUT

55

IN

55

IN

55

IN

55

IN

55

IN

55

IN

54 96

IN

54 96

IN

55

OUT

53 96

OUT

LFT. SPKR AMP. SIG. SOURCE

53 96

OUT

53 96

OUT

RT. SPKR AMP. SIG. SOURCE

53 96

OUT

53 96

OUT

LFT SUBWOOFER AMP. SIG. SOURCE

53 96

OUT

53 96

OUT

RT. SUBWOOFER AMP. SIG. SOURCE

53 96

OUT

51 55

GND_AUDIO_CODEC

12

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

51 55

D

C

B

4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456

PLACE XW6201 NEAR 5V SOURCE

XW6201

SM

21

PP5V_S4

37 38 61 66 67 69 81 84 86 51

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

A

PM_SLP_S3_BUF_L

66 67 81 82 86

PP5V_S4_AUDIO_XW

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

R6207

22K

5%

1/20W

MF

201

NOSTUFF

21

L6200

FERR-22-OHM-1A-0.055OHM

0201

R6200

2.2K

21

5%

1/20W

MF

201

21

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

4V5_REG_IN

4V5_REG_EN

1

C6200

0.1UF

10%

16V

2

X7R-CERM

0402

1

C6201

1UF

2

U6200

TPS71745

6

IN

CRITICAL

4

EN

10%
10V
X5R
402

GND

SON

2

OUT

NR/FB

XW6200

1

3

4V5_NR

5

NC

SM

CRITICAL

C6202

0.01UF

21

X5R-CERM

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

6 3

0201

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

CRITICAL

1

1

C6203

1.0UF

10%
25V

20%
10V

2

2

X5R-CERM
0201-1

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0V

51 55

SYNC_MASTER=JOE_J45

PAGE TITLE

AUDIO:CODEC, ANALOG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/30/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

62 OF 119

SHEET

51 OF 97

SIZE

A

D

124578

8 7 6 5 4 3

12

L6300

11 12 13 15 17 19
64 67 81 84 86

PP1V5_S0

FERR-22-OHM-1A-0.055OHM

D

R6323

100K

5%

1/20W

MF

201

NOSTUFF

R6322

100K

5%

1/20W

MF

201

C

0201

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

53

21

PD_CS4208_GPIO1

55 86

55 86

54

21

11 52 91

11 52 91

11 91

11 52 91

11 91

21

C6300

4.7UF

20%
4V
X5R-1
402

GPIO0_SPKR_SHUTDOWN

OUT

SPKRCONN_L_ID

IN

SPKRCONN_R_ID

IN

DFET_OPENUS

OUT

DFET_OPENCH

HDA_BIT_CLK

IN

HDA_SYNC

IN

HDA_SDIN0

OUT

HDA_SDOUT

IN

HDA_RST_L

IN

NC_CS4208_MCLKA
NC_CS4208_SCLKA
NC_CS4208_LRCLKA
NC_CS4208_SDOUTA

NC_CS4208_MCLKB
NC_CS4208_SCLKB
NC_CS4208_LRCLKB
NC_CS4208_SDOUTB

1

1

C6301

0.1UF

10%
16V

2

2

X7R-CERM
0402

BYPASS=U6201.J2:J1:5 mm

OUT

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.07MM

VOLTAGE=1.5V

54

R6331

22

1/20W

201

BYPASS=U6201.E1:F1:5 mm

1

C6302

0.1UF

10%
16V

2

X7R-CERM
0402

1

R6324

100K

5%
1/20W
MF
201

2

21

5%

MF

1

R6325

100K

5%
1/20W
MF
201

2

NC_CS4208_GPO0
NC_CS4208_GPO1

CS4208_HDA_SDOUT0_R

52 91

TP_CS4208_HDA_SDOUT1

NO_TEST=TRUE
NO_TEST=TRUE

AUDIO CODEC, DIGITAL BLOCKS

APPLE P/N 353S4080

BYPASS=U6201.G1:F1:5 mm

A7G1E1K1J2

VD

VL_HD

VL_IF

VL_SP

LGND

LGND

LGND

VL_DM

LGND

K3J3F3E3F1

H3
H2
H1
C4
C5
C7

C9
B9

F2
E2
D1
C1
D2
C2
C3
B1
D3

A5
B2
B4
A3
B3

A6
B6
B5
B8
A4

C6
B7

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

GPO0
GPO1

BCLK
SYNC
SDI0
SDI1
SDO0
SDO1
SDO2
SDO3
RST*

MCLK_A
SCLK_A
LRCK_A
SDOUT_A
SDIN_A

MCLK_B
SCLK_B
LRCK_B
SDOUT_B
SDIN_B

SDA
SCL

U6201

CS4208-CRZR

VFBGA

DIGITAL

SYM 2 OF 2

DGND

LGND

J1

SPDIF_IN

SPDIF_OUT

DMIC_SDA0
DMIC_SCL0

DMIC_SDA1
DMIC_SCL1

DMIC_SDA2
DMIC_SCL2

DMIC_SDA3
DMIC_SCL3

1

C6303

2

NC
NC
NC
NC
NC
NC
NC
NC
NC

0.1UF

10%

6.3V
CERM-X5R
0201

BYPASS=U6201.K1:K3:5 mm

1

C6304

0.1UF

10%

6.3V

2

CERM-X5R
0201

G3

CS4208_SPDIF_IN

G2

CS4208_SPDIF_OUT

N3
N2

N1
M1

M2
L1

K2
L2

F6
F7
F8
G6
G7
G8
H6
H7
H8

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

C6305

10UF

20%

6.3V
CERM-X6S
0402

R6302

OMIT

SHORT

1

2

21

402

NC_DMIC_CLK0

NC_DMIC_CLK1

NC_DMIC_CLK2

PP3V3_S0

C6306

DMIC_CLK3_R

10UF

20%

6.3V
CERM-X6S
0402

1

2

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

BYPASS=U6201.A7:E3:5 mm

1

C6307

0.1UF

10%

6.3V

2

CERM-X5R
0201

R6330

33

21

5%
1/16W
MF-LF

402

R6332

75

21

1%
1/16W
MF-LF

402

DMIC_SDA3

52 55 86

PP3V3_S0

SPDIF_OUT_JACK

DMIC_SDA3

DMIC_CLK3

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

55

OUT

52 55 86

IN

55 86

OUT

PP6301

P3MM

SM

1

PP

PLACE_NEAR=U6201.N3:5 mm

D

C

PP6302

P3MM

SM

HDA_BIT_CLK

11 52 91

B

HDA_SYNC

11 52 91

HDA_SDOUT

11 52 91

1

PP

PLACE_NEAR=U6201.F2:5 mm

PP6303

P3MM

SM

1

PP

PLACE_NEAR=U6201.E2:5 mm

PP6304

P3MM

SM

1

PP

B

PLACE_NEAR=U6201.D2:5 mm

PP6305

P3MM

SM

CS4208_HDA_SDOUT0_R

52 91

1

PP

PLACE_NEAR=U6201.D1:5 mm

A

6 3

SYNC_MASTER=JOE_J45

PAGE TITLE

AUDIO:CODEC, DIGITAL

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/30/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

63 OF 119

SHEET

52 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PP5V_S0_AUDIO_AMP_L

53 85

CRITICAL

CRITICAL

L6410

51 96

AUD_LO2_L_P

IN

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

D

GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
1ST ORDER FC (SUB) = NOM 9 HZ

51 96

IN

53

AUD_LO2_L_N

SPKR_SHUTDOWN

51 96

IN

FERR-1000-OHM

CRITICAL

AUD_LO2_R_P

C

FERR-1000-OHM

51 96

PP5V_S0_AUDIO_AMP_R

53 85

CRITICAL

CRITICAL

L6430

AUD_LO3_R_P

51 96

IN

AUD_LO3_R_N

51 96

IN

FERR-1000-OHM

CRITICAL

L6431

FERR-1000-OHM

0402

21

96

0402

21

AUD_SPKRAMP_RSUBIN_N

96

AUD_SPKRAMP_RSUBIN_P

CRITICAL

C6433

0.22UF

CRITICAL

C6434

0.22UF

10%
16V

CERM

402

10%
16V

CERM

402

21

RSUBIN_N

21

RSUBIN_P

NO_TEST=TRUE

NO_TEST=TRUE

SPKR_SHUTDOWN

53

C6432

100UF

6.3V
TANT

CASE-AL1

20%

1

2

C2

CRITICAL

VDD

U6430

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

OUT+
OUT-

GAIN

EDGE

C1

IN

C3

B3

A3

B2

AUD_LO2_R_N

RSUB_GAIN

1

2

96

0402

L6411

96

0402

52

FERR-1000-OHM

CRITICAL

C6436

4700PF

10%
50V
X7R-CERM
0402

21

AUD_SPKRAMP_LIN_P

21

AUD_SPKRAMP_LIN_N

GPIO0_SPKR_SHUTDOWN

IN

CRITICAL

L6420

FERR-1000-OHM

L6421

96

0402

BYPASS=U6430.C2:C1:5 mm

1

C6431

0.1UF

10%
16V

2

X5R-CERM
0201

21

96

0402

21

AUD_SPKRAMP_RIN_N

CRITICAL

AUD_SPKRAMP_RIN_P

C6414

0.01UF

10%
50V

X7R-CERM

0402

CRITICAL

CRITICAL

C6413

0.01UF

10%
50V

X7R-CERM

0402

21

L6401

FERR-1000-OHM

0402

CRITICAL

PP5V_S0_AUDIO_AMP_R

53 85

CRITICAL

C6423

0.01UF

X7R-CERM

C6424

0.01UF

21

10%
50V

X7R-CERM

53

0402

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

21

96

96

21

21

10%
50V

0402

96

NO_TEST=TRUE

SPKR_SHUTDOWN

NO_TEST=TRUE
SPKRAMP_LIN_P
SPKRAMP_LIN_N

NO_TEST=TRUE

96

SPKRAMP_RIN_N

1

C6412

47UF

20%

6.3V

2

TANT-POLY

CASE-A4

1

R6400

100K

5%
1/16W
MF-LF

402

2

CRITICAL

C6422

47UF

20%

6.3V

TANT-POLY

CASE-A4

NO_TEST=TRUE

SPKRAMP_RIN_P

C6411 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6410 (CSP)

BYPASS=U6410.A1:A2:5 mm

1

C6411

0.1UF

SPKR_L_GAIN

R6410

100K

1/16W
MF-LF

B1
C1

C3

SPKR_R_GAIN

R6420

2

402

100K

1/16W
MF-LF

10%
50V
X7R
603-1

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

1

5%

2

BYPASS=U6420.A1:A2:5 mm

1

C6421

0.1UF

10%
16V

2

X5R-CERM
0201

1

5%

402

2

55 86 96

OUT

55 86 96

OUT

MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_N

CRITICAL

A1

PVDD

U6410

MAX98300

WLP

A3

IN+

B3

IN-

C2

B2

NC

OUT+
OUT-

GAINSHDN*

B1
C1

C3

PGND

A2

1

A1

U6420

MAX98300

IN+
IN-

NC

PVDD

WLP

CRITICAL

OUT+
OUT-

GAINSHDN*

2

A3
B3

C2

B2

PGND

A2

B

12

SPKRCONN_L_OUT_N

55 86 96

OUT

OUT

55 86 96

OUT

55 86 96

OUT

D

55 86 96

C

B

53 85

CRITICAL

L6440

AUD_LO3_L_P

FERR-1000-OHM

51 96

IN

CRITICAL

L6441

51 96

IN

AUD_LO3_L_N

FERR-1000-OHM

0402

0402

96

21

96

21

AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N

CRITICAL

C6443

0.22UF

CRITICAL

C6444

0.22UF

CERM

21

10%
16V

CERM

402

21

NO_TEST=TRUE

10%
16V

402

LSUBIN_P

NO_TEST=TRUE

LSUBIN_N

53

A

6 3

PP5V_S0_AUDIO_AMP_L

CRITICAL

C6442

100UF

20%

6.3V
TANT

CASE-AL1

SPKR_SHUTDOWN

C6441 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6440 (CSP)

1

2

C2

CRITICAL

VDD

U6440

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

C1

OUT+
OUT-

GAIN

EDGE

C3

B3

A3

B2

LSUB_GAIN

1

2

BYPASS=U6440.C2:C1:5 mm

1

C6441

0.1UF

10%
50V

2

X7R
603-1

C6446

4700PF

10%
50V
X7R-CERM
0402

SPKRCONN_SL_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_N

55 86 96

OUT

55 86 96

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SYNC_MASTER=JOE_J45

PAGE TITLE

OUT

AUDIO: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/30/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

64 OF 119

SHEET

53 OF 97

SIZE

A

D

124578

8 7 6 5 4 3

12

D

R6550

C6562

0.1UF

10%
16V
X5R-CERM
0201

2.2K

21

5%
1/16W
MF-LF

402

R6559

2.2K

5%
1/16W
MF-LF

402

BYPASS=U6500.B2::3MM

1

2

HS_MIC_P

51 96

OUT

R6556

100K

5%

1/20W

MF

201

51 96

OUT

HS_MIC_N

R/C6550 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS

(SEE RADAR # 6210118)

1

R6520

10K

5%
1/16W
MF-LF
402

2

DFET_OPENCH

52

C

IN

1

2

1

C6560

1.0UF

10%
35V

2

CERM-X5R
0402

CRITICAL

1

C6550

3300PF

10%
10V

2

X7R-CERM
0201

1

2

BYPASS=U6500.B2::3MM

MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.2MM

AUD_HS_MIC_P

21

AUD_HS_MIC_N

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.06MM

C6563

0.01UF

10%
10V
X5R-CERM
0201

DFET_CPO1

1

2

C6501

1000PF

5%
25V
NP0-C0G
0402

CRITICAL

1

C6558

27PF

5%
25V

2

C0G
0201

TAIC3027A0YFFR

C2

PSEL

C1

CP

IN

IN

B2

VDD

U6500

WCSP

GND

B1

55 96

55 96

OUT1
OUT2

A1

AUD_CONN_SLEEVE_XW

A2

AUD_CONN_SLEEVE_XW

54 55

OUT

54 55

OUT

D

C

IN

DFET_OPENUS

1

R6521

10K

5%
1/16W
MF-LF
402

2

1

C6530

1.0UF

10%
35V

2

CERM-X5R
0402

1

C6542

0.1UF

10%
16V

2

X5R-CERM
0201

BYPASS=U6501.B2::3MM

BYPASS=U6501.B2::3MM

1

C6543

0.01UF

10%
10V

2

X5R-CERM
0201

DFET_CPO2

1

C6502

1000PF

5%
25V

2

NP0-C0G
0402

TAIC3027A0YFFR

C2

PSEL

C1

CP

B2

VDD

U6501

WCSP

GND

B1

OUT1
OUT2

A1

AUD_CONN_RING2_XW

A2

AUD_CONN_RING2_XW

6 3

B

54 55

OUT

54 55

OUT

SIZE

A

D

SYNC_MASTER=CLEAN_X305

PAGE TITLE

AUDIO: JACK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/24/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

65 OF 119

SHEET

54 OF 97

124578

52

B

A

8 7 6 5 4 3

12

D

C

B

A

51

OUT

51

OUT

51

IN

GND_AUDIO_CODEC

51

51

IN

CODEC OUTPUT SIGNAL PATHS

FUNCTION

TWEETERS
SUB
SPDIF OUT

CODEC INPUT SIGNAL PATHS

FUNCTION
DMIC 1
DMIC 2 0X1C (28)

HEADSET MIC

OTHER CODEC GPIO LINES

LEFT SPEAKER ID
RIGHT SPEAKER ID
DFET CONTROL

AUD_HP_PORT_REFCH

51

OUT

120-OHM-25%-1.3A

AUD_CH_HS_GND

VOLUME
0X02 (2)
0X03 (3)
0X04 (4)
N/A

GPIO2 INPUT
GPIO3
GPIO4

CRITICAL

L6611

0402

INPUT
OUTPUT

21

CONVERTER
0X02 (2)
0X03 (3)
0X04 (4)
0X0E (14)

CONVERTER
0X09 (9)
0X09 (9)

0X07 (7)

HIGH = FG, LOW = MERRY
HIGH = FG, LOW = MERRY
HIGH = DFETs OPEN

AUD_CONN_SLEEVE

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

XW6601

AUD_HS_MIC_P

54 96

OUT

CRITICAL

L6613

AUD_HP_PORT_REFUS

AUD_US_HS_GND

51

OUT

120-OHM-25%-1.3A

0402

21

AUD_CONN_RING2

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

XW6603

AUD_HS_MIC_N

54 96

AUD_HP_PORT_L

2

R6602

2.2K

1

201

R6603

2

2.2K

201

1

AUD_HP_PORT_R

52

5%
1/20W
MF

5%
1/20W
MF

OUT

IN

51

OUT

51

OUT

51

OUT

SPDIF_OUT_JACK

AUD_TIPDET_2

AUD_TIPDET_1

AUD_TYPEDET

CRITICAL

L6604

120-OHM-25%-1.3A

0402

CRITICAL

L6608

FERR-470-OHM

0201

CRITICAL

L6605

120-OHM-25%-1.3A

0402

CRITICAL

L6606

FERR-470-OHM

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

21

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

21

L6607

FERR-470-OHM

21

AUD_CONN_HP_RIGHT

0201

PIN COMPLEX
0X10 (16)
0X12 (18)
0X13 (19)
0X21 (33)

PIN COMPLEX
0X1C (28)

0X18 (24)

SM

21

SM

21

AUD_CONN_TIPDET_2

CRITICAL

21

AUD_CONN_TIPDET_1

0201

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

21

AUD_CONN_TYPEDET

1

R6601

10K

2

5%
1/16W
MF-LF
402

C6602

100PF

MUTE CONTROL

VREF

CRITICAL

L6612

120-OHM-25%-1.3A

0402

CRITICAL

L6614

120-OHM-25%-1.3A

0402

CRITICAL

2

ESDALC5-1BM2

SOD882

1

1

5%

25V

2

0201

C0G

ESDALC5-1BM2

N/AHP/HS OUT
CODEC GPIO0
CODEC GPIO0
N/A

3.3V

3.3V

2.7V

21

21

DZ6607

CRITICAL

DZ6601

SOD882

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

PLACE_NEAR=J6600.3:2.54mm

XW6600

SM

21

AUD_CONN_SLEEVE_XW

54

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

PLACE_NEAR=J6600.5:2.54mm

XW6602

SM

21

AUD_CONN_RING2_XW

54

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

1

C6603

100PF

5%
25V

2

C0G
0201

2

C6604

100PF

25V

1

0201

C0G

DMIC_SDA3

52 86

OUT

OMIT

R6680

SHORT

402

DMIC_CLK3

52 86

OUT

2

C6605

100PF

5%
25V
C0G

2

1

5%

2

1

0201

CRITICAL

DZ6602

ESDALC5-1BM2

SOD882

1

2

1

DMIC_SDA2

86

21

CRITICAL

DZ6603

ESDALC5-1BM2

SOD882

C6606

100PF

0201

2

1

1

5%
25V
C0G

2

ESDALC5-1BM2

2-MIC CONNECTOR

APN: 518S0769

FF14A-5C-R11DL-B-3H

CRITICAL

DZ6606

ESDALC5-1BM2

SOD882

CRITICAL

DZ6605

SOD882

J6601

F-RT-SM

6

1
2
3
4
5

7

2

1

1

C6607

100PF

5%
25V

2

C0G
0201

C6608

6 3

100PF

0201

CRITICAL

J6602

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

CRITICAL

J6603

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

D

SPKRCONN_L_OUT_P

53 86 96

IN

SPKRCONN_L_OUT_N

53 86 96

IN

52 86

IN

SPKRCONN_SL_OUT_P

53 86 96

IN

SPKRCONN_SL_OUT_N

53 86 96

IN

SPKRCONN_R_OUT_P

53 86 96

IN

SPKRCONN_R_OUT_N

53 86 96

IN

52 86

IN

SPKRCONN_SR_OUT_P

53 86 96

IN

SPKRCONN_SR_OUT_N

53 86 96

IN

SPEAKER CONNECTOR

SPKRCONN_L_ID

SPKRCONN_R_ID

HP=80HZ

APN: 518S0672

C

APN: 514-0875

J6600

AUDIO-SPDIF-J44

F-RT-TH

5

MIC

6

AUDIO GND

2

2RTN

1

DET2

8

NC

1

C6600

1UF

10%
10V
X5R

402-1

2

1

5%

25V

2

C0G

CRITICAL

DZ6604

1

ESDALC5-1BM2

SOD882

1

C6601

0.1UF

10%

2

6.3V

2

CERM-X5R
0201

SYNC_MASTER=CLEAN_X305

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DET1

7

1RTN

3

R.AUDIO

4

AUDIO GND

AUDIO

9

VIN

10

VDD

11

GND

OPERATING VOLTAGE 3.3

POF
12
13

SHELL

14

PINS

15

SYNC_DATE=06/24/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

66 OF 119

SHEET

55 OF 97

SIZE

B

A

D

124578

8 7 6 5 4 3

12

MagSafe DC Power Jack

CRITICAL

F7005

2.0K

1/16W
MF-LF

5%

402

6AMP-32V-0.0095OHM

1

2

SYS_ONEWIRE

PP20V_DCIN_FUSE

CRITICAL

J7000

WTB-PWR-M82

D

M-RT-SM

518S0508

1
2
3
4
5
6

86

MIN_LINE_WIDTH=1MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=20V

TP_TDM_ONEWIRE_MPM

C7000

0.1UF

ADAPTER_SENSE

86

CERM

1

20%
10V

2

402

NOSTUFF

1

C7005

0.01UF

20%
50V

2

CERM
0603

SMC_BC_ACOK_VCC

1

VCC

U7000

MAX9940

SC70-5

5

EXT INT

CRITICAL

NC

GND

2

3

R7029

4

0603

CRITICAL

U7001

TC7SZ08FEAPE

SOT665

4

21

PP3V42_G3H

1

C7008

0.1UF

20%

PLACEMENT_NOTE=PLACE NEAR U7100 and U7001

10V

2

CERM

5

Y

3

BI

402

2

SMC_BC_ACOK

A

1

B

40

IN

40 41 42 57

NC

Q7010

C

1-Wire OverVoltage Protection

The chassis ground will otherwise float and can
send transients onto ADAPTER_SENSE when AC is

connected.

SI5419DU

POWERPAK

D

1

G

4

DCIN_ISOL_GATE_R

PPDCIN_G3H_ISOL

44 57 84

S

84 86
42 43 50
19 34 37
38 40 41
56 57 67

5A

5

PPDCIN_G3H

1

R7012

22.1K

2

1

C7012

0.047UF

10%
25V

2

X7R
0402

DCIN_ISOL_GATE

6.8V Zener

57 84 86

Input impedance of 22.1K meets

1%

sparkitecture requirements

1/20W
MF

for D2 design only

201

1

R7010

100K

5%
1/20W
MF
201

2

R7011

10K

21

5%

1/20W

MF

201

K

D7010

CDZ6.8B

SM

A

When input voltage is 2V the FET will be off
blocking the leakage path and 22.1K can be
properly detected.

When input voltage is at 16V+, FET will
conduct and power charger and 3.42V reg

D

C

0603

10%
35V

CRITICAL

D7005

BAT30CWFILM

SOT-323

1

2

1

C7097

4.7UF

2

X5R-CERM

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=20V

1

10%
35V

2

0603

R7001

0

5%

1/20W

MF

0201

OMIT

C7001

NOSTUFF

NONE
NONE
NONE

21

1

2

402

P3V42G3H_SHDN_L

NOSTUFF

1

R7002

49.9K

1%
1/20W
MF
201

2

APN:353S3733

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3

6

BOOST

VIN

U7090

LT3470AED

DFN

SHDN*

CRITICAL

7

NC

NC

GND

5

BIAS

THRM

PAD

48

SW

2

1

FB

9

P3V42G3H_BOOST

DIDT=TRUE

1

C7094

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P3V42G3H_FB

0.22UF

10%
16V

CERM

402

CRITICAL

2

10UH-20%-0.85A-0.46OHM

P3V42G3H_BIAS

1

C7095

22PF

5%
50V

2

C0G
0201

Vout = 1.25V * (1 + Ra / Rb)

L7095

2520

R7097

1/16W
MF-LF

<Ra>

R7095

348K

1/20W

<Rb>

R7096

200K

1/20W

B

PP3V42_G3H

21

Vout = 3.425V
300MA MAX OUTPUT

1

(Switcher limit)

0

5%

402

2

1

C7099

10UF

20%

6.3V

2

CERM-X6S
0402

1

1%

MF

201

2

1

1%

MF

201

2

1

C7098

10UF

20%

6.3V

2

CERM-X6S
0402

SYNC_MASTER=CLEAN_X425

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

19 34 37 38 40 41 42 43 50 56
57 67 84 86

NOTE: R7097 can be replaced

by SHORT at PVT

SYNC_DATE=11/04/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

70 OF 119

SHEET

56 OF 97

SIZE

A

D

124578

R7020

47

21

PP20V_DCIN_CONN_R

1%

1/3W

MF

805

B

30 44 47 57 63 65 84 86

PPBUS_G3H

R7005

10

5%

1/8W

MF-LF

805

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=20V

21

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

NOTE: MIRROR C7092 and C7096

1

2

NOSTUFF

C7091

4.7UF

X5R-CERM

0603

40 43 57 86 95

40 43 57 86 95

1

R7050

10K

5%
1/16W
MF-LF
402

2

1

C7092

10%
35V

2

4.7UF

X5R-CERM

0603

1

C7093

10%
35V

2

4.7UF

X5R-CERM

0603

1

C7096

10%
35V

4.7UF

2

X5R-CERM

NOTE: MIRROR C7093 and C7097

NOSTUFF

C7090

4.7UF

10%
35V

X5R-CERM

BATTERY CONNECTOR

518-0376

CRITICAL

J7050

BAT-J5

F-ST-TH

POS

12 1

POS

13 2

POS

14 3

POS

15 4

SCL

16 5

A

NC
NC

SDA

17 6

SYS_DETECT

18 7

NEG

19 8

NEG

20 9

NEG

21 10

NEG

22 11

VER 1

PPVBAT_G3H_CONN

57 86

SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L

86

C7050

0.1UF

X7R-CERM

0402

CRITICAL

D7050

1

C7060

10%
25V

1UF

2

CER-X6S

0402

RCLAMP2402B

1

10%
16V

2

SC-75

0603

2

1

3

6 3

8 7 6 5 4 3

12

NOSTUFF

For Erp Lot6 spec

CHGR_DCIN_D_R

57

MIN_NECK_WIDTH=0.25 mm

NC

NCNCNC

4

8

C7185

0.1UF

10%
25V
X7R-CERM
0402

Inrush Limiter

1

R7185

470K

1%
1/16W
MF-LF

402

2

R7186

3

CHGR_DCIN_D_R

57

12
13
11
10

18
17

IRF9395TRPBF

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

1

332K

1%
1/16W
MF-LF

402

2

R7101

4.7

21

5%
1/16W
MF-LF

402

19

VDD

VHST

CRITICAL

SMB_RST_N
SCL

U7100

TQFN

SDA

4

VFRQ

6

CELL

3

5
7
8

ACIN

ICOMP
VCOMP
VNEG
CSOP
CSON

(AGND)

THRM_PAD

29

ISL6259

XW7100

PLACE_NEAR=U7100.29:1mm

PLACE_NEAR=U7100.22:1mm

CRITICAL

Q7180

DIRECTFET-MC

R7105

20

21

5%
1/16W
MF-LF

402

PP5V1_CHGR_VDDP

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

VDDP

2

DCIN

26

SGATE

1

AGATE

28

95

CSIP

27

95

CSIN

25

BOOT

24

UGATE

23

PHASE

21

LGATE

16

BGATE

9

AMON

20V/V

36V/V

(OD)

15

BMON

14

ACOK

PGND

353S2392

22

SM

21

S

D

G

6

(CHGR_DCIN)

1

C7101

1UF

10%
10V

2

X6S-CERM

0402

CHGR_DCIN

57

CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N

CHGR_BOOT
CHGR_UGATE
CHGR_PHASE

CHGR_LGATE

MIN_LINE_WIDTH=0.6 mm

CHGR_BGATECHGR_CSO_P
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

FROM ADAPTER

PPDCIN_G3H

56 84 86

D

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V
Sparkitecture impedance is set by R7112 in D2

19 34 37 38 40 41 42 43 50 56
67 84 86

C

1

2

1

2

B

R7112

1/16W
MF-LF

R7110

130K

1%
1/16W
MF-LF
402

R7111

40.2K

1%
1/16W
MF-LF
402

402

1

1K

1%

2

50

SMC_RESET_L

40

IN

41
86

1

R7115

330K

5%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

1

R7142

1K

5%
1/16W
MF-LF
402

2

CHGR_VNEG_R

1

C7116

470PF

10%
50V

2

CERM
0402

PPDCIN_G3H_ISOL

44 56 84

PP3V42_G3H

C7102

1UF

X6S-CERM

0402

C7115

220PF

10%
50V

X7R-CERM

0402

R7116

3.01K

1/16W
MF-LF

402

1

10%
10V

2

GND_CHGR_AGND

R7100

0

21

5%

40 43 56
86 95

1/16W
MF-LF

40 43 56
86 95

402

67

1

2

1

1%

2

57

IN
BI
IN

95

95

1

2

1

2

CRITICAL

D7105

BAT30CWFILM

SOT-323

1

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V

NO STUFF

1

R7102

100K

5%
1/16W
MF-LF
402

2

CHGR_RST_L
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
CHGR_VFRQ
CHGR_CELL

CHGR_ACIN
CHGR_ICOMP

CHGR_VCOMP
CHGR_VNEG

CHGR_CSO_N

C7150

1UF

10%
16V
CER-X6S
0402

251

1097

S

D

G

3

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

(CHGR_SGATE)(CHGR_AGATE)

1

C7120

0.047UF

10%
16V

2

X7R-CERM
0402

C7122

0.1UF

CER-X7R

DIDT=TRUE

44

44

40 41 42 56

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

OUT
OUT
OUT

OMIT

1

C7180

NOSTUFF

NONE
NONE

2

NONE
603

10%
50V

0402

Reverse-Current Protection

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=20V

1

R7180

100K

5%
1/16W
MF-LF
402

2

1

R7181

62K

5%
1/16W
MF-LF
402

2

R7121

10

21

5%
1/16W
MF-LF

402

R7122

10

21

5%
1/16W
MF-LF

402

1

1

C7121

0.1UF

10%
50V

2

2

CER-X7R
0402

PLACE_NEAR=U7100.25:2mm

1

C7125

0.22UF

10%
16V

2

CERM
402

G

4

5

D

S

4

CRITICAL

Q7135

NTMFS4C10N

DFN

321

G

R7151
R7152

CHGR_ICOMP_RC

1

C7142

0.1UF

10%
50V

2

CER-X7R
0402

C7111

0.01UF

X7R-CERM

0402

10%
16V

1

1

C7100

1UF

10%
10V

2

2

X6S-CERM
0402

C7105

0.22UF

10%
50V

CER-X7R

0603

1

2

GND_CHGR_AGND

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

0.001UF

C7126

10%
50V

X7R-CERM

0402

1

2

MIN_LINE_WIDTH=0.5 mm

PLACE_SIDE=BOTTOM

CHGR_CSI_R_P

96

CHGR_CSI_R_N

96

5

CRITICAL

D

Q7130

NTMFS4C06N

DFN

S

321

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

DIDT=TRUE

21

2.2

96

21

96

C7191

4.7UF

10%
35V

X5R-CERM

0603

PLACE_SIDE=TOP

NOTE: MIRROR C7190

CRITICAL

2

R7120

0.02

0.5%
1W
MF
0612-6

341

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=20V

Max Current = 8A
(L7130 limit)
f = 400 kHz

CHGR_CSO_R_P

1/16W5%MF-LF

CHGR_CSO_R_N

1/16W5%MF-LF0402

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

402

4.7UF

X5R-CERM

0603

10%
35V

1

2

1

2

C7190

NC

AND C7191

1

C7130

2

CRITICAL

4.7UH-20%-14.5A-9MOHM

L7130

PIME173T-SM

152S1466

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

CRITICAL

R7150

0.005

1%
1W
MF

0612-6

2 1
4 3

6

VIN

U7190

LT3470A

SHDN*

CRITICAL

7

NC

CRITICAL
10UF

20%
35V
TANT-POLY
CASE-D2-SM

1

2

21

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.6V

3

BOOST

DFN

BIAS

THRM

GND

PAD

9

5

CRITICAL

C7131

10UF

20%
35V
TANT-POLY
CASE-D2-SM

SW

FB

C7155

P5V1_BOOST

DIDT=TRUE

1

C7194

48

P5V1_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1

0.22UF

10%
16V

CERM

33UH-20%-0.39A-0.435OHM

402

2

1

C7195

2

22PF

5%
50V
C0G
0201

CRITICAL

L7195

DP418C-SM

P5V1_FB

Vout = 1.25V * (1 + Ra / Rb)

CRITICAL

1

C7132

10UF

20%
35V

2

TANT-POLY
CASE-D2-SM

CRITICAL

1

C7133

10UF

20%
35V

2

TANT-POLY
CASE-D2-SM

CRITICAL

1

C7134

10UF

20%
35V

2

TANT-POLY
CASE-D2-SM

8AMP-32V-0.006OHM

8AMP-32V-0.006OHM

1UF

0603

10%
25V
X7R

CRITICAL

1

C7140

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C7156

2

X7R-CERM

0.1UF

0402

10%
16V

1

2

1

C7145

0.001UF

10%
50V

2

X7R-CERM
0402

C7157

0.01UF

10%
16V

X7R-CERM

0402

21

<Ra>

R7195

681K

1%

1/20W

MF

201

<Rb>

R7196

200K

1%

1/20W

MF

201

MIRROR C7135 AND C7136

CRITICAL

1

C7135

1.0UF

10%
35V

2

CERM-X6S
0402

PLACE_NEAR=Q7130.5:2mm

CRITICAL

F7140

21

0603

CRITICAL

F7141

21

0603

CRITICAL

SI7137DP

S

321

1

2

CRITICAL

1

C7198

1

10UF

20%

6.3V

2

CERM-X6S
0402

2

PLACE_SIDE=TOP

1

2

CRITICAL

1

C7136

1.0UF

10%
35V

2

CERM-X6S
0402

PLACE_NEAR=Q7130.5:2mm

Q7155

SO-8

D

5

G
4

R7190

0

21

5%

1/16W

402

CHGR_DCIN

MF-LF

PP5V1_CHGR_VDDP

CRITICAL

1

C7199

10UF

20%

6.3V

2

CERM-X6S
0402

PLACE_SIDE=BOTTOM

1

C7137

2

Vout = 5.50V
100MA MAX OUTPUT

(Switcher limit)

NOTE: MIRROR C7198

AND C7199

0.001UF

10%
50V
X7R-CERM
0402

TO SYSTEM

PPBUS_G3H

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

57

57

D

C

30 44 47 56 63 65 84 86

B

56 86

A

SYNC_MASTER=CLEAN_X305

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=01/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

71 OF 119

SHEET

57 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

PP5V_S0

18 19 36 49 59 62 63 66 67 73
79 80 84 85 86

R7220

4.02K

1%
1/20W
MF
201

40 41 89

PLACE_NEAR=U7200.16:2mm

6

OUT

18 19 40 67 86

45

NO_XNET_CONNECTION=TRUE

R7235

9.31K

CPUVR_NTC_R

1

R7236

95.3K

1%

1/20W

MF

201

R7215

845

1%

1/20W

1

C7210

0.22UF

20%

6.3V

2

X6S-CERM
0201

2

21
201

MF

PPVCCIO_S0_CPU

5 6 8

10 18

1

C7279

0.01UF

10%
16V

2

X7R-CERM
0402

PLACE_NEAR=U7200.32:2mm

CPU_VIDSOUT

8

89

C

BI

CPU_VIDALERT_L

8

89

OUT

CPU_VIDSCLK

8

89

IN

CPUVR_ISUMP

59

IN

59

IN

59

IN

59

IN

59

IN

NO_XNET_CONNECTION=TRUE

CPUVR_ISUMN

CPUVR_ISEN1
CPUVR_ISEN2
CPUVR_ISEN3

B

R7279

54.9

1/20W

201

1

1%
MF

2

C7214

220PF

X7R-CERM

C7213

0.1UF

1

R7280

110

1%
1/20W
MF
201

2

PLACE_NEAR=U7200.30:2mm

1

10%
25V

2

201

1

10%

6.3V

2

X6S

0201

1

R7237

100KOHM

0201

2

CPUVR_ISUMN_RC

R7210

487

1%

1/20W

MF

201

1

C7211

0.22UF

20%

6.3V

2

X6S-CERM
0201

21

1

C7212

0.22UF

20%

6.3V

2

X6S-CERM
0201

NO_XNET_CONNECTION=TRUE

CPU_VCCSENSE_P_R

R7243

C7260

330PF

10%
16V
X7R
0201

5%

1/20W

MF

0201

0

CPU_VCCSENSE_P

8

89

IN

CPU_VCCSENSE_N

9

89

IN

1

2

NO_XNET_CONNECTION=TRUE

21

1

C7261

330PF

10%
16V

2

X7R
0201

C7242

100PF

2 1

5%
25V
C0G

0201

CPU_VCCSENSE_P_RC

21

1%

1/20W

MF

201

1

R7223

102K

1%
1/20W
MF
201

2

C7215

2700PF

21

201

10%

X7R-CERM

10V

CPUVR_COMP_RC

R7241

2.94K

1%

1/20W

MF

201

(GND)

1

R7222

9.31K

1%
1/20W
MF
201

2

C7240

1

1800PF

10%
25V

2

X7R-CERM

0201

C7241

1

R7240

365K

1%

1/20W

MF

201

2

21

NO_XNET_CONNECTION=TRUE

R7242

2 1

39PF

18PF

0201

21

0201

NP0-C0G

5%
25V
C0G

1

2

1

2

1

R7221

154K

1%
1/20W
MF
201

2

C7216

5%

25V

NO_XNET_CONNECTION=TRUE

1K

1%

1/20W

MF

201

IN

OUT

C7231

47PF

R7250

NO STUFF

R7201

1

21

5%
1/16W
MF-LF

402

CPUVR_NTC
CPU_PROCHOT_L
CPUVR_SLOPE
CPUVR_PROG1

CPUVR_PROG2
CPUVR_PROG3

ALL_SYS_PWRGD

CPUVR_COMP

(CPU_VCCSENSE_N)

CPUVR_FB
CPUVR_FB2

(CPUVR_ISUMP)

CPUVR_ISUMN_R
CPUVR_IMON

1

C7230

1500PF

5%

25V

2

C0G

0201

2K

21

1%

1/20W

MF

201

PP5V_S0_CPUVR_VDD

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

1

C7201

1UF

10%
10V

2

X6S-CERM
0402

1

10%
10V

2

X7R

0201

1

R7230

93.1K

1%
1/20W
MF
201

2

CPUVR_FB_RC

PPVIN_S0_CPUVR_VIN

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.9V

17

16

VINVDD

U7200

ISL95826AHRZ-_S2378

5

4

29

28
27

1

30
31
32

6

13

7
8

15
14

3

12
11
10

NTC

VR_HOT*

SLOPE

PROG1
PROG2
PROG3

VR_ON

SDA
ALERT*
SCLK

COMP

RTN

FB
FB2

ISUMP
ISUMN

IMON

ISEN1
ISEN2
ISEN3

1

2

LLP

CRITICAL

THRM

33

C7250

330PF

10%
16V
X7R
0201

NO STUFF

PAD

MIN_LINE_WIDTH=0.3 mm

C7202

0.22UF

18

CPUVR_FCCM

FCCM

23

CPUVR_PWM3

PWM3

22

CPUVR_PWM2

PWM2

2026

CPUVR_PWM1

PWM1

25

CPUVR_DRSEL

DRSEL

2

CPUVR_PGOOD

PGOOD

9

NC

NC

19

NC

NC

21

NC

NC

24

NC

NC

0402

10%
25V
X7R

R7202

10

21

5%
1/16W
MF-LF

1

2

402

PLACE_NEAR=U7200.17:2mm

59

OUT

59

OUT

59

OUT

59

OUT

19

OUT

PPVIN_S5_HS_COMPUTING_ISNS

R7224

2.49M

21

1%

1/16W

MF

0402

44 59 60 62 84

D

C

B

A

6 3

SYNC_MASTER=CLEAN_X425

PAGE TITLE

SYNC_DATE=01/09/2015

CPU VR12.5 VCC Regulator IC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

72 OF 119

SHEET

58 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

PPVIN_S5_HS_COMPUTING_ISNS

C7311

0.22UF

10%
16V

CERM

402

44 58 60 62 84

R7311

1 2

1/16W
MF-LF

21

CPUVR_PHASE1_K

0

5%

402

CPUVR_BOOT1

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PHASE 1

4

BOOT

39

DISB*

6

GH

NC

36

GL

NC

7

PHASE

40

PWM

1

ZCD_EN*

38

THWN*

NC

2

VCIN

CGND

5

37

41

VDRV

U7310

FDMF6808N

PQFN

CRITICAL

353S3836

18

17

16

1

C7310

1UF

10%
16V

2

X6S-CERM

0402

3

NC

VIN

VSWH

PGND

25242322212019

282726

73 79 80 84 85

PP5V_S0

18 19 36 49 58
59 62 63 66 67
86

CPUVR_BOOT1_RC

58

58 59

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_PWM1

IN

CPUVR_FCCM

IN

D

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

8
9
10
11
12
13
14
42

15

NC

29
30
31
32
33
34
35
43

CRITICAL

1

C7340

12PF

5%
NP0-C0G

2

0201
25V

CPUVR_PHASE1
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

CRITICAL

1

C7341

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

0.36UH-20%-36A-0.00108OHM

NOSTUFF

1

R7312

2.2

5%
1/10W
MF-LF

603

2

CRITICAL

L7310

PIMS103T-SM

152S1538

CRITICAL

1

C7313

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

21

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

CPUVR_PH1_SNUB

DIDT=TRUE

NOSTUFF

1

C7312

0.001UF

10%
50V

2

X7R-CERM
0402

NO_XNET_CONNECTION=TRUE

CRITICAL

1

C7314

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPVCC_S0_CPU_PH1

CPUVR_ISNS1_P

R7315

CRITICAL

1

C7315

2

1/20W

NOSTUFF

10UF

20%
16V
X6S-CERM
0603

1K

1%
MF

201

C7317

1UF

10%
16V
X6S-CERM
0402

THESE TWO CAPS ARE FOR EMC

C7318

0.001UF

10%
50V
X7R-CERM
0402

45 59 96 45 96

1

C7319

0.001UF

10%
50V

2

X7R-CERM
0402

OUT

OUT

OUT

1

2

OUTOUT

58 59

58

58 59

R7317

10K

1%

1/20W

MF

201

R7318

10K

1%

1/20W

MF

201

CPUVR_ISNS2_N

21

NO_XNET_CONNECTION=TRUE

CPUVR_ISNS3_N

21

NO_XNET_CONNECTION=TRUE

NOSTUFF

CRITICAL

C7316

10UF

20%
16V
X6S-CERM
0603

1

2

21
43

CRITICAL

R7310

0.00075

0612-1

1

2

1%
1W
MF

CPUVR_ISNS1_N

1

R7314

3.9

1%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

CPUVR_ISUMN

1

1

R7316

10K

1%
1/20W
MF
201

2

2

NO_XNET_CONNECTION=TRUE

CPUVR_ISEN1
CPUVR_ISUMP

Additonal Input Bulk Caps

CRITICAL

1

C7372

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

45 59 96

45 59 96

CRITICAL

1

C7370

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7371

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7373

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7374

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7377

15UF

20%
16V

2

TANT
SM

CRITICAL

1

C7375

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7378

15UF

20%
16V

2

TANT
SM

CRITICAL

1

C7376

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7379

15UF

20%
16V

2

TANT
SM

12

CRITICAL

1

C7380

15UF

20%
16V

2

TANT
SM

D

C7327

1UF

10%
16V
X6S-CERM
0402

1

C7337

1UF

10%
16V

2

X6S-CERM
0402

CPUVR_ISUMN

CPUVR_ISEN3
CPUVR_ISUMP

THESE TWO CAPS ARE FOR EMC

1

2

OUTOUT

1

C7328

0.001UF

10%
50V
X7R-CERM
0402

C7329

0.001UF

10%
50V

2

X7R-CERM
0402

45 59 96 45 96

THESE TWO CAPS ARE FOR EMC

1

C7338

0.001UF

10%
50V

2

X7R-CERM
0402

OUT

OUT

OUT

1

C7339

0.001UF

10%
50V

2

X7R-CERM
0402

58 59

58

58 59

OUT

OUT

OUT

58 59

58

58 59

R7327

10K

1%

1/20W

MF

201

R7328

10K

1%

1/20W

MF

201

R7337

R7338

CPUVR_ISNS1_N

21

NO_XNET_CONNECTION=TRUE

CPUVR_ISNS3_N

21

NO_XNET_CONNECTION=TRUE

10K

CPUVR_ISNS1_N

21

NO_XNET_CONNECTION=TRUE

1%

1/20W

MF

201

10K

CPUVR_ISNS2_N

21

NO_XNET_CONNECTION=TRUE

1%

1/20W

MF

201

45 59 96

45 59 96

45 59 96

PPVCC_S0_CPU

6 8

10 45 84 86

Vout = 1.85V max
95A max output
f = 450 kHz

SYNC_MASTER=CLEAN_X425

PAGE TITLE

CPU VR12.5 VCC Power Stage

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/09/2015

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

73 OF 119

SHEET

59 OF 97

124578

SIZE

C

B

A

D

1

2

NOSTUFF

CRITICAL

1

C7335

10UF

2

1/20W

201

20%
16V
X6S-CERM
0603

1K

1%
MF

NOSTUFF

CRITICAL

1

C7326

10UF

20%
16V

2

X6S-CERM
0603

CRITICAL

R7320

0.00075

1%
1W
MF

0612-1

2 1
4 3

CPUVR_ISNS2_N

1

R7324

3.9

1%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

1

R7326

10K

1%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

NOSTUFF

CRITICAL

1

C7336

10UF

20%
16V

2

X6S-CERM
0603

CRITICAL

R7330

0.00075

1%
1W
MF

0612-1

1

1

R7336

10K

1%
1/20W
MF
201

2

2

NO_XNET_CONNECTION=TRUE

1

2

CPUVR_ISUMN

CPUVR_ISEN2
CPUVR_ISUMP

21
43

CPUVR_ISNS3_N

1

R7334

3.9

1%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

NOSTUFF

CRITICAL

CRITICAL

L7320

PIMS103T-SM

152S1538

CPUVR_PH2_SNUB

CRITICAL

L7330

PIMS103T-SM

152S1538

1

C7323

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

DIDT=TRUE

NOSTUFF

1

C7322

0.001UF

10%
50V

2

X7R-CERM
0402

NO_XNET_CONNECTION=TRUE

CPUVR_PH3_SNUB

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

C

PHASE 2

3

VDRV

U7320

FDMF6808N

PQFN

CRITICAL

353S3836

58

58 59

IN

IN

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_PWM2

CPUVR_FCCM

C7321

0.22UF

10%
16V

CERM

402

R7321

1 2

1/16W
MF-LF

21

CPUVR_PHASE2_K

0

5%

402

CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

4

BOOT

39

DISB*

6

GH

NC

36

GL

NC

7

PHASE

40

PWM

1

ZCD_EN*

38

THWN*

NC

2

VCIN

CGND

5

B

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

37

18

17

16

41

PHASE 3

R7331

0

C7331

0.22UF

10%
16V

CERM

402

1 2

1/16W
MF-LF

21

CPUVR_PHASE3_K

5%

402

CPUVR_BOOT3

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT3_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_PWM3

58

IN

CPUVR_FCCM

58 59

A

IN

4

BOOT

39

DISB*

6

GH

NC

36

GL

NC

7

PHASE

40

PWM

1

ZCD_EN*

38

THWN*

NC

2

VCIN

U7330

FDMF6808N

CRITICAL

353S3836

CGND

5

37

18

17

16

41

PGND

VDRV

PQFN

C7320

X6S-CERM

3

1UF

0402

PGND

10%
16V

25242322212019

C7330

X6S-CERM

1

2

0.36UH-20%-36A-0.00108OHM

CPUVR_PHASE2
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

NOSTUFF

R7322

1/10W
MF-LF

2.2

1

5%

603

2

VSWH

VIN

8

NC

9
10
11
12
13
14
42

15

NC

29
30
31
32
33
34
35
43

282726

1

1UF

10%
16V

2

0402

0.36UH-20%-36A-0.00108OHM

CPUVR_PHASE3

MIN_LINE_WIDTH=1.5 MM

8

NC

9
10
11

VIN

12
13
14
42

15

NC

29
30
31

VSWH

32
33
34
35
43

25242322212019

282726

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

NOSTUFF

R7332

1/10W
MF-LF

2.2

1

5%

603

2

CRITICAL

1

C7324

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPVCC_S0_CPU_PH2

21

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

CRITICAL

1

C7333

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPVCC_S0_CPU_PH3

21

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

45 96 45 59 96

DIDT=TRUE

NOSTUFF

1

C7332

0.001UF

10%
50V

2

X7R-CERM
0402

NO_XNET_CONNECTION=TRUE

CRITICAL

1

C7325

10UF

20%
16V

2

X6S-CERM
0603

CPUVR_ISNS2_P

R7325

1K

1%

1/20W

MF

201

CRITICAL

1

C7334

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CPUVR_ISNS3_P

OUT OUT

R7335

6 3

8 7 6 5 4 3

12

D

PP1V35_S3

21 45 60 66 84 86

PP5V_S3

21 36 66 67 84 86

BYPASS=U7400.12:10:5MM

C7400

10UF

20%

6.3V

CERM-X6S

0402

1

2

C

MEMVTT_EN

21 85

IN

DDRREG_EN

67

IN

1

1

C7415

0.1UF

10%
16V

2

X7R-CERM

0402

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

B

VOLTAGE=0V

R7415

19.6K

1%
1/16W
MF-LF
402

2

1

R7416

60.4K

1%
1/16W
MF-LF
402

2

1

C7416

0.01UF

10%
16V

2

X7R-CERM
0402

(VDDQ/VTTREF Enable)

1

R7417

200K

1%
1/16W
MF-LF
402

2

BYPASS=U7400.2:10:5MM

(VTT Enable)

DDRREG_1V8_VREF

DDRREG_FB
DDRREG_MODE

DDRREG_TRIP

1

R7418

52.3K

1%
1/16W
MF-LF
402

2

C7401

10UF

6.3V

CERM-X6S

0402

V5IN

17

S3

16

S5

6

VREF

8

REFIN

19

MODE

18

TRIP

20%

1

2

TPS51916

CRITICAL

PGND

10

2

VLDOIN

U7400

QFN

VTT

GND

7

4

VBST
DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

SW

VTT

XW7400

1512
14
13

11
20
9
3
1

86
84

5

DDR3L (1V35 S3) REGULATOR

PPVIN_S5_HS_COMPUTING_ISNS

44 58 59 62 84

CRITICAL

1

15UF

20%
16V

2

TANT

R7425

DIDT=TRUE
DIDT=TRUE

20%
X6S

0402

POLY-TANT

CASE-D2E-SM

SM

0

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

21

DIDT=TRUE

1

C7462

4V

2

PLACE_SIDE=BOTTOM

C7460, C7461, C7462, C7463 close to memory
NOTE:MIRROR C7460, C7462 and C7461, C7463

1

C7430

68UF

20%
16V

2

DDRREG_VBST_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

1

10UF

20%

4V

2

X6S

0402

PLACE_NEAR=U7400.3:3mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST
DDRREG_DRVH
DDRREG_LL

DDRREG_DRVL
DDRREG_PGOOD
DDRREG_VDDQSNS
PPVTT_S0_DDR

DDRREG_VTTSNS
PPVTTDDR_S3

10mA max load

2

C7450

0.22UF

SM

1

BYPASS=U7400.5:7:5mm

CRITICAL

C7435

GATE_NODE=TRUE
SWITCH_NODE=TRUE

GATE_NODE=TRUE

67

OUT

SM

21

PLACE_NEAR=C7461.1:3mm

XW7460

PLACE_NEAR=C2730.1:1mm

C7460

PLACE_SIDE=TOP

1

10%
16V

2

CERM

402

10UF

CRITICAL

C7431

68UF

20%
16V

POLY-TANT

CASE-D2E-SM

C7425

0.1UF

10%
25V

X7R-CERM

0402

(DDRREG_LL)
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

PLACE_SIDE=TOP

PLACE_NEAR=C2724.1:3mm

1

C7461

10UF

20%
4V

2

X6S
0402

PLACE_SIDE=BOTTOM

1

C7464

10UF

20%
4V

2

X6S
0402

NOTE: MIRROR C7432 and C7434

1

1

C7432

1.0UF

10%
25V

2

2

X6S
0402

21

(DDRREG_DRVH)

C7463

10UF

0402

C7465

10UF

0402

20%
X6S

20%
X6S

4V

4V

3

4

5

1

2

1

PLACE_NEAR=U7400.3:3mm

2

1

C7433

0.001UF

10%
50V

2

X7R-CERM
0402

CSD58872Q5D

TG

TGR

BG

1

C7434

1.0UF

10%
25V

2

X6S
0402

CRITICAL

Q7430

VIN

SON5X6

VSW

PGND

9

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

1

6
7
8

DDRREG_VSW

SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

152S0905

CRITICAL

L7430

0.68UH-18A-3.3MOHM

PCMB103T

21

CRITICAL

1

C7440

270UF

20%
2V

2

TANT
CASE-B4-SM

CRITICAL

C7441

270UF

CASE-B4-SM

R7401

10

1%

1/20W

MF

201

TANT

20%

21

PP1V35_S3

1

1

C7445

10UF

20%

2V

4V

2

2

X6S
0402

1

C7447

10UF

20%
4V

2

X6S
0402

1

C7446

0.001UF

10%
50V

2

X7R-CERM
0402

Vout = 1.35V
18A max output
(Q7335 limit)
f = 400 kHz

D

C

21 45 60 66 84 86

B

A

SYNC_MASTER=CLEAN_X305

PAGE TITLE

1.35V DDR3L SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=01/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

74 OF 119

SHEET

60 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

VOUT = 5.0V
11A MAX OUTPUT

F = 400 KHZ

150UF-0.035OHM

C

CRITICAL

POLY-TANT

CASE-B2-SM

150UF-0.035OHM

C7554

6.3V

1

20%

2

CASE-D3L-SM

NO STUFF
CRITICAL

1

C7555

150UF-0.035OHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

B

PPVIN_S5_HS_OTHER5V_ISNS

44 84

37 38 51 61 66 67
69 81 84 86

CRITICAL

C7543

PP5V_S4

C7551

CERM-X6S

15UF

20%
16V

TANT

SM

CRITICAL

10UF

20%

6.3V
0402

CRITICAL

1

C7544

2

POLY-TANT

CASE-D2E-SM

1

2

68UF

20%
16V

1

2

CASE-D2E-SM

CRITICAL

20%

6.3V

1

C7550

2

CERM-X6S

1

C7571

0.001UF

10%
50V

2

X7R-CERM
0402

CRITICAL

1

10UF

20%

6.3V
2

0402

1

R7522

10

5%
1/16W
MF-LF
402

2

PLACE_NEAR=L7520.1:3MM

XW7520

PLACE_NEAR=L7520.1:3MM

2

SM

1

1

C7553

20%

6.3V

2

POLY-TANT
CASE-B2-SM

CRITICAL

C7552

330UF

POLY-TANT

P5VS4_VFB1_R

1

R7520

40.2K

0.1%
1/16W
MF
0402

2

1

R7521

10K

0.1%
1/16W
MF
0402

2

NOTE: Change R7522 to XW7522 at PVT

NOTE: MIRROR C7540 and C7541

CRITICAL

POLY-TANT

1

2

2

XW7521

1

1

1

C7542

68UF

20%
16V

CRITICAL

L7520

2.2UH-20%-13A-9MOHM

PCMB103T-SM

P5VS4_VSW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PLACE_NEAR=L7520.2:3MM

SM

P5VS4_CSP1_R

DIDT=TRUE

C7541

2

2

NO STUFF

1

R7599

1

5%
1/10W
MF-LF
603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

1.0UF

10%
25V
X6S
0402

NO STUFF

C7599

0.0033UF

X7R-CERM

CRITICAL

1

6
7
8

10%
50V

0402

1

C7540

1.0UF

10%
25V

2

X6S
0402

Q7520

CSD58872Q5D

VIN

SON5X6

VSW

PGND

1

2

1

C7570

0.001UF

10%
50V

2

X7R-CERM
0402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

TG

3

TGR

4

BG

5

9

1

R7556

4.75K

1%
1/16W
MF-LF

402

2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

P5VS4_VBST

DIDT=TRUE

1

C7524

0.1UF

10%
25V

2

X7R-CERM
0402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

C7518

0.15UF

10%
10V
X5R
402

R7547

3.24K

1%
1/16W
MF-LF

402

R7545

21

21

C7500

1UF

0603

SKIP_5V3V3:AUDIBLE

1

21

5%
1/16W
MF-LF

402

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

C7537

15PF

50V
CERM
0402

1

10%
25V

2

X7R

SKIP_5V3V3:INAUDIBLE

1

R7500

0

5%

1/20W

MF

0201

2

67

IN

67

OUT

1

R7537

10K

1%
1/16W
MF-LF
402

2

P5VS4_COMP1_R

1

1

C7536

5%

2

4700PF

10%
100V

2

CERM
402

(P5VP3V3_VREF2) (P5VP3V3_VREF2)

PP5V_S4

37 38 51 61 66 67 69 81 84
86

1

R7501

0

5%

1/20W

MF

0201

2

P5VP3V3_SKIPSEL

P5VS4_VBST_R

DIDT=TRUE

P5VS4_DRVH

DIDT=TRUE

P5VS4_LL

DIDT=TRUE

P5VS4_DRVL

DIDT=TRUE

P5VS4_CSP1
P5VS4_CSN1

P5VS4_VFB1
P5VS4_COMP1

P5VS4_EN
P5VS4_PGOOD

1

R7536

12.1K

1%
1/16W
MF-LF

402

2

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

29

23

2

VIN

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4
5

XW7500

PLACE_NEAR=U7501.28:1MM

CRITICAL

U7501

GND

28

SM

VREG5

QFN

TPS51980

THRM_PAD

2

1

22

VREG3

33

VBST2VBST1

DRVH2DRVH1

DRVL2

COMP2COMP1

PGOOD2PGOOD1

CSP2
CSN2CSN1

P5VP3V3_VREG3
P5VP3V3_VREF2

13

VREF2

12

EN

26

DIDT=TRUE

24

DIDT=TRUE

25

SW2SW1

EN2EN1

DIDT=TRUE

27

DIDT=TRUE

18
17

3

RF

16
15

21
20

1

C7501

0.22UF

10%
16V

2

CERM

402

SMC_PM_G2_EN

P3V3S5_VBST_R
P3V3S5_DRVH
P3V3S5_LL

GATE_NODE=TRUE

P3V3S5_DRVL
P3V3S5_CSP2

P3V3S5_CSN2
P3V3S5_RF

P3V3S5_VFB2
P3V3S5_COMP2

P3V3S5_EN
S5_PWRGD

1

R7538

12.1K

1%
1/16W
MF-LF
402

2

P3V3S5_COMP2_R

1

C7503

2.2UF

20%
10V

2

CER-X6S
0402

IN

SWITCH_NODE=TRUE

GATE_NODE=TRUE

IN

OUT

R7539

C7538

4700PF

10%
100V
CERM

402

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

40 41 67

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

67

40 67

1

20.0K

1%
1/16W
MF-LF

402

2

1

2

PP5V_S5

VOUT = 5V
100MA MAX OUTPUT

1

C7505

10UF

20%

6.3V

2

CERM-X6S
0402

R7564

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE
GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

R7506

249K

1%
1/16W
MF-LF

402

2

1

C7539

47PF

5%
50V

2

CER
0402

PPVIN_S5_HS_OTHER3V3_ISNS

44 84

66 84 86

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM

1

21

P3V3S5_VBST

DIDT=TRUE

5%
1/16W
MF-LF

402

C7588

0.15UF

R7546

C7564

0.1UF

X7R-CERM

0402

10%
10V
X5R
402

1K

1%
1/16W
MF-LF

402

10%
25V

21

1

2

21

1

10

8

1

R7516

4.02K

1%
1/16W
MF-LF
402

2

P3V3S5_CSP2_R

DIDT=TRUE

NOTE: MIRROR C7581 and C7586

1

C7581

1.0UF

10%
25V

2

X6S
0402

15UF

TANT

20%
16V

SM

CRITICAL

1

C7585

2

CRITICAL

C7584

CRITICAL

Q7560

NTMFD4951NF

DFN8

D1

2
3
4

G1

S1/D2

G2

9

5
6

S2

7

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

NO STUFF

1

C7598

0.001UF

10%
50V

2

X7R-CERM
0402

15UF

TANT

1

20%
16V

2

SM

1.0UH-22A

NO STUFF

1

C7586

1.0UF

10%
25V

2

X6S
0402

CRITICAL

C7580

68UF

POLY-TANT

CASE-D2E-SM

152S0754

CRITICAL

L7560

PCMC063T-SM

R7598

10

5%
1/10W
MF-LF

603

XW7560

1

20%
16V

2

CASE-D2E-SM

2 1

1

2

PLACE_NEAR=L7560.1:3MM

2

SM

1

CRITICAL

C7582

68UF

20%
16V

POLY-TANT

PLACE_NEAR=L7560.2:3MM

PLACE_NEAR=L7560.2:3MM

2

XW7561

SM

1

1

R7562

10

5%
1/16W
MF-LF
402

2

P3V3S5_VFB2_R

1

1

C7583

0.001UF

10%
50V

2

2

X7R-CERM
0402

PP3V3_S5

VOUT = 3.3V
10A MAX OUTPUT
F = 400 KHZ

150UF-0.035OHM

X7R-CERM

0402

10UF

20%

6.3V
CERM-X6S
0402

10%
50V

1

2

C7572

0.001UF

1

C7590

2

150UF-0.035OHM

R7560

23.2K

1/16W
MF-LF

CRITICAL

C7593

POLY-TANT

CASE-B2-SM

CRITICAL

1

C7592

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

CRITICAL

C7594

POLY-TANT

CASE-B2-SM

1

C7591

2

1

1%

402

2

64 66 67 82 84
12 14 15 17 18
19 21 31 32 33
85 86 96

20%

6.3V

20%

6.3V

10UF

20%

6.3V
CERM-X6S
0402

D

1

C

2

1

2

B

1

R7561

10K

1%
1/16W
MF-LF

402

2

NOTE: Change R7562 to XW7562 at PVT

A

SYNC_MASTER=CLEAN_X425

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/04/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

75 OF 119

SHEET

61 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

1V05 S0 REGULATOR

PPVIN_S5_HS_COMPUTING_ISNS

44 58 59 60 84

PP5V_S0

18 19 36 49 58 59 63 66 67 73

PLACE_NEAR=U1100.AJ12:1MM

XW7601

SM

XW7602

SM

21

P1V05S0_SENSE_P

96

21

P1V05S0_SENSE_N

96

NO_XNET_CONNECTION=TRUE

1

R7604

3.01K

1%
1/16W
MF-LF

402

2

<Ra> <Ra>

1

R7605

2.74K

1%
1/16W
MF-LF

402

2

Vout = 0.5V * (1 + Ra / Rb)

NO_XNET_CONNECTION=TRUE

1

R7644

3.01K

1%
1/16W
MF-LF
402

2

1

R7645

2.74K

1%
1/16W
MF-LF
402

2

<Rb><Rb>

1

C7604

10PF

CERM
0402

50V

1

C7605

5%

10PF

5%
50V

2

2

CERM
0402

67

IN

67

OUT

BYPASS=U7600.13:1:5mm

C7602

2.2UF

CER-X6S

0402

1

C7603

0.047UF

10%
16V

2

X7R-CERM
0402

20%
10V

1

2

PP1V05_S0

10 14 15 17 18 41 62
67 84 86

C

PLACE_NEAR=U1100.AK14:1MM

B

79 80 84 85 86

PP5V_S0_P1V05S0_VCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

P1V05S0_EN
P1V05S0_FB
P1V05S0_SREF
P1V05S0_VO
P1V05S0_OCSET
P1V05S0_PGOOD
P1V05S0_RTN
P1V05S0_FSEL

NO STUFF

1

R7603

0

5%
1/16W
MF-LF
402

2

P1V05S0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

1

R7601

2.2

5%
1/16W
MF-LF

402

2

13

VCC

U7600

ISL95870

3 12

EN

CRITICAL

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

GND

1

XW7600

SM

PLACE_NEAR=U7600.1:1mm

UTQFN

21

PVCC

PGND

14

UGATE

PHASE

LGATE

16

1

C7601

2

BYPASS=U7600.14:16:5mm

BOOT

10UF

20%

6.3V
CERM-X6S
0402

11

10

15

P1V05S0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

R7630

1/10W
MF-LF

603

P1V05S0_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

P1V05S0_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P1V05S0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

(PCHVCCIOS0_OCSET)

(PCHVCCIOS0_VO)

1

C7630

1

1UF

0

5%

10%
16V

2

CER-X6S
0402

2

CRITICAL

NTMFD4951NF

G1

1

10

S1/D2

G2

8

Q7630

DFN8

D1

S2

376S00043

(P1V05S0_LL)

R7641

OCP = R7641 x 8.5uA / R7640
OCP = 14.4A

2
3
4
9

5
6
7

1.37K

1/20W

0.68UH-25A-5.5MOHM

1

1%
MF

C7640

201

2

0.0018UF

2 1

10%
50V

X7R-CERM

0402

CRITICAL

C7620

68UF

POLY-TANT

CASE-D2E-SM

CRITICAL

L7630

PCMC063T-SM

152S0955

P1V05S0_CS_P

45 62 96

P1V05S0_CS_N

45 62 96

1

R7642

1.37K

1%
1/20W
MF
201

2

20%
16V

CRITICAL

1

C7621

68UF

20%

2

16V

POLY-TANT

CASE-D2E-SM

21

PP1V05_S0_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

NOTE: MIRROR C7624 and C7625

1

1

C7622

1000PF

5%
25V

2

2

CERM
0402

BYPASS=Q7630.2:5:6mm

MAKE_BASE=TRUE
MAKE_BASE=TRUE

BYPASS=Q7630.2:5:6mm

CRITICAL

R7640

0.001

1%

1W
MF-3
0612

PLACE_NEAR=L7630.2:1.5mm

1

C7624

1.0UF

10%
25V

2

X6S
0402

12
34

C7623

1000PF

CERM
0402

BYPASS=Q7630.2:5:6mm

1

5%

25V

2

1

C7625

1.0UF

10%
25V

2

X6S
0402

CRITICAL

C7649

270UF

CASE-B4-SM

CRITICAL

1

C7648

270UF

20%
2V

2

TANT
CASE-B4-SM

P1V05S0_CS_N

P1V05S0_CS_P

20%

TANT

1

2V

2

PP1V05_S0

Vout = 1.05V
12A MAX OUTPUT
f = 500 kHz

45 62 96

OUT

45 62 96

OUT

62 67 84
10 14 15
17 18 41
86

C

B

A

6 3

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

1V05V POWER SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

76 OF 119

SHEET

62 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PPVIN_S0_LCDBKLT (9-12.6V LCD Backlight Input)

- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)

- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)

BOM options provided by this page:

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds
BKLT:PROD - Stuffs 0 ohm series R for production

D

PPBUS_G3H

30 44 47 56 57 65 84
86

C

B

CRITICAL

F7700

3AMP-32V

0603

21

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.6V

ISNS_LCDBKLT_P

96

OUT

ISNS_LCDBKLT_N

96

OUT

CRITICAL

69 85 86

IN

69 85 86

BI

R7700

82 86

40

0.025

1%
1W
MF

0612-1

21
43

LCD_BKLT_EN

IN

SMC_SYS_KBDLED

IN

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

I2C_BKLT_SCL

I2C_BKLT_SDA

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.6V

1

C7700

1000PF

10%
16V

2

X7R-1
0201

R7742

0

5%

1/20W

MF

0201

GND_BKLT_SGND

63

R7747

0

5%

1/20W

MF

0201

GND_BKLT_SGND

63

1

1

R7760

1.8K

1/20W

201

5%
MF

R7761

1.8K

5%
1/20W
MF
201

2

2

Q7706

FDC638APZ_SBMS001

4

1

R7701

80.6K

1%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.4 MM

1

R7702

63.4K

1%
1/16W
MF-LF
402

2

21

21

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

GND_BKLT_SGND

63

1

R7740

1M

5%
1/20W
MF
201

2

(PPBUS_S0_BKLT_PWR_R)
(PPBUS_S0_BKLT_PWR_F)

NO STUFF

1

C7742

33PF

5%
25V

2

NPO-C0G
0201

NO STUFF

1

C7747

33PF

5%
25V

2

NPO-C0G
0201

R7758

0

1/20W

5%

R7757

0

1/20W

5%

CRITICAL

SSOT6-HF

3

6
5
2
1

LCDBKLT_EN_L

R7743

C7740

402-2

BKLT_SD

BKLT_SENSE_OUT
BKLT_EN_R

BKLT_PWM_KEYB

21

BKLT_SCL

0201

MF

21

BKLT_SDA

0201

MF

PPBUS_SW_BKL

84

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.6V

NOSTUFF

1

C7701

0.001UF

10%
50V

2

CERM
402

1

0

5%
1/16W
MF-LF

402

2

1

1UF

10%
10V

2

X5R

1

C7710

4.7UF

10%
25V

2

X6S-CERM
0603

PP5V_S0

1

R7744

0

5%
1/16W
MF-LF

VOLTAGE=5V

402

MIN_LINE_WIDTH=0.4 MM

2

MIN_NECK_WIDTH=0.2 MM

PP5V_S0_BKLT_VDDA
PP5V_S0_BKLT_VDDD

1

C7741

1UF

10%
10V

2

X5R
402-2

5

18

VDDD

VDDA

U7701

SD
VSENSE_N
VSENSE_P

SENSE_OUT

EN
PWM_KEYB

SCL

(IPU)

SDA

(IPU)

CRITICAL

353S4159

GND_SW

GND_SW

24

23

XW7700

QFN

ISET_KEYB

GND_SW2

GNDD

3

7

SM

22

LP8548B1SQ_-03

11

9

10

19

17
12

15
16

22UH-20%-2.4A-0.105OHM

1

C7711

4.7UF

10%
25V

2

X6S-CERM
0603

2

SW

1

SW

21

FB

4

GD

20

BKLT_ISET_KEYB

13

BKLT_KEYB1

KEYB1

14

BKLT_KEYB2

KEYB2

6

SW2

8

FB2

THRM

GNDA

PAD

25

21

GND_BKLT_SGND

63

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

152S1527

CRITICAL

L7710

DEM8030C-SM

1

C7712

0.1UF

10%
25V

2

X5R
402

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

BKL_SW

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

BKL_FET_CNTL_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

R7703

0

5%
1/16W
MF-LF
402

2

BKL_FET_CNTL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

BKL_FB

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PART NUMBER

116S0004

21

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=45V

SWITCH_NODE=TRUE
DIDT=TRUE

PLACE_NEAR=L7710.2:3MM

4

5

321

QTY

2

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

PLACE_NEAR=L7710.2:3MM

CRITICAL

D7701

POWERDI-123

KA

DFLS2100

CRITICAL

Q7701

SI7812DN

PWRPK-1212-8

R7708

18.2K

1%
1/16W
MF-LF

402

R7709

150K

1%
1/16W
MF-LF

402

DESCRIPTION

PLACE_NEAR=D7701.K:3MM

1

2

1

2

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

CRITICAL

1

C7715

2.2UF

10%
100V

2

X7R
1210-1

1

C7730

12PF

2%
100V

2

CERM
0402

REFERENCE DES

R7723,R7724

CRITICAL

1

C7716

2.2UF

10%
100V

2

X7R
1210-1

PLACE_NEAR=D7701.K:5MM

1

C7731

12PF

2%
100V

2

CERM
0402

CRITICAL

1

C7718

2.2UF

10%
100V

2

X7R
1210-1

PLACE_NEAR=D7701.K:3MM

PLACE_NEAR=D7701.K:5MM

BKLT:ENG

R7723

10.2

21

0.1%

1/16W

402

1

R7741

31.6K

1%
1/20W
MF
201

2

PPVOUT_BKLT_FB2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=40V

KBDBKLT_SW

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

C7720, C7721 SHOULD BE PLACED MIRRORED C7723, C7724 SHOULD BE PLACED MIRRORED

BKLT:ENG

TF

R7724

10.2

0.1%

1/16W

R7783

0

5%
1/16W
MF-LF

402

1

C7720

2.2UF

10%
25V

2

X5R-CERM
603

21

TF

402

21

PP5V_S0_KBDLED_R

1

C7721

2.2UF

10%
25V

2

X5R-CERM
603

KBDBKLT_RETURN1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

KBDBKLT_RETURN2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

152S1701

CRITICAL

10UH-20%-1.4A-0.17OHM

1

C7722

0.1UF

10%
16V

2

X5R-CERM
0201

L7720

PST041H-CDH46D14-SM

39 86

39 86

2

XW7720

SM

PLACE_NEAR=D7720.K:2MM

1

371S0572

CRITICAL

D7720

21

SOD-123

KA

RB160M-60G

CRITICAL

CRITICAL

1

C7719

2.2UF

10%
100V

2

X7R
1210-1

1

2

1

C7723

1.0UF

10%
50V

2

X7R
0805

C7726

1.0UF

10%
50V
X7R
0805

BOM OPTION

BKLT:PROD

1

C7717

1000PF

10%
100V

2

X7R-CERM
0603

PLACE_NEAR=D7701.K:5MM

1

C7727

1.0UF

10%
50V

2

X7R
0805

1

C7724

1.0UF

10%
50V

2

X7R
0805

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=55V

1

C7728

12PF

2%
100V

2

CERM
0402

PPVOUT_S0_KBDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=40V

1

C7725

0.001UF

10%
50V

2

X7R-CERM
0402

1

C7729

12PF

2%
100V

2

CERM
0402

69 86

D

C

B

39 86

A

SYNC_MASTER=CLEAN_X425

PAGE TITLE

LCD/KBD Backlight Driver

Apple Inc.

R

82

IN

LCD_BKLT_PWM

5%

0201

R7780

0

21

MF

LCD_BKLT_PWM_R

1/20W

NOTICE OF PROPRIETARY PROPERTY:

69 86

OUT

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

77 OF 119

SHEET

63 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

1.5V S0 Regulator

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 66 67 82 84 85 86 96

CRITICAL

1

1

VIN

U7810

ISL8009B

C

P3V3S0_P1V5_S0_EN

66 67

IN

P1V5S0_PGOOD

67

OUT

DFN

2

EN

CRITICAL

3

POR

4 5

SKIP

GND

7

THRM_PAD

9

LX

VFB

RSI

C7850

10UF

20%

6.3V

2

CERM-X6S
0402

8

6

P1V5S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P1V5S0_FB

CRITICAL

1

C7851

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

L7870

2.2UH-3A

PCMB042T-IHLP1616BZ

C7876

27PF

CERM

0402-1

50V

21

1

R7880

1

100K

5%

1%
1/16W

2

MF-LF
402

2

<Ra>

1

R7881

113K

1%
1/16W
MF-LF
402

2

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.508V
Max Current = 1.5A

Freq = 1.6MHZ

PP1V5_S0

CRITICAL

1

C7871

47UF

20%

6.3V

2

X5R-CERM
0805-1

CRITICAL

1

C7872

12PF

5%
NP0-C0G

2

0201
25V

C7872, C7873 FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

CRITICAL

1

C7873

12PF

5%
NP0-C0G

2

0201
25V

11 12 13 15 17 19 52 67 81 84
86

Lynx Point-H requires JTAG pull-ups to be powered at 1.05V in SUS.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V SUS, which burns 100mW in all S-states.

PP3V3_SUS

11 12 13 14 15 17 50 66 67 84

1.05V SUS LDO

CRITICAL

XDP_PCH

U7840

TPS720105

SON

4

XDP_PCH

C7840

1UF

6.3V
CERM

10%

402

BIAS

6

IN

3

EN

1

2

5

THRM

PADGND

7

OUT

1

2

NC

NC

PP1V05_SUS

18 84

Vout = 1.05V
Max Current = 0.35A

XDP_PCH

1

C7841

2.2UF

10%

6.3V

2

X5R
402

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=CLEAN_X305

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

78 OF 119

SHEET

64 OF 97

124578

8 7 6 5 4 3

12

321

CRITICAL

Q7979

SI7121DN

PWRPK-1212-8

S

G

4

5

D

1

C7970

0.01UF

10%
16V

2

X7R-CERM

0402

1

2

NOSTUFF

CRITICAL

C7979

10UF

20%
16V
X6S-CERM
0603

PPBUS_S4_TPAD

45 84

D

C

86

PP3V3_S4

20 33 38 41 42 45
46 66 67 81 84 85

1

R7976

100K

5%
1/20W
MF
201

2

D

PVIN_S4_TPAD_EN

PPBUS_G3H

30 44 47 56 57 63 84 86

1

R7922

0

5%
1/16W
MF-LF
402

SMC_ACTUATOR_DISABLE_L

40

C

BI

(Open-Drain)

TPAD_ACTUATOR_THRMTRIP_L

38 86

IN

(Open-Drain)

2

1

R7926

0

5%
1/16W
MF-LF
402

2

CRITICAL

Q7972

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

G S

3

D

2

RC Value not Final

1

R7972

47K

5%
1/16W
MF-LF

402

2

PVIN_S4_TPAD_EN_L

R7970

33K

2 1

5%
1/16W
MF-LF

402

C7971

0.033UF

10%
16V
X5R
402

1

2

PVIN_S4_TPAD_SS

SIZE

B

A

D

B

A

PBUS ONLY CONTROL INPUTS

SYSTEM STATE

G3H, S5

S4, S3, S0

S4, S3, S0

S4, S3, S0

SMC_ACTUATOR_DISABLE_L

X

Hi-Z

0 V

X

TPAD_ACTUATOR_THRMTRIP_L

X

Hi-Z

X

0 V

T101 POWER

0 V

PBUS

0 V

0 V

SYNC_MASTER=CLEAN_MAXWELL

PAGE TITLE

X249 POWER SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=07/02/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

79 OF 119

SHEET

65 OF 97

124578

8 7 6 5 4 3

12

3.3V S4 FET

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

1

R8002

220K

6

D

G

2

S

1

VER 1

5%
1/16W
MF-LF

402

2

P3V3S4_EN_L

IN

Q8002

DMN5L06VK-7

SOT563

S4_PWR_EN

D

31 32 67

0.033UF

R8000

1

C8009

47K

5%
1/16W
MF-LF

402

10%
16V
X5R
402

2

1

2

P3V3S3_S4

3.3V S3 FET

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

1

R8012

3

1

G S

D

2

47K

1/16W
MF-LF

5%

402

2

P3V3S3_EN_L

R8010

Q8012

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

P3V3S3_EN

67

IN

C8011

0.033UF

39K

5%
1/16W
MF-LF

402

16V

10%

X5R
402

21

1

2

P3V3S3_SS

5V S3 FET

C

67

IN

37 38 51 61 66 67 69 81 84 86

Q8052

DMN5L06VK-7

SOT563

P5VS3_EN

PP5V_S4

2

1

R8052

6

200K

VER 1

1/16W
MF-LF

402

5%

2

P5VS3_EN_L

R8050

D

G

S

1

C8051

0.033UF

5.1K

5%
1/16W
MF-LF

402

1

10%
16V

2

X5R
402

21

P5VS3_SS

1.35V S3/S0 FET

PP5V_S5

61 84 86

1

C8001

0.1UF

20%
10V

2

CERM

402

P1V35CPU_SLEW_CTL

CPUVDDQ_EN

21

B

IN

Slew rate :

0.8V/ms = 19.75nF

0.018UF

C8002

1

10%
16V

2

X7R
402

1

VDD

U8001

SLG5AP1438V

TDFN

CAP

CRITICAL

GND

8

PP1V35_S3

37

D

52

SON

376S0945

CRITICAL

Q8000

SIA413DJ

SC70-6L

74

S

D

G

3

C8000

0.01UF

21

10%
16V

X7R-CERM

0402

CRITICAL

Q8010

SIA413DJ

SC70-6L

74

S

D

G

3

C8010

0.01UF

10%
16V

X7R-CERM

SC70-6L

S

0402

D

1

CRITICAL

Q8050

SIA427DJ

74

G

3

C8050

0.01UF

21

10%
16V

X7R-CERM

0402

PP1V35_S3RS0_FET

84

1

21

1

PP5V_S3

PP3V3_S4

MOSFET
CHANNEL
RDS(ON)
LOADING

PP3V3_S3

CRITICAL

1

C8012

12PF

5%
NP0-C0G

2

0201
25V

MOSFET
CHANNEL
RDS(ON)
LOADING

SENSOR_NONPROD_R

EDP is per J45 Power Budget rev5

20 33 38 41 42 45 46 65 67 81
84 85 86

3.3V S4 FET

SiA427
P-TYPE 8V/5V

26 mOhm @1.8V

1.3 A (EDP)

SSD_PWR_EN

13 18

13 20 21 43 45 46 81 82 84 86

FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

PM_SLP_S3_BUF_L

51 67 81 82 86

3.3V S3 FET

MOSFET
CHANNEL
RDS(ON)
LOADING

21 36 60 67 84 86

SiA427
P-TYPE 8V/5V
26 mOhm @1.8V

1.1 A (EDP)

5V S3 FET

SiA427
P-TYPE 8V/5V
26 mOhm @1.8V

0.3 A (EDP)

1.35V S3/S0 FET

86
21 45
60 84

Integ. MOSFET
CHANNEL
RDS(ON)
LOADING

R8005

0.002

1%
1W

CYN

0612

21
43

SLG5AP1438V
N-TYPE

9.6 mOhm

4.8 A (EDP)

PP1V35_S3RS0_CPUDDR

ISNS_CPUDDR_N
ISNS_CPUDDR_P

SSD_PWR_EN:GPIO

R8073

0

1/20W

0201

0201

OUT

OUT

5% MF

SSD_PWR_EN:S0

R8074

0

1/20W

5% MF

34

6 8

10 21 67 84 96

46 96

46 96

PM_SLP_SUS_L

12 44 67

IN

21

66 67 82 84 85 86

PP3V3_S5

12 14 15 17 18 19
21 31 32 33 61 64
96

21

Q8072

DMN32D2LFB4

DFN1006H4-3

SSD_PWR_FET_EN

PP5V_S4

37 38 51 61 66 67 69 81 84 86

67

IN

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

Q8002

DMN5L06VK-7

SOT563

SYM_VER_2

1

G S

Q8052

DMN5L06VK-7

SOT563

P5VS0_EN

5

D

G

3

2

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

68

3

D

S

4

R8072

R8062

270K

5

PP3V3_S5

P3V3_S0GPU_EN

IN

47K

1/16W
MF-LF

1/16W
MF-LF

G

VER 1

5%

402

5%

402

R8022

100K

5%
1/16W
MF-LF

402

1

2

P3V3_SSD_EN_L

1

2

P5V0S0_EN_L

3

D

S

4

3.3V SUS FET

1

2

P3V3SUS_EN_L

3.3V S0 SSD FET

0.033UF

5.0V S0 FET

C8061

0.12UF

R8060

6.2K

VER 1

1UF

6.3V

1

10%

2

X5R
402

C8090

1

C8021

0.033UF

10%
16V

2

X5R
402

R8020

12K

21

5%
1/16W
MF-LF

402

C8071

R8070

33K

5%

1/16W
MF-LF

402

CERM-X5R

5%

1/16W
MF-LF

402

P3V3SUS_SS

1

10%
16V

2

X5R
402

21

P3V3_SSD_SS

1

10%

10.0V

2

402

21

P5V0S0_SS

GPU_3.3V S0 Switch

Max Current = 0.11A

U8090

TPS22904

CSP

A1

VIN

VOUT

CRITICAL

B1

ON

GND

B2

CRITICAL

Q8020

SIA413DJ

SC70-6L

74

S

D

G

3

C8020

0.01UF

21

10%
16V

X7R-CERM

0402

PLACE_NEAR=R5549.2:6mm

CRITICAL

Q8070

SI7615DN

PWRPK-1212-8

S

321

CRITICAL

Q8060

SI7615DN

PWRPK-1212-8

S

321

G

4

0.01UF

G

4

C8070

10%
16V

X7R-CERM

0402

C8060

0.47UF

10%
10V

X5R

0402

D

21

D

21

APN 353S3979

A2

PP3V3_S0GPU

1

PP3V3_SUS

CHANNEL
RDS(ON)
LOADING

PP3V3_S0SW_SSD_R

5

MOSFET
CHANNEL
RDS(ON)
LOADING

PP5V_S0

5

MOSFET
CHANNEL
RDS(ON)
LOADING

NOSTUFF

C8091

0.1UF

1

10%
16V

2

X5R
402

11 12 13 14 15 17 50 64 67 84

3.3V SUS FET

SiA427MOSFET
P-TYPE 8V/5V
26 mOhm @1.8V

0.5 A (EDP)

3.3V S0 SSD FET

SI7615DN
P-TYPE 20V/12V

5.5 mOhm @4.5V
5 A (EDP)

18 19 36 49 58 59 62 63 67 73
79 80 84 85 86

5.0V S0 FET

SI7615DN
P-TYPE 20V/12V

5.5 MOHM @4.5V

2.8 A (EDP)

Part

Type

R(on)
@ 3.6V

Current

47 68 71 72 76 77 79 80 84

45 84

U8090

TPS22904

Load Switch

66 mOhm Typ
90 mOhm Max

0.5A Max

D

C

B

U8030

Part

3.3V S0 Switch

86 96

PP3V3_S5

12 14 15 17 18 19 21 31 32
33 61 64 66 67 82 84 85

A

64 67

P3V3S0_P1V5_S0_EN

IN

C8030

1UF

1

10%
16V

2

X5R
603

U8030

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

CSP

VOUT

GND

C1

C8030 USING 0603 PAKAGE IS FOR DFM TO PROTECT U8030 (CSP)

APN 353S2741

PP3V3_S0

A1

Max Current = 2A

B1

SYNC_MASTER=J45_IG

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

Type
R(on)

@ 2.5V

67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

Power FETs

6 3

TPS22924C
Load Switch

18.5 mOhm Typ

25.8 mOhm Max

SYNC_DATE=07/01/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

80 OF 119

SHEET

66 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

Power State Debug LEDs

PP3V3_S5

DBGLED

PLACE_SIDE=BOTTOM

R8194

0

2 1

5%
1/16W
MF-LF

402

D

DBGLED_S5

DBGLED

A

D8190

GREEN-56MCD-2MA-2.65V
LTQH9G-SM

K

PLACE_SIDE=BOTTOM
SILK_PART=S5_ON

31 32 66 67

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V

DBGLED

1

R8190

20K

5%
1/20W
MF
201

2

DBGLED

Q8190

DMN5L06VK-7

SOT563

S4_PWR_EN

PP3V3_S5_DBGLED

DBGLED_S4

DBGLED

A

D8191

GREEN-56MCD-2MA-2.65V
LTQH9G-SM

K

PLACE_SIDE=BOTTOM
SILK_PART=S4_ON

DBGLED_S4_D

C

PP5V_S0

1

R8151

54.9K

1%
1/16W
MF-LF

402

2

R8152

15.0K

1%
1/16W
MF-LF

VMON_5V_DIV

1

402

2

5.0V Divider:1.07V

96

PP1V35_S3RS0_CPUDDR

6 8

10 21 66

67 84

PP3V3_S0

B

A

1

R8158

15.0K

1%
1/16W
MF-LF

402

2

VMON_3V3_DIV

3V3 Divider:1.07V

1

R8159

7.15K

1%

1/16W
MF-LF

402

2

Thresholds:

96
84
82
68
66
52
49
47
45
43
29
19
15
13

PP3V3_S0 PP3V3_S0

11
12
14
17
20
34

86

44

85

46

84

48

80

51

79

55

73

67

67

69

66

83

63

86

62
58 59

PP5V_S0

18 19
36 49

S0PGOOD_ISL

R8160

6.04K

P5V_VMON divider

3.16V @4.5V

S0PGOOD_ISL

R8161

15.0K

1/16W

VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

keep R8171 DDRCPU 1.35V only

NOSTUFF

C8162

0.1UF

20%
10V

X7R-CERM

0402

PLACE_NEAR=U8160.2:7mm

PP1V35_S3RS0_CPUDDR

6 8

10 21 66 67 84

96

1

S0PGOOD_ISL

R8170

1%
1/16W
MF-LF

402

2

P5V_DIV_VMON

S0PGOOD_ISL

1

R8171

1%

MF-LF

402

2

1V35_VMON divider

0.717V @1.31V

1/16W
MF-LF

12.4K

1/16W

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

66 67 68 69 82 83
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
84 86 96

S0PGOOD_ISL

R8195

10

5%

1

1/16W
MF-LF

402

PLACE_NEAR=U8160.2:4mm

2

PP1V05_S0

10 14 15 17 18
41 62 84 86

1

S0PGOOD_ISL

10K

R8172

1%

6.04K

1%

402

2

P1V5_DIV_VMON

1

S0PGOOD_ISL

2

1/16W
MF-LF

R8173

15.0K

1/16W

402

MF-LF

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=3.3V

21

PP3V3_S0_VMON_P2

1

1%

402

2

P1V05_VID_VMON

1

1%

MF-LF

1V05_VMON divider

402

2

0.716V @1.02V

(For development only)

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

DBGLED

1

R8191

20K

5%
1/20W
MF
201

2

DBGLED_S3

DBGLED

A

D8192

GREEN-56MCD-2MA-2.65V
LTQH9G-SM

K

PLACE_SIDE=BOTTOM
SILK_PART=S3_ON

DBGLED_S3_D

DBGLED

6

Q8190

DMN5L06VK-7

D

SOT563

G

2

12 21 33 37 40 67 81 86

VER 1

S

1

PM_SLP_S4_L

G

5

PM_SLP_S3_BUF_L

51 66 67 81 82 86

CPUVCORE ENABLE

ALL_SYS_PWRGD

18 19 40 58 67 86

MAKE_BASE=TRUE

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

R8153

1K

VMON_Q2_BASE

21

5%
1/16W
MF-LF

402

R8154

1K

21

VMON_Q3_BASE

5%
1/16W
MF-LF

402

R8155

1K

21

VMON_Q4_BASE

5%
1/16W
MF-LF

402

Vbe 0.7V max @2mA
Vce(sat) 0.1V max @1mA
Q1 Vth 0.7~1V @Id 250uA

S0 Rail PGOOD Circuitry

(ISL Version in development)

1

C8160

0.1UF

20%
10V

2

X7R-CERM

0402

S0PGOOD_ISL

PLACE_NEAR=U8160.2:4mm

3

V2MON

5

V3MON

6

S0 Rail PGOOD (BJT Version)

1

R8156

150K

1%
1/16W
MF-LF

402

2

S0PGD_C

6

5

Q2

8

NC

7

Q3

2

NC

1

Q4

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=3.3V

PP3V3_S0_VMON_P7

67

2
VDD

U8160

ISL88042IRTEZ

TDFN

353S2310

CRITICAL

GND

THRM_PAD

4

S0PGOOD_ISL

7

RST*V4MON

9

MF-LF

1

PLACE_NEAR=U8160.7:4mm

C8161

0.1UF

2

20%

10V
X7R-CERM
0402

S0PGOOD_ISL

PLACE_NEAR=U8160.2:4mm

(IPU)

1

MR*

8

DBGLED

1

R8192

20K

5%
1/20W
MF
201

2

3

D

S

4

CRITICAL

3

S0PGOOD_ISL

R8196

10

5%

402

64

62

VMON_MR

ALL_SYS_PWRGD_R

DBGLED_S0

DBGLED

A

D8193

GREEN-56MCD-2MA-2.65V
LTQH9G-SM

K

PLACE_SIDE=BOTTOM
SILK_PART=S0_ON

DBGLED_S0_D

DBGLED

Q8191

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

VER 1

G S

ALL_SYS_PWRGD

ALL_SYS_PWRGD

4

Q8150

Q1

ASMCC0179

DFN2015H4-8

353S2809

S0PGD_BJT_GND_R

R8157

1/16W
MF-LF

1/16W

21

NOSTUFF

1

C8163

0.1UF

20%
10V

2

X7R-CERM

0402

PLACE_NEAR=U8160.2:7mm

P1V5S0_PGOOD from U7810

P1V5S0_PGOOD

IN

P1V05S0_PGOOD

IN

67

S0PGOOD_ISL

R8162

DBGLED

1

R8193

20K

5%
1/20W
MF
201

2

3

D

2

11 12 13 14 15 17 50
64 66 67 84

1

100

5%

402

2

PM_SLP_S3_BUF_L

51 66 67 81
82 86

330

21

ALL_SYS_PWRGD

5%
1/16W
MF-LF

402

67 82 84 85 86 96

PP3V3_S5

12 14 15 17 18 19
21 31 32 33 61 64 66

18 19 40 58 67 86

OUT

18 19 40 58 67 86

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

No stuff C8131, 12ms
Min delay time

U8130 Sense input
threhold is 3.07V

PP3V3_SUS

SUS_PGOOD_CT

NO STUFF

1

C8131

0.001UF

20%
50V

2

CERM
402

PP3V3_S0_VMON_P7

PLACE_NEAR=U8160.7:4mm

NOSTUFF

R8197

100K

5%
1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

402

VMON_MR

R8167

10K

1/16W

MF-LF

100

21

5%

402

100

21

5%

402

67 68 69 82

67

47 48 49
11 12 13 14 15 17 19 20 29 34
43 44 45 46
51 52 55 66
83 84 86 96

R8168

R8169

6 3

Mobile System Power State Table

SMC_ADAPTER_EN

toggle 3Hz

PM_SLP_S5_L:100K pull down on PCH page

PM_SLP_S5_L

12 40

IN

SMC_S4_WAKESRC_EN

40 41

IN

SMC_PM_G2_ENABLE

X
1

1 1
0
1

1

Battery Off (G3HotAC)

BYPASS=U8170.6:3:2.3mm

C8170

0.1uF

State

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (dS4AC)

Deep Sleep (dS4)

Deep Sleep (dS5AC)

Deep Sleep (dS5)

Battery Off (G3Hot)

1

20%
10V

2

CERM

402

3.3V SUS Enable

PM_SLP_SUS_L

IN

MAKE_BASE=TRUE

PM_SLP_SUS_L: 100K pull down on PCH page

PM_SLP_SUS_L
PM_SLP_SUS_L

3.3V SUS Detect

CRITICAL

5 1

SENSE

TPS3808G33DBVRG4

4

CT

1

2

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

1

5%

402

2

OUT

R8136

81 84 86

PP1V5_S0

11 12 13 15
17 19 52 64

R8135

18 19 40 58 67 86

R8134

23.7K

54.9K

61.9K

6

VDD

U8130

SOT23-6

GND

2

PP3V3_S5

1%
1/16W
MF-LF

402

1%
1/16W
MF-LF

402

1%
1/16W
MF-LF

402

BYPASS=U8130.6::2.3mm

RESET*

1

C8134

2

PM_1V5_PGD_L

R8139

1

2

PM_P1V5_PGD_DIV

1

2

1

C8130

0.1uF

20%
10V

2

CERM

402

PM_RSMRST_L

3

TP_SUS_PGOOD_MR_L

MR*

1V5 S0 "PGOOD" Delay

DELAY_1V5S0_PGD

1

2.2UF

10%

6.3V
2

X5R

2.0K

1/16W
MF-LF

402

1

1%

402

2

G

2

PM_1V5_PGD_L_R

3

5

4

SMC_S4_WAKESRC_EN

1
1
10

1
1
10
0
0

1
1
1
1 0 0
1
0
0
0
0

S4 Power Enable

U8170

6

74LVC1G32

2

SOT891

1

NC

5 3

NC

PM_SLP_S3_L

12 21 40 86

IN

PM_SLP_S3_L:100K pull down in PCH page

12 44 66 67 12 44 66 67

OUT

12 44 66 67

OUT

PP3V3_SUS

1

R8133

100K

5%
1/16W
MF-LF

402

2

12 86 91

OUT

PM_RSMRST_L goes to U1100.C21

R8137

100

1/16W
MF-LF

6
D

S
1

CRITICAL

Q8151

DMB53D0UV

SOT-563

VBEon: 0.58~0.7V

1V5 Divider:0.75~0.85V

402

CRITICAL

Q8151

DMB53D0UV

SOT-563

Vgs:0.7V~1.0V

S4_PWR_EN

4

MAKE_BASE=TRUE

P5VS4_EN_D

21

ALL_SYS_PWRGD

5%

PM_SLP_SUS_L

1
1
1

0
0

0
0

BYPASS=U8180.5:3:2.3mm

R8178

100

5%
1/16W
MF-LF

402

11 12 13 14 15 17 50 64 66 67
84

DMN32D2LFB4

PM_SLP_S3_R_L

31 32 44 67

PM_SLP_S4_LPM_SLP_S5_L

1

1
0
0
0
00
0

PLACE_NEAR=R8174.1:6mm

A

D8174

SOD-523

BAT54XV2T1

K

R8175

240

5%
1/16W
MF-LF

402

PP3V3_S5

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

C8180

0.1uF

20%
10V

CERM

402

21

PM_SLP_S3_R_L

MAKE_BASE=TRUE

PM_SLP_S3_L

PLACE_NEAR=U7501.4:6mm

1

R8174

43K

5%
1/16W
MF-LF
402

2

61 67

PLACE_NEAR=U7501.4:6mm

1

2

1
0
0
0
0
0
0
0
0

S4_PWR_EN
S4_PWR_EN
S4_PWR_EN

MAKE_BASE=TRUE

P5VS4_EN

C8174

2.2UF

10%

6.3V
X5R
402

1

U8180

2

1
11
1

0
0
0
0
00

21

1

2

PM_SLP_S3_R_L

PM_SLP_S3_R_L

SMC_PM_G2_EN

40 41 61 67

IN

MAKE_BASE=TRUE

18 19 40 58 67 86

OUT

CHGR VFRQ Generation

VFRQ High: Variable Frequency
VFRQ Low: Fix Frequency

PP3V42_G3H

19 34 37 38 40 41 42
43 50 56 57 67 84 86

Q8131

DFN1006H4-3

SYM_VER_2

1

G S

1

R8131

100K

5%
1/16W
MF-LF
402

2

CHGR_VFRQ

3

D

2

OUT

S3 ENABLE

PM_SLP_S4_L

12 21 33 37 40 67 81 86

PM_SLP_S4_L:100K pull down in PCH page

31 32 66 67

OUT

31 32 66 67

OUT

31 32 66 67

OUT

P5VS4_EN

MC74VHC1G08

SC70-HF

5

4

3

NO STUFF

1

R8180

100K

2

P1V05_EN_D

PLACE_NEAR=R8138.1:6mm

31 32 44 67

OUT

31 32 44 67

OUT

IN

61 67

OUT

S0 ENABLE

(PM_SLP_S3_BUF_L)

5%
1/16W
MF-LF
402

PLACE_NEAR=R8185.2:6mm

A

D8185

SOD-523

BAT54XV2T1

K

R8138

820

5%
1/16W
MF-LF

402

1

2

21

62 67

1

2

1

R8111

5.1K

5%
1/16W
MF-LF
402

2

PLACE_NEAR=U7400.16:6mm

PLACE_NEAR=U7400.16:6mm

1

C8110

0.47UF

10%

6.3V

2

CERM-X5R
402

R8185

130K

5%
1/16W
MF-LF
402

PLACE_NEAR=U7600.3:6mm

P1V05S0_EN

MAKE_BASE=TRUE

C8185

0.82UF

10%

6.3V
X5R
402

PLACE_NEAR=U7600.3:6mm

1

R8112

0

5%
1/16W
MF-LF
402

2

PLACE_NEAR=Q8012.1:6mm

PLACE_NEAR=Q8012.1:6mm

NO STUFF

1

C8112

0.47UF

10%

6.3V

2

CERM-X5R
402

1

2

PLACE_NEAR=Q8052.2:6MM

PLACE_NEAR=Q8052.2:6MM

NO STUFF

1

2

PM_SLP_S3_BUF_L

1

R8186

20K

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

P3V3S0_P1V5_S0_EN

64 66 67

1

C8186

0.68UF

10%

6.3V

2

CERM
402

R8113

0

5%
1/16W
MF-LF
402

66 67

66 67

60 67

C8113

0.47UF

10%

6.3V
CERM-X5R
402

PLACE_NEAR=Q8052.5:6mm

1

R8114

3.3K

2

PLACE_NEAR=J4801.22:10MM

TPAD_VBUS_EN
P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

PLACE_NEAR=J4801.22:10MM

NO STUFF

1

2

66 67

S5 Rail Enables & PGOOD

PP3V42_G3H

19 34 37 38 40 41 42 43 50 56

PLACE_NEAR=U7501.21:7mm

R8140

100

21

5%
1/16W
MF-LF

402

SMC_PM_G2_EN

OUT

P3V3S5_EN

61 67

MAKE_BASE=TRUE

61

NO STUFF

40
41
67

1

C8142

0.0033UF

10%
50V

2

X7R-CERM
0402

PLACE_NEAR=U7501.21:7mm

P3V3S5_EN

OUT

57 67 84 86

PLACE_NEAR=U7501.20:7mm

61 67

S5_PWRGD

40 61 67

WLAN Enable Generation

NOTE: S4 term is guaranteed by S4 pull-up on open-drain AP_PWR_EN signal.

57

60

61

"WLAN" = ("S4" && "AP_PWR_EN" && ("AC" || "S0"))

PM_WLAN_EN

33 40 67

IN

Unused PGOOD signals

DDRREG_PGOOD

IN

P5VS4_PGOOD

IN

PP5V_S3

1

R8120

470K

5%
1/20W
MF
201

2

PP5V_S4

1

2

R8165

470K

5%
1/16W
MF-LF
402

21 36 60 66 84 86

37 38 51 61 66
69 81 84 86

PP3V3_S4

1

R8125

330K

5%
1/20W
MF
201

2

PM_WLAN_EN

MAKE_BASE=TRUE

SYNC_MASTER=J45_IG

PAGE TITLE

Power Control 1/ENABLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

5%
1/20W
MF
201

C8114

0.47UF

10%

6.3V
CERM-X5R
402

1

R8187

0

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

P5VS0_EN

PLACE_NEAR=Q8052.5:6mm

1

C8187

0.68UF

10%

6.3V

2

CERM
402

NO STUFF

R8141

100K

1/16W
MF-LF

12

P5VS3_EN
P3V3S3_EN
DDRREG_EN

51 66 67 81 82 86

OUT

P5VS0_EN
P3V3S0_P1V5_S0_EN

P3V3S0_P1V5_S0_EN
P1V05S0_EN

1

5%

S5_PWRGD-->SMC
SMC-->PM_DSW_PWRGD

402

2

S5_PWRGD

MAKE_BASE=TRUE

20 33 38 41 42 45 46 65 66 81
84 85 86

33 40 67

OUT

SYNC_DATE=07/01/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

38 86

OUT

66 67

OUT

66 67

OUT

60 67

OUT

OUT

OUT

OUT

OUT

<E4LABEL>

<BRANCH>

81 OF 119

67 OF 97

D

66 67

64 66
67

C

64 66
67

62 67

67
40

OUT

61

B

A

SIZE

D

8 7 6 5 4 3

12

GPU Rails Power UP Sequencing

Venus GPU requires rails to come

up in the following order:

1) GPU_3.3V

2) GPU_0V95 (BIF_VDDC) & GPU_1V8 (VDD_CT)

3) GPUVCore

4) VDDCI

D

EG_RAIL1_EN

82

P0V95R1V8GPU_R_EN

68 82

5) FB VRAM MVDD

R8234

0

21

5%

1/16W MF-LF

402

PLACE_NEAR=U8090.B1:7mm

82

P0V95R1V8GPU_R_EN

68

MAKE_BASE=TRUE

R8232

5%

402

PLACE_NEAR=U9400.13:7mm

P3V3_S0GPU_EN P3V3_S0GPU_EN

66 68

MAKE_BASE=TRUE

R8231

0

5%

1/16W

402

0

PLACE_NEAR=U8750.3:7mm

21

MF-LF1/16W

21

MF-LF

1

2

P0V95_S0GPU_EN

68 73

P1V8_S0GPU_EN

68 80

C8232

0.47UF

20%
4V
CERM-X5R-1
201

NO STUFF

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

C8231

0.47UF

20%
4V

2

CERM-X5R-1
201

NO STUFF

P0V95_S0GPU_EN

P1V8_S0GPU_EN

66 68

OUT

68 73

OUT

68 80

OUT

PCIE TEST STRUCTURES (FOR LAB USE)
Pending Layout. Can add more.

GND_VOID=TRUE

PLACE_NEAR=C8420.1:3mm

C8220

70 89

70 89

PEG_D2R_C_P<0> GAP_PEG_D2R_P0

IN

PEG_D2R_C_N<0>

IN

0.22UF

20%

6.3V
X5R
201

GND_VOID=TRUE

PLACE_NEAR=C8421.1:3mm

C8221

0.22UF

20%

6.3V
X5R
201

21

NOSTUFF

GAP_PEG_D2R_N0

21

NOSTUFF

PLACE_NEAR=C8420.1:3mm

1

R8220

49.9

1%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=C8421.1:3mm

1

R8221

49.9

1%
1/20W
MF
201

2

NOSTUFF

D

R8236

0

82

C

EG_RAIL4_EN

82

EG_RAIL5_EN

82

PLACE_NEAR=U9300.38:7mm

PLACE_NEAR=U9450.15:7mm

PLACE_NEAR=U8700.15:7mm

5%

402

R8235

0

5%

1/16W MF-LF

402

R8233

0

5%

1/16W MF-LF

402

21

MF-LF1/16W

21

21

EXT GPU PWRGD Pullup

B

GPUVCORE_PGOOD

68 79 82

IN

P1V35R1V5FB_PGOOD

68 73

IN

P0V95_S0GPU_PGOOD

68 73 82

IN

PVDDCI_PGOOD

68 80 82

IN

IN

68 82

PP3V3_S0GPU

47 66 71 72 76 77 79 80 84

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

P1V8GPU_PGOOD

MAKE_BASE=TRUE

P3V3_S0GPU_PGOOD

MAKE_BASE=TRUE

R8290

100K

1/20W

201

5%
MF

1

R8291

2

100K

1/20W

201

5%
MF

1

R8292

2

A

68 73

P1V35R1V5FB_PGOOD

R8295

100K

1/20W

0

5%

1/20W

MF

201

201

GPUVCORE_EN

68 79

PVDDCI_GPU_EN

68 80

P1V35R1V5FB_EN

68 73

1

R8293

5%
MF

2

21

201

5%
MF

1

R8296

2

GPUVCORE_ENEG_RAIL3_EN

PVDDCI_GPU_EN

P1V35R1V5FB_EN

1

10K

5%

1/20W

MF

201

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

100K

5%

1/20W

MF

201

1

R8294

2

100K

1/20W

GPUVCORE_PGOOD
P1V35R1V5FB_PGOOD
P0V95_S0GPU_PGOOD
PVDDCI_PGOOD
P1V8GPU_PGOOD

PGOOD ON SEQUENCE

1. GPU 3V3 GPU_PGOOD1

2. 0.95_S0GPU GPU_PGOOD6_2

3. 1V8_GPU GPU_PGOOD2

4. GPUVCORE GPU_PGOOD3

5. VDDCI GPU_PGOOD4

6. FB MVDD GPU_PGOOD5

(GPU_PGOOD6_2 is up before 1V8GPU_PGOOD after 3V3GPU_PGOOD)

PM_ALL_GPU_PGOOD

P3V3_S0GPU_PGOOD

68 82

OUT

68 79

OUT

70 85 89

68 80

OUT

68 73

OUT

68 79 82

68 73

OUT

68 73 82

OUT

68 80 82

OUT

68 80 82 68 80 82

OUT

68 82

OUT

68 82

70 85 89

66 67 69 82 83 84 86 96

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

PM_ALL_GPU_PGOOD

PEG_R2D_C_P<0>

IN

PEG_R2D_C_N<0>

IN

Power State Debug LEDs

(For development only)

DBG_RAIL_5

G

1

6 3

GND_VOID=TRUE

PLACE_NEAR=C8434.1:3mm

C8240

0.22UF

21

20%

6.3V
X5R
201

NOSTUFF

GND_VOID=TRUE

PLACE_NEAR=C8435.1:3mm

C8241

0.22UF

21

20%

6.3V
X5R
201

DBGLED

1

R8212

20K

5%
1/20W
MF
201

2

DBGLED

A

D8211

GREEN-56MCD-2MA-2.65V
LTQH9G-SM

K

PLACE_SIDE=BOTTOM
SILK_PART=ALL_GPU_PGOOD

DBG_RAIL5_D

3

D

DBGLED

Q8210

DMN32D2LFB4

S

DFN1006H4-3

SYM_VER_1

2

GAP_PEG_R2D_P0

GAP_PEG_R2D_N0

NOSTUFF

PLACE_NEAR=C8434.1:3mm

1

R8240

49.9

1%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=C8435.1:3mm

1

R8241

49.9

1%
1/20W
MF
201

2

NOSTUFF

SYNC_MASTER=MARY_X425G

PAGE TITLE

Power Sequencing EG/PGOOD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/11/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

82 OF 119

SHEET

68 OF 97

124578

SIZE

C

B

A

D

D

C

PP3V3_S0_EDP_SW

PLACE_NEAR=Q8300.2:3.5mm

1

R8336

100K

1%
1/20W
MF
201

2

PLACE_NEAR=Q8300.2:3.5mm

1

R8337

66.5K

1%
1/20W
MF
201

2

3V3_EDP_DIV min(V) 1.14

B

PP5VR3V3_SW_LCD_ISNS

PLACE_NEAR=U8330.3:2.5mm

1

R8331

680K

1%
1/20W
MF
201

2

PLACE_NEAR=U8330.3:2.5mm

A

1

R8332

88.7K

1%
1/20W
MF
201

2

U8330 Sense input
threhold is 0.505V

5V_EDP_DIV min 0.5057V

8 7 6 5 4 3

PP3V3_S0_EDP_SW

SMBUS_SMC_0_S0_SDA

36 40 43 48 76 85 86 95

BI

SMBUS_SMC_0_S0_SCL

36 40 43 48 76 85 86 95

IN

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

69

VOLTAGE=1.19V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.1 mm

SNS_3V3EDP_DIV

69

NOSTUFF

1

C8336

390PF

2%
25V

2

C0G
0201

Vgs:0.7V~1.0V

LCD_PWR_EN

69 82 86

IN

VOLTAGE=0.5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.1 mm

SNS_5VEDP_DIV

69

NOSTUFF

1

C8332

1000PF

10%
16V

2

X7R-CERM
0201

DMN5L06VK-7

DMN5L06VK-7

APN 376S0764

CRITICAL

Q8300

DMB53D0UV

G

2

DMN32D2LFB4

LCD_PWR_EN

69 82 86

69

69

R8380

Q8302

SOT563

VER 5

6

PP3V3_S0_EDP_SW

69

Q8302

SOT563

VER 5

3

R8339

SOT-563

Q8301

DFN1006H4-3

SYM_VER_2

3.3V_EDP ON/OFF CONTROL

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

APN 353S3999

1

ENABLE SENSE_OUT

3

SENSE

G

SD

G

SD

20

1

75K

1%

1/20W

MF

201

2

6
D

S
1

3

D

1

G S

2

6

VCC

U8330

TPS3895ADRY

USON

CRITICAL

GND

2

680uF 2% APN 131S00033

2

1

R8381

5

4

BUF_5V_EN

69

PLT_RST_BUF_L

IN

LCD_5V_EN_R_L

CRITICAL

C8334

0.68UF

6.3V
0402

BYPASS=U8330.6::2.3mm

C8330

0.1UF

X6S-CERM

0201

CT

PLACE_NEAR=U8330.5:3.5mm

C8331 (680pF) 2.7ms

1

2.0K

5%

1/20W

MF

201

2

I2C_TCON_SDA_R

1

2.0K

5%

1/20W

MF

201

2

I2C_TCON_SCL_R

0

5%

1/20W

R8305

52 55 66 67 68 69 82 83 84

PP3V3_S0

11 12 13 14 15 17 19 20 29
34 43 44 45 46 47 48 49 51
86 96

R8334

1

R8335

510

1%
1/20W
MF
201

2

APN 376S0764

LCD_5V_EN_L

VBEon: 0.58~0.7V

1

5V_eDP ON delay:9.4ms ~13.7ms

5%

2

X6S

1

20%
16V

2

LCD_3V3_EN_R

69

4

EDP5V_PGD_CT

5

CRITICAL

1

C8331

680PF

10%
25V

2

CERM
201

APN 132S0332

delay time

69

R8333

470K

5%

1/20W

MF

201

NOSTUFF

SNS_3V3EDP_DIV

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SNS_5VEDP_DIV

MAKE_BASE=TRUE

LCD_3V3_EN_R

MAKE_BASE=TRUE

69

69

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

21

LCD_5V_PLT_RST_BUF_L

201

MF

1

24K

5%

1/20W

MF

201

2

BUF_5V_EN

3

CRITICAL

5

Q8300

DMB53D0UV

4

SOT-563

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

R8330

0

1/20W

5%

1

2

69

1

C8307

0.1UF

10%
10V

2

X5R-CERM
0201

69

21

LCD_3V3_EN

201

MF

SNS_3V3EDP_DIV

LCD_5V_EN_RLCD_5V_EN_R

SNS_5VEDP_DIV

LCD_3V3_EN_R

PP3V3_S0_EDP_SW

NOSTUFF

1

R8350

2

1

R8351

2

CRITICAL

74LVC1G08

6

U8305

08

NC

5 3

SOT891

4

69

LCD_5V_EN_R

2

1

NC

PP5V_S4

37 38 51 61 66 67 81 84 86

1

C8309

0.1UF

10%
10V

2

X5R-CERM
0201

3.3V TCON Switch

TCON 3V3 <30mA

U8310

TPS22904

CSP

A1

VIN

VOUT

CRITICAL

B1

ON

1.0UF

20%

6.3V
X5R

GND

B2

69

69 69

69 69

69 69

1

2

C8308

0201-1

100K

5%
1/20W
MF
201

LCD_FSS

100K

5%
1/20W
MF
201

1/20W

R8338

69 82 85 86

63 85 86

63 85 86

63 86

5V TCON Switch

VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.1 mm

PP5V_FETCAP_LCD

LCD_5V_EN

69

1

C8313

4700PF

10%
10V

2

X7R
201

Part

Type

R(on)
@100mA

Current

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm

A2

U8310

Part

Type

R(on)
@ 3.6V

Current

I2C_BKLT_SCL

IN

I2C_BKLT_SDA

BI

PP3V3_S0_EDP_SW

69

I2C_TCON_SCL_R

69

I2C_TCON_SDA_R

69

LCD_BKLT_PWM_R

IN

0

21

LCD_5V_EN

201

5% MF

TCON 5V 2A

APN 353S3920

U8300

SLG5AP1443V

Load Switch

17 mOhm Typ
19 mOhm Max

2.5 A Max

TPS22904(353S3979)

Load Switch

66 mOhm Typ
90 mOhm Max

0.5A Max

69

1

VDD

U8300

SLG5AP1443V

TDFN

CAP

CRITICAL

GND

8

1

C8350

12PF

5%
NP0-C0G

2

0201
25V

82

69 82 85 86

82 97

82 97

37

D

52

69

SON

NOSTUFF

1

C8304

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=J8300.5::5MM

1

C8351

12PF

5%
NP0-C0G

2

0201
25V

LCD_HPD

OUT

LCD_FSS

OUT

DP_INT_AUXCH_C_P

BI

DP_INT_AUXCH_C_N

BI

DP_INT_ML_C_P<0>

82 97

IN

DP_INT_ML_C_N<0>

82 97

IN

DP_INT_ML_C_P<1>

82 97

IN

DP_INT_ML_C_N<1>

82 97

IN

DP_INT_ML_C_P<2>

82 97

IN

DP_INT_ML_C_N<2>

82 97

IN

DP_INT_ML_C_P<3>

82 97

IN

DP_INT_ML_C_N<3>

82 97

IN

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5VR3V3_SW_LCD_ISNS

1

C8311

0.1UF

10%
16V

2

X7R-CERM
0402

PP3V3_S0_EDP_SW

PLACE_NEAR=J8300.5:2mm

1

C8314

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8352

12PF

5%
NP0-C0G

2

0201
25V

1

C8312

10UF

20%
10V

2

X6S-CERM
0603

69

LCD PANEL INTERFACE (eDP)

C8328

0.1UF

C8329

0.1UF

R8320

0.025

0612-1

1

C8353

12PF

5%
NP0-C0G

2

0201
25V

GND_VOID

TRUE

C8320

0.1UF

TRUE

C8321

0.1UF

TRUE

C8322

0.1UF

TRUE

C8323

0.1UF

TRUE

C8324

0.1UF

TRUE

C8325

0.1UF

TRUE

C8326

0.1UF

TRUE

C8327

0.1UF

1%
1W

SENSOR_NONPROD_R

MF

21
43

ISNS_LCD_PANEL_N
ISNS_LCD_PANEL_P

69 86 97

69 86 97

69 86 97

69 86 97

69 86 97

69 86 97

69 86 97

69 86 97

1

C8354

12PF

5%
NP0-C0G

2

0201
25V

R8300

21
10%

16V

X5R-CERM

0201
21
10%

16V

X5R-CERM 0201

GND_VOID

21
10%

X5R-CERM

TRUE

21
10%

X5R-CERM 0201

TRUE

21
10%

TRUE

21
10%

X5R-CERM

TRUE

21
10%

X5R-CERM

TRUE

21
10%

X5R-CERM

TRUE

21
10%

X5R-CERM 0201

TRUE

21
X5R-CERM 0201

TRUE

CRITICAL

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

DP_INT_ML_P<0>

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

DP_INT_ML_P<2>

DP_INT_ML_N<2>

DP_INT_ML_P<3>

DP_INT_ML_N<3>

6 3

1

C8355

12PF

5%
NP0-C0G

2

0201
25V

DP_INT_ML_F_P<0>

97

16V

0201

DP_INT_ML_F_N<0>

97

16V

DP_INT_ML_F_P<1>

97 69 86 97

16V

0201X5R-CERM

DP_INT_ML_F_N<1>

97

16V

0201

DP_INT_ML_F_P<2>

97

16V

0201

DP_INT_ML_F_N<2>

97

16V

0201

DP_INT_ML_F_P<3>

97

16V

DP_INT_ML_F_N<3>

97

16V10%

46 96

OUT

46 96

OUT

GND_VOID

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

0

21

5%

C8301

0.1UF

X7R-CERM

R8311

1M

5%

1/20W

MF

201

R8313

1/20W

R8315

R8317

1/20W

1

C8356

12PF

5%
NP0-C0G

2

0201
25V

1/20WMF0201

FL8300

CRITICAL

3.25-OHM-0.1A-2.4GHZ

1

FL8302

CRITICAL

3.25-OHM-0.1A-2.4GHZ

1

FERR-220-OHM

1

10%
16V

2

0402

21

R8312

1M

21
5%
MF

201

1M

21

5%

1/20W

MF

201

1M

21
5%
MF

201

GND_VOID

TAM0605-4SM

SYM_VER-1

GND_VOID

TAM0605-4SM

SYM_VER-1

CRITICAL

L8300

0805

C8302

0.001UF

X7R-CERM

1M

5%

1/20W

MF

201

R8314

1M

5%

1/20W

MF

201

R8316

1M

5%

1/20W

MF

201

R8318

1M

5%

1/20W

MF

201

1

C8357

12PF

5%
NP0-C0G

2

0201
25V

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-1

1

TRUETRUETRUETRUE

GND_VOID

4

TRUETRUE

TRUE

TRUE

FL8301

CRITICAL

32

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-1

1

TRUETRUETRUETRUE

GND_VOID

4

TRUETRUETRUETRUE

FL8303

CRITICAL

32

21

1

10%
50V

2

0402

21

21

21

21

1

C8358

12PF

5%
NP0-C0G

2

0201
25V

4

32

4

32

1

2

PLACE_NEAR=J8300.28:2mm

C8303

12PF

5%
NP0-C0G
0201
25V

PPVOUT_S0_LCDBKLT

63 86

NC

LCD_HPD_CONN

69 86

DP_INT_AUX_P

69 86 97

DP_INT_AUX_N

69 86 97

DP_INT_ML_P<0>

69 86 97

DP_INT_ML_N<0>

69 86 97

DP_INT_ML_P<1>

DP_INT_ML_N<1>

69 86 97

DP_INT_ML_P<2>

69 86 97

DP_INT_ML_N<2>

69 86 97

DP_INT_ML_P<3>

69 86 97

DP_INT_ML_N<3>

69 86 97

PLACE_NEAR=J8300.28:2mm

1

C8315

3.0PF

2

PP5VR3V3_SW_LCD

86

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

+/-0.1PF

C8300

25V
NP0-C0G

1000PF

0201

10%

100V

X7R

0603

1

1

2

2

C8306

12PF

2%
100V
CERM
0402

GND_VOID

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

1

2

C8305 is placeholder for 3pF cap

LCD Panel HPD & AUX strapping

PP3V3_S0_EDP_SW

69

DP_INT_AUX_N

69 86 97

DP_INT_AUX_P LCD_HPD_CONN

69 86 97 69 86

SYNC_MASTER=MARY_X425G

PAGE TITLE

eDP Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NOSTUFF

1

R8303

1M

5%
1/20W
MF
201

2

NOSTUFF

1

R8302

1M

5%
1/20W
MF
201

2

12

CRITICAL

J8300

20525-130E-01

F-RT-SM

31

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

33
34
35
36
37
38
39
40
41

32

518S0829

C8305

12PF

2%
100V
CERM
0402

SYNC_DATE=12/11/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

83 OF 119

SHEET

69 OF 97

124578

1

R8301

1M

5%
1/20W
MF
201

2

SIZE

D

C

B

A

D

Power aliases required by this page:

- =PPV95_GPU_PCIE

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

8 7 6 5 4 3

Page Notes

12

D

GND_VOID=TRUE

0.22UF

PEG_R2D_C_P<0>

68 85 89

IN

PEG_R2D_C_N<0>

68 85 89

IN

PEG_R2D_C_P<1>

85 89

IN

PEG_R2D_C_N<1>

85 89

IN

PEG_R2D_C_P<2>

85 89

IN

PEG_R2D_C_N<2>

85 89

IN

PEG_R2D_C_P<3>

85 89

IN

PEG_R2D_C_N<3>

85 89

IN

C

85 89

85 89

85 89

85 89

85 89

85 89

85 89

85 89

PEG_R2D_C_P<4>

IN

PEG_R2D_C_N<4>

IN

PEG_R2D_C_P<5>

IN

PEG_R2D_C_N<5>

IN

PEG_R2D_C_P<6>

IN

PEG_R2D_C_N<6>

IN

PEG_R2D_C_P<7>

IN

PEG_R2D_C_N<7>

IN

C8420

GND_VOID=TRUE

0.22UF

C8421

GND_VOID=TRUE

0.22UF

C8422

GND_VOID=TRUE

0.22UF

C8423

GND_VOID=TRUE

0.22UF

C8424

GND_VOID=TRUE

0.22UF

C8425

GND_VOID=TRUE

0.22UF

C8426

GND_VOID=TRUE

0.22UF

C8427

GND_VOID=TRUE

0.22UF

C8428

GND_VOID=TRUE

0.22UF

C8429

GND_VOID=TRUE

0.22UF

C8430

GND_VOID=TRUE

0.22UF

C8431

GND_VOID=TRUE

0.22UF

C8432

GND_VOID=TRUE

0.22UF

C8433

GND_VOID=TRUE

0.22UF

C8434

GND_VOID=TRUE

0.22UF

C8435

B

PLACE_NEAR=U8400.AA38:7mm

21

20%

PLACE_NEAR=U8400.Y37:7mm

21

20%

PLACE_NEAR=U8400.Y35:7mm

21

20%

PLACE_NEAR=U8400.W36:7mm

21

20%

PLACE_NEAR=U8400.W38:7mm

21

20%

PLACE_NEAR=U8400.V37:7mm

21

20%

PLACE_NEAR=U8400.V35:7mm

21

20%

PLACE_NEAR=U8400.U36:7mm

21

20%

PLACE_NEAR=U8400.U38:7mm

21

20%

PLACE_NEAR=U8400.T37:7mm

21

20%

PLACE_NEAR=U8400.T35:7mm

21

20%

PLACE_NEAR=U8400.R36:7mm

21

20%

PLACE_NEAR=U8400.R38:7mm

21

20%

PLACE_NEAR=U8400.P37:7mm

21

20%

PLACE_NEAR=U8400.P35:7mm

21

20%

PLACE_NEAR=U8400.N36:7mm

21

20%

82 85

1

R8404

1K

5%
1/20W
MF
201

2

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

IN

PEG_R2D_P<0>

89

PEG_R2D_N<0>

89

PEG_R2D_P<1>

89

PEG_R2D_N<1>

89

PEG_R2D_P<2>

89

PEG_R2D_N<2>

89

PEG_R2D_P<3>

89

PEG_R2D_N<3>

89

PEG_R2D_P<4>

89

PEG_R2D_N<4>

89

PEG_R2D_P<5>

89

PEG_R2D_N<5>

89

PEG_R2D_P<6>

89

PEG_R2D_N<6>

89

PEG_R2D_P<7>

89

PEG_R2D_N<7>

89

EG_RESET_L

R8400

1/20W

201

11 85 91

11 85 91

0

5%
MF

IN
IN

21

PEG_CLK100M_P
PEG_CLK100M_N

GPU_TEST_PG

GPU_RESET_R_L

PEG_D2R_C_P<0>

68 89

PEG_D2R_C_N<0>

68 89

PEG_D2R_C_P<1>

89

PEG_D2R_C_N<1>

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

NC

M37

PCIE_RX8N

NC

M35

PCIE_RX9P

NC

L36

PCIE_RX9N

NC

L38

PCIE_RX10P

NC

K37

PCIE_RX10N

NC

K35

PCIE_RX11P

NC

J36

PCIE_RX11N

NC

J38

PCIE_RX12P

NC

H37

PCIE_RX12N

NC

H35

PCIE_RX13P

NC

G36

PCIE_RX13N

NC

G38

PCIE_RX14P

NC

F37

PCIE_RX14N

NC

F35

PCIE_RX15P

NC

E37

PCIE_RX15N

NC

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

TEST_PG

AA30

PERST*

U8400

VENUS-XT

FCBGA

(1 OF 9)

OMIT_TABLE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALR_TX
PCIE_CALR_RX

Y33
Y32

W33
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30
Y29

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

71 73 78 84

NC

PLACE_NEAR=U8400.Y29:2.54MM

NC
NC

NC
NC

NC

PEG_CALRP
PEG_CALRN

PP0V95_S0GPU

R8401

1/20W

1

1K

1%

MF

201

2

PLACE_NEAR=U8400.Y30:2.54MM

1

R8405

1.69K

1%
1/20W
MF
201

2

89

PEG_D2R_C_P<2>

89

PEG_D2R_C_N<2>

89

PEG_D2R_C_P<3>

89

PEG_D2R_C_N<3>

89

PEG_D2R_C_P<4>

89

PEG_D2R_C_N<4>

89

PEG_D2R_C_P<5>

89

PEG_D2R_C_N<5>

89

PEG_D2R_C_P<6>

89

PEG_D2R_C_N<6>

89

PEG_D2R_C_P<7>

89

PEG_D2R_C_N<7>

89

GND_VOID=TRUE

0.22UF

C8455

GND_VOID=TRUE

0.22UF

C8456

GND_VOID=TRUE

0.22UF

C8457

GND_VOID=TRUE

0.22UF

C8458

GND_VOID=TRUE

0.22UF

C8459

GND_VOID=TRUE

0.22UF

C8460

GND_VOID=TRUE

0.22UF

C8461

GND_VOID=TRUE

0.22UF

C8462

GND_VOID=TRUE

0.22UF

C8463

GND_VOID=TRUE

0.22UF

C8464

GND_VOID=TRUE

0.22UF

C8465

GND_VOID=TRUE

0.22UF

C8466

GND_VOID=TRUE

0.22UF

C8467

GND_VOID=TRUE

0.22UF

C8468

GND_VOID=TRUE

0.22UF

C8469

GND_VOID=TRUE

0.22UF

C8470

PLACE_NEAR=U0500.F10:7mm

21

20%

PLACE_NEAR=U0500.E10:7mm

21

20%

PLACE_NEAR=U0500.D10:7mm

21

20%

PLACE_NEAR=U0500.C10:7mm

21

20%

PLACE_NEAR=U0500.A10:7mm

21

20%

PLACE_NEAR=U0500.B10:7mm

21

20%

PLACE_NEAR=U0500.F9:7mm

21

20%

PLACE_NEAR=U0500.E9:7mm

21

20%

PLACE_NEAR=U0500.C9:7mm

21

20%

PLACE_NEAR=U0500.D9:7mm

21

20%

PLACE_NEAR=U0500.A9:7mm

21

20%

PLACE_NEAR=U0500.B9:7mm

21

20%

PLACE_NEAR=U0500.M5:7mm

21

20%

PLACE_NEAR=U0500.L5:7mm

21

20%

PLACE_NEAR=U0500.L1:7mm

21

20%

PLACE_NEAR=U0500.L2:7mm

21

20%

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

0201X6S-CERM6.3V

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

85 89

OUT

C

B

A

6 3

SYNC_MASTER=MARY_X425G

PAGE TITLE

Venus PCI-E

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/22/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

84 OF 119

SHEET

70 OF 97

124578

SIZE

A

D

GPU

D

C

B

A

71 76 78 80
84

84
47 66 68 72
76 77 79 80

71 76 78 80
84

71 76 78 80 84

71 76 78 80 84

70 71 73
78 84

84

PP0V95_S0GPU

73
70
71
78

PP1V8_GPUIFPX

PP3V3_S0GPU

PP1V8_GPUIFPX

PP1V8_GPUIFPX

PP1V8_GPUIFPX

PP0V95_S0GPU

CRITICAL

1

C8559

12PF

5%
NP0-C0G

2

0201
25V

8 7 6 5 4 3

1

C8505

2.2UF

20%
4V

2

X6S-CERM
0201

PLACE_NEAR=L8520.1:2.54MM

1

C8515

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=L8551.1:2.54MM

1

C8516

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=L8531.1:2.54MM

1

C8518

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=L8532.1:2.54MM

1

C8519

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=L8530.1:2.54MM

1

C8503

0.1UF

10%

6.3V

2

X7R
0201

CRITICAL

1

C855A

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8506

2

2.2UF

20%
4V
X6S-CERM
0201

1

C8507

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

L8520

120OHM-25%-1.8A-0.06DCR

0402

CRITICAL

120OHM-25%-1.8A-0.06DCR

L8551

0402

CRITICAL

L8531

220-OHM-1A

0402

150mohm DCR

CRITICAL

120OHM-25%-1.8A-0.06DCR

L8532

0402

XW8542

SM

CRITICAL

C8550

10UF
20%

6.3V
CERM-X6S
0402

L8530

0402

1

2

C8551

10UF
20%

6.3V
CERM-X6S
0402

120OHM-25%-1.8A-0.06DCR

1

2

PP1V35_GPU_REG

47 72 73 74 75 84

1

C8508

2.2UF

20%
4V

2

X6S-CERM
0201

PP1V8_GPU_VDD_CT

21

1

C8525

10UF
20%

6.3V

2

CERM-X6S
0402

PP3V3_GPU_VDDR3

21

1

C8533

1UF

20%

6.3V

2

X6S-CERM
0201

1

C85C0

10UF
20%

6.3V

2

CERM-X6S
0402

PP1V8_GPU_MEM_PLL

21

1

C8537

10UF
20%

6.3V

2

CERM-X6S
0402

PP1V8_GPU_PLL

21

1

C8542

10UF
20%

6.3V

2

CERM-X6S
0402

21

PLACE_NEAR=U8400.AM10:2.54MM

PP0V95_GPU_PLL

21

1

C8530

10UF
20%

6.3V

2

CERM-X6S
0402

1

C8552

1.0UF

20%
4V

2

X6S
0201

CRITICAL

1

C8504

12PF

5%
NP0-C0G

2

0201
25V

1

C8509

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8528

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.AG26:2.54MM

1

C8534

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U8400.AG23:2.54MM

1

C8510

0.01UF

10%
10V

2

X7R-CERM
0201

1

C8520

0.1UF

10%

6.3V

2

X7R
0201

250mA

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

C8529

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=U8400.AF26:2.54MM

60mA

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C8535

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=U8400.AF23:2.54MM

300mA

1

C85C1

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.AG13:2.54MM

1

C8538

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.H8:2.54MM

1

C8543

1.0UF

20%
4V

2

X6S
0201

1

C8531

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.AN9:2.54MM

1

2

1

2

150mA

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

2

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

PLACE_NEAR=U8400.AM10:2.54MM

1

2

150mA

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.95V

1

2

C8553

1.0UF

20%
4V
X6S
0201

C85C2

0.1UF

10%

6.3V
X7R
0201

PLACE_NEAR=U8400.AF12:2.54MM

PLACE_NEAR=U8400.H7:2.54MM

C8540

0.1UF

10%

6.3V
X7R
0201

75mA

C8544

0.1UF

10%

6.3V
X7R
0201

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

C8532

0.1UF

10%

6.3V
X7R
0201

PLACE_NEAR=U8400.AN9:2.54MM

1

C8554

1.0UF

20%
4V

2

X6S
0201

CRITICAL

1

C8517

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8511

0.01UF

10%
10V

2

X7R-CERM
0201

1

C8521

0.1UF

10%

6.3V

2

X7R
0201

1

2

C8555

1.0UF

20%
4V
X6S
0201

1

C8500

10UF
20%

6.3V

2

CERM-X6S
0402

1

C8512

0.01UF

10%
10V

2

X7R-CERM
0201

1

C8522

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=U8400.AB37:2.54MM

PP1V8_GPUIFPX

71 76 78
80 84

1

C8545

10UF
20%

6.3V

2

CERM-X6S
0402

1

C8556

1.0UF

20%
4V

2

X6S
0201

2000mA

1

C8501

10UF
20%

6.3V

2

CERM-X6S
0402

1

C8513

0.01UF

10%
10V

2

X7R-CERM
0201

1

C8523

0.1UF

10%

6.3V

2

X7R
0201

GND_SPLL_PVSS

VSNS_GPU_VDDC_P

71 79 85 96

VSNS_GPU_VDDI_P

71 80 85 96

GPU_GND_SENSE

71

PLACE_NEAR=U8400.AB37:2.54MM

1

C8547

1.0UF

20%
4V

2

X6S
0201

1

C8557

1.0UF

20%
4V

2

X6S
0201

1

C8502

10UF
20%

6.3V

2

CERM-X6S
0402

1

C8514

0.01UF

10%
10V

2

X7R-CERM
0201

1

C8524

0.1UF

10%

6.3V

2

X7R
0201

200mA

1

2

1

2

C8548

1.0UF

20%
4V
X6S
0201

2500mA

C8558

1.0UF

20%
4V
X6S
0201

AC7

AD11

AF7

AG10

AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10

K11
K13

L12
L16
L21
L23
L26

M11
N11

R11
U11

Y11

AF26
AF27
AG26
AG27

AF23
AF24
AG23
AG24

AD12
AF11
AF12
AF13
AF15
AG11
AG13
AG15

AM10

AN9

AN10

AF28

AG28

AH29

V28
W29

AA31
AA32
AA33
AA34

W30
Y31

AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

J7
J9

K8

L7

P7

U7

Y7

H7
H8

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

FB_VDDC

FB_VDDCI

FB_GND

PCIE_PVDD

VDDR1

VDD_CT

VDDR3

VDDR4

MPLL_PVDD

NC_BIF_VDDC

NC_PCIE_VDDR

PCIE_VDDC

U8400

VENUS-XT

FCBGA

(7 OF 9)

OMIT_TABLE

VDDC

BIF_VDDC

VDDC

BIF_VDDC

VDDC

VDDCI

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

1

2

1

2

1

2

1200mA

1

2

1

2

C8560

2.2UF

20%
4V
X6S-CERM
0201

C8570

2.2UF

20%
4V
X6S-CERM
0201

C8590

10UF
20%

6.3V
CERM-X6S
0402

C85A0

0.1UF

10%

6.3V
X7R
0201

C85B0

10UF
20%

6.3V
CERM-X6S
0402

1

C8561

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8571

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8591

10UF
20%

6.3V

2

CERM-X6S
0402

PP0V95_S0GPU

1

C85A1

0.1UF

10%

6.3V

2

X7R
0201

PPVCORE_GPU

47 71 79 84

1

C8562

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8572

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8592

10UF
20%

6.3V

2

CERM-X6S
0402

71 80 84

1

C85A2

0.1UF

10%

6.3V

2

X7R
0201

70 71 73 78 84

6 3

52A (63A?)

1

C8563

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8573

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8593

10UF

20%

6.3V

2

CERM-X6S
0402

PPVDDCI_S0_ISENSE

1

C85A7

1.0UF

20%
4V

2

X6S
0201

1

2

1

2

1

2

7A@0.9V

1

2

C8564

2.2UF

20%
4V
X6S-CERM
0201

C8574

2.2UF

20%
4V
X6S-CERM
0201

C8594

10UF
20%

6.3V
CERM-X6S
0402

GPU_GND_SENSE

71

VOLTAGE=0.0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

C85A8

1.0UF

20%
4V
X6S
0201

1

C8565

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8575

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8595

10UF
20%

6.3V

2

CERM-X6S
0402

1

C85A9

1.0UF

20%
4V

2

X6S
0201

Page Notes

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V5R1V35_GPU_FB_VDDR1

- =PP1V8_GPU_VDD_CT

- =PP1V0_GPU_PLL

- =PP3V3_GPU_VDDR3

- =PP3V3_GPU_VDDR4

- =PP1V8_GPU_MEM_PLL

- =PP1V8_GPU_PLL

- =PP1V8_GPU_PCIE_VDDR

- =PP1V8_GPU_PCIE_VDDC

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

1

C8566

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8576

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8596

10UF
20%

6.3V

2

CERM-X6S
0402

CRITICAL

1

C85A3

12PF

5%
NP0-C0G

2

0201
25V

SYNC_MASTER=MARY_X425G

PAGE TITLE

1

C8567

2.2UF

20%
4V

2

X6S-CERM
0201

1

C8577

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

1

C8597

12PF

5%
NP0-C0G

2

0201
25V

PPVCORE_GPU

NOSTUFF

1

R8510

100

1%
1/20W
MF

PLACE_NEAR=U8400.AF28:2.54MM

201

2

VSNS_GPU_VDDC_P

NOSTUFF

1

R8511

100

1%
1/20W
MF
201

2

PLACE_NEAR=U8400.AH29:2.54MM

PPVDDCI_S0_ISENSE

NOSTUFF

1

R8512

100

1%
1/20W
MF
201

2

PLACE_NEAR=U8400.AG28:2.54MM

VSNS_GPU_VDDI_P

CRITICAL

1

C85A4

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

1

C8598

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

47 71 79 84

R8510/1/2 only stuffed
for GPU VR measurement

85 96
71 79

NO_XNET_CONNECTION=TRUE

XW8510

21

SM

XW8512

21

SM

NO_XNET_CONNECTION=TRUE

71 80 84

71 80 85 96

Venus CORE/FB POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

VSNS_GPU_VDDC_N

VSNS_GPU_VDDI_N

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

79 96

OUT

80 96

OUT

SYNC_DATE=09/22/2014

<E4LABEL>

<BRANCH>

85 OF 119

71 OF 97

SIZE

D

C

B

GPU

A

D

8 7 6 5 4 3

FB_A0_DQ<0>

74 97

BI

FB_A0_DQ<1>

74 97

BI

FB_A0_DQ<2>

74 97

BI

FB_A0_DQ<3>

74 97

BI

FB_A0_DQ<4>

74 97

BI

FB_A0_DQ<5>

74 97

BI

FB_A0_DQ<6>

74 97

BI

FB_A0_DQ<7>

74 97

BI

FB_A0_DQ<8>

74 97

BI

FB_A0_DQ<9>

74 97

BI

FB_A0_DQ<10>

74 97

BI

FB_A0_DQ<11>

74 97

D

C

B

BI

FB_A0_DQ<12>

74 97

BI

FB_A0_DQ<13>

74 97

BI

FB_A0_DQ<14>

74 97

BI

FB_A0_DQ<15>

74 97

BI

FB_A0_DQ<16>

74 97

BI

FB_A0_DQ<17>

74 97

BI

FB_A0_DQ<18>

74 97

BI

FB_A0_DQ<19>

74 97

BI

FB_A0_DQ<20>

74 97

BI

FB_A0_DQ<21>

74 97

BI

FB_A0_DQ<22>

74 97

BI

FB_A0_DQ<23>

74 97

BI

FB_A0_DQ<24>

74 97

BI

FB_A0_DQ<25>

74 97

BI

FB_A0_DQ<26>

74 97

BI

FB_A0_DQ<27>

74 97

BI

FB_A0_DQ<28>

74 97

BI

FB_A0_DQ<29>

74 97

BI

FB_A0_DQ<30>

74 97

BI

FB_A0_DQ<31>

74 97

BI

FB_A1_DQ<0>

74 97

BI

FB_A1_DQ<1>

74 97

BI

FB_A1_DQ<2>

74 97

BI

FB_A1_DQ<3>

74 97

BI

FB_A1_DQ<4>

74 97

BI

FB_A1_DQ<5>

74 97

BI

FB_A1_DQ<6>

74 97

BI

FB_A1_DQ<7>

74 97

BI

FB_A1_DQ<8>

74 97

BI

FB_A1_DQ<9>

74 97

BI

FB_A1_DQ<10>

74 97

BI

FB_A1_DQ<11>

74 97

BI

FB_A1_DQ<12>

74 97

BI

FB_A1_DQ<13>

74 97

BI

FB_A1_DQ<14>

74 97

BI

FB_A1_DQ<15>

74 97

BI

FB_A1_DQ<16>

74 97

BI

FB_A1_DQ<17>

74 97

BI

FB_A1_DQ<18>

74 97

BI

FB_A1_DQ<19>

74 97

BI

FB_A1_DQ<20>

74 97

BI

FB_A1_DQ<21>

74 97

BI

FB_A1_DQ<22>

74 97

BI

FB_A1_DQ<23>

74 97

BI

FB_A1_DQ<24>

74 97

BI

FB_A1_DQ<25>

74 97

BI

FB_A1_DQ<26>

74 97

BI

FB_A1_DQ<27>

74 97

BI

FB_A1_DQ<28>

74 97

BI

FB_A1_DQ<29>

74 97

BI

FB_A1_DQ<30>

74 97

BI

FB_A1_DQ<31>

74 97

BI

FB_A_VREFD

72

FB_A_VREFS

72

NOSTUFF

R8613

1/20W

PLACE_NEAR=U8400.M27:2.54MM

120

201

21

FB_CALRP0

1%
MF

C37

DQA0_0

C35

DQA0_1

A35

DQA0_2

E34

DQA0_3

G32

DQA0_4

D33

DQA0_5

F32

DQA0_6

E32

DQA0_7

D31

DQA0_8

F30

DQA0_9

C30

DQA0_10

A30

DQA0_11

F28

DQA0_12

C28

DQA0_13

A28

DQA0_14

E28

DQA0_15

D27

DQA0_16

F26

DQA0_17

C26

DQA0_18

A26

DQA0_19

F24

DQA0_20

C24

DQA0_21

A24

DQA0_22

E24

DQA0_23

C22

DQA0_24

A22

DQA0_25

F22

DQA0_26

D21

DQA0_27

A20

DQA0_28

F20

DQA0_29

D19

DQA0_30

E18

DQA0_31

C18

DQA1_0

A18

DQA1_1

F18

DQA1_2

D17

DQA1_3

A16

DQA1_4

F16

DQA1_5

D15

DQA1_6

E14

DQA1_7

F14

DQA1_8

D13

DQA1_9

F12

DQA1_10

A12

DQA1_11

D11

DQA1_12

F10

DQA1_13

A10

DQA1_14

C10

DQA1_15

G13

DQA1_16

H13

DQA1_17

J13

DQA1_18

H11

DQA1_19

G10

DQA1_20

G8

DQA1_21

K9

DQA1_22

K10

DQA1_23

G9

DQA1_24

A8

DQA1_25

C8

DQA1_26

E8

DQA1_27

A6

DQA1_28

C6

DQA1_29

E6

DQA1_30

A5

DQA1_31

L18

MVREFDA

L20

MVREFSA

L27

AG12

AH12

N12

M27
M12

NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2

MEM_CALRP0
NC_MEM_CALRP1
NC_MEM_CALRP2

NC
NC
NC

NC
NC

U8400

VENUS-XT

FCBGA

(4 OF 9) (5 OF 9)

OMIT_TABLE

WCKA0_0*

WCKA0_1*

WCKA1_0*

WCKA1_1*

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7

MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7

WCKA0_0

WCKA0_1

WCKA1_0

WCKA1_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

ADBIA0
ADBIA1

CLKA0

CLKA0*

CLKA1

CLKA1*

RASA0*
RASA1*

CASA0*
CASA1*

CSA0_0*
CSA0_1*

CSA1_0*
CSA1_1*

CKEA0
CKEA1

WEA0*
WEA1*

MAA0_8
MAA0_9

MAA1_8
MAA1_9

G24
J23
H24
J24
H26
J26
H21
G21

H19
H20
L13
G16
J16
H16
J17
H17

A32
C32

D23
E22

C14
A14

E10
D9

C34
D29
D25
E20

E16
E12
J10
D7

A34
E30
E26
C20

C16
C12
J11
F8

J21
G19

H27
G27

J14
H14

K23
K19

K20
K17

K24
K27

M13
K16

K21
J20

K26
L15

H23
M21

J19
M20

FB_A0_A<0>
FB_A0_A<1>
FB_A0_A<2>
FB_A0_A<3>
FB_A0_A<4>
FB_A0_A<5>
FB_A0_A<6>
FB_A0_A<7>

FB_A1_A<0>
FB_A1_A<1>
FB_A1_A<2>
FB_A1_A<3>
FB_A1_A<4>
FB_A1_A<5>
FB_A1_A<6>
FB_A1_A<7>

FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>

FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>

FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>

FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>

FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>

FB_A0_ABI_L
FB_A1_ABI_L

FB_A0_CLK_P
FB_A0_CLK_N

FB_A1_CLK_P
FB_A1_CLK_N

FB_A0_RAS_L
FB_A1_RAS_L

FB_A0_CAS_L
FB_A1_CAS_L

FB_A0_CS_L

NC

FB_A1_CS_L

NC

FB_A0_CKE_L
FB_A1_CKE_L

FB_A0_WE_L
FB_A1_WE_L

FB_A0_A<8>
NC_FB_A0_A<9>

FB_A1_A<8>
NC_FB_A1_A<9>

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7

MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7

WCKB0_0

WCKB0_0*

WCKB0_1

WCKB0_1*

WCKB1_0

WCKB1_0*

WCKB1_1

WCKB1_1*

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB0
ADBIB1

CLKB0

CLKB0*

CLKB1

CLKB1*

RASB0*
RASB1*

CASB0*
CASB1*

CSB0_0*
CSB0_1*

CSB1_0*
CSB1_1*

CKEB0
CKEB1

WEB0*
WEB1*

MAB0_8
MAB0_9

MAB1_8
MAB1_9

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8

Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1

T3
T5

AE4
AF5

AK6
AK5

F6
K3
P3
V5

AB5
AH1
AJ9
AM5

G7
K1
P1
W4

AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
U12

W8
V12

AH11

FB_B0_A<0>
FB_B0_A<1>
FB_B0_A<2>
FB_B0_A<3>
FB_B0_A<4>
FB_B0_A<5>
FB_B0_A<6>
FB_B0_A<7>

FB_B1_A<0>
FB_B1_A<1>
FB_B1_A<2>
FB_B1_A<3>
FB_B1_A<4>
FB_B1_A<5>
FB_B1_A<6>
FB_B1_A<7>

FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>

FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>

FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>

FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>

FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>

FB_B0_ABI_L
FB_B1_ABI_L

FB_B0_CLK_P
FB_B0_CLK_N

FB_B1_CLK_P
FB_B1_CLK_N

FB_B0_RAS_L
FB_B1_RAS_L

FB_B0_CAS_L
FB_B1_CAS_L

FB_B0_CS_L

NC

FB_B1_CS_L

NC

FB_B0_CKE_L
FB_B1_CKE_L

FB_B0_WE_L
FB_B1_WE_L

FB_B0_A<8>
NC_FB_B0_A<9>

FB_B1_A<8>
NC_FB_B1_A<9>

GPU_FB_RESET_L

PLACE_NEAR=U8400.AH11:5MM

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

OUT

87

OUT

PLACE_NEAR=U8400.AH11:5MM

87

1

R8660

4.99K

1%

1/20W

MF

201

2

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

IN

75 97

IN

75 97

IN

75 97

IN

75 97

IN

75 97

IN

75 97

IN

75 97

IN

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

BI

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

R8661

10

1%

1/20W

MF

201

Power aliases required by this page:

- =PP1V5R1V35_FB_CAL

- =PP1V5R1V35_FB_REF

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

FB_RESET_RC_L

21

PLACE_NEAR=R8661.2:5MM

1

C8660

120PF

5%
50V

2

C0G-CERM
0402

1

R8650

10K

5%
1/20W
MF
201

2

AA12

AD28

AK10
AL10

AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

Y12

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31

DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

MVREFDB
MVREFSB

TESTEN

CLKTESTA
CLKTESTB

U8400

VENUS-XT

FCBGA

OMIT_TABLE

201

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

75 97

72

21

1%

MF

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

47 66 68
71 76 77
79 80 84

1

2

1

2

FB_B0_DQ<0>
FB_B0_DQ<1>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<4>
FB_B0_DQ<5>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<12>
FB_B0_DQ<13>
FB_B0_DQ<14>
FB_B0_DQ<15>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<18>
FB_B0_DQ<19>
FB_B0_DQ<20>
FB_B0_DQ<21>
FB_B0_DQ<22>
FB_B0_DQ<23>
FB_B0_DQ<24>
FB_B0_DQ<25>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<28>
FB_B0_DQ<29>
FB_B0_DQ<30>
FB_B0_DQ<31>

FB_B1_DQ<0>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<5>
FB_B1_DQ<6>
FB_B1_DQ<7>
FB_B1_DQ<8>
FB_B1_DQ<9>
FB_B1_DQ<10>
FB_B1_DQ<11>
FB_B1_DQ<12>
FB_B1_DQ<13>
FB_B1_DQ<14>
FB_B1_DQ<15>
FB_B1_DQ<16>
FB_B1_DQ<17>
FB_B1_DQ<18>
FB_B1_DQ<19>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<22>
FB_B1_DQ<23>
FB_B1_DQ<24>
FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<30>
FB_B1_DQ<31>

FB_B_VREFD
FB_B_VREFS

72

GPU_TEST_EN

GPU_CLK_TEST_P

97

GPU_CLK_TEST_N

97

NOSTUFF

1

C8652

0.1UF

10%

6.3V

2

X5R
201

GPU_CLK_TEST_RC_N

97

NOSTUFF

1

R8652

51.1

1%
1/20W
MF
201

2

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

IN

74 97

IN

74 97

IN

74 97

IN

74 97

IN

74 97

IN

74 97

IN

74 97

IN

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

BI

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

74 97

OUT

PP3V3_S0GPU

74 97

OUT

74 97

OUT

74 97

OUT

87

74 97

OUT

87

GPU_CLK_TEST_RC_P

97

NOSTUFF

R8665

10K

5%

1/20W

MF

201

NOSTUFF

C8651

0.1UF

6.3V

NOSTUFF

R8651

51.1

10%

X5R
201

1/20W

Page Notes

PLACE_NEAR=R8661.2:5MM

R8662

51

5%

1/20W

MF

201

FB_RESET_L

21

12

D

C

B

74 75

OUT

PP1V35_GPU_REG

PP1V35_GPU_REG

84

PLACE_NEAR=U8400.L18:2.54MM

A

PLACE_NEAR=U8400.L18:2.54MM

NOSTUFF

1

R8600

40.2

1%
1/20W
MF
201

2

FB_A_VREFD

NOSTUFF

1

R8601

100

1%
1/20W
MF
201

2

72

NOSTUFF

PLACE_NEAR=U8400.L18:2.54MM

1

C8600

1.0UF

20%

6.3V

2

X5R
0201

PP1V35_GPU_REG

47 71 72 73 74 75 84 47 71 72 73 74 75

PLACE_NEAR=U8400.L20:2.54MM

PLACE_NEAR=U8400.L20:2.54MM

NOSTUFF

1

R8602

40.2

1%
1/20W
MF
201

2

FB_A_VREFS

NOSTUFF

1

R8603

100

1%
1/20W
MF
201

2

72

NOSTUFF

PLACE_NEAR=U8400.L20:2.54MM

1

C8601

1.0UF

20%

6.3V

2

X5R
0201

47 71 72 73 74 75 84

PLACE_NEAR=U8400.Y12:2.54MM

PLACE_NEAR=U8400.Y12:2.54MM

NOSTUFF

1

R8604

40.2

1%
1/20W
MF
201

2

FB_B_VREFD

NOSTUFF

1

R8605

100

1%
1/20W
MF
201

2

72

NOSTUFF

PLACE_NEAR=U8400.Y12:2.54MM

1

C8602

1.0UF

20%

6.3V

2

X5R
0201

6 3

PP1V35_GPU_REG

47 71 72 73 74 75 84

PLACE_NEAR=U8400.AA12:2.54MM

PLACE_NEAR=U8400.AA12:2.54MM

NOSTUFF

1

R8606

40.2

1%
1/20W
MF
201

2

FB_B_VREFS

NOSTUFF

1

R8607

100

1%
1/20W
MF
201

2

72

NOSTUFF

PLACE_NEAR=U8400.AA12:2.54MM

1

C8603

1.0UF

20%

6.3V

2

X5R
0201

SYNC_MASTER=J45G_AMD SYNC_DATE=06/30/2014

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Venus FRAME BUFFER I/F

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

<E4LABEL>

<BRANCH>

86 OF 119

72 OF 97

124578

SIZE

GPU

A

D

47 71 72 73 74
75 84

NO_XNET_CONNECTION=TRUE

D

96

C

8 7 6 5 4 3

PPVIN_S5_HS_GPU_ISNS

47 73 79 80 84

1

R8709

0

5%
1/16W
MF-LF

402

2

GPUFB_DRVH_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

GPUFB_LL

DIDT=TRUE

GPUFB_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

GPUFB_BOOT_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

1

C8705

0.1UF

10%
16V

2

X7R-CERM
0402

R8739

2 1

1

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

CASE-D2E-SM

GPUFB_DRVH

C8706

68UF

POLY-TANT

CRITICAL

1

C8707

68UF

POLY-TANT

CASE-D2E-SM

732

20%
16V

376S0959

CRITICAL

Q8710

SIZ710DT

POWERPAK-6X3.7

20%
16V

2

1

8

6

54

PP1V35_GPU_REG

VSNS_GPU_FB_XW_P

96

VSNS_GPU_FB_XW_N

NO_XNET_CONNECTION=TRUE

21

21

SM

SM

XW8703

NO_XNET_CONNECTION=TRUE

R8703

1.62K

1%

1/20W

MF

201

1

2

XW8731

NO_XNET_CONNECTION=TRUE

R8731

1.62K

21

1%

1/20W

MF

201

21

NOSTUFF

1

C8726

10PF

5%
50V
C0G
0201

R8704

4.64K

1%
1/20W
MF
201

2

NOSTUFF

1

R8702

4.64K

1%
1/20W
MF
201

2

C8723

1

C8715

2

0.01UF

X7R-CERM

10PF

5%
50V
C0G
0201

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

PP5V_S0GPU_P1V35_GPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

68

IN

P1V35R1V5FB_EN

GPUFB_SENSE_DIV

GPUFB_SREF

1

R8717

191K

0.1%
1/20W
MF
0201

2

68

OUT

GPUFB_VO

GPUFB_OCSET

P1V35R1V5FB_PGOOD

GPUFB_RTN_DIV

GPUFB_FSEL

1

0

5%

1/20W

MF

201

2

GPUFB_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

GPUFB_SET0

GPUFB_SET1

76 77

IN

FBVDD_ALTVO

1

10%
16V

2

1

0402

R8718

95.3K

0.1%
1/20W
MF
0201

2

R8700

0

5%

1/20W

MF

201

NOSTUFF

R8713

1

C8722

2.2UF

10%
10V

2

X6S-CERM

21

0402

GPUFB_SET_R

1

R8734

16.9K

0.1%
1/20W
MF
0201

2

15 18

10

7

12

11

14

4

13

8

9

6

5

PLACE_NEAR=U8700.1:1mm

R8701

1/20W

EN

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

SET0

SET1

VID0

VID1

XW8700

1

2.2

5%

MF

201

2

19

VCC

U8700

ISL95870AH

UTQFN

CRITICAL

GND

3

SM

21

PVCC

PGND

1

2

20

2

R8706

2.2

5%
1/20W
MF
201

BOOT

UGATE

PHASE

LGATE

PP5V_S0_GPUFB_PVCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

1

C8721

10UF

20%

6.3V

2

CERM-X6S
0402

GPUFB_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

17

16

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

1

SWITCH_NODE=TRUE

1

2

MIRROR C8702 AND C8708

PLACE_NEAR=Q8710.1:1.5MM

CRITICAL

1

C8709

33UF

20%
16V

2

POLY-TANT
CASED12-SM

APN 152S00140

L8710

0.68UH-20%-14A

PILE063T-SM

1

C8708

2.2UF

2

CRITICAL

21

1

C8702

2.2UF

20%
25V
X6S-CERM
0402

20%
25V

2

X6S-CERM
0402

PP1V5R1V35_GPU_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

GPUFB_CS_P

47 96

R8721

4.64K

1%

1/20W

MF

201

1

2

C8703

1000PF

1

5%

25V

2

CERM
0402

CRITICAL

R8730

0.002

1%
1W

CYN

0612

PLACE_NEAR=L8760.2:1.5MM

47 96

C8770

2200PF

2 1

10%
25V
X7R

0201

CRITICAL

1

C8701

12PF

5%
NP0-C0G

2

0201
25V

21
43

C8711

1000PF

GPUFB_CS_N

1

R8772

4.64K

1%
1/20W
MF
201

2

CRITICAL

1

5%

25V

2

CERM

CASE-B2-SM

0402

PLACE_NEAR=L8710.2:3MM

GPIO 21 --> VID1

CRITICAL

1

C8704

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

GPU FB SUPPLY

VOUT = 1.5V / 1.35V
12A MAX OUTPUT
F = 500 KHZ

PP1V35_GPU_REG

C8710

270UF

TANT

1

20%

2V

2

CRITICAL

C8712

270UF

TANT

CASE-B2-SM

PLACE_NEAR=L8710.2:3MM

1

20%

2V

2

CRITICAL

C8713

270UF

CASE-B2-SM

PLACE_NEAR=L8710.2:3MM

VID1 VID0 FBVDD

0 0 1.5V

1 0 1.35V

TANT

20%

2V

12

CRITICAL

1

2

CASE-B2-SM

PLACE_NEAR=L8710.2:3MM

47 71 72 73 74 75 84

1

C8714

270UF

20%

2V

2

TANT

D

C

B

NO_XNET_CONNECTION=TRUE

A

PP0V95_S0GPU

70 71 73 78 84

NO_XNET_CONNECTION=TRUE

21

SM

XW8754

VSNS_GPU_0V95_XW_N

96

1

R8754

3.01K

0.1%

1/20W

MF

0201

2

<Ra>

1

R8756

3.32K

0.1%

1/20W

0201

<Rb>

MF

2

C8754

10PF

1

5%

50V

2

C0G

0201

Vout = 0.5V * (1 + Ra / Rb)

NO_XNET_CONNECTION=TRUE

21

SM

XW8755

VSNS_GPU_0V95_XW_P

NO_XNET_CONNECTION=TRUE

1

R8755

3.01K

0.1%
1/20W
MF
0201

2

<Ra>

1

R8757

3.32K

0.1%
1/20W
MF
0201

2

1

<Rb>

C8755

2

10PF

5%
50V
C0G
0201

PPVIN_S5_HS_GPU_ISNS

1

2.2

5%
MF

201

2

13

VCC

U8750

ISL95870

UTQFN

CRITICAL

GND

1

SM

47 73 79 80 84

MIRROR C8750 AND C8758

1

C8751

10UF

20%

6.3V

2

CERM-X6S
0402

14

PVCC

12

BOOT

UGATE

PHASE

LGATE

P0V95_GPU_VBST

11

P0V95_GPU_DRVH_R

10

P0V95_GPU_LL

15

P0V95_GPU_DRVL

PGND

16

21

P0V95_GPU_BOOT_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

R8775

2.2

5%
1/16W
MF-LF

402

R8796

1

2 1

5%
1/16W
MF-LF

402

1

C8795

1

0.1UF

10%
16V

2

X7R-CERM
0402

2

CRITICAL

C8756

POLY-TANT

CASE-D2E-SM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

P0V95_GPU_DRVH

68UF

1

20%
16V

2

3

4

5

PLACE_NEAR=Q8760.1:1.5MM

1

2

376S1038

CRITICAL

Q8760

CSD58873Q3D

Q3D

TG

TGR

BG

9

C8758

2.2UF

20%
25V
X6S-CERM
0402

VIN

VSW

PGND

1

6
7
8

1.0UH-20%-8.6A

P0V95_GPU_LL_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

1

C8750

2.2UF

20%
25V

2

X6S-CERM
0402

152S00139

CRITICAL

L8760

PIME053T-SM

R8771

3.01K

1%

1/20W

MF

201

1

C8757

1000PF

5%

25V

2

CERM
0402

21

P0V95_S0GPU_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

ISNS_PP0V95_S0GPU_P

47 96

ISNS_PP0V95_S0GPU_N

47 96

1

C8700

2200PF

2

2 1

10%
25V
X7R

0201

CRITICAL

1

C8771

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C8772

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

GPU 0.95V/BIF_VDDC SUPPLY

CRITICAL

R8795

0.003

1%
1W

CYN

0612

1

R8705

3.01K

1%
1/20W
MF
201

2

21
43

C8759

1000PF

5%

25V
CERM
0402

PLACE_NEAR=L8760.2:1.5MM

CRITICAL

1

2

CASE-B2-SM

SYNC_MASTER=ADITYA_X425G

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP0V95_S0GPU

CRITICAL

1

C8760

270UF

20%

2V

2

TANT

CASE-B2-SM

PLACE_NEAR=L8760.2:3MM

0V95 GPU / 1V35 FB Power Supply

R

CRITICAL

1

C8761

270UF

20%

2V

2

TANT

CASE-B2-SM

PLACE_NEAR=L8760.2:3MM

Apple Inc.

C8762

270UF

TANT

VOUT = 0.95V

5.2A MAX OUTPUT
F = 500 KHZ

1

20%

2V

2

PLACE_NEAR=L8760.2:3MM

70 71 73 78 84

SYNC_DATE=09/16/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

87 OF 119

SHEET

73 OF 97

SIZE

B

GPU

A

D

124578

PP5V_S0

18 19 36 49 58 59 62 63 66
67 73 79 80 84 85 86

R8751

1/20W

PP5V_S0GPU_P1V05_GPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

IN

OUT

2.2UF

X6S-CERM

10%
10V

0402

VOLTAGE=5V

P0V95_GPU_FB

P0V95_GPU_SREF

P0V95_GPU_VO

P0V95_GPU_OCSET

P0V95_S0GPU_PGOOD

P0V95_GPU_RTN

P0V95_GPU_FSEL

NOSTUFF

1

R8753

1

0

5%
1/20W
MF

2

201

2

P0V95_GPU_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

P0V95_S0GPU_EN

3

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

XW8750

PLACE_NEAR=U8750.1:1mm

96

68

68 82

C8752

1

C8753

0.047UF

10%
16V

2

X7R-CERM
0402

6 3

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

D

C

74 75

PP1V35_GPU_REG

47 71
72 73
84

B

A

PP1V35_GPU_REG

47 71 72 73 74 75 84

1

C8800

4.7UF

20%

6.3V

2

X6S
0402

1

C8803

4.7UF

20%

6.3V

2

X6S
0402

1

C8806

1.0UF

20%
4V

2

X6S
0201

1

C8810

1.0UF

20%
4V

2

X6S
0201

1

C8814

1.0UF

20%
4V

2

X6S
0201

1

C8818

0.1UF

10%

6.3V

2

X7R
0201

1

C8822

0.1UF

10%

6.3V

2

X7R
0201

8 7 6 5 4 3

Page Notes

U8800

BGA

H5GC4H24MFR-T2C

1

C8801

2

1

C8804

2

1

C8807

2

1

C8811

2

1

C8815

2

1

C8819

2

1

C8823

2

4.7UF

20%

6.3V
X6S
0402

4.7UF

20%

6.3V
X6S
0402

1.0UF

20%
4V
X6S
0201

1.0UF

20%
4V
X6S
0201

1.0UF

20%
4V
X6S
0201

0.1UF

10%

6.3V
X7R
0201

0.1UF

10%

6.3V
X7R
0201

1

R8800

120

1%
1/20W
MF
201

2

(MF=0)

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_A1_VREFC

74

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_A1_VREFD1

74

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_A1_VREFD2

74

SYM 1 OF 2

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

1

R8830

2.37K

1%
1/20W
MF
201

2

1

R8831

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8832

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8833

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8834

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8835

5.49K

1%
1/20W
MF
201

2

VSS

VSSQ

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

ZQ

J1

MF

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

FB_A1_A<2>

72 97

IN

FB_A1_A<5>

72 97

IN

FB_A1_A<4>

72 97

IN

FB_A1_A<3>

72 97

IN

FB_A1_A<7>

72 97

IN

FB_A1_A<1>

72 97

C10
D11

G11
G14

L11
L14
P11

R10

B12
B14

D12
D14

E10

F12
F14

G13

H12

K12

L13

M12
M14

N10

P12
P14

T12
T14

J14
A10
U10

IN

FB_A1_A<0>

72 97

IN

FB_A1_A<6>

72 97

IN

FB_A1_CKE_L

72 97

IN

FB_A1_CLK_P
FB_A1_CLK_N
FB_A1_CS_L

72 97

IN

FB_A1_WE_L

72 97

IN

FB_A1_CAS_L

72 97

IN

FB_A1_RAS_L

72 97

IN

FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
FB_RESET_L

72 74 75

IN

FB_A1_ABI_L

72 97

IN

FB_A1_EDC<0>

72 97

OUT

FB_A1_EDC<1>

72 97

OUT

FB_A1_EDC<3>

72 97

OUT

FB_A1_EDC<2>

72 97

OUT

FB_A1_WCLK_P<0>

72 97

IN

FB_A1_WCLK_N<0>

72 97

IN

FB_A1_WCLK_P<1>

72 97

IN

FB_A1_WCLK_N<1>

72 97

IN

U8800

BGA

H5GC4H24MFR-T2C

C5

G1
G4

VDD

L1
L4

SYM 2 OF 2

R5

B1
B3

D1
D3

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

E5

F1
F3

G2

VDDQ

H3

K3

L2

M1
M3

N5

P1
P3

T1
T3

VREFC

VREFD

1

R8801

60.4

1%
1/16W
MF-LF
402

IN
IN

1

C8802

4.7UF

20%

6.3V

2

X6S
0402

1

C8805

4.7UF

20%

6.3V

2

X6S
0402

1

C8808

1.0UF

20%
4V

2

X6S
0201

1

C8812

1.0UF

20%
4V

2

X6S
0201

1

C8816

0.1UF

10%

6.3V

2

X7R
0201

1

C8820

0.1UF

10%

6.3V

2

X7R
0201

1

C8824

0.1UF

10%

6.3V

2

X7R
0201

74

74

74

2

1

R8804

1K

5%
1/20W
MF
201

2

FB_A1_VREFC
FB_A1_VREFD1
FB_A1_VREFD2

72 97

72 97

CRITICAL

1

C8826

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C8827

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8809

1.0UF

20%
4V

2

X6S
0201

1

C8813

1.0UF

20%
4V

2

X6S
0201

1

C8817

0.1UF

10%

6.3V

2

X7R
0201

1

C8821

0.1UF

10%

6.3V

2

X7R
0201

1

C8825

0.1UF

10%

6.3V

2

X7R
0201

1

R8802

60.4

1%
1/16W
MF-LF
402

2

1

R8803

1K

5%
1/20W
MF
201

2

DBI0*
DBI1*
DBI2*
DBI3*

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VPP/NC

A12/A13

VPP/NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

D2
D13

P13

P2

A4

A2
B4

B2

E4
E2

F4
F2

A11

A13
B11

B13

E11
E13

F11

F13
U11

U13
T11

T13

N11
N13

M11

M13
U4

U2

T4
T2

N4
N2

M4

M2

A5

J5
U5

NOSTUFF

1

C8830

1.0UF

2

1

C8831

1.0UF

2

NOSTUFF

1

C8832

1.0UF

2

NOSTUFF

1

C8833

1.0UF

2

NOSTUFF

1

C8834

1.0UF

2

NOSTUFF

1

C8835

1.0UF

2

FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<3>
FB_A1_DBI_L<2>

FB_A1_DQ<2>
FB_A1_DQ<5>
FB_A1_DQ<4>
FB_A1_DQ<6>
FB_A1_DQ<1>
FB_A1_DQ<7>
FB_A1_DQ<0>
FB_A1_DQ<3>
FB_A1_DQ<8>
FB_A1_DQ<9>
FB_A1_DQ<10>
FB_A1_DQ<11>
FB_A1_DQ<12>
FB_A1_DQ<14>
FB_A1_DQ<15>
FB_A1_DQ<13>
FB_A1_DQ<28>
FB_A1_DQ<31>
FB_A1_DQ<29>
FB_A1_DQ<25>
FB_A1_DQ<27>
FB_A1_DQ<26>
FB_A1_DQ<24>
FB_A1_DQ<30>
FB_A1_DQ<21>
FB_A1_DQ<16>
FB_A1_DQ<20>
FB_A1_DQ<19>
FB_A1_DQ<17>
FB_A1_DQ<23>
FB_A1_DQ<18>
FB_A1_DQ<22>

NC

FB_A1_A<8>

NC

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

72 97

BI

72 97

BI

72 97

BI

72 97

BI

47 71 72 73 74 75 84

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

IN

PP1V35_GPU_REG

47 71 72 73 74 75 84

PP1V35_GPU_REG

1

C8850

4.7UF

20%

6.3V

2

X6S
0402

1

C8853

4.7UF

20%

6.3V

2

X6S
0402

1

C8856

1.0UF

20%
4V

2

X6S
0201

1

C8860

1.0UF

20%
4V

2

X6S
0201

1

C8864

1.0UF

20%
4V

2

X6S
0201

1

C8868

0.1UF

10%

6.3V

2

X7R
0201

1

C8872

0.1UF

10%

6.3V

2

X7R
0201

1

C8851

4.7UF

20%

6.3V

2

X6S
0402

1

C8854

4.7UF

20%

6.3V

2

X6S
0402

1

C8857

1.0UF

20%
4V

2

X6S
0201

1

C8861

1.0UF

20%
4V

2

X6S
0201

1

C8865

1.0UF

20%
4V

2

X6S
0201

1

C8869

0.1UF

10%

6.3V

2

X7R
0201

1

C8873

0.1UF

10%

6.3V

2

X7R
0201

1

R8850

120

1%
1/20W
MF
201

2

CRITICAL

1

C8876

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C8877

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8859

1.0UF

20%
4V

2

X6S
0201

1

C8863

1.0UF

20%
4V

2

X6S
0201

1

C8867

0.1UF

10%

6.3V

2

X7R
0201

1

C8871

0.1UF

10%

6.3V

2

X7R
0201

1

C8875

0.1UF

10%

6.3V

2

X7R
0201

1

R8852

60.4

1%
1/16W
MF-LF
402

2

1

R8853

1K

5%
1/20W
MF
201

2

C5

C10
D11

G1

G4
G11

G14

L1

L4

L11

L14
P11

R5
R10

B1

B3

B12

B14

D1

D3

D12
D14

E5
E10

F1

F3
F12

F14

G2
G13

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12
P14

T1

T3
T12

T14

J14

A10

U10

1

R8851

60.4

1%
1/16W
MF-LF
402

IN
IN

1

2

1

2

1

2

1

2

1

2

1

2

1

2

C8852

4.7UF

20%

6.3V
X6S
0402

C8855

4.7UF

20%

6.3V
X6S
0402

C8858

1.0UF

20%
4V
X6S
0201

C8862

1.0UF

20%
4V
X6S
0201

C8866

0.1UF

10%

6.3V
X7R
0201

C8870

0.1UF

10%

6.3V
X7R
0201

C8874

0.1UF

10%

6.3V
X7R
0201

74

74

74

2

1

R8854

1K

5%
1/20W
MF
201

2

FB_A0_VREFC
FB_A0_VREFD1
FB_A0_VREFD2

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 74 75

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

VDD

VDDQ

VREFC

VREFD

FB_A0_A<2>

IN

FB_A0_A<5>

IN

FB_A0_A<4>

IN

FB_A0_A<3>

IN

FB_A0_A<7>

IN

FB_A0_A<1>

IN

FB_A0_A<0>

IN

FB_A0_A<6>

IN

FB_A0_CKE_L

IN

FB_A0_CLK_P
FB_A0_CLK_N
FB_A0_CS_L

IN

FB_A0_WE_L

IN

FB_A0_CAS_L

IN

FB_A0_RAS_L

IN

FB_A0_ZQ
FB_A0_MF
FB_A0_SEN

FB_RESET_L

IN

FB_A0_ABI_L

IN

FB_A0_EDC<0>

OUT

FB_A0_EDC<1>

OUT

FB_A0_EDC<3>

OUT

FB_A0_EDC<2>

OUT

FB_A0_WCLK_P<0>

IN

FB_A0_WCLK_N<0>

IN

FB_A0_WCLK_P<1>

IN

FB_A0_WCLK_N<1>

IN

H5GC4H24MFR-T2C

SYM 2 OF 2

OMIT_TABLE

U8850

BGA

GDDR5-128MX32-4GB-38NM-MFL

6 3

VSSQ

VSS

12

U8850

BGA

H5GC4H24MFR-T2C

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

ZQ

J1

MF

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

B5

B10
D10

G5

G10
H1

H14

K1
K14

L5

L10
P10

T5
T10

A1

A3

A12
A14

C1
C3

C4

C11
C12

C14

E1
E3

E12

E14
F5

F10
H2

H13

K2
K13

M5

M10
N1

N3

N12
N14

R1
R3

R4

R11
R12

R14

U1
U3

U12

U14

SYM 1 OF 2

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

(MF=0)

84

PP1V35_GPU_REG PP1V35_GPU_REG

47 71 72
73 74 75

FB_A0_VREFC

74

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_A0_VREFD1

74

1

R8880

2.37K

1%
1/20W
MF
201

2

1

R8881

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8882

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8883

5.49K

1%
1/20W
MF
201

2

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

VPP/NC

A12/A13

VPP/NC

SYNC_MASTER=MARY_X425G

PAGE TITLE

J5

U5

1

2

1

2

1

2

1

2

NC

NC

NOSTUFF

C8880

1.0UF

20%
4V
X6S
0201

C8881

1.0UF

20%
4V
X6S
0201

NOSTUFF

C8882

1.0UF

20%
4V
X6S
0201

NOSTUFF

C8883

1.0UF

20%
4V
X6S
0201

FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<3>
FB_A0_DBI_L<2>

FB_A0_DQ<4>
FB_A0_DQ<7>
FB_A0_DQ<5>
FB_A0_DQ<6>
FB_A0_DQ<0>
FB_A0_DQ<3>
FB_A0_DQ<2>
FB_A0_DQ<1>
FB_A0_DQ<8>
FB_A0_DQ<10>
FB_A0_DQ<9>
FB_A0_DQ<12>
FB_A0_DQ<11>
FB_A0_DQ<15>
FB_A0_DQ<13>
FB_A0_DQ<14>
FB_A0_DQ<24>
FB_A0_DQ<25>
FB_A0_DQ<26>
FB_A0_DQ<30>
FB_A0_DQ<29>
FB_A0_DQ<28>
FB_A0_DQ<27>
FB_A0_DQ<31>
FB_A0_DQ<19>
FB_A0_DQ<17>
FB_A0_DQ<18>
FB_A0_DQ<16>
FB_A0_DQ<22>
FB_A0_DQ<23>
FB_A0_DQ<21>
FB_A0_DQ<20>

FB_A0_A<8>

47 71 72 73 74 75 84

FB_A0_VREFD2

74

GDDR5 Frame Buffer A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

NOSTUFF

1

R8884

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8885

5.49K

1%
1/20W
MF
201

2

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

NOSTUFF

1

C8884

2

1

C8885

2

SYNC_DATE=09/22/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

88 OF 119

SHEET

74 OF 97

1.0UF

20%
4V
X6S
0201

NOSTUFF

1.0UF

20%
4V
X6S
0201

SIZE

D

C

B

GPU

A

D

124578

Power aliases required by this page:

www.repairlap.com

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

C

74 75

PP1V35_GPU_REG

47 71
72 73
84

B

A

PP1V35_GPU_REG

47 71 72 73 74 75 84

1

C8900

4.7UF

20%

6.3V

2

X6S
0402

1

C8903

4.7UF

20%

6.3V

2

X6S
0402

1

C8906

1.0UF

20%
4V

2

X6S
0201

1

C8910

1.0UF

20%
4V

2

X6S
0201

1

C8914

1.0UF

20%
4V

2

X6S
0201

1

C8918

0.1UF

10%

6.3V

2

X7R
0201

1

C8922

0.1UF

10%

6.3V

2

X7R
0201

8 7 6 5 4 3

Page Notes

U8900

BGA

H5GC4H24MFR-T2C

1

C8901

2

1

C8904

2

1

C8907

2

1

C8911

2

1

C8915

2

1

C8919

2

1

C8923

2

4.7UF

20%

6.3V
X6S
0402

4.7UF

20%

6.3V
X6S
0402

1.0UF

20%
4V
X6S
0201

1.0UF

20%
4V
X6S
0201

1.0UF

20%
4V
X6S
0201

0.1UF

10%

6.3V
X7R
0201

0.1UF

10%

6.3V
X7R
0201

1

R8900

120

1%
1/20W
MF
201

2

(MF=0)

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_B1_VREFC

75

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_B1_VREFD1

75

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_B1_VREFD2

75

SYM 1 OF 2

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

1

R8930

2.37K

1%
1/20W
MF
201

2

1

R8931

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8932

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8933

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8934

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8935

5.49K

1%
1/20W
MF
201

2

VSS

VSSQ

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

ZQ

J1

MF

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

B5
B10

D10
G5

G10

H1
H14

K1

K14
L5

L10

P10
T5

T10

A1
A3

A12

A14
C1

C3
C4

C11

C12
C14

E1

E3
E12

E14

F5
F10

H2
H13

K2

K13
M5

M10

N1
N3

N12

N14
R1

R3
R4

R11

R12
R14

U1

U3
U12

U14

FB_B1_A<2>

72 97

IN

FB_B1_A<5>

72 97

IN

FB_B1_A<4>

72 97

IN

FB_B1_A<3>

72 97

IN

FB_B1_A<7>

72 97

IN

FB_B1_A<1>

72 97

1

R8901

60.4

1%
1/16W
MF-LF
402

IN
IN

1

C8902

4.7UF

20%

6.3V

2

X6S
0402

1

C8905

4.7UF

20%

6.3V

2

X6S
0402

1

C8908

1.0UF

20%
4V

2

X6S
0201

1

C8912

1.0UF

20%
4V

2

X6S
0201

1

C8916

0.1UF

10%

6.3V

2

X7R
0201

1

C8920

0.1UF

10%

6.3V

2

X7R
0201

1

C8924

0.1UF

10%

6.3V

2

X7R
0201

75

75

75

2

1

R8904

1K

5%
1/20W
MF
201

2

FB_B1_VREFC
FB_B1_VREFD1
FB_B1_VREFD2

72 97

72 97

CRITICAL

1

C8926

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C8927

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8909

1.0UF

20%
4V

2

X6S
0201

1

C8913

1.0UF

20%
4V

2

X6S
0201

1

C8917

0.1UF

10%

6.3V

2

X7R
0201

1

C8921

0.1UF

10%

6.3V

2

X7R
0201

1

C8925

0.1UF

10%

6.3V

2

X7R
0201

1

R8902

60.4

1%
1/16W
MF-LF
402

2

1

R8903

1K

5%
1/20W
MF
201

2

IN

FB_B1_A<0>

72 97

IN

FB_B1_A<6>

72 97

IN

FB_B1_CKE_L

72 97

IN

FB_B1_CLK_P
FB_B1_CLK_N
FB_B1_CS_L

72 97

IN

FB_B1_WE_L

72 97

IN

FB_B1_CAS_L

72 97

IN

FB_B1_RAS_L

72 97

IN

FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
FB_RESET_L

72 74 75

IN

FB_B1_ABI_L

72 97

IN

FB_B1_EDC<0>

72 97

OUT

FB_B1_EDC<1>

72 97

OUT

FB_B1_EDC<3>

72 97

OUT

FB_B1_EDC<2>

72 97

OUT

FB_B1_WCLK_P<0>

72 97

IN

FB_B1_WCLK_N<0>

72 97

IN

FB_B1_WCLK_P<1>

72 97

IN

FB_B1_WCLK_N<1>

72 97

IN

U8900

BGA

H5GC4H24MFR-T2C

C5
C10

D11

G1

G4

G11
G14

VDD

L1

L4
L11

L14

P11

R5

R10

B1

B3
B12

B14

D1

D3

D12

D14

E5

E10

F1

F3

F12
F14

G2

G13

H3

H12

K3
K12

L2
L13

M1

M3
M12

M14

N5
N10

P1

P3
P12

P14

T1

T3

T12
T14

J14

VREFC

A10

VREFD

U10

SYM 2 OF 2

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

VDDQ

DBI0*
DBI1*
DBI2*
DBI3*

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VPP/NC

A12/A13

VPP/NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

D2
D13
P13
P2

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

A5
J5
U5

NOSTUFF

1

C8930

1.0UF

2

1

C8931

1.0UF

2

NOSTUFF

1

C8932

1.0UF

2

NOSTUFF

1

C8933

1.0UF

2

NOSTUFF

1

C8934

1.0UF

2

1

C8935

1.0UF

2

NC

NC

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

20%
4V
X6S
0201

NOSTUFF

20%
4V
X6S
0201

FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<3>
FB_B1_DBI_L<2>

FB_B1_DQ<3>
FB_B1_DQ<4>
FB_B1_DQ<6>
FB_B1_DQ<1>
FB_B1_DQ<2>
FB_B1_DQ<0>
FB_B1_DQ<5>
FB_B1_DQ<7>
FB_B1_DQ<10>
FB_B1_DQ<9>
FB_B1_DQ<8>
FB_B1_DQ<13>
FB_B1_DQ<11>
FB_B1_DQ<15>
FB_B1_DQ<12>
FB_B1_DQ<14>
FB_B1_DQ<30>
FB_B1_DQ<31>
FB_B1_DQ<28>
FB_B1_DQ<29>
FB_B1_DQ<26>
FB_B1_DQ<27>
FB_B1_DQ<25>
FB_B1_DQ<24>
FB_B1_DQ<23>
FB_B1_DQ<22>
FB_B1_DQ<20>
FB_B1_DQ<21>
FB_B1_DQ<19>
FB_B1_DQ<18>
FB_B1_DQ<17>
FB_B1_DQ<16>

FB_B1_A<8>

72 97

BI

72 97

BI

72 97

BI

72 97

BI

47 71 72 73 74 75 84

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

BI

72 97

IN

PP1V35_GPU_REG

47 71 72 73 74 75 84

PP1V35_GPU_REG

1

C8950

4.7UF

20%

6.3V

2

X6S
0402

1

C8953

4.7UF

20%

6.3V

2

X6S
0402

1

C8956

1.0UF

20%
4V

2

X6S
0201

1

C8960

1.0UF

20%
4V

2

X6S
0201

1

C8964

1.0UF

20%
4V

2

X6S
0201

1

C8968

0.1UF

10%

6.3V

2

X7R
0201

1

C8972

0.1UF

10%

6.3V

2

X7R
0201

1

C8951

4.7UF

20%

6.3V

2

X6S
0402

1

C8954

4.7UF

20%

6.3V

2

X6S
0402

1

C8957

1.0UF

20%
4V

2

X6S
0201

1

C8961

1.0UF

20%
4V

2

X6S
0201

1

C8965

1.0UF

20%
4V

2

X6S
0201

1

C8969

0.1UF

10%

6.3V

2

X7R
0201

1

C8973

0.1UF

10%

6.3V

2

X7R
0201

1

R8950

120

1%
1/20W
MF
201

2

CRITICAL

1

C8976

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C8977

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C8959

1.0UF

20%
4V

2

X6S
0201

1

C8963

1.0UF

20%
4V

2

X6S
0201

1

C8967

0.1UF

10%

6.3V

2

X7R
0201

1

C8971

0.1UF

10%

6.3V

2

X7R
0201

1

C8975

0.1UF

10%

6.3V

2

X7R
0201

1

R8952

60.4

1%
1/16W
MF-LF
402

2

1

R8953

1K

5%
1/20W
MF
201

2

C5

C10
D11

G1

G4
G11

G14

L1

L4

L11

L14
P11

R5
R10

B1

B3

B12

B14

D1

D3

D12
D14

E5
E10

F1

F3
F12

F14

G2
G13

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12
P14

T1

T3
T12

T14

J14

A10

U10

1

R8951

60.4

1%
1/16W
MF-LF
402

IN
IN

1

2

1

2

1

2

1

2

1

2

1

2

1

2

C8952

4.7UF

20%

6.3V
X6S
0402

C8955

4.7UF

20%

6.3V
X6S
0402

C8958

1.0UF

20%
4V
X6S
0201

C8962

1.0UF

20%
4V
X6S
0201

C8966

0.1UF

10%

6.3V
X7R
0201

C8970

0.1UF

10%

6.3V
X7R
0201

C8974

0.1UF

10%

6.3V
X7R
0201

75

75

75

2

1

R8954

1K

5%
1/20W
MF
201

2

FB_B0_VREFC
FB_B0_VREFD1
FB_B0_VREFD2

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 74 75

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

VDD

VDDQ

VREFC

VREFD

FB_B0_A<2>

IN

FB_B0_A<5>

IN

FB_B0_A<4>

IN

FB_B0_A<3>

IN

FB_B0_A<7>

IN

FB_B0_A<1>

IN

FB_B0_A<0>

IN

FB_B0_A<6>

IN

FB_B0_CKE_L

IN

FB_B0_CLK_P
FB_B0_CLK_N
FB_B0_CS_L

IN

FB_B0_WE_L

IN

FB_B0_CAS_L

IN

FB_B0_RAS_L

IN

FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
FB_RESET_L

IN

FB_B0_ABI_L

IN

FB_B0_EDC<1>

OUT

FB_B0_EDC<0>

OUT

FB_B0_EDC<2>

OUT

FB_B0_EDC<3>

OUT

FB_B0_WCLK_P<0>

IN

FB_B0_WCLK_N<0>

IN

FB_B0_WCLK_P<1>

IN

FB_B0_WCLK_N<1>

IN

H5GC4H24MFR-T2C

SYM 2 OF 2

U8950

BGA

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

6 3

VSSQ

VSS

12

U8950

BGA

H5GC4H24MFR-T2C

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

ZQ

J1

MF

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

B5

B10
D10

G5

G10
H1

H14

K1
K14

L5

L10
P10

T5
T10

A1

A3

A12
A14

C1
C3

C4

C11
C12

C14

E1
E3

E12

E14
F5

F10
H2

H13

K2
K13

M5

M10
N1

N3

N12
N14

R1
R3

R4

R11
R12

R14

U1
U3

U12

U14

SYM 1 OF 2

GDDR5-128MX32-4GB-38NM-MFL

OMIT_TABLE

(MF=0)

84

PP1V35_GPU_REG PP1V35_GPU_REG

47 71 72
73 74 75

FB_B0_VREFC

75

84

PP1V35_GPU_REG

47 71 72
73 74 75

FB_B0_VREFD1

75

1

R8980

2.37K

1%
1/20W
MF
201

2

1

R8981

5.49K

1%
1/20W
MF
201

2

NOSTUFF

1

R8982

2.37K

1%
1/20W
MF
201

2

1

R8983

5.49K

1%
1/20W
MF
201

2

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

VPP/NC

A12/A13

VPP/NC

SYNC_MASTER=MARY_X425G

PAGE TITLE

J5
U5

1

2

1

2

1

2

1

2

NC

NC

NOSTUFF

C8980

1.0UF

20%
4V
X6S
0201

C8981

1.0UF

20%
4V
X6S
0201

NOSTUFF

C8982

1.0UF

20%
4V
X6S
0201

NOSTUFF

C8983

1.0UF

20%
4V
X6S
0201

FB_B0_DBI_L<1>
FB_B0_DBI_L<0>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>

FB_B0_DQ<8>
FB_B0_DQ<9>
FB_B0_DQ<10>
FB_B0_DQ<11>
FB_B0_DQ<14>
FB_B0_DQ<13>
FB_B0_DQ<15>
FB_B0_DQ<12>
FB_B0_DQ<0>
FB_B0_DQ<5>
FB_B0_DQ<1>
FB_B0_DQ<4>
FB_B0_DQ<6>
FB_B0_DQ<7>
FB_B0_DQ<2>
FB_B0_DQ<3>
FB_B0_DQ<21>
FB_B0_DQ<23>
FB_B0_DQ<18>
FB_B0_DQ<22>
FB_B0_DQ<20>
FB_B0_DQ<16>
FB_B0_DQ<17>
FB_B0_DQ<19>
FB_B0_DQ<31>
FB_B0_DQ<29>
FB_B0_DQ<30>
FB_B0_DQ<26>
FB_B0_DQ<27>
FB_B0_DQ<24>
FB_B0_DQ<28>
FB_B0_DQ<25>

FB_B0_A<8>

47 71 72 73 74 75 84

FB_B0_VREFD2

75

GDDR5 Frame Buffer B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

NOSTUFF

1

R8984

2.37K

1%
1/20W
MF
201

2

NOSTUFF

1

R8985

5.49K

1%
1/20W
MF
201

2

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

72 97

NOSTUFF

1

C8984

2

1

C8985

2

SYNC_DATE=09/22/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

89 OF 119

SHEET

75 OF 97

1.0UF

20%
4V
X6S
0201

NOSTUFF

1.0UF

20%
4V
X6S
0201

SIZE

D

C

B

GPU

A

D

124578

8 7 6 5 4 3

HSYNC
VSYNC

RSET

AVDD

AVSSQ

VDD1DI
VSS1DI

AVSSN0
AVSSN1
AVSSN2

CEC_1

CLKREQ*

DDC1CLK

DDC1DATA

AUX1P
AUX1N

DDC2CLK

DDC2DATA

AUX2P
AUX2N

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

AD39

R

AE36

G

AF37

B

AC36
AC38

AB34

AD34
AE34

AC33
AC34

AE38
AD35
AD37

AD29
AC29

AC30
AN13

AF33

AF31
AF30

AM26
AN26

AM27
AL27

AM19
AL19

AN20
AM20

AL30
AM30

AL29
AM29

AN21
AM21

AJ30
AJ31

AK30
AK29

DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>
DP_TBTSNK0_ML_C_N<0>

NC
NC

NC
NC

NC
NC

NC
NC

DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_N<0>

NC
NC

NC
NC

NC
NC

NC
NC

NC

Straps for audio on DP and HDMI

NC

NC

GPU_AUD_1
GPU_AUD_0

GPU_RSET

R9004

10K

1/20W

R9050

5%

MF

201

PP1V8_GPUIFPX

NC
NC

NC

TP_CLKREQ_L

NC

NC
NC

DPA_EG_DDC_CLK
DPA_EG_DDC_DATA

DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N

DPB_EG_DDC_CLK
DPB_EG_DDC_DATA

DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N

NC
NC

NC
NC

HDMI_EG_DDC_CLK_Q
HDMI_EG_DDC_DATA_Q

NC
NC

DP_INT_EG_AUX_P
DP_INT_EG_AUX_N

PP3V3_S0GPU

1

2

499

21

1/20W

201

1

R9005

10K

5%
1/20W
MF
201

2

MF
1%

71 76 78 80 84

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

28 89 97

OUT

77

77 83

OUT

77 83

BI

77 83 97

BI

77 83 97

BI

77 83

OUT

77 83

BI

77 83 97

BI

77 83 97

BI

77 82 97

BI

77 82 97

BI

47 66 68 71 72 76 77 79 80 84

PP3V3_S0GPU

47 66 68 71 72 76 77 79
80 84

1

R9025

4.7K

1%
1/20W
MF
201

2

OMIT_TABLE

1

R9026

4.7K

1%
1/20W
MF
201

2

Power aliases required by this page:

- =PP3V3_GPU_I2C

- =PP1V8_GPU_VREFG

- =PP1V8_GPU_DPLL

- =PP1V0_GPU_DPLL

- =PP1V0_GPU_TS

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

AK27

U8400

VENUS-XT

FCBGA

(3 OF 9)

VARY_BL

DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXOUT_U3P
TXOUT_U3N

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

TXOUT_L3P
TXOUT_L3N

SYNC_MASTER=MARY_X425G

PAGE TITLE

AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

5

G

S D

4

2

G

S D

1

Venus HDMI/DP/GPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Page Notes

GPU_LCD_BLK_PWM
EG_LCD_PWR_EN

DP_INT_EG_ML_P<3>
DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<2>
DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<0>
DP_INT_EG_ML_N<0>

NC
NC

HDMI_EG_CLK_P
HDMI_EG_CLK_N

HDMI_EG_DATA_P<0>
HDMI_EG_DATA_N<0>

HDMI_EG_DATA_P<1>
HDMI_EG_DATA_N<1>

HDMI_EG_DATA_P<2>
HDMI_EG_DATA_N<2>

NC
NC

CRITICAL

Q9000

DMN5L06VK-7

SOT563

VER 5

3

HDMI_EG_DDC_CLK

CRITICAL

Q9000

DMN5L06VK-7

SOT563

VER 5

6

HDMI_EG_DDC_DATA

DDC 3.3V level isolation

NC
NC

NC
NC

NC

NOSTUFF

1

R9024

1K

5%
1/20W
MF
201

2

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AK26

SCL

AJ26

SDA

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AJ23

SMBCLK

AH23

SMBDATA

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCS*

AK32

GPIO_28_FDO

AG32

GPIO_29

AG33

GPIO_30

AM23

JTAG_TRST*

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AK24

HPD1

AH13

VREFG

AV33

XTALIN

AU34

XTALOUT

AW34

XO_IN

AW35

XO_IN2

AF29

DPLUS

AG29

DMINUS

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

U8400

VENUS-XT

FCBGA

(2 OF 9)

OMIT_TABLE

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P
TXCCM_DPC3N

TX0P_DPC2P
TX0M_DPC2N

TX1P_DPC1P
TX1M_DPC1N

TX2P_DPC0P
TX2M_DPC0N

TXCDP_DPD3P
TXCDM_DPD3N

TX3P_DPD2P
TX3M_DPD2N

TX4P_DPD1P
TX4M_DPD1N

TX5P_DPD0P
TX5M_DPD0N

GENLK_CLK

GENLK_VSYNC

NC_TSVSSQ

NC_XTAL_PVSS
NC_XTAL_PVDD

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCVGACLK

DDCVGADATA

DDCCLK_AUX6P

DDCDATA_AUX6N

NC_DVPCNTL_M<0>

87

NC_DVPCNTL_M<1>

87

NC_DVPCNTL<0>

87

NC_DVPCNTL<1>

87

NC_DVPCNTL<2>

87

NC_DVPCLK

87

TP_DVPDATA<0>
TP_DVPDATA<1>
TP_DVPDATA<2>
TP_DVPDATA<3>

D

GPU Int Temp Sense can not be read through SMBUS

CRITICAL

Q9010

SMBUS "0"

36 40 43 48 69

OUT

85 86 95

SMBUS_SMC_0_S0_SCL

DMN5L06VK-7

SOT563

VER 5

6

2

G

SD

1

C

CRITICAL

Q9010

36 40 43 48 69

BI

85 86 95

SMBUS_SMC_0_S0_SDA

DMN5L06VK-7

SOT563

VER 5

3

5

G

SD

4

B

PP1V8_GPUIFPX

71 76 78 80 84

1

PLACE_NEAR=U8400.AH13:2.54MM

R9002

499

1%

1/20W

MF

201

2

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

R9020

4.7K

1/20W

1

5%

MF

201

2

1

R9021

4.7K

2

1

R9035

10K

5%
1/20W
MF
201

2

5%
1/20W
MF
201

77 80

77

77

77

77 79

77 82

77

77

77

77 79

77 79

77 79

77 82

77 79

77 79

77

77 82

77

77 79

73 77

77

77

77 79

77 86

77 86

77 86

77 86

77 86

77

77

77

77

77

77 82

77

77 82

TP_DVPDATA<4>
TP_DVPDATA<5>
NC_DVPDATA<6>

87

NC_DVPDATA<7>

87

NC_DVPDATA<8>

87

NC_DVPDATA<9>

87

NC_DVPDATA<10>

87

NC_DVPDATA<11>

87

NC_DVPDATA<12>

87

NC_DVPDATA<13>

87

NC_DVPDATA<14>

87

NC_DVPDATA<15>

87

NC_DVPDATA<16>

87

NC_DVPDATA<17>

87

NC_DVPDATA<18>

87

NC_DVPDATA<19>

87

NC_DVPDATA<20>

87

NC_DVPDATA<21>
NC_DVPDATA<22>

87

NC_DVPDATA<23>

87

GFX_VDDCI_ALTV
NC_GPU_GPIO_1
NC_GPU_GPIO_2
GPU_SMB_CLK
GPU_SMB_DAT
GPU_GFX_PWR_LEVEL_R_L
GFXIMVP_VR_ICCMAX_WARN_L
EG_BKLT_EN
GPU_ROM_SO
GPU_ROM_SI
GPU_ROM_SCLK
GPU_VCORE_VID4
GPU_VCORE_VID5
GPU_VCORE_VID0
DP_TBTSNK1_HPD_EG
GPU_VCORE_VID1
GPU_VCORE_VID2
GFX_SELF_THROTTLE_R
HDMI_EG_HPD
GPU_GFX_OVERTEMP_R
GPU_VCORE_VID3
FBVDD_ALTVO
GPU_ROM_CS_L
GPU_MLPS_EN_L
GPU_VCORE_PSI_L
GFXIMVP_DPSLP_EN_R

GPU_JTAG_TRST_L
GPU_JTAG_TDI
GPU_JTAG_TCK
GPU_JTAG_TMS
GPU_JTAG_TDO

NC_GPU_GENERICA
NC_GPU_GENERICB
NC_DP_EXTB_CA_DET_EG
NC_DP_EXTA_CA_DET_EG
NC_GPU_GPIO_33
DP_INT_EG_HPD
NC_GPU_GPIO_35

DP_TBTSNK0_HPD_EG

GPU_VREFG

PLACE_NEAR=U8400.AH13:2.54MM

C9000

0.1UF

1

10%

6.3V
2

X7R

0201

A

PP1V8_GPUIFPX

84
71 76
78 80

120OHM-25%-1.8A-0.06DCR

PLACE_NEAR=L9002.1:2.54MM

1

C9015

0.1UF

XW9001

10%

6.3V

2

X7R
0201

R9003

249

1/20W

201

CRITICAL

L9002

0402

SM

1

1%
MF

2

21

PLACE_NEAR=U8400.AH13:2.54MM

1

C9080

15PF

5%

50V

2

C0G

0201

21

PLACE_NEAR=U8400.AJ32:2.54MM

1

C9007

10UF

20%

6.3V

2

CERM-X6S
0402

CRITICAL

Y9000

2.50X2.00MM-SM

27MHZ-30PPM-12PF-40OHM

R9082

1M

1/20W

5%

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

1

C9008

2

1.0UF

20%
4V
X6S
0201

VOLTAGE=1.8V

1

2

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

31

42

201

MF

C9009

0.1UF

10%

6.3V
X7R
0201

1

2

21

PLACE_NEAR=U8400.AJ32:2.54MM

GND_GPU_TSVSS

C9081

15PF

5%
50V
C0G
0201

PP1V8_GPU_TSVDD

(GND_GPU_TSVSS)

VOLTAGE=0V

48 96

IN

48 96

OUT

GPU_27M_XTAL_IN
GPU_27M_XTAL_OUT

PD_GPU_CLK27M

PD_GPU_CLK100M

GPU_TDIODE_P
GPU_TDIODE_N

8mA

NOSTUFF

1

R9023

1K

5%
1/20W
MF
201

2

6 3

12

1

2

77 82

OUT

OUT

BI

SYNC_DATE=09/22/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

90 OF 119

SHEET

76 OF 97

124578

R9006

10K

5%
1/20W
MF
201

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

81

81

82 97

82 97

82 97

82 97

82 97

82 97

82 97

82 97

81 86 97

81 86 97

81 86 97

81 86 97

81 86 97

81 86 97

81 86 97

81 86 97

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

GPU GPIO TABLE

Native Func

Native Func

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GP

GFX_VDDCI_ALTV

76 77 80

NC_GPU_GPIO_1

76 77

NC_GPU_GPIO_2

76 77

GPU_GFX_PWR_LEVEL_R_L

76 77

GFXIMVP_VR_ICCMAX_WARN_L

D

76 77 79

EG_BKLT_EN

76 77 82

GPU_ROM_SO

76 77

GPU_ROM_SI

76 77

GPU_ROM_SCLK

GPU_VCORE_VID4

76 77 79

GPU_VCORE_VID5

76 77 79

GPU_VCORE_VID0

76 77 79

DP_TBTSNK1_HPD_EG

76 77 82

GPU_VCORE_VID1

76 77 79

GPU_VCORE_VID2

76 77 79

GFX_SELF_THROTTLE_R

76 77

HDMI_EG_HPD

76 77 82

GPU_GFX_OVERTEMP_R

76 77

GPU_VCORE_VID3

76 77 79

FBVDD_ALTVO

73 76 77

GPU_ROM_CS_L

C

76 77

TP_CLKREQ_L

76 77

NC_GPU_GENERICA

76 77

NC_GPU_GENERICB

76 77

GPU_VCORE_PSI_L

76 77

GFXIMVP_DPSLP_EN_R

76 77 79

NC_DP_EXTB_CA_DET_EG

76 77

NC_DP_EXTA_CA_DET_EG

76 77

NC_GPU_GPIO_33

76 77

DP_INT_EG_HPD

76 77 82

NC_GPU_GPIO_35

76 77

DP_TBTSNK0_HPD_EG

76 77 82

GPIOs

GPIOs

GFX_VDDCI_ALTV

MAKE_BASE=TRUE

NC_GPU_GPIO_1

MAKE_BASE=TRUE

NC_GPU_GPIO_2

MAKE_BASE=TRUE

GPU_GFX_PWR_LEVEL_R_L

MAKE_BASE=TRUE

GFXIMVP_VR_ICCMAX_WARN_L

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

GPU_ROM_SO

MAKE_BASE=TRUE

GPU_ROM_SI

MAKE_BASE=TRUE

GPU_ROM_SCLK

MAKE_BASE=TRUE

GPU_VCORE_VID4

MAKE_BASE=TRUE

GPU_VCORE_VID5

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_EG

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

GFX_SELF_THROTTLE_R

MAKE_BASE=TRUE

HDMI_EG_HPD

MAKE_BASE=TRUE

GPU_GFX_OVERTEMP_R

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

FBVDD_ALTVO

MAKE_BASE=TRUE

GPU_ROM_CS_L

MAKE_BASE=TRUE

TP_CLKREQ_L

MAKE_BASE=TRUE

NC_GPU_GENERICA

MAKE_BASE=TRUE

NC_GPU_GENERICB

MAKE_BASE=TRUE

GPU_VCORE_PSI_L

MAKE_BASE=TRUE

GFXIMVP_DPSLP_EN_R

MAKE_BASE=TRUE

NC_DP_EXTB_CA_DET_EG

MAKE_BASE=TRUE

NC_DP_EXTA_CA_DET_EG

MAKE_BASE=TRUE

NC_GPU_GPIO_33

MAKE_BASE=TRUE

DP_INT_EG_HPD

MAKE_BASE=TRUE

NC_GPU_GPIO_35

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_EG

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

76 77 80

76 77

76 77

76 77

76 77 79

76 77 82

76 77

76 77

76 77 76 77

76 77 79

76 77 79

76 77 79

76 77 82

76 77 79

76 77 79

76 77

76 77 82

76 77

76 77 79

73 76 77

76 77

76 77

76 77

76 77

76 77

76 77 79

76 77

76 77

76 77

76 77 82

76 77

76 77 82

76 82 97

BI

76 82 97

BI

76 83 97

BI

76 83 97

BI

76 83 97

BI

76 83 97

BI

PLACE_NEAR=U8400.AM27:2.54MM

PLACE_NEAR=U8400.AM26:2.54MM

76 83

IN

76 83

BI

76 83

IN

76 83

BI

DP_INT_EG_AUX_N

DP_INT_EG_AUX_P

DP_TBTSNK0_EG_AUXCH_N
DP_TBTSNK0_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_N
DP_TBTSNK1_EG_AUXCH_P

PLACE_NEAR=U8400.AL27:2.54MM

NOSTUFF

R9173

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

PLACE_NEAR=U8400.AN26:2.54MM

NOSTUFF

R9150

DPA_EG_DDC_CLK

DPA_EG_DDC_DATA

DPB_EG_DDC_CLK

DPB_EG_DDC_DATA

AMD AUX PD

NOSTUFF

2

R9172

100K

MF

1

5%

1/20W

100K

1/20W

5%

MF

201

201

1

2

DDC PULL UP

PLACE_NEAR=U8400.AM19:2.54MM

NOSTUFF

1

470K

1/16W
MF-LF

R9151

5%

402

470K

5%
1/16W
MF-LF

2

402

PLACE_NEAR=U8400.AN20:2.54MM

1

2

PLACE_NEAR=U8400.AM20:2.54MM

NOSTUFF

R9171

PLACE_NEAR=U8400.AL19:2.54MM

470K

1/16W
MF-LF

NOSTUFF

1

5%

402

2

NOSTUFF

R9154

100K

1/20W

201

R9155

470K

1/16W
MF-LF

PLACE_NEAR=U8400.AK30:2.54MM

NOSTUFF

2

R9170

100K

1

MF

5%

1/20W

201

5%

MF

2

5%

402

1

1

2

PLACE_NEAR=U8400.AK29:2.54MM

NOSTUFF

R9174

100K

1/20W

NOSTUFF

1

R9175

5%
MF

201

2

100K

1/20W

1

5%
MF

201

2

D

C

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

1

GPU ROM

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

GPU_ROM:YES

1

R9120

10K

5%

1/20W

MF

201

2

GPU_ROM_SI_R

GPU_ROM_SCLK_R

GPU_ROM_CS_L_R

GPU_ROM_WP_L

NO STUFF

1

R9122

100K

5%
1/20W
MF
201

2

R9121

1/20W

10K

1

5%

MF

201

2

1

3

7

5

6

D

C

S*

W*

HOLD*

VCC

U9101

M25P10A

UFDFPN8

CRITICAL

OMIT_TABLE

VSS

489

THRM

PAD

B

GPU_ROM_SI

76 77

GPU_ROM:YES

GPU_ROM_SCLK

76 77

GPU_ROM:YES

GPU_ROM_CS_L

76 77

GPU_ROM:YES

R9123

33

5%

1/20W

MF

201

R9124

33

5%

1/20W

MF

201

R9125

33

5%

1/20W

MF

201

GPU_ROM:YES

21

21

21

2

Q

GPU_ROM:YES

1

C9121

0.1UF

10%

6.3V

2

X7R
0201

GPU_ROM_SO_R

GPU_ROM:YES

R9126

33

5%

1/20W

MF

201

21

GPU_ROM_SO

76 77

(GPIO5)

(GPIO17)

GPU_GFX_PWR_LEVEL_R_L

76 77

76 77

47

IN

GPU_VCORE_PSI_L

76 77

76
77

76 77 82

GPU_GFX_OVERTEMP_R

GPUCORE_VR_ICCWARN_BUF_L

GFX_SELF_THROTTLE_R

HDMI_EG_HPD

R9197

10K

1/20W

5%
MF

201

2

R9128

5%

0

MF

JTAG signals

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

NOSTUFF

1

R9160

R9164

10K

1/20W

10K

5%

1/20W

MF

201

2

1

5%

MF

201

2

A

R9161

10K

1/20W

1

5%

MF

201

2

R9162

10K

1/20W

1

5%

MF

201

2

R9163

10K

1/20W

1

5%

MF

201

2

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_JTAG_TDO

GPU_JTAG_TMS

GPU_JTAG_TRST_L

76 86

76 86

76 86

76 86

76 86

R9198

1/20W

10K

5%

MF

201

6 3

GPU GPIO PU/PD

(PD on GUMX page)

PU on U5760 and VR page

21

GFXIMVP_VR_ICCMAX_WARN_L

1/20W

MAKE_BASE=TRUE

201

(PU on VR page)

(PD on GMUX page)

1

R9192

1

2

1/20W

10K

5%

MF

201

2

R9193

1/20W

10K

R9181

0

R9158

GFXIMVP_VR_ICCMAX_WARN_L

76 77 79

R9182

R9199

1

1

R9194

10K

5%

5%

1/20W

MF

201

MF

201

2

2

0

0

21

5%

0

21

5%

GPUCORE_VR_ICCMAX_WARN_L
logic low if GPUCORE VR ICCMAX above 61A
logic high if GPUCORE VR ICCMAX not more than 61A

21

5%

21

5%

GPU_GFX_PWR_LEVEL_L

1/16W MF-LF

GPU_GFX_OVERTEMP

1/20W

MF

GFXIMVP_PSI_L

MF-LF1/16W

GFX_SELF_THROTTLE

MF-LF

1/16W

402

201

402

402

EG_LCD_PWR_EN

EG_BKLT_EN

FBVDD_ALTVO

SYNC_MASTER=MARY_X425G

PAGE TITLE

Venus GPIOs & STRAPs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

82

82

76 77 79

79

82

76 82

76 77 82

73 76 77

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/07/2014

<E4LABEL>

<BRANCH>

91 OF 119

77 OF 97

SIZE

B

GPU

A

D

124578

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PP1V8_GPU_DP_AB

- =PP1V8_GPU_DP_CD

- =PP1V8_GPU_DP_EF

- =PP1V0_GPU_DP_AB

- =PP1V0_GPU_DP_CD

- =PP1V0_GPU_DP_EF

Signal aliases required by this page:

(NONE)

D

BOM options provided by this page:

(NONE)

D

U8400

VENUS-XT

FCBGA

AN24

NC

AP24

NC

AP25

NC
NC
NC
NC

NC
NC
NC
NC
NC

PP1V8_GPUIFPX

71 76 78 80 84

1

C9200

10UF
20%

6.3V

C

PLACE_NEAR=U8400.AM34:5.08MM

R9210

PP1V8_GPUIFPX

71 76 78 80 84

B

8.45K

1%

1/20W

MF

201

PLACE_NEAR=U8400.AM34:5.08MM

PLACE_NEAR=U8400.AD31:5.08MM

R9212

8.45K

1%

1/20W

MF

201

PLACE_NEAR=U8400.AD31:5.08MM

GPU_PS_0

21

1

R9211

2K

1%
1/20W
MF
201

2

GPU_PS_1

21

1

R9213

2K

1%
1/20W
MF
201

2

1

C9210

0.082UF

10%
16V

2

CERM-X7R
402

PLACE_NEAR=U8400.AM34:5.08MM

NOSTUFF

1

C9211

0.68UF

5%

6.3V

2

X6S
0402

PLACE_NEAR=U8400.AD31:5.08MM

2

CERM-X6S
0402

1

C9201

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.AF34:2.54MM

PLACE_NEAR=U8400.AM37:2.54MM

PLACE_NEAR=U8400.AW28:2.54MM

R9200

21

1%

1/20W

MF

201

150

PLACE_NEAR=U8400.AW18:2.54MM

R9201

21

1/20W

1%
MF

201

150

PLACE_NEAR=U8400.AM39:2.54MM

R9202

21

1/20W

1%

201

MF

150

NC

1

C9202

0.1UF

10%

6.3V

2

X7R
0201

GPU_DP_AB_CALR

GPU_DP_CD_CALR

GPU_DP_EF_CALR

NC
NC
NC
NC
NC
NC
NC
NC
NC

AP26
AU28
AV29

AP20
AP21
AP22
AP23
AU18
AV19

AH34
AJ34
AF34
AG34
AM37
AL38
AM32

AW28

AW18

AM39

AM34

AD31

AG31

AD33

AC32
AF32
AD30

AC31
AA29
AG21
AD32

U13
V13

DP_VDDR

DP_VDDR

DP_VDDR

DPAB_CALR

DPCD_CALR

DPEF_CALR

PS_0

PS_1

PS_2

PS_3

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

(6 OF 9)

OMIT_TABLE

DP_VDDC

NC_DP_VDDC

DP_VSSR

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

AP13
AT13
AP14
AP15

AF39
AH39
AK39
AL34
AM35
AN17
AN19
AN27
AN29
AN34
AN38
AP16
AP17
AP18
AP19
AP27
AP28
AP29
AP30
AP39
AR18
AR28
AR39
AU37
AV17
AV27
AW14
AW16
AW20
AW22
AW24
AW26
AW30
AW32
AN32

1

C9203

2

NC
NC
NC
NC

CONFIG STRAPS - MLPS

NOSTUFF

PLACE_NEAR=U8400.AG31:5.08MM

R9214

4.53K

1%

1/20W

MF

201

A

NOSTUFF

R9216

4.53K

1%

1/20W

MF

201

GPU_PS_2

21

1

R9215

4.75K

1%
1/20W
MF
201

2

PLACE_NEAR=U8400.AG31:5.08MM

PLACE_NEAR=U8400.AD33:5.08MM

GPU_PS_3

21

1

R9217

4.75K

1%
1/20W
MF
201

2

PLACE_NEAR=U8400.AD33:5.08MM

1

C9212

0.68UF

5%

6.3V

2

X6S
0402

PLACE_NEAR=U8400.AG31:5.08MM

1

C9213

0.68UF

5%

6.3V

2

X6S
0402

PLACE_NEAR=U8400.AD33:5.08MM

-------------------------

PCIe Gen3 Enabled, Full-Swing, TX De-Emp Enabled
VBIOS Disabled, Boot from EFI
VGA Enabled
All Ports Audio-Capable Display Output
256MB FB Aperture Size
EFI BOOT (NO ROM)

PS_0: R9120=8.45K,R9211=2K,C9210=0.082uF
PS_1: R9122=8.45K,R9213=2K,C9211NOSTUFF
PS_2: R9214 NOSTUFF,R9215=4.75K,C9213=0.68uF

PS_2: R9216 NOSTUFF,R9217=4.75K,C9213=0.68uF

10UF
20%

6.3V
CERM-X6S
0402

PP0V95_S0GPU

1

C9204

1.0UF

20%
4V

2

X6S
0201

PLACE_NEAR=U8400.AM33:2.54MM

70 71 73 84

1

C9205

0.1UF

10%

6.3V

2

X7R
0201

PLACE_NEAR=U8400.AP32:2.54MM

GPIO_28 pull low at power up

PS_0

-----------------------------

EFI BOOT (NO ROM) 8.45K 2K 0.082
ROM BOOT 3.24K 5.62K 0.082

PS_1

-----------------------------

EFI BOOT (NO ROM) 8.45K 2K NC
ROM BOOT 8.45K 2K NC

PS_2

-----------------------------

EFI BOOT (NO ROM) NC 4.75K 0.68
ROM BOOT 4.53K 4.99K 0.68

PS_3

-----------------------------

EFI BOOT (NO ROM) NC 4.75K 0.68
ROM BOOT NC 4.75K 0.68

PU(ohm) PD(OHM) C(uF)

PU(ohm) PD(OHM) C(uF)

PU(ohm) PD(OHM) C(uF)

PU(ohm) PD(OHM) C(uF)

AB39

E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39

GND

N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

A39

NC

AW1

AW39

VSS_MECH

NC
NC

U8400

VENUS-XT

FCBGA

(8 OF 9)

OMIT_TABLE

6 3

GND

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18

AF21

AG17

AG2
AG20
AG22

AG6

AG9
AH21
AJ10
AJ11

AJ2
AJ28

AJ6
AK11
AK31

AK7
AL11
AL14
AL17

AL2
AL20
AL23
AL26
AL32

AL6

AL8
AM11
AM31

AM9
AN11

AN2
AN30

AN6

AN8
AP11

AP7

AP9

AR5

B11

B13

B15

B17

B19

B21

B23

B25

B27

B29

B31

B33

B7
B9

C1
C39
E35

E5
F11
F13
F15
F17
F19
F21
F23
F25
F27
F29

SYNC_MASTER=MARY_X425G

PAGE TITLE

U8400

VENUS-XT

FCBGA

(9 OF 9)

OMIT_TABLE

GND GND

PX_EN

Venus DP PWR/GNDs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

AL21

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

NC

SYNC_DATE=09/22/2014

<E4LABEL>

<BRANCH>

92 OF 119

78 OF 97

SIZE

C

B

GPU

A

D

8 7 6 5 4 3

12

D

(GND_GFXIMVP_AGND)

R9340

147K

21

1%

1/20W

MF

201

R9318

30.1K

21

1%

1/20W

MF

201

C

C9316

560PF

10%
50V

X7R-CERM

0201

GFXIMVP_COMP_R

R9313

249K

1/20W

201

R9315

3.09K

1/20W

201

NO_XNET_CONNECTION=TRUE

NOSTUFF

1

R9317

49.9

1%
1/20W
MF
201

B

A

2

GFXIMVP_FB_GND_R

NOSTUFF

1

C9341

5600PF

10%
10V

2

CERM
201

GPU_VCORE_VID0

76 77

IN

79

76 77
79

76 77
79

76 77 79

76 77
79

76 77 79

Default Vcore set to 0.85V.

0.85V is set by setting VID0-VID5
as 001011

GPU_VCORE_VID1

IN

GPU_VCORE_VID2

IN

GPU_VCORE_VID3

IN

GPU_VCORE_VID4

IN

GPU_VCORE_VID5

IN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

1

C9317

100PF

5%
25V

2

2

C0G
0201

1

1%
MF

2

1

R9316

301

1%
1/20W
MF
201

2

1

GFXIMVP_FB_SNS_R

NO_XNET_CONNECTION=TRUE

1

1%
MF

C9340

470PF

10%
16V

2

2

X5R-X7R-CERM
0201

71 85 96

IN

71 96

IN

NOSTUFF

C9318

22PF

NP0-C0G-CERM

0201

VSNS_GPU_VDDC_P

VSNS_GPU_VDDC_N

1

5%

50V

2

NO_XNET_CONNECTION=TRUE

18 19 36 49 58 59 62 63 66 67
73 80 84 85 86

1

R9314

5.11K

1%
1/20W
MF
201

2

PLACE_NEAR=U9300.37:5mm

XW9315

2 1

SM

XW9314

2 1

SM

C9315

R9387

R9388

2.2K

1/20W

PP5V_S0

1

C9319

1000PF

2

1000PF

X7R-1

0201

NOSTUFF

2.2K

1/20W

201

1

5%
MF

201

2

10%
16V
X7R-1
0201

1

R9319

10K

5%
1/20W
MF
201

2

1

10%
16V

2

1

5%
MF

2

R9385

R9301

1/20W

GFXIMVP_RBIAS
GFXIMVP_NTC
GPUVCORE_PGOOD

68 82

OUT

GFXIMVP_VR_TT_L

79

GPU_VCORE_VID0

76 77 79

GPU_VCORE_VID1

76 77 79

GPU_VCORE_VID2

76 77 79

GPU_VCORE_VID3

76 77 79

GPU_VCORE_VID4

76 77 79

GPU_VCORE_VID5

76 77 79

GFXIMVP6_VID6

GFXIMVP_PSI_L

77 79

GFXIMVP_DPSLP_EN

79

GPUVCORE_EN

68

IN

GFXIMVP_VW
GFXIMVP_COMP
GFXIMVP_FB2

GFXIMVP_FB

GPUVCORE_SENSE_P

96

CKPLUS_WAIVE=PdifPr_badTerm

GPUVCORE_SENSE_N

96

GFXIMVP6_IMON

47

OUT

NO_XNET_CONNECTION=TRUE

1

C9314

1000PF

10%
16V

2

X7R-1
0201

NO_XNET_CONNECTION=TRUE

NOSTUFF

1

R9384

2.2K

5%

1/20W

MF

201

2

NOSTUFF

1

R9383

2.2K

1/20W

201

5%
MF

2

2.2K

1/20W

PLACE_NEAR=U9300.25:1mm

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

1

21

PP5V_S0_GFXIMVP_VDD

5%

PLACE_NEAR=U9300.16:1mm

MF

201

NO_XNET_CONNECTION=TRUE

1

R9312

10K

1%

1/20W

MF

201

2

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

1

R9382

2.2K

5%

1/20W

MF

201

2

1

R9396

5%
MF

201

2

PPVIN_S5_HS_GPU_ISNS

47 73 79 80 84

C9302

1UF

10%
25V

X6S-CERM

0402

1UF

X6S-CERM

0402

1

5%
MF

201

2

1

10%
25V

2

3

RBIAS

5

NTC

1

PGOOD

4

VR_TT*

40

CLK_EN*

31

VID0

32

VID1

33

VID2

34

VID3

35

VID4

36

VID5

37

VID6

2

PSI*

39

DPRSLPVR

38

VR_ON

6

VW

7

COMP

9

FB2

8

FB

12

VSEN

13

RTN

18

IMON

NOSTUFF

R9392

2.2K

1/20W

R9391

C9301

1

C9313

0.1UF

10%

6.3V

2

X6S
0201

GND_GFXIMVP_AGND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

NOSTUFF

R9395

2.2K

1/20W

1

2.2K

5%

1/20W

MF

201

2

6 3

1

2

16

25

VCCP

U9300

ISL62882C

TQFN

353S3679

THRM

PAD

41

PLACE_NEAR=U9300.41:1mm

1

2.2K

5%

1/20W

MF

201

2

1

R9379

5%
MF

201

2

1

R9300

10

5%
1/20W
MF
201

MIN_LINE_WIDTH=0.6MM

2

MIN_NECK_WIDTH=0.2MM
VOLTAGE=12.8V

PPVIN_S0_GFXIMVP_R

PLACE_NEAR=U9300.17:1mm

1

C9300

0.22UF

10%
25V

2

X7R
0402

17

BOOT2

UGATE2

PHASE2

LGATE2

VSSP2

ISEN2

BOOT1

UGATE1

PHASE1

LGATE1A

LGATE1B

VSSP1

ISEN1

ISUM+

ISUM-

SM

R9378

2.2K

1/20W

201

5%
MF

79

2.2K

30

29

28

26

27

10

19

20

21

23

24

22

11

15

1/20W

1

2

Line Width & DIDT
on all DIDT nets

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE

GFXIMVP_BOOT2

GATE_NODE=TRUE

GFXIMVP_UGATE2

SWITCH_NODE=TRUE

GFXIMVP_PHASE2

GATE_NODE=TRUE

GFXIMVP_LGATE2
GFXIMVP_VSSP2

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

GFXIMVP_ISEN2
GFXIMVP_BOOT1

GATE_NODE=TRUE

GFXIMVP_UGATE1

SWITCH_NODE=TRUE

GFXIMVP_PHASE1

GATE_NODE=TRUE

GFXIMVP_LGATE1

NC

GFXIMVP_VSSP1
GFXIMVP_ISEN1
GFXIMVP_ISUMP

GFXIMVP_ISUMN_R

14

1

5%
MF

201

2

GPU_VCORE_VID0
GPU_VCORE_VID1
GPU_VCORE_VID2
GPU_VCORE_VID3
GPU_VCORE_VID4
GPU_VCORE_VID5

VINVDD

XW9300

2 1

NOSTUFF

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

NOSTUFF

0.1UF

6.3V
0201

10%
X6S

1

2

76 77 79

76 77 79

76 77 79

76 77 79

76 77 79

76 77 79

C9312

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE

GFXIMVP_BOOT2_R

1

R9330

0

5%
1/10W
MF-LF
603

2

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE

GFXIMVP_BOOT1_R

R9310

1.54K

1%

1/20W

MF

201

GFXIMVP_ISUMP_C

R9375 = GFXIMVP_VR_TT_L GPIO13

R9377 = DPSLP Control GPIO 30

76 77

IN

GFXIMVP_DPSLP_EN_R

76 77

IN

1

C9330

0.22UF

10%
16V

2

CERM

402

1

R9360

0

5%
1/10W
MF-LF
603

2

21

C9365

0.22UF

NOSTUFF

R9311

1.15K

1/20W

PLACE_NEAR=Q9331.3:1mm

1%
MF

201

XW9330

SM

2 1

1

10%
16V

2

CERM

402

PLACE_NEAR=Q9361.3:1mm

1

2

C9310

5600PF

10%
10V
CERM
201

21

XW9331

SM

2 1

GFXIMVP_ISUMN

1

C9311

0.1UF

10%

6.3V

2

X6S
0201

Stuff option for GPIO control

R9375

GFXIMVP_VR_ICCMAX_WARN_L

0

5%

1/20W

MF

201

NOSTUFF

R9377

0

5%

1/20W

MF

201

7

D

G

2

S

3

1

D

G

4

S

653

D

G

1

S

NCNC

1

D

G

4

S

21

GFXIMVP_VR_TT_L

21

GFXIMVP_DPSLP_EN

CRITICAL

1

C9325

33UF

20%
16V

2

POLY-TANT
CASED12-SM

8

Q9330

IRF6802SDTRPBF

DIRECTFET-SA

CRITICAL

L9330

0.2UH-20%-28A-0.0011OHM

NCNC

PILA63T-SM

782

CRITICAL

Q9331

649135PBF

DIRECTFET_S3C

21

NO_XNET_CONNECTION

376S1011

PPVIN_S5_HS_GPU_ISNS

6

5

Q9330

IRF6802SDTRPBF

DIRECTFET-SA

4

CRITICAL

L9360

0.2UH-20%-28A-0.0011OHM

PILA63T-SM

782

CRITICAL

Q9361

649135PBF

DIRECTFET_S3C

376S1011

653

79

79

77 79

79

79

79

CRITICAL

C9320

68UF

POLY-TANT

CASE-D2E-SM

C9328

2.2UF

X6S-CERM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V

PPVCORE_S0_GFX_PH2

GFXIMVP_ISNS2_P

96

TRUE

1

R9331

10K

1%

1/20W

MF

201

2

TRUE

1

R9332

10K

1%

1/20W

MF

201

2

47 73
79 80 84

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V

21

PPVCORE_S0_GFX_PH1

GFXIMVP_ISNS1_P

96

NO_XNET_CONNECTION

GFXIMVP_VR_TT_L
GFXIMVP_PSI_L
GFXIMVP_DPSLP_EN

R9361

R9362

PP3V3_S0GPU

47 66 68 71 72 76 77 79 80 84

TRUE

TRUE

10K

1/20W

10K

1/20W

1%
MF

201

1%
MF

201

CRITICAL

1

C9321

2

1

2

R9398

0.00075

2 1
4 3

1K

1%

1/20W

MF

201

C9331

0.22UF

20%

6.3V

X6S-CERM

0201

TRUE

1K

1/20W

201

C9366

0.22UF

X6S-CERM

1

R9370

10K

1%
1/20W
MF
201

2

68UF

POLY-TANT

CASE-D2E-SM

C9327

2.2UF

X6S-CERM

1%
1W
MF

0612-1

79 96

1

2

21

R9399

0.00075

0612-1

1

1%
MF

2

21

20%

6.3V
0201

1%
1W
MF

20%
16V

20%
25V

0402

TRUE

R9333

GFXIMVP_ISNS1_N

1

R9363

2

1

2

GFXIMVP_ISNS2_N

CRITICAL

1

C9322

2

1

2

68UF

POLY-TANT

CASE-D2E-SM

C9323

2.2UF

X6S-CERM

0402

20%
16V

20%
25V

~30.5A max per phase

GFXIMVP_ISNS2_N

TRUE

1

R9334

1.00

1%
1/20W
MF-LF
0201

2

GFXIMVP_ISUMN
GFXIMVP_ISUMP

79 96

21
43

GFXIMVP_ISNS1_N

79 96

TRUE

1

R9364

1.00

1%
1/20W
MF-LF
0201

2

GFXIMVP_ISUMN
GFXIMVP_ISUMP

79 96

NOSTUFF

1

R9371

10K

5%
1/20W
MF
201

2

NOSTUFF

1

R9372

100K

5%
1/20W
MF
201

2

1

R9374

100K

2

1

R9373

100K

2

0402

CRITICAL

1

20%
16V

2

CASE-D2E-SM

1

C9324

20%
25V

2

C9326

68UF

POLY-TANT

2.2UF

20%
25V

X6S-CERM

0402

1

20%
16V

2

1

2

CRITICAL

1

C9329

33UF

20%
16V

2

POLY-TANT
CASED12-SM

CRITICAL

1

C9332

12PF

5%
NP0-C0G

2

0201
25V

PPVCORE_GPU

CRITICAL

1

C9361

270UF

20%
2V

2

TANT
CASE-B2-SM

79

79

79

79

VIMON = Imon* R9312
Imon = 3* Idroop. Idroop = 2*Rsns*Io/(N*Ri)

VIMON = 1.46104uA/A * Io * 14.6104mV/A*Io
1A will generate 14.6104mV and 891.23mV for 61A

5%
1/20W
MF
201

Do not config
PSI_L = HIGH & DPSLP_EN = HIGH

SYNC_MASTER=ADITYA_X425G

PAGE TITLE

CRITICAL

1

C9362

270UF

20%
2V

2

TANT
CASE-B2-SM

CRITICAL

1

C9363

270UF

20%
2V

2

TANT
CASE-B2-SM

GFX IMVP VCore Regulator

Apple Inc.

5%
1/20W
MF
201

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R

CRITICAL

1

C9333

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

1

C9364

330UF-6MOHM

20%

2.0V

3 2

POLY-TANT
D15T-ECGLT-COMBO

SYNC_DATE=09/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

93 OF 119

SHEET

79 OF 97

124578

47 71 84

SIZE

D

C

B

GPU

A

D

8 7 6 5 4 3

12

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 84 85 86

1

1

2

19

VCC

PVCC

U9450

UTQFN

CRITICAL

GND

PGND

2

3

R9406

2.2

5%
1/20W

VOLTAGE=5V

MF

MIN_NECK_WIDTH=0.2 MM

201

MIN_LINE_WIDTH=0.4 MM

2

PP5V_VDDCI_PVCC

1

2

20

MIN_NECK_WIDTH=0.2 mm

REG_BOOT_GPU_VDDCI

BOOT

17

UGATE

16

PHASE

1

LGATE

R9405

VSNS_GPU_VDDI_P

71 85 96

IN

VSNS_GPU_VDDI_N

71 96

IN

2

2

D

GPU_VDDCI_SENSE_XW_N

96

XW9470

PLACE_NEAR=U8400.AH28:5mm

NO_XNET_CONNECTION=TRUE

<Ra>

R9470

2.8K

0.1%

1/20W

0201

XW9471

SM

SM

PLACE_NEAR=U8400.AG28:5mm

1

1

GPU_VDDCI_SENSE_XW_P

NO_XNET_CONNECTION=TRUE

<Ra>

1

1

R9471

2.8K

0.1%
1/20W
MF

MF

0201

2

2

96

68

IN

PVDDCI_GPU_EN

VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM

PP5V_VDDCI_VCC

C9403

CER-X6S

AGND_GPU_VDDCI

80

1UF

10%
16V

0402

1

2

REG_GPU_VDDCI_FB

REG_GPU_VDDCI_SREF

1

C9490

0.033UF

10%
16V
X5R
402

<Rb><Rb>

1

C9470

10PF

0201

50V
C0G

R9472

4.02K

0.1%

1/20W

0201

1

MF

2

2

1

5%

2

R9473

4.02K

0.1%
1/20W
MF
0201

1

C9485

10PF

5%
50V

2

C0G
0201

C

1

2

2

1

2

REG_GPU_VDDCI_SET1_R

1

2

Vout = 0.5 * (1 + Ra / Rb)

PP3V3_S0GPU

47 66 68 71 72 76 77 79 84

R9484

0

21

5%

1/20W

MF

0201

NOSTUFF

R9485

GFX_VDDCI_ALTV

76 77

IN

5%

1/20W

MF

0201

0

21

VID1 VID0 GPU VDDCI
1 1 0.85V

B

1 0 0.9V

--> DEFAULT

REG_GPU_VDDCI_VO

R9474

17.4K

80

0.1%
1/20W
MF
0201

R9475

34.8K

0.1%
1/20W
MF
0201-1

R9478

249K

0.1%
1/20W
MF
0201

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

1

R9483

10K

5%
1/20W
MF
201

2

GFX_VDDCI_ALTV0

GFX_VDDCI_ALTV1

1

R9481

10K

5%
1/20W
MF
201

2

REG_GPU_VDDCI_OCSET

PVDDCI_PGOOD

68 82

OUT

REG_GPU_VDDCI_RTN

REG_GPU_VDDCI_FSEL

REG_GPU_VDDCI_SET0

REG_GPU_VDDCI_SET1

NOSTUFF

1

R9476

0

5%
1/20W
MF
0201

R9477

2

0

21

5%

1/20W

MF

0201

AGND_GPU_VDDCI

80

PLACE_NEAR=U9450.3:1mm

10

5%

1/20W

MF

201

ISL95870AH

15 18

EN

10

FB

7

SREF

12

VO

11

OCSET

14

PGOOD

4

RTN

13

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

XW9473

SM

2 1

GPU VDDCI REGULATOR

REG_BOOT_GPU_VDDCI_RC

1

C9404

2.2UF

10%
10V
X6S-CERM
0402

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

REG_UGATE_VDDCI_R

DIDT=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm

REG_PHASE_GPU_VDDCI

REG_LGATE_GPU_VDDCI

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE
DIDT=TRUE

R9407

GATE_NODE=TRUE

2.2

5%
1/16W
MF-LF

402

2

R9408

MIN_LINE_WIDTH=0.6 mm

REG_UGATE_VDDCI

1

21

5%
1/16W
MF-LF

402

1

C9405

0.1UF

10%
16V

2

X7R-CERM
0402

DIDT=TRUE

GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

PPVIN_S5_HS_GPU_ISNS

47 73 79 80 84

APN376S1005

CRITICAL

Q9410

CSD58873Q3D

Q3D

3

TG

4

TGR

5

BG

CRITICAL

CRITICAL

C9402

68UF

20%
16V

POLY-TANT

CASE-D2E-SM

EMC

PLACE_NEAR=Q9410.1:4mm

C9409

2.2UF

X6S-CERM

0402

1

VIN

6
7

VSW

VR_PHASE_GPU_VDDCI

8

PGND

9

1

2

REG_SNUBBER_GPU_VDDCI

1

2

EMC

PLACE_NEAR=Q9410.1:4mm

1

C9410

20%
25V

2.2UF

2

X6S-CERM

APN152S1822

1.0UH-20%-15A-0.0066OHM

NOSTUFF

C9411

0.001UF

10%
50V
X7R-CERM
0402

NOSTUFF

R9409

2.2

5%
1/10W
MF-LF
603

REG_GPU_VDDCI_OCSET

80

REG_GPU_VDDCI_VO

80

1

2

20%
25V

0402

CRITICAL

L9410

PIME063T-SM

1

2

1

2

R9410

C9406

12PF

5%
NP0-C0G
0201
25V

C9408

1000PF

21

VRVDDCI_R

3.92K

1%

1/20W

MF

201

CERM
0402

25V

1

5%

2

1

2

CRITICAL

1

C9407

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

R9400

0.003

1%
1W

CYN

0612

2 1
4 3

REG_GPU_VDDCI_OCSET_R

PLACE_NEAR=R9410.2:3mm

C9412

0.0022UF

21

10%
50V

CERM

402

Note:

Regulator requires
a minimum load to
prevent noise in the
audio frequencies

1

C9413

1000PF

5%

25V

2

CERM
0402

CRITICAL

1

C9414

270UF

20%
2V

2

TANT
CASE-B2-SM

XW9480

2 1

REG_GPU_VDDCI_VO_R

XW9481

2 1

1

R9411

3.92K

1%
1/20W
MF
201

2

CRITICAL

SM

SM

1

R9412

2

1

C9415

270UF

20%
2V

2

TANT
CASE-B2-SM

200

5%
1/16W
MF-LF
402

VOUT = 0.9V
7A MAX OUTPUT
F = 500 KHZ

PPVDDCI_S0_ISENSE

CRITICAL

1

C9417

10UF

20%
10V

2

X6S-CERM
0603

CRITICAL

1

C9416

270UF

20%
2V

2

TANT
CASE-B2-SM

VDDCIS0_CS_P

VDDCIS0_CS_N

1

2

CRITICAL

1

C9419

270UF

20%
2V

2

TANT
CASE-B2-SM

CRITICAL

C9418

10UF

20%
10V
X6S-CERM
0603

CRITICAL

OUT

OUT

71 84

1

C9431

270UF

20%
2V

2

TANT
CASE-B2-SM

47 96

47 96

D

C

B

1.8V S0 GPU Regulator

12

PPVIN_S5_HS_GPU_ISNS

47 73 79 80 84

CRITICAL

1

C9432

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

1

C9433

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

CRITICAL

1

C9420

33UF

20%
16V

2

POLY-TANT
CASED12-SM

CRITICAL

1

C9421

2.2UF

20%
25V

2

X6S-CERM
0402

A

CRITICAL

1

C9422

2.2UF

20%
25V

2

X6S-CERM
0402

R9420

10

5%

1/20W

MF

201

C9423

0.1UF

0402

21

PPVIN_S0GPU_1V8_RC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=8.4V

68

1

10%
25V

2

X6S

AGND_PVDDR

P1V8_S0GPU_EN

IN

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

10

8

13

7

11

PVIN

U9400

TPS62130ARGT

AVIN

QFN

CRITICAL

DEF

353S4283

EN

FSW

PGND

PGND

16

15

XW9420

SM

AGND

6

21

PVIN

THRM

17

SS/TR

PAD

VOS

SW
SW
SW

FB

PG

REG_PHASE_PVDDR

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE
DIDT=TRUE

1
2
3

14

REG_VOS_PVDDR

5

REG_FB_PVDDR

4

P1V8GPU_PGOOD

9

REG_SSTR_PVDDR

1

C9424

4700PF

10%
10V

2

X7R
201

Vout = 0.8V * (Ra + Rb) / Rb

6 3

APN152S00137

CRITICAL

OUT

L9400

PIFE32251B-SM

68 82

R9421

1/20W

R9422

105K

0.1%

1/20W

0201-1

<Ra>

R9423

82.5K

0.1%

1/20W

0201-1

<Rb>

201

21

1

10

5%
MF

2

1

MF

2

1

MF

2

1.5UH-20%-2.61A-0.068OHM

CRITICAL

1

C9425

47UF

20%

6.3V

2

POLY-TANT
0805

CRITICAL

1

C9426

47UF

20%

6.3V

2

POLY-TANT
0805

PP1V8_GPUIFPX

CRITICAL

1

C9427

47UF

20%

6.3V

2

POLY-TANT
0805

CRITICAL

1

C9428

47UF

20%

6.3V

2

POLY-TANT
0805

Output voltage:

71 76 78
84

Max peak current:
Switching freq:

CRITICAL

1

C9429

47UF

20%

6.3V

2

POLY-TANT
0805

1.818 V

1.5A
1250 kHz

CRITICAL

1

C9430

47UF

20%

6.3V

2

POLY-TANT
0805

SYNC_MASTER=ADITYA_X425G

PAGE TITLE

VREG GPU VDDCI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/16/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

94 OF 119

SHEET

80 OF 97

124578

SIZE

GPU

A

D

8 7 6 5 4 3

12

D

Wire-to-Board (Micro-coax) Connector

NO_XNET_CONNECTION=TRUE

BP9505

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

X5R-CERM

X5R-CERM

BP9506

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

BP9501

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

BP9502

BEAD-PROBE

SM

1

TP

13 90

13 90

SM

1

TP

13 86 90

13 86 90

IN

IN

OUT
OUT

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_EXTB_D2R_P
USB3_EXTB_D2R_N

C9501

C9502

0.1UF

0.1UF

21
10%

21
10%

GND_VOID=TRUE

16V

GND_VOID=TRUE
16V

C

NO_XNET_CONNECTION=TRUE

BP9503

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

BP9504

BEAD-PROBE

Board-to-Board (Flex) Connector

CRITICAL

J9510

DF40HC-3.0-40DS-0.4V-51

PP5V_S4 PP5V_S4

37 38 51 61 66 67 69 81 84 86 37 38 51 61 66 67 69 81 84 86

B

PP3V3_S3

13 20 21 43 45 46 66 81 82 84
86

PP1V5_S0

11 12 13 15 17 19 52 64 67 84
86

RIO_SDCONN_STATE_CHANGE_L

20 86

OUT

SD_PWR_EN

13 18 86

IN

USB_EXTB_OC_L

18 86

OUT

HDMI_HPD

20 82 86

OUT

PP3V3_S3

13 20 21 43 45 46 66 81 82 84
86

C9510

0.1uF

CERM

1

20%
10V

2

402

F-ST-SM
2
4
6 5
8 7

10
12 11
14 13
16 15
18 17
20
22 21
24 23
26 25
28 27
30
32 31
34 33
36 35
38 37
40

516S00052

1
3

9

SMBUS_PCH_DATA

19

SMBUS_PCH_CLK
PP3V3_S4

PP3V3_S3

29

39

HDMI_EG_DDC_DATA
HDMI_EG_DDC_CLK
PM_SLP_S4_L
PM_SLP_S3_BUF_L

1

C9511

0.1uF

2

20%
10V
CERM
402

1

C9512

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J9510.1:3mm

13 18 43 85 86 91

BI

13 18 43

IN

85 86 91

20 33 38 41 42 45 46 65
66 67 84 85 86

76

BI

76

IN

12 21 33 37 40 67 86

IN

51 66 67 82 86

IN

C9512&C9513 FOR DESENSE IMPROVEMENT
LOCATION DEPENDS ON DESENSE TEAM

13 20 21 43 45 46 66 81 82 84

12PF

5%
NP0-C0G
0201
25V

PLACE_NEAR=J9510.21:3mm

86

1

C9513

2

0201

0201

SM

1

TP

SM

1

TP

SM

1

TP

SM

1

TP

13 86 90

BI

13 86 90

BI

76 86 97

IN

76 86 97

IN

76 86 97

IN

76 86 97

IN

76 86 97

IN

76 86 97

IN

76 86 97

IN

76 86 97

IN

13 20 86 91

OUT

13 20 86 91

OUT

13 20 86 91

IN

13 20 86 91

IN

USB_EXTB_P
USB_EXTB_N

USB3_EXTB_R2D_P

86 90

USB3_EXTB_R2D_N

86 90

HDMI_EG_DATA_P<0>
HDMI_EG_DATA_N<0>

HDMI_EG_DATA_P<1>
HDMI_EG_DATA_N<1>

HDMI_EG_DATA_P<2>
HDMI_EG_DATA_N<2>

HDMI_EG_CLK_P
HDMI_EG_CLK_N

USB3_SD_D2R_P
USB3_SD_D2R_N

USB3_SD_R2D_C_P
USB3_SD_R2D_C_N

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

CRITICAL

J9500

20525-130E-01

F-RT-SM

31

1

2

3
4

5

6
7

8

9
10

11
12

13

14
15

16

17
18

19

20
21

22
23

24

25
26

27

28
29

30

33

34
35

36

37
38

39

40
41

32

518S0829

D

C

B

A

SYNC_MASTER=CLEAN_MAXWELL

PAGE TITLE

RIO Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=07/01/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

95 OF 119

SHEET

81 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52

DPMUX_UC_MD2

3

1

G S

1

C9603

0.1UF

20%
10V

2

X7R-CERM

0402

B1

M12

VCC

AVCC

R4F2113NLG

RES*

XTAL
EXTAL

VSS

D2

R9610
R9611
R9612
R9613
R9614
R9615
R9616
R9617
R9618
R9619
R9642

R9655
R9656

R9640
R9641

PP3V3_S0

1

R9670

4.7K

5%
1/20W
MF
201

2

GMUX_SLP_S3_BUF_L

NOSTUFF

R9671

470K

5%
1/20W
MF
201

28 32

D

2

1

20%
10V

2

H10

M1

VCC

VCC

U9600

TLP-145V

SYM 3 OF 3

OMIT_TABLE

VSS

VSS

VSS

C5

L3

F10

MAKE_BASE=TRUE

IN

E1

B11

VCL

VSS

100K

100K

100K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

L11

AVREF

L9

10K

0

Q9690

DMN32D2LFB4

TP_DPMUX_UC_P10
TP_DPMUX_UC_P11
TP_DPMUX_UC_P12
TP_DPMUX_UC_P13

D

68 82

OUT

68 82

OUT

68 82

OUT

68 82

OUT

68 82

OUT

11 82 85

OUT

70 82 85

OUT

13 40 91

BI

13 40 91

BI

13 40 91

BI

13 40 91

BI

13 40 91

IN

20

IN

69 85 86

IN

C

82 85

OUT

82 85

IN

TP_DPMUX_UC_P14
TP_DPMUX_UC_P15
TP_DPMUX_UC_P16
TP_DPMUX_UC_P17

EG_RAIL1_EN
P0V95R1V8GPU_R_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_RAIL5_EN
PEG_CLKREQ_L
EG_RESET_L
TP_FB_CLAMP

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
DPMUX_LRESET_L

20 82

LPC_CLK33M_DPMUX_UC

TP_DPMUX_UC_P37

TP_DPMUX_UC_P40
TP_DPMUX_UC_P41
TP_DPMUX_UC_P42
LCD_FSS
LCD_MUX_SEL

82

TP_DPMUX_UC_P45
TP_DPMUX_UC_P46
TP_DPMUX_UC_P47

DPMUX_UC_TX
DPMUX_UC_RX
TP_DPMUX_UC_P52

B12

P10/WUE0*

A13

P11/WUE1*

A12

P12/WUE2*

B13

P13/WUE3*

D11

P14/WUE4*

C13

P15/WUE5*

C12

P16/WUE6*

D10

P17/WUE7*

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30/LAD0

D9

P31/LAD1

C8

P32/LAD2

B7

P33/LAD3

A8

P34/LFRAM*

D8

P35/LRESET*

D7

P36/LCLK

D6

P37/SERIRQ

D4

P40/TMI0/TCMCYI0

A5

P41/TMO0/TCMCKI0/TCMMCI0

B4

P42/TCMCYI1

A1

P43/TMI1/TCMCKI1/TCMMCI1

C2

P44/TMO1/PWMU2B/TCMCYI2

B2

P45/PWMU3B/TCMCKI2/TCMMCI2

C1

P46/PWMU4B

C3

P47/PWMU5B

G2

P50/FTXD

F3

P51/FRXD

E4

P52/SCL0

CONNECT I2C TO LCD BKLT IC

N3

PA0/KIN8*/SDA1

N1

PA1/KIN9*/SCL1

M3

PA2/KIN10*/PS2AC

M2

PA3/KIN11*/PS2AD

NC

N2

PA4/KIN12*/PS2BC

NC

L1

PA5/KIN13*/PS2BD

NC

K3

PA6/KIN14*/PS2CC

L2

PA7/KIN15*/PS2CD

B8

PB0/LSMI*

C9

PB1/LSCI

B9

PB2/RI*/PWMU0B

A10

PB3/DCD*/PWMU1B

C10

PB4/DSR*/FSIDO

B10

PB5/DTR*/FSIDI

C11

PB6/CTS*/FSICK

A11

PB7/RTS*/FSISS

G11

PC0/TIOCA0/WUE8*

G13

PC1/TIOCB0/WUE9*

F12

PC2/TIOCC0/TCLKA/WUE10*

H13

PC3/TIOCD0/TCLKB/WUE11*

G10

PC4/TIOCA1/WUE12*

G12

PC5/TIOCB1/TCLKC/WUE13*

H11

PC6/TIOCA2/WUE14*

J13

PC7/TIOCB2/TCLKD/WUE15*

M10

PD0/AN8

N9

PD1/AN9

K10

PD2/AN10

L8

PD3/AN11

M9

PD4/SSO

N8

PD5/SSI

K9

PD6/SSCK

L7

PD7/SCS

PP3V3_S0_DPMUX_UC_R

82

DPMUX_UC_TX

82 85

DPMUX_UC_RX

82 85

DPMUX_UC_RESET_L

82

DPMUX_UC_MD1

82

82

I2C_DPMUX_UC_SDA
I2C_DPMUX_UC_SCL
DPMUX_UC_IRQ

SMC_GFX_OVERTEMP

TP_FB_CLAMP_TOGGLE_REQ_L

TP_DPA_EG_HPD
TP_DPB_EG_HPD
DP_TBTSNK0_HPD_EG
DP_TBTSNK1_HPD_EG
SMC_GFX_SELF_THROTTLE
GPU_GFX_PWR_LEVEL_L
HDMI_EG_HPD
DP_INT_EG_HPD

LCD_PWR_EN
LCD_BKLT_EN
TP_DPMUX_UC_PC2
TP_DPMUX_UC_PC3
LCD_MUX_EN
TP_LCD_MUX_REQ
LCD_BKLT_PWM
DP_DDC_MUX_CROSSBAR_L

TP_DPA_IG_HPD
TP_DPB_IG_HPD
DP_TBTSNK0_HPD_IG
DP_TBTSNK1_HPD_IG
TP_DP_EXTA_CA_DET_IG
TP_DP_EXTB_CA_DET_IG
TP_HDMI_IG_HPD
DP_INT_IG_HPD

43

BI

43

OUT

14 85

OUT

40 42 82

OUT

76 77 82

OUT

76 77 82

OUT

40 42 82

OUT

77

B

PU OFFPAGE

OUT

76 77

OUT

76 77 82

OUT

69 82 86

OUT

63 82 86

OUT

63 82

OUT

83

OUT

12 82 85

OUT

12 82 85

OUT

20 82

OUT

A

U9600

R4F2113NLG

TLP-145V

SYM 1 OF 3

OMIT_TABLE

U9600

R4F2113NLG

TLP-145V

SYM 2 OF 3

OMIT_TABLE

PG0/EXIRQ8*/TMIX/SDAA
PG1/EXIRQ9*/TMIY/SCLA

PG2/EXIRQ10*/SDAB
PG3/EXIRQ11*/SCLB
PG4/EXIRQ12*/SDAC
PG5/EXIRQ13*/SCLC
PG6/EXIRQ14*/SDAD
PG7/EXIRQ15*/SCLD

J9600

1909782

M-RT-SM

7

1
2
3
4
5
6

8

P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/KIN6*

P67/IRQ7*/KIN7*

P82/CLKRUN*

P83/LPCPD*
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P86/IRQ5*/SCK1

P90/IRQ2*
P91/IRQ1*

P92/IRQ0*
P93/IRQ12*
P94/IRQ13*
P95/IRQ14*

P97/SDA0/IRQ15*

PE0/EXEXCL

PE1/ETCK
PE2/ETDI
PE3/ETDO
PE4/ETMS

PE5/ETRST*

PF0/IRQ8*/PWMU0A
PF1/IRQ9*/PWMU1A

PF2/IRQ10*/TMOY

PF3/IRQ11*/TMOX
PF4/PWMU2A/EXDSR
PF5/PWMU3A/EXDTR
PF6/PWMU4A/EXCTS
PF7/PWMU5A/EXRTS

PH0/IRQ6*

PH1/EXIRQ7*

PEVREF

DPMUX_DEBUG

DPMUX UC DEBUG HEADER

P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7

P80/PME*
P81/GA20

P96/EXCL

PECI

L13
K12
K11
J12
K13
J10
J11
H12

N10
M11
L10
N11
N12
M13
N13
L12

A7
B6
C7
D5
A6
B5
C6

J4
G3
H2
G1
H4
G4
F4
F1

K1
J3
K2
J1
K4
H3

K5
N5
M6
L5
M5
N4
L4
M4

M8
N7
K8
K7
K6
N6
M7
L6

E2
F2
A4
B3

NC
NC
NC
NC
NC
NC
NC
NC

DPMUX_UC_CLK32K
DPMUX_UC_TCK
DPMUX_UC_TDI
DPMUX_UC_TDO
DPMUX_UC_TMS
DPMUX_UC_TRST_L

EG_LCD_PWR_EN
EG_BKLT_EN

PM_ALL_GPU_PGOOD

P0V95_S0GPU_PGOOD
PVDDCI_PGOOD
GPUVCORE_PGOOD
P1V8GPU_PGOOD
P3V3_S0GPU_PGOOD

NC_I2C_DPMUX_A_SDA
NC_I2C_DPMUX_A_SCL

NC
NC
NC

DPMUX_LRESET_L
HDMI_HPD
LCD_HPD

EDP_IG_PANEL_PWR
EDP_IG_BKL_ON
DPMUX_UC_PECI
DPMUX_UC_PEVREF

DP_EXTA_MUX_EN
DP_EXTA_MUX_SEL_EG
TP_DPMUX_UC_P62
GMUX_SLP_S3_BUF_L
DP_EXTB_MUX_EN
DP_EXTB_MUX_SEL_EG
TP_DPMUX_UC_P66
TP_DPMUX_UC_P67

TP_DPMUX_UC_P80
TP_DPMUX_UC_P81
TP_DPMUX_UC_P82
TP_DPMUX_UC_P83
DPMUX_UC_TX
DPMUX_UC_RX
TP_LCD_IRQ

GPU_GFX_OVERTEMP
TP_DP_TBTPB_HPD_BUF
DP_TBTSNK0_HPD
DP_TBTSNK1_HPD
GFX_SELF_THROTTLE
SMC_GFX_PWR_LEVEL_L
TP_DPMUX_UC_P96
TBT_DDC_XBAR_EN_L

28 31

IN

83

OUT

83

OUT

82

83

OUT

83

OUT

PP3V3_S3

13 20 21 43 45 46 66 81 84 86

55 66 67 68 69 82 83 84 86

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

82 85

OUT

82 85

IN

IN

IN
IN
IN
IN

IN

82

82

82

82

82

82

IN
IN
IN
IN
IN
IN
IN
IN

BI

OUT

IN
IN
IN

IN
IN

82

82

PM_SLP_S3_BUF_L

51 66 67 81 86

55 66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52
96

TBT_A_CONFIG1_BUF TBT_B_CONFIG1_BUF

DPMUX_UC_RESET_L

82

77 82

DPMUX_LRESET_L

20 82

28

28

77 82

40 42 82

28

76 77

76 77

68

68 73

68 80

68 79

68 80

68

43

43

20 82

20 81 86

69

12 85

12 85

PP3V3_S5

12 14 15 17 18 19 21 31 32
33 61 64 66 67 84 85 86 96

C9670

0.1UF

6.3V
0201

PP3V3_S0

NOSTUFF

Q9610

DMN5L06VK-7

SOT563

VER 5

3

10%
X7R

R9600

TP_DPMUX_UC_XTAL
DPMUX_UC_EXTAL

1

2

2

1

NC NC

5

G

SD

4

DPMUX_UC_MD1

82

0

21

5%
1/16W
MF-LF

402

1

C9600

X7R-CERM

0.1UF

20%
10V

2

0402

NOSTUFF

R9602

0

21

5%
1/16W
MF-LF

402

DPMUX_UC_NMI

82

DPMUX_UC_TRST_L

82

DPMUX_UC_MD1

82

DPMUX_UC_MD2

82

DPMUX_UC_CLK32K

82

DPMUX_UC_TCK

82

DPMUX_UC_TDI

82

DPMUX_UC_TDO

82

DPMUX_UC_TMS

82

PEG_CLKREQ_L

11 82 85

SMC_GFX_PWR_LEVEL_L

40 42 82

LCD_MUX_EN

82

LCD_MUX_SEL

82

DPMUX_UC_RESET_L

82

6

VCC

U9670

74LVC1G07GF

SOT891

A

C9601

X7R-CERM

NC NC

GND

3

CA_DET ISOLATION-Will delete

R9660

100K

5%

1/20W

MF

201

DFN1006H4-3

SYM_VER_2

R9601

0

21

PP3V3_S3_DPMUX_UC_R

MIN_LINE_WIDTH=0.3MM

5%

MIN_NECK_WIDTH=0.2MM

1/16W

VOLTAGE=3.3V

MF-LF

402

PP3V3_S0_DPMUX_UC_R

82

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

1

C9602

0.1UF

0402

0.1UF

20%
10V

2

X7R-CERM

0402

D3

A3
A2

1

R9650

10K

5%

1/20W

MF

201

2

DPMUX UC PULL-UPS

Y

4

5

1

2

21

82

1

C9604

0.1UF

20%
10V

2

X7R-CERM
0402

DPMUX_UC_VCL

J2

VBAT

MDCKN

MD1
MD2

NMI

NC

AVSS

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

C9605

0.47UF

X6S-CERM

C4

D1
H1

E3

E5

NC

49 51 52 55 66 67 68

PP3V3_S0

11 12 13 14 15 17 19
20 29 34 43 44 45 46 47 48
69 82 83 84 86 96

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5% MF

21

5%

21

5% MF

NOSTUFF

21

21

5%

21

21

NOSTUFF

NOSTUFF

21

5%

21

GMUX_SLP_S3_BUF_L

1/20W

1/20W

GMUX_SLP_S3_BUF_L

PP3V3_S0

NOSTUFF

Q9610

DMN5L06VK-7

SOT563

VER 5

6

10%

6.3V
0402

DPMUX_UC_MD1
DPMUX_UC_MD2

DPMUX_UC_NMI

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

PU on PCH Page

1/20W

1/20W

1/20W

1/20W

96

1

C9650

B2
B1

D2
D1

E2
E1

F2
F1

H2
H1

J1

C2

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

0.1UF

20%
10V

2

X7R-CERM
0402

DP_INT_ML_C_P<0>
DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>
DP_INT_ML_C_N<1>

DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>

DP_INT_ML_C_P<3>
DP_INT_ML_C_N<3>

DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N

DPMUX_HPD_PD

NOSTUFF

1/20W

5%

1/20W

5%

5%

1/20W

1/20W

5%

5%

1/20W

1/20W

5% MF

1/20W

5%

1/20W

5%

5%

1/20W

NOSTUFF

5%

1/20W

NOSTUFF

1/20W

5%

NOSTUFF

5%

1/20W

5%

1/20W

1/20W

5%

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

NOSTUFF

5%

1/20W

DP 2:1 ANALOG MUX

J4

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

IN

5

85 97

BI

5

85 97

BI

76 97

IN

76 97

IN

76 97

IN

76 97

IN

76 97

IN

76 97

1

2

82

82

82

201

MF

MF

201

MF

201

MF

201

201

MF

201

MF

201

MF

201

201

201

MF5%

MF

201

201

MF5%

MF5%

201

MF

201

MF5%

201

82

IN

76 97

IN

76 97

IN

76 77 97

BI

76 77 97

BI

82

82

82

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_N<0>

DP_INT_IG_ML_P<1>
DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<2>
DP_INT_IG_ML_N<2>

DP_INT_IG_ML_P<3>
DP_INT_IG_ML_N<3>

DP_INT_IG_AUX_P
DP_INT_IG_AUX_N

DP_INT_EG_ML_P<0>
DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<2>
DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<3>
DP_INT_EG_ML_N<3>

DP_INT_EG_AUX_P
DP_INT_EG_AUX_N

LCD_MUX_SEL

LCD_MUX_EN

DPMUX UC PULL-DOWNS

DPMUX_UC_RESET_L

82

EG_RAIL1_EN

68 82

P0V95R1V8GPU_R_EN

68 82

EG_RAIL3_EN

68 82

EG_RAIL4_EN

68 82

EG_RAIL5_EN

68 82

LCD_PWR_EN

69 82 86

LCD_BKLT_EN

63 82 86

LCD_BKLT_PWM

63 82

DPMUX_UC_NMI

82

DPMUX_UC_MD1

82

DPMUX_UC_MD2

82

DPMUX_UC_PECI

82

DPMUX_UC_PEVREF

82

EG_RESET_L

70 82 85

DP_TBTSNK0_HPD_IG

12 82 85

DP_TBTSNK0_HPD_EG

76 77 82

DP_TBTSNK1_HPD_IG

12 82 85

DP_TBTSNK1_HPD_EG

76 77 82

DP_INT_IG_HPD

20 82

DP_INT_EG_HPD

76 77 82

GPU_GFX_OVERTEMP

77 82

GFX_SELF_THROTTLE

77 82

SMC_GFX_OVERTEMP

40 42 82

SMC_GFX_SELF_THROTTLE

40 42 82

LCD_MUX_SEL

82

LCD_MUX_EN

82

B4
A4

B5
A5

B6
A6

A8
A9

H9
J9

H8

NC

J8

NC

J2

NC

B8
B9

D8
D9

E8
E9

F8
F9

H6
J6

H5

NC

J5

NC

H3

NC

A1

B7

A2

DIN1_0+
DIN1_0-

DIN1_1+
DIN1_1-

DIN1_2+
DIN1_2-

DIN1_3+
DIN1_3-

DAUX1+
DAUX1-

DDC_CLK1
DDC_DAT1

VDD

U9650

CBTL06142EEE

CRITICAL

HPD_1

DIN2_0+
DIN2_0-

DIN2_1+
DIN2_1-

DIN2_2+
DIN2_2-

DIN2_3+
DIN2_3-

DAUX2+
DAUX2-

DDC_CLK2
DDC_DAT2

HPD_2

GPU_SEL

XSD*

GND

GND

B3

R9620
R9621
R9622
R9623
R9624
R9625
R9626
R9627
R9628
R9629
R9630
R9631
R9632
R9633
R9635
R9636
R9637
R9638
R9639
R9645
R9646
R9647
R9648
R9649
R9652

R9653
R9654

SYNC_MASTER=MARY_X425G

PAGE TITLE

VDD

TFBGA

DOUT_0+
DOUT_0-

DOUT_1+
DOUT_1-

DOUT_2+
DOUT_2-

DOUT_3+
DOUT_3-

HPDIN

DDC_AUX_SEL

GND

GND

GND

GND

G2H7H4G8C8

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

100K

100K

100K

100K

100K

100K

100K

100K

100K

100K

100K

100K
100K

AUX+
AUX-

eDP Mux

Apple Inc.

R9661

100K

2

G

SD

TP_DP_B_CA_DET_BUFTP_DP_A_CA_DET_BUF

1

1/20W

21

5%

MF

201

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R

6 3

1

2

R9662

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

MF

C9651

0.1UF

20%
10V
X7R-CERM
0402

100K

1%

1/20W

201

12

21

MF

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

SYNC_DATE=09/22/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

96 OF 119

SHEET

82 OF 97

124578

D

69 97

OUT

69 97

OUT

69 97

OUT

69 97

OUT

69 97

OUT

69 97

OUT

69 97

OUT

69 97

OUT

69 97

BI

69 97

BI

C

B

A

SIZE

D

8 7 6 5 4 3

12

D

DP A & DP B AUX MUX

55 66 67 68 69 82 84 86 96

PP3V3_S0

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52

OUT
BI

OUT
BI

NOSTUFF

R9740

1

470K

1%
1/20W
MF
201

2

82 83

IN

DP_TBTPA_DDC_CLK
DP_TBTPA_DDC_DATA

82 83

IN

DP_TBTPB_DDC_CLK
DP_TBTPB_DDC_DATA

82

IN

1

C9700

0.1UF

20%
10V

2

X7R-CERM
0402

13

VCC

U9700

TS3DS10224

DP_EXTA_MUX_EN

82 83

IN

DP_TBTSNK0_AUXCH_C_P

28 89 97

BI

DP_TBTSNK0_AUXCH_C_N

28 89 97

BI

C

DP_EXTB_MUX_EN

82 83

IN

DP_TBTSNK1_AUXCH_C_P

28 89 97

BI

DP_TBTSNK1_AUXCH_C_N

28 89 97

BI

16

ENA

1

QFN

INA+

2

INA-

14

SAI

10

ENB

3

INB+

4

INB-

SBI

GND

5

OUTA1+
OUTA1-

OUTA0+
OUTA0-

OUTB1+
OUTB1-

OUTB0+
OUTB0-

PAD

THRM

21

SAO

SBO

20

DP_TBTSNK0_EG_AUXCH_P

19

DP_TBTSNK0_EG_AUXCH_N

18

DPA_IG_AUX_CH_P

17

DPA_IG_AUX_CH_N

15

DP_EXTA_MUX_SEL_EG

6

DP_TBTSNK1_EG_AUXCH_P

7

DP_TBTSNK1_EG_AUXCH_N

8

DPB_IG_AUX_CH_P

9

DPB_IG_AUX_CH_N

1112

DP_EXTB_MUX_SEL_EG

76 77 97

BI

76 77 97

BI

12 85 89

BI

12 85 89

BI

82 83

IN

76 77 97

BI

76 77 97

BI

12 85 89

BI

12 85 89

BI

82 83

IN

NOSTUFF

R9720

1

470K

1%
1/20W
MF
201

2

NOSTUFF

R9730

1

470K

1%
1/20W
MF
201

2

31

31

32

32

DP A & DP B DDC MUX

NOSTUFF

R9750

1

470K

1%
1/20W
MF
201

2

DP_EXTA_MUX_EN

DP_EXTB_MUX_EN

DP_DDC_MUX_CROSSBAR_L

R9710

10K

1/16W
MF-LF

1

5%

402

2

16

ENA

1

INA+

2

INA-

14

SAI

10

ENB

3

INB+

4

INB-

SBI

13

DDC_XBAR_MUX

VCC

U9710

TS3DS10224

QFN

GND

5

OUTA1+
OUTA1-

OUTA0+
OUTA0-

OUTB1+
OUTB1-

OUTB0+
OUTB0-

PAD

THRM

21

1

2

SAO

SBO

C9710

0.1UF

20%
10V
X7R-CERM
0402

20
19

18
17

15

6
7

8
9

1112

R9751

1

470K

1%
1/20W
MF
201

2

DPA_EG_DDC_CLK
DPA_EG_DDC_DATA

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DP_EXTA_MUX_SEL_EG

DPB_EG_DDC_CLK
DPB_EG_DDC_DATA

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DP_EXTB_MUX_SEL_EG

R9752

1

470K

1%
1/20W
MF
201

2

R9753

1

470K

1%
1/20W
MF
201

2

76 77

IN

76 77

BI

12 85

IN

12 85

BI

82 83

IN

76 77

IN

76 77

BI

12 85

IN

12 85

BI

82 83

IN

R9754

1

470K

1%
1/20W
MF
201

2

D

C

MUX TRUTH TABLE

SAI/SBI SAO SBO | INA INB

0 0 0 OUTB0 OUTA0

B

0 0 1 OUTB1 OUTA0
0 1 0 OUTB0 OUTA1
0 1 1 OUTB1 OUTA1

1 0 0 OUTA0 OUTB0
1 0 1 OUTA0 OUTB1
1 1 0 OUTA1 OUTB0
1 1 1 OUTA1 OUTB1

A

SYNC_MASTER=MARY_X425G

PAGE TITLE

eDP Muxed Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/15/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

97 OF 119

SHEET

83 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

86
57 63

PPBUS_G3H

30 44
47 56
65 84

62 84

D

PPVIN_S5_HS_COMPUTING_ISNS

59 60

PPVIN_S5_HS_OTHER3V3_ISNS

44 61
84

PPVIN_S5_HS_OTHER5V_ISNS

44 61
84

PPBUS_S4_TPAD

45 65
84

PPVIN_S4_TPAD

38 45
84 86

84

PPVIN_S5_HS_GPU_ISNS

47 73
79 80

C

PPDCIN_G3H

56 57
84 86

PPDCIN_G3H_ISOL

44 56
57 84

84 86
50 56
40 41

PP3V42_G3H

19 34
37 38
42 43
57 67

B

84

PPVRTC_G3H

11 12
15 19

PP5V_S5

61 66 84
86

69 81 84

PP5V_S4

37 38 51
61 66 67
86

86

PP5V_S3

21 36 60
66 67 84

80 84 85 86

PP5V_S0

18 19 36 49 58 59
62 63 66 67 73 79

A

G3H/5V Rails TBT RAILS

PPBUS_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_COMPUTING_ISNS
PPVIN_S5_HS_COMPUTING_ISNS
PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_OTHER3V3_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_OTHER3V3_ISNS

PPVIN_S5_HS_OTHER5V_ISNS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_OTHER5V_ISNS
PPBUS_S4_TPAD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPBUS_S4_TPAD

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=13.05V
MAKE_BASE=TRUE

PPBUS_S4_TPAD

PPVIN_S4_TPAD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVIN_S4_TPAD

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_GPU_ISNS

PPVIN_S5_HS_GPU_ISNS
PPVIN_S5_HS_GPU_ISNS

PPVIN_S5_HS_GPU_ISNS

PPVIN_S5_HS_GPU_ISNS

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H
PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H_ISOL
PPDCIN_G3H_ISOL

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

PP5V_S5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM

PP5V_S5

PP5V_S4

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PP5V_S4
PP5V_S4
PP5V_S4
PP5V_S4
PP5V_S4
PP5V_S4
PP5V_S4

PP5V_S3

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PP5V_S3
PP5V_S3

PP5V_S3

PP5V_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0

PP5V_S0
PP5V_S0

PP5V_S0

PP5V_S0

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=13.05V
MAKE_BASE=TRUE

VOLTAGE=20V
MAKE_BASE=TRUE

VOLTAGE=20V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

84 85 86 96
32 33 61

PP3V3_S5

12 14 15 17
18 19 21 31
64 66 67 82

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

30 44 47 56 57 63 65 84 86

44 58 59 60 62 84 44 58

44 58 59 60 62 84

44 58 59 60 62 84

44 58 59 60 62 84

44 61 84

44 61 84

44 61 84

44 61 84

45 65 84

PP3V3_S4

20 33 38 41 42 45 46 65 66 67

81 84 85 86

45 65 84

45 65 84

38 45 84 86

38 45 84 86

47 73 79 80 84

47 73 79 80 84

47 73 79 80 84

84

47 73 79 80 84

47 73 79 80 84

47 73 79 80 84

PP3V3_SUS

11
12 13 14 15 17 50 64 66 67

56 57 84 86

56 57 84 86

44 56 57 84

44 56 57 84

44 56 57 84

50 56 57 67 84 86
19 34 37 38
40 41 42 43

PP3V3_S3

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56

57 67 84 86
86
19 34 37 38 40 41 42 43 50 56

57 67 84
86

PP3V3_S0

19 34 37
38 40 41 42 43 50 56 57 67 84

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

11 12 15 19 84

11 12 15 19 84

61 66 84 86

61 66 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

37 38 51 61 66 67 69 81 84 86

21 36 60 66 67 84 86

21 36 60 66 67 84 86

21 36 60 66 67 84 86

21 36 60 66 67 84 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67

73 79 80 84 85 86
85 86
18 19 36 49 58 59 62 63 66 67

73 79 80 84 85 86
18 19 36 49 58 59 62 63 66 67

80 84

PP3V3_S3RS0_CAMERA

18 19
36 49 58 59 62 63 66 67 73 79
85 86

18 19 36 49 58 59 62 63 66
67 73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

73 79 80 84

3.3V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

PP3V3_S5

PP3V3_S5
PP3V3_S5

PP3V3_S4

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE

PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4

PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS

PP3V3_S3

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3

PP3V3_S3

PP3V3_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.075 MM

PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0
PP3V3_S0

PP3V3_S3RS0_CAMERA

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S3RS0_CAMERA

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

1.5V/1.35V/1.05V/VCORE/BKLT Rails

PP1V35_S3

21 45 60 66
84 86

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

32 33 61 64 66 67 82 84 85 86
12 14 15 17
18 19 21 31
96

84 85 86 96
19 21 31 32 33 61 64 66 67 82
12 14 15 17 18

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

84 85 86 96
12 14 15 17 18 19 21 31 32 33
61 64 66 67 82

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 86 96

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

20 33 38 41 42
45
85
86
11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

11 12 13 14 15 17 50 64 66 67
84

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

13 20 21 43 45 46 66 81 82 84
86

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

67 68 69 82 83 84 86 96
44 45 46 47 48 49 51 52 55 66
11 12 13 14 15 17 19 20 29 34

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

67 68 69 82 83 84 86 96
44 45 46 47 48 49 51 52 55 66
11 12 13 14 15 17 19 20 29 34

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

83 84 86 96
48 49 51 52 55 66 67 68 69 82
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47

66 67 68
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

66 67
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

66 67 68 69 82 83 84 86 96
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55
66 67 68 69 82 83 84 86 96

PP1V35_S3_MEM

22 23 24 25 26 27 45 84 92

PP1V35_S3RS0_FET

82 84 85 86 96
32 33 61 64 66 67
12 14 15 17 18 19 21

PP1V35_S3RS0_CPUDDR

6 8

10 21 66 67 84 96

PP1V5_S0

11 12 13 15
17 19 52 64 67 81 84 86

46 65 66 67 81 84

PPVTTDDR_S3

60 84 86

PPVTT_S0_DDR

21 27 60 84 86

PP1V05_SUS

18 64 84

PP1V05_S0

10 14 15 17
18 41 62 67 84 86

PPVCC_S0_CPU

6 8

10 45 59

84 86

PPBUS_SW_BKL

63 84

13 20 35 46 84

13 20 35 46 84

31

43

43

28 29 30 45 84

PP3V3_S0SW_SSD_R

45 66 84

PP3V3_S0SW_SSD

34 45 84 86

PP3V3_S4_TBT

PP1V35_S3

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.17 MM

PP1V35_S3

PP1V35_S3

PP1V35_S3
PP1V35_S3
PP1V35_S3

PP1V35_S3_MEM

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.17 MM

PP1V35_S3_MEM
PP1V35_S3_MEM
PP1V35_S3_MEM

PP1V35_S3RS0_FET

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V35_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V35_S3RS0_CPUDDR
PP1V35_S3RS0_CPUDDR

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM

PPVTT_S0_DDR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.17 mm

PPVTT_S0_DDR
PPVTT_S0_DDR

PPVTT_S0_DDR

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0

PPVCC_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPVCC_S0_CPU
PPVCC_S0_CPU

PPBUS_SW_BKL

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM

PP3V3_S4_TBT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM

PP3V3_S0SW_SSD_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP3V3_S0SW_SSD

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.35V
MAKE_BASE=TRUE

VOLTAGE=1.35V
MAKE_BASE=TRUE

VOLTAGE=1.35V
MAKE_BASE=TRUE

VOLTAGE=1.35V
MAKE_BASE=TRUE

VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=0.675V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.675V
MAKE_BASE=TRUE

VOLTAGE=1.05V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=1.8V
MAKE_BASE=TRUE

VOLTAGE=12.6V
MAKE_BASE=TRUE

21 45 60 66
84 86

21 45 60 66 84 86

21 45 60 66 84 86

21 45 60 66 84 86

21
45 60 66 84 86

21 45 60 66 84 86

22 23 24 25 26 27 45 84 92

22 23 24 25 26 27 45 84 92

22 23 24 25 26 27 45 84 92

22 23 24 25 26 27 45 84 92

66 84 66 84

6 8

10 21 66 67 84 96

6 8

10 21 66 67 84 96

6 8

10 21 66 67 84 96

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

11 12 13 15 17 19 52 64 67 81
84 86

60 84 86

21 27 60 84 86

21 27 60 84 86

21 27 60 84 86

21 27 60 84 86

18 64 84

18 64 84

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62
67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67 84 86

10 14 15 17 18 41 62 67
84 86

10 14 15 17 18 41 62 67 84 86

6 8

10 45 59 84 86

6 8

10 45 59 84 86

6 8

10 45 59 84 86

63 84

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_TBTLC

PP15V_TBT

30 31 32 84

PP1V8_GPUIFPX

71 76 78 80 84

PP3V3_S0GPU

47 66 68 71 72 76 77
79 80 84

PP1V35_GPU_REG

47 71 72 73 74 75 84

PP0V95_S0GPU

71 80 84

PPVCORE_GPU

47
71 79 84

28 29 30 45 84

45 66 84

34 45 84 86

PPVDDCI_S0_ISENSE

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.15 MM

PP3V3_TBTLC

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM

PP15V_TBT
PP15V_TBT

PPVIN_SW_TBTBST

VOLTAGE=12.8V

"GPU" Rails

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8_GPUIFPX

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM

PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU
PP3V3_S0GPU

PP3V3_S0GPU

PP3V3_S0GPU
PP3V3_S0GPU

PP1V35_GPU_REG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.35V
MAKE_BASE=TRUE

PP1V35_GPU_REG
PP1V35_GPU_REG
PP1V35_GPU_REG
PP1V35_GPU_REG
PP1V35_GPU_REG

PP0V95_S0GPU

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.95V
MAKE_BASE=TRUE

PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU
PP0V95_S0GPU

PPVDDCI_S0_ISENSE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVDDCI_S0_ISENSE

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVCORE_GPU

GND

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.085 MM
VOLTAGE=0V
MAKE_BASE=TRUE

SYNC_MASTER=CLEAN_X305

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

12

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=15V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE
VOLTAGE=3.3V

VOLTAGE=1.12V
MAKE_BASE=TRUE

VOLTAGE=1.0V
MAKE_BASE=TRUE

SYNC_DATE=05/30/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

100 OF 119

SHEET

84 OF 97

124578

19 20 28
29 84

19 20 28
29 84

30 31 32 84

30 31 32 84

30 31 32 84

30

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

71 76 78 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 66 68 71 72 76
77 79 80 84

47 71 72 73 74
75 84

47 71 72 73 74
75 84

47 71 72 73 74
75 84

47 71 72 73 74
75 84

47 71 72 73 74
75 84

47 71 72 73 74
75 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

70 71 73 78 84

71 80 84

71 80 84

47 71 79 84

47 71 79 84

SIZE

D

D

C

B

A

8 7 6 5 4 3

CPU signals

Display Aliases

EDP_IG_PANEL_PWR

12 82 85

MAKE_BASE=TRUE

EDP_IG_BKL_ON

12 82 85

MAKE_BASE=TRUE

DP_INT_IG_ML_P<3..0>

5

82 97

MAKE_BASE=TRUE

DP_INT_IG_ML_N<3..0>

5

D

C

82 97

MAKE_BASE=TRUE

DP_INT_IG_AUX_P

5

82 85 97

MAKE_BASE=TRUE

DP_INT_IG_AUX_N

5

82 85 97

MAKE_BASE=TRUE

DPA_IG_AUX_CH_P

12 83 85 89

MAKE_BASE=TRUE

DPA_IG_AUX_CH_N

12 83 85 89

MAKE_BASE=TRUE

DPB_IG_AUX_CH_P

12 83 85 89

MAKE_BASE=TRUE

DPB_IG_AUX_CH_N

12 83 85 89

MAKE_BASE=TRUE

DPA_IG_DDC_CLK

12 83 85

MAKE_BASE=TRUE

DPA_IG_DDC_DATA

12 83 85

MAKE_BASE=TRUE

DPB_IG_DDC_CLK

12 83 85

MAKE_BASE=TRUE

DPB_IG_DDC_DATA

12 83 85

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_IG

12 82 85

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_IG

12 82 85

MAKE_BASE=TRUE

DPMUX_UC_RX

82 85

MAKE_BASE=TRUE

DPMUX_UC_TX

82 85

MAKE_BASE=TRUE

EG_RESET_L

70 82 85

MAKE_BASE=TRUE

MAKE_BASE=TRUE

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

TP_DP_IG_A_MLP<3..0>

TP_DP_IG_A_MLN<3..0>

DP_INT_IG_AUX_P

DP_INT_IG_AUX_N

DPA_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DPB_IG_AUX_CH_P

DPB_IG_AUX_CH_N

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DP_TBTSNK0_HPD_IG
DP_TBTSNK1_HPD_IG

DPMUX_UC_RX

DPMUX_UC_TX

EG_RESET_L
PEG_CLKREQ_LPEG_CLKREQ_L

12 82 85

12 82 85

5

82 85 97

5

82 85 97

12 83 85 89

12 83 85 89

12 83 85 89

12 83 85 89

12 83 85

12 83 85

12 83 85

12 83 85

12 82 85

12 82 85

82 85

82 85

70 82 85

11 82 85 11 82 85

LCD_FSS

MAKE_BASE=TRUE

PEG_CLK100M_N

11 70 85 91

MAKE_BASE=TRUE

PEG_CLK100M_P

11 70 85 91

MAKE_BASE=TRUE

VSNS_GPU_VDDC_P

MAKE_BASE=TRUE

VSNS_GPU_VDDI_P

71 80 85 96

MAKE_BASE=TRUE

LCD_FSS

PEG_CLK100M_N
PEG_CLK100M_P

VSNS_GPU_VDDC_P

VSNS_GPU_VDDI_P

69 82 85 86 69 82 85 86

11 70 85 91

11 70 85 91

71 79 85 96 71 79 85 96

71 80 85 96

5

34 89

5

34 89

5

34 89

5

34 89

5

28 89

5

28 89

5

28 89

5

28 89

MEMVTT_EN

21 60 85

MAKE_BASE=TRUE

J9510 RIO FLEX CONN

SMBUS_PCH_DATA SMBUS_PCH_DATA

13 18 43 81 85 86 91 13 18 43 81 85 86 91

SMBUS_PCH_CLK

13 18 43 81 85 86 91

SSD Signals Through PEG

PCIE_SSD_D2R_P<3..0>

IN

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<3..0>

IN

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<3..0>

OUT

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<3..0>

OUT

MAKE_BASE=TRUE

Thunderbolt Signals Through PEG

PCIE_TBT_D2R_P<3..0>

IN

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

IN

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

OUT

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

OUT

MAKE_BASE=TRUE

GUP PEG Lanes

PEG_D2R_P<7..0>

70 89

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

70 89

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

68 70 89

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

68 70 89

MAKE_BASE=TRUE

MEMVTT_EN

SMBUS_PCH_CLK

=PEG_D2R_P<15..12>
=PEG_D2R_N<15..12>
=PEG_R2D_C_P<15..12>
=PEG_R2D_C_N<15..12>

=PEG_D2R_P<11..8>
=PEG_D2R_N<11..8>
=PEG_R2D_C_P<11..8>
=PEG_R2D_C_N<11..8>

=PEG_D2R_P<7..0>
=PEG_D2R_N<7..0>
=PEG_R2D_C_P<7..0>
=PEG_R2D_C_N<7..0>

12

21 60 85

13 18 43 81 85 86 91

OUT

OUT

IN

IN

OUT

OUT

IN

IN

5

5

5

5

D

C

DP_AUXCH_ISOL_L

MAKE_BASE=TRUE

DP_AUXCH_ISOL_L

11 18 85 11 18 85

Unused PCH PCIE Lanes

NC_PCIE_SSD_D2RP<3..0>

13

NC_PCIE_SSD_D2RN<3..0>

13

NC_PCIE_SSD_R2D_CP<3..0>

13

NC_PCIE_SSD_R2D_CN<3..0>

PP3V3_S4

20 33 38 41 42 45 46 65 66 67
81 84 85 86

RA294

100K

2 1

1%

Unused TPAD SPI

B

TPAD_SPI_BUS_EN TPAD_SPI_BUS_EN

38 85

TPAD_SPI_CS_L

38 85 91

TPAD_SPI_INT_L

38 85

TPAD_SPI_MISO

38 85 91

TPAD_SPI_MOSI

38 85 91

TPAD_SPI_SCLK

38 85 91

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

22 23 24 85 89 92 22 23 24 85 89 92

PP0V75_S3_MEM_VREFDQ_B

22 25 26 85 89

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

PP0V75_S3_MEM_VREFCA

22 23 24 25 26 85 89 92

38 85

TPAD_SPI_CS_L

38 85 91

TPAD_SPI_INT_L

38 85

TPAD_SPI_MISO

38 85 91

TPAD_SPI_MOSI

38 85 91

TPAD_SPI_SCLK

38 85 91

VOLTAGE

0.675V

0.675V

0.675V

MAKE_BASE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MAKE_BASE

TRUE

TRUE

TRUE

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA

1/20W

MF

201

RA296

100K

2 1

1%

1/20W

MF

201

RA298

100K

2 1

1%

1/20W

MF

201

RA295

100K

2 1

1%

1/20W

MF

201

RA297

100K

2 1

1%

1/20W

MF

201

RA299

100K

2 1

1%

1/20W

MF

201

22 25 26 85 89

22 23 24 25 26 85 89 92

PP3V3_S3_FAN_CTL

49 85

RA201

0

5%

1/20W

MF

0201

0

5%

1/20W

MF

0201

RA202

NOSTUFF

21

21

PP3V3_S5

PP3V3_S4

PP3V3_S3_FAN_CTL

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

MAKE_BASE=TRUE

13

49 85

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 86 96

20 33 38 41 42 45 46 65 66 67
81 84 85 86

A

PP5V_S0

18 19 36 49 58 59 62 63 66 67
73 79 80 84 86

XWA202

SM

21

XWA203

SM

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

21

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

53

53

I2C_BKLT_SCL

63 69 85 86

MAKE_BASE=TRUE

I2C_BKLT_SDA

63 69 85 86

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

36 40 43 48 69 76 85 86 95

SMBUS_SMC_0_S0_SDA

36 40 43 48 69 76 85 86 95

EDP CABLE

I2C_BKLT_SCL

I2C_BKLT_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

63 69 85 86

63 69 85 86

36 40 43 48 69 76 85 86 95

36 40 43 48 69 76 85 86 95

MAKE_BASE

12

14

14

14

14

11

11

12

12

12

14

14 82

11 82 85

11

12

28

12

14

SYNC_MASTER=J15_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

NO_TEST

TRUETRUE

TRUE TRUE

TRUE TRUE

TRUE TRUE

=PCIE_SSD_D2R_P<3..0>
=PCIE_SSD_D2R_N<3..0>
=PCIE_SSD_R2D_C_P<3..0>
=PCIE_SSD_R2D_C_N<3..0>

Unused signals

BT_PWRRST_L
MEM_VDD_SEL_1V5_L
FW_PWR_EN_PCH
WOL_EN
FW_PME_L
DP_TBT_SEL
ENET_MEDIA_SENSE_RDIV
AUD_IPHS_SWITCH_EN_PCH
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
TBT_GO2SX_BIDIR
DPMUX_UC_IRQ
PEG_CLKREQ_L
ENET_CLKREQ_L
ENET_LOW_PWR_PCH
HDMITBTMUX_SEL_TBT
SDCONN_OC_L
LPCPLUS_GPIO

Signal Aliases

Apple Inc.

R

I1490

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

102 OF 119

SHEET

85 OF 97

124578

SIZE

B

A

D

8 7 6 5 4 3

Functional Test Points

12

J6100 - spi

PP3V42_G3H

TRUE

SMC_RESET_L

TRUE

SMC_TCK

TRUE

SMC_TMS

TRUE

SPIROM_USE_MLB

TRUE

GND

TRUE

J4801 - ipd flex

USB_TPAD_N

TRUE

USB_TPAD_P

TRUE

IOXP2_INT_L

TRUE

I2C_IOXP_SCL

TRUE

I2C_IOXP_SDA

TRUE

SMC_PME_S4_WAKE_L

TRUE

TPAD_ACTUATOR_THRMTRIP_L

TRUE

TPAD_VBUS_EN

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

SMC_LID

TRUE

SMC_ACTUATOR_EN_L

TRUE

PPVIN_S4_TPAD

TRUE

GND_ACTUATOR

TRUE

PP3V3_S4

TRUE

PP5V_S4

TRUE

GND

TRUE

J4813 - keyboard

PP3V3_S4

TRUE

PP3V42_G3H

TRUE

WS_CONTROL_KBD

TRUE

WS_KBD1

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD2

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

GND

TRUE

J4915 - kbd bklt

KBDBKLT_RETURN1

TRUE

KBDBKLT_RETURN2

TRUE

PPVOUT_S0_KBDBKLT

TRUE

GND

TRUE

19 34 37 38 40 41 42 43 50 56
57 67 84 86

40 41 50 57

40 41 50

40 41 50

14 50

2X

13 38 90

13 38 90

38

38

38

33 38 40 42

38 65

38 67

38 40 43 95

38 40 43 95

38 40 41 42

38 40

4X

38 45 84

4X

38

20 33 38 41 42 45 46 65 66 67
81 84 85 86

37 38 51 61 66 67 69 81 84 86

2X

20 33 38 41 42 45 46 65 66 67
81 84 85 86

19 34 37 38 40 41 42 43 50 56
57 67 84 86

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

2X

2X

39 63

2X

39 63

39 63

4X

I1929

I1930

I1931
I1932

I1934

I1936
I1935

I1938
I1939

I1940

I1941

I1942
I1944

I1943

I2036
I2035

I2034

I2033
I2032

I2030

I2029
I2028

I2027

I2026
I2025

I2024
I2023

I2022

I2021
I2020

I2019

I2018
I2017

I1965

I1966

I1967

J6601 - mic

DMIC_CLK3

TRUE

PP3V3_S0

TRUE

DMIC_SDA2

TRUE

DMIC_SDA3

TRUE

GND

TRUE

J6602 - L speaker

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_SL_OUT_P

TRUE

GND

TRUE

J6603 - R speaker

SPKRCONN_R_ID

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_SR_OUT_P

TRUE

GND

TRUE

J7000 - DC PWR

ADAPTER_SENSE

TRUE

PP20V_DCIN_FUSE

TRUE

GND

TRUE

J7050 - battery

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SYS_DETECT_L

TRUE

GND

TRUE

J8300 - eDP

DP_INT_AUX_N

TRUE

DP_INT_AUX_P

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_N<1>

TRUE

DP_INT_ML_N<2>

TRUE

DP_INT_ML_N<3>

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_P<2>

TRUE

DP_INT_ML_P<3>

TRUE

LCD_FSS

TRUE

LCD_HPD_CONN

TRUE

LCD_BKLT_PWM_R

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

I2C_BKLT_SDA

TRUE

I2C_BKLT_SCL

TRUE

PP5VR3V3_SW_LCD

TRUE

PPVOUT_S0_LCDBKLT

TRUE

GND

TRUE

Power Rails

PM_SLP_S3_L

TRUE

PPVTT_S0_DDR

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

PPVCC_S0_CPU

TRUE

PPVTTDDR_S3

TRUE

PP3V3_S0SW_SSD

TRUE

PP1V5_S0

TRUE

PP1V35_S3

TRUE

52 55
66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

55

52 55

52 55

53 55 96

53 55 96

53 55 96

53 55 96

52 55

53 55 96

53 55 96

53 55 96

53 55 96

56

2X

56

2X

8X

56 57

40 43 56 57 95

40 43 56 57 95

56

8X

69 97

69 97

69 97

69 97

69 97

69 97

69 97

69 97

69 97

69 97

69 82 85

69

63 69

36 40 43 48 69 76 85 86 95

36 40 43 48 69 76 85 86 95

63 69 85

63 69 85

3X

69

63 69

16X

12 21 40 67

21 27 60 84
66 67 68 69 82 83 84 86 96

11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

13 20 21 43 45 46 66 81 82 84
86

12 14 15 17 18 19 21 31 32 33
61 64 66 67 82 84 85 96

40 41

19 34 37 38 40 41 42 43 50 56
57 67 84 86

18 19 36 49 58 59 62 63 66 67
73 79 80 84 85 86

21 36 60 66 67 84

61 66 84

30 44 47 56 57 63 65 84

56 57 84

6 8

10 45 59 84

60 84

34 45 84

11 12 13 15 17 19 52 64 67 81
84

21 45 60 66 84

I2071

I2070

I2069
I2068

I2067

FUNC_TEST

FUNC_TEST

D

J3501 - airport

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PCIE_AP_D2R_PI_N

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3RS4_BT_F

TRUE

PP3V3_WLAN

TRUE

USB_BT_CONN_N

TRUE

USB_BT_CONN_P

TRUE

WIFI_EVENT_L

TRUE

GND

TRUE

33

33

91

91

33 91

33 91

33 91

33 91

12 33 35 91

33

33 41

33 90

33 90

33 40 41

4X

J4002 - Camera

MIPI_CLK_CONN_N

TRUE

MIPI_CLK_CONN_P

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

MIPI_DATA_CONN_N

TRUE

MIPI_DATA_CONN_P

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

GND

TRUE

C

J9500 - rio coax

HDMI_EG_CLK_N

TRUE

HDMI_EG_CLK_P

TRUE

HDMI_EG_DATA_N<0>

TRUE

HDMI_EG_DATA_N<1>

TRUE

HDMI_EG_DATA_N<2>

TRUE

HDMI_EG_DATA_P<0>

TRUE

HDMI_EG_DATA_P<1>

TRUE

HDMI_EG_DATA_P<2>

TRUE

USB3_SD_D2R_N

TRUE

USB3_SD_D2R_P

TRUE

USB3_SD_R2D_C_N

TRUE

USB3_SD_R2D_C_P

TRUE

USB3_EXTB_D2R_N

TRUE

USB3_EXTB_D2R_P

TRUE

USB3_EXTB_R2D_N

TRUE

USB3_EXTB_R2D_P

TRUE

USB_EXTB_N

TRUE

USB_EXTB_P

TRUE

GND

TRUE

36 94

36 94

36

36 94

36 94

36 40 43 48 69 76 85 86 95

36 40 43 48 69 76 85 86 95

35 36

35 36

36

76 81 97

76 81 97

76 81 97

76 81 97

76 81 97

76 81 97

76 81 97

76 81 97

13 20 81 91

13 20 81 91

13 20 81 91

13 20 81 91

13 81 90

13 81 90

81 90

81 90

13 81 90

13 81 90

19X

I2053
I2052

I2051

I2049
I2050

I2047

I2048
I2045

I2044
I2043

I2041

I2042
I2040

I2038

I2039
I2037

J9510 - rio flex

SD_PWR_EN

TRUE

B

A

I2016

I2015

I2014
I2013

I2012

I2011
I2010

I2009
I2008

I2007

I2006
I2005

I2004

HDMI_DDC_CLK

TRUE

HDMI_DDC_DATA

TRUE

HDMI_HPD

TRUE

SMBUS_PCH_CLK

TRUE

SMBUS_PCH_DATA

TRUE

PM_SLP_S3_BUF_L

TRUE

PM_SLP_S4_L

TRUE

PP3V3_S3

TRUE

PP3V3_S4

TRUE

PP5V_S4

TRUE

RIO_SDCONN_STATE_CHANGE_L

TRUE

USB_EXTB_OC_L

TRUE

GND

TRUE

J5150 - hall effect

PP3V42_G3H

TRUE

SMC_LID_R

TRUE

GND

TRUE

J6050 - left fan

FAN_LT_PWM

TRUE

FAN_LT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

J6060 - right fan

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

13 18 81

20 81 82

13 18 43 81 85 91

13 18 43 81 85 91

51 66 67 81 82

12 21 33 37 40 67 81

3X

13 20 21 43 45 46 66 81 82
84 86

20 33 38 41 42 45 46 65 66 67
81 84 85 86

5X

37 38 51 61 66 67 69 81 84
86

20 81

18 81

10X

19 34 37 38 40 41 42 43 50 56
57 67 84 86

42

49

49

3X

18 19 36 49 58 59 62 63 66
67 73 79 80 84 85 86

5X

49

49

18 19 36 49 58 59 62 63 66

3X

67 73 79 80 84 85 86

5X

I1948
I1949

I1950

I1951
I1952

I1953

I1955
I1954

I1956

I1957
I1958

I1959
I1960

I1961

I1962
I1963

I1968

I1969

I1970
I1971

I1972

I1973
I1974

I2072
I2073

I2074

I2075
I2076

I2077

FUNC_TEST

FUNC_TEST

FUNC_TEST

6 3

XDP

XDP_CPU_TCK

TRUE

XDP_PCH_TCK

TRUE

XDP_CPU_TDI

TRUE

XDP_CPU_TDO

TRUE

XDP_CPUPCH_TRST_L

TRUE

XDP_CPU_TMS

TRUE

XDP_PCH_TMS

TRUE

XDP_PCH_TDI

TRUE

XDP_PCH_TDO

TRUE

XDP_CPU_PREQ_L

TRUE

XDP_CPU_PRDY_L

TRUE

PM_RSMRST_L

TRUE

PM_PCH_PWROK

TRUE

PM_SYSRST_L

TRUE

CPU_CFG<3>

TRUE

PP1V05_S0

TRUE

GND

TRUE

Power Sequence

SMC_ONOFF_L

TRUE

PM_DSW_PWRGD

TRUE

ALL_SYS_PWRGD

TRUE

PM_PCH_SYS_PWROK

TRUE

PLT_RESET_L

TRUE

LCD_PWR_EN

TRUE

LCD_BKLT_EN

TRUE

GPU_VENUS JTAG

GPU_JTAG_TCK

TRUE

GPU_JTAG_TDI

TRUE

GPU_JTAG_TDO

TRUE

GPU_JTAG_TMS

TRUE

GPU_JTAG_TRST_L

TRUE

GPU_PWRGOOD

TRUE

6

18 89

11 18

6

18 89

6

18 89

6

18 89

6

18 89

11 18

11 18

11 18

6

18 89

6

18 89

12 67 91

12 19 91

12 19 40 91

6

18 89

10 14 15 17 18 41 62 67 84

2X GND

38 40 41

12 40 91

18 19 40 58 67

12 18 19 40 91

12 18 20 21

69 82

63 82

76 77

76 77

76 77

76 77

76 77

SYNC_MASTER=J15_MLB

PAGE TITLE

SYNC_DATE=10/31/2012

Functional Test Points

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

104 OF 119

SHEET

86 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

NC NO_TESTs

12

PCH

NO_TEST NO_TEST

NC_USB3_SPARE_D2RN

13 87

NC_USB3_SPARE_D2RP

13 87

NC_USB3_SPARE_R2D_CN
NC_USB3_SPARE_R2D_CP

13 87

NC_USB3_EXTC_D2RN

13 87 90

NC_USB3_EXTC_D2RP

D

C

B

13 87 90

NC_USB3_EXTC_R2D_CN

13 87 90

NC_USB3_EXTC_R2D_CP

13 87 90

NC_USB3_EXTD_D2RN

13 87 90

NC_USB3_EXTD_D2RP

13 87 90

NC_USB3_EXTD_R2D_CN

13 87 90

NC_USB3_EXTD_R2D_CP

13 87 90

NC_PCIE_ENET_D2RN

87

NC_PCIE_ENET_D2RP

87

NC_PCIE_ENET_R2D_CN

87

NC_PCIE_ENET_R2D_CP

87

NC_SATA_A_D2RN

11 87 90

NC_SATA_A_D2RP

11 87 90

NC_SATA_A_R2D_CN

11 87 90

NC_SATA_A_R2D_CP

11 87 90

NC_SATA_B_D2RN

11 87 90

NC_SATA_B_D2RP

11 87 90

NC_SATA_B_R2D_CN

11 87 90

NC_SATA_B_R2D_CP

11 87 90

NC_SATA_ODD_D2RN

11 87

NC_SATA_ODD_D2RP

11 87 11 87

NC_SATA_ODD_R2D_CN

11 87

NC_SATA_ODD_R2D_CP

11 87

NC_SATA_D_D2RN

11 87

NC_SATA_D_D2RP

11 87

NC_SATA_D_R2D_CN

11 87

NC_SATA_D_R2D_CP

11 87

NC_SATA_F_D2RN

11 87

NC_SATA_F_D2RP

11 87

NC_SATA_F_R2D_CN

11 87

NC_SATA_F_R2D_CP

11 87

NC_USB_EXTCN

13 87 90

NC_USB_EXTCP

13 87 90

NC_USB_SDN

13 87 90

NC_USB_SDP

13 87 90

NC_USB_WLANN

13 87 13 87

NC_USB_WLANP

13 87

NC_USB_6N

13 87 90

NC_USB_6P

13 87 90

NC_USB_7N

13 87 90

NC_USB_7P

13 87 90

NC_USB_EXTDN

13 87 90

NC_USB_EXTDP

13 87 90

NC_USB_PSOCN

13 87

NC_USB_PSOCP

13 87

NC_USB_IRN

13 87 90

NC_USB_IRP

13 87 90

MAKE_BASE
TRUE TRUE
TRUE TRUE
TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE TRUE
TRUE TRUE

TRUE

TRUE TRUE

TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE
TRUE TRUE

TRUE

TRUE
TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE TRUE
TRUE
TRUE

NC_USB3_SPARE_D2RN
NC_USB3_SPARE_D2RP
NC_USB3_SPARE_R2D_CN

TRUE

NC_USB3_SPARE_R2D_CP
NC_USB3_EXTC_D2RN
NC_USB3_EXTC_D2RP
NC_USB3_EXTC_R2D_CN

TRUETRUE

NC_USB3_EXTC_R2D_CP
NC_USB3_EXTD_D2RN
NC_USB3_EXTD_D2RP

TRUETRUE

NC_USB3_EXTD_R2D_CN

TRUETRUE

NC_USB3_EXTD_R2D_CP

TRUETRUE

NC_PCIE_ENET_D2RN

TRUE

NC_PCIE_ENET_D2RP

TRUETRUE

NC_PCIE_ENET_R2D_CN

TRUETRUE

NC_PCIE_ENET_R2D_CP

TRUETRUE

NC_SATA_A_D2RN

TRUETRUE

NC_SATA_A_D2RP

TRUETRUE

NC_SATA_A_R2D_CN

TRUETRUE

NC_SATA_A_R2D_CP

TRUETRUE

NC_SATA_B_D2RN

TRUETRUE

NC_SATA_B_D2RP
NC_SATA_B_R2D_CN

TRUETRUE

NC_SATA_B_R2D_CP

TRUETRUE

NC_SATA_ODD_D2RN

TRUE

NC_SATA_ODD_D2RP
NC_SATA_ODD_R2D_CN
NC_SATA_ODD_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP

TRUETRUE

NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP

TRUETRUE

NC_SATA_F_R2D_CN

TRUETRUE

NC_SATA_F_R2D_CP

TRUETRUE

NC_USB_EXTCN

TRUE

NC_USB_EXTCP
NC_USB_SDN

TRUETRUE

NC_USB_SDP

TRUE

NC_USB_WLANN

TRUETRUE

NC_USB_WLANP

TRUE

NC_USB_6N

TRUE

NC_USB_6P
NC_USB_7N
NC_USB_7P
NC_USB_EXTDN
NC_USB_EXTDP

TRUETRUE

NC_USB_PSOCN
NC_USB_PSOCP

TRUE

NC_USB_IRN

TRUE

NC_USB_IRP

TRUETRUE

13 87

13 87

13 87 13 87

13 87

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

87

87

87

87

11 87 90

11 87 90

11 87 90

11 87 90

11 87
90

11 87 90

11 87 90

11 87 90

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

13 87 90

13 87 90

13 87 90

13 87 90

13 87

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

13 87 90

13 87

13 87

13 87 90

13 87 90

NC_TBT_XTAL25OUT

28 87

TP_DP_TBTSRC_ML_CP<3..0>
TP_DP_TBTSRC_ML_CN<3..0>
NC_DP_TBTSRC_AUXCH_CP

28
87

NC_DP_TBTSRC_AUXCH_CN

28
87

NC_DP_IG_D_AUXCHN

12 87

NC_DP_IG_D_AUXCHP

12 87

NC_PCIE_CLK100M_PE5N

11
87

NC_PCIE_CLK100M_PE5P

11 87

NC_PCIE_CLK100M_ENETSDN

11
87

NC_PCIE_CLK100M_ENETSDP

11
87

NC_PCIE_CLK100M_ENETN

11
87

NC_PCIE_CLK100M_ENETP

11 87

NC_PCIE_CLK100M_PEGBN

11 87

NC_PCIE_CLK100M_PEGBP

11 87

NC_PCIE_CLK100M_SWN

11 87

NC_PCIE_CLK100M_SWP

11 87

NC_PCH_GPIO64_CLKOUTFLEX0

11 87

NC_PCH_GPIO65_CLKOUTFLEX1

11 87

NC_PCH_GPIO66_CLKOUTFLEX2

11 87

NC_PCH_GPIO67_CLKOUTFLEX3

11 87

NC_USB_4N

13 87

NC_USB_4P

13 87

TP_DVPCNTL_M<1..0>
TP_DVPCNTL<2..0>
NC_DVPCLK

76 87

TP_NC_DVPDATA<23..6>
NC_FB_B0_A<9>

72 87

NC_FB_B1_A<9>

72 87

NC_FB_A1_A<9>

72 87 72 87

Thunderbolt

TRUE TRUE
TRUE TRUE

TRUE
TRUE TRUE

TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE TRUE

TRUE TRUE
TRUE TRUE

TRUE TRUE

TRUE TRUE
TRUE TRUE

TRUE TRUE
TRUE TRUE
TRUE TRUE

TRUE TRUE

MAKE_BASE

TRUETRUE

TRUETRUE
TRUETRUE

TRUE

TRUETRUE

TRUETRUE

TRUETRUE

TRUETRUE

TRUETRUE
TRUETRUE

TRUETRUE
TRUETRUE

TRUETRUE

TRUETRUE

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_ML_CP<3..0>
NC_DP_TBTSRC_ML_CN<3..0>
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN

NC_DP_IG_D_AUXCHN
NC_DP_IG_D_AUXCHP

NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_ENETSDN
NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_PEGBN
NC_PCIE_CLK100M_PEGBP
NC_PCIE_CLK100M_SWN
NC_PCIE_CLK100M_SWP

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

NC_USB_4N
NC_USB_4P

NC_DVPCNTL_M<1..0>
NC_DVPCNTL<2..0>
NC_DVPCLK
NC_DVPDATA<23..6>
NC_FB_B0_A<9>
NC_FB_B1_A<9>
NC_FB_A0_A<9>NC_FB_A0_A<9>
NC_FB_A1_A<9>

28 87

28

28

28 87

28 87

12 87

12 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

13 87

13 87

76

76

76 87

76

72 87

72 87

72 87 72 87

11 87

11 87

11 87

11 87

28 31 93

28 31 93

PLACEABLE BEAD-PROBES FOR TBT

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>

1
1

TP

SM

TP

SM

BEAD-PROBE
BEAD-PROBE

BPA531
BPA532

NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE

D

C

B

NC_ITPXDP_CLK100MN

11 87 89

NC_ITPXDP_CLK100MP

11 87 89

NC_PCI_PME_L

12 87

NC_HDA_SDIN1

11 87

NC_HDA_SDIN2

11 87

NC_HDA_SDIN3

11 87

NC_LPC_DREQ0_L

13 87

NC_CLINK_CLK

13 87

NC_CLINK_DATA

13 87

NC_CLINK_RESET_L

13 87

NC_EDP_IG_BKL_PWM

12 87

TRUE TRUE

TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE
TRUE TRUE

TRUE

A

NC_USB_SMCP

87 90

NC_USB_SMCN

87 90

NC_SMC_INTERFACE_2

87

TRUE TRUE

TRUE TRUE

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP

TRUETRUE

NC_PCI_PME_L

TRUETRUE

NC_PCI_CLK33M_OUT3NC_PCI_CLK33M_OUT3
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
NC_LPC_DREQ0_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

TRUE

NC_LPC_CLK33M_LPCPLUS_RNC_LPC_CLK33M_LPCPLUS_R

NC_EDP_IG_BKL_PWM

TRUE

NC_USB_SMCP

TRUETRUE

NC_USB_SMCN

NC_SMC_INTERFACE_2

11 87 89

11 87 89

12 87

11 87 11 87

11 87

11 87

11 87

13 87

13 87

13 87

13 87

11 87 91 11 87 91

12 87

87 90

87 90

87

I1975
I1977

I1976

I1978

TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE

PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
PCIE_TBT_D2R_C_N<3..0>

DMI_S2N_P<3..1>
DMI_S2N_N<3..1>
DMI_N2S_P<3..1>
DMI_N2S_N<3..1>

28 89

28 89

28 89

28 89

5

5

5

5

12 89

12 89

12 89

12 89

6 3

SYNC_MASTER=J15_MLB

PAGE TITLE

NC & No Test

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/31/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

105 OF 119

SHEET

87 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

X425G BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

DEFAULT

LAYER

ALLOW ROUTE
ON LAYER?

*
*

MINIMUM LINE WIDTH

Y
Y

MINIMUM NECK WIDTH

=45_OHM_SE 10 MM=45_OHM_SE

=DEFAULTSTANDARD =DEFAULT

BOARD AREAS

NO_TYPE,BGA,P65BGA

MAXIMUM NECK LENGTH

10 MM

DIFFPAIR PRIMARY GAP

D

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

50_OHM_SE
50_OHM_SE

45_OHM_SE

40_OHM_SE

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

40_OHM_SE

LAYER

37_OHM_SE

TOP,BOTTOM

37_OHM_SE =STANDARD

C

27P4_OHM_SE

LAYER

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

* Y

ALLOW ROUTE
ON LAYER?

27P4_OHM_SE

LAYER

ALLOW ROUTE
ON LAYER?

72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ALLOW ROUTE
ON LAYER?

80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ALLOW ROUTE
ON LAYER?

85_OHM_DIFF

B

85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ALLOW ROUTE
ON LAYER?

90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

MINIMUM LINE WIDTH

Y

0.095 MM 0.095 MM

0.066 MM

MINIMUM LINE WIDTH

Y

Y

0.116 MM 0.116 MM

MINIMUM LINE WIDTH

0.145 MM 0.095 MM

Y* =STANDARD=STANDARD

MINIMUM LINE WIDTH

Y

0.165 MM

MINIMUM NECK WIDTH

0.066 MM

MINIMUM NECK WIDTH

0.083 MM0.083 MM

MINIMUM NECK WIDTH

0.090 MM0.102 MM

MINIMUM NECK WIDTH

0.095 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD45_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.090 MM0.118 MM

MINIMUM LINE WIDTH

Y
Y* =STANDARD

0.265 MM

0.186 MM

MINIMUM LINE WIDTH

=STANDARD
Y
Y
Y

N* =STANDARD
Y

0.105 MM 0.105 MM

0.146 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.092 MM
Y
Y

0.125 MM

MINIMUM LINE WIDTH

N =STANDARD*
Y
Y
Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.095 MM

0.1 MM

MINIMUM NECK WIDTH

0.105 MM0.105 MM

0.146 MM

MINIMUM NECK WIDTH

0.092 MM

0.092 MM0.092 MM

0.125 MM

MINIMUM NECK WIDTH

=STANDARD=STANDARD

0.080 MM0.080 MM

0.080 MM0.080 MM

0.105 MM0.105 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=STANDARD=STANDARD =STANDARD
Y
Y
Y

0.078 MM 0.078 MM

0.078 MM0.078 MM

0.101 MM0.101 MM

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM0 MM

=DEFAULT

=DEFAULT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARDY

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* Y =STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* N =STANDARD

0.120 MM

0.120 MM

0.120 MM

0.120 MM

0.120 MM 0.120 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

0.120 MM0.120 MM

0.120 MM

0.155 MM

0.120 MM

0.155 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

0.120 MM 0.120 MM

0.120 MM0.120 MM

0.125 MM

0.125 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD* N

0.200 MM 0.200 MM

0.200 MM

0.200 MM

0.180 MM 0.180 MM

ALLEGRO
VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

* *

**

SPACING_RULE_SET

DEFAULT
STANDARD
BGA_P1MM
BGA_P2MM

P072_SPACE
P075_SPACE

LAYER

LINE-TO-LINE SPACING

*
*
*
*
*
*

Stackup-Defined Spacing Rules

Note: Outer dielectric is 0.058 mm nominal,
Inner dielectric is 0.053 mm nominal.

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

PHYSICAL_RULE_SET

P65BGA

P65_BGA

SPACING_RULE_SET

1:1_SPACING

SPACING_RULE_SET

1x_DIELECTRIC
1x_DIELECTRIC
1X_DIELECTRIC

LAYER

* Y

NET_PHYSICAL_TYPE

*

LAYER

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

ALLOW ROUTE
ON LAYER?

AREA_TYPE

AREA_TYPE

BGA

P65BGA

0.1 MM

=DEFAULT

0.1 MM

0.2 MM

0.071 MM

0.075 MM

0.1 MM

0.058 MM

0.053 MM

0.101 MM

P65_BGA

SPACING_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

P072_SPACE

TABLE_SPACING_ASSIGNMENT_ITEM

P075_SPACE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

0.071MM0.071MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

C

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.126MM0.075MM

B

A

1:1_DIFFPAIR

LAYER

* Y

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

=STANDARD

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

6 3

SYNC_MASTER=SIDLE_J45

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

110 OF 119

SHEET

88 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU Signal Constraints

LAYER

CPU_50S

CPU_45S

CPU_27P4S

CPU_85D

ALLOW ROUTE
ON LAYER?

*

*

=45_OHM_SE =45_OHM_SE

*

=27P4_OHM_SE

*

=85_OHM_DIFF

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING_RULE_SET

D

CPU_AGTL

CPU_8MIL

CPU_COMP

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

LAYER

LINE-TO-LINE SPACING

*

* ?

* ?

SOURCE: IVB PLATFORM DG , Tables 205-207

Spacing Rule Sets

LINE-TO-LINE SPACING

SPACING_RULE_SET

DMI_2SAME

DMI_TXRX

DMICLK2N2S

DMICLK2S2N

DMICLK2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

DMI_N2S
DMI_S2N DMI_N2S
CLK_DMI
CLK_DMI
CLK_DMI

LAYER

* ?

=3X_DIELECTRIC
=6X_DIELECTRIC

*
* ?

=6X_DIELECTRIC

* ?

=3X_DIELECTRIC

* ?

=4X_DIELECTRIC

=SAMEDMI_*

DMI_S2N

DMI_N2S
DMI_S2N

*

=STANDARD

8 MIL

20 MIL

=2:1_SPACING

25 MIL

AREA_TYPE

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=27P4_OHM_SE

SPACING_RULE_SET

*
*
*

DMICLK2N2S

*

DMICLK2S2N

*
*

DMICLK2OTHER

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

WEIGHT

?

DMI_2SAME

DMI_TXRX
DMI_TXRX

MINIMUM NECK WIDTH

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MAXIMUM NECK LENGTH

=50_OHM_SE

=45_OHM_SE=45_OHM_SE

=27P4_OHM_SE=27P4_OHM_SE

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

LAYER

CPU_AGTL

CPU_VID

CPU_VREF

SPACING_RULE_SET

DMI_2SAME

DMI_TXRX

TOP,BOTTOM

LAYER

TOP,BOTTOM
TOP,BOTTOM

DMICLK2N2S TOP,BOTTOM

DMICLK2S2N

DMICLK2OTHER

TOP,BOTTOM
TOP,BOTTOM

LINE-TO-LINE SPACING

=2x_DIELECTRIC

* ?

LINE-TO-LINE SPACING

=4X_DIELECTRIC
=10X_DIELECTRIC
=10X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

PEG - SSD & TBT

PEG_80D

SPACING_RULE_SET

PEG_2SAME

PEG_TXRX

PEG_2OTHER

PEG_2CLK

SPACING_RULE_SET

PEG3_2SAME

PEG3_TXRX

B

PEG3_2OTHER

PEG3_2CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PEG_* =SAME

PEG_R2D

PEG_* PEG_2OTHER
PEG_* CLK_*

LAYER

*

LAYER

*

*

*

*

LAYER

*

*

*

*

PEG_D2R

ALLOW ROUTE
ON LAYER?

=80_OHM_DIFF

LINE-TO-LINE SPACING

LINE-TO-LINE SPACING

*

=3X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

=7X_DIELECTRIC

=4X_DIELECTRIC

=8X_DIELECTRIC

=5X_DIELECTRIC

=8X_DIELECTRIC

AREA_TYPE

*
*
*
*

MINIMUM LINE WIDTH

=80_OHM_DIFF

WEIGHT

?
?
?

WEIGHT

?
?
?
?

SPACING_RULE_SET

PEG_2SAME

PEG_TXRX

PEG_2CLK

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=80_OHM_DIFF =80_OHM_DIFF

SPACING_RULE_SET

PEG_2SAME

PEG_TXRX

PEG_2OTHER TOP,BOTTOM

PEG_2CLK

SPACING_RULE_SET

PEG3_2SAME

PEG3_TXRX

PEG3_2OTHER

PEG3_2CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

PEG3_*

PEG3_*
PEG3_*

LINE-TO-LINE SPACING

LINE-TO-LINE SPACING

=SAME

PEG3_D2RPEG3_R2D

*

CLK_*

DIGITAL VIDEO SIGNAL CONSTRAINTS

LAYER

DP_85D

SPACING_RULE_SET

DP_2SAME

DP_2OTHER

HDMICLK_2CLK

HDMICLK_2DP

HDMICLK_2OTHER

A

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LAYER

DISPLAYPORT
DISPLAYPORT

HDMI_CLK
HDMI_CLK

DISPLAYPORT

HDMI_CLK

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

*

*

=SAME

*

CLK_*

* *

=3x_DIELECTRIC

=4x_DIELECTRIC

=7x_DIELECTRIC

=4x_DIELECTRIC

=7x_DIELECTRIC

AREA_TYPE

*
*
*
*

MINIMUM LINE WIDTH

WEIGHT

?*

?

?*

?*

?

SPACING_RULE_SET

DP_2SAME

DP_2OTHER

HDMICLK_2CLK

HDMICLK_2DP

HDMICLK_2OTHER

MINIMUM NECK WIDTH

=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

DP_2SAME

DP_2OTHER

HDMICLK_2CLK

HDMICLK_2DP

HDMICLK_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

LINE-TO-LINE SPACING

DIFFPAIR PRIMARY GAP

=STANDARD

=STANDARD

7 MIL

0.457 MM

12 MIL

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF

=4X_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

=12X_DIELECTRIC

=8X_DIELECTRIC

=12X_DIELECTRIC

AREA_TYPE

*
*
*
*

DIFFPAIR PRIMARY GAP

=4x_DIELECTRIC

=6x_DIELECTRIC

=10x_DIELECTRIC

=6x_DIELECTRIC

=10x_DIELECTRIC

6 3

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD

=85_OHM_DIFF=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

PEG3_2SAME

PEG3_TXRX

PEG3_2OTHER

PEG3_2CLK

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

7 MIL

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N CPU_85D DMI_S2N
DMI_N2S CPU_85D
DMI_N2S CPU_85D
FDI_INT CPU_50S
FDI_CSYNC
DMI_CLK CPU_85D CLK_DMI

I125

DMI_CLK

I126

CPU_CLK135_PLL CPU_85D

I151

CPU_EDP_COMP

I132

CPU_PEG_COMP CPU_COMP

I130

CPU_CFG CPU_45S

I133

XDP_CLK_PCH
XDP_CLK_PCH

XDP_TDO CPU_ITPCPU_45S
XDP_TMS CPU_ITPCPU_45S
XDP_TCK CPU_ITPCPU_45S
XDP_TRST_L

XDP_BPM_L
XDP_BDRESET_L

I134

XDP_PRDY_L

I135

XDP_PREQ_L

I136

CPU_CATERR_L CPU_AGTL
CPU_PECI
CPU_PROCHOT_L

CPU_PWRGD

I150

PM_THRMTRIP_L
PM_MEM_PWRGD
PM_SYNC

CPU_VID CPU_VIDCPU_45S
CPU_VID CPU_VID
CPU_VID CPU_45S CPU_VID
CPU_VCCSENSE
CPU_VCCSENSE CPU_VCCSENSE
CPU_MEM_VREF

I140

CPU_MEM_VREF

I141

CPU_MEM_VREF

I255

CPU_MEM_VREF

I256

CPU_MEM_VREF

I254

CPU_MEM_VREF

I253

PCIE_D2R_GPU PEG3_D2R

I265

PCIE_D2R_GPU

I266
I267

PCIE_D2R_GPU

I268

I264
I263

I261

I262

PCIE_D2R_SSD

I252

I251

PCIE_R2D_SSD PEG3_R2D

I250

PCIE_R2D_SSD PEG3_R2D

I249
I248

I247

PEG_D2R_TBT

I153

PEG_D2R_TBT

I152
I154

I155

PEG_R2D_TBT

I156

PEG_R2D_TBT

I158

I157
I159

NET_TYPE

PHYSICAL

CPU_85D DMI_S2NDMI_S2N

CPU_50S

CPU_85D CLK_DMI
CPU_85DCPU_CLK135_PLL

CPU_85DCPU_CLK135_PLL
CPU_85DCPU_CLK135_PLL
CPU_27P4S
CPU_27P4S

CLK_PCIE_85D

CPU_45S
CPU_45SXDP_BPM

CPU_45S CPU_ITP

CPU_45S

CPU_45S

CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_27P4S

CPU_45S

CPU_27P4S
CPU_27P4S

PEG_80D
PEG_80D
PEG_80D
PEG_80D
PEG_80D
PEG_80D
PEG_80D
PEG_80D

CPU_85D
CPU_85D
CPU_85D
CPU_85D
CPU_85D
CPU_85D

CPU_85D
CPU_85D PEG_D2R
CPU_85D PEG_D2R
CPU_85D PEG_D2R
CPU_85D

CPU_85D PEG_R2D
CPU_85D PEG_R2D

SPACING

DMI_N2S
DMI_N2S
CPU_AGTL
CPU_AGTL

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_COMP

CPU_ITP

CLK_PCIECLK_PCIE_85D
CLK_PCIE
CPU_ITPXDP_TDI CPU_45S

CPU_ITP
CPU_ITP
CPU_ITPCPU_45S
CPU_ITPCPU_45S

CPU_ITPCPU_45S

CPU_VIDCPU_45S
CPU_AGTL

CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_COMPCPU_SM_RCOMP

CPU_VCCSENSE

MEM_12MIL
MEM_12MIL
MEM_PWR
CPU_VREF
MEM_PWR
MEM_PWR

PEG3_D2R
PEG3_D2RPCIE_D2R_GPU
PEG3_D2R
PEG3_R2DPCIE_R2D_GPU
PEG3_R2DPCIE_R2D_GPU
PEG3_R2DPCIE_R2D_GPU
PEG3_R2DPCIE_R2D_GPU

PEG3_D2R
PEG3_D2RPCIE_D2R_SSD

PEG3_R2D
PEG3_R2D

PEG_D2R

PEG_R2D
PEG_R2DCPU_85D

DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_INT
FDI_CSYNC
DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N
CPU_CLK135M_DPLLREF_N
CPU_CLK135M_DPLLREF_P
CPU_CLK135M_DPLLSS_N
CPU_CLK135M_DPLLSS_P
CPU_EDP_RCOMP
CPU_PEG_RCOMP
CPU_CFG<19..0>

NC_ITPXDP_CLK100MP
NC_ITPXDP_CLK100MN
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPUPCH_TRST_L
XDP_BPM_L<3..0>
XDP_BPM_L<7..4>
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_L

CPU_PWRGD

PM_THRMTRIP_L
PM_MEM_PWRGD

PM_SYNC
CPU_SM_RCOMP<2..0>

CPU_VIDSOUT
CPU_VIDSCLK

CPU_VIDALERT_L
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA
PP0V75_S3_MEM_VREFCA

PEG_D2R_C_P<7..0>
PEG_D2R_C_N<7..0>
PEG_D2R_P<7..0>
PEG_D2R_N<7..0>
PEG_R2D_C_P<7..0>
PEG_R2D_C_N<7..0>
PEG_R2D_P<7..0>
PEG_R2D_N<7..0>

PCIE_SSD_D2R_P<3..0>
PCIE_SSD_D2R_N<3..0>
PCIE_SSD_R2D_C_P<3..0>
PCIE_SSD_R2D_C_N<3..0>
PCIE_SSD_R2D_P<3..0>
PCIE_SSD_R2D_N<3..0>

PCIE_TBT_D2R_P<3..0>
PCIE_TBT_D2R_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
PCIE_TBT_D2R_C_N<3..0>
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>

5

12 87

5

12 87

5

12 87

5

12 87

5

12

5

12

6

11

6

11

6

11

6

11

6

11

6

11

5

5

6

18 86

11 87

11 87

6

18 86

6

18 86

6

18 86

6

18 86

6

18 86

6

18

6

18

6

18 19

6

18 86

6

18 86

6

40

6

14 41

6

40 41 58

6

14 18

6

14 41

6

12 21

6

12

6

8

58

8

58

8

58

8

58

9

58

7

22

7

22

22 23 24 85 92

22 25 26 85

22 23 24 25 26 85 89 92

22 23 24 25 26 85 89 92

68 70

68 70

70 85

70 85

68 70 85

68 70 85

70

70

5

34 85

5

34 85

5

34 85

5

34 85

34

34

5

28 85

5

28 85

28 87

28 87

28 87

28 87

5

28 85

5

28 85

DP AUX NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

DP_IG_AUX

I257

DP_IG_AUX

I258

DP_IG_AUX

I259

DP_IG_AUX

I260

PHYSICAL

DP_85D

DP_85D

DP_85D
DP_85D

DP / HDMI NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

DP_TBT_ML0

I235

DP_TBT_ML0

I236

I237
I238

DP_TBT_ML1

I239

DP_TBT_ML1

I240
I241

I242

TBTSNK_AUXCH

I223

TBTSNK_AUXCH

I224
I228

I229

TBTSNK_AUXCH

I227

TBTSNK_AUXCH

I226

I225
I230

PHYSICAL

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NET_TYPE

SPACING

DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_AUX_CH_N

DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>
DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>

DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N

NET_TYPE

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

SPACING

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

CPU Constraints

Apple Inc.

R

12 83 85

12 83 85

12 83 85

12 83 85

28 76 97

28 76 97

28 97

28 97

28 76 97

28 76 97

28 97

28 97

28 97

28 97

28 83 97

28 83 97

28 97

28 97

28 83 97

28 83 97

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

111 OF 119

SHEET

89 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

SATA Interface Constraints

LAYER

SATA_85D

SATA_37SE

SATA_45SE

SPACING_RULE_SET

SATA_2SAME

SATA_TXRX

SATA_2OTHER

SATA_RCOMP

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SATA_*

SATA_R2D

SATA_*

LAYER

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

*

*

*

=37_OHM_SE

=45_OHM_SE

LINE-TO-LINE SPACING

* ?

* ?

* ?

* ?

=SAME

SATA_D2R

*

=3X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

=6X_DIELECTRIC

AREA_TYPE

*
*
*

MINIMUM LINE WIDTH

=37_OHM_SE

SPACING_RULE_SET

SATA_2SAME

SATA_TXRX

SATA_2OTHER

USB 2.0 Interface Constraints

C

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB *

USB_RBIAS

BT_WAKE

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

*

*

=85_OHM_DIFF

LINE-TO-LINE SPACING

* ?

*

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF

=4X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

USB 3.0 INTERFACE CONSTRAINTS

USB3_85D

SPACING_RULE_SET

USB3_2SAME

USB3_TXRX

USB3_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

USB3_*

USB3_*

*

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

LAYER

LAYER

*

*

*

=SAME USB3_2SAME

USB3_D2RUSB3_R2D

=3X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

AREA_TYPE

*
*
**

MINIMUM LINE WIDTH

SPACING_RULE_SET

USB3_TXRX

USB3_2OTHER

System Clock Signal Constraints

LAYER

ALLOW ROUTE
ON LAYER?

CLK_SLOW_45S

CLK_25M_45S

*
*

LINE-TO-LINE SPACING

=4x_DIELECTRIC

SPACING_RULE_SET

LAYER

CLK_SLOW

CLK_25M =5x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

WEIGHT

WEIGHT

MINIMUM NECK WIDTH

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

=37_OHM_SE =37_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=45_OHM_SE

SPACING_RULE_SET

SATA_2SAME TOP,BOTTOM

SATA_TXRX

SATA_2OTHER

SATA_RCOMP

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=STANDARD=STANDARD

=85_OHM_DIFF

SPACING_RULE_SET

USB

USB_RBIAS

MINIMUM NECK WIDTH

=85_OHM_DIFF

SPACING_RULE_SET

USB3_2SAME

USB3_TXRX

USB3_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE
=45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?

NOTE: Latest Intel DG calls out 50ohms SE for sys clocks

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

MAXIMUM NECK LENGTH

=85_OHM_DIFF=85_OHM_DIFF

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE=45_OHM_SE

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

=10X_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD

=85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=6X_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRICBT_WAKE

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD*
=STANDARD

WEIGHT

WEIGHT

WEIGHT

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

I272

I271
I299

I298

I300
I301

=85_OHM_DIFF=85_OHM_DIFF

=37_OHM_SE=37_OHM_SE

=45_OHM_SE=45_OHM_SE

=STANDARD

=85_OHM_DIFF=85_OHM_DIFF

=STANDARD*

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCH_SATA_RCOMP

I213

USB_EXTA
USB_EXTA
USB_EXTA

I245

USB_EXTA

I244

USB_EXTA

I248

USB_EXTA

I249

USB_NC
USB_NC
USB_NC

I238

USB_NC

I239
I273

I274

USB_SMC

USB_NC

I281

USB_NC

I282

USB_NC

I283

USB_NC

I284

USB_EXTB
USB_EXTB
USB_NC

I260

USB_NC

I259

USB_BT
USB_BT

USB_NC

I285

USB_NC

I286

USB_TPAD

I288

USB_TPAD

I287

I302
I303

PCH_USB_RBIASPCH_USB_RBIAS

USB3_EXTA_RX

I228

USB3_EXTA_RX

I231

I267
I265

USB3_EXTA_TX USB3_R2D

I230

USB3_EXTA_TX

I229
I268

I266

USB3_EXTB_RX USB3_D2R

I222
I223

I264

I262
I220

USB3_EXTB_TX

I221
I261

I263

NC_USB3 USB_85D

I290

NC_USB3

I291
I293

I292

NC_USB3 USB_85D

I295

NC_USB3

I294

I296
I297

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

NET_TYPE

PHYSICAL

SATA_85D SATA_R2D
SATA_85D SATA_R2D
SATA_85D SATA_D2R
SATA_85D SATA_D2R

SATA_45SE

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

USB_85D
USB_85D
USB_85D
USB_85D
CPU_45S

USB_85DUSB_SMC
USB_85D

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

SPACING

SATA_R2DSATA_85D
SATA_R2DSATA_85D
SATA_D2RSATA_85D
SATA_D2RSATA_85D

SATA_RCOMP

USB
USB
USB
USB
USB
USB

USB
USB
USB
USB
CPU_ITP
CPU_ITPCPU_45S
USB
USB

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

USB_RBIAS

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

USB_85D
USB_85D
USB_85D

USB_85D
USB_85D
USB_85D

USB3_D2R
USB3_D2R
USB3_D2R
USB3_D2R

USB3_R2D
USB3_R2D
USB3_R2D

USB3_D2RUSB3_EXTB_RX
USB3_D2R
USB3_D2R
USB3_R2DUSB3_EXTB_TX
USB3_R2D
USB3_R2D
USB3_R2D

USB3_D2R
USB3_D2R
USB3_R2D
USB3_R2D
USB3_D2R
USB3_D2R
USB3_R2D
USB3_R2D

NC_SATA_A_R2D_CP
NC_SATA_A_R2D_CN
NC_SATA_A_D2RP
NC_SATA_A_D2RN
NC_SATA_B_R2D_CP
NC_SATA_B_R2D_CN
NC_SATA_B_D2RP
NC_SATA_B_D2RN

PCH_SATA_RCOMP

USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_LT1_P
USB_LT1_N

NC_USB_EXTCP
NC_USB_EXTCN
NC_USB_SDP
NC_USB_SDN
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
NC_USB_SMCP
NC_USB_SMCN

NC_USB_6P
NC_USB_6N
NC_USB_7P
NC_USB_7N
USB_EXTB_P
USB_EXTB_N
NC_USB_EXTDP
NC_USB_EXTDN
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
NC_USB_IRP
NC_USB_IRN
USB_TPAD_P
USB_TPAD_N
USB_TPAD_R_P
USB_TPAD_R_N

PCH_USB_RBIAS

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_D2R_C_P
USB3_EXTA_D2R_C_N
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTB_D2R_C_P
USB3_EXTB_D2R_C_N
USB3_EXTB_R2D_P
USB3_EXTB_R2D_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_C_N

NC_USB3_EXTC_D2RP
NC_USB3_EXTC_D2RN
NC_USB3_EXTC_R2D_CP
NC_USB3_EXTC_R2D_CN
NC_USB3_EXTD_D2RP
NC_USB3_EXTD_D2RN
NC_USB3_EXTD_R2D_CP
NC_USB3_EXTD_R2D_CN

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11 87

11

13 37

13 37

37

37

37

37

13 87

13 87

13 87

13 87

37 40 41

37 40 41

87

87

13 87

13 87

13 87

13 87

13 81 86

13 81 86

13 87

13 87

13 33

13 33

33 86

33 86

13 87

13 87

13 38 86

13 38 86

13

13 37

13 37

37

37

13 37

13 37

13 81 86

13 81 86

81 86

81 86

13 81

13 81

13 87

13 87

13 87

13 87

13 87

13 87

13 87

13 87

D

C

B

A

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

I256

SYSCLK_CLK25M_SB

I255
I254

SYSCLK_CLK25M_CAM

I253

SYSCLK_CLK25M_TBT

I251

I250

NET_TYPE

PHYSICAL

CLK_SLOW_45S CLK_SLOW

CLK_25M_45S
CLK_25M_45S
CLK_25M_45S

CLK_25M_45S
CLK_25M_45S

SPACING

CLK_25M
CLK_25M
CLK_25M

CLK_25M
CLK_25M

SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB

SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R

11 19

11 19

11

19 36

19 28

28

6 3

SYNC_MASTER=SIDLE_J45

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

112 OF 119

SHEET

90 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_45S

CLK_LPC_45S

SPACING_RULE_SET

LPC

CLK_LPC

D

SMBus Interface Constraints

SMB_45S

SPACING_RULE_SET

SMB

LAYER

LAYER

LAYER

HD Audio Interface Constraints

LAYER

HDA_45S

SPACING_RULE_SET

HDA

LAYER

SPI Interface Constraints

LAYER

SPI_45S

C

SPACING_RULE_SET

SPI

SPI3X

LAYER

PCH Single Net Constraints

LAYER

PCH_45S

SPACING_RULE_SET

PCH_SE

LAYER

PCI-Express

PCIE_85D

SPACING_RULE_SET

B

PCIE_2SAME

PCIE_TXRX

PCIE_2OTHER

PCIE_2CLK

PCIECLK_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_*

PCIE_R2D

PCIE_*
PCIE_*

CLK_PCIE

ALLOW ROUTE
ON LAYER?

*

=45_OHM_SE =45_OHM_SE

*

LINE-TO-LINE SPACING

* ?

*

ALLOW ROUTE
ON LAYER?

*

=45_OHM_SE

LINE-TO-LINE SPACING

*

*

*

*

*

*

*

LAYER

*

*

LAYER

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

=3x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=45_OHM_SE =45_OHM_SE =45_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

=85_OHM_DIFF

LINE-TO-LINE SPACING

* ?

*

*

*

*

=2X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

=7X_DIELECTRIC

=7X_DIELECTRIC

=SAME

PCIE_D2R

CLK_*

* *

A

MINIMUM LINE WIDTH

=45_OHM_SE

=45_OHM_SE =45_OHM_SE

6 MIL

8 MIL

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

=45_OHM_SE=45_OHM_SE

8 MIL

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

=85_OHM_DIFF

=85_OHM_DIFFCLK_PCIE_85D =85_OHM_DIFF

AREA_TYPE

*
*
**
*

SPACING_RULE_SET

PCIE_2SAME

PCIE_TXRX

PCIE_2OTHER

PCIE_2CLK

PCIECLK_2OTHER

WEIGHT

WEIGHT

WEIGHT

WEIGHT

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

SPACING_RULE_SET

PCH_SE

MINIMUM NECK WIDTH

=85_OHM_DIFF =85_OHM_DIFF

SPACING_RULE_SET

PCIE_2SAME

PCIE_TXRX

PCIE_2OTHER

PCIE_2CLK

PCIECLK_2OTHER

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

TOP,BOTTOM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=45_OHM_SE=45_OHM_SE

=45_OHM_SE

LAYER

TOP,BOTTOM

TOP,BOTTOM?=10X_DIELECTRIC

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

LINE-TO-LINE SPACING

=85_OHM_DIFF

LAYER

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=3x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

=85_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

=6X_DIELECTRIC

=10X_DIELECTRIC

=10X_DIELECTRIC

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD
LPC_FRAME_L

SMBUS_PCH_CLK
SMBUS_PCH_DATA SMB_45S
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_PCH_1_CLK
SMBUS_PCH_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L
HDA_SDIN0
HDA_SDIN0_R
HDA_SDOUT

USB3_SD_R2D
USB3_SD_R2D
USB3_SD_D2R
USB3_SD_D2R

PCIE_AP_R2D
PCIE_AP_R2D

I304

I303

PCIE_AP_D2R
PCIE_AP_D2R

I275

I276

PCIE_CAMERA_R2D

I325

PCIE_CAMERA_R2D

I326

I327
I328

PCIE_CAMERA_D2R

I329

PCIE_CAMERA_D2R

I330
I331

I332

PCH_LPC_CLK0

I293

PCIE_CLK100M CLK_PCIE

I298

PCIE_CLK100M CLK_PCIE

I258

PCIE_CLK100M CLK_PCIE

I260

PCIE_CLK100M_PCH

I253

PCIE_CLK100M_PCH

I254

PCIE_CLK100M_TBT

I262

PCIE_CLK100M_TBT

I261

PCIE_CLK100M_DOT

I255

PCIE_CLK100M_DOT

I257

PCIE_CLK100M_SATA

I256

PCIE_CLK100M_SATA

I259

PCIE_CLK100M_ENET
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_AP

I300
I299

PCIE_CLK100M_S2
PCIE_CLK100M_S2

I333

I334

PCIE_CLK100M_FW

I281

I282

PCIE_CLK100M_GPU

I397
I396

PHYSICAL

LPC_45S
LPC_45S

SMB_45S

SMB_45S
SMB_45S
SMB_45S
SMB_45S

HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S

USB3_85D USB3_D2R
USB3_85D USB3_D2R

PCIE_85D PCIE_R2D

PCIE_85D PCIE_R2D

PCIE_85D
PCIE_85D
PCIE_85D PCIE_D2R
PCIE_85D PCIE_D2R

PCIE_85D PCIE_R2D
PCIE_85D PCIE_R2D
PCIE_85D PCIE_R2D
PCIE_85D PCIE_R2D
PCIE_85D
PCIE_85D
PCIE_85D PCIE_D2R
PCIE_85D PCIE_D2R

CLK_LPC_45S
CLK_LPC_45S

CLK_LPC_45S
CPU_45S
CPU_45S
CPU_45S
CLK_PCIE_85D
CLK_PCIE_85D
CLK_PCIE_85D
CLK_PCIE_85D
CLK_PCIE_85D
CLK_PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D CLK_PCIE

CLK_PCIE_85D CLK_PCIE
CLK_PCIE_85D CLK_PCIE

CLK_PCIE_85D
CLK_PCIE_85D CLK_PCIE

CLK_PCIE_85D CLK_PCIE

NET_TYPE

SPACING

LPC
LPC

SMB
SMB
SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

USB3_R2DUSB3_85D
USB3_R2DUSB3_85D

PCIE_R2DPCIE_85D

PCIE_R2DPCIE_85D
PCIE_R2DPCIE_85D

PCIE_R2DPCIE_85D
PCIE_D2R
PCIE_D2R

PCIE_D2R
PCIE_D2R

CLK_LPC
CLK_LPC

CLK_LPC

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIEPCIE_85D
CLK_PCIE
CLK_PCIE
CLK_PCIE

CLK_PCIECLK_PCIE_85D
CLK_PCIECLK_PCIE_85D

CLK_PCIE

CLK_PCIECLK_PCIE_85D

LPC_AD<3..0>
LPC_FRAME_L

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
CS4208_HDA_SDOUT0_R
HDA_SDOUT
HDA_SDOUT_R

USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
USB3_SD_D2R_P
USB3_SD_D2R_N

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N

PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC

NC_LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIIN
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIOUT
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N

PCIE_CLK100M_SD_P

PCIE_CLK100M_SD_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_CAMERA_P

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PEG_CLK100M_P
PEG_CLK100M_N

13 40 82

13 40 82

13 18 43 81 85 86

13 18 43 81 85 86

13 43

13 43

13 43

13 43

11 52

11

11 52

11

11

11 52

11 52

52

11 52

11 19

WEIGHT

?

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

?
?
?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

=STANDARD

=STANDARD=STANDARD

=STANDARD

=STANDARD

=STANDARD

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

6 3

13 20 81 86

13 20 81 86

13 20 81 86

13 20 81 86

33 86

33 86

13 33

13 33

13 20 33

13 20 33

86

86

35 36

35 36

13 36

13 36

13 20 36

13 20 36

35 36

35 36

11 19

19 40

11 87

11 19

11

11 19

11

11

11 28

11 28

11

11

11

11

11 33

11 33

33 86

33 86

11 36

11 36

35 36

35 36

11 34

11 34

11 70 85

11 70 85

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

PCH_PM_NET

I313

PCH_PM_NET

I314

PCH_PM_NET

I315

PCH_PM_NET

I316

PCH_PM_NET

I308

PCH_PM_NET

I307

PCH_PM_NET

I318

PCH_PM_NET

I317

PCH_PM_NET

I320

PCH_PM_NET

I319

PCH_PM_NET

I321

PCH_PM_NET

I322

PCH_PCIE_WAKE

I323

PCH_PM_NET

I324

I386
I369

I368

SPI_MLB

I383

SPI_MLB

I382

I395

SPI_MLB

I364

SPI_MLB

I363

SPI_MLB

I392

SPI_MLB

I391

I390
I359

I358

SPI_MLB SPI_45S

I387
I381

I380

SPI_MLB

I354

SPI_MLB

I353

SPI_MLB SPI_45S

I377

SPI_MLB

I376

SPI_MLB_IO2

I375

SPI_MLB_IO2

I374

SPI_MLB_IO2

I371

SPI_MLB_IO3

I373

SPI_MLB_IO3

I372

SPI_MLB_IO3

I370

SPI_TPAD

I344

SPI_TPAD_CS

I343

SPI_TPAD

I342

SPI_TPAD

I341

NET_TYPE

PHYSICAL

PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S

SPI_45SSPI_MLB
SPI_45SSPI_MLB
SPI_45SSPI_MLB
SPI_45S
SPI_45S

SPI_45SSPI_MLB
SPI_45S
SPI_45S
SPI_45S
SPI_45S

SPI_45SSPI_MLB
SPI_45SSPI_MLB
SPI_45SSPI_MLB

SPI_45SSPI_MLB

SPI_45SSPI_MLB
SPI_45S
SPI_45S

SPI_45S

SPI_45S
SPI_45S
SPI_45S

SPI_45S
SPI_45S
SPI_45S

SPI_45S
SPI_45S
SPI_45S
SPI_45S

SYNC_MASTER=CLEAN_X305_PEG

PAGE TITLE

SPACING

PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE
PCH_SE

SPI3X
SPI
SPI
SPI3X
SPI3X

SPI3X
SPI
SPI
SPI3X
SPI3X

SPI3X
SPI
SPI
SPI3X
SPI3X

SPI3X
SPI
SPI
SPI3X
SPI3X

SPI3X
SPI3X
SPI3X

SPI3X
SPI3X
SPI3X

SPI
SPI
SPI
SPI

PCH_INTRUDER_L
PCH_INTVRMEN_L
PCH_DSWVRMEN
PCH_SRTCRST_L
PM_RSMRST_L
PM_SYSRST_L
PM_PCH_PWROK
PM_PCH_PWROK
PM_DSW_PWRGD
PM_PCH_SYS_PWROK
PM_PWRBTN_L
PM_THRMTRIP_L_R
PCIE_WAKE_L
PCH_RCIN_L

SPI_ALT_CLK
SPI_CLK
SPI_CLK_R
SPI_MLB_CLK
SPI_SMC_CLK

SPI_ALT_CS_L
SPI_CS0_L
SPI_CS0_R_L
SPI_MLB_CS_L
SPI_SMC_CS_L

SPI_ALT_IO1_MISO
SPI_MISO
SPI_MISO_R
SPI_MLB_IO1_MISO
SPI_SMC_MISO

SPI_ALT_IO0_MOSI
SPI_MOSI
SPI_MOSI_R
SPI_MLB_IO0_MOSI
SPI_SMC_MOSI

SPI_IO<2>
SPI_MLB_IO2_WP_L
SPI_ALT_IO2_WP_L

SPI_IO<3>
SPI_MLB_IO3_HOLD_L
SPI_ALT_IO3_HOLD_L

TPAD_SPI_SCLK
TPAD_SPI_CS_L
TPAD_SPI_MISO
TPAD_SPI_MOSI

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

11

11

12

11

12 67 86

12 19 40 86

12 19 86 91

12 19 86 91

12 40 86

12 18 19 40 86

12 18 40

14 41 42

12 33 35 86

14

50

13 50

50

40 50

50

13 50

50

40 50

13 50

50

50

40 50

50

13 50

50

40 50

13 50

50

13 50

50

38 85

38 85

38 85

38 85

SYNC_DATE=02/18/2014

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

113 OF 119

SHEET

91 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Memory Bus Constraints

MEM_37S
MEM_40S
MEM_72D
MEM_45S
MEM_85D

LAYER

ALLOW ROUTE
ON LAYER?

=37_OHM_SE =37_OHM_SE

* =STANDARD

=40_OHM_SE

=72_OHM_DIFF*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

*

=85_OHM_DIFF

MINIMUM LINE WIDTH

=72_OHM_DIFF

=45_OHM_SE

=85_OHM_DIFF

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=37_OHM_SE=37_OHM_SE
=40_OHM_SE=40_OHM_SE=40_OHM_SE

=72_OHM_DIFF =72_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* =STANDARD
=STANDARD

=72_OHM_DIFF =72_OHM_DIFF

=STANDARD=STANDARD*

=85_OHM_DIFF=85_OHM_DIFF

D

Spacing Rule Sets

LINE-TO-LINE SPACING

SPACING_RULE_SET

MEM_DATA2SELF

MEM_DQS2OWNDATA

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

MEM_CLK2CLK

MEM_2OTHERMEM

MEM_2PWR
MEM_2GND

MEM_2OTHER

LAYER

=2x_DIELECTRIC

*

=2x_DIELECTRIC
=2x_DIELECTRIC

* ?

=2x_DIELECTRIC

* ?

=2x_DIELECTRIC
=4x_DIELECTRIC

*

=4x_DIELECTRIC
=2x_DIELECTRIC

*

=2x_DIELECTRIC

* ?

=6x_DIELECTRIC

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

MEM_DATA2SELF

MEM_DQS2OWNDATA

MEM_CMD2CMD

MEM_CMD2CTRL

MEM_CTRL2CTRL

MEM_CLK2CLK

MEM_2OTHERMEM

MEM_2PWR
MEM_2GND

MEM_2OTHER

LAYER

TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

LINE-TO-LINE SPACING

=5x_DIELECTRIC
=5x_DIELECTRIC
=5x_DIELECTRIC
=5x_DIELECTRIC
=5x_DIELECTRIC
=8x_DIELECTRIC
=8x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC

=10x_DIELECTRIC

WEIGHT

?
?
?
?
?
?
?
?
?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

C

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DATA_*

MEM_*_DQS_*

MEM_CMD

MEM_CTRL

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DATA_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CMD MEM_CMD
MEM_CMD

B

MEM_CTRL MEM_CTRL

MEM_* MEM_*

*
*
*

=SAME

MEM_CTRL

MEM_CLKMEM_CLK

AREA_TYPE

**
**
*
*
*

AREA_TYPE

*

AREA_TYPE

*
*
*
*
*

SPACING_RULE_SET

SPACING_RULE_SET

SPACING_RULE_SET

MEM_CLK2CLK

MEM_2OTHERMEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA2SELF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD2CMD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD2CTRL

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL2CTRL

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DQS_0*MEM_A_DATA_0
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_7
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_2
MEM_B_DQS_3
MEM_B_DQS_4
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_7

MEM_A_DATA_1
MEM_A_DATA_2
MEM_A_DATA_3
MEM_A_DATA_4
MEM_A_DATA_5
MEM_A_DATA_6
MEM_A_DATA_7
MEM_B_DATA_0
MEM_B_DATA_1
MEM_B_DATA_2
MEM_B_DATA_3
MEM_B_DATA_4
MEM_B_DATA_5
MEM_B_DATA_6
MEM_B_DATA_7

DDR3 (Memory Down):

DQ signals should be matched within 0.508mm of associated DQS pair
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

SOURCE: Double checked with Doc#486985 Chief River SFF Platform DG: Memory Down
SOURCE: Need to re-confirm CRW DG for memory down (Intel not yet provided)

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_PWR

MEM_*

A

AREA_TYPE

*
**

SPACING_RULE_SET

MEM_2PWR

DEFAULTMEM_PWR

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

SPACING_RULE_SET

MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA
MEM_DQS2OWNDATA

Memory to GND Spacing

MEM_2GND

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

MEM_*

AREA_TYPE

*

SPACING_RULE_SET

6 3

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK0
MEM_A_CLK0
MEM_A_CLK1

I130

MEM_A_CLK1

I129

MEM_A_CNTL0
MEM_A_CNTL1

I124

MEM_A_CNTL0

I125

MEM_A_CNTL1

I101

MEM_A_CNTL0

I126

MEM_A_CNTL1

I103

MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_DATA_0 MEM_A_DATA_0
MEM_A_DATA_1 MEM_A_DATA_1
MEM_A_DATA_2 MEM_A_DATA_2
MEM_A_DATA_3 MEM_A_DATA_3
MEM_A_DATA_4 MEM_A_DATA_4
MEM_A_DATA_5 MEM_A_DATA_5
MEM_A_DATA_6 MEM_A_DATA_6
MEM_A_DATA_7

I105

MEM_A_DQS0

I106

MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6

I117

MEM_A_DQS6

I118

MEM_A_DQS7

I116

MEM_A_DQS7

I119

MEM_B_CLK0
MEM_B_CLK0
MEM_B_CLK1

I127

MEM_B_CLK1

I128

MEM_B_CNTL0
MEM_B_CNTL1

I120

MEM_B_CNTL0

I121

MEM_B_CNTL1

I122

MEM_B_CNTL0

I123

MEM_B_CNTL1
MEM_B_CMD

I108

MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_DATA_0 MEM_B_DATA_0
MEM_B_DATA_1

MEM_B_DATA_3
MEM_B_DATA_4 MEM_B_DATA_4
MEM_B_DATA_5 MEM_B_DATA_5

MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6

I113

MEM_B_DQS6

I112

MEM_B_DQS7

I115

MEM_B_DQS7

I114

I110

I109
I111

NET_TYPE

PHYSICAL

MEM_CLKMEM_72D
MEM_CLKMEM_72D
MEM_CLKMEM_72D

MEM_CLKMEM_72D
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S MEM_CMD

MEM_40S
MEM_40S
MEM_40S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D

MEM_72D MEM_CLK
MEM_72D
MEM_72D MEM_CLK

MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S MEM_CMD
MEM_40S
MEM_40S
MEM_40S

MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CMDMEM_40S

MEM_CMD

MEM_CMD

MEM_CMD

MEM_A_DATA_7

MEM_A_DQS_0

MEM_A_DQS_0

MEM_A_DQS_1

MEM_A_DQS_1

MEM_A_DQS_2

MEM_A_DQS_2

MEM_A_DQS_3

MEM_A_DQS_3

MEM_A_DQS_4

MEM_A_DQS_4

MEM_A_DQS_5

MEM_A_DQS_5

MEM_A_DQS_6

MEM_A_DQS_6

MEM_A_DQS_7

MEM_A_DQS_7

MEM_CLK

MEM_CLKMEM_72D

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_CMD

MEM_CMD

MEM_CMD

MEM_CMDMEM_40S

MEM_B_DATA_1

MEM_B_DATA_2MEM_B_DATA_2

MEM_B_DATA_3

MEM_B_DATA_6MEM_B_DATA_6

MEM_B_DATA_7MEM_B_DATA_7

MEM_B_DQS_0

MEM_B_DQS_0

MEM_B_DQS_1

MEM_B_DQS_1

MEM_B_DQS_2

MEM_B_DQS_2

MEM_B_DQS_3

MEM_B_DQS_3

MEM_B_DQS_4

MEM_B_DQS_4

MEM_B_DQS_5

MEM_B_DQS_5

MEM_B_DQS_6

MEM_B_DQS_6

MEM_B_DQS_7

MEM_B_DQS_7

MEM_PWR

MEM_PWR

MEM_PWR

SPACING

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

7

23 27

7

23 27

7

24 27

7

24 27

7

23 27

7

24 27

7

23 27

7

24 27

7

23 27

7

24 27

7

23 24 27

7

23 24 27

7

23 24 27

7

23 24 27

7

23 24 27

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

23 24

7

25 27

7

25 27

7

26 27

7

26 27

7

25 27

7

26 27

7

25 27

7

26 27

7

25 27

7

26 27

7

25 26 27

7

25 26 27

7

25 26 27

7

25 26 27

7

25 26 27

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

7

25 26

22 23 24 85 89

22 23 24 25 26 85 89

22 23 24 25 26 27 45 84

SYNC_MASTER=SIDLE_J45

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

114 OF 119

SHEET

92 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_45S

SPACING_RULE_SET

TBT_SPI =2x_DIELECTRIC

D

Thunderbolt/DP Connector Signal Constraints

TBTDP_85D

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

TBT_DP Interface Constraints

TBTDP_85D

SPACING_RULE_SET

TBTDP_2SAME

TBTDP_TXRX

TBTDP_2OTHER

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE

LINE-TO-LINE SPACING

*

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

*

LINE-TO-LINE SPACING

*

* ?

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF

=3X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=85_OHM_DIFF

SPACING_RULE_SET

TBTDP_2SAME

TBTDP_2OTHER

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

TOP,BOTTOM

TOP,BOTTOMTBTDP_TXRX

TOP,BOTTOM

LAYER

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD*

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

WEIGHT

12

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF=85_OHM_DIFF*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=85_OHM_DIFF=85_OHM_DIFF

TBT_A_R2D

DP_A_LSX_ML DISPLAYPORT
DP_A_LSX_ML
DP_A_LSX_ML
DP_A_LSX_ML DISPLAYPORT
DP_A_LSX_ML DISPLAYPORT
DP_A_LSX_ML
DP_TBTPA_ML DISPLAYPORT

I308

DP_TBTPA_ML DISPLAYPORT

I310

DP_TBTPA_ML

I311

DP_TBTPA_ML

I309

TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R1

I312

TBT_A_D2R1

I313

TBT_A_D2R1

I314

TBT_A_D2R1

I315

TBT_A_D2R1
TBT_A_D2R1

TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH

NET_TYPE

PHYSICAL

TBTDP_85DTBT_A_R2D
TBTDP_85DTBT_A_R2D
TBTDP_85D TBTDP_R2D
TBTDP_85DTBT_A_R2D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D TBTDP_D2R
TBTDP_85D

TBTDP_85D TBTDP_D2R
TBTDP_85D TBTDP_D2R
TBTDP_85D TBTDP_D2R
TBTDP_85D
TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D

SPACING

TBTDP_R2D
TBTDP_R2D

TBTDP_R2D

DISPLAYPORT
DISPLAYPORT

DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

TBTDP_D2R
TBTDP_D2RTBTDP_85D
TBTDP_D2RTBTDP_85D

TBTDP_D2R
TBTDP_D2R
TBTDP_D2R

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>
DP_TBTPA_ML_P<1>
DP_TBTPA_ML_N<1>
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>
DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>
DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>
TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N

28 31

28 31

31

31

28 31

28 31

31

31

31

31

28 31

28 31

31

31

31

31

28 31

28 31

31

31

28 31 87

28 31 87

31

31

28 31

28 31

31

31

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

TBTDP_*

TBTDP_R2D TBTDP_D2R

TBTDP_*

B

=SAME

* *

AREA_TYPE

*
*

TBTDP_2SAME

TBTDP_TXRX

TBTDP_2OTHER

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

TBT_B_R2D

I316

TBT_B_R2D

I317

TBT_B_R2D

I318

TBT_B_R2D

I319

DP_B_LSX_ML

I321

DP_B_LSX_ML

I322

DP_B_LSX_ML

I320

DP_B_LSX_ML

I324

DP_B_LSX_ML

I325

DP_B_LSX_ML

I323

DP_TBTPB_ML

I327

DP_TBTPB_ML

I326

DP_TBTPB_ML

I328

DP_TBTPB_ML

I329

TBT_B_D2R0

I331

TBT_B_D2R0

I332

TBT_B_D2R0

I330

TBT_B_D2R0

I334

TBT_B_D2R1

I333

TBT_B_D2R1

I336

TBT_B_D2R1

I337

TBT_B_D2R1

I335

TBT_B_D2R1

I339

TBT_B_D2R1

I338

TBT_B_AUXCH

I341

TBT_B_AUXCH

I340

TBT_B_AUXCH

I342

TBT_B_AUXCH

I343

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

TBTDP_85D TBTDP_R2D
TBTDP_85D TBTDP_R2D
TBTDP_85D TBTDP_R2D
TBTDP_85D TBTDP_R2D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D TBTDP_D2R
TBTDP_85D TBTDP_D2R

TBTDP_85D TBTDP_D2R
TBTDP_85D TBTDP_D2R

DP_85D
DP_85D
DP_85D
DP_85D

PHYSICAL

DP_85D
DP_85D
DP_85D
DP_85D

TBT_SPI_45STBT_SPI_CLK
TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S

NET_TYPE

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBTDP_D2RTBTDP_85D
TBTDP_D2RTBTDP_85D

TBTDP_D2RTBTDP_85D
TBTDP_D2RTBTDP_85D

TBTDP_D2RTBTDP_85D
TBTDP_D2RTBTDP_85D

SPACING

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<1>
DP_TBTPB_ML_P<1>
DP_TBTPB_ML_N<1>
DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>
DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>
DP_TBTPB_ML_P<3>
DP_TBTPB_ML_N<3>

TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N

DP_TBTSRC_ML_C_P<3..0>
DP_TBTSRC_ML_C_N<3..0>
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

28 32

28 32

32

32

28 32

28 32

32

32

32

32

28 32

28 32

32

32

32

32

28 32

28 32

32

32

28 32

28 32

32

32

28 32

28 32

32

32

Only used on dual-port hosts.

Only used on hosts supporting Thunderbolt video-in

28

28

28

28

C

B

A

SYNC_MASTER=SIDLE_J45

PAGE TITLE

Thunderbolt Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

115 OF 119

SHEET

93 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

Camera Net Properties

ELECTRICAL_CONSTRAINT_SET

MIPI Interface Constraints

*

*

*

*

* *

CLK_MIPI

*

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

LAYER

D

MIPI_85D

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LAYER

MIPI_DATA
MIPI_DATA

CLK_MIPI

=4X_DIELECTRIC

=6X_DIELECTRIC

=7X_DIELECTRIC

AREA_TYPE

*
*

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

WEIGHT

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

TOP,BOTTOM

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=6X_DIELECTRIC

=8X_DIELECTRIC

=10X_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

Memory Bus Constraints

LAYER

S2_MEM_45S =45_OHM_SE
S2_MEM_85D

C

Spacing Rule Sets

SPACING_RULE_SET

LAYER

S2_DATA2SELF

S2_DQS2OWNDATA

S2_CMD2CMD

S2_CMD2CTRL

S2_CTRL2CTRL

S2_2OTHERMEM

S2MEM_2PWR
S2MEM_2GND

S2MEM_2OTHER

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

*
* =85_OHM_DIFF

LINE-TO-LINE SPACING

=2x_DIELECTRIC
=2x_DIELECTRIC
=2x_DIELECTRIC

* ?

=2x_DIELECTRIC
=2x_DIELECTRIC
=4x_DIELECTRIC

* ?

=2x_DIELECTRIC
=2x_DIELECTRIC

* ?

=6x_DIELECTRIC

MINIMUM LINE WIDTH

=45_OHM_SE

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=45_OHM_SE

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

?*
?*
?*

?*

?*
?*

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

S2_DATA2SELF

TABLE_SPACING_RULE_ITEM

S2_DQS2OWNDATA =4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

S2_CMD2CMD

TABLE_SPACING_RULE_ITEM

S2_CMD2CTRL

TABLE_SPACING_RULE_ITEM

S2_CTRL2CTRL

TABLE_SPACING_RULE_ITEM

S2_2OTHERMEM

TABLE_SPACING_RULE_ITEM

S2MEM_2PWR?TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

S2MEM_2GND TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

S2MEM_2OTHER

LAYER

TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=STANDARD

=85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=4x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC
=6x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC

=10x_DIELECTRIC

WEIGHT

?
?
?
?
?
?

?
?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D
S2_MEM_CLK S2_MEM_85D S2_MEM_CLK

S2_MEM_CNTL

I101

I102

S2_MEM_CMD

I103
I104

S2_MEM_CMD

S2_MEM_CMD S2_MEM_45S

S2_MEM_DQS0

I106

S2_MEM_DQS0

I108
I107

S2_MEM_DATA_0

I109

S2_MEM_DATA_1

I110

S2_MEM_A

I147

S2_MEM_DATA_0
S2_MEM_DATA_1

MIPI_DATA_S2

I127

MIPI_DATA_S2 MIPI_85D

I128

I129
I130

MIPI_CLK_S2

I134

MIPI_CLK_S2

I133

I132

I131

I145
I146

I148

I149

NET_TYPE

PHYSICAL

S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45SS2_MEM_CMD

S2_MEM_45SS2_MEM_CMD S2_MEM_CMD
S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S

S2_MEM_45S
S2_MEM_45S

MIPI_85D

MIPI_85D
MIPI_85D

MIPI_85D
MIPI_85D
MIPI_85D
MIPI_85D CLK_MIPI

SPACING

S2_MEM_CTRL
S2_MEM_CTRLS2_MEM_CNTL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CMDS2_MEM_45S
S2_MEM_CMDS2_MEM_CMD S2_MEM_45S
S2_MEM_CMD

S2_MEM_DQS0
S2_MEM_DQS0
S2_MEM_DQS1S2_MEM_DQS1
S2_MEM_DQS1S2_MEM_DQS1
S2_MEM_DATA0
S2_MEM_DATA1
S2_MEM_CMD

S2_MEM_DATA0
S2_MEM_DATA1

MIPI_DATA
MIPI_DATA
MIPI_DATA
MIPI_DATA

CLK_MIPI
CLK_MIPI
CLK_MIPI

S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_CKE
MEM_CAM_CS_L
MEM_CAM_ODT
MEM_CAM_CAS_L
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>
MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<0>
MEM_CAM_DQS_P<1>
MEM_CAM_DQS_N<1>
MEM_CAM_DM<0>
MEM_CAM_DM<1>
MEM_CAM_A<14..0>

MEM_CAM_DQ<7..0>
MEM_CAM_DQ<15..8>

MIPI_DATA_P
MIPI_DATA_N
MIPI_DATA_CONN_P
MIPI_DATA_CONN_N

MIPI_CLK_P
MIPI_CLK_N
MIPI_CLK_CONN_P
MIPI_CLK_CONN_N

PP1V35_CAM
PP0V675_CAM_VREF
PP0V675_MEM_CAM_VREFCA
PP0V675_MEM_CAM_VREFDQ

35 36

35 36

35 36

35 36

36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

35 36

36 86

36 86

35 36

35 36

36 86

36 86

35 36

35 36

36

36

D

C

Memory Bus Spacing Group Assignments

S2MEM_2OTHERS2_MEM_DATA*
S2MEM_2OTHER
S2MEM_2OTHER
S2MEM_2OTHER
S2MEM_2OTHER

S2_DATA2SELF

S2_CMD2CMD

S2_CMD2CTRL

S2_CTRL2CTRL

S2_2OTHERMEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_DQS1
S2_MEM_DQS0

S2_MEM_DATA1
S2_MEM_DATA0

AREA_TYPE

*
*

SPACING_RULE_SET

S2_DQS2OWNDATA
S2_DQS2OWNDATA

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_PWR

S2_MEM_*

S2_MEM_PWR

AREA_TYPE

SPACING_RULE_SET

*
**

NET_SPACING_TYPE1 NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

* *

S2_MEM_DQS*

S2_MEM_CMD

B

S2_MEM_CTRL

S2_MEM_CLK

S2_MEM_DATA*

S2_MEM_CMD
S2_MEM_CMD

* *
*

=SAME

S2_MEM_CMD

S2_MEM_CTRL

S2_MEM_CTRL S2_MEM_CTRL

S2_MEM_*S2_MEM_*

**
**

*
*
*
*
*
*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

S2MEM_2PWR

TABLE_SPACING_ASSIGNMENT_ITEM

DEFAULT

B

Memory to GND Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

S2_MEM_*

AREA_TYPE

SPACING_RULE_SET

*

A

6 3

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

S2MEM_2GND

SYNC_MASTER=SIDLE_J45

PAGE TITLE

Camera Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

116 OF 119

SHEET

94 OF 97

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL

D

SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

1TO1_DIFFPAIR
1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

C

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SPACING

SPACING

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_g3_SCL
SMBUS_SMC_5_G3_SDA
NC_SMBUS_SMC_3_SCL
NC_SMBUS_SMC_3_SDA

CHGR_CSI_P
CHGR_CSI_N

CHGR_CSO_P
CHGR_CSO_N

38 40 43 86

38 40 43 86

40 43 48

40 43 48

36 40 43 48 69 76 85 86

36 40 43 48 69 76 85 86

40 43 56 57 86

40 43 56 57 86

40 42

40 42

57

57

57

57

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=SIDLE_J45

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

117 OF 119

SHEET

95 OF 97

124578

8 7 6 5 4 3

12

*

*

*

*

*

*

*

*

*

*

*

*

*

LAYER

*
*
*
*
*

TOP

TOP

ISL9

*

LAYER

*

ALLOW ROUTE
ON LAYER?

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

LINE-TO-LINE SPACING

LINE-TO-LINE SPACING

ALLOW ROUTE
ON LAYER?

PHYSICAL_RULE_SET

1:1_DIFFPAIR

ALLOW ROUTE
ON LAYER?

LAYER

SENSE_1TO1_50S

THERM_1TO1_50S

DIFFPAIR

AUDIODIFF

THERM_1TO1_45S

SENSE_1TO1_45S

D

SPACING_RULE_SET

SENSE

THERM

AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

LAYER

LAYER

LAYER

C

MEM_40S 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_72D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_85D

CPU_27P4S

BOTTOM
USB3_85D
USB3_85D

ISL10

DP_85D

PCIE_85D

NET_PHYSICAL_TYPE

1TO1_DIFFPAIR

ISL10

AREA_TYPE

B

SENSE_GPUVR

AMD Net Properties

ELECTRICAL_CONSTRAINT_SET

I544

I545

I546
I547

I549

I548
I550

I551

I552
I553

I554
I555

I556

I557
I558

I559

I560

A

I561

I562

I563
I564

I565

I568
I569

I566

I567
I570

I571

SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S
SENSE_DIFFPAIR SENSE_1TO1_45S
SENSE_DIFFPAIR SENSE_1TO1_45S
SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_DIFFPAIR THERM_1TO1_45S

PHYSICAL

THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45SSENSE_DIFFPAIR
THERM_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR

THERM_1TO1_45S

=2X_DIELECTRIC

=2X_DIELECTRIC

=2X_DIELECTRIC

=STANDARD

0.20 MM

0.20 MM

Y

MINIMUM LINE WIDTH

=50_OHM_SE

=50_OHM_SE

=45_OHM_SE =45_OHM_SETHERM_45S_CPUVRISNS1

=45_OHM_SE =45_OHM_SE =45_OHM_SE

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MINIMUM LINE WIDTH

WEIGHT

WEIGHT

WEIGHT

1000

1000

MINIMUM NECK WIDTH

=50_OHM_SE

0.1 MM0.1 MM

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU_COMP GND_P2MM

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MINIMUM NECK WIDTH

0.09 MM

0.1 MM

0.23 MM 100 MIL

0.1 MM

0.075 MM

0.075 MM

0.075 MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

0.300 MM 0.200 MM 3.000 MM

NET_TYPE

SPACING

THERM
THERM
THERM

THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

SENSE
SENSE

SENSE
SENSE
SENSE

MINIMUM NECK WIDTH

GPUFB_CS_P
GPUFB_CS_N
GPU_TDIODE_P
GPU_TDIODE_N
GPU_VDDCISENSE_P
GPU_VDDCISENSE_N

GPU_VDDCI_SENSE_XW_P
GPU_VDDCI_SENSE_XW_N

GPUVCORE_SENSE_P
GPUVCORE_SENSE_N

ISNS_PP0V95_S0GPU_R_P
ISNS_PP0V95_S0GPU_R_N

VSNS_GPU_0V95_XW_P

VSNS_GPU_0V95_XW_N
VDDCIS0_CS_R_P
VDDCIS0_CS_R_N

GPUFB_CS_R_P
GPUFB_CS_R_N

VSNS_GPU_VDDC_P
VSNS_GPU_VDDC_N
VSNS_GPU_VDDI_P
VSNS_GPU_VDDI_N

ISNS_1V8_GPU_R_P

ISNS_1V8_GPU_R_N
ISNS_1V8_GPU_P
ISNS_1V8_GPU_N

VSNS_GPU_FB_XW_P

VSNS_GPU_FB_XW_N

MAXIMUM NECK LENGTH

CLK_PCIE

GND

GND

SB_POWER

USB

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=50_OHM_SE

=50_OHM_SE=50_OHM_SE

=1:1_DIFFPAIR

10 MM

=45_OHM_SE

GND

GND

100 MIL0.09 MM
100 MILMEM_37S 0.09 MM
100 MILMEM_85D 0.09 MM

10 MM

500 MIL

500 MIL

SB_POWERCLK_PCIE

47 73

47 73

48 76

48 76

80

80

79

79

47

47

73

73

47

47

47

47

71 79 85

71 79

71 80 85

71 80

73

73

GND

PCIE_*

SATA_*

GNDUSB

SATA_*

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

0.1 MM

0.2 MM

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

AREA_TYPE

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

SPACING_RULE_SET

*

*

GND_P2MM

AREA_TYPE

0.400 MM 0.200 MM

SPACING_RULE_SET

*

*

*

*

*

*

*

6 3

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR

=1:1_DIFFPAIR

0.1 MM

0.2 MM

=1:1_DIFFPAIR

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

GND_P2MM

GND_P2MM

GND_P2MM

GND_P2MM

PWR_P2MM

PWR_P2MM

PWR_P2MMSB_POWER

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.090 MM

0.090 MM

0.090 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

X425G Specific Net Properties X425G Specific Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR

I426

SENSE_DIFFPAIR

I425
I421

I423

SENSE_DIFFPAIR
SENSE_DIFFPAIR

I422

SENSE_DIFFPAIR

I424

SENSE_DIFFPAIR

SENSE_DIFFPAIR

SENSE_DIFFPAIR

I419

I420

SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_45S
SENSE_DIFFPAIR

I533

SENSE_DIFFPAIR

I532

I523

I521

SENSE_DIFFPAIR

I522
I520

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SENSE_DIFFPAIR SENSE_1TO1_45S
SENSE_DIFFPAIR SENSE_1TO1_45S

I514
I515

SENSE_DIFFPAIR

SENSE_DIFFPAIR THERM_1TO1_45S

I510

SENSE_DIFFPAIR THERM_1TO1_45S

I511

SENSE_DIFFPAIR

I530

SENSE_DIFFPAIR

I531

SENSE_DIFFPAIR

I528

SENSE_DIFFPAIR

I529

SENSE_DIFFPAIR

I527

SENSE_DIFFPAIR

I526

SENSE_DIFFPAIR THERM_1TO1_45S

I432

SENSE_DIFFPAIR

I436

SENSE_DIFFPAIR THERM_1TO1_45S

I498

SENSE_DIFFPAIR THERM_1TO1_45S

I499

SENSE_DIFFPAIR

I502

SENSE_DIFFPAIR

I503

AUDIO_DIFFPAIR

I405

AUDIO_DIFFPAIR

I406

I407
I408

I446

I445
I447

I448

SENSE_DIFFPAIR THERM_1TO1_45S

I449

I450

SENSE_DIFFPAIR

I451

I452

SENSE_DIFFPAIR THERM_1TO1_45S

I453

I454

AUDIO_DIFFPAIR

I455

I456

AUDIO_DIFFPAIR

I457

I458

SENSE_DIFFPAIR

I534

SENSE_DIFFPAIR SENSE_1TO1_45S

I535

SENSE_DIFFPAIR SENSE_1TO1_45S

I536

SENSE_DIFFPAIR

I537

SENSE_DIFFPAIR

I539

SENSE_DIFFPAIR

I538

SENSE_DIFFPAIR

I541

SENSE_DIFFPAIR SENSE_1TO1_45S

I540

SENSE_DIFFPAIR

I543

SENSE_DIFFPAIR THERM_1TO1_45S

I542

THERM_45S_CPUVRISNS1
THERM_45S_CPUVRISNS1
THERM_45S_CPUVRISNS1
THERM_45S_CPUVRISNS1

THERM_45S_CPUVRISNS1
THERM_45S_CPUVRISNS1

NET_TYPE

PHYSICAL

THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45SSENSE_DIFFPAIR
THERM_1TO1_45S
THERM_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45SSENSE_DIFFPAIR
SENSE_1TO1_45S

SENSE_1TO1_45S
SENSE_1TO1_45S

THERM_1TO1_45S

THERM_1TO1_45S
THERM_1TO1_45S

AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
THERM_1TO1_45SSENSE_DIFFPAIR
THERM_1TO1_45S
THERM_1TO1_45SSENSE_DIFFPAIR
THERM_1TO1_45S

THERM_1TO1_45S

THERM_1TO1_45S
THERM_1TO1_45S

THERM_1TO1_45S

AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF

SENSE_1TO1_45S

SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S

THERM_1TO1_45S

SPACING

ISNS_CPUDDR_P

THERM

ISNS_CPUDDR_N

THERM

ISNS_CPU_DDR_R_P

THERM

ISNS_CPU_DDR_R_N

THERM

CPUTHMSNS_D2_P

THERM

CPUTHMSNS_D2_N

THERM

ISNS_LCD_PANEL_P

SENSE

ISNS_LCD_PANEL_N

SENSE

DDR3THMSNS_D1_P

THERM

DDR3THMSNS_D1_N

THERM

FINTHMSNS_D_P

THERM

FINTHMSNS_D_N

THERM

ISNS_1V35_MEM_P

SENSE

ISNS_1V35_MEM_N

SENSE

ISNS_1V35_MEM_R_P

SENSE

ISNS_1V35_MEM_R_N

SENSE

ISNS_AIRPORT_P

SENSE

ISNS_AIRPORT_N

SENSE

ISNS_AIRPORT_R_P

SENSE

ISNS_AIRPORT_R_N

SENSE

ISNS_LCDBKLT_N

SENSE

ISNS_LCDBKLT_P

SENSE

ISNS_LCD_PANEL_N

SENSE

ISNS_LCD_PANEL_P

SENSE

ISNS_PCH_R_P

SENSE

ISNS_PCH_R_N

SENSE

ISNS_TPAD_P

SENSE

ISNS_TPAD_N

SENSE

ISNS_HS_OTHER5V_P

SENSE

ISNS_HS_OTHER5V_N

SENSE

ISNS_HS_OTHER3V3_P

SENSE

ISNS_HS_OTHER3V3_N

SENSE

ISNS_HS_COMPUTING_P

SENSE

ISNS_HS_COMPUTING_N

SENSE

CPUVR_ISNS_P

SENSE

CPUVR_ISNS_N

SENSE

P1V05_GPU_PEX_IOVDD_SNS_P

THERM

P1V05_GPU_PEX_IOVDD_SNS_N

THERM

DIFFERENTIAL_PAIR

THERM

CPUVR_ISNS1
CPUVR_ISNS1

THERM
THERM

CPUVR_ISNS2

THERM

CPUVR_ISNS2

THERM

CPUVR_ISNS3

THERM

CPUVR_ISNS3

CPUVR_ISUM_R_P

THERM

CPUVR_ISUM_R_N

THERM

GFXIMVP_ISNS1_P

THERM

GFXIMVP_ISNS1_N

THERM

GFXIMVP_ISNS1_P

THERM

GFXIMVP_ISNS1_N

THERM

ISNS_TBT_N

AUDIO

ISNS_TBT_P

AUDIO

ISNS_TBT_R_N

AUDIO

ISNS_TBT_R_P

AUDIO

ISNS_SSD_P

THERM

ISNS_SSD_N

THERM

ISNS_SSD_R_P

THERM

ISNS_SSD_R_N

THERM

P1V05S0_CS_P

THERM

P1V05S0_CS_N

THERM

DIFFERENTIAL_PAIR

THERM

P1V05S0_SENSE

THERM

P1V05S0_SENSE

TBT_THERMDP

THERM

TBT_THERMDN

THERM

CHGR_CSI_R_P

AUDIO

CHGR_CSI_R_N

AUDIO

CHGR_CSO_R_P

AUDIO

CHGR_CSO_R_N

AUDIO

GFXIMVP_ISNS2_P

SENSE

GFXIMVP_ISNS2_N

SENSE

ISNS_HS_GPU_P

SENSE

ISNS_HS_GPU_N

SENSE

ISNS_PP0V95_S0GPU_P

SENSE

ISNS_PP0V95_S0GPU_N

SENSE

VDDCIS0_CS_P

SENSE

VDDCIS0_CS_N

SENSE

GPUTHMSNS_D_P

THERM

GPUTHMSNS_D_N

THERM

CPUVR_ISNS1_P
CPUVR_ISNS1_N
CPUVR_ISNS2_P
CPUVR_ISNS2_N
CPUVR_ISNS3_P
CPUVR_ISNS3_N

P1V05S0_SENSE_P
P1V05S0_SENSE_N

46 66

46 66

46

46

48

48

46 69 96

46 69 96

48

48

45

45

45

45

46

46

63

63

46 69 96

46 69 96

45

45

45

45

44

44

44

44

44

44

45

45

45 59

45 59

45 59

45 59

45 59

45 59

45

45

79 96

79 96

79 96

79 96

45

45

45

45

45

45

45

45

45 62

45 62

28 48

48

57

57

57

57

79

79

47

47

47 73

47 73

47 80

47 80

48

48

I361
I362

I459

I440

I441
I442

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

I461

I462
I460

I463

AUDIO_DIFFPAIR

I358

AUDIO_DIFFPAIR

I357

AUDIO_DIFFPAIR

I360

AUDIO_DIFFPAIR

I359

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

I480

AUDIO_DIFFPAIR

I481

AUDIO_DIFFPAIR

I482

AUDIO_DIFFPAIR

I483

AUDIO_DIFFPAIR

I484

I485
I486

I487

I489
I488

I490

I491

AUDIO_DIFFPAIR

I494

AUDIO_DIFFPAIR

I495

AUDIO_DIFFPAIR

I493

AUDIO_DIFFPAIR

I492

62

62

PHYSICAL

AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF

NET_TYPE

SPACING

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SB_POWER
SB_POWER
SB_POWER

GND

SYNC_MASTER=SIDLE_J45

PAGE TITLE

AUD_SPKRAMP_RSUBIN_P
AUD_SPKRAMP_RSUBIN_N
AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N
RSUBIN_P
RSUBIN_N
LSUBIN_P
LSUBIN_N

AUD_LO2_R_P

AUD_LO2_R_N

AUD_LO2_L_P

AUD_LO2_L_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_N

SPKRAMP_RIN_P

SPKRAMP_RIN_N

SPKRAMP_LIN_P

SPKRAMP_LIN_N

SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N
SPKRCONN_SR_OUT_P
SPKRCONN_SR_OUT_N
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
AUD_MIC_IN1_R_P
AUD_MIC_IN1_R_N
CODEC_HS_MIC_P
CODEC_HS_MIC_N
AUD_MIC_IN1_L_P
AUD_MIC_IN1_L_N
AUD_HS_MIC_P
AUD_HS_MIC_N
HS_MIC_P
HS_MIC_N
AUD_CONN_HS_MIC_P
AUD_CONN_HS_MIC_N
AUD_LO3_R_P
AUD_LO3_R_N
AUD_LO3_L_P
AUD_LO3_L_N

PP3V3_S5
PP3V3_S0
PP1V35_S3RS0_CPUDDR

GND

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

53

53

53

53

53

53

53

53

51 53

51 53

51 53

51 53

53

53

53

53

53

53

53

53

53 55 86

53 55 86

53 55 86

53 55 86

53 55 86

53 55 86

53 55 86

53 55 86

51

51

54 55

54 55

51 54

51 54

51 53

51 53

51 53

51 53

66 67 82 84 85 86
12 14 15 17 18 19 21 31 32 33

66 67 68 69 82 83 84 86
11 12 13 14 15 17 19 20 29 34
43 44 45 46 47 48 49 51 52 55

6 8

10 21 66 67 84

61 64

SYNC_DATE=12/10/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

118 OF 119

SHEET

96 OF 97

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

GDDR5 Frame Buffer Signal Constraints

LAYER

GDDR5_45R50SE

GDDR5_80D

SPACING_RULE_SET

D

GDDR5_CLK
GDDR5_CMD

GDDR5_DATA

GDDR5_EDC

GDDR5_CMD spacing can be relaxed to 2x per AMD recommendation for x32_4.5G config.

Breakout Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GDDR5_*

SPACING_RULE_SET

GDDR5_BGA

ALLOW ROUTE
ON LAYER?

*

=50_OHM_SE

* =STANDARD=STANDARD

=45_OHM_SE

*

=80_OHM_DIFF

LINE-TO-LINE SPACING

LAYER

*

=5x_DIELECTRIC

*

=3x_DIELECTRIC

*

=3x_DIELECTRIC

*

=7x_DIELECTRIC

*

LINE-TO-LINE SPACING

LAYER

*

=1.3x_DIELECTRIC

MINIMUM LINE WIDTH

AREA_TYPE

BGA

=50_OHM_SE

=80_OHM_DIFF

WEIGHT

SPACING_RULE_SET

GDDR5_BGA

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=50_OHM_SE
=45_OHM_SEGDDR5_45SE =45_OHM_SE=45_OHM_SE

=80_OHM_DIFF

C

MAXIMUM NECK LENGTH

12.7 MM

=80_OHM_DIFF

SPACING_RULE_SET

GDDR5_CLK
GDDR5_CMD

LAYER

TOP,BOTTOM
TOP,BOTTOM

GDDR5_DATA?TOP,BOTTOM

GDDR5_EDC

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=STANDARD

=80_OHM_DIFF

LINE-TO-LINE SPACING

=5x_DIELECTRIC
=4x_DIELECTRIC
=5x_DIELECTRIC
=7x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

GDDR5 FB A Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

FB_A0_CLK

I453

FB_A0_CLK

I454

I452

FB_A1_CLK

I451

FB_A0_CMD

I450

FB_A1_CMD

I448

FB_A0_CMD GDDR5_CMD

I449

FB_A1_CMD GDDR5_CMD

I447

FB_A0_CMD GDDR5_CMD

I446

FB_A1_CMD

I445

FB_A0_CMD GDDR5_CMD

I444

I442

FB_A0_CMD

I443

FB_A1_CMD

I440
I441

FB_A1_CMD

I439

FB_A0_CMD

I437

FB_A1_CMD GDDR5_CMD

I438

FB_A0_EDC0

I435

I436
I402

FB_A0_EDC3

I400

FB_A1_EDC0

I401
I398

I399

FB_A1_EDC3

I397

FB_A0_DBI_L0

I395

FB_A0_DBI_L1

I396

FB_A0_DBI_L2

I394

FB_A0_DBI_L3

I392

FB_A1_DBI_L0

I393

FB_A1_DBI_L1

I390

FB_A1_DBI_L2

I391

FB_A1_DBI_L3

I389

FB_A0_WCLK0

I388

FB_A0_WCLK0

I387

FB_A0_WCLK1

I385

FB_A0_WCLK1

I386

FB_A1_WCLK0

I384

FB_A1_WCLK0

I383

FB_A1_WCLK1

I382

FB_A1_WCLK1

I380

FB_A0_DQ_BYTE0

I381

FB_A0_DQ_BYTE1

I379

FB_A0_DQ_BYTE2

I378

FB_A0_DQ_BYTE3

I377

FB_A1_DQ_BYTE0

I376

FB_A1_DQ_BYTE1

I375

FB_A1_DQ_BYTE2

I374

FB_A1_DQ_BYTE3

I373

FB_A0_CMD_R

I372

FB_A1_CMD_R

I371

GDDR5_80D GDDR5_CLK
GDDR5_80D GDDR5_CLKFB_A1_CLK

GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SEFB_A0_EDC1
GDDR5_45SEFB_A0_EDC2
GDDR5_45SE
GDDR5_45SE
GDDR5_45SEFB_A1_EDC1
GDDR5_45SEFB_A1_EDC2
GDDR5_45SE
GDDR5_45SE GDDR5_DATA
GDDR5_45SE
GDDR5_45SE GDDR5_DATA
GDDR5_45SE
GDDR5_45SE

GDDR5_45SE GDDR5_DATA
GDDR5_80D

GDDR5_80D
GDDR5_80D
GDDR5_80D

GDDR5_80D

GDDR5_45SE
GDDR5_45SE
GDDR5_45SE

GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE

PHYSICAL

NET_TYPE

SPACING

GDDR5_CLKGDDR5_80D

GDDR5_CLKGDDR5_80D
GDDR5_CMD
GDDR5_CMD

GDDR5_CMD

GDDR5_CMDFB_A1_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMDFB_A0_CMD
GDDR5_CMD
GDDR5_CMD

GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC

GDDR5_DATA

GDDR5_DATA
GDDR5_DATA
GDDR5_DATAGDDR5_45SE
GDDR5_DATAGDDR5_45SE

GDDR5_CLK
GDDR5_CLKGDDR5_80D
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLKGDDR5_80D
GDDR5_CLK
GDDR5_CLKGDDR5_80D
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATAGDDR5_45SE
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD

FB_A0_CLK_P
FB_A0_CLK_N
FB_A1_CLK_P
FB_A1_CLK_N
FB_A0_A<8..0>
FB_A1_A<8..0>
FB_A0_ABI_L
FB_A1_ABI_L
FB_A0_RAS_L
FB_A1_RAS_L
FB_A0_CAS_L
FB_A1_CAS_L
FB_A0_WE_L
FB_A1_WE_L
FB_A0_CKE_L
FB_A1_CKE_L
FB_A0_CS_L
FB_A1_CS_L
FB_A0_EDC<0>
FB_A0_EDC<1>
FB_A0_EDC<2>
FB_A0_EDC<3>
FB_A1_EDC<0>
FB_A1_EDC<1>
FB_A1_EDC<2>
FB_A1_EDC<3>
FB_A0_DBI_L<0>
FB_A0_DBI_L<1>
FB_A0_DBI_L<2>
FB_A0_DBI_L<3>
FB_A1_DBI_L<0>
FB_A1_DBI_L<1>
FB_A1_DBI_L<2>
FB_A1_DBI_L<3>
FB_A0_WCLK_P<0>
FB_A0_WCLK_N<0>
FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>
FB_A1_WCLK_P<0>
FB_A1_WCLK_N<0>
FB_A1_WCLK_P<1>
FB_A1_WCLK_N<1>
FB_A0_DQ<7..0>
FB_A0_DQ<15..8>
FB_A0_DQ<23..16>
FB_A0_DQ<31..24>
FB_A1_DQ<7..0>
FB_A1_DQ<15..8>
FB_A1_DQ<23..16>
FB_A1_DQ<31..24>
FB_A0_RESET_L
FB_A1_RESET_L

GDDR5 FB B Net Properties

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

72 74

FB_B0_CLK GDDR5_CLKGDDR5_80D

I473

FB_B0_CLK GDDR5_CLKGDDR5_80D

I474

FB_B1_CLK GDDR5_CLKGDDR5_80D

I472

FB_B1_CLK GDDR5_CLKGDDR5_80D

I470

FB_B0_CMD GDDR5_CMD

I471

FB_B1_CMD GDDR5_CMD

I468

FB_B0_CMD GDDR5_CMD

I469

FB_B1_CMD

I467

FB_B0_CMD GDDR5_CMD

I466

FB_B1_CMD GDDR5_CMD

I465

FB_B0_CMD

I464

FB_B1_CMD GDDR5_CMD

I463

FB_B0_CMD

I462

FB_B1_CMD

I460

FB_B0_CMD

I461

FB_B1_CMD

I459

I457

FB_B1_CMD

I458

FB_B0_EDC0

I455

FB_B0_EDC1

I456

FB_B0_EDC2

I434

FB_B0_EDC3

I433

FB_B1_EDC0

I432

FB_B1_EDC1

I430

FB_B1_EDC2

I431

FB_B1_EDC3 GDDR5_45SE

I429

FB_B0_DBI_L0

I428

FB_B0_DBI_L1

I427

FB_B0_DBI_L2

I426

FB_B0_DBI_L3

I424

FB_B1_DBI_L0

I425

FB_B1_DBI_L1

I423

FB_B1_DBI_L2

I422

FB_B1_DBI_L3

I421

FB_B0_WCLK0

I420

FB_B0_WCLK0

I419

FB_B0_WCLK1

I418

FB_B0_WCLK1

I417

FB_B1_WCLK0

I416

FB_B1_WCLK0

I414

FB_B1_WCLK1

I415

FB_B1_WCLK1

I412

FB_B0_DQ_BYTE0

I413

FB_B0_DQ_BYTE1

I411

FB_B0_DQ_BYTE2

I410

FB_B0_DQ_BYTE3

I409

FB_B1_DQ_BYTE0

I408

FB_B1_DQ_BYTE1

I407

FB_B1_DQ_BYTE2

I406

FB_B1_DQ_BYTE3

I404

FB_B0_CMD_R

I405

FB_B1_CMD_R

I403

NET_TYPE

PHYSICAL

GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE

GDDR5_45SE

GDDR5_45SE GDDR5_DATA
GDDR5_45SE

GDDR5_45SE
GDDR5_45SE
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D

GDDR5_80D

GDDR5_45SE GDDR5_DATA
GDDR5_45SE GDDR5_DATA
GDDR5_45SE GDDR5_DATA
GDDR5_45SE
GDDR5_45SE

SPACING

GDDR5_CMD

GDDR5_CMD

GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMDFB_B0_CMD
GDDR5_CMD
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_DATAGDDR5_45SE
GDDR5_DATA
GDDR5_DATAGDDR5_45SE

GDDR5_DATA
GDDR5_DATAGDDR5_45SE
GDDR5_DATA
GDDR5_DATA
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLKGDDR5_80D
GDDR5_CLK
GDDR5_CLKGDDR5_80D
GDDR5_DATAGDDR5_45SE
GDDR5_DATAGDDR5_45SE
GDDR5_DATAGDDR5_45SE
GDDR5_DATAGDDR5_45SE
GDDR5_DATAGDDR5_45SE

GDDR5_CMD
GDDR5_CMD

FB_B0_CLK_P
FB_B0_CLK_N
FB_B1_CLK_P
FB_B1_CLK_N
FB_B0_A<8..0>
FB_B1_A<8..0>
FB_B0_ABI_L
FB_B1_ABI_L
FB_B0_RAS_L
FB_B1_RAS_L
FB_B0_CAS_L
FB_B1_CAS_L
FB_B0_WE_L
FB_B1_WE_L
FB_B0_CKE_L
FB_B1_CKE_L
FB_B0_CS_L
FB_B1_CS_L
FB_B0_EDC<0>
FB_B0_EDC<1>
FB_B0_EDC<2>
FB_B0_EDC<3>
FB_B1_EDC<0>
FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<3>
FB_B0_DBI_L<0>
FB_B0_DBI_L<1>
FB_B0_DBI_L<2>
FB_B0_DBI_L<3>
FB_B1_DBI_L<0>
FB_B1_DBI_L<1>
FB_B1_DBI_L<2>
FB_B1_DBI_L<3>
FB_B0_WCLK_P<0>
FB_B0_WCLK_N<0>
FB_B0_WCLK_P<1>
FB_B0_WCLK_N<1>
FB_B1_WCLK_P<0>
FB_B1_WCLK_N<0>
FB_B1_WCLK_P<1>
FB_B1_WCLK_N<1>
FB_B0_DQ<7..0>
FB_B0_DQ<15..8>
FB_B0_DQ<23..16>
FB_B0_DQ<31..24>
FB_B1_DQ<7..0>
FB_B1_DQ<15..8>
FB_B1_DQ<23..16>
FB_B1_DQ<31..24>
FB_B0_RESET_L
FB_B1_RESET_L

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

72 75

12

D

C

MUXGFX & DP AUX MUX NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

I486

I485
I484

B

A

I483

I482
I481

I480

I479
I477

I478

I349
I350

I345
I346

I517

I518
I519

I520

I338

I337

I339
I340

I502

I501

I500
I499

I497

I498
I496

I494
I495

I492

I493
I491

I489

I490
I488

I487

DP_INT_ML
DP_INT_ML

DP_INT_AUXCH
DP_INT_AUXCH

DP_INT_ML

DP_INT_ML

DP_EG_AUX
DP_EG_AUX
DP_EG_AUX
DP_EG_AUX

TBTSNK_AUXCH
TBTSNK_AUXCH

TBTSNK_AUXCH
TBTSNK_AUXCH

DP_TBT_ML
DP_TBT_ML

DP_TBT_ML1
DP_TBT_ML1

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D

DP_85D

DP_85D

DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

6 3

PHYSICAL

NET_TYPE

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

DISPLAYPORT

DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

SPACING

DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>
DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_AUX_P
DP_INT_AUX_N
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
DP_INT_EG_ML_P<3..0>
DP_INT_EG_ML_N<3..0>

DP_INT_IG_AUX_P
DP_INT_IG_AUX_N
DP_INT_IG_ML_P<3..0>
DP_INT_IG_ML_N<3..0>

DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>
DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>

69 82

69 82

69

69

69 86

69 86

69 82

69 82

69 86

69 86

76 77 82

76 77 82

76 82

76 82

5

82 85

5

82 85

5

82 85

5

82 85

76 77 83

76 77 83

76 77 83

76 77 83

28 89

28 89

28 83 89

28 83 89

28 89

28 89

28 83 89

28 83 89

28 89

28 89

28 76 89

28 76 89

28 89

28 89

28 76 89

28 76 89

Kepler Net Properties

ELECTRICAL_CONSTRAINT_SET

I514

I513

GPU_CLK_TEST

I515

GPU_CLK_TEST

I516

HDMI_DATA
HDMI_DATA

HDMI_CLK HDMI_CLK

PHYSICAL

1:1_DIFFPAIR
1:1_DIFFPAIR

1:1_DIFFPAIR

1:1_DIFFPAIR

DP_85D
DP_85D
DP_85D
DP_85D

NET_TYPE

SPACING

GPU_CLK_TEST_RC_P
GPU_CLK_TEST_RC_N
GPU_CLK_TEST_P
GPU_CLK_TEST_N

DISPLAYPORT
DISPLAYPORT
HDMI_CLKHDMI_CLK

HDMI_EG_DATA_P<2..0>
HDMI_EG_DATA_N<2..0>
HDMI_EG_CLK_P
HDMI_EG_CLK_N

SYNC_MASTER=J45G_AMD SYNC_DATE=07/01/2014

PAGE TITLE

GPU (AMD VENUS) Constraints

Apple Inc.

R

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