Apple MacBook Pro 15 A1707 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

SCHEM,MLB_BAFFIN,X363G

2 1

CK

ECNREV DESCRIPTION OF REVISION

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

APPD

DATE

2016-08-24000689728910 ENGINEERING RELEASED

D

1
2
3
4
5

1
2
3
4

5
6 6
7
8
9

7

8

9
10
11
12
13
14

11

12

13

14

MLB_BAFFIN
BOM Configuration
BOM Configuration
PD Parts
CPU DMI/PEG/FDI/RSVD
CPU Clock/Misc/JTAG/CFG
CPU DDR3 Interfaces
CPU Power
CPU Ground
CPU Decoupling 1 [10]
CPU Decoupling 2 [11]
PCH RTC/HDA/JTAG/SATA/CLK
PCH DMI/FDI/PM/GFX/PCI
PCH PCI-E/USB

J80_MLB

J80_MLB_BAFFIN_CLEAN

J80_MLB

X363_AGOTETI

J80_MLB

J80_MLB

J80_MLB

J80_MLB

J80_DTUZMAN_MLB_BAFFIN

X363_SEAN

X363_SAKKOC

J80_MLB

X363_SAKKOC

07/07/2015
12/02/2015
11/16/2015
01/21/2016
11/06/2015
11/06/2015
08/16/2015
08/17/2015
11/22/2015
02/01/2016
04/14/2016
11/06/2015
04/14/2016

61

65

66
63
64
65

69

70

71
66 72

7367
68
69
7010
71
72
73

74

76

78

79

80

81
74 82

AUDIO Speaker Amps & Conn
AUDIO JACK CONNECTOR62
DC-In & Battery Connectors
PBUS Supply & Battery Charger
CORE & SA IMVP IC
CORE IMVP POWER BLOCK
SA IMVP IC
GT & GTX IMVP POWER BLOCK
Power - 5V 3.3V Supply
PMIC-1 & Power Control
PMIC-1 1.2V 0.6V VCCIO
PMIC-1 1V 1.8V VCCPCH
PMIC-1 Aliases & TPs
Power FETs

X363_AUDIO

J80_MLB

J80_MLB

J80_MLB

J80_DTUZMAN_MLB_BAFFIN

J80_DTUZMAN_MLB_BAFFIN

J80_DTUZMAN_MLB_BAFFIN

J80_DTUZMAN_MLB_BAFFIN

J80_DTUZMAN_MLB_BAFFIN

J80_MLB

J80_MLB

X363_ZIFENGSHEN

J80_SILUCHEN_MLB_BAFFIN

J80_SAKKOC_MLB_BAFFIN

01/25/2016
11/06/2015
11/06/2015
11/06/2015
12/10/2015
09/03/2015
11/18/2015
09/03/2015
12/09/2015
12/08/2015
11/06/2015
04/14/2016
12/08/2015
12/11/2015

D

C

15
16
17
18
19
20
21
22
23
24
25
26
27

15

PCH GPIO/MISC/NCTF
16 PCH Power
17
18
19
20
22
23
24
25
26
27
28

PCH DECOUPLING

CPU/PCH Merged XDP

Chipset Support 1

Chipset Support 2

LPDDR3 VREF MARGINING

LPDDR3 DRAM Channel A (0-31)

LPDDR3 DRAM Channel A (32-63)

LPDDR3 DRAM Channel B (0-31)

LPDDR3 DRAM Channel B (32-63)

LPDDR3 DRAM Termination

USB-C HIGH SPEED 1

USB-C HIGH SPEED 22928

X363_SAKKOC

X363_SAKKOC

J80_MLB

X363_SAKKOC

X363_SAKKOC

X363_SAKKOC

J80_MLB

J80_MLB

J80_MLB

J80_MLB

J80_MLB

J80_MLB

J80_MLB

J80_MLB

04/29/2016
01/25/2016
11/06/2015
01/25/2016
04/29/2016
01/14/2016
11/06/2015
11/06/2015
11/06/2015
11/06/2015
11/06/2015
11/06/2015

11/06/2015

75
76
77
78
79

84
85
86
87

88
80 89
81
82
83
84
85
86

90

91

92

93

94

95

968711/06/2015
88

97

LCD Backlight Driver
eDP Display Connector
POLARIS_CONTROLLER
POLARIS POWER
POLARIS GND
Connector
TEMP SENSORS
NAND 1/2
NAND 2/2
POLARIS PMIC
SSD NAND VR
SSD SUPPORT
Lifeboat
Constraints

J80_DTUZMAN_MLB_BAFFIN

J80_ZIFENGSHEN_MLB_BAFFIN

X363_JSAMUELS

X363_JSAMUELS

X363_JSAMUELS

X363_JSAMUELS

J80_MLB

X363_JSAMUELS

X363_JSAMUELS

X363_JSAMUELS

X363_JSAMUELS

X363_ZIFENGSHEN

X363_BBABADI

Constraints

12/03/2015
12/03/2015
04/01/2016
05/18/2016
04/01/2016
04/01/2016
11/06/2015
08/09/2016
08/09/2016
08/09/2016
04/01/2016
04/15/2016
01/20/2016
05/18/2016

C

B

29
30
31
32
33
34
35
36
37
38
39
40
41
42

30
31
32
33
34
35
37
38
39
40
41
42
43
44

USB-C Support
USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR A
USB-C CONNECTOR B
TBT 5V REGULATOR
WIFI/BT: MODULE 1
WIFI/BT: MODULE 2
Camera/DFR 1
Camera/DFR 2
Camera/DFR 3
Berkelium - 1
Berkelium - 2
T208 Support

X363_AGOTETI

X362_GKOO

J80_MLB

X362_MLB

X362_MLB

J80_ZIFENGSHEN_MLB_BAFFIN

X363_SAKKOC

J80_MLB

X363_SAKKOC

X362_T208

X362_T208

X362_T208

X362_T208

X362_T208

08/08/2016
08/08/2016
11/06/2015
03/30/2016
03/29/2016
12/04/2015
04/29/2016
11/06/2015
04/29/2016
03/22/2016
04/25/2016
01/27/2016
03/15/2016
06/30/2016

89
90
91
92
93
94

98

99

100

101

102

103
95 104
96
97
98
99
100
101
102

105

106

107

108

109

110

111

eDP Mux
GPU PCC
BAFFIN PCI-E
Baffin CORE/FB POWER
Baffin FRAME BUFFER I/F
Baffin 1V05 GPU / 1V35 FB Power Supply
GDDR5 Frame Buffer A
GDDR5 Frame Buffer B
GFX IMVP VCore Regulator [106]
Baffin GPIOs,CLK & Straps
Baffin DP/GPIO
Baffin VSS & MISC
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2

dpmux

X363_SEAN

X363_SEAN

X363_SEAN

J80_SEAN

J80_DTUZMAN_MLB_BAFFIN

J80_SEAN

J80_SEAN

J80_DTUZMAN_MLB_BAFFIN

X363_SEAN

X363_SEAN

X363_SEAN

J80_MLB

J80_MLB

08/22/2015
01/27/2016
01/27/2016
02/01/2016
04/29/2015
12/08/2015
04/29/2015
04/29/2015
12/08/2015
01/28/2016
01/27/2016
01/27/2016
11/06/2015
11/06/2015

B

43
44
45
46
47
48
49
50
51
52
53
54
55
56

45
47
49
50
51
52
53
54
55
56
57
58
59
60

Connectors&ESD
External A USB3 Connector
MESA
SMC
SMC Shared Support
SMC Project Support
SMBus Connections
Power Sensors: High Side
Power Sensors: Load Side
Power Sensors: Extended
Power Sensors: Extended 2
Thermal Sensors
Sensor Extended 3
Fans

X363_SAMANTHA

J80_MLB

X362_P49

X363_ZIFENGSHEN

J80_ZIFENGSHEN_MLB_BAFFIN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

X363_ZIFENGSHEN

01/08/2016
08/26/2015
01/08/2016
04/14/2016
11/19/2015
04/14/2016
04/14/2016
04/14/2016
04/14/2016
04/14/2016
04/14/2016
04/14/2016
05/19/2016
04/14/2016

103
104
105
106

112

113

114

115
107 116
108
109
110
111
112
113
114
115
116

117

120

121

122

123

124

125

126

127

USB-C Support
USB-C PORT CONTROLLER A
USB-C PORT CONTROLLER B
USB-C CONNECTOR A
USB-C CONNECTOR B
TBT 5V REGULATOR
Power Aliases - 1
Power Aliases - 2
Signal Aliases
Memory Bit/Byte Swizzle
ICT & FCT 1
ICT & FCT 2
NC & No Test
Desense Caps

J80_AGOTETI_MLB_BAFFIN

J80_MLB

J80_MLB

X362_MLB

X362_MLB

J80_ZIFENGSHEN_MLB_BAFFIN

J80_MLB

X363_SAKKOC

X363_SAKKOC

J80_MLB

X363_SAKKOC

J80_BBABADI_MLB_BAFFIN

X363_BBABADI

X363_ZIFENGSHEN

12/07/2015
11/06/2015
11/06/2015
03/30/2016
03/29/2016
12/04/2015
08/16/2015
01/14/2016
01/13/2016
11/06/2015
04/14/2016
12/10/2015
01/26/2016
04/15/2016

A

DRAWING

TITLE=MLB_BAFFIN
ABBREV=ABBREV

LAST_MODIFIED=Wed Aug 24 09:57:44 2016

Schematic / PCB #'s

051-00647 1

820-00281 1

57
58
59
60

SCHEM,MLB-BAFFIN,X363G

PCBF,MLB-BAFFIN,X363G

61
62
63
64

SPI Debug Connector
HDA Bridge
AUDIO JACK CODEC
AUDIO Speaker Amps & Conn

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALSCH

CRITICALPCB

J80_MLB

X363_AUDIO

X363_AUDIO

X363_AUDIO

11/06/2015
01/11/2016
01/25/2016
01/25/2016

This is the PVT design

117
118
119
120

128

130

141

142

Desense Caps
Project Specific Constraints
639 BOM Configuration
639 BOM Configuration 2

LAST_MODIFICATION=Wed Aug 24 09:57:44 2016

3

DESENSE

X363_ZIFENGSHEN
J80_MLB
J80_MLB

05/18/2016
06/02/2016
07/23/2015
07/23/2015

DRAWING TITLE

SCHEM,MLB-BAFFIN,X363

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

1 OF 145

SHEET

1 OF 121

1245678

A

SIZEDRAWING NUMBER

D

345678

2 1

D

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00076 COMMON PARTS,MLB-BAFFIN,X363 X363_COMMON
985-00126

DEV,MLB-BAFFIN,X363

X363_DEVEL:PVT

985-00232 X363_DEVEL:PVTDEV,MLB-BAFFIN,PVT,X363

639 BOMs have been moved to the end of the schematic

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

X363 BOM Groups

BOM GROUP BOM OPTIONS

X363_COMMON
X363_COMMON1
X363_COMMON2
X363_COMMON3
X363_COMMON4

X363_PROGPARTS
X363_DEVEL:ENG
X363_DEVEL:DVT
X363_DEVEL:PVT

ENGISNS

ALTERNATE,COMMON,X363_COMMON1,X363_COMMON2,X363_COMMON3,X363_COMMON4,X363_PROGPARTS

SOC:HYNIX,SE:PROD,SKIP_5V3V3:AUDIBLE,DIPLEXER:MURATA,T208_PROG:REV5,BOARD_ID:17,VCCHDA:S0

XDP:YES,SAMCONN,SOC_BOOT:SPI,DPMUX_XTAL:NO,GPUCLK:OSC,BAFFIN,AP_TEMP,VCCPLLOC:S3,WIFI_SAK:NO

CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,OTHERRC:YES,DDRRC:YES,TBTRC:YES,TPADRC:YES,LID_FEATURE_ON
EDP:YES,CPUPEG:X8X4X4,TBTTHRM_SNS,GPUTHRM_SNS,S3_STATE:YES,GPU_ROM:YES,SVID_PU:CORE
BOOTROM_PROG:DVT,BT_PROG:DVT,WIFI_PROG:DVT,UPCROM_PROG:DVT,SMC_PROG:PVT,DPMUXMCU:PROG,PCC:NO

ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG,GPUROM:BLANK,PCC:YES

ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG

ALTERNATE,XDP_CONN,USBC_DBG

TBTISNS,LOADISNS,TPADISNS,DDRISNS,OTHERISNS

Module Parts

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

C

B

GPU Options

BOM GROUP BOM OPTIONS

2GB_MC_BAFFIN FB_2GB_MICRON,VRAM:GRP1
2GB_HY_BAFFIN FB_2GB_HYNIX,VRAM:GRP1
2GB_SM_BAFFIN FB_2GB_SAMSUNG,VRAM:GRP2
4GB_SM_BAFFIN FB_4GB_SAMSUNG,VRAM:GRP1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

337S00227 U05001 CRITICAL
337S00228 U0500
337S00229
998-04701

1
1 U0500
1 CRITICAL

1 CRITICAL337S00258

4

338S00254 CRITICAL2

1 U7000 CRITICAL353S01016
338S00221
338S00142

337S00330

1

1

337S00332 CRITICALUA000

1

998-04866

1 UA000998-04867

2677-04532 CRITICALJ5250,J5260

CPU,SKY,SR2FT,R1,PRQ,4/2,2.9,BGA1440

CPU,SKY,SR2FU,R1,PRQ,4/2,2.7,BGA1440

CPU,SKY,SR2FQ,R1,PRQ,4/2,2.6,BGA1440

INTERPOSER,INTEL,BGA1440,MM940989

IC,SKL PCH-H,SFF,SR2NH,PRQ,D1,BGA939

IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96

IC,TBT,ALPINE RIDGE DP,QT5S,QS,C1,BGA337

IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM

IC,PMU,P650839,7X7MM.BGA168

IC,CODEC,CLIFDEN,CS42L83A,B0,WLCSP49

IC,GPU,BAFFIN,ULA,A1,PS,BGA769

IC,GPU,BAFFIN,PROA,A1,PS,BGA769

IC,GPU,BAFFIN,LEA,A1,PS,BGA769

INTERPOSER,AMD,C988,BGA769,VDDC

SUBASSY (T&R) PCBA, AMR, INTERPOSER, X363

U0500

U1100

U3100,U3200,UB300,UB400

U2800,UB000

U63001

UA000

UA0001 CRITICALINTERPOSER,AMD,C989,BGA769,VDDCI/MVDD

CRITICAL
CRITICAL

CRITICAL353S00961

CRITICAL1 U7800
CRITICAL

CRITICALUA000
CRITICAL337S00331

CRITICAL

CPU_SKL:2.9
CPU_SKL:2.7
CPU_SKL:2.6

CPU_SKL:SOCKET

BAFFIN_ULA

BAFFIN_PROA

BAFFIN_LEA

STARDUST:VDDCI_MVDD

STARDUST:VDDC

Development/Base BOMs

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 BASE685-00076 COMMON PARTS,MLB-BAF,X363 BASE_BOMCRITICAL
985-00126

WIFI/BT Diplexers

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

FLTR,DIPLEXER,2.45/5.54GHZ,0805

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

FB_4GB_MICRON,VRAM:GRP14GB_MC_BAFFIN

Main DRAM Parts

333S00050
333S00070

4
4

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

CRITICAL3155S0979 U3810,U3820,U3830 DIPLEXER:MURATA

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL
CRITICAL

DEVEL_BOM1 CRITICALDEVELDEV,MLB-BAF,X363

16G_SAMSUNG_2133

16G_MICRON_2133

Strategic Silicon

PART# COMMENT

337S00229

333S00050

333S00070 07

335S00149

335S00204 02

335S00205 02

335S00219 02

339S00154 02

339S00155 02

338S00166

337S00225

337S00285

337S00286

333S00044

333S00043

333S00078

333S00074

333S00075

343S00135

343S00136

343S00137

338S00138

353S3978 02

338S00097

353S00961 09

338S00142

359S00006

STRATEGIC VALUE

08337S00227

08337S00228

08

07

02

02

08

08

08

07

07

07

07

07

10

10

10

10

09338S00193

02

08338S00254

09

07353S00604

08353S4316

08338S00221

09353S00853

05339S00056

08

09353S00795

CPU

CPU

CPU

MAIN MEMORY

MAIN MEMORY

SSD NAND

SSD NAND

SSD NAND

SSD NAND

SSD CONTROLLER

SSD CONTROLLER

SSD PMIC

GPU

GPU

GPU

VIDEO MEMORY

VIDEO MEMORY

VIDEO MEMORY

VIDEO MEMORY

VIDEO MEMORY

T208

T208

T208

T208

BERKELIUM

MOJAVE

SECURE ELEMENT

ALPINE RIDGE

ACE

CLIFDEN

AUDIO AMP

BAYSIDE

BANJO

TUBA

ICEBOCK

GREEN CLOCK

DEBUG MUX

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

C

B

A

FB VDRAM Parts

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

333S00044
333S00043
333S00078
333S00074
333S00075

4
4
4
4
4

IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

UA400,UA450,UA500,UA550

CRITICAL
CRITICAL

CRITICAL
CRITICAL

Sub-BOM DIPLEXER

BOM NUMBER BOM NAME BOM OPTIONS

685-00085 DIPLEXERS,MURATA,X363G DIPLEXER:MURATA

FB_2GB_MICRON

FB_2GB_HYNIX

FB_2GB_SAMSUNGCRITICAL
FB_4GB_SAMSUNG

FB_4GB_MICRON

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Main DRAM SPD Straps

BOM GROUP BOM OPTIONS

16G_SAMSUNG_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG0:LRAM_16G_SAMSUNG_2133
16G_MICRON_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG1:LRAM_16G_MICRON_2133

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/07/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

2 OF 145

SHEET

2 OF 121

A

8 7 5 4 2 1

36

Programmable Parts

345678

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

2 1

D

338S1231
341S00701
335S00013
341S00699
353S00926
341S00707
341S00708
335S00024

341S00709

341S3565

335S0724 1 UA701

1
1
1
1
2
1
1
1
1341S00695
1
1 U9800

IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA

IC,SMC-B1,EXT (v2.37F7) PVT,X363G

IC,SPI SERIAL FLASH,64M BITS,3V,8P SOIC,QE=1

IC,EFI ROM (V0193), DVT, X363G

IC,CD3215,ACE,B03,BLNK,BGA96

T29,AR1 (V10.5) PVT, X363G

T29,AR2 (V10.5) PVT, X363G

IC,SERIAL-FLASH,2MBIT,4V,8-USON,2x3x,6MM

IC,BT ROM (V28), DVT, X362/X363

WIFI ROM (P107) DVT,NEW,WW1,X362/X363

IC, EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

U5000
U5000
U6100
U6100

U2890,UB090

U2890
UB090
U3750
U3750
U3710

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

SMC_PROG:BLANK

SMC_PROG:PVT

BOOTROM_PROG:BLANK

BOOTROM_PROG:DVT

UPCROM_PROG:BLANK

UPCROM_PROG:DVT

UPCROM_PROG:DVT

BT_PROG:BLANK

BT_PROG:DVT

WIFI_PROG:DVT

DPMUXMCU:PROG

GPUROM:BLANK

Blank

TI

Blank

Macronix/Winbond

Blank

Winbond

Winbond

Blank
Macronix/Winbond

Rohm/On Semi

Blank

D

C

C

B

B

A

SYNC_MASTER=J80_MLB_BAFFIN_CLEAN SYNC_DATE=12/02/2015

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

3 OF 145
3 OF 121

A

D

345678

2 1

D

C

B

Pogo Pins

APN 870-01771

PG0410

POGO-2.3OD-4.63H-SM

SM

1

PG0411

POGO-2.3OD-4.63H-SM

SM

1

PG0420

POGO-2.3OD-4.63H-SM

SM

1

PG0421

POGO-2.3OD-4.63H-SM

SM

1

PG0430

POGO-2.3OD-4.63H-SM

SM

1

PG0471

POGO-2.3OD-4.63H-SM

SM

1

PG0470

POGO-2.3OD-4.63H-SM

SM

1

APN 870-01772

PG0400

POGO-2.3OD-4.06H-SM

SM

1

PG0401

POGO-2.3OD-4.06H-SM

SM

1

APN 860-00392

BS0400

3.4OD1.75ID-1.12H-SM

1

BS0410

3.4OD1.75ID-1.12H-SM

1

APN 806-06520

BS0420

3.4OD1.75ID-1.45H-SM

1

APN 806-06521

BS0430

3.4OD1.75ID-1.9H-SM

1

BS0440

3.4OD1.75ID-1.9H-SM

1

BS0450

3.4OD1.75ID-1.9H-SM

1

APN 860-00413

BS0460

3.4OD1.75ID-1.57H-SM

1

APN 860-00469

BS0470

2.7X1.8R-1.4ID-0.91H-SM

1

SMT Bosses

USB-C Left
BOT side - North

USB-C Right
BOT side - North

DFR Touch
BOT side

DFR Display
BOT side - Left

Keyboard
BOT side - Left

Trackpad
BOT side - Left

Lifeboat
BOT side - North

eDP
TOP side - Left

BS0401

3.4OD1.75ID-1.12H-SM

1

USB-C Left
BOT side - South

BS0411

3.4OD1.75ID-1.12H-SM

1

USB-C Right
BOT side - South

APN 806-06600

BS0480

3.4OD1.75ID-2.12H-SM

1

BS0431

3.4OD1.75ID-1.9H-SM

1

DFR Display
BOT side - Right

BS0441

3.4OD1.75ID-1.9H-SM

1

Keyboard
BOT side - Right

BS0451

3.4OD1.75ID-1.9H-SM

1

Trackpad
BOT side - Right

BS0461

3.4OD1.75ID-1.57H-SM

1

Lifeboat
BOT side - South

BS0701

2.7X1.8R-1.4ID-0.91H-SM

1

eDP
TOP side - Right

USB-C Right

BOT side - Left

Rubber Mount
Standoffs

APN 860-00452

BM0400

3.09OD1.4ID-3.25H-SM

1

2

APN 860-00435

BM0401

2.8OD1.2ID-1.55H-SM

1

2

BM0402

2.8OD1.2ID-1.55H-SM

1

2

BM0403

2.8OD1.2ID-1.55H-SM

1

2

BM0404

2.8OD1.2ID-1.55H-SM

1

2

BM0405

2.8OD1.2ID-1.55H-SM

1

2

BM0406

2.8OD1.2ID-1.55H-SM

1

2

BM0407

2.8OD1.2ID-1.55H-SM

1

2

BM0408

2.8OD1.2ID-1.55H-SM

1

2

BM0409

2.8OD1.2ID-1.55H-SM

1

Shield Can TH

APN 998-2691

TH0400

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0401

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0410

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0411

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0420

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0421

TH-NSP

1

SL-1.1X0.4-1.4X0.7

T208 through holes are non-plated... for now

TH0440

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0441

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0450

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0451

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0460

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0461

TH-NSP

1

SL-1.1X0.4-1.4X0.7

System Memory - BOT side - Left

System Memory - BOT side - Right

TBT Left - BOT side - North

TBT Left - BOT side - South

TBT Right - BOT side - North

TBT Right - BOT side - South

T208 - TOP side - North

T208 - TOP side - South

SSD - BOT side - North

SSD - BOT side - South

SSD - TOP side - North

SSD - TOP side - South

Frame Buffer Memory - BOT side - Left

Frame Buffer Memory - BOT side - Right

Shield Can Fence

1

SH0400

SM

SHLD-FENCE-MLB-M8-X379

1

SH0410

SM

SHLD-FENCE-MLB-M8-X379

1

SH0420

SM

SHLD-FENCE-MLB-M8-X379

1

SH0430

SM

SHLD-FENCE-M8-X379

1

SH0440

SM

SHLD-FENCE-MLB-M8-X379

1

SH0450

SM

SHLD-FENCE-MLB-M8-X379

1

SH0460

SM

SHLD-FENCE-MLB-M8-X379

1

SH0470

SM

SHLD-FENCE-MLB-M8-X379

OMIT_TABLE

DRAM - BOT side

APN 806-06590

OMIT_TABLE

AR Right - BOT side

APN 806-06586

OMIT_TABLE

AR Left - BOT side

APN 806-06588

T208 - TOP side

APN 806-07814

OMIT_TABLE

SSD - TOP side

APN 806-06584

OMIT_TABLE

SSD - BOT side

APN 806-06585

OMIT_TABLE

Diplexer - BOT side

APN 806-06591

OMIT_TABLE

VRAM - BOT side

APN 806-08026

D

C

B

A

APN 806-07958

TOUCH-COWLING-HOOK-X378

1

BS0704

SM

DFR Touch - TOP side

2

BM0410

2.8OD1.2ID-1.55H-SM

1

2

BM0411

2.8OD1.2ID-1.55H-SM

1

2

BM0483

2.8OD1.2ID-1.55H-SM

1

2

APN 860-00500

BM0484

2.8OD1.2ID-3.5H-SM

1

2

APN 860-00500

BM0485

2.8OD1.2ID-3.5H-SM

1

2

BM0486

2.8OD1.2ID-3.5H-SM

1

2

BM0487

2.8OD1.2ID-3.5H-SM

1

2

Shield Can Omit Table

806-08023 1 SH0400 CRITICAL

1 CRITICALSH0410806-08019
1 CRITICALSH0420806-08021

806-07918

1 SH0450 CRITICAL806-07917

806-08024 CRITICALSH04601

BOM_COST_GROUP=MECHANICALS

SHIELD,FENCE,DRAM,X378

SHIELD,FENCE,ALPINE RIDGE,RIGHT,X378

SHIELD,FENCE,ALPINE RIDGE,LEFT,X378

SHIELD,NAND,TOP,ALT,X363

SHIELD,NAND,BOTTOM,ALT,X363

SHIELD,DIPLEX,EG,X378

FENCE,VRAM,EG,X378

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SH0440 CRITICAL1

SH0470 CRITICAL1806-08026

PAGE TITLE

PD Parts

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/16/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

4 OF 145

SHEET

4 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

113 13

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

E8

DMI_RXN0

F6

DMI_RXN1

E5

DMI_RXN2

J9

DMI_RXN3

D8

DMI_RXP0

E6

DMI_RXP1

D5

DMI_RXP2

J8

DMI_RXP3

A8

DMI_TXN0

B6

DMI_TXN1

A5

DMI_TXN2

B4

DMI_TXN3

B8

DMI_TXP0

C6

DMI_TXP1

B5

DMI_TXP2

D4

DMI_TXP3

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 1 OF 13

DMI

PEG_RCOMP

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8

PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

PEG_RXP8

PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

G2

D25
F24
D23
F22
D21
F20
D19
F18
E17
E16
E15
E14
E13
E12
E11
E10

E25
E24
E23
E22
E21
E20
E19
E18
D17
F16
D15
F14
D13
F12
D11
F10

CPU_PEG_RCOMP

PEG_GPU_D2R_N<0>
PEG_GPU_D2R_N<1>
PEG_GPU_D2R_N<2>
PEG_GPU_D2R_N<3>
PEG_GPU_D2R_N<4>
PEG_GPU_D2R_N<5>
PEG_GPU_D2R_N<6>
PEG_GPU_D2R_N<7>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_T_D2R_N<0>
PCIE_TBT_T_D2R_N<1>
PCIE_TBT_T_D2R_N<2>
PCIE_TBT_T_D2R_N<3>

PEG_GPU_D2R_P<0>
PEG_GPU_D2R_P<1>
PEG_GPU_D2R_P<2>
PEG_GPU_D2R_P<3>
PEG_GPU_D2R_P<4>
PEG_GPU_D2R_P<5>
PEG_GPU_D2R_P<6>
PEG_GPU_D2R_P<7>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_D2R_P<1>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_T_D2R_P<0>
PCIE_TBT_T_D2R_P<1>
PCIE_TBT_T_D2R_P<2>
PCIE_TBT_T_D2R_P<3>

PPVCCIO_S0_CPU

1

R0510

24.9

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.G2:5mm

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

5 8 109

NC_DDI1_ML_C_N<0>

111

NC_DDI1_ML_C_P<0>

111

NC_DDI1_ML_C_N<1>

111

NC_DDI1_ML_C_P<1>

111

NC_DDI1_ML_C_N<2>

111

NC_DDI1_ML_C_P<2>

111

NC_DDI1_ML_C_N<3>

111

NC_DDI1_ML_C_P<3>

111

NC_DDI2_ML_C_N<0>

111

NC_DDI2_ML_C_P<0>

111

NC_DDI2_ML_C_N<1>

111

NC_DDI2_ML_C_P<1>

111

NC_DDI2_ML_C_N<2>

111

NC_DDI2_ML_C_P<2>

111

NC_DDI2_ML_C_N<3>

111

NC_DDI2_ML_C_P<3>

111

NC_DDI3_ML_N<2>

111

NC_DDI3_ML_P<2>

111

NC_DDI3_ML_N<3>

111

NC_DDI3_ML_P<3>

111

NC_DDI3_ML_N<0>

111

NC_DDI3_ML_P<0>

111

NC_DDI3_ML_N<1>

111

NC_DDI3_ML_P<1>

111

Port D pins out of order
to match Intel symbol.

K37
K36

J34

J35
H36
H37

J38

J37

H33

H34
G38

F37
F35
F34
E36
E37

E33
F33
B33

C33
D34

C34

B34
B36

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

DDI3_TXN2
DDI3_TXP2
DDI3_TXN3
DDI3_TXP3

DDI3_TXN0
DDI3_TXP0
DDI3_TXN1
DDI3_TXP1

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 11 OF 13

EDP

EDP_DISP_UTIL

DIGITAL DISPLAY INTERFACES

EDP_AUXN
EDP_AUXP

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

EDP_RCOMP

DDI1_AUXN
DDI1_AUXP

DDI2_AUXN
DDI2_AUXP

DDI3_AUXN
DDI3_AUXP

B26
C26

E29
E28
B29
B28

D29
F28
A29
C28

D37
A33

E27
D27

E26
F26

B27
A27

NC

DP_INT_IG_AUX_N
DP_INT_IG_AUX_P

DP_INT_IG_ML_N<0>
DP_INT_IG_ML_N<1>
DP_INT_IG_ML_N<2>
DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<0>
DP_INT_IG_ML_P<1>
DP_INT_IG_ML_P<2>
DP_INT_IG_ML_P<3>

CPU_EDP_RCOMP

NC_DDI1_AUXCH_C_N
NC_DDI1_AUXCH_C_P

NC_DDI2_AUXCH_C_N
NC_DDI2_AUXCH_C_P

NC_DDI3_AUXCH_N
NC_DDI3_AUXCH_P

111

111

111

111

111

111

113 89

113 89

113 89

113 89

113 89

113 89

113 89

113 89

113 89

113 89

PPVCCIO_S0_CPU

1

R0530

24.9

1%
1/16W
MF-LF
402

2

D

5 8 109

PLACE_NEAR=U0500.D37:5mm

C

B

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TXN6
PEG_TXN7
PEG_TXN8

PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8

PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

A25
C24
A23
C22
A21
C20
A19
C18
B17
B16
B15
B14
B13
B12
B11
B10

B25
B24
B23
B22
B21
B20
B19
B18
A17
C16
A15
C14
A13
C12
A11
C10

PEG_GPU_R2D_C_N<0>
PEG_GPU_R2D_C_N<1>
PEG_GPU_R2D_C_N<2>
PEG_GPU_R2D_C_N<3>
PEG_GPU_R2D_C_N<4>
PEG_GPU_R2D_C_N<5>
PEG_GPU_R2D_C_N<6>
PEG_GPU_R2D_C_N<7>
PCIE_TBT_X_R2D_C_N<0>
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_T_R2D_C_N<0>
PCIE_TBT_T_R2D_C_N<1>
PCIE_TBT_T_R2D_C_N<2>
PCIE_TBT_T_R2D_C_N<3>

PEG_GPU_R2D_C_P<0>
PEG_GPU_R2D_C_P<1>
PEG_GPU_R2D_C_P<2>
PEG_GPU_R2D_C_P<3>
PEG_GPU_R2D_C_P<4>
PEG_GPU_R2D_C_P<5>
PEG_GPU_R2D_C_P<6>
PEG_GPU_R2D_C_P<7>
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_R2D_C_P<1>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_R2D_C_P<3>
PCIE_TBT_T_R2D_C_P<0>
PCIE_TBT_T_R2D_C_P<1>
PCIE_TBT_T_R2D_C_P<2>
PCIE_TBT_T_R2D_C_P<3>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

111

TP-P5
TP-P5

TP-P5
TP-P5
TP-P5

TP0501
TP0502

TP0503
TP0504
TP0505

TP
TP

TP
TP
TP

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 13 OF 13

OPC_RCOMP

OPCE_RCOMP

OPCE_RCOMP2

PROC_TRIGIN

PROC_TRIGOUT

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDR_VTT_CNTL

PM_DOWN

BT29
BR25
BP25

H23
J23

G27
G25
G29

BT13
BP31

CPU_EOPIO_RCOMP
CPU_OPC_OPIO_RCOMP
CPU_OPC_OPIO_RCOMP_ED2

PCH_CPU_TRIGGER
CPU_PCH_TRIGGER_R

PCH_DISPA_BCLK
PCH_DISPA_SDO
CPU_PROC_AUD_SDO_R

PM_MEMVTT_EN

CPU_PCH_PM_DOWN_R

IN

5

IN
IN

5

OUT

5

13

20

20

71

1

R0521

49.9

1%
1/20W
MF
201

2

1

R0522

49.9

1%
1/20W
MF
201

2

1

R0523

49.9

1%
1/20W
MF
201

2

NC

NC

B2

B38
BP1
BR2

C1

C38

BR33

AT13

AW13

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

SKTOCC*
ZVM*

MSM*

1
1

1
1
1

CPU_DC_B2_C1
CPU_DC_B38_C38

NC

CPU_DC_BR2_BR1
CPU_DC_C1_B2
CPU_DC_C38_B38

NC

CPU Daisy-Chain Strategy:

Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP's on each corner.

R0524

30

5

1 2

5%

1/20W

MF

201

CPU_PCH_TRIGGERCPU_PCH_TRIGGER_R

OUT

13

B

A

5

5

BOM_COST_GROUP=CPU & CHIPSET

CPU_PCH_PM_DOWN_R

CPU_PROC_AUD_SDO_R

SYNC_MASTER=X363_AGOTETI SYNC_DATE=01/21/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R0525

20

1 2

5%

1/20W

MF

201

CPU_PCH_PM_DOWN

OUT

13

R0526

20

1 2

5%

1/20W

MF

201

PCH_DISPA_SDI

OUT

20

CPU DMI/PEG/FDI/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

5 OF 145

SHEET

5 OF 121

A

D

8 7 5 4 2 1

36

PP1V0_S3

6 8 11 110

PLACE_NEAR=U0500.BM30:10mm

1

R0604

49.9

1%
1/20W
MF
201

2

OMIT_TABLE

345678

2 1

D

PP1V0_S0SW

8 11 18 110

PP1V0_S3

6 8 11 110

65 47 46

48 47 46 13

OUT

U0500

Note: Confirm values for 0603 and 0601. Different for J145

NC

1

R0605

1K

1%
1/16W
MF-LF
402

BI

CPU_PROCHOT_L

2

1

R0601

1K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U0500.BR30:5mm

R0603

499

1 2

1%

402

1/16W

MF-LF

46

47 13

13

13

13

OUT

BI

IN
IN
IN

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC
CPU_RESET_L
CPU_PWRGD

BN1

BM30

BT34

BR30

BM34

BP35

BT31

PROC_SELECT*

CATERR*

PECI

PROCHOT*

J31

THERMTRIP*

PM_SYNC
RESET*
PROCPWRGD

SKYLAKE-4+4E

BGA

SYM 2 OF 13

(IPU)
(IPU)

(IPD)
(IPU)

(IPU)

(IPU)

JTAG DDR3

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

PROC_PRDY*
PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

G1
H1
J2

BP27
BL30

BR28
BP28
BP30

BL32
BT28

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

OUT

IN

IN
IN
IN

IN

OUT

1

R0614

162

115 18 13

115 18 13

115 18

115 18

115 18 13

115 18

115 18

1%
1/16W
MF-LF
402

2

1

R0613

121

1%
1/16W
MF-LF
402

2

1

R0612

200

1%
1/16W
MF-LF
402

2

D

C

B

A

P2MM

SM

1

PP0600
PP0601
PP0602

PP0603

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

TP_CPU_RSVD_R14

1

TP_CPU_RSVD_N29

1

TP_CPU_RSVD_AE29

1

TP_CPU_RSVD_AA14

6

6

6

6

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1K

5%

1/20W

MF

201

NOSTUFF

R0647

1K

5%

1/20W

MF

201

CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1K

5%

1/20W

MF

201

1

2

1

2

R0648

NOSTUFF

1

R0643

1K

5%
1/20W
MF
201

2

NOSTUFF

R0641

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0640

1K

5%
1/20W
MF
201

2

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>

CPUCFG6_PD

1K

5%

1/20W

MF

201

1

2

1

2

R0646

CPUCFG5_PD

1

R0645

1K

5%
1/20W
MF
201

2

EDP:YES

R0644

1K

5%

1/20W

MF

201

1

2

CPU_CFG<2>

NOSTUFF

1

R0642

1K

5%
1/20W
MF
201

2

18 6

18 6

115 18 6

18 6

18 6

18 6

18 6

18 6

18 6

18 6

BOM GROUP BOM OPTIONS

CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

113 12

113 12

113 12

113 12

113 12

113 12

IN
IN

IN
IN

IN
IN

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

PLACE_NEAR=U0500.BT31:157mm

R0611

10K

5%
1/16W
MF-LF

402

1

2

D31
E31

C36
D35

A32
B31

CLK24N
CLK24P

PCI_BCLKN
PCI_BCLKP

BCLKN
BCLKP

CLOCK PWR THERMAL

(IPU)
(IPU)
(IPU)
(IPU)

BPM0*
BPM1*
BPM2*
BPM3*

BR27
BT27
BM31
BT30

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

18

BI

18

BI

18

BI

18

BI

C

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 12 OF 13

RESERVED

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG_RCOMP

(IPU)

(IPU)

RSVD_TP
RSVD_TP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD

RSVD

VSS
VSS

VSS
VSS

RSVD
RSVD
RSVD

BK24
BK16
BJ16
BJ24

BT25
BP23

BN22
BN23
BP22

AU13
AY13
J24
J3

BR17
BN33
BP16
BR16

BP17
BR35
BR31

BN35
BT17

C30

BT2
BR1

W3
W2

V6
W1

H24
E30
F30

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TP_CPU_RSVD_TP_BK24
TP_CPU_RSVD_TP_BK16
TP_CPU_RSVD_TP_BJ16
TP_CPU_RSVD_TP_BJ24

CPU_CFG_RCOMP
CPU_CFG<16>

CPU_CFG<18>
CPU_CFG<17>
CPU_CFG<19>

NC
NC
NC
NC

NC
NC
NC
NC

NC
NC
NC

NC
NC

NC

TP_CPU_RSVD_TP_BT2
CPU_DC_BR1_BR2

NC
NC
NC

18 6

18

18

18

1

TP

TP-P5

TP0610

1

R0690

49.9

1%
1/16W
MF-LF
402

2

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

CPU Clock/Misc/JTAG/CFG

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

6 OF 145

SHEET

6 OF 121

D

B

A

18 6

18 6

18 6

115 18 6

18 6

18 6

18 6

18 6

18

18 6

18

18

18

18

18

18

TP_CPU_RSVD_TP_BJ34
TP_CPU_RSVD_TP_BJ33

TP_CPU_RSVD_TP_BL33
TP_CPU_RSVD_TP_BM33

TP_CPU_RSVD_TP_D1

PPVCC_S0_CPU

8 55 109

TP_CPU_RSVD_R14

6

TP_CPU_RSVD_N29

6

TP_CPU_RSVD_AE29

6

TP_CPU_RSVD_AA14

6

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>

CPUCFG5_PDCPUPEG:X8X8

NC
NC
NC

BJ34
BJ33

BL33

BM33

D1

V30
V12
V29
Y35

R14

N29
AE29
AA14

BN25
BN27
BN26
BN28
BR20

BM20

BT20
BP20
BR23
BR22

BT23

BT22

BM19

BR19
BP19

BT19

G3

G13

BT16

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_TP

VSS
VSS
VSS
VCC

RSVD
RSVD
RSVD
RSVD

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD
RSVD
RSVD

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

8 7 5 4 2 1

36

D

C

B

A

0

1 2

5%

1/20W

MF

201

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 26 22

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

R0701

21

21

21

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

NOSTUFF

1 2

5%

1/20W

MF

201

OUT

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ

0

R0703

DDR0_PAR
MEM_A_ALERT

CPU_DIMM_VREFCA

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

BR6

BT6
BP3
BR3
BN5
BP6
BP2
BN3

BL4

BL5

BL2

BM1

BK4
BK5
BK1
BK2

BT11

BR11

BT8
BR8

BP11
BN11

BP8
BN8

BL12
BL11

BL8

BJ8
BJ11
BJ10

BL7

BJ7

BG4
BG5

BF4

BF5
BG2
BG1

BF1

BF2

BD2
BD1
BC4
BC5
BD5
BD4
BC1

BC2
BG11
BG10

BG8

BF8
BF11
BF10

BG7

BF7

BB11
BC11

BB8

BC8
BC10
BB10

BC7

BB7

AG3

AU5
BN13

BP13
BR13

BJ26

AP1

AT4
AP3
AN3
AN1
AU1
AU4
AN2
AU3
AU2

DDR0_DQ0
DDR0_DQ1

SKYLAKE-4+4E

DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQ32
DDR0_DQ33
DDR0_DQ34
DDR0_DQ35
DDR0_DQ36
DDR0_DQ37
DDR0_DQ38
DDR0_DQ39
DDR0_DQ40
DDR0_DQ41
DDR0_DQ42
DDR0_DQ43
DDR0_DQ44
DDR0_DQ45
DDR0_DQ46
DDR0_DQ47
DDR0_DQ48
DDR0_DQ49
DDR0_DQ50
DDR0_DQ51
DDR0_DQ52
DDR0_DQ53
DDR0_DQ54
DDR0_DQ55
DDR0_DQ56
DDR0_DQ57
DDR0_DQ58
DDR0_DQ59
DDR0_DQ60
DDR0_DQ61
DDR0_DQ62
DDR0_DQ63

DDR0_PAR
DDR0_ALERT*
DDR_VREF_CA

DDR0_VREF_DQ
DDR1_VREF_DQ

RSVD
DDR0_CAA0

DDR0_CAA1
DDR0_CAA2
DDR0_CAA3
DDR0_CAA4
DDR0_CAA5
DDR0_CAA6
DDR0_CAA7
DDR0_CAA8
DDR0_CAA9

OMIT_TABLE

U0500

BGA

SYM 3 OF 13

MEMORY CHANNEL DDR0

DDR0_DQSN0
DDR0_DQSN1
DDR0_DQSN2
DDR0_DQSN3
DDR0_DQSN4
DDR0_DQSN5
DDR0_DQSN6
DDR0_DQSN7
DDR0_DQSN8

DDR0_DQSP0
DDR0_DQSP1
DDR0_DQSP2
DDR0_DQSP3
DDR0_DQSP4
DDR0_DQSP5
DDR0_DQSP6
DDR0_DQSP7
DDR0_DQSP8

RSVD

DDR0_CKN0
DDR0_CKP0
DDR0_CKE0

DDR0_CKN1
DDR0_CKP1
DDR0_CKE1

DDR0_CLKN2
DDR0_CLKP2

DDR0_CKE2

DDR0_CLKN3
DDR0_CLKP3

DDR0_CKE3

DDR0_CS0*
DDR0_CS1*
DDR0_CS2*
DDR0_CS3*

DDR0_ODT0
DDR0_ODT1
DDR0_ODT2
DDR0_ODT3

VSS

DDR0_MA3
DDR0_MA4

DDR0_ECC0
DDR0_ECC1
DDR0_ECC2
DDR0_ECC3
DDR0_ECC4
DDR0_ECC5
DDR0_ECC6
DDR0_ECC7

RSVD
RSVD

RSVD
RSVD_TP
RSVD_TP

RSVD

DDR0_CAB0
DDR0_CAB1
DDR0_CAB2
DDR0_CAB3
DDR0_CAB4
DDR0_CAB5
DDR0_CAB6
DDR0_CAB7
DDR0_CAB8
DDR0_CAB9

BJ23
AG2

AG1
AT1

AK1
AK2
AT2

AK3
AL3
AT3

AL1
AL2
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

U38

AP5
AP2

BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2

BR5
BL3
BP9
BL9
BG3
BD3
BG9
BC9
BA3

BP5
BK3
BR9
BJ9
BF3
BC3
BF9
BB9
AY3

AJ8
B30
BH30
BJ13
BJ14
BJ21

AE3
AD1
AG4
AH4
AH5
AN4
AH1
AH2
AP4
AH3

NC

NC
NC

NC
NC

NC
NC

NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC

NC

NC
NC
NC
NC
NCNC

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>

MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

345678

2 1

OMIT_TABLE

113 26 22

113 26 22

26 22

113 26 23

113 26 23

26 22

26 23

26 23

26 23 22

26 23 22

26 23 22

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

1 2

112

0

5%

1/20W

MF

201

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

0

1 2

R0702

5%

1/20W

MF

201

R0704

DDR1_PAR

MEM_B_ALERT

AB1
AB2
AA4
AA5
AB5
AB4
AA2
AA1

V5
V2
U1
U2
V1
V4
U5

U4
AA11
AA10
AC11
AC10

AA7
AA8
AC8
AC7

W8

W7
V10
V11

W11
W10

V7
V8
R2
P5
R4
P4
R5
P2
R1

P1
M4
M1

L4

L2
M5
M2

L5

L1

R11
P11

P7

R8
R10
P10

R7

P8

L11

M11

L7

M8

L10

M10

M7

L8

AJ7

AR8

DDR1_DQ0
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ30
DDR1_DQ31
DDR1_DQ32
DDR1_DQ33
DDR1_DQ34
DDR1_DQ35
DDR1_DQ36
DDR1_DQ37
DDR1_DQ38
DDR1_DQ39
DDR1_DQ40
DDR1_DQ41
DDR1_DQ42
DDR1_DQ43
DDR1_DQ44
DDR1_DQ45
DDR1_DQ46
DDR1_DQ47
DDR1_DQ48
DDR1_DQ49
DDR1_DQ50
DDR1_DQ51
DDR1_DQ52
DDR1_DQ53
DDR1_DQ54
DDR1_DQ55
DDR1_DQ56
DDR1_DQ57
DDR1_DQ58
DDR1_DQ59
DDR1_DQ60
DDR1_DQ61
DDR1_DQ62
DDR1_DQ63

DDR1_PAR
DDR1_ALERT*

U0500

SKYLAKE-4+4E

BGA

SYM 4 OF 13

MEMORY CHANNEL DDR1

RSVD

DDR1_CKN0
DDR1_CKP0
DDR1_CKE0

DDR1_CKN1
DDR1_CKP1
DDR1_CKE1

DDR1_CLKN2
DDR1_CLKP2

DDR1_CKE2

DDR1_CLKN3
DDR1_CLKP3

DDR1_CKE3

DDR1_CS0*
DDR1_CS1*
DDR1_CS2*
DDR1_CS3*

DDR1_ODT0
DDR1_ODT1
DDR1_ODT2
DDR1_ODT3

VSS

DDR1_MA3
DDR1_MA4

DDR1_ECC0
DDR1_ECC1
DDR1_ECC2
DDR1_ECC3
DDR1_ECC4
DDR1_ECC5
DDR1_ECC6
DDR1_ECC7

DDR1_DQSN0
DDR1_DQSN1
DDR1_DQSN2
DDR1_DQSN3
DDR1_DQSN4
DDR1_DQSN5
DDR1_DQSN6
DDR1_DQSN7
DDR1_DQSN8

DDR1_DQSP0
DDR1_DQSP1
DDR1_DQSP2
DDR1_DQSP3
DDR1_DQSP4
DDR1_DQSP5
DDR1_DQSP6
DDR1_DQSP7
DDR1_DQSP8

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 23

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

113 26 24

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

AM6

AR11

AN7
AN8

AN10

AR9
AR10
AN11

AT9

AR7

DDR1_CAA0
DDR1_CAA1
DDR1_CAA2
DDR1_CAA3
DDR1_CAA4
DDR1_CAA5
DDR1_CAA6
DDR1_CAA7
DDR1_CAA8
DDR1_CAA9

RSVD

DDR1_CAB0
DDR1_CAB1
DDR1_CAB2
DDR1_CAB3
DDR1_CAB4
DDR1_CAB5
DDR1_CAB6
DDR1_CAB7
DDR1_CAB8
DDR1_CAB9

BJ27
AN9

AM9
AT8

AM8
AM7
AT10

AM10
AM11
AT7

AJ11
AJ10
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

Y38

AL5
AL6

AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7

AA3
U3
AC9
W9
P3
L3
R9
M9
AY9

AB3
V3
AA9
V9
R3
M3
P9
L9
AW9

BK28
BK26
BK27
BK23
BK21
BJ35
BJ28
BJ36

AF9
AF8
AH11
AH10
AH8
AK5
AH9
AH7
AK6
AJ9

NC

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>

MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<1>

OUT
OUT
OUT

OUT
OUT
OUT

NC
NC

MEM_B_CKE<2>

OUT

NC
NC

MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

OUT

OUT
OUT

NC
NC

MEM_B_ODT<0>

OUT

NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

BI
BI
BI
BI
BI
BI
BI
BI

NC

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

BI
BI
BI
BI
BI
BI
BI
BI

NC

NC
NCNC
NC
NC
NC
NC
NC
NC

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BOM_COST_GROUP=CPU & CHIPSET

113 26 24

113 26 24

26 24

113 26 25

113 26 25

26 24

D

26 25

26 25

26 25 24

26 25 24

26 25 24

C

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

B

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 112

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

113 26 25

PAGE TITLE

CPU DDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER SIZE

051-00647

051-00647

REVISION

BRANCH

dvt-fab10

dvt-fab10

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

10.0.0

10.0.0

7 OF 145

7 OF 145
7 OF 1217 OF 121

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V0_S3

6 8 11 110

CPU_VCCST_PWRGD_R

8

PP1V0_S0SW

6 11 18 110

PPVCCGT_S0_CPU

AW36

AW37

AW38

AY29

VCCGT

VCCGT

VCCGT

U0500

OMIT_TABLE

VCCGT

BGA

SYM 7 OF 13

SKYLAKE-4+4E

VCCGT

VCCGT

AJ31

AJ32

VCCGT

VCCGT

AJ29

AJ30

AY30

AY31

VCCGT

VCCGT

POWER

VCCGT

VCCGT

AJ33

AJ34

AY32

AY35

VCCGT

VCCGT

VCCGT

VCCGT

AJ35

AJ36

AY36

AY37

VCCGT

VCCGT

VCCGT

VCCGT

AK31

AK32

8 55 109

AY38

BA13

VCCGT

VCCGT

VCCGT

VCCGT

AK33

AK34

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC

NC
NC

BA14

BA29

VCCGT

VCCGT

VCCGT

VCCGT

AK35

AK36

OMIT_TABLE

AF29
AF30
AF31
AF32
AF33

AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32

AH36
AH35 J14

BK17

BK19

BK20

BL16
BL17
BL18
BL19
BL20

BL21
BM17
BN17

BL15
BM16

BP15
BR15
BT15

BN15

BM15

BA30

VCCGT

VCCGT

AK37

VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX

AJ13

VCCGTX

AJ14

VCCGTX
VCCGTX_SENSE

VSSGTX_SENSE

BJ17

VCCOPC

BJ19

VCCOPC

BJ20

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

VCCOPC_SENSE
VSSOPC_SENSE

H30

VCCST

H13

VCCST_PWRGD

G30

VCCSTG

H29

VCCSTG
VCCEOPIO

VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

BA31

BA32

BA33

BA34

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AL13

AL29

AK38

AL30

U0500

SKYLAKE-4+4E

SYM 6 OF 13

POWER

BA35

BA36

BB13

BB14

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AL35

AL36

VCCGT

AL37

VCCGT

AL31

AL32

BGA

BB31

BB32

VCCGT

VCCGT

VCCGT

VCCGT

AL38

VCCIO_SENSE

VSSIO_SENSE

VCCSA_SENSE

VSSSA_SENSE

VCCPLL_OC
VCCPLL_OC

VCC_OPC_1P8
VCC_OPC_1P8

BB33

BB34

BB35

BB36

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AM13

AM14

AM29

AM30

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCPLL
VCCPLL

BB37

BB38

VCCGT

VCCGT

VCCGT

VCCGT

AM31

AM32

BC29

VCCGT

VCCGT

VCCGT

VCCGT

AM33

AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27

H14

J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36

M38
M37

H28
J28

BH13
G11

BL14
BM14

BC30

BC31

VCCGT

VCCGT

AM34

AM35

PPVCCIO_S0_CPU

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

PPVCCSA_S0_CPU

CPU_VCCSASENSE_P
CPU_VCCSASENSE_N

PP1V0_S3

PP1V2_S0SW

109

NC
NC

BC32

BC35

BC36

BC37

BC38

BD13

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AN32

AN33

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AN13

AM36

VCCGT

VCCGT

VCCGT

AN14

AN31

BD14

BD29

VCCGT

VCCGT

VCCGT

VCCGT

AN34

AN35

BD30

BD31

VCCGT

VCCGT

VCCGT

VCCGT

AN36

AN37

BD32

BD33

VCCGT

VCCGT

VCCGT

VCCGT

AP13

AN38

11 110

BD34

BD35

VCCGT

VCCGT

VCCGT

VCCGT

AP14

AP29

5 8 109

OUT
OUT

8 53 109

OUT
OUT

1

C0802

2

BD36

BE31

VCCGT

VCCGT

VCCGT

VCCGT

AP30

AP31

71 8

71 9

65 8

65 9

1UF

20%

6.3V
X6S-CERM
0201

BE32

BE33

BE34

VCCGT

VCCGT

VCCGT

VCCGT

AP32

AP35

AP36

BE35

BE36

VCCGT

VCCGT

VCCGT

VCCGT

AP37

AP38

1

2

1

C0803

1UF

20%

6.3V

2

X6S-CERM
0201

BE37

BE38

VCCGT

VCCGT

VCCGT

VCCGT

AR29

AR30

R0864

100

5%
1/20W
MF
201

70

IN

BF13

BF14

BF29

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AR31

AR32

AR33

PPVCC_S0_CPU

1

R0865

100

5%
1/20W
MF
201

2

PPVCCGT_S0_CPU
PPVCCSA_S0_CPU

PLACE_NEAR=U0500.AG37:50.8mm
PLACE_NEAR=U0500.AH38:50.8mm
PLACE_NEAR=U0500.M38:50.4mm

1

R0866

100

5%
1/20W
MF
201

2

8 55 109

8 53 109

CPU_VCCSASENSE_P
CPU_VCCGTSENSE_P
CPU_VCCSENSE_P

PPVCCIO_S0_CPU

PLACE_NEAR=U0500.H14:50.8mm

1

R0861

100

5%
1/20W
MF
201

2

CPU_VCCIOSENSE_P

PULL-UPS FOR SENSE LINES

PP1V0_S3

6 8 11 110

1

R0840

1K

1%
1/16W
MF-LF
402

2

R0841

60.4

BG33

BG34

VCCGT

VCCGT

VCCGT

VCCGT

AT38

AU14

1 2

1%

1/20W

MF

201

1

R0802

100

5%
1/20W
MF
201

2

BG35

BG36

BH33

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AU29

AU30

AU31

BH34

BH35

VCCGT

VCCGT

VCCGT

VCCGT

AU32

AU35

BH36

VCCGT

VCCGT

AU36

CPU_VCCST_PWRGD

PP1V0_S3

6 8 11 110

65

65

Place on bottom side of U0500

Place on bottom side of U0500

BF30

VCCGT

VCCGT

VCCGT

VCCGT

AR34

CPU_VIDALERT_L

IN

OUT

BF31

BF32

VCCGT

VCCGT

AR35

AR36

CPU_VIDSCLK

65

BI

BF35

BF36

BF37

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AT14

AT31

AT32

CPU_VIDSOUT

BF38

VCCGT

VCCGT

AT33

BG29

BG30

VCCGT

VCCGT

VCCGT

VCCGT

AT34

AT35

BG31

BG32

VCCGT

VCCGT

AT36

AT37

6 8 55 109

65 8

65 8

65 8

CPU_VCCST_PWRGD_R

1

R0800

56.2

1%
1/20W
MF
201

2

R0810

220

1 2

5%

1/20W

MF

201

R0811

0

1 2

5%
1/16W
MF-LF

402

R0812

0

1 2

5%
1/16W
MF-LF

402

65 9

65 8

BH37

BH38

VCCGT

VCCGT

VCCGT

VCCGT

AU37

AU38

OUT
OUT

BJ37

VCCGT

VCCGT

VCCGT

VCCGT

AV29

CPU_VCCGTSENSE_N
CPU_VCCGTSENSE_P

BJ38

BL36

BL37

BM36

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AV30

AV31

AV32

AV33

5 8 109

71 8

BM37

BN36

VCCGT

VCCGT

VCCGT

VCCGT

AV34

AV35

PP1V2_S3_CPUDDR

8 109

PP1V2_S3_CPUDDR

8 109

PLACE_NEAR=U0500.Y12:5mm

8

PPVCC_S0_CPU

6 8 55 109

65 8

65 9

OUT
OUT

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

TP_CPU_RSVD_TP75
TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP78

PPVCC_S0_CPU

6 8 55 109

BN37

BN38

BP37

BP38

BR37

BT37

AH38

AH37

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VSSGT_SENSE

VCCGT_SENSE

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

VCCGT

AV36

AW14

AW31

AW32

AW33

AW34

AW35

NC
NC
NC
NC

1

C0801

10UF

20%
10V

2

X5R-CERM
0402-7

NC
NC
NC
NC

NC
NC
NC
NC

BL31

BL34
BM22
BM24

AA6

AE12

AF5

AF6
AG5
AG9

AJ12
AL11

AP6

AP7

AR12

AR6

AT12

AW6

AY6

J5
J6

K12

K6

L12

L6

R6

T6

W6

Y12

BL25
BL22
BL24
BL23

U36

V13

AG37
AG38

BL26

BN16

BL28
BL27

BH31
BH32
BH29

Y7

Y8
E2
E1

E3
Y9

Y13

W4

W34

Y10

W5

Y14

W12

Y37

W33

Y11

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AB30
AB31
AA38
AB29

V14
V31
V32
V33
V34
V35
V36
V37

V38
W13
W14

OMIT_TABLE

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQC

RSVD
RSVD
RSVD
RSVD

VCC
VCC

VCC_SENSE
VSS_SENSE

RSVD
RSVD
RSVD
RSVD

VIDALERT*
VIDSCK
VIDSOUT

VSS

VSS
RSVD_TP
RSVD_TP

RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U0500

SKYLAKE-4+4E

BGA

SYM 5 OF 13

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

BOM_COST_GROUP=CPU & CHIPSET

AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y36

PPVCC_S0_CPU

PAGE TITLE

6 8 55 109

CPU Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/16/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

8 OF 145

SHEET

8 OF 121

D

C

B

A

8 7 5 4 2 1

36

OMIT_TABLE

345678

2 1

D

C

B

AU34
AU33
AU12
AU11
AU10

AU9
AU8
AU7

AU6
AT30
AT29

AT6
AR38
AR37

AR5
AR14
AR13

AR4

AR1
AP34
AP33
AP12

AR3

AR2

AP9

AP11

AP8
AP10
AN12

AN6

AN5
AN30
AN29

AM38
AM37
AM12

AM5

AM2

AM4

AM1

AM3

AL34
AL33
AL14

AL8

AL12

AL7

AL4
AK30
AK29

AL10

AL9

AK4
AJ38
AJ37

AJ6
AJ3
AJ5
AJ2
AJ4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 8 OF 13

GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ1
AH34
AH33
AG29
AH12
AG11
AH6
AG30
AG10
AG8
AF14
AG7
AG6
AF13
AF4
AF3
AF2
AF1
AF12
AE34
AE33
AE6
AD30
AD11
AD29
AD10
AD12
AD8
AD7
AD9
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AD6
AB6
AC38
AC37
AC12
AA30
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6
AA29

AW2

AW29

AW3

AW30

AW4

AW5
AY12
AV37
AY14
AY33
AY34

B9
BA10
AV38

AW1

AW12

BA37
BA38

BA6
BA7
BA8
BA9

BB1
BB12
BA11
BA12

BB2

BB6
BC12
BB29
BC13
BC14
BC33

BB3
BC34
BB30

BC6

BB4
BD10

BB5
BD37
BD38

BD6

BD7

BD8

BD9

BE1

BE2
BE29
BD11

BE3
BE30

BE4
BD12

BE6
BF12
BF33
BF34

BF6

BG12
BG13

BN2

BN19
BN20
BN21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U0500

SKYLAKE-4+4E

BGA

SYM 9 OF 13

GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BG14
BE5
BG38
BG6
BH1
BH10
BH11
BH12
BH14
BH2
BH3
BH4
BH5
BG37
BH9
BJ12
BJ15
BJ18
BJ22
BJ25
BJ29
BH6
BJ30
BH7
BJ31
BJ32
BK13
BK14
BH8
BK29
BK6
BL13
BL29
BL35
BL38
BL6
BM11
BM12
BM13
BM18
BM2
BM21
BM23
BM25
BM26
BM27
BM28
BM29
BM3
BM5
BM6
BM7
BM8
BM9
BK15
BK18
BK22
BK25
U6
BN24
G8
G9
H11
H12
H18

CPU_VCCGTSENSE_N

CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N
CPU_VCCSENSE_N

1

R0961

100

5%
1/20W
MF
201

2

1

R0963

100

5%
1/20W
MF
201

2

1

R0965

100

5%
1/20W
MF
201

2

1

R0966

100

5%
1/20W
MF
201

2

OUT

OUT

OUT
OUT

D

65 8

71 8

65 8

65 8

C

B

H22

H25

H32

H35

VSS

VSS

VSS

VSS

BGA

U0500

OMIT_TABLE

SKYLAKE-4+4E

SYM 10 OF 13

J10

VSS

J18

VSS

J22

VSS

G23

VSS

G24

VSS

G26

VSS

J32

VSS

J33

VSS

J25

VSS

J4

VSS

J7

VSS

K10

VSS

J36K1K2

VSS

VSS

K11

VSS

K3

VSS

K38

VSS

K4K5K7

VSS

VSS

VSS

L29

VSS

K8

VSS

VSS

K9

VSS

L33

VSS

L34M6M12

VSS

VSS

M13

VSS

L30

VSS

M14

VSS

N1

VSS

N10

VSS

N11

VSS

VSS

N12

VSS

N4

VSS

N2

N5N6N7

VSS

VSS

VSS

N3

VSS

N33

VSS

N9

VSS

N8

VSS

P12

VSS

P37

VSS

P38

VSS

P6

VSS

R12

VSS

T10

VSS

R29

VSS

T11

VSS

T12

VSS

T13

VSS

R30

VSS

T1T2T3

VSS

VSS

VSS

T14

VSS

T34

VSS

T4T5T7

VSS

VSS

VSS

VSS

T33

VSS

U37

VSS

T8

VSS

T9

VSS

A36

VSS

A37

VSS

BM35

BM38

VSS

VSS

N34

VSS

G6

VSS

A3

A4

A34

NCTFVSS

NCTFVSS

NCTFVSS

B3

B37

BR38

NCTFVSS

NCTFVSS

NCTFVSS

BT3

BT35

BT36C2D38

NCTFVSS

NCTFVSS

NCTFVSS

CPU_DC_BR38_BT36
CPU_DC_BT36_BR38

BT4

NCTFVSS

NCTFVSS

NCTFVSS

1

TP

1

TP0900

TP

TP0901

TP-P5
TP-P5

A

VSS

BN12

BN29

VSS

BN30

VSS

BN31

VSS

VSS

BN4

BN34

VSS

BN7

VSS

BN9

VSS

BP12

VSS

BP14

VSS

BN14

VSS

BP18

VSS

BP21

VSS

BN18

VSS

BP26

VSS

BP29

VSS

BP33

VSS

BP34

VSS

BP7

VSS

VSS

BP24

BR12

VSS

BR14

VSS

BR18

VSS

BR21

VSS

BR24

VSS

BR26

VSS

BR29

VSS

VSS

VSS

BR7

BR36

VSS

BT12

BT14

VSS

BT18

VSS

BT21

VSS

BT24

VSS

BT26

VSS

BT32

VSS

BT5

VSS

BT9

VSS

VSS

C11

VSS

C13

VSS

C15

VSS

C21

BR34

VSS

C23

VSS

C25

VSS

C27

VSS

C29

VSS

C31

VSS

C37

VSS

C5

VSS

C17

VSS

C8

VSS

C9

VSS

D10

VSS

D12

VSS

C19

VSS

D16

VSS

D18

VSS

D20

VSS

D22

VSS

D24

VSS

D26

VSS

VSS

D28

VSS

D3

VSS

D30

VSS

D33

VSS

D6

VSS

D14

VSS

E34

VSS

E35

VSS

E38

VSS

E4

VSS

E9

VSS

F11

F13

VSS

F15

VSS

F17

VSS

F19

VSS

F2

VSS

F21

VSS

F23

VSS

F25

VSS

VSS

F27

VSS

F29

VSS

F3

VSS

F31

VSS

F36

VSS

D9

VSS

F4

VSS

G10

VSS

F5

VSS

G12

VSS

G14

VSS

G16

VSS

F8

VSS

G18

VSS

G20

VSS

G22

VSS

F9

VSS

G28

VSS

G4

VSS

G5

SYNC_MASTER=J80_MLB SYNC_DATE=08/17/2015

PAGE TITLE

CPU Ground

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

9 OF 145
9 OF 121

A

D

345678

2 1

D

PPVCC_S0_CPU

109

CPU VCORE Decoupling

Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side
Apple Implementation:

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1000

1UF

20%
4V

2

CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1023

1UF

20%
4V

2

CERM-X6S
0201

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1001

1UF

20%
4V

2

CERM-X6S
0201

1

C1024

1UF

20%
4V

2

CERM-X6S
0201

1

C1002

1UF

20%
4V

2

CERM-X6S
0201

1

C1025

1UF

20%
4V

2

CERM-X6S
0201

1

C1003

1UF

20%
4V

2

CERM-X6S
0201

1

C1026

1UF

20%
4V

2

CERM-X6S
0201

1

C1004

1UF

20%
4V

2

CERM-X6S
0201

1

C1027

1UF

20%
4V

2

CERM-X6S
0201

1

C1005

1UF

20%
4V

2

CERM-X6S
0201

1

C1028

1UF

20%
4V

2

CERM-X6S
0201

1

C1006

1UF

20%
4V

2

CERM-X6S
0201

1

C1029

1UF

20%
4V

2

CERM-X6S
0201

1

C1007

1UF

20%
4V

2

CERM-X6S
0201

1

C1030

1UF

20%
4V

2

CERM-X6S
0201

1

C1008

1UF

20%
4V

2

CERM-X6S
0201

1

C1031

1UF

20%
4V

2

CERM-X6S
0201

Vcc CPU Core Decoupling from 20140905 BOM

1

C1009

1UF

20%
4V

2

CERM-X6S
0201

1

C1032

1UF

20%
4V

2

CERM-X6S
0201

1

C1010

1UF

20%
4V

2

CERM-X6S
0201

1

C1033

1UF

20%
4V

2

CERM-X6S
0201

1

C1011

1UF

20%
4V

2

CERM-X6S
0201

1

C1034

1UF

20%
4V

2

CERM-X6S
0201

1

C1012

1UF

20%
4V

2

CERM-X6S
0201

1

C1035

1UF

20%
4V

2

CERM-X6S
0201

1

C1013

1UF

20%
4V

2

CERM-X6S
0201

1

C1036

1UF

20%
4V

2

CERM-X6S
0201

1

C1014

1UF

20%
4V

2

CERM-X6S
0201

1

C1037

1UF

20%
4V

2

CERM-X6S
0201

1

C1015

1UF

20%
4V

2

CERM-X6S
0201

1

C1038

1UF

20%
4V

2

CERM-X6S
0201

1

C1016

1UF

20%
4V

2

CERM-X6S
0201

1

C1039

1UF

20%
4V

2

CERM-X6S
0201

1

C1017

1UF

20%
4V

2

CERM-X6S
0201

1

C1040

1UF

20%
4V

2

CERM-X6S
0201

1

C1018

1UF

20%
4V

2

CERM-X6S
0201

1

C1041

1UF

20%
4V

2

CERM-X6S
0201

1

C1019

1UF

20%
4V

2

CERM-X6S
0201

1

C1042

1UF

20%
4V

2

CERM-X6S
0201

1

C1020

1UF

20%
4V

2

CERM-X6S
0201

1

C1043

1UF

20%
4V

2

CERM-X6S
0201

1

C1021

1UF

20%
4V

2

CERM-X6S
0201

1

C1044

1UF

20%
4V

2

CERM-X6S
0201

1

C1022

1UF

20%
4V

2

CERM-X6S
0201

1

C1045

1UF

20%
4V

2

CERM-X6S
0201

D

C

1

C1046

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C10A0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

1

C10A1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D0

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1047

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

1

2

1

2

C10A2

20UF

20%

2.5V
X6S-CERM
0402-1

1

C10D1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1048

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

1

C10A3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

1

C1049

1UF

20%
4V

2

CERM-X6S
0201

C10D2

20UF

20%

2.5V
X6S-CERM
0402-1

1

C10A4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D3

2

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1050

1UF

20%
4V

2

CERM-X6S
0201

1

C10A5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1051

1UF

20%
4V

2

CERM-X6S
0201

1

C10A6

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10D5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1052

1UF

20%
4V

2

CERM-X6S
0201

1

C10A7

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10D6

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10A8

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1053

1UF

20%
4V

2

CERM-X6S
0201

1

C10D7

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10A9

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1054

1UF

20%
4V

2

CERM-X6S
0201

1

2

NOSTUFF

1

C10E0

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C10B0

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1055

1UF

20%
4V

2

CERM-X6S
0201

1

C10B1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10E1

2

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1056

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C10B2

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10E2

20UF

2

20%

2.5V
X6S-CERM
0402-1

1

C1057

1UF

20%
4V

2

CERM-X6S
0201

1

C10B3

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10E3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

1

C10B4

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1058

1UF

20%
4V
CERM-X6S
0201

1

2

1

C1059

1UF

20%
4V

2

CERM-X6S
0201

C10B5

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1060

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C10B6

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10B7

20UF

20%

2.5V

2

X6S-CERM
0402-1

Noise Floor caps

1

C10N1

12PF

5%
25V

2

NP0-C0G
0201

1

C10N2

12PF

5%
25V

2

NP0-C0G
0201

1

C1061

1UF

20%
4V

2

CERM-X6S
0201

1

2

1

C10N3

12PF

5%
25V

2

NP0-C0G
0201

NOSTUFF

C10B8

20UF

20%

2.5V
X6S-CERM
0402-1

1

2

1

C10N4

12PF

5%
25V

2

NP0-C0G
0201

C1062

1UF

20%
4V
CERM-X6S
0201

NOSTUFF

1

C10B9

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10N5

12PF

5%
25V

2

NP0-C0G
0201

1

C10C0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10N6

12PF

5%
25V

2

NP0-C0G
0201

1

C10C1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

C10N7

12PF

5%
25V
NP0-C0G
0201

NOSTUFF

1

C10C3

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10C4

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10C5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10C6

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10C7

20UF

20%

2.5V

2

X6S-CERM
0402-1

C

B

PP1V2_S3_CPUDDR

109 116

1

C1068

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1069

220UF

20%
2V

23

ELEC
SM-COMBO

Place on bottom side of U0500.

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500

1

C1070

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1071

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1072

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1073

220UF

20%
2V

23

ELEC
SM-COMBO

NOSTUFF

1

C10Z1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10Z2

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10Z3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10Z4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C10Z5

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10Z6

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10Z7

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10Z8

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10Z9

20UF

20%

2.5V

2

X6S-CERM
0402-1

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

NOSTUFF

1

C10ZA

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10ZB

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C10ZC

20UF

20%

2.5V

2

X6S-CERM
0402-1

B

A

1

C1080

20UF

20%

2.5V

2

X6S-CERM
0402-1

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

C1090

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1081

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1091

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1082

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1092

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1083

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1093

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1084

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1094

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1085

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1095

20UF

20%

2.5V

2

X6S-CERM
0402-1

CPU VDDQ Decoupling

Intel recommendation: 10x 10uF 0402, 4x 22uF 0602
Apple Implementation:

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

PPVCCIO_S0_CPU

109

CPU VCCIO Decoupling

Intel recommendation: 3x 10uF 0402 (opposite CPU)
Apple Implementation:

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

Place near U0500 on bottom side

1

C1086

20UF

20%

2.5V

2

X6S-CERM
0402-1

Place near U0500 on bottom side

1

C1087

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1088

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1089

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C108A

20UF

20%

2.5V

2

X6S-CERM
0402-1

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU Decoupling 1 [10]

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/22/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

10 OF 145

SHEET

10 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

PPVCCGT_S0_CPU

109 116

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

1

2

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

Place on bottom side of U0500

C1100

1UF

20%
4V
CERM-X6S
0201

C1124

1UF

20%
4V
CERM-X6S
0201

1

C1101

1UF

20%
4V

2

CERM-X6S
0201

1

C1125

1UF

20%
4V

2

CERM-X6S
0201

CPU VGTSlice Decoupling

Vcc GT Slice Core Decoupling from 20140905 BOM

Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201
Apple Implementation:

1

C1102

1UF

20%
4V

2

CERM-X6S
0201

1

C1126

1UF

20%
4V

2

CERM-X6S
0201

1

C1103

1UF

20%
4V

2

CERM-X6S
0201

1

C1127

1UF

20%
4V

2

CERM-X6S
0201

1

C1104

1UF

20%
4V

2

CERM-X6S
0201

1

C1128

1UF

20%
4V

2

CERM-X6S
0201

1

C1105

1UF

20%
4V

2

CERM-X6S
0201

1

C1129

1UF

20%
4V

2

CERM-X6S
0201

1

C1106

1UF

20%
4V

2

CERM-X6S
0201

1

C1130

1UF

20%
4V

2

CERM-X6S
0201

1

C1107

1UF

20%
4V

2

CERM-X6S
0201

1

C1131

1UF

20%
4V

2

CERM-X6S
0201

1

C1108

1UF

20%
4V

2

CERM-X6S
0201

1

C1132

1UF

20%
4V

2

CERM-X6S
0201

1

C1109

1UF

20%
4V

2

CERM-X6S
0201

1

C1133

1UF

20%
4V

2

CERM-X6S
0201

Board Edge: 4x220uF, 7x 47uF rest on back side

1

C1110

1UF

20%
4V

2

CERM-X6S
0201

1

C1134

1UF

20%
4V

2

CERM-X6S
0201

1

C1111

1UF

20%
4V

2

CERM-X6S
0201

1

C1135

1UF

20%
4V

2

CERM-X6S
0201

1

C1112

1UF

20%
4V

2

CERM-X6S
0201

1

C1136

1UF

20%
4V

2

CERM-X6S
0201

1

C1113

1UF

20%
4V

2

CERM-X6S
0201

1

C1137

1UF

20%
4V

2

CERM-X6S
0201

1

C1114

1UF

20%
4V

2

CERM-X6S
0201

1

C1138

1UF

20%
4V

2

CERM-X6S
0201

1

C1115

1UF

20%
4V

2

CERM-X6S
0201

1

C1139

1UF

20%
4V

2

CERM-X6S
0201

1

C1116

1UF

20%
4V

2

CERM-X6S
0201

1

C1140

1UF

20%
4V

2

CERM-X6S
0201

1

C1117

1UF

20%
4V

2

CERM-X6S
0201

1

C1141

1UF

20%
4V

2

CERM-X6S
0201

1

C1118

1UF

20%
4V

2

CERM-X6S
0201

1

C1142

1UF

20%
4V

2

CERM-X6S
0201

1

C1119

1UF

20%
4V

2

CERM-X6S
0201

1

C1143

1UF

20%
4V

2

CERM-X6S
0201

1

C1120

1UF

20%
4V

2

CERM-X6S
0201

1

C1144

1UF

20%
4V

2

CERM-X6S
0201

1

C1121

1UF

20%
4V

2

CERM-X6S
0201

1

C1145

1UF

20%
4V

2

CERM-X6S
0201

1

C1122

1UF

20%
4V

2

CERM-X6S
0201

1

C1146

1UF

20%
4V

2

CERM-X6S
0201

1

C1123

1UF

20%
4V

2

CERM-X6S
0201

1

C1147

1UF

20%
4V

2

CERM-X6S
0201

D

C

1

C1148

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11A0

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11F0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1149

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11A1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11F1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11A2

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1150

1UF

20%
4V

2

CERM-X6S
0201

1

C11F2

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11A3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1151

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11A4

2

NOSTUFF

1

C11F3

20UF

20%

2.5V

2

X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1152

1UF

2

NOSTUFF

1

C11A5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11F4

20UF

20%

2.5V

2

X6S-CERM
0402-1

20%
4V
CERM-X6S
0201

NOSTUFF

1

C11A6

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11F5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1153

1UF

20%
4V

2

CERM-X6S
0201

1

C11A7

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11F6

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1154

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11A8

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11F7

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1155

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11A9

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11B0

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11E0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1156

1UF

20%
4V

2

CERM-X6S
0201

1

C11B1

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11E1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1157

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11B2

2

NOSTUFF

1

C11E2

2

20UF

20%

2.5V
X6S-CERM
0402-1

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1158

1UF

20%
4V

2

CERM-X6S
0201

1

C11B3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11E3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1159

1UF

2

NOSTUFF

1

C11B4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

20%
4V
CERM-X6S
0201

1

2

C11E4

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1160

1UF

2

NOSTUFF

C11B5

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

1

C11E5

20UF

2

20%
4V
CERM-X6S
0201

NOSTUFF

1

C11B6

20UF

20%

2.5V

2

X6S-CERM
0402-1

20%

2.5V
X6S-CERM
0402-1

1

C1161

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11B7

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1162

1UF

20%
4V

2

CERM-X6S
0201

1

C11B8

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11B9

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1163

1UF

20%
4V

2

CERM-X6S
0201

1

C11C0

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1164

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11C1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C1165

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11C2

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

NOSTUFF

1

C11C3

20UF

20%

2.5V

2

X6S-CERM
0402-1

C1166

1UF

20%
4V
CERM-X6S
0201

1

C11C4

2

20UF

20%

2.5V
X6S-CERM
0402-1

1

C1167

1UF

20%
4V

2

CERM-X6S
0201

1

C11C5

2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

1

C11C6

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11C7

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

NOSTUFF

1

C11C8

20UF

20%

2.5V

2

X6S-CERM
0402-1

C11D4

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

1

C11D3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11C9

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

2

1

C11D0

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

C11D2

20UF

20%

2.5V
X6S-CERM
0402-1

NOSTUFF

1

C11D1

20UF

20%

2.5V

2

X6S-CERM
0402-1

C

1

C1168

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1169

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1170

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1171

220UF

20%
2V

23

ELEC
SM-COMBO

1

C1172

220UF

20%
2V

23

ELEC
SM-COMBO

B

PPVCCSA_S0_CPU

109

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

1

C11H0

1UF

20%
4V

2

CERM-X6S
0201

1

C11H1

1UF

20%
4V

2

CERM-X6S
0201

1

C11H2

1UF

20%
4V

2

CERM-X6S
0201

NOSTUFF

1

C11I0

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11I1

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11I2

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11I3

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11I4

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11I5

20UF

20%

2.5V

2

X6S-CERM
0402-1

1

C11I6

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

1

C11I7

20UF

20%

2.5V

2

X6S-CERM
0402-1

CPU VCCSTG Decoupling

PP1V0_S0SW

6 8 18 110

Place near U0500 on bottom side

Place near U0500 on bottom side

1

2

C11L1

1UF

20%
4V
CERM-X6S
0201

1

C11L2

1UF

20%
4V

2

CERM-X6S
0201

CPU VCCPLL and VCCST Decoupling

PP1V0_S3

8 110

1

C11M1

1UF

20%
4V

2

CERM-X6S
0201

PP1V0_S3

6 8 110

1

C11M2

1UF

20%
4V

2

CERM-X6S
0201

B

A

Place near U0500 on bottom side

NOSTUFF

1

C11J0

47UF

20%

6.3V

2

POLY-TANT
0805

NOSTUFF

1

C11J1

47UF

20%

6.3V

2

POLY-TANT
0805

CPU VCCSA Decoupling

1

C11K9

220UF

20%
2V

23

ELEC
SM-COMBO

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

8 7 5 4 2 1

Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_

2x 220uF, 1x 22uF on board edge, everything else on back side

Apple Implementation:

BOM_COST_GROUP=CPU & CHIPSET

36

Place near U0500 on bottom side

SYNC_MASTER=X363_SEAN SYNC_DATE=02/01/2016

PAGE TITLE

CPU Decoupling 2 [11]

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0
dvt-fab10
11 OF 145
11 OF 121

A

D

D

48

48

IN

OUT

NOSTUFF

R1204

0

5%

1/20W

MF

0201

345678

2 1

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 4 OF 12

SYSTEM POWER MANAGEMENT

SMC_PCH_SUSACK_L

115 46 18 12

114 73 46

1

115 70

2

114 35 20

115 73 46 18

IN

IN

IN

OUT

IN

PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK

PLT_RST_L
PM_RSMRST_L
SMC_PCH_SUSWARN_L

48 12

IN

PM_PWRBTN_L
SSD_SR_EN_L

12

AL15

AJ11

AG23

AF12

AJ16

AM10 AK9

AL12

GPP_A15/SUSACK*

AJ4

SYS_RESET*

AK3

SYS_PWROK
PCH_PWROK

GPP_B13/PLTRST*
RSMRST*

GPP_A13/SUSWARN*

/SUSPWRDNACK

GPD3/PWRBTN*
GPD1/ACPRESENT

(IPU)

DRAM_RESET*

(OD)

(IPD-DeepSx)

GPP_A14/SUS_STAT*/ESPI_RESET*

(IPU-RSMRST#)

DSW_PWROK

WAKE*

GPP_A8/CLKRUN*

GPD8/SUSCLK

GPD10/SLP_S5*

GPD5/SLP_S4*
GPD4/SLP_S3*

GPD6/SLP_A*

AM11
AF8
AG12
AK14
AM15
AH12
AG10
AK10

AG11

NC_PCH_DRAM_RESET_L
PM_DSW_PWRGD
PCIE_WAKE_L
LPC_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
NC_PCH_SLP_A_L

20

IN

BI

OUT

OUT

OUT

OUT

OUT

20

46

47

PP3V3_S0

12 13 15 110

46

IN

BT_LOW_PWR_L

19 12

46 12

73 46 20 12

73 70 46 43 20 12

1

R1205

100K

5%
1/20W
MF
201

2

114 101 89 76 73 70 46 27 20 12

35 12

R1213

10K

1 2

5% MF 2011/20W

D

C

PP3V0_G3H

1

R1201

1M

5%
1/20W
MF
201

2

R1202

20K

5%

1/20W

MF

201

C1202

1UF

10%
10V
X5R

402-1

103 46 29 12

70 46 20 12

16 17 109

1

2

1

R1203

20K

5%
1/20W
MF
201

2

PCH_SRTCRST_L
PCH_INTRUDER_L

RTC_RESET_L

12

12

12

12

12

12

IN

OUT

59 12

20

IN

20

OUT

PCH_INTRUDER_L
PCH_SRTCRST_L
RTC_RESET_L

PM_BATLOW_L
PM_SLP_S0_L
NC_PCH_SLP_WLAN_L

111

NC_PCH_PME_L

20

AUD_PWR_EN

SYSCLK_CLK32K_PCH
NC_PCH_CLK32K_RTCX2

(IPU)

AM12
AM22

AH10
AG16
AG18

AL8

AM8

AJ10

AJ8

AH8

GPD0/BATLOW*
GPP_B12/SLP_S0*
GPD9/SLP_WLAN*
GPP_A11/PME*
GPP_A12/BMBUSY*/ISH_GP6

/SX_EXIT_HOLDOFF*

RTCX1
RTCX2

INTRUDER*

RTC

SRTCRST*
RTCRST*

ESPI/LPC

SLP_SUS*

SLP_LAN*

GPD2/LAN_WAKE*

GPD11/LANPHYPC

GPP_B2/VRALERT*

GPP_A0/RCIN*/ESPI_ALERT1*

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME*/ESPI_CS0*

GPP_A6/SERIRQ/ESPI_CS1*

GPP_A7/PIRQA*/ESPI_ALERT0*

GPD7/RSVD

OMIT_TABLE

1

2

1

C1203

1UF

10%
10V

2

X5R
402-1

113 35

113 35

OUT
OUT

PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P

J5

CLKOUT_PCIE_N0

J6

CLKOUT_PCIE_P0

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 2 OF 12

XTAL24_IN

XTAL24_OUT

AH13
AK11
AL9
AJ13
AH20

AM13
AK12
AK13
AG20
AM14
AL14
AH14
AJ18

AL11

B4
B3

PM_SLP_SUS_L
NC_PCH_SLP_LAN_L
SMC_WAKE_SCI_L
NC_PCH_LANPHYPC
BT_LOW_PWR_L

PCH_RCIN_L_PU
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L

R1440
R1441
R1442
R1443
R1444

LPC_SERIRQ
SMC_RUNTIME_SCI_L

NC_PCH_GPD7

SYSCLK_CLK24M_PCH
NC_PCH_CLK24M_XTALOUT

OUT

20

IN

20

OUT

33
33
33

BI

IN

20

73 70 12

46 12

35 12

12

1 2
1 2
1 2
1 2
1 2

46 12

46 12

IN

OUT

1/20W 201MF5%
1/20W 2015% MF
1/20W 2015%
1/20W5% MF33201
1/20W MF332015%

20

MF

PLACE_NEAR=U1100.AL14:1.25mm

113 20

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

BI
BI
BI

BI

OUT

PP3V3_S4

110

SSD_SR_EN_L

12

89 46

89 46

89 46

89 46

89 46

115 46 18 12

PM_SYSRST_L

R1211

PP3V3_SUS

14 16 17 110

R1247

100K

3.0K

1 2

2015% 1/20W MF

1 2

2011/20W MF5%

C

PP3V3_SUS

15 16 17 110

PP3V3_S5

16 17 110

B

111

111

111

111

27

27

101

101

113 87

113 87

111

111

111

111

111

111

111

111

111

111

111

111

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

NC_CLKOUT_PCIE_1_N
NC_CLKOUT_PCIE_1_P

NC_CLKOUT_PCIE_2_N
NC_CLKOUT_PCIE_2_P

PCIE_CLK100M_TBT_X_N
PCIE_CLK100M_TBT_X_P

PCIE_CLK100M_TBT_T_N
PCIE_CLK100M_TBT_T_P

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

NC_CLKOUT_PCIE_6_N
NC_CLKOUT_PCIE_6_P

EG_PEG_CLK100M_N
EG_PEG_CLK100M_P

NC_CLKOUT_PCIE_8_N
NC_CLKOUT_PCIE_8_P

NC_CLKOUT_PCIE_9_N
NC_CLKOUT_PCIE_9_P

NC_CLKOUT_PCIE_10_N
NC_CLKOUT_PCIE_10_P

NC_CLKOUT_PCIE_11_N
NC_CLKOUT_PCIE_11_P

F2

CLKOUT_PCIE_N1

F1

CLKOUT_PCIE_P1

K6

CLKOUT_PCIE_N2

K5

CLKOUT_PCIE_P2

F3

CLKOUT_PCIE_N3

F4

CLKOUT_PCIE_P3

G2

CLKOUT_PCIE_N4

G3

CLKOUT_PCIE_P4

E2

CLKOUT_PCIE_N5

E1

CLKOUT_PCIE_P5

K2

CLKOUT_PCIE_N6

K3

CLKOUT_PCIE_P6

L1

CLKOUT_PCIE_N7

L2

CLKOUT_PCIE_P7

M3

CLKOUT_PCIE_N8

M4

CLKOUT_PCIE_P8

M2

CLKOUT_PCIE_N9

M1

CLKOUT_PCIE_P9

R6

CLKOUT_PCIE_N10

R7

CLKOUT_PCIE_P10

T6

CLKOUT_PCIE_N11

T5

CLKOUT_PCIE_P11

CLOCK SIGNALS

GPP_A9/CLKOUT_LPC0

GPP_A10/CLKOUT_LPC1

GPP_A16/CLKOUT_48

CLKOUT_CPUBCLK_N
CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N
CLKOUT_CPUNSSC_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

XCLK_BIASREF

/ESPI_CLK

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

E4

AJ14

AH15

AL16

L6
L5

J3
J4

H1
H2

J1
J2

PCH_DIFFCLK_BIASREF

PLACE_NEAR=U1100.E4:1.25mm

PLACE_NEAR=U1100.AJ14:1.4mm

LPC_CLK24M_DPMUX_UC_R

CAMERA_PWR_EN

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP

CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P

CPU_CLK24M_NSSC_CLK_N
CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N
CPU_CLK100M_PCIBCLK_P

R1234

2.7K

2 1

1%

1/20W

MF

201

22

20

PP1V0_SUS

R1235

1 2

12

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

PCIE_WAKE_L

19 12

SMC_WAKE_SCI_L

46 12

PM_PWRBTN_L

12 48

103 46 29 12

110

LPC_CLK24M_SMCLPC_CLK24M_SMC_R

1/20W MF 2011%

115 113 18

115 113 18

113 6

113 6

113 6

113 6

113 6

113 6

R1238

R1240

R1239

46

BI

114 101 89 76 73 70 46 27

R1244

R1243

R1242

R1241

73 46 20 12

73 70 46 43 20 12

70 46 20 12

73 70 12

R1246

R1245

PM_BATLOW_L

SMC_RUNTIME_SCI_L

46 12

LPC_CLKRUN_L

46 12

PCH_RCIN_L_PU

12

LPC_SERIRQ

46 12

AUD_PWR_EN

59 12

CAMERA_PWR_EN

12

AP_S0IX_WAKE_L

19 12

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

20 12

PM_SLP_S0_L
AP_S0IX_WAKE_SEL

19 12

PM_SLP_SUS_L

PP3V3_S0

R1248
R1209
R1210
R1212

R1207
R1208
R1251

PP3V3_S0

12 13 15 110

R1206
R1214
R1215
R1216

R1230
R1231
R1232
R1233
R1236
R1237

14 20 73 110

100K
100K

1K

10K

100K

10K

100K

10K

100K
100K
100K

100K
100K
100K
100K
100K
100K

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

5% MF

1/20W 201
1/20W

5% 201MF

1/20W

5% MF 2011/20W

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201
5% 1/20W MF
5% MF1/20W 201

1/20W

1/20W MF 201

5%
5%

1/20W MF 201

5%

MF 2015%

201MF1/20W5%

MF1/20W5% 201

201

201MF1/20W5%
201MF5%
2011/20W MF5%

201MF1/20W

B

A

111

111

20

20

111

111

111

111

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

NC_CLKOUT_PCIE_12_N
NC_CLKOUT_PCIE_12_P

NC_CLKOUT_PCIE_13_N
NC_CLKOUT_PCIE_13_P

NC_CLKOUT_PCIE_14_N
NC_CLKOUT_PCIE_14_P

NC_CLKOUT_PCIE_15_N
NC_CLKOUT_PCIE_15_P

N3

CLKOUT_PCIE_N12

N2

CLKOUT_PCIE_P12

P5

CLKOUT_PCIE_N13

P6

CLKOUT_PCIE_P13

N5

CLKOUT_PCIE_N14

N6

CLKOUT_PCIE_P14

M6

CLKOUT_PCIE_N15

M7

CLKOUT_PCIE_P15

PCI EXPRESS

CLOCKS & CONTROL

GPP_B5/SRCCLKREQ0*
GPP_B6/SRCCLKREQ1*
GPP_B7/SRCCLKREQ2*
GPP_B8/SRCCLKREQ3*
GPP_B9/SRCCLKREQ4*

GPP_B10/SRCCLKREQ5*

GPP_H0/SRCCLKREQ6*
GPP_H1/SRCCLKREQ7*
GPP_H2/SRCCLKREQ8*

GPP_H3/SRCCLKREQ9*
GPP_H4/SRCCLKREQ10*
GPP_H5/SRCCLKREQ11*
GPP_H6/SRCCLKREQ12*
GPP_H7/SRCCLKREQ13*
GPP_H8/SRCCLKREQ14*
GPP_H9/SRCCLKREQ15*

AL20
AM19
AK20
AL19
AH22
AK22

AM25
AH26
AL25
AF26
AK26
AL26
AJ27
AH27
AM26
AK27

AP_CLKREQ_L_R
ENETSD_CLKREQ_L
CAMERA_CLKREQ_L
TBT_X_CLKREQ_L_R
TBT_T_CLKREQ_L_R
SSD_CLKREQ_L_R

TBT_W_CLKREQ_L
EG_CLKREQ_OUT_L
AP_S0IX_WAKE_SEL
AP_S0IX_WAKE_L
TBT_X_CIO_PWR_EN
TBT_T_CIO_PWR_EN
TBT_W_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_USB_PWR_EN
TBT_W_USB_PWR_EN

111

OUT

47K

201

1 2

47K

201

100K

100K

100K

100K

100K

100K

1 2

1 2

1 2

1 2

1 2

1 2

201

1 2

201

201

201

201

BOM_COST_GROUP=CPU & CHIPSET

201

201

IN
IN

IN

OUT
OUT
OUT
OUT
OUT
OUT

20

20

20

29

103

20

29

103

20

PAGE TITLE

PCH RTC/HDA/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

12 OF 145

SHEET

12 OF 121

A

47K

1 2

20

BI

20

IN

20

IN

20

BI

19 12

IN

19 12

8 7 5 4 2 1

36

D

PP3V3_S0

PP3V3_S0

12 13 15 110

12 13 15 110

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

113 5

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN
IN

DMI_S2N_N<0>
DMI_S2N_P<0>

DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_S2N_N<2>
DMI_S2N_P<2>

DMI_S2N_N<3>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_P<0>

DMI_N2S_N<1>
DMI_N2S_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>

DMI_N2S_N<3>
DMI_N2S_P<3>

B19
A19

C20
B20

A21
B21

C22
D22

F20
F19

G19

F21

E21
G22

F22

DMI_TXN0
DMI_TXP0

DMI_TXN1
DMI_TXP1

DMI_TXN2
DMI_TXP2

DMI_TXN3
DMI_TXP3

DMI_RXN0
DMI_RXP0

DMI_RXN1
DMI_RXP1

DMI_RXN2
DMI_RXP2

DMI_RXN3
DMI_RXP3

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 5 OF 12

DMI

CPU/MISC

PROCPWRGD

THERMTRIP*

PECI

GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1

GPP_B23/SML1ALERT*/PCHHOT*

CPU_TRST*

PLTRST_PROC*

PRDY*

PREQ*

PCH_TRIGIN

PCH_TRIGOUT

PM_DOWN

PM_SYNC

AC4
AC5
AB5
AH21

AM21
W28
U29
AK23

AF2E20
AC6
AE4
AE6
AD7

AB6
AD5

AE7

345678

PCH_PROCPWRGD
PM_THRMTRIP_L_R
PCH_PECI

BT_PWRRST_L

BT_TIMESTAMP

XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_B2

NC_PCH_STRP_BSSB_SEL_GPIO

XDP_CPU_TRST_L

CPU_RESET_L

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_PCH_TRIGGER

PCH_CPU_TRIGGER_R PCH_CPU_TRIGGER

PLACE_NEAR=U1100.AB6:1.27mm 2015% MF

CPU_PCH_PM_DOWN

PM_SYNC_R

PLACE_NEAR=U1100.AE7:1.27mm 1/20W 201

R1308

R1309
R1315

R1314

R1319

0

620

13

13

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

1 2

1 2

1 2
1 2

35 13

18

14

20 13

6

5

IN

1 2

5

IN

5%
MF

5% 1/20W

115 18 6

115 18 6

115 18 6

33

33

5% MF

1/20W

0201

201MF

1/20W5%

201MF

1/20W

2 1

CPU_PWRGD

PM_THRMTRIP_L
CPU_PECI

NO STUFF

1

R1331

100K

5%
1/20W
MF
201

2

PM_SYNC

OUT

OUT

OUT

IN

BI

6

48 47 46 6

47 6

D

5

6

C

PP3V3_SUS

R1318
R1341

R1304
R1300
R1303

R1307

R1316

R1301

R1302

R1305

R1306

R1317

1K
1K

47K

47K

1K

150K

100K

47K
47K
47K

47K

100K

1 2
1 2

1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2

OMIT

1/20W 201MF5%

1/20W 201MF5%

1/20W

5% MF 201

1/20W

5% MF 201

1/20W

5% 1/20W

1/20W

5%

1/20W5% MF 201

1/20W

5% 1/20W 201MF

16 17 110

NC_PCH_STRP_BSSB_SEL_GPIO

SPI_CS0_R_L

TPAD_SPI_CS_L

AUD_SPI_CS_L
AUD_SPI_MOSI

MF5% 201

MF 201

MF5% 201

2011/20W MF

TPAD_SPI_MOSI

BT_PWRRST_L

AUD_SPI_CLK
AUD_SPI_MISO
TPAD_SPI_CLK

MF 2015%

TPAD_SPI_MISO

BT_TIMESTAMP

MF 2011/20W5%

13 20

57 13

43 13

13

13

13

13

13

35 13

1

R1326

OMIT_TABLE

U1100

SKL-PCH-SFF

150K

5%
1/20W
MF
201

2

H65946

FCBGA

A25

NC

114 43 13

114 43 13

114 43 13

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

AF24

AH11

AA6
AA7

AL4
AL5
B11

B25
C11
C19

C2

D19

D2
H5
H6

W5

Y5
Y6

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

SYM 1 OF 12

RSVD & TP PINS

AUDIO

GPP_D5/I2S0_SFRM

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

DISPA_BCLK

GPP_D6/I2S0_TXD

GPP_D7/I2S0_RXD

GPP_D8/I2S0_SCLK

HDA_BCLK

HDA_SYNC

HDA_SDI0
HDA_SDI1

HDA_SDO

HDA_RST*

DISPA_SDI

DISPA_SDO

AJ7
AM6
AK5

AK6
AJ6
AM5
AE3

AE1
AD4

AC30
AD31
AE30
AC31
AB32
AB31
AA33
AA32

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

PCH_DISPA_BCLK_R

PCH_DISPA_SDI

PCH_DISPA_SDO_R

BT_I2S_SYNC_R
BT_I2S_R2D_R
BT_I2S_D2R_R
BT_I2S_CLK_R

TP_PCH_DMIC_CLK1

TP_PCH_DMIC_DATA1

TP_PCH_DMIC_CLK0

TP_PCH_DMIC_DATA0

R1327
R1328
R1329
R1330

20

20

20

20

33

1/20WMF 5%201

201 1/20WMF

201 MF 1/20W 5% PLACE_NEAR=U1100.AJ6:1.5mm

1/20W201 5%MF PLACE_NEAR=U1100.AM5:2.27mm
1/20WMF201 PLACE_NEAR=U1100.AE3:1.27mm

MF201 5%

1/20W PLACE_NEAR=U1100.AD4:1.27mm

201

1/20WMF 5%201

201 1/20WMF 5%

MF201 1/20W 5%

5%

5%MF 1/20W

12
12

12
12
12

12

12
12
12
12

R1310

PLACE_NEAR=U1100.AJ7:1.27mm

33

R1311

PLACE_NEAR=U1100.AM6:1.27mm5%

33

R1313

33

R1312

33

R1320

33

R1321

33
33
33
33

HDA_BIT_CLK

HDA_SYNC

HDA_SDIN0

NC_HDA_SDIN1

HDA_SDOUT
HDA_RST_L

PCH_DISPA_BCLK

PCH_DISPA_SDO

BT_I2S_SYNC
BT_I2S_R2D
BT_I2S_D2R
BT_I2S_CLK

115

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

58

58

58

58

58

20

20

IN

20

35

BI

35

35

IN

35

BI

C

B

115 18

115 18

115 18

115 18

20

NC_PCH_TP1_AH9

20

NC_PCH_TP1_AG9

20

ITP_PMODE

18

IN

IN

OUT

IN

IN

XDP_PCH_TCK
XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
PCH_JTAGX

57

OUT

57 13

57 18

57 18

111

111

57

57

OUT

OUT

OUT

BI

BI

BI

BI

SPI_CLK_R
SPI_CS0_R_L
NC_SPI_CS1_L
NC_SPI_CS2_L
SPI_MOSI_R
SPI_MISO
SPI_IO<2>
SPI_IO<3>

(IPD)

(IPU)

(Undriven)

(IPU)

AJ26
AJ24

AK25
AG25
AM23
AH25
AM24

AK24

AH9

TP1

AG9

TP2

AF1

ITP_PMODE

AG6

JTAG_TCK

AF5

JTAG_TDI

AF6

JTAG_TDO

AG5

JTAG_TMS

AF4

JTAGX

SPI0_CLK
SPI0_CS0*
SPI0_CS1*
SPI0_CS2*
SPI0_MOSI
SPI0_MISO
SPI0_IO2
SPI0_IO3

(IPU)

(IPU)
(IPU)

(IPD)

(IPU)

(IPU)
(IPU)

JTAG

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 3 OF 12

GSPIC-LINK

SPI

GPP_B15/GSPI0_CS*

GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS*

GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

AK21
AJ21
AJ20
AK19
AL23
AJ23
AH23
AH24

AUD_SPI_CS_L
AUD_SPI_CLK
AUD_SPI_MISO
AUD_SPI_MOSI
TPAD_SPI_CS_L_R
TPAD_SPI_CLK_R
TPAD_SPI_MISO_R
TPAD_SPI_MOSI_R

13

13

13

13

201
201
201
201 MF 5%

1/20W 5%MF
MF 5%1/20W
MF 1/20W 5%

1/20W

B

33

12
12
12
12

33

0

33

R1322
R1323
R1324
R1325

TPAD_SPI_CS_L
TPAD_SPI_CLK
TPAD_SPI_MISO
TPAD_SPI_MOSI

OUT
OUT

OUT

43 13

114 43 13

IN

114 43 13

114 43 13

A

CL_CLK

CL_DATA

CL_RST*

AG3
AG2
AH4

8 7 5 4 2 1

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

115

115

115

36

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

PCH DMI/FDI/PM/GFX/PCI

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0
dvt-fab10
13 OF 145
13 OF 121

A

D

345678

2 1

D

C

29

29

29

29

114

114

114

114

IN
IN

OUT
OUT

IN
IN

OUT
OUT

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_TEST_D2R_N
USB3_TEST_D2R_P

USB3_TEST_R2D_N
USB3_TEST_R2D_P

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

F5

USB3_1_RXN

G5

USB3_1_RXP

D4

USB3_1_TXN

D5

USB3_1_TXP

G6

USB3_2_RXN/SSIC_1_RXN

F6

USB3_2_RXP/SSIC_1_RXP

B6

USB3_2_TXN/SSIC_1_TXN

A6

USB3_2_TXP/SSIC_1_TXP

G7

USB3_3_RXN/SSIC_2_RXN

H7

USB3_3_RXP/SSIC_2_RXP

C6

USB3_3_TXN/SSIC_2_TXN

B7

USB3_3_TXP/SSIC_2_TXP

D7

USB3_4_RXN

E7

USB3_4_RXP

C8

USB3_4_TXN

B8

USB3_4_TXP

F8

USB3_5_RXN

G8

USB3_5_RXP

B9

USB3_5_TXN

A8

USB3_5_TXP

F9

USB3_6_RXN

G9

USB3_6_RXP

C9

USB3_6_TXN

D9

USB3_6_TXP

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 7 OF 12

USB3

USB2

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2N_11
USB2P_11

USB2N_12
USB2P_12

V4
V3

W2
W3

U6
U7

Y1
Y2

U4
T4

AA4
AA3

T1
T2

AA2
AA1

R3
R4

AB3
AB2

R2
R1

AC1
AC2

NC
NC

USB_UPC_PCH_TA_N
USB_UPC_PCH_TA_P

USB_CAMERA_DFR_N
USB_CAMERA_DFR_P

USB_TEST_N
USB_TEST_P

USB_UPC_PCH_XB_N
USB_UPC_PCH_XB_P

NC_USB2N_6
NC_USB2P_6

USB_UPC_PCH_TB_N
USB_UPC_PCH_TB_P

NC_USB2N_8
NC_USB2P_8

NC_USB2N_9
NC_USB2P_9

NC_USB2N_10
NC_USB2P_10

USB_UPC_PCH_XA_N
USB_UPC_PCH_XA_P

NC_USB2N_12
NC_USB2P_12

OMIT_TABLE

U1100

G14

NC
NC

103

BI

103

BI

114

114

BI
BI

BI
BI

BI
BI

113 38

113 38

29

29

103

103

29

29

PCIE_AP_D2R_N

14

PCIE_AP_D2R_P

14

BI
BI

BI
BI

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

PCIE5_RXN

F14

PCIE5_RXP

D14

PCIE5_TXN

C14

PCIE5_TXP

E15

PCIE6_RXN

F15

PCIE6_RXP

A15

PCIE6_TXN

B15

PCIE6_TXP

G15

PCIE7_RXN

G16

PCIE7_RXP

C16

PCIE7_TXN

B16

PCIE7_TXP

F18

PCIE8_RXN

E18

PCIE8_RXP

B18

PCIE8_TXN

C18

PCIE8_TXP

F25

PCIE11_RXN

G25

PCIE11_RXP

A24

PCIE11_TXN

B24

PCIE11_TXP

F26

PCIE12_RXN

E26

PCIE12_RXP

C25

PCIE12_TXN

D25

PCIE12_TXP

E10

PCIE1_RXN/USB3_7_RXN

F10

PCIE1_RXP/USB3_7_RXP

SKL-PCH-SFF

H65946

FCBGA

SYM 8 OF 12

PCIE/SATA/USB3

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE13_RXN/SATA0B_RXN

PCIE13_RXP/SATA0B_RXP
PCIE13_TXN/SATA0B_TXN

PCIE13_TXP/SATA0B_TXP

PCIE14_RXN/SATA1B_RXN

PCIE14_RXP/SATA1B_RXP
PCIE14_TXN/SATA1B_TXN

PCIE14_TXP/SATA1B_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

F23
E23

B22
A22

E24
F24

B23
C23

D27
D28

B26
C26

E28
F27

A27
B27

H27
G27

A28
B28

G28
F29

B29
C29

G29
G30

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

14 113

14 113

D

C

B

PP3V3_SUS

12 16 17 110

USB2N_13
USB2P_13

USB2N_14
USB2P_14

GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

USB2_COMP

USB2_ID

USB2_VBUSSENSE

P1
P2

AD2
AD1

W30
U31
U33
V31

P30
N29
P31
L29

V1

USB2_COMP

W6
U2

NC_USB2N_13
NC_USB2P_13

NC_USB2N_14
NC_USB2P_14

XDP_PCH_OBSDATA_C0
XDP_PCH_OBSDATA_C1
XDP_PCH_OBSDATA_C2
XDP_PCH_OBSDATA_C3

NC_PCH_GPP_F15
NC_PCH_GPP_F16
NC_PCH_GPP_F17
NC_PCH_GPP_F18

USB2_ID
USB2_VBUSSENSE

14 29

14 29

14 103

14 103

111

IN

111

IN

111

IN

111

IN

PLACE_NEAR=U1100.V1:10.0mm

1

R1410

1K

5%
1/20W
MF
201

2

1

R1411

1K

5%
1/20W
MF
201

2

1

R1470

113

1%
1/20W
MF
201

2

18

18

18

18

18

113 35

113 35

14

14

14

OUT
OUT
OUT
OUT
OUT

OUT
OUT

PCIE_AP_R2D_C_N

XDP_PCH_OBSFN_C0
XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_A1

XDP_PCH_OBSDATA_D0
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSFN_C1

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

B12

PCIE1_TXN/USB3_7_TXN

A12

PCIE1_TXP/USB3_7_TXP

E11

PCIE2_RXN/USB3_8_RXN

F11

PCIE2_RXP/USB3_8_RXP

D12

PCIE2_TXN/USB3_8_TXN

C12

PCIE2_TXP/USB3_8_TXP

G12

PCIE3_RXN/USB3_9_RXN

F12

PCIE3_RXP/USB3_9_RXP

B13

PCIE3_TXN/USB3_9_TXN

C13

PCIE3_TXP/USB3_9_TXP

E13

PCIE4_RXN/USB3_10_RXN

F13

PCIE4_RXP/USB3_10_RXP

B14

PCIE4_TXN/USB3_10_TXN

A14

PCIE4_TXP/USB3_10_TXP

W31

GPP_E0/SATAXPCIE0/SATAGP0

Y30

GPP_E1/SATAXPCIE1/SATAGP1

W29

GPP_E2/SATAXPCIE2/SATAGP2

U30

GPP_F0/SATAXPCIE3/SATAGP3

T32

GPP_F1/SATAXPCIE4/SATAGP4

T30

GPP_F2/SATAXPCIE5/SATAGP5

T28

GPP_F3/SATAXPCIE6/SATAGP6

R32

GPP_F4/SATAXPCIE7/SATAGP7

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

PCIE19_RXN/SATA6_RXN
PCIE19_RXP/SATA6_RXP

PCIE19_TXN/SATA6_TXN

PCIE19_TXP/SATA6_TXP

PCIE20_RXN/SATA7_RXN
PCIE20_RXP/SATA7_RXP

PCIE20_TXN/SATA7_TXN

PCIE20_TXP/SATA7_TXP

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_F5/DEVSLP3
GPP_F6/DEVSLP4
GPP_F7/DEVSLP5
GPP_F8/DEVSLP6
GPP_F9/DEVSLP7

B30
C30

H29
H28

C31
B31

J29
J28

D32
C32

K28
K29

E31
E32

V32
V33
W33

T33
P27
P29
R29
N28

PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0>PCIE_AP_R2D_C_P

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>

XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1

TBT_X_PCI_RESET_L
TBT_T_PCI_RESET_L
SSD_RESET_L
NC_HDD_PWR_EN
SSD_PWR_EN

14

OUT
OUT

OUT
OUT
OUT
OUT
OUT

14

14

14

14

14 113

14 113

18

18

20

20

20

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

113 87

87

113 77

77

113 77

77

113 77

77

B

115 114 87 20

115 114 87 14

A

13

OUT

R1462
R1460

R1461
R1420
R1421

XDP_PCH_OBSFN_C0

14

XDP_PCH_OBSDATA_A0

14

XDP_PCH_OBSDATA_A1

14

XDP_PCH_OBSDATA_B1

14

XDP_PCH_OBSDATA_B2
XDP_PCH_OBSDATA_B3

14

XDP_PCH_OBSDATA_C0

14 29

XDP_PCH_OBSDATA_C1

14 29

XDP_PCH_OBSDATA_C2

14 103

XDP_PCH_OBSDATA_C3

14 103

PP3V3_S0

100K

10K
10K
10K
10K

1 2

1 2
1 2
1 2
1 2

12 20 73 110

1/20W

5% 201MF

1/20W5%
1/20W 201MF5%

5% 1/20W

1/20W MF 2015%

1

TP

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

TP1882

TP

TP1883

TP

TP1884

TP

TP1885

TP

TP1886

TP

TP1887

MF 201

MF 201

XDP_PCH_OBSDATA_C0
XDP_PCH_OBSDATA_C1
XDP_PCH_OBSDATA_C2
XDP_PCH_OBSDATA_C3

U27

PAGE TITLE

XDP_PCH_OBSDATA_B3

14

A

SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC

SSD_PWR_EN

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

XDP_PCH_OBSDATA_C2
XDP_PCH_OBSDATA_C3

14 29

14 29

14 103

14 103

TBT_POC_RESET
NC_PCH_CAM_RESET
NC_PCH_CAM_EXT_BOOT_L
NC_WOL_EN

PCH_PCIE_RCOMPP

1

R1400

100

1%
1/20W
MF
201

2

103 29 15

20

20

20

OUT
OUT
OUT
OUT

PCH_PCIE_RCOMPN

115 114 87 14

14 113

14 113

14

14

14

14

14 113

14 113

14

14

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_AP_D2R_N
PCIE_AP_D2R_P

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

T29

GPP_F10/SCLOCK

R31

GPP_F11/SLOAD

M29

GPP_F12/SDATAOUT1

P33

GPP_F13/SDATAOUT0

A10

PCIE_RCOMPP

B10

PCIE_RCOMPN

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_AP_D2R_N
PCIE_AP_D2R_P

GPP_E8/SATALED*

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

113 87

113 87

113 77

113 77

113 77

113 77

113 77

113 77

113 35

113 35

PCH PCI-E/USB

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

BI
BI
BI
BI

18

18

18

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

18

BOM_COST_GROUP=CPU & CHIPSET

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

14 OF 145

SHEET

14 OF 121

D

8 7 5 4 2 1

36

345678

2 1

D

C

RAMCFG0:L

R1530

1K

5%

1/20W

MF

201

1

2

RAMCFG1:L

1

R1531

1K

5%
1/20W
MF
201

2

RAMCFG2:L

R1532

1K

5%

1/20W

MF

201

RAMCFG3:L

1

1

2

R1533

1K

5%
1/20W
MF
201

2

RAM Configuration Straps

BOM GROUP BOM OPTIONS

RAMCFG_SLOT

PART# DESCRIPTIONQTY

117S0006 0 RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD1117S0006 R1540

RES,MF,1/20W,1KOHM,5%,0201,SMD1 R1541117S0006 BOARD_ID:1D

2117S0006 R1541,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD R1542 BOARD_ID:1B1117S0006

117S0006 3 RES,MF,1/20W,1KOHM,5%,0201,SMD

117S0006 R15431 RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD2117S0006 R1543,R1540

RES,MF,1/20W,1KOHM,5%,0201,SMD

MLB_RAMCFG0
MLB_RAMCFG1
MLB_RAMCFG2

MLB_RAMCFG3

RAMCFG4:L

1

R1534

1K

5%
1/20W
MF
201

2

MLB_RAMCFG4

RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

BOM OPTIONREFERENCE DESIGNATOR(S)

BOARD_ID:1F

BOARD_ID:1E

BOARD_ID:1C

R1542,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD117S0006 2

R1542,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD

R1542,R1541,R1540

R1543,R1541,R15403117S0006 BOARD_ID:14

BOARD_ID:1A

BOARD_ID:19

BOARD_ID:18

BOARD_ID:17

BOARD_ID:16

BOARD_ID:15R1543,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD

MLB_BOARD_ID4

MLB_BOARD_ID3
MLB_BOARD_ID2
MLB_BOARD_ID1
MLB_BOARD_ID0

15

15

15

15

15

15

15

15

15

15

R1558
R1559

TABLE_5_HEAD

TABLE_5_ITEM

100K
100K

PROTO 0 = 0x1F = 1 1 1 1 1 (-01 PCB)

TABLE_5_ITEM

PROTO 0B = 0x1E = 1 1 1 1 0 (-02 PCB)

TABLE_5_ITEM

PROTO 1 = 0x1D = 1 1 1 0 1 (-03 PCB)

TABLE_5_ITEM

PROTO 2 = 0x1C = 1 1 1 0 0 (-04 & -05 PCB)

TABLE_5_ITEM

EVT1 = 0x1B = 1 1 0 1 1 (-06 PCB)

TABLE_5_ITEM

EVT2 = 0x1A = 1 1 0 1 0 (-07 PCB)

TABLE_5_ITEM

DVT = 0x19 = 1 1 0 0 1 (-08 PCB)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

DVT1-1 = 0x18 = 1 1 0 0 0 (-09 PCB)

PVT = 0x17 = 1 0 1 1 1 (-10 PCB)

0x16 = 1 0 1 1 0

0x15 = 1 0 1 0 1

0x14 = 1 0 1 0 0

1 2

1 2

EDP_IG_PANEL_PWR_EN

1/20W 201MF5%

EDP_IG_BKLT_EN

MF 2011/20W5%

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

114 57 15

103 29 15

103

101 29

29

103 15

20

89 15

89 15

111

20

89

89

89

89

89

20

20

20

20

20

20

29 15

29 15

27 15

15

20

20

20

20

20

29

15

20

89 15

89 15

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT
OUT

OUT

IN
IN

IN
IN

IN
IN
IN

NC_ENET_LOW_PWR
EDP_IG_PANEL_PWR_EN
EDP_IG_BKLT_EN
NC_EDP_IG_BKLT_PWM
NC_TCON_RESET_L
SPIROM_USE_MLB

DP_X_SNK0_HPD_IG
DP_X_SNK1_HPD_IG
DP_T_SNK0_HPD_IG
DP_T_SNK1_HPD_IG

DP_INT_IG_HPD
NC_PCH_DDPB_CTRLCLK

PCH_DDPB_CTRLDATA
NC_PCH_DDPC_CTRLCLK

PCH_DDPC_CTRLDATA
NC_PCH_DDPD_CTRLCLK

PCH_DDPD_CTRLDATA

JTAG_ISP_TDO
JTAG_ISP_TDI
JTAG_ISP_TCK

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS

15

DPMUX_UC_IRQ
NC_ENET_MEDIA_SENSE
NC_BKLT_FAULT_INT_L

NC_SDCONN_STATE_CHANGE
NC_SDCONN_OC_L

TBT_X_CIO_PLUG_EVENT_L
TBT_T_CIO_PLUG_EVENT_L
NC_TBT_W_PLUG_EVENT_L

R28

M28

P32
N31
N30

L27

AH3

AJ5

AG7
AH7

AH2
AH1

AG1

AJ2
AK2

AL3

AH5

AM27

AK28

AJ29

AG27

AH28

AG28
AM28

AL28

AK29

AM29

AL29

AH29

AL30
AL31

GPP_F14
GPP_F19/EDP_VDDEN
GPP_F20/EDP_BKLTEN
GPP_F21/EDP_BKLTCTL
GPP_F22
GPP_F23

GPP_I0/DDPB_HPD0
GPP_I1/DDPC_HPD1
GPP_I2/DDPD_HPD2
GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD
GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_H10/SML2CLK
GPP_H11/SML2DATA
GPP_H12/SML2ALERT*

GPP_H13/SML3CLK
GPP_H14/SML3DATA
GPP_H15/SML3ALERT*

GPP_H16/SML4CLK
GPP_H17/SML4DATA
GPP_H18/SML4ALERT*

GPP_H19/ISH_I2C0_SDA
GPP_H20/ISH_I2C0_SCL

GPP_H21/ISH_I2C1_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H23

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 9 OF 12

GPPF/

GPPH/I2C/INTEGRATED SENSOR

BACKLIGHT

GPPG

GPPI/DISPLAY

/SMLINK

GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1
GPP_G2/FAN_TACH_2
GPP_G3/FAN_TACH_3
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6
GPP_G7/FAN_TACH_7

GPP_G8/FAN_PWM_0

GPP_G9/FAN_PWM_1
GPP_G10/FAN_PWM_2
GPP_G11/FAN_PWM_3

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET*

GPP_G16/GSXCLK

GPP_G17/ADR_COMPLETE

GPP_G18/NMI*

GPP_G19/SMI*

GPP_G20
GPP_G21
GPP_G22
GPP_G23

N33
M33
M32
M31
L30
L33
L32
L31

J32
J33
K30
K33

H32
H31
K31
J31
F31

G31

G33
H33

E33
E30
F32
F33

SSD_BOOT_L
NC_TP_PCH_GPP_G1
NC_TP_PCH_GPP_G2
NC_TP_PCH_GPP_G3
NC_TP_PCH_GPP_G4
NC_TP_PCH_GPP_G5
NC_TP_PCH_GPP_G6
NC_TP_PCH_GPP_G7

NC_TP_PCH_GPP_G8
PCH_BT_ROM_BOOT
SOC_S2R_ACK_L
SOC_PCH_DBELL_L

SOC_SWD_CLK
PCH_SWD_IO
PCH_SWD_MUX_SEL
PCH_SOC_DBELL_L
PCH_SOC_FORCE_DFU

PCH_SOC_WDOG

PCH_SOC_DFU_STATUS
SOC_PANIC_L

DEBUGUART_SEL_SOC

NC_AUD_IPHS_SWITCH_EN
NC_AUD_IP_PERIPHERAL_DET
NC_AUD_I2C_INT_L

38 15

42 15

38 15

SOC_S2R_ACK_L

SOC_SWD_CLK

15 20 42

PCH_SWD_IO
PCH_SOC_DBELL_L

15 20 37

DEBUGUART_SEL_SOC

15

SOC_PANIC_L

SOC_PCH_DBELL_L

15 20 38

NO STUFF

OUT

111

111

111

111

111

111

111

111

35 15

38 15

15 20 38

15 20 42

42 15

42 15

15 20 37

38

37

IN

15

BI
BI
BI

16 17 109

114 87 15

115

38 15

20

20

20

PP1V8_SUS

R1561
R1537
R1538
R1539
R1546
R1557
R1562

100K
100K
100K
100K
100K
100K
100K

1 2
1 2
1 2
1
1 2
1 2
1 2

1

R1556

100K

5%
1/20W
MF
201

2

1/20W 201MF5%

5%

2

1/20W MF

5% MF

1/20W
1/20W5%
1/20W5% MF

D

37

IN

MF 2011/20W5%

201

MF 2011/20W5%

201
201MF
201

C

B

A

MLB_ID4:L

1

R1544

1K

5%
1/20W
MF
201

2

MLB_ID3:L

1

R1543

1K

5%
1/20W
MF
201

2

MLB_ID2:L

1

R1542

1K

5%
1/20W
MF
201

2

MLB_ID1:L

1

R1541

1K

5%
1/20W
MF
201

2

MLB_ID0:L

1

R1540

1K

5%
1/20W
MF
201

2

MLB_DEV_L

1

R1545

1K

5%
1/20W
MF
201

2

NOSTUFF

15

MLB BOARD ID Configuration Straps

PP3V3_SUS
PP3V3_SUS

PP3V3_S0

R1553
R1554
R1555
R1529
R1535
R1502
R1503
R1504
R1505
R1506
R1507
R1508
R1509
R1512
R1520
R1521
R1522
R1525
R1515

R1526
R1599

R1524
R1523

R1513
R1511

R1527
R1528
R1536
R1548
R1549
R1551
R1552

10K
10K

10K
100K
100K

47K

47K

47K

47K

47K

47K

1K

1K
10K
47K
47K
47K

100K
100K

100K
100K

100K

47K

100K
100K

1K

1K

100K
100K
100K

47K

100K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

12 13 110

5% 1/20W 201MF

5% 1/20W MF

5% MF1/20W 201

5% MF

5% MF 201

BOMOPTION=OMIT

BOMOPTION=OMIT

5%

5%

5% 1/20W MF 201

12 16 17 110

16 17 110

201MF1/20W5%

1/20W 201MF5%

1/20W 201MF5%

1/20W5% MF 201

201

MF1/20W5%

201

MF5% 1/20W 201

1/20W5%

1/20W 201

1/20W

1/20W

1/20W MF 2015%

5%

1/20W 201MF

5% 1/20W MF 201

1/20W MF 2015%

1/20W5% 201

1/20W MF 201

1/20W MF 2015%

201MF

MF5%

MF

2015% 1/20W

2011/20W

MF5% 1/20W

201

2015% 1/20W

MF

2015% 1/20W MF

MF5% 201

MF 2011/20W5%

MF 2011/20W5%

201MF5% 1/20W

MF

2015% 1/20W

MF

2011/20W

MF

201MF1/20W5%

NO STUFF

NO STUFF

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS
TBT_X_CIO_PLUG_EVENT_L
TBT_T_CIO_PLUG_EVENT_L

PCH_BT_UART_D2R
PCH_BT_UART_R2D
PCH_BT_UART_RTS_L
PCH_BT_UART_CTS_L
ALS_SOC_UART_D2R
ALS_SOC_UART_R2D
I2C_SSD_SDA
I2C_SSD_SCL

JTAG_ISP_TDO

SOC_UART_D2R
SOC_UART_R2D
SOC_UART_RTS_L
TPAD_SPI_INT_L

SPIROM_USE_MLB

TPAD_SPI_IF_EN

LCD_IRQ_L

SOC_UART_CTS_L
JTAG_ISP_TDI
JTAG_ISP_TCK

SPKR_ID0_NC

NC_SPKR_ID1
TBT_POC_RESET

SSD_DEBUGI2C_SEL_PCH

LCD_PSR_EN

PCH_UART2_CTS_L

AP_DEV_WAKE

15

15 29

15 103

35 15

35 15

35 15

35 15

15 20

15 20

86 15

86 15

20 15

20 15

15

43 15

43 15

15

29 15

29 15

15

15 20

86 15

15

15

15

84 83 81 80 78 77

82 114

OMIT_TABLE

U1100

SKL-PCH-SFF

115 114 15

87

42 15

35 15

SSD_BOOT_L
PCH_SWD_MUX_SEL

PCH_BT_ROM_BOOT

H65946

FCBGA

SYM 6 OF 12

20

OUT

114 36 35 20

114 76 15

29 27 15

103 101 29 15

103 29 15

114 57 15

114 76 15

91

91

43 15

43 15

86 15

20

20 15

20

20

20

OUT
OUT

IN

IN
OUT
OUT

OUT

OUT

IN

IN

IN

OUT

NC_CAMERA_RESET_L
AP_RESET_L
LCD_IRQ_L
TBT_X_DPMUX_SEL
TBT_T_DPMUX_SEL
TPAD_SPI_IF_EN
TPAD_SPI_INT_L

SSD_DEBUGI2C_SEL_PCH
AP_DEV_WAKE

15

NC_ISOLATE_CPU_MEM_L
PCH_STRP_TOPBLK_SWP_L

47

MLB_RAMCFG0

15

MLB_RAMCFG1

15

MLB_RAMCFG2

15

MLB_RAMCFG3

15

SPKR_ID0_NC

15

NC_SPKR_ID1
NC_PCH_BSSB_CLK
NC_PCH_BSSB_DATA

MLB_BOARD_ID0

15

MLB_BOARD_ID1

15

MLB_BOARD_ID2

15

MLB_BOARD_ID3

15

MLB_BOARD_ID4

15

MLB_DEV_L

15

MLB_RAMCFG4

15

TBT_W_PCI_RESET_L

AK16

AM18

AL18
AH16
AH18
AK15

AG15

AG22
AG21

AM20

AL22

AD28
AD29
AC27
AC29

AB28
AB29
AB30

Y31

Y27
AA29
AA28

Y29

Y33
AA31

AC33
AC32

GPP_A17/ISH_GP7
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_B0
GPP_B1
GPP_B11
GPP_B14/SPKR

GPP_D0/SPI1_CS*
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D15/ISH_UART0_RTS*
GPP_D16/ISH_UART0_CTS*

GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

GPPA/

INTEGRATED SENSOR

GPPB

GPPC/SMLINK/I2C/UART

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPPD/INTEGRATED SENSOR/UART/I2C

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_C8/UART0_RXD

GPP_C9/UART0_TXD
GPP_C10/UART0_RTS*
GPP_C11/UART0_CTS*

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL

GPP_C20/UART2_RXD

GPP_C21/UART2_TXD
GPP_C22/UART2_RTS*
GPP_C23/UART2_CTS*

AJ30
AK31
AK32

AJ32
AH31
AH33

AH32
AG32

AG29
AF28
AF30
AF29

AG33
AH30
AG31
AF33

AE33
AF31

AE29
AE27

AD33
AD32
AE32
AE31

SMBUS_PCH_CLK
SMBUS_PCH_DATA
NC_PCH_STRP_TLSCONF

SML_PCH_0_CLK
SML_PCH_0_DATA
NC_PCH_STRP_ESPI

SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA

PCH_BT_UART_D2R
PCH_BT_UART_R2D
PCH_BT_UART_RTS_L
PCH_BT_UART_CTS_L

SOC_UART_D2R
SOC_UART_R2D
SOC_UART_RTS_L
SOC_UART_CTS_L

I2C_SSD_SDA
I2C_SSD_SCL

NC_I2C_UPC_SDA
NC_I2C_UPC_SCL

ALS_SOC_UART_D2R
ALS_SOC_UART_R2D
LCD_PSR_EN
PCH_UART2_CTS_L

SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016

PAGE TITLE

PP1V8_SSD_FMC

R1550

R1547
R1560

R1563

OUT

BI

IN

OUT

BI

IN

OUT

BI

IN
OUT
OUT

IN

20 15

20 15

15

15

BI

OUT

BI

OUT

15 20

15 20

15

15

100K

100K
100K

100K

49

49

20

49

49

20

49

49

35 15

35 15

35 15

35 15

86 15

86 15

20

PROJ-SPECIFIC PULLUP, GPPBCH RAIL

20

1 2

1 2
1 2

1 2

1/20W5% MF 201

1/20W 2015% MF

MF 2015% 1/20W

1/20W MF

2015%

B

A

PCH GPIO/MISC/NCTF

DRAWING NUMBER SIZE

103 29 14

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

15 OF 145

SHEET

15 OF 121

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V0_SUS

17 110

PP3V3_SUS

12 14 17
110

PP1V_S5_PCH_DCPDSW

17

PP1V0_SUS

17 110

PP3V3_S0

17 110

110

110

110

110

17

PP1V0_SUS

PP1V0_SUS

PP1V0_SUS

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK5_F

AA14
AA15
AA16
AA17
AA18
AA19
AB15

N12
N13
P15
P16
P17
P18
P19
P20
R15
R16
R17
R18
R19
R20

T11
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
V18
V19
Y14
Y15
Y16
Y17
Y18
Y19

AB12
AC14
AD14

AD19

K22

L22

T12

K10

M10
M11

K13

L12

J11
J12

AD13

PRIMARY WELL

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

PRIMARY WELL HVCMOS

VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3

DCPDSW_1P0

PCIE PLL EBB PRIMARY

VCCAPLLEBB_1P0
VCCAPLLEBB_1P0

THERMAL SENSOR PW

VCCATS

VCCCLK1

VCCCLK2
VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5
VCCCLK5

HD AUDIO POWER

VCCHDA

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 10 OF 12

POWER

AUDIO PLL

MOD PHY PRIMARY

DEEP SX WELL

ANALOG PLL USB3/
PCIE2/SATA2/PCIE3

MIPI PLL

GPPA PRIMARY WELL

GPPB/GPPC/GPPH
PRIMARY WELL

GPPD PRIMARY WELL

GPPE/GPPEF
PRIMARY WELL

GPPG PRIMARY WELL

RTC WELL SUPPLY

RTC LOGIC PW/VRM

SPI

ANALOG PLL USB2/VRM

CLOCK BUFFERS PRIMARY 1.0 V

VCCHDAPLL_1P0

VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0

VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCMIPIPLL_1P0

VCCPGPPA

VCCPGPPBCH
VCCPGPPBCH
VCCPGPPBCH

VCCPGPPD
VCCPGPPD
VCCPGPPD

VCCPGPPEF
VCCPGPPEF

VCCPGPPG

DCPRTC

VCCRTC

VCCRTCPRIM_3P3

VCCSPI
VCCSPI

VCCUSB2PLL_1P0
VCCUSB2PLL_1P0

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

17

AC11

K19
L14
L15
L16
L17
L18
L19

AC20
AD20
P10
P11

K24
L24

K21

AC19

AA22
AA23
AB23

V22
W22
W23

T23
U23

PP1V0_SUS

PP3V3_S5

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS

PP3V3_SUS
PP3V3_SUS

PP1V_SUS_PCH_VCCHDAPLL_F

GPPD 1.8V

P23

AD18

AC17

AD16

AC22
AD22

AB10
AC10

PP1V8_SUS

PPDCPRTC_PCH

PP3V0_G3H

PP3V3_SUS

PP3V3_SUS

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

PP1V8_SUS

15 16 17
109

PP1V8_S0

17 109

PP1V8_S0_PCH_VCCHDA_F

L1600

FERR-220-OHM-2A

1 2

0603

C1600

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

17 110

12 17 110

17

17

12 15 17 110

13 17 110

17 110

15 16 17 110

15 16 17 110

15 16 17 109

17

12 17 109

17 110

17 110

17

L1602

FERR-220-OHM-2A

1 2

0603

VCCHDA:SUS

L1601

FERR-220-OHM-2A

1 2

0603

VCCHDA:S0

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

C1601

3.0PF

+/-0.1PF

NP0-C0G

1

2

VOLTAGE=1.0V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000

25V

0201

1

2

1

2

C1602

0.1UF

10%

6.3V

X5R
0201

1

C1603

0.1UF

10%

6.3V

2

X5R
0201

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

A11

VSS

A13

VSS

A16

VSS

A18

VSS

A20

VSS

A23

VSS

A26

VSS

A29

VSS

A5

VSS

A7

VSS

A9

VSS

AA10
AA11
AA12
AA13
AA20
AA21
AA24
AA27
AA30

AB11
AB13
AB14
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB24
AB27
AB33

AC12
AC13
AC15
AC16
AC18
AC21
AC23
AC24
AC28

AD10
AD11
AD12
AD15
AD17
AD21
AD23
AD24
AD27

AD30

AE28

AF10
AF11
AF13
AF14
AF15
AF16
AF18
AF19
AF20
AF21
AF22
AF23
AF25
AF27

AF32

AG13
AG14
AG19
AG24
AG26
AG30

AH19

AJ12
AJ15
AJ19
AJ22

AA5
AB1

AB4
AB7

AC3
AC7

AD3

AD6
AE2

AE5

AF3

AF7
AF9

AG4
AG8

AH6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Current data from LPT EDS (doc #486708, Rev 1.0).

FCBGA

SYM 11 OF 12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ25
AJ28
AJ3
AJ31
AJ9
AK18
AK30
AK4
AK7
AK8
AL10
AL13
AL21
AL24
AL27
AL6
AL7
AM16
AM7
AM9
B5
C10
C15
C21
C24
C27
C28
C3
C4
C5
C7
D10
D11
D13
D15
D16
D18
D20
D21
D23
D24
D26
D29
D3
D30
D31
D6
D8
E12
E14
E16
E19
E22
E25
E27
E29
E3
E5
E6
E8
E9
F16
F28
F30
F7
G1
G10
G11
G13
G18
G20
G21
G23
G24
G26
G32
G4
H3
H30
H4
J10
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J27
J30

J7

K1
K11
K12
K14
K15
K16
K17
K18
K20
K23
K27
K32

K4

K7

L10
L11
L13
L20
L21
L23
L28

L3
L4

L7
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M27
M30

M5

N1
N10
N11
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N27
N32

N4

N7
P12
P13
P14
P21
P22
P24
P28

P3

P4

P7
R10
R11
R12
R13
R14
R21
R22
R23
R24
R27
R30
R33

R5

T10
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T24
T27

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 12 OF 12

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

BOM_COST_GROUP=CPU & CHIPSET

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T3
T31
T7
U1
U10
U11
U12
U13
U20
U21
U22
U24
U28
U3
U32
U5
V10
V11
V12
V13
V2
V20
V21
V23
V24
V27
V28
V29
V30
V5
V6
V7
W1
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W24
W27
W32
W4
W7
Y10
Y11
Y12
Y13
Y20
Y21
Y22
Y23
Y24
Y28
Y3
Y32
Y4
Y7

D1
C1
B1
A2
A3
A4
B2
A30
A31
A32
A33
B33
C33
D33
B32
AJ33
AK33
AL33
AM33
AM32
AM31
AM30
AL32
AM4
AM3
AM2
AM1
AL1
AK1
AJ1
AL2

PAGE TITLE

PCH Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/25/2016SYNC_MASTER=X363_SAKKOC

DRAWING NUMBER SIZE

051-00647

REVISION

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BRANCH

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C

B

A

8 7 5 4 2 1

36

345678

2 1

1000PF CAPS ARE INTEL PLACEHOLDERS & ALL PLACENEAR NEED TO BE UPDATED

PLACE_NEAR=U1100.AD19:1MM

16 110

PLACE_NEAR=U1100.N12:1MM

1

C1743

1UF

10%

6.3V

2

CERM
402

C1750

12PF

5%

25V

NP0-C0G

0201

1

2

1

C1730

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1731

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1732

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1733

0.1UF

10%

16V

2

X5R-CERM
0201

PP1V0_SUS

PLACE_NEAR=U1100.U17:1MM

PLACE_NEAR=U1100.V17:1MM

1

C1701

1UF

10%

6.3V

2

CERM
402

C1700

22UF

20%

X5R-CERM-1

6.3V

603

1

2

PP1V_S5_PCH_DCPDSW

16

VOLTAGE=1V

1

C1708

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V8_SUS

15 16 109

PLACE_NEAR=U1100.P23:1MM

20%

6.3V

603

1

2

C1747

22UF

X5R-CERM-1

PLACE_NEAR=U1100.P23:1MM

1

C1714

0.1UF

10%

16V

2

X5R-CERM
0201

D

PP1V0_SUS

16 110

C1751

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1100.L17:1.4MM

PLACE_NEAR=U1100.L17:2.1MM

1

2

1

C1736

47UF

20%

6.3V

2

POLY-TANT
0805

1

C1737

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1734

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1735

0.1UF

10%

16V

2

X5R-CERM
0201

PP1V0_SUS

16 110

PLACE_NEAR=U1100.K22:1MM

VOLTAGE=3.3V

PPDCPRTC_PCH

16

1

C1738

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1739

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.K22:1MM

PLACE_NEAR=U1100.AD18:1MM

PLACE_NEAR=U1100.L17:1MM

1

C1702

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1703

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1709

0.1UF

10%

16V

2

X5R-CERM
0201

PP3V3_SUS

13 16 110

PP3V3_SUS

15 16 110

12 15 16 110

PP3V3_SUS

PLACE_NEAR=U1100.AA23:1MM

1

C1710

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.U23:1MM

1

C1713

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.AC19:1MM

1

C1746

0.1UF

10%

16V

2

X5R-CERM
0201

PP3V3_SUS

16 110

PP3V3_S0

16 110

PP3V0_G3H

12 16 109

PLACE_NEAR=U1100.AC17:1MM

PLACE_NEAR=U1100.W22:1MM

1

C1716

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.T12:1MM

1

C1718

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.AC17:1MM

1

C1721

1UF

20%

6.3V

2

X6S-CERM
0201

1

C1722

0.1UF

10%

16V

2

X5R-CERM
0201

D

C

B

PP3V3_SUS

12 14 16 110

PP3V3_S5

12 16 110

PP3V3_SUS

16 110

16 109

PLACE_NEAR=U1100.AD13:1.2MM

1

C1749

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1744

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1100.AD16:1MM

1

C1745

1UF

20%

6.3V

2

X6S-CERM
0201

PP1V8_S0

1

C1748

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C1752

12PF

5%

25V

2

NP0-C0G
0201

PLACE_NEAR=U1100.AD14:1MM

1

C1719

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.AD16:1MM

1

C1715

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.AD13:1MM

1

C1717

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.AB12:1MM

1

C1720

0.1UF

10%

16V

2

X5R-CERM
0201

PLACE_NEAR=U1100.P10:1MM

PP1V0_SUS

110

110

C1754

NP0-C0G

PP1V0_SUS

C1755

NP0-C0G

12PF

5%

25V

0201

12PF

5%

25V

0201

RAIL SIDE

PCH SIDE

C

OMIT_TABLE

L1700

2.2UH-240MA-0.221OHM

1 2

0603

1

PLACE_NEAR=U1100.K24:3MM

2

1

C1704

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1100.K24:1MM

MAKE_BASE=TRUE

OMIT_TABLE

VOLTAGE=1V

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PLACE_NEAR=U1100.L24:1MM

1

C1740

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1705

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.K21:1MM

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

16

16

L1701

2.2UH-240MA-0.221OHM

1 2

0603

1

2

PLACE_NEAR=U1100.J12:3MM

1

C1706

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1100.J12:1MM

PP1V_SUS_PCH_VCCCLK5_F

MAKE_BASE=TRUE

VOLTAGE=1V

PLACE_NEAR=U1100.J11:1MM

1

C1741

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1707

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.J11:1MM

PP1V_SUS_PCH_VCCCLK5_F

16

B

C1753

12PF

5%

25V

NP0-C0G

0201

16 110

1

C1723

0.1UF

2

PLACE_NEAR=U1100.AC20:1MM

20%

10V

CERM

402

1

2

PP3V3_SUS

1

C1724

0.1UF

20%

10V

2

CERM
402

PLACE_NEAR=U1100.AC22:1MM

1

C1757

0.1UF

10%

16V

2

X5R-CERM
0201

PP1V0_SUS

110

C1756

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

OMIT_TABLE

L1702

2.2UH-240MA-0.221OHM

1 2

1

PLACE_NEAR=U1100.AC10:3.6MM

2

0603

1

C1711

47UF

20%

6.3V

2

POLY-TANT
0805

PLACE_NEAR=U1100.AC10:2.1MM

MAKE_BASE=TRUE

VOLTAGE=1V

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

PLACE_NEAR=U1100.AB10:1MM

1

C1742

0.1UF

10%

16V

2

X5R-CERM
0201

1

C1712

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U1100.AC11:1MM

PP1V_SUS_PCH_VCCUSB2HDAPLL_F
PP1V_SUS_PCH_VCCUSB2HDAPLL_F

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

16

16

A

Current data from LPT EDS (doc #486708, Rev 1.0).

8 7 5 4 2 1

113S0022 3

BOM_COST_GROUP=CPU & CHIPSET

36

L1700,L1701,L1702RES,MF,1A MAX,0OHM,5%,0603

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

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10.0.0

BRANCH

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A

D

C

6

IN

6

IN

6

IN

6

IN

115 73 46 12

48 46

57 13

115 18 6

20

Extra BPM Testpoints

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>

IN

OUT

OUT

OUT

PM_RSMRST_L

PM_PWRBTN_L

IN

SPI_MOSI_R

XDP_CPU_TCK

PCH_JTAGX

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1800
TP1801
TP1802
TP1803

PP3V3_SUS

18 73 110

PLACE_NEAR=J1800.48:2.54MM

XDP:YES

PLACE_NEAR=U1100.AF12:3.8MM

R1800

1K

R1802

PLACE_NEAR=U1100.AM10:3MM

R1803

PLACE_NEAR=U1100.AM23:2.54MM

R1835

1K

0

1 2

XDP:YES

1 2

XDP:YES

XDP:YES

1 2

1 2

XDP:YES

1K

5%

1/20W

MF

201

1

2

201

MF5%101/20W 201

MF 201

R1804

5%

1/20W MF

5% 1/20W

5% MF1/20W 0201

PLACE_NEAR=J1800.58:28MM

115 13 6

115 13 6

115 6

115 18 13

345678

2 1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V0_SUS

110

NOTE: This is not the standard XDP pinout.

XDP_CONN

XDP:YES

1K

5%

1/20W

MF

201

1

NO_XNET_CONNECTION

2

XDP_PIN_1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

NC
NC

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

VCC_OBS_AB

NC

NC
NC

XDP:YES

OBSFN_A0
OBSFN_A1

OBSFN_B0
OBSFN_B1

HOOK0
HOOK1

HOOK2
HOOK3

SDA

SCL
TCK1
TCK0

C1800

0.1UF

10%

6.3V

CERM-X5R

0201

PLACE_NEAR=J1800.44:28MM

1

2

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

PLACE_NEAR=U0500.BN28:2.54MM

XDP_PRESENT_CPU
XDP_CPU_PREQ_L

BI

IN

6

IN

6

IN

6

IN
IN

6

IN

6

IN

6

IN

6

IN

XDP_CPU_PRDY_L

CPU_CFG<0>
CPU_CFG<1>

CPU_CFG<2>
CPU_CFG<3>

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

XDP_PM_RSMRST_L
XDP_CPU_PWRBTN_L

SPI_MOSI_R_CONN

OUT

XDP_PCH_TCK

XDP:YES

10%

6.3V
0201

1

2

C1804

0.1UF

CERM-X5R

PLACE_NEAR=J1800.42:28MM

DF40RC-60DP-0.4V

J1800

M-ST-SM1

62

61

12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960

6364

518S0847

PLACE_NEAR=J1800.43:28MM

Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#

NC_ITPXDP_CLK100MP
NC_ITPXDP_CLK100MN

XDP:YES

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.47:28MM

1

2

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

ITP_PMODE
XDP_DBRESET_L

XDP:YES

C1806

0.1UF

10%

6.3V
CERM-X5R
0201

115 18 13

IN

0

0

0

0

115 18 13

115 18 13

115 18 13

13

115 18 6

115 18 6

1 2

XDP:YES

1 2

XDP:YES

1 2

XDP:YES

1 2

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

IN
IN

115 113 12

115 113 12

1

R1830

1K

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.E8:2.54MM

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

XDP_PCH_TDO

PLACE_NEAR=U1100.AF6:28MM

XDP_PCH_TDI

PLACE_NEAR=U1100.AF5:28MM

XDP_PCH_TMS

PLACE_NEAR=U1100.AG5:28MM 1/20W

XDP_CPU_TDO

PLACE_NEAR=U0500.BT28:28MM

XDP_CPU_TCK

PLACE_NEAR=U0500.BR28:28MM

XDP_PCH_TCK

PLACE_NEAR=U1100.AG6:28MM

XDP_PCH_TRST_L

18

PROPER WAY TO TERMINATE?

XDP_CPU_TDO

MF5% 1/20W 0201

XDP_CPU_TRST_L

5% 1/20W

MF 0201

XDP_CPU_TDI

1/20W

MF 02015%

XDP_CPU_TMS

MF 02015% 1/20W

XDP:YES

1 2

R1890
R1891
R1892
R1810

R1813
R1897

R1898

R1806

0

5%

1/20W

MF

0201

PM_SYSRST_L

XDP:YES

PP1V0_S0SW

6 8 11 110

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

NOSTUFF

51

2 1

NOSTUFF

51

2 1

IN

OUT

OUT

OUT

MF 2015% 1/20W

MF5% 1/20W 201

D

MF 2015%

1/20W MF 2015%

MF 2015% 1/20W

1/20W5% 201MF

MF 2015% 1/20W

BI

115 46 12

C

115 18 6

115 13 6

115 6

115 6

B

13

14

14

14

14

14

14

14

14

14

14

14

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PP3V3_SUS

18 73 110

PP3V3_SUS

18 73 110

XDP:YES

6

VCC

1

C1830

0.1UF

10%
10V

2

X5R-CERM
0201

XDP:YES

XDP_PCH_TDO
XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

IN

18

OUT
OUT

115 18 13

115 18 13

115 18 13

U1830

PCH/XDP Signals

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_C0
XDP_PCH_OBSDATA_C1
XDP_PCH_OBSDATA_C2
XDP_PCH_OBSDATA_C3
XDP_PCH_OBSDATA_D0
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSFN_C1

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1870
TP1871
TP1872
TP1873
TP1874
TP1875
TP1876
TP1877
TP1878
TP1879
TP1880
TP1881

Non-XDP Signals

XDP:YES

1

R1850

100K

5%
1/20W
MF
201

2

74AUP1G07GF

SOT891

2
1

GND

3

(OD)

NCNC

PLACE_NEAR=U1830.4:7.54MM

SPI_IO2_STRAP_L

4

YA

5

NCNC

PLACE_NEAR=U1830.4:2.54MM

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

R1831

1.5K

NO_XNET_CONNECTION

MF

1 2

XDP:YES

R1832

49.9

NO_XNET_CONNECTION

1 2

MF

NOSTUFF

XDP_PRESENT_L

SPI_IO<2>

5% 1/20W

201

(STRAP TO PCH)

1%

1/20W

201

OUT

OUT

57 13

B

73

A

DESIGN: X502/MLB
LAST CHANGE: Mon Jun 15 22:04:28 2015

SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/25/2016

PAGE TITLE

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

8 7 5 4 2 1

36

IV ALL RIGHTS RESERVED

CPU/PCH Merged XDP

DRAWING NUMBER SIZE

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R

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A

D

345678

2 1

D

CRITICAL

C1907

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

113

System 32kHz / 12MHz / 24MHz Clock Generator

SYSCLK_CLK24M_X2

R1900

0

1 2

5%

1/20W

MF

0201

20

20

46

20

20

PPVIO_32K_B_RC

20

PPVIO_VIOE_A_RC

20

NC_PPVIOE_CAMCLK

IN

NC_PPVIOE_SSDCLK

IN

SMC_CLK12M_EN

IN

SYSCLK_CLK24M_X2_R

113

PPVRTC_U1900_RC

PPVDD_U1900_RC

12

VIO_32K_B

2

VIOE_24M_A

5

VIOE_24M_B

15

VIOE_24M_C

8

OE_12M

19

X2

20

X1

1

VDD

U1900

SLG3AP3444

STQFN

GND

11

VRTC

VOUT

32.768K_A

32.768K_B
24M_A

24M_B
24M_C

12M

PP2V9_SYSCLK

17
10

13
3

6
16

7

SYSCLK_CLK32K_PCH
SYSCLK_CLK32K_CAMERA_BT_AP

SYSCLK_CLK24M_PCH
NC_SYSCLK_CLK24M_CAMERA
NC_SYSCLK_CLK24M_SSD

SYSCLK_CLK12M_SMC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

VOLTAGE=2.9V

BYPASS=U1900.17:18:5MM

1

C1900

2.2UF

20%

6.3V

2

X5R-CERM
0201

20

20

20

20

20

46

109

PCH ME Disable Strap

SPI_DESCRIPTOR_OVERRIDE_L

1

G

IN

PP1V8_S0

S

2

Q1930

DMP31D0U

SOT23

D

3

SPI_DESCRIPTOR_OVERRIDE

1

R1930

1K

5%
1/20W
MF
201

2

HDA_SDOUT_R

PCH IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
***** Circuit does not support HDA voltage >3.3V.

46

IN

D

13

OUT

C

2 4

CRITICAL

C1908

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

CRITICAL

Y1900

1 3

2.5X2.0MM-SM

NO STUFF

1

R1901

1M

24MHZ-10PPM-8PF-40OHM

5%
1/20W
MF
201

2

SYSCLK_CLK24M_X1

113

NOTE: 30 PPM or better required for SKL PCH

14

4

9

18

C

B

B

A

PCIe Wake Muxing

PP3V3_S5

110

CRITICAL

10%

6.3V
0201

1

25%

6

5

4 3

U1910

PI5A3157BC6E

SEL

VCC

A

SC70

VER 1

B1

1

1

2

GND

0

B0

35

1

R1910

C1910

0.1UF

100K

1/20W
MF
201

2

CERM-X5R

AP_PCIE_WAKE_L PCIE_WAKE_L

8 7 5 4 2 1

AP_S0IX_WAKE_SEL

SEL OUTPUT

L PCIE_WAKE_L (B0)
H AP_S0IX_WAKE_L (B1)

AP_S0IX_WAKE_L

OUT

OUTIN

12

IN

SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016

PAGE TITLE

12

12

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Chipset Support 1

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

36

051-00647

10.0.0
dvt-fab10
19 OF 145
19 OF 121

A

D

345678

2 1

D

C

B

A

Platform Reset Connections

Buffered

35 20 12

114

114 35 20 12

109 20

110

IN

R2080
R2081
R2082
R2083

IN

PP3V3_S0

PLT_RST_L

C2071

0.1UF

X5R-CERM

IN

PLT_RST_L

PP3V3_S0

PP1V8_S4

LDO

1

10%
16V

2

0201

NOSTUFF

12 14 20 73 110

47K

47K

47K

47K

1 2

1 2

1 2

1 2

CRITICAL

5

1

U2071

2

PLACE_NEAR=R2001:5MM

MC74VHC1G08

3

Unbuffered

100K

100K

100K

10K

100K

100K

5% MF

5%

5% 201MF1/20W

C2013

Scrub for Layout Optimization

SC70-HF

4

PLT_RST_L_BUF

1

R2070

100K

5%
1/20W
MF
201

2

NOSTUFF

5%

1/20W

MF

0201

1

0

2

R2073

PLACE_NEAR=U2071:5MM

1

R2072

4.99K

1%
1/20W
MF
201

2

MAKE_BASE=TRUE

TBT_X_PCI_RESET_L

R2000

12

MF

2015% 1/20W

TBT_X_PCI_RESET_L

MAKE_BASE=TRUE

TBT_T_PCI_RESET_L

R2001

12

R2002

12

R2003

12

R2004

12

12

1/20W

5% 201MF

R2005

MF1/20W5% 201

2011/20W5% MF

MF1/20W5%

201

201MF1/20W5%

TBT_T_PCI_RESET_L

AP_RESET_L

SSD_RESET_L

SMC_LRESET_L

TBT_W_PCI_RESET_L

PCIE CLKREQS

115 87

SSD_CLKREQ_L

1/20W5% 201

27

1/20W 201

101

1/20W MF 201

35

MF

TBT_X_CLKREQ_L

TBT_T_CLKREQ_L

AP_CLKREQ_L

R2016

3.3

1 2

1/20W

1

1.0UF

20%

6.3V

2

X5R

0201-1

5%
MF

201

MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000

VOLTAGE=1.8V

PPVCC_RTC_OSC

1

2

R2084

1/20W

R2085

1/20W 201MF5%

R2086
R2087

1/20W

5% MF 201

C2014

0.1UF

10%

6.3V
CERM-X5R
0201

1 2

201MF5%

1 2

1 2

2015% MF1/20W

1 2

1

C2015

0.01UF

10%
10V

2

X5R-CERM
0201

1K

1K

1K

1K

J80 & J80G Display Port DDPB, DDPC,DDPD

6

1

PP3V3_S0

DBGLED

R2092

1/20W

DBGLED_S3DBGLED_S4

DBGLED

A

D2092

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM
SILK_PART=S3_ON

DBGLED_S3_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

5

G S

20K

5%
MF

201

1

2

3

D

4

PCH_DDPB_CTRLDATA

15

PCH_DDPC_CTRLDATA

15

PCH_DDPD_CTRLDATA

15

PP3V3_S5

110

DBGLED

R2090

20K

1/20W

201

DBGLED_S5

DBGLED

A

D2090

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM
SILK_PART=S5_ON

73 46 12

73 70 46 43 12

114 101 89 76 73 70 46 27 12

70 46 12

5%
MF

12 14 20 73 110

R2050

201 MF1/20W5%

R2051

201 MF1/20W5%

R2052

201 MF1/20W5%

2.2K

1 2

2.2K

1 2

2.2K

1 2

Power State Debug LEDs

DBGLED

20K

5%

1/20W

MF

201

1

2

D

1

2

DBGLED

A

R2091

D2091

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM
SILK_PART=STBY_ON

DBGLED_S4_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

2

G S

IN
IN
IN
IN

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L

114 35 20 12

12 20

LPC_CLK24M_DPMUX_UC_R

LPC_CLK24M_DPMUX_UC_R

MAKE_BASE=TRUE

14

27 29

14

101

114 36 35 15

115 114 87 14

46

15

SSD_CLKREQ_L_R

12

TBT_X_CLKREQ_L_R

12

TBT_T_CLKREQ_L_R

12

AP_CLKREQ_L_R

12

4

VCC

Y2001

32.768KHZ-25PPM-15PF-5.5V

2.50X2.00-SM-COMBO

1

EN/DIS OUT

GND

2

(For development only)

DBGLED

R2093

1/20W

DBGLED

A

D2093

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM
SILK_PART=S0I3_ON

DBGLED_S0I3_D

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

2

G S

DPMUX Connections

PLT_RST_L

IN

DPMUX_UC_IRQ

15

113 12

20K

IN

19

IN

3

SYSCLK_CLK32K_OSC_Y1901

1

5%
MF

201

2

D

NC_PCH_CLK24M_XTALOUT

MAKE_BASE=TRUE

SYSCLK_CLK24M_PCH

MAKE_BASE=TRUE

SSD_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_X_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_T_CLKREQ_L_R

MAKE_BASE=TRUE

AP_CLKREQ_L_R

109 20

IN

DBGLED

R2095

20K

1/20W

201

DBGLED_S0DBGLED_S0I3

DBGLED

A

D2095

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM
SILK_PART=S0_ON

DBGLED_S0_D

DBGLED

Q2091

6

1

DMN5L06VK-7

PP1V8_S4

LDO

1

5%
MF

2

SOT563

VER 3

5

G S

100K

R2007

22

1 2

5%

1/20W

MF

201

3

D

4

R2006

12

1/20W 201MF5%

DPMUX_LRESET_L

LPC_CLK24M_DPMUX_UC

MAKE_BASE=TRUE

DPMUX_UC_IRQ

5%

1/20W

MF

201

1

2

R2089

100K

MAKE_BASE=TRUE

NC_PCH_CLK24M_XTALOUT

SYSCLK_CLK24M_PCH

GreenCLK VIOEs

MAKE_BASE=TRUE

NC_PPVIOE_CAMCLK

MAKE_BASE=TRUE

NC_PPVIOE_SSDCLK

R2017

0

1 2

5%

1/20W

MF

0201

R2018

0

1 2

5%

1/20W

MF

0201

NOSTUFF

SYSCLK_CLK32K_WIFIBT

SYSCLK_CLK32K_OSC_SOC

PLACE_NEAR=U3900.AA22:3mm

C2003

110

IN

1.0UF

6.3V

0201-1

1

20%

2

X5R

PP1V0_SUS

F = 500kHz

109 20

IN

OUT

R2012

3.3

1 2

5%

1/20W

MF

201

C2006

1.0UF

IN

PP3V3_G3H

F = 1.7MHz

109 20

89

89

OUT

89

12

NC_PPVIOE_CAMCLK

NC_PPVIOE_SSDCLK

OUT

R2026

0

1 2

5%

1/20W

MF

0201

MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000

VOLTAGE=1.8V

PPVIO_32K_B_RC

1

C2002

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U1900.12:18:5MM

R2013

3.3

1 2

5%

1/20W

MF

201

20%

6.3V
X5R

0201-1

1

2

RC Filter -3dB @ 240KHz

C2009

1.0UF

0201-1

IN

PP3V3_G3H

F = 1.7MHz

NC_AUD_IPHS_SWITCH_EN

15

NC_AUD_IP_PERIPHERAL_DET

15

NC_AUD_I2C_INT_L

15

NC_ENET_MEDIA_SENSE

15

NC_BKLT_FAULT_INT_L

15

NC_SDCONN_STATE_CHANGE

15

NC_SDCONN_OC_L

15

NC_TBT_W_PLUG_EVENT_L

15

SOC_UART_D2R

15

SOC_UART_R2D

15

35

SOC_CLK_32K

NOSTUFF

19

1

C2001

0.1UF

10%

6.3V

2

CERM-X5R
0201

MIN_NECK_WIDTH=0.1750

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.0V

PPVIO_VIOE_A_RC

1

C2004

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U1900.02:18:5MM

1

2

R2014

3.3

1 2

5%

1/20W

MF

201

20%

6.3V
X5R

1

2

R2015

1 2

20%
X5R

1

2

C2010

1.0UF

6.3V

0201-1

NC ALIASES 3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

89

15

15

13

19

19

OUT

37

19

13

13

13

15

15

15

12

12

12

20 12

20 12

12

SOC_PCH_DBELL_L

15 38

SOC_SWD_CLK

15 42

PCH_SOC_DBELL_L

15 37

C2000

0.1UF

10%

6.3V
CERM-X5R
0201

MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000

VOLTAGE=3.3V

PPVDD_U1900_RC

1

2

3.3

5%

1/20W

MF

201

C2011

0.1UF

10%

6.3V
CERM-X5R
0201

MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000

VOLTAGE=3.3V

PPVRTC_U1900_RC

1

2

1

C2005

0.1UF

10%

6.3V

2

X5R
0201

C2007

0.1UF

10%

6.3V
CERM-X5R
0201

MAKE_BASE=TRUE

NC_AUD_IPHS_SWITCH_EN

MAKE_BASE=TRUE

NC_AUD_IP_PERIPHERAL_DET

MAKE_BASE=TRUE

NC_AUD_I2C_INT_L

MAKE_BASE=TRUE

NC_ENET_MEDIA_SENSE

MAKE_BASE=TRUE

NC_BKLT_FAULT_INT_L

MAKE_BASE=TRUE

NC_SDCONN_STATE_CHANGE

MAKE_BASE=TRUE

NC_SDCONN_OC_L

MAKE_BASE=TRUE

NC_TBT_W_PLUG_EVENT_L

SOC_UART_D2R
SOC_UART_R2D

SIGNAL ALIASES

BKLT_PWM_MLB2TCON

ALS_SOC_UART_D2R
ALS_SOC_UART_R2D
PCH_JTAGX

PCH_DISPA_BCLK
PCH_DISPA_SDI
PCH_DISPA_SDO

NC_PCH_DDPB_CTRLCLK
NC_PCH_DDPC_CTRLCLK
NC_PCH_DDPD_CTRLCLK

NC_PCH_SLP_A_L
NC_PCH_LANPHYPC
NC_PCH_GPD7

NC_CLKOUT_PCIE_13_N
NC_CLKOUT_PCIE_13_P

NC_PCH_PME_L

19

1

C2008

0.1UF

10%

6.3V

2

X5R
0201

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC ALIASES 2

19

INTEL SKL DEBUG

13

13

13

13

GREENCLK CLOCK OUT ALIASES

MAKE_BASE=TRUE

SYSCLK_CLK32K_PCH

42

42

MAKE_BASE=TRUE

19

MAKE_BASE=TRUE

SYSCLK_CLK32K_CAMERA_BT_AP

IN

BKLT_PWM_MLB2TCON

MAKE_BASE=TRUE

ALS_SOC_UART_D2R

MAKE_BASE=TRUE

ALS_SOC_UART_R2D

MAKE_BASE=TRUE

PCH_JTAGX

PCH_DISPA_BCLK
PCH_DISPA_SDI
PCH_DISPA_SDO

MAKE_BASE=TRUE

NC_PCH_DDPB_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_DDPC_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_DDPD_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_SLP_A_L

MAKE_BASE=TRUE

NC_PCH_LANPHYPC

MAKE_BASE=TRUE

NC_PCH_GPD7

MAKE_BASE=TRUE

NC_CLKOUT_PCIE_13_N

MAKE_BASE=TRUE

NC_CLKOUT_PCIE_13_P

MAKE_BASE=TRUE

NC_PCH_PME_L

MAKE_BASE=TRUE

SOC_PCH_DBELL_L

MAKE_BASE=TRUE

SOC_SWD_CLK

MAKE_BASE=TRUE

PCH_SOC_DBELL_L

UNUSED NETS in J80

ENETSD_CLKREQ_L
CAMERA_CLKREQ_L

TBT_W_CLKREQ_L
TBT_W_CIO_PWR_EN

TBT_W_USB_PWR_EN

BOM_COST_GROUP=CPU & CHIPSET

115

MAKE_BASE=TRUE

114 76

42

42

18

5

5

5

13

OUT

OUT

OUT

12

IN

IN

TP_PCH_DMIC_CLK1

TP_PCH_DMIC_DATA1

TP_PCH_DMIC_CLK0

TP_PCH_DMIC_DATA0

NC_PCH_CLK32K_RTCX2

20 12

20 12

20 12

NC_PCH_DRAM_RESET_L

NC_TCON_RESET_L

15

NC_SPKR_ID1

15

NC_HDD_PWR_EN

14

NC_PCH_TP1_AH9

13

NC_PCH_TP1_AG9

13

NC_PCH_BSSB_CLK

15

NC_PCH_BSSB_DATA

15

NC_PCH_SLP_LAN_L

12

NC_ISOLATE_CPU_MEM_L

15

NC_PCH_CAM_RESET

14

NC_PCH_CAM_EXT_BOOT_L

14

NC_WOL_EN

14

NC_ENET_LOW_PWR

15

NC_I2C_UPC_SDA

15

NC_I2C_UPC_SCL

15

NC_SYSCLK_CLK24M_CAMERA

19

NC_SYSCLK_CLK24M_SSD

19

NC_PCH_STRP_TLSCONF

15

NC_PCH_STRP_ESPI

15

NC_PCH_STRP_BSSB_SEL_GPIO

LPC_CLK24M_DPMUX_UC_R

12 20

NC_CAMERA_RESET_L

15

SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/14/2016

12

12

12

12

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

PP2000
PP2001
PP2002

PP2003

SYSCLK_CLK32K_PCH
NC_PCH_CLK32K_RTCX2

R2043

0

1 2

5%

1/20W

MF

0201

SOC_PMU_CLK_32K

NC ALIASES

MAKE_BASE=TRUE

NC_PCH_DRAM_RESET_L

MAKE_BASE=TRUE

NC_TCON_RESET_L

MAKE_BASE=TRUE

NC_SPKR_ID1

MAKE_BASE=TRUE

NC_HDD_PWR_EN

MAKE_BASE=TRUE

NC_PCH_TP1_AH9

MAKE_BASE=TRUE

NC_PCH_TP1_AG9

MAKE_BASE=TRUE

NC_PCH_BSSB_CLK

MAKE_BASE=TRUE

NC_PCH_BSSB_DATA

MAKE_BASE=TRUE

NC_PCH_SLP_LAN_L

MAKE_BASE=TRUE

NC_ISOLATE_CPU_MEM_L

MAKE_BASE=TRUE

NC_PCH_CAM_RESET

MAKE_BASE=TRUE

NC_PCH_CAM_EXT_BOOT_L

MAKE_BASE=TRUE

NC_WOL_EN

MAKE_BASE=TRUE

NC_ENET_LOW_PWR

MAKE_BASE=TRUE

NC_I2C_UPC_SDA

MAKE_BASE=TRUE

NC_I2C_UPC_SCL

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_SSD

MAKE_BASE=TRUE

NC_PCH_STRP_TLSCONF

MAKE_BASE=TRUE

NC_PCH_STRP_ESPI

MAKE_BASE=TRUE

NC_PCH_STRP_BSSB_SEL_GPIO

MAKE_BASE=TRUE

LPC_CLK24M_DPMUX_UC_R

MAKE_BASE=TRUE

NC_CAMERA_RESET_L

Chipset Support 2

Apple Inc.

12 19

OUTIN

12

IN

OUT

DRAWING NUMBER SIZE

051-00647

REVISION

41 37

20 12

D

10.0.0

BRANCH

dvt-fab10

PAGE

20 OF 145

SHEET

20 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
LPDDR3 (1.2V) ?.??mV per step

7

IN

7

IN

7

IN

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU-Based Margining

PP1V2_S3

VRef Dividers

R2223

10

1 2

1%

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_A_RC

PLACE_NEAR=R2221.2:1mm

R2222

8.2K

1/20W

201

R2220

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2241.2:1mm

R2242

8.2K

1/20W

201

R2240

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2261.2:1mm

R2262

8.2K

1/20W

201

R2260

24.9

1 2

1%

1/20W

MF

201

1

1%
MF

2

1

1%
MF

2

1

1%
MF

2

1

R2221

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.1450

1

R2241

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000

1

R2261

8.2K

1%
1/20W
MF
201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.1450

D

109

109

C

109

109

B

A

PAGE TITLE

LPDDR3 VREF MARGINING

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0
dvt-fab10
22 OF 145
21 OF 121

A

D

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-16GB

FBGA

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

26 7

26 7

113 26 7

113 26 7

26 23 7

26 23 7

26 23 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0>
MEM_A_ZQ<1>

243

1%

1/20W

MF

201

1

10%

6.3V
X5R
201

1

2

2

C2340

0.047UF

109 23

109 23

1

C2341

0.047UF

10%

6.3V

2

X5R
201

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

22 23 24 25 109 116

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

1

C2300

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

R2301

R2

P2
N2
N3

M3

F3

E3

E2
D2
C2

K3

K4

J3
J2

L3
L4

L8

G8

P8
D8

J8

B3

B4
H4

J11

A1

A2

A12
A13

B1

B13

T1

T13

U1
U2

U12
U13

C4

K9
R3

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

NC

1

2

OMIT_TABLE

C2301

0.1UF

10%
16V
X5R-CERM
0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

1

C2302

1.0UF

20%
10V

2

X5R-CERM
0201-1

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

1

C2303

1.0UF

20%
10V

2

X5R-CERM
0201-1

MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<15>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<2>
MEM_A_DQ<0>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<16>
MEM_A_DQ<22>
MEM_A_DQ<18>
MEM_A_DQ<23>
MEM_A_DQ<17>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<21>
MEM_A_DQ<24>
MEM_A_DQ<26>
MEM_A_DQ<31>
MEM_A_DQ<25>
MEM_A_DQ<28>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<27>

MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>

MEM_A_DQS_P<1>
MEM_A_DQS_P<0>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>

1

C2304

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2305

1.0UF

20%
10V

2

X5R-CERM
0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2306

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2307

10UF

20%
4V

2

X6S-CERM
0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8

A9
D4
D5
D6
G5
H5
H6

H12

J5

J6
K5
K6

K12

L5
P4
P5
P6

U8
U9

F2

G2
H3

L2

M2

A11
C12

E8

E12

G12

H8
H9

H11

J9

J10

K8

K11

L12

N8
N12
R12
U11

VDD1

VDD2

VDDCA

VDDQ

U2300

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2320

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2310

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2330

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2321

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2311

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2331

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2322

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2312

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2332

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2323

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2333

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2324

10UF

20%
4V

2

X6S-CERM
0402-2

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

BOM_COST_GROUP=DRAM

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

23 OF 145

SHEET

22 OF 121

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-16GB

FBGA

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

26 7

26 7

113 26 7

113 26 7

26 22 7

26 22 7

26 22 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>

MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2>
MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

10%

6.3V
X5R
201

1

2

2

C2440

0.047UF

109 22

109 22

1

C2441

0.047UF

10%

6.3V

2

X5R
201

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

22 23 24 25 109 116

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

1

C2400

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

R2401

R2

P2
N2
N3

M3

F3

E3

E2
D2
C2

K3

K4

J3
J2

L3
L4

L8

G8

P8
D8

J8

B3

B4
H4

J11

A1

A2

A12
A13

B1

B13

T1

T13

U1
U2

U12
U13

C4

K9
R3

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

NC

1

2

OMIT_TABLE

C2401

0.1UF

10%
16V
X5R-CERM
0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

1

C2402

1.0UF

20%
10V

2

X5R-CERM
0201-1

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

1

C2403

1.0UF

20%
10V

2

X5R-CERM
0201-1

MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<41>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_DQ<49>
MEM_A_DQ<53>
MEM_A_DQ<55>
MEM_A_DQ<51>
MEM_A_DQ<54>
MEM_A_DQ<52>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<62>
MEM_A_DQ<59>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<58>
MEM_A_DQ<63>
MEM_A_DQ<60>
MEM_A_DQ<61>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<4>
MEM_A_DQS_N<7>

MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4>
MEM_A_DQS_P<7>

1

C2404

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2405

1.0UF

20%
10V

2

X5R-CERM
0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2406

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2407

10UF

20%
4V

2

X6S-CERM
0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8

A9
D4
D5
D6

G5

H5
H6

H12

J5

J6
K5
K6

K12

L5
P4
P5
P6

U8
U9

F2

G2

H3

L2

M2

A11
C12

E8

E12

G12

H8
H9

H11

J9

J10

K8

K11

L12

N8
N12
R12
U11

VDD1

VDD2

VDDCA

VDDQ

U2400

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2420

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2410

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2430

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2421

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2411

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2431

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2422

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2412

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2432

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2423

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2433

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2424

10UF

20%
4V

2

X6S-CERM
0402-2

PLACEMENT_NOTE:

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM.
Distribute evenly.Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

24 OF 145

SHEET

23 OF 121

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-16GB

FBGA

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

26 7

26 7

113 26 7

113 26 7

26 25 7

26 25 7

26 25 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0>
MEM_B_ZQ<1>

243

1%

1/20W

MF

201

1

109 25

1

C2541

0.047UF

10%

6.3V

2

X5R
201

10%

6.3V
X5R
201

1

2

2

C2540

0.047UF

PP0V6_S3_MEM_VREFCA_A

25 109

PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

22 23 24 25 109 116

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

1

C2500

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

R2501

R2

P2
N2
N3

M3

F3

E3

E2
D2
C2

K3

K4

J3
J2

L3
L4

L8

G8

P8
D8

J8

B3

B4
H4

J11

A1

A2

A12
A13

B1

B13

T1

T13

U1
U2

U12
U13

C4

K9
R3

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

NC

1

2

OMIT_TABLE

C2501

0.1UF

10%
16V
X5R-CERM
0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

1

C2502

1.0UF

20%
10V

2

X5R-CERM
0201-1

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

1

C2503

1.0UF

20%
10V

2

X5R-CERM
0201-1

MEM_B_DQ<8>
MEM_B_DQ<15>
MEM_B_DQ<12>
MEM_B_DQ<9>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<20>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<16>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<3>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_DQ<7>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<6>
MEM_B_DQ<4>
MEM_B_DQ<26>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<25>
MEM_B_DQ<28>
MEM_B_DQ<24>

MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<0>
MEM_B_DQS_N<3>

MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DQS_P<3>

1

C2504

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2505

1.0UF

20%
10V

2

X5R-CERM
0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2506

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2507

10UF

20%
4V

2

X6S-CERM
0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8

A9
D4
D5
D6

G5

H5
H6

H12

J5

J6
K5
K6

K12

L5
P4
P5
P6

U8
U9

F2

G2

H3

L2

M2

A11
C12

E8

E12

G12

H8
H9

H11

J9

J10

K8

K11

L12

N8
N12
R12
U11

VDD1

VDD2

VDDCA

VDDQ

U2500

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2520

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2510

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2530

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2521

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2511

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2531

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2522

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2512

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2532

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2523

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2533

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2524

10UF

20%
4V

2

X6S-CERM
0402-2

PLACEMENT_NOTE:

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM.
Distribute evenly.

Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

25 OF 145

SHEET

24 OF 121

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-16GB

FBGA

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

113 26 7

26 7

26 7

113 26 7

113 26 7

26 24 7

26 24 7

26 24 7

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>

MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2>
MEM_B_ZQ<3>

243

1%

1/20W

MF

201

1

1

C2641

0.047UF

10%

6.3V

2

X5R
201

10%

6.3V
X5R
201

1

2

2

C2640

0.047UF

24 109

109 24

PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

22 23 24 25 109 116

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

1

C2600

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

R2601

R2

P2
N2
N3

M3

F3

E3

E2
D2
C2

K3

K4

J3
J2

L3
L4

L8

G8

P8
D8

J8

B3

B4
H4

J11

A1

A2

A12
A13

B1

B13

T1

T13

U1
U2

U12
U13

C4

K9
R3

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CKE0
CKE1

CK_T
CK_C

CS0*
CS1*

DM0
DM1
DM2
DM3

ODT

ZQ0
ZQ1

VREFCA
VREFDQ

NU

NC

1

2

OMIT_TABLE

C2601

0.1UF

10%
16V
X5R-CERM
0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

1

C2602

1.0UF

20%
10V

2

X5R-CERM
0201-1

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

1

C2603

1.0UF

20%
10V

2

X5R-CERM
0201-1

MEM_B_DQ<47>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<44>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<38>
MEM_B_DQ<34>
MEM_B_DQ<39>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<35>
MEM_B_DQ<62>
MEM_B_DQ<59>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<63>
MEM_B_DQ<58>
MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<4>
MEM_B_DQS_N<7>

MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<4>
MEM_B_DQS_P<7>

1

C2604

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2605

1.0UF

20%
10V

2

X5R-CERM
0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2606

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2607

10UF

20%
4V

2

X6S-CERM
0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3
A4
A5
A6

A10

U3
U4
U5
U6

U10

A8

A9
D4
D5
D6

G5

H5
H6

H12

J5

J6
K5
K6

K12

L5
P4
P5
P6

U8
U9

F2

G2

H3

L2

M2

A11
C12

E8

E12

G12

H8
H9

H11

J9

J10

K8

K11

L12

N8
N12
R12
U11

VDD1

VDD2

VDDCA

VDDQ

U2600

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2620

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2610

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2630

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2621

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2611

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2631

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2622

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C2612

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2632

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2623

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2633

10UF

20%
4V

2

X6S-CERM
0402-2

1

C2624

10UF

20%
4V

2

X6S-CERM
0402-2

PLACEMENT_NOTE:

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM.
Distribute evenly.

Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

26 OF 145

SHEET

25 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

113 22 7

113 22 7

113 22 7

113 22 7

113 22 7

113 22 7

113 22 7

22 7

22 7

113 22 7

113 22 7

113 22 7

113 22 7

113 22 7

113 23 7

113 23 7

113 23 7

113 23 7

113 23 7

113 23 7

113 23 7

23 7

23 7

113 23 7

113 23 7

113 23 7

113 23 7

113 23 7

23 22 7

23 22 7

23 22 7

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

109 116

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_A_CAA<9>
MEM_A_CAA<8>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<5>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_CAA<4>
MEM_A_CAA<3>
MEM_A_CAA<2>
MEM_A_CAA<1>
MEM_A_CAA<0>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<5>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CKE<3>
MEM_A_CAB<4>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>

R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730

68
68
68
68
68
39
39
82

68
68
68
68
68
68
68
68
68

39
39
82

68

68
68
68
82
82
82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

MF2011% 1/20W

1% 1/20W 201 MF

1/20W1% 201 MF

1% MF2011/20W

201 MF1% 1/20W
201 MF1% 1/20W

MF2011% 1/20W

2011/20W1% MF

MF2011%821/20W
201 MF1% 1/20W
201 MF1% 1/20W

MF2011/20W1%

MF2011/20W1%
2011/20W MF1%

1%
1%
1%
1% 2011/20W MF
1%681/20W MF201
1% MF201

1/20W
1%
1%
1% 1/20W 20182MF

1%681/20W 201 MF
1%
1% MF

1/20W 201
1%
1% 1/20W MF

1/20W

1/20W MF2011%

2011/20W MF

MF1/20W 201

2011/20W MF

2011/20W MF

MF1/20W 201

201 MF1/20W1%

MF2011/20W

201 MF1/20W
201

MF1% 201

1

C2700

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2701

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2703

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2705

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2707

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2709

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2721

12PF

5%
25V

2

NP0-C0G
0201

113 24 7

113 24 7

113 24 7

113 24 7

113 24 7

113 24 7

113 24 7

24 7

24 7

113 24 7

113 24 7

113 24 7

113 24 7

113 24 7

113 25 7

113 25 7

113 25 7

113 25 7

113 25 7

113 25 7

113 25 7

25 7

25 7

113 25 7

113 25 7

113 25 7

113 25 7

113 25 7

25 24 7

25 24 7

25 24 7

D

PP0V6_S0_DDRVTT

109 116

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<4>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CKE<3>
MEM_B_CAB<4>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<1>
MEM_B_CAB<0>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>

R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770

68
68
68
68
68
39
39
82
82
68
68
68
68
68
68
68
68
68
68
39

82
82
68
68
68
68

82
82
82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1% MF1/20W 201
1% MF1/20W 201

1/20W1% MF201
1/20W1% MF201

1% 201 MF1/20W

1/20W MF2011%

MF2011% 1/20W
1% 1/20W
1%

1/20W1% MF201
1/20W MF2011%

1% 201 MF1/20W

1% 201 MF

1/20W
1%391/20W 201 MF
1% 2011/20W MF
1% 201 MF

1/20W
1% MF1/20W 201
1% 2011/20W MF

1% 201 MF1/20W
1% MF1/20W68201

1/20W 2011%

1/20W MF

MF201
MF1/20W 201

2011/20W MF1%
2011/20W MF1%

201 MF1/20W1%
201 MF1/20W1%
201 MF1% 1/20W
201 MF1% 1/20W
201 MF1% 1/20W

2011/20W MF1%

MF
MF1/20W 2011%

2011%

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2711

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2713

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2715

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2717

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2719

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2712

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2714

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2716

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2718

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2741

12PF

5%
25V

2

NP0-C0G
0201

C

B

CRITICAL

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1
603

B

A

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0
dvt-fab10
27 OF 145
26 OF 121

A

D

345678

2 1

D

C

B

A

1

R2890

3.3K

5%
1/20W
MF
201

2

TBT_X_SPI_CS_L

29

TBT_X_ROM_WP_L

27

TBT_X_ROM_HOLD_L

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

113 99

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

100K

1 2

100K

1 2

1 2

1 2

1 2

1 2

DP_X_SNK0_ML_C_P<0>

DP_X_SNK0_ML_C_N<0>

DP_X_SNK0_ML_C_P<1>

DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<2>

DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<3>

DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

DP_X_SNK1_ML_C_N<0>

DP_X_SNK1_ML_C_P<1>

DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<2>

DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<3>

DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

5% MF

1M

5%

1M

1M

1/20W5% 201MF

1M

5% MF1/20W 201

R2891

3.3K

1/20W

R2862

2015% 1/20W MF

R2872

1/20W 201

R2860

MF 2011/20W

R2861

MF5%

2011/20W

R2870
R2871

1

1

5%
MF

201

2

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

R2893

3.3K

5%
1/20W
MF
201

2

6
1

3

7

DP_XA_HPD

DP_XB_HPD

TBT_XA_LSTX

TBT_XA_LSRX

TBT_XB_LSTX

TBT_XB_LSRX

PP3V3_UPC_XB_LDO

R2892

3.3K

5%

1/20W

8

VCC

MF

201

U2890

8MBIT-3.0V

W25Q80DVUXIE

CLK
CS*
WP*(IO2)
HOLD*(IO3)

GND EPAD

USON

DI(IO0)

DO(IO1)

OMIT_TABLE

CRITICAL

4

9

5
2

SNK0 AC Coupling

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201
X5R-CERM

1 2

10% 16V
X5R-CERM

1 2

10% 16V 0201
X5R-CERM

1 2

X5R-CERM

1 2

10% 16V
X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

16V 020110%

16V10%

SNK1 AC Coupling

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10%
X5R-CERM

1 2

X5R-CERM

1 2

10%
X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

16V10%

X5R-CERM

1 2

X5R-CERM

1 2

16V10% 0201

X5R-CERM

30 29 27

31 27

30 27

30 27

31 27

31 27

29

1

1

2

C2890

1UF

10%

6.3V

2

CERM
402

TBT_X_SPI_MOSITBT_X_SPI_CLK
TBT_X_SPI_MISO

DP_X_SNK0_ML_P<0>

020110% 16V

DP_X_SNK0_ML_N<0>

020116V10%

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

0201

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

020116V10%

DP_X_SNK0_ML_P<3>

0201

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

020116V10%

DP_X_SNK1_ML_P<0>

020116V10%

DP_X_SNK1_ML_N<0>

020116V10%

DP_X_SNK1_ML_P<1>

020116V

DP_X_SNK1_ML_N<1>

020116V10%

DP_X_SNK1_ML_P<2>

020116V

DP_X_SNK1_ML_N<2>

020116V10%

DP_X_SNK1_ML_P<3>

020116V10%

DP_X_SNK1_ML_N<3>

0201

DP_X_SNK1_AUXCH_P

020116V10%

DP_X_SNK1_AUXCH_N

29 29

29

113 29

113 29

113 29

113 29

IN
IN

IN
IN

PCIE_TBT_X_R2D_P<0>
PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>
PCIE_TBT_X_R2D_N<1>

Y23
Y22

T23
T22

PCIE_RX0_P
PCIE_RX0_N

PCIE_RX1_P
PCIE_RX1_N

U2800

TBT-AR-4C-CNTRL

SYM 1 OF 2

FCBGA

OMIT_TABLE

PCIE_TX0_P

PCIE_TX0_N

PCIE_TX1_P

PCIE_TX1_N

CRITICAL

113 29

113 29

113 29

113 29

10K PU ON CLOCKS PAGE

113 27

113 27

113 27

113 27

113 27

89 29

OUT

113 27

R2830

100K

5%

100K

5%

1/20W

MF

201

1 2

TF

R2855

1/20W

MF

201

1

2

1/20W

GND_VOID=TRUE

12

0.1UF

12

0.1UF

GND_VOID=TRUE

113 27

113 27

113 27

113 27

89 29

OUT

R2831

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 30

113 30

DP_XA_AUXCH_P

BI

DP_XA_AUXCH_N

BI

PLACE_NEAR=U2800.H6:2MM
PLACE_NEAR=U2800.J6:2MM

0201

0201

16V

10%

X5R-CERM

16V

10%

X5R-CERM

IN
IN

IN
IN

1

2

14K

R2850

4.75K

0.5%
0201

C2810
C2811

12

IN

12

IN

20

OUT

29

29

29

29

12

201

1% MF

113 32

113 32

113 32

113 32

113 32

113 32

113 32

113 32

29

29

30 27

30 27

30 29 27

PCIE_TBT_X_R2D_P<2>
PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>
PCIE_TBT_X_R2D_N<3>

PCIE_CLK100M_TBT_X_P
PCIE_CLK100M_TBT_X_N
TBT_X_CLKREQ_L

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2>
DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P
DP_X_SNK0_AUXCH_N

DP_X_SNK0_HPD

DP_X_SNK0_DDC_CLK

IN

DP_X_SNK0_DDC_DATA

BI

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

DP_X_SNK1_ML_P<0>
DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_N

DP_X_SNK1_HPD

DP_X_SNK1_DDC_CLK

IN

DP_X_SNK1_DDC_DATA

BI

DP_X_SNK_RBIAS

1/20W

101 29

29 15

101 29

103 101 29

OUT

PLACE_NEAR=U2800.Y18:2MM

JTAG_TBT_TDI

IN

JTAG_TBT_X_TMS

IN

JTAG_TBT_TCK

IN

JTAG_ISP_TDO

TBT_X_RBIAS
TBT_X_RSENSE

IN
IN

OUT
OUT

OUT
OUT

IN
IN

113

113

BI
BI

OUT

IN
IN

USBC_XA_D2R_P<2>
USBC_XA_D2R_N<2>

USBC_XA_R2D_C_P<2>
USBC_XA_R2D_C_N<2>

USBC_XA_R2D_C_P<1>
USBC_XA_R2D_C_N<1>

USBC_XA_D2R_P<1>
USBC_XA_D2R_N<1>

DP_XA_AUXCH_C_P
DP_XA_AUXCH_C_N

USB_UPC_XA_P
USB_UPC_XA_N

TBT_XA_LSTX
TBT_XA_LSRX
DP_XA_HPD

TBT_XA_USB2_RBIAS

PLACE_NEAR=U2800.H19:6MM

R2854

499

1/20W

1%
MF

201

1

2

54

OUT

TBTTHMSNS_X_D1_P

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

NC

M23
M22

AC5 N16

AC7

AC9

AB11

AC11

AB13

AC13

W11

AB15

AC15

AB17

AC17

AB19

AC19

AB21

AC21

W12

W15

AC23

AB23

AC1

PCIE_RX2_P
PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N
PCIE_CLKREQ*

AB7

DPSNK0_ML0_P
DPSNK0_ML0_N

AB9

DPSNK0_ML1_P
DPSNK0_ML1_N

DPSNK0_ML2_P
DPSNK0_ML2_N

DPSNK0_ML3_P
DPSNK0_ML3_N

Y11

DPSNK0_AUX_P
DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA
DPSNK1_ML0_P

DPSNK1_ML0_N
DPSNK1_ML1_P

DPSNK1_ML1_N
DPSNK1_ML2_P

DPSNK1_ML2_N
DPSNK1_ML3_P

DPSNK1_ML3_N

Y12

DPSNK1_AUX_P
DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P
PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS
THERMDA

THERMDA

V18

PCIE_ATEST
TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

SINK PORT 0

SINK PORT 1

PORT A

DEBUG

PCIE GEN3

SOURCE PORT 0

MISC

PORT B POC GPIO LC GPIO

PB_DPSRC_AUX_N

TBT PORTS

PCIE_TX2_P

PCIE_TX2_N

PCIE_TX3_P

PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P
DPSRC_ML0_N

DPSRC_ML1_P

DPSRC_ML1_N

DPSRC_ML2_P

DPSRC_ML2_N

DPSRC_ML3_P

DPSRC_ML3_N
DPSRC_AUX_P

DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7

GPIO_8
POC_GPIO_0
POC_GPIO_1
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6

TEST_EN

TEST_PWR_GOOD

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO
EE_CS*
EE_CLK

PB_RX1_P

PB_RX1_N

PB_TX1_P

PB_TX1_N

PB_TX0_P

PB_TX0_N
PB_RX0_P

PB_RX0_N

PB_DPSRC_AUX_P

PB_USB2_D_P
PB_USB2_D_N

PB_LSTX
PB_LSRX

PB_DPSRC_HPD
PB_USB2_RBIAS

MONDC_SVR

ATEST_P
ATEST_N

USB2_ATEST

MONDC_DPSNK_0
MONDC_DPSNK_1

MONDC_DPSRC

113

113

V23
V22

P23
P22

K23
K22

F23
F22

L4

PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L
TBT_X_PCIE_BIAS

R2
R1

N2
N1

L2
L1

J2
J1

W19
Y19

G1
N6
U1

U2
V1
V2
W1
W2
Y1
Y2
AA1
J4
E2
D4
H4
F2
D2
F1

E1
AB5
F4
D22

D23
AB3

AC4
AC3
AB4

B7
A7

A9
B9

A11
B11

A13
B13

Y16
W16

E19
D19

B4
B5
G2

F19
D6
A23

B23
E18
W13

W18

AB2

NC_DP_X_SRC_ML_P<0>
NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1>
NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2>
NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3>
NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

29

DP_X_SRC_RBIAS
I2C_TBT_X_SDA

I2C_TBT_X_SCL

TBT_X_ROM_WP_L

27

TBT_X_TMU_CLK_OUT
SMC_PME_S4_DARK_L
TBT_X_CIO_PLUG_EVENT_L
TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK
TBT_X_TMU_CLK_IN
I2C_TBT_XA_INT_L
I2C_TBT_XB_INT_L
TBT_X_USB_PWR_EN
TBT_X_FORCE_PWR
PM_BATLOW_L
PM_SLP_S3_L
TBT_X_CIO_PWR_EN

TBT_X_TEST_EN
TBT_X_TEST_PWR_GOOD
USBC_X_RESET_L
TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT
UPC_X_SPI_MOSI

UPC_X_SPI_MISO
UPC_X_SPI_CS_L
UPC_X_SPI_CLK

USBC_XB_D2R_P<2>
USBC_XB_D2R_N<2>

USBC_XB_R2D_C_P<2>
USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<1>
USBC_XB_R2D_C_N<1>

USBC_XB_D2R_P<1>
USBC_XB_D2R_N<1>

DP_XB_AUXCH_C_P
DP_XB_AUXCH_C_N

USB_UPC_XB_P
USB_UPC_XB_N

TBT_XB_LSTX
TBT_XB_LSRX
DP_XB_HPD

BI
BI

OUT

IN
IN

TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:5MM

1

R2853

NC
NC

NC

499

1%
1/20W
MF
201

2

BOM_COST_GROUP=TBT

29

29

29

29

IN

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

IN

IN

OUT

29

29

33 29

113 29

113 29

To SPI Flash

IN
IN

OUT
OUT

OUT
OUT

IN
IN

31 27

31 27

31 27

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

29 20

113 29

113 29

113 29

113 29

113 29

113 29

113 29

113 29

PLACE_NEAR=

U2800.N6:2MM

R2852

1/20W

1 2

1%

29

OUT
OUT

29

OUT

BI

91

OUT

103

IN

IN

29

IN
IN

29

IN

113 32

113 32

113 32

113 32

113 32

113 32

113 32

GND_VOID=TRUE

113 32

103 101 29

91

31 30 29

PU at PCH

PU at PCH

31 30

1

R2829

100

5%
1/20W
MF
201

2

C2812

0.1UF

C2813

0.1UF

GND_VOID=TRUE

DRAWING

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=U2800.N16:2MM

R2851

3.01K

1 2

1%

1/20W

MF

201

201MF

14K

PP3V3_S5_TBT_X_SW

1

R2836

2.2K

5%
1/20W
MF
201

2

29

IN

114 101 89 76 73 70 46 20 12

1

R2825

100

5%
1/20W
MF
201

2

1 2

1 2

DP_XB_AUXCH_P

10% 16V

X5R-CERM

10% 16V

X5R-CERM

0201

DP_XB_AUXCH_N

0201

LAST_MODIFIED=Wed Aug 24 09:57:49 2016

USB-C HIGH SPEED 1

Apple Inc.

R

PP3V3_S5_TBT_X_SW

1

R2834

2.2K

5%
1/20W
MF
201

2

1

R2837

2.2K

5%
1/20W
MF
201

2

IN

not used

1

R2827

100K

5%
1/20W
MF
201

2

BI

29

29

BI

BI

1

R2835

2.2K

5%
1/20W
MF
201

2

BI

27 33

113 31

113 31

27 33

29

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

28 OF 145

SHEET

27 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2931

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2984

1.0UF

20%

6.3V

2

X5R
0201-1

C2945

1.0UF

20%

6.3V
X5R

0201-1

1

C2932

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

1

C2933

2

1

C2964

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R
0201-1

C2946

1.0UF

20%

6.3V
X5R

0201-1

1.0UF

20%

6.3V
X5R
0201-1

1

2

SOURCED BY INTERNAL SWITCH

1

C2934

1.0UF

2

1

C2965

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY INTERNAL SWITCH

SOURCED BY INTERNAL SWITCH

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

C2947

1.0UF

20%

6.3V
X5R

0201-1

20%

6.3V
X5R
0201-1

VOLTAGE=3.3V

1

2

1

C2935

1.0UF

2

1

C2966

1.0UF

20%

6.3V

2

X5R
0201-1

PP0V9_TBT_X_DP

1

C2936

1.0UF

20%

6.3V
X5R
0201-1

SOURCED BY INTERNAL SWITCH

SOURCED BY INTERNAL SWITCH

20%

6.3V

2

X5R
0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R
0201-1

PP0V9_TBT_X_PCIE

29

PP0V9_TBT_X_USB

29

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=0.9V

PP0V9_TBT_X_CIO

29

PP3V3_TBT_X_ANA_PCIE

PP3V3_TBT_X_ANA_USB2

1

C2920

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R
0201-1

SOURCED BY
INTERNAL SWITCH

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12
A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F20

VSS_ANA

F16

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J18

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

P1

VSS_ANA

P2

VSS_ANA

R5

VSS_ANA

R18

VSS_ANA

R19

VSS_ANA

R20

VSS_ANA

R22

VSS_ANA

U2800

TBT-AR-4C-CNTRL

SYM 2 OF 2

FCBGA

OMIT_TABLE

CRITICAL

VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC

VCC0P9_LVR_SENSE

GND

VCC3P3_LC
VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR
VCC3P3_SVR
VCC3P3_SVR

VCC0P9_SVR
VCC0P9_SVR

SVR_IND
SVR_IND
SVR_IND

SVR_VSS
SVR_VSS

SVR_VSS

VCC0P9_LVR
VCC0P9_LVR
VCC0P9_LVR

VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANAVSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R6
F8
R13
H9
A2

A3
B3

L9
M9
E12
E13
F11
F12
F13
F15
J9

C1
C2
D1

A1
B1
B2

F18
H18
J11
H11

R23
T1
T2
T5
T20
U23
U22
V5
V6
V8
V9
V15
V16
V20
W5
W6
W8
W9
W20
W22
W23
Y9
Y13
Y20
AA22
AA23
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
D5
E4
E5
E6
F5
F6
H5
H8
J8
J12
J13
J15
L13
M12
N8
N9
N11
N12
N13
T6
T8
T9
T13
T15
T16
T18
AB1
AC2
M11

PP3V3_TBT_X_LC
PP3V3_S5_TBT_X_SW

1

C2991

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2975

10UF

20%

6.3V

2

CERM-X5R
0402-4

BYPASS=U2800.A2:A1:3MM

116

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

DIDT=TRUE
SWITCH_NODE=TRUE

1

C2976

10UF

20%

6.3V

2

CERM-X5R
0402-4

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_X

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V

C2992

1.0UF

0201-1

1

20%

6.3V

2

X5R

support page

XW

XW2900

SM

1 2

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

PP3V3_TBT_X_F

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

1

C2977

10UF

20%

6.3V

2

CERM-X5R
0402-4

CRITICAL

L2950

1 2

1210

SOURCED BY
INTERNAL SWITCH

20%

6.3V
X5R

1

2

C2993

1.0UF

0201-1

29

TBTTHMSNS_X_D1_N

C2954

CERM-X5R

10UF

20%

6.3V

0402-4

1

C2978

10UF

20%

6.3V

2

CERM-X5R
0402-4

1

2

OUT

C2990

1.0UF

0201-1

1

2

C2955

10UF

CERM-X5R

0402-4

2x 10uF outside BGA area

1

20%

6.3V

2

X5R

1

2

C2950

47UF

20%

6.3V
CER-X5R
0603

1

20%

6.3V

2

C2994

47UF

CER-X5R

C2917

12PF

5%
25V
NP0-C0G
0201

20%

6.3V
0603

1

C2951

47UF

2

1

2

1

2

20%

6.3V
CER-X5R
0603

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V

54

BOM_COST_GROUP=TBT

C2995

47UF

20%

6.3V

CER-X5R

0603

C2910

1.0UF

20%

6.3V
X5R
0201-1

1

2

1

2

1

2

1 2

0603

L2990

1.0UH-20%-2.1A-0.128OHM

CRITICAL

C2911

1.0UF

20%

6.3V
X5R
0201-1

C2952

47UF

20%

6.3V
CER-X5R
0603

FROM USB-C PORT
CONTROLLER (UPC)

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

PP3V3_TBT_X_S0

1

C2912

1.0UF

20%

6.3V

2

X5R
0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2913

1.0UF

20%

6.3V

2

X5R
0201-1

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SOURCED BY
INTERNAL SWITCH

29 33

1

C2914

1.0UF

20%

6.3V

2

X5R
0201-1

ISOLATE GND OF SVR_IND CAPSAdd XW or alias on

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

1

2

29 110 116

1

C2915

1.0UF

20%

6.3V

2

X5R
0201-1

C2980

0.1UF

10%
16V
X5R-CERM
0201

29

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

1

C2916

1.0UF

20%

6.3V

2

X5R
0201-1

USB-C HIGH SPEED 2

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

BRANCH

dvt-fab10

PAGE

29 OF 145

SHEET

28 OF 121

D

C

B

A

D

10.0.0

8 7 5 4 2 1

36

345678

2 1

TMU CLKs

TBT_X_TMU_CLK_OUT

27

MAKE_BASE=TRUE

TBT_X_TMU_CLK_OUT

USBC 5V EN PD

UPC_X_5V_EN

29 30

5%

R3032

1/20W 201MF

D

DP SRC OPTIONS

IF DP SRC NOT USED

NC_DP_X_SRC_ML_P<3..0>

27

NC_DP_X_SRC_ML_N<3..0>

27

NC_DP_X_SRC_AUX_P

27

NC_DP_X_SRC_AUX_N

27

FUSES FOR UPC

PP20V_USBC_XA_VBUS

29 30

C

PP20V_USBC_XB_VBUS

29 31

TBT_X_XTAL25M_OUT

IN

NOSTUFF

R3006

to/from Ridge

OUT

AR/ACE SPI BUS SERIES R'S

27

B

27

27

27

TBT_X_XTAL25M_IN

TBT_X_SPI_CLK
TBT_X_SPI_CS_L
TBT_X_SPI_MOSI
TBT_X_SPI_MISO

ROM

R3025

1/20W MF5% 201

PLACE_NEAR=U2800.V2:5mm

ACE/SMC I2C PU

100K

PLACE_NEAR=Q3100:5MM

6AMP-32V-0.0095OHM

PLACE_NEAR=Q3200:5MM

6AMP-32V-0.0095OHM

21

27

NC_DP_X_SRC_ML_P<3..0>

NC_DP_X_SRC_ML_N<3..0>

NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_AUX_N

CRITICAL

0603

F3000

21

PP20V_USBC_XA_VBUS_F

CRITICAL

0603

740S0135

F3001

21

PP20V_USBC_XB_VBUS_F

25MHz xtal

R3007

1M

5%

1/20W

MF

201

113

0

1

2

TBT_X_XTAL25M_OUT_R

21

2015%

MF1/20W

31

R3094
R3095
R3096
R3097
R3098
R3090
R3091
R3092
R3093

15

21

TBT_T_TMU_CLK_IN

PP3V3_G3H

R3038

10K

1/20W

DP_X_SRC_HPD

42

5%
MF

201

CRITICAL

21

SMC_USBC_INT_L

Y3000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

100

15
15
15
15
15
15
15
15

21

21

21

21

21

21

21

21

21

MAKE_BASE=TRUE

TBT_T_TMU_CLK_IN

109

100K

1/20W5%

201MF

21

103

R3026

R3040

1M

21

5%

1/20W

MF

201

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE
NO_TEST=1

MAKE_BASE=TRUE
MAKE_BASE=TRUE

30

31

C3002

20PF

21

5%
25V
C0G

0201

C3003

20PF

21

5%
25V
C0G

0201

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG

1/20W 2015% MF

UPC_XB_SPI_CLK

5% 2011/20W

UPC_XB_SPI_CS_L

5%

UPC_XB_SPI_MOSI
UPC_XB_SPI_MISO

1/20W

UPC_X_SPI_CLK

5%

1/20W

UPC_X_SPI_CS_L

1/20W MF5% 201

UPC_X_SPI_MOSI

1/20W MF5% 201

UPC_X_SPI_MISO

5%

MF

MF1/20W 201

201MF5% 1/20W

201MF5%

MF 201

201MF1/20W

101

46 29

OMIT

R3089

NOSTUFF

2 1

NONE

NONE

R3088

NOSTUFF

2 1

NONE

ACE Debug Support

UPC_XA_DBG_UART_TX

402NONE

UPC_XA_DBG_UART_RX

OMIT

TP_UPC_XB_DBG_UART_TX

402

NONENONE

TP_UPC_XB_DBG_UART_RX

Ridge PDs

DP_X_SNK0_DDC_CLK

27

MAKE_BASE=TRUE

DP_X_SNK0_DDC_CLK

DP_X_SNK0_DDC_DATA

27

DP_X_SNK0_DDC_DATA

27

DP_X_SNK1_DDC_CLK

27

DP_X_SNK1_DDC_DATA

29

IN

IN

IN

OUT

IN

IN

IN

OUT

MAKE_BASE=TRUE

DP_X_SNK1_DDC_CLK

MAKE_BASE=TRUE

DP_X_SNK1_DDC_DATA

MAKE_BASE=TRUE

29 27

89 27

89 27

30 27

29 30 31

28

29 27

29

29

103 46 29

31 30 31 30

31

31

Ace

31

31

29 27

AR

29 27

29 27

29 27

I2C_TBT_XB_INT_L
I2C_UPC_X_SCL2
I2C_UPC_X_SDA2
SMC_USBC_INT_L

UPC_XA_UART_TX UPC_XA_UART_RX

101 27

101 27

114 30

30

114 30

30

114 31

114 31

R3067

100K

1/20W

5%
MF

201

21

31

R3068

100K

1/20W

5%
MF

201

21

R3069

100K

1/20W

5%
MF

201

21

R3070

100K

1/20W

TBT_X_CIO_PLUG_EVENT_L
DP_X_SNK0_HPD
DP_X_SNK1_HPD
DP_XA_HPD
TBT_POC_RESET
PP3V3_TBT_X_LC

21

5%
MF

201

USBC_DBG

RIDGE DEBUG CONN

Place on bottom

ACE DEBUG CONN

Place on bottom

USBC_DBG

J3000

505070-1220

M-ST-SM

1413

21
43
65
87
109
1211

15

RIDGE JTAG ISOLATION

JTAG_TBT_TCK

JTAG_TBT_TDI

30

30

TP_UPC_XA_SWD_DATA

?

TP_UPC_XA_SWD_CLK
TP_UPC_XB_SWD_DATA

31

TP_UPC_XB_SWD_CLK

31

16

R3043
R3044

ACE A RPD STRAPPING

USBC_XA_CC1

USBC_XA_CC2

MAKE_BASE=TRUE

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

NC ALIASES / NO TEST

IN

15

I2C_TBT_XA_INT_L
I2C_TBT_X_SDA

I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCLTBT_X_SPI_CLK_DBG

NC_UPC_XB_I2C_ADDR

GND ALIASES

GND

30 31 103 104
105

GND

31

GND

30

GND

30

GND

30

GND

30

GND

30

GND

30

GND

31

GND

30

J3001

M-ST-SM

1413

21
43

65
7
9

8

10

1211

16

I2C_TBT_X_SCL

0

21

0

21

PLACE_NEAR=U1100.AK28:10mm

505070-1220

TBT_X_PCI_RESET_L
USBC_X_RESET_L

PP3V3_S5_TBT_X_SW
PP0V9_TBT_X_PCIE
PP0V9_TBT_X_USB
PP0V9_TBT_X_CIO

PLACE_NEAR=U1100.AJ29:10mm

JTAG_ISP_TCK

MF1/20W5%

JTAG_ISP_TDI

5% MF1/20W 0201

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP3004

MAKE_BASE=TRUE

0201

TP3001
TP3002

TP3003

30

30 29

15

15

30 29

31 29

20 27

33 27

28 33

28

28

28

29 27

29 27

29 27

15

30

31

IN

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

103

32 30

32 30

USBC_XB_CC1

31

USBC_XB_CC2

31

UPC_XA_HPD_RX

5% 1/20W 201MF

UPC_XB_HPD_RX

USB_UPC_XA_P

27

USB_UPC_XA_N

27

29 30

31

USB2_UPC_XB_P

31

MAKE_BASE=TRUE

NOSTUFF

NOSTUFF

R3036

1/20W MF 2015%

UPC_X_5V_EN
UPC_X_5V_EN

USB2_UPC_XB_P

USB2_UPC_XB_N

31

MAKE_BASE=TRUE

USB2_UPC_XB_N

TBT_X_CIO_PWR_EN

27 30 31

TBT_X_USB_PWR_EN

27 30 31

PM_BATLOW_L

27

SMC_PME_S4_DARK_L

27 101 103

SMC_PME_S4_DARK_L

30 31 103 104
105

UPC_X_SPI_CLK
UPC_X_SPI_CS_L
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_T_SPI_CLK
UPC_T_SPI_CS_L
UPC_T_SPI_MOSI
UPC_T_SPI_MISO

JTAG_ISP_TDO

31

27 29

27 29

27 29

27 29

101 103

101 103

101 103

101 103

27 101 103

IN

TBT_POC_RESET

TBT_X_CIO_PLUG_EVENT_L

IN

UPC_XA_FAULT_L

UPC_XB_FAULT_L

PP3V3_S4

30

ACE B RPD STRAPPING

ACE PDs

30 29

UPC_XA_HPD_RX

31 29

UPC_XB_HPD_RX

R3035

R3081

2 1

5% 1/20W MF 0201

R3082

2 1

1/20W MF5%

0

0

0

0

0201

21

21

R3084

R3085

5% 1/20W MF 0201

0

21

MF1/20W5%

0

21

SIGNAL ALIASES

UPC_X_5V_EN

MAKE_BASE=TRUE

R3086

5%

R3087

MF

SMC_USBC_INT_L

SMC_USBC_INT_L

TBT_X_CIO_PLUG_EVENT_L

R3078

R3079

5%
MF

0

21

1/20W

0201

5% 1/20W
MF 0201

0

21

USB_UPC_PCH_XB_P

1/20W

0201MF

0

21

USB_UPC_PCH_XB_N

1/20W5%

0201

MAKE_BASE=TRUE

TBT_X_CIO_PWR_EN

MAKE_BASE=TRUE

TBT_X_USB_PWR_EN

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

SMC_USBC_INT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

0

21

MAKE_BASE=TRUE

JTAG_TBT_X_TMS

MAKE_BASE=TRUE

JTAG_TBT_T_TMS

MAKE_BASE=TRUE

PP3V3_S4

TBT_POC_RESET

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

R3033

1/20W

R3034

MF5% 1/20W 201

SMC_RESET_L

USB_UPC_XB_P

NOSTUFF

0201

USB_UPC_XB_N

NOSTUFF

34

27 15

103 101 15

NO_STUFF

100K

201MF5%

NO_STUFF

100K

14

14

29 27

14

14

114 110 103

OUTIN

OUTIN

12

12

21

27

27

I2C SERIES R'S

PLACE_NEAR=U5000:5mm

I2C_UPC_X_SDA2

32 31

32 31

30

I2C_UPC_X_SDA2

31

29

30

31

29

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2
I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

5% 201

5% MF

R3041

MF1/20W

R3042

1/20W 201

33

21

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_4_G3H_SDA

PLACE_NEAR=U5000:5mm

33

21

SMBUS_SMC_4_G3H_SCL

SMBUS_SMC_4_G3H_SCL

49

49

49

49

D

21

RIDGE 0.9V SVR XW

XW3000

P0V9_TBT_X_SVR_AGND

28

114 76 64 57 48

NO_XNET_CONNECTION=1

SM

21

TBT to ACE

TBT

Alpine Ridge U2800

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

27
29

27
29

27
29
27
29

(MASTER)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L

I2C_TBT_XB_INT_L

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL
I2C_TBT_X_SDA
I2C_TBT_XB_INT_L

103 46 12

103 48 47 46

Ridge PCIE Caps

GND_VOID=TRUE

113 111

113 111

113 111

113 111

113 111

103 15

103 46 29 30

103 15 14 31 30 29

113 111

113 111

IN

IN

IN

IN

IN

IN

IN

113 111

113 27

113 27

113 27

PCIE_TBT_X_R2D_C_P<0>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<0>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<1>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<1>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<2>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<2>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<3>

GND_VOID=TRUE

IN

IN

IN

IN

PCIE_TBT_X_R2D_C_N<3>

PCIE_TBT_X_D2R_C_P<0>

PCIE_TBT_X_D2R_C_N<0>

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3V

X5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3VX5R0201 20%

6.3V

X5R0201 20%

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

C3040

0.22UF

C3041

0.22UF

C3042

0.22UF

C3043

0.22UF

C3044

0.22UF

C3045

0.22UF

C3046

0.22UF

C3047

0.22UF

C3050

0.22UF

C3051

0.22UF

C3052

0.22UF

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2>

PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>

PCIE_TBT_X_R2D_N<3>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<1>PCIE_TBT_X_D2R_C_P<1>

GND_VOID=TRUE

Pri ACE

U3100

Sec ACE

U3200

30

30

30

31

31

31

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

113 27

113 27

113 27

113 27

113 27

113 27

113 27

113 27

111
113

111
113

111
113

C

B

A

POWER ALIASES

PP3V3_UPC_XB_LDO

27

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XA_LDO

30

PP3V3_UPC_XA_LDO

30

PP20V_USBC_XA_VBUS

29 30

PP20V_USBC_XB_VBUS

29 31

PPDCIN_G3H

30 31 103 104 105

PP5V_S4_X_USBC

30

PP5V_S4_X_USBC

31

PP5V_S4_X_USBC

34 116

PP3V3_TBT_X_S0

28 110 116

MAKE_BASE=TRUE

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PPDCIN_G3H

PP5V_S4_X_USBC

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP3V3_TBT_X_S0

31

30

32

32

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=20V

116 114 64 50

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
VOLTAGE=5V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V

14

14

114 47 46

114 47 46

USB3_EXTA_R2D_C_P

IN

IN

USB3_EXTA_R2D_C_N

PP3V3_S4

31

MAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

IN

OUT

30

MAKE_BASE=TRUE

SMC_DEBUGPRT_RX_L

TP_USBC_XA_RESET_L

DCI

PCH USB3

X5R-CERM2116V 10% 0201

USB2_UPC_XA_P

30

MAKE_BASE=TRUE

USB2_UPC_XA_P

USB2_UPC_XA_N

30

MAKE_BASE=TRUE

USB2_UPC_XA_N

14

14

OUT
OUT

0.1UF

0.1UF

21

10%

SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L

MAKE_BASE=TRUE

TP_USBC_XA_RESET_L

MAKE_BASE=TRUE

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

MAKE_BASE=TRUE

C3020

USB3_EXTA_R2D_P

MAKE_BASE=TRUE

C3021

USB3_EXTA_R2D_N

0201X5R-CERM 16V

R3076

5%
MF 0201

R3077

5% 1/20W
MF

MAKE_BASE=TRUE

0

21

USB_UPC_PCH_XA_P

1/20W

0

21

USB_UPC_PCH_XA_N

0201

SMC MOJO

31

31

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

14

14

IN
IN

OUT

OUT

PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>

PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_N<3>

30

30

30

113 27

113 27

113 27

113 27

113 27

30

IN

IN

IN

IN

IN

BOM_COST_GROUP=TBT

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

SYNC_MASTER=X363_AGOTETI SYNC_DATE=08/08/2016

PAGE TITLE

C3053

0.22UF

C3054

0.22UF

C3055

0.22UF

C3056

0.22UF

C3057

0.22UF

PCIE_TBT_X_D2R_N<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<3>

OUT

OUT

OUT

OUT

OUT

111
113

111
113

111
113

111
113

111
113

USB-C Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

30 OF 145

SHEET

29 OF 121

D

A

8 7 5 4 2 1

36

D

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

345678

2 1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

105 104 103 31 29

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_XA_VBUS

29

PP3V3_UPC_XA_LDO

29

PP3V3_G3H

109

GND

PP5V_S4_X_USBC

29

FUSE

Add on
support page

1

C3100

10UF

20%

6.3V

2

CERM-X5R
0402-1

29

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

1

C3101

1UF

10%
35V

2

X5R
0402

B11

A11

PP_5V0

PP_5V0

D11

C11

PP_5V0

PP_5V0

A7

A6

PP_HV

PP_HV

B7

A8

PP_HV

PP_HV

H11

H10

PP_CABLE

J10

VBUS

VBUS

S2
5

K11

J11

VBUS

G2
4

H1

VBUS

B1

VDDIO

VIN_3V3

3

2

NC

TP_Q3100_DRAIN

UPC_XA_GATE2

G1

H2

LDO_3V3

VOUT_3V3

A2

K1

LDO_1V8A

LDO_1V8D

G1

S1

1

8

UPC_XA_GATE1

E1

LDO_BMC

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20%
4V

2

X5R-CERM
0201

105 104 103 31 29

P3V3_TBT_X_SX_EN_R

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R
0201-1

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0520
VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

33

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0520
VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R
0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R
0402-1

29

C

B

PP3V3_UPC_XA_LDO

1M

1M

1M

R3109

21

5% 201MF1/20W

R3108

21

1/20W

5% 201MF

21

R3105

5% MF1/20W

29

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

UPC_XA_UART_RX

201

29 30

29 30

29 30 31

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

CRITICAL

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

R3103

15K

0.1%
1/20W
TF-LF

0201

TO SMC

29 31

IN

29

OUT

29
114

29
114

27 29 31

IN

27 29 31

IN

27 29

OUT

29

29

OUT

29 31 103 104 105

OUT

29

OUT

29

IN

GND I2C_ADDR
PRIMARY ONLY

1

29

2

29

29

29

29

29

29

29

29

29

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN

OUT

TBT_POC_RESET
TP_USBC_XA_RESET_L

UPC_XA_DBG_UART_TX

UPC_XA_DBG_UART_RX

TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN

DP_XA_HPD

UPC_XA_HPD_RX

UPC_X_5V_EN

SMC_PME_S4_DARK_L

UPC_XA_FAULT_L

GND

GND

UPC_XA_R_OSC

I2C_UPC_XA_DBG_CTL_SCL

29 30

I2C_UPC_XA_DBG_CTL_SDA

29 30

I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_TBT_XA_INT_L

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

SMC_USBC_INT_L
GND

GND
GND
GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL
OMIT_TABLE

SS

SENSEP
SENSEN

HV_GATE1
HV_GATE2

C_CC1
C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1
C_SBU2

NC

H7
B10

A10
B9

A9

L9

USBC_XA_CC1

L10

USBC_XA_CC2

K9

USBC_XA_CC1

K10

USBC_XA_CC2

K6
L6

K7
L7

K8
L8

L11

USBC_XA_USB_DBG_TOP_P
USBC_XA_USB_DBG_TOP_N

USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_BOT_N

USBC_XA_SBU1
USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

UPC_XA_SS

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R
0201

BI
BI

BI
BI

29

29

32 115

32 115

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.2000

BI

29 32

BI

1

C3114

32

BI

32

BI

32

BI

32

BI

220PF

10%
16V

2

CER-X7R
0201

1

C3113

220PF

10%
16V

2

CER-X7R
0201

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.2000

B

A

29

BI

29

BI

PU to PP3V3_S4 if convenient
for layout.
Otherwise PU to PP3V3_UPC_XA_LDO

USB2_UPC_XA_P

USB2_UPC_XA_N

PP3V3_S4

29

NO_XNET_CONNECTION=1

PLACE_NEAR=U3100:5mm

27 113

BI

27 113

BI

L3000

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

4

32

1

R3110

100K

5%
1/20W
MF
201

2

29

29

29 30 31

29 31

27

27

29

29

29

29

TP_UPC_XA_SWD_DATA
TP_UPC_XA_SWD_CLK

IN

OUT

IN

OUT

UPC_XA_UART_RX
UPC_XA_UART_TX

TBT_XA_LSTX
TBT_XA_LSRX

USB_UPC_XA_F_P
USB_UPC_XA_F_N

DP_XA_AUXCH_P
DP_XA_AUXCH_N

BI
BI
BI
BI

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P
USB3_EXTA_R2D_N

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

GND

GND

GND

GND

GND

GND

L1

B8

H4

H5

G8

H8

D8

GND

E8

GND

F6

GND

F7

GND

F8

GND

G6

GND

G7

PAGE TITLE

SYNC_DATE=08/08/2016SYNC_MASTER=X362_GKOO

A

1

R3111

100K

NO_XNET_CONNECTION=1

8 7 5 4 2 1

5%
1/20W
MF
201

2

GND

PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION

29

BOM_COST_GROUP=USB-C

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

USB-C PORT CONTROLLER A

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

31 OF 145

30 OF 121

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