Apple MacBook Pro 15 A1707 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

SCHEM,MLB_BAFFIN,X363G

2 1

CK

ECNREV DESCRIPTION OF REVISION

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

APPD

DATE

2016-08-24000689728910 ENGINEERING RELEASED

D

1 2 3 4 5

1 2 3 4

5 6 6 7 8 9

7

8

9 10 11 12 13 14

11

12

13

14

MLB_BAFFIN BOM Configuration BOM Configuration PD Parts CPU DMI/PEG/FDI/RSVD CPU Clock/Misc/JTAG/CFG CPU DDR3 Interfaces CPU Power CPU Ground CPU Decoupling 1 [10] CPU Decoupling 2 [11] PCH RTC/HDA/JTAG/SATA/CLK PCH DMI/FDI/PM/GFX/PCI PCH PCI-E/USB

J80_MLB

J80_MLB_BAFFIN_CLEAN

J80_MLB

X363_AGOTETI

J80_MLB

J80_DTUZMAN_MLB_BAFFIN

X363_SEAN

X363_SAKKOC

J80_MLB

X363_SAKKOC

07/07/2015 12/02/2015 11/16/2015 01/21/2016 11/06/2015 11/06/2015 08/16/2015 08/17/2015 11/22/2015 02/01/2016 04/14/2016 11/06/2015 04/14/2016

61

65

66 63 64 65

69

70

71 66 72

7367 68 69 7010 71 72 73

74

76

78

79

80

81 74 82

AUDIO Speaker Amps & Conn AUDIO JACK CONNECTOR62 DC-In & Battery Connectors PBUS Supply & Battery Charger CORE & SA IMVP IC CORE IMVP POWER BLOCK SA IMVP IC GT & GTX IMVP POWER BLOCK Power - 5V 3.3V Supply PMIC-1 & Power Control PMIC-1 1.2V 0.6V VCCIO PMIC-1 1V 1.8V VCCPCH PMIC-1 Aliases & TPs Power FETs

X363_AUDIO

J80_MLB

J80_DTUZMAN_MLB_BAFFIN

J80_MLB

X363_ZIFENGSHEN

J80_SILUCHEN_MLB_BAFFIN

J80_SAKKOC_MLB_BAFFIN

01/25/2016 11/06/2015 11/06/2015 11/06/2015 12/10/2015 09/03/2015 11/18/2015 09/03/2015 12/09/2015 12/08/2015 11/06/2015 04/14/2016 12/08/2015 12/11/2015

D

C

15 16 17 18 19 20 21 22 23 24 25 26 27

15

PCH GPIO/MISC/NCTF 16 PCH Power 17 18 19 20 22 23 24 25 26 27 28

PCH DECOUPLING

CPU/PCH Merged XDP

Chipset Support 1

Chipset Support 2

LPDDR3 VREF MARGINING

LPDDR3 DRAM Channel A (0-31)

LPDDR3 DRAM Channel A (32-63)

LPDDR3 DRAM Channel B (0-31)

LPDDR3 DRAM Channel B (32-63)

LPDDR3 DRAM Termination

USB-C HIGH SPEED 1

USB-C HIGH SPEED 22928

X363_SAKKOC

J80_MLB

X363_SAKKOC

J80_MLB

04/29/2016 01/25/2016 11/06/2015 01/25/2016 04/29/2016 01/14/2016 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015

11/06/2015

75 76 77 78 79

84 85 86 87

88 80 89 81 82 83 84 85 86

90

91

92

93

94

95

968711/06/2015 88

97

LCD Backlight Driver eDP Display Connector POLARIS_CONTROLLER POLARIS POWER POLARIS GND Connector TEMP SENSORS NAND 1/2 NAND 2/2 POLARIS PMIC SSD NAND VR SSD SUPPORT Lifeboat Constraints

J80_DTUZMAN_MLB_BAFFIN

J80_ZIFENGSHEN_MLB_BAFFIN

X363_JSAMUELS

J80_MLB

X363_JSAMUELS

X363_ZIFENGSHEN

X363_BBABADI

Constraints

12/03/2015 12/03/2015 04/01/2016 05/18/2016 04/01/2016 04/01/2016 11/06/2015 08/09/2016 08/09/2016 08/09/2016 04/01/2016 04/15/2016 01/20/2016 05/18/2016

C

B

29 30 31 32 33 34 35 36 37 38 39 40 41 42

30 31 32 33 34 35 37 38 39 40 41 42 43 44

USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR WIFI/BT: MODULE 1 WIFI/BT: MODULE 2 Camera/DFR 1 Camera/DFR 2 Camera/DFR 3 Berkelium - 1 Berkelium - 2 T208 Support

X363_AGOTETI

X362_GKOO

J80_MLB

X362_MLB

J80_ZIFENGSHEN_MLB_BAFFIN

X363_SAKKOC

J80_MLB

X363_SAKKOC

X362_T208

08/08/2016 08/08/2016 11/06/2015 03/30/2016 03/29/2016 12/04/2015 04/29/2016 11/06/2015 04/29/2016 03/22/2016 04/25/2016 01/27/2016 03/15/2016 06/30/2016

89 90 91 92 93 94

98

99

100

101

102

103 95 104 96 97 98 99 100 101 102

105

106

107

108

109

110

111

eDP Mux GPU PCC BAFFIN PCI-E Baffin CORE/FB POWER Baffin FRAME BUFFER I/F Baffin 1V05 GPU / 1V35 FB Power Supply GDDR5 Frame Buffer A GDDR5 Frame Buffer B GFX IMVP VCore Regulator [106] Baffin GPIOs,CLK & Straps Baffin DP/GPIO Baffin VSS & MISC USB-C HIGH SPEED 1 USB-C HIGH SPEED 2

dpmux

X363_SEAN

J80_SEAN

J80_DTUZMAN_MLB_BAFFIN

J80_SEAN

J80_DTUZMAN_MLB_BAFFIN

X363_SEAN

J80_MLB

08/22/2015 01/27/2016 01/27/2016 02/01/2016 04/29/2015 12/08/2015 04/29/2015 04/29/2015 12/08/2015 01/28/2016 01/27/2016 01/27/2016 11/06/2015 11/06/2015

B

43 44 45 46 47 48 49 50 51 52 53 54 55 56

45 47 49 50 51 52 53 54 55 56 57 58 59 60

Connectors&ESD External A USB3 Connector MESA SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Power Sensors: Extended 2 Thermal Sensors Sensor Extended 3 Fans

X363_SAMANTHA

J80_MLB

X362_P49

X363_ZIFENGSHEN

J80_ZIFENGSHEN_MLB_BAFFIN

X363_ZIFENGSHEN

01/08/2016 08/26/2015 01/08/2016 04/14/2016 11/19/2015 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 05/19/2016 04/14/2016

103 104 105 106

112

113

114

115 107 116 108 109 110 111 112 113 114 115 116

117

120

121

122

123

124

125

126

127

USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Power Aliases - 1 Power Aliases - 2 Signal Aliases Memory Bit/Byte Swizzle ICT & FCT 1 ICT & FCT 2 NC & No Test Desense Caps

J80_AGOTETI_MLB_BAFFIN

J80_MLB

X362_MLB

J80_ZIFENGSHEN_MLB_BAFFIN

J80_MLB

X363_SAKKOC

J80_MLB

X363_SAKKOC

J80_BBABADI_MLB_BAFFIN

X363_BBABADI

X363_ZIFENGSHEN

12/07/2015 11/06/2015 11/06/2015 03/30/2016 03/29/2016 12/04/2015 08/16/2015 01/14/2016 01/13/2016 11/06/2015 04/14/2016 12/10/2015 01/26/2016 04/15/2016

A

DRAWING

TITLE=MLB_BAFFIN ABBREV=ABBREV

LAST_MODIFIED=Wed Aug 24 09:57:44 2016

Schematic / PCB #'s

051-00647 1

820-00281 1

57 58 59 60

SCHEM,MLB-BAFFIN,X363G

PCBF,MLB-BAFFIN,X363G

61 62 63 64

SPI Debug Connector HDA Bridge AUDIO JACK CODEC AUDIO Speaker Amps & Conn

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALSCH

CRITICALPCB

J80_MLB

X363_AUDIO

11/06/2015 01/11/2016 01/25/2016 01/25/2016

This is the PVT design

117 118 119 120

128

130

141

142

Desense Caps Project Specific Constraints 639 BOM Configuration 639 BOM Configuration 2

LAST_MODIFICATION=Wed Aug 24 09:57:44 2016

3

DESENSE

X363_ZIFENGSHEN J80_MLB J80_MLB

05/18/2016 06/02/2016 07/23/2015 07/23/2015

DRAWING TITLE

SCHEM,MLB-BAFFIN,X363

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

1 OF 145

SHEET

1 OF 121

1245678

A

SIZEDRAWING NUMBER

D

345678

2 1

D

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00076 COMMON PARTS,MLB-BAFFIN,X363 X363_COMMON 985-00126

DEV,MLB-BAFFIN,X363

X363_DEVEL:PVT

985-00232 X363_DEVEL:PVTDEV,MLB-BAFFIN,PVT,X363

639 BOMs have been moved to the end of the schematic

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

X363 BOM Groups

BOM GROUP BOM OPTIONS

X363_COMMON X363_COMMON1 X363_COMMON2 X363_COMMON3 X363_COMMON4

X363_PROGPARTS X363_DEVEL:ENG X363_DEVEL:DVT X363_DEVEL:PVT

ENGISNS

ALTERNATE,COMMON,X363_COMMON1,X363_COMMON2,X363_COMMON3,X363_COMMON4,X363_PROGPARTS

SOC:HYNIX,SE:PROD,SKIP_5V3V3:AUDIBLE,DIPLEXER:MURATA,T208_PROG:REV5,BOARD_ID:17,VCCHDA:S0

XDP:YES,SAMCONN,SOC_BOOT:SPI,DPMUX_XTAL:NO,GPUCLK:OSC,BAFFIN,AP_TEMP,VCCPLLOC:S3,WIFI_SAK:NO

CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,OTHERRC:YES,DDRRC:YES,TBTRC:YES,TPADRC:YES,LID_FEATURE_ON EDP:YES,CPUPEG:X8X4X4,TBTTHRM_SNS,GPUTHRM_SNS,S3_STATE:YES,GPU_ROM:YES,SVID_PU:CORE BOOTROM_PROG:DVT,BT_PROG:DVT,WIFI_PROG:DVT,UPCROM_PROG:DVT,SMC_PROG:PVT,DPMUXMCU:PROG,PCC:NO

ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG,GPUROM:BLANK,PCC:YES

ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG

ALTERNATE,XDP_CONN,USBC_DBG

TBTISNS,LOADISNS,TPADISNS,DDRISNS,OTHERISNS

Module Parts

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

C

B

GPU Options

BOM GROUP BOM OPTIONS

2GB_MC_BAFFIN FB_2GB_MICRON,VRAM:GRP1 2GB_HY_BAFFIN FB_2GB_HYNIX,VRAM:GRP1 2GB_SM_BAFFIN FB_2GB_SAMSUNG,VRAM:GRP2 4GB_SM_BAFFIN FB_4GB_SAMSUNG,VRAM:GRP1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

337S00227 U05001 CRITICAL 337S00228 U0500 337S00229 998-04701

1 1 U0500 1 CRITICAL

1 CRITICAL337S00258

4

338S00254 CRITICAL2

1 U7000 CRITICAL353S01016 338S00221 338S00142

337S00330

1

337S00332 CRITICALUA000

1

998-04866

1 UA000998-04867

2677-04532 CRITICALJ5250,J5260

CPU,SKY,SR2FT,R1,PRQ,4/2,2.9,BGA1440

CPU,SKY,SR2FU,R1,PRQ,4/2,2.7,BGA1440

CPU,SKY,SR2FQ,R1,PRQ,4/2,2.6,BGA1440

INTERPOSER,INTEL,BGA1440,MM940989

IC,SKL PCH-H,SFF,SR2NH,PRQ,D1,BGA939

IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96

IC,TBT,ALPINE RIDGE DP,QT5S,QS,C1,BGA337

IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM

IC,PMU,P650839,7X7MM.BGA168

IC,CODEC,CLIFDEN,CS42L83A,B0,WLCSP49

IC,GPU,BAFFIN,ULA,A1,PS,BGA769

IC,GPU,BAFFIN,PROA,A1,PS,BGA769

IC,GPU,BAFFIN,LEA,A1,PS,BGA769

INTERPOSER,AMD,C988,BGA769,VDDC

SUBASSY (T&R) PCBA, AMR, INTERPOSER, X363

U0500

U1100

U3100,U3200,UB300,UB400

U2800,UB000

U63001

UA000

UA0001 CRITICALINTERPOSER,AMD,C989,BGA769,VDDCI/MVDD

CRITICAL CRITICAL

CRITICAL353S00961

CRITICAL1 U7800 CRITICAL

CRITICALUA000 CRITICAL337S00331

CRITICAL

CPU_SKL:2.9 CPU_SKL:2.7 CPU_SKL:2.6

CPU_SKL:SOCKET

BAFFIN_ULA

BAFFIN_PROA

BAFFIN_LEA

STARDUST:VDDCI_MVDD

STARDUST:VDDC

Development/Base BOMs

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 BASE685-00076 COMMON PARTS,MLB-BAF,X363 BASE_BOMCRITICAL 985-00126

WIFI/BT Diplexers

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

FLTR,DIPLEXER,2.45/5.54GHZ,0805

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

FB_4GB_MICRON,VRAM:GRP14GB_MC_BAFFIN

Main DRAM Parts

333S00050 333S00070

4 4

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

U2300,U2400,U2500,U2600

CRITICAL3155S0979 U3810,U3820,U3830 DIPLEXER:MURATA

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL CRITICAL

DEVEL_BOM1 CRITICALDEVELDEV,MLB-BAF,X363

16G_SAMSUNG_2133

16G_MICRON_2133

Strategic Silicon

PART# COMMENT

337S00229

333S00050

333S00070 07

335S00149

335S00204 02

335S00205 02

335S00219 02

339S00154 02

339S00155 02

338S00166

337S00225

337S00285

337S00286

333S00044

333S00043

333S00078

333S00074

333S00075

343S00135

343S00136

343S00137

338S00138

353S3978 02

338S00097

353S00961 09

338S00142

359S00006

STRATEGIC VALUE

08337S00227

08337S00228

08

07

02

08

07

10

09338S00193

02

08338S00254

09

07353S00604

08353S4316

08338S00221

09353S00853

05339S00056

08

09353S00795

CPU

MAIN MEMORY

SSD NAND

SSD CONTROLLER

SSD PMIC

GPU

VIDEO MEMORY

T208

BERKELIUM

MOJAVE

SECURE ELEMENT

ALPINE RIDGE

ACE

CLIFDEN

AUDIO AMP

BAYSIDE

BANJO

TUBA

ICEBOCK

GREEN CLOCK

DEBUG MUX

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

C

B

A

FB VDRAM Parts

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

333S00044 333S00043 333S00078 333S00074 333S00075

4 4 4 4 4

IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA

UA400,UA450,UA500,UA550

UA400,UA450,UA500,UA550IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA

UA400,UA450,UA500,UA550

CRITICAL CRITICAL

Sub-BOM DIPLEXER

BOM NUMBER BOM NAME BOM OPTIONS

685-00085 DIPLEXERS,MURATA,X363G DIPLEXER:MURATA

FB_2GB_MICRON

FB_2GB_HYNIX

FB_2GB_SAMSUNGCRITICAL FB_4GB_SAMSUNG

FB_4GB_MICRON

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Main DRAM SPD Straps

BOM GROUP BOM OPTIONS

16G_SAMSUNG_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG0:LRAM_16G_SAMSUNG_2133 16G_MICRON_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG1:LRAM_16G_MICRON_2133

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=07/07/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

2 OF 145

SHEET

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A

8 7 5 4 2 1

36

Programmable Parts

345678

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

2 1

D

338S1231 341S00701 335S00013 341S00699 353S00926 341S00707 341S00708 335S00024

341S00709

341S3565

335S0724 1 UA701

1 1 1 1 2 1 1 1 1341S00695 1 1 U9800

IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA

IC,SMC-B1,EXT (v2.37F7) PVT,X363G

IC,SPI SERIAL FLASH,64M BITS,3V,8P SOIC,QE=1

IC,EFI ROM (V0193), DVT, X363G

IC,CD3215,ACE,B03,BLNK,BGA96

T29,AR1 (V10.5) PVT, X363G

T29,AR2 (V10.5) PVT, X363G

IC,SERIAL-FLASH,2MBIT,4V,8-USON,2x3x,6MM

IC,BT ROM (V28), DVT, X362/X363

WIFI ROM (P107) DVT,NEW,WW1,X362/X363

IC, EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG

U5000 U5000 U6100 U6100

U2890,UB090

U2890 UB090 U3750 U3750 U3710

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

SMC_PROG:BLANK

SMC_PROG:PVT

BOOTROM_PROG:BLANK

BOOTROM_PROG:DVT

UPCROM_PROG:BLANK

UPCROM_PROG:DVT

BT_PROG:BLANK

BT_PROG:DVT

WIFI_PROG:DVT

DPMUXMCU:PROG

GPUROM:BLANK

Blank

TI

Blank

Macronix/Winbond

Blank

Winbond

Blank Macronix/Winbond

Rohm/On Semi

Blank

D

C

B

A

SYNC_MASTER=J80_MLB_BAFFIN_CLEAN SYNC_DATE=12/02/2015

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

3 OF 145 3 OF 121

A

D

345678

2 1

D

C

B

Pogo Pins

APN 870-01771

PG0410

POGO-2.3OD-4.63H-SM

SM

1

PG0411

POGO-2.3OD-4.63H-SM

SM

1

PG0420

POGO-2.3OD-4.63H-SM

SM

1

PG0421

POGO-2.3OD-4.63H-SM

SM

1

PG0430

POGO-2.3OD-4.63H-SM

SM

1

PG0471

POGO-2.3OD-4.63H-SM

SM

1

PG0470

POGO-2.3OD-4.63H-SM

SM

1

APN 870-01772

PG0400

POGO-2.3OD-4.06H-SM

SM

1

PG0401

POGO-2.3OD-4.06H-SM

SM

1

APN 860-00392

BS0400

3.4OD1.75ID-1.12H-SM

1

BS0410

3.4OD1.75ID-1.12H-SM

1

APN 806-06520

BS0420

3.4OD1.75ID-1.45H-SM

1

APN 806-06521

BS0430

3.4OD1.75ID-1.9H-SM

1

BS0440

3.4OD1.75ID-1.9H-SM

1

BS0450

3.4OD1.75ID-1.9H-SM

1

APN 860-00413

BS0460

3.4OD1.75ID-1.57H-SM

1

APN 860-00469

BS0470

2.7X1.8R-1.4ID-0.91H-SM

1

SMT Bosses

USB-C Left BOT side - North

USB-C Right BOT side - North

DFR Touch BOT side

DFR Display BOT side - Left

Keyboard BOT side - Left

Trackpad BOT side - Left

Lifeboat BOT side - North

eDP TOP side - Left

BS0401

3.4OD1.75ID-1.12H-SM

1

USB-C Left BOT side - South

BS0411

3.4OD1.75ID-1.12H-SM

1

USB-C Right BOT side - South

APN 806-06600

BS0480

3.4OD1.75ID-2.12H-SM

1

BS0431

3.4OD1.75ID-1.9H-SM

1

DFR Display BOT side - Right

BS0441

3.4OD1.75ID-1.9H-SM

1

Keyboard BOT side - Right

BS0451

3.4OD1.75ID-1.9H-SM

1

Trackpad BOT side - Right

BS0461

3.4OD1.75ID-1.57H-SM

1

Lifeboat BOT side - South

BS0701

2.7X1.8R-1.4ID-0.91H-SM

1

eDP TOP side - Right

USB-C Right

BOT side - Left

Rubber Mount Standoffs

APN 860-00452

BM0400

3.09OD1.4ID-3.25H-SM

1

2

APN 860-00435

BM0401

2.8OD1.2ID-1.55H-SM

1

2

BM0402

2.8OD1.2ID-1.55H-SM

1

2

BM0403

2.8OD1.2ID-1.55H-SM

1

2

BM0404

2.8OD1.2ID-1.55H-SM

1

2

BM0405

2.8OD1.2ID-1.55H-SM

1

2

BM0406

2.8OD1.2ID-1.55H-SM

1

2

BM0407

2.8OD1.2ID-1.55H-SM

1

2

BM0408

2.8OD1.2ID-1.55H-SM

1

2

BM0409

2.8OD1.2ID-1.55H-SM

1

Shield Can TH

APN 998-2691

TH0400

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0401

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0410

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0411

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0420

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0421

TH-NSP

1

SL-1.1X0.4-1.4X0.7

T208 through holes are non-plated... for now

TH0440

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0441

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0450

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0451

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0460

TH-NSP

1

SL-1.1X0.4-1.4X0.7

TH0461

TH-NSP

1

SL-1.1X0.4-1.4X0.7

System Memory - BOT side - Left

System Memory - BOT side - Right

TBT Left - BOT side - North

TBT Left - BOT side - South

TBT Right - BOT side - North

TBT Right - BOT side - South

T208 - TOP side - North

T208 - TOP side - South

SSD - BOT side - North

SSD - BOT side - South

SSD - TOP side - North

SSD - TOP side - South

Frame Buffer Memory - BOT side - Left

Frame Buffer Memory - BOT side - Right

Shield Can Fence

1

SH0400

SM

SHLD-FENCE-MLB-M8-X379

1

SH0410

SM

SHLD-FENCE-MLB-M8-X379

1

SH0420

SM

SHLD-FENCE-MLB-M8-X379

1

SH0430

SM

SHLD-FENCE-M8-X379

1

SH0440

SM

SHLD-FENCE-MLB-M8-X379

1

SH0450

SM

SHLD-FENCE-MLB-M8-X379

1

SH0460

SM

SHLD-FENCE-MLB-M8-X379

1

SH0470

SM

SHLD-FENCE-MLB-M8-X379

OMIT_TABLE

DRAM - BOT side

APN 806-06590

OMIT_TABLE

AR Right - BOT side

APN 806-06586

OMIT_TABLE

AR Left - BOT side

APN 806-06588

T208 - TOP side

APN 806-07814

OMIT_TABLE

SSD - TOP side

APN 806-06584

OMIT_TABLE

SSD - BOT side

APN 806-06585

OMIT_TABLE

Diplexer - BOT side

APN 806-06591

OMIT_TABLE

VRAM - BOT side

APN 806-08026

D

C

B

A

APN 806-07958

TOUCH-COWLING-HOOK-X378

1

BS0704

SM

DFR Touch - TOP side

2

BM0410

2.8OD1.2ID-1.55H-SM

1

2

BM0411

2.8OD1.2ID-1.55H-SM

1

2

BM0483

2.8OD1.2ID-1.55H-SM

1

2

APN 860-00500

BM0484

2.8OD1.2ID-3.5H-SM

1

2

APN 860-00500

BM0485

2.8OD1.2ID-3.5H-SM

1

2

BM0486

2.8OD1.2ID-3.5H-SM

1

2

BM0487

2.8OD1.2ID-3.5H-SM

1

2

Shield Can Omit Table

806-08023 1 SH0400 CRITICAL

1 CRITICALSH0410806-08019 1 CRITICALSH0420806-08021

806-07918

1 SH0450 CRITICAL806-07917

806-08024 CRITICALSH04601

BOM_COST_GROUP=MECHANICALS

SHIELD,FENCE,DRAM,X378

SHIELD,FENCE,ALPINE RIDGE,RIGHT,X378

SHIELD,FENCE,ALPINE RIDGE,LEFT,X378

SHIELD,NAND,TOP,ALT,X363

SHIELD,NAND,BOTTOM,ALT,X363

SHIELD,DIPLEX,EG,X378

FENCE,VRAM,EG,X378

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

SH0440 CRITICAL1

SH0470 CRITICAL1806-08026

PAGE TITLE

PD Parts

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/16/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

4 OF 145

SHEET

4 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

113 13

IN IN IN IN

OUT OUT OUT OUT

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

E8

DMI_RXN0

F6

DMI_RXN1

E5

DMI_RXN2

J9

DMI_RXN3

D8

DMI_RXP0

E6

DMI_RXP1

D5

DMI_RXP2

J8

DMI_RXP3

A8

DMI_TXN0

B6

DMI_TXN1

A5

DMI_TXN2

B4

DMI_TXN3

B8

DMI_TXP0

C6

DMI_TXP1

B5

DMI_TXP2

D4

DMI_TXP3

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 1 OF 13

DMI

PEG_RCOMP

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8

PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0

PEG_RXP1

PEG_RXP2

PEG_RXP3

PEG_RXP4

PEG_RXP5

PEG_RXP6

PEG_RXP7

PEG_RXP8

PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

G2

D25 F24 D23 F22 D21 F20 D19 F18 E17 E16 E15 E14 E13 E12 E11 E10

E25 E24 E23 E22 E21 E20 E19 E18 D17 F16 D15 F14 D13 F12 D11 F10

CPU_PEG_RCOMP

PEG_GPU_D2R_N<0> PEG_GPU_D2R_N<1> PEG_GPU_D2R_N<2> PEG_GPU_D2R_N<3> PEG_GPU_D2R_N<4> PEG_GPU_D2R_N<5> PEG_GPU_D2R_N<6> PEG_GPU_D2R_N<7> PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_N<3> PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_N<2> PCIE_TBT_T_D2R_N<3>

PEG_GPU_D2R_P<0> PEG_GPU_D2R_P<1> PEG_GPU_D2R_P<2> PEG_GPU_D2R_P<3> PEG_GPU_D2R_P<4> PEG_GPU_D2R_P<5> PEG_GPU_D2R_P<6> PEG_GPU_D2R_P<7> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_D2R_P<3> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_D2R_P<2> PCIE_TBT_T_D2R_P<3>

PPVCCIO_S0_CPU

1

R0510

24.9

1% 1/16W MF-LF 402

2

PLACE_NEAR=U0500.G2:5mm

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

111

IN

5 8 109

NC_DDI1_ML_C_N<0>

111

NC_DDI1_ML_C_P<0>

111

NC_DDI1_ML_C_N<1>

111

NC_DDI1_ML_C_P<1>

111

NC_DDI1_ML_C_N<2>

111

NC_DDI1_ML_C_P<2>

111

NC_DDI1_ML_C_N<3>

111

NC_DDI1_ML_C_P<3>

111

NC_DDI2_ML_C_N<0>

111

NC_DDI2_ML_C_P<0>

111

NC_DDI2_ML_C_N<1>

111

NC_DDI2_ML_C_P<1>

111

NC_DDI2_ML_C_N<2>

111

NC_DDI2_ML_C_P<2>

111

NC_DDI2_ML_C_N<3>

111

NC_DDI2_ML_C_P<3>

111

NC_DDI3_ML_N<2>

111

NC_DDI3_ML_P<2>

111

NC_DDI3_ML_N<3>

111

NC_DDI3_ML_P<3>

111

NC_DDI3_ML_N<0>

111

NC_DDI3_ML_P<0>

111

NC_DDI3_ML_N<1>

111

NC_DDI3_ML_P<1>

111

Port D pins out of order to match Intel symbol.

K37 K36

J34

J35 H36 H37

J38

J37

H33

H34 G38

F37 F35 F34 E36 E37

E33 F33 B33

C33 D34

C34

B34 B36

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

DDI3_TXN2 DDI3_TXP2 DDI3_TXN3 DDI3_TXP3

DDI3_TXN0 DDI3_TXP0 DDI3_TXN1 DDI3_TXP1

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 11 OF 13

EDP

EDP_DISP_UTIL

DIGITAL DISPLAY INTERFACES

EDP_AUXN EDP_AUXP

EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3

EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3

EDP_RCOMP

DDI1_AUXN DDI1_AUXP

DDI2_AUXN DDI2_AUXP

DDI3_AUXN DDI3_AUXP

B26 C26

E29 E28 B29 B28

D29 F28 A29 C28

D37 A33

E27 D27

E26 F26

B27 A27

NC

DP_INT_IG_AUX_N DP_INT_IG_AUX_P

DP_INT_IG_ML_N<0> DP_INT_IG_ML_N<1> DP_INT_IG_ML_N<2> DP_INT_IG_ML_N<3>

DP_INT_IG_ML_P<0> DP_INT_IG_ML_P<1> DP_INT_IG_ML_P<2> DP_INT_IG_ML_P<3>

CPU_EDP_RCOMP

NC_DDI1_AUXCH_C_N NC_DDI1_AUXCH_C_P

NC_DDI2_AUXCH_C_N NC_DDI2_AUXCH_C_P

NC_DDI3_AUXCH_N NC_DDI3_AUXCH_P

111

113 89

PPVCCIO_S0_CPU

1

R0530

24.9

1% 1/16W MF-LF 402

2

D

5 8 109

PLACE_NEAR=U0500.D37:5mm

C

B

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TXN6 PEG_TXN7 PEG_TXN8

PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8

PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

A25 C24 A23 C22 A21 C20 A19 C18 B17 B16 B15 B14 B13 B12 B11 B10

B25 B24 B23 B22 B21 B20 B19 B18 A17 C16 A15 C14 A13 C12 A11 C10

PEG_GPU_R2D_C_N<0> PEG_GPU_R2D_C_N<1> PEG_GPU_R2D_C_N<2> PEG_GPU_R2D_C_N<3> PEG_GPU_R2D_C_N<4> PEG_GPU_R2D_C_N<5> PEG_GPU_R2D_C_N<6> PEG_GPU_R2D_C_N<7> PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_N<1> PCIE_TBT_X_R2D_C_N<2> PCIE_TBT_X_R2D_C_N<3> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_N<1> PCIE_TBT_T_R2D_C_N<2> PCIE_TBT_T_R2D_C_N<3>

PEG_GPU_R2D_C_P<0> PEG_GPU_R2D_C_P<1> PEG_GPU_R2D_C_P<2> PEG_GPU_R2D_C_P<3> PEG_GPU_R2D_C_P<4> PEG_GPU_R2D_C_P<5> PEG_GPU_R2D_C_P<6> PEG_GPU_R2D_C_P<7> PCIE_TBT_X_R2D_C_P<0> PCIE_TBT_X_R2D_C_P<1> PCIE_TBT_X_R2D_C_P<2> PCIE_TBT_X_R2D_C_P<3> PCIE_TBT_T_R2D_C_P<0> PCIE_TBT_T_R2D_C_P<1> PCIE_TBT_T_R2D_C_P<2> PCIE_TBT_T_R2D_C_P<3>

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

111

TP-P5 TP-P5

TP-P5 TP-P5 TP-P5

TP0501 TP0502

TP0503 TP0504 TP0505

TP TP

TP TP TP

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 13 OF 13

OPC_RCOMP

OPCE_RCOMP

OPCE_RCOMP2

PROC_TRIGIN

PROC_TRIGOUT

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

DDR_VTT_CNTL

PM_DOWN

BT29 BR25 BP25

H23 J23

G27 G25 G29

BT13 BP31

CPU_EOPIO_RCOMP CPU_OPC_OPIO_RCOMP CPU_OPC_OPIO_RCOMP_ED2

PCH_CPU_TRIGGER CPU_PCH_TRIGGER_R

PCH_DISPA_BCLK PCH_DISPA_SDO CPU_PROC_AUD_SDO_R

PM_MEMVTT_EN

CPU_PCH_PM_DOWN_R

IN

5

IN IN

5

OUT

5

13

20

71

1

R0521

49.9

1% 1/20W MF 201

2

1

R0522

49.9

1% 1/20W MF 201

2

1

R0523

49.9

1% 1/20W MF 201

2

NC

B2

B38 BP1 BR2

C1

C38

BR33

AT13

AW13

NCTF NCTF NCTF NCTF NCTF NCTF

SKTOCC* ZVM*

MSM*

1 1

1 1 1

CPU_DC_B2_C1 CPU_DC_B38_C38

NC

CPU_DC_BR2_BR1 CPU_DC_C1_B2 CPU_DC_C38_B38

NC

CPU Daisy-Chain Strategy:

Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP's on each corner.

R0524

30

5

1 2

5%

1/20W

MF

201

CPU_PCH_TRIGGERCPU_PCH_TRIGGER_R

OUT

13

B

A

5

BOM_COST_GROUP=CPU & CHIPSET

CPU_PCH_PM_DOWN_R

CPU_PROC_AUD_SDO_R

SYNC_MASTER=X363_AGOTETI SYNC_DATE=01/21/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R0525

20

1 2

5%

1/20W

MF

201

CPU_PCH_PM_DOWN

OUT

13

R0526

20

1 2

5%

1/20W

MF

201

PCH_DISPA_SDI

OUT

20

CPU DMI/PEG/FDI/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

5 OF 145

SHEET

5 OF 121

A

D

8 7 5 4 2 1

36

PP1V0_S3

6 8 11 110

PLACE_NEAR=U0500.BM30:10mm

1

R0604

49.9

1% 1/20W MF 201

2

OMIT_TABLE

345678

2 1

D

PP1V0_S0SW

8 11 18 110

PP1V0_S3

6 8 11 110

65 47 46

48 47 46 13

OUT

U0500

Note: Confirm values for 0603 and 0601. Different for J145

NC

1

R0605

1K

1% 1/16W MF-LF 402

BI

CPU_PROCHOT_L

2

1

R0601

1K

1% 1/16W MF-LF 402

2

PLACE_NEAR=U0500.BR30:5mm

R0603

499

1 2

1%

402

1/16W

MF-LF

46

47 13

13

OUT

BI

IN IN IN

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC CPU_RESET_L CPU_PWRGD

BN1

BM30

BT34

BR30

BM34

BP35

BT31

PROC_SELECT*

CATERR*

PECI

PROCHOT*

J31

THERMTRIP*

PM_SYNC RESET* PROCPWRGD

SKYLAKE-4+4E

BGA

SYM 2 OF 13

(IPU) (IPU)

(IPD) (IPU)

(IPU)

JTAG DDR3

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

PROC_PRDY* PROC_PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

G1 H1 J2

BP27 BL30

BR28 BP28 BP30

BL32 BT28

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

OUT

IN

IN IN IN

IN

OUT

1

R0614

162

115 18 13

115 18

115 18 13

115 18

1% 1/16W MF-LF 402

2

1

R0613

121

1% 1/16W MF-LF 402

2

1

R0612

200

1% 1/16W MF-LF 402

2

D

C

B

A

P2MM

SM

1

PP0600 PP0601 PP0602

PP0603

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

TP_CPU_RSVD_R14

1

TP_CPU_RSVD_N29

1

TP_CPU_RSVD_AE29

1

TP_CPU_RSVD_AA14

6

These can be placed close to

J1800 and only for debug access

NOSTUFF

R0649

1K

5%

1/20W

MF

201

NOSTUFF

R0647

1K

5%

1/20W

MF

201

CPU_CFG<16> CPU_CFG<9> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>

NOSTUFF

1K

5%

1/20W

MF

201

1

2

1

2

R0648

NOSTUFF

1

R0643

1K

5% 1/20W MF 201

2

NOSTUFF

R0641

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0640

1K

5% 1/20W MF 201

2

CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4>

CPUCFG6_PD

1K

5%

1/20W

MF

201

1

2

1

2

R0646

CPUCFG5_PD

1

R0645

1K

5% 1/20W MF 201

2

EDP:YES

R0644

1K

5%

1/20W

MF

201

1

2

CPU_CFG<2>

NOSTUFF

1

R0642

1K

5% 1/20W MF 201

2

18 6

115 18 6

18 6

BOM GROUP BOM OPTIONS

CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

113 12

IN IN

CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P

CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P

PLACE_NEAR=U0500.BT31:157mm

R0611

10K

5% 1/16W MF-LF

402

1

2

D31 E31

C36 D35

A32 B31

CLK24N CLK24P

PCI_BCLKN PCI_BCLKP

BCLKN BCLKP

CLOCK PWR THERMAL

(IPU) (IPU) (IPU) (IPU)

BPM0* BPM1* BPM2* BPM3*

BR27 BT27 BM31 BT30

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>

18

BI

18

BI

18

BI

18

BI

C

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 12 OF 13

RESERVED

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_RCOMP

(IPU)

RSVD_TP RSVD_TP

CFG16 CFG18 CFG17 CFG19

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

RSVD RSVD

RSVD

VSS VSS

RSVD RSVD RSVD

BK24 BK16 BJ16 BJ24

BT25 BP23

BN22 BN23 BP22

AU13 AY13 J24 J3

BR17 BN33 BP16 BR16

BP17 BR35 BR31

BN35 BT17

C30

BT2 BR1

W3 W2

V6 W1

H24 E30 F30

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TP_CPU_RSVD_TP_BK24 TP_CPU_RSVD_TP_BK16 TP_CPU_RSVD_TP_BJ16 TP_CPU_RSVD_TP_BJ24

CPU_CFG_RCOMP CPU_CFG<16>

CPU_CFG<18> CPU_CFG<17> CPU_CFG<19>

NC NC NC NC

NC NC NC

NC NC

NC

TP_CPU_RSVD_TP_BT2 CPU_DC_BR1_BR2

NC NC NC

18 6

18

1

TP

TP-P5

TP0610

1

R0690

49.9

1% 1/16W MF-LF 402

2

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

CPU Clock/Misc/JTAG/CFG

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

6 OF 145

SHEET

6 OF 121

D

B

A

18 6

115 18 6

18 6

18

18 6

18

TP_CPU_RSVD_TP_BJ34 TP_CPU_RSVD_TP_BJ33

TP_CPU_RSVD_TP_BL33 TP_CPU_RSVD_TP_BM33

TP_CPU_RSVD_TP_D1

PPVCC_S0_CPU

8 55 109

TP_CPU_RSVD_R14

6

TP_CPU_RSVD_N29

6

TP_CPU_RSVD_AE29

6

TP_CPU_RSVD_AA14

6

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPUCFG5_PDCPUPEG:X8X8

NC NC NC

BJ34 BJ33

BL33

BM33

D1

V30 V12 V29 Y35

R14

N29 AE29 AA14

BN25 BN27 BN26 BN28 BR20

BM20

BT20 BP20 BR23 BR22

BT23

BT22

BM19

BR19 BP19

BT19

G3

G13

BT16

RSVD_TP RSVD_TP

RSVD_TP

VSS VSS VSS VCC

RSVD RSVD RSVD RSVD

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RSVD RSVD RSVD

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

8 7 5 4 2 1

36

D

C

B

A

0

1 2

5%

1/20W

MF

201

113 26 22

113 112

R0701

21

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

NOSTUFF

1 2

5%

1/20W

MF

201

OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

0

R0703

DDR0_PAR MEM_A_ALERT

CPU_DIMM_VREFCA

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9>

BR6

BT6 BP3 BR3 BN5 BP6 BP2 BN3

BL4

BL5

BL2

BM1

BK4 BK5 BK1 BK2

BT11

BR11

BT8 BR8

BP11 BN11

BP8 BN8

BL12 BL11

BL8

BJ8 BJ11 BJ10

BL7

BJ7

BG4 BG5

BF4

BF5 BG2 BG1

BF1

BF2

BD2 BD1 BC4 BC5 BD5 BD4 BC1

BC2 BG11 BG10

BG8

BF8 BF11 BF10

BG7

BF7

BB11 BC11

BB8

BC8 BC10 BB10

BC7

BB7

AG3

AU5 BN13

BP13 BR13

BJ26

AP1

AT4 AP3 AN3 AN1 AU1 AU4 AN2 AU3 AU2

DDR0_DQ0 DDR0_DQ1

SKYLAKE-4+4E

DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ30 DDR0_DQ31 DDR0_DQ32 DDR0_DQ33 DDR0_DQ34 DDR0_DQ35 DDR0_DQ36 DDR0_DQ37 DDR0_DQ38 DDR0_DQ39 DDR0_DQ40 DDR0_DQ41 DDR0_DQ42 DDR0_DQ43 DDR0_DQ44 DDR0_DQ45 DDR0_DQ46 DDR0_DQ47 DDR0_DQ48 DDR0_DQ49 DDR0_DQ50 DDR0_DQ51 DDR0_DQ52 DDR0_DQ53 DDR0_DQ54 DDR0_DQ55 DDR0_DQ56 DDR0_DQ57 DDR0_DQ58 DDR0_DQ59 DDR0_DQ60 DDR0_DQ61 DDR0_DQ62 DDR0_DQ63

DDR0_PAR DDR0_ALERT* DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

RSVD DDR0_CAA0

DDR0_CAA1 DDR0_CAA2 DDR0_CAA3 DDR0_CAA4 DDR0_CAA5 DDR0_CAA6 DDR0_CAA7 DDR0_CAA8 DDR0_CAA9

OMIT_TABLE

U0500

BGA

SYM 3 OF 13

MEMORY CHANNEL DDR0

DDR0_DQSN0 DDR0_DQSN1 DDR0_DQSN2 DDR0_DQSN3 DDR0_DQSN4 DDR0_DQSN5 DDR0_DQSN6 DDR0_DQSN7 DDR0_DQSN8

DDR0_DQSP0 DDR0_DQSP1 DDR0_DQSP2 DDR0_DQSP3 DDR0_DQSP4 DDR0_DQSP5 DDR0_DQSP6 DDR0_DQSP7 DDR0_DQSP8

RSVD

DDR0_CKN0 DDR0_CKP0 DDR0_CKE0

DDR0_CKN1 DDR0_CKP1 DDR0_CKE1

DDR0_CLKN2 DDR0_CLKP2

DDR0_CKE2

DDR0_CLKN3 DDR0_CLKP3

DDR0_CKE3

DDR0_CS0* DDR0_CS1* DDR0_CS2* DDR0_CS3*

DDR0_ODT0 DDR0_ODT1 DDR0_ODT2 DDR0_ODT3

VSS

DDR0_MA3 DDR0_MA4

DDR0_ECC0 DDR0_ECC1 DDR0_ECC2 DDR0_ECC3 DDR0_ECC4 DDR0_ECC5 DDR0_ECC6 DDR0_ECC7

RSVD RSVD

RSVD RSVD_TP RSVD_TP

RSVD

DDR0_CAB0 DDR0_CAB1 DDR0_CAB2 DDR0_CAB3 DDR0_CAB4 DDR0_CAB5 DDR0_CAB6 DDR0_CAB7 DDR0_CAB8 DDR0_CAB9

BJ23 AG2

AG1 AT1

AK1 AK2 AT2

AK3 AL3 AT3

AL1 AL2 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

U38

AP5 AP2

BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2

BR5 BL3 BP9 BL9 BG3 BD3 BG9 BC9 BA3

BP5 BK3 BR9 BJ9 BF3 BC3 BF9 BB9 AY3

AJ8 B30 BH30 BJ13 BJ14 BJ21

AE3 AD1 AG4 AH4 AH5 AN4 AH1 AH2 AP4 AH3

NC

NC NC

NC NC NC

NC NC

NC NC NC NC NC NC NC NC

NC

NC NC NC NC NCNC

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>

MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

OUT OUT OUT

OUT

OUT OUT

OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

345678

2 1

OMIT_TABLE

113 26 22

26 22

113 26 23

26 22

26 23

26 23 22

113 112

113

113 112

1 2

112

0

5%

1/20W

MF

201

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

0

1 2

R0702

5%

1/20W

MF

201

R0704

DDR1_PAR

MEM_B_ALERT

AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1

V5 V2 U1 U2 V1 V4 U5

U4 AA11 AA10 AC11 AC10

AA7 AA8 AC8 AC7

W8

W7 V10 V11

W11 W10

V7 V8 R2 P5 R4 P4 R5 P2 R1

P1 M4 M1

L4

L2 M5 M2

L5

L1

R11 P11

P7

R8 R10 P10

R7

P8

L11

M11

L7

M8

L10

M10

M7

L8

AJ7

AR8

DDR1_DQ0 DDR1_DQ1 DDR1_DQ2 DDR1_DQ3 DDR1_DQ4 DDR1_DQ5 DDR1_DQ6 DDR1_DQ7 DDR1_DQ8 DDR1_DQ9 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR1_DQ16 DDR1_DQ17 DDR1_DQ18 DDR1_DQ19 DDR1_DQ20 DDR1_DQ21 DDR1_DQ22 DDR1_DQ23 DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 DDR1_DQ28 DDR1_DQ29 DDR1_DQ30 DDR1_DQ31 DDR1_DQ32 DDR1_DQ33 DDR1_DQ34 DDR1_DQ35 DDR1_DQ36 DDR1_DQ37 DDR1_DQ38 DDR1_DQ39 DDR1_DQ40 DDR1_DQ41 DDR1_DQ42 DDR1_DQ43 DDR1_DQ44 DDR1_DQ45 DDR1_DQ46 DDR1_DQ47 DDR1_DQ48 DDR1_DQ49 DDR1_DQ50 DDR1_DQ51 DDR1_DQ52 DDR1_DQ53 DDR1_DQ54 DDR1_DQ55 DDR1_DQ56 DDR1_DQ57 DDR1_DQ58 DDR1_DQ59 DDR1_DQ60 DDR1_DQ61 DDR1_DQ62 DDR1_DQ63

DDR1_PAR DDR1_ALERT*

U0500

SKYLAKE-4+4E

BGA

SYM 4 OF 13

MEMORY CHANNEL DDR1

RSVD

DDR1_CKN0 DDR1_CKP0 DDR1_CKE0

DDR1_CKN1 DDR1_CKP1 DDR1_CKE1

DDR1_CLKN2 DDR1_CLKP2

DDR1_CKE2

DDR1_CLKN3 DDR1_CLKP3

DDR1_CKE3

DDR1_CS0* DDR1_CS1* DDR1_CS2* DDR1_CS3*

DDR1_ODT0 DDR1_ODT1 DDR1_ODT2 DDR1_ODT3

VSS

DDR1_MA3 DDR1_MA4

DDR1_ECC0 DDR1_ECC1 DDR1_ECC2 DDR1_ECC3 DDR1_ECC4 DDR1_ECC5 DDR1_ECC6 DDR1_ECC7

DDR1_DQSN0 DDR1_DQSN1 DDR1_DQSN2 DDR1_DQSN3 DDR1_DQSN4 DDR1_DQSN5 DDR1_DQSN6 DDR1_DQSN7 DDR1_DQSN8

DDR1_DQSP0 DDR1_DQSP1 DDR1_DQSP2 DDR1_DQSP3 DDR1_DQSP4 DDR1_DQSP5 DDR1_DQSP6 DDR1_DQSP7 DDR1_DQSP8

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

113 26 23

113 26 24

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

AM6

AR11

AN7 AN8

AN10

AR9 AR10 AN11

AT9

AR7

DDR1_CAA0 DDR1_CAA1 DDR1_CAA2 DDR1_CAA3 DDR1_CAA4 DDR1_CAA5 DDR1_CAA6 DDR1_CAA7 DDR1_CAA8 DDR1_CAA9

RSVD

DDR1_CAB0 DDR1_CAB1 DDR1_CAB2 DDR1_CAB3 DDR1_CAB4 DDR1_CAB5 DDR1_CAB6 DDR1_CAB7 DDR1_CAB8 DDR1_CAB9

BJ27 AN9

AM9 AT8

AM8 AM7 AT10

AM10 AM11 AT7

AJ11 AJ10 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

Y38

AL5 AL6

AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7

AA3 U3 AC9 W9 P3 L3 R9 M9 AY9

AB3 V3 AA9 V9 R3 M3 P9 L9 AW9

BK28 BK26 BK27 BK23 BK21 BJ35 BJ28 BJ36

AF9 AF8 AH11 AH10 AH8 AK5 AH9 AH7 AK6 AJ9

NC

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1>

OUT OUT OUT

NC NC

MEM_B_CKE<2>

OUT

NC NC

MEM_B_CKE<3>

MEM_B_CS_L<0> MEM_B_CS_L<1>

OUT

OUT OUT

NC NC

MEM_B_ODT<0>

OUT

NC NC NC

NC NC

NC NC NC NC NC NC NC NC

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

BI BI BI BI BI BI BI BI

NC

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

BI BI BI BI BI BI BI BI

NC

NC NCNC NC NC NC NC NC NC

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BOM_COST_GROUP=CPU & CHIPSET

113 26 24

26 24

113 26 25

26 24

D

26 25

26 25 24

C

113 112

B

113 112

113 26 25

PAGE TITLE

CPU DDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00647

REVISION

BRANCH

dvt-fab10

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

10.0.0

7 OF 145

7 OF 145 7 OF 1217 OF 121

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V0_S3

6 8 11 110

CPU_VCCST_PWRGD_R

8

PP1V0_S0SW

6 11 18 110

PPVCCGT_S0_CPU

AW36

AW37

AW38

AY29

VCCGT

U0500

OMIT_TABLE

VCCGT

BGA

SYM 7 OF 13

SKYLAKE-4+4E

VCCGT

AJ31

AJ32

VCCGT

AJ29

AJ30

AY30

AY31

VCCGT

POWER

VCCGT

AJ33

AJ34

AY32

AY35

VCCGT

AJ35

AJ36

AY36

AY37

VCCGT

AK31

AK32

8 55 109

AY38

BA13

VCCGT

AK33

AK34

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC NC NC

NC NC

BA14

BA29

VCCGT

AK35

AK36

OMIT_TABLE

AF29 AF30 AF31 AF32 AF33

AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32

AH36 AH35 J14

BK17

BK19

BK20

BL16 BL17 BL18 BL19 BL20

BL21 BM17 BN17

BL15 BM16

BP15 BR15 BT15

BN15

BM15

BA30

VCCGT

AK37

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

AJ13

VCCGTX

AJ14

VCCGTX VCCGTX_SENSE

VSSGTX_SENSE

BJ17

VCCOPC

BJ19

VCCOPC

BJ20

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

VCCOPC_SENSE VSSOPC_SENSE

H30

VCCST

H13

VCCST_PWRGD

G30

VCCSTG

H29

VCCSTG VCCEOPIO

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

BA31

BA32

BA33

BA34

VCCGT

AL13

AL29

AK38

AL30

U0500

SKYLAKE-4+4E

SYM 6 OF 13

POWER

BA35

BA36

BB13

BB14

VCCGT

AL35

AL36

VCCGT

AL37

VCCGT

AL31

AL32

BGA

BB31

BB32

VCCGT

AL38

VCCIO_SENSE

VSSIO_SENSE

VCCSA_SENSE

VSSSA_SENSE

VCCPLL_OC VCCPLL_OC

VCC_OPC_1P8 VCC_OPC_1P8

BB33

BB34

BB35

BB36

VCCGT

AM13

AM14

AM29

AM30

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCPLL VCCPLL

BB37

BB38

VCCGT

AM31

AM32

BC29

VCCGT

AM33

AG12 G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27

H14

J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36

M38 M37

H28 J28

BH13 G11

BL14 BM14

BC30

BC31

VCCGT

AM34

AM35

PPVCCIO_S0_CPU

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

PPVCCSA_S0_CPU

CPU_VCCSASENSE_P CPU_VCCSASENSE_N

PP1V0_S3

PP1V2_S0SW

109

NC NC

BC32

BC35

BC36

BC37

BC38

BD13

VCCGT

AN32

AN33

VCCGT

AN13

AM36

VCCGT

AN14

AN31

BD14

BD29

VCCGT

AN34

AN35

BD30

BD31

VCCGT

AN36

AN37

BD32

BD33

VCCGT

AP13

AN38

11 110

BD34

BD35

VCCGT

AP14

AP29

5 8 109

OUT OUT

8 53 109

OUT OUT

1

C0802

2

BD36

BE31

VCCGT

AP30

AP31

71 8

71 9

65 8

65 9

1UF

20%

6.3V X6S-CERM 0201

BE32

BE33

BE34

VCCGT

AP32

AP35

AP36

BE35

BE36

VCCGT

AP37

AP38

1

2

1

C0803

1UF

20%

6.3V

2

X6S-CERM 0201

BE37

BE38

VCCGT

AR29

AR30

R0864

100

5% 1/20W MF 201

70

IN

BF13

BF14

BF29

VCCGT

AR31

AR32

AR33

PPVCC_S0_CPU

1

R0865

100

5% 1/20W MF 201

2

PPVCCGT_S0_CPU PPVCCSA_S0_CPU

PLACE_NEAR=U0500.AG37:50.8mm PLACE_NEAR=U0500.AH38:50.8mm PLACE_NEAR=U0500.M38:50.4mm

1

R0866

100

5% 1/20W MF 201

2

8 55 109

8 53 109

CPU_VCCSASENSE_P CPU_VCCGTSENSE_P CPU_VCCSENSE_P

PPVCCIO_S0_CPU

PLACE_NEAR=U0500.H14:50.8mm

1

R0861

100

5% 1/20W MF 201

2

CPU_VCCIOSENSE_P

PULL-UPS FOR SENSE LINES

PP1V0_S3

6 8 11 110

1

R0840

1K

1% 1/16W MF-LF 402

2

R0841

60.4

BG33

BG34

VCCGT

AT38

AU14

1 2

1%

1/20W

MF

201

1

R0802

100

5% 1/20W MF 201

2

BG35

BG36

BH33

VCCGT

AU29

AU30

AU31

BH34

BH35

VCCGT

AU32

AU35

BH36

VCCGT

AU36

CPU_VCCST_PWRGD

PP1V0_S3

6 8 11 110

65

Place on bottom side of U0500

BF30

VCCGT

AR34

CPU_VIDALERT_L

IN

OUT

BF31

BF32

VCCGT

AR35

AR36

CPU_VIDSCLK

65

BI

BF35

BF36

BF37

VCCGT

AT14

AT31

AT32

CPU_VIDSOUT

BF38

VCCGT

AT33

BG29

BG30

VCCGT

AT34

AT35

BG31

BG32

VCCGT

AT36

AT37

6 8 55 109

65 8

CPU_VCCST_PWRGD_R

1

R0800

56.2

1% 1/20W MF 201

2

R0810

220

1 2

5%

1/20W

MF

201

R0811

0

1 2

5% 1/16W MF-LF

402

R0812

0

1 2

5% 1/16W MF-LF

402

65 9

65 8

BH37

BH38

VCCGT

AU37

AU38

OUT OUT

BJ37

VCCGT

AV29

CPU_VCCGTSENSE_N CPU_VCCGTSENSE_P

BJ38

BL36

BL37

BM36

VCCGT

AV30

AV31

AV32

AV33

5 8 109

71 8

BM37

BN36

VCCGT

AV34

AV35

PP1V2_S3_CPUDDR

8 109

PP1V2_S3_CPUDDR

8 109

PLACE_NEAR=U0500.Y12:5mm

8

PPVCC_S0_CPU

6 8 55 109

65 8

65 9

OUT OUT

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R

TP_CPU_RSVD_TP75 TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP78

PPVCC_S0_CPU

6 8 55 109

BN37

BN38

BP37

BP38

BR37

BT37

AH38

AH37

VCCGT

VSSGT_SENSE

VCCGT_SENSE

VCCGT

AV36

AW14

AW31

AW32

AW33

AW34

AW35

NC NC NC NC

1

C0801

10UF

20% 10V

2

X5R-CERM 0402-7

NC NC NC NC

BL31

BL34 BM22 BM24

AA6

AE12

AF5

AF6 AG5 AG9

AJ12 AL11

AP6

AP7

AR12

AR6

AT12

AW6

AY6

J5 J6

K12

K6

L12

L6

R6

T6

W6

Y12

BL25 BL22 BL24 BL23

U36

V13

AG37 AG38

BL26

BN16

BL28 BL27

BH31 BH32 BH29

Y7

Y8 E2 E1

E3 Y9

Y13

W4

W34

Y10

W5

Y14

W12

Y37

W33

Y11

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AB30 AB31 AA38 AB29

V14 V31 V32 V33 V34 V35 V36 V37

V38 W13 W14

OMIT_TABLE

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

RSVD RSVD RSVD RSVD

VCC VCC

VCC_SENSE VSS_SENSE

RSVD RSVD RSVD RSVD

VIDALERT* VIDSCK VIDSOUT

VSS

VSS RSVD_TP RSVD_TP

RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

U0500

SKYLAKE-4+4E

BGA

SYM 5 OF 13

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

BOM_COST_GROUP=CPU & CHIPSET

AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y36

PPVCC_S0_CPU

PAGE TITLE

6 8 55 109

CPU Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=08/16/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

8 OF 145

SHEET

8 OF 121

D

C

B

A

8 7 5 4 2 1

36

OMIT_TABLE

345678

2 1

D

C

B

AU34 AU33 AU12 AU11 AU10

AU9 AU8 AU7

AU6 AT30 AT29

AT6 AR38 AR37

AR5 AR14 AR13

AR4

AR1 AP34 AP33 AP12

AR3

AR2

AP9

AP11

AP8 AP10 AN12

AN6

AN5 AN30 AN29

AM38 AM37 AM12

AM5

AM2

AM4

AM1

AM3

AL34 AL33 AL14

AL8

AL12

AL7

AL4 AK30 AK29

AL10

AL9

AK4 AJ38 AJ37

AJ6 AJ3 AJ5 AJ2 AJ4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OMIT_TABLE

U0500

SKYLAKE-4+4E

BGA

SYM 8 OF 13

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ1 AH34 AH33 AG29 AH12 AG11 AH6 AG30 AG10 AG8 AF14 AG7 AG6 AF13 AF4 AF3 AF2 AF1 AF12 AE34 AE33 AE6 AD30 AD11 AD29 AD10 AD12 AD8 AD7 AD9 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AD6 AB6 AC38 AC37 AC12 AA30 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6 AA29

AW2

AW29

AW3

AW30

AW4

AW5 AY12 AV37 AY14 AY33 AY34

B9 BA10 AV38

AW1

AW12

BA37 BA38

BA6 BA7 BA8 BA9

BB1 BB12 BA11 BA12

BB2

BB6 BC12 BB29 BC13 BC14 BC33

BB3 BC34 BB30

BC6

BB4 BD10

BB5 BD37 BD38

BD6

BD7

BD8

BD9

BE1

BE2 BE29 BD11

BE3 BE30

BE4 BD12

BE6 BF12 BF33 BF34

BF6

BG12 BG13

BN2

BN19 BN20 BN21

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U0500

SKYLAKE-4+4E

BGA

SYM 9 OF 13

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BG14 BE5 BG38 BG6 BH1 BH10 BH11 BH12 BH14 BH2 BH3 BH4 BH5 BG37 BH9 BJ12 BJ15 BJ18 BJ22 BJ25 BJ29 BH6 BJ30 BH7 BJ31 BJ32 BK13 BK14 BH8 BK29 BK6 BL13 BL29 BL35 BL38 BL6 BM11 BM12 BM13 BM18 BM2 BM21 BM23 BM25 BM26 BM27 BM28 BM29 BM3 BM5 BM6 BM7 BM8 BM9 BK15 BK18 BK22 BK25 U6 BN24 G8 G9 H11 H12 H18

CPU_VCCGTSENSE_N

CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N CPU_VCCSENSE_N

1

R0961

100

5% 1/20W MF 201

2

1

R0963

100

5% 1/20W MF 201

2

1

R0965

100

5% 1/20W MF 201

2

1

R0966

100

5% 1/20W MF 201

2

OUT

OUT OUT

D

65 8

71 8

65 8

C

B

H22

H25

H32

H35

VSS

BGA

U0500

OMIT_TABLE

SKYLAKE-4+4E

SYM 10 OF 13

J10

VSS

J18

VSS

J22

VSS

G23

VSS

G24

VSS

G26

VSS

J32

VSS

J33

VSS

J25

VSS

J4

VSS

J7

VSS

K10

VSS

J36K1K2

VSS

K11

VSS

K3

VSS

K38

VSS

K4K5K7

VSS

L29

VSS

K8

VSS

K9

VSS

L33

VSS

L34M6M12

VSS

M13

VSS

L30

VSS

M14

VSS

N1

VSS

N10

VSS

N11

VSS

N12

VSS

N4

VSS

N2

N5N6N7

VSS

N3

VSS

N33

VSS

N9

VSS

N8

VSS

P12

VSS

P37

VSS

P38

VSS

P6

VSS

R12

VSS

T10

VSS

R29

VSS

T11

VSS

T12

VSS

T13

VSS

R30

VSS

T1T2T3

VSS

T14

VSS

T34

VSS

T4T5T7

VSS

T33

VSS

U37

VSS

T8

VSS

T9

VSS

A36

VSS

A37

VSS

BM35

BM38

VSS

N34

VSS

G6

VSS

A3

A4

A34

NCTFVSS

B3

B37

BR38

NCTFVSS

BT3

BT35

BT36C2D38

NCTFVSS

CPU_DC_BR38_BT36 CPU_DC_BT36_BR38

BT4

NCTFVSS

1

TP

1

TP0900

TP

TP0901

TP-P5 TP-P5

A

VSS

BN12

BN29

VSS

BN30

VSS

BN31

VSS

BN4

BN34

VSS

BN7

VSS

BN9

VSS

BP12

VSS

BP14

VSS

BN14

VSS

BP18

VSS

BP21

VSS

BN18

VSS

BP26

VSS

BP29

VSS

BP33

VSS

BP34

VSS

BP7

VSS

BP24

BR12

VSS

BR14

VSS

BR18

VSS

BR21

VSS

BR24

VSS

BR26

VSS

BR29

VSS

BR7

BR36

VSS

BT12

BT14

VSS

BT18

VSS

BT21

VSS

BT24

VSS

BT26

VSS

BT32

VSS

BT5

VSS

BT9

VSS

C11

VSS

C13

VSS

C15

VSS

C21

BR34

VSS

C23

VSS

C25

VSS

C27

VSS

C29

VSS

C31

VSS

C37

VSS

C5

VSS

C17

VSS

C8

VSS

C9

VSS

D10

VSS

D12

VSS

C19

VSS

D16

VSS

D18

VSS

D20

VSS

D22

VSS

D24

VSS

D26

VSS

D28

VSS

D3

VSS

D30

VSS

D33

VSS

D6

VSS

D14

VSS

E34

VSS

E35

VSS

E38

VSS

E4

VSS

E9

VSS

F11

F13

VSS

F15

VSS

F17

VSS

F19

VSS

F2

VSS

F21

VSS

F23

VSS

F25

VSS

F27

VSS

F29

VSS

F3

VSS

F31

VSS

F36

VSS

D9

VSS

F4

VSS

G10

VSS

F5

VSS

G12

VSS

G14

VSS

G16

VSS

F8

VSS

G18

VSS

G20

VSS

G22

VSS

F9

VSS

G28

VSS

G4

VSS

G5

SYNC_MASTER=J80_MLB SYNC_DATE=08/17/2015

PAGE TITLE

CPU Ground

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

9 OF 145 9 OF 121

A

D

345678

2 1

D

PPVCC_S0_CPU

109

CPU VCORE Decoupling

Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side Apple Implementation:

Place on bottom side of U0500

1

C1000

1UF

20% 4V

2

CERM-X6S 0201

Place on bottom side of U0500

1

C1023

1UF

20% 4V

2

CERM-X6S 0201

Place on bottom side of U0500

1

C1001

1UF

20% 4V

2

CERM-X6S 0201

1

C1024

1UF

20% 4V

2

CERM-X6S 0201

1

C1002

1UF

20% 4V

2

CERM-X6S 0201

1

C1025

1UF

20% 4V

2

CERM-X6S 0201

1

C1003

1UF

20% 4V

2

CERM-X6S 0201

1

C1026

1UF

20% 4V

2

CERM-X6S 0201

1

C1004

1UF

20% 4V

2

CERM-X6S 0201

1

C1027

1UF

20% 4V

2

CERM-X6S 0201

1

C1005

1UF

20% 4V

2

CERM-X6S 0201

1

C1028

1UF

20% 4V

2

CERM-X6S 0201

1

C1006

1UF

20% 4V

2

CERM-X6S 0201

1

C1029

1UF

20% 4V

2

CERM-X6S 0201

1

C1007

1UF

20% 4V

2

CERM-X6S 0201

1

C1030

1UF

20% 4V

2

CERM-X6S 0201

1

C1008

1UF

20% 4V

2

CERM-X6S 0201

1

C1031

1UF

20% 4V

2

CERM-X6S 0201

Vcc CPU Core Decoupling from 20140905 BOM

1

C1009

1UF

20% 4V

2

CERM-X6S 0201

1

C1032

1UF

20% 4V

2

CERM-X6S 0201

1

C1010

1UF

20% 4V

2

CERM-X6S 0201

1

C1033

1UF

20% 4V

2

CERM-X6S 0201

1

C1011

1UF

20% 4V

2

CERM-X6S 0201

1

C1034

1UF

20% 4V

2

CERM-X6S 0201

1

C1012

1UF

20% 4V

2

CERM-X6S 0201

1

C1035

1UF

20% 4V

2

CERM-X6S 0201

1

C1013

1UF

20% 4V

2

CERM-X6S 0201

1

C1036

1UF

20% 4V

2

CERM-X6S 0201

1

C1014

1UF

20% 4V

2

CERM-X6S 0201

1

C1037

1UF

20% 4V

2

CERM-X6S 0201

1

C1015

1UF

20% 4V

2

CERM-X6S 0201

1

C1038

1UF

20% 4V

2

CERM-X6S 0201

1

C1016

1UF

20% 4V

2

CERM-X6S 0201

1

C1039

1UF

20% 4V

2

CERM-X6S 0201

1

C1017

1UF

20% 4V

2

CERM-X6S 0201

1

C1040

1UF

20% 4V

2

CERM-X6S 0201

1

C1018

1UF

20% 4V

2

CERM-X6S 0201

1

C1041

1UF

20% 4V

2

CERM-X6S 0201

1

C1019

1UF

20% 4V

2

CERM-X6S 0201

1

C1042

1UF

20% 4V

2

CERM-X6S 0201

1

C1020

1UF

20% 4V

2

CERM-X6S 0201

1

C1043

1UF

20% 4V

2

CERM-X6S 0201

1

C1021

1UF

20% 4V

2

CERM-X6S 0201

1

C1044

1UF

20% 4V

2

CERM-X6S 0201

1

C1022

1UF

20% 4V

2

CERM-X6S 0201

1

C1045

1UF

20% 4V

2

CERM-X6S 0201

D

C

1

C1046

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C10A0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

1

C10A1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D0

20UF

20%

2.5V

2

X6S-CERM 0402-1

C1047

1UF

20% 4V CERM-X6S 0201

NOSTUFF

1

2

1

2

C10A2

20UF

20%

2.5V X6S-CERM 0402-1

1

C10D1

20UF

20%

2.5V

2

X6S-CERM 0402-1

C1048

1UF

20% 4V CERM-X6S 0201

NOSTUFF

1

C10A3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

1

C1049

1UF

20% 4V

2

CERM-X6S 0201

C10D2

20UF

20%

2.5V X6S-CERM 0402-1

1

C10A4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D3

2

20UF

20%

2.5V X6S-CERM 0402-1

1

C1050

1UF

20% 4V

2

CERM-X6S 0201

1

C10A5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1051

1UF

20% 4V

2

CERM-X6S 0201

1

C10A6

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10D5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1052

1UF

20% 4V

2

CERM-X6S 0201

1

C10A7

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D6

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10A8

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1053

1UF

20% 4V

2

CERM-X6S 0201

1

C10D7

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10A9

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1054

1UF

20% 4V

2

CERM-X6S 0201

1

2

NOSTUFF

1

C10E0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

C10B0

20UF

20%

2.5V X6S-CERM 0402-1

1

C1055

1UF

20% 4V

2

CERM-X6S 0201

1

C10B1

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10E1

2

20UF

20%

2.5V X6S-CERM 0402-1

1

C1056

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C10B2

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10E2

20UF

2

20%

2.5V X6S-CERM 0402-1

1

C1057

1UF

20% 4V

2

CERM-X6S 0201

1

C10B3

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10E3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

1

C10B4

20UF

20%

2.5V

2

X6S-CERM 0402-1

C1058

1UF

20% 4V CERM-X6S 0201

1

2

1

C1059

1UF

20% 4V

2

CERM-X6S 0201

C10B5

20UF

20%

2.5V X6S-CERM 0402-1

1

C1060

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C10B6

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10B7

20UF

20%

2.5V

2

X6S-CERM 0402-1

Noise Floor caps

1

C10N1

12PF

5% 25V

2

NP0-C0G 0201

1

C10N2

12PF

5% 25V

2

NP0-C0G 0201

1

C1061

1UF

20% 4V

2

CERM-X6S 0201

1

2

1

C10N3

12PF

5% 25V

2

NP0-C0G 0201

NOSTUFF

C10B8

20UF

20%

2.5V X6S-CERM 0402-1

1

2

1

C10N4

12PF

5% 25V

2

NP0-C0G 0201

C1062

1UF

20% 4V CERM-X6S 0201

NOSTUFF

1

C10B9

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10N5

12PF

5% 25V

2

NP0-C0G 0201

1

C10C0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10N6

12PF

5% 25V

2

NP0-C0G 0201

1

C10C1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

C10N7

12PF

5% 25V NP0-C0G 0201

NOSTUFF

1

C10C3

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C4

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10C6

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10C7

20UF

20%

2.5V

2

X6S-CERM 0402-1

C

B

PP1V2_S3_CPUDDR

109 116

1

C1068

220UF

20% 2V

23

ELEC SM-COMBO

1

C1069

220UF

20% 2V

23

ELEC SM-COMBO

Place on bottom side of U0500.

Place on bottom side of U0500

Place on bottom side of U0500.

Place on bottom side of U0500

1

C1070

220UF

20% 2V

23

ELEC SM-COMBO

1

C1071

220UF

20% 2V

23

ELEC SM-COMBO

1

C1072

220UF

20% 2V

23

ELEC SM-COMBO

1

C1073

220UF

20% 2V

23

ELEC SM-COMBO

NOSTUFF

1

C10Z1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10Z2

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10Z3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10Z4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10Z5

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10Z6

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10Z7

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10Z8

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10Z9

20UF

20%

2.5V

2

X6S-CERM 0402-1

Place near inductors on bottom side.

NOSTUFF

1

C10ZA

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10ZB

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10ZC

20UF

20%

2.5V

2

X6S-CERM 0402-1

B

A

1

C1080

20UF

20%

2.5V

2

X6S-CERM 0402-1

Place on bottom side of U0500

1

C1090

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1081

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1091

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1082

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1092

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1083

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1093

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1084

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1094

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1085

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1095

20UF

20%

2.5V

2

X6S-CERM 0402-1

CPU VDDQ Decoupling

Intel recommendation: 10x 10uF 0402, 4x 22uF 0602 Apple Implementation:

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

PPVCCIO_S0_CPU

109

CPU VCCIO Decoupling

Intel recommendation: 3x 10uF 0402 (opposite CPU) Apple Implementation:

Place near U0500 on bottom side

1

C1086

20UF

20%

2.5V

2

X6S-CERM 0402-1

Place near U0500 on bottom side

1

C1087

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1088

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1089

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C108A

20UF

20%

2.5V

2

X6S-CERM 0402-1

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU Decoupling 1 [10]

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/22/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

10 OF 145

SHEET

10 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

PPVCCGT_S0_CPU

109 116

Place on bottom side of U0500

1

2

Place on bottom side of U0500

1

2

Place on bottom side of U0500

C1100

1UF

20% 4V CERM-X6S 0201

C1124

1UF

20% 4V CERM-X6S 0201

1

C1101

1UF

20% 4V

2

CERM-X6S 0201

1

C1125

1UF

20% 4V

2

CERM-X6S 0201

CPU VGTSlice Decoupling

Vcc GT Slice Core Decoupling from 20140905 BOM

Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201 Apple Implementation:

1

C1102

1UF

20% 4V

2

CERM-X6S 0201

1

C1126

1UF

20% 4V

2

CERM-X6S 0201

1

C1103

1UF

20% 4V

2

CERM-X6S 0201

1

C1127

1UF

20% 4V

2

CERM-X6S 0201

1

C1104

1UF

20% 4V

2

CERM-X6S 0201

1

C1128

1UF

20% 4V

2

CERM-X6S 0201

1

C1105

1UF

20% 4V

2

CERM-X6S 0201

1

C1129

1UF

20% 4V

2

CERM-X6S 0201

1

C1106

1UF

20% 4V

2

CERM-X6S 0201

1

C1130

1UF

20% 4V

2

CERM-X6S 0201

1

C1107

1UF

20% 4V

2

CERM-X6S 0201

1

C1131

1UF

20% 4V

2

CERM-X6S 0201

1

C1108

1UF

20% 4V

2

CERM-X6S 0201

1

C1132

1UF

20% 4V

2

CERM-X6S 0201

1

C1109

1UF

20% 4V

2

CERM-X6S 0201

1

C1133

1UF

20% 4V

2

CERM-X6S 0201

Board Edge: 4x220uF, 7x 47uF rest on back side

1

C1110

1UF

20% 4V

2

CERM-X6S 0201

1

C1134

1UF

20% 4V

2

CERM-X6S 0201

1

C1111

1UF

20% 4V

2

CERM-X6S 0201

1

C1135

1UF

20% 4V

2

CERM-X6S 0201

1

C1112

1UF

20% 4V

2

CERM-X6S 0201

1

C1136

1UF

20% 4V

2

CERM-X6S 0201

1

C1113

1UF

20% 4V

2

CERM-X6S 0201

1

C1137

1UF

20% 4V

2

CERM-X6S 0201

1

C1114

1UF

20% 4V

2

CERM-X6S 0201

1

C1138

1UF

20% 4V

2

CERM-X6S 0201

1

C1115

1UF

20% 4V

2

CERM-X6S 0201

1

C1139

1UF

20% 4V

2

CERM-X6S 0201

1

C1116

1UF

20% 4V

2

CERM-X6S 0201

1

C1140

1UF

20% 4V

2

CERM-X6S 0201

1

C1117

1UF

20% 4V

2

CERM-X6S 0201

1

C1141

1UF

20% 4V

2

CERM-X6S 0201

1

C1118

1UF

20% 4V

2

CERM-X6S 0201

1

C1142

1UF

20% 4V

2

CERM-X6S 0201

1

C1119

1UF

20% 4V

2

CERM-X6S 0201

1

C1143

1UF

20% 4V

2

CERM-X6S 0201

1

C1120

1UF

20% 4V

2

CERM-X6S 0201

1

C1144

1UF

20% 4V

2

CERM-X6S 0201

1

C1121

1UF

20% 4V

2

CERM-X6S 0201

1

C1145

1UF

20% 4V

2

CERM-X6S 0201

1

C1122

1UF

20% 4V

2

CERM-X6S 0201

1

C1146

1UF

20% 4V

2

CERM-X6S 0201

1

C1123

1UF

20% 4V

2

CERM-X6S 0201

1

C1147

1UF

20% 4V

2

CERM-X6S 0201

D

C

1

C1148

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11A0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11F0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1149

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11A1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11F1

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11A2

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1150

1UF

20% 4V

2

CERM-X6S 0201

1

C11F2

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11A3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1151

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11A4

2

NOSTUFF

1

C11F3

20UF

20%

2.5V

2

X6S-CERM 0402-1

20UF

20%

2.5V X6S-CERM 0402-1

1

C1152

1UF

2

NOSTUFF

1

C11A5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11F4

20UF

20%

2.5V

2

X6S-CERM 0402-1

20% 4V CERM-X6S 0201

NOSTUFF

1

C11A6

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11F5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1153

1UF

20% 4V

2

CERM-X6S 0201

1

C11A7

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11F6

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1154

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11A8

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11F7

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1155

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11A9

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11B0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11E0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1156

1UF

20% 4V

2

CERM-X6S 0201

1

C11B1

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11E1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1157

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11B2

2

NOSTUFF

1

C11E2

2

20UF

20%

2.5V X6S-CERM 0402-1

20UF

20%

2.5V X6S-CERM 0402-1

1

C1158

1UF

20% 4V

2

CERM-X6S 0201

1

C11B3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11E3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1159

1UF

2

NOSTUFF

1

C11B4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

20% 4V CERM-X6S 0201

1

2

C11E4

20UF

20%

2.5V X6S-CERM 0402-1

1

C1160

1UF

2

NOSTUFF

C11B5

20UF

20%

2.5V X6S-CERM 0402-1

NOSTUFF

1

C11E5

20UF

2

20% 4V CERM-X6S 0201

NOSTUFF

1

C11B6

20UF

20%

2.5V

2

X6S-CERM 0402-1

20%

2.5V X6S-CERM 0402-1

1

C1161

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11B7

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1162

1UF

20% 4V

2

CERM-X6S 0201

1

C11B8

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11B9

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1163

1UF

20% 4V

2

CERM-X6S 0201

1

C11C0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1164

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11C1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1165

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11C2

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

NOSTUFF

1

C11C3

20UF

20%

2.5V

2

X6S-CERM 0402-1

C1166

1UF

20% 4V CERM-X6S 0201

1

C11C4

2

20UF

20%

2.5V X6S-CERM 0402-1

1

C1167

1UF

20% 4V

2

CERM-X6S 0201

1

C11C5

2

20UF

20%

2.5V X6S-CERM 0402-1

NOSTUFF

1

C11C6

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11C7

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

NOSTUFF

1

C11C8

20UF

20%

2.5V

2

X6S-CERM 0402-1

C11D4

20UF

20%

2.5V X6S-CERM 0402-1

NOSTUFF

1

C11D3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11C9

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

2

1

C11D0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

C11D2

20UF

20%

2.5V X6S-CERM 0402-1

NOSTUFF

1

C11D1

20UF

20%

2.5V

2

X6S-CERM 0402-1

C

1

C1168

220UF

20% 2V

23

ELEC SM-COMBO

1

C1169

220UF

20% 2V

23

ELEC SM-COMBO

1

C1170

220UF

20% 2V

23

ELEC SM-COMBO

1

C1171

220UF

20% 2V

23

ELEC SM-COMBO

1

C1172

220UF

20% 2V

23

ELEC SM-COMBO

B

PPVCCSA_S0_CPU

109

Place on bottom side of U0500

Place on bottom side of U100.

Place on bottom side of U0500

1

C11H0

1UF

20% 4V

2

CERM-X6S 0201

1

C11H1

1UF

20% 4V

2

CERM-X6S 0201

1

C11H2

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C11I0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11I1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11I2

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11I3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11I4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11I5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C11I6

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C11I7

20UF

20%

2.5V

2

X6S-CERM 0402-1

CPU VCCSTG Decoupling

PP1V0_S0SW

6 8 18 110

Place near U0500 on bottom side

1

2

C11L1

1UF

20% 4V CERM-X6S 0201

1

C11L2

1UF

20% 4V

2

CERM-X6S 0201

CPU VCCPLL and VCCST Decoupling

PP1V0_S3

8 110

1

C11M1

1UF

20% 4V

2

CERM-X6S 0201

PP1V0_S3

6 8 110

1

C11M2

1UF

20% 4V

2

CERM-X6S 0201

B

A

Place near U0500 on bottom side

NOSTUFF

1

C11J0

47UF

20%

6.3V

2

POLY-TANT 0805

NOSTUFF

1

C11J1

47UF

20%

6.3V

2

POLY-TANT 0805

CPU VCCSA Decoupling

1

C11K9

220UF

20% 2V

23

ELEC SM-COMBO

NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)

8 7 5 4 2 1

Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_

2x 220uF, 1x 22uF on board edge, everything else on back side

Apple Implementation:

BOM_COST_GROUP=CPU & CHIPSET

36

Place near U0500 on bottom side

SYNC_MASTER=X363_SEAN SYNC_DATE=02/01/2016

PAGE TITLE

CPU Decoupling 2 [11]

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 11 OF 145 11 OF 121

A

D

48

IN

OUT

NOSTUFF

R1204

0

5%

1/20W

MF

0201

345678

2 1

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 4 OF 12

SYSTEM POWER MANAGEMENT

SMC_PCH_SUSACK_L

115 46 18 12

114 73 46

1

115 70

2

114 35 20

115 73 46 18

IN

OUT

IN

PM_SYSRST_L PM_PCH_SYS_PWROK PM_PCH_PWROK

PLT_RST_L PM_RSMRST_L SMC_PCH_SUSWARN_L

48 12

IN

PM_PWRBTN_L SSD_SR_EN_L

12

AL15

AJ11

AG23

AF12

AJ16

AM10 AK9

AL12

GPP_A15/SUSACK*

AJ4

SYS_RESET*

AK3

SYS_PWROK PCH_PWROK

GPP_B13/PLTRST* RSMRST*

GPP_A13/SUSWARN*

/SUSPWRDNACK

GPD3/PWRBTN* GPD1/ACPRESENT

(IPU)

DRAM_RESET*

(OD)

(IPD-DeepSx)

GPP_A14/SUS_STAT*/ESPI_RESET*

(IPU-RSMRST#)

DSW_PWROK

WAKE*

GPP_A8/CLKRUN*

GPD8/SUSCLK

GPD10/SLP_S5*

GPD5/SLP_S4* GPD4/SLP_S3*

GPD6/SLP_A*

AM11 AF8 AG12 AK14 AM15 AH12 AG10 AK10

AG11

NC_PCH_DRAM_RESET_L PM_DSW_PWRGD PCIE_WAKE_L LPC_CLKRUN_L LPC_PWRDWN_L PM_CLK32K_SUSCLK_R PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L NC_PCH_SLP_A_L

20

IN

BI

OUT

20

46

47

PP3V3_S0

12 13 15 110

46

IN

BT_LOW_PWR_L

19 12

46 12

73 46 20 12

73 70 46 43 20 12

1

R1205

100K

5% 1/20W MF 201

2

114 101 89 76 73 70 46 27 20 12

35 12

R1213

10K

1 2

5% MF 2011/20W

D

C

PP3V0_G3H

1

R1201

1M

5% 1/20W MF 201

2

R1202

20K

5%

1/20W

MF

201

C1202

1UF

10% 10V X5R

402-1

103 46 29 12

70 46 20 12

16 17 109

1

2

1

R1203

20K

5% 1/20W MF 201

2

PCH_SRTCRST_L PCH_INTRUDER_L

RTC_RESET_L

12

IN

OUT

59 12

20

IN

20

OUT

PCH_INTRUDER_L PCH_SRTCRST_L RTC_RESET_L

PM_BATLOW_L PM_SLP_S0_L NC_PCH_SLP_WLAN_L

111

NC_PCH_PME_L

20

AUD_PWR_EN

SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2

(IPU)

AM12 AM22

AH10 AG16 AG18

AL8

AM8

AJ10

AJ8

AH8

GPD0/BATLOW* GPP_B12/SLP_S0* GPD9/SLP_WLAN* GPP_A11/PME* GPP_A12/BMBUSY*/ISH_GP6

/SX_EXIT_HOLDOFF*

RTCX1 RTCX2

INTRUDER*

RTC

SRTCRST* RTCRST*

ESPI/LPC

SLP_SUS*

SLP_LAN*

GPD2/LAN_WAKE*

GPD11/LANPHYPC

GPP_B2/VRALERT*

GPP_A0/RCIN*/ESPI_ALERT1*

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME*/ESPI_CS0*

GPP_A6/SERIRQ/ESPI_CS1*

GPP_A7/PIRQA*/ESPI_ALERT0*

GPD7/RSVD

OMIT_TABLE

1

2

1

C1203

1UF

10% 10V

2

X5R 402-1

113 35

OUT OUT

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

J5

CLKOUT_PCIE_N0

J6

CLKOUT_PCIE_P0

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 2 OF 12

XTAL24_IN

XTAL24_OUT

AH13 AK11 AL9 AJ13 AH20

AM13 AK12 AK13 AG20 AM14 AL14 AH14 AJ18

AL11

B4 B3

PM_SLP_SUS_L NC_PCH_SLP_LAN_L SMC_WAKE_SCI_L NC_PCH_LANPHYPC BT_LOW_PWR_L

PCH_RCIN_L_PU LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L

R1440 R1441 R1442 R1443 R1444

LPC_SERIRQ SMC_RUNTIME_SCI_L

NC_PCH_GPD7

SYSCLK_CLK24M_PCH NC_PCH_CLK24M_XTALOUT

OUT

20

IN

20

OUT

33 33 33

BI

IN

20

73 70 12

46 12

35 12

12

1 2 1 2 1 2 1 2 1 2

46 12

IN

OUT

1/20W 201MF5% 1/20W 2015% MF 1/20W 2015% 1/20W5% MF33201 1/20W MF332015%

20

MF

PLACE_NEAR=U1100.AL14:1.25mm

113 20

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

BI BI BI

BI

OUT

PP3V3_S4

110

SSD_SR_EN_L

12

89 46

115 46 18 12

PM_SYSRST_L

R1211

PP3V3_SUS

14 16 17 110

R1247

100K

3.0K

1 2

2015% 1/20W MF

1 2

2011/20W MF5%

C

PP3V3_SUS

15 16 17 110

PP3V3_S5

16 17 110

B

111

27

101

113 87

111

OUT OUT

NC_CLKOUT_PCIE_1_N NC_CLKOUT_PCIE_1_P

NC_CLKOUT_PCIE_2_N NC_CLKOUT_PCIE_2_P

PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P

PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

NC_CLKOUT_PCIE_6_N NC_CLKOUT_PCIE_6_P

EG_PEG_CLK100M_N EG_PEG_CLK100M_P

NC_CLKOUT_PCIE_8_N NC_CLKOUT_PCIE_8_P

NC_CLKOUT_PCIE_9_N NC_CLKOUT_PCIE_9_P

NC_CLKOUT_PCIE_10_N NC_CLKOUT_PCIE_10_P

NC_CLKOUT_PCIE_11_N NC_CLKOUT_PCIE_11_P

F2

CLKOUT_PCIE_N1

F1

CLKOUT_PCIE_P1

K6

CLKOUT_PCIE_N2

K5

CLKOUT_PCIE_P2

F3

CLKOUT_PCIE_N3

F4

CLKOUT_PCIE_P3

G2

CLKOUT_PCIE_N4

G3

CLKOUT_PCIE_P4

E2

CLKOUT_PCIE_N5

E1

CLKOUT_PCIE_P5

K2

CLKOUT_PCIE_N6

K3

CLKOUT_PCIE_P6

L1

CLKOUT_PCIE_N7

L2

CLKOUT_PCIE_P7

M3

CLKOUT_PCIE_N8

M4

CLKOUT_PCIE_P8

M2

CLKOUT_PCIE_N9

M1

CLKOUT_PCIE_P9

R6

CLKOUT_PCIE_N10

R7

CLKOUT_PCIE_P10

T6

CLKOUT_PCIE_N11

T5

CLKOUT_PCIE_P11

CLOCK SIGNALS

GPP_A9/CLKOUT_LPC0

GPP_A10/CLKOUT_LPC1

GPP_A16/CLKOUT_48

CLKOUT_CPUBCLK_N CLKOUT_CPUBCLK_P

CLKOUT_CPUNSSC_N CLKOUT_CPUNSSC_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

XCLK_BIASREF

/ESPI_CLK

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

E4

AJ14

AH15

AL16

L6 L5

J3 J4

H1 H2

J1 J2

PCH_DIFFCLK_BIASREF

PLACE_NEAR=U1100.E4:1.25mm

PLACE_NEAR=U1100.AJ14:1.4mm

LPC_CLK24M_DPMUX_UC_R

CAMERA_PWR_EN

NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP

CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P

CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P

CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P

R1234

2.7K

2 1

1%

1/20W

MF

201

22

20

PP1V0_SUS

R1235

1 2

12

OUT OUT

PCIE_WAKE_L

19 12

SMC_WAKE_SCI_L

46 12

PM_PWRBTN_L

12 48

103 46 29 12

110

LPC_CLK24M_SMCLPC_CLK24M_SMC_R

1/20W MF 2011%

115 113 18

113 6

R1238

R1240

R1239

46

BI

114 101 89 76 73 70 46 27

R1244

R1243

R1242

R1241

73 46 20 12

73 70 46 43 20 12

70 46 20 12

73 70 12

R1246

R1245

PM_BATLOW_L

SMC_RUNTIME_SCI_L

46 12

LPC_CLKRUN_L

46 12

PCH_RCIN_L_PU

12

LPC_SERIRQ

46 12

AUD_PWR_EN

59 12

CAMERA_PWR_EN

12

AP_S0IX_WAKE_L

19 12

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

20 12

PM_SLP_S0_L AP_S0IX_WAKE_SEL

19 12

PM_SLP_SUS_L

PP3V3_S0

R1248 R1209 R1210 R1212

R1207 R1208 R1251

PP3V3_S0

12 13 15 110

R1206 R1214 R1215 R1216

R1230 R1231 R1232 R1233 R1236 R1237

14 20 73 110

100K 100K

1K

10K

100K

10K

100K

10K

100K 100K 100K

100K 100K 100K 100K 100K 100K

1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2

5% MF

1/20W 201 1/20W

5% 201MF

1/20W

5% MF 2011/20W

5% 1/20W MF 201

5% 1/20W MF 201 5% 1/20W MF 5% MF1/20W 201

1/20W

1/20W MF 201

5% 5%

1/20W MF 201

5%

MF 2015%

201MF1/20W5%

MF1/20W5% 201

201

201MF1/20W5% 201MF5% 2011/20W MF5%

201MF1/20W

B

A

111

20

111

OUT OUT

NC_CLKOUT_PCIE_12_N NC_CLKOUT_PCIE_12_P

NC_CLKOUT_PCIE_13_N NC_CLKOUT_PCIE_13_P

NC_CLKOUT_PCIE_14_N NC_CLKOUT_PCIE_14_P

NC_CLKOUT_PCIE_15_N NC_CLKOUT_PCIE_15_P

N3

CLKOUT_PCIE_N12

N2

CLKOUT_PCIE_P12

P5

CLKOUT_PCIE_N13

P6

CLKOUT_PCIE_P13

N5

CLKOUT_PCIE_N14

N6

CLKOUT_PCIE_P14

M6

CLKOUT_PCIE_N15

M7

CLKOUT_PCIE_P15

PCI EXPRESS

CLOCKS & CONTROL

GPP_B5/SRCCLKREQ0* GPP_B6/SRCCLKREQ1* GPP_B7/SRCCLKREQ2* GPP_B8/SRCCLKREQ3* GPP_B9/SRCCLKREQ4*

GPP_B10/SRCCLKREQ5*

GPP_H0/SRCCLKREQ6* GPP_H1/SRCCLKREQ7* GPP_H2/SRCCLKREQ8*

GPP_H3/SRCCLKREQ9* GPP_H4/SRCCLKREQ10* GPP_H5/SRCCLKREQ11* GPP_H6/SRCCLKREQ12* GPP_H7/SRCCLKREQ13* GPP_H8/SRCCLKREQ14* GPP_H9/SRCCLKREQ15*

AL20 AM19 AK20 AL19 AH22 AK22

AM25 AH26 AL25 AF26 AK26 AL26 AJ27 AH27 AM26 AK27

AP_CLKREQ_L_R ENETSD_CLKREQ_L CAMERA_CLKREQ_L TBT_X_CLKREQ_L_R TBT_T_CLKREQ_L_R SSD_CLKREQ_L_R

TBT_W_CLKREQ_L EG_CLKREQ_OUT_L AP_S0IX_WAKE_SEL AP_S0IX_WAKE_L TBT_X_CIO_PWR_EN TBT_T_CIO_PWR_EN TBT_W_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_USB_PWR_EN TBT_W_USB_PWR_EN

111

OUT

47K

201

1 2

47K

201

100K

1 2

201

1 2

201

BOM_COST_GROUP=CPU & CHIPSET

201

IN IN

IN

OUT OUT OUT OUT OUT OUT

20

29

103

20

29

103

20

PAGE TITLE

PCH RTC/HDA/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

12 OF 145

SHEET

12 OF 121

A

47K

1 2

20

BI

20

IN

20

IN

20

BI

19 12

IN

19 12

8 7 5 4 2 1

36

D

PP3V3_S0

12 13 15 110

113 5

OUT OUT

IN IN

DMI_S2N_N<0> DMI_S2N_P<0>

DMI_S2N_N<1> DMI_S2N_P<1>

DMI_S2N_N<2> DMI_S2N_P<2>

DMI_S2N_N<3> DMI_S2N_P<3>

DMI_N2S_N<0> DMI_N2S_P<0>

DMI_N2S_N<1> DMI_N2S_P<1>

DMI_N2S_N<2> DMI_N2S_P<2>

DMI_N2S_N<3> DMI_N2S_P<3>

B19 A19

C20 B20

A21 B21

C22 D22

F20 F19

G19

F21

E21 G22

F22

DMI_TXN0 DMI_TXP0

DMI_TXN1 DMI_TXP1

DMI_TXN2 DMI_TXP2

DMI_TXN3 DMI_TXP3

DMI_RXN0 DMI_RXP0

DMI_RXN1 DMI_RXP1

DMI_RXN2 DMI_RXP2

DMI_RXN3 DMI_RXP3

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 5 OF 12

DMI

CPU/MISC

PROCPWRGD

THERMTRIP*

PECI

GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 GPP_E3/CPU_GP0 GPP_E7/CPU_GP1

GPP_B23/SML1ALERT*/PCHHOT*

CPU_TRST*

PLTRST_PROC*

PRDY*

PREQ*

PCH_TRIGIN

PCH_TRIGOUT

PM_DOWN

PM_SYNC

AC4 AC5 AB5 AH21

AM21 W28 U29 AK23

AF2E20 AC6 AE4 AE6 AD7

AB6 AD5

AE7

345678

PCH_PROCPWRGD PM_THRMTRIP_L_R PCH_PECI

BT_PWRRST_L

BT_TIMESTAMP

XDP_PCH_OBSDATA_A2 XDP_PCH_OBSDATA_B2

NC_PCH_STRP_BSSB_SEL_GPIO

XDP_CPU_TRST_L

CPU_RESET_L

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

CPU_PCH_TRIGGER

PCH_CPU_TRIGGER_R PCH_CPU_TRIGGER

PLACE_NEAR=U1100.AB6:1.27mm 2015% MF

CPU_PCH_PM_DOWN

PM_SYNC_R

PLACE_NEAR=U1100.AE7:1.27mm 1/20W 201

R1308

R1309 R1315

R1314

R1319

0

620

13

OUT OUT OUT OUT

OUT

1 2

1 2 1 2

35 13

18

14

20 13

6

5

IN

1 2

5

IN

5% MF

5% 1/20W

115 18 6

33

5% MF

1/20W

0201

201MF

1/20W5%

201MF

1/20W

2 1

CPU_PWRGD

PM_THRMTRIP_L CPU_PECI

NO STUFF

1

R1331

100K

5% 1/20W MF 201

2

PM_SYNC

OUT

IN

BI

6

48 47 46 6

47 6

D

5

6

C

PP3V3_SUS

R1318 R1341

R1304 R1300 R1303

R1307

R1316

R1301

R1302

R1305

R1306

R1317

1K 1K

47K

1K

150K

100K

47K 47K 47K

47K

100K

1 2 1 2

1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2

OMIT

1/20W 201MF5%

1/20W

5% MF 201

1/20W

5% MF 201

1/20W

5% 1/20W

1/20W

5%

1/20W5% MF 201

1/20W

5% 1/20W 201MF

16 17 110

NC_PCH_STRP_BSSB_SEL_GPIO

SPI_CS0_R_L

TPAD_SPI_CS_L

AUD_SPI_CS_L AUD_SPI_MOSI

MF5% 201

MF 201

MF5% 201

2011/20W MF

TPAD_SPI_MOSI

BT_PWRRST_L

AUD_SPI_CLK AUD_SPI_MISO TPAD_SPI_CLK

MF 2015%

TPAD_SPI_MISO

BT_TIMESTAMP

MF 2011/20W5%

13 20

57 13

43 13

13

35 13

1

R1326

OMIT_TABLE

U1100

SKL-PCH-SFF

150K

5% 1/20W MF 201

2

H65946

FCBGA

A25

NC

114 43 13

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

AF24

AH11

AA6 AA7

AL4 AL5 B11

B25 C11 C19

C2

D19

D2 H5 H6

W5

Y5 Y6

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

SYM 1 OF 12

RSVD & TP PINS

AUDIO

GPP_D5/I2S0_SFRM

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

DISPA_BCLK

GPP_D6/I2S0_TXD

GPP_D7/I2S0_RXD

GPP_D8/I2S0_SCLK

HDA_BCLK

HDA_SYNC

HDA_SDI0 HDA_SDI1

HDA_SDO

HDA_RST*

DISPA_SDI

DISPA_SDO

AJ7 AM6 AK5

AK6 AJ6 AM5 AE3

AE1 AD4

AC30 AD31 AE30 AC31 AB32 AB31 AA33 AA32

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

PCH_DISPA_BCLK_R

PCH_DISPA_SDI

PCH_DISPA_SDO_R

BT_I2S_SYNC_R BT_I2S_R2D_R BT_I2S_D2R_R BT_I2S_CLK_R

TP_PCH_DMIC_CLK1

TP_PCH_DMIC_DATA1

TP_PCH_DMIC_CLK0

TP_PCH_DMIC_DATA0

R1327 R1328 R1329 R1330

20

33

1/20WMF 5%201

201 1/20WMF

201 MF 1/20W 5% PLACE_NEAR=U1100.AJ6:1.5mm

1/20W201 5%MF PLACE_NEAR=U1100.AM5:2.27mm 1/20WMF201 PLACE_NEAR=U1100.AE3:1.27mm

MF201 5%

1/20W PLACE_NEAR=U1100.AD4:1.27mm

201

1/20WMF 5%201

201 1/20WMF 5%

MF201 1/20W 5%

5%

5%MF 1/20W

12 12

12 12 12

12

12 12 12 12

R1310

PLACE_NEAR=U1100.AJ7:1.27mm

33

R1311

PLACE_NEAR=U1100.AM6:1.27mm5%

33

R1313

33

R1312

33

R1320

33

R1321

33 33 33 33

HDA_BIT_CLK

HDA_SYNC

HDA_SDIN0

NC_HDA_SDIN1

HDA_SDOUT HDA_RST_L

PCH_DISPA_BCLK

PCH_DISPA_SDO

BT_I2S_SYNC BT_I2S_R2D BT_I2S_D2R BT_I2S_CLK

115

OUT

IN

OUT

58

20

IN

20

35

BI

35

IN

35

BI

C

B

115 18

20

NC_PCH_TP1_AH9

20

NC_PCH_TP1_AG9

20

ITP_PMODE

18

IN

OUT

IN

XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS PCH_JTAGX

57

OUT

57 13

57 18

111

57

OUT

BI

SPI_CLK_R SPI_CS0_R_L NC_SPI_CS1_L NC_SPI_CS2_L SPI_MOSI_R SPI_MISO SPI_IO<2> SPI_IO<3>

(IPD)

(IPU)

(Undriven)

(IPU)

AJ26 AJ24

AK25 AG25 AM23 AH25 AM24

AK24

AH9

TP1

AG9

TP2

AF1

ITP_PMODE

AG6

JTAG_TCK

AF5

JTAG_TDI

AF6

JTAG_TDO

AG5

JTAG_TMS

AF4

JTAGX

SPI0_CLK SPI0_CS0* SPI0_CS1* SPI0_CS2* SPI0_MOSI SPI0_MISO SPI0_IO2 SPI0_IO3

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU) (IPU)

JTAG

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 3 OF 12

GSPIC-LINK

SPI

GPP_B15/GSPI0_CS*

GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS*

GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

AK21 AJ21 AJ20 AK19 AL23 AJ23 AH23 AH24

AUD_SPI_CS_L AUD_SPI_CLK AUD_SPI_MISO AUD_SPI_MOSI TPAD_SPI_CS_L_R TPAD_SPI_CLK_R TPAD_SPI_MISO_R TPAD_SPI_MOSI_R

13

201 201 201 201 MF 5%

1/20W 5%MF MF 5%1/20W MF 1/20W 5%

1/20W

B

33

12 12 12 12

33

0

33

R1322 R1323 R1324 R1325

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

OUT OUT

OUT

43 13

114 43 13

IN

114 43 13

A

CL_CLK

CL_DATA

CL_RST*

AG3 AG2 AH4

8 7 5 4 2 1

NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

115

36

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

PCH DMI/FDI/PM/GFX/PCI

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 13 OF 145 13 OF 121

A

D

345678

2 1

D

C

29

114

IN IN

OUT OUT

IN IN

OUT OUT

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

USB3_TEST_D2R_N USB3_TEST_D2R_P

USB3_TEST_R2D_N USB3_TEST_R2D_P

NC NC

F5

USB3_1_RXN

G5

USB3_1_RXP

D4

USB3_1_TXN

D5

USB3_1_TXP

G6

USB3_2_RXN/SSIC_1_RXN

F6

USB3_2_RXP/SSIC_1_RXP

B6

USB3_2_TXN/SSIC_1_TXN

A6

USB3_2_TXP/SSIC_1_TXP

G7

USB3_3_RXN/SSIC_2_RXN

H7

USB3_3_RXP/SSIC_2_RXP

C6

USB3_3_TXN/SSIC_2_TXN

B7

USB3_3_TXP/SSIC_2_TXP

D7

USB3_4_RXN

E7

USB3_4_RXP

C8

USB3_4_TXN

B8

USB3_4_TXP

F8

USB3_5_RXN

G8

USB3_5_RXP

B9

USB3_5_TXN

A8

USB3_5_TXP

F9

USB3_6_RXN

G9

USB3_6_RXP

C9

USB3_6_TXN

D9

USB3_6_TXP

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 7 OF 12

USB3

USB2

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2N_11 USB2P_11

USB2N_12 USB2P_12

V4 V3

W2 W3

U6 U7

Y1 Y2

U4 T4

AA4 AA3

T1 T2

AA2 AA1

R3 R4

AB3 AB2

R2 R1

AC1 AC2

NC NC

USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P

USB_CAMERA_DFR_N USB_CAMERA_DFR_P

USB_TEST_N USB_TEST_P

USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P

NC_USB2N_6 NC_USB2P_6

USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P

NC_USB2N_8 NC_USB2P_8

NC_USB2N_9 NC_USB2P_9

NC_USB2N_10 NC_USB2P_10

USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P

NC_USB2N_12 NC_USB2P_12

OMIT_TABLE

U1100

G14

NC NC

103

BI

103

BI

114

BI BI

113 38

29

103

29

PCIE_AP_D2R_N

14

PCIE_AP_D2R_P

14

BI BI

NC NC

PCIE5_RXN

F14

PCIE5_RXP

D14

PCIE5_TXN

C14

PCIE5_TXP

E15

PCIE6_RXN

F15

PCIE6_RXP

A15

PCIE6_TXN

B15

PCIE6_TXP

G15

PCIE7_RXN

G16

PCIE7_RXP

C16

PCIE7_TXN

B16

PCIE7_TXP

F18

PCIE8_RXN

E18

PCIE8_RXP

B18

PCIE8_TXN

C18

PCIE8_TXP

F25

PCIE11_RXN

G25

PCIE11_RXP

A24

PCIE11_TXN

B24

PCIE11_TXP

F26

PCIE12_RXN

E26

PCIE12_RXP

C25

PCIE12_TXN

D25

PCIE12_TXP

E10

PCIE1_RXN/USB3_7_RXN

F10

PCIE1_RXP/USB3_7_RXP

SKL-PCH-SFF

H65946

FCBGA

SYM 8 OF 12

PCIE/SATA/USB3

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE13_RXN/SATA0B_RXN

PCIE13_RXP/SATA0B_RXP PCIE13_TXN/SATA0B_TXN

PCIE13_TXP/SATA0B_TXP

PCIE14_RXN/SATA1B_RXN

PCIE14_RXP/SATA1B_RXP PCIE14_TXN/SATA1B_TXN

PCIE14_TXP/SATA1B_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

F23 E23

B22 A22

E24 F24

B23 C23

D27 D28

B26 C26

E28 F27

A27 B27

H27 G27

A28 B28

G28 F29

B29 C29

G29 G30

NC NC

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

14 113

D

C

B

PP3V3_SUS

12 16 17 110

USB2N_13 USB2P_13

USB2N_14 USB2P_14

GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2* GPP_E12/USB2_OC3*

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_ID

USB2_VBUSSENSE

P1 P2

AD2 AD1

W30 U31 U33 V31

P30 N29 P31 L29

V1

USB2_COMP

W6 U2

NC_USB2N_13 NC_USB2P_13

NC_USB2N_14 NC_USB2P_14

XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3

NC_PCH_GPP_F15 NC_PCH_GPP_F16 NC_PCH_GPP_F17 NC_PCH_GPP_F18

USB2_ID USB2_VBUSSENSE

14 29

14 103

111

IN

111

IN

111

IN

111

IN

PLACE_NEAR=U1100.V1:10.0mm

1

R1410

1K

5% 1/20W MF 201

2

1

R1411

1K

5% 1/20W MF 201

2

1

R1470

113

1% 1/20W MF 201

2

18

113 35

14

OUT OUT OUT OUT OUT

OUT OUT

PCIE_AP_R2D_C_N

XDP_PCH_OBSFN_C0 XDP_PCH_OBSDATA_A0 XDP_PCH_OBSDATA_A1

XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1 XDP_PCH_OBSDATA_D2 XDP_PCH_OBSDATA_D3 XDP_PCH_OBSFN_C1

NC NC

B12

PCIE1_TXN/USB3_7_TXN

A12

PCIE1_TXP/USB3_7_TXP

E11

PCIE2_RXN/USB3_8_RXN

F11

PCIE2_RXP/USB3_8_RXP

D12

PCIE2_TXN/USB3_8_TXN

C12

PCIE2_TXP/USB3_8_TXP

G12

PCIE3_RXN/USB3_9_RXN

F12

PCIE3_RXP/USB3_9_RXP

B13

PCIE3_TXN/USB3_9_TXN

C13

PCIE3_TXP/USB3_9_TXP

E13

PCIE4_RXN/USB3_10_RXN

F13

PCIE4_RXP/USB3_10_RXP

B14

PCIE4_TXN/USB3_10_TXN

A14

PCIE4_TXP/USB3_10_TXP

W31

GPP_E0/SATAXPCIE0/SATAGP0

Y30

GPP_E1/SATAXPCIE1/SATAGP1

W29

GPP_E2/SATAXPCIE2/SATAGP2

U30

GPP_F0/SATAXPCIE3/SATAGP3

T32

GPP_F1/SATAXPCIE4/SATAGP4

T30

GPP_F2/SATAXPCIE5/SATAGP5

T28

GPP_F3/SATAXPCIE6/SATAGP6

R32

GPP_F4/SATAXPCIE7/SATAGP7

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

PCIE19_RXN/SATA6_RXN PCIE19_RXP/SATA6_RXP

PCIE19_TXN/SATA6_TXN

PCIE19_TXP/SATA6_TXP

PCIE20_RXN/SATA7_RXN PCIE20_RXP/SATA7_RXP

PCIE20_TXN/SATA7_TXN

PCIE20_TXP/SATA7_TXP

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_F5/DEVSLP3 GPP_F6/DEVSLP4 GPP_F7/DEVSLP5 GPP_F8/DEVSLP6 GPP_F9/DEVSLP7

B30 C30

H29 H28

C31 B31

J29 J28

D32 C32

K28 K29

E31 E32

V32 V33 W33

T33 P27 P29 R29 N28

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>PCIE_AP_R2D_C_P

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_PCH_OBSDATA_B1

TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L SSD_RESET_L NC_HDD_PWR_EN SSD_PWR_EN

14

OUT OUT

OUT OUT OUT OUT OUT

14

14 113

18

20

OUT OUT

113 87

87

113 77

77

113 77

77

113 77

77

B

115 114 87 20

115 114 87 14

A

13

OUT

R1462 R1460

R1461 R1420 R1421

XDP_PCH_OBSFN_C0

14

XDP_PCH_OBSDATA_A0

14

XDP_PCH_OBSDATA_A1

14

XDP_PCH_OBSDATA_B1

14

XDP_PCH_OBSDATA_B2 XDP_PCH_OBSDATA_B3

14

XDP_PCH_OBSDATA_C0

14 29

XDP_PCH_OBSDATA_C1

14 29

XDP_PCH_OBSDATA_C2

14 103

XDP_PCH_OBSDATA_C3

14 103

PP3V3_S0

100K

10K 10K 10K 10K

1 2

1 2 1 2 1 2 1 2

12 20 73 110

1/20W

5% 201MF

1/20W5% 1/20W 201MF5%

5% 1/20W

1/20W MF 2015%

1

TP

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

TP1882

TP

TP1883

TP

TP1884

TP

TP1885

TP

TP1886

TP

TP1887

MF 201

XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3

U27

PAGE TITLE

XDP_PCH_OBSDATA_B3

14

A

SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC

SSD_PWR_EN

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3

14 29

14 103

TBT_POC_RESET NC_PCH_CAM_RESET NC_PCH_CAM_EXT_BOOT_L NC_WOL_EN

PCH_PCIE_RCOMPP

1

R1400

100

1% 1/20W MF 201

2

103 29 15

20

OUT OUT OUT OUT

PCH_PCIE_RCOMPN

115 114 87 14

14 113

14

14 113

14

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

T29

GPP_F10/SCLOCK

R31

GPP_F11/SLOAD

M29

GPP_F12/SDATAOUT1

P33

GPP_F13/SDATAOUT0

A10

PCIE_RCOMPP

B10

PCIE_RCOMPN

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

GPP_E8/SATALED*

IN IN

113 87

113 77

113 35

PCH PCI-E/USB

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

BI BI BI BI

18

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

18

BOM_COST_GROUP=CPU & CHIPSET

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

14 OF 145

SHEET

14 OF 121

D

8 7 5 4 2 1

36

345678

2 1

D

C

RAMCFG0:L

R1530

1K

5%

1/20W

MF

201

1

2

RAMCFG1:L

1

R1531

1K

5% 1/20W MF 201

2

RAMCFG2:L

R1532

1K

5%

1/20W

MF

201

RAMCFG3:L

1

2

R1533

1K

5% 1/20W MF 201

2

RAM Configuration Straps

BOM GROUP BOM OPTIONS

RAMCFG_SLOT

PART# DESCRIPTIONQTY

117S0006 0 RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD1117S0006 R1540

RES,MF,1/20W,1KOHM,5%,0201,SMD1 R1541117S0006 BOARD_ID:1D

2117S0006 R1541,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD R1542 BOARD_ID:1B1117S0006

117S0006 3 RES,MF,1/20W,1KOHM,5%,0201,SMD

117S0006 R15431 RES,MF,1/20W,1KOHM,5%,0201,SMD

RES,MF,1/20W,1KOHM,5%,0201,SMD2117S0006 R1543,R1540

RES,MF,1/20W,1KOHM,5%,0201,SMD

MLB_RAMCFG0 MLB_RAMCFG1 MLB_RAMCFG2

MLB_RAMCFG3

RAMCFG4:L

1

R1534

1K

5% 1/20W MF 201

2

MLB_RAMCFG4

RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

BOM OPTIONREFERENCE DESIGNATOR(S)

BOARD_ID:1F

BOARD_ID:1E

BOARD_ID:1C

R1542,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD117S0006 2

R1542,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD

R1542,R1541,R1540

R1543,R1541,R15403117S0006 BOARD_ID:14

BOARD_ID:1A

BOARD_ID:19

BOARD_ID:18

BOARD_ID:17

BOARD_ID:16

BOARD_ID:15R1543,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD

MLB_BOARD_ID4

MLB_BOARD_ID3 MLB_BOARD_ID2 MLB_BOARD_ID1 MLB_BOARD_ID0

15

R1558 R1559

TABLE_5_HEAD

TABLE_5_ITEM

100K 100K

PROTO 0 = 0x1F = 1 1 1 1 1 (-01 PCB)

TABLE_5_ITEM

PROTO 0B = 0x1E = 1 1 1 1 0 (-02 PCB)

TABLE_5_ITEM

PROTO 1 = 0x1D = 1 1 1 0 1 (-03 PCB)

TABLE_5_ITEM

PROTO 2 = 0x1C = 1 1 1 0 0 (-04 & -05 PCB)

TABLE_5_ITEM

EVT1 = 0x1B = 1 1 0 1 1 (-06 PCB)

TABLE_5_ITEM

EVT2 = 0x1A = 1 1 0 1 0 (-07 PCB)

TABLE_5_ITEM

DVT = 0x19 = 1 1 0 0 1 (-08 PCB)

TABLE_5_ITEM

DVT1-1 = 0x18 = 1 1 0 0 0 (-09 PCB)

PVT = 0x17 = 1 0 1 1 1 (-10 PCB)

0x16 = 1 0 1 1 0

0x15 = 1 0 1 0 1

0x14 = 1 0 1 0 0

1 2

EDP_IG_PANEL_PWR_EN

1/20W 201MF5%

EDP_IG_BKLT_EN

MF 2011/20W5%

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

114 57 15

103 29 15

103

101 29

29

103 15

20

89 15

111

20

89

20

29 15

27 15

15

20

29

15

20

89 15

OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

IN IN

IN IN IN

NC_ENET_LOW_PWR EDP_IG_PANEL_PWR_EN EDP_IG_BKLT_EN NC_EDP_IG_BKLT_PWM NC_TCON_RESET_L SPIROM_USE_MLB

DP_X_SNK0_HPD_IG DP_X_SNK1_HPD_IG DP_T_SNK0_HPD_IG DP_T_SNK1_HPD_IG

DP_INT_IG_HPD NC_PCH_DDPB_CTRLCLK

PCH_DDPB_CTRLDATA NC_PCH_DDPC_CTRLCLK

PCH_DDPC_CTRLDATA NC_PCH_DDPD_CTRLCLK

PCH_DDPD_CTRLDATA

JTAG_ISP_TDO JTAG_ISP_TDI JTAG_ISP_TCK

JTAG_TBT_X_TMS JTAG_TBT_T_TMS JTAG_TBT_W_TMS

15

DPMUX_UC_IRQ NC_ENET_MEDIA_SENSE NC_BKLT_FAULT_INT_L

NC_SDCONN_STATE_CHANGE NC_SDCONN_OC_L

TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L NC_TBT_W_PLUG_EVENT_L

R28

M28

P32 N31 N30

L27

AH3

AJ5

AG7 AH7

AH2 AH1

AG1

AJ2 AK2

AL3

AH5

AM27

AK28

AJ29

AG27

AH28

AG28 AM28

AL28

AK29

AM29

AL29

AH29

AL30 AL31

GPP_F14 GPP_F19/EDP_VDDEN GPP_F20/EDP_BKLTEN GPP_F21/EDP_BKLTCTL GPP_F22 GPP_F23

GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_H10/SML2CLK GPP_H11/SML2DATA GPP_H12/SML2ALERT*

GPP_H13/SML3CLK GPP_H14/SML3DATA GPP_H15/SML3ALERT*

GPP_H16/SML4CLK GPP_H17/SML4DATA GPP_H18/SML4ALERT*

GPP_H19/ISH_I2C0_SDA GPP_H20/ISH_I2C0_SCL

GPP_H21/ISH_I2C1_SDA GPP_H22/ISH_I2C1_SCL GPP_H23

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 9 OF 12

GPPF/

GPPH/I2C/INTEGRATED SENSOR

BACKLIGHT

GPPG

GPPI/DISPLAY

/SMLINK

GPP_G0/FAN_TACH_0 GPP_G1/FAN_TACH_1 GPP_G2/FAN_TACH_2 GPP_G3/FAN_TACH_3 GPP_G4/FAN_TACH_4 GPP_G5/FAN_TACH_5 GPP_G6/FAN_TACH_6 GPP_G7/FAN_TACH_7

GPP_G8/FAN_PWM_0

GPP_G9/FAN_PWM_1 GPP_G10/FAN_PWM_2 GPP_G11/FAN_PWM_3

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET*

GPP_G16/GSXCLK

GPP_G17/ADR_COMPLETE

GPP_G18/NMI*

GPP_G19/SMI*

GPP_G20 GPP_G21 GPP_G22 GPP_G23

N33 M33 M32 M31 L30 L33 L32 L31

J32 J33 K30 K33

H32 H31 K31 J31 F31

G31

G33 H33

E33 E30 F32 F33

SSD_BOOT_L NC_TP_PCH_GPP_G1 NC_TP_PCH_GPP_G2 NC_TP_PCH_GPP_G3 NC_TP_PCH_GPP_G4 NC_TP_PCH_GPP_G5 NC_TP_PCH_GPP_G6 NC_TP_PCH_GPP_G7

NC_TP_PCH_GPP_G8 PCH_BT_ROM_BOOT SOC_S2R_ACK_L SOC_PCH_DBELL_L

SOC_SWD_CLK PCH_SWD_IO PCH_SWD_MUX_SEL PCH_SOC_DBELL_L PCH_SOC_FORCE_DFU

PCH_SOC_WDOG

PCH_SOC_DFU_STATUS SOC_PANIC_L

DEBUGUART_SEL_SOC

NC_AUD_IPHS_SWITCH_EN NC_AUD_IP_PERIPHERAL_DET NC_AUD_I2C_INT_L

38 15

42 15

38 15

SOC_S2R_ACK_L

SOC_SWD_CLK

15 20 42

PCH_SWD_IO PCH_SOC_DBELL_L

15 20 37

DEBUGUART_SEL_SOC

15

SOC_PANIC_L

SOC_PCH_DBELL_L

15 20 38

NO STUFF

OUT

111

35 15

38 15

15 20 38

15 20 42

42 15

15 20 37

38

37

IN

15

BI BI BI

16 17 109

114 87 15

115

38 15

20

PP1V8_SUS

R1561 R1537 R1538 R1539 R1546 R1557 R1562

100K 100K 100K 100K 100K 100K 100K

1 2 1 2 1 2 1 1 2 1 2 1 2

1

R1556

100K

5% 1/20W MF 201

2

1/20W 201MF5%

5%

2

1/20W MF

5% MF

1/20W 1/20W5% 1/20W5% MF

D

37

IN

MF 2011/20W5%

201

MF 2011/20W5%

201 201MF 201

C

B

A

MLB_ID4:L

1

R1544

1K

5% 1/20W MF 201

2

MLB_ID3:L

1

R1543

1K

5% 1/20W MF 201

2

MLB_ID2:L

1

R1542

1K

5% 1/20W MF 201

2

MLB_ID1:L

1

R1541

1K

5% 1/20W MF 201

2

MLB_ID0:L

1

R1540

1K

5% 1/20W MF 201

2

MLB_DEV_L

1

R1545

1K

5% 1/20W MF 201

2

NOSTUFF

15

MLB BOARD ID Configuration Straps

PP3V3_SUS PP3V3_SUS

PP3V3_S0

R1553 R1554 R1555 R1529 R1535 R1502 R1503 R1504 R1505 R1506 R1507 R1508 R1509 R1512 R1520 R1521 R1522 R1525 R1515

R1526 R1599

R1524 R1523

R1513 R1511

R1527 R1528 R1536 R1548 R1549 R1551 R1552

10K 10K

10K 100K 100K

47K

1K

1K 10K 47K 47K 47K

100K 100K

100K

47K

100K 100K

1K

100K 100K 100K

47K

100K

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

12 13 110

5% 1/20W 201MF

5% 1/20W MF

5% MF1/20W 201

5% MF

5% MF 201

BOMOPTION=OMIT

5%

5% 1/20W MF 201

12 16 17 110

16 17 110

201MF1/20W5%

1/20W 201MF5%

1/20W5% MF 201

201

MF1/20W5%

201

MF5% 1/20W 201

1/20W5%

1/20W 201

1/20W

1/20W MF 2015%

5%

1/20W 201MF

5% 1/20W MF 201

1/20W MF 2015%

1/20W5% 201

1/20W MF 201

1/20W MF 2015%

201MF

MF5%

MF

2015% 1/20W

2011/20W

MF5% 1/20W

201

2015% 1/20W

MF

2015% 1/20W MF

MF5% 201

MF 2011/20W5%

201MF5% 1/20W

MF

2015% 1/20W

MF

2011/20W

MF

201MF1/20W5%

NO STUFF

JTAG_TBT_X_TMS JTAG_TBT_T_TMS JTAG_TBT_W_TMS TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L

PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L ALS_SOC_UART_D2R ALS_SOC_UART_R2D I2C_SSD_SDA I2C_SSD_SCL

JTAG_ISP_TDO

SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L TPAD_SPI_INT_L

SPIROM_USE_MLB

TPAD_SPI_IF_EN

LCD_IRQ_L

SOC_UART_CTS_L JTAG_ISP_TDI JTAG_ISP_TCK

SPKR_ID0_NC

NC_SPKR_ID1 TBT_POC_RESET

SSD_DEBUGI2C_SEL_PCH

LCD_PSR_EN

PCH_UART2_CTS_L

AP_DEV_WAKE

15

15 29

15 103

35 15

15 20

86 15

20 15

15

43 15

15

29 15

15

15 20

86 15

15

84 83 81 80 78 77

82 114

OMIT_TABLE

U1100

SKL-PCH-SFF

115 114 15

87

42 15

35 15

SSD_BOOT_L PCH_SWD_MUX_SEL

PCH_BT_ROM_BOOT

H65946

FCBGA

SYM 6 OF 12

20

OUT

114 36 35 20

114 76 15

29 27 15

103 101 29 15

103 29 15

114 57 15

114 76 15

91

43 15

86 15

20

20 15

20

OUT OUT

IN

IN OUT OUT

OUT

IN

OUT

NC_CAMERA_RESET_L AP_RESET_L LCD_IRQ_L TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL TPAD_SPI_IF_EN TPAD_SPI_INT_L

SSD_DEBUGI2C_SEL_PCH AP_DEV_WAKE

15

NC_ISOLATE_CPU_MEM_L PCH_STRP_TOPBLK_SWP_L

47

MLB_RAMCFG0

15

MLB_RAMCFG1

15

MLB_RAMCFG2

15

MLB_RAMCFG3

15

SPKR_ID0_NC

15

NC_SPKR_ID1 NC_PCH_BSSB_CLK NC_PCH_BSSB_DATA

MLB_BOARD_ID0

15

MLB_BOARD_ID1

15

MLB_BOARD_ID2

15

MLB_BOARD_ID3

15

MLB_BOARD_ID4

15

MLB_DEV_L

15

MLB_RAMCFG4

15

TBT_W_PCI_RESET_L

AK16

AM18

AL18 AH16 AH18 AK15

AG15

AG22 AG21

AM20

AL22

AD28 AD29 AC27 AC29

AB28 AB29 AB30

Y31

Y27 AA29 AA28

Y29

Y33 AA31

AC33 AC32

GPP_A17/ISH_GP7 GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_B0 GPP_B1 GPP_B11 GPP_B14/SPKR

GPP_D0/SPI1_CS* GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL GPP_D15/ISH_UART0_RTS* GPP_D16/ISH_UART0_CTS*

GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

GPPA/

INTEGRATED SENSOR

GPPB

GPPC/SMLINK/I2C/UART

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS*/ISH_UART1_RTS* GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPPD/INTEGRATED SENSOR/UART/I2C

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_C8/UART0_RXD

GPP_C9/UART0_TXD GPP_C10/UART0_RTS* GPP_C11/UART0_CTS*

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL

GPP_C20/UART2_RXD

GPP_C21/UART2_TXD GPP_C22/UART2_RTS* GPP_C23/UART2_CTS*

AJ30 AK31 AK32

AJ32 AH31 AH33

AH32 AG32

AG29 AF28 AF30 AF29

AG33 AH30 AG31 AF33

AE33 AF31

AE29 AE27

AD33 AD32 AE32 AE31

SMBUS_PCH_CLK SMBUS_PCH_DATA NC_PCH_STRP_TLSCONF

SML_PCH_0_CLK SML_PCH_0_DATA NC_PCH_STRP_ESPI

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L

SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L SOC_UART_CTS_L

I2C_SSD_SDA I2C_SSD_SCL

NC_I2C_UPC_SDA NC_I2C_UPC_SCL

ALS_SOC_UART_D2R ALS_SOC_UART_R2D LCD_PSR_EN PCH_UART2_CTS_L

SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016

PAGE TITLE

PP1V8_SSD_FMC

R1550

R1547 R1560

R1563

OUT

BI

IN

OUT

BI

IN

OUT

BI

IN OUT OUT

IN

20 15

15

BI

OUT

BI

OUT

15 20

15

100K

100K 100K

100K

49

20

49

20

49

35 15

86 15

20

PROJ-SPECIFIC PULLUP, GPPBCH RAIL

20

1 2

1 2 1 2

1 2

1/20W5% MF 201

1/20W 2015% MF

MF 2015% 1/20W

1/20W MF

2015%

B

A

PCH GPIO/MISC/NCTF

DRAWING NUMBER SIZE

103 29 14

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

15 OF 145

SHEET

15 OF 121

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V0_SUS

17 110

PP3V3_SUS

12 14 17 110

PP1V_S5_PCH_DCPDSW

17

PP1V0_SUS

17 110

PP3V3_S0

17 110

110

17

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK5_F

AA14 AA15 AA16 AA17 AA18 AA19 AB15

N12 N13 P15 P16 P17 P18 P19 P20 R15 R16 R17 R18 R19 R20

T11 U14 U15 U16 U17 U18 U19 V14 V15 V16 V17 V18 V19 Y14 Y15 Y16 Y17 Y18 Y19

AB12 AC14 AD14

AD19

K22

L22

T12

K10

M10 M11

K13

L12

J11 J12

AD13

PRIMARY WELL

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

PRIMARY WELL HVCMOS

VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3

DCPDSW_1P0

PCIE PLL EBB PRIMARY

VCCAPLLEBB_1P0 VCCAPLLEBB_1P0

THERMAL SENSOR PW

VCCATS

VCCCLK1

VCCCLK2 VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5 VCCCLK5

HD AUDIO POWER

VCCHDA

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

SYM 10 OF 12

POWER

AUDIO PLL

MOD PHY PRIMARY

DEEP SX WELL

ANALOG PLL USB3/ PCIE2/SATA2/PCIE3

MIPI PLL

GPPA PRIMARY WELL

GPPB/GPPC/GPPH PRIMARY WELL

GPPD PRIMARY WELL

GPPE/GPPEF PRIMARY WELL

GPPG PRIMARY WELL

RTC WELL SUPPLY

RTC LOGIC PW/VRM

SPI

ANALOG PLL USB2/VRM

CLOCK BUFFERS PRIMARY 1.0 V

VCCHDAPLL_1P0

VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0

VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCMIPIPLL_1P0

VCCPGPPA

VCCPGPPBCH VCCPGPPBCH VCCPGPPBCH

VCCPGPPD VCCPGPPD VCCPGPPD

VCCPGPPEF VCCPGPPEF

VCCPGPPG

DCPRTC

VCCRTC

VCCRTCPRIM_3P3

VCCSPI VCCSPI

VCCUSB2PLL_1P0 VCCUSB2PLL_1P0

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

17

AC11

K19 L14 L15 L16 L17 L18 L19

AC20 AD20 P10 P11

K24 L24

K21

AC19

AA22 AA23 AB23

V22 W22 W23

T23 U23

PP1V0_SUS

PP3V3_S5

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PP1V_SUS_PCH_VCCHDAPLL_F

GPPD 1.8V

P23

AD18

AC17

AD16

AC22 AD22

AB10 AC10

PP1V8_SUS

PPDCPRTC_PCH

PP3V0_G3H

PP3V3_SUS

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

PP1V8_SUS

15 16 17 109

PP1V8_S0

17 109

PP1V8_S0_PCH_VCCHDA_F

L1600

FERR-220-OHM-2A

1 2

0603

C1600

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

17 110

12 17 110

17

12 15 17 110

13 17 110

17 110

15 16 17 110

15 16 17 109

17

12 17 109

17 110

17

L1602

FERR-220-OHM-2A

1 2

0603

VCCHDA:SUS

L1601

FERR-220-OHM-2A

1 2

0603

VCCHDA:S0

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

VOLTAGE=1.8V

C1601

3.0PF

+/-0.1PF

NP0-C0G

1

2

VOLTAGE=1.0V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

25V

0201

1

2

1

2

C1602

0.1UF

10%

6.3V

X5R 0201

1

C1603

0.1UF

10%

6.3V

2

X5R 0201

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

A11

VSS

A13

VSS

A16

VSS

A18

VSS

A20

VSS

A23

VSS

A26

VSS

A29

VSS

A5

VSS

A7

VSS

A9

VSS

AA10 AA11 AA12 AA13 AA20 AA21 AA24 AA27 AA30

AB11 AB13 AB14 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB24 AB27 AB33

AC12 AC13 AC15 AC16 AC18 AC21 AC23 AC24 AC28

AD10 AD11 AD12 AD15 AD17 AD21 AD23 AD24 AD27

AD30

AE28

AF10 AF11 AF13 AF14 AF15 AF16 AF18 AF19 AF20 AF21 AF22 AF23 AF25 AF27

AF32

AG13 AG14 AG19 AG24 AG26 AG30

AH19

AJ12 AJ15 AJ19 AJ22

AA5 AB1

AB4 AB7

AC3 AC7

AD3

AD6 AE2

AE5

AF3

AF7 AF9

AG4 AG8

AH6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Current data from LPT EDS (doc #486708, Rev 1.0).

FCBGA

SYM 11 OF 12

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ25 AJ28 AJ3 AJ31 AJ9 AK18 AK30 AK4 AK7 AK8 AL10 AL13 AL21 AL24 AL27 AL6 AL7 AM16 AM7 AM9 B5 C10 C15 C21 C24 C27 C28 C3 C4 C5 C7 D10 D11 D13 D15 D16 D18 D20 D21 D23 D24 D26 D29 D3 D30 D31 D6 D8 E12 E14 E16 E19 E22 E25 E27 E29 E3 E5 E6 E8 E9 F16 F28 F30 F7 G1 G10 G11 G13 G18 G20 G21 G23 G24 G26 G32 G4 H3 H30 H4 J10 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J27 J30

J7

K1 K11 K12 K14 K15 K16 K17 K18 K20 K23 K27 K32

K4

K7

L10 L11 L13 L20 L21 L23 L28

L3 L4

L7 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M27 M30

M5

N1 N10 N11 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N27 N32

N4

N7 P12 P13 P14 P21 P22 P24 P28

P3

P4

P7 R10 R11 R12 R13 R14 R21 R22 R23 R24 R27 R30 R33

R5

T10 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T24 T27

OMIT_TABLE

U1100

SKL-PCH-SFF

H65946

FCBGA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SYM 12 OF 12

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

BOM_COST_GROUP=CPU & CHIPSET

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

T3 T31 T7 U1 U10 U11 U12 U13 U20 U21 U22 U24 U28 U3 U32 U5 V10 V11 V12 V13 V2 V20 V21 V23 V24 V27 V28 V29 V30 V5 V6 V7 W1 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W24 W27 W32 W4 W7 Y10 Y11 Y12 Y13 Y20 Y21 Y22 Y23 Y24 Y28 Y3 Y32 Y4 Y7

D1 C1 B1 A2 A3 A4 B2 A30 A31 A32 A33 B33 C33 D33 B32 AJ33 AK33 AL33 AM33 AM32 AM31 AM30 AL32 AM4 AM3 AM2 AM1 AL1 AK1 AJ1 AL2

PAGE TITLE

PCH Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/25/2016SYNC_MASTER=X363_SAKKOC

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

16 OF 145

SHEET

16 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

1000PF CAPS ARE INTEL PLACEHOLDERS & ALL PLACENEAR NEED TO BE UPDATED

PLACE_NEAR=U1100.AD19:1MM

16 110

PLACE_NEAR=U1100.N12:1MM

1

C1743

1UF

10%

6.3V

2

CERM 402

C1750

12PF

5%

25V

NP0-C0G

0201

1

2

1

C1730

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1731

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1732

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1733

0.1UF

10%

16V

2

X5R-CERM 0201

PP1V0_SUS

PLACE_NEAR=U1100.U17:1MM

PLACE_NEAR=U1100.V17:1MM

1

C1701

1UF

10%

6.3V

2

CERM 402

C1700

22UF

20%

X5R-CERM-1

6.3V

603

1

2

PP1V_S5_PCH_DCPDSW

16

VOLTAGE=1V

1

C1708

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V8_SUS

15 16 109

PLACE_NEAR=U1100.P23:1MM

20%

6.3V

603

1

2

C1747

22UF

X5R-CERM-1

PLACE_NEAR=U1100.P23:1MM

1

C1714

0.1UF

10%

16V

2

X5R-CERM 0201

D

PP1V0_SUS

16 110

C1751

12PF

5%

25V

NP0-C0G

0201

PLACE_NEAR=U1100.L17:1.4MM

PLACE_NEAR=U1100.L17:2.1MM

1

2

1

C1736

47UF

20%

6.3V

2

POLY-TANT 0805

1

C1737

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1734

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1735

0.1UF

10%

16V

2

X5R-CERM 0201

PP1V0_SUS

16 110

PLACE_NEAR=U1100.K22:1MM

VOLTAGE=3.3V

PPDCPRTC_PCH

16

1

C1738

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1739

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.K22:1MM

PLACE_NEAR=U1100.AD18:1MM

PLACE_NEAR=U1100.L17:1MM

1

C1702

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1703

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1709

0.1UF

10%

16V

2

X5R-CERM 0201

PP3V3_SUS

13 16 110

PP3V3_SUS

15 16 110

12 15 16 110

PP3V3_SUS

PLACE_NEAR=U1100.AA23:1MM

1

C1710

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.U23:1MM

1

C1713

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.AC19:1MM

1

C1746

0.1UF

10%

16V

2

X5R-CERM 0201

PP3V3_SUS

16 110

PP3V3_S0

16 110

PP3V0_G3H

12 16 109

PLACE_NEAR=U1100.AC17:1MM

PLACE_NEAR=U1100.W22:1MM

1

C1716

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.T12:1MM

1

C1718

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.AC17:1MM

1

C1721

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1722

0.1UF

10%

16V

2

X5R-CERM 0201

D

C

B

PP3V3_SUS

12 14 16 110

PP3V3_S5

12 16 110

PP3V3_SUS

16 110

16 109

PLACE_NEAR=U1100.AD13:1.2MM

1

C1749

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1744

47UF

20%

6.3V

2

POLY-TANT 0805

PLACE_NEAR=U1100.AD16:1MM

1

C1745

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V8_S0

1

C1748

22UF

20%

6.3V

2

X5R-CERM-1 603

1

C1752

12PF

5%

25V

2

NP0-C0G 0201

PLACE_NEAR=U1100.AD14:1MM

1

C1719

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.AD16:1MM

1

C1715

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.AD13:1MM

1

C1717

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.AB12:1MM

1

C1720

0.1UF

10%

16V

2

X5R-CERM 0201

PLACE_NEAR=U1100.P10:1MM

PP1V0_SUS

110

C1754

NP0-C0G

PP1V0_SUS

C1755

NP0-C0G

12PF

5%

25V

0201

12PF

5%

25V

0201

RAIL SIDE

PCH SIDE

C

OMIT_TABLE

L1700

2.2UH-240MA-0.221OHM

1 2

0603

1

PLACE_NEAR=U1100.K24:3MM

2

1

C1704

47UF

20%

6.3V

2

POLY-TANT 0805

PLACE_NEAR=U1100.K24:1MM

MAKE_BASE=TRUE

OMIT_TABLE

VOLTAGE=1V

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

PLACE_NEAR=U1100.L24:1MM

1

C1740

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1705

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.K21:1MM

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

16

L1701

2.2UH-240MA-0.221OHM

1 2

0603

1

2

PLACE_NEAR=U1100.J12:3MM

1

C1706

47UF

20%

6.3V

2

POLY-TANT 0805

PLACE_NEAR=U1100.J12:1MM

PP1V_SUS_PCH_VCCCLK5_F

MAKE_BASE=TRUE

VOLTAGE=1V

PLACE_NEAR=U1100.J11:1MM

1

C1741

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1707

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.J11:1MM

PP1V_SUS_PCH_VCCCLK5_F

16

B

C1753

12PF

5%

25V

NP0-C0G

0201

16 110

1

C1723

0.1UF

2

PLACE_NEAR=U1100.AC20:1MM

20%

10V

CERM

402

1

2

PP3V3_SUS

1

C1724

0.1UF

20%

10V

2

CERM 402

PLACE_NEAR=U1100.AC22:1MM

1

C1757

0.1UF

10%

16V

2

X5R-CERM 0201

PP1V0_SUS

110

C1756

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

OMIT_TABLE

L1702

2.2UH-240MA-0.221OHM

1 2

1

PLACE_NEAR=U1100.AC10:3.6MM

2

0603

1

C1711

47UF

20%

6.3V

2

POLY-TANT 0805

PLACE_NEAR=U1100.AC10:2.1MM

MAKE_BASE=TRUE

VOLTAGE=1V

PP1V_SUS_PCH_VCCUSB2HDAPLL_F

PLACE_NEAR=U1100.AB10:1MM

1

C1742

0.1UF

10%

16V

2

X5R-CERM 0201

1

C1712

1UF

20%

6.3V

2

X6S-CERM 0201

PLACE_NEAR=U1100.AC11:1MM

PP1V_SUS_PCH_VCCUSB2HDAPLL_F PP1V_SUS_PCH_VCCUSB2HDAPLL_F

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

16

A

Current data from LPT EDS (doc #486708, Rev 1.0).

8 7 5 4 2 1

113S0022 3

BOM_COST_GROUP=CPU & CHIPSET

36

L1700,L1701,L1702RES,MF,1A MAX,0OHM,5%,0603

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

17 OF 145

SHEET

17 OF 121

A

D

C

6

IN

6

IN

6

IN

6

IN

115 73 46 12

48 46

57 13

115 18 6

20

Extra BPM Testpoints

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>

IN

OUT

PM_RSMRST_L

PM_PWRBTN_L

IN

SPI_MOSI_R

XDP_CPU_TCK

PCH_JTAGX

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1800 TP1801 TP1802 TP1803

PP3V3_SUS

18 73 110

PLACE_NEAR=J1800.48:2.54MM

XDP:YES

PLACE_NEAR=U1100.AF12:3.8MM

R1800

1K

R1802

PLACE_NEAR=U1100.AM10:3MM

R1803

PLACE_NEAR=U1100.AM23:2.54MM

R1835

1K

0

1 2

XDP:YES

1 2

XDP:YES

1 2

XDP:YES

1K

5%

1/20W

MF

201

1

2

201

MF5%101/20W 201

MF 201

R1804

5%

1/20W MF

5% 1/20W

5% MF1/20W 0201

PLACE_NEAR=J1800.58:28MM

115 13 6

115 6

115 18 13

345678

2 1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V0_SUS

110

NOTE: This is not the standard XDP pinout.

XDP_CONN

XDP:YES

1K

5%

1/20W

MF

201

1

NO_XNET_CONNECTION

2

XDP_PIN_1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

NC NC

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

VCC_OBS_AB

NC

NC NC

XDP:YES

OBSFN_A0 OBSFN_A1

OBSFN_B0 OBSFN_B1

HOOK0 HOOK1

HOOK2 HOOK3

SDA

SCL TCK1 TCK0

C1800

0.1UF

10%

6.3V

CERM-X5R

0201

PLACE_NEAR=J1800.44:28MM

1

2

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

PLACE_NEAR=U0500.BN28:2.54MM

XDP_PRESENT_CPU XDP_CPU_PREQ_L

BI

IN

6

IN

6

IN

6

IN IN

6

IN

6

IN

6

IN

6

IN

XDP_CPU_PRDY_L

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L

SPI_MOSI_R_CONN

OUT

XDP_PCH_TCK

XDP:YES

10%

6.3V 0201

1

2

C1804

0.1UF

CERM-X5R

PLACE_NEAR=J1800.42:28MM

DF40RC-60DP-0.4V

J1800

M-ST-SM1

62

61

12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960

6364

518S0847

PLACE_NEAR=J1800.43:28MM

Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

TDO TRSTn TDI TMS XDP_PRESENT#

NC_ITPXDP_CLK100MP NC_ITPXDP_CLK100MN

XDP:YES

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=J1800.47:28MM

1

2

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

ITP_PMODE XDP_DBRESET_L

XDP:YES

C1806

0.1UF

10%

6.3V CERM-X5R 0201

115 18 13

IN

0

115 18 13

13

115 18 6

1 2

XDP:YES

1 2

XDP:YES

1 2

XDP:YES

1 2

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

IN IN

115 113 12

1

R1830

1K

5% 1/20W MF 201

2

PLACE_NEAR=U0500.E8:2.54MM

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

XDP_PCH_TDO

PLACE_NEAR=U1100.AF6:28MM

XDP_PCH_TDI

PLACE_NEAR=U1100.AF5:28MM

XDP_PCH_TMS

PLACE_NEAR=U1100.AG5:28MM 1/20W

XDP_CPU_TDO

PLACE_NEAR=U0500.BT28:28MM

XDP_CPU_TCK

PLACE_NEAR=U0500.BR28:28MM

XDP_PCH_TCK

PLACE_NEAR=U1100.AG6:28MM

XDP_PCH_TRST_L

18

PROPER WAY TO TERMINATE?

XDP_CPU_TDO

MF5% 1/20W 0201

XDP_CPU_TRST_L

5% 1/20W

MF 0201

XDP_CPU_TDI

1/20W

MF 02015%

XDP_CPU_TMS

MF 02015% 1/20W

XDP:YES

1 2

R1890 R1891 R1892 R1810

R1813 R1897

R1898

R1806

0

5%

1/20W

MF

0201

PM_SYSRST_L

XDP:YES

PP1V0_S0SW

6 8 11 110

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

NOSTUFF

51

2 1

NOSTUFF

51

2 1

IN

OUT

MF 2015% 1/20W

MF5% 1/20W 201

D

MF 2015%

1/20W MF 2015%

MF 2015% 1/20W

1/20W5% 201MF

MF 2015% 1/20W

BI

115 46 12

C

115 18 6

115 13 6

115 6

B

13

14

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PP3V3_SUS

18 73 110

PP3V3_SUS

18 73 110

XDP:YES

6

VCC

1

C1830

0.1UF

10% 10V

2

X5R-CERM 0201

XDP:YES

XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

IN

18

OUT OUT

115 18 13

U1830

PCH/XDP Signals

BI

XDP_PCH_OBSDATA_A2 XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3 XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1 XDP_PCH_OBSDATA_D2 XDP_PCH_OBSDATA_D3 XDP_PCH_OBSFN_C1

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1870 TP1871 TP1872 TP1873 TP1874 TP1875 TP1876 TP1877 TP1878 TP1879 TP1880 TP1881

Non-XDP Signals

XDP:YES

1

R1850

100K

5% 1/20W MF 201

2

74AUP1G07GF

SOT891

2 1

GND

3

(OD)

NCNC

PLACE_NEAR=U1830.4:7.54MM

SPI_IO2_STRAP_L

4

YA

5

NCNC

PLACE_NEAR=U1830.4:2.54MM

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

R1831

1.5K

NO_XNET_CONNECTION

MF

1 2

XDP:YES

R1832

49.9

NO_XNET_CONNECTION

1 2

MF

NOSTUFF

XDP_PRESENT_L

SPI_IO<2>

5% 1/20W

201

(STRAP TO PCH)

1%

1/20W

201

OUT

57 13

B

73

A

DESIGN: X502/MLB LAST CHANGE: Mon Jun 15 22:04:28 2015

SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/25/2016

PAGE TITLE

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

8 7 5 4 2 1

36

CPU/PCH Merged XDP

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 18 OF 145 18 OF 121

A

D

345678

2 1

D

CRITICAL

C1907

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

113

System 32kHz / 12MHz / 24MHz Clock Generator

SYSCLK_CLK24M_X2

R1900

0

1 2

5%

1/20W

MF

0201

20

46

20

PPVIO_32K_B_RC

20

PPVIO_VIOE_A_RC

20

NC_PPVIOE_CAMCLK

IN

NC_PPVIOE_SSDCLK

IN

SMC_CLK12M_EN

IN

SYSCLK_CLK24M_X2_R

113

PPVRTC_U1900_RC

PPVDD_U1900_RC

12

VIO_32K_B

2

VIOE_24M_A

5

VIOE_24M_B

15

VIOE_24M_C

8

OE_12M

19

X2

20

X1

1

VDD

U1900

SLG3AP3444

STQFN

GND

11

VRTC

VOUT

32.768K_A

32.768K_B 24M_A

24M_B 24M_C

12M

PP2V9_SYSCLK

17 10

13 3

6 16

7

SYSCLK_CLK32K_PCH SYSCLK_CLK32K_CAMERA_BT_AP

SYSCLK_CLK24M_PCH NC_SYSCLK_CLK24M_CAMERA NC_SYSCLK_CLK24M_SSD

SYSCLK_CLK12M_SMC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=2.9V

BYPASS=U1900.17:18:5MM

1

C1900

2.2UF

20%

6.3V

2

X5R-CERM 0201

20

46

109

PCH ME Disable Strap

SPI_DESCRIPTOR_OVERRIDE_L

1

G

IN

PP1V8_S0

S

2

Q1930

DMP31D0U

SOT23

D

3

SPI_DESCRIPTOR_OVERRIDE

1

R1930

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

PCH IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. ***** Circuit does not support HDA voltage >3.3V.

46

IN

D

13

OUT

C

2 4

CRITICAL

C1908

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

CRITICAL

Y1900

1 3

2.5X2.0MM-SM

NO STUFF

1

R1901

1M

24MHZ-10PPM-8PF-40OHM

5% 1/20W MF 201

2

SYSCLK_CLK24M_X1

113

NOTE: 30 PPM or better required for SKL PCH

14

4

9

18

C

B

A

PCIe Wake Muxing

PP3V3_S5

110

CRITICAL

10%

6.3V 0201

1

25%

6

5

4 3

U1910

PI5A3157BC6E

SEL

VCC

A

SC70

VER 1

B1

1

2

GND

0

B0

35

1

R1910

C1910

0.1UF

100K

1/20W MF 201

2

CERM-X5R

AP_PCIE_WAKE_L PCIE_WAKE_L

8 7 5 4 2 1

AP_S0IX_WAKE_SEL

SEL OUTPUT

L PCIE_WAKE_L (B0) H AP_S0IX_WAKE_L (B1)

AP_S0IX_WAKE_L

OUT

OUTIN

12

IN

SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016

PAGE TITLE

12

BOM_COST_GROUP=CPU & CHIPSET

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Chipset Support 1

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

36

051-00647

10.0.0 dvt-fab10 19 OF 145 19 OF 121

A

D

345678

2 1

D

C

B

A

Platform Reset Connections

Buffered

35 20 12

114

114 35 20 12

109 20

110

IN

R2080 R2081 R2082 R2083

IN

PP3V3_S0

PLT_RST_L

C2071

0.1UF

X5R-CERM

IN

PLT_RST_L

PP3V3_S0

PP1V8_S4

LDO

1

10% 16V

2

0201

NOSTUFF

12 14 20 73 110

47K

1 2

CRITICAL

5

1

U2071

2

PLACE_NEAR=R2001:5MM

MC74VHC1G08

3

Unbuffered

100K

10K

100K

5% MF

5%

5% 201MF1/20W

C2013

Scrub for Layout Optimization

SC70-HF

4

PLT_RST_L_BUF

1

R2070

100K

5% 1/20W MF 201

2

NOSTUFF

5%

1/20W

MF

0201

1

0

2

R2073

PLACE_NEAR=U2071:5MM

1

R2072

4.99K

1% 1/20W MF 201

2

MAKE_BASE=TRUE

TBT_X_PCI_RESET_L

R2000

12

MF

2015% 1/20W

TBT_X_PCI_RESET_L

MAKE_BASE=TRUE

TBT_T_PCI_RESET_L

R2001

12

R2002

12

R2003

12

R2004

12

1/20W

5% 201MF

R2005

MF1/20W5% 201

2011/20W5% MF

MF1/20W5%

201

201MF1/20W5%

TBT_T_PCI_RESET_L

AP_RESET_L

SSD_RESET_L

SMC_LRESET_L

TBT_W_PCI_RESET_L

PCIE CLKREQS

115 87

SSD_CLKREQ_L

1/20W5% 201

27

1/20W 201

101

1/20W MF 201

35

MF

TBT_X_CLKREQ_L

TBT_T_CLKREQ_L

AP_CLKREQ_L

R2016

3.3

1 2

1/20W

1

1.0UF

20%

6.3V

2

X5R

0201-1

5% MF

201

MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000

VOLTAGE=1.8V

PPVCC_RTC_OSC

1

2

R2084

1/20W

R2085

1/20W 201MF5%

R2086 R2087

1/20W

5% MF 201

C2014

0.1UF

10%

6.3V CERM-X5R 0201

1 2

201MF5%

1 2

2015% MF1/20W

1 2

1

C2015

0.01UF

10% 10V

2

X5R-CERM 0201

1K

J80 & J80G Display Port DDPB, DDPC,DDPD

6

1

PP3V3_S0

DBGLED

R2092

1/20W

DBGLED_S3DBGLED_S4

DBGLED

A

D2092

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

DBGLED_S3_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

5

G S

20K

5% MF

201

1

2

3

D

4

PCH_DDPB_CTRLDATA

15

PCH_DDPC_CTRLDATA

15

PCH_DDPD_CTRLDATA

15

PP3V3_S5

110

DBGLED

R2090

20K

1/20W

201

DBGLED_S5

DBGLED

A

D2090

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

73 46 12

73 70 46 43 12

114 101 89 76 73 70 46 27 12

70 46 12

5% MF

12 14 20 73 110

R2050

201 MF1/20W5%

R2051

201 MF1/20W5%

R2052

201 MF1/20W5%

2.2K

1 2

2.2K

1 2

2.2K

1 2

Power State Debug LEDs

DBGLED

20K

5%

1/20W

MF

201

1

2

D

1

2

DBGLED

A

R2091

D2091

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED_S4_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

2

G S

IN IN IN IN

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

114 35 20 12

12 20

LPC_CLK24M_DPMUX_UC_R

MAKE_BASE=TRUE

14

27 29

14

101

114 36 35 15

115 114 87 14

46

15

SSD_CLKREQ_L_R

12

TBT_X_CLKREQ_L_R

12

TBT_T_CLKREQ_L_R

12

AP_CLKREQ_L_R

12

4

VCC

Y2001

32.768KHZ-25PPM-15PF-5.5V

2.50X2.00-SM-COMBO

1

EN/DIS OUT

GND

2

(For development only)

DBGLED

R2093

1/20W

DBGLED

A

D2093

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED_S0I3_D

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

2

G S

DPMUX Connections

PLT_RST_L

IN

DPMUX_UC_IRQ

15

113 12

20K

IN

19

IN

3

SYSCLK_CLK32K_OSC_Y1901

1

5% MF

201

2

D

NC_PCH_CLK24M_XTALOUT

MAKE_BASE=TRUE

SYSCLK_CLK24M_PCH

MAKE_BASE=TRUE

SSD_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_X_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_T_CLKREQ_L_R

MAKE_BASE=TRUE

AP_CLKREQ_L_R

109 20

IN

DBGLED

R2095

20K

1/20W

201

DBGLED_S0DBGLED_S0I3

DBGLED

A

D2095

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

DBGLED_S0_D

DBGLED

Q2091

6

1

DMN5L06VK-7

PP1V8_S4

LDO

1

5% MF

2

SOT563

VER 3

5

G S

100K

R2007

22

1 2

5%

1/20W

MF

201

3

D

4

R2006

12

1/20W 201MF5%

DPMUX_LRESET_L

LPC_CLK24M_DPMUX_UC

MAKE_BASE=TRUE

DPMUX_UC_IRQ

5%

1/20W

MF

201

1

2

R2089

100K

MAKE_BASE=TRUE

NC_PCH_CLK24M_XTALOUT

SYSCLK_CLK24M_PCH

GreenCLK VIOEs

MAKE_BASE=TRUE

NC_PPVIOE_CAMCLK

MAKE_BASE=TRUE

NC_PPVIOE_SSDCLK

R2017

0

1 2

5%

1/20W

MF

0201

R2018

0

1 2

5%

1/20W

MF

0201

NOSTUFF

SYSCLK_CLK32K_WIFIBT

SYSCLK_CLK32K_OSC_SOC

PLACE_NEAR=U3900.AA22:3mm

C2003

110

IN

1.0UF

6.3V

0201-1

1

20%

2

X5R

PP1V0_SUS

F = 500kHz

109 20

IN

OUT

R2012

3.3

1 2

5%

1/20W

MF

201

C2006

1.0UF

IN

PP3V3_G3H

F = 1.7MHz

109 20

89

OUT

89

12

NC_PPVIOE_CAMCLK

NC_PPVIOE_SSDCLK

OUT

R2026

0

1 2

5%

1/20W

MF

0201

MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000

VOLTAGE=1.8V

PPVIO_32K_B_RC

1

C2002

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.12:18:5MM

R2013

3.3

1 2

5%

1/20W

MF

201

20%

6.3V X5R

0201-1

1

2

RC Filter -3dB @ 240KHz

C2009

1.0UF

0201-1

IN

PP3V3_G3H

F = 1.7MHz

NC_AUD_IPHS_SWITCH_EN

15

NC_AUD_IP_PERIPHERAL_DET

15

NC_AUD_I2C_INT_L

15

NC_ENET_MEDIA_SENSE

15

NC_BKLT_FAULT_INT_L

15

NC_SDCONN_STATE_CHANGE

15

NC_SDCONN_OC_L

15

NC_TBT_W_PLUG_EVENT_L

15

SOC_UART_D2R

15

SOC_UART_R2D

15

35

SOC_CLK_32K

NOSTUFF

19

1

C2001

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIN_NECK_WIDTH=0.1750

MIN_LINE_WIDTH=0.2000

VOLTAGE=1.0V

PPVIO_VIOE_A_RC

1

C2004

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.02:18:5MM

1

2

R2014

3.3

1 2

5%

1/20W

MF

201

20%

6.3V X5R

1

2

R2015

1 2

20% X5R

1

2

C2010

1.0UF

6.3V

0201-1

NC ALIASES 3

MAKE_BASE=TRUE

89

15

13

19

OUT

37

19

13

15

12

20 12

12

SOC_PCH_DBELL_L

15 38

SOC_SWD_CLK

15 42

PCH_SOC_DBELL_L

15 37

C2000

0.1UF

10%

6.3V CERM-X5R 0201

MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000

VOLTAGE=3.3V

PPVDD_U1900_RC

1

2

3.3

5%

1/20W

MF

201

C2011

0.1UF

10%

6.3V CERM-X5R 0201

MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000

VOLTAGE=3.3V

PPVRTC_U1900_RC

1

2

1

C2005

0.1UF

10%

6.3V

2

X5R 0201

C2007

0.1UF

10%

6.3V CERM-X5R 0201

MAKE_BASE=TRUE

NC_AUD_IPHS_SWITCH_EN

MAKE_BASE=TRUE

NC_AUD_IP_PERIPHERAL_DET

MAKE_BASE=TRUE

NC_AUD_I2C_INT_L

MAKE_BASE=TRUE

NC_ENET_MEDIA_SENSE

MAKE_BASE=TRUE

NC_BKLT_FAULT_INT_L

MAKE_BASE=TRUE

NC_SDCONN_STATE_CHANGE

MAKE_BASE=TRUE

NC_SDCONN_OC_L

MAKE_BASE=TRUE

NC_TBT_W_PLUG_EVENT_L

SOC_UART_D2R SOC_UART_R2D

SIGNAL ALIASES

BKLT_PWM_MLB2TCON

ALS_SOC_UART_D2R ALS_SOC_UART_R2D PCH_JTAGX

PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO

NC_PCH_DDPB_CTRLCLK NC_PCH_DDPC_CTRLCLK NC_PCH_DDPD_CTRLCLK

NC_PCH_SLP_A_L NC_PCH_LANPHYPC NC_PCH_GPD7

NC_CLKOUT_PCIE_13_N NC_CLKOUT_PCIE_13_P

NC_PCH_PME_L

19

1

C2008

0.1UF

10%

6.3V

2

X5R 0201

MAKE_BASE=TRUE

NC ALIASES 2

19

INTEL SKL DEBUG

13

GREENCLK CLOCK OUT ALIASES

MAKE_BASE=TRUE

SYSCLK_CLK32K_PCH

42

MAKE_BASE=TRUE

19

MAKE_BASE=TRUE

SYSCLK_CLK32K_CAMERA_BT_AP

IN

BKLT_PWM_MLB2TCON

MAKE_BASE=TRUE

ALS_SOC_UART_D2R

MAKE_BASE=TRUE

ALS_SOC_UART_R2D

MAKE_BASE=TRUE

PCH_JTAGX

PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO

MAKE_BASE=TRUE

NC_PCH_DDPB_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_DDPC_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_DDPD_CTRLCLK

MAKE_BASE=TRUE

NC_PCH_SLP_A_L

MAKE_BASE=TRUE

NC_PCH_LANPHYPC

MAKE_BASE=TRUE

NC_PCH_GPD7

MAKE_BASE=TRUE

NC_CLKOUT_PCIE_13_N

MAKE_BASE=TRUE

NC_CLKOUT_PCIE_13_P

MAKE_BASE=TRUE

NC_PCH_PME_L

MAKE_BASE=TRUE

SOC_PCH_DBELL_L

MAKE_BASE=TRUE

SOC_SWD_CLK

MAKE_BASE=TRUE

PCH_SOC_DBELL_L

UNUSED NETS in J80

ENETSD_CLKREQ_L CAMERA_CLKREQ_L

TBT_W_CLKREQ_L TBT_W_CIO_PWR_EN

TBT_W_USB_PWR_EN

BOM_COST_GROUP=CPU & CHIPSET

115

MAKE_BASE=TRUE

114 76

42

18

5

13

OUT

12

IN

TP_PCH_DMIC_CLK1

TP_PCH_DMIC_DATA1

TP_PCH_DMIC_CLK0

TP_PCH_DMIC_DATA0

NC_PCH_CLK32K_RTCX2

20 12

NC_PCH_DRAM_RESET_L

NC_TCON_RESET_L

15

NC_SPKR_ID1

15

NC_HDD_PWR_EN

14

NC_PCH_TP1_AH9

13

NC_PCH_TP1_AG9

13

NC_PCH_BSSB_CLK

15

NC_PCH_BSSB_DATA

15

NC_PCH_SLP_LAN_L

12

NC_ISOLATE_CPU_MEM_L

15

NC_PCH_CAM_RESET

14

NC_PCH_CAM_EXT_BOOT_L

14

NC_WOL_EN

14

NC_ENET_LOW_PWR

15

NC_I2C_UPC_SDA

15

NC_I2C_UPC_SCL

15

NC_SYSCLK_CLK24M_CAMERA

19

NC_SYSCLK_CLK24M_SSD

19

NC_PCH_STRP_TLSCONF

15

NC_PCH_STRP_ESPI

15

NC_PCH_STRP_BSSB_SEL_GPIO

LPC_CLK24M_DPMUX_UC_R

12 20

NC_CAMERA_RESET_L

15

SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/14/2016

12

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

PP2000 PP2001 PP2002

PP2003

SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2

R2043

0

1 2

5%

1/20W

MF

0201

SOC_PMU_CLK_32K

NC ALIASES

MAKE_BASE=TRUE

NC_PCH_DRAM_RESET_L

MAKE_BASE=TRUE

NC_TCON_RESET_L

MAKE_BASE=TRUE

NC_SPKR_ID1

MAKE_BASE=TRUE

NC_HDD_PWR_EN

MAKE_BASE=TRUE

NC_PCH_TP1_AH9

MAKE_BASE=TRUE

NC_PCH_TP1_AG9

MAKE_BASE=TRUE

NC_PCH_BSSB_CLK

MAKE_BASE=TRUE

NC_PCH_BSSB_DATA

MAKE_BASE=TRUE

NC_PCH_SLP_LAN_L

MAKE_BASE=TRUE

NC_ISOLATE_CPU_MEM_L

MAKE_BASE=TRUE

NC_PCH_CAM_RESET

MAKE_BASE=TRUE

NC_PCH_CAM_EXT_BOOT_L

MAKE_BASE=TRUE

NC_WOL_EN

MAKE_BASE=TRUE

NC_ENET_LOW_PWR

MAKE_BASE=TRUE

NC_I2C_UPC_SDA

MAKE_BASE=TRUE

NC_I2C_UPC_SCL

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_SSD

MAKE_BASE=TRUE

NC_PCH_STRP_TLSCONF

MAKE_BASE=TRUE

NC_PCH_STRP_ESPI

MAKE_BASE=TRUE

NC_PCH_STRP_BSSB_SEL_GPIO

MAKE_BASE=TRUE

LPC_CLK24M_DPMUX_UC_R

MAKE_BASE=TRUE

NC_CAMERA_RESET_L

Chipset Support 2

Apple Inc.

12 19

OUTIN

12

IN

OUT

DRAWING NUMBER SIZE

051-00647

REVISION

41 37

20 12

D

10.0.0

BRANCH

dvt-fab10

PAGE

20 OF 145

SHEET

20 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

7

IN

7

IN

7

IN

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU-Based Margining

PP1V2_S3

VRef Dividers

R2223

10

1 2

1%

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_A_RC

PLACE_NEAR=R2221.2:1mm

R2222

8.2K

1/20W

201

R2220

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2241.2:1mm

R2242

8.2K

1/20W

201

R2240

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2261.2:1mm

R2262

8.2K

1/20W

201

R2260

24.9

1 2

1%

1/20W

MF

201

1

1% MF

2

1

1% MF

2

1

1% MF

2

1

R2221

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1450

1

R2241

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

1

R2261

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1450

D

109

C

109

B

A

PAGE TITLE

LPDDR3 VREF MARGINING

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0 dvt-fab10 22 OF 145 21 OF 121

A

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-16GB

FBGA

113 26 7

26 7

113 26 7

26 23 7

IN IN IN IN IN IN IN IN IN IN

IN IN

IN

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9>

MEM_A_CKE<0> MEM_A_CKE<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0> MEM_A_ZQ<1>

243

1%

1/20W

MF

201

1

10%

6.3V X5R 201

1

2

C2340

0.047UF

109 23

1

C2341

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

22 23 24 25 109 116

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2301

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4 H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

C4

K9 R3

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

1

2

OMIT_TABLE

C2301

0.1UF

10% 16V X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

1

C2302

1.0UF

20% 10V

2

X5R-CERM 0201-1

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

1

C2303

1.0UF

20% 10V

2

X5R-CERM 0201-1

MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<15> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<14> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<3> MEM_A_DQ<1> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<2> MEM_A_DQ<0> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<16> MEM_A_DQ<22> MEM_A_DQ<18> MEM_A_DQ<23> MEM_A_DQ<17> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<21> MEM_A_DQ<24> MEM_A_DQ<26> MEM_A_DQ<31> MEM_A_DQ<25> MEM_A_DQ<28> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<27>

MEM_A_DQS_N<1> MEM_A_DQS_N<0> MEM_A_DQS_N<2> MEM_A_DQS_N<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<0> MEM_A_DQS_P<2> MEM_A_DQS_P<3>

1

C2304

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2305

1.0UF

20% 10V

2

X5R-CERM 0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2306

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2307

10UF

20% 4V

2

X6S-CERM 0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2 H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

K8

K11

L12

N8 N12 R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2300

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2320

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2310

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2330

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2321

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2311

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2331

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2322

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2312

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2332

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2323

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2333

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2324

10UF

20% 4V

2

X6S-CERM 0402-2

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

BOM_COST_GROUP=DRAM

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

23 OF 145

SHEET

22 OF 121

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-16GB

FBGA

113 26 7

26 7

113 26 7

26 22 7

IN IN IN IN IN IN IN IN IN IN

IN IN

IN

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2> MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

10%

6.3V X5R 201

1

2

C2440

0.047UF

109 22

1

C2441

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

22 23 24 25 109 116

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2401

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4 H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

C4

K9 R3

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

1

2

OMIT_TABLE

C2401

0.1UF

10% 16V X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

1

C2402

1.0UF

20% 10V

2

X5R-CERM 0201-1

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

1

C2403

1.0UF

20% 10V

2

X5R-CERM 0201-1

MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<41> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<40> MEM_A_DQ<49> MEM_A_DQ<53> MEM_A_DQ<55> MEM_A_DQ<51> MEM_A_DQ<54> MEM_A_DQ<52> MEM_A_DQ<48> MEM_A_DQ<50> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<62> MEM_A_DQ<59> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<58> MEM_A_DQ<63> MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<4> MEM_A_DQS_N<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<4> MEM_A_DQS_P<7>

1

C2404

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2405

1.0UF

20% 10V

2

X5R-CERM 0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2406

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2407

10UF

20% 4V

2

X6S-CERM 0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6

G5

H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

K8

K11

L12

N8 N12 R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2400

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2420

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2410

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2430

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2421

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2411

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2431

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2422

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2412

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2432

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2423

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2433

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2424

10UF

20% 4V

2

X6S-CERM 0402-2

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM. Distribute evenly.Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

24 OF 145

SHEET

23 OF 121

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-16GB

FBGA

113 26 7

26 7

113 26 7

26 25 7

IN IN IN IN IN IN IN IN IN IN

IN IN

IN

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

243

1%

1/20W

MF

201

1

109 25

1

C2541

0.047UF

10%

6.3V

2

X5R 201

10%

6.3V X5R 201

1

2

C2540

0.047UF

PP0V6_S3_MEM_VREFCA_A

25 109

PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

22 23 24 25 109 116

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2501

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4 H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

C4

K9 R3

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

1

2

OMIT_TABLE

C2501

0.1UF

10% 16V X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

1

C2502

1.0UF

20% 10V

2

X5R-CERM 0201-1

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

1

C2503

1.0UF

20% 10V

2

X5R-CERM 0201-1

MEM_B_DQ<8> MEM_B_DQ<15> MEM_B_DQ<12> MEM_B_DQ<9> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<20> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<16> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<19> MEM_B_DQ<3> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DQ<7> MEM_B_DQ<5> MEM_B_DQ<2> MEM_B_DQ<6> MEM_B_DQ<4> MEM_B_DQ<26> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<31> MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<28> MEM_B_DQ<24>

MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<0> MEM_B_DQS_N<3>

MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<0> MEM_B_DQS_P<3>

1

C2504

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2505

1.0UF

20% 10V

2

X5R-CERM 0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2506

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2507

10UF

20% 4V

2

X6S-CERM 0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6

G5

H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

K8

K11

L12

N8 N12 R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2500

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2520

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2510

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2530

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2521

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2511

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2531

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2522

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2512

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2532

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2523

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2533

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2524

10UF

20% 4V

2

X6S-CERM 0402-2

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM. Distribute evenly.

Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

25 OF 145

SHEET

24 OF 121

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-16GB

FBGA

113 26 7

26 7

113 26 7

26 24 7

IN IN IN IN IN IN IN IN IN IN

IN IN

IN

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2> MEM_B_ZQ<3>

243

1%

1/20W

MF

201

1

C2641

0.047UF

10%

6.3V

2

X5R 201

10%

6.3V X5R 201

1

2

C2640

0.047UF

24 109

109 24

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

22 23 24 25 109 116

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2601

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4 H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

C4

K9 R3

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

1

2

OMIT_TABLE

C2601

0.1UF

10% 16V X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

CRITICAL

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

1

C2602

1.0UF

20% 10V

2

X5R-CERM 0201-1

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

1

C2603

1.0UF

20% 10V

2

X5R-CERM 0201-1

MEM_B_DQ<47> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<44> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<48> MEM_B_DQ<53> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<49> MEM_B_DQ<38> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<35> MEM_B_DQ<62> MEM_B_DQ<59> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<63> MEM_B_DQ<58> MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<4> MEM_B_DQS_N<7>

MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<4> MEM_B_DQS_P<7>

1

C2604

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2605

1.0UF

20% 10V

2

X5R-CERM 0201-1

PP1V8_S3_MEM

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

112

BI

1

C2606

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2607

10UF

20% 4V

2

X6S-CERM 0402-2

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V2_S3

22 23 24 25 109 116

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6

G5

H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

K8

K11

L12

N8 N12 R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2600

LPDDR3-16GB

FBGA

(2 OF 2)

EDFA232A1MA-GD-F

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

22 23 24 25 109 116

PP1V2_S3

22 23 24 25 109

PP1V8_S3_MEM

22 23 24 25 109 116

1

C2620

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2610

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2630

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2621

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2611

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2631

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2622

1.0UF

20% 10V

2

X5R-CERM 0201-1

1

C2612

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2632

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2623

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2633

10UF

20% 4V

2

X6S-CERM 0402-2

1

C2624

10UF

20% 4V

2

X6S-CERM 0402-2

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

10uF caps are shared between DRAM. Distribute evenly.

Distribute evenly.

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

26 OF 145

SHEET

25 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

113 22 7

22 7

113 22 7

113 23 7

23 7

113 23 7

23 22 7

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

109 116

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

MEM_A_CAA<9> MEM_A_CAA<8> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<5> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<1> MEM_A_CKE<0> MEM_A_CAA<4> MEM_A_CAA<3> MEM_A_CAA<2> MEM_A_CAA<1> MEM_A_CAA<0> MEM_A_CAB<9> MEM_A_CAB<8> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<5> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CKE<2> MEM_A_CKE<3> MEM_A_CAB<4> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<1> MEM_A_CAB<0> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0>

R2700 R2701 R2702 R2703 R2704 R2705 R2706 R2707 R2708 R2709 R2710 R2711 R2712 R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 R2721 R2722 R2723 R2724 R2725 R2726 R2727 R2728 R2729 R2730

68 68 68 68 68 39 39 82

68 68 68 68 68 68 68 68 68

39 39 82

68

68 68 68 82 82 82

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

MF2011% 1/20W

1% 1/20W 201 MF

1/20W1% 201 MF

1% MF2011/20W

201 MF1% 1/20W 201 MF1% 1/20W

MF2011% 1/20W

2011/20W1% MF

MF2011%821/20W 201 MF1% 1/20W 201 MF1% 1/20W

MF2011/20W1%

MF2011/20W1% 2011/20W MF1%

1% 1% 1% 1% 2011/20W MF 1%681/20W MF201 1% MF201

1/20W 1% 1% 1% 1/20W 20182MF

1%681/20W 201 MF 1% 1% MF

1/20W 201 1% 1% 1/20W MF

1/20W

1/20W MF2011%

2011/20W MF

MF1/20W 201

2011/20W MF

MF1/20W 201

201 MF1/20W1%

MF2011/20W

201 MF1/20W 201

MF1% 201

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2701

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2703

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2705

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2707

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2709

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2702

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2704

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2706

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2708

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2721

12PF

5% 25V

2

NP0-C0G 0201

113 24 7

24 7

113 24 7

113 25 7

25 7

113 25 7

25 24 7

D

PP0V6_S0_DDRVTT

109 116

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

MEM_B_CAA<9> MEM_B_CAA<8> MEM_B_CAA<7> MEM_B_CAA<6> MEM_B_CAA<5> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<1> MEM_B_CKE<0> MEM_B_CAA<4> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<1> MEM_B_CAA<0> MEM_B_CAB<9> MEM_B_CAB<8> MEM_B_CAB<7> MEM_B_CAB<6> MEM_B_CAB<5> MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<2> MEM_B_CKE<3> MEM_B_CAB<4> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<1> MEM_B_CAB<0> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_ODT<0>

R2740 R2741 R2742 R2743 R2744 R2745 R2746 R2747 R2748 R2749 R2750 R2751 R2752 R2753 R2754 R2755 R2756 R2757 R2758 R2759 R2760 R2761 R2762 R2763 R2764 R2765 R2766 R2767 R2768 R2769 R2770

68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39

82 82 68 68 68 68

82 82 82

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1% MF1/20W 201 1% MF1/20W 201

1/20W1% MF201 1/20W1% MF201

1% 201 MF1/20W

1/20W MF2011%

MF2011% 1/20W 1% 1/20W 1%

1/20W1% MF201 1/20W MF2011%

1% 201 MF1/20W

1% 201 MF

1/20W 1%391/20W 201 MF 1% 2011/20W MF 1% 201 MF

1/20W 1% MF1/20W 201 1% 2011/20W MF

1% 201 MF1/20W 1% MF1/20W68201

1/20W 2011%

1/20W MF

MF201 MF1/20W 201

2011/20W MF1% 2011/20W MF1%

201 MF1/20W1% 201 MF1/20W1% 201 MF1% 1/20W 201 MF1% 1/20W 201 MF1% 1/20W

2011/20W MF1%

MF MF1/20W 2011%

2011%

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2712

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2714

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2716

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2718

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2741

12PF

5% 25V

2

NP0-C0G 0201

C

B

CRITICAL

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1 603

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1 603

B

A

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0 dvt-fab10 27 OF 145 26 OF 121

A

D

345678

2 1

D

C

B

A

1

R2890

3.3K

5% 1/20W MF 201

2

TBT_X_SPI_CS_L

29

TBT_X_ROM_WP_L

27

TBT_X_ROM_HOLD_L

113 99

IN

BI

IN

BI

100K

1 2

100K

1 2

DP_X_SNK0_ML_C_P<0>

DP_X_SNK0_ML_C_N<0>

DP_X_SNK0_ML_C_P<1>

DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<2>

DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<3>

DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

DP_X_SNK1_ML_C_N<0>

DP_X_SNK1_ML_C_P<1>

DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<2>

DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<3>

DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

5% MF

1M

5%

1M

1/20W5% 201MF

1M

5% MF1/20W 201

R2891

3.3K

1/20W

R2862

2015% 1/20W MF

R2872

1/20W 201

R2860

MF 2011/20W

R2861

MF5%

2011/20W

R2870 R2871

1

5% MF

201

2

GND_VOID=TRUE

R2893

3.3K

5% 1/20W MF 201

2

6 1

3

7

DP_XA_HPD

DP_XB_HPD

TBT_XA_LSTX

TBT_XA_LSRX

TBT_XB_LSTX

TBT_XB_LSRX

PP3V3_UPC_XB_LDO

R2892

3.3K

5%

1/20W

8

VCC

MF

201

U2890

8MBIT-3.0V

W25Q80DVUXIE

CLK CS* WP*(IO2) HOLD*(IO3)

GND EPAD

USON

DI(IO0)

DO(IO1)

OMIT_TABLE

CRITICAL

4

9

5 2

SNK0 AC Coupling

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

10% 16V X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

X5R-CERM

1 2

10% 16V X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

16V 020110%

16V10%

SNK1 AC Coupling

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

16V10%

X5R-CERM

1 2

X5R-CERM

1 2

16V10% 0201

X5R-CERM

30 29 27

31 27

30 27

31 27

29

1

2

C2890

1UF

10%

6.3V

2

CERM 402

TBT_X_SPI_MOSITBT_X_SPI_CLK TBT_X_SPI_MISO

DP_X_SNK0_ML_P<0>

020110% 16V

DP_X_SNK0_ML_N<0>

020116V10%

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

0201

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

020116V10%

DP_X_SNK0_ML_P<3>

0201

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

020116V10%

DP_X_SNK1_ML_P<0>

020116V10%

DP_X_SNK1_ML_N<0>

020116V10%

DP_X_SNK1_ML_P<1>

020116V

DP_X_SNK1_ML_N<1>

020116V10%

DP_X_SNK1_ML_P<2>

020116V

DP_X_SNK1_ML_N<2>

020116V10%

DP_X_SNK1_ML_P<3>

020116V10%

DP_X_SNK1_ML_N<3>

0201

DP_X_SNK1_AUXCH_P

020116V10%

DP_X_SNK1_AUXCH_N

29 29

29

113 29

IN IN

PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1>

Y23 Y22

T23 T22

PCIE_RX0_P PCIE_RX0_N

PCIE_RX1_P PCIE_RX1_N

U2800

TBT-AR-4C-CNTRL

SYM 1 OF 2

FCBGA

OMIT_TABLE

PCIE_TX0_P

PCIE_TX0_N

PCIE_TX1_P

PCIE_TX1_N

CRITICAL

113 29

10K PU ON CLOCKS PAGE

113 27

89 29

OUT

113 27

R2830

100K

5%

100K

5%

1/20W

MF

201

1 2

TF

R2855

1/20W

MF

201

1

2

1/20W

GND_VOID=TRUE

12

0.1UF

12

0.1UF

GND_VOID=TRUE

113 27

89 29

OUT

R2831

113 27

113 30

DP_XA_AUXCH_P

BI

DP_XA_AUXCH_N

BI

PLACE_NEAR=U2800.H6:2MM PLACE_NEAR=U2800.J6:2MM

0201

16V

10%

X5R-CERM

16V

10%

X5R-CERM

IN IN

1

2

14K

R2850

4.75K

0.5% 0201

C2810 C2811

12

IN

12

IN

20

OUT

29

12

201

1% MF

113 32

29

30 27

30 29 27

PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3>

PCIE_CLK100M_TBT_X_P PCIE_CLK100M_TBT_X_N TBT_X_CLKREQ_L

113 27

DP_X_SNK0_ML_P<0> DP_X_SNK0_ML_N<0>

DP_X_SNK0_ML_P<1> DP_X_SNK0_ML_N<1>

DP_X_SNK0_ML_P<2> DP_X_SNK0_ML_N<2>

DP_X_SNK0_ML_P<3> DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P DP_X_SNK0_AUXCH_N

DP_X_SNK0_HPD

DP_X_SNK0_DDC_CLK

IN

DP_X_SNK0_DDC_DATA

BI

113 27

DP_X_SNK1_ML_P<0> DP_X_SNK1_ML_N<0>

DP_X_SNK1_ML_P<1> DP_X_SNK1_ML_N<1>

DP_X_SNK1_ML_P<2> DP_X_SNK1_ML_N<2>

DP_X_SNK1_ML_P<3> DP_X_SNK1_ML_N<3>

DP_X_SNK1_AUXCH_P DP_X_SNK1_AUXCH_N

DP_X_SNK1_HPD

DP_X_SNK1_DDC_CLK

IN

DP_X_SNK1_DDC_DATA

BI

DP_X_SNK_RBIAS

1/20W

101 29

29 15

101 29

103 101 29

OUT

PLACE_NEAR=U2800.Y18:2MM

JTAG_TBT_TDI

IN

JTAG_TBT_X_TMS

IN

JTAG_TBT_TCK

IN

JTAG_ISP_TDO

TBT_X_RBIAS TBT_X_RSENSE

IN IN

OUT OUT

IN IN

113

BI BI

OUT

IN IN

USBC_XA_D2R_P<2> USBC_XA_D2R_N<2>

USBC_XA_R2D_C_P<2> USBC_XA_R2D_C_N<2>

USBC_XA_R2D_C_P<1> USBC_XA_R2D_C_N<1>

USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>

DP_XA_AUXCH_C_P DP_XA_AUXCH_C_N

USB_UPC_XA_P USB_UPC_XA_N

TBT_XA_LSTX TBT_XA_LSRX DP_XA_HPD

TBT_XA_USB2_RBIAS

PLACE_NEAR=U2800.H19:6MM

R2854

499

1/20W

1% MF

201

1

2

54

OUT

TBTTHMSNS_X_D1_P

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

NC

M23 M22

AC5 N16

AC7

AC9

AB11

AC11

AB13

AC13

W11

AB15

AC15

AB17

AC17

AB19

AC19

AB21

AC21

W12

W15

AC23

AB23

AC1

PCIE_RX2_P PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N PCIE_CLKREQ*

AB7

DPSNK0_ML0_P DPSNK0_ML0_N

AB9

DPSNK0_ML1_P DPSNK0_ML1_N

DPSNK0_ML2_P DPSNK0_ML2_N

DPSNK0_ML3_P DPSNK0_ML3_N

Y11

DPSNK0_AUX_P DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA DPSNK1_ML0_P

DPSNK1_ML0_N DPSNK1_ML1_P

DPSNK1_ML1_N DPSNK1_ML2_P

DPSNK1_ML2_N DPSNK1_ML3_P

DPSNK1_ML3_N

Y12

DPSNK1_AUX_P DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS THERMDA

THERMDA

V18

PCIE_ATEST TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

SINK PORT 0

SINK PORT 1

PORT A

DEBUG

PCIE GEN3

SOURCE PORT 0

MISC

PORT B POC GPIO LC GPIO

PB_DPSRC_AUX_N

TBT PORTS

PCIE_TX2_P

PCIE_TX2_N

PCIE_TX3_P

PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P

DPSRC_ML1_N

DPSRC_ML2_P

DPSRC_ML2_N

DPSRC_ML3_P

DPSRC_ML3_N DPSRC_AUX_P

DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7

GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_EN

TEST_PWR_GOOD

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO EE_CS* EE_CLK

PB_RX1_P

PB_RX1_N

PB_TX1_P

PB_TX1_N

PB_TX0_P

PB_TX0_N PB_RX0_P

PB_RX0_N

PB_DPSRC_AUX_P

PB_USB2_D_P PB_USB2_D_N

PB_LSTX PB_LSRX

PB_DPSRC_HPD PB_USB2_RBIAS

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

MONDC_DPSNK_0 MONDC_DPSNK_1

MONDC_DPSRC

113

V23 V22

P23 P22

K23 K22

F23 F22

L4

PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L TBT_X_PCIE_BIAS

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1 N6 U1

U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1

E1 AB5 F4 D22

D23 AB3

AC4 AC3 AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4 B5 G2

F19 D6 A23

B23 E18 W13

W18

AB2

NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

29

DP_X_SRC_RBIAS I2C_TBT_X_SDA

I2C_TBT_X_SCL

TBT_X_ROM_WP_L

27

TBT_X_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_X_CIO_PLUG_EVENT_L TBT_X_HDMI_DDC_DATA TBT_X_HDMI_DDC_CLK TBT_X_TMU_CLK_IN I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L TBT_X_USB_PWR_EN TBT_X_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_X_CIO_PWR_EN

TBT_X_TEST_EN TBT_X_TEST_PWR_GOOD USBC_X_RESET_L TBT_X_XTAL25M_IN

TBT_X_XTAL25M_OUT UPC_X_SPI_MOSI

UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK

USBC_XB_D2R_P<2> USBC_XB_D2R_N<2>

USBC_XB_R2D_C_P<2> USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<1> USBC_XB_R2D_C_N<1>

USBC_XB_D2R_P<1> USBC_XB_D2R_N<1>

DP_XB_AUXCH_C_P DP_XB_AUXCH_C_N

USB_UPC_XB_P USB_UPC_XB_N

TBT_XB_LSTX TBT_XB_LSRX DP_XB_HPD

BI BI

OUT

IN IN

TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:5MM

1

R2853

NC NC

NC

499

1% 1/20W MF 201

2

BOM_COST_GROUP=TBT

29

IN

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

IN

OUT

29

33 29

113 29

To SPI Flash

IN IN

OUT OUT

IN IN

31 27

OUT OUT

29 20

113 29

PLACE_NEAR=

U2800.N6:2MM

R2852

1/20W

1 2

1%

29

OUT OUT

29

OUT

BI

91

OUT

103

IN

29

IN IN

29

IN

113 32

GND_VOID=TRUE

113 32

103 101 29

91

31 30 29

PU at PCH

31 30

1

R2829

100

5% 1/20W MF 201

2

C2812

0.1UF

C2813

0.1UF

GND_VOID=TRUE

DRAWING

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=U2800.N16:2MM

R2851

3.01K

1 2

1%

1/20W

MF

201

201MF

14K

PP3V3_S5_TBT_X_SW

1

R2836

2.2K

5% 1/20W MF 201

2

29

IN

114 101 89 76 73 70 46 20 12

1

R2825

100

5% 1/20W MF 201

2

1 2

DP_XB_AUXCH_P

10% 16V

X5R-CERM

10% 16V

X5R-CERM

0201

DP_XB_AUXCH_N

0201

LAST_MODIFIED=Wed Aug 24 09:57:49 2016

USB-C HIGH SPEED 1

Apple Inc.

R

PP3V3_S5_TBT_X_SW

1

R2834

2.2K

5% 1/20W MF 201

2

1

R2837

2.2K

5% 1/20W MF 201

2

IN

not used

1

R2827

100K

5% 1/20W MF 201

2

BI

29

BI

1

R2835

2.2K

5% 1/20W MF 201

2

BI

27 33

113 31

27 33

29

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

28 OF 145

SHEET

27 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2931

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2984

1.0UF

20%

6.3V

2

X5R 0201-1

C2945

1.0UF

20%

6.3V X5R

0201-1

1

C2932

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

1

C2933

2

1

C2964

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R 0201-1

C2946

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

1

2

SOURCED BY INTERNAL SWITCH

1

C2934

1.0UF

2

1

C2965

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY INTERNAL SWITCH

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

C2947

1.0UF

20%

6.3V X5R

0201-1

20%

6.3V X5R 0201-1

VOLTAGE=3.3V

1

2

1

C2935

1.0UF

2

1

C2966

1.0UF

20%

6.3V

2

X5R 0201-1

PP0V9_TBT_X_DP

1

C2936

1.0UF

20%

6.3V X5R 0201-1

SOURCED BY INTERNAL SWITCH

20%

6.3V

2

X5R 0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R 0201-1

PP0V9_TBT_X_PCIE

29

PP0V9_TBT_X_USB

29

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=0.9V

PP0V9_TBT_X_CIO

29

PP3V3_TBT_X_ANA_PCIE

PP3V3_TBT_X_ANA_USB2

1

C2920

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY INTERNAL SWITCH

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12 A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F20

VSS_ANA

F16

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J18

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

P1

VSS_ANA

P2

VSS_ANA

R5

VSS_ANA

R18

VSS_ANA

R19

VSS_ANA

R20

VSS_ANA

R22

VSS_ANA

U2800

TBT-AR-4C-CNTRL

SYM 2 OF 2

FCBGA

OMIT_TABLE

CRITICAL

VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC

VCC0P9_LVR_SENSE

GND

VCC3P3_LC VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC0P9_SVR VCC0P9_SVR

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS

SVR_VSS

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VSS_ANA VSS_ANA VSS_ANA VSS_ANAVSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R6 F8 R13 H9 A2

A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11

PP3V3_TBT_X_LC PP3V3_S5_TBT_X_SW

1

C2991

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2975

10UF

20%

6.3V

2

CERM-X5R 0402-4

BYPASS=U2800.A2:A1:3MM

116

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V

DIDT=TRUE SWITCH_NODE=TRUE

1

C2976

10UF

20%

6.3V

2

CERM-X5R 0402-4

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_X

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V

C2992

1.0UF

0201-1

1

20%

6.3V

2

X5R

support page

XW

XW2900

SM

1 2

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

PP3V3_TBT_X_F

VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

C2977

10UF

20%

6.3V

2

CERM-X5R 0402-4

CRITICAL

L2950

1 2

1210

SOURCED BY INTERNAL SWITCH

20%

6.3V X5R

1

2

C2993

1.0UF

0201-1

29

TBTTHMSNS_X_D1_N

C2954

CERM-X5R

10UF

20%

6.3V

0402-4

1

C2978

10UF

20%

6.3V

2

CERM-X5R 0402-4

1

2

OUT

C2990

1.0UF

0201-1

1

2

C2955

10UF

CERM-X5R

0402-4

2x 10uF outside BGA area

1

20%

6.3V

2

X5R

1

2

C2950

47UF

20%

6.3V CER-X5R 0603

1

20%

6.3V

2

C2994

47UF

CER-X5R

C2917

12PF

5% 25V NP0-C0G 0201

20%

6.3V 0603

1

C2951

47UF

2

1

2

1

2

20%

6.3V CER-X5R 0603

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V

54

BOM_COST_GROUP=TBT

C2995

47UF

20%

6.3V

CER-X5R

0603

C2910

1.0UF

20%

6.3V X5R 0201-1

1

2

1

2

1

2

1 2

0603

L2990

1.0UH-20%-2.1A-0.128OHM

CRITICAL

C2911

1.0UF

20%

6.3V X5R 0201-1

C2952

47UF

20%

6.3V CER-X5R 0603

FROM USB-C PORT CONTROLLER (UPC)

1

C2981

1.0UF

20%

6.3V

2

X5R 0201-1

PP3V3_TBT_X_S0

1

C2912

1.0UF

20%

6.3V

2

X5R 0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2913

1.0UF

20%

6.3V

2

X5R 0201-1

SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SOURCED BY INTERNAL SWITCH

29 33

1

C2914

1.0UF

20%

6.3V

2

X5R 0201-1

ISOLATE GND OF SVR_IND CAPSAdd XW or alias on

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

1

2

29 110 116

1

C2915

1.0UF

20%

6.3V

2

X5R 0201-1

C2980

0.1UF

10% 16V X5R-CERM 0201

29

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

C2916

1.0UF

20%

6.3V

2

X5R 0201-1

USB-C HIGH SPEED 2

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

BRANCH

dvt-fab10

PAGE

29 OF 145

SHEET

28 OF 121

D

C

B

A

D

10.0.0

8 7 5 4 2 1

36

345678

2 1

TMU CLKs

TBT_X_TMU_CLK_OUT

27

MAKE_BASE=TRUE

TBT_X_TMU_CLK_OUT

USBC 5V EN PD

UPC_X_5V_EN

29 30

5%

R3032

1/20W 201MF

D

DP SRC OPTIONS

IF DP SRC NOT USED

NC_DP_X_SRC_ML_P<3..0>

27

NC_DP_X_SRC_ML_N<3..0>

27

NC_DP_X_SRC_AUX_P

27

NC_DP_X_SRC_AUX_N

27

FUSES FOR UPC

PP20V_USBC_XA_VBUS

29 30

C

PP20V_USBC_XB_VBUS

29 31

TBT_X_XTAL25M_OUT

IN

NOSTUFF

R3006

to/from Ridge

OUT

AR/ACE SPI BUS SERIES R'S

27

B

27

TBT_X_XTAL25M_IN

TBT_X_SPI_CLK TBT_X_SPI_CS_L TBT_X_SPI_MOSI TBT_X_SPI_MISO

ROM

R3025

1/20W MF5% 201

PLACE_NEAR=U2800.V2:5mm

ACE/SMC I2C PU

100K

PLACE_NEAR=Q3100:5MM

6AMP-32V-0.0095OHM

PLACE_NEAR=Q3200:5MM

6AMP-32V-0.0095OHM

21

27

NC_DP_X_SRC_ML_P<3..0>

NC_DP_X_SRC_ML_N<3..0>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

CRITICAL

0603

F3000

21

PP20V_USBC_XA_VBUS_F

CRITICAL

0603

740S0135

F3001

21

PP20V_USBC_XB_VBUS_F

25MHz xtal

R3007

1M

5%

1/20W

MF

201

113

0

1

2

TBT_X_XTAL25M_OUT_R

21

2015%

MF1/20W

31

R3094 R3095 R3096 R3097 R3098 R3090 R3091 R3092 R3093

15

21

TBT_T_TMU_CLK_IN

PP3V3_G3H

R3038

10K

1/20W

DP_X_SRC_HPD

42

5% MF

201

CRITICAL

21

SMC_USBC_INT_L

Y3000

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

100

15 15 15 15 15 15 15 15

21

MAKE_BASE=TRUE

TBT_T_TMU_CLK_IN

109

100K

1/20W5%

201MF

21

103

R3026

R3040

1M

21

5%

1/20W

MF

201

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE NO_TEST=1

MAKE_BASE=TRUE MAKE_BASE=TRUE

30

31

C3002

20PF

21

5% 25V C0G

0201

C3003

20PF

21

5% 25V C0G

0201

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG

1/20W 2015% MF

UPC_XB_SPI_CLK

5% 2011/20W

UPC_XB_SPI_CS_L

5%

UPC_XB_SPI_MOSI UPC_XB_SPI_MISO

1/20W

UPC_X_SPI_CLK

5%

1/20W

UPC_X_SPI_CS_L

1/20W MF5% 201

UPC_X_SPI_MOSI

1/20W MF5% 201

UPC_X_SPI_MISO

5%

MF

MF1/20W 201

201MF5% 1/20W

201MF5%

MF 201

201MF1/20W

101

46 29

OMIT

R3089

NOSTUFF

2 1

NONE

R3088

NOSTUFF

2 1

NONE

ACE Debug Support

UPC_XA_DBG_UART_TX

402NONE

UPC_XA_DBG_UART_RX

OMIT

TP_UPC_XB_DBG_UART_TX

402

NONENONE

TP_UPC_XB_DBG_UART_RX

Ridge PDs

DP_X_SNK0_DDC_CLK

27

MAKE_BASE=TRUE

DP_X_SNK0_DDC_CLK

DP_X_SNK0_DDC_DATA

27

DP_X_SNK0_DDC_DATA

27

DP_X_SNK1_DDC_CLK

27

DP_X_SNK1_DDC_DATA

29

IN

OUT

IN

OUT

MAKE_BASE=TRUE

DP_X_SNK1_DDC_CLK

MAKE_BASE=TRUE

DP_X_SNK1_DDC_DATA

MAKE_BASE=TRUE

29 27

89 27

30 27

29 30 31

28

29 27

29

103 46 29

31 30 31 30

31

Ace

31

29 27

AR

29 27

I2C_TBT_XB_INT_L I2C_UPC_X_SCL2 I2C_UPC_X_SDA2 SMC_USBC_INT_L

UPC_XA_UART_TX UPC_XA_UART_RX

101 27

114 30

30

114 30

30

114 31

R3067

100K

1/20W

5% MF

201

21

31

R3068

100K

1/20W

5% MF

201

21

R3069

100K

1/20W

5% MF

201

21

R3070

100K

1/20W

TBT_X_CIO_PLUG_EVENT_L DP_X_SNK0_HPD DP_X_SNK1_HPD DP_XA_HPD TBT_POC_RESET PP3V3_TBT_X_LC

21

5% MF

201

USBC_DBG

RIDGE DEBUG CONN

Place on bottom

ACE DEBUG CONN

Place on bottom

USBC_DBG

J3000

505070-1220

M-ST-SM

1413

21 43 65 87 109 1211

15

RIDGE JTAG ISOLATION

JTAG_TBT_TCK

JTAG_TBT_TDI

30

TP_UPC_XA_SWD_DATA

?

TP_UPC_XA_SWD_CLK TP_UPC_XB_SWD_DATA

31

TP_UPC_XB_SWD_CLK

31

16

R3043 R3044

ACE A RPD STRAPPING

USBC_XA_CC1

USBC_XA_CC2

MAKE_BASE=TRUE

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

NC ALIASES / NO TEST

IN

15

I2C_TBT_XA_INT_L I2C_TBT_X_SDA

I2C_UPC_XA_DBG_CTL_SDA I2C_UPC_XA_DBG_CTL_SCLTBT_X_SPI_CLK_DBG

NC_UPC_XB_I2C_ADDR

GND ALIASES

GND

30 31 103 104 105

GND

31

GND

30

GND

30

GND

30

GND

30

GND

30

GND

30

GND

31

GND

30

J3001

M-ST-SM

1413

21 43

65 7 9

8

10

1211

16

I2C_TBT_X_SCL

0

21

0

21

PLACE_NEAR=U1100.AK28:10mm

505070-1220

TBT_X_PCI_RESET_L USBC_X_RESET_L

PP3V3_S5_TBT_X_SW PP0V9_TBT_X_PCIE PP0V9_TBT_X_USB PP0V9_TBT_X_CIO

PLACE_NEAR=U1100.AJ29:10mm

JTAG_ISP_TCK

MF1/20W5%

JTAG_ISP_TDI

5% MF1/20W 0201

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

TP3004

MAKE_BASE=TRUE

0201

TP3001 TP3002

TP3003

30

30 29

15

30 29

31 29

20 27

33 27

28 33

28

29 27

15

30

31

IN

JTAG_TBT_X_TMS JTAG_TBT_T_TMS

103

32 30

USBC_XB_CC1

31

USBC_XB_CC2

31

UPC_XA_HPD_RX

5% 1/20W 201MF

UPC_XB_HPD_RX

USB_UPC_XA_P

27

USB_UPC_XA_N

27

29 30

31

USB2_UPC_XB_P

31

MAKE_BASE=TRUE

NOSTUFF

R3036

1/20W MF 2015%

UPC_X_5V_EN UPC_X_5V_EN

USB2_UPC_XB_P

USB2_UPC_XB_N

31

MAKE_BASE=TRUE

USB2_UPC_XB_N

TBT_X_CIO_PWR_EN

27 30 31

TBT_X_USB_PWR_EN

27 30 31

PM_BATLOW_L

27

SMC_PME_S4_DARK_L

27 101 103

SMC_PME_S4_DARK_L

30 31 103 104 105

UPC_X_SPI_CLK UPC_X_SPI_CS_L UPC_X_SPI_MOSI UPC_X_SPI_MISO UPC_T_SPI_CLK UPC_T_SPI_CS_L UPC_T_SPI_MOSI UPC_T_SPI_MISO

JTAG_ISP_TDO

31

27 29

101 103

27 101 103

IN

TBT_POC_RESET

TBT_X_CIO_PLUG_EVENT_L

IN

UPC_XA_FAULT_L

UPC_XB_FAULT_L

PP3V3_S4

30

ACE B RPD STRAPPING

ACE PDs

30 29

UPC_XA_HPD_RX

31 29

UPC_XB_HPD_RX

R3035

R3081

2 1

5% 1/20W MF 0201

R3082

2 1

1/20W MF5%

0

0201

21

R3084

R3085

5% 1/20W MF 0201

0

21

MF1/20W5%

0

21

SIGNAL ALIASES

UPC_X_5V_EN

MAKE_BASE=TRUE

R3086

5%

R3087

MF

SMC_USBC_INT_L

TBT_X_CIO_PLUG_EVENT_L

R3078

R3079

5% MF

0

21

1/20W

0201

5% 1/20W MF 0201

0

21

USB_UPC_PCH_XB_P

1/20W

0201MF

0

21

USB_UPC_PCH_XB_N

1/20W5%

0201

MAKE_BASE=TRUE

TBT_X_CIO_PWR_EN

MAKE_BASE=TRUE

TBT_X_USB_PWR_EN

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

SMC_USBC_INT_L

MAKE_BASE=TRUE

0

21

MAKE_BASE=TRUE

JTAG_TBT_X_TMS

MAKE_BASE=TRUE

JTAG_TBT_T_TMS

MAKE_BASE=TRUE

PP3V3_S4

TBT_POC_RESET

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

R3033

1/20W

R3034

MF5% 1/20W 201

SMC_RESET_L

USB_UPC_XB_P

NOSTUFF

0201

USB_UPC_XB_N

NOSTUFF

34

27 15

103 101 15

NO_STUFF

100K

201MF5%

NO_STUFF

100K

14

29 27

14

114 110 103

OUTIN

12

21

27

I2C SERIES R'S

PLACE_NEAR=U5000:5mm

I2C_UPC_X_SDA2

32 31

30

I2C_UPC_X_SDA2

31

29

30

31

29

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2 I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

5% 201

5% MF

R3041

MF1/20W

R3042

1/20W 201

33

21

SMBUS_SMC_4_G3H_SDA

PLACE_NEAR=U5000:5mm

33

21

SMBUS_SMC_4_G3H_SCL

49

D

21

RIDGE 0.9V SVR XW

XW3000

P0V9_TBT_X_SVR_AGND

28

114 76 64 57 48

NO_XNET_CONNECTION=1

SM

21

TBT to ACE

TBT

Alpine Ridge U2800

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

27 29

27 29 27 29

(MASTER)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L

I2C_TBT_XB_INT_L

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L

103 46 12

103 48 47 46

Ridge PCIE Caps

GND_VOID=TRUE

113 111

103 15

103 46 29 30

103 15 14 31 30 29

113 111

IN

113 111

113 27

PCIE_TBT_X_R2D_C_P<0>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<0>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<1>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<1>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<2>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_N<2>

GND_VOID=TRUE

PCIE_TBT_X_R2D_C_P<3>

GND_VOID=TRUE

IN

PCIE_TBT_X_R2D_C_N<3>

PCIE_TBT_X_D2R_C_P<0>

PCIE_TBT_X_D2R_C_N<0>

6.3VX5R0201 20%

6.3V

X5R0201 20%

6.3VX5R0201 20%

6.3V

X5R0201 20%

2 1

C3040

0.22UF

C3041

0.22UF

C3042

0.22UF

C3043

0.22UF

C3044

0.22UF

C3045

0.22UF

C3046

0.22UF

C3047

0.22UF

C3050

0.22UF

C3051

0.22UF

C3052

0.22UF

PCIE_TBT_X_R2D_P<0>

PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1>

PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2>

PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3>

PCIE_TBT_X_R2D_N<3>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<0>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<1>PCIE_TBT_X_D2R_C_P<1>

GND_VOID=TRUE

Pri ACE

U3100

Sec ACE

U3200

30

31

OUT

113 27

111 113

C

B

A

POWER ALIASES

PP3V3_UPC_XB_LDO

27

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XB_LDO

31

PP3V3_UPC_XA_LDO

30

PP3V3_UPC_XA_LDO

30

PP20V_USBC_XA_VBUS

29 30

PP20V_USBC_XB_VBUS

29 31

PPDCIN_G3H

30 31 103 104 105

PP5V_S4_X_USBC

30

PP5V_S4_X_USBC

31

PP5V_S4_X_USBC

34 116

PP3V3_TBT_X_S0

28 110 116

MAKE_BASE=TRUE

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PPDCIN_G3H

PP5V_S4_X_USBC

MAKE_BASE=TRUE

PP3V3_TBT_X_S0

31

30

32

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=20V

116 114 64 50

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

14

114 47 46

USB3_EXTA_R2D_C_P

IN

USB3_EXTA_R2D_C_N

PP3V3_S4

31

MAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

IN

OUT

30

MAKE_BASE=TRUE

SMC_DEBUGPRT_RX_L

TP_USBC_XA_RESET_L

DCI

PCH USB3

X5R-CERM2116V 10% 0201

USB2_UPC_XA_P

30

MAKE_BASE=TRUE

USB2_UPC_XA_P

USB2_UPC_XA_N

30

MAKE_BASE=TRUE

USB2_UPC_XA_N

14

OUT OUT

0.1UF

21

10%

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

MAKE_BASE=TRUE

TP_USBC_XA_RESET_L

MAKE_BASE=TRUE

USB3_EXTA_D2R_P USB3_EXTA_D2R_N

MAKE_BASE=TRUE

C3020

USB3_EXTA_R2D_P

MAKE_BASE=TRUE

C3021

USB3_EXTA_R2D_N

0201X5R-CERM 16V

R3076

5% MF 0201

R3077

5% 1/20W MF

MAKE_BASE=TRUE

0

21

USB_UPC_PCH_XA_P

1/20W

0

21

USB_UPC_PCH_XA_N

0201

SMC MOJO

31

USB3_EXTA_D2R_P USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

14

IN IN

OUT

PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2>

PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_N<3>

30

113 27

30

IN

BOM_COST_GROUP=TBT

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

2 1

6.3VX5R0201 20%

SYNC_MASTER=X363_AGOTETI SYNC_DATE=08/08/2016

PAGE TITLE

C3053

0.22UF

C3054

0.22UF

C3055

0.22UF

C3056

0.22UF

C3057

0.22UF

PCIE_TBT_X_D2R_N<1>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<2>

GND_VOID=TRUE

PCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>

GND_VOID=TRUE

PCIE_TBT_X_D2R_N<3>

OUT

111 113

USB-C Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

30 OF 145

SHEET

29 OF 121

D

A

8 7 5 4 2 1

36

D

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

345678

2 1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

105 104 103 31 29

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_XA_VBUS

29

PP3V3_UPC_XA_LDO

29

PP3V3_G3H

109

GND

PP5V_S4_X_USBC

29

FUSE

Add on support page

1

C3100

10UF

20%

6.3V

2

CERM-X5R 0402-1

29

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

1

C3101

1UF

10% 35V

2

X5R 0402

B11

A11

PP_5V0

D11

C11

PP_5V0

A7

A6

PP_HV

B7

A8

PP_HV

H11

H10

PP_CABLE

J10

VBUS

S2 5

K11

J11

VBUS

G2 4

H1

VBUS

B1

VDDIO

VIN_3V3

3

2

NC

TP_Q3100_DRAIN

UPC_XA_GATE2

G1

H2

LDO_3V3

VOUT_3V3

A2

K1

LDO_1V8A

LDO_1V8D

G1

S1

1

8

UPC_XA_GATE1

E1

LDO_BMC

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20% 4V

2

X5R-CERM 0201

105 104 103 31 29

P3V3_TBT_X_SX_EN_R

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

33

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R 0402-1

29

C

B

PP3V3_UPC_XA_LDO

1M

R3109

21

5% 201MF1/20W

R3108

21

1/20W

5% 201MF

21

R3105

5% MF1/20W

29

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

UPC_XA_UART_RX

201

29 30

29 30 31

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

CRITICAL

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

R3103

15K

0.1% 1/20W TF-LF

0201

TO SMC

29 31

IN

29

OUT

29 114

27 29 31

IN

27 29 31

IN

27 29

OUT

29

OUT

29 31 103 104 105

OUT

29

OUT

29

IN

GND I2C_ADDR PRIMARY ONLY

1

29

2

29

BI BI OUT

OUT OUT

IN

OUT

TBT_POC_RESET TP_USBC_XA_RESET_L

UPC_XA_DBG_UART_TX

UPC_XA_DBG_UART_RX

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

DP_XA_HPD

UPC_XA_HPD_RX

UPC_X_5V_EN

SMC_PME_S4_DARK_L

UPC_XA_FAULT_L

GND

UPC_XA_R_OSC

I2C_UPC_XA_DBG_CTL_SCL

29 30

I2C_UPC_XA_DBG_CTL_SDA

29 30

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XA_INT_L

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

SMC_USBC_INT_L GND

GND GND GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL OMIT_TABLE

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1 C_SBU2

NC

H7 B10

A10 B9

A9

L9

USBC_XA_CC1

L10

USBC_XA_CC2

K9

USBC_XA_CC1

K10

USBC_XA_CC2

K6 L6

K7 L7

K8 L8

L11

USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N

USBC_XA_USB_DBG_BOT_P USBC_XA_USB_DBG_BOT_N

USBC_XA_SBU1 USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

UPC_XA_SS

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI BI

29

32 115

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

BI

29 32

BI

1

C3114

32

BI

32

BI

32

BI

32

BI

220PF

10% 16V

2

CER-X7R 0201

1

C3113

220PF

10% 16V

2

CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

B

A

29

BI

29

BI

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO

USB2_UPC_XA_P

USB2_UPC_XA_N

PP3V3_S4

29

NO_XNET_CONNECTION=1

PLACE_NEAR=U3100:5mm

27 113

BI

27 113

BI

L3000

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

4

32

1

R3110

100K

5% 1/20W MF 201

2

29

29 30 31

29 31

27

29

TP_UPC_XA_SWD_DATA TP_UPC_XA_SWD_CLK

IN

OUT

IN

OUT

UPC_XA_UART_RX UPC_XA_UART_TX

TBT_XA_LSTX TBT_XA_LSRX

USB_UPC_XA_F_P USB_UPC_XA_F_N

DP_XA_AUXCH_P DP_XA_AUXCH_N

BI BI BI BI

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P USB3_EXTA_R2D_N

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1

GND

D6

GND

E5

GND

E6

GND

E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

L1

B8

H4

H5

G8

H8

D8

GND

E8

GND

F6

GND

F7

GND

F8

GND

G6

GND

G7

PAGE TITLE

SYNC_DATE=08/08/2016SYNC_MASTER=X362_GKOO

A

1

R3111

100K

NO_XNET_CONNECTION=1

8 7 5 4 2 1

5% 1/20W MF 201

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

29

BOM_COST_GROUP=USB-C

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

USB-C PORT CONTROLLER A

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0

dvt-fab10

31 OF 145

30 OF 121

D

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3200

FDPC4044

PWR-CLIP-33

PP20V_USBC_XB_VBUS

29

PP3V3_UPC_XB_LDO

29

PP3V3_G3H

109

GND

PP5V_S4_X_USBC

29

CAP FOR PP_5V0 ON VR PAGE

FUSE

Add on support page

1

C3200

10UF

20%

6.3V

2

CERM-X5R 0402-1

PP20V_USBC_XB_VBUS_F

29

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=20V

1

2

A11

B11

C11

D11

A6A7A8

PP_HV

PP_5V0

PP_HV

PP_5V0

C3201

1UF

10% 35V X5R 0402

H10

B7

PP_HV

PP_CABLE

S2 5

H11

J10

VBUS

G2 4

J11

VBUS

K11B1H1

VBUS

VIN_3V3

NC

2

3

VDDIO

K1

H2

LDO_3V3

VOUT_3V3

G1

S1

1

8

UPC_XB_GATE1

TP_Q3200_DRAIN

UPC_XB_GATE2

A2G1E1

LDO_1V8A

LDO_BMC

LDO_1V8D

345678

1

C3205

1.0UF

20%

6.3V

2

X5R 0201-1

1

C3208

10UF

20%

6.3V

2

CERM-X5R 0402-1

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

PP1V1_UPC_XB_LDO_BMC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V

2 1

29 30 103 104 105

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

PP3V3_UPC_XB_LDO P3V3_TBT_X_SX_EN_R

PP1V8_UPC_XB_LDOA

PP1V8_UPC_XB_LDOD

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V

1

C3204

2.2UF

20% 4V

2

X5R-CERM 0201

29

33

VOLTAGE=3.3V

VOUT_3V3 FOR RIDGE, OR FLOAT IF UNUSED

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

C3206

0.47UF

10%

6.3V

2

CERM-X5R 0201

D

C

B

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

PP3V3_UPC_XB_LDO

1M

1 2

1M

1 2

1M

1 2

R3209

5%

R3208

1/20W5% MF 201

R3205

5%

29

I2C_UPC_XB_DBG_CTL_SCL

2011/20W MF

I2C_UPC_XB_DBG_CTL_SDA

UPC_XA_UART_TX

201MF1/20W

31

TBT_POC_RESET USBC_X_RESET_L_R

TP_UPC_XB_DBG_UART_TX TP_UPC_XB_DBG_UART_RX

BI BI

27

29

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

OUT

DP_XB_HPD UPC_XB_HPD_RX

OUT OUT OUT

IN

UPC_X_5V_EN

SMC_PME_S4_DARK_L

UPC_XB_FAULT_L

GND

NC_UPC_XB_I2C_ADDR

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

105 104 103 30 29

30 29

IN

33

OUT

114 29

30 29 27

UPC_XB_R_OSC

CRITICAL

15K

0.1% 1/20W TF-LF

0201

1

2

TO SMC

R3203

31 30 29

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

NEED 0.1%

I2C_UPC_XB_DBG_CTL_SCL

31

I2C_UPC_XB_DBG_CTL_SDA

31

29

BI BI OUT

OUT OUT

IN

OUT

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XB_INT_L

I2C_UPC_X_SDA2 I2C_UPC_X_SCL2

SMC_USBC_INT_L

UPC_XB_SPI_CLK UPC_XB_SPI_MOSI UPC_XB_SPI_MISO UPC_XB_SPI_CS_L

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

U3200

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL OMIT_TABLE

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP

C_USB_BN

C_SBU1 C_SBU2

NC

H7 B10

A10 B9

A9

L9

USBC_XB_CC1

L10

USBC_XB_CC2

K9

USBC_XB_CC1

K10

USBC_XB_CC2

K6

USBC_XB_USB_TOP_P

L6

USBC_XB_USB_TOP_N

K7

USBC_XB_USB_BOT_P

L7

USBC_XB_USB_BOT_N

K8

USBC_XB_SBU1

L8

USBC_XB_SBU2

GROUND

L11

UPC_XB_SS

NC or GND to dissipate heat

1

C3209

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI BI

29

32

C

BI

1

C3214

220PF

10% 16V

2

CER-X7R 0201

115 32

1

C3213

220PF

10% 16V

2

CER-X7R 0201

32 29

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

B

29

31 30 29

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

BI

USB2_UPC_XB_P

1

4

PLACE_NEAR=U3200.L5:5mm

30 29

27

OUT

IN

OUT

TP_UPC_XB_SWD_DATA TP_UPC_XB_SWD_CLK

UPC_XA_UART_TX

UPC_XA_UART_RX

TBT_XB_LSTX

TBT_XB_LSRX

USB_UPC_XB_F_P

BI

USB2_UPC_XB_N

2 3

PLACE_NEAR=U3200.K5:5mm

USB_UPC_XB_F_N DP_XB_AUXCH_P

DP_XB_AUXCH_N

PP3V3_S4

29

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO

NO_XNET_CONNECTION=1

113 27

BI BI

1

R3210

100K

5% 1/20W MF 201

2

42

29

BI BI BI BI

SOC_SWCLK_DBG

SOC_SWDIO_DBG

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

GND

A1D6E5E6E7

GND

F5

GND

G5

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

L1

H4

H5G8H8

B8D8E8

GND

F6F7F8

GND

G6

GND

G7

GND

A

5%

1/20W

MF

201

1

PAGE TITLE

USB-C PORT CONTROLLER B

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

29

BOM_COST_GROUP=USB-C

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

36

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

R3211

100K

NO_XNET_CONNECTION=1

8 7 5 4 2 1

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0 dvt-fab10 32 OF 145 31 OF 121

A

D

345678

2 1

D

C

B

CC1

31 29

113 27

TBT_R2D0

113 27

TBT_D2R0 SBU2

113 27

115 31

USB2 BOT

SBU1

115 30

113 27

TBT_R2D1

113 27

TBT_D2R1 CC2

113 27

30 29

29

CRITICAL

D3300

NSR20F40NX_G

BI

IN

IN OUT OUT BI

31

BI

31

BI

30

BI

30

BI BI

IN

IN OUT OUT BI

VOLTAGE=20V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

USBC_XB_CC1

USBC_XB_R2D_C_N<1>

USBC_XB_R2D_C_P<1> USBC_XB_D2R_N<1> USBC_XB_D2R_P<1> USBC_XB_SBU2 USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P

USBC_XA_USB_DBG_BOT_N USBC_XA_USB_DBG_BOT_P

USBC_XA_SBU1

USBC_XA_R2D_C_P<2>

USBC_XA_R2D_C_N<2>

USBC_XA_D2R_P<2>

USBC_XA_D2R_N<2>

USBC_XA_CC2

PP20V_USBC_XA_VBUS PP20V_USBC_XA_VBUS_CONN

OMIT_TABLE

K

DSN2

A

C3304

1UF

10% 25V X5R 402

VOLTAGE=20V

29

GND_VOID=TRUE

D3354

DZ3301

5.5V-6.2PF

0201-THICKSTNCL

1

2

VOLTAGE=20V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

PP20V_USBC_XB_VBUS PP20V_USBC_XB_VBUS_CONN

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

GND_VOID=TRUE

1

C3373

GND_VOID=TRUE

C3372

GND_VOID=TRUE

2

ESD8011

1

D3327

XW3300

K

1610

ESDA25P35-1U1M

D3301

A

CRITICAL

D3370

DSN2

NSR20F40NX_G

C3391 C3390

ESD8011

D3349

1 2

GND_VOID=TRUE

2

1 2

DZ3350

X3DFN2-THICKSTNCL

10%

2

D3326

1

X3DFN2-THICKSTNCL

VOLTAGE=20V

SM

12

0201-THICKSTNCL

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

ESD8011

OMIT_TABLE

K

A

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

10%

2

C3354

1UF

10% 25V X5R 402

6.3V10% X5R-CERM 0201

6.3V

X5R-CERM

GND_VOID=TRUE

D3353

1

5.5V-6.2PF

USBC_XA_R2D_P<2>

0201X5R-CERM6.3V

USBC_XA_R2D_N<2>

X5R-CERM

GND_VOID=TRUE

ESD8011

D3325

X3DFN2-THICKSTNCL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

02016.3V

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

1

2

0201

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

ESD8011

D3324

X3DFN2-THICKSTNCL

BYPASS=J3300.59::2MM

CRITICAL

1

2

K

1610

ESDA25P35-1U1M

D3302

A

USBC_XB_R2D_N<1>

USBC_XB_R2D_P<1>

ESD8011

D3352

DZ3303

0201-THICKSTNCL

C3300

0.01UF

10% 25V X5R-CERM 0201

CRITICAL

1

C3306

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

XW3350

SM

12

GND_VOID=TRUE

2

ESD8011

D3351

X3DFN2-THICKSTNCL

GND_VOID=TRUE

2

ESD8011

5.5V-6.2PF

1

BYPASS=J3300.59::2MM

D3312

1

X3DFN2-THICKSTNCL

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

BYPASS=J3300.59::2MM

CRITICAL

1

C3301

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3307

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

2

1

2

1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

2

ESD8011

D3350

ESD8011

D3328

PLACE VBUS CAP NEAR EACH VBUS PIN

CRITICAL

1

C3302

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3308

0.01UF

10% 25V

2

X5R-CERM 0201

DZ3352

5.5V-6.2PF

X3DFN2-THICKSTNCL

0201-THICKSTNCL

BYPASS=J3300.59::2MM

1

BYPASS=J3300.59::2MM

CRITICAL

1

C3303

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3309

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

CRITICAL

1

C3312

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3305

0.01UF

10% 25V

2

X5R-CERM 0201

20759-056E-02

GND_VOID=TRUE GND_VOID=TRUE

J3300

F-ST-SM

57 58

PWR

SIGNAL

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

PWR

59 60

GND

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

TP_J3300_P2

GND_VOID=TRUE GND_VOID=TRUE

TP_J3300_P56

114

OUT

DZ3351

OUT

DZ3300

114

2

1

5.5V-6.2PF

0201-THICKSTNCL

BYPASS=J3300.58::2MM

CRITICAL

1

C3350

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

CRITICAL

1

C3356

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

GND_VOID=TRUE

2

ESD8011

1

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

D3321

D3355

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

2

1

X3DFN2-THICKSTNCL

2

ESD8011

1

D3320

PP20V_USBC_XA_VBUS_CONN

BYPASS=J3300.58::2MM

CRITICAL

1

C3351

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3357

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

USBC_XB_R2D_N<2>

USBC_XB_R2D_P<2>

GND_VOID=TRUE

ESD8011

D3356

X3DFN2-THICKSTNCL

ESD8011

D3358

X3DFN2-THICKSTNCL

USBC_XA_R2D_P<1>

USBC_XA_R2D_N<1>

GND_VOID=TRUE

2

ESD8011

D3304

X3DFN2-THICKSTNCL

1

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.58::2MM

CRITICAL

1

C3352

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

CRITICAL

1

C3358

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

CRITICAL

1

C3353

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3359

0.01UF

10% 25V

2

X5R-CERM 0201

GND_VOID=TRUE

C3392

GND_VOID=TRUE

C3393

GND_VOID=TRUE

2

D3360

1

ESD8011

D3359

X3DFN2-THICKSTNCL

GND_VOID=TRUE

ESD8011

X3DFN2-THICKSTNCL

C3370

GND_VOID=TRUE

C3371

GND_VOID=TRUE

2

ESD8011

D3329

116 115 114 32

X3DFN2-THICKSTNCL

ESD8011

D3323

1

X3DFN2-THICKSTNCL

1 2

2

1

2

1

CRITICAL

1

2

1

1 2

D3322

BYPASS=J3300.58::2MM

CRITICAL

C3362

0.01UF

10% 25V X5R-CERM 0201

GND_VOID=TRUE

1

2

0.22UF

GND_VOID=TRUE

0.22UF

10% 6.3V

ESD8011

D3357

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

X5R-CERM

2

X3DFN2-THICKSTNCL

6.3V10% 0201

6.3V

1

5.5V-6.2PF

DZ3353

0201-THICKSTNCL

X5R-CERM

X5R-CERM10%

USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N

2

ESD8011

X3DFN2-THICKSTNCL

5.5V-6.2PF

DZ3302

1

0201-THICKSTNCL

C3355

0.01UF

10% 25V X5R-CERM 0201

USBC_XB_CC2 USBC_XB_R2D_C_N<2>

0201X5R-CERM6.3V10%

USBC_XB_R2D_C_P<2>

0201

USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N USBC_XB_D2R_N<2> USBC_XB_D2R_P<2>

USBC_XB_SBU1

USBC_XA_SBU2

USBC_XA_R2D_C_P<1>

USBC_XA_R2D_C_N<1>

0201

USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>

USBC_XA_CC1

IN

OUT OUT

BI

BI BI

BI

IN

OUT OUT

D

31 29

CC2

113 27

115 31

TBT_R2D1

USB2 TOP

TBT_D2R1

SBU1

113 27

31

113 27

C

30

115 30

113 27

30 29

SBU2

TBT_R2D0

USB2 BOT

TBT_D2R0 CC1

BI

BI BI

BI

B

A

2

CAP,CER,X5R,1UF,10%,25V,0402

BOM_COST_GROUP=USB-C

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

C3304, C3354

CRITICAL

LAST CHANGE: Wed Apr 1 22:57:37 2015

PAGE TITLE

USB-C CONNECTOR A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

NOSTUFF138S0683

A

SYNC_DATE=03/30/2016SYNC_MASTER=X362_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

33 OF 145

SHEET

32 OF 121

8 7 5 4 2 1

36

345678

2 1

D

TBT X "POC" Power-up Reset

MAKE_BASE=TRUE

P3V3_TBT_X_SX_EN_R

NOSTUFF

R3400

0

1 2

MF-LF 1/16W

402

5%

D

C

30

31

P3V3_TBT_X_SX_EN_R

IN IN

P3V3_TBT_X_SX_EN_R

R3401

1 2

5%

1/20W

MF

201

1

R3404

100K

5% 1/20W MF 201

2

CRITICAL

U3400

SLG5AP1449V

0

P3V3_TBT_X_SX_EN

31

IN

USBC_X_RESET_L_R

1

ON

STDFN

GND

4

2

D

3

S

PP3V3_S5

110 116

PP3V3_S5_TBT_X_SW PP3V3_S5_TBT_X_SW PP3V3_S5_TBT_X_SW

1

R3402

100K

1% 1/20W MF 201

2

MAKE_BASE=TRUE

USBC_X_RESET_L_R TBTXPOCRST_SNS TBTXPOCRST_CT

1

R3403

24.9K

1% 1/20W MF 201

2

CRITICAL

TPS3895ADRY

1 3

SENSE

6

VCC

U3401

USON

SENSE_OUTENABLE

CT

GND

2

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

U3401

Output

Delay

Vth

4

USBC_X_RESET_L

5

Push-pull

440us +/- 20us

2.508V nominal

C3400

100PF

5% 25V C0G

0201

28 29

27

1

2

OUT

C

29 27

B

NOSTUFF

R3431

10K

1 2

5%

1/20W

MF

201

D3400

SC2

AK

DSF01S30SCAP

1

C3431

1.0UF

20%

6.3V

2

X5R 0201-1

NOSTUFF

B

A

DESIGN: X502/DEV_MLB_U

LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_MASTER=X362_MLB

PAGE TITLE

USB-C CONNECTOR B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

.

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/29/2016

051-00647

10.0.0 dvt-fab10 34 OF 145 33 OF 121

A

D

345678

2 1

D

PP5V_S4_X_USBC

29 34 116

2

XW3501

P5VUSBCX_RTN_DIV_R P5VUSBCX_SENSE_DIV_R

R3503

NO_XNET_CONNECTION=1

SM

27.4K

0.1%

1/20W

MF

0201

1

2

XW3502

SM

1

R3531

27.4K

0.1% 1/20W MF 0201

2

NO_XNET_CONNECTION=1

1

R3517

191K

0.1% 1/20W MF 0201

2

1

C3517

22PF

5% 50V

2

C0G 0201

PP5V_USBCX_VCC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=5V

1

C3522

2.2UF

10% 10V

2

X6S-CERM 0402

29

IN

PP5V_S4

108 110

R3501

UPC_X_5V_EN

P5VUSBCX_SENSE_DIV

P5VUSBCX_SREF P5VUSBCX_LL

P5VUSBCX_VO

P5VUSBCX_OCSET

NC

P5VUSBCX_RTN_DIV

P5VUSBCX_FSEL

10 7 12 11

14

4

13

EN FB SREF VO OCSET PGOOD RTN FSEL

1

2.2

5%

1/20W

MF

201

2

19

U3500

ISL95870AH

UTQFN

CRITICAL

PVCCVCC

20

BOOT

UGATE

PHASE

LGATE

1

C3521

10UF

20% 10V

2

X5R-CERM 0402-1

P5VUSBCX_VBST

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

1815 17 16 1

P5VUSBCX_DRVH_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE

P5VUSBCX_DRVL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

DIDT=TRUE

PPBUS_G3H

108 109 116

R3509

2.2

5%

1/20W

MF

201

P5VUSBCX_BOOT_RC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

1

2

C3516

0.1UF

10% 16V

2

X7R-CERM 0402

R3539

0

12

5%

1/20W

MF

0201

P5VUSBCX_DRVH

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

CRITICAL

C3504

33UF

20% 16V

TANT-POLY

CASE-B3

CRITICAL

Q3501

FDPC1012S

1

HSG

2

SW

3 4

1

2

LLP

CRITICAL

C3503

33UF

20% 16V

TANT-POLY

CASE-B3

V+

8

V+

9

LSG

7

CRITICAL

1

C3502

33UF

2

TANT-POLY

CASE-B3

1

20% 16V

2

CRITICAL

1

C3500

2.2UF

20% 25V

2

X5R-CERM 0402-1

L3500

1.5UH-20%-12.5A-0.017OHM

1 2

PIMB062D-SM

P5VUSBCX_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

C3501

2

NO_XNET_CONNECTION=1

P5VUSBCX_P

2.2UF

20% 25V X5R-CERM 0402-1

CRITICAL

R3530

0.002

1%

1/2W

MF

0306

1 2 3 4

C3505

2.2UF

20% 25V

X5R-CERM

0402-1

D

PP5V_S4_X_USBC

1

C3506

2.2UF

2

X5R-CERM

0402-1

20% 25V

1

2

1

C3509

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

1

C3508

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

29 34 116

1

C3507

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

C

1

C3526

10PF

5% 50V

2

C0G 0201

1

R3504

10K

0.1% 1/20W MF 0201-1

2

1

R3502

10K

0.1% 1/20W MF 0201-1

2

C3523

1

C3515

10PF

5% 50V

2

C0G 0201

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

R3518

95.3K

0.1% 1/20W MF 0201

2

P5VUSBCX_SET_R

NOSTUFF

R3513

5%

1/20W

MF

201

1

0

2

P5VUSBCX_SET0

P5VUSBCX_SET1

R3500

11K

1 2

1%

1/20W

MF

201

P5VUSBCX_AGND

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

8

SET0

9

SET1

6

VID0

5

VID1

3

XW3500

SM

1 2

PLACE_NEAR=U3500.2:1mm

GND

5

GND

6

GND

10

P5VUSBCX_N

Vout = 5.23V

1%

1/20W

MF

201

1

NO_XNET_CONNECTION=1

C3570

2

2200PF

12

10% 25V

CER-X7R

0201

1

R3572

2.74K

1% 1/20W MF 201

2

Freq = 500 kHz Max OCP = 13.9A

Nom OCP = 11.6A Min OCP = 9.37A

C

R3521

2.74K

PGNDGND

2

B

A

SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN SYNC_DATE=12/04/2015

PAGE TITLE

TBT 5V REGULATOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 35 OF 145 34 OF 121

A

D

345678

2 1

D

C

B

A

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196

U3730

LBEE5UQ1HG-844

LGA

SYM 2 OF 2

THRM_PADTHRM_PAD

197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292

PP3V3_S4_BT

MAKE_BASE=TRUE

PP3V3_S4_BT

35

1

C3761

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

SROM_STRAPS

PP3V3_S4_WLAN_SW

35

WLAN_STRAP_0

35

STRAP_0 HI:SROM (Default) STRAP_1 LO:16kb SROM

15

IN

35

WLAN SERIAL EEPROM

PP3V3_S4_WLAN_SW

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S4_WLAN_SW

35

1

C3763

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C3742

12PF

5% 25V

2

NP0-C0G 0201

1

C3740

12PF

5% 25V

2

NP0-C0G 0201

PP3V3_S4_BT

1

C3736

10UF

20%

6.3V

2

CERM-X5R 0402-4

35

1

C3762

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

36 35 110

FEM SUPPLY SHUNT CAPACITORS PLACE ON THE TOP SIDE CLOSE TO U3730

WLAN_STRAP_1

35

10K

5%

1/20W

MF

201

1

2

35

NOSTUFF

1

R3701

1K

5% 1/20W MF 201

2

1

GS

2

Q3701

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

1

R3759

270K

5% 1/20W MF 201

2

NOSTUFF

R3731

10K

1/20W

5% MF

201

1

2

R3734

PCH_BT_ROM_BOOT

BLUETOOTH SERIAL FLASH

PP3V3_S4_BT

35

100K

5%

1/20W

MF

201

1

R3753

100K

2

R3754

1K

1 2

5%

1/20W

MF

201

BT_SFLASH_HOLD_L

8

VCC

U3710

CAS93C86B

CS SK

PE

OMIT_TABLE

UDFN8

5

EPADGND

9

3 4 1 2

7

1

5%

1/20W

MF

201

2

BT_SFLASH_CS_L

BT_SFLASH_WP_L

DODI

6

ORG

WIFI_SROM_ORG

BT_SPI2_CLK

35

SPROM_DINSPROM_DOUT

R3712

10K

R3751

100K

1/20W

BT_SPI2_CSN

SPROM_CS

35

SPROM_CLK

35

5% MF

201

1

2

R3752

PP3V3_S4_WLAN_SW

35

NC

1

C3741

12PF

5% 25V

2

NP0-C0G 0201

WLAN_JTAG_SEL WLAN_EXT_POR_L

35

35 13

IN

6

SCLK

MX25L2006EZUI-12G

1

CS*

3

WP*

7

HOLD*

1

C3711

0.1UF

10% 35V

2

CER-X5R 0201

35 35

12

5% MF

201

PP3V3_S4_WLAN_SW

1

C3737

10UF

20%

6.3V

2

CERM-X5R 0402-4

WLAN_UART_RX WLAN_UART_TX

WLAN_JTAG_TDI

35

48 35

WLAN_JTAG_TMS WLAN_JTAG_TCK WLAN_JTAG_TRST_L

CORE2_5G_CTL2_WLAN_JTAG_TDO

WLAN_STRAP_0

35

WLAN_STRAP_1

SPROM_CLK SPROM_DOUT SPROM_CS SPROM_DIN

BT_SPI2_MOSI BT_SPI2_CSN BT_SPI2_MISO BT_SPI2_CLK

NC

BT_ROM_BOOT_L

35

BT_TIMESTAMP

8

VCC

OMIT_TABLE

U3750

2MBIT

USON

SI/SIO0

SO/SIO1

GND

THRM

PAD

4

9

113 36

5

2

35

1

C3738

10UF

20%

6.3V

2

CERM-X5R 0402-4

NC

BI BI BI BI BI BI

1

C3756

0.1UF

10% 35V

2

CER-X5R 0201

BT_SPI2_MOSI

BT_SPI2_MISO

FOR JTAG MODE REMOVE R3735

NO_XNET_CONNECTION=1

R3735

0

12

WLAN_1P2V_EN

5%

1/20W

MF

201

45

BT_RF1

50_G_0_MATCH 50_G_1_MATCH

50_G_2_MATCH

50_A_0_MATCH 50_A_1_MATCH

50_A_2_MATCH

35

47

2G_ANT_CORE0

63

2G_ANT_CORE1

78

2G_ANT_CORE2

61

5G_ANT_CORE0

74

5G_ANT_CORE1

85

5G_ANT_CORE2

22

WL_GPIO_6/UART_RX

23

WL_GPIO_7/UART_TX

93

WL_JTAG_TDI/GPIO_3

72

WL_JTAG_TMS

71

WL_JTAG_TCK

70

WL_JTAG_TRST*

94

WL_JTAG_SEL

21

WLAN_EXT_POR*

92

WL_JTAG_TDO

91

C0_FEMCTRL_2/STRAP_0

90

C2_FEMCTRL_2/STRAP_1

97

SPROM_CLK

98

SPROM_DOUT

99

SPROM_CS

100

SPROM_DIN

58

BT_SPI2_MOSI

59

BT_SPI2_CSN

65

BT_SPI2_MISO

66

BT_SPI2_CLK

29

BT_GPIO_2/BT_JTAG_TRST_N

28

BT_GPIO_3

27

BT_GPIO_4

GND

1

3

5

8

95

2

89

96

VDD3P3

1P2V_EN

VDD3P3_PAD

VDD3P3_REG1P2

LBEE5UQ1HG-844

GND

1114182026

CORE2_5G_CTL2_WLAN_JTAG_TDO

35

114 36 20 15

GND

3839404446485154606264676973757677798082838486

48 46 36

SMC_WIFI_PWR_EN

48 35

35

35 20

35 19

35

1

C3758

12PF

5% 25V

2

NP0-C0G 0201

PP3V3_S4_BT

88

68

81

55

VDD3P3_REG1P8

VDD3P3_FEM_CORE2

VDD3P3_FEM_CORE1

VDD3P3_FEM_CORE0

U3730

LGA

SYM 1 OF 2

GND

DEBUG CONNECTOR

WLAN_UART_TX WLAN_UART_RX

WLAN_JTAG_TCK WLAN_JTAG_TMS WLAN_JTAG_TDI

WLAN_JTAG_TRST_L WLAN_JTAG_SEL

AP_CLKREQ_L AP_RESET_L AP_PCIE_WAKE_L PP3V3_S4_WLAN_SW

1

C3757

12PF

5% 25V

2

NP0-C0G 0201

35

30

32

24

VDD_BT

BT_VDDIO

BT_OTP_VDD3P3V

BT_UART_CTS*/BT_JTAG_TMS

BT_UART_RTS*/BT_JTAG_TCK

BT_UART_TXD/BT_JTAG_TDO

BT_HOST_WAKE/BT_HOST_WAKE*

GND

WIFI_DBG

GND

J3701

AA25D-S038VA1

F-ST-SM

39 40

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

41 42

BT_LOW_PWR_L SMC_PME_S4_DARK_L SMC_BT_PWR_EN BT_UART_D2R BT_UART_R2D BT_UART_CTS_R2D_L BT_UART_RTS_D2R_L

BT_ROM_BOOT_L BT_TIMESTAMP BT_TIMESTAMP BT_SWDIO

BT_SWDCLK

SYSCLK_CLK32K_WIFIBT

PP3V3_S4_WLAN_SW

1

C3704

10UF

20%

6.3V

2

CERM-X5R 0402-4

19

WL_VDDIO

PCIE_RDP

PCIE_RDN

PCIE_TDP

PCIE_TDN PCIE_REFCLK_PC PCIE_REFCLK_NC

PCIE_WAKE_CL

PCIE_CLKREQ*

PCIE_PRST*

BT_RX_ACTIVE/BT_GPIO_5

BT_UART_RXD/BT_JTAG_TDI

BT_SWDIO

BT_SWDCLK

WL_XTAL32

BT_XTAL32

BT_DEV_WAKE

BT_PCM_SYNC

BT_PCM_IN

BT_PCM_OUT

BT_PCM_CLK

BT_RST*

BT_JTAG_SEL

GND

87

35

35 48

46 35

35

BT_SPI2_CLK BT_SPI2_CSN BT_SPI2_MISO BT_SPI2_MOSI

35

BT_ROM_BOOT_L

35

BOM_COST_GROUP=WIRELESS

PP3V3_S4_WLAN_SW

1

C3705

0.1UF

10% 35V

2

CER-X5R 0201

C3739

10UF

20%

6.3V

CERM-X5R

0402-4

6

PCIE_AP_R2D_P

113

7

PCIE_AP_R2D_N

113

10

PCIE_AP_D2R_P

9

PCIE_AP_D2R_N

13

PCIE_CLK100M_AP_P

12

PCIE_CLK100M_AP_N

15

AP_PCIE_WAKE_L

16

AP_CLKREQ_L

17

AP_RESET_CONN_L

43

41

BT_UART_CTS_R2D_L

42

BT_UART_RTS_D2R_L

36

BT_UART_R2D

37

BT_UART_D2R

57

BT_SWDIO

56

BT_SWDCLK

4

WL_CLK32K

25

33

SMC_PME_S4_DARK_L

35

49

BT_I2S_SYNC

50

BT_I2S_R2D

52

BT_I2S_D2R

53

BT_I2S_CLK

31 34

SMC_BT_PWR_EN

NC

35 20

BT_RX_ACTIVE

BT_LOW_PWR_L

35

1

2

13

114 35 20 12

35

MAKE_BASE=TRUE

35 13

MAKE_BASE=TRUE

35

46 35

PP3V3_S4_BT

1

2

OUT OUT

IN IN

OUT

BI

36

IN

35

15

35

C3701

0.1UF

10% 35V CER-X5R 0201

C3759

0.1UF

GND_VOID=TRUE GND_VOID=TRUE

113 14

113 12

35 19

35 20

10%

6.3V X7R

0201

R3762

GND_VOID=TRUE GND_VOID=TRUE

12

10K

5% MF

201

12

PP3V3_S4_WLAN_SW

Q3702

DMN32D2LFB4

1

GS

2

BT_LOW_PWR_L

MAKE_BASE=TRUE

DFN1006H4-3

SYM_VER_3

D

3

OUT

12

IN

BT UART TX & RTS ISOLATION CIRCUIT

R3764

0

1 2

5%

1/20W

MF

201

NO STUFF

35

IN

BT_UART_RTS_D2R_L

BT_UART_D2R PLT_RST_L

R3765

0

1 2

5%

1/20W

MF

201

NO STUFF

BT UART RX & CTS ISOLATION CIRCUIT

R3774

0

1 2

5%

1/20W

MF

201

NO STUFF

IN

IN IN

PCH_BT_UART_R2D PLT_RST_L

R3775

0

1 2

5%

1/20W

MF

201

NO STUFF

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

C3760

48 35

PP3V3_S4_WLAN_SW

PP3V3_S4_BT

1

C3703

0.1UF

10% 35V

2

CER-X5R 0201

1

C3702

0.1UF

10% 35V

2

CER-X5R 0201

0.1UF

12

10%

6.3V X7R

0201

BT_UART_CTS_R2D_L

35

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

R3766

100K

5%

1/20W

MF

201

IN

12

PP3V3_S4_BT

113 14

R3767

BT_UART_RTS_D2R_L

35

100K

1/20W

5% MF

201

12

R3776

BT_UART_R2D

35

36 35

BT_UART_D2R

35

2 1 5 7

PP3V3_S4

35 110

8

VCC

U3760

74LVC2G126

X2-DFN2010

1OE

A2

2OE

GND

4

PP3V3_S4

35 110

8

VCC

U3770

74LVC2G126

X2-DFN2010

1OE

A2

2OE

GND

4

CRITICAL

6

Y1A1

3

Y2

CRITICAL

6

Y1A1

3

Y2

100K

1/20W

R3777

100K

12

5% MF

201

MF

12

2011/20W

5%

SYSCLK_CLK32K_WIFIBT

1

C3764

0.1UF

10% 35V

2

CER-X5R 0201

PCH_BT_UART_CTS_L

PCH_BT_UART_D2R

1

C3774

0.1UF

10% 35V

2

CER-X5R 0201

BT_UART_CTS_R2D_LPCH_BT_UART_RTS_L

BT_UART_R2D

WIFI/BT: MODULE 1

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

37 OF 145

SHEET

35 OF 121

35

113 14

35

OUT

35

15

35 20

D

C

B

A

SYNC_DATE=04/29/2016SYNC_MASTER=X363_SAKKOC

8 7 5 4 2 1

36

D

WLAN Power Switch

1

VDD

U3840

SLG5AP1443V

WIFI_SW_CAP

7 3

CAP

TDFN

PP3V3_S4_WLAN

D

345678

2 1

CRITICAL

R3814

0

50_A_0_DIPLEXER

113

CORE0 DIPLEXER AND MATCHING

OMIT_TABLE

CRITICAL

J3810

20449-001E-03

110 36

F-ST-SM

2

3

1

50_0_ANT

113

CRITICAL

4

C3817

0.1PF

+/-0.05PF

25V C0G

0201

1

2

CRITICAL

R3810

0

1 2

5%

1/20W

MF

201

CRITICAL

1

C3816

0.1PF

+/-0.05PF 25V

2

C0G 0201

50_0_COM

113

U3810

DPX205950DT

SM

2

COM

GND

1

3

5

HI

LO

4 6

113

50_G_0_DIPLEXER

NO STUFF

C3815

0.2PF

+/-0.05PF

25V

COG-CERM

0201

NO STUFF

C3812

0.2PF

+/-0.05PF

25V

COG-CERM

0201

1

2

1

2

1 2

5%

1/20W

MF

201

CRITICAL

L3811

2.4NH+/-0.1NH-0.6A

1 2

0201

L3813

2.8NH-+/-0.1NH-0.6A-0.12OHM

50_A_0_MATCH

0201

1 2

50_G_0_MATCH

NO STUFF

1

C3810

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

113 35

D

113 35

C

48 46 36 35

SMC_WIFI_PWR_EN

Supervisor & CLKREQ# Isolation

1

C3841

4700PF

10% 10V

2

X7R 201

2 5

ON S

GND

8

PP3V3_S4_WLAN_SW

Delay = 130ms +/- 20%

36 35

CRITICAL

R3824

0

CORE1 DIPLEXER AND MATCHING

CRITICAL

J3820

20449-001E-03

F-ST-SM

2

3

4

1

113

50_1_ANT

CRITICAL

C3827

0.1PF

+/-0.05PF

25V C0G

0201

1

2

CRITICAL

R3820

0

1 2

5%

1/20W

MF

201

113

CRITICAL

1

C3826

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

50_1_COM

OMIT_TABLE

U3820

DPX205950DT

SM

2

COM

GND

3

5

LO

1

HI

1

2

1 2

5%

1/20W

MF

201

CRITICAL

50_A_1_DIPLEXER

113

CRITICAL

C3825

0.2PF

+/-0.05PF

25V

COG-CERM

0201

4 6

L3821

2.4NH+/-0.1NH-0.6A

50_G_1_DIPLEXER

113

NO STUFF

C3822

0.2PF

+/-0.05PF

25V

COG-CERM

0201

1 2

0201

1

2

50_A_1_MATCH

L3823

CRITICAL

2.4NH+/-0.1NH-0.6A

0201

1 2

50_G_1_MATCH

NO STUFF

1

C3820

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

113 35

C

113 35

B

35

OUT

AP_RESET_CONN_L

PP3V3_S4_WLAN_SW

36 35

WIFI_SAK:YES

R3859

0

1 2

5%

1/20W

MF

201

R3856

232K

1%

1/20W

MF

201

R3857

100K

5%

1/20W

MF

201

1

2

WLAN_3V3_VMON

AP_RESET_CONN_R_L

1

2

VDD

U3850

SLG4AP041V

TDFN

2

SENSE

4

RESET*

7

IN

VREF

THRM

PAD

9

+

-

PP3V3_S4_WLAN

1

2

1

DLY

3

MR*

6

EN

8

OUT

(OD)

GND

5

C3851

0.1UF

10% 25V X6S-CERM 0201

AP_RESET_L

SMC_WIFI_PWR_EN

NC

110 36

CRITICAL

R3834

0

113

CORE2 DIPLEXER AND MATCHING

CRITICAL

C3835

0.1PF

+/-0.05PF

OMIT_TABLE

CRITICAL

J3830

20449-001E-03

IN

48

46 36 35

IN

114 35 20 15

F-ST-SM

2

3

1

4

50_2_ANT

113

0.8NH-+/-0.05NH-1.1A-0.04OHM

NO STUFF

25V

0201

1

2

C3837

0.2PF

+/-0.05PF

COG-CERM

CRITICAL

L3830

1 2

0201

113

CRITICAL

1

C3836

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

50_2_COM

U3830

DPX205950DT

SM

2

COM

GND

1

3

5

HI

LO

4 6

113

25V C0G

0201

C3832

0.2PF

+/-0.05PF

25V

COG-CERM

0201

NO STUFF

1 2

5%

1/20W

1

2

MF

201

CRITICAL

L3831

2.4NH+/-0.1NH-0.6A

1 2

0201

1

2

L3833

CRITICAL

2.4NH+/-0.1NH-0.6A

0201

1 2

NO STUFF

1

C3830

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

50_A_2_MATCH50_A_2_DIPLEXER

50_G_2_MATCH50_G_2_DIPLEXER

113 35

B

A

WIFI_SAK:NO

R3854

0

1 2

5%

1/20W

MF

201

BOM_COST_GROUP=WIRELESS

8 7 5 4 2 1

36

PAGE TITLE

WIFI/BT: MODULE 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00647

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

D

10.0.0 dvt-fab10 38 OF 145 36 OF 121

A

345678

2 1

D

C

B

343S00136 SOC:HYNIX

1 U3900 CRITICAL

IC,M8+512MB 20NM DDR,A12,S,SCK,BGA700

L3900

120-OHM-0.1A-1.5-OHM

PP1V1_SLEEP1_SW2

41

unstuff R3951 and stuff R3952 to enable boundary scan

PP1V8_SLEEP2_SW3A

NOSTUFF

1K

5%

1/20W

R3952

R3951

MF

201

1 2

SOC_JTAG_SEL

10K

5%

1/20W

MF

201

1 2

M7 needed stronger PU but should be fixed on M8

PP1V8_AWAKE_SW3C

37 38 39 41

R3953

SOC_SWDIO

42 37

PP1V8_SLEEP2_SW3A

39 41

41 37

PMU_TO_SOC_RESET_L

1 2

41 40

37

NOSTUFF

1 2

R3973

0201

1K

5%

1/20W

MF

201

1 2

10K

5%

1/20W

MF

201

1

C3960

100PF

5% 25V

2

C0G 0201

32K CLK OPTION

PLACE_NEAR=U3900.AA22:3mm

R3990

0

41 20

41

IN

GREENCLK

PMU_TO_SOC_CLK_32K

SOC PMU

PP1V1_SLEEP1_SW2

41

R3901

1 2

5%

1/20W

MF

0201

R3925

1 2

1/20W

PLACE_NEAR=U3900.AA22:3mm

240

1%

1/20W

MF

201

1 2

SOC_CLK_32KSOC_PMU_CLK_32K

0

5% MF

0201

NOSTUFF

R3902

SOC_DDR_RREF

41 37

41

IN

SOC

240

1%

1/20W

MF

201

1 2

PMU_TO_SOC_SLEEP1_PWRGD PMU_TO_SOC_SYS_ALIVE

VOLTAGE=1.1V

1

C3900

0.22UF

10%

6.3V

2

X5R-CERM 0201

37 20

SOC_PAD_ZQ_A

NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC

PP1V1_SLEEP1_PLL_DDR_FILT

PP1V1_SLEEP3_BUCK2

41

L25

DDR0_CA_0

L26

DDR0_CA_1

N26

DDR0_CA_2

N27

DDR0_CA_3

P26

DDR0_CA_4

P25

DDR0_CA_5

M26

DDR0_CK_P

M27

DDR0_CK_N

M25

DDR0_CKE

L27

DDR0_CS

J26

DDR0_DMI_0

V27

DDR0_DMI_1

E26

DDR0_DQ_0

F26

DDR0_DQ_1

G26

DDR0_DQ_2

H26

DDR0_DQ_3

G27

DDR0_DQ_4

K25

DDR0_DQ_5

H27

DDR0_DQ_6

K26

DDR0_DQ_7

AA25

DDR0_DQ_8

Y25

DDR0_DQ_9

W25

DDR0_DQ_10

Y26

DDR0_DQ_11

V26

DDR0_DQ_12

U26

DDR0_DQ_13

T26

DDR0_DQ_14

T27

DDR0_DQ_15

E27

DDR0_DQS_P_0

F27

DDR0_DQS_N_0

W26

DDR0_DQS_P_1

W27

DDR0_DQS_N_1

R26

PAD_ZQ_A

M24

DDR0_RESET_N

N24

DDR0_RREF

L24

DDR0_RET_N

P24

DDR0_SYS_ALIVE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

N25

U21

SEP_ROM_WC

1

R3970

10K

5% 1/20W MF 201

2

39 37 38 41

PP1V8_AWAKE_SW3C

37 38 39 41

1

C3903

2

PP1V8_AWAKE_SW3C

SEP_I2C_SCL

0.1UF

10%

6.3V CERM-X5R 0201

T208

PLACE_NEAR=U3901.8:2mm

SEP ROM

8

VCC

U3901

M24128

EEPROM

VSS

MLP

THM_P

4

9

3

E2

2

E1

1

E0

7

WC*

6 5

SCL SDA

SEP_I2C_SDA

IC,RTM2,DEV,PN549A1,P61D0

IC,RTM2,MP,PN549A1,P61D0

R3900

499

PP1V8_SLEEP2_LPPLL_FILT

1

VOLTAGE=1.8V

BIIN

38 37 38 37

AA23

C3902

0.47UF

10%

6.3V

2

CERM-X5R 0201

1 2

1%

1/20W

MF

201

PP1V8_SLEEP2_SW3A

U3905

41

41 40 38 37

1

2

PP1V8_AWAKE_SW3C

1

C3918

1.0UF

20%

6.3V

2

X5R 0201-1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PP3V3_S0_LEFT110

C3919

4.7UF

20%

6.3V X5R 402

CRITICAL SE:DEV1338S00147 CRITICAL SE:PRODU39051338S00097

STOCKHOLM

NC

D3

B5

C7

C6

VDD

VBAT

SIM_PMU_VCC

G2

PVDD

E7

VUP

PP_STOCKHOLM_TVDD

PPVDD_STOCKHOLM

37

PPSVDD_STOCKHOLM

D7

B7

TVDD

AVDD

VOLTAGE=1.8V

C5

SVDD

ESE_VDD

1

C3916

0.1UF

2

VOLTAGE=1.8V

1

C3915

0.1UF

10%

6.3V

2

CERM-X5R 0201

10%

6.3V CERM-X5R 0201

VOLTAGE=1.8V

1

C3925

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

C3917

1.0UF

20%

6.3V X5R 0201-1

D

OMIT_TABLE

VDDIO11_PLL_DDR

VDDIO11_RET_DDR

OMIT_TABLE

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(1 OF 7)

AOP_PSENSE_CTRL_4 AOP_PSENSE_CTRL_5 AOP_PSENSE_CTRL_6 AOP_PSENSE_CTRL_7

AOP_PSPI_CS_TRIG_3 AOP_PSPI_CS_TRIG_4

DDR0

AOP_SWD_TCK_OUT

AOP_SWD_TMS0 AOP_SWD_TMS1

AOP_DETECT_0 AOP_DETECT_1

AOP_PDM_CLK AOP_PDM_DAT

AOP_PLED_0 AOP_PLED_1 AOP_PLED_2 AOP_PLED_3 AOP_PLED_4 AOP_PLED_5 AOP_PLED_6 AOP_PLED_7

AOP_PSPI_MISO AOP_PSPI_MOSI AOP_PSPI_SCLK

AOP_SPI0_MISO AOP_SPI0_MOSI

AOP_SPI0_SCLK

AOP_MON_0 AOP_MON_1 AOP_MON_2 AOP_MON_3 AOP_MON_4 AOP_MON_5 AOP_MON_6 AOP_MON_7

AOP_I2S0_MCK AOP_I2S1_MCK

AD26 AD27

AA10 AB10

AC10 Y10 AC14 AA13 AD12 AD13 AC15 AB14

AA24 W24 AA21 Y24

AD22 AD23

AD24 Y20 AB21

AC22 AC23 AD21

AE13 AE14 AB15 Y14 AE15 AD15 AA14 AC16

AA9 AB9

AE16 AD16 AB16

DFR_TOUCH_RESET_L

NC NC

NC NC NC NC

OUT

42 37

TP_SOC_CLKOUT

41 37

NC NC

NC NC NC NC

DFR_TOUCH_SPI_CS_L

NC

DFR_TOUCH_SPI_MISO DFR_TOUCH_SPI_MOSI DFR_TOUCH_SPI_CLK

NC NC NC

SOC_TO_STOCKHOLM_DWLD_REQ

PCH_SOC_DBELL_L

NC

IN

PMU_TO_SOC_IRQ_L

NC NC

41 38

NC

41

41 37

NC NC

NC NC NC

SOC_JTAG_SEL

37

42

114 42

BI IN

TP_SOC_JTAG_TRST_L

SOC_SWDIO

SOC_SWCLK TP_SOC_JTAG_TDI TP_SOC_JTAG_TDO

41 37

IN

OUT

OUT OUT

20 15

IN

OUT

IN

PMU_TO_SOC_RESET_L

IN

PMU_TO_SOC_SLEEP1_PWRGD

41

IN

37 20

SOC_SLEEP1_REQ

OUT

SOC_WDOG_RST

37

114 42

41

42

OUT

41

SOC_VDD_HI_LO

37

NC NC

SOC_CLK_32K

PMU_TO_SOC_AWAKE_PWRGD SOC_AWAKE_REQ PMU_TO_SOC_RESET_L

AB12

AB11

AC13 AD10

AD9

AA11

AE10

Y12

AB13

AE11

AE12

AC11 AC12

AA22

AB24

AD11

AA12

JTAG_SEL

JTAG_TRSTN

JTAG_TMS JTAG_TCK JTAG_TDI

M8-LPDDR4-H-A-FUSE

JTAG_TDO

CFSB_AOP

AOP_DDR_PWRGOOD

AOP_DDR_REQ

WDOG

SOC_VDD_HI_LO

AOP_DOCK_ATTENTION AOP_DOCK_CONNECT

RT_CLK32768

AWAKE_PWRGOOD AWAKE_REQ COLD_RESETN

I2C Pullups

VDD18_LPPLL

OMIT_TABLE

U3900

UFBGA

(2 OF 7)

AOP_LSPI_MISO AOP_LSPI_MOSI AOP_LSPI_SCLK

AOP_SPI_CS_TRIG_0 AOP_SPI_CS_TRIG_1 AOP_SPI_CS_TRIG_2 AOP_SPI_CS_TRIG_3 AOP_SPI_CS_TRIG_4 AOP_SPI_CS_TRIG_5 AOP_SPI_CS_TRIG_6 AOP_SPI_CS_TRIG_7 AOP_SPI_CS_TRIG_8

AOP_SPI_CS_TRIG_9 AOP_SPI_CS_TRIG_10 AOP_SPI_CS_TRIG_11 AOP_SPI_CS_TRIG_12 AOP_SPI_CS_TRIG_13 AOP_SPI_CS_TRIG_14 AOP_SPI_CS_TRIG_15

AOP_UART0_CTSN AOP_UART0_RTSN

AOP_UART0_RXD AOP_UART0_TXD

AOP_UART1_CTSN AOP_UART1_RTSN

AOP_UART1_RXD AOP_UART1_TXD

AOP_UART2_RXD AOP_UART2_TXD

AA20 AB22 AD25

AE20 AB17 AB18 AE21

MESA_PWR_EN

SOC_TO_STOCKHOLM_DEV_WAKE

SOC_SPI_BOOT_STATUS

AD19 AA17 AC19 AE22 AE23 AB19 AA18 AE24 AD20 AC21 Y18 AE25

AC17 AE18 AE17 AA15

AA16 AE19 AD17 AC18

AD18 Y16

NC NC NC

NC

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

NC NC

38

SOC_TO_STOCKHOLM_DWLD_REQ

37

UART_SOC_TO_STOCKHOLM_TXD

IN

OUT

UART_STOCKHOLM_TO_SOC_TXD UART_SOC_TO_STOCKHOLM_RTS_L

IN

UART_STOCKHOLM_TO_SOC_RTS_L

IN

R3943

78.7K

1%

1/20W

MF

201

45

37

1

R3941

10K

5% 1/20W MF 201

2

41 40 38 37

SOC_TO_STOCKHOLM_EN

1

2

37

1

R3942

10K

5% 1/20W MF 201

2

D1

NC

A5

NC

B2 A2

NC

A3

NC

C1 B1 D2

A1 E1

NC NC NC NC NC

NC

E3 E4

F4 B3 B4 E6

C3

PPSVDD_STOCKHOLM

PP1V8_AWAKE_SW3C

42

IN

38

SOC_ROM_SPI_RST_L

SOC_ROM_SPI_CLK_R

IN

SOC_ROM_SPI_CS_L SOC_ROM_SPI_WP_L

IRQ

PN66VEU3-A101D004

SVDD_REQ DWL CLK_REQ NFC_CLK_XTAL1 RX TX CTS RTS

VEN SMX_RST*

SMX_CLK

ESE_IO1 SPIM_MOSI SPIM_MISO SPIM_SCK

XTAL2

VSS

E2

4MB SPI ROM

1

C3920

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

C

1

S*

3

W*/VPP/DQ2

7

HOLD*/DQ3

U3905

UFLGA

AVSS

DVSS

F3

D4

D6

B6

8

VCC

U3906

4MX8-1.8V

UFDFPN

N25Q032A11E

SPIM_IRQ

SIM_SWIO

GPIO0

SPIM_NSS

TX_PWR_REQ

ESE_DWPM_DBG

ESE_DWPS_DBG

WKUP_REQ

VMID

SE2_PWR_REQ

SE2_SVDD_IN

DVSS

TVSS

PVSS

G4

C2

C4

OMIT_TABLE

DQ0

DQ1

F1

NC

A4

NC

A7

NC

A6

NC

D5

NC

G7

NC

G6

NC

F6

RXP RXN

TX1

TX2

5

2

NC

F5

NC

G3

NC

G5

NC

E5

SOC_TO_STOCKHOLM_DEV_WAKE

F7

PP_STOCKHOLM_VMID

VOLTAGE=1.8V

F2

NC

G1

NC

SOC_ROM_SPI_MOSI_R

SOC_ROM_SPI_MISO_R

1

C3926

0.1UF

10%

6.3V

2

CERM-X5R 0201

IN

OUT

42

37

C

B

THRM_PADVSS

PP1V8_AWAKE_SW3C

1

R3911

2.2K

5% 1/20W MF 201

2

1

R3912

2.2K

5% 1/20W MF 201

2

1

R3915

2.2K

5% 1/20W MF 201

2

1

R3916

2.2K

5% 1/20W MF 201

2

9

4

10

AOP_I2C0_SCL

AOP_I2C0_SDA

AOP_I2C1_SCL

AOP_I2C1_SDA

AB20 AE26

AE27 AA19

MESA_I2C_SCL

MESA_I2C_SDA

ALS_SCL_I2C_1V8 ALS_SDA_I2C_1V8

OUT

BI

OUT

BI

PP1V8_AWAKE_SW3C PP1V8_S0SW_DFR

114 45

42 37

1

R3904

2.2K

5% 1/20W MF 201

2

40 38 37 41 40 38 37 114 42 37

41

1

R3905

2.2K

5% 1/20W MF 201

2

A

38

IN

SOC_SPI_BOOT_STATUS

37

DFU_STATUS

SEP_I2C_SCL

SEP_I2C_SDA

1

2

R3960

3.0K

5% 1/20W MF 201

1

R3961

3.0K

5% 1/20W MF 201

2

R3981

0

1 2

5%

1/20W

MF

0201

R3980

0

1 2

5%

1/20W

MF

0201

T208 DFU_STATUS Isolation

37 38 42 109

DFU_SPI_STATUS

NOSTUFF

PP1V8_S0

DFU_STATUS can be driven high outside of S0 U3910 creates version that is only high in S0

74LVC2G08GT/S505

8

4

SOT833

PCH_SOC_DFU_STATUS

3

Y

5

6

A

B

U3910

08

15

OUT

SOC_WDOG_RST

37

PP1V8_S0

37 38 42 109

1

2

C3950

0.1UF

10%

6.3V CERM-X5R 0201

1

R3972

300K

5% 1/20W MF 201

2

T208 WDOG Isolation

SOC_WDOG_RESET can be driven high outside of S0

U3910 creates version that is only high in S0

74LVC2G08GT/S505

8

4

SOT833

7

Y

PCH_SOC_WDOG

1

2

A

B

U3910

08

1

R3971

100K

5% 1/20W MF 201

2

OUT

15

38 37

PP1V8_S0

42 109

ALS_SCL_I2C_1V8

42 37

ALS_SDA_I2C_1V8

42 37

8 7 5 4 2 1

SOC_PMU_I2C_SCL

41 38

SOC_PMU_I2C_SDA

109

114 76 38

PP1V8_S0

I2C_CAM_SCL

I2C_CAM_SDA

1

R3906

1K

5% 1/20W MF 201

2

114 42 38

42 38 41 38

114

42 37

1

R3907

1K

5% 1/20W MF 201

2

42 38

114 42 38

DFR_TOUCH_ROM_I2C_SCL

DFR_TOUCH_ROM_I2C_SDA

114

PP1V8_S0SW_DFR

DFRDRV_I2C_SCL

DFRDRV_I2C_SDA

1

R3917

4.7K

5% 1/20W MF 201

2

36

37

1

R3918

4.7K

5% 1/20W MF 201

2

335S00203

SOC_TO_STOCKHOLM_DWLD_REQ

BOM_COST_GROUP=T151

IC,FLASH,SERIAL,SPI,4MX8,4X3MM,DFN8

SYNC_MASTER=X363_SAKKOC

NOSTUFF

1

R3940

100K

5% 1/20W MF 201

2

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R

U39061

Camera/DFR 1

Apple Inc.

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

BOM OPTIONCRITICAL

051-00647

10.0.0 dvt-fab10 39 OF 145 37 OF 121

TABLE_5_HEAD

TABLE_5_ITEM

D

SYNC_DATE=04/29/2016

A

345678

2 1

D

C

B

PP1V8_AWAKE_SW3C

41

1

C4002

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V8_S4

42 109

38

SOC_BOOT:SPI

PP1V8_AWAKE_SW3C

37 38 39 41

1

R4023

100K

5% 1/20W MF 201

2

NOSTUFF

114 42 37

113

SOC_XTAL_24M_I

PP1V8_AWAKE_SW3C

37 38 39 41

PP1V1_SLEEP1_SW2

41

SOC_BOOT:DFU

1

R4035

47K

5% 1/20W MF 201

2

SOC_FORCE_DFU

41

IN

41 37

R4017

2.2K

1/20W

201

1 2

41 37

5% MF

OUT

BI

OUT

BI

114 42 37

PMU_TO_SOC_AWAKE_PWRGD

IN

SOC_BOOT_CONFIG_0

42

114 42

45

37

114 42

DFR_TOUCH_ROM_I2C_SCL

DFR_TOUCH_ROM_I2C_SDA

OUT

BI

42 39

1

C4001

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4000

0.1UF

10%

6.3V

2

CERM-X5R 0201

37

SOC_REQUEST_DFU1

38

SOC_REQUEST_DFU2

38

DFU_STATUS

OUT

PMU_TO_SOC_VDD_OK

TP_SOC_TST_CKOUT

DFR_CLKIN_RESET_L

NC NC

NC

NC NC

SOC_BOARD_ID_3 SOC_BOARD_REV_0 SOC_BOARD_REV_1 SOC_BOARD_REV_2

PP1V8_AWAKE_SW3C

DFR_DISP_RST_L

DFR_TOUCH_INT_L

MESA_SNSR_INT

SOC_TO_STOCKHOLM_EN

DFR_DISP_INT

NC NC

39

OUT

IN

OUT

IN IN IN IN IN

OUT

IN

SOC_PMU_I2C_SCL

SOC_PMU_I2C_SDA

DFRDRV_I2C_SCL DFRDRV_I2C_SDA

SOC_ROM_SPI_MISO SOC_ROM_SPI_MOSI

OUT

SOC_ROM_SPI_CLK

OUT

SOC_ROM_SPI_CS_L

OUT

MESA_SPI_MISO MESA_SPI_MOSI MESA_SPI_CLK

37

45

42

IN

IN OUT OUT

PP1V1_SLEEP1_SW2

41

P1

DFU_STATUS

F4

FORCE_DFU

E3

REQUEST_DFU1

D1

REQUEST_DFU2

R3

DROOP_N

D3

CFSB

C3

HOLD_RESET

T6

TST_CLKOUT

A3

TESTMODE

E2

CLK32K_OUT

C23

GPIO_0

F20

GPIO_1

C22

GPIO_2

E20

GPIO_3

D25

GPIO_4

C24

GPIO_5

D21

GPIO_6

C25

GPIO_7

E19

GPIO_8

D20

GPIO_9

C21

GPIO_10

A22

GPIO_11

B22

GPIO_12

B23

GPIO_13

D19

GPIO_14

F18

GPIO_15

C19

GPIO_16

B21

GPIO_17

B8

I2C0_SCL

C8

I2C0_SDA

A8

I2C1_SCL

D8

I2C1_SDA

E8

I2C2_0_SCL

B7

I2C2_0_SDA

C7

NC NC

NC

A7

E10 D10 B10 A10

A9 C9 B9 E9

AA8 AB8

I2C2_1_SCL I2C2_1_SDA

SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN

SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN

XI0 XO0

J12

H12

H10Y8J22

VDD11_UVD

J6

H3

J5

VDD30_USB

VDD18_USB

VDD18_TSADC

VDD11_PLL_SOC1

VDD11_PLL_SOC0

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(3 OF 7)

OMIT_TABLE

PP1V1_SLEEP1_XTAL_FILT

VDD11_XTAL

VDD_FIXED_USB

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

TMR32_PWM0 TMR32_PWM1 TMR32_PWM2

UART0_RXD

UART0_TXD

UART1_RTSN UART1_CTSN

UART1_RXD

UART1_TXD

UART2_RTSN UART2_CTSN

UART2_RXD

UART2_TXD

UART3_RTXD

UART4_RXD

UART4_TXD

UART5_RXD

UART5_TXD

I2S0_BCLK

I2S0_LRCK

I2S0_DIN

I2S0_DOUT

I2S1_BCLK

I2S1_LRCK

I2S1_DIN

I2S1_DOUT

I2S2_BCLK

I2S2_LRCK

I2S2_DIN

I2S2_DOUT

1

C4004

0.1UF

10%

6.3V

2

CERM-X5R 0201

120-OHM-0.2A-0.5-OHM

VOLTAGE=1.1V

1

C4050

0.22UF

10%

6.3V

2

X5R-CERM 0201

G1

USB_CAMERA_DFR_P

G2

USB_CAMERA_DFR_N

K6

SOC_USB_VBUS

J3 H4

SOC_USB_REXT

D18 E18 A23

A6

PCH_TO_SOC_UART_TXD

D7

SOC_TO_PCH_UART_TXD

D5 B3 C4

PCH_ALS_TO_SOC_UART_TXD

B4

SOC_TO_PCH_ALS_UART_TXD

E6 A4 B5 D6

UART_SOC_TO_STOCKHOLM_RTS_L UART_STOCKHOLM_TO_SOC_RTS_L

UART_STOCKHOLM_TO_SOC_TXD

UART_SOC_TO_STOCKHOLM_TXD

E7 A5

B6 C5 C6

B17 C15 E15 A17

C14 B16 E14 A16

B15 F14 D13 A15

NC

PLACE_NEAR=U3900.H4:2mm

NC NC

NC NC NC

NC NC NC NC

PP3V0_AWAKE_LDO7

38 41

1

C4005

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP0V8_SLEEP1_SW1

41

L4010

1 2

0201

BI

R4001

200

1 2

1/20W

201

NC NC NC

NC NC

BI

1% MF

113 14

To/From PCH for logging/debug

42

IN

42

OUT

To/From PCH for ALS

IN

OUT

42

1

C4003

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V1_SLEEP1_SW2

PP3V0_AWAKE_LDO7

1

R4022

10K

5% 1/20W MF 201

2

PLACE_NEAR=U3900.K1:2mm

37

OUT

37

IN

37

IN

37

OUT

PP1V8_AWAKE_SW3C

41

1

C4006

1.0UF

20%

6.3V

2

X5R 0201-1

41

38 41

PP3V3_S4_SOC_PMU

1

R4042

10K

5% 1/20W MF 201

2

NOSTUFF

R4003

4.02K

1 2

1%

1/20W

MF

201

SOC_MIPI1C_REXT

114 76 37

42 110

114 38

1

C4007

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIPIC_DATA_P MIPIC_DATA_N

MIPIC_CLK_P MIPIC_CLK_N

I2C_CAM_SDA

BI

OUT

I2C_CAM_SCL

NC NC

NC NC NC

NC NC

NC NC NC NC

NC NC

NC

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

CKPLUS_WAIVE=PWRTERM2GND

G24

G23

V23

U23

F24

VDD18_EFUSE5

VDD18_EFUSE4

VDD18_EFUSE2

VDD18_EFUSE1

VDD18_EFUSE3

M3

MIPI1C_DPDATA0

M2

MIPI1C_DNDATA0

L1

MIPI1C_DPCLK

L2

MIPI1C_DNCLK

K1

MIPI1C_REXT

B2

ISP0_SDA

A2

ISP0_SCL

D12

ENET_MDC

C12

ENET_MDIO

A12

RMII_CLK

A11

RMII_CRSDV

B11

RMII_RXD_0

F10

RMII_RXD_1

B12

RMII_RXER

E11

RMII_TXD_0

C10

RMII_TXD_1

C11

RMII_TXEN

B14

SD_CLKOUT

E13

SD_CMD_IO

A14

SD_DATA_IO_0

C13

SD_DATA_IO_1

F12

SD_DATA_IO_2

B13

SD_DATA_IO_3

A13

SDIO_IRQ

E12

WL_HOST_WAKE

B1

SWD_TMS2

F5

SWD_TMS3

C1

ANALOGMUX_OUT

H6

BB_HSIC_DATA

F2

BB_HSIC_STROBE

G3

F3

VDD12_HSIC

VDD18_EFUSE6

L4

G5

M4

K4

VDD18_MIPI

VDD_FIXED_HSIC

N4

VDD_FIXED_MIPI

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(4 OF 7)

OMIT_TABLE

PP0V8_SLEEP1_SW1

1

C4008

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V8_AWAKE_SW3C

G4

VDD18_AMUX

MIPI0D_DPDATA0

MIPI0D_DNDATA0

MIPI0D_DPCLK MIPI0D_DNCLK

MIPI0D_REXT

DISP_VSYNC

DISP_TE

NAND_CEN_0 NAND_CEN_1

NAND_ALE

NAND_CLE

NAND_REN

NAND_WEN

NAND_IO_0 NAND_IO_1 NAND_IO_2 NAND_IO_3 NAND_IO_4 NAND_IO_5 NAND_IO_6 NAND_IO_7

MON_0 MON_1 MON_2 MON_3 MON_4 MON_5 MON_6 MON_7

SEP_GPIO0 SEP_GPIO1

SEP_SPI0_MISO SEP_SPI0_MOSI SEP_SPI0_SCLK

SEP_I2C_SCL

SEP_I2C_SDA

H1 H2

J2 J1

K2

C2 D2

D17 B20

D15 C16

A20 A18

E16 A19 B18 D16 C17 A21 B19 E17

N3 P6 P4 P3 N2 P5 R4 P2

D24 E21

D22 F22 E24

E22 D23

37 38 39 41

1

2

MIPID_DATA_P MIPID_DATA_N

MIPID_CLK_P MIPID_CLK_N

SOC_MIPI0D_REXT

DFR_DISP_VSYNC

DFR_DISP_TE

SOC_NAND_CEN_0

DFR_TOUCH_PANEL_DETECT

DFR_TOUCH_GPIO2

DFR_TOUCH_ROM_WC

SOC_PANIC_L S2R_ACK_L SOC_PCH_DBELL_L

SEP_I2C_SCL SEP_I2C_SDA

41

PP1V8_AWAKE_SW3C

R4036

10K

5% 1/20W MF 201

114 42

PP1V8_AWAKE_SW3C

1

R4024

100K

5% 1/20W MF 201

2

114 42

15

20 15

MIPIC_DATA_P

MIPIC_DATA_N

MIPIC_CLK_P

NC NC

NC

NC NC NC NC NC NC NC NC

NC

38

NC

NC NC

NC NC NC

OUT

IN IN

114 38

BI

114 38

BI

OUT

37

BI BI

OUT OUT

BI

IN

38 114

41 40 38 37

PP1V8_AWAKE_SW3C

1

R4037

10K

5% 1/20W MF 201

2

SOC_REQUEST_DFU2SOC_REQUEST_DFU1

38 38

R4004

4.02K

1 2

1%

1/20W

MF

201

41 40 38 37

MIPIC FILTERING

L4002

3.25-OHM-0.1A-2.4GHZ

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

TAM0605-4SM

SYM_VER-1

1

2 3

L4003

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

1

PLACE_NEAR=U3900.K2:3mm

PLACE_NEAR=J8500:2.54mm

GND_VOID=TRUE

4

MIPI_DATA_CONN_P

MIPI_DATA_CONN_N

PLACE_NEAR=J8500:2.54mm

GND_VOID=TRUEGND_VOID=TRUE

4

MIPI_CLK_CONN_P

D

41 40 38 37

C

B

76

BI

76

BI

76

OUT

A

1

C4041

12PF

5% 50V

2

C0G-CERM 0201

R4010

499K

1 2

1%

1/20W

MF

201

113

SOC_XTAL_24M_O

Y4000

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

1 3

113

SOC_XTAL_24M_O_R

2 4

1

R4020

0.00

1% 1/20W MF 0201

2

1

C4040

12PF

5% 50V

2

C0G-CERM 0201

38 15

GND_VOID=TRUE GND_VOID=TRUE

114 38

MIPIC_CLK_N

2 3

MIPI_CLK_CONN_N

OUT

76

L4004

T208 SOC_S2R_ACK_L bi-directional Isolation

PP3V3_S0_LEFT

42 110

BI

PCH

NOSTUFF

1

R4080

200K

5% 1/20W MF 201

2

S

SYM_VER_1

Q4000 to act as bi-directional islation for SOC_S2R_ACK_L When in system S0 and M8 AWAKE, FET will be on & line will be pulled high Below S0, SOC_S2R_ACK_L will be low and FET will be open (isolated from M8 power rails) When M8 enters S2R, FET will be on, PP1V8_AWAKE_SW3C will turn off and SOC_S2R_ACK_L will be low

PP1V8_AWAKE_SW3C

1

G

D

3

Q4000

DMN32D2LFB4

DFN1006H4-3

1

R4082

10K

5% 1/20W MF 201

2

S2R_ACK_LSOC_S2R_ACK_L

T208

38

37 38 42 109

PP1V8_S0

1

C4080

0.1UF

10%

6.3V

2

CERM-X5R 0201

38

NOSTUFF

S2R_ACK_L

T208

T208 SOC_S2R_ACK_L Isolation (NOSTUFF)

NOSTUFF

6

2

B

U4080

1

A

NC

5

74LVC1G08FW5

DFN1010

4

Y

3

SOC_S2R_ACK_L

NC

OUT

PCH

115 110

PP5V_S0

T208 FORCE_DFU Isolation

PP1V8_S037 38 42 109

SOC_BOOT:DFU

38 15

15

PCH

1

R4070

47K

5% 1/20W MF 201

2

IN

PCH_SOC_FORCE_DFU

1

C4070

0.1UF

10%

6.3V

2

CERM-X5R 0201

2

B

1

A

NC

R4071

1 2

201

SOC_FORCE_DFU should be pulled up to S4 In the SOC_BOOT:DFU option

U4070 prevents it from leaking into PCH

SOC_BOOT:DFU

6

74LVC1G08FW5

DFN1010

U4070

3

5

4

Y

SOC_FORCE_DFU

0

5%

SOC_BOOT:SPI

1/20W

MF

BOM_COST_GROUP=T151

T208

38

SYNC_MASTER=X362_T208

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

FERR-120-OHM-1.5A

1 2

0402A

PP5V_S0_ALSCAM_F

VOLTAGE=5V

Camera/DFR 2

Apple Inc.

1

C4062

0.1UF

10% 10V

2

X5R-CERM 0201

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

40 OF 145

SHEET

38 OF 121

114 76

SYNC_DATE=03/22/2016

A

8 7 5 4 2 1

36

345678

2 1

U5

V5

U4

T4

D

C

B

A

PP1V1_SLEEP3_BUCK2

41

1

C4106

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V1_SLEEP1_SW2

41

1

C4116

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4119

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP0V8_SLEEP1_SW1

39 41

1

C4121

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

PP1V8_SLEEP2_SW3A

37 41

1

C4112

1.0UF

20%

6.3V

2

X5R 0201-1

PP1V8_AWAKE_SW3C

37 38 39 41

1

C4114

1.0UF

20%

6.3V

2

X5R 0201-1

1

PP0V8_SLEEP2_BUCK1

41

1

C4141

2

41

234

1.0UF

20%

6.3V X5R 0201-1

PP1V8_SLEEP3_BUCK3

1

C4100

1.0UF

20%

6.3V

2

X5R 0201-1

C4107

4.3UF

20%

4V

CER-X5R

0402

C4117

4.3UF

20%

4V

CER-X5R

0402

C4122

4.3UF

20%

4V

CER-X5R

0402

1

C4113

0.1UF

10%

6.3V

2

X5R 0201

1

C4115

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

2

1

2

234

1

234

C4142

2.2UF

20%

6.3V X5R-CERM 0201

C4101

0.1UF

10%

6.3V CERM-X5R 0201

C4108

4.3UF

20%

4V

CER-X5R

0402

C4118

4.3UF

20%

4V

CER-X5R

0402

C4123

4.3UF

20%

4V

CER-X5R

0402

A24 AC24 AC28

C27

VDD1

K28

N1

R28

A27 AC25 AC27

B24

J28

VDD2

K27

M1

M28

P28

T28

AB23

W12 W16 W18

Y13

VDDIO18_AOP

Y15

Y19

Y22

Y9

E5 F19 F21

F7

F9 G10 G12 G14 G16

AB25 AB26

M23

W10 W15 W19

M14 M18 M20 M22

W13

VDDIO18_GRP0

R5

VDDIO18_GRP1

H23

VDD18_FMON

B25 B26 D28

F28

H28

J23

K23

L23

VDDIO11_DDR

N23 P23 R23 R27

T23 U27 U28 Y28

VDD_SRAM_AON

Y21

L17

M8

N11

N5 P12 P14 P18 P20 P22

P8

T12 T14 T18 T20

T22 V13 V21

W9

Y23

M8-LPDDR4-H-A-FUSE

VDD_SRAM

U3900

UFBGA

(5 OF 7)

OMIT_TABLE

VDD_SOC

VDD_SOC_AON

VDD_SRAM

E4 F11 F15 G17 G19 G22 G6 G8 H14 H16 H18 H8 J15 J19 J21 J9 K10 K12 K16 K18 L13 L15 L19 L21 L5 L7 L9 M10 M12 M16 N13 N15 N17 N19 N21 N6 N9 P10 P16 R11 R13 R15 R17 R19 R21 R9 T10 T16 U11 U13 U15 U17 U19 U9 V10 V12 V22 W11 W23

V14 V16 V18 V20 W17 W21 Y11

F13 F17 F23 F6 F8 G11 G13 G15 G18 G21 G9 H17 H20 H22 J11 J13 J17 J7 K14 K20 K22 K5 K8 L11

1

C4102

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4109

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

234

1

234

PP0V6_SLEEP2_LDO0

PP0V8_SLEEP1_SW1

PP0V6_SLEEP1_BUCK0

1

C4103

4.3UF

20%

4V

CER-X5R

0402

234

1

C4110

4.3UF

20%

4V

CER-X5R

0402

1

C4120

0.1UF

10%

6.3V

2

CERM-X5R 0201

BOM GROUP BOM OPTIONS

234

41

T208_PROG:REV0 T208_PROG:REV1

T208_PROG:REV2 T208_PROG:REV3 T208_PROG:REV4 T208_PROG:REV5

C4104

4.3UF

20%

4V

CER-X5R

0402

C4111

4.3UF

20%

4V

CER-X5R

0402

A1 A25 A26 A28

AA1 AA26 AA27 AA28

AA4 AB27 AB28 AC20 AC26

AC9 AD14 AD28

AD5

AE1

AE28

B27

B28 C18 C20 C26 C28 D11 D14 D26 D27

D4 D9

E1 E23 E25 E28

F1 F16 F25

G20 G25 G28

G7 H11 H13 H15 H19 H21 H24 H25

H5

H7

H9

J10 J14 J16 J18 J20 J24 J25 J27

J4

J8 K11 K13 K15 K17 K19 K21 K24

K3 K7

K9 L10 L12 L14 L16 L18 L20

M8-LPDDR4-H-A-FUSE

VSS

U3900

UFBGA

(6 OF 7)

OMIT_TABLE

VSS

T208_CONFIG2_H,T208_CONFIG1_H,T208_CONFIG0_H

T208_CONFIG2_H,T208_CONFIG1_H T208_CONFIG2_H,T208_CONFIG0_H

T208_CONFIG2_H

T208_CONFIG1_H, T208_CONFIG0_H

T208_CONFIG1_H

L22 L28 L3 L6 L8 M11 M13 M15 M17 M19 M21 M5 M9 N10 N12 N14 N16 N18 N20 N22 N28 N8 P11 P13 P15 P17 P19 P21 P27 P9 R10 R12 R14 R16 R18 R20 R22 R24 R25 R8 T11 T13 T15 T17 T19 T21 T24 T25 T7 T9 U10 U12 U14 U16 U18 U20 U22 U24 U25 U6 U8 V11 V15 V17 V19 V24 V25 V28 V7 V9 W14 W20 W22 W28 W6 W8 Y17 Y27

CKPLUS_WAIVE=PWRTERM2GND

VDD12_MAR_LV

VDD12_MAR_HV

VDD12_MAR_PLL

OMIT_TABLE

CKPLUS_WAIVE=PWRTERM2GNDCKPLUS_WAIVE=PWRTERM2GND

CKPLUS_WAIVE=PWRTERM2GND

VDD12_MAR_BG

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

U3

(7 OF 7)

VSS_MXL

V3

W3

W4

MAR_VDD1V2_FORCE_PWM

Y3

AC8

CFSB_MAR

T2

MAX_RX_IP

T1

MAX_RX_IM

R1

MAX_RX_QP

R2

MAX_RX_QM

V1

MAX_TX_IP

V2

MAX_TX_IM

W1

MAX_TX_QP

W2

MAX_TX_QM

U1

MAX_TX_BTAP

U2

MAX_TX_BTAM

Y1

MAX_TX_WLETP

Y2

MAX_TX_WLETM

T3

MAX_FREF

T5

MAX_TEST_OUT

CKPLUS_WAIVE=PWRTERM2GND

M7

N7

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

R6

CKPLUS_WAIVE=PWRTERM2GND

R7

VDD_SOC_MAR

U7

CKPLUS_WAIVE=PWRTERM2GND

V4

CKPLUS_WAIVE=PWRTERM2GND

V6

CKPLUS_WAIVE=PWRTERM2GND

AA3

CKPLUS_WAIVE=PWRTERM2GND

M6

CKPLUS_WAIVE=PWRTERM2GND

P7

CKPLUS_WAIVE=PWRTERM2GND

T8

VDD_SRAM_MAR

CKPLUS_WAIVE=PWRTERM2GND

V8

CKPLUS_WAIVE=PWRTERM2GND

W5

CKPLUS_WAIVE=PWRTERM2GND

W7

CKPLUS_WAIVE=PWRTERM2GND

Y4

CKPLUS_WAIVE=PWRTERM2GND

Y5

CKPLUS_WAIVE=PWRTERM2GND

VDDIO18_MAR

Y6

CKPLUS_WAIVE=PWRTERM2GND

Y7

CKPLUS_WAIVE=PWRTERM2GND

T208 BOARD REV/BOARD ID

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

4. DISABLE PD AND ENABLE PU

PP1V8_AWAKE_SW3C

T208_CONFIG1_H

R4101

2.2K

5%

1/20W

MF

201

1 2

PP1V8_AWAKE_SW3C38 SOC_BOARD_REV_2

38

SOC_BOARD_REV_1

38

SOC_BOARD_REV_0

38

T208_CONFIG2_H

R4100

2.2K

5%

1/20W

MF

201

1 2

BOARD REV[3:0] MODE

1111 T208_Rev0 (X362 P0) 1110 T208_Rev1 (X363 P0) 1101 T208_Rev2 (X362 P1) 1100 T208_Rev3 (X362 P2) 1011 T208_Rev4 (X363 P2/X362 localEVT) 1010 T208_Rev5 (X363 EVT/X362 EVT1)

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM_COST_GROUP=T151

T208_CONFIG0_H

R4102

2.2K

5%

1/20W

MF

201

1 2

SYNC_MASTER=X362_T208 SYNC_DATE=04/25/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

ID_3 reserved for DEV

MAR_SYSALIVE

MAR_TX_THROTTLE_N

MAR_BT_RFIC_IRQ

MAR_WL_RFIC_IRQ MAR_RFIC_PDET_0

MAR_RFIC_PDET_1

MAR_VDD1V2_PWR_REQ

MAR_RF_SWITCH_CTRL_0 MAR_RF_SWITCH_CTRL_1 MAR_RF_SWITCH_CTRL_2

MAR_RFIC_EN

MAR_PA_EN

MAR_PA_CTRL

MAR_ETIC_GPIO_0 MAR_ETIC_GPIO_1

MAR_RFFE_SCLK

MAR_RFFE_SDATA

MAR_SPARE_0 MAR_SPARE_1 MAR_SPARE_2

MAR_SPI_CLK

MAR_SPI_CS MAR_SPI_DATA_0 MAR_SPI_DATA_1 MAR_SPI_DATA_2 MAR_SPI_DATA_3 MAR_SPI_DATA_4 MAR_SPI_DATA_5 MAR_SPI_DATA_6 MAR_SPI_DATA_7

MAR_COEX_UART_RXD

MAR_COEX_UART_TXD

37 38 39 41

PP1V8_AWAKE_SW3C

37 38 39 41

SOC_BOARD_ID_3

38

SOC_ROM_SPI_MISO

42 38

SOC_ROM_SPI_MOSI

42 38

SOC_ROM_SPI_CLK

42 38

BOARD ID[3:0] MODE

1XXX T202 DEV 0010 T208

Camera/DFR 3

Apple Inc.

R

AC6 AD2 AB1

AC1 AC2

AB2 AB3

AD1 AD8

AE7 AE9

AA7 AC7 AD7

AD6 AE8

AD3 AA5

AA2 AB4 AC3

AD4 AE2 AC4 AB5 AE3 AE4 AE5 AA6 AC5 AB6

AB7 AE6

NOSTUFF

1/20W

1 2

R4103

2.2K

5% MF

201

NOSTUFF

R4104

2.2K

5%

1/20W

MF

201

1 2

DRAWING NUMBER SIZE

1 2

R4105

2.2K

5%

1/20W

MF

201

051-00647

REVISION

NOSTUFF

R4106

2.2K

5%

1/20W

MF

201

1 2

D

10.0.0

BRANCH

dvt-fab10

PAGE

41 OF 145

SHEET

39 OF 121

D

C

B

A

8 7 5 4 2 1

36

Berkelium

345678

2 1

D

C

B

41 40

SW1_EXT_ON

40

PP0V8_SLEEP1_SW1

1 2 5 6 8

3

G

D

S

4 7

PP0V8_SLEEP2_BUCK1

Q4201

CSD58892Q2

SON2X2

PLACE_NEAR=U4200.M4:2mm

VOLTAGE=1.8V

PP1V8_ALWAYS_LDO9

1

C4227

0.22UF

20% 10V

2

CERM-X5R 0201

41 40

PLACE_NEAR=U4200.A7:2mm

40 41 110

PLACE_NEAR=U4200.E1:3mm

PP3V3_S4_SOC_PMU

PP3V3_S4_SOC_PMU40 41 110

1

C4219

2.2UF

20%

6.3V

2

X5R-CERM 0201

PLACE_NEAR=U4200.L8:2mm

C4220

2.2UF

20%

6.3V

X5R-CERM

0201

1

C4226

0.022UF

10%

6.3V

2

X5R-CERM 0201

1

2

PP0V6_SLEEP2_LDO0

41

PP3V3_S4_SOC_PMU40 41 110

CRITICAL

1

C4204

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4207

2

1

C4218

2.2UF

20%

6.3V

2

X5R-CERM 0201

PP3V0_AWAKE_LDO7

41

40 41 110

15UF

20%

6.3V CERM 0402

PP3V3_S4_SOC_PMU

PP0V8_SLEEP2_BUCK1

41 40

PP0V8_SLEEP1_SW1

41 40

PP3V3_S4_SOC_PMU40 41 110

CRITICAL

1

C4203

15UF

20%

6.3V

2

CERM 0402

PLACE_NEAR=U4200.K11:2mm

PP3V3_S4_SOC_PMU

40 41 110

PLACE_NEAR=U4200.F12:2mm

CRITICAL

1

C4205

15UF

20%

6.3V

2

CERM 0402

PLACE_NEAR=U4200.A2:2mm

NC

SW1_EXT_ON

40

NC NC NC NC

NC

NC NC NC

NC

CRITICAL

1

C4206

15UF

20%

6.3V

2

CERM 0402

C6

SW0_EXT

D7

SW1_EXT

E1

BB_LX1

G1

BB_LX2

J3

BB_FB

H1

BB_OUT

M4

VDD_HVLDO_237

N2

VDD_HVLDO_45

L8

VDD_HVLDO_RTC

L3

VDD_HVLDO_SW6

M5

LDO2_OUT

N4

LDO3_OUT

M1

LDO4_OUT

N3

LDO5_OUT

N5

LDO7_OUT

M2

SW4_OUT

M10

VDD_MAIN_LDO_16

M6

VDD_MAIN_LDO_8

M9

VDD_MAIN_LDO_9

N7

VDD_MAIN_LDO_AUX

CKPLUS_WAIVE=PWRTERM2GND

N10

LDO1_OUT

N9

LDO6_OUT

N6

LDO8_OUT

M8

LDO9_OUT

N8

AUX_PWR_OUT

B10

SW1_IN

A11

SW1_OUT

C10

LDO0_OUT

A7A8A2

VDD_MAIN_BUCK0

F12

G12

VDD_MAIN_BUCK1

VDD_MAIN_BUCK2

VDD_MAIN_BUCK4

VDD_MAIN_BUCK3

D1

K11

L11

M11

VDD_MAIN_BB

VDD_MAIN_CHG

U4200

D2346A1-OTP-CE

WLCSP

SYM 1 OF 2

NC

J1

VDD_MAIN_BBCORE

K3

L2

ACT_DIODE*

VDD_MAIN_SW4

NC

K12

L12

VBAT

NC

M12

VBAT

NC

K10

VBAT_S

BUCK0_LX

BUCK0_FB

BUCK1_LX

BUCK1_FB

BUCK2_LX

BUCK2_FB

BUCK3_LX

BUCK3_FB

A6

SOC_PMU_BUCK0_LX

C9

SOC_PMU_BUCK0_FB

A9

SOC_PMU_BUCK1_LX

D9

SOC_PMU_BUCK1_FB

A3

SOC_PMU_BUCK2_LX

C2

SOC_PMU_BUCK2_FB

E12

SOC_PMU_BUCK3_LX

D10

SOC_PMU_BUCK3_FB

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

PP3V3_S4_SOC_PMU

CRITICAL

Place same side as PMU

L4202

1.0UH-1.82A-0.203OHM

1 2

MCFK2012-SM

40

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4203

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4204

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4205

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

40 41 110

PLACE_NEAR=U4200.D1:2mm

CRITICAL

1

C4202

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4208

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4211

4.2UF

10% 16V

2

X5R-CERM 0402-1

CRITICAL

1

C4238

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C4234

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

1

C4235

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

1

C4209

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4231

4.2UF

10% 16V

2

X5R-CERM 0402-1

CRITICAL

1

C4239

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C4236

4.7UF

20%

6.3V

2

CER-X5R 0402

SOC_PMU_BUCK0_FB PP0V6_SLEEP1_BUCK0

40 41 40

SOC_PMU_BUCK1_FB

40

SOC_PMU_BUCK3_FB

40

PP0V6_SLEEP1_BUCK0

1

C4210

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C4230

2.2UF

20%

6.3V

2

X5R-CERM 0201

Mirror Capacitors in Layout

PP0V8_SLEEP2_BUCK1

CRITICAL

20%

6.3V CER-X5R 0402

1

2

1

C4233

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

Mirror Capacitors in Layout

CRITICAL

1

C4240

4.7UF

20%

6.3V

2

CER-X5R 0402

Mirror Capacitors in Layout

PP1V1_SLEEP3_BUCK2

1

C4241

4.7UF

2

PP1V8_SLEEP3_BUCK3

CRITICAL

1

C4237

4.7UF

20%

6.3V

2

CER-X5R 0402

C4232

4.7UF

20%

6.3V CER-X5R 0402

CRITICAL

FB for Bucks

R4200

0

1 2

5% 1/16W MF-LF

402

R4201

0

1 2

5% 1/16W MF-LF

402

R4202

0

1 2

5% 1/16W MF-LF

402

R4203

0

1 2

5% 1/16W MF-LF

402

41 40

VDD_SOC

501MA MAX

41 40

VDD_SRAM_AON VDD_SRAM VDD_SOC_AON

VDD_FIXED_MIPI VDD_FIXED_USB 300MA MAX

VDD2

41 40

VDDQ

VDD11_XTAL

460MA MAX

VDD1 VDD18_USB VDDIO18_GRP0

100MA MAX

PP0V8_SLEEP1_SW1

PP1V1_SLEEP3_BUCK2SOC_PMU_BUCK2_FB

PP1V8_SLEEP3_BUCK3

D

41 40

41 40 40

41 40

C

B

A

VOLTAGE=0.6V

1

C4228

2.2UF

20%

6.3V

2

X5R-CERM 0201

41 40

41

41 40

41 37

41 38 37

PP1V1_SLEEP3_BUCK2 PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3 PP1V8_SLEEP2_SW3A

NC

PP1V8_AWAKE_SW3C

NC NC

B1 C1

B12 B11

C11 C12

K1

L1

K2

SW2_IN SW2_OUT

SW3_IN SW3A_OUT

SW3B_OUT SW3C_OUT

SW5_IN SW5_OUT SW6_OUT

VSS1

B2

VSS2

B9

VSS3

C4

VSS3

C5

VSS4

E5

VSS4

E6

VSS4

H5

VSS4

H6

VSS4

F5

VSS4

F6

VSS4

G5

VSS4

G6

M3

VSS7

VSS6

M7

VSS8

G8

VSS8

H7

VSS8

H8

VSS8

E7

VSS8

F7

VSS8

F8

VSS8

A1

G7

VSS9

A12

BUCK4_LX

BUCK4_FB

VSS_BB VSS_BUCK0 VSS_BUCK1 VSS_BUCK2 VSS_BUCK3 VSS_BUCK4

VSS9

N1

N12

Not using Buck4

H12 J10

F1 A5 A10 A4 D12 J12

NC NC

Mirror Capacitors in Layout

BOM_COST_GROUP=T151

SYNC_MASTER=X362_T208 SYNC_DATE=01/27/2016

PAGE TITLE

Berkelium - 1

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

42 OF 145

SHEET

40 OF 121

D

A

8 7 5 4 2 1

36

D

C

B

NOSTUFF

1

C4300

100PF

5% 25V

2

C0G 0201

PMU_TCAL_GND

1

2

1 2

PMU_VREF

1

C4301

0.1UF

10% 16V

2

X5R-CERM 0201

PP1V8_SLEEP2_SW3A

R4305

10K

5% 1/20W MF 201

PMU_TO_SOC_SYS_ALIVE

PMU_TCAL_PWR

NOSTUFF

R4307

3.92K

1%

1/20W

MF

201

OMIT

XW4300

SHORT-8L-0.1MM-SM

1 2

PMU_IREF

R4308

200K

1 2

0.1%

1/20W

TF

0201

37 20

1

C4302

0.1UF

2

NC

SOC_PMU_CLK_32K

IN

41

PMU_VDD_RTC

10% 16V X5R-CERM 0201

41 37

PMU_VPUMP

1

C4303

0.01UF

10% 25V

2

X5R-CERM 0201

F4

CLK_32K_ALT

F3

CLK_32K_IN

L9

TCAL

L6

VREF

N11

IREF

J5

VDD_RTC_DIG

L7

VDD_RTC

D2

VPUMP

U4200

D2346A1-OTP-CE

WLCSP

SYM 2 OF 2

BB_FORCE_PWM

ACTIVE_REQUEST

ACTIVE_PWRGOOD

SLEEP1_REQUEST

SLEEP1_PWRGOOD

SOC_VDD_CORE_HI_LO

VSS8

E8

VSS8

J7

J8

K8

VSS8

K7

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

VBUS_DET*

SHDN RESET_IN1 RESET_IN2

INCKT_OTP

IRQ*

RESET*

VDD_OK

SYS_ALIVE

UWAKE*

BUTTON1 BUTTON2 BUTTON3

DBLCLICK_DET

GPIO1 GPIO2

GPI3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9

GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15

AMUX_IN1 AMUX_IN2 AMUX_IN3 AMUX_IN4

AMUX_OUT

NTC1 NTC2 NTC3 NTC4

TBAT

E3 E4 G3 G4

B4

K9 G2 H2 H3 B3

E11 B7 B8

D11 D6 E9 D5 E10 F2

H4 E2

D3 D4 C3

C7 B5 B6 C8 D8 F9 F10 F11 G9 G10 G11 H9 H10 H11 J11

K6 L4 J6 K5 L5

J9 J2 K4 J4 L10

SOC_PMU_I2C_SCL

SOC_PMU_I2C_SDA

SMBUS_SOC_PMU_BR_SCL

SMBUS_SOC_PMU_BR_SDA

BB_FORCE_PWM

PMU_SOC_VBUS_DET_L

SMC_SOCPMU_RESET SOC_PMU_INCKT_OTP

PMU_TO_SOC_IRQ_L PMU_TO_SOC_RESET_L PMU_TO_SOC_VDD_OK

PMU_TO_SOC_SYS_ALIVE

SOC_AWAKE_REQ

PMU_TO_SOC_AWAKE_PWRGD

SOC_SLEEP1_REQ

PMU_TO_SOC_SLEEP1_PWRGD

SOC_VDD_HI_LO

PMU_SOC_UWAKE_L

PMU_TO_SOC_CLK_32K

Berkelium - 2

41

37

OUT

38 37

BI

1 2

R4321

41

37

OUT

37

OUT

38

OUT

IN

OUT

37

IN

37

38 37

37

OUT

R4320

5%

MF

2011/20W

0

SMBUS_SOC_PMU_SCL

SMBUS_SOC_PMU_SDA

1/20W5% 201

41 37

38 37

37

0

MF

PMU_SOC_VBUS_DET_L

R4301

100K

1 2

5%

1/20W

MF

201

We can remove R4304 this once we verify grounding is ok

IN

41

NC NC

41

IN

41

NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

To T208, Device ID=0x3C, READ=0x79, WRITE-0x78

49

IN

49

BI

To SMC, Device ID=0x3C, READ=0x79, WRITE-0x78

R4302

100K

PP3V3_S4_SOC_PMU

5%

1/20W

MF

201

1 2

PMU_SOC_UWAKE_L

41

BB_FORCE_PWM

SOC_PMU_INCKT_OTP

40 110

41

R4303

R4315

0

5%

1/20W

MF

201

1 2

1/20W

1 2

100K

5% MF

201

345678

BUCK0

BUCK1

BUCK2

BUCK3

SW3C

LDO7

LDO0

SW1

SW2

SW3A

38

39 117

39

37

PP1V1_SLEEP3_BUCK2

39

37 39

PP0V6_SLEEP1_BUCK0

PP0V8_SLEEP2_BUCK1

PP0V6_SLEEP2_LDO0

PP0V8_SLEEP1_SW1

PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3

PP1V8_SLEEP2_SW3A

PP1V8_AWAKE_SW3C

PP3V0_AWAKE_LDO7

2 1

T208 POWER ALIASES

PP0V6_SLEEP1_BUCK0

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V8_SLEEP2_BUCK1

VOLTAGE=0.8V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V6_SLEEP2_LDO0

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V8_SLEEP1_SW1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V8_SLEEP1_SW1

PP1V1_SLEEP3_BUCK2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V1_SLEEP3_BUCK2

PP1V1_SLEEP1_SW2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V1_SLEEP1_SW2 PP1V1_SLEEP1_SW2 PP1V1_SLEEP1_SW2 PP1V1_SLEEP1_SW2

PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_SLEEP2_SW3A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V8_SLEEP2_SW3A

PP1V8_AWAKE_SW3C

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V8_AWAKE_SW3C

PP3V0_AWAKE_LDO7

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=3.0V

VOLTAGE=1.1V

VOLTAGE=1.8V

40

VOLTAGE=0.8V

40

39

40

37

38

37

40

40 37

37

41

40 38 37

38

37 38 39

40

D

38

C

B

A

46

SMC_SOCPMU_RESET

Signal Aliases

SMC_SOCPMU_RESET

41

MAKE_BASE=TRUE

BOM_COST_GROUP=T151

PAGE TITLE

Berkelium - 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

43 OF 145

SHEET

41 OF 121

A

SYNC_DATE=03/15/2016SYNC_MASTER=X362_T208

8 7 5 4 2 1

36

T208 Support

345678

2 1

D

PP1V8_S0SW_DFR

1

R4491

24K

5% 1/20W MF 201

2

BI

IN

114 42

38 37 114

114 37

IN BI IN

R4481

4.7K

5%

1/20W

MF

201

114 42 37

1

SMC_LID

SYM_VER_2

D

3

S G

2

Q4400

DMN32D2LFB4

DFN1006H4-3

114

DFR_TOUCH_LID DFR_TOUCH_GPIO2

DFR_TOUCH_SPI_CS_L

DFR_TOUCH_SPI_MOSI_R

DFR_TOUCH_ROM_I2C_SCL DFR_TOUCH_ROM_I2C_SDA

DFR_TOUCH_RESET_L

114 42 37

1

2

PP1V8_S0SW_DFR

PP5V_S0_T139

110

DFR Connectors

114 48 47 43

1

C4490

100PF

5% 25V

2

C0G 0201

114 42 37

DFR Touch Conn

J4402

AA07-S022VA1

F-ST-SM

24 23

12 34 56 78 910 1112 1314 1516 1718 1920 2122

25 26

114 42 37

DFR_TOUCH_PANEL_DETECT DFR_DISP_VSYNC

DFR_TOUCH_SPI_MISO_R DFR_TOUCH_SPI_CLK_R

DFR_TOUCH_INT_L DFR_CLKIN_RESET_L

DFR_TOUCH_ROM_WC

PP1V8_S0SW_DFR

114

42 37

R4480

10K

5%

1/20W

MF

201

PP1V8_S0SW_DFR

BI

OUT

114 42

IN

1

114 38

114 42 38

114 38

IN

114 38

NOSTUFF

2

76 42

IN

NOSTUFF

1

R4485

4.7K

5% 1/20W MF 201

2

P3V3S0SW_RAMP

1

2

DFR_DISP_PWR_EN

C4410

2200PF

10% 10V

X7R-CERM

0201

38

76

OUT

R4492

IN

114 38

100K

1/20W

201

DFR_DISP_RST_L

DFR_DISP_SMC_RST_L

1

109

5% MF

2

3.3V DFR Switch

1

VDD

U4405

SLG5AP1443V

7 3

CAP

2 5

ON S

TDFN

42

PP1V8_S037 38

1

C4403

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP3V3_S5_T139

1

2

D

EDP: 182mA

2

1

NC

6.3V 0201-1

R4490

1 2

5%

1/20W

B

U4406

A

NC

5

C4400

1.0UF

20% X5R

0

6

3

NOSTUFF

MF

201

74LVC1G08FW5

DFN1010

4

Y

R4400

42 110

PP3V3_S0SW_DFR

114

100K

5%

1/20W

MF

201

DFR Disp Conn

J4401

DF40PG(1.5)-26DS-04V(51)

42 38 114

114 38

1

2

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

OUT OUT

OUT

VOLTAGE=3.3V

DFR_DISP_VSYNC

DFR_DISP_TE

DFR_DISP_INT

DFR_DISP_RESET_L

114

10%

6.3V X5R

0201

1

2

C4470

0.1UF

F-ST-SM

GND

2728

12

34 56

78

910 1112

1314

1516 1718 1920 2122 2324

2526

2930

GND_VOID=TRUE

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

DFRDRV_I2C_SCL DFRDRV_I2C_SDA

VOLTAGE=1.8V

IN

BI

MIPID_CLK_CONN_P

MIPID_CLK_CONN_N

MIPID_DATA_CONN_P

MIPID_DATA_CONN_N

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

PP1V8_S0SW_DFR

1

114 38 37

PLACE_NEAR=J4401:5mm

2

GND_VOID=TRUE

C4471

1UF

10%

10V

X5R-CERM 0402

1

2

MIPID FILTERING

L4401

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

4

L4400

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

4

1

EDP: 32.6mA

OUT

C4401

1UF

10%

10V

X5R-CERM 0402

PLACE_NEAR=J4401:2.54mm

GND_VOID=TRUE

1

23

GND_VOID=TRUE

1

23

MIPID_CLK_P

GND_VOID=TRUE

MIPID_CLK_N

PLACE_NEAR=J4401:2.54mm

MIPID_DATA_P

GND_VOID=TRUEGND_VOID=TRUE

MIPID_DATA_N

U4404

NCP160AMX180

XDFN-COMBO

EPAD GND

5

2

IN

EN

4

3

DFR_DISP_PWR_EN

IN

114 38

PP3V3_S5_T139

IN

42 110

1

76 42

C4402

1UF

10%

10V

2

X5R-CERM 0402

D

C

B

15

GND

8

SWD DEBUG MUX

PP3V3_S4_SOC_PMU

38 42 110

9

SOC

37

OUT

BI

SOC_SWCLK

SOC_SWDIO

INT PU SOC 50k

IN

PCH_SWD_MUX_SEL

1

Y+

2

Y-

PI3USB102EZLE

10

VCC

U4408

TQFN

GND

3

OE*SEL

M+

M-

D+

D-

5 4

7 6

8

PLACE_NEAR=U4408:2mm

1

C4444

0.1UF

10%

6.3V

2

CERM-X5R 0201

SOC_XB_DBG1_1V8 SOC_XB_DBG2_1V8

SOC_SWD_CLK PCH_SWD_IO

(When SEL driven high)

ACE

(Default)

42

IN

15

BI

PCH

Bus

AP0 AP1

20 15

AP2_0 Tesla AOP0

Device

PMU Touch EEPROM

Mesa EEPROM AOP1 ALS SEP

M34128 EEPROM

Part

Type

R(on) @ 3.3V 19 mOhm Max

Current

T208 I2C Mapping

SLG5AP1443V

Load Switch

17 mOhm Typ

2.5A Max

7-bit Address

0011110 (0x3C) 1010000 (0x50) 1010100 (0x4C)

101000x (0x50/0x51)

0111001 (0x39) 1010001 (0x51)

U4405

8-bit Address

Read

Write

0x79 0x78 0xA1 0xA0 0x99 0x98

0xA1/A3 0xA0/A2

0x73 0x72 0xA3 0xA2

37

OUT

37

38

DFR_TOUCH_SPI_MISO

PLACE_NEAR=U3900.Y20:5mm

37

IN

PLACE_NEAR=U3900.AB21:5mm

IN

PLACE_NEAR=U3900.C9:5mm

IN

PLACE_NEAR=U3900.B9:5mm

IN

DFR_TOUCH_SPI_MOSI

DFR_TOUCH_SPI_CLK

MESA_SPI_MOSI

MESA_SPI_CLK

R4453

0

1 2

5%

1/20W

MF

201

R4455

0

1 2

5%

1/20W

MF

201

R4456

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=J4402.7:5mm

DFR_TOUCH_SPI_MISO_R

R4454

0

1 2

5%

1/20W

MF

201

DFR_TOUCH_SPI_MOSI_R

DFR_TOUCH_SPI_CLK_R

MESA_SPI_MOSI_R

R4457

0

1 2

5%

1/20W

MF

201

MESA_SPI_CLK_R

SPI TERM

114 42

OUT

39 38

114 42

39 38

45

OUT

114 42

39 38

PLACE_NEAR=U3900.B10:5mm

IN

45

SOC_ROM_SPI_MISO

PLACE_NEAR=U3900.D10:5mm

IN

SOC_ROM_SPI_MOSI

SOC_ROM_SPI_CLK

R4450

100

1 2

5%

1/20W

MF

201

R4452

0

1 2

5%

1/20W

MF

201

SOC_BOOT:SPI

PLACE_NEAR=U3906.2:5mm

SOC_ROM_SPI_MISO_R

R4451

0

1 2

5%

1/20W

MF

201

SOC_ROM_SPI_CLK_R

SOC_BOOT:SPI

SOC_ROM_SPI_MOSI_R

SOC_BOOT:SPI

37

IN

OUT

37

OUT

C

37

B

A

T208

37

ALS I2C

8

VCCVL

IO/VCC1 IO/VCC2

PP3V3_S0_LEFT110

1

C4451

0.1UF

10% 16V

2

X5R-CERM 0201

R4420

100

1/20W

201

MF

7

I2C_ALS_SCL_R

6

I2C_ALS_SDA_R

5%

1

R4421

100

1/20W

201 MF

2

5%

PP1V8_S0

37 109

1

C4450

0.1UF

10% 16V

2

X5R-CERM 0201

1 2

R4470

100K

5%

1/20W

MF

201

1

U4403

NLSX4402

ALS_SCL_I2C_1V8 I2C_ALS_SCL

BI

ALS_SDA_I2C_1V8

IN

SOC_ALS_LS_EN

2 3

5

IO/VL1 IO/VL2

EN

UDFN

GND

4

PP1V8_S037 38 42 109

R4440

47K

5%

1/20W

MF

201

1 2

PCH_TO_SOC_UART_TXD

PCH_ALS_TO_SOC_UART_TXD SOC_TO_PCH_ALS_UART_TXD

38

R4441

47K

1/20W

201

1 2

5% MF

OUT

R4471

1/20W

1 2

R4472

1K

5% MF

201

BI

38

R4442

47K

38

1 2

5%

1/20W

MF

201

IN

R4443

47K

5%

1/20W

114 76

IN

MF

201

1 2

38

OUT

1K

5%

1/20W

MF

201

1 2

ALS

76

OUT

I2C_ALS_SDA SOC_TO_PCH_UART_TXD

114

1

C4440

0.1UF

10% 16V

2

X5R-CERM 0201

SOC_UART_LS_EN

T208

T208 LEVEL SHIFTING

ALS/DEBUG UART

1 2

R4444

100K

5%

1/20W

MF

201

12

2 3 4 5

1

VL VCC

U4401

NLSX5014MU_G

EN IOLV[1] IOLV[2] IOLV[3] IOLV[4]

UQFN

GND

6

PP3V3_S0_LEFT

11

IOVCC[1] IOVCC[2] IOVCC[3] IOVCC[4]

10 9 8 7

1

C4441

0.1UF

10% 16V

2

X5R-CERM 0201

SOC_UART_R2D

SOC_UART_D2R ALS_SOC_UART_R2D ALS_SOC_UART_D2R

38 110

IN

OUT

PCH

IN

OUT

20

ACE SWD DBG

38 109

T208 SWD MUX ACE DBG

PP1V8_S4

1

C4460

0.1UF

10% 16V

2

X5R-CERM 0201

1 2

R4460

100K

5%

1/20W

MF

201

1

U4402

NLSX4402

SOC_XB_DBG1_1V8

42

SOC_XB_DBG2_1V8

42

SOC_SWD_LS_EN

2 3

5

IO/VL1 IO/VL2

EN

UDFN

GND

4

BOM_COST_GROUP=T151

PP3V3_S4_SOC_PMU

8

VCCVL

IO/VCC1 IO/VCC2

7 6

38 42 110

1

C4461

0.1UF

10% 16V

2

X5R-CERM 0201

MAKE_BASE=TRUE

SOC_SWCLK_DBG SOC_SWDIO_DBG

MAKE_BASE=TRUE

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SOC_SWCLK_DBG SOC_SWDIO_DBG

T208 Support

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 44 OF 145 42 OF 121

31

D

A

SYNC_DATE=06/30/2016SYNC_MASTER=X362_T208

8 7 5 4 2 1

36

KBD CONNECTOR

345678

TPAD CONNECTOR

2 1

D

C

114 43

115 114 56

43 110

48 109

114 43

110

114 43

GND_FAN

PP5V_S0_FAN_CONN

FAN_LT_TACH FAN_LT_PWM

PP5V_S0_KBD

PP3V3_G3H KBD_BLC_GSSOUT

KBD_BLC_GSLAT

PP3V3_S4 KBD_BLC_GSSIN KBD_BLC_XBLANK

J4500

DF40PC-40DS-0.4V-51

F-ST-SM

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

114 43

XW4500

SM

GND_FAN

VOLTAGE=0V

1 2

XW4502

PP5V_S0_FAN_CONN

VOLTAGE=5V

FAN_RT_TACH

FAN_RT_PWM

PP5V_S0_KBD

KBD_I2C_SDA KBD_INT_L KBD_I2C_SCL SMC_LSOC_RST_L

KBD_BLC_GSSCK

518S00177 (RCPT, 0.3A per pin) MATE WITH PLUG 516S00054

43 110

114 43

114 48

114 43

1 2

115 114 56

SM

PP5V_S0

56 110 117

114 13

110

TPAD_SPI_CLK

PP5V_S4

L4500

FERR-120-OHM-1.5A

0402A

C4500

0.1UF

10% 25V X5R 402

PPBUS_S4_HS_TPAD

109

1 2

1

2

1

2

R4510

0

5%

1/20W

MF

201

NOSTUFF

C4511

12PF

NP0-C0G

5%

25V

0201

1

2

VOLTAGE=5V

F4500

2.5A-16V-0.1OHM

1 2

1812

114 48 47 42

48

114 43

114 13

114 43

114 13

114 43 114 43

PP3V3_S4_TPAD

43 110

PP3V3_S0

43 110

SMC_VIBE_L

46

114

114 43

ACT_GND

PPVIN_S4_TPAD_FUSE

VOLTAGE=12.6V

DF40C-50DS-0.4V-51

SMC_LID SMC_PME_S4_WAKE_L

SMC_ACTUATOR_DISABLE_L

TPAD_SPI_INT_L_CONN

TPAD_SPI_MOSI TPAD_SPI_CS_L_CONN

TPAD_SPI_MISO TPAD_SPI_IF_EN_CONN TPAD_SPI_CLK_CONN PP5V_S4_TPAD_CONN

CRITICAL

J4501

F-ST-SM

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA KBD_INT_L KBD_I2C_SDA

KBD_I2C_SCL KBD_BLC_XBLANK

KBD_BLC_GSSIN

KBD_BLC_GSSOUT KBD_BLC_GSSCK

KBD_BLC_GSLAT

114 43

ACT_GND

VOLTAGE=0V

PPVIN_S4_TPAD_FUSE

49

114 43

XW4501

SM

1 2

114 43

D

C

B

516S00187, MATE WITH 516S00188

B

TRACKPAD ISOLATION GATES/FET

A

43 110

15

73 70 46 20 12

PP3V3_S4_TPAD

TPAD_SPI_IF_EN

PM_SLP_S4_L

1

C4520

0.1UF

10% 16V

2

X5R-CERM 0201

2

B

1

A

NC

R4520

6

U4520

NC

3

5

0

5%

1/20W

MF

201

NOSTUFF

74LVC1G08FW5

DFN1010

4

Y

12

TPAD_SPI_IF_EN_CONN

PP3V3_S4_TPAD

43 110

PP3V3_SUS

110

PP3V3_S4_TPAD

43 110

1

R4530

100K

PP3V3_S0

43 110

114 43

1

GS

2

Q4530

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

5% 1/20W MF 201

2

TPAD_SPI_CS_L_CONNTPAD_SPI_CS_L

114 43 13

TPAD_SPI_INT_L

15

1

C4540

0.1UF

10% 16V

2

X5R-CERM 0201

74LVC1G08GW

SOT353

4

5

Y

U4540

3

1

B

2

A

1

R4540

100K

5% 1/20W MF 201

2

TPAD_SPI_INT_L_CONN

114 43

R4531

0

12

5%

1/20W

MF

201

NOSTUFF

R4541

0

5%

1/20W

MF

201

NOSTUFF

12

SYNC_MASTER=X363_SAMANTHA SYNC_DATE=01/08/2016

A

PAGE TITLE

Connectors&ESD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=KEYBOARD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 45 OF 145 43 OF 121

D

345678

2 1

D

C

Debug Stuff Was Here

C

B

A

PAGE TITLE

External A USB3 Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=08/26/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0 dvt-fab10 47 OF 145 44 OF 121

A

D

MOJAVE 16V BOOST

345678

2 1

ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE

D

PP3V3_S4_T151

45 110

1

C4910

10UF

20%

6.3V

2

CERM-X5R 0402-9

PP3V3_S4_T151

45 110

45

MESA_BOOST_EN

L4901

1.0UH-0.4A-0.636OHM

1 2

NOSTUFF

R4915

0

1 2

5%

1/20W

MF

0201

0402

R4916

1 2

0

5%

1/20W

MF

0201

PP3V3_S4_MESA_SW

DIDT=TRUE VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200

MOJAVE_EN_M

B1 A2 B2

A3 C2

SW

VIN EN_M

EN_S LDOIN

U4900

LM3638

BGA

PGND

AGND

B3

A1

XW4900

SHORT-0201

1 2

VOUT

PMID

C3

C1

P16V0_AGND

PP16V0_MESA

VOLTAGE=17V

PP17V0_MOJAVE_LDOIN

1

C4923

2.2UF

20% 25V

2

X5R 0402-3

VOLTAGE=0V

1

C4924

2.2UF

20% 25V

2

X5R 0402-3

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=16V

1

C4925

2.2UF

20% 25V

2

X5R 0402-3

1

C4926

56PF

5% 25V

2

NP0-C0G 0201

EDP:12.5mA

45

42

38

IN

OUT

MESA_SPI_MISO

R4950

0

1 2

5%

1/20W

MF

0201

R4951

56

1 2

5%

1/20W

MF

201

R4912

0

1 2

5%

1/20W

MF

0201

PLACE_NEAR=J4900:3MM

MESA_SPI_MOSI_CONN

1

C4950

56PF

5% 25V

2

NP0-C0G 0201

MESA_SPI_CLK_CONNMESA_SPI_CLK_R

1

C4951

56PF

5% 25V

2

NP0-C0G 0201

1

C4952

56PF

5% 25V

2

NP0-C0G 0201

45 114

OUT

OUTIN

MESA_SNSR_INTMESA_SPI_MOSI_R

MESA_BOOST_EN

SMC_ONOFF_LMESA_SPI_MISO_CONN

R4953

680

1 2

5%

1/20W

MF

201

R4954

680

1 2

5%

1/20W

MF

201

R4911

0

1 2

5%

1/20W

MF

201

MESA_SNSR_INT_CONN

1

C4953

100PF

5% 25V

2

C0G 0201

MESA_BOOST_EN_CONN

1

C4954

100PF

5% 25V

2

C0G 0201

MENU_KEY_L

1

C4955

100PF

5% 25V

2

C0G 0201

114 45

D

114 45

C

3.0V MESA

Option to feed LDO from 5V in case of dropout issue

PP3V3_S4_T151

45 110

1

C4911

1UF

10% 10V

2

X5R-CERM 0402

PP1V8_MESA

45

FL4900

80-OHM-25%-500MA

PP16V0_MESA PP16V0_MESA_CONN

45 114 45

1 2

0201

1

C4927

100PF

5% 25V

2

C0G 0201

VOLTAGE=16V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000

MESA FLEX CONNECTOR

Proto1 Connector for X434/X435 Support

PLUG (516S00115) - X434/ X435 Jumper Recptacle (516S00203) - X362/X363 MLB

114 45

PP3V0_MESA_CONN

C

U4910

NCP160AMX300

4

IN

3

EN

XDFN-COMBO

EPADGND

5

2

OUT

1

PP3V0_MESA

1

C4916

1UF

10% 10V

2

X5R-CERM 0402

EDP:100mA

45

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200

VOLTAGE=3.0V

114 45

J4900

505066-1220

F-ST-SM

1314

12

MESA_SPI_MISO_CONN MESA_SNSR_INT_CONN MESA_BOOST_EN_CONN MESA_SPI_MOSI_CONN

114 45 37

MESA_I2C_SDA MESA_I2C_SCL

PP1V8_MESA_CONN

34 56 78

MENU_KEY_L

910 1112

MESA_SPI_CLK_CONN

PP16V0_MESA_CONN

114 45

45 114

114 45

B

1.8V MESA

PP3V3_S4_T151

45 110

1

C4912

1UF

10% 10V

2

X5R-CERM 0402

MESA_PWR_EN

U4920

LP5907SNX-1.825

4 1

VIN

3

EN

X2SON

2

VOUT

EPADGND

5

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000

PP1V8_MESA

1

C4914

1UF

10% 10V

2

X5R-CERM 0402

1

C4920

2.2UF

20%

6.3V

2

X5R-CERM 0201

EDP:1.5mA

45

1

C4921

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C4922

2.2UF

20%

6.3V

2

X5R-CERM 0201

FL4910

80-OHM-25%-500MA

1 2

0201

C4928

0.1UF

10% 16V

X5R-CERM

0201

1516

PP3V0_MESA_CONNPP3V0_MESA

VOLTAGE=3.0V

MIN_LINE_WIDTH=0.6000

1

C4929

100PF

2

5% 25V C0G

0201

1

2

MIN_NECK_WIDTH=0.1200

114 45 45

Mesa Power Sequencing Requirements

Power On: 1V8 -> 3V3 -> 16V0

B

PP1V8_MESA_CONN

1

R4920

2.2K

5% 1/20W MF 201

114 45 37 37

MESA_I2C_SCL

ININ

2

1

R4921

2

I2C pullups on same rail as EEPROM VCC

2.2K

5% 1/20W MF 201

114 45

A

FL4920

80-OHM-25%-500MA

PP1V8_MESA PP1V8_MESA_CONN

45 114 45

1

C4918

2.2UF

20%

6.3V

2

X5R-CERM 0201

1 2

0201

1

C4917

100PF

5% 25V

2

C0G 0201

VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000

114 45 37

MESA_I2C_SDA

BI

BOM_COST_GROUP=T151

SYNC_MASTER=X362_P49 SYNC_DATE=01/08/2016

PAGE TITLE

MESA

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

49 OF 145

SHEET

45 OF 121

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

114 48 47

103 48 47 29

B

70 20 12

114 101 89 76 73 70 27 20 12

73 70 43 20 12

73 20 12

114 48 47 45

48 36 35

89 12

12

89 12

20

12

114 49

49

48

114 49

48

114 49

56

47

48

114 48

89

48

19

48

47

48

70 47

48 47

114 43

48

103 29

48 47

48

BI BI BI

BI IN IN IN

BI

OUT

IN

OUT OUT

BI

OUT

IN

OUT

IN

OUT OUT

IN

BI

OUT BI OUT OUT

BI

OUT

IN IN IN IN

BI IN IN IN

IN IN IN IN IN IN IN IN

IN

OUT

IN

OUT

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK24M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ LPC_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

SMBUS_SMC_2_S4_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH SMC_TOPBLK_SWP_L SMC_SENSOR_PWR_EN

SMC_DEV_SUPPLY_L SMC_ACTUATOR_DISABLE_L SMC_GFX_SELF_THROTTLE TP_SYS_ONEWIRE SMC_CLK12M_EN SMC_PCH_SUSACK_L

CPU_PECI_R SMC_PECI_L

SMC_CHGR_INT_L NC_SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_PMIC_INT_L SMC_SENSOR_ALERT_L SMC_VIBE_L SMC_LID_LEFT

SMC_PCH_SUSWARN_L SMC_USBC_INT_L SMC_BC_ACOK PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L

SMC_DEBUGPRT2_RX_L SMC_DEBUGPRT2_TX_L

SMC_LID_RIGHT SMC_WIFI_PWR_EN

(OD) (OD)

(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD)

(IPU) (OD) (IPD)

(OD)

(IPD when sampling)

D10 B13 C11 A13 H10 C12

C13 G10 G11

F10

G12

B11

D13 D12

N4

L5

N10

K8 N9

M9

L9 L8

N5

M5

H13 H11

A12 B12

K4 A9

L12 M12 N13

L11

K3 K2

C6 C7

J10

H12

K6 J11 J12

K7

A7

L6

D2

D1

F1

M6

N6

L7

M7

N7

L3

K5

E13 E12

TM4EA231H6ZXRI

PL3 PL2 PL1 PL0 PM5 PL4 PL5 PM4 PM2 PM0 PM1 PK5

PB2/I2C0SCL PB3/I2C0SDA PA6 PA7 PF6 PF7 PG0 PG1 PG2 PG3 PG6 PG7

PM6 PM7 PK6 PK7 PN2 PN3

PN4 PN5 PN6 PN7 PH2 PH3

PJ7 PJ6

PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7

PQ0 PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 PQ7

PA0/U0RX PA1/U0TX

PL7 PL6

U5000

BGA

SYM 1 OF 2

OMIT_TABLE

PE3 PE2 PE1

PE0 PD7 PD6 PD5 PD4

PE5

PE4

PB4

PB5 PD3 PD2 PD1 PD0

PK0

PK1

PK2

PK3

PE7

PE6 PN1 PN0

PC7 PC6 PC4 PC5

PJ5 PJ4

PA2/SSI0CLK PA3/SSI0FSS

PA4/SSI0RX

PA5/SSI0TX

PB0

PB1

PB6

PB7

PF0

PF1

PF2

PF3

PF4

PF5

PG4 PG5

PH0 PH1

PH4 PH5 PH6 PH7

PJ0 PJ1 PJ2 PJ3

PM3

G4 G3 G2 G1 C2 C3 A1 A2 A3 B3 A4 B4 D4 D3 C1 B1 H4 H3 H1 H2 C4 C5 B5 A5

M1 N1 M3 M2 B6 A6

N2 N3 L4 M4

E11 D11 E3 E4

L10 N11 N12 M11 K10 M10

M8 N8

L2 L1

K1 J3 J2 J4

D8 A8 B8 C8

G13

SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_CPUGT_ISENSE SMC_CPU_ISENSE SMC_GPU_CORE_ISENSE SMC_GPU_CORE_VSENSE SMC_DDR1V2_ISENSE SMC_GPU_VDDCI_ISENSE SMC_GPU_VDDCI_VSENSE SMC_GPU_1V8_ISENSE SMC_GPU_FB_ISENSE SMC_SSDLIM_ISENSE SMC_GPU_FBIC_ISENSE SMC_GPU_HS_ISENSE SMC_CPUSA_ISENSESMBUS_SMC_2_S4_SCL SMC_CPUDDR_ISENSE SMC_CPUSA_VSENSE SMC_CPU_VSENSE SMC_CPUGT_VSENSE SMC_CPU_IMON_ISENSE SMC_CPUGT_IMON_ISENSE

CPU_PROCHOT_L SMC_VCCIO_CPU_DIV2 PM_THRMTRIP_L

SPI_DESCRIPTOR_OVERRIDE_L

CPU_CATERR_L SMC_BT_PWR_EN

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L PM_RSMRST_L SMC_GFX_PWR_LEVEL_L

(IPU)

NC_SPI_SMC_MISO NC_SPI_SMC_MOSI NC_SPI_SMC_CLK NC_SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

SMC_CBC_ON SMC_GFX_OVERTEMP

(IPD)

ALL_SYS_PWRGD SMC_THRMTRIP

PM_PWRBTN_L PM_SYSRST_L

(OD) (OD)

TCON_BKLT_PWM SMC_ADAPTER_EN

SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_SOCPMU_RESET TP_SMC_DEBUGPRT_EN_L

PM_BATLOW_L

OUT

OUT OUT OUT OUT

OUT

IN

BI

OUT OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

D

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

48

IN

IN IN IN

IN

IN IN

IN

65 47 6

47

48 47 13 6

19

6

35

73 70 47

12

47

114 47 29

115 73 18 12

48

73

114 73 12

64

89 48

73 70

47

48 18

115 18 12

48

47

48

41

48

103 29 12

PP3V3_G3H

BYPASS=U5000.E6::5MM

1

C5002

1.0UF

20%

6.3V

2

X5R 0201-1

47 76 109

BYPASS=U5000.E6::5MM

1

C5003

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.G8::5MM

1

C5007

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.F6::5MM

1

C5004

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.H6::5MM

1

C5008

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.F8::5MM

1

C5005

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.H7::5MM

1

C5009

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.G6::5MM

1

C5006

0.1UF

10% 10V

2

X5R-CERM 0201

1

R5002

1M

5% 1/20W MF 201

2

76 48

47

IN

BI

BUF_SMC_RESET_L

SMC_WIFI_EVENT_L SMC_WAKE_L NC_SMC_HIB_L

47

IN

SMC_CLK32K NC_SMC_XOSC1

19

IN

SYSCLK_CLK12M_SMC NC_SMC_OSC1

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V

BYPASS=U5000.D7::5MM

1

C5010

1.0UF

20%

6.3V

2

X5R 0201-1

BYPASS=U5000.H9::5MM

1

C5017

1.0UF

20%

6.3V

2

X5R 0201-1

L5001

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

U5000

TM4EA231H6ZXRI

BGA

SYM 2 OF 2

F11

RST*

(OD)

BYPASS=U5000.D7::5MM

1

C5015

0.1UF

10% 10V

2

X5R-CERM 0201

PK4

M13

WAKE*

L13

HIB*

K11

XOSC0

K12

XOSC1

F13

OSC0

F12

OSC1

K13

VBAT

E6

VDDS

E7

VDDS

F6

VDDS

F7

VDDS

F8

VDDS

G6

VDDS

G7

VDDS

G8

VDDS

H6

VDDS

H7

VDDS

D7

VDDC

H9

VDDC

J1

VDDC

J9

VDDC

J13

VDDC

BYPASS=U5000.H9::5MM

1

C5016

0.1UF

10% 10V

2

X5R-CERM 0201

OMIT_TABLE

PC0/SWCLK/TCK PC1/SWDIO/TMS

PC3/SWO/TDO

BYPASS=U5000.J9::5MM

1

2

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

PC2/TDI

NC

VDDA

VREFA+

VREFA-

GNDA GNDA

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

C5014

1.0UF

20%

6.3V X5R 0201-1

B9 C9 C10A11 B10

B7

F3

E1 E2

F2 F4

A10 D5 D6 D9 E5 E8 E9 E10 F5 F9 G5 G9 H5 H8 J5 J6 J7 J8 K9

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

NC

PP3V0_S5_AVREF_SMC

47

55 53 51 50 48 47

BYPASS=U5000.J1::5MM

1

C5012

0.1UF

10% 10V

2

X5R-CERM 0201

GND_SMC_AVSS

BYPASS=U5000.J9::5MM

1

C5013

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5001

0.1UF

10% 10V

2

X5R-CERM 0201

114 57 47

47

XW5000

PLACE_NEAR=U5000.A10:6MM

1

C5020

0.01UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.E1:F2:1MM

BYPASS=U5000.J13::5MM

1

2

BYPASS=U5000.E1:F2:1MM

C5011

0.1UF

10% 10V X5R-CERM 0201

SM

12

1

C5021

1.0UF

20%

6.3V

2

X5R 0201-1

C

B

A

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

NOTE: Unused pins have "SMC_Pxx" names. Unused

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

pins designed as outputs can be left floating, those designated as inputs require pull-ups.

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SMC

8 7 5 4 2 1

36

SMC

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 50 OF 145 46 OF 121

A

D

345678

2 1

D

PP3V3_G3H

109

C5165

1.0UF

20%

6.3V X5R

0201-1

SMC AVREF Supply

U5165

TS3330-COMBO

QFN

5

1

2

CRITICAL

IN

GND

4

OUT

NC0 NC1

NC2

NC3 NC4

8

1

NC

2

NC

3

NC

6

NC

7

NC

C5166

CERM-X5R

0402-1

10UF

20%

6.3V

PROCHOT/THRMTRIP Support PECI Support

PP1V0_S3

CRITICAL

R5158

100

PP3V0_S5_AVREF_SMC

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.0V

1

2

1

C5167

0.1UF

10% 10V

2

X5R-CERM 0201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V

46

55 53 51 50 48 46

65 46 6

48 46 13 6

BI

OUT

CPU_PROCHOT_L SMC_PROCHOT_L

PLACE_NEAR=Q5159.6:5MM

PLACE_NEAR=Q5159.3:5MM

1 2

1%

1/20W

MF

201

R5159

100

1 2

1%

1/20W

MF

201

DMN32D2LFB4

Q5159

6

1

DMN5L06VK-7

D

SOT563

VER 3

2

GS

46

IN

SMC_PECI_L

From SMC

SMC_PROCHOT CPU_PECI

46

IN

46 13 6

OUT BI

CPU_PECI_R

To SMC

SMC_THRMTRIP_LPM_THRMTRIP_L

Q5159

3

DMN5L06VK-7

D

SOT563

VER 3

PLACE_NEAR=Q5150.2:5MM

Q5150

DFN1006H4-3

SYM_VER_2

NOSTUFF

C5134

47PF

5% 25V C0G

0201

1

2

3

D

SG

2

1

R5151

330

5% 1/20W MF 201

2

R5134

33

1 2

5%

1/20W

MF

201

From/To CPU/PCH

47 110

D

C

B

46

Top-Block Swap

R5182

1/20W

SMC_TOPBLK_SWP_L

1K

5% MF

201

PP3V3_S0

1

2

R5183

1 2

1/20W

1K

5% MF

201

PCH_STRP_TOPBLK_SWP_L

110

5

4

GS

SMC_THRMTRIP

IN

47 46

C

SMC_BC_ACOK

MAKE_BASE=TRUE

48 47 46

R5112

22

12

PM_CLK32K_SUSCLK_R

1 2

5%

1/20W

MF

201

Place near CPU

15

OUTIN

SMC_CLK32K

46

OUTIN

PP1V0_S3

47 110

SMC_VCCIO_CPU_DIV2

46

1

R5197

100K

1% 1/20W MF 201

2

1

R5196

100K

1% 1/20W MF 201

2

PP3V3_G3H

46 76 109

PP3V3_S4

48 110

PP3V3_S0

110

B

114 48 46

103 48 46 29

46

70

46

114 48 46 45

48 46

114 48 43 42

114 46 29

114 57 46

46

114 57 46

48 47 46

46

47 46

46

73 70 46

SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_WIFI_EVENT_L SMC_PMIC_INT_L SMC_ONOFF_L SMC_SENSOR_ALERT_L SMC_LID

NOSTUFF

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BC_ACOK

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF

SMC_ADAPTER_EN SMC_THRMTRIP SMC_DELAYED_PWRGD SMC_PM_G2_EN

R5166 R5167 R5168 R5169 R5170 R5172 R5171

R5175 R5176 R5177 R5178 R5179 R5180 R5187 R5185 R5186 R5191 R5192

100K 100K 100K 100K

10K 10K

330K

20K 20K 10K 10K 10K

10K 100K 100K

1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

2011/20W5% MF 1/20W5% 201MF 1/20W

5% 201MF

MF 2015% 1/20W MF 2011/20W5% MF5% 1/20W

201 1/20W5% 201MF

1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% MF 201 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

5% 1/20W 201MF

2011/20W5% MF

5% 1/20W MF 201

2011/20W5% MF

A

SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN SYNC_DATE=11/19/2015

PAGE TITLE

SMC Shared Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SMC

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 51 OF 145 47 OF 121

A

D

345678

2 1

D

C

B

A

47 46 13 6

SMC12 ADC Assignments

46

OUT

SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_CPUGT_ISENSE SMC_CPU_ISENSE SMC_GPU_CORE_ISENSE SMC_GPU_CORE_VSENSE SMC_DDR1V2_ISENSE SMC_GPU_VDDCI_ISENSE SMC_GPU_VDDCI_VSENSE SMC_GPU_1V8_ISENSE SMC_GPU_FB_ISENSE SMC_SSDLIM_ISENSE SMC_GPU_FBIC_ISENSE SMC_GPU_HS_ISENSE SMC_CPUSA_ISENSE SMC_CPUDDR_ISENSE SMC_CPUSA_VSENSE SMC_CPU_VSENSE SMC_CPUGT_VSENSE SMC_CPU_IMON_ISENSE SMC_CPUGT_IMON_ISENSE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_CPUGT_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_GPU_CORE_ISENSE

MAKE_BASE=TRUE

SMC_GPU_CORE_VSENSE

MAKE_BASE=TRUE

SMC_DDR1V2_ISENSE

MAKE_BASE=TRUE

SMC_GPU_VDDCI_ISENSE

MAKE_BASE=TRUE

SMC_GPU_VDDCI_VSENSE

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

SMC_GPU_FB_ISENSE

MAKE_BASE=TRUE

SMC_SSDLIM_ISENSE

MAKE_BASE=TRUE

SMC_GPU_FBIC_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HS_ISENSE

MAKE_BASE=TRUE

SMC_CPUSA_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_CPUSA_VSENSE

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPUGT_VSENSE

MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

SMC_CPUGT_IMON_ISENSE

MAKE_BASE=TRUE

SMC12 Pin Assignments

SMC_GFX_PWR_LEVEL_L

46

TP_SYS_ONEWIRE

46

TP_SMC_DEBUGPRT_EN_L

46

NC_SMC_DP_HPD_L

46

OUT

46

46 12

OUT IN

PM_THRMTRIP_L

NC_SPI_SMC_MISO NC_SPI_SMC_MOSI

NC_SPI_SMC_CLK NC_SPI_SMC_CS_L

SMC_PCH_SUSWARN_L

MAKE_BASE=TRUE

SMC_PCH_SUSACK_L

MAKE_BASE=TRUE

48 46

46 18

47 46

114 46

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUE

PM_PWRBTN_L

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SCL

49

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

49

MAKE_BASE=TRUE

SMBUS_SMC_2_S4_SCL

49

MAKE_BASE=TRUE

SMBUS_SMC_2_S4_SDA

49

MAKE_BASE=TRUE

SMC_OOB1_D2R_L

46

MAKE_BASE=TRUE

SMC_OOB1_R2D_L

46

MAKE_BASE=TRUE

SMC_ACTUATOR_DISABLE_L

MAKE_BASE=TRUE

SMC_CHGR_INT_L

46

MAKE_BASE=TRUE

SMC_GFX_PWR_LEVEL_L

MAKE_BASE=TRUE

TP_SYS_ONEWIRE

MAKE_BASE=TRUE

TP_SMC_DEBUGPRT_EN_L

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

CRITICAL

3

D

Q5290

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

S G

2

1

SMC_GFX_OVERTEMP

NC_SPI_SMC_MISO NC_SPI_SMC_MOSI

NC_SPI_SMC_CLK NC_SPI_SMC_CS_L

SMC_PCH_SUSWARN_L SMC_PCH_SUSACK_L

SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN

PM_PWRBTN_L

SMC_BC_ACOK

SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA

SMC_OOB1_D2R_L SMC_OOB1_R2D_L

SMC_ACTUATOR_DISABLE_L

SMC_CHGR_INT_L

12 46

OUTIN

89

IN

115

50

IN

50

IN

50

IN

50

IN

50

IN

53

IN

51

IN

55

IN

55

IN

51

IN

55

IN

55

IN

55

IN

55

IN

53

IN

55

IN

55

IN

53

IN

51

IN

53

IN

55

IN

55

IN

89 46

TRUE TRUE

74

50

12

64

50

46

77 80 114

43

64

Debug Power "Buttons"

PLACE_SIDE=TOP SILK_PART=PWR_BTN

R5226

RES

0603-NSP

13

SM

BOMOPTION=OMIT

12

24

SMC_ONOFF_L

OUT

Debug RESET "Buttons"

BOMOPTION=DBG_BTN

PLACE_SIDE=BOTTOM SILK_PART=RESET_BTN

CRITICAL

SW5227

SOX-152HNT

114 48 47 46 45

SM

1 2

SMC_RESET_L

OUT

114 76 64 57 29

Hall Effect Pads - Left

J5250

AMR-MLB-X502

SM

8 7 6

OMIT_TABLE

1 2 3 45

HALL_SENSOR_LEFT

PP3V3_G3H

NOSTUFF

48 109

C5250

1000PF

10% 16V

X7R-1

0201

1

2

R5252

10K

1 2

5%

1/20W

MF

201

SMC_LID_LEFT_R

48

D

BOMOPTION=DBG_BTN

SW5200

SILK_PART=PWR_BTN

PLACE_SIDE=BOTTOM

Hall Effect Pads - Right

EVQPUA02K

J5260

AMR-MLB-X502

100

5% MF

201

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

NOSTUFF

R5217

100

1 2

5%

1/20W

MF

201

R5214

100

1 2

5%

1/20W

MF

201

R5221

100

1 2

5%

1/20W

MF

201

R5211

100

1 2

5%

1/20W

MF

201

R5256

100K

5%

1/20W

MF

201

CPUTHRM_THRM:SMC

CPUTHRM_ALRT:SMC

TBTTHRM_THRM:SMC

TBTTHRM_ALRT:SMC

SMC_SENSOR_ALERT_L

BYPASS=U5256.5::5MM

1

2

5

1

2

SN74LVC1G02

SOT553-5

4

02

U5256

3

OUT

47 46

PP3V3_G3H

10% 10V

1

2

C5256

0.1UF

X5R-CERM

0201

SMC_4FINGERS_RST

OUT

Specify one of these BOM GROUPs.

BOM GROUP BOM OPTIONS

CPUTHRM:THRM CPUTHRM_THRM:SMC

Specify one of these BOM GROUPs.

BOM GROUP BOM OPTIONS

TBTTHRM:BOTH TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC

43 109

64

SMC_DEBUGPRT2_TX_L

46

Thermal Alerts

51

IN

54

IN

54

IN

54

55 51

55 53

54

SMC_CPUHI_COMP_ALERT_L

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

IN

TBTTHMSNS_X_THM_L

TBTTHMSNS_T_THM_L

IN

TBTTHMSNS_X_ALERT_L

TBTTHMSNS_T_ALERT_L

IN

114 48 47 46 45

114 43

R5216

1 2

1/20W

R5220

1 2

R5210

1 2

SMC_LSOC_RST_L

IN

SMC_ONOFF_L

IN

CRITICAL

S4 SMC Wake Sources

43

35

IN

SMC_PME_S4_WAKE_L

SMC_PME_S4_DARK_L

R5258

0

1 2

5%

1/20W

MF

LID_FEATURE_ON

201

SMC_LID_R

4

CRITICAL

SMC_LID_LEFT_R

48

SMC_LID_RIGHT

48 46

PP3V3_G3H

48 109

BYPASS=U5255.6::5MM

C5255

0.1UF

10% 10V

X5R-CERM

0201

1

2

U5255

6

2

1

NC

74LVC1G32

SOT891

35

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_LID_LEFT

1

R5257

0

5% 1/20W MF 201

2

LID_FEATURE_OFF

R5255

10K

1 2

5%

1/20W

MF

201

SMC_LID

OUT

46

OUT

114 47 46

103 47 46 29

114 47 43 42

46 36 35

48 46

SMC_WIFI_PWR_EN

SMC_SENSOR_PWR_EN

SM

8 7 6

OMIT_TABLE

1 2 3 45

HALL_SENSOR_RIGHT

PP3V3_G3H

NOSTUFF

48 109

C5260

1000PF

10% 16V

X7R-1

0201

1

2

R5253

10K

1 2

5%

1/20W

MF

201

SMC_LID_RIGHT

OUT

48 46

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMCCPUTHRM:BOTH

TABLE_BOMGROUP_ITEM

CPUTHRM_ALRT:SMCCPUTHRM:ALRT

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PUTBTTHRM:THRM

TABLE_BOMGROUP_ITEM

TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMCTBTTHRM:ALRT

TABLE_BOMGROUP_ITEM

TBTTHRM_THRM:PU,TBTTHRM_ALRT:PUTBTTHRM:NONE

PP3V3_S4

47 110

1

2

1

2

10K

1

R5273

10K

5% 1/20W MF 201

2

WLAN_UART_RX

WLAN_UART_TXSMC_DEBUGPRT2_RX_L

PP3V3_G3H

1

R5281

10K

5% 1/20W MF 201

2

SMC_DEBUGPRT2_R_TX

SMC_DEBUGPRT2_R_RX

1 2

1/20W

NOSTUFF

1 2

1/20W5% MF

NOSTUFF

2015% MF

201

1

TP-P6

1

TP-P6

35

35 46

109

A

TP5200

A

TP5201

B

PLACE_SIDE=BOTTOM

R5275

1 2

PLACE_SIDE=BOTTOM

R5277

0

1 2

5%

1/20W

MF

0201

PLACE_SIDE=BOTTOM

R5274

NOSTUFF

0

5%

1/20W

MF

0201

NOSTUFF

R5276

1 2

1/20W

0201

R5280

R5278

0

1 2

5%

1/20W

MF

0201

R5295 R5294

100K

1/20W

201

0

5% MF

100K

1/20W

201

5% MF

R5259

SMC_DEV_SUPPLY_L

46

C5257

3300PF

10% 10V

X7R-CERM

0201

NOSTUFF

1

2

0

1 2

5%

1/20W

MF

201

R5260

10

5%

1/20W

MF

201

SMC_DEV_SUPPLY_R_L

12

BKLT_PWM_TCON2MLBTCON_BKLT_PWM

114

114 76 46

NOSTUFF

C5270

1000PF

10% 16V

X7R-CERM

0201

BUF_SMC_RESET_L

1

2

GND_SMC_AVSS

76 46

55 53 51 50 47 46

BOM_COST_GROUP=SMC

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

SMC Project Support

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

52 OF 145

SHEET

48 OF 121

D

A

8 7 5 4 2 1

36

345678

2 1

D

LYNX POINT LP S0 "SMBus 0" Connections

LYNX POINT LP

U0500

(MASTER)

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_PCH_DATA

15

MAKE_BASE=TRUE

PP3V3_S0

49 110

R5300

1K

5%

1/20W

MF

201

SMC SMBus "0" S0 Connections

SMC SMBus "5" G3H Connections

Internal DP

PP3V3_S0

110

J8500

PP3V3_G3H

109

16 addresses

1

2

1

R5301

1K

5% 1/20W MF 201

2

114 46

SMC

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

R5350

1.5K

5%

1/20W

MF

201

1

R5381

2.0K

5% 1/20W MF 201

2

Battery Charger

ISL6259 - U7000

(Write: 0x12 Read: 0x13)(MASTER)

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

Battery

J6950

(Write: 0x16 Read: 0x17)

SMBUS_SMC_5_G3_SCL

63

64

D

2.0K

5%

1/20W

MF

201

1

2

1

2

1

R5351

1.5K

5% 1/20W MF 201

2

(Write: 0x20 Read: 0x21)

thru

(Write: 0x3E Read: 0x3F)

( when VRR_FLAG = 0 )

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

76 114

114 46 15

114 46

SMC

U5000U5000

(MASTER)

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

R5380

Banjo

U7800

(Write: 0x68 Read: 0x69)

70

SMBUS_SMC_5_G3_SCL

C

B

DPMUX IC

U9800

(MASTER)

NC_I2C_DPMUX_A_SCL

89

NC_I2C_DPMUX_A_SDA

89

DPMUX IC

U9800

(MASTER)

I2C_DPMUX_UC_SCL

89

I2C_DPMUX_UC_SDA

89

LYNX POINT LP S0 "SMLink 0" Connections

PP3V3_S0

89 98 110

DPMUX Connections

NC_I2C_DPMUX_A_SCL

MAKE_BASE=TRUE

NC_I2C_DPMUX_A_SDA

DPMUX Connections

R5305

2.0K

5%

1/20W

MF

201

1

2

1

R5306

2.0K

5% 1/20W MF 201

2

I2C_DPMUX_UC_SCL

MAKE_BASE=TRUE

I2C_DPMUX_UC_SDA

MAKE_BASE=TRUE

SMC

U5000

(MASTER)

SMBUS_SMC_2_S4_SCL

48

SMBUS_SMC_2_S4_SDA

48

SMC SMBus "2" S4 Connections

PP3V3_S4

110

Berkelium

R5370

1K

5%

1/20W

MF

201

MAKE_BASE=TRUE

SMBUS_SOC_PMU_SCL SMBUS_SOC_PMU_SDA

MAKE_BASE=TRUE

R5373

0

1 2

5%

1/20W

MF

0201

UGLY HACK

R5372

0

1 2

5%

1/20W

MF

0201

1K

5%

1/20W

MF

201

1

(Write: 0x78 Read: 0x79)

2

1

2

R5371

SMBUS_SOC_PMU_SCL

SMBUS_SOC_PMU_SDA

(Write: 0x10 Read: 0x11)

SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA

(Write: 0x14 Read: 0x15)

SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA

U4200

EADC1

U5700

EADC2

U5710

41

53

70

SMBUS_SMC_5_G3_SDA

SMC SMBus "3" S0 Connections

PP3V3_S0

110

SMC

U5000

(MASTER)

114 46

43

56

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

Trackpad

J4501

(Write: 0x99 Read: 0x98)

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

CARBON

U6000

(Write: 0xD5 Read: 0xD4)

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

PP3V3_G3H

109

SMBUS_SMC_5_G3_SDA

R5390

2.0K

5%

1/20W

MF

201

1

2

1

R5391

2.0K

5% 1/20W MF 201

2

(Write: 0x92 Read: 0x93)

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

(Write: 0x90 Read: 0x91)

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

(Write: 0x96 Read: 0x97)

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

SMC SMBUS "4" G3H CONNECTIONS

63

X100 Temp

TMP105: J9510

TBT & Airflow Left

TMP461: U5850

TBT & Airflow Right

TMP461: U5800

54

C

B

A

LYNX POINT LP

U0500

(MASTER)

SML_PCH_0_CLK

15

MAKE_BASE=TRUE

SML_PCH_0_DATA

15

MAKE_BASE=TRUE

LYNX POINT LP S0 "SMLink 1" Connections

LYNX POINT LP

U0500

(Write: 0x88 Read: 0x89)

SMBUS_SMC_1_S0_SCL

15

SMBUS_SMC_1_S0_SDA

15

SMLink 1 is slave port to access PCH.

PP3V3_S0

49 110

R5310

8.2K

5%

1/20W

MF

201

SMC SMBus "1" S0 Connections

SMC

1

2

1

R5311

8.2K

5% 1/20W MF 201

2

PP3V3_S0

110

SMC

U5000

(MASTER)

SMBUS_SMC_1_S0_SCL

46

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

46

MAKE_BASE=TRUE

GPU THERM

TMP442A: UA960

(Write: 0x98 Read: 0x99)

SMBUS_SMC_1_S0_SCL

100

SMBUS_SMC_1_S0_SDA

100

R5360

2.0K

5%

1/20W

MF

201

U5000

(MASTER)

1

2

1

R5361

2.0K

5% 1/20W MF 201

2

CPU, Mem, Airflow,

Fixstack Prox

TMP513AISAR:U5870

(Write: 0xB8 Read: 0xB9)

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

54

SMBUS_SMC_4_G3H_SCL

48

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

48

MAKE_BASE=TRUE

USB-C PORT CONTROLLER TA

CD3215A (ACE) - UB300

(WRITE: 0X40 READ: 0X41)

SMBUS_SMC_4_G3H_SCL

103

GPU

SMBUS_SMC_4_G3H_SDA

UA000

(Write: 0x82 Read: 0x83)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

99

103

USB-C PORT CONTROLLER TB

CD3215A (ACE) - UB400

(WRITE: 0X4E READ: 0X4F)

SMBUS_SMC_4_G3H_SCL

103

SMBUS_SMC_4_G3H_SDA

103

BOM_COST_GROUP=SMC

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

R5320

1.5K

1/20W

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

5% MF

201

1

2

1

R5321

1.5K

5% 1/20W MF 201

2

USB-C PORT CONTROLLER XA

CD3215A (ACE) - U3100

(WRITE: 0X70 READ: 0X71)

SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA

USB-C PORT CONTROLLER XB

CD3215A (ACE) - U3200

(WRITE: 0X7E READ: 0X7F)

SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA

SMBus Connections

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

BRANCH

PAGE

SHEET

29

A

D

10.0.0 dvt-fab10 53 OF 145 49 OF 121

8 7 5 4 2 1

36

345678

2 1

D

C

B

109

109 117

CPU High Side Current Sense (IC0R)

Gain: 100x, EDP: 16.8 A Rsense: 0.001 (R5400) Vsense: 16.8 mV, Range: 30 A

(PRODUCTION)

PPBUS_HS_CPU

52

0.001

R5400

CRITICAL

PPBUS_G3H

0612 MF-3

1W 1%

PLACE_NEAR=U5400.5:10MM

123

ISNS_HS_COMPUTING_N

ISNS_HS_COMPUTING_P

4

PLACE_NEAR=U5400.4:10MM

PP3V3_S0_LEFT

110

3

V+

U5400

5

IN-

4

INA214

SC70

CRITICAL

100x

GND

2

OUT

6

1

REFIN+

OTHER 5V High Side Current Sense (IO5R)

Gain: 200x, EDP: 1.22 A Rsense: 0.01 (R5410) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 12.2 mV, Range: 1.5 A

50 110

SMC ADC:7

6

V+

PPBUS_G3H

PPBUS_HS_OTH5V

OMIT

R5410

0.005

1%

1/3W

0306-SHORT

MF

PLACE_NEAR=U5410.2:3:10MM

1

ISNS_HS_OTHER5V_P

234

ISNS_HS_OTHER5V_N

PLACE_NEAR=U5410.4:5:10MM

2

IN+

3

IN+

4

IN-

5

IN-

U5410

INA210A

UQFN

CRITICAL

OTHERISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

NC NC

OTHER 3.3V High Side Current Sense (IO3R)

Gain: 200x, EDP: 4.31 A Rsense: 0.003 (R5440) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 12.93 mV, Range: 5 A

50 110

SMC ADC:8

6

V+

PPBUS_G3H

PPBUS_HS_OTH3V3

OMIT

R5440

0.005

1%

1/3W

0306-SHORT

MF

PLACE_NEAR=U5440.2:3:10MM

1 3

2

ISNS_HS_OTHER3V3_P

ISNS_HS_OTHER3V3_N

4

PLACE_NEAR=U5440.4:5:10MM

2

IN+

3

IN+

4

IN-

5

IN-

U5440

INA210A

UQFN

CRITICAL

OTHERISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

NC NC

LCD Backlight Current Sense (IBLR)

Gain: 100x. EDP: 0.87 A Rsense: 0.025 (R8400) Vsense: 21.75 mV, Range: 1.32 A EADC1: CH0

75

IN

75

IN

52 55 110 50 51 53

PLACE_NEAR=R8400.4:5MM

ISNS_LCDBKLT_P ISNS_LCDBKLT_IOUT

ISNS_LCDBKLT_N

PLACE_NEAR=R8400.3:5MM

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5450

INA214A

UQFN

CRITICAL LOADISNS

100x

GND

9

OUT

REF

NC NC

10 8 1

7

LOADISNS

1

C5450

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U5450.6::5MM

1

R5455

NC NC

6.04K

1% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5450.10:5MM

LOADISNS

R5459

453K

1 2

1/20W

201

BYPASS=U5400.3::5MM

1

C5401

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R5405

15K

5% 1/20W MF 201

2

PLACE_NEAR=U5400.6:5MM

OTHERISNS

BYPASS=U5410.6::5MM

1

C5411

0.1UF

10%

6.3V

2

CERM-X5R 0201

HS_OTHER5V_IOUT

1

R5415

15K

1% 1/20W MF 201

2

OTHERISNS

PLACE_NEAR=U5410.10:5MM

OTHERISNS

BYPASS=U5440.6::5MM

1

C5441

0.1UF

10%

6.3V

2

CERM-X5R 0201

HS_OTHER3V3_IOUT

1

R5445

15K

1% 1/20W MF 201

2

OTHERISNS

PLACE_NEAR=U5440.10:5MM

PLACE_NEAR=U5700.22:5MM

EADC1_LCDBKLT_ISENSE

1% MF

1

C5459

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5700.22:5MM

GND_EADC1_COM

(to CPU High Side Threshold Alert circuit)

PLACE_NEAR=U5000.G4:5MM

R5409

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_HI_ISENSECPUHI_IOUT

1

C5409

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.G4:5MM

GND_SMC_AVSS

OTHERISNS

PLACE_NEAR=U5700.3:5MM

R5419

453K

1 2

1%

1/20W

MF

201

EADC1_OTHER5V_HI_ISENSE

1

C5419

0.22UF

20%

6.3V

2

X5R 0201

OTHERRC:YES

PLACE_NEAR=U5700.3:5MM

GND_EADC1_COM

OTHERISNS

PLACE_NEAR=U5710.4:5MM

R5449

453K

1 2

1%

1/20W

MF

201

52

EADC2_OTHER3V3_HI_ISENSE

1

C5449

0.22UF

20%

6.3V

2

X5R 0201

OTHERRC:YES

PLACE_NEAR=U5710.4:5MM

GND_EADC2_COM

53

OUT

53 51 50

PBUS Voltage Sense & Enable (VP0R)

OUT

51

48

Gain: 0.167x Vnominal: 12.6 V, Range: 17.97 V SMC ADC: 01

(PRODUCTION)SMC ADC: 00

Enables PBUS VSense divider when in S0.

SMC_SENSOR_PWR_EN

IN

SM

PBUS_S0_VSENSE_IN

109

PPBUS_G3H

48

XW5480

1 2

PLACE_NEAR=R5400.1:70 MM

55 53 51 50 48 47 46

100K

1%

1/20W

MF

201

1

2

R5481

CRITICAL

Q5480

NTUD3169CZ

SOT-963

N-CHANNEL

2

1

5

4

G

P-CHANNEL

PBUSVSENS_EN_L_DIV

D

S

D

S

DC In Voltage Sense & Enable (VD0R)

Gain: 0.13067x Vnominal: 20 V, Range: 22 V SMC ADC: 04

(PRODUCTION)

53

OUT

Enables DC-In VSense divider when AC present.

2

1

5

4

OUT

48

IN

53 52 51 50

116 114 64 29

53

Charger (BMON) Current Sense (IPBR)

SMC_BC_ACOK

PPDCIN_G3H

R5491

69.8K

1%

1/20W

MF

201

1

2

Charger Gain: 20x, EDP: 7.2 A Rsense: 0.005 (R7060) SMC ADC: 02

114 64

53 52 51 50

IN

PLACE_NEAR=U5000.G2:5MM

R5429

300K

1 2

1%

1/20W

MF

201

SMC_BMON_ISENSECHGR_BMON

1

C5429

3300PF

10% 10V

2

X7R-CERM 0201

PLACE_NEAR=U5000.G2:5MM

GND_SMC_AVSS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

117S0008 OTHERRC:NO 117S0008

1 1 C5469 TPADRC:NO117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5419,C54492

C5459

CRITICAL

Q5490

DMC31D5UDJ

SOT963

N-CHANNEL

D

G

S

D

G

S

P-CHANNEL

PDCINVSENS_EN_L_DIV

48

OUT

46 55

LOADRC:NO

6

3

53 51 50 48 47

6

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

DCINVSENS_EN_L

DCIN_S5_VSENSE

DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 4.6 A Rsense: 0.020 (R7020) SMC ADC: 03

(PRODUCTION)(PRODUCTION)

114 64

IN

CHGR_AMON

R5482

100K

1%

1/20W

MF

201

R5492

200K

1%

1/20W

MF

201

1

2

1%

1/20W

MF

201

1

Rthevenin = 4573 Ohms

2

R5488

27.4K

SMC_PBUS_VSENSE

R5489

5.49K

1%

1/20W

MF

201

1

2

1

C5489

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

1

2

PLACE_NEAR=U5000.C2:5MM

1%

1/20W

MF

201

1

Rthevenin = 4573 Ohms

2

R5498

31.6K

SMC_DCIN_VSENSE

R5499

4.75K

1%

1/20W

MF

201

1

2

1

C5499

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

PLACE_NEAR=U5000.G1:5MM

R5439

45.3K

1 2

1%

1/20W

MF

201

SMC_DCIN_ISENSE

1

C5439

2200PF

10% 10V

2

X7R-CERM 0201

GND_SMC_AVSS

48

OUT

PLACE_NEAR=U5000.G3:5MM PLACE_NEAR=U5000.G3:5MM

48

OUT

PLACE_NEAR=U5000.C2:5MM

48

OUT

PLACE_NEAR=U5000.G1:5MM

D

55 53 51 50 48 47 46

C

55 53 51 50 48 47 46

B

A

Trackpad Actuator X239 Current Sense (ITAR)

Gain: 49.8x, EDP: 2.61 A (Transient) Rsense: 0.02 (R5460) Vsense: 52.2 mV, Range: 3.31 A EADC2: CH7

109

PPBUS_G3H

PLACE_NEAR=U5460.3:7MM

ISNS_TPAD_P

PP3V3_S4SW_SNS

50 51 52 53 55 110

10%

6.3V 0201

1

2

C5460

0.1UF

CERM-X5R

BYPASS=U5460.5::5MM

TPADISNS

V+

OMIT

R5460

0.005

1%

1/3W

MF

0306-SHORT

21 43

ISNS_TPAD_N

3

4

VIN-VIN+

U5460

INA139

SOT23-5

TPADISNS CRITICAL

GND

2

PPBUS_S4_HS_TPAD

PLACE_NEAR=U5460.4:7MM

15

OUT

ISNS_X239_IOUT_BUF

1

R5461

24.9K

1% 1/20W MF 201

2

50 51 52 53 55 110

109

OUTIN

PP3V3_S4SW_SNS

TPADISNS

PLACE_NEAR=U5460.1:5MM

Gain: 1000uA/V * 24.9KOhm = 24.9

C5462

0.1UF

10%

6.3V

CERM-X5R

0201

PP3V3_S4SW_SNS

50 51 52 53 55 110

TPADISNS CRITICAL

ISNS_X239_IOUT

TPADISNS CRITICAL

U5462

8

3

V+

2

1

2

V-

TPADISNS

BYPASS=U5462.8::5MM

OPA2340

MSOP

1

4

TPADISNS

R5465

10K

1 2

1%

1/20W

MF

201

ISNS_X239_INT_NI

TPADISNS

R5468

10K

1 2

1%

1/20W

MF

201

5

V+

6

V-

TPADISNS

1

ISNS_X239_INT_I

U5462

8

OPA2340

MSOP

4

R5467

10K

2

1%

1/20W

MF

201

PLACE_NEAR=U5710.5:5MM

R5469

7

ISNS_X239_IOUT_INT

4.53K

1 2

1%

1/20W

MF

201

TPADISNS

SMC_TPAD_ISENSE

1

C5469

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.5:5MM

TPADRC:YES

GND_EADC2_COM

OUT

53

53 52 51 50

BOM_COST_GROUP=SENSORS

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

Power Sensors: High Side

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

54 OF 145

SHEET

50 OF 121

A

D

8 7 5 4 2 1

36

D

C

B

A

PCH 1.0V Current Sense (ISCC)

Gain: 200x, EDP: 4.11 A Rsense: 0.003 (R8004) or XWTBD Vsense: 11.33 mV, Range: 5 A SMC ADC: 22

PP3V3_S4SW_SNS

50 51 52 53 55 110

PLACE_NEAR=R8004.4:5MM

72

ISNS_1V0_P

IN

PLACE_NEAR=R8004.3:5MM

72

ISNS_1V0_N

IN

DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)

Gain: 100x, EDP: 9.01 A Rsense: 0.003 (R7918) or XWTBD Vsense: 27.03 mV, Range: 10 A SMC ADC: 09

71

ISNS_CPUDDR_N

IN

PLACE_NEAR=R7918.3:5MM

ISNS_CPUDDR_P

IN

PLACE_NEAR=R7918.4:5MM

52

PP3V3_S4SW_SNS

50 51 53 55 110

CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC)

Gain: 200x, EDP: 2 A Rsense: 0.005 (R5510) or Rsense SHORT Vsense: 10 mV, Range: 3 A

52

53 55 110

PP3V3_S4SW_SNS

50 51

SMC ADC: 18

109

PP1V2_S3_CPUDDR

OMIT

0306-SHORT

MF

1/3W

1%

0.005

R5510

PLACE_NEAR=U5510.5:3:10MM

2

4

ISNS_CPUVDDQ_N

ISNS_CPUVDDQ_P

1 3

PLACE_NEAR=U5510.4:5:10MM

109

PP1V2_S3

T139 Current Sense (IF3C)

Gain: 200x, EDP: 0.06 A Rsense: 0.05 (R5520) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 3 mV, Range: 0.25 A

50 51 52 53 55 110

EADC1: CH3

110

PP3V3_S5

PP3V3_S5_T139

OMIT

R5520

0.005

1%

1/3W

0306-SHORT

MF

PLACE_NEAR=U5520.2:3:10MM

1 3

2

ISNS_T139_P

ISNS_T139_N

4

PLACE_NEAR=U5520.4:5:10MM

WLAN Current Sense (IAPC)

Gain: 200x, EDP: 1.67 A Rsense: 0.01 (R5530) or Rsense SHORT Vsense: 25.05 mV, Range: 1.88 A EADC1: CH4

PP5V_S4

53 110

110

PP3V3_S4

PLACE_NEAR=R5533.1:10MM

1 3

ISNS_WLAN_N

OMIT

0306-SHORT

MF

1/3W

1%

0.005

ISNS_WLAN_P

2

4

110

R5530

PP3V3_S4_WLAN

PLACE_NEAR=R5532.1:10MM

LOADISNS

1/20W MF0.1% 0201

1/20W 0.1% 0201MF

LOADISNS

DSF01S30SCAP

R5533

120

1 2

R5532

120

1 2

2 3

4 5

5

IN-

4

5

IN-

4

IN+ REF

2 3

4 5

D5530

SC2

A K

ISNS_WLAN_R_N

ISNS_WLAN_R_P

6

V+

U5560

INA210A

IN+ IN+

UQFN

CRITICAL

OUT

REF

LOADISNS

ININ-

200x

GND

9

3

V+

NC NC

U5570

INA214

SC70

CRITICAL

DDRISNS

100x

GND

2

3

V+

OUT

REFIN+

U5510

INA210

SC70

CRITICAL

LOADISNS

OUT

200x

GND

2

6

V+

U5520

INA210A

IN+ IN+

ININ-

UQFN

CRITICAL LOADISNS

200x

GND

9

OUT

REF

NC NC

PP5V_S4_ISNS_D

VOLTAGE=5V

U5530

LTC2050HVCS5

TSOT23-5

4

3

CRITICAL LOADISNS

145x

10 8 1

7

6

1

6

1

10 8 1

7

LOADISNS

BYPASS=U5560.6::5MM

1

C5560

0.1UF

10%

6.3V

2

CERM-X5R 0201

PCH_1V0_IOUT

1

R5565

NC NC

51K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5560.10:5MM

DDRISNS

BYPASS=U5570.3::5MM

1

C5570

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_DDR_IOUT

1

R5575

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5570.6:5MM

LOADISNS

BYPASS=U5510.3::5MM

1

C5510

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_CPUDDR_IOUT

1

R5515

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5510.6:5MM

LOADISNS

BYPASS=U5520.6::5MM

1

C5520

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_PP3V3S0_IOUT

1

R5525

NC NC

2 5

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5520.10:5MM

Q5530

DMP31D0UFB4

DFN1006H4-3

2

S

1

IAPC_OPA_OUT

R5535

100K

5%

1/20W

MF

201

LOADISNS

D

G

1

2

NO_XNET_CONNECTION=1

PLACE_NEAR=U5000.B5:5MM

NOSTUFF

R5569

453K

1 2

1%

1/20W

MF

201

DDRISNS

PLACE_NEAR=U5000.B3:5MM

R5579

4.53K

1 2

1%

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5000.H1:5MM

R5519

4.53K

1 2

1%

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5700.1:5MM

R5529

453K

1 2

1%

1/20W

MF

201

LOADISNS

BYPASS=U5530.6::5MM

1

C5530

0.1UF

10%

6.3V

2

3

ISNS_PP3V3S4_WLAN_IOUT

1

R5534

17.4K

0.1% 1/20W MF 0201

2

LOADISNS

CERM-X5R 0201

PLACE_NEAR=U5700.2:5MM

SMC_CPU_IMON_ISENSE

1

C5569

0.22UF

20%

6.3V

2

X5R 0201

NOSTUFF

PLACE_NEAR=U5000.B5:5MM

GND_SMC_AVSS

SMC_DDR1V2_ISENSE

1

C5579

0.22UF

20%

6.3V

2

X5R 0201

OUT

PLACE_NEAR=U5000.B3:5MM

DDRRC:YES

GND_SMC_AVSS

SMC_CPUDDR_ISENSE

1

C5519

0.22UF

20%

6.3V

2

X5R 0201

OUT

PLACE_NEAR=U5000.H1:5MM

LOADRC:YES

GND_SMC_AVSS

EADC1_PP3V3S5_T139_ISENSE

1

C5529

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.1:5MM

LOADRC:YES

GND_EADC1_COM

LOADISNS

1/20W MF1%

1 2

R5539

4.53K

PLACE_NEAR=U5700.2:5MM

EADC1_PP3V3S4_WLAN_ISENSE

201

20%

6.3V 0201

1

2

C5539

2.2UF

X5R-CERM

LOADRC:YES

GND_EADC1_COM

OUT

48

46

48

46 47

CPU Fixed Current Sense (ICAC)

Gain: 177.71x, EDP: 67 A Rsense: 3x of 0.00075 (R7210, R7220,R7230), Rsum: 0.00025 Vsense: 16.75 mV, Range: 67.52 A SMC ADC: 06

66

IN

55 48

55 53 51 50 48 47 46

66

IN

CPUCORE_ISNS1_P

NO_XNET_CONNECTION=1

PLACE_NEAR=R7210:5MM

CPUCORE_ISNS2_P

NO_XNET_CONNECTION=1

PLACE_NEAR=R7220:5MM

CPUCORE_ISNS3_P

NO_XNET_CONNECTION=1

PLACE_NEAR=R7230:5MM

CPUCORE_ISNS1_N

NO_XNET_CONNECTION=1

PLACE_NEAR=R7210:5MM

CPUCORE_ISNS2_N

NO_XNET_CONNECTION=1

PLACE_NEAR=R7220:5MM

CPUCORE_ISNS3_N

NO_XNET_CONNECTION=1

PLACE_NEAR=R7230:5MM

BT Current Sense (IBTC)

Gain: 200x, EDP: 0.06 A Rsense: 0.05 (R5580) or XWTBD Vsense: 3 mV, Range: 0.25 A EADC2: CH05

110

55 53 51 50 48 47

110

CPU High Side Current (IC0R) Threshold Alert

Gain: 100x Rsense: 0.001 (R5400)

Trip Target on CPU High current: TBD A Hysteresis Circuit: Vref = 0.737 V Vth = 0.616 V -> 2.054 A on CPU High current

55 53 51 50 48

Vtl = 0.771 V -> 2.571 A on CPU High current Hysteresis Margin = 0.518 A

53

OUT

1.8V Current Sense (I18C)

PP3V3_S4SW_SNS

50 52 53 55 110 51

53 52 51 50

PLACE_NEAR=R8024.3:5MM

72

IN

72

IN

PLACE_NEAR=R8024.4:5MM

ISNS_1V8_SUS_P

ISNS_1V8_SUS_N

OUT

117S0008 117S0008 DDRRC:NO1

53 52 51 50

53

LOADISNS

PP3V3_S4

PP3V3_S4_BT

110

V+

U5590

INA210A

UQFN

CRITICAL LOADISNS

200x

GND

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

6

2

IN+

3

IN+

4

IN-

5

IN-

R5545

4.42K

1 2

1/20W 0201

MF0.1%

R5546

4.42K

1 2

0.1%

1/20W 0201

MF

R5550

4.42K

1 2

0.1%

1/20W

MF

R5547

4.42K

1 2

MF0.1%

02011/20W

R5548

4.42K

1 2

0.1%

1/20W

R5551

4.42K

1 2

0.1%

1/20W

PP3V3_S0

6

OUT

REF

9

0201

CPUVR_ISNS_N

MF 0201

MF

0201

OMIT

R5580

0.005

0306-SHORT

LOADISNS

BYPASS=U5590.6::5MM

1

C5590

0.1UF

10%

6.3V

2

CERM-X5R 0201

10

P1V8SUS_IOUT

8 1

NC NC

NC

7

NC

LOADISNS

R5542

2.55K

1 2

0.1%

1/20W

MF

0201

CPUVR_ISNS_R_PCPUVR_ISNS_P

1

R5544

715K

0.1% 1/20W MF 0201

2

LOADISNS

NO_XNET_CONNECTION=1

LOADISNS

R5543

2.55K

1%

1/3W

MF

1 2

0.1%

1/20W

MF

0201

PP3V3_S4SW_SNS

50 51 52 53 55 110

PLACE_NEAR=U5580.2:3:10MM

1 3

2

ISNS_BT_P

ISNS_BT_N

4

PLACE_NEAR=U5580.4:5:10MM

CPUVR_ISNS_R_N

1

2

1

2

RB521ZS-30

LOADISNS

PLACE_NEAR=U5700.23:5MM

R5599

1 2

1

R5595

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5590.10:5MM

C5519,C5529,C5539,C5549,C5589,C5599

C5579

345678

2

IN+

3

IN+

4

IN-

5

IN-

CPUHYS

R5554

294K

1% 1/20W MF 201

CPUHYS

R5555

84.5K

1% 1/20W MF 201

NOSTUFF

D5557

SM-201

453K

1%

1/20W

MF

201

PP3V3_S0

110

1

3

R5541

715K

1 2

0.1%

1/20W

0201

LOADISNS

BYPASS=U5580.6::5MM

1

6

V+

U5580

INA210A

UQFN

CRITICAL LOADISNS

200x

GND

9

BYPASS=U5551.5::5MM

CPUHYS

1

C5551

0.1UF

10%

6.3V

2

CERM-X5R 0201

CPUHI_COMP_VREF

NOSTUFF

1

R5557

0

5% 1/20W MF 0201

2

BMON_IOUT_D

A

K

EADC1_P1V8SUS_ISENSE

1

C5599

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.23:5MM

LOADRC:YES

GND_EADC1_COM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BOM_COST_GROUP=SENSORS

OUT

REF

NC NC

10 8 1

7

C5580

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_BT_IOUT

1

NC NC

2

NOSTUFF

LOADRC:NO

LOADISNS CRITICAL

U5540

5

ISL28133

SC70-5

V+

V-

2

MF

4

CPUVR_ISUM_IOUT

LOADISNS

NO_XNET_CONNECTION=1

LOADISNS

NO_XNET_CONNECTION=1

R5585

20K

5% 1/20W MF 201

CPUHYS

R5556

12K

1 2

1%

1/20W

MF

201

CPUHI_IOUT_R

CPUHYS

1

R5552

0

5% 1/20W MF 0201

2

CPUHI_IOUT

Gain: 200x, EDP: 0.7 A Rsense: 0.025 (R8024) or Rsense SHORT Vsense: 17.5 mV, Range: 0.6 A EADC1: CH1

53

OUT

53 52 51 50

2 1

LOADISNS

BYPASS=U5540.5::5MM

1

C5540

0.1UF

10%

6.3V

2

X7R 0201

R5549

4.53K

1 2

1%

1

R5540

20K

5%

1/20W

MF

201

2

NOSTUFF

PLACE_NEAR=U5540.4:5MM

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5000.A1:5MM

SMC_CPU_ISENSE

1

C5549

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.A1:5MM

OUT

48

GND_SMC_AVSS

55 53 51 50 48 47 46

R5589

4.53K

1 2

1%

1/20W

MF

201

EADC2_BT_ISENSE

LOADRC:YES

1

C5589

2.2UF

20%

6.3V

2

X5R-CERM 0201

GND_EADC2_COM

53

OUT

53 52 50

NOSTUFF

C5553

0.22UF

1 2

20%

6.3V X5R

0201

R5553

255K

CPUHI_COMP_FB

CPUHYS

U5551

3

4

NOSTUFF

1

C5552

0.1UF

10%

6.3V

2

CERM-X5R 0201

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

5

MAX9119EXK-T SC70-5

1

CRITICAL

2

CPUHYS

DMN32D2LFB4

50

IN

CPUHI_COMP_OUT

SMC_CPUHI_COMP_ALERT_L

U5552

DFN1006H4-3

SYM_VER_2

1

1 2

1%

1/20W

MF

201

CPUHYS

3

D

SG

2

OUT

48

Power Sensors: Load Side

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

55 OF 145

SHEET

51 OF 121

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

T139 5V Current Sense (IF5C)

Gain: 200x, EDP: 0.004 A Rsense: 0.05 (R5630) or Rsense SHORT Vsense: 0.2 mV, Range: 0.25 A EADC1: CH6

110

PP5V_S0

PP5V_S0_T139

OMIT

R5630

0.005

1%

1/3W

0306-SHORT

MF

110 55 53 52 51 50

PLACE_NEAR=U5630.2:3:10MM

1

ISNS_PP5V_T139_P

ISNS_PP5V_T139_N

432

PLACE_NEAR=U5630.4:5:10MM

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5630

INA210A

UQFN

CRITICAL LOADISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

Thunderbolt TBT LEFT Current Sense (IULC)

Gain: 200x. EDP: 0.5 A Rsense: 0.025 (R5640) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH7

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5640

INA210A

UQFN

CRITICAL

TBTISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

NC NC

110

PP3V3_S0_LEFT

PP3V3_TBT_X_S0

OMIT

R5640

0.005

1%

1/3W

0306-SHORT

MF

110 55 53 52 51 50

PLACE_NEAR=U5640.2:3:10MM

ISNS_TBT_X_P ISNS_TBT_X_IOUT

ISNS_TBT_X_N

4312

PLACE_NEAR=U5640.4:5:10MM

LCD Panel Current Sense (ILDC)

Gain: 200x. EDP: 1 A RSENSE: 0.01 (R8520) or Rsense SHORT Vsense: 5 mV, Range: 1.25 A EADC2: CH0

76 53

76

ISNS_LCDPANEL_P

ISNS_LCDPANEL_N

IN

PP3V3_S0

110

6

V+

U5620

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL LOADISNS

200x

GND

9

Trackpad 3V Current Sense (IT3C)

Gain: 200x, EDP: 0.2 A Rsense: 0.05 (R5650) or Rsense SHORT Vsense: 10 mV, Range: 0.25 A EADC2: CH1

110

PP3V3_S4

OMIT

R5650

0.005

1/3W

0306-SHORT

110

PP3V3_S4_TPAD

1% MF

110 55 53 52 51 50

PLACE_NEAR=U5650.2:3:10MM

1 3

ISNS_PP3V3_TPAD_P ISNS_PP3V3_TPAD_IOUT

ISNS_PP3V3_TPAD_N

2

4

PLACE_NEAR=U5650.4:5:10MM

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5650

INA210A

UQFN

CRITICAL

TPADISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

LOADISNS

BYPASS=U5630.6::5MM

1

C5630

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_PP5V_T139_IOUT

1

R5635

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5630.10:5MM

TBTISNS

BYPASS=U5640.6::5MM

1

C5640

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R5645

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5640.10:5MM

LOADISNS

BYPASS=U5620.6::5MM

1

C5620

0.1UF

10%

6.3V

2

CERM-X5R 0201

OUT

REF

NC NC

10 8 1

7

ISNS_LCDPANEL_IOUT

1

R5625

NC NC

51K

5% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5620.10:5MM

TPADISNS

BYPASS=U5650.6::5MM

1

C5650

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R5655

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5650.10:5MM

LOADISNS

PLACE_NEAR=U5700.4:5MM

R5639

453K

1

1/20W

1% MF

201

2

EADC1_PP5V_T139_ISENSE

1

C5639

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.4:5MM

LOADRC:YES

GND_EADC1_COM

TBTISNS

PLACE_NEAR=U5700.5:5MM

R5649

453K

1

1/20W

1% MF

201

2

EADC1_TBT_X_ISENSE

1

C5649

0.22UF

20%

6.3V

2

X5R 0201

TBTRC:YES

PLACE_NEAR=U5700.5:5MM

GND_EADC1_COM

LOADISNS

PLACE_NEAR=U5710.22:5MM

R5629

453K

1/20W

TPADISNS

PLACE_NEAR=U5710.23:5MM

1% MF

201

21

EADC2_LCDPANEL_ISENSE

1

C5629

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5710.22:5MM

GND_EADC2_COM

R5659

453K

1/20W

1% MF

201

21

EADC2_PP3V3_TPAD_ISENSE

1

C5659

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.23:5MM

TPADRC:YES

GND_EADC2_COM

50 51 52 53

OUT

50 53

51 52

50 51 52 53

OUT

53

50 51 52 53

OUT

53

CPU High Side (IC0R) Peak Detection Support

NOSTUFF

R5660

47

PP3V3_S0_LEFT

110

1/20W

CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm

PLACE_NEAR=R5400.3:10MM

50 52

IN

50 52

IN

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PLACE_NEAR=R5400.4:10MM

CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm

2

IN+

3

IN+

4

IN-

5

IN-

21

5% MF

201

V+

U5660

INA210A

UQFN

CRITICAL LOADISNS

200x

GND

ISNS_CPUHIGAIN_R_P

PLACE_NEAR=U5660.10:10MM

1

R5662

1

C5660

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U5660.6::5MM

6

R5665

10

OUT

8

REF

1

NC

7

NC

9

ISNS_CPUHIGAIN_OUT

1

R5664

NC NC

15K

5% 1/20W MF 201

2

PLACE_NEAR=U5660.10:5MM

0

5%

1/20W

MF

0201

21

ISNS_CPUHIGAIN_OUT_R

1

C5665

0.22UF

20%

6.3V

2

X5R 0201

NOSTUFF

In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current.

SENSE+ pins of EMC1704 sink 10-20uA current. This deviation has been designed in our Peak Detection circuit. With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

1K

1% 1/20W MF 201

2

ISNS_CPUHIGAIN_R_N

PLACE_NEAR=U5660.10:10MM

1

R5661

16K

1% 1/20W MF 201

2

50 52

IN

50 52

IN

ISNS_HS_COMPUTING_P

PLACE_NEAR=U5660.10:10MM

ISNS_HS_COMPUTING_N

PLACE_NEAR=U5660.10:10MM

R5666

0

21

5%

1/20W

MF

0201

NOSTUFF

R5668

0

21

5%

1/20W

MF

0201

ISNS_CPUHIGAIN_P

R5667

0

21

5%

1/20W

MF

0201

ISNS_CPUHIGAIN_N

R5669

0

21

5%

1/20W

MF

0201

OUT

54

D

Thunderbolt TBT RIGHT Current Sense (IURC)

Gain: 200x. EDP: 0.5 A Rsense: 0.025 (R5680) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH2

52 50 110 55 53 51

110

OUTIN

PP3V3_S0

PP3V3_TBT_T_S0

OMIT

R5680

0.005

1%

1/3W

0306-SHORT

MF

PLACE_NEAR=U5670.2:3:10MM

ISNS_TBT_T_P

ISNS_TBT_T_N

4312

PLACE_NEAR=U5670.4:5:10MM

PP3V3_S4SW_SNS

2 3

4 5

U5670

INA210A

IN+

CRITICAL

IN+

TBTISNS

ININ-

200x

6

V+

UQFN

GND

9

OUT

REF

NC NC

10 8 1

7

TBTISNS

BYPASS=U5670.6::5MM

1

C5680

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_TBT_T_IOUT

1

NC NC

R5685

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5670.10:5MM

TBTISNS

PLACE_NEAR=U5700.24:5MM

R5689

453K

1

1/20W

1% MF

201

2

EADC1_TBT_T_ISENSE

1

C5689

0.22UF

20%

6.3V

2

X5R 0201

TBTRC:YES

PLACE_NEAR=U5700.24:5MM

GND_EADC1_COM

53

OUT

50 51 52 53

C

T151 Current Sense (IIDC)

Gain: 200x, EDP: 0.1638 A

53

Rsense: 0.05 (R5690) or Rsense SHORT Vsense: 819 mV, Range: 0.25 A

110 55 53 52 51 50

EADC2: CH4

110

PP3V3_S4

OMIT

ISNS_T151_P

ISNS_T151_N

4312

110

PP3V3_S4_T151

R5690

0.005

1%

1/3W

0306-SHORT

MF

PP3V3_S4SW_SNS

2 3

4 5

U5690

INA210A

IN+

CRITICAL

IN+

LOADISNS

ININ-

6

V+

UQFN

OUT

REF

200x

GND

9

NC NC

10 8 1

7

LOADISNS

BYPASS=U5690.6::5MM

1

C5690

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_T151_IOUT

1

R5695

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5690.10:5MM

LOADISNS

PLACE_NEAR=U5710.2:5MM

R5699

453K

1/20W

1% MF

201

21

EADC2_T151_ISENSE

1

C5699

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.2:5MM

LOADRC:YES

GND_EADC2_COM

50 51

OUT

52 53

B

53

A

Camera Current Sense (ICMC)

Gain: 200x. EDP: 0.82 A Rsense: 0.015 (R5610) or XW5610 Vsense: 12.3 mV, Range: 0.83 A EADC2: CH2

110

PP3V3_S4

PP3V3_S4_SOC_PMU

OMIT

R5610

0.005

1%

1/3W

0306-SHORT

MF

110 55 53 52 51 50

PLACE_NEAR=U5610.2:3:10MM

1 3

2

4

ISNS_CAMERA_P

ISNS_CAMERA_N

PLACE_NEAR=U5610.4:5:10MM

PP3V3_S4SW_SNS

LOADISNS

BYPASS=U5610.6::5MM

1

C5610

6

V+

U5610

INA210A

2

IN+

3

IN+

UQFN

CRITICAL LOADISNS

4

IN-

5

IN-

200x

GND

9

OUT

REF

NC NC

10 8 1

7

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_CAMERA_IOUT

1

R5615

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5610.10:5MM

LOADISNS

PLACE_NEAR=U5710.24:5MM

R5619

453K

1/20W

1% MF

201

21

EADC2_CAMERA_ISENSE

1

C5619

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5710.24:5MM

GND_EADC2_COM

53

OUT

50 51 52 53

117S0008

4 2 1 TPADRC:NO117S0008

RES,MTL FILM,100K,1/16W,0201,SMD,LF

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5619,C5629,C5639,C5699

C5649,C5689

C5659

BOM_COST_GROUP=SENSORS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LOADRC:NO117S0008

TBTRC:NO

A

SYNC_DATE=04/14/2016SYNC_MASTER=X363_ZIFENGSHEN

PAGE TITLE

Power Sensors: Extended

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

56 OF 145

SHEET

52 OF 121

D

8 7 5 4 2 1

36

345678

2 1

D

C

SSDLIM Current Sense (IHDC)

Gain: 200x, EDP: 2.61 A RSENSE: 0.005 (R5750) Vsense: 13.05 mV, Range: 3.0 A SMC ADC: 14

78 84 86

PP3V3_SSD_LIM

OMIT

0306-SHORT

MF

1/3W

1%

0.005

R5750

84

PP3V3_SSD_ISNS_R

55 53 52 51 50 110

PLACE_NEAR=U5750.5:5:10MM

2 4

ISNS_SSDNAND_N

MAKE_BASE=TRUE

ISNS_SSDNAND_P

31

MAKE_BASE=TRUE

PLACE_NEAR=U5750.4:3:10MM

PP3V3_S4SW_SNS

KB backlite Current Sense (IKBC)

Gain: 200x, EDP: 300m A Rsense: 0.035 (R5730) Vsense: 10.5 mV, Range: 0.36 A EADC2: CH3

110

PP5V_S0

OMIT

R5730

0.005

1/3W

0306-SHORT

110

PP5V_S0_KBD

52 50 55 53 51 110

PLACE_NEAR=U5730.2:3:10MM

1 3

1% MF

2

ISNS_KBBLT_P

ISNS_KBBLT_N

4

PLACE_NEAR=U5730.4:5:10MM

PP3V3_S4SW_SNS

LPDDR 1.8V Current Sense (IM1C)

Gain: 200x, EDP: 0.555 A Rsense: 0.025 (R5720) or Rsense SHORT Vsense: 13.875 mV, Range: 0.6 A SMC ADC: 23 (OPTIONAL)

109

PP1V8_S3

R5720

0.025

1%

1/3W

MF

0306

109

CRITICAL

PP1V8_S3_MEM

53 52 51 50

110 55

PLACE_NEAR=U5720.2:3:10MM

1

ISNS_LPDDR_P

ISNS_LPDDR_N

432

PLACE_NEAR=U5720.4:5:10MM

PP3V3_S4SW_SNS

CPU GT Current Sense (ICTC)

LOADISNS

BYPASS=U5750.3::5MM

1

C5750

0.1UF

3

V+

U5750

5

IN-

4

IN+ REF

INA210

SC70

CRITICAL

LOADISNS

200x

GND

2

OUT

6

1

10%

6.3V

2

CERM-X5R 0201

ISNS_SSDNAND_IOUT

1

R5755

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5750.6:5MM

LOADISNS

PLACE_NEAR=U5000.C1:5MM

R5789

4.53K

1/20W

1% MF

201

21

SMC_SSDLIM_ISENSE

1

C5789

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.C1:5MM

GND_SMC_AVSS

48

OUT

46 47 48 50 51 53

68

55

68

BYPASS=U5730.6::5MM

1

C5730

6

V+

U5730

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_KBBLT_IOUT

1

R5735

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5730.10:5MM

LOADISNS

PLACE_NEAR=U5710.1:5MM

R5739

453K

1/20W

1% MF

201

21

EADC2_KBBLT_ISENSE

1

C5739

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.1:5MM

LOADRC:YES

GND_EADC2_COM

53

50 51 53

68

52

BYPASS=U5730.6::5MM

1

C5720

6

V+

U5720

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10 8 1

7

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_LPDDR_IOUT

1

R5725

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

NO_XNET_CONNECTION=1

NOSTUFF

R5729

453K

1

1/20W

1% MF

201

2

SMC_CPUGT_IMON_ISENSE

1

C5729

0.22UF

20%

6.3V

2

X5R 0201

NOSTUFF

OUT

48 55

Gain: 202.93x, EDP: 55 A Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375 Vsense: 20.625 mV, Range:57.62 A SMC ADC: 5

IN

CPUGT_ISNS1_P

PLACE_NEAR=R7410.4:5MM

NO_XNET_CONNECTION=1

LOADISNS

R5745

4.42K

1/20W

0.1% MF

0201

21

LOADISNS

R5746

IN

CPUGT_ISNS2_P CPUGT_ISNS_R_P

PLACE_NEAR=R7420.4:5MM

NO_XNET_CONNECTION=1

LOADISNS

4.42K

1/20W

0.1% MF

0201

21

R5748

IN

CPUGT_ISNS1_N

PLACE_NEAR=R7410.3:5MM

NO_XNET_CONNECTION=1

LOADISNS

4.42K

1/20W

0.1% MF

0201

21

LOADISNS

R5757

IN

CPUGT_ISNS2_N

PLACE_NEAR=R7420.3:5MM

NO_XNET_CONNECTION=1

LOADISNS

4.42K

1/20W

0.1% MF

0201

21

CPUGT_ISNS_R_N

CPU SA Current Sense (ICSC)

Gain: 200x, EDP: 8 A Rsense: 0.002 (R7570) Vsense: 16 mV, Range: 7.5 A SMC ADC: 17

67

110 55 53 52 51 50

CPUSA_ISNS_N

PLACE_NEAR=R7370.3:20.5MM

IN

CPUSA_ISNS_P

PLACE_NEAR=R7370.4:20.5MM

PP3V3_S4SW_SNS

R5742

2.94K

1/20W

1% MF

201

21

R5743

2.94K

1/20W

1% MF

201

21

PP3V3_S0

110

CPUGT_ISNS_P

1

R5744

715K

0.1% 1/20W MF 0201

2

LOADISNS

NO_XNET_CONNECTION=1

CPUGT_ISNS_N

3

V+

U5770

5

IN-

4

INA214

SC70

CRITICAL

LOADISNS

100x

GND

2

OUT

REFIN+

1

3

R5741

715K

0.1%

1/20W

0201

LOADISNS

BYPASS=U5770.3::5MM

1

C5770

0.1UF

10%

6.3V

2

X7R 0201

6

ISNS_CPUSA_IOUT

1

R5775

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5770.6:5MM

MF

LOADISNS

CRITICAL

U5740

5

ISL28133

SC70-5

V+

V-

2

21

LOADISNS

NO_XNET_CONNECTION=1

4

CPUGT_ISUM_IOUT

1

R5740

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5740.4:5MM

LOADISNS

PLACE_NEAR=U5000.H2:5MM

R5779

4.53K

1/20W

1% MF

201

21

BYPASS=U5740.5::5MM

LOADISNS

1

C5740

0.1UF

10%

6.3V

2

X7R 0201

LOADISNS

PLACE_NEAR=U5000.C3:5MM

R5749

4.53K

1/20W

SMC_CPUSA_ISENSE

1

C5779

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.H2:5MM

LOADRC:YES

GND_SMC_AVSS

1% MF

201

21

SMC_CPUGT_ISENSE

1

C5749

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.C3:5MM

GND_SMC_AVSS

OUT

48

OUTIN

46 47 48 50 51 55

48

46 47 48 50 51 53 55

53

D

C

B

A

110 53 51

PP5V_S4

BYPASS=U5700.12::5MM

50

51

50

52

50 51 52

EADC1_LCDBKLT_ISENSE EADC1_P1V8SUS_ISENSE

EADC1_PP3V3S5_T139_ISENSE EADC1_PP3V3S4_WLAN_ISENSE EADC1_OTHER5V_HI_ISENSE EADC1_PP5V_T139_ISENSE PP2V5_ADC1_VREF EADC1_TBT_X_ISENSE

VOLTAGE=0V

GND_EADC1_COM

LOADISNS

VOLTAGE=5V

R5700

10

21

PP5V_EADC1_AVDD

5%

1/20W

MF

201

BYPASS=U5700.12::5MM

PLACE_NEAR=U5700.6:1MM

1

2

BYPASS=U5700.12::5MM

PLACE_NEAR=U5700.25:1MM

C5701

0.1UF

10%

10V

X5R-CERM 0201

LOADISNS

XW5700

SM

2 1

1

C5702

4.7UF

20%

10V

2

X5R-CERM 0402

LOADISNS

22

CH0

23

CH1

24

CH2

1

CH3

2

CH4

3

CH5

4

CH6

5

CH7

6

COM

EADC1

1

C5703

2

LOADISNS

13

12 AVDD DVDD

U5700

LTC2309

QFN

CRITICAL

LOADISNS

GND

9

11

10

BYPASS=U5700.8::5MM

18

19

20

BYPASS=U5700.21::5MM

21

VREF

REFCOMP

THRM

PAD

25

(Write: 0x10 Read: 0x11)

VOLTAGE=5V

0.1UF

10%

10V

X5R-CERM 0201

14

AD0

15

AD1

17

SDA

16

SCL

7

8

1

2

1

C5704

4.7UF

20%

10V

2

X5R-CERM 0402

LOADISNS

BYPASS=U5700.21::5MM

SMBUS_SMC_2_S4_SDA SMBUS_SMC_2_S4_SCL

ADC1_REFCOMP

1

C5705

0.1UF

10%

6.3V

CERM-X5R 0201

LOADISNS

C5706

10UF

20%

10V

2

X5R-CERM 0402-10

LOADISNS

BYPASS=U5700.8::5MM

110 53 51

PP5V_S4

BYPASS=U5710.12::=5MM

49

1

C5700

2.2UF

20%

6.3V

2

X5R-CERM 0201

LOADISNS

BYPASS=U5700.7::5MM

GND_SMC_AVSS

LOADISNS

R5710

10

5%

1/20W

MF

201

BYPASS=U5710.12::5MM

52

52 52

53

52

51

50

GND_EADC2_COM

50 51 52 53

EADC2_LCDPANEL_ISENSE EADC2_PP3V3_TPAD_ISENSE EADC2_CAMERA_ISENSEEADC1_TBT_T_ISENSE EADC2_KBBLT_ISENSE EADC2_T151_ISENSE EADC2_BT_ISENSE EADC2_OTHER3V3_HI_ISENSE

SMC_TPAD_ISENSE

VOLTAGE=0V

46 47 48 50 51 53 55

VOLTAGE=5V

21

LOADISNS

1

C5711

0.1UF

10%

6.3V

2

CERM-X5R 0201

XW5710

2 1

PP5V_EADC2_AVDD

1

C5712

4.7UF

20%

10V

2

X5R-CERM 0402

LOADISNS

22

CH0

23

CH1

24

CH2

1

CH3

2

CH4

3

CH5

4

CH6

5

CH7

6

COM

SM

PLACE_NEAR=U5710.6:1MM

PLACE_NEAR=U5710.25:1MM

EADC2

13

12 AVDD DVDD

U5710

LTC2309

QFN

CRITICAL

LOADISNS

GND

9

11

10

20

19

18

BYPASS=U5710.10::5MM

VOLTAGE=5V

BYPASS=U5710.21::5MM

1

C5713

0.1UF

10%

10V

2

X5R-CERM 0201

LOADISNS

BYPASS=U5710.21::5MM

21

1

C5714

4.7UF

20%

10V

2

X5R-CERM 0402

LOADISNS

R5712

AD0 AD1

SDA

SCL

VREF

REFCOMP

THRM

PAD

25

14 15

17 16

7

8

ADC2_REFCOMP

1

C5715

0.1UF

2

LOADISNS

100K

SMBUS_SMC_2_S4_SDA SMBUS_SMC_2_S4_SCL

PP2V5_ADC2_VREF

10%

6.3V

CERM-X5R 0201

EADC2_AD0

21

PP5V_S4

5%

1/20W

MF

201

BOMOPTION=NOSTUFF

1

C5716

10UF

20%

10V

2

X5R-CERM 0402-10

LOADISNS

BYPASS=U5710.10::5MM

(Write: 0x14 Read: 0x15)

49

1

C5710

2.2UF

20%

6.3V

2

X5R-CERM 0201

LOADISNS

4

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

110 53 51

BYPASS=U5710.7::5MM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

C5739,C5749,C5779,C5789

LOADRC:NO117S0008

CPU SA Voltage Sense (VCSC)

SMC ADC: 19

(PRODUCTION)

PPVCCSA_S0_CPU

109 8

BOM_COST_GROUP=SENSORS

XW5778

SM

21

CPUSAVSENSE_IN

PLACE_NEAR=R7370.2:5 MM

PLACE_NEAR=U5000.H3:5MM

R5778

4.53K

1%

1/20W

MF

201

PAGE TITLE

Power Sensors: Extended 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

21

SMC_CPUSA_VSENSE

1

C5778

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.H3:5MM

GND_SMC_AVSS

48

OUT

46 47 48 50 51 53 55

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

57 OF 145

SHEET

53 OF 121

B

A

SYNC_DATE=04/14/2016SYNC_MASTER=X363_ZIFENGSHEN

8 7 5 4 2 1

36

D

Thermal Sensor A: Thunderbolt Die, Airflow Left

I2C Write: 0xD8, I2C Read: 0xD9

Thermal Diode: TBT Die (TTLD)

Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.

27

28

345678

2 1

R5850

47

PP3V3_S0_LEFT

110

BI

TBTTHMSNS_X_D1_P

MAKE_BASE=TRUE

PLACE_NEAR=U5850.2:5MM

1 2

5%

1/20W

MF

201

C5851

2200PF

X7R-CERM

TBTTHRM_SNS

BI

TBTTHMSNS_X_D1_N

MAKE_BASE=TRUE

Note: Use GND pin AC22 on U2800 for N leg.

PLACE_NEAR=U5850.3:5MM

PP3V3_S0_TBTTHMSNS_X_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

10% 10V

2

0201

2

D+

3

D-

5

A0

10

A1 THERM*

CRITICAL

1

V+

U5850

TMP461

QFN

TBTTHRM_SNS

ALERT*/THERM2*

SCL SDA

BYPASS=U5850.1::5MM

1

C5850

0.1UF

10%

6.3V

2

CERM-X5R 0201

TBTTHRM_SNS

SMBUS_SMC_3_SCL

9 8

SMBUS_SMC_3_SDA

7

TBTTHMSNS_X_ALERT_L

4

TBTTHMSNS_X_THM_L

TBTTHRM_THRM:PU

49

BI

49

BI

1

R5851

100K

1% 1/20W MF 201

2

U5850 I2C Address:TMP461 A1->GND A0->GND 0X90/0X91

1

R5852

100K

1% 1/20W MF 201

2

TBTTHRM_ALRT:PU

48

OUT

48

OUT

D

C

Thermal Sensor C: Thunderbolt Die, Air Flow Right

I2C Write: 0x98, I2C Read: 0x99

Thermal Diode: TBT Die (TTRD)

Placement Note:

The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.

101

102

PP3V3_S0

110

TBTTHMSNS_T_D1_P

BI

TBTTHMSNS_T_D1_N

BI

Note: Use GND pin AC22 on UB000 for N leg.

TBTTHMSNS_T_D1_P

MAKE_BASE=TRUE

TBTTHMSNS_T_D1_N

MAKE_BASE=TRUE

R5800

47

1 2

5%

1/20W

MF

201

PLACE_NEAR=U5800.2:5MM

C5801

2200PF

X7R-CERM

PLACE_NEAR=U5800.3:5MM

TBTTHRM_SNS

PP3V3_S0_TBTTHMSNS_T_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

10% 10V

2

0201

NC

2

D+

3

D-

5

A0

10

A1 THERM*

GND

6

CRITICAL

1

V+

U5800

TMP461

QFN

TBTTHRM_SNS

ALERT*/THERM2*

Thermal Diode: Airflow Left Proximity (TaLC)

Placement Note: Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector.

BYPASS=U5850.1::5MM

U5800 I2C Address:TMP461 A1->Floating A0->GND 0X96/0X97

1

C5800

SCL SDA

0.1UF

10%

6.3V

2

CERM-X5R 0201

TBTTHRM_SNS

9

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

8 7

TBTTHMSNS_T_ALERT_L

4

TBTTHMSNS_T_THM_L

TBTTHRM_THRM:PU

BI

54 49

1

R5801

100K

1% 1/20W MF 201

2

1

R5802

100K

1% 1/20W MF 201

2

TBTTHRM_ALRT:PU

48

OUT

48

OUT

C

B

A

Thermal Sensor B & CPU High Peak Detection: CPU Proximity, Memory Proximity, Fin Stack Left, Fin Stack Right

I2C Write: 0x98, I2C Read: 0x99

Q5871

BC846BLP

DFN1006H4-3

Q5873

BC846BLP

DFN1006H4-3

Q5872

BC846BLP

DFN1006H4-3

CPUTHMSNS_D1_P

3

CRITICAL

2

1

PLACE_NEAR=U5870.6:5MM

C5871

2200PF

10% 10V

X7R-CERM

0201

PLACE_NEAR=U5870.7:5MM

1

2

CPUTHMSNS_D1_N CPUTHMSNS_D2_P

3

CRITICAL

2

1

PLACE_NEAR=U5870.8:5MM

C5872

2200PF

10% 10V

X7R-CERM

PLACE_NEAR=U5870.9:5MM

0201

1

2

CPUTHMSNS_D2_N

CPUTHMSNS_D3_P

3

CRITICAL

1

2

PLACE_NEAR=U5870.10:5MM

C5873

2200PF

10% 10V

X7R-CERM

PLACE_NEAR=U5870.11:5MM

0201

1

2

CPUTHMSNS_D3_N ISNS_CPUHIGAIN_N

Thermal Diode: Memory Proximity (TM0P)

Placement Note: Place Q5872 between two rows of Memory devices, between channel A and B, on the BOTTOM side.

PP3V3_S0

110

54 49

BI BI

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL

R5870

47

1 2

5%

1/20W

MF

201

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

Thermal Diode: Fin Stack Left (Th2H)

Placement Note: Place Q5871, Airflow thermal indicator, above the X100, on the TOP side.

Thermal Diode: Fin Stack Right (Th1H)

Placement Note: Place U5870 at corner near right Fan, on the TOP side.

52

IN IN

ISNS_CPUHIGAIN_P

GND

6

Thermal Diode: Airflow Right Proximity (TaRC)

Placement Note: Place U5800 on the TOP side, on the left portion of the board, 1" to the right of USB connector.

BYPASS=U5870.1::5MM

1

C5870

0.1UF

10%

6.3V

2

X7R

16

CRITICAL

V+

0201

U5870

TMP513AISAR

QFN

10 11

6 7

8 9

1 2

DXP1 DXN1

DXP2 DXN2 DXP3

DXN3 VIN+

VIN-

GND

14

FILTER C

ALERT

SDA

SCL

GPIO

THRM

PAD

17

Thermal Sensor: CPU Proximity (TC0P)

Placement Note: Place Q5873 under the CPU, on the BOTTOM side.

I2C ADDRESS (U5870): 0XB8/0XB9

A0

15

CPUTHMSNS_FILTER

5

CPUTHMSNS_ADDR_SEL

13

CPUTHMSNS_ALERT_L

3

SMBUS_SMC_1_S0_SDA

4

SMBUS_SMC_1_S0_SCL

12

CPUTHMSNS_THM_L

1

R5873

10K

5% 1/20W MF 201

2

1

R5872

100K

1% 1/20W MF 201

2

1

R5871

100K

1% 1/20W MF 201

2

OUT

BI BI

OUT

1

C5874

0.47UF

10%

6.3V

2

CERM-X5R 0201

48

49

48

49

110

BI

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL

BOM_COST_GROUP=SENSORS

X100 PROXIMITY (TW0P)

PP3V3_S0_LEFT

AP_TEMP

1

PLACE_SIDE=BOTTOM

PLACE_NEAR=U3730::10MM

Placement note:

PLACE U5820 ON BOTTOM NEAR X100

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

5

V+

U5820

HPA00330AI

6

SDA

1

SCL ALERT

SOT563

CRITICAL

AP_TEMP

GND

2

Thermal Sensors

Apple Inc.

R

ADD0

4 3

C5820

0.1UF

10%

6.3V

2

CERM-X5R 0201

X29THMSNS_A0

NC

WRITE ADDRESS: 0X92 READ ADDRESS: 0X93

AP_TEMP

1

R5820

10K

5% 1/20W MF 201

2

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

58 OF 145

SHEET

54 OF 121

B

A

8 7 5 4 2 1

36

D

SENSORS: EXTENDER 3

CPU Core Voltage Sense (VCAC) CPU Core IMON Current Sense (ICAM)

SMC ADC: 20

(PRODUCTION)

109 8 6

PPVCC_S0_CPU

PLACE_NEAR=R7210.2:5 MM

XW5900

SM

21

CPUVSENSE_IN

PLACE_NEAR=U5000.C4:5MM

CPU GT Voltage Sense (VCTC)

SMC ADC: 21

(PRODUCTION)

PPVCCGT_S0_CPU

109 8

PLACE_NEAR=R7410.2:5 MM

XW5910

SM

21

CPUGTVSENSE_IN

PLACE_NEAR=U5000.C5:5.2MM

R5900

4.53K

1/20W

1% MF

201

21

R5910

4.53K

1%

1/20W

MF

201

SMC_CPU_VSENSE

1

C5900

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.C4:5MM

21

SMC_CPUGT_VSENSE

1

C5910

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.C5:5MM

GND_SMC_AVSS

48

OUT

48

OUT

46 47 48 50 51 53 55

Gain: 1 A / 17.123 mV, Range: 67 A. SMC ADC: 22

65

PLACE_NEAR=U5000.B5:5MM

R5901

0

5%

1/20W

MF

0201

LOADISNS

21

1

C5901

2

SMC_CPU_IMON_ISENSEIMON_A_CPUCORE

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U5000.B5:5MM

NOSTUFF

GND_SMC_AVSSGND_SMC_AVSS

CPU GT IMON Current Sense (ICTM)

Gain: 1 A / 21.701 mV, Range: 64 A. SMC ADC: 23

IMON_B_CPUGT SMC_CPUGT_IMON_ISENSE

65

PLACE_NEAR=U5000.A5:5MM

R5911

0

5%

1/20W

MF

0201

LOADISNS

21

1

C5911

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A5:5MM

NOSTUFF

GND_SMC_AVSS

OUT

With R7154 (Ri) set to 365 Ohm, R7210 (Rsen) set to 0.75 mOhm, R7194 set to 100 kOhm, Num Phases (N) is 3, and Io (ICCmax) is 67A, then 1A of Io gives 17.123mV at the Vimon.

46 47 48 50 51 53 55 46 47 48 50 51 53 55

OUT

With R7150 (Ri) set to 432 Ohm, R7410 (Rsen) set to 0.75 mOhm, R7160 set to 100 kOhm, Num Phases (N) is 2, and Io (ICCmax) is 55A,

46 47 48 50 51 53 55

then 1A of Io gives 21.701mV at the Vimon.

48 51

48 53

345678

2 1

GPU CORE Voltage Sense (VG0C)

SMC ADC: 8

(PRODUCTION)

110 92 90

PPVCORE_S0_GPU

PLACE_NEAR=RA651.2:5 MM

XW5980

SM

21

R5980

GPUCOREVSENSE_IN SMC_GPU_CORE_VSENSE

PLACE_NEAR=U5000.A3:5MM

GPU VDDCI Voltage Sense (VG2C)

SMC ADC: 11

(PRODUCTION)

PPVDDCI_S0_GPU

92 110

XW5982

SM

21

GPUVDDCIVSENSE_IN

R5982

4.53K

1%

1/20W

MF

201

4.53K

1%

1/20W

MF

201

21

1

C5981

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A3:5MM

GND_SMC_AVSS

21

SMC_GPU_VDDCI_VSENSE

1

C5983

0.22UF

20%

6.3V

2

X5R 0201

48

OUT

46 47 48 50 51 53 55

48

OUT

D

C

B

A

97

116 110

110

GPU CORE Current Sense (IG0C)

Gain: 122.01x, EDP: 64.2 A Rsense: 2x of 0.00075 (RA651, RA641), Rsum: 0.000375 Vsense: 22.875 mV, Range: 65.57 A SMC ADC: 7

IN

GFXIMVP_ISNS1_P

GFXIMVP_ISNS2_P

LOADISNS

R5920

4.42K

1

0.1%

1/20W

MF

0201

R5921

4.42K

0.1%

1/20W

MF

0201

110 55 53 52 51 50

2

LOADISNS

R5926

21

GFXIMVP_ISNS_R_P

3.65K

1

1/20W

1% MF

201

2

R5927

R5923

IN

GFXIMVP_ISNS1_N

4.42K

1/20W

LOADISNS

0.1% MF

0201

21

3.65K

1

1/20W

1% MF

201

2

LOADISNS

GFXIMVP_ISNS_N

R5924

IN

GFXIMVP_ISNS2_N

4.42K

1/20W

LOADISNS

0.1% MF

0201

21

GFXIMVP_ISNS_R_N

GPU VDDCI Current Sense (IG2C)

Gain: 100x, EDP: 9.7 A

55 53 52 51 50

Rsense: 0.003 (RA368) Vsense: 24 mV, Range: 10 A SMC ADC: 10

94

VDDCIS0_CS_N

IN

VDDCIS0_CS_P

IN

PP3V3_S4SW_SNS

110

3

V+

U5940

5

IN-

4

INA214

SC70

CRITICAL

100x

LOADISNS

GND

2

OUT

REFIN+

GPU 1V8 Current Sense (IG3C)

Gain: 200x, EDP: 2.3 A Rsense: 0.005 (R5950) Vsense: 7.5 mV, Range: 3 A SMC ADC: 12

PP1V8_S0_GPU

OMIT

0306-SHORT

MF

1/3W

1%

0.005

R5950

PP1V8_GPU

52 110 55 53 51 50

PLACE_NEAR=U5950.5:5:10MM

4312

ISNS_GPU1V8_N

ISNS_GPU1V8_P

PLACE_NEAR=U5950.4:3:10MM

PP3V3_S4SW_SNS

5

IN-

4

IN+ REF

U5950

INA210

CRITICAL LOADISNS

200x

PP3V3_S4SW_SNS

GFXIMVP_ISNS_P

1

R5928

715K

0.1% 1/20W MF 0201

2

LOADISNS

NO_XNET_CONNECTION=1

LOADISNS

BYPASS=U5940.3::5MM

1

C5940

0.1UF

10%

6.3V

2

X7R 0201

6

ISNS_GPUVDDCI_IOUT

1

R5940

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5940.6:5MM

LOADISNS

BYPASS=U5950.3::5MM

1

C5950

0.1UF

3

SC70

GND

2

V+

OUT

6

1

10%

6.3V

2

CERM-X5R 0201

ISNS_GPU1V8_IOUT

LOADISNS CRITICAL

U5920

5

ISL28133

1

3

R5929

715K

0.1%

1/20W

MF

0201

SC70-5

V+

V-

2

4

GFXIMVP_ISUM_IOUT

21

LOADISNS

NO_XNET_CONNECTION=1

1

2

LOADISNS

PLACE_NEAR=U5000.A4:5MM

R5941

4.53K

1/20W

1% MF

201

21

1

2

LOADISNS

PLACE_NEAR=U5000.D4:5MM

R5952

4.53K

1

R5951

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5950.6:5MM

1/20W

201

BYPASS=U5920.5::5MM

LOADISNS

1

C5920

0.1UF

10%

6.3V

2

CERM-X5R 0201

LOADISNS

PLACE_NEAR=U5000.A2:5MM

R5931

4.53K

1/20W

R5930

20K

5% 1/20W MF 201

NOSTUFF

PLACE_NEAR=U5920.4:5MM

SMC_GPU_VDDCI_ISENSE

1% MF

201

21

SMC_GPU_CORE_ISENSE

1

C5921

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.A2:5MM

GND_SMC_AVSS

C5941

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U5000.A4:5MM

LOADRC:YES

GND_SMC_AVSS

21

SMC_GPU_1V8_ISENSE

1% MF

1

C5951

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.D4:5MM

LOADRC:YES

GND_SMC_AVSS

GPU SENSORS

48

OUT

55 53 51 50 48 47 46

48

46 47 48 50 51 53 55

48

OUT

46 47 48 50 51 53 55

GPU FB Current Sense (IG1C)

Gain: 100x, EDP: 10.7 A Rsense: 0.002 (RA300) Vsense: 16 mV, Range: 15 A SMC ADC: 13

94

GPUFB_CS_N

IN

GPUFB_CS_P

IN

53 52 51

110

PP3V3_S4SW_SNS

50 55

3

V+

U5960

5

IN-

INA214

SC70

CRITICAL

OUT

100x

4

LOADISNS

GND

2

REFIN+

GPU FB IC Current Sense (IG4C)

PP3V3_S4SW_SNS

5

IN-

4

IN+ REF

U5970

INA210

CRITICAL

LOADISNS

110

Gain: 200x, EDP: 4.8 A Rsense: 0.005 (R5970) Vsense: 10 mV, Range: 3 A SMC ADC: 15

PP1V5R1V35_S0_GPU_IC

OMIT

0306-SHORT

MF

1/3W

1%

0.005

R5970

PP1V5R1V35_S0_GPU_MEM

110 55 53 52 51 50

PLACE_NEAR=U5970.5:5:10MM

4312

ISNS_GPUFBIC_N

ISNS_GPUFBIC_P

PLACE_NEAR=U5970.4:3:10MM

GPU HIGH SIDE Current Sense (IG0R)

Gain: 200x, EDP: 4 A Rsense: 0.002 (R5990) or Rsense SHORT Vsense: 8 mV, Range: 7.5 A SMC ADC: 16

(PRODUCTION)

109

PPBUS_HS_GPU

0612

CYN

1W 1%

432

0.002

109

R5990

PPBUS_G3H

1

CRITICAL

5

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

110 55 53 52 51 50

ISNS_GPU_HS_N

ISNS_GPU_HS_P

C5921,C5941,C5951,C5961,C5971

PP3V3_S4SW_SNS

5

IN-

4

IN+ REF

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U5990

INA210

CRITICAL

200x

BOM_COST_GROUP=SENSORS

1

2

6

ISNS_GPUFB_IOUT

1

3

V+

SC70

OUT

200x

GND

2

3

V+

SC70

GND

2

OUT

LOADISNS

BYPASS=U5960.3::5MM

C5960

0.1UF

10%

6.3V X7R 0201

LOADISNS

PLACE_NEAR=U5000.D3:5MM

R5961

1

R5960

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5960.6:5MM

LOADISNS

BYPASS=U5970.3::5MM

1

C5970

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

ISNS_GPUFBIC_IOUT

1

6

1

LOADRC:NO117S0008

1

R5971

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5970.6:5MM

BYPASS=U5990.3::5MM

1

C5990

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_GPU_HS_IOUT

1

R5991

20K

5% 1/20W MF 201

2

PLACE_NEAR=U5990.6:5MM

GND_SMC_AVSS

4.53K

1/20W

1% MF

201

21

SMC_GPU_FB_ISENSE

1

C5961

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.D3:5MM

LOADRC:YES

GND_SMC_AVSS

LOADISNS

PLACE_NEAR=U5000.A1:5MM

R5972

4.53K

1/20W

PLACE_NEAR=U5000.H4:5MM

1% MF

201

21

SMC_GPU_FBIC_ISENSE

1

C5971

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A1:5MM

LOADRC:YES

GND_SMC_AVSS

R5992

4.53K

1/20W

PAGE TITLE

1% MF

201

21

SMC_GPU_HS_ISENSE

1

C5992

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.H4:5MM

GND_SMC_AVSS

Sensor Extended 3

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

46 47 48 50 51 53 55

48

OUT

46 47 48 50 51 53 55

48

46 47 48 50 51 53 55

48

OUT

46 47 48 50 51 53 55

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

59 OF 145

SHEET

55 OF 121

C

B

SYNC_DATE=05/19/2016SYNC_MASTER=X363_ZIFENGSHEN

A

D

8 7 5 4 2 1

36

345678

2 1

KEEP THE 5 PIN CONNECTOR FROM D1FAN CONNECTOR

D

46

OUT

IN

SMC_FAN_0_TACH

R6001

100K

1/20W

201

SMC_FAN_0_CTL

5% MF

PP3V3_S0

56 110

PP3V3_S0

56 110

D

PP5V_S0

47K

5% MF

201

1

2

SMC_FAN_1_TACH

R6051

100K

1/20W

201

1

5% MF

2

FAN_LT_TACH

46

OUT

115 114 43 115 114 43

FAN_LT_PWM

46

IN

SMC_FAN_1_CTL

R6055

47K

1 2

5%

1/20W

MF

201

1

GS

2

Q6050

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

R6000

1/20W

R6005

47K

1 2

5%

1/20W

MF

201

1

GS

2

Q6000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

R6050

1/20W

47K

5% MF

201

1

BOMOPTION=DBG_FAN

2

CRITICAL

J6000

FAN_RT_TACH

FAN_RT_PWM

FF14A-5C-R11DL-B-3H

NC

NC NC

NC

115 114 43 115 114 43

F-RT-SM

6

1 2 3 4 5

7

518S0769

43 56 110 117

5V DC

GND

PP5V_S0

BOMOPTION=DBG_FAN

FF14A-5C-R11DL-B-3H

NC

NC NC

NC

43 56 110 117

CRITICAL

J6001

F-RT-SM

6

1 2 3 4 5

7

5V DC

GND

518S0769

C

B

C

CARBON_ISOL

R6013

PP3V3_S0_LEFT

56 110

0

1 2

5%

MF

0201

1/20W

C6002

10UF

20%

6.3V

CERM-X5R

0402-1

CARBON

R6010

PP3V3_S0_LEFT56 110

TP6001

TP-P5

A A

1 1

TP-P5

5%

1/20W

100K

12

CARBON_CS

MF

201

TP_CARBON_INT1 TP_CARBON_INT2

TP6002

5

7 6

9 10 11 15

VOLTAGE=3.3V

PP3V3_S0_CARBON_R

1

2

16

1

VDD_IOVDD

U6000

AP6DS2AB

LGA

CS

INT1 INT2

RES RES RES RES

CARBON

GND

12

SCL/SPC

SDA/SDI/SDO

SDO/SA0

13

1

C6000

0.1UF

2

DEN

CAP

10%

16V

X5R-CERM 0201

CARBON

2

CARBON_SCL_R

3

CARBON_SDA_R

4

CARBON_SA0

8

CARBON_DEN

14

CARBON_CAP

1 2

1

C6001

0.01UF

10% 25V

2

X5R-CERM 0201

CARBON

R6012

0

5%

MF

CARBON

R6021

0

1 2

1/20W 0201

R6020

0

1 2

5%

CARBON

R6011

100K

1/20W

0201

CARBON_ISOL

SMBUS_SMC_3_SCL

MF5%

CARBON_ISOL

SMBUS_SMC_3_SDA

MF

02011/20W

12

MF5%

201

49

BI

49

BI

B

A

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

PAGE TITLE

Fans

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=FAN

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 60 OF 145 56 OF 121

A

D

57

114 57 15

PP3V3_SUS

110

SPI_MLB_CS_L SPIROM_USE_MLB

U6101

74LVC1G99

2 3 5 6

SOT833

CRITICAL

B C D

8

VCC

GND

4

OE*

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

BYPASS=U6101::3mm

1

C6101

0.1UF

10% 16V

2

X5R-CERM 0201

57

7

YA

1

SPI_MLBROM_CS_L

PLACE_NEAR=U6100.1:12MM

57

BYPASS=U6100::3mm

C6100

0.1UF

10% 16V

X5R-CERM

0201

SPI_MLB_CLK

SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

1

2

6

1

3

7

8

CRITICAL

VCC

U6100

W25Q64FVZPIG

64MBIT

GND

4

WSON

IO2

IO3

THRM_PAD

CLK

OMIT_TABLE

CS* WP*(IO2) HOLD*(IO3)

9

IO0

DI(IO0)

IO1

DO(IO1)

BYPASS=U6100::3mm

1

C6102

1.0UF

20% 10V

2

X5R-CERM 0201-1

5

SPI_MLB_IO0_MOSI

2

SPI_MLB_IO1_MISO

345678

2 1

SPI+SWD SAM Connector

SAMCONN CRITICAL

J6100

DF40PC-12DP-0.4V-51

PP3V3_G3H

109

57 114 57

57

114 76 64 48 29

114 57

OUT OUT

SPI_ALT_IO0_MOSI SPI_ALT_IO1_MISO

SPI_ALT_IO2_WP_L SPI_ALT_IO3_HOLD_L

SMC_RESET_L

16

M-ST-SM

1314

12 34 56 78 910 1112

15

SPI_ALT_CLK SPI_ALT_CS_L

SPIROM_USE_MLB SMC_TMS SMC_TCK

(SWDIO) (SWCLK)

D

114 57

BI BI

114 57 15

114 47 46

C

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes.

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

SPI Bus Series Termination (Modified per PDG)

PLACE_NEAR=J6100.10:7MM

PLACE_NEAR=J6100.8:8MM

SAMCONN

1

R6133

0

5% 1/20W MF 0201

2

SAMCONN

1

R6132

0

5% 1/20W MF 0201

2

PLACE_NEAR=J6100.6:7MM

PLACE_NEAR=J6100.4:5MM

SAMCONN

1

R6128

0

5% 1/20W MF 0201

2

SAMCONN

1

R6127

0

5% 1/20W MF 0201

2

PLACE_NEAR=J6100.3:7MM

PLACE_NEAR=J6100.5:6MM

SAMCONN

1

R6126

0

5% 1/20W MF 0201

2

SAMCONN

1

R6125

0

5% 1/20W MF 0201

2

SPI_ALT_IO3_HOLD_L SPI_ALT_IO2_WP_L SPI_ALT_IO1_MISO SPI_ALT_IO0_MOSI SPI_ALT_CLK

SPI_ALT_CS_L

C

114 57

Sam Card ROM Slave

B

R6110

22

13

IN

SPI_CS0_R_L

PLACE_NEAR=U1100.AJ24:50MM

R6111

22

13

IN

18 13

BI

CPU Master SPI ROM Slave

SPI_CLK_R

PLACE_NEAR=U1100.AJ26:50MM

SPI_MOSI_R

(SPI_IO<0>)

PLACE_NEAR=U1100.AM23:50MM

1 2

5%

1/20W

MF

201

R6113

22

13

18 13

13

BI

PLACE_NEAR=U1100.AH25:50MM

(SPI_IO<1>)

BI

SPI_IO<2>

PLACE_NEAR=U1100.AM24:50MM

SPI_IO<3>

PLACE_NEAR=U1100.AK24:50MM

R6118

22

1 2

5%

1/20W

MF

201

1 2

5%

1/20W

MF

201

R6119

22

1 2

5%

1/20W

MF

201

1 2

5%

1/20W

MF

201

R6112

22

1 2

5%

1/20W

MF

201

SPI_CS0_L

SPI_CLK

SPI_MOSI

SPI_MISO_RSPI_MISO

SPI_IO2_R

SPI_IO3_R

R6121

22

1 2

5%

1/20W

MF

201

R6123

22

1 2

5%

1/20W

MF

201

R6131

22

1 2

5%

1/20W

MF

201

R6120

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.6:12MM

PLACE_NEAR=U6100.1:12MM

R6122

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.2:12MM

PLACE_NEAR=U6100.5:12MM

R6130

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.7:12MM

PLACE_NEAR=U6100.3:12MM

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_MLB_IO3_HOLD_L

57

B

A

PAGE TITLE

SPI Debug Connector

DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

051-00647

10.0.0 dvt-fab10 61 OF 145 57 OF 121

A

D

345678

2 1

D

C

B

PCH AUDIO

3-MIC CONNECTOR

APN: 518S0818

J6200

FF14A-6C-R11DL-B-3H

F-RT-SM

7

NC

1 2 3 4 5 6

8

NC

PP1V8_S0

58 60 61 109

13

IN

13

IN

13

IN

13

OUT

13

IN

114

PP1V8_S0

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

HDA_SDIN0

HDA_RST_L

DMIC1_DATA

114

DMIC1_CLK

58 60 61 109

DMIC2_DATA

114

DMIC2_CLK

114

U6200.B2:A1:5 MM

1

C6203

0.22UF

10% 10V

2

CERM 402

1 2

R6206

33

1 2

5%

1/20W

MF

201

R6208

33

1 2

5%

1/20W

MF

201

R6203

33

5%

1/20W

MF

201

R6205

0

1 2

5%

1/20W

MF

201

R6207

0

1 2

5%

1/20W

MF

201

U6200.E2:C3:5 MM

1

C6204

0.1UF

10% 25V

2

X5R 0201

PLACE_NEAR=U6200:5MM

8409_HDA_SDIN0_R

PLACE_NEAR=U6200:5MM

8409_DMIC1_DATA

PLACE_NEAR=U6200:5MM

8409_DMIC1_CLK_R

PLACE_NEAR=U6200:5MM

8409_DMIC2_DATA

PLACE_NEAR=U6200:5MM

8409_DMIC2_CLK_R

1

C6201

0.1UF

10% 25V

2

X5R 0201

BYPASS=U6200.C4:C3:5 MM

B1

BCLK

B3

SYNC

A2

SDO

C1

SDI

A3

RST*

D2

DMIC1_DATA

E1

DMIC1_CLK

C2

DMIC2_DATA

D1

DMIC2_CLK

8409_VA_PLL

A6E2B2

VL_DM

VA_PLL

U6200

CS8409

WLCSP

GND_PLL

GNDL

A5

C3

1

2

C4

VL_SP

VL_HD

ASP2_MCLK

ASP2_SCLK

ASP2_LRCK/FSYNC

ASP2_SDIN

ASP2_SDOUT

ASP1_MCLK

ASP1_SCLK

ASP1_LRCK/FSYNC

ASP1_SDIN

ASP1_SDOUT

SPI_SCLK

MOSI

GPIO0/MISO1

GPIO1/CS1* GPIO2/CS2*

GPIO6/SCL

GPIO7/SDA

GPIO3/MISO2

GPIO4 GPIO5

GNDD

A1

U6200.A6:A5:5 MM

C6200

1UF

10% 16V X5R 603

F3

NC

F2

8409_ASP2_SCLK_R

E4

8409_ASP2_LRCLK_R

E3 F4

8409_ASP2_SDOUT_R

B6

NC

C5

8409_ASP1_SCLK_R

D6

8409_ASP1_LRCLK_R

B5

NC

C6

8409_ASP1_SDOUT_R

E6

NC

B4

NC

E5 D5 F5

SPKR_ID0

D4

8409_I2C_SCL

D3

8409_I2C_SDA

F6

NC

F1 A4

1

R6224

47K

5% 1/20W MF 201

2

IN

1

2

114 61

1

2

R6226

1.5K

5% 1/20W MF 201

NO_STUFF

C6288

100PF

5% 25V C0G 0201

ESD

R6280

0

1 2

5%

1/20W

MF

201

R6282

0

1 2

5%

1/20W

MF

201

R6284

0

1 2

5%

1/20W

MF

201

PP1V8_S0

1

R6227

1.5K

5% 1/20W MF 201

2

NO_STUFF

1

2

R6281

0

1 2

5%

1/20W

MF

201

R6283

1 2

1/20W

R6285

1 2

1/20W

C6289

100PF

5% 25V C0G 0201

ESD

0

5% MF

201

0

5% MF

201

PLACE_NEAR=U6200:5MM

8409_ASP2_SCLK

PLACE_NEAR=U6200:5MM

8409_ASP2_LRCLK

PLACE_NEAR=U6200:5MM

8409_ASP2_SDOUT

NOSTUFF

1

C6281

27PF

5% 25V

2

C0G 0201

PLACE_NEAR=U6200:5MM

8409_ASP1_SCLK

PLACE_NEAR=U6200:5MM

8409_ASP1_LRCLK

PLACE_NEAR=U6200:5MM

8409_ASP1_SDOUT

1

C6285

47PF

5% 25V

2

C0G 0201

58 60 61 109

1

C6282

47PF

5% 25V

2

C0G 0201

NOSTUFF

1

C6286

47PF

5% 25V

2

C0G 0201

NOSTUFF

1

C6283

47PF

5% 25V

2

C0G 0201

NOSTUFF

1

C6287

47PF

5% 25V

2

C0G 0201

R6210

33

1 2

5%

1/20W

MF

201

R6213

33

1 2

5%

1/20W

MF

201

R6219

33

1 2

5%

1/20W

MF

201

R6221

33

1 2

5%

1/20W

MF

201

R6223

33

1 2

5%

1/20W

MF

201

R6228

33

1 2

5%

1/20W

MF

201

R6229

33

1 2

5%

1/20W

MF

201

R6230

33

1 2

5%

1/20W

MF

201

R6231

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:10MM

AUD_ASP2_SCLK

R6211

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:10MM

AUD_ASP2_LRCLK

PLACE_NEAR=U6200:10MM

AUD_ASP2_SDOUT

PLACE_NEAR=U6200:10MM

AUD_ASP1B_SCLK

R6220

33

1 2

5%

1/20W

MF

201

R6222

33

1 2

5%

1/20W

MF

201

R6225

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

PLACE_NEAR=U6200:10MM

AUD_ASP1B_LRCLK

PLACE_NEAR=U6200:10MM

AUD_ASP1B_SDOUT

PLACE_NEAR=U6200:10MM

AUD_ASP1A_SCLK

PLACE_NEAR=U6200:10MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6200:10MM

AUD_ASP1A_SDOUT

AUD_I2C_1A_SCL

PLACE_NEAR=U6200:5MM

AUD_I2C_1B_SCL

PLACE_NEAR=U6200:5MM

AUD_I2C_1A_SDA

PLACE_NEAR=U6200:5MM

AUD_I2C_1B_SDA

AUD_ASP2_SDIN

60

OUT

60

BI

59

OUT

D

59

OUT

AUDIO JACK CODEC

59

IN

59

OUT

61

OUT

RIGHT SPEAKER AMPS

61

OUT

61

OUT

C

60

OUT

LEFT SPEAKER AMPS

60

OUT

60

OUT

61 59

B

61 59

A

R6290

47K

5%

1/20W

MF

201

PP1V8_S0

47K

5%

1/20W

MF

201

1

2

1

2

R6291

AUD_SPKRAMP_RESET_L

58 60 61 109

AUD_CODEC_INT_L

AUD_CODEC_RESET_L

AUD_SPKRAMP_INT_L

OUT

59

IN

59

IN

61 60

SYNC_MASTER=X363_AUDIO SYNC_DATE=01/11/2016

PAGE TITLE

A

HDA Bridge

DRAWING NUMBER SIZE

BOM_COST_GROUP=AUDIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

62 OF 145

SHEET

58 OF 121

D

8 7 5 4 2 1

36

AUDIO JACK CODEC I2C ADDRESS AD1 GND GND

GND

1.8V

AD0

1.8V GND

1.8V

ADDRESS

0x48 <-0x49 0x4A 0x4B

AUD_PWR_EN

12

345678

L6361

FERR-470-OHM

1

0201

2

2 1

L83_LDO_EN

D

C

B

62

117

PP1V8_S0_LDO_AUD

59

GND_AUDIO_CODEC

L6300

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

CRITICAL

1

C6301

2.2UF

10% 10V

2

X5R-CERM 0402

BYPASS=U6300.B1:C2:5 MM

110 59

PP3V3_S0

L6360

FERR-22-OHM-1A-0.055OHM

PP3V3_S0_AUD_F

1

0201

BYPASS=U6360.A1:B2:3 MM

2

CRITICAL

1

C6360

2

1.0UF

20% 10V X5R-CERM 0201-1

4

IN

3

EN

NOSTUFF

1

R6360

100K

5% 1/20W MF 201

2

XW6300

SHORT-8L-0.25MM-SM

1

2

U6360

NCP160AMX180

XDFN-COMBO

EPADGND

5

2

OUT

1

PP1V8_S0_LDO_AUD

CRITICAL

1

C6361

1.0UF

20% 10V

2

X5R-CERM 0201-1

GND_AUDIO_CODEC

VOLTAGE=1.8V

59

BYPASS=U6360.A2:B2:3 MM

117 59

D

FERR-22-OHM-1A-0.055OHM

1

0201

2

L83_VCP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

L6301

FERR-22-OHM-1A-0.055OHM

PP1V8_S0_LDO_AUD

59

BYPASS=U6300.A3:B3:5 MM

62

OUT

NO_XNET_CONNECTION=1

59 117

NO_XNET_CONNECTION=1

62

OUT

CRITICAL

IN

AUD_HS_MIC_P

C6352

27PF

IN

AUD_HS_MIC_N

0201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

AUD_HP_PORT_L

R6300

GND_AUDIO_CODEC

R6301

AUD_HP_PORT_R

R6351

5% 25V C0G

2.2K

2

1/20W

1

2

R6352

2.2K

2

1/20W

1% MF

201

1% MF

201

1

1K

5%

1/20W

MF

201

1K

5%

1/20W

MF

201

2

1

2

110 59

C6321 C6322

CRITICAL

10% 10V

0201

1

2

C6351

3300PF

X7R-CERM

R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS

(SEE RADAR # 6210118)

1

R6350

100K

5% 1/20W MF 201

2

PLACE_NEAR=U6300:10mm

PP3V3_S0

62

IN

62

IN

62

BI

PLACE_NEAR=U6300:10mm

470PF

PLACE_NEAR=U6300:10mm

470PF

62

BI

FERR-22-OHM-1A-0.055OHM

BYPASS=U6300.D7:C7:5 MM

AUD_HP_SENSE_L

AUD_HP_SENSE_R

AUD_HP_PORT_CH_GND

NOSTUFF

1

2

X5R-X7R

16V

10%

1

10%

NOSTUFF

X5R-X7R

16V

2

AUD_HP_PORT_US_GND

HS_MIC_P

HS_MIC_N

AUD_RING_SENSE

62

IN

1

R6310

0

5% 1/20W MF 201

2

BYPASS=U6300.F3:E3:5 MM

1

0201

L6302

1

0201

201

AUD_TIP_SENSE

CRITICAL

C6309

4.7UF

2

1

20%

6.3V X5R 402

2

CRITICAL

C6303

0.1UF

2

CRITICAL

C6304

X5R-CERM

0402-7

C6320

560PF

5% 25V C0G

0201

L83_HSBIAS_FILT

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

L83_HSBIAS_FILT_REF

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

L83_VL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

1

10% 50V

2

X7R

603-1

L83_VP

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1000

1

10UF

20% 10V

2

1

PLACE_NEAR=U6300:10mm

NOSTUFF

2

VP

D5

HPSENSA

E5

HPOUTA

F5

HPSENSB

G5

HPOUTB

F1

HS4

E2

HS_CLAMP2

E1

HSIN+

G2

HS3

F2

HS_CLAMP1

D1

HSIN-

F4

HS4_REF

G4

HS3_REF

G3

RING_SENSE

E4

TIP_SENSE

F3

HSBIAS_FILT

E3

HSBIAS_FILT_REF

NC

A3

D7

VL VA VCP

A7

VD_FILT

CRITICAL

B1

U6300

CS42L83A

WLCSP-SKT

APN:338S00142

GNDL

B3

B6

C7

GNDHS GNDAGNDD

G1

D6

+VCP_FILT

-VCP_FILT GNDCP

VL_SEL

DIGLDO_PDN*

INT*

WAKE*

RESET*

SPDIF_TX

SWIRE_SEL

ASP_LRCK/FSYNC

SWIRE_SD/ASP_SDIN

ASP_SDOUT

SWIRE_CLK/ASP_SCLK

AD0 AD1

SDA

SCL

FLYP FLYC FLYN

FILT_P

D2

C2

L83_VCP_FILTP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

L83_VCP_FILTN

E6 G6

F6 C4 D4 B7 C6

C5

A6

NC

D3 B5 A5 A4

B4

C3 B2

A1 A2 E7 F7 G7

C1

L83_FILTP

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

AUD_CODEC_WAKE_L

L83_SDOUT_R

AUD_I2C_1B_SDA AUD_I2C_1B_SCL

OMIT_TABLE

L83_FLYP L83_FLYC L83_FLYN

1

2

C6302

2.2UF

1

10% 10V

X5R-CERM

0402

C6305

4.7UF

1

10% 10V X5R

0402

C6306

4.7UF

10% 10V X5R

0402

<RDAR://PROBLEM/22033298>

CRITICAL

2

BYPASS=U6300.E6:F6:5 MM

2

BYPASS=U6300.G6:F6:5 MM

21

R6304

0

1

5%

1/20W

MF

201

BYPASS=U6300.E7:F7:5 MM

61

58

BI

58

IN

CRITICAL

61

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

C6310

10UF

20% 10V X5R 0603

BYPASS=U6300.C1:C2:5 MM

BYPASS=U6300.D6:F6:5 MM

XW6301

SHORT-8L-0.25MM-SM

GND_VCP

1

R6302

47K

5% 1/20W MF 201

2

PLACE_NEAR=U6300:5mm

2

L83_SDOUT

CRITICAL

C6307

2.2UF

10% 10V

X5R-CERM

0402

C6308

2.2UF

1

10% 10V

X5R-CERM

0402

CRITICAL

21

2

PP3V3_S0

R6303

100K

1

1/20W

BYPASS=U6300.G7:F7:5 MM

2

1% MF

201

NOSTUFF

1

C6380

47PF

5% 25V

2

C0G 0201

59 110

R6306

33

1

5%

1/20W

MF

201

AUD_CODEC_INT_L

AUD_CODEC_RESET_L

AUD_ASP2_LRCLK

AUD_ASP2_SDOUT

PLACE_NEAR=U6300:10MM

2

AUD_ASP2_SDIN

AUD_ASP2_SCLK

OUT

IN

OUT

IN

58

C

B

A

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

59 117

SYNC_MASTER=X363_AUDIO

PAGE TITLE

AUDIO JACK CODEC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

138S0719

2 CAP,CER,4.7UF,20%,10V,X5R,0402,MURATA

C6305,C6306

8 7 5 4 2 1

CRITICAL

BOM_COST_GROUP=AUDIO

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 63 OF 145 59 OF 121

SYNC_DATE=01/25/2016

D

A

2X MONO SPEAKER AMPLIFIER

APN: 353S00604 0dBFS = 9VPK

345678

2 1

D

61 58

OUT

IN

AUD_SPKRAMP_INT_L

AUD_SPKRAMP_RESET_L

5%

1/20W

MF

201

1

58 60

2

58 60

R6401

100K

VREF_AMP_WL

BYPASS=U6400.E4:C4:5 MM

PP1V8_S0

58 60 61 109

BYPASS=U6400.A4:B4:5 MM

60 58

PLACE_NEAR=U6400:5MM

IN

AUD_ASP1A_SCLK

PLACE_NEAR=U6400:5MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6400:5MM

AUD_ASP1A_SDOUT

R6402

0

1 2

5%

1/20W

MF

201

R6405

0

1 2

5%

1/20W

MF

201

R6403

1 2

0

5%

1/20W

MF

201

BI

AUD_I2C_1A_SCL

IN

AUD_I2C_1A_SDA

SPKRAMP_WL_SCLK

SPKRAMP_WL_LRCLK

SPKRAMP_WL_SDIN

1

2

1

C6400

1.0UF

20% 10V

2

X5R-CERM 0201-1

C6405

1.0UF

20% 10V X5R-CERM 0201-1

D5 A6

B6 E5 E6 C6 D6

NC

C5

DVDD

IRQ* SCL

SDA RESET* BCLK LRCLK DIN DOUT

AGND

C4

E4

A4

VREFC

MAX98706

CRITICAL

DGND

D4

A2E2A3

PVDD

U6400

WLP

B4

B3

PGND

C1C2C3

BYPASS=U6400.E3:D3:5 MM

1

2

E3

OUTPSNS

OUTP

OUTN

OUTNSNS

ADDR0 ADDR1

D3

BYPASS=U6400.A3:B3:5 MM

C6401

0.1UF

10% 16V X7R-CERM 0402

E1 D1 D2 B1 B2 A1

B5 A5

PP1V8_S0

1

2

SPKRAMP_WL_OUT_POS

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

SPKRAMP_WL_OUT_NEG

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

I2C ADDRESS = 0x31

BYPASS=U6400.E2:C2:10 MM

C6402

0.1UF

10% 16V X7R-CERM 0402

1

2

58 60 61 109

BYPASS=U6400.A2:C2:10 MM

1

C6403

10UF

20% 35V X5R-CERM 0603

C6404

10UF

20% 35V

2

X5R-CERM 0603

L6400

180OHM-3.4A

1 2

L6401

180OHM-3.4A

0806

1

C6480

100UF

20% 20V

2

POLY SM-1

PPBUS_G3H

1

C6481

100UF

20% 20V

2

POLY SM-1

114

SPKRCONN_WL_OUT_POS

SPKRCONN_WL_OUT_NEG

114

1

C6406

220PF

5% 25V

2

C0G-CERM 0402

60 61 109

1

C6407

220PF

5% 25V

2

C0G-CERM 0402

APN: 518S00521

J6410

78171-0004

M-RT-SM

5

1 2 3 4

6

D

LEFT SPEAKER CONNECTOR

C

B

60 58

C

VREF_AMP_TL

BYPASS=U6450.E4:C4:5 MM

PP1V8_S0

58 60 61 109

BYPASS=U6450.A4:B4:5 MM

60 58

IN

60 58

PLACE_NEAR=U6450:5MM

IN

AUD_ASP1A_SCLK

PLACE_NEAR=U6450:5MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6450:5MM

AUD_ASP1A_SDOUT

R6452

0

1 2

5%

1/20W

MF

201

R6455

0

1 2

5%

1/20W

MF

201

R6453

1 2

0

5%

1/20W

MF

201

BI

AUD_I2C_1A_SCL

AUD_I2C_1A_SDA

SPKRAMP_TL_SCLK

SPKRAMP_TL_LRCLK

SPKRAMP_TL_SDIN

1

2

1

C6450

1.0UF

20% 10V

2

X5R-CERM 0201-1

C6455

1.0UF

20% 10V X5R-CERM 0201-1

D5 A6

B6 E5 E6 C6 D6

NC

C5

DVDD

IRQ* SCL

SDA RESET* BCLK LRCLK DIN DOUT

AGND

C4

E4

A4

VREFC

MAX98706

CRITICAL

DGND

D4

A2E2A3

PVDD

U6450

WLP

B4

B3

PGND

C1C2C3

BYPASS=U6450.E3:D3:5 MM

1

2

E3

OUTPSNS

OUTP

OUTN

OUTNSNS

ADDR0 ADDR1

D3

BYPASS=U6450.A3:B3:5 MM

C6451

0.1UF

10% 16V X7R-CERM 0402

E1 D1 D2 B1 B2 A1

B5 A5

1

2

SPKRAMP_TL_OUT_POS

SPKRAMP_TL_OUT_NEG

I2C ADDRESS = 0x32

BYPASS=U6450.E2:C2:10 MM

C6452

0.1UF

10% 16V X7R-CERM 0402

1

C6453

2

BYPASS=U6450.A2:C2:10 MM

PPBUS_G3H

1

C6454

10UF

20% 35V X5R-CERM 0603

10UF

20% 35V

2

X5R-CERM 0603

L6450

180OHM-3.4A

1 2

L6451

180OHM-3.4A

0806

60 61 109

114

SPKRCONN_TL_OUT_POS

SPKRCONN_TL_OUT_NEG

1

C6456

220PF

5% 25V

2

C0G-CERM 0402

1

C6457

220PF

5% 25V

2

C0G-CERM 0402

B

A

PAGE TITLE

AUDIO Speaker Amps & Conn

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 64 OF 145 60 OF 121

SYNC_DATE=01/25/2016SYNC_MASTER=X363_AUDIO

A

D

2X MONO SPEAKER AMPLIFIER

APN: 353S00604 0dBFS = 9VPK

345678

2 1

D

C

60 58

OUT

IN

AUD_SPKRAMP_INT_L

AUD_SPKRAMP_RESET_L

61 58

BYPASS=U6500.E2:C2:10 MM

PPBUS_G3H

60 61 109

VREF_AMP_TR

BYPASS=U6500.E3:D3:5 MM

BYPASS=U6500.A3:B3:5 MM

BYPASS=U6500.A2:C2:10 MM

D

1

C6502

0.1UF

10% 16V

2

X7R-CERM 0402

SPKRAMP_TR_OUT_POS

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

SPKRAMP_TR_OUT_NEG

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

PP1V8_S0

I2C ADDRESS = 0X3A

D3

1

C6501

0.1UF

10% 16V

2

X7R-CERM 0402

E1 D1 D2 B1 B2 A1

B5 A5

BYPASS=U6500.E4:C4:5 MM

PP1V8_S0

58 60 61 109

BYPASS=U6500.A4:B4:5 MM

61 59 58

PLACE_NEAR=U6500:5MM

IN

AUD_ASP1B_SCLK

PLACE_NEAR=U6500:5MM

AUD_ASP1B_LRCLK

PLACE_NEAR=U6500:5MM

AUD_ASP1B_SDOUT

R6502

0

1 2

5%

1/20W

MF

201

R6505

0

1 2

5%

1/20W

MF

201

R6503

1 2

1/20W

0

5% MF

201

IN

BI

AUD_I2C_1B_SCL AUD_I2C_1B_SDA

SPKRAMP_R_SCLK

SPKRAMP_R_LRCLK

SPKRAMP_R_SDIN

1

2

1

C6500

1.0UF

20% 10V

2

X5R-CERM 0201-1

C6505

1.0UF

20% 10V X5R-CERM 0201-1

D5 A6

B6 E5 E6 C6 D6

NC

C5

DVDD

IRQ* SCL

SDA RESET* BCLK LRCLK DIN DOUT

AGND

C4

E4

A4

VREFC

MAX98706

CRITICAL

DGND

D4

A2E2A3

PVDD

U6500

WLP

B4

B3

E3

OUTPSNS

OUTP

OUTN

OUTNSNS

ADDR0 ADDR1

PGND

C1C2C3

1

C6503

10UF

20% 35V

2

X5R-CERM 0603

114 109 61

1

C6504

10UF

20% 35V

2

X5R-CERM 0603

CRITICAL

FL6500

180OHM-3.4A

1 2

0806

CRITICAL

FL6501

180OHM-3.4A

0806

1

C6580

100UF

20% 20V

2

POLY SM-1

114

SPKRCONN_TR_OUT_POS

114

SPKRCONN_TR_OUT_NEG

1

C6506

220PF

5% 25V

2

C0G-CERM 0402

1

C6581

100UF

20% 20V

2

POLY SM-1

1

C6507

220PF

5% 25V

2

C0G-CERM 0402

114 58

OUT

SPKR_ID0

APN: 518S0672

J6500

78171-6006

M-RT-SM

7

1 2 3 4 5 6

8

RIGHT SPEAKER CONNECTOR

C

B

61 58

VREF_AMP_WR

BYPASS=U6550.E4:C4:5 MM

PP1V8_S0

58 60 61 109

BYPASS=U6550.A4:B4:5 MM

61 59 58

PLACE_NEAR=U6550:5MM

IN

AUD_ASP1B_SCLK

PLACE_NEAR=U6550:5MM

AUD_ASP1B_LRCLK

PLACE_NEAR=U6550:5MM

AUD_ASP1B_SDOUT

R6552

0

1 2

5%

1/20W

MF

201

R6555

0

1 2

5%

1/20W

MF

201

R6553

1 2

1/20W

0

5% MF

201

IN

BI

AUD_I2C_1B_SCL AUD_I2C_1B_SDA

SPKRAMP_WR_SCLK

SPKRAMP_WR_LRCLK

SPKRAMP_WR_SDIN

1

2

1

C6550

1.0UF

20% 10V

2

X5R-CERM 0201-1

C6555

1.0UF

20% 10V X5R-CERM 0201-1

D5 A6

B6 E5 E6 C6 D6

NC

C5

DVDD

IRQ* SCL

SDA RESET* BCLK LRCLK DIN DOUT

AGND

C4

E4

A4

VREFC

MAX98706

CRITICAL

DGND

D4

A2E2A3

PVDD

U6550

WLP

B4

B3

E3

PGND

C1C2C3

BYPASS=U6550.E3:D3:5 MM

1

2

OUTPSNS

OUTP

OUTN

OUTNSNS

ADDR0 ADDR1

D3

E1 D1 D2 B1 B2 A1

B5 A5

BYPASS=U6550.A3:B3:5 MM

C6551

0.1UF

10% 16V X7R-CERM 0402

1

C6552

0.1UF

10% 16V

2

X7R-CERM 0402

SPKRAMP_WR_OUT_POS

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

SPKRAMP_WR_OUT_NEG

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

PP1V8_S0

I2C ADDRESS = 0X39

BYPASS=U6550.A2:C2:10 MM

1

2

BYPASS=U6550.E2:C2:10 MM

C6553

10UF

20% 35V X5R-CERM 0603

1

C6554

10UF

20% 35V

2

X5R-CERM 0603

CRITICAL

FL6550

180OHM-3.4A

1 2

CRITICAL

1 2

FL6551

180OHM-3.4A

114 109 61

0806

PPBUS_G3H

114

SPKRCONN_WR_OUT_POS

114

SPKRCONN_WR_OUT_NEG

1

C6556

220PF

5% 25V

2

C0G-CERM 0402

60 61 109

1

C6557

220PF

5% 25V

2

C0G-CERM 0402

B

A

PAGE TITLE

AUDIO Speaker Amps & Conn

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 65 OF 145 61 OF 121

SYNC_DATE=01/25/2016SYNC_MASTER=X363_AUDIO

A

D

345678

2 1

D

C

59

IN

OUT

AUD_HP_PORT_L

AUD_HP_PORT_R

AUD_HP_PORT_US_GND

AUD_HP_PORT_CH_GND

AUD_HP_SENSE_L

AUD_HP_SENSE_R

CRITICAL

FL6601

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6600

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6603

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6605

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6606

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6607

120-OHM-25%-1.3A

1 2

0402

114 62

114

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

AUD_CONN_RING2

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000

AUD_CONN_SLEEVE

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000

AUD_CONN_HP_SENSE_L

114

AUD_CONN_HP_SENSE_R

Audio Jack Flex Connector

APN: 510S0009

(Matching plug APN: 510S0010)

J6600

51138-0274

F-ST-SM

22 21

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

NC

19 20

23 24

AUD_CONN_HP_LEFT

AUD_CONN_HP_RIGHT

AUD_CONN_RING2

AUD_CONN_SLEEVE

D

C

114 62

B

59

OUT

AUD_TIP_SENSE

AUD_HS_MIC_P

AUD_HS_MIC_N

R6600

2K

1 2

1%

1/20W

MF

201

CRITICAL

FL6602

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6604

120-OHM-25%-1.3A

1 2

0402

114

AUD_CONN_TIP_SENSE

114

AUD_CONN_SLEEVE_XW

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

114

AUD_CONN_RING2_XW

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000

B

A

PAGE TITLE

AUDIO JACK CONNECTOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 66 OF 145 62 OF 121

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

A

D

J80 Battery Hotbar Flex Pads 998-03902

Flex Pad TO MLB 998-03780.

345678

2 1

D

OMIT_TABLE

CRITICAL

J6950

PWR-MLB-X363

HB-SM

10

9

8

3

2

7 1

6

5

4

17

16

15

14

13

12

11

C6950

0.1UF

10% 25V X5R 402

PPVBAT_G3H_CONN

1

2

C6960

1UF

10% 25V X5R

603-1

APN:518S0818

D

J6951

FF14A-6C-R11DL-B-3H

114 64

1

2

F-RT-SM

7

NC

1 2 3 4 5 6

8

NC

SYS_DETECT_L

114

1

R6950

10K

5% 1/16W MF-LF 402

2

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

TP_BMON_IOUT

D6950

RCLAMP3552T

SLP1006N3T

49

BI

49

BI

114

OUT

1

2

CRITICAL

3

C

BMU POWER FLEX HOTBAR'd TO THE MLB:

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

632-00862 PCBA,FLEX,BMU PWR,X3631 J6950 CRITICAL

FROM USB-C SOURCE

116 114 64

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=8.6V

B

PPBUS_G3H

109

R6920

0

1 2

5% 1/16W MF-LF

402

R6907

2.2

1 2

5%

1/8W

MF-LF

805

PPDCIN_G3H_CHGR_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=8.6V

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V

D6902

BAT30CWFILM

SOT-323

1

3

2

64

PM_EN_P3V3_G3H

64

PPVIN_G3H_P3V3G3H

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=8.6V

R6921

1 2

0

5%

1/20W

MF

201

1

C6905

2.2UF

20% 35V

2

X5R-CERM 0402

1

C6906

2

PM_EN_P3V3_G3H_R

1

TP6910

TP

TP-P5

2.2UF

20% 35V X5R-CERM 0402

NC

U6903

MAX77596

2

SUP

7

MODE

10

EN

6

RESET* BIAS

TDFN

CRITICAL

PGND

EPAD

11

AGND

5

4

BST

LX

OUT/FB

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

1 3

9 8

P3V3G3H_VBST P3V3G3H_LX

P3V3G3H_FB P3V3G3H_BIAS

DIDT=TRUE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

P3V3G3H_VBST_R

1

R6908

0

5% 1/20W MF 0201

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

SWITCH_NODE=TRUE

1

C6907

0.1UF

10% 16V

2

X5R-CERM 0201

DIDT=TRUE

CRITICAL

L6900

10UH-20%-1.4A-0.399OHM

1 2

PIYA25201B-SM

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200

VOLTAGE=3.3V

R6910

115K

1 2

0.1%

1/20W

MF

0201

C6911

5.6PF

PP3V3_G3H_REG_R

1

R6912

10

5% 1/20W MF 201

2

12

P3V3G3H_FB_RC

1

C6912

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C6913

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

R6923

0

1 2

5% 1/10W MF-LF

603

1

C6914

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

PP3V3_G3H

1

C6915

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C6916

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

109

1

C6917

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

C6919

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

C6919 FOR DESENSE

B

A

XW6900

SM

1 2

1

C6910

0.33UF

10% 16V

2 0201

CERM-X7R 603

R6911

47K

0.1% 1/20W MF

2

P3V3G3H_FB_R

1

R6913

1.47K

1% 1/20W MF 201

2

P3V3G3H_AGND

+/-0.1PF

25V C0G

0201

BOM_COST_GROUP=PLATFORM POWER

SYNC_MASTER=J80_MLB

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=11/06/2015

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

69 OF 145

SHEET

63 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

116 114 50 29

CRITICAL

1

C7042

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

1

2

FROM USB-C SOURCE

PPDCIN_G3H

64

114 64

48 64

TBA_GATE_Q1

TBA_GATE_Q2

TBA_GATE_Q3

TBA_GATE_Q4

TBA_LX1

TBA_LX2

SMC_CHGR_INT_L

CRITICAL

C7043

6.8UF

20% 35V-0.09OHM POLY-TANT CASE-B1-2-SM

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

1

TP

TP-P5

CRITICAL

1

C7024

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

TP7001

TP7002

TP7003

TP7004

TP7005

TP7006

TP7007

64 63

CRITICAL

1

C7025

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

PP3V3_G3H

109

C7080

X5R-CERM

PPVIN_G3H_P3V3G3H

PLACE_NEAR=U7000.A5:2MM

C7081

X5R-CERM

1.0UF

20% 10V

0201-1

2.2UF

20% 35V

0402

CRITICAL

1

C7026

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

1

2

1

2

8X B1

1

2

NO STUFF

C7016

0.01UF

10% 25V

X5R-CERM

0201

R7009

100K

1/20W

201

CRITICAL

C7027

6.8UF

20% 35V-0.09OHM POLY-TANT CASE-B1-2-SM

0.047UF

1

R7015

750K

2

1

2

1

5% MF

2

CRITICAL

1

C7028

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7029

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

(AMON)

R7020

0.01

0.5%

0.5W MF

0306

12 34

TBA_CSI_R_P TBA_CSI_R_N

R7021

1.00

1/20W MF-LF

TBA_CSI_P

C7021

10% 50V

CER-X7R

0402

1% 1/20W MF 201

1%

0201

1

2

1

2

1

R7022

1.00

1% 1/20W MF-LF 0201

2

TBA_CSI_N

1

C7022

0.047UF

10% 50V

2

CER-X7R 0402

TBA_AUX_DET

1

R7016

255K

1% 1/20W MF 201

2

49

48

SMBUS_SMC_5_G3_SDA

BI

SMBUS_SMC_5_G3_SCL

IN

SMC_4FINGERS_RST

IN

114

HPWR_EN_L

C7023

0.47UF

12

PLACE_NEAR=U7000.C5:1MM

20%

4V

CERM-X5R-1

201

PPVIN_G3H_P3V3G3H

63 64

TBA_COMP

NO STUFF

C7070

0.12UF

10%

10.0V

CERM-X5R

402

1

2

1

C7071

0.12UF

10%

10.0V

2

CERM-X5R 402

116 114 63

Q7030

FDMD8800

114

B5 C5 D5

A5 D3

B2 C2

E4

F5 G5 H5 G2 G3

E5 G4

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

2

1

D1

DFN

C7032

2.2UF

20% 35V X5R-CERM 0402

2

3

13

G1 12

1

C7033

2.2UF

20% 35V

2

X5R-CERM 0402

PLACE_NEAR=Q7030.2:1MM

7

8

9

S1/D2

G1R 11

TBA_GATE_Q1

TBA_LX1

1

2

1

R7030

0

2

R7075

1 2

TBA_VDDA

1

C7075

2.2UF

20% 25V

2

X6S-CERM 0402

BOMOPTION=OMIT_TABLE

TBA_VDDP

A2

D2

VDDP

VDDA

U7000

P_IN CSIN CSIP MPM_PBUS AUX_DET

SGATE AGATE

MPM_DET VR1_3P3

SDA SCL

SMC_RST_IN

HPWR_EN* COMP

CELL

ISL9239

WCSP-1

PGND

AGND

E3

E2

2.7UH-20%-21.5A-0.0135OHM

TBA_PHASE1

10

5

6

14

S2

G2 4

TBA_GATE_Q2

C7030

0.1UF

10% 25V X7R-CERM 0402

TBA_BOOT1_RC

5% 1/16W MF-LF 402

TBA_BOOT1

4.7

5%

1/20W

MF

201

C7077

10UF

X5R-CERM

GATE_Q1

GATE_Q2 GATE_Q3

GATE_Q4

SMC_RST*

MPM_OK

1

20% 25V

2

0603

BOOT1

LX1

LX2

BOOT2

PBUS CSOP CSON

BGATE

VBAT

EN_VR1

IRQ*

CBC_ON

AUX_OK

AMON BMON

H1 F1 G1 E1 D1 B1 C1 A1 A3 A4 B4 B3 C3 F2 H4 H3 H2 F4 F3 D4 C4

1

C7034

2.2UF

20% 35V

2

X5R-CERM 0402

PLACE_NEAR=Q7030.1:3mm

BOMOPTION=OMIT_TABLE

1

C7035

2.2UF

20% 35V

2

X5R-CERM 0402

L7030

1 2

IHLP4040CZ-PIMA103T-SM-COMBO

CRITICAL

TBA_GATE_Q3

PM_EN_P3V3_G3H

SMC_CHGR_INT_L

NC

IND,MLD,2.7UH,16A,14.8MO,10.9x10.0x3.00152S00199 1 CRITICAL

TBA_PHASE2

9

10

5

6

14

S2

G2 4

114 64

C7040

X7R-CERM

TBA_LX2

0.1UF

10% 25V

0402

1

2

TBA_BOOT2_RC

0

5% 1/16W MF-LF

402

1

2

R7040

TBA_BOOT2

SMC_RST_L

SMC_CBC_ON

SMC_BC_ACOK

CHGR_AMON CHGR_BMON

8

OUT

OUT OUT

OUT OUT OUT

7

S1/D2

G1R 11

63

46

48

CRITICAL

1

C7050

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

1

2

3

13

D1

DFN

G1 12

TBA_GATE_Q4

(PBUS)

0.047UF

64 48

114 50

L7030

1

2

114

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

Q7040

FDMD8800

(BMON)

TBA_CSO_R_P

1% 1/20W MF-LF

0201

1

2

R7061

1.00

TBA_CSO_P

C7061

CER-X7R

R7090

100K

1 2

1/20W

201

1

10% 50V

2

0402

PLACE_NEAR=U7000.A4:1MM

5% MF

CRITICAL

C7051

68UF

20% 16V POLY-TANT CASE-D2E-SM

CRITICAL

R7060

0.005

1% 1W MF

0612-5

12 34

TBA_CSO_R_N

C7020

0.47UF

12

20%

4V

CERM-X5R-1

201

SMC_RESET_L

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BOM_COST_GROUP=PLATFORM POWER

4X D2

CRITICAL

1

C7052

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

20% 25V X5R

1

2

C7066

2.2UF

0402-1

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

R7062

1.00

1% 1/20W MF-LF 0201

2

TBA_CSO_N

1

C7062

0.047UF

10% 50V

2

CER-X7R 0402

OUT

CRITICAL

1

C7056

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

C7069

2.2UF

0402-1

114 76 57 48 29

1

20% 25V

2

X5R

C7064

1000PF

1 2

0201

1

2

CRITICAL

F7000

12AMP-32V

1 2

CRITICAL

F7001

12AMP-32V

1 2

C7067

CRITICAL

Q7065

SI7137DP

3

S

2 1

G

10% 25V X7R

C7053

2.2UF

20% 25V X5R 0402-1

1

C7055

2.2UF

20% 25V

2

X5R 0402-1

1

C7057

2.2UF

20% 25V

2

X5R 0402-1

TO SYSTEM

PPBUS_G3H

1206

0.1UF

10% 25V X5R

0201

SO-8

SYM-VER-2

4

1

C7068

0.01UF

2

X5R-CERM

TO/FROM BATTERY

5

D

1

10% 25V

2

0201

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

PLACE_NEAR=Q7065.5:2MM

1

C7060

0.1UF

10% 25V

2

X5R 0201

TBA_BGATE

1

C7063

4700PF

10% 25V

2

CER-X5R 0201

PAGE TITLE

PBUS Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

C7058

2.2UF

20% 25V

2

X5R 0402-1

109 116

114 63

1

C7054

1000PF

10% 25V

2

X7R 0201

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

70 OF 145

SHEET

64 OF 121

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

9 8

8

68 65

67 65

9 8

IN

8

CPU_VCCGTSENSE_P

CPU_VCCGTSENSE_N

CPUGT_ISUMP

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISEN2

IN

CPUSA_ISUMP

CPUSA_ISUMN

CPU_VCCSASENSE_P

CPU_VCCSASENSE_N RTN_C_CPUSA

68

IN

67

IN

R7160

100K

1 2

1%

1/20W

MF

201

R7190

C7154

0.01UF

X7R-CERM

C7160

150PF

CER-C0G

C7181

220PF

10% 25V

X7R-CERM

201

C7182

0.01UF

10% 10V

X7R-CERM

0201

100K

1/20W

1% MF

201

12

1

10% 10V

2

0201

IMON_B_CPUGT

12

5%

50V

0201

1

2

R7181

1 2

1/20W

1

2

C7190

150PF

12

5%

50V

CER-C0G

0201

C7153

0.01UF

X7R-CERM

1K

1%

MF

201

0201

10% 25V

201

10% 16V X7R

1

2

1

2

1

2

C7141

330PF

C7151

220PF

X7R-CERM

10% 10V

0201

R7180

499

1%

1/20W

MF

201

SA_ISUMN_R

IMON_C_CPUSA

C7171

330PF

10% 16V X7R

0201

1 2

1

2

65 55

12

1

2

R7142

0

5%

1/20W

MF

201

1

C7142

330PF

10% 16V

2

X7R 0201

R7151

1 2

1/20W

C7152

0.01UF

10% 10V X7R-CERM 0201

R7172

0

1 2

5%

1/20W

MF

201

1

C7172

330PF

10% 16V

2

X7R 0201

FB_GT_R

C7144

3300PF

X7R-CERM

XW7140

SM

1 2

R7150

432

1%

1/20W

MF

201

1K

GT_ISUMN_R

1% MF

201

C7161

6800PF

10% 10V

X7R-CERM

0201

C7180

3300PF

1 2

10% 10V

X7R-CERM

0201

65

FB_SA_R

XW7170

SM

1 2

R7143

3.01K

1 2

1%

1/20W

MF

201

12

FB_B_GT_R

10% 10V

0201

RTN_B_CPUGT

12

CPU VCC GT + GTx Merged

C7162

68PF

25V C0G

12

0201

COMP_B_CPUGT_L

CPUSA_ISUMN_R

C7191

6800PF

X7R-CERM

R7173

C7174

2200PF

12

FB_C_SA_R

10% 10V

X7R-CERM

0201

C7150

3300PF

1 2

10% 10V

X7R-CERM

0201

12

5%

12

COMP_C_CPUSA_L

10% 10V

0201

2.49K

1/20W

1% MF

201

12

R7144

1K

12

1%

1/20W

MF

201

65

109

CPUGT_ISUMN_R

COMP_B_CPUGT

R7161

4.64K

12

1%

1/20W

MF

201

CPU VCC SA

65

C7192

150PF

12

5%

50V

CER-C0G

0201

R7174

1K

12

1%

1/20W

MF

201

65

FB_B_CPUGT

R7145

560

1 2

1%

1/20W

MF

201

PPBUS_HS_CPU

FB_B_CPUGT_RC

65

R7191

2.7K

1%

1/20W

MF

201

FB_C_CPUSA

R7175

560

1 2

1%

1/20W

MF

201

65

1

C7143

820PF

10% 25V

2

X7R-CERM 0201

65

68

OUT

68

OUT

68

OUT

68 65

67 65

67

IN

65

IN IN

65

65 55

65

OUT

IN

65

COMP_C_CPUSA

12

FB_C_CPUSA_RC

1

C7173

820PF

10% 25V

2

X7R-CERM 0201

R7101

10

1 2

5%

1/20W

MF

201

CPUGT_FCCM

CPUGT_PWM1 CPUGT_PWM2

CPUGT_ISUMP CPUGT_ISUMN_R

CPUGT_ISEN1 CPUGT_ISEN2

COMP_B_CPUGT

FB_B_CPUGT

RTN_B_CPUGT

IMON_B_CPUGT

NTC_B_CPUGT

CPUSA_FCCM

CPUSA_PWM

CPUSA_ISUMP CPUSA_ISUMN_R

COMP_C_CPUSA

FB_C_CPUSA

RTN_C_CPUSA

IMON_C_CPUSA

PROG1_CPUCOREVR

PROG2_CPUCOREVR PROG3_CPUCOREVR

PROG4_CPUCOREVR PROG5_CPUCOREVR

65

1

R7111

110K

1% 1/20W MF 201

2

1

2

65

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V

C7101

0.22UF

10% 25V X7R 0402

34

32 33

29

30

31 45

28

40 39 38 37 36

PROG1_CPUCOREVR

1

R7112

71.5K

1% 1/20W MF 201

2

ISL95828HRTZ

FCCM_B PWM1_B

PWM2_B

ISUMP_B ISUMN_B

ISEN1_B ISEN2_B

COMP_B FB_B RTN_B

IMON_B

NTC_B

FCCM_C

PWM_C

ISUMP_C ISUMN_C

COMP_C FB_C RTN_C

IMON_C

PROG1 PROG2 PROG3 PROG4 PROG5

PROG2_CPUCOREVR

PROG3_CPUCOREVR

1

R7113

16.9K

1% 1/20W MF 201

2

42

41

VIN

VCC

U7100

LLP

THRM_PAD

49

65

1

R7114

182K

1% 1/20W MF 201

2

PP5V_COREVR_VCC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

SDA

2411

2512 2613 27

197 208

219 2210 23

164

175

186

142

153

46

4735

48

43

44

FCCM_A

PWM1_A PWM2_A PWM3_A

ISUMP_A ISUMN_A

ISEN1_A ISEN2_A ISEN3_A

COMP_A

FB_A

RTN_A

IMON_A

NTC_A

VR_HOT*

VR_READY

VR_ENABLE

ALERT*

SCLK

PSYS

65

1

PROG4_CPUCOREVR

1

R7115

121K

1% 1/20W MF 201

2

1

2

CPUCORE_FCCM

CPUCORE_PWM1 CPUCORE_PWM2 CPUCORE_PWM3

CPUCORE_ISUMP CPUCORE_ISUMN_R

CPUCORE_ISEN1 CPUCORE_ISEN2 CPUCORE_ISEN3

COMP_A_CPUCORE

FB_A_CPUCORE

RTN_A_CPUCORE

IMON_A_CPUCORE

NTC_A_CPUCORE

CPUCORE_PROCHOT_R_L

CPUVR_PGOOD

CPU_VR_EN_R

CPUCORE_VIDSOUT_R

CPUCORE_VIDALERT_R_L

CPUCORE_VIDSCLK_R

CPUCORE_PSYS

1

C7108

4700PF

10% 10V

2

X7R 201

65

PROG5_CPUCOREVR

R7100

1

1 2

5%

1/20W

MF

201

C7100

1UF

10% 10V X6S-CERM 0402

73

1 2

1

R7107

12.1K

1% 1/20W MF 201

2

1

R7108

12.1K

1% 1/20W MF 201

2

65

PP5V_S4

OUT

OUT OUT OUT

IN

65

IN IN IN

65

65 55

65

R7106

49.9

1%

1/20W

MF

201

PP5V_S0

NOSTUFF

66

66 65

CPU VCC Core

R7103

0

1 2

5%

1/20W

MF

201

SVID_PU:CORE

1

R7110

45.3

1% 1/20W MF 201

2

R7105

0

1 2

5%

1/20W

MF

201

NTC_A_CPUCORE

65

110

R7102

100

1 2

5%

1/20W

MF

201

66 67 110

NTC_B_CPUGT

65

R7104

10

1 2

5%

1/20W

MF

201

FB_A_CPUCORE

FB_A_CPUCORE_RC

C7148

680PF

X7R-CERM

CPUCORE_ISUMN_R

65

CPU_PROCHOT_L

ALL_SYS_PWRGD

PP1V0_S3

SVID_PU:CORE

1

R7109

100

1% 1/20W MF 201

2

CPU_VIDSOUT

CPU_VIDALERT_L

CPU_VIDSCLK

R7121

14K

1 2

1/20W

R7120

14K

1 2

1%

1/20W

MF

201

10% 25V

0201

1

2

R7149

560

1 2

1%

1/20W

MF

201

R7148

1 2

65

C7155

3300PF

1 2

10% 10V

X7R-CERM

0201

NTC_B_CPUGT_R

1% MF

201

NTC_A_CPUCORE_R

BOM_COST_GROUP=CPU & CHIPSET

CORE_ISUMN_R

OUT

73

IN

110

8

BI

8

IN

8

IN

1K

1%

1/20W

MF

201

FB_A_CORE_R

RTN_A_CPUCORE

R7154

365

1 2

1%

1/20W

MF

201

47 46 6

1

R7123

220KOHM-3%

0201

2

R7147

2.61K

1 2

1%

1/20W

MF

201

R7155

1K

1 2

1%

1/20W

MF

201

65

1

R7124

220KOHM-3%

0201

2

FB_CORE_R

C7147

470PF

1 2

10% 16V

X5R-X7R-CERM

0201

XW7141

SM

1

2

1

C7149

0.01UF

10% 10V

2

X7R-CERM 0201

COMP_A_CPUCORE

65 55

SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/10/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

R7146

0

5%

1/20W

MF

201

12

10% 16V X7R

0201

1

2

C7146

330PF

C7156

220PF

10% 25V X7R-CERM 201

1

C7157

0.01UF

10% 10V

2

X7R-CERM 0201

IMON_A_CPUCORE

R

12

1

C7145

330PF

10% 16V

2

X7R 0201

1

C7158

0.01UF

10% 10V

2

X7R-CERM 0201

R7193

2.87K

1 2

1%

1/20W

MF

201

CORE & SA IMVP IC

Apple Inc.

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUCORE_ISUMP

CPUCORE_ISUMN

CPUCORE_ISEN1

CPUCORE_ISEN2

CPUCORE_ISEN3

1

C7159

0.01UF

10% 10V

2

X7R-CERM 0201

C7193

56PF

1 2

5%

25V

NP0-C0G

0201

COMP_A_CPUCORE_L

C7195

150PF

1 2

5%

50V

CER-C0G

0201

8

IN

66

IN

C7194

6800PF

1 2

10% 10V

X7R-CERM

0201

R7194

100K

1 2

1%

1/20W

MF

201

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

71 OF 145

SHEET

65 OF 121

D

9 8

66 65

C

66 65

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

PPBUS_HS_CPU

66 109

PP5V_S0

65 66 67 110

PPBUS_HS_CPU

66 109

R7216

1

1 2

5% 1/16W MF-LF

402

PVCCCORE_PH1_AGND

66

66 65

65

IN

CPUCORE_FCCM

CPUCORE_PWM1

CPU VCC Phase 1

PVCCCORE_PH1_VCC

20% 25V

0402

1

2

66

PVCCCORE_PH1_AGND

C7217

2.2UF

X6S-CERM

NC NC

31

8 9

2 1

29

3

VCC

PVCC

U7210

VIN VIN

FCCM PWM

NC NC

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

4

32

PLACE_NEAR=U7210.32:2MM

PGND

12

XW7210

SM

OMIT_TABLE

BOOT

PHASE

SW SW

GL0 GL1

PGND

28

12

GH

5 7 16

24 27

3330

6

NC NC

NC

1

C7216

2.2UF

20% 25V

2

X6S-CERM 0402

CRITICAL

1

C7251

33UF

20% 16V

2

TANT-POLY CASE-B3

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

CPUCORE_BOOT1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_BP1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_PHASE1

CRITICAL

1

C7252

33UF

20% 16V

2

TANT-POLY CASE-B3

R7219

0

5% 1/16W MF-LF

402

C7219

0.22UF

10% 25V X7R

0402

CRITICAL

1

C7253

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

L7211

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

1

R7218

2.2

5% 1/10W MF-LF

1

2

1

2

603

2

NOSTUFF

CPUCORE_SW1_SNUB

DIDT=TRUE

1

C7218

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

CRITICAL

1

C7254

33UF

20% 16V

2

TANT-POLY CASE-B3

PPVCC_CPU_PH1CPUCORE_SW1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V

NO_XNET_CONNECTION

CRITICAL

1

C7255

33UF

20% 16V

2

TANT-POLY CASE-B3

R7212

1K

1%

1/20W

MF

201

1

2

CRITICAL

1

C7256

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

R7210

0.00075

1% 1W MF

0612-1

12 34

1

R7211

2.2

1% 1/20W MF 201

2

1

R7213

200K

1% 1/20W MF 201

2

7x 33uF B3

CRITICAL

1

C7257

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUCORE_ISNS1_P CPUCORE_ISNS1_N

NO_XNET_CONNECTION

1

C7258

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUCORE_ISUMN

CPUCORE_ISEN1

CPUCORE_ISUMP

1

2

OUT OUT

C7259

33UF

20% 16V TANT-POLY CASE-B3

51

66 51

OUT

6X 2.2UF 0402

THESE TWO CAPS ARE FOR EMC

1

C7290

0.001UF

10% 50V

2

X7R-CERM 0402

66 65

R7214

200K

65

66 65

1%

1/20W

MF

201

12

R7215

1

C7291

0.001UF

10% 50V

2

X7R-CERM 0402

CPUCORE_ISNS2_N

NO_XNET_CONNECTION

200K

1%

1/20W

MF

201

12

CPUCORE_ISNS3_N

NO_XNET_CONNECTION

D

PPVCC_S0_CPU

Vout = 0.55 - 1.5V ICCMAX = 68A F = 750kHz

66 51

109

C

B

PP5V_S0

65 66 67 110

PVCCCORE_PH2_AGND

66

CPU VCC Phase 2

66 65

65

R7226

1

1 2

5% 1/16W MF-LF

402

IN

PVCCCORE_PH2_VCC

C7227

2.2UF

X6S-CERM

CPUCORE_FCCM

CPUCORE_PWM2

20% 25V

0402

1

2

8 9

2 1

31

NC NC

66

PVCCCORE_PH2_AGND

29

3

VCC

PVCC

U7220

VIN VIN

FCCM PWM

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

4

32

PGND

12

XW7220

SM

OMIT_TABLE

BOOT

PHASE

SW SW

GL0 GL1

GH

PGND

28

12

5 7 16

24 27

3330

6

NC NC

NC

1

C7226

2.2UF

20% 25V

2

X6S-CERM 0402

CPUCORE_SW2

MIN_LINE_WIDTH=0.2000 DIDT=TRUE

SWITCH_NODE=TRUE

CPUCORE_BOOT2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_BP2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_PHASE2

R7229

1/16W MF-LF

402

C7229

0.22UF

10% 25V X7R

0402

C7271

2.2UF

20% 25V

X6S-CERM

0402

THESE TWO CAPS ARE FOR EMC

1

C7292

0.001UF

10% 50V

2

X7R-CERM 0402

20% 25V

0402

1

C7273

2.2UF

2

X6S-CERM

1

C7272

2.2UF

2

X6S-CERM

20% 25V

0402

1

C7274

2.2UF

2

X6S-CERM

0402

20% 25V

1

C7275

2.2UF

2

X6S-CERM

20% 25V

0402

1

C7299

2.2UF

2

X6S-CERM

20% 25V

0402

1

2

1

C7293

0.001UF

10% 50V

2

X7R-CERM 0402

C

CRITICAL

1 2 3 4

1

2

R7220

0.00075

1% 1W MF

0612-1

1

R7223

200K

1% 1/20W MF 201

2

1

R7221

2.2

NO_XNET_CONNECTION

1% 1/20W MF 201

2

NO_XNET_CONNECTION

CPUCORE_ISNS2_P CPUCORE_ISNS2_N

OUT OUT

CPUCORE_ISUMN

CPUCORE_ISEN2

CPUCORE_ISUMP

51

66 51

OUT

66 65

R7224

OUT

200K

65

66 65

1%

1/20W

MF

201

12

R7225

200K

1%

1/20W

MF

201

CPUCORE_ISNS1_N

NO_XNET_CONNECTION

12

CPUCORE_ISNS3_N

NO_XNET_CONNECTION

66 51

CRITICAL

L7221

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

1

R7228

2.2

5% 1/10W MF-LF

1

0

5%

2

1

2

603

2

NOSTUFF

CPUCORE_SW2_SNUB

DIDT=TRUE

1

C7228

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

PPVCC_CPU_PH2

MIN_LINE_WIDTH=0.2000MIN_NECK_WIDTH=0.1200 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V

NO_XNET_CONNECTION

R7222

1K

1%

1/20W

MF

201

B

A

PPBUS_HS_CPU

66 109

PP5V_S0

65 66 67 110

PVCCCORE_PH3_AGND

66

CPU VCC Phase 3

66 65

65

R7236

1

1 2

5% 1/16W MF-LF

402

IN

PVCCCORE_PH3_VCC

C7237

2.2UF

X6S-CERM

CPUCORE_FCCM

CPUCORE_PWM3

20% 25V

0402

1

2

8 9

2 1

31

NC NC

66

PVCCCORE_PH3_AGND

PLACE_NEAR=U7220.32:2MM

29

3

VCC

PVCC

U7230

VIN VIN

FCCM PWM

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

4

32

PLACE_NEAR=U7230.32:2MM

PGND

12

XW7230

SM

OMIT_TABLE

BOOT

PHASE

SW SW

GL0 GL1

GH

PGND

28

12

5 7 16

24 27

3330

6

NC NC

NC

1

C7236

2.2UF

20% 25V

2

X6S-CERM 0402

CPUCORE_SW3

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

CPUCORE_BOOT3

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_BP3

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUCORE_PHASE3

R7239

1/16W MF-LF

402

C7239

0.22UF

10% 25V X7R

0402

CRITICAL

L7231

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

1

R7238

2.2

5% 1/10W MF-LF

1

0

5%

2

1

2

603

2

NOSTUFF

CPUCORE_SW3_SNUB

DIDT=TRUE

1

C7238

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

PPVCC_CPU_PH3

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V

NO_XNET_CONNECTION

R7232

1K

1%

1/20W

MF

201

1

2

R7230

0.00075

1% 1W MF

0612-1

1

R7233

200K

1% 1/20W MF 201

2

12 34

1

R7231

2.2

1% 1/20W MF 201

2

CPUCORE_ISNS3_P CPUCORE_ISNS3_N

NO_XNET_CONNECTION

OUT OUT

CPUCORE_ISUMN

CPUCORE_ISEN3

CPUCORE_ISUMP

51

66 51

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

OUT

3353S00497 CRITICAL

66 65

IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5

U7210,U7220,U7230

R7234

OUT

200K

65

66 65

1%

1/20W

MF

201

12

CPUCORE_ISNS1_N

NO_XNET_CONNECTION

R7235

200K

1%

1/20W

MF

201

12

CPUCORE_ISNS2_N

NO_XNET_CONNECTION

BOM_COST_GROUP=CPU & CHIPSET

66 51

SYNC_DATE=09/03/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

PAGE TITLE

66 51

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CORE IMVP POWER BLOCK

DRAWING NUMBER SIZE

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 72 OF 145 66 OF 121

A

D

8 7 5 4 2 1

36

345678

2 1

D

PPBUS_HS_CPU

109

PP5V_S0

65 66 110

1 2

PVCCCSA_AGND

67

65

IN

65

IN

CPU VCCSA

R7375

1

5% 1/16W MF-LF

402

PVCCCSA_VCIN

CPUSA_FCCM

CPUSA_PWM

C7377

2.2UF

20% 25V

X6S-CERM

0402

3X 33UF B3

CRITICAL

1

C7380

33UF

20% 16V

2

TANT-POLY

1

C7376

2.2UF

20%

1

2

VCIN

11

VDRV

2

25V X6S-CERM 0402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

0.22UH-20%-22A-0.0037OHM

U7370

SIC535CD

NC

6

VIN

MLP4535

CRITICAL

1

ZCD_EN*

12

PWM

3

NC

PGND

CGND

7

13

10

XW7370

SM

12

PVCCCSA_AGND

67

PLACE_NEAR=U7370.10:2MM

BOOT

PHASE

VSWH

GL GL

4

5

8

9 14

NC NC

CPUSA_BOOTSA

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUSA_PHASESA

R7379

CPUSA_BPSA

DIDT=TRUE

C7379

0.22UF

1/16W MF-LF

10% 25V X7R

0402

5%

402

1

0

2

1

2

BOMOPTION=OMIT_TABLE

CRITICAL

L7330

1 2

IHLP2020BD-SM

1

R7378

2.2

5% 1/10W MF-LF 603

2

CPUSA_SW_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7378

0.001UF

10% 50V X7R-CERM 0402

NOSTUFF

PPVCCSA_CPU_RCPUVR_SWSA

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V

CRITICAL

R7370

0.002

1%

1/2W

MF

0306

1 2 3 4

1 2

CASE-B3

CPUSA_ISNS_P CPUSA_ISNS_N

R7372

0

5%

1/20W

MF

201

NO_XNET_CONNECTION=1

R7374

1K

1 2

1%

1/20W

MF

201

CRITICAL

1

C7381

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUSA_ISUMN

CPUSA_ISUMP

NO_XNET_CONNECTION=1

L7330

CRITICAL

1

C7382

33UF

20% 16V

2

TANT-POLY CASE-B3

53

OUT

53

OUT

1

65

C7383

33UF

20% 16V

2

TANT-POLY CASE-B3

C7395

2.2UF

20% 25V

X6S-CERM

0402

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1152S00371 IND,MLD,0.22UH,20%,22A,3.7MO,5.1x5.2x2.4

2X 2.2UF 0402

1

2

C7396

2.2UF

20% 25V

X6S-CERM

0402

1

2

D

PPVCCSA_S0_CPU

Vout = 0.55 - 1.15V ICCMAX = 11.1A F = 750kHz

109

C

B

A

PAGE TITLE

SA IMVP IC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/18/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

051-00647

10.0.0 dvt-fab10 73 OF 145 67 OF 121

A

D

345678

2 1

D

PPBUS_HS_CPU

68 109

PP5V_S0

68 110

1 2

PVCCCGT_PH1_AGND

68

68 65

CPU VCCGT Phase 1

R7416

1

5% 1/16W MF-LF

402

IN

65

IN

PLACE_NEAR=U7410.32:2MM

PVCCCGT_PH1_VCC

C7417

2.2UF

20% 25V

X6S-CERM

0402

CPUGT_FCCM

CPUGT_PWM1

68

PVCCCGT_PH1_AGND

CRITICAL

1

C7400

33UF

20% 16V

2

TANT-POLY CASE-B3

1

2

NC NC

NC

C7416

2.2UF

20% 25V X6S-CERM 0402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUGT_PHASE1

CPUGT_SW1

MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUGT_BP1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

29

3

1

VCC

2

8

VIN

9

VIN

PQFN-COMBO-THICKSTNCL

2

FCCM

1

PWM

31

NC NC

XW7410

U7410

FDMF5808A

CRITICAL

AGND

4

32

SM

12

OMIT_TABLE

PVCC

PGND

12

28

BOOT

PHASE

SW SW

GL0 GL1

GH

5 7 16

24 27

3330 6

CRITICAL

1

C7401

33UF

20% 16V

2

TANT-POLY CASE-B3

1/16W MF-LF

10% 25V X7R

0402

5%

402

1

0

2

1

2

R7419

C7419

0.22UF

0.22UH-20%-44A-0.0019OHM

CRITICAL

1

C7402

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

L7410

1 2

PILA082D-SM

1

R7418

2.2

5% 1/10W MF-LF 603

2

CPUGT_SW1_SNUB

DIDT=TRUE

1

2

NOSTUFF

C7418

0.001UF

10% 50V X7R-CERM 0402

NOSTUFF

CRITICAL

1

C7403

33UF

20% 16V

2

TANT-POLY CASE-B3

PPVCCGT_CPU_PH1

MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V

NO_XNET_CONNECTION

CRITICAL

1

C7404

33UF

20% 16V

2

TANT-POLY CASE-B3

R7412

1/20W

1K

201

1

1%

MF

2

CRITICAL

1

C7405

33UF

20% 16V

2

TANT-POLY CASE-B3

R7410

0.00075

1% 1W MF

0612-1

1 2 3 4

1

2

1

R7413

200K

1% 1/20W MF 201

2

CRITICAL

1

C7406

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

CPUGT_ISNS1_P CPUGT_ISNS1_NCPUGT_BOOT1

R7411

2.2

1% 1/20W MF 201

NO_XNET_CONNECTION

1

C7407

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISUMP

7X 33UF B3

1

C7408

33UF

20% 16V

2

TANT-POLY CASE-B3

53

OUT OUT

68 53

OUT

65

PPVCCGT_S0_CPU

109

D

Vout = 0.55 - 1.5V ICCMAX = 55A F = 750kHz

68 65

R7414

200K

68 65

1%

1/20W

MF

201

12

CPUGT_ISNS2_N

NO_XNET_CONNECTION

68 53

C

PPBUS_HS_CPU

68 109

R7426

1

68 110

PP5V_S0

PVCCCGT_PH2_AGND

68

1 2

5% 1/16W MF-LF

402

68 65

65

IN

CPU VCCGT Phase 2

PLACE_NEAR=U7420.32:2MM

PVCCCGT_PH2_VCC

20% 25V

0402

1

2

C7427

2.2UF

X6S-CERM

CPUGT_FCCM

CPUGT_PWM2

PVCCCGT_PH2_AGND

68

NC NC

8 9

2 1

31

PP5V_S0

68 110

29

3

VCC

PVCC

U7420

VIN VIN

FCCM PWM

NC NC

XW7420

FDMF5808A

PQFN-COMBO-THICKSTNCL

CRITICAL

AGND

SM

AGND

4

32

12

PGND

12

OMIT_TABLE

BOOT

PHASE

SW SW

GL0 GL1

GH

PGND

28

5 7 16

24 27

3330

6

1

C7426

2.2UF

20% 25V

2

X6S-CERM 0402

NC NC

NC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUGT_PHASE2

CPUGT_BOOT2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

CPUGT_BP2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

DIDT=TRUE

CPUGT_SW2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

R7429

1/16W MF-LF

C7429

0.22UF

10% 25V X7R

0402

5%

402

C7420

2.2UF

20% 25V

X6S-CERM

0402

CRITICAL

L7420

0.22UH-20%-44A-0.0019OHM

1 2

PILA082D-SM

1

R7428

2.2

5% 1/10W MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUGT_SW2_SNUB

DIDT=TRUE

1

C7428

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

1

C7421

2.2UF

2

PPVCCGT_CPU_PH2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V

X6S-CERM

NO_XNET_CONNECTION

20% 25V

0402

1

2

R7422

1K

1%

1/20W

MF

201

C7422

2.2UF

X6S-CERM

0402

CRITICAL

R7420

0.00075

0612-1

1

2

20% 25V

1% 1W MF

1

2

12 34

1

R7421

2.2

1% 1/20W MF 201

2

1

R7423

200K

1% 1/20W MF 201

2

4x 2.2uF 0402

20% 25V

1

2

C7423

2.2UF

X6S-CERM

0402

CPUGT_ISNS2_P CPUGT_ISNS2_N

NO_XNET_CONNECTION

CPUGT_ISUMN

CPUGT_ISEN2

CPUGT_ISUMP

OUT OUT

53

C

68 53

65

68 65

R7424

200K

68 65

1%

1/20W

MF

201

12

CPUGT_ISNS1_N

NO_XNET_CONNECTION

68 53

OUT

B

U7410,U7420

B

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL353S00497 IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X52

A

SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

PAGE TITLE

GT & GTX IMVP POWER BLOCK

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/03/2015

051-00647

10.0.0 dvt-fab10 74 OF 145 68 OF 121

A

D

345678

2 1

D

C

B

2.2UF

X6S-CERM

1

C7608

2.2UF

20% 25V

2

X6S-CERM 0402

PPBUS_HS_OTH5V

109 117

C7600

TANT-POLY

CASE-B3

PP5V_S4

69 110 117

VOUT = 5V

1.58A MAX OUTPUT F = 500 KHZ

20% 25V

0402

1

2

1

C7605

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

C7606

P5VS4_VFB1_R

NO_XNET_CONNECTION=1

1

R7677

200

1% 1/20W MF 201

2

5VS4_VFB1_RR

1

R7678

41.2K

0.1% 1/16W MF 0402

2

1

R7679

10K

0.1% 1/16W MF 0402

2

1

33UF

20% 16V

2

C7607

150UF

20%

6.3V

TANT-POLY

CASE-B1S-1

XW7675

XW7671

5V S0 - V5

1

C7601

2.2UF

20% 25V

2

X6S-CERM 0402

1

CRITICAL

L7600

2.2UH-20%-4.5A-0.043OHM

PIMA042T-SM

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

2

SM

1

SM

P5VS4_VSW

NO STUFF

1

R7674

1

5% 1/10W

PLACE_NEAR=C7607.1:3MM

MF-LF 603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

PLACE_NEAR=L7600.1:3MM

2

1

SWITCH_NODE=TRUE

PLACE_NEAR=L7600.2:3MM

2

XW7670

SM

NO_XNET_CONNECTION=1

1

P5VS4_CSP1_R

1

C7602

2.2UF

20% 25V

2

X6S-CERM 0402

1

6 7 8

NO STUFF

C7674

0.0033UF

DIDT=TRUE

10% 50V

CERM

402

CRITICAL

U7600

CSD58879Q3D

Q3D

VIN

VSW

PGND

9

1

2

TG

TGR

BG

R7672

4.87K

3

4

5

1%

1/20W

MF

201

1

2

PPBUS_HS_OTH3V3

109 117

10% 25V X6S

0402

1

2

C7650

1.0UF

P5VS0_TG

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE

P5VS0_VBST_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

1

C7609

0.1UF

10% 25V

2 1/20W

X6S-CERM 0201

R7609

0

5% MF

201

SKIP_5V3V3:AUDIBLE

1

2

SKIP_5V3V3:INAUDIBLE

1

R7665

1

5% 1/20W MF 201

2

R7651

0

5%

1/20W

MF

0201

1

2

P5VP3V3_SKIPSEL

P5VS4_VBST P5VS4_DRVH

MIN_LINE_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

C7673

SWITCH_NODE=TRUEMIN_LINE_WIDTH=0.2000 DIDT=TRUE

GATE_NODE=TRUE

P5VS4_SW

P5VS4_CSP1 P5VS4_CSN1

0.1UF

1 2

P5VS4_VFB1

10%

6.3V X7R

0201

R7673

698

1 2

1%

1/20W

MF

201

73 70

BOMOPTION=NOSTUFF

1

R7676

10K

1% 1/20W MF 201

2

P5VS4_COMP1 P5VS4_EN_RCD

P5VS4_PGOOD

P5VS4_COMP1_R

C7678

270PF

10% 16V

X7R-CERM

0201-1

1

2

1

C7679

4700PF

10% 10V

2

X7R 201

(P5VP3V3_VREF2)

GND_5V3V3_AGND

73

PM_SLP_S5_L

PP5V_S4

69 110 117

1

R7650

0

5%

1/20W

MF

0201

2

DIDT=TRUESWITCH_NODE=TRUE

1%

1/20W

MF

1

2

PLACE_NEAR=U7650.28:1MM

R7675

3.92K

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V

R7663

1 2

1/20W

D7663

RB521ZS-30

NO STUFF

100

5%

1/20W

MF

201

1

2

R7664

NO STUFF

P5VS4_EN_RD

2

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

VBST1 VBST2

1

DRVH1 DRVH2

32

SW1 SW2

30

DRVL1

7

CSP1

8

CSN1 CSN2

11

MODE

9

10

COMP1 COMP2

4

EN1 EN2

5

PGOOD1 PGOOD2

23

VIN

GND

28

XW7650

0

5% MF

201

SM-201

P5VS4_EN_RCD

AK

1

2

29

VREG5

CRITICAL

U7650

QFN

2201

SM

1

C7654

1.0UF

10% 25V X6S 0402

22

TPS51980A

THRM_PAD

NO STUFF

VREG3

33

69

P5VP3V3_VREG3 P5VP3V3_VREF2

13

VREF2

12

EN

DRVL2

CSP2

RF

VFB2VFB1

26 24 25 27 18

17 3

16 15

21 20

DIDT=TRUE

DIDT=TRUE GATE_NODE=TRUE

10% 10V

CERM

402

1

2

C7652

0.22UF

PM_EN_PVXS5

P3V3S5_VBST

SWITCH_NODE=TRUE

P3V3S5_SW P3V3S5_DRVLP5VS4_DRVL P3V3S5_CSP2

P3V3S5_CSN2 P3V3S5_RF

P3V3S5_VFB2 P3V3S5_COMP2

P3V3S5_EN_RCD S5_PWRGD

1

R7695

3.92K

1% 1/20W MF 201

2

BOMOPTION=NOSTUFF

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

1

C7653

2.2UF

10% 10V

2

X5R-CERM 0402

IN

69 69

OUTOUT

R7696

C7699

2700PF

10% 10V

X7R-CERM

201

CRITICAL

1

C7651

10UF

20% 10V

2

X5R-CERM 0402-1

73

73 70

10K

1%

1/20W

MF

201

1

2

PP5V_S5

VOUT = 5V 100MA MAX OUTPUT

R7685

1

1 2

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE

P3V3S5_VBST_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

1

R7669

0

5% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2000GATE_NODE=TRUE MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2000DIDT=TRUE SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200

MIN_LINE_WIDTH=0.2000MIN_LINE_WIDTH=0.2000 DIDT=TRUE MIN_NECK_WIDTH=0.1200

200K

1%

1/20W

MF

201

1

2

R7655

1

2

1

C7698

330PF

10% 16V

2

X7R 0201

110

P3V3S5_TG

C7671

0.1UF

10% 25V

X6S-CERM

0201

C7693

0.1UF

1 2

R7693

1.58K

1 2

1/20W

3.3V DSW - V6

CRITICAL

1UH-20%-17A-0.01OHM

U7660

CSD58873Q3D

1

2

10%

6.3V X7R

0201

1% MF

201

3

TG

4

TGR

5

BG

1

R7692

3.83K

1% 1/20W MF 201

2

P3V3S5_CSP2_R

Q3D

VIN

VSW

PGND

9

DIDT=TRUE

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE

1

2

CRITICAL

1

C7660

33UF

20% 16V

2

TANT-POLY CASE-B3

APN: 152S1032

CRITICAL

L7660

PIMC063T-SM

1

6 7 8

P3V3S5_SNUBR

NO STUFF

C7694

0.001UF

10% 50V X7R-CERM 0402

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

P3V3S5_VSWP3V3S5_DRVH

NO STUFF

R7694

1/10W MF-LF

NO_XNET_CONNECTION=1

1

10

5%

603

2

XW7690

CRITICAL

1

C7661

33UF

20% 16V

2

TANT-POLY CASE-B3

1

2

PLACE_NEAR=C7665.1:3MM

PLACE_NEAR=L7660.1:3MM

2

PLACE_NEAR=L7660.2:3MM

XW7691

SM

2

SM

1

NO_XNET_CONNECTION=1

1

CRITICAL

1

C7662

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C7665

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

CASE-B1S-1

2

XW7695

SM

1

P3V3S5_VFB2_R

R7697

P3V3S5_VFB2_RR

R7698

R7699

C7666

150UF

20%

6.3V

TANT-POLY

C7669

2.2UF

X6S-CERM

1

10

5%

1/20W

MF

201

2

1

23.2K

0.1%

1/16W

MF

0402

2

1

10K

0.1%

1/16W

MF

0402

2

CRITICAL

1

C7680

33UF

20% 16V

2

TANT-POLY CASE-B3

PP3V3_S5

VOUT = 3.3V

8.47A MAX OUTPUT F = 500 KHZ

1

C7667

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

1

2

20% 25V

0402

1

2

C7668

TANT-POLY

CASE-B1S-1

C7670

2.2UF

X6S-CERM

C7664

2.2UF

X6S-CERM

150UF

20%

6.3V

20% 25V

0402

20% 25V

0402

1

2

1

2

1

2

110 117

1

C7672

150UF

2

C7663

2.2UF

20% 25V

X6S-CERM

0402

20%

6.3V TANT-POLY CASE-B1S-1

C7676

150UF

20%

6.3V

TANT-POLY

CASE-B1S-1

NO STUFF

D

1

2

1

2

C

B

A

73

PM_EN_PVXS5

R7644

100

1/20W

201

NO STUFF

P3V3S5_EN_RD

5% MF

1

2

R7643

0

1 2

5%

1/20W

MF

201

D7643

SM-201

AK

RB521ZS-30

NO STUFF

P3V3S5_EN_RCD

1

C7644

1.0UF

10% 25V

2

X6S 0402

NO STUFF

69

BOM_COST_GROUP=PLATFORM POWER

SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/09/2015

PAGE TITLE

Power - 5V 3.3V Supply

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

76 OF 145

SHEET

69 OF 121

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

70 73

GND

73 47 46

R7820

1M

1%

1/20W

MF

NOSTUFF

201

R7821

5%

1/20W

MF

201

73 70

BANJO - PMIC Control

73 70

GND

70 73

CKPLUS_WAIVE=PWRTERM2GND

L1

ECVCC

U7800

P650839A0B

PBGA

(8 OF 10)

IN

73 70

1

2

SMC_PM_G2_EN PP3V3_PMICLDO

70

PPBUS_PMIC

GND

70 73

PMIC_VDCSNS

1

0

2

PP3V3_PMICLDO

70 73

D11

ACOK

H2

PWRBTNIN

E5

VINPP

F1

G1

BAT2

E2

ACIN

G3

VDCSNS

H9

NVDC*

(LDO3V = 3S)

CRITICAL

(OD)

(PP)

(OD)

RSMRST_L_PWRGD

(OD)

OMIT_TABLE

DS3_VREN

1HZ

SYS_PWROK

PCH_PWROKBAT1

ALL_SYS_PWRGD

PMIC_INT*

EC_RST*

EC_ONOFF*

PCH_PWRBTN*

(OD)

DPWROK

ACSWON*

BAT1SWON* BAT2SWON*

VCCST_PWRGD

K13 K11 H11 E11 G11 J11 D12 J3 K4 K2 K12 J2 F2

G2 E4

NC NC

PM_PCH_SYS_PWROK

PM_PCH_PWROK

ALL_SYS_PWRGD

PM_RSMRST_L

SMC_PMIC_INT_L

GND

CPU_VCCST_PWRGD

(Pull up on Chipset Page)

OUT

70 73

8

73

PMIC_SHUTDOWN_L

70

70 46 20 12

115 70 12

73 70 46

73 70

47 46

114 101 89 76 73 70 46 27 20 12

73 70 69

73 72

73 46 43 20 12

73 12

73 70

70 46 20 12

73

IN

73 70

IN

IN IN IN

IN IN

73 70

IN IN

IN

PM_SLP_S0_L PP3V3_SUS

110

PP1V8_S3

109

PP3V3_PMICLDO S5_PWRGD

PP3V3_S0_LEFT

70 110

PP1V8_S0 P5VS4_PGOOD PM_SLP_S3_L

P1V8SUS_PGOOD PM_SLP_S4_L

PP3V3_PMICLDO

PM_SLP_SUS_L PM_SLP_S3_L

CPUVR_PGOOD PM_SLP_S0_L

PP3V3_PMICLDO

PLACE_NEAR=U7800.D1:2MM

C7839

2.2UF

X6S-CERM

GND

70 73

D9

E7 K9 K8 E6 F4 E8

J10

F5

B12 C11 C12

J13

F10

J12

B10

L11

L6

1

10% 10V

2

0402

SHUTDOWN* STANDBY* VSA

VSB VSC VSD VSE VSF VSG VSH

ENA ENB ENC END ENE ENF ENG ENH

ENLVA

L8

D1

VDDPG

U7800

P650839A0B

PBGA

(1 OF 10)

CRITICAL

PP3V3_S5

VDDLV

(PP) (PP)

(PP) (PP) (PP) (PP) (OD)

(OD) (OD)

PLACE_NEAR=U7800.L8:2MM

1

C7840

1UF

20% 10V

2

X6S-CERM 0201

GND

PGA PGB PGC PGD PGE

PGF

PGH

LVA

LVB

C8C7

D6 C5 C6 H3 C4 H4 F3 M6

L12 L10

RESET*

PGG

NC

TP_PMIC_PGC TP_PMIC_PGD TP_PMIC_PGE TP_PMIC_PGF TP_PMIC_PGG

70 110

70 73

P3V3SUS_PGOOD

P1V8S3_EN

PVCCIO_EN PM_SLP_S0S3_L

PM_PCH_PWROK

OUT OUT

OUT

115 70 12

73

74

70

73 69

69 70 73

70

73 70

70 73

70 110

P5VS4_PGOOD

S5_PWRGD

PP3V3_PMICLDO

PMIC_SHUTDOWN_L

PP3V3_S0_LEFT

70 110

CPUVR_PGOOD

PP3V3_SUS

110

PM_RSMRST_L

PP3V3_S5

1

2

1

2

1

2

1

R7801

100K

5% 1/20W MF 201

2

R7860

100K

5% 1/20W MF 201

R7861

100K

5% 1/20W MF 201

R7810

4.7K

5% 1/20W MF 201

1

R7802

100K

5% 1/20W MF 201

2

D

C

B

73 70

PP3V3_PMICLDO

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

BI

SMBUS_SMC_5_G3_SCL PMIC_SLAVEADDR

70

PMIC_EN3V3SW P5VS4_PGOOD

73

PP5V_S4

73

R7837

100K

1 2

5%

1/20W

MF

201

49

IN

73 70

PP3V3_PMICLDO

1UF

20% 10V

0201

1

2

C7830

X6S-CERM

C7841

1UF

20% 10V

X6S-CERM

0201

M5

1

2

H1

SDA

J1

SCLK

L3

SLAVEADDR

K3

EN3V3SW EN5VSW

N5

VIN5VSW

70 73

PP5V_PMICLDO_R

M13

VDDIO1

D3

VDD5_VPROGOTP

E1

VDDIO0

U7800

P650839A0B

PBGA

(7 OF 10)

TEMP_ALERT*

CRITICAL

OMIT_TABLE

VOUT3V3SW

LDO3V

VREF1V25

LDO5V

R7866

0

1 2

5%

1/20W

MF

201

L2 M7

PP3V3_PMICLDO

N8 B1

PP1V25_PMICVREF

N7

PP5V_PMICLDO

1

C7831

1UF

20% 10V

2

X6S-CERM 0201

72 71 70

PP5V_PMICLDO

70

OMIT_TABLE

PP3V0_G3H

109

72 71 70

C13

V3P3A_RTC

U7800

PBGA

(10 OF 10)

PP3V0_G3H

109

GND

70 73

B13

VBATTBKUP

J4

VCOMP

OMIT_TABLE

P650839A0B

CRITICAL

AGND

F6F7F8

73 70

G5G6G7

H5H6H7

G8

J5J6J7

H8

PLACE_NEAR=U7800.C13:2MM

1

C7880

1UF

20% 10V

2

X6S-CERM 0201

GND

K6

TRIP*

NC0 NC1 NC2 NC3

K7

(OD)

J8

H10

A1 A13 N1 N13

NC NC NC NC

70 73

GND

115 70 12

73 70 46

70 73

70 71

109

PP3V3_S0_LEFT

70 110

PM_PCH_PWROK ALL_SYS_PWRGD

PP3V3_S5

70 110

PVCCIO_EN

PPBUS_G3H

R7865

0

1 2

5%

1/20W

MF

201

1

R7804

10K

5% 1/20W MF 201

2

PPBUS_PMIC

VOLTAGE=13.1V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

R7805

10K

5% 1/20W MF 201

2

1

R7807

100K

5% 1/20W MF 201

2

70

B

A

PLACE_NEAR=U7800.M8:2MM

C7837

1.0UF

10% 25V X6S

0402

70

PLACE_NEAR=U7800.N6:2MM

10% 25V X6S

0402

1

2

1

C7838

1.0UF

2

PP3V3_PMICLDO

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

PPBUS_PMIC PPBUS_PMIC

70 73

GND

M8

VINLDO3

N6

VIN

AGND2

AGND3

L13

AGND4

D13

72

PLACE_NEAR=U7800.N7:2MM

1

C7836

10UF

20%

6.3V

2

CERM-X6S 0402

71 70

PP1V25_PMICVREF

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.25V

PLACE_NEAR=U7800.N7:2MM

1

C7835

10UF

20%

6.3V

2

CERM-X6S 0402

70

PLACE_NEAR=U7800.B1:2MM

1

C7834

0.47UF

10% 10V

2

X7R 0402

PLACE_NEAR=U7800.N8:2MM

1

C7833

10UF

20%

6.3V

2

CERM-X6S 0402

114 101 89 76 73 70 46 27 20 12

PM_SLP_S3_L

AGND1

K1

C1

73 70

PP5V_PMICLDO

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

PMIC_SLAVEADDR

70

1

R7808

100K

5% 1/20W MF 201

2

PM_SLP_S0S3_L

70

PVCCIO_EN

70 71

PVCCIO_EN

70

R7864

0

1 2

5%

1/20W

MF

201

NOSTUFF

PP3V3_PMICLDO

PM_SLP_S0S3_L

MAKE_BASE=TRUE

PVCCIO_EN

MAKE_BASE=TRUE

BOM_COST_GROUP=PLATFORM POWER

73 70

SYNC_DATE=12/08/2015SYNC_MASTER=J80_MLB

PAGE TITLE

A

PMIC-1 & Power Control

73

71

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

78 OF 145

SHEET

70 OF 121

8 7 5 4 2 1

36

345678

2 1

D

1.2V VDDQ - V10 (Banjo#1 VR4)

OMIT_TABLE

P650839A0B

PP5V_PMICLDO P1V2_VBST_R

P1V2S3_ILIM_HS

GND

IN

PM_MEMVTT_EN

IN

PVCCIO_EN PM_SLP_S4_L

OUT

VREGVR4

D2

ILIMVR4

D4

DDRID

E3

DDR_VTT_CTRL

B5

PGVR4

C2 D5

ENVR4

CRITICAL

(OD)

Check R7901

R7900

11.5K

1%

1/20W

MF

201

1

2

R7901

100K

5%

1/20W

MF

201

72 70

73

5

70

73

1

2

U7800

PBGA

(5 OF 10)

PGNDVR4

A4

VBSTVR4

DRVHVR4

SWVR4

DRVLVR4

FBVR4+

FBVR4-

B3B4

A2 A3 A5

C3

P1V2_VBST

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

P1V2_DRVH_R P1V2_SW P1V2_DRVL_R

P1V2S3_FB_P P1V2S3_FB_N

R7902

0

1 2

5%

1/20W

MF

201

1

R7903

0

5% 1/20W MF 201

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

1

2

R7904

10

5% 1/20W MF 201

P1V2S3_FB_R_P

109

PPBUS_HS_CPU

C7904

0.1UF

1 2

20% 16V

X6S-CERM

0201

DIDT=TRUE GATE_NODE=TRUEMIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

DIDT=TRUE GATE_NODE=TRUEMIN_NECK_WIDTH=0.1200MIN_LINE_WIDTH=0.2000

P1V2_DRVH

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

SWITCH_NODE=TRUEDIDT=TRUEMIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

P1V2_DRVL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

GATE_NODE=TRUEDIDT=TRUE

R7905

1

1 2

1/20W5%

201MF

R7906

0

1 2

5% 1/16W MF-LF

402

GATE_NODE=TRUE

CRITICAL

CSD58873Q3D

3

TG

4

TGR

5

BG

U7900

Q3D

9

VIN

VSW

PGND

1

DIDT=TRUE

6 7 8

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

P1V2_PHASE

NOSTUFF

P1V2_SW_SNUB

DIDT=TRUE

NOSTUFF

CRITICAL

C7900

33UF

20% 16V

TANT-POLY

CASE-B3

2.2

1/10W MF-LF

10% 50V

0402

5%

603

1

2

1

2

R7917

C7917

0.001UF

X7R-CERM

1

2

CRITICAL

C7901

TANT-POLY

CASE-B3

33UF

20% 16V

1

2

1

C7902

2.2UF

20% 25V

2

X6S-CERM 0402

CRITICAL

L7900

0.47UH-20%-22A-0.0042OHM

1

PIMC063T-SM

PP1V2_S3_REG_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V

51

OUT OUT

ISNS_CPUDDR_P ISNS_CPUDDR_N

2

1

C7903

2.2UF

20% 25V

2

X6S-CERM 0402

OMIT

R7918

0.005

1%

1/3W

MF

0306-SHORT

XW7904

SM

1 2

D

21 43

CRITICAL

1

C7905

270UF

20% 2V

2

TANT CASE-B

C7906

270UF

20%

2V

TANT

CASE-B

1

2

CRITICAL

C7908

270UF

20%

TANT

CASE-B

1

C7907

270UF

20% 2V

2

TANT CASE-B

CRITICAL

1

2V

2

CRITICAL

1

C7909

270UF

20% 2V

2

TANT CASE-B

CRITICAL

1

C7913

10UF

20% 4V

2

X6S 0402

CRITICAL

C7914

10UF

20% X6S

0402

4V

1

2

PP1V2_S3

Vout = 1.2V ICCMAX = 9.01A

F = 600kHz

74 109 117

C

PP1V2_S3

109 117

CRITICAL

C7935

10UF

20% X6S

0402

4V

CRITICAL

1

2

C7930

10UF

20%

4V

X6S

0402

P1V2S3_FB_R_N

0.6V VTT - V13 (Banjo#1 LDO1)

OMIT_TABLE

U7800

1

2

XW7931

SM

1 2

PMIC_VINLDO1S

A6

VINLDO1_0

B6

VINLDO1_1

F9

VINLDO1S

P650839A0B

PBGA

(9 OF 10)

VOUTLDO1_0 VOUTLDO1_1

CRITICAL

A8 B8

XW7930

SM

CRITICAL

1

2

1 2

C7931

15UF

20% 2V X6S 0402

CRITICAL

1

C7932

15UF

20% 2V

2

X6S 0402

CRITICAL

1

C7933

15UF

20% 2V

2

X6S 0402

CRITICAL

1

C7934

15UF

20% 2V

2

X6S 0402

1 2

XW7903

SM

CRITICAL

1

C7936

15UF

20% 2V

2

X6S 0402

PP0V6_S0_DDRVTT

CRITICAL

1

C7937

15UF

20% 2V

2

X6S 0402

C

109 117

Vout = 0.6V ICCMAX = 0.572A

B

A

0.95V VCCIO - V6 (Banjo#1 VR3)

OMIT_TABLE

XW7964

SM

PPBUS_HS_CPU

71 109

R7961

7.5K

1%

1/20W

MF

201

1

2

1 2

73

OUT

70

IN

PMIC_VINVR3

PVCCIO_ILIM_LS

PVCCIO_PGOOD PVCCIO_EN

VINVR3

CRITICAL

D10

ILIMVR3HS

C9

ILIMVR3LS

B9

PGVR3

E9 D7

ENVR3

U7800

P650839A0B

PBGA

(4 OF 10)

PGNDVR3

A10

VBSTVR3

DRVHVR3

SWVR3

DRVLVR3

FBVR3+

FBVR3-

B11G9

PVCCIO_VBST

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

A12

PVCCIO_DRVH

A11

PVCCIO_SW

A9

PVCCIO_DRVL_R

C10

PVCCIO_FB_P PVCCIO_FB_N

PGNDLDO1_0

A7

PVCCIO_VBST_R

MIN_LINE_WIDTH=0.2000

1

R7964

1

5% 1/20W MF 201

2

MIN_NECK_WIDTH=0.1200 DIDT=TRUEMIN_LINE_WIDTH=0.2000 GATE_NODE=TRUE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUEDIDT=TRUE

MIN_LINE_WIDTH=0.2000

R7962

0

5%

1/20W

MF

201

1

2

R7963

MIN_NECK_WIDTH=0.1200 DIDT=TRUEGATE_NODE=TRUE

1

10

5%

1/20W

MF

201

2

MIN_NECK_WIDTH=0.1200 DIDT=TRUE

1

C7963

0.1UF

20% 16V

2

X6S-CERM 0201

FBLDO1

PGNDLDO1_1

B7

PVCCIO_DRVL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

D8

PVTT_FB

R7965

0

1 2

5% 1/16W MF-LF

402

PPBUS_HS_CPU

71 109

3

4

5

R7930

1 2

1/20W

CRITICAL

U7960

CSD58873Q3D

TG

TGR

BG

10

5% MF

201

Q3D

9

VIN

VSW

PGND

PVTT_FB_R

1

DIDT=TRUE MIN_NECK_WIDTH=0.1200

6

MIN_LINE_WIDTH=0.2000

7 8

PVCCIO_PHASE

CRITICAL

C7968

TANT-POLY

CASE-B3

NOSTUFF

PVCCIO_SW_SNUB

DIDT=TRUE

R7969

33UF

20% 16V

2.2

1/10W MF-LF

603

CRITICAL

1

2

1UH-20%-17A-0.01OHM

1

5%

2

33UF

20% 16V

1

2

C7960

TANT-POLY

CASE-B3

CRITICAL

L7960

1 2

PIMC063T-SM

C7969

0.001UF

NOSTUFF

10% 50V

X7R-CERM

0402

1

C7961

2.2UF

2

1

2

20% 25V X6S-CERM 0402

C7964

CRITICAL

10UF

20%

4V

X6S

0402

1

C7962

2.2UF

20% 25V

2

X6S-CERM 0402

1

2

C7955

10UF

20%

4V

X6S

0402

CRITICAL

B

PPVCCIO_S0_CPU

1

2

1

C7966

220UF

20% 2V

23

ELEC SM-COMBO

1

C7967

220UF

20% 2V

23

ELEC SM-COMBO

1

C7970

220UF

20% 2V

23

ELEC SM-COMBO

Vout = 0.95V ICCMAX = 5.50A F = 500kHz

PAGE TITLE

109 117

SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB

A

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

8

IN

9 8

IN

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=PLATFORM POWER

8 7 5 4 2 1

36

PMIC-1 1.2V 0.6V VCCIO

Apple Inc.

R

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 79 OF 145 71 OF 121

D

345678

2 1

D

72 71 70

1V - V11 (Banjo#1 VR1)

PP5V_PMICLDO

C8016

1UF

X6S-CERM

0201

8.45K

1%

1/20W

MF

201

1

73

OUT

73

2

IN

R8000

1

20% 10V

2

P1VS4_ILIM_HS

P1VSUS_PGOOD P3V3SUS_PGOOD

OMIT_TABLE

U7800

P650839A0B

PBGA

(2 OF 10)

VREGVR1

CRITICAL

L9

ILIMVR1

M9

PGVR1

M12 J9

ENVR1

PGNDVR1

N10

VBSTVR1

DRVHVR1

SWVR1

DRVLVR1

FBVR1+

FBVR1-

M11M10

N12 N11 N9

K10

P1VS4_VBST

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

P1VS4_DRVH P1VS4_SW P1VS4_DRVL

P1VS4_FB_P P1VS4_FB_N

DIDT=TRUE

1

R8002

0

5% 1/20W MF 201

2

P1VS4_VBST_R

1

R8001

0

5% 1/20W MF 201

2

1

R8003

10

5% 1/20W MF 201

2

P1VS4_FB_R_P P1VS4_FB_R_N

109

MIN_NECK_WIDTH=0.1200MIN_LINE_WIDTH=0.2000 DIDT=TRUE

1

C8003

0.1UF

20% 16V

2

X6S-CERM 0201

GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.1200MIN_LINE_WIDTH=0.2000

DIDT=TRUEMIN_NECK_WIDTH=0.1200MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE

GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.1200MIN_LINE_WIDTH=0.2000

PPBUS_G3H

3

TG

4

TGR

5

BG

CRITICAL

U8000

CSD58889Q3D

Q3D

VSW

9

VIN

PGND

ROOM=BANJO

1

C8002

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

PP1V_PCH_REG_RP1VS4_PHASE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V

51

OUT

51

OUT

1

C8008

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

ISNS_1V0_P ISNS_1V0_N

XW8003

CRITICAL

SM

1 2 1 2

R8004

0.003

1%

1/2W

MF

0306

D

PP1V0_SUS

12 34

CRITICAL

C8004

10UF

20%

4V

X6S

0402

1

2

CRITICAL

C8005

10UF

20%

4V

X6S

0402

1

2

1

C8006

220UF

20% 2V

23

ELEC SM-COMBO

1

C8007

220UF

20% 2V

23

ELEC SM-COMBO

Vout = 1.0V ICCMAX = 4.11A F = 500kHz

110 117

1

C8010

220UF

20% 2V

23

ELEC SM-COMBO

20% 25V

0402

1

2

C8000

2.2UF

X6S-CERM

1

C8001

2.2UF

X6S-CERM

20% 25V

0402

1

2

CRITICAL

DIDT=TRUE

6 7 8

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

NOSTUFF

R8009

2.2

5% 1/10W MF-LF

603

1

2

1UH-20%-17A-0.01OHM

P1VS4_SW_SNUB

DIDT=TRUE

NOSTUFF

L8000

1 2

PIMC063T-SM

10% 50V

0402

1

2

C8009

0.001UF

X7R-CERM

C

PP3V3_S5

110

C8024

2.2UF

20% 25V

X6S-CERM

0402

XW8004

SM

1.8V - V8 (Banjo#1 VR2)

C

Stuff with 107S00058/107S00103 at Proto

OMIT_TABLE

U7800

P650839A0B

PBGA

(3 OF 10)

F12 F13

VINVR2_0 VINVR2_1

SWVR2_0 SWVR2_1

CRITICAL

72 71 70

1

C8020

2.2UF

2

X6S-CERM

20% 25V

0402

1

2

1

C8021

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

PP5V_PMICLDO

1

C8025

1UF

20% 10V

2

X6S-CERM 0201

73 70

73

OUT

IN

P1V8SUS_PGOOD PM_SLP_SUS_L

E13

VREGVR2

E12

PGVR2

F11 E10

ENVR2

PGNDVR2_0

PGNDVR2_1

G12

G13

FBVR2+

FBVR2-

H12

P1V8SUS_SW

H13

G10

P1V8SUS_FB_N

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE

R8020

100

1/20W

201

NOSTUFF

1

R8021

1

5%

MF

2

10

5% 1/20W MF 201

2

P1V8SUS_FB_R_P

0.47UH-20%-4.0A-28MOHM

R8029

2.2

5% 1/10W MF-LF

603

CRITICAL

APN: 152S1682

L8020

1 2

PIFE25201B-SM

1

DIDT=TRUE

2

P1V8S3_SW_SNUBP1V8SUS_FB_P

NOSTUFF

C8028

0.01UF

C8029

0.001UF

X7R-CERM

10% 10V X7R

0201-1

10% 50V

0402

1

2

PP1V8_SUS_REG_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V

51

1

2

OUT OUT

ISNS_1V8_SUS_P ISNS_1V8_SUS_N

R8025

100

1 2

5%

1/20W

MF

201

P1V8SUS_FB_RC

OMIT

R8024

0.005

1%

1/3W

MF

0306-SHORT

XW8021

1 2

21 43

SM

PP1V8_SUS

CRITICAL

1

C8022

100UF

20%

6.3V

2

TANT-POLY CASE-A3-LLP

109 117

CRITICAL

1

C8023

100UF

20%

6.3V

2

TANT-POLY CASE-A3-LLP

Vout = 1.8V ICCMAX = 0.7A F = 2MHz

CRITICAL

1

C8026

20UF

20%

2.5V

2

X6S-CERM 0402-1

CRITICAL

1

C8027

20UF

20%

2.5V

2

X6S-CERM 0402-1

B

109

PPBUS_G3H

R8050

0

1 2

5%

1/20W

MF

201

PPVIN_SUS_VR5_R

VOLTAGE=13.1V

VINVR5

K5

ILIMVR5HS

L5

ILIMVR5LS

OMIT_TABLE

U7800

P650839A0B

PBGA

(6 OF 10)

CRITICAL

VBSTVR5

DRVHVR5

SWVR5

DRVLVR5

M3L7

M1 N2 N4

NC

NC NC NC

P1V8SUS_FB_R_N

1 2

XW8020

SM

B

A

M4

M2

PGVR5

ENVR5

FBVR5+

FBVR5-

G4 L4

NC

PGNDVR5

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016

N3

PAGE TITLE

PMIC-1 1V 1.8V VCCPCH

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=PLATFORM POWER

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 80 OF 145 72 OF 121

A

D

345678

2 1

KEEP THESE RAILS ON WHEN USING XDP

PP3V3_SUS

18 73 110

D

C

70 47 46

SUS Enables

70 12

46 20 12

73 70 46 43 20 12

114 101 89 76 70 46 27 20 12

S5 Enables

R8110

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

MAKE_BASE=TRUE

1 2

S4 Enables

PM_SLP_S5_L

MAKE_BASE=TRUE

S3 Enables

PM_SLP_S4_L

MAKE_BASE=TRUE

S0 Enables

PM_SLP_S3_L

MAKE_BASE=TRUE

0

5%

1/20W

MF

201

MAKE_BASE=TRUE

PM_EN_PVXS5

PM_SLP_SUS_L PM_SLP_SUS_L

PM_SLP_S5_L PM_SLP_S5_L PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L PM_SLP_S3_L PM_SLP_S3_L

OUT OUT

73

OUT OUT OUT

OUT

OUT OUT

69

72

74

69

71

74

70

110

70 69

70 46

PP3V3_PMICLDO CPUVR_PGOOD

MAKE_BASE=TRUE

PP5V_S4

P5VS4_PGOOD

MAKE_BASE=TRUE

GND

70 73

MAKE_BASE=TRUE

P3V3SUS_PGOOD

70

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

S5_PWRGD

69 70

PP3V3_PMICLDO

PP5V_S4

P5VS4_PGOOD P5VS4_PGOOD

GND

P3V3SUS_PGOOD

ALL_SYS_PWRGD

S5_PWRGD

MAKE_BASE=TRUE

70

OUT

71

72

65

46

70

73 70

71

72

72 70

IN

PVCCIO_PGOOD

P1VSUS_PGOOD

P1V8SUS_PGOOD

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

PP8100

PP8101

PP8102

PP8106

73 18

73 70 46 43 20 12

73 18

73 70

XDP:YES

10% 10V

0201

1

2

(INV)

XDP:YES

U8192

165

3

74AUP1T97GM

SOT886

4

P1V0S3_EN

XDP:YES

2

1

R8192

100K

5% 1/20W MF 201

2

(S4# OR XDP)

74

OUT

D

C8192

0.1UF

X5R-CERM

IN

XDP_PRESENT_L

PM_SLP_S4_L

XDP:NO

R8193

0

1 2

5%

1/20W

MF

201

PP3V3_SUS

18 73 110

XDP:YES

10% 10V

0201

1

2

(INV)

XDP:YES

U8194

1

5

6

3

2

74AUP1T97GM

SOT886

4

P1VS0SW_EN_RC

XDP:YES

1

R8194

100K

5% 1/20W MF 201

2

(S3# AND S0# OR XDP)

73

C

C8194

0.1UF

X5R-CERM

IN

XDP_PRESENT_L

PM_SLP_S0S3_L

XDP:NO

R8195

0

1 2

5%

1/20W

MF

201

B

S0i Enables

P1VS0SW_EN_RC

73

MAKE_BASE=TRUE

PM_SLP_S0S3_L

MAKE_BASE=TRUE

P1VS0SW_EN_RC

PM_SLP_S0S3_L

OUT

OUTIN

74

74 73 70

115 46 18 12

73 70

PM_RSMRST_L

MAKE_BASE=TRUE

GND

70 73

MAKE_BASE=TRUE

CPUVR_PGOOD

MAKE_BASE=TRUE

109

PM_RSMRST_L

CPUVR_PGOOD

PP1V8_S0PP1V8_S0

70

65

OUT

70

114 73 46 12

J80G specific

PM_PCH_SYS_PWROK

MAKE_BASE=TRUE

PP3V3_S0

12 14 20 110

114 73 46 12

PM_PCH_SYS_PWROK

10K

1%

1/20W

MF

201

1

2

R8199

70

B

A

73

PM_SLP_S3_L

R8164

100

1/20W

201

NO STUFF

P5VS0_EN_RD

5% MF

R8163

0

1 2

5%

1

2

1/20W

MF

201

D8163

SM-201

AK

RB521ZS-30

NO STUFF

BOM_COST_GROUP=PLATFORM POWER

P5VS0_EN

1

C8154

1.0UF

10% 25V

2

X6S 0402

NO STUFF

OUT

74

PAGE TITLE

PMIC-1 Aliases & TPs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/08/2015SYNC_MASTER=J80_SILUCHEN_MLB_BAFFIN

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

81 OF 145

SHEET

73 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

C

PP3V3_S5

110

73

IN

C8206

4700PF

73

IN

PM_SLP_S5_L

10% 10V X7R 201

PM_SLP_SUS_L PP3V3_SUS

PP3V3_S5

74 110

74 73

1

2

3.3V SUS Switch

U8200

SLG5AP1569V

STDFN

VIN ON

CRITICAL

GND

4

C8200

1.0UF

20%

6.3V X5R

0201-1

2

1

2

3.3V S4 Switch

U8203

TPS22969DNY

1

VIN

1

C8203

1.0UF

20%

6.3V

2

X5R 0201-1

2 4 3

CRITICAL

ON VBIAS

GND

5

R8209

0

1 2

5%

1/20W

MF

201

NOSTUFF

P3V3S4_EN_R

C8209

0.1UF

10% 16V

X5R-CERM

0201

1

2

3.3V S0 Switch

1

VDD

U8205

SLG5AP1445V

P3V3S0_CAP

74

PM_SLP_S3_L

IN

7 3

CAP

2 5

ON S

TDFN8

CRITICAL

GND

8

5V S0 Switch

PP5V_S4

110

VOUT

DFN8

EPAD

D

9

3

VOUT

6

PP3V3_S5

C8205

1.0UF

0201-1

PP3V3_S5

Type

R(on) @ 3.6V

Current

PP3V3_S4

1

20%

6.3V

2

X5R

110

EDP: 416mA

EDP: 3.55A

PP3V3_S0

EDP: 2.031A

U8200

SLG5AP1569VPart

Load Switch

34 mOhm Typ 46 mOhm Max

1A Max

110 117

74 110

Part

Type

R(on) @ 3.6V

Current 6A MAX

74 110

91 110

U8205

Part

Type

R(on) @ 3.6V

Current

U8203

TPS22969

Load Switch

4.4 MOHM TYP

6.6 MOHM MAX

SLG5AP1445V

Load Switch

7.8 MOHM TYP

8.5 MOHM MAX

4A MAX

PP3V3_S5

110

S3_STATE:YES

C8215

4700PF

10% 10V X7R 201

73

110

1

2

110

IN

PP3V3_S5

70

IN

PP3V3_S5

1UF

10% 10V X5R

1

2

C8211

402-1

PM_SLP_S5_L

P1V8S3_RAMP P1V8S3_EN

1.8V S4 LDO

U8212

LP5907MFX-1.8V

1 5

3

SOT23-5-COMBO

VIN

EN

GND

2

VOUT

NC1

4

1.8V S3 Switch

S3_STATE:YES

C8214

1UF

10% 10V X5R

402-1

1

2

7 3

CAP

2 5

ON S

1

S3_STATE:YES

VDD

U8215

SLG5AP1453V

TDFN

GND

8

D

1.8V S0 Switch

NC

1

C8212

1UF

10% 10V

2

X5R 402-1

PP1V8_SUS

S3_STATE:NO

R8281

1/20W

201

PP1V8_S4

EDP: 0.020 A

1

0

5% MF

2

Part Type R(on)

@ 5.3A Current

109

D8215

SOD523

AK

PP1V2_S3

PMEG3010EB/S500

D8216

SOD523

AK

PMEG3010EB/S500

PP1V8_S3

EDP: 0.550 A

U8215

SLG5AP1453V Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

C8296

4700PF

10% 10V X7R 201

109

71 109 117

109

S3_STATE:YES

1

C8284

2

74 73

1

2

100PF

5% 25V C0G 0201

P3V3S0_CAP

74

PM_SLP_S3_L

IN

110

P1V0S3_RAMP

PP3V3_S5

73

IN

3.3V S0 Switch LEFT

1

20%

6.3V

2

X5R

PP3V3_S0_LEFT

EDP: 2.031A

1

VDD

U8295

SLG5AP1445V

7 3

CAP

2 5

ON S

TDFN8

CRITICAL

GND

8

D

C8295

1.0UF

0201-1

PP3V3_S5

1.0V S3 Switch

S3_STATE:YES

1

P1V0S3_EN

C8283

0.1UF

10% 16V

2

X5R-CERM 0201

U8283

SLG5AP1635V

7 3

CAP

2 5

ON

1

VDD

STDFN

GND

8

S3_STATE:YES

D S

74 110

91 110

Part

Type

R(on) @ 3.6V

PP1V0_SUS

PP1V0_S3

Part Type R(on)

@ 25C Current

Ton Total

U8295

SLG5AP1445V

Load Switch

7.8 MOHM TYP

8.5 MOHM MAX

4A MAXCurrent

R8282

1

S3_STATE:NO

0

5%

1/20W

MF

201

2

EDP: 0.240 A

U8283

SLG5AP1635V Load Switch 20 mOhm Typ

28 mOhm Max

2.5A Max

39us max @ 1V

D

110

C

110

B

C8207

4700PF

10% 10V X7R 201

1

VDD

U8209

1

C8208

0.1UF

10% 16V

2

X5R-CERM 0201

C8218

402-1

SLG5AP1453V

P5VS0_FET_RAMP

73

1

2

IN

P5VS0_EN

7 3

CAP

2 5

ON S

TDFN

CRITICAL

GND

8

D

73

PP5V_S0

EDP: 1.6mA

110 117

C8219

4700PF

10% 10V X7R 201

1

2

IN

P1V8S0_RAMP

PM_SLP_S3_L

U8209

Part

Type Load Switch

R(on)

Current

SLG5AP1453V

7.8 mOhm Typ

9.6 mOhm Max

5.3A

1UF

10% 10V X5R

1

2

1

VDD

U8218

SLG5AP1453V

7 3

CAP

2 5

ON S

TDFN

GND

8

1.0V S0 SW Switch

D

PP1V8_SUS PP1V8_S0

EDP: 0.140 A

109

U8218

Part Type

@ 5.3A Current

SLG5AP1453V Load Switch

7.8 mOhm TypR(on)

9.6 mOhm Max

5.3A Max

1

C8287

100PF

5% 25V

2

C0G 0201

PP3V3_S5

110

P1V0S0SW_RAMP

73

IN

P1VS0SW_EN_RC

1

C8286

0.1UF

10% 16V

2

X5R-CERM 0201

1

VDD

U8285

SLG5AP1635V

7 3

CAP

2 5

ON

STDFN

GND

8

D S

Part

PP1V0_S3

U8285

SLG5AP1635V

PP1V0_S0SW

EDP: 0.04 A

B

110

A

110

PP3V3_S5

48

IN

3.3V Sensor Switch

SMC_SENSOR_PWR_EN

C8210

1.0UF

6.3V

0201-1

20% X5R

Type

1.2V S0 SW Switch

R(on) @ 25C

PP3V3_SUS

110

1UF

10% 10V X5R

1

2

7 3

CAP

2 5

ON S

U8210

SLG5AP1569V

2

VIN

1

ON

1

2

STDFN

CRITICAL

GND

4

VOUT

3

PP3V3_S4SW_SNS_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1200

Part

Type

R(on) @ 3.6V

Current

R8210

0

1 2

5% 1/16W MF-LF

402

U8210

SLGAP1569V

Load Switch

34 mOhm Typ 46 mOhm Max

1A Max

PP3V3_S4SW_SNS

110

10% 10V X7R 201

1

2

C8222

4700PF

BOMOPTION=VCCPLLOC:S0G

P1V2S0SW_RAMP

73

IN

PM_SLP_S0S3_L

C8221

402-1

1

VDD

U8220

SLG5AP1453V

TDFN

GND

8

BOMOPTION=VCCPLLOC:S0G

D

PP1V2_S3

1

R8220

0

5% 1/16W MF-LF 402

2

Part Type R(on)

@ 5.3A Current

BOMOPTION=VCCPLLOC:S3

PP1V2_S0SW

EDP: 0.260 A

U8220

SLG5AP1453V Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

109

BOM_COST_GROUP=PLATFORM POWER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

Current

Ton Total

Power FETs

Apple Inc.

R

Load Switch 20 mOhm Typ

28 mOhm Max

2.5A Max

39us max @ 1V

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 82 OF 145 74 OF 121

SYNC_DATE=12/11/2015SYNC_MASTER=J80_SAKKOC_MLB_BAFFIN

A

D

8 7 5 4 2 1

36

Page Notes

345678

2 1

D

C

109

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

PPBUS_G3H

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

740S0159

CRITICAL

F8400

3AMP-32V

1 2

75

0603

SENSOR ON PAGE 54 USES R8400 TO MEASURE THE

PPVIN_S0SW_LCDBKLT_FET

VOLTAGE=12.6V

50

ISNS_LCDBKLT_P

OUT

ISNS_LCDBKLT_N

OUT

CRITICAL

POWER GOING TO LCD BACKLIGHT

R8400

0.025

1% 1W MF

0612-1

1 2 3 4

107S00034

89

IN

EDP_BKLT_EN

PPVIN_S0SW_LCDBKLT_R

75

VOLTAGE=12.6V

1

C8400

1000PF

10% 16V

2

X7R-1 0201

1 2

GND_BKLT_SGND

75

1

R8401

80.6K

1% 1/16W MF-LF 402

2

1

R8402

63.4K

1% 1/16W MF-LF 402

2

R8442

0

5%

1/20W

MF

0201

CRITICAL

Q8400

FDC638APZ_SBMS001

SSOT6-HF

4

3

LCDBKLT_EN_L

PP5V_S0

75 110

PLACE_NEAR=U8400.5:5MM

75

GND_BKLT_SGND

1

R8440

1M

5% 1/20W MF 201

2

BKLT_SD

BKLT_SENSE_OUT

BKLT_EN_R

NO STUFF

1

C8442

33PF

5% 25V

2

NPO-C0G 0201

6 5 2 1

NOSTUFF

1

C8401

0.001UF

10% 50V

2

CERM 402

1/16W MF-LF

402

1UF

10% 10V X5R

402-1

5%

1

0

2

1

2

R8444

C8440

MIN_LINE_WIDTH=0.1200 MIN_NECK_WIDTH=0.6000

1

R8445

0

5% 1/16W MF-LF 402

2

75

PP5V_S0_BKLT_A PP5V_S0_BKLT_D

75

1

C8441

PLACE_NEAR=U8400.18:5MM

1UF

10% 10V

2

X5R 402-1

LP8548B1SQ_-03

11

SD

9

VSENSE_N

10

VSENSE_P

19

SENSE_OUT

17

EN

12

PWM_KEYB

15

SCL

16

SDA

PPVIN_S0SW_LCDBKLT

75

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V MAKE_BASE=TRUE

Ben IC - V3

18

5

VDDA

VDDD

U8400

QFN

SW SW

ISET_KEYB

KEYB1

(IPU)

CRITICAL

KEYB2

SW2

FB2

FB

GD

PLACE_NEAR=L8410.1:5MM

2

LCDBKLT_SW

1 21

LCDBKLT_FB

4

LCDBKLT_FET_DRV

20

NC

13

NC

14

NC

6

NC

8

NC

CRITICAL

1

C8410

4.7UF

10% 25V

2

X6S-CERM 0603

PLACEMENT_NOTE:

SANDWICH C8210 AND C8211

SANDWICH C8410 AND C8411

PLACE_NEAR=L8410.1:5MM

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=59V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.3000

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

GATE_NODE=TRUE

DIDT=TRUE

PLACE_NEAR=L8410.1:5MM

CRITICAL

1

C8411

4.7UF

10% 25V

2

X6S-CERM 0603

LCDBKLT_FET_DRV_R

75

PLACE_NEAR=Q8401.5:3MM

CRITICAL

L8410

15UH-20%-1.9A-0.24OHM

1 2

PIME062D-SM

152S00253

1

C8412

0.1UF

10% 25V

2

X5R 402

1

R8433

10

5% 1/16W MF-LF 402

2

371S00077

PLACE_NEAR=L8410.2:3MM

CRITICAL

D8410

SOD123-COMBO

A K

PMEG10020ELR-DFLS2100

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V MAKE_BASE=TRUE

75

PPVIN_SW_LCDBKLT_SW

5

4

1 2 3

PLACE_NEAR=U8400.1:5MM

376S0678

CRITICAL

Q8401

SI7812DN

PWRPK-1212-8

PLACE_NEAR=D8410.K:4MM

XW8410

2

SM

1

R8431

LCDBKLT_TB_XWR

28.7K

1% 1/16W MF-LF 402

2

1

R8432

150K

1% 1/16W MF-LF 402

2

PLACE_NEAR=D8410.K:8MM

CRITICAL

1

C8460

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:6MM

CRITICAL

1

C8465

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8470

2.2UF

10% 100V

2

X5R 1206

R8431:

28.7K FOR J80 DISPLAY.

NOSTUFF

1

C8430

100PF

5% 100V

2

C0G-CERM 0603

PLACE_NEAR=D8410.K:6MM

CRITICAL

1

C8461

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:8MM

CRITICAL

1

C8466

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:6MM

CRITICAL

1

C8471

2.2UF

10% 100V

2

X5R 1206

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V MAKE_BASE=TRUE

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8462

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8467

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:7MM

CRITICAL

1

C8472

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:6MM

CRITICAL

1

C8463

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8468

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8473

2.2UF

10% 100V

2

X5R 1206

VOUT = 52V TYP, 59V MAX IOUT = 0.135A TYP, 0.15A MAX FS = 625KHZ TYP (+/- 7%)

PLACE_NEAR=D8410.K:7MM

CRITICAL

1

C8464

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8469

2.2UF

10% 100V

2

X5R 1206

116 114 76 75

D

C

B

PP5V_S0

75 110

111

BI

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

I2C_BKLT_SCL

IN

I2C_BKLT_SDA

1

R8452

1.8K

5% 1/20W MF 201

2

BKLT_PWM_KEYB

1

R8447

10K

5% 1/20W MF 201

2

1

R8453

1.8K

5% 1/20W MF 201

2

PLACE_NEAR=U8400.15:10MM

R8450

0

1 2

5%

R8451

0

1 2

5%

1/20W

MF

PLACE_NEAR=U8400.16:10MM

0201

1/20W

MF

0201

BKLT_SCL

BKLT_SDA

GND_SW

7

23

24

XW8400

1 2

GND_SW2

3

SM

PAD

22

THRM

GNDA

GNDD

25

GND_BKLT_SGND

MIN_LINE_WIDTH=0.1500 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V

B

75

A

PBUS LINE WIDTHS

PP5V_S0_BKLT_A

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

PP5V_S0_BKLT_D

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

75 75

75

PPVIN_S0SW_LCDBKLT_FET

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V

PPVIN_S0SW_LCDBKLT_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V

PPVIN_S0SW_LCDBKLT_FET

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V

75

LCDBKLT_FET_DRV_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V

GATE_NODE=TRUE

DIDT=TRUE

8 7 5 4 2 1

LCD BKLT LINE WIDTHS

PPVIN_SW_LCDBKLT_SW

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V

SWITCH_NODE=TRUE

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V

DIDT=TRUE

75

PAGE TITLE

LCD Backlight Driver

116 114 76 75

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DISPLAY

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

36

051-00647

10.0.0

dvt-fab10

84 OF 145

75 OF 121

SYNC_DATE=12/03/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

A

D

PP5V_S0

110

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

345678

2 1

D

R8517

330

2015%

1/20W

MF

R8515

150K

5%

1/20W

MF

201

21

PANEL_P5V_EN_D

CRITICAL

1

VDD

U8500

SLG5AP1443V

LCD_PWR_SLEW

21

PANEL_P5V_EN

D8517

SC2

KA

DSF01S30SCAP

1

C8515

0.1UF

10% 10V

2

X5R-CERM 0201

1

C8509

2200PF

10% 10V

2

X7R-CERM 0201

CAP ON S

TDFN

GND

8

R8516

R8518

330

5%MF201 1/20W

200K

1/20W

21

PANEL_P3V3_EN_D

1% MF

201

21

PANEL_P3V3_EN

D8518

SC2

K A

DSF01S30SCAP

37

D

52

1

C8511

0.1UF

10% 10V

2

X5R-CERM 0201

1

C8512

10UF

20% 10V

2

X5R-CERM 0402-7

LCD_PWR_SLEW_3V3

1

C8516

0.47UF

10%

6.3V

2

CERM-X5R 0201

VOLTAGE=5V

PP5V_S0SW_LCD

PP3V3_S5

110

CRITICAL

SLG5AP1443V

CAP ON S

1

C8513

2200PF

10% 10V

2

X7R-CERM 0201

1

VDD

U8501

TDFN

GND

8

76 114

PPVOUT_S0_LCDBKLT

Stuff with 107S0276/107S0020 at Proto

OMIT

R8520

0.005

37

D

52

1

2

C8510

1.0UF

20% X5R

0201-1

VOLTAGE=3.3V

PP3V3_S0SW_LCD_R

6.3V

ISNS_LCDPANEL_P

52

ISNS_LCDPANEL_N

52

1/3W

0306-SHORT

1 3

NO_XNET_CONNECTION=1

1% MF

2 4

PP3V3_S0SW_LCD

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V

76 114

C8500

1000PF

100V

X7R-CERM

0603

1

10%

2

NO_XNET_CONNECTION=1

75 76 114 116

J8500

20759-042E-02

F-ST-SM

D

C

114

EDP_PANEL_PWR_EN

76 89

29 48 57 64 76

SMC_RESET_L

U8510 BYPASS

NO_STUFF

R8590

0

0201

MF

NO_STUFF

R8591

0

MF5%0201

NO_STUFF

R8592

0

5%

MF 0201

21

1/20W5%

21

1/20W

21

1/20W

BUF_EDP_PANEL_PWR_EN

PANEL_FET_EN_DLY

BUF_SMC_RESET_L

OUTIN

76

76 114

46 48 76

76

PANEL_FET_EN_DLY

109 47 46

PP3V3_G3H

CRITICAL

1

VDD

BUF_SMC_RESET_L DFR_DISP_PWR_EN DFR_DISP_SMC_RST_L

OUT OUT OUT

46 48 76

42

SLG4AP4998

76 89

IN

12 20 27 46 70 73 89 101 114

IN

29 48 57 64 76 114

IN

EDP_PANEL_PWR_EN

PM_SLP_S3_L SMC_RESET_L

2

EDP_PANEL_PWR_EN

4 8

PM_SLP_S3_L SMC_RESET_INPUT_L

U8510

PANEL_FET_EN_DLY

PANEL_PWR_EN_CONN

STQFN

SMC_RESET_OUTPUT_L

X604_DISP_PWR_EN

X604_DISP_SMC_RST_L

GND

7

NC0 NC1

3

912 6 10

5

NC_U8510_5

11

NC_U8510_11

BUF_EDP_PANEL_PWR_EN

76 114

114

38

114 76

76

BI BI

IN IN

76 114

PWR

SIGNAL

EDP_AUXCH_C_N EDP_AUXCH_C_P

EDP_INT_ML_N<0> EDP_INT_ML_P<0>

EDP_INT_ML_N<1> EDP_INT_ML_P<1>

EDP_INT_ML_N<2> EDP_INT_ML_P<2>

EDP_INT_ML_N<3> EDP_INT_ML_P<3>

MIPI_DATA_CONN_N

MIPI_CLK_CONN_N MIPI_CLK_CONN_P

PWR

PP5V_S0SW_LCD

4443

21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 2625 2827 3029 3231 3433 3635 3837 4039 4241

4645

PP3V3_S0SW_LCDPPVOUT_S0_LCDBKLT

BUF_EDP_PANEL_PWR_EN

DP_INT_HPD_R LCD_FSS LCD_IRQ_L

BKLT_PWM_TCON2MLB BKLT_PWM_MLB2TCON

I2C_BKLT_SDA I2C_BKLT_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL

I2C_ALS_SDAMIPI_DATA_CONN_P I2C_ALS_SCL I2C_CAM_SCL I2C_CAM_SDA

PP5V_S0_ALSCAM_F

76 114 75 76 116

76 114

76

76 89 114

15 114

OUT

48 114

OUT

20 114

IN

BI

111 114

IN

BI

49 114

IN

BI

42 114

IN

37 38 114

IN

BI

38 114

C

111 114

49 114

42 114

37 38 114

B

114

LCD_FSS

76 89

PP3V3_S0

110

NO_XNET_CONNECTION=1

NO_STUFF

1

R8503

1M

5% 1/20W MF 201

2

GND

111 114

IN

111 114

IN

111 114

IN

111 114

IN

111 114

IN

111 114

IN

EDP_INT_ML_P<0>

EDP_INT_ML_N<0>

EDP_INT_ML_P<1>

EDP_INT_ML_N<1>

EDP_INT_ML_P<2>

EDP_INT_ML_N<2>

EDP_INT_ML_P<0>

MAKE_BASE=TRUE

EDP_INT_ML_N<0>

MAKE_BASE=TRUE

EDP_INT_ML_P<1>

MAKE_BASE=TRUE

EDP_INT_ML_N<1>

MAKE_BASE=TRUE

EDP_INT_ML_P<2>

MAKE_BASE=TRUE

EDP_INT_ML_N<2>

MAKE_BASE=TRUE

76

4847 5049 5251 5453 5655 5857 6059 6261 6463 6665 6867

B

R8505

0

89 114

DP_INT_HPD DP_INT_HPD_R

OUT

5%

MF

21

1/20W

0201

76

EDP_AUXCH_C_N

114 76

EDP_AUXCH_C_P

114 76

111 114

IN

111 114

IN

EDP_INT_ML_P<3>

EDP_INT_ML_N<3>

EDP_INT_ML_P<3>

MAKE_BASE=TRUE

EDP_INT_ML_N<3>

MAKE_BASE=TRUE

76

A

NO_XNET_CONNECTION=1

R8504

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

1

2

1

2

R8501

LCD Panel HPD, FSS & AUX strapping

8 7 5 4 2 1

NO_STUFF

1

R8502

1M

5% 1/20W MF 201

2

111 113

BI

111 113

BI

EDP_AUXCH_C_P

EDP_AUXCH_C_N

EDP_AUXCH_C_P

MAKE_BASE=TRUE

EDP_AUXCH_C_N

MAKE_BASE=TRUE

114 76

A

SYNC_DATE=12/03/2015SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN

PAGE TITLE

eDP Display Connector

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

85 OF 145

SHEET

76 OF 121

BOM_COST_GROUP=DISPLAY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

36

D

345678

2 1

D

C

B

113 87

14

113 14

14

113 14

14

113 14

GND_VOID=TRUE

C8650

IN

PCIE_SSD_R2D_LB_P<0>

GND_VOID=TRUE

C8651

IN

PCIE_SSD_R2D_LB_N<0>

0.22UF

1 2

0.22UF

1 2

GND_VOID=TRUE

6.3V 0201X6S-CERM20%

GND_VOID=TRUE

6.3V

0201X6S-CERM20%

GND_VOID=TRUE

IN

PCIE_SSD_R2D_C_P<1>

C8652

0.22UF

1 2

GND_VOID=TRUE

X6S-CERM20% 6.3V

0201

GND_VOID=TRUE

IN

PCIE_SSD_R2D_C_N<1>

C8653

0.22UF

1 2

GND_VOID=TRUE

020120% 6.3V X6S-CERM

GND_VOID=TRUE

IN

PCIE_SSD_R2D_C_P<2>

C8654

0.22UF

1 2

GND_VOID=TRUE

0201X6S-CERM20% 6.3V

GND_VOID=TRUE

IN

PCIE_SSD_R2D_C_N<2>

C8655

0.22UF

1 2

GND_VOID=TRUE

02016.3V X6S-CERM20%

GND_VOID=TRUE

IN

PCIE_SSD_R2D_C_P<3>

GND_VOID=TRUE

C8657

C8656

IN

PCIE_SSD_R2D_C_N<3>

113 87

R8600

R8601

113 87

MF-LF

IN

49.9

1 2

1/16W

1 2

1%

49.9

1%

1/16W

402

IN

402

PCIE_CLK100M_SSD_LB_N

PCIE_CLK100M_SSD_LB_P

PLACE_NEAR=U8605.M1:3MM

MF-LF

PLACE_NEAR=U8605.N1:3MM

0.22UF

1 2

0.22UF

1 2

GND_VOID=TRUE

X6S-CERM0201 20% 6.3V

GND_VOID=TRUE

20%0201 6.3V X6S-CERM

PLACE_NEAR=U8605.J18:3MM

R8604

PP1V2_SSD_DRAM PP1V8_SSD_FMC

84 78 114 84 83 82 81 80 78 15

1

R8630

4.7K

1% 1/20W MF 201

2

1

R8632

4.7K

1% 1/20W MF 201

2

SSD_VREF_DQSSD_VREF_CA

77 77

PCIE_SSD_R2D_P<0>

113

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_P<1>

113

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<2>

113

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3>

113

PCIE_SSD_R2D_N<3>

PLACE_NEAR=U8605.AD10:3MM

R8602

240

1 2

1%

240

1 2

1%

240

1 2

1/20W1%MF 201

R8603

PLACE_NEAR=U8605.AE9:3MM

201

MF1/20W

77

83 82 77

MF1/20W 201

115 87

84

114 80

84 78 77

84 81 80

IN

IN IN OUT IN

1

R8620

4.7K

1% 1/20W MF 201

2

SSD_SZQ

PP1V2_SSD_DRAM_L12

SSD_I2C_CLK SSD_I2C_DAT

SSD_RESET_LB_L

SSD_RESET_B_L

SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO SSD_JTAG_TMS

SSD_FVREF0

SSD_ZQ0 SSD_ZQ1

SSD_SVREF1

SSD_VREF_CA SSD_VREF_DQ

SSD_FVREF0

NC

83 82 77

R2 P2

V2 U2

AB2 AA2

AD4 AD3

M1

N1

J3

F1

AD10

AE9 G14

F10

AD14

A16 P18

T18 V13 V15

D5 E3

J18

G11

D9 H6

D6

L2

D4

E4 C2 G1

RXDP0 RXDN0

RXDP1 RXDN1

RXDP2 RXDN2

RXDP3 RXDN3

REFCLKP REFCLKN

TESTMOD SUSCLK ZQ0

ZQ1 SVREF1

SVREF3 VREF_CA

VREF_DQ

VREF_NAND

FSOURCE0 FSOURCE1

SZQ SCKEIN

I2C_CLK I2C_DAT

PERST RESET* TCK

TDI TDO TMS

OMIT_TABLE

U8605

KG10000C2E-A200TAB

BGA

SYM 3 OF 5

CRITICAL

GP10_SPIDI_DO GP11_SPIDO_DI

PLL_REF_RETURN_01

PLL_REF_RETURN_23

TSEN_TEST_OUT

TXDP0 TXDN0

TXDP1 TXDN1

TXDP2 TXDN2

TXDP3 TXDN3

BOOTSEL

CLKOSCI

CLKOSCO

CLKREQ

GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7

GP8_SPICLK

GP9_SPICS

GP12 GP13 GP14 GP15

GP16_DAT

GP17_CLK

GP18_URX

GP19_UTX

GP20 GP21 GP22 GP23

PWRCON0 PWRCON1 PWRCON2 PWRCON3 PWRCON4

VDDPLL_01

REXT

VDDPLL_23

T1 R1

W1 V1

AC1 AB1

AE5 AE4

C10 B3

A3 H3 C9

C6 A6 B8 B9 D8 D3 G7 G8 C5 B7 B10 H4 F2 D7 C7 G2 J2 G4 G3 F8 B5 C3 D2

J4 K2 L3 K3 K1

P6 R4

P4 U6

AA4 G17

113

PCIE_SSD_D2R_C_P<0>

113

PCIE_SSD_D2R_C_N<0>

113

PCIE_SSD_D2R_C_P<1>

113

PCIE_SSD_D2R_C_N<1>

113

PCIE_SSD_D2R_C_P<2>

113

PCIE_SSD_D2R_C_N<2>

113

PCIE_SSD_D2R_C_P<3>

113

PCIE_SSD_D2R_C_N<3>

NC

SSD_CLKIN SSD_CLKOUT

SSD_CLKREQ_LB_L

NC NC NC NC NC NC

NC

SSD_PWRCON0 SSD_PWRCON1 SSD_PWRCON2 SSD_PWRCON3

NC

PP1V8_SSD_PLL01 PPVSS_SSD_PLL01

PREXT_SSD

PP1V8_SSD_PLL23 PPVSS_SSD_PLL23

NC

113 77

OUT

SSD_GP0 SSD_GP1

SSD_GP8 SSD_GP9 SSD_GP10

SSD_GP12 SSD_PGOOD_L

80

SSD_BOOT_LB_L

80 114

SSD_DEBUG_I2C_DAT SSD_DEBUG_I2C_CLK

SMC_OOB1_R2D_L SMC_OOB1_D2R_L

SSD_GP20 SSD_GP21 SSD_GP22 SSD_GP23

84

OUT

84

OUT

84

OUT

84

OUT

D

PLACE AC COUPLING CAPS NEAR U8605 IN LINEAR PATTERN, SAME SIDE

GND_VOID=TRUE

X6S-CERM20% 6.3V

GND_VOID=TRUE

20% 6.3V X6S-CERM

GND_VOID=TRUE

20% 6.3V X6S-CERM

GND_VOID=TRUE

20% 6.3V X6S-CERM

GND_VOID=TRUE

20% 6.3V X6S-CERM

GND_VOID=TRUE

20% 6.3V X6S-CERM

GND_VOID=TRUE

X6S-CERM

GND_VOID=TRUE

X6S-CERM6.3V20%

115 87

80

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

SSD_PGOOD_L

SSD_BOOT_LB_L SSD_DEBUG_I2C_DAT

SSD_DEBUG_I2C_CLK

1 2

0201

1 2

0201

1 2

0201

1 2

0201

1 2

0201

1 2

0201

1 2

020120% 6.3V

1 2

0201

MAKE_BASE=TRUE

114 80 48

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1200

80

IN

OUT

1

R8640

100K

1% 1/20W MF 201

2

PLACE_NEAR=U8605.P6:5MM

1

C8680

0.22UF

10% 16V

2

CERM 402

R8670

1 2

1/16W

PLACE_NEAR=U8605.R4:3MM

1K

1%

MF-LF

402

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1200

PLACE_NEAR=U8605.U6:5MM

1

C8683

0.22UF

10% 16V

2

CERM 402

C8640

0.22UF

C8641

0.22UF

C8642

0.22UF

C8643

0.22UF

C8644

0.22UF

C8645

0.22UF

C8646

0.22UF

C8647

0.22UF

IN

114 84

115 114 87

BI

OUT

1

2

1

C8684

1UF

10%

6.3V

2

X7R 0402

PCIE_SSD_D2R_LB_P<0>

PCIE_SSD_D2R_LB_N<0>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

113 77

SSD_CLKIN

PLACE_NEAR=Y8660.1:1MM

114 86

84 80 78

C8681

1UF

10%

6.3V X7R 0402

PP1V8_SSD_DRAM

1

C8682

1UF

10%

6.3V

2

X7R 0402

R8681

1 2

1

C8685

1UF

10%

6.3V

2

X7R 0402

1/16W MF-LF

10

1%

402

OUT

1

C8660

10PF

5% 50V

2

C0G 0201

R8680

10

1 2

1% 1/16W MF-LF

402

113 87

113 14

R8660

1 2

1/20W

Y8660

2.00X1.60-SM

25MHZ-30PPM-6PF-120OHM

1 3

PLACE_NEAR=U8605.B3:4MM

NC

1M

1% MF

201

4

2

PLACE_NEAR=U8605.A3:4MM

NCNC

NC

SSD_CLKOUT

1

R8661

240

1% 1/20W MF 201

2

PLACE_NEAR=Y8660.3:1MM

SSD_CLKOUT_R

PLACE_NEAR=Y8660.3:1MM

1

C8661

2

10PF

5% 50V C0G 0201

C

113 77

113

B

A

1

C8630

0.1UF

10% 16V

2

CER 0201

1

R8631

4.7K

1% 1/20W MF 201

2

1

C8631

0.1UF

10% 16V

2

CER 0201

1

R8633

4.7K

1% 1/20W MF 201

2

1

C8620

0.1UF

10% 16V

2

CER 0201

1

R8621

4.7K

1% 1/20W MF 201

2

84 78 77

PP1V2_SSD_DRAM_L12

1

C8610

0.1UF

10% 16V

2

CER 0201

1

R8610

4.7K

1% 1/20W MF 201

2

SSD_SVREF1

1

R8611

4.7K

1% 1/20W MF 201

2

77

8 7 5 4 2 1

PLL RETURN CONNECTS TO GND ON PACKAGE

SYNC_MASTER=X363_JSAMUELS

PAGE TITLE

POLARIS_CONTROLLER

DRAWING NUMBER SIZE

BOM_COST_GROUP=SSD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

36

051-00647

10.0.0 dvt-fab10 86 OF 145 77 OF 121

SYNC_DATE=04/01/2016

D

A

345678

2 1

D

C

114 84

PP1V0_SSD_CORE

1

C8746

12PF

5% 25V

2

NP0-C0G 0201

1

C8745

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

86 84

PP3V3_SSD_LIM

53

1

C8744

1UF

10%

6.3V

2

X7R 0402

1

C8796

12PF

5% 25V

2

NP0-C0G 0201

1

C8743

1UF

10%

6.3V

2

X7R 0402

1

C8797

2

1

C8742

0.1UF

10% 16V

2

CER 0201

84 80 78 77

84 78 77

3.0PF

+/-0.1PF 25V NP0-C0G 0201

PP1V8_SSD_DRAM

PP1V2_SSD_DRAM

C8795

0.22UF

1

C8741

0.1UF

10% 16V

2

CER 0201

20%

6.3V X5R

0201

1

2

1

C8740

0.1UF

10% 16V

2

CER 0201

B4

B23

AD8

AD21

A4

A8 A15 A23

C1

J1

AE8 AE14 AE18 AE21

E2 E1

M9

N10

P9

R10

T9

U10

VDD1

VDD2

VDD33_ALV33 VDD33_UART

VDD10_ALV

VDD10_SRAM

OMIT_TABLE

U8605

KG10000C2E-A200TAB

BGA

SYM 4 OF 5

CRITICAL

VDD18_ALV18

VDD18_GPIO

VDD18_LVDS

VDD18_NAND

K4 L4 M4

F6 G6

T7 F17

F20 J20 K18 L18 N18 N20 R18 U18 V10 V12 V14 V16 V18 Y12 Y18 Y20

PP1V8_SSD_DRAM

PP1V8_SSD_DRAM_L12

PP1V8_SSD_LVDS

PP1V8_SSD_FMC

78

84 78

PP1V1_SSD_PCIE

L8700

FERR-30-OHM-2.2A-0.035-OHM

PP1V1_SSD_LVDS

78

VOLTAGE=1.1V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

84 80 78 77

1

C8700

1UF

10%

6.3V

2

X7R 0402

84 80 78 77

1 2

1

C8701

0.1UF

10% 16V

2

CER 0201

PP1V8_SSD_DRAM

L8710

0402

D

FERR-30-OHM-2.2A-0.035-OHM

PP1V8_SSD_LVDS

78

84 78

114 84 83 82 81 80 78 77 15

VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

1

C8710

1UF

10%

6.3V

2

X7R 0402

1 2

1

C8711

0.1UF

10% 16V

2

CER 0201

0402

L8715

FERR-30-OHM-2.2A-0.035-OHM

PP1V8_SSD_OSC

78

VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

1

C8716

1UF

10%

6.3V

2

X7R 0402

1

2

1 2

C8715

0.1UF

10% 16V CER 0201

0402

C

84 78

PP1V8_SSD_DRAM_L12

B

84 78 77

84 78

PP1V0_SSD_CORE_L12

PP1V2_SSD_DRAM_L12

PP1V2_SSD_DRAM

PP1V0_SSD_CORE_L12

1

C8774

12PF

5% 25V

2

NP0-C0G 0201

1

C877B

12PF

5% 25V

2

NP0-C0G 0201

1

C8773

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C877A

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C8758

12PF

5% 25V

2

NP0-C0G 0201

1

C8757

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C8756

1UF

10%

6.3V

2

X7R 0402

L8760

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

1

C8761

1UF

10%

6.3V

2

X7R 0402

1

C8772

1UF

10%

6.3V

2

X7R 0402

1

C8779

1UF

10%

6.3V

2

X7R 0402

1

C8771

0.22UF

10% 16V

2

CERM 402

1

C8778

1UF

10%

6.3V

2

X7R 0402

1

C8770

0.1UF

10% 16V

2

CER 0201

1

C8777

1UF

10%

6.3V

2

X7R 0402

1

C8755

1UF

10%

6.3V

2

X7R 0402

VOLTAGE=1.0V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

1

C8760

0.1UF

10% 16V

2

CER 0201

1

C8776

2

0.1UF

10% 16V CER 0201

1

C8754

1UF

10%

6.3V

2

X7R 0402

1

2

84 78 77

C8775

0.1UF

10% 16V CER 0201

NOSTUFF

1

C8753

0.1UF

10% 16V

2

CER 0201

PP1V2_SSD_DRAM_L12

NOSTUFF

1

C8752

0.1UF

10% 16V

2

CER 0201

78

84 78 77

1

C8751

0.1UF

10% 16V

2

CER 0201

PP1V0_SSD_PLL

PP1V1_SSD_LVDS

PP1V2_SSD_DRAM

1

C8750

0.1UF

10% 16V

2

CER 0201

H17

K9 K11 K13 K15 K17

M11 M15 M17

P11 P15 P17 T11 T13 T15 T17

K8

R7 F11

G9

G13

H7

H8

H9

H10 H11 H12 H13 H14 H15 H16

VDD10_LOG

VDD10_PLL VDD11_LVDS VDD12_CKE

VDD12_DDR

VDD18_OSC

VDD18_PLL0 VDD18_PLL1 VDD18_PLL2 VDD18_PLL3

VDD18_TS

VDDCA

VDDIO_01

VDDIO_23_0 VDDIO_23_1

VDDIO_SENSE_01 VDDIO_SENSE_23

VDDQ

F4 M6

M7 K6 K7

G16 AE10

AE13 AE15 AE19

P8 R8

U8 V8

T4 AB4

A5 A7 A9 A11 A14 A17 A19 A22 C25 D1 D25 H1 H25

NC NC

PP1V8_SSD_OSC

PP1V8_SSD_PLL0 PP1V8_SSD_PLL1 PP1V8_SSD_PLL2 PP1V8_SSD_PLL3

PP1V8_SSD_FMC

PP1V2_SSD_DRAM

1

2

PP1V2_SSD_DRAM

78

C8702

0.1UF

10% 16V CER 0201

84 78 77

1

C8703

0.1UF

10% 16V

2

CER 0201

84 78 77

114 84 83 82 81 80 78 77 15

1

C8704

1UF

10%

6.3V

2

X7R 0402

1

C870C

12PF

5% 25V

2

NP0-C0G 0201

PP1V1_SSD_PCIE

1

C8705

1UF

10%

6.3V

2

X7R 0402

1

C870D

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

78

VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

84 78

VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

78

PP1V8_SSD_PLL0

PP1V8_SSD_PLL1

PP1V8_SSD_PLL2

PP1V8_SSD_PLL3

1

C8721

1UF

10%

6.3V

2

X7R 0402

1

C8726

1UF

10%

6.3V

2

X7R 0402

1

C8731

1UF

10%

6.3V

2

X7R 0402

1

C8736

1UF

10%

6.3V

2

X7R 0402

L8720

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

1

C8720

0.1UF

10% 16V

2

CER 0201

L8725

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

1

C8725

0.1UF

10% 16V

2

CER 0201

L8730

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

1

C8730

0.1UF

10% 16V

2

CER 0201

L8735

FERR-30-OHM-2.2A-0.035-OHM

1 2

0402

1

C8735

0.1UF

10% 16V

2

CER 0201

B

A

84 80 78 77

PP3V3_SSD_NAND

1

C870A

12PF

5% 25V

2

NP0-C0G 0201

1

C870B

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

PAGE TITLE

POLARIS POWER

Apple Inc.

R

PP1V8_SSD_DRAM

1

C8791

1UF

10%

6.3V

2

X7R 0402

1

C8790

1UF

10%

6.3V

2

X7R 0402

114 84 83 82 81 80 78 77 15

PP1V8_SSD_FMC

1

C8784

1UF

10%

6.3V

2

X7R 0402

1

C8783

1UF

10%

6.3V

2

X7R 0402

1

C8782

1UF

10%

6.3V

2

X7R 0402

1

C8781

0.22UF

10% 16V

2

CERM 402

1

C8780

0.1UF

10% 16V

2

CER 0201

84 83 82

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

87 OF 145

SHEET

78 OF 121

A

SYNC_DATE=05/18/2016SYNC_MASTER=X363_JSAMUELS

D

C

B

A

A1

A2 A10 A24 A25

B1

B2

B6 B12 B14 B21 B24 B25

C4

C8 C14 C16 C18 C20 D10 D12 D15 D23

E25

F7 F9

F14 G10 G15 G19 G22 G24

H2

J6 J7

J8 J10 J12 J14 J16

K19 K23 K25

L6 L7

L8 L10 L12 L14 L16

M3 M8

M18

N16 N23 N25 R12 R14 R16 R19 R24 U12 U14 U16 U23

V9 V11 V19 V25

W10 W14 W17

Y23

AA25 AB16 AB20 AB23

AC9 AC13 AD11 AD17 AD22 AD24 AD25 AE24 AE25

VSSI

OMIT_TABLE

U8605

KG10000C2E-A200TAB

BGA

SYM 5 OF 5

CRITICAL

VSSIO

VSS18_OSC

VSS_LVDS

L1 M2 N2 N3 N4 N6 N7 N8 P1 P3 R3 R6 T2 T3 T6 T8 U1 U3 U4 U7 V3 V4 V6 W2 W3 W4 W8 Y1 Y2 Y3 Y4 AA1 AA3 AB3 AB5 AC2 AC3 AC4 AC5 AD1 AD2 AD5 AD6 AE1 AE2 AE3 AE6 AE7

F3 P7

V7

345678

2 1

D

C

B

A

D

BOM_COST_GROUP=SSD

SYNC_MASTER=X363_JSAMUELS

PAGE TITLE

PAGE_TITLE=POLARIS GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=04/01/2016

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

88 OF 145

SHEET

79 OF 121

8 7 5 4 2 1

36

SSD RELATED BOM Groups

BOM GROUP BOM OPTIONS

SSD_CONFIG:1TB NAND_TYPE:1TB,SSD_CTRL_TYPE:8GBIT

345678

2 1

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

SSD_GPIO9,NAND_TYPE:256GB,SSD_CTRL_TYPE:4GBITSSD_CONFIG:256GB

TABLE_BOMGROUP_ITEM

SSD_GPIO8,NAND_TYPE:512GB,SSD_CTRL_TYPE:4GBITSSD_CONFIG:512GB

TABLE_BOMGROUP_ITEM

SSD_GPIO10,NAND_TYPE:2TB,SSD_CTRL_TYPE:8GBITSSD_CONFIG:2TB

D

77

SSD_GP0

SSD_GP1

NOSTUFF

R8926

0

1 2

5%

1/20W

MF

201

R8927

0

1 2

5%

1/20W

MF

201

SATA/NVME_L SELECT

ROM CODE DEBUG

NAND Parts

335S00149

335S00205 CRITICAL

4

NAND,1Z,64GBM,TOGG DDR2,64G,SS,BGA 168 CRITICAL4

NAND,V3,128GBM,TOGG DDR2,256G,SSBGA 1684

NAND,V3,256GBM,TOGG DDR2,256G,SS,BGA 168

NAND,V3,512GBM,TOGG DDR2,256G,SS,BGA 168

SSD Controller Parts

339S00154

POP,POLARIS+4GBIT,SSD CTRL,A2,BGA5161 CRITICAL POP,POLARIS+8GBIT,SSD CTRL,A2,BGA516339S00155 1

U9100,U9110,U9200,U9210

U8605

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL335S00204

CRITICAL4335S00219

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL

D

NAND_TYPE:256GB NAND_TYPE:512GB

NAND_TYPE:1TB NAND_TYPE:2TB

SSD_CTRL_TYPE:4GBIT

SSD_CTRL_TYPE:8GBIT

C

SSD_GP22

77

SSD_GP23

77

NOSTUFF

R8964

0

1 2

5%

1/20W

MF

201

R8967

0

1 2

5%

1/20W

MF

201

FORM FACTOR ID: TURNKIT=11

Internal pullup on GP22,GP23

84 81 77

SSD_I2C_CLK

SSD_I2C_DAT

84 78 77

PP1V8_SSD_DRAM

R8940

4.7K

1 2

1%

1/20W

MF

201

R8941

4.7K

1 2

1%

1/20W

MF

201

SSD_GPIO10

J8900

14-5843-12-022-829+

1

GND

114 77

114 103 86 114 103 86

OUT OUT OUT

SSD_JTAG_TMS SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO

IN IN BI

SSD_DEBUG_I2C_CLK_CONN

2

TMS

3

TCK

4

TDI

5

TDO UTX

6 7

MCTP_CLK

M-ST-SM

MCTP_DAT

BOMOPTION=SSD_DEBUG

VDD GP15 GP12

URX

12 11 10 9 8

PP1V8_SSD_FMC

SSD_BOOT_LB_L

SSD_GP12 SMC_OOB1_R2D_L SMC_OOB1_D2R_L

SSD_DEBUG_I2C_DAT_CONN

OUT OUT OUT

114 84 83 82 81 78 77 15

77

GND

13 14 15 16

SSD CONFIGURATIONS

OUT

114 77

C

114 77 48

1

R8975

0

NOSTUFF

5% 1/20W MF 201

2

B

SSD_PGOOD_L

77

SSD_GP20

77

SSD_GP21

77

NOSTUFF

R8929

0

1 2

5%

1/20W

MF

201

R8920

0

1 2

5%

1/20W

MF

201

R8960

0

1 2

5%

1/20W

MF

201

PMIC PGOOD

DEBUG

SSD_GP10

77

SSD_GP8

77

SSD_GP9

77

R8928

0

1 2

5%

1/20W

MF

201

SSD_GPIO8

R8980

0

1 2

5%

1/20W

MF

201

SSD_GPIO9

R8981

0

1 2

5%

1/20W

MF

201

SSD DENSITY

128 GB

256 GB

512 GB

1 TB

2 TB

NAND APN

335S00149

335S00204

335S00205

335S00219

CONTROLLER APNCAPACITY

--

339S00154 (A2 4GB DRAM)

339S00155 (A2 8GB DRAM)

R8980/GPIO8

STUFF-0

NOSTUFF-1

STUFF-0

NOSTUFF-1

R8981/GPIO9

STUFF-0

NOSTUFF-1

R8928/GPIO10

STUFF-0

NOSTUFF-1

STUFF-0

B

A

SYNC_MASTER=X363_JSAMUELS SYNC_DATE=04/01/2016

PAGE TITLE

Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 89 OF 145 80 OF 121

A

D

345678

2 1

D

C

PP1V8_SSD_FMC

15 77 78 80 81 82 83 84 114

ADDR: B'0011 000(R/W)

77 80 81 84

BI

77 80 81 84

IN

SSD_I2C_DAT

SSD_I2C_CLK

1

C9000

0.1UF

10% 16V

2

CER 0201

D

PP1V8_SSD_FMC

15 77 78 80 81 82 83 84 114

1

C9010

0.1UF

10% 16V

2

CER 0201

PLACE NEAR CONTROLLER on TOP side

8

VCC

U9000

CAT34TS00

1

A0

2

A1

3

A2

5

SDA

6

SCL

TDFN

CRITICAL

EVENT*

VSS EPAD

9

4

ADDR: B'0011 001(R/W)

IN

SSD_I2C_DAT

SSD_I2C_CLK

77 80 81 84

7

NC

BI

77 80 81 84

1

A0

2

A1

3

A2

5

SDA

6

SCL

U9010

CAT34TS00

CRITICAL

VSS EPAD

4

PLACE NEAR NAND U9100 on BOTTOM side

8

VCC

TDFN

EVENT*

9

7

NC

C

B

PP1V8_SSD_FMC

15 77 78 80 81 82 83 84 114

ADDR: B'0011 011(R/W)

77 80 81 84

SSD_I2C_DAT

BI

SSD_I2C_CLK

IN

1

C9030

0.1UF

10% 16V

2

CER 0201

PLACE NEAR NAND U9200 on BOTTOM side

8

VCC

B

U9030

CAT34TS00

1

A0

2

A1

3

A2

5

SDA

6

SCL

TDFN

CRITICAL

EVENT*

VSS EPAD

4

9

7

NC

A

SYNC_MASTER=J80_MLB

PAGE TITLE

PAGE_TITLE=TEMP SENSORS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 90 OF 145 81 OF 121

SYNC_DATE=11/06/2015

D

A

345678

2 1

D

C

B

A

84 83 82 78

113 85

114 84 83 82 81 80 78 77 15

PP3V3_SSD_NAND

1

C9156

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

SSD_NAND_FC_DQ0

BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI

SSD_NAND_FC_DQ1 SSD_NAND_FC_DQ2 SSD_NAND_FC_DQ3 SSD_NAND_FC_DQ4 SSD_NAND_FC_DQ5 SSD_NAND_FC_DQ6 SSD_NAND_FC_DQ7

SSD_NAND_FA_DQ0 SSD_NAND_FA_DQ1 SSD_NAND_FA_DQ2 SSD_NAND_FA_DQ3 SSD_NAND_FA_DQ4 SSD_NAND_FA_DQ5 SSD_NAND_FA_DQ6 SSD_NAND_FA_DQ7

PP1V8_SSD_FMC

1

C9150

12PF

5% 25V

2

NP0-C0G 0201

P10 N11

M10

L9 P5 N4

M5

L6

C5 D4 E5

F6 C10 D11 E10

F9

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

A1 A11 A12 A13 A14

A2

A3

A4

B1 B13 B14

B2

C1 C14

D1 D14

G13

G2 G4

G9 H10 H13

H2

H4 J11 J13

J2

J5 K11 K13

K2 K6 N1

N14

P1

P14

R1 R13 R14

R2

T1 T11 T12 T13 T14

T2

T3

T4

1

2

DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0

DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1

NC

NU

B3

B10

1

C9157

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

C9100

4.7UF

20% 10V X5R-CERM 0402

B6B9F13F2L13L2R6

VCC VPP

B5

C11

C12

C3

C4

1

C9151

2

D2

D13

12PF

5% 25V NP0-C0G 0201

R9

D5

E11

1

C9101

0.1UF

10% 16V

2

CER 0201

B11B4C13C2D10

D12D3E4E6F10L5M11M9N12N3N5

1

C9102

0.1UF

2

VCCQ

OMIT_TABLE

U9100

NAND-MLC-V3-CS-2TB-HDP

K9UUGY8S7M-1CK0TP1

BGA

CRITICAL

VSS

J4

E12

E2E3E9

E13

F5

H11

L10

M12

10% 16V CER 0201

M13

M2M3M4

84 83 82

M6

N10

PP12V_SSD_VPP

P13P2R11

N13

N2

P11

R4

P12

P3

B12

P4

R3

CE0_0* CE1_0* CE2_0* CE3_0*

CLE0

ALE0

WE0*

RE_0

RE_0*

DQS0

DQS0*

WP0*

R/B0_0* R/B1_0*

CE0_1* CE1_1* CE2_1* CE3_1*

CLE1

ALE1

WE1*

RE_1

RE_1*

DQS1

DQS1*

WP1*

R/B0_1* R/B1_1*

VREF

RESET0* RESET1*

RFU

R10

R12

R5

1

C9152

12PF

5% 25V

2

NP0-C0G 0201

K3 J3 K5 K4

K10 K9 J9

N6 P6

N9 P9

J10

G3 H3

G12 H12 G10 G11

G5 G6 H6

D9 C9

D6 C6

H5

K12 J12

F11 L4

J6 H9

F12 F3 F4 L11 L12 L3

1

C9158

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

SSD_NAND_FC_CE_B0_L SSD_NAND_FC_CE_B1_L SSD_NAND_FC_CE_B2_L SSD_NAND_FC_CE_B3_L

SSD_NAND_FC_CLE SSD_NAND_FC_ALE SSD_NAND_FC_WE_L

SSD_NAND_FC_RE_P SSD_NAND_FC_RE_N

SSD_NAND_FC_DQS_P SSD_NAND_FC_DQS_N

SSD_NAND_FC_RDY

SSD_NAND_FA_CE_B0_L SSD_NAND_FA_CE_B1_L SSD_NAND_FA_CE_B2_L SSD_NAND_FA_CE_B3_L

SSD_NAND_FA_CLE SSD_NAND_FA_ALE SSD_NAND_FA_WE_L

SSD_NAND_FA_RE_P SSD_NAND_FA_RE_N

SSD_NAND_FA_DQS_P SSD_NAND_FA_DQS_N

SSD_NAND_FA_RDY

SSD_NAND_FC_RESET_L SSD_NAND_FA_RESET_L

NC NC NC NC NC NC

85 113 85

INBI

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

114 84 83 82 81 80 78 77 15

BI BI

113 85

R9100

4.7K

1 2

1%

1/20W

MF

NOSTUFF

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

114 84 83 82 81 80 78 77 15

BI BI

113 85

201

R9101

4.7K

1 2

1%

1/20W

MF

201

SSD_FVREF0

1

85

IN

85

IN

C9103

0.1UF

10% 16V

2

CER 0201

84 83 82 78

PP3V3_SSD_NAND

PP1V8_SSD_FMC

NOSTUFF

113 85

83 82 77

1

C9159

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

BI BI BI BI BI BI BI BI

SSD_NAND_FB_DQ0 SSD_NAND_FB_CE_B0_L SSD_NAND_FB_DQ1 SSD_NAND_FB_DQ2 SSD_NAND_FB_DQ3 SSD_NAND_FB_DQ4 SSD_NAND_FB_DQ5 SSD_NAND_FB_DQ6 SSD_NAND_FB_DQ7

SSD_NAND_FD_DQ0 SSD_NAND_FD_DQ1 SSD_NAND_FD_DQ2 SSD_NAND_FD_DQ3 SSD_NAND_FD_DQ4 SSD_NAND_FD_DQ5 SSD_NAND_FD_DQ6 SSD_NAND_FD_DQ7

114 84 83 82 81 80 78 77 15

1

C9153

12PF

5% 25V

2

NP0-C0G 0201

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

PP1V8_SSD_FMC

1

2

P10

DQ0_0

N11

DQ1_0

M10

DQ2_0

L9

DQ3_0

P5

DQ4_0

N4

DQ5_0

M5

DQ6_0

L6

DQ7_0

C5

DQ0_1

D4

DQ1_1

E5

DQ2_1

F6

DQ3_1

C10

DQ4_1

D11

DQ5_1

E10

DQ6_1

F9

DQ7_1

A1 A11 A12 A13 A14

A2

A3

A4

B1 B13 B14

B2

C1

C14

D1

D14

G13

G2 G4

G9 H10 H13

NC

H2

H4 J11 J13

J2

J5 K11 K13

K2 K6 N1

N14

P1

P14

R1 R13 R14

R2

T1 T11 T12 T13 T14

T2

T3

NU

T4

B3

B10

C9160

3.0PF

+/-0.1PF 25V NP0-C0G 0201

1

C9154

2

B6B9F13F2L13L2R6

VCC VPP

B5

C11

C12

C3

C4

D13

D2

12PF

5% 25V NP0-C0G 0201

R9

D5

E11

1

C9110

0.1UF

10% 16V

2

CER 0201

B11B4C13C2D10

D12D3E4E6F10L5M11M9N12N3N5

1

C9111

0.1UF

10% 16V

2

CER 0201

VCCQ

OMIT_TABLE

U9110

NAND-MLC-V3-CS-2TB-HDP

K9UUGY8S7M-1CK0TP1

BGA

CRITICAL

VSS

J4

E12

E2E3E9

E13

F5

H11

L10

M12

PP12V_SSD_VPP

P13P2R11

N13

N2

P11

R4

P12

P3

M2M3M4

M13

84 83 82

M6

N10

BOM_COST_GROUP=SSD

B12

P4

R3

CE0_0* CE1_0* CE2_0* CE3_0*

CLE0 ALE0

WE0*

RE_0

RE_0*

DQS0

DQS0*

WP0*

R/B0_0* R/B1_0*

CE0_1* CE1_1* CE2_1* CE3_1*

CLE1 ALE1

WE1*

RE_1

RE_1*

DQS1

DQS1*

WP1*

R/B0_1* R/B1_1*

VREF

RESET0* RESET1*

RFU

R10

R12

1

C9155

12PF

5% 25V

2

NP0-C0G 0201

1

C9161

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

K3 J3

SSD_NAND_FB_CE_B1_L

K5

SSD_NAND_FB_CE_B2_L

K4

SSD_NAND_FB_CE_B3_L

K10

SSD_NAND_FB_CLE

K9

SSD_NAND_FB_ALE

J9

SSD_NAND_FB_WE_L

N6

SSD_NAND_FB_RE_P

P6

SSD_NAND_FB_RE_N

N9

SSD_NAND_FB_DQS_P

P9

SSD_NAND_FB_DQS_N

J10

G3 H3

G12 H12 G10 G11

G5 G6 H6

D9 C9

D6 C6

SSD_NAND_FB_RDY

SSD_NAND_FD_CE_B0_L SSD_NAND_FD_CE_B1_L SSD_NAND_FD_CE_B2_L SSD_NAND_FD_CE_B3_L

SSD_NAND_FD_CLE SSD_NAND_FD_ALE SSD_NAND_FD_WE_L

SSD_NAND_FD_RE_P SSD_NAND_FD_RE_N

SSD_NAND_FD_DQS_P SSD_NAND_FD_DQS_N

H5

K12 J12

SSD_NAND_FD_RDY

F11 L4

J6

SSD_NAND_FB_RESET_L

H9

SSD_NAND_FD_RESET_L

F12 F3 F4 L11 L12 L3

NC NC NC NC NC NC

R5

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

114 84 83 82 81 80 78 77 15

BI BI

113 85

R9110

4.7K

1 2

1%

1/20W

MF

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

85

IN

114 84 83 82 81 80 78 77 15

BI BI

113 85

201

R9111

4.7K

1 2

1%

1/20W

MF

201

SSD_FVREF0

1

85

IN

85

IN

NAND 1/2

C9112

0.1UF

10% 16V

2

CER 0201

PP1V8_SSD_FMC

NOSTUFF

PP1V8_SSD_FMC

NOSTUFF

77

83 82

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

91 OF 145

SHEET

82 OF 121

D

C

B

A

SYNC_DATE=08/09/2016SYNC_MASTER=X363_JSAMUELS

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

84 83 82 78

113 85

85

BI BI BI BI BI BI BI BI

114 84 83 82 81 80 78 77 15

PP3V3_SSD_NAND

1

C9256 C9250

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

SSD_NAND_FE_DQ0 SSD_NAND_FE_DQ1 SSD_NAND_FE_DQ2 SSD_NAND_FE_DQ3 SSD_NAND_FE_DQ4 SSD_NAND_FE_DQ5 SSD_NAND_FE_DQ6 SSD_NAND_FE_DQ7

SSD_NAND_FG_DQ0 SSD_NAND_FG_DQ1 SSD_NAND_FG_DQ2 SSD_NAND_FG_DQ3 SSD_NAND_FG_DQ4 SSD_NAND_FG_DQ5 SSD_NAND_FG_DQ6 SSD_NAND_FG_DQ7

PP1V8_SSD_FMC

1

12PF

5% 25V

2

NP0-C0G 0201

P10 N11

M10

L9

P5

N4

M5

L6

C5 D4

E5

F6 C10 D11 E10

F9

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

A1 A11 A12 A13 A14

A2

A3

A4

B1 B13 B14

B2

C1

C14

D1

D14

G13

G2 G4

G9 H10 H13

H2

H4

J11 J13

J2

J5 K11 K13

K2 K6

N1

N14

P1

P14

R1 R13 R14

R2

T1 T11 T12 T13 T14

T2

T3

T4

1

2

DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0

DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1

NC

NU

B3

B10

1

C9257

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

C9200

4.7UF

20% 10V X5R-CERM 0402

F13

B6

B9

B5

C11

C12

F2

L13L2R6

1

C9251

12PF

5% 25V

2

NP0-C0G 0201

R9

B11

B4

1

C9201

0.1UF

10% 16V

2

CER 0201

C13C2D10

D12D3E4E6F10L5M11M9N12N3N5

VCC VPP

1

C9202

0.1UF

10% 16V

2

CER 0201

VCCQ

84 83 82

P13P2R11

PP12V_SSD_VPP

R4

B12

OMIT_TABLE

U9200

NAND-MLC-V3-CS-2TB-HDP

K9UUGY8S7M-1CK0TP1

BGA

CRITICAL

VSS

J4

C3

C4

D13

D2

D5

E11

E12

E2E3E9

E13

F5

H11

L10

M12

M2M3M4

M13

M6

N10

N13

N2

P11

P12

P3

P4

R3

CE0_0* CE1_0* CE2_0* CE3_0*

CLE0 ALE0

WE0*

RE_0

RE_0*

DQS0

DQS0*

WP0*

R/B0_0* R/B1_0*

CE0_1* CE1_1* CE2_1* CE3_1*

CLE1 ALE1

WE1*

RE_1

RE_1*

DQS1

DQS1*

WP1*

R/B0_1* R/B1_1*

VREF

RESET0* RESET1*

RFU

R10

R12

R5

1

C9252

12PF

5% 25V

2

NP0-C0G 0201

K3

SSD_NAND_FE_CE_B0_L

J3

SSD_NAND_FE_CE_B1_L

K5

SSD_NAND_FE_CE_B2_L

K4

SSD_NAND_FE_CE_B3_L

K10

SSD_NAND_FE_CLE

K9

SSD_NAND_FE_ALE

J9

SSD_NAND_FE_WE_L

N6

SSD_NAND_FE_RE_P

P6

SSD_NAND_FE_RE_N

N9

SSD_NAND_FE_DQS_P

P9

SSD_NAND_FE_DQS_N

J10

G3 H3

G12 H12 G10 G11

G5 G6 H6

D9 C9

D6 C6

SSD_NAND_FE_RDY

SSD_NAND_FG_CE_B0_L SSD_NAND_FG_CE_B1_L SSD_NAND_FG_CE_B2_L SSD_NAND_FG_CE_B3_L

SSD_NAND_FG_CLE SSD_NAND_FG_ALE SSD_NAND_FG_WE_L

SSD_NAND_FG_RE_P SSD_NAND_FG_RE_N

SSD_NAND_FG_DQS_P SSD_NAND_FG_DQS_N

H5

K12 J12

SSD_NAND_FG_RDY

F11 L4

J6

SSD_NAND_FE_RESET_L

H9

SSD_NAND_FG_RESET_L

F12 F3 F4 L11 L12 L3

NC NC NC NC NC NC

1

C9258

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

IN IN IN IN

IN IN IN

IN IN

114 84 83

BI BI

IN IN IN IN

IN IN IN

IN IN

BI BI

IN IN

85

82 81 80 78 77 15

113 85

R9200

4.7K

1 2

1%

1/20W

MF

85

113 85

201

81 80 78 77 15

114 84 83 82

R9201

4.7K

1 2

1%

1/20W

MF

201

SSD_FVREF0

1

85

C9203

0.1UF

10% 16V

2

CER 0201

PP1V8_SSD_FMC

NOSTUFF

PP1V8_SSD_FMC

NOSTUFF

84 83 82 78

113 85

83 82 77

114 84 83 82 81 80 78 77 15

PP3V3_SSD_NAND

1

2

BI BI BI BI BI BI BI BI

SSD_NAND_FF_DQ1 SSD_NAND_FF_DQ2 SSD_NAND_FF_DQ3 SSD_NAND_FF_DQ4 SSD_NAND_FF_DQ5 SSD_NAND_FF_DQ6 SSD_NAND_FF_DQ7

SSD_NAND_FH_DQ0 SSD_NAND_FH_DQ1 SSD_NAND_FH_DQ2 SSD_NAND_FH_DQ3 SSD_NAND_FH_DQ4 SSD_NAND_FH_DQ5 SSD_NAND_FH_DQ6 SSD_NAND_FH_DQ7

C9259

3.0PF

+/-0.1PF 25V NP0-C0G 0201

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

PP1V8_SSD_FMC

1

C9253

12PF

5% 25V

2

NP0-C0G 0201

P10

DQ0_0

N11

DQ1_0

M10

DQ2_0

L9

DQ3_0

P5

DQ4_0

N4

DQ5_0

M5

DQ6_0

L6

DQ7_0

C5

DQ0_1

D4

DQ1_1

E5

DQ2_1

F6

DQ3_1

C10

DQ4_1

D11

DQ5_1

E10

DQ6_1

F9

DQ7_1

A1 A11 A12 A13 A14

A2

A3

A4

B1 B13 B14

B2

C1

C14

D1

D14 G13

G2 G4

G9 H10 H13

NC

H2

H4 J11 J13

J2

J5 K11 K13

K2 K6 N1

N14

P1

P14

R1 R13 R14

R2

T1 T11 T12 T13 T14

T2

T3

NU

T4

B10

1

C9260

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

B6B9F13F2L13L2R6

VCC VPP

B3

B5

C11

C12

C3

C4

D13

D2

1

2

R9

D5

C9254

12PF

5% 25V NP0-C0G 0201

B11B4C13C2D10

NAND-MLC-V3-CS-2TB-HDP

E12

E2E3E9

E13

E11

1

C9210

0.1UF

10% 16V

2

CER 0201

1

C9211

0.1UF

10% 16V

2

CER 0201

D12D3E4E6F10L5M11M9N12N3N5

VCCQ

OMIT_TABLE

U9210

K9UUGY8S7M-1CK0TP1

BGA

CRITICAL

VSS

J4

F5

H11

L10

M12

M2M3M4

M13

BOM_COST_GROUP=SSD

84 83 82

M6

N10

PP12V_SSD_VPP

P13P2R11

N13

N2

P11

R4

P12

P3

B12

P4

R3

CE0_0* CE1_0* CE2_0* CE3_0*

CLE0

ALE0

WE0*

RE_0

RE_0*

DQS0

DQS0*

WP0*

R/B0_0* R/B1_0*

CE0_1* CE1_1* CE2_1* CE3_1*

CLE1

ALE1

WE1*

RE_1

RE_1*

DQS1

DQS1*

WP1*

R/B0_1* R/B1_1*

VREF

RESET0* RESET1*

RFU

R10

R12

R5

1

C9255

12PF

5% 25V

2

NP0-C0G 0201

K3

SSD_NAND_FF_CE_B0_LSSD_NAND_FF_DQ0

J3

SSD_NAND_FF_CE_B1_L

K5

SSD_NAND_FF_CE_B2_L

K4

SSD_NAND_FF_CE_B3_L

K10

SSD_NAND_FF_CLE

K9

SSD_NAND_FF_ALE

J9

SSD_NAND_FF_WE_L

N6

SSD_NAND_FF_RE_P

P6

SSD_NAND_FF_RE_N

N9

SSD_NAND_FF_DQS_P

P9

SSD_NAND_FF_DQS_N

1

C9261

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

IN IN IN IN

IN IN IN

IN IN

J10

G3 H3

G12 H12 G10 G11

G5 G6 H6

D9 C9

D6 C6

SSD_NAND_FF_RDY

SSD_NAND_FH_CE_B0_L SSD_NAND_FH_CE_B1_L SSD_NAND_FH_CE_B2_L SSD_NAND_FH_CE_B3_L

SSD_NAND_FH_CLE SSD_NAND_FH_ALE SSD_NAND_FH_WE_L

SSD_NAND_FH_RE_P SSD_NAND_FH_RE_N

SSD_NAND_FH_DQS_P SSD_NAND_FH_DQS_N

IN IN IN IN

IN IN IN

IN IN

114 84 83 82 81 80 78 77 15

H5

K12 J12

SSD_NAND_FH_RDY

F11 L4

J6

SSD_NAND_FF_RESET_L

H9

SSD_NAND_FH_RESET_L

F12 F3 F4 L11 L12 L3

NC NC NC NC NC NC

PAGE TITLE

IN IN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

85

114 84 83 82 81 80 78 77 15

BI BI

113 85

R9210

4.7K

1 2

1%

1/20W

MF

85

BI BI

113 85

201

NOSTUFF

R9211

4.7K

1 2

1%

1/20W

MF

201

SSD_FVREF0

1

85

NAND 2/2

C9212

0.1UF

10% 16V

2

CER 0201

PP1V8_SSD_FMC

NOSTUFF

83 82 77

DRAWING NUMBER SIZE

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

92 OF 145

SHEET

83 OF 121

D

C

B

A

SYNC_DATE=08/09/2016SYNC_MASTER=X363_JSAMUELS

8 7 5 4 2 1

36

345678

2 1

CRITICAL

D

C

B

A

PP3V3_S5_POLARIS

87 115

1

C9300

22UF

20% 10V

2

X5R-CERM 0603-1

84

PP3V3_SSD_LIM

53 78 86

53 78 84 86

80

PP1V8_SSD_DRAM

77 78 84

77

OUT

87 115

IN

1

C9310

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9314

2.2UF

20%

6.3V

2

X5R-CERM 0201

PP3V3_SSD_LIM

1

R9321

4.7K

1% 1/20W MF 201

2

77 114

OUT

1

C9322

0.1UF

10% 16V

2

CER 0201

SSD PMIC Alternate Parts

1 2

3 4

1

C9308

0.1UF

10% 16V

2

CER 0201

1

C9311

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9315

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C9317

0.1UF

10% 16V

2

CER 0201

XW9300

ADDED XW ON AVIN

1

R9320

2

SSD_RESET_B_L

1

2

1

2

SM

21

100K

1% 1/20W MF 201

77

77 80 81

BI

PART NUMBER

152S00309152S00457 ALL

152S00310152S1721 ALL

U9300

TPS22965

SON

VIN

ON CT VBIAS

GND

5

C9312

22UF

20% 10V X5R-CERM 0603-1

C9318

0.1UF

10% 16V CER 0201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

PP3V3_SSD_PMIC_AVIN

1

C9320

2

SSD_PGOOD_L

SSD_PWRCON0

IN

SSD_I2C_CLK

IN

SSD_I2C_DAT

VOUT

EPAD

9

1

2

1

2

2.2UF

20%

6.3V X5R-CERM 0201

C9313

22UF

20% 10V X5R-CERM 0603-1

8 7

6

C9319

0.1UF

10% 16V CER 0201

U9390

TPS22965

GND

5

NC

SON

VOUT

EPAD

9

VOUT1

VOUT2

VOUT1

VOUT2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

PP3V3_SSD_ISNS_R

SSD_3V3_SSSSD_PWR_LB_EN

1

C9303

0.001UF

10% 50V

2

X7R-CERM 0402

1

C9301

22UF

20% 10V

2

X5R-CERM 0603-1

NOSTUFF

1

C9302

22UF

20% 10V

2

X5R-CERM 0603-1

CRITICAL

U9310

30 28

4 2 5

7 13 10 11 21 19

32 33

31 17 14 16 15

S2FPS04X01-1030

PVIN1 PGND1 PVIN2 PGND2 PVIN3 PGND3 PVIN4 PGND4 PGND4 PVIN5 PGND5

AVIN AGND

PG RSTO PMRST SCL SDA

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

QFN

EPAD

37

OTP_W

35

NC

TABLE_ALT_HEAD

TABLE_ALT_ITEM

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

PVIN6

PGND6

PVIN6O

VOUT6

OTP_R

36

SW1

SW2

SW3

SW4

SW5

SW6

LDO

29 27 3 1 6 8 12 9 20 18

PP3V3_SSD_LIM

26 23 25

P12V_SSD_VPP_SW

24 22

34

SSD_PMIC_LDO

1

C9321

1UF

10%

6.3V

2

X7R 0402

53

53 78 84 86

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000

SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE

0.47UH-20%-4.0A-28MOHM

P1V0_SSD_CORE_SW

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE

P1V2_SSD_DRAM_SW

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.4000 MIN_LINE_WIDTH=0.4000 SWITCH_NODE=TRUE DIDT=TRUE

0.47UH-20%-4.0A-28MOHM

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE

P1V8_SSD_DRAM_SW

L9360

21

PIFE25201B-SM

2.2UH-20%-1A-0.263OHM

1

C9381

2.2UF

20%

6.3V

2

X5R-CERM 0201

PLACE_NEAR=L9380.1:3MM

CRITICAL

L9330

21

PIFE25201B-SM

CRITICAL

L9340

1UH-20%-1.1A-0.1OHM

21

0805

CRITICAL

L9350

1UH-20%-1.1A-0.1OHM

21

0805

CRITICAL

1

C9360

22UF

20% 10V

2

X5R-CERM 0603-1

CRITICAL

L9370

0.47UH-20%-4.0A-28MOHM

21

PIFE25201B-SM

CRITICAL

L9380

0806

MIN_NECK_WIDTH=0.2000 SWITCH_NODE=TRUE

DIDT=TRUE

21

P12V_SSD_VPP_SW_L

1

C9330

22UF

20% 10V

2

X5R-CERM 0603-1

MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V

PP1V1_SSD_PCIEP1V1_SSD_PCIE_SW

1

C9340

22UF

20% 10V

2

X5R-CERM 0603-1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V

PP1V8_SSD_DRAM

1

C9350

22UF

20% 10V

2

X5R-CERM 0603-1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V

PP1V0_SSD_CORE

1

C9361

22UF

20% 10V

2

X5R-CERM 0603-1

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V

1

C9370

22UF

20% 10V

2

X5R-CERM 0603-1

MIN_LINE_WIDTH=0.2000

D9380

SOD1608

MIN_NECK_WIDTH=0.1200 VOLTAGE=12V

KA

PMEG4010EPKS500

CRITICAL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V

PP1V8_SSD_FMCP1V8_SSD_FMC_SW

1

C9331

22UF

20% 10V

2

X5R-CERM 0603-1

78

77 78 80 84

77 84

IN

78 84 114

PP1V2_SSD_DRAM

1

C9371

22UF

20% 10V

2

X5R-CERM 0603-1

PP12V_SSD_VPP

1

C9380

4.7UF

10% 25V

2

X5R-CER 0805

15 77 78 80 81 82 83 114

PP1V8_SSD_DRAM

77 78 80 84

SSD_PWRCON1

PP3V3_SSD_LIM

53 78 84 86

1

C9307

0.1UF

10% 16V

2

CER 0201

77 78 84

83 82

NOSTUFF

1

C9382

4.7UF

10% 35V

2

X5R-CERM 0603-1

PP1V2_SSD_DRAM

77 78 84

77 84

PP1V0_SSD_CORE

78 84 114

R9390

R9391

R9392

R9393

IN

53 78 84 86

SSD_PWRCON1

PP3V3_SSD_LIM

1/20W

1K

5%

1/20W

MF

201

1K

5%

1/20W

MF

201

PP3V3_SSD_LIM

53 78 84 86

77

1

C9306

0.1UF

10% 16V

2

CER 0201

1K

21

SSD_PWRCON1_R0

5% MF

201

1K

21

SSD_PWRCON1_R1

5% MF

201

21

SSD_PWRCON1_R2

21

SSD_PWRCON1_R3

IN

53 78 84 86

SSD_PWRCON2

PP3V3_SSD_LIM

1 2

3 4

77

IN

1

C9305

0.1UF

10% 16V

2

CER 0201

SSD_PWRCON3

1 2

3

ON CT

4

VBIAS

CRITICAL

U9393

TPS22965

SON

NC

VOUT

EPAD

9

TPS22966 POWER PINS USE SINGLE PAD ON PCB

1 3

12

4 6 5

10

1 3

12

4 6 5

10

VIN

ON CT VBIAS

GND

5

1

C9304

0.1UF

10% 16V

2

CER 0201

CRITICAL

U9391

TPS22965

SON

VIN

GND

EPAD

5

8 7

6

NC

VIN1 ON1 CT1 VBIAS VIN2 ON2 CT2

SYNC_MASTER=X363_JSAMUELS

PAGE TITLE

VOUT

9

1

VIN

2 3

ON CT

4

VBIAS

8 7

6

U9395

TPS22966

DPU

CRITICAL

GND

11

PAD

THRM

15

U9397

TPS22966

DPU

CRITICAL

GND

11

PAD

THRM

15

8 7

6

SSD_P3V3_NAND_CT

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V

PP1V8_SSD_DRAM_L12

13

8

13

8

MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V

PP3V3_SSD_NAND

1

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V

PP1V2_SSD_DRAM_L12

1

2

1

C9393

1UF

20% 4V

2

CERM-X6S 0201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V

PP1V0_SSD_CORE_L12

1

C9395

1UF

20% 4V

2

CERM-X6S 0201

78 82 83

C9390

33PF

5% 50V C0G 0402

C9391

1UF

20% 4V CERM-X6S 0201

78

77 78

78

SYNC_DATE=08/09/2016

D

C

B

A

PAGE_TITLE=POLARIS PMIC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 93 OF 145 84 OF 121

D

345678

2 1

D

C

82

113 82

82

OUT OUT BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT

OUT OUT OUT OUT

SSD_NAND_FA_ALE SSD_NAND_FA_CLE SSD_NAND_FA_DQS_N SSD_NAND_FA_DQS_P SSD_NAND_FA_DQ0 SSD_NAND_FA_DQ1 SSD_NAND_FA_DQ2 SSD_NAND_FA_DQ3 SSD_NAND_FA_DQ4 SSD_NAND_FA_DQ5 SSD_NAND_FA_DQ6 SSD_NAND_FA_DQ7 SSD_NAND_FA_CE_B0_L SSD_NAND_FA_CE_B1_L SSD_NAND_FA_CE_B2_L SSD_NAND_FA_CE_B3_L

NC NC NC NC

SSD_NAND_FA_RE_N SSD_NAND_FA_RE_P SSD_NAND_FA_WE_L SSD_NAND_FA_RESET_L SSD_NAND_FA_ZQ

85

B16 C17 A13 A12 B11 B13 C13 C12 D14 D11 D13 C11 A18

F12

B17

F13 B19 C15 B15

G12

F15

F16 D16 B18 D17

F0ALE F0CLE F0DQS* F0DQS F0DQ0 F0DQ1 F0DQ2 F0DQ3 F0DQ4 F0DQ5 F0DQ6 F0DQ7 F0CEB0 F0CEB1 F0CEB2 F0CEB3 F0CEB4 F0CEB5 F0CEB6 F0CEB7 F0RE* F0RE F0WE* F0NDRST* F0ZQ

OMIT_TABLE

U8605

KG10000C2E-A200TAB

BGA

SYM 1 OF 5

CRITICAL

20

F2NDRST*

F2ALE

F2CLE

F2DQS*

F2DQS

F2DQ0 F2DQ1 F2DQ2 F2DQ3 F2DQ4 F2DQ5 F2DQ6

F2DQ7 F2CEB0 F2CEB1 F2CEB2 F2CEB3 F2CEB4 F2CEB5 F2CEB6 F2CEB7

F2RE*

F2RE

F2WE*

K22 J22 F25 G25 F23 E22 F22 H22 H20 F24 H24 G23 J24 H23 M19 L19

SSD_NAND_FC_ALE SSD_NAND_FC_CLE SSD_NAND_FC_DQS_N SSD_NAND_FC_DQS_P SSD_NAND_FC_DQ0 SSD_NAND_FC_DQ1 SSD_NAND_FC_DQ2 SSD_NAND_FC_DQ3 SSD_NAND_FC_DQ4 SSD_NAND_FC_DQ5 SSD_NAND_FC_DQ6

SSD_NAND_FC_DQ7 SSD_NAND_FC_CE_B0_L SSD_NAND_FC_CE_B1_L SSD_NAND_FC_CE_B2_L SSD_NAND_FC_CE_B3_L

L22 J25 K24 N19 K20 L20 M20 J23

SSD_NAND_FC_RE_N

SSD_NAND_FC_RE_P

SSD_NAND_FC_WE_L SSD_NAND_FC_RESET_L

NC NC NC NC

OUT OUT

BI BI BI BI BI BI BI BI BI

BI OUT OUT OUT OUT

OUT OUT OUT OUT

82

D

OMIT_TABLE

U8605

KG10000C2E-A200TAB

BGA

SYM 2 OF 5

83

OUT

83

OUT

113 82

113 83

83

BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT

SSD_NAND_FE_ALE SSD_NAND_FE_CLE SSD_NAND_FE_DQS_N SSD_NAND_FE_DQS_P SSD_NAND_FE_DQ0 SSD_NAND_FE_DQ1 SSD_NAND_FE_DQ2 SSD_NAND_FE_DQ3 SSD_NAND_FE_DQ4 SSD_NAND_FE_DQ5 SSD_NAND_FE_DQ6 SSD_NAND_FE_DQ7 SSD_NAND_FE_CE_B0_L SSD_NAND_FE_CE_B1_L SSD_NAND_FE_CE_B2_L SSD_NAND_FE_CE_B3_L

NC NC NC NC NC

83

OUT OUT OUT OUT

SSD_NAND_FE_RE_N SSD_NAND_FE_RE_P SSD_NAND_FE_WE_L SSD_NAND_FE_RESET_L

W23

Y24

W25

Y25 V24

U24

T23

U25

T24 V23

U22

V22

W22

Y22 Y19

W19 AA23 AA24 AA22

W18

V20 W20 W24

U20

F4ALE F4CLE F4DQS* F4DQS F4DQ0 F4DQ1 F4DQ2 F4DQ3 F4DQ4 F4DQ5 F4DQ6 F4DQ7 F4CEB0 F4CEB1 F4CEB2 F4CEB3 F4CEB4 F4CEB5 F4CEB6 F4CEB7 F4RE* F4RE F4WE* F4NDRST*

CRITICAL

64

F6ALE

F6CLE

F6DQS*

F6DQS

F6DQ0 F6DQ1 F6DQ2 F6DQ3 F6DQ4 F6DQ5 F6DQ6

F6DQ7 F6CEB0 F6CEB1 F6CEB2 F6CEB3 F6CEB4 F6CEB5 F6CEB6 F6CEB7

F6RE*

F6RE

F6WE*

F6NDRST*

W13 Y15 AE16 AE17 AC18 AB17 AD18 AC17 AC16 AB15 AC15 AD16 AD15 AC14 W12 AD13

SSD_NAND_FG_ALE SSD_NAND_FG_CLE SSD_NAND_FG_DQS_N SSD_NAND_FG_DQS_P SSD_NAND_FG_DQ0 SSD_NAND_FG_DQ1 SSD_NAND_FG_DQ2 SSD_NAND_FG_DQ3 SSD_NAND_FG_DQ4 SSD_NAND_FG_DQ5 SSD_NAND_FG_DQ6

SSD_NAND_FG_DQ7 SSD_NAND_FG_CE_B0_L SSD_NAND_FG_CE_B1_L SSD_NAND_FG_CE_B2_L SSD_NAND_FG_CE_B3_L

W11 AB11 AC12 AB12 Y14 Y13 AB13 AB14

SSD_NAND_FG_RE_N

SSD_NAND_FG_RE_P

SSD_NAND_FG_WE_L SSD_NAND_FG_RESET_L

NC NC NC

OUT OUT

BI BI BI BI BI BI BI BI BI

BI OUT OUT OUT OUT

OUT OUT OUT OUT

83

113 83

83

113 83

83

C

83

B

82

113 82

82

OUT OUT BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT

OUT OUT OUT OUT

SSD_NAND_FB_ALE SSD_NAND_FB_CLE SSD_NAND_FB_DQS_N SSD_NAND_FB_DQS_P SSD_NAND_FB_DQ0 SSD_NAND_FB_DQ1 SSD_NAND_FB_DQ2 SSD_NAND_FB_DQ3 SSD_NAND_FB_DQ4 SSD_NAND_FB_DQ5 SSD_NAND_FB_DQ6 SSD_NAND_FB_DQ7 SSD_NAND_FB_CE_B0_L SSD_NAND_FB_CE_B1_L SSD_NAND_FB_CE_B2_L SSD_NAND_FB_CE_B3_L

NC NC NC NC

SSD_NAND_FB_RE_N SSD_NAND_FB_RE_P SSD_NAND_FB_WE_L SSD_NAND_FB_RESET_L

D22 C22 A20 A21 D20 D18 C19 D21 D19 B20 B22 C21 H18

G18

C23 E23 E24

J19

G20

D24

F18

F19 H19 C24

F1ALE F1CLE F1DQS* F1DQS F1DQ0 F1DQ1 F1DQ2 F1DQ3 F1DQ4 F1DQ5 F1DQ6 F1DQ7 F1CEB0 F1CEB1 F1CEB2 F1CEB3 F1CEB4 F1CEB5 F1CEB6 F1CEB7 F1RE* F1RE F1WE* F1NDRST*

1 3

F3ALE

F3CLE

F3DQS*

F3DQS

F3DQ0 F3DQ1 F3DQ2 F3DQ3 F3DQ4 F3DQ5 F3DQ6

F3DQ7 F3CEB0 F3CEB1 F3CEB2 F3CEB3 F3CEB4 F3CEB5 F3CEB6 F3CEB7

F3RE*

F3RE

F3WE*

F3NDRST*

P23 T19 M25 L25 L23 P19 L24 M22 M23 N22 N24 M24 T25 R22 P24 T22

SSD_NAND_FD_ALE SSD_NAND_FD_CLE SSD_NAND_FD_DQS_N SSD_NAND_FD_DQS_P SSD_NAND_FD_DQ0 SSD_NAND_FD_DQ1 SSD_NAND_FD_DQ2 SSD_NAND_FD_DQ3 SSD_NAND_FD_DQ4 SSD_NAND_FD_DQ5 SSD_NAND_FD_DQ6

SSD_NAND_FD_DQ7 SSD_NAND_FD_CE_B0_L SSD_NAND_FD_CE_B1_L SSD_NAND_FD_CE_B2_L

SSD_NAND_FD_CE_B3_L

R23 P25 U19 R25 R20 P20 P22 T20

SSD_NAND_FD_RE_N

SSD_NAND_FD_RE_P

SSD_NAND_FD_WE_L SSD_NAND_FD_RESET_L

NC NC NC NC

OUT OUT

BI BI BI BI BI BI BI BI BI

BI OUT OUT OUT OUT

OUT OUT OUT OUT

82

83

OUT

83

OUT

113 82

113 83

83

BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT

SSD_NAND_FF_ALE SSD_NAND_FF_CLE SSD_NAND_FF_DQS_N SSD_NAND_FF_DQS_P SSD_NAND_FF_DQ0 SSD_NAND_FF_DQ1 SSD_NAND_FF_DQ2 SSD_NAND_FF_DQ3 SSD_NAND_FF_DQ4 SSD_NAND_FF_DQ5 SSD_NAND_FF_DQ6 SSD_NAND_FF_DQ7 SSD_NAND_FF_CE_B0_L SSD_NAND_FF_CE_B1_L SSD_NAND_FF_CE_B2_L SSD_NAND_FF_CE_B3_L

NC NC NC NC

83

OUT OUT OUT OUT

SSD_NAND_FF_RE_N SSD_NAND_FF_RE_P SSD_NAND_FF_WE_L SSD_NAND_FF_RESET_L

V17 AB18 AE22 AE23 AB25

AC24

AB24

AC25 AC23

AB22

AC22 AD23 AC20 AC21 AD20

AB21

W15 W16

AD19

AE20

Y16

Y17 AB19

AC19

F5ALE F5CLE F5DQS* F5DQS F5DQ0 F5DQ1 F5DQ2 F5DQ3 F5DQ4 F5DQ5 F5DQ6 F5DQ7 F5CEB0 F5CEB1 F5CEB2 F5CEB3 F5CEB4 F5CEB5 F5CEB6 F5CEB7 F5RE* F5RE F5WE* F5NDRST*

5 7

F7ALE

F7CLE

F7DQS*

F7DQS

F7DQ0 F7DQ1 F7DQ2 F7DQ3 F7DQ4 F7DQ5 F7DQ6

F7DQ7 F7CEB0 F7CEB1 F7CEB2 F7CEB3 F7CEB4 F7CEB5 F7CEB6 F7CEB7

F7RE*

F7RE

F7WE*

F7NDRST*

W9 AC7 AE12 AE11 AD12 AC11 AB10 AC10 AB9 AD9 AB8 AC8 AB7 Y7 W7 AB6

SSD_NAND_FH_ALE SSD_NAND_FH_CLE SSD_NAND_FH_DQS_N SSD_NAND_FH_DQS_P SSD_NAND_FH_DQ0 SSD_NAND_FH_DQ1 SSD_NAND_FH_DQ2 SSD_NAND_FH_DQ3 SSD_NAND_FH_DQ4 SSD_NAND_FH_DQ5 SSD_NAND_FH_DQ6

SSD_NAND_FH_DQ7 SSD_NAND_FH_CE_B0_L SSD_NAND_FH_CE_B1_L SSD_NAND_FH_CE_B2_L SSD_NAND_FH_CE_B3_L

Y6 W6 Y8 AC6 Y10 Y11 Y9 AD7

SSD_NAND_FH_RE_N

SSD_NAND_FH_RE_P

SSD_NAND_FH_WE_L SSD_NAND_FH_RESET_L

NC NC NC NC

OUT OUT

BI BI BI BI BI BI BI BI BI

BI OUT OUT OUT OUT

OUT OUT OUT OUT

83

113 83

83

B

83

A

SSD_NAND_FA_ZQ

85

1

R9400

240

1% 1/20W MF 201

2

BOM_COST_GROUP=SSD

SYNC_MASTER=X363_JSAMUELS SYNC_DATE=04/01/2016

PAGE TITLE

SSD NAND VR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

94 OF 145

SHEET

85 OF 121

D

A

8 7 5 4 2 1

36

345678

2 1

D

84 78 53

D

PP3V3_SSD_LIM

C

114 77

SSD_DEBUG_I2C_CLK SSD_DEBUG_I2C_DAT

BI

From Polaris

SSD_DEBUGI2C_SEL_PCH

15

NO_XNET_CONNECTION=1

1 2

CRITICAL

Y+ Y-

U9500

PI3USB102EZLE

TQFN

10

PLACE_NEAR=U9500:2mm

9

VCC

5

M+

4

M-

7

D+

6

D-

SSD_DEBUG_MUX_OE

8

OE*SEL

GND

3

1

C9500

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R9504

1K

5% 1/20W MF 201

2

1

R9550

1K

5% 1/20W MF 201

2

1

R9551

1K

5% 1/20W MF 201

2

SSD_DEBUG_I2C_CLK_CONN SSD_DEBUG_I2C_DAT_CONN

From Debug Connector / ACE TA SPEED = 3.2Mbps SEL = LOW

I2C_SSD_SCL I2C_SSD_SDA

From PCH SPEED = 1Mbps

SEL = HIGH

C

INOUT

BI

15

IN

BI

114 103 80 114 77

114 103 80

15

B

NOSTUFF

NO_XNET_CONNECTION=1

NOSTUFF

NO_XNET_CONNECTION=1

R9503

0

1 2

5%

1/20W

MF

201

R9502

0

1 2

5%

1/20W

MF

201

B

A

SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/15/2016

PAGE TITLE

SSD SUPPORT

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 95 OF 145 86 OF 121

A

D

345678

2 1

D

C

LIFEBOAT

J9600

20759-042E-02

PCH Side SSD Side

PP3V3_S5

110

115 114 15

115 114 14

115 20

113 14

14

113 14

113 12

113 12 113 77

SSD_BOOT_L

IN

SSD_PWR_EN

IN

SSD_RESET_L

SSD_CLKREQ_L

OUT

PCIE_SSD_D2R_N<0>

OUT

PCIE_SSD_R2D_C_P<0>

IN

PCIE_SSD_R2D_C_N<0>

IN

PCIE_CLK100M_SSD_P

IN

PCIE_CLK100M_SSD_N

IN OUT

GND_VOID=TRUE

F-ST-SM

43 44

PWR

SIGNAL

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

GND_VOID=TRUE

PP3V3_S5_POLARIS

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

SSD_BOOT_LB_L SSD_PWR_LB_EN

SSD_RESET_LB_L SSD_CLKREQ_LB_L

PCIE_SSD_D2R_LB_P<0>PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_LB_N<0>

PCIE_SSD_R2D_LB_P<0> PCIE_SSD_R2D_LB_N<0>

PCIE_CLK100M_SSD_LB_P PCIE_CLK100M_SSD_LB_N

Detect Pin

115 84

NC

OUT OUT

NC

OUTIN

IN

IN IN

OUT OUT

OUT

D

115 114 77

115 84

115 77 115 114 20 14

115 77

113 77

C

B

PWR

45 46

GND

47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

B

A

PAGE TITLE

Lifeboat

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=01/20/2016SYNC_MASTER=X363_BBABADI

051-00647

10.0.0 dvt-fab10 96 OF 145 87 OF 121

A

D

345678

2 1

D

C

B

A

SYNC_MASTER=Constraints SYNC_DATE=05/18/2016

PAGE TITLE

Constraints

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 97 OF 145 88 OF 121

A

D

C

B

A

CONNECT I2C TO LCD BKLT IC

PP3V3_S0_DPMUX_UC_R

89

DPMUX_UC_TX

111 89

DPMUX_UC_RX

111 89

DPMUX_UC_RESET_L

89

DPMUX_UC_MD1

89

TP_DPMUX_UC_P10 TP_DPMUX_UC_P11 TP_DPMUX_UC_P12 TP_DPMUX_UC_P13 TP_DPMUX_UC_P14 TP_DPMUX_UC_P15 TP_DPMUX_UC_P16 TP_DPMUX_UC_P17

91 89

111 89

OUT OUT OUT OUT OUT

98 89

OUT

EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_RAIL5_EN EG_CLKREQ_SEL_L EG_RESET_L TP_FB_CLAMP

46 12

20

IN

89 20

IN

LPC_AD<0>

BI

LPC_AD<1>

BI

LPC_AD<2>

BI

LPC_AD<3>

BI

LPC_FRAME_L DPMUX_LRESET_L LPC_CLK24M_DPMUX_UC

TP_DPMUX_UC_P37

TP_DPMUX_UC_P40 TP_DPMUX_UC_P41 TP_DPMUX_UC_P42

114 76

IN

89

LCD_FSS LCD_MUX_SEL TP_DPMUX_UC_P45 TP_DPMUX_UC_P46 TP_DPMUX_UC_P47

111 89

OUT

IN

DPMUX_UC_TX DPMUX_UC_RX TP_DPMUX_UC_P52

49

20

89 48 46

BI OUT OUT

OUT

I2C_DPMUX_UC_SDA I2C_DPMUX_UC_SCL DPMUX_UC_IRQ

SMC_GFX_OVERTEMP

TP_FB_CLAMP_TOGGLE_REQ_L

TP_DPA_EG_HPD

99 89

99

89 46

99 89

89 76

89 75

OUT OUT OUT OUT OUT OUT OUT

OUT OUT

DP_X_SNK0_HPD_EG DP_X_SNK1_HPD_EG DP_T_SNK0_HPD_EG DP_T_SNK1_HPD_EG GPU_GFX_PWR_LEVEL_L SMC_GFX_SELF_THROTTLE DP_INT_EG_HPD

EDP_PANEL_PWR_EN EDP_BKLT_EN TP_DPMUX_UC_PC2 TP_DPMUX_UC_PC3

89

LCD_MUX_EN TP_LCD_MUX_REQ

89 20

OUT

BKLT_PWM_MLB2TCON TP_DPMUX_UC_PC7

TP_DPA_IG_HPD

89 15

OUT OUT OUT OUT

DP_X_SNK0_HPD_IG DP_X_SNK1_HPD_IG DP_T_SNK0_HPD_IG DP_T_SNK1_HPD_IG TP_DPMUX_UC_PD5 TP_DPMUX_UC_PD6

89 15

OUT

DP_INT_IG_HPD

DPMUX UC DEBUG HEADER

J9800

1909782

M-RT-SM

7

1 2 3 4 5 6

8

DPMUX_DEBUG

B12 A13 A12 B13 D11 C13 C12 D10

D13 E11 D12

F11 E13 E12

F13 E10

A9 D9 C8

B7

A8 D8 D7

P36/LCLK

D6 D4

A5

B4

A1 C2

B2 C1 C3

G2

F3

E4

N3 N1

M3

NC NC NC

M2

N2

K3

B8 C9 B9

A10

C10

B10

C11

A11

G11 G13

F12

H13 G10 G12

H11

J13

M10

N9

K10

M9

N8 K9

R9890

10K

5%

1/20W

MF

201

R9891

10K

5%

1/20W

MF

201

U9800

P10/WUE0* P11/WUE1* P12/WUE2* P13/WUE3* P14/WUE4* P15/WUE5* P16/WUE6* P17/WUE7*

P20 P21 P22 P23 P24 P25 P26 P27

P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAM* P35/LRESET*

was 33MHz now 24MHz!!!

P37/SERIRQ P40/TMI0/TCMCYI0

P41/TMO0/TCMCKI0/TCMMCI0 P42/TCMCYI1 P43/TMI1/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWMU4B P47/PWMU5B

P50/FTXD P51/FRXD P52/SCL0

PA0/KIN8*/SDA1 PA1/KIN9*/SCL1 PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD PA4/KIN12*/PS2BC

L1

PA5/KIN13*/PS2BD PA6/KIN14*/PS2CC

L2

PA7/KIN15*/PS2CD PB0/LSMI*

PB1/LSCI PB2/RI*/PWMU0B PB3/DCD*/PWMU1B PB4/DSR*/FSIDO PB5/DTR*/FSIDI PB6/CTS*/FSICK PB7/RTS*/FSISS

PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10* PC3/TIOCD0/TCLKB/WUE11* PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15*

PD0/AN8 PD1/AN9 PD2/AN10

L8

PD3/AN11 PD4/SSO PD5/SSI PD6/SSCK

L7

PD7/SCS

PP3V3_S0

1

DPMUX_XTAL:YES

2

DPMUX_UC_MDCKN

1

DPMUX_XTAL:NO

2

R4F2113NLG

TLP-145V

SYM 1 OF 3

OMIT_TABLE

R4F2113NLG

TLP-145V

SYM 2 OF 3

OMIT_TABLE

U9800

49 89 98 110

89

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4* P65/KIN5* P66/KIN6*

P67/IRQ7*/KIN7*

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7

P80/PME* P81/GA20

P82/CLKRUN*

P83/LPCPD*

P84/IRQ3*/TXD1 P85/IRQ4*/RXD1 P86/IRQ5*/SCK1

P90/IRQ2* P91/IRQ1*

P92/IRQ0* P93/IRQ12* P94/IRQ13* P95/IRQ14*

P96/EXCL

P97/SDA0/IRQ15*

PE0/EXEXCL

PE1/ETCK

PE2/ETDI PE3/ETDO PE4/ETMS

PE5/ETRST*

PF0/IRQ8*/PWMU0A PF1/IRQ9*/PWMU1A

PF2/IRQ10*/TMOY

PF3/IRQ11*/TMOX PF4/PWMU2A/EXDSR PF5/PWMU3A/EXDTR PF6/PWMU4A/EXCTS PF7/PWMU5A/EXRTS

PG0/EXIRQ8*/TMIX/SDAA

PG1/EXIRQ9*/TMIY/SCLA

PG2/EXIRQ10*/SDAB

PG3/EXIRQ11*/SCLB

PG4/EXIRQ12*/SDAC

PG5/EXIRQ13*/SCLC

PG6/EXIRQ14*/SDAD

PG7/EXIRQ15*/SCLD

PH0/IRQ6*

PH1/EXIRQ7*

PECI

PEVREF

DPMUX_XTAL:YES

R9892

0

1 2

5%

1/20W

MF

201

113

DPMUX_UC_XTAL_R

DBG_XTAL

1

C9890

12PF

5% 50V

2

C0G-CERM 0201

K1 J3 K2 J1 K4 H3

K5 N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 A4 B3

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

NC NC NC

NC NC NC NC NC NC NC NC

DBG_XTAL

TP_DPMUX_UC_P60 TP_DPMUX_UC_P61 TP_DPMUX_UC_P62 GMUX_SLP_S3_BUF_L TP_DPMUX_UC_P64 TP_DPMUX_UC_P65 TP_DPMUX_UC_P66 TP_DPMUX_UC_P67

TP_DPMUX_UC_P80 TP_DPMUX_UC_P81 TP_DPMUX_UC_P82 TP_DPMUX_UC_P83 DPMUX_UC_TX DPMUX_UC_RX TP_LCD_IRQ

GPU_GFX_OVERTEMP DP_X_SNK0_HPD DP_X_SNK1_HPD DP_T_SNK0_HPD DP_T_SNK1_HPD SMC_GFX_PWR_LEVEL_L GFX_SELF_THROTTLE TP_DPMUX_UC_P97

DPMUX_UC_CLK32K DPMUX_UC_TCK DPMUX_UC_TDI DPMUX_UC_TDO DPMUX_UC_TMS DPMUX_UC_TRST_L

EG_LCD_PWR_EN EG_BKLT_EN

PM_ALL_GPU_PGOOD

P5_S0GPU_PGOOD GPUVCORE_PGOOD PVDDCI_PGOOD P1V8GPU_PGOOD P3V3_S0GPU_PGOOD

NC_I2C_DPMUX_A_SDA NC_I2C_DPMUX_A_SCL

DPMUX_LRESET_L TP_DPMUX_UC_PG6 DP_INT_HPD

EDP_IG_PANEL_PWR_EN EDP_IG_BKLT_EN DPMUX_UC_PECI DPMUX_UC_PEVREF

114 101 76 73 70 46 27 20 12

Y9800

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

1 3

2 4

DPMUX_UC_EXTAL_R

113

DBG_XTAL

1

C9891

12PF

5% 50V

2

C0G-CERM 0201

89

110

49 89 98 110

111

OUT

111

IN

IN IN IN

101

IN

101

IN IN IN

89

99

IN

99

IN

91

IN

91

IN

91

IN

91

IN

91

IN

91

IN

49

BI

49

OUT

IN

15

IN

15

IN

89

PM_SLP_S3_L

DPMUX_XTAL:YES

R9893

0

1 2

5%

1/20W

MF

201

PP3V3_S4

PP3V3_S0

89

99 89

29 27

89 20

29 27

89 48

99 89

89 20

114 76

PP3V3_S5

110

C9870

0.1UF

1 2

DPMUX_UC_RESET_L

DPMUX_LRESET_L

113 89

1

10%

6.3V 0201

X7R

2

DPMUX_UC_XTAL

DPMUX_UC_EXTAL

DPMUX_UC_MD1

89

R9800

0

5% 1/16W MF-LF

402

20% 10V

0402

1

2

C9800

0.1UF

X7R-CERM

NOSTUFF

R9802

0

1 2

5% 1/16W MF-LF

402

DPMUX_UC_EXTAL

DPMUX_XTAL:NO

DPMUX_UC_NMI

89

DPMUX_UC_TRST_L

89

DPMUX_UC_MD1

89

DPMUX_UC_MD2

89

DPMUX_UC_CLK32K

89

DPMUX_UC_TCK

89

DPMUX_UC_TDI

89

DPMUX_UC_TDO

89

DPMUX_UC_TMS

89

98 89

89 48

EG_CLKREQ_SEL_L

SMC_GFX_PWR_LEVEL_L

LCD_MUX_EN

89

LCD_MUX_SEL

89

DPMUX_UC_RESET_L

89

6

VCC

U9870

74LVC1G07GF

SOT891

2

A

1

GND

3

113 89

Q9890

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

R9801

0

1 2

5% 1/16W MF-LF

402

89

PP3V3_S0_DPMUX_UC_R

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

C9801

0.1UF

20% 10V

X7R-CERM

0402

R9850

10K

5%

1/20W

MF

201

DPMUX UC PULL-UPS

4

Y

5

NCNC

PP3V3_S3_DPMUX_UC_R

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

20% 10V

0402

1

2

1

2

C9802

0.1UF

X7R-CERM

M12

AVCC

D3

RES*

A3

XTAL

A2

EXTAL

1

2

PP3V3_S0

1

R9870

4.7K

5% 1/20W MF 201

2

GMUX_SLP_S3_BUF_L

NOSTUFF

NCNC

1

R9871

470K

5% 1/20W MF 201

2

DPMUX_UC_MD2_R DPMUX_UC_MD2

3

D

SG

2

20% 10V

0402

1

2

C9803

0.1UF

X7R-CERM

B1M1H10

VCC

U9800

R4F2113NLG

TLP-145V

SYM 3 OF 3

OMIT_TABLE

VSS

L3

D2

R9810 R9811 R9812 R9813 R9814 R9815 R9816 R9817 R9818 R9819 R9842

R9855 R9856

R9840 R9841

C5

F10

MAKE_BASE=TRUE

89 15

99 89

89 15

99 89

1 2

DPMUX_UC_VCL

L11

E1

VCL

J2

VBAT

AVREF

MDCKN

MD1 MD2

NMI

NC

AVSS

VSS

L9

B11

10K

100K

10K

100K

0

1 2

49 89 98 110

DP_T_SNK0_HPD_IG

DP_T_SNK0_HPD_EG

DP_T_SNK1_HPD_IG

DP_T_SNK1_HPD_EG

R9894

0

5%

1/20W

MF

201

1

C9804

0.1UF

20% 10V

2

X7R-CERM 0402

C9805

0.47UF

10%

6.3V

X6S-CERM

0402

C4

D1 H1

E3

E5

NC

PP3V3_S0

49 89 98 110

5% 201

NOSTUFF

GMUX_SLP_S3_BUF_L

DPMUX_UC_MDCKN

DPMUX_UC_MD1 DPMUX_UC_MD2DPMUX_UC_XTAL

DPMUX_UC_NMI

1/20W5% 201MF

5%

5% 201

5% MF 201

5% 2011/20W MF

5% 1/20W MF 201

5% 201

1/20W MF

1/20W

1/20W5% MF 201

1/20W MF5%

1/20W MF

1/20W MF5% 201

1/20W MF

GMUX_SLP_S3_BUF_L

5%

1

2

MF1/20W 201

MF 2011/20W

MF1/20W

R9872 R9873 R9874 R9875

345678

PP3V3_S0

110

89

DP 2:1 ANALOG MUX

113 5

113 5 111

113 5

113 99

89

89 113 89

89

2011/20W5% MF

201

201MF1/20W

89

100K

89

1 2

BOM_COST_GROUP=GRAPHICS

IN IN

IN IN OUT

BI BI

IN IN

BI BI

89

91 89

89 76

89 75

111 89

89 15

99 89

89 15

99 89

89 15

99 89

89 48 46

89 46

1/20W

5% 201

DP_INT_IG_ML_P<0> DP_INT_IG_ML_N<0>

DP_INT_IG_ML_P<1> DP_INT_IG_ML_N<1>

DP_INT_IG_ML_P<2> DP_INT_IG_ML_N<2>

DP_INT_IG_ML_P<3> DP_INT_IG_ML_N<3>

DP_INT_IG_AUX_P DP_INT_IG_AUX_N

NC NC

NC

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

NC NC

NC

LCD_MUX_SEL

LCD_MUX_EN

B4 A4

B5 A5

B6 A6

A8 A9

H9

J9

H8

J8 J2

B8 B9

D8 D9

E8 E9

F8 F9

H6

J6

H5

J5

H3

A1 B7

DIN1_0+ DIN1_0-

DIN1_1+ DIN1_1-

DIN1_2+ DIN1_2-

DIN1_3+ DIN1_3-

DAUX1+ DAUX1-

DDC_CLK1 DDC_DAT1

HPD_1

DIN2_0+ DIN2_0-

DIN2_1+ DIN2_1-

DIN2_2+ DIN2_2-

DIN2_3+ DIN2_3-

DAUX2+ DAUX2-

DDC_CLK2 DDC_DAT2

HPD_2

GPU_SEL XSD*

DPMUX UC PULL-DOWNS

DPMUX_UC_RESET_L

89

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

EG_RAIL5_EN

EDP_PANEL_PWR_EN

EDP_BKLT_EN

BKLT_PWM_MLB2TCON

20 89

DPMUX_UC_NMI

89

DPMUX_UC_MD1

89

DPMUX_UC_MD2

89

DPMUX_UC_PECI

89

DPMUX_UC_PEVREF

89

EG_RESET_L

DP_X_SNK0_HPD_IG

DP_X_SNK0_HPD_EG

DP_X_SNK1_HPD_IG

DP_X_SNK1_HPD_EG

DP_INT_IG_HPD

DP_INT_EG_HPD

GPU_GFX_OVERTEMP

GFX_SELF_THROTTLE

SMC_GFX_OVERTEMP

SMC_GFX_SELF_THROTTLE

LCD_MUX_SEL

89

LCD_MUX_EN

89

2015% 1/20W MF

2015% MF

2015% 1/20W MF

MF1/20W

2 1

1

C9850

0.1UF

20% 10V

2

X7R-CERM

A2

VDD

J4

VDD

0402

U9850

CBTL06142EEE

TFBGA

CRITICAL

DOUT_0+

DOUT_0-

DOUT_1+

DOUT_1-

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

AUX+

HPDIN

DDC_AUX_SEL

GND

H7

100K

100K 100K

G2

10K

R

GND

B3

C8G8H4

R9820 R9821 R9822 R9823 R9824 R9825 R9826 R9827 R9828 R9829 R9830 R9831 R9832 R9833 R9835 R9836 R9837 R9838 R9839 R9845 R9846 R9847 R9848 R9849 R9852

R9853 R9854

PAGE TITLE

GND

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

B2 B1

D2 D1

E2 E1

F2 F1

H2 H1

AUX-

J1

C2

1 2

1 2 1 2

Apple Inc.

DPMUX_HPD_PD

NOSTUFF

5%

5% 2011/20W MF

5% 201MF1/20W

5% 2011/20W MF

NOSTUFF

5% 201MF1/20W

5% 1/20W MF 201

5%

5% 201MF

NOSTUFF

5% 1/20W MF

eDP Mux

EDP_INT_ML_P<0> EDP_INT_ML_N<0>

EDP_INT_ML_P<1> EDP_INT_ML_N<1>

EDP_INT_ML_P<2> EDP_INT_ML_N<2>

EDP_INT_ML_P<3> EDP_INT_ML_N<3>

EDP_AUXCH_C_P EDP_AUXCH_C_N

1/20W MF 2015%

1/20W5% MF

1/20W5% 201MF

1/20W

1/20W5%

1

C9851

0.1UF

20% 10V

2

X7R-CERM 0402

R9862

100K

1 2

1%

201

201MF1/20W

MF1/20W 2015%

201

MF1/20W 2015%

201MF5% 1/20W

MF1/20W 2015%

201MF1/20W5%

201MF5%

201MF1/20W5%

201MF1/20W

2015% 1/20W MF

MF 2015%

MF1/20W5% 201

MF 201

MF1/20W5% 201

201

MF1/20W5%

201

111

OUT

111

OUT

111

OUT

111

OUT

111

OUT

111

OUT

111

OUT

111

BI

111

BI

MF1/20W

SYNC_DATE=08/22/2015SYNC_MASTER=dpmux

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

98 OF 145

SHEET

89 OF 121

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

55 90 92 110

100 91

PP5V_S0_GPUFET

PLACE_NEAR=L9900.1:2.54MM

PPVCORE_S0_GPU

PCC:YES

L9900

120OHM-25%-1.8A-0.06DCR

1 2

0402

PCC:YES

1

C9900

0.1UF

10%

6.3V

2

X6S 0201

PLACE_NEAR=U9900.6:2.54MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

PCC:YES

1

C9901

10UF

20%

6.3V

2

CERM-X6S 0402

PLACE_NEAR=U9900.6:2.54MM

XW9901 should be the lower voltage placement should be at the GPU power pin furthest from the VR

XW9901

SHORT-0201

1 2

XW9900

SHORT-0201

1 2

GPU_VCORE_LOAD

GPU_VCORE_SOURCE

XW9900 should be the higher voltage placement should be immediately after the last of the output bulk caps

PCC:YES

1

C9902

1UF

20%

6.3V

2

X6S-CERM 0201

TP_U9900_5

PP5V_S0_GPU_OPAMP

PCC:YES

1

C9903

0.1UF

10%

6.3V

2

X6S 0201

PLACE_NEAR=U9900.6:2.54MM

PCC:YES

V+

U9900

4

IN-

3

IN+

5

NC

LMP8640

SOT23-6

50X

V-

2 6

VOUT

90 90

R9901

1

LBW_AMP_OUT_R

1 2

PCC:YES

0

5%

1/20W

MF

0201

PCC:YES

1

C9915

0.01UF

10% 10V

2

X5R 201

PCC:YES

R9900

2.2

1 2

5%

1/20W

MF

201

LBW_AMP_OUT

VOLTAGE=5V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

PP5V_VREF_PCCPP5V_S0_GPU_OPAMP

PCC:YES

1

C9904

1UF

20%

6.3V

2

X6S-CERM 0201

1

TP-P6

A

PCC:YES

U9901

SC4437

1 2

TP9900

SOT23-3

IN OUT

GND

3

PLACE_NEAR=U9903.5:2.54MM

PCC:YES

1

C9911

0.1UF

10%

6.3V

2

X6S 0201

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1200

PP3V3_VREF_PCC

PCC:YES

1

C9905

0.1UF

10%

6.3V

2

X6S 0201

PP5V_S0_GPU_OPAMP

BOMOPTION=NOSTUFF

1

C9912

1UF

20%

6.3V

2

X6S-CERM 0201

90

PCC:YES

1

R9912

130

1% 1/16W MF-LF 402

2

PP3V3_S0_GPU

PCC:YES

1

R9913

130

1% 1/16W MF-LF 402

2

D

90 94 97 99 110

C

B

PP3V3_VREF_PCC

1

C9909

0.1UF

10%

6.3V

2

X6S 0201

PCC:YES

1

R9903

0

5% 1/20W MF 201

2

PCC:YES

1

C9906

0.1UF

10%

6.3V

2

X6S 0201

PCC:YES

1

C9907

4.7UF

20%

6.3V

2

CER-X5R 0402

PP3V3_S0_GPU

90 94 97 99 110

R9915

2.0K

5%

1/20W

MF

201

These pullups remain stuffed even when the PCC circuit is unstuffed

1

2

R9916

2.0K

5%

1/20W

MF

201

90

PCC:YES

1

2

1

R9902

10K

5% 1/20W MF 201

2

PCC:YES

8

U9910

PCC_POT_WP

99

I2C_GPU_PCC_SDA PCC_POT_LEVEL_R

99

1 2 3

CAT5140ZI-50-G

MSOP

SCL SDA

GND VCC

4

RHWP*

RL

RW

7 6 5

PCC_POT_RH PCC_POT_RLI2C_GPU_PCC_SCL PCC_POT_REF

PCC:YES

1

R9904

0

5% 1/20W MF 201

2

PCC:YES

R9905

2

1 2

5% 1/16W MF-LF

402

1

2

PCC:YES

C9908

0.01UF

10% 10V X5R-CERM 0201

1

R9906

10K

5% 1/20W MF 201

2

BOMOPTION=NOSTUFF

1

R9907

10K

5% 1/20W MF 201

2

PLACE_NEAR=U9903.3:2.54MM

PLACE_NEAR=U9903.1:2.54MM

PCC:YES

R9908

0

1 2

5%

1/20W

MF

0201

PCC_POT_LEVEL

PCC:YES

1

C9910

10PF

5% 25V

2

C0G 0201

BOMOPTION=NOSTUFF

D9900

DSN2

A K

NSR05F20NXT5G

1

TP-P6

A

3

1

5

VCC+

GND

2

PCC_POT_LEVEL_D

TP9901

PCC:YES

U9903

LMV331

SC70

4

PCC_COMP_OUT

BOMOPTION=NOSTUFF

R9909

1M

1 2

5%

1/20W

MF

201

PCC:YES

R9910

130

1 2

1% 1/16W MF-LF

402

PCC:YES

R9911

130

1 2

1% 1/16W MF-LF

402

PCC:YES

C9913

10PF

1 2

5% 25V C0G

0201

PCC_COMP_OUT_BASE

This pulldown remains stuffed even when the PCC circuit is unstuffed

C

2

PCC:YES

Q9900

1

2N3906

SOT23-HF

3

1

R9914

33.2K

1% 1/20W MF 201

2

1

TP-P6

A

GPU_VCORE_PCC

BOMOPTION=NOSTUFF

1

C9914

220PF

10% 25V

2

X7R-CERM 201

TP9902

OUT

99

B

BOMOPTION=NOSTUFF

A

SYNC_MASTER=X363_SEAN SYNC_DATE=01/27/2016

PAGE TITLE

GPU PCC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

BOM_COST_GROUP=GRAPHICS

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00647

10.0.0 dvt-fab10 99 OF 145 90 OF 121

A

D

345678

2 1

D

C

113 111

IN

110 99

PEG_GPU_R2D_C_P<0>

PEG_GPU_R2D_C_N<0>

PEG_GPU_R2D_C_P<1>

PEG_GPU_R2D_C_N<1>

PEG_GPU_R2D_C_P<2>

PEG_GPU_R2D_C_N<2>

PEG_GPU_R2D_C_P<3>

PEG_GPU_R2D_C_N<3>

PEG_GPU_R2D_C_P<4>

PEG_GPU_R2D_C_N<4>

PEG_GPU_R2D_C_P<5>

PEG_GPU_R2D_C_N<5>

PEG_GPU_R2D_C_P<6>

PEG_GPU_R2D_C_N<6>

PEG_GPU_R2D_C_P<7>

PEG_GPU_R2D_C_N<7>

PP1V8_S0_GPU

CA020

GND_VOID=TRUE

CA021

GND_VOID=TRUE

CA022

GND_VOID=TRUE

CA023

GND_VOID=TRUE

CA024

GND_VOID=TRUE

CA025

GND_VOID=TRUE

CA026

GND_VOID=TRUE

CA027

GND_VOID=TRUE

CA028

GND_VOID=TRUE

CA029

GND_VOID=TRUE

CA039

GND_VOID=TRUE

CA047

GND_VOID=TRUE

CA048

GND_VOID=TRUE

CA059

GND_VOID=TRUE

CA060

GND_VOID=TRUE

CA061

GND_VOID=TRUE

BOMOPTION=BAFFIN

RA000

1K

1 2

1%

1/20W

MF

201

0.22UF

PLACE_NEAR=UA000.AY13:5MM

1

RA001

1K

1% 1/20W MF 201

2

1 2

20% 02016.3V X6S-CERM

1 2

20%

1 2

BOMOPTION=SPEED

111 99

X6S-CERM20% 02016.3V

6.3V

X6S-CERM6.3V

X6S-CERM

6.3V 0201

6.3V X6S-CERM 020120%

X6S-CERM 020120%

6.3V

X6S-CERM6.3V20%

6.3V X6S-CERM 020120%

6.3V 020120%

X6S-CERM

6.3V

X6S-CERM

X6S-CERM6.3V

111

IN

020120% X6S-CERM

020120%

0201

020120%

020120% X6S-CERM6.3V

020120%

020120% X6S-CERM6.3V

IN IN

EG_RESET_L

EG_PEG_CLK100M_P EG_PEG_CLK100M_N

1 2

RA002

113

0

1/20W

MF

0201

GPU_TEST_PG

GPU_RESET_R_L

5%

PEG_GPU_R2D_P<0>

PEG_GPU_R2D_N<0>

113

PEG_GPU_R2D_P<1>

PEG_GPU_R2D_N<1>

113

PEG_GPU_R2D_P<2>

113

PEG_GPU_R2D_N<2>

113

PEG_GPU_R2D_P<3>

113

PEG_GPU_R2D_N<3>

113

PEG_GPU_R2D_P<4>

113

PEG_GPU_R2D_N<4>

113

PEG_GPU_R2D_P<5>

113

PEG_GPU_R2D_N<5>

113

PEG_GPU_R2D_P<6>

113

PEG_GPU_R2D_N<6>

113

PEG_GPU_R2D_P<7>

113

PEG_GPU_R2D_N<7>

AT41 AT40

AR41 AR40

AP41 AP40

AM41 AM40

AL41 AL40

AK41 AK40

AJ41 AJ40

AH41 AH40

AV33 AU33

AY13 AV41

BOMOPTION=OMIT_TABLE

PCIE_RX0+ PCIE_RX0-

PCIE_RX1+ PCIE_RX1-

PCIE_RX2+ PCIE_RX2-

PCIE_RX3+ PCIE_RX3-

PCIE_RX4+ PCIE_RX4-

PCIE_RX5+ PCIE_RX5-

PCIE_RX6+ PCIE_RX6-

PCIE_RX7+ PCIE_RX7-

PCIE_REFCLK+ PCIE_REFCLK-

TEST_PG PERST*

UA000

100-CK4803-ES

BGA

SYM 1 OF 7

PCIE_TX0+

PCIE_TX0-

PCIE_TX1+

PCIE_TX1-

PCIE_TX2+

PCIE_TX2-

PCIE_TX3+

PCIE_TX3-

PCIE_TX4+

PCIE_TX4-

PCIE_TX5+

PCIE_TX5-

PCIE_TX6+

PCIE_TX6-

PCIE_TX7+

PCIE_TX7-

113

AV35 AU35

AU38 AU39

AR37 AR38

AN37 AN38

AL37 AL38

AJ37 AJ38

AG37 AG38

AE37 AE38

PEG_GPU_D2R_C_P<0>

PEG_GPU_D2R_C_N<0>

PEG_GPU_D2R_C_P<1>

PEG_GPU_D2R_C_N<1>

PEG_GPU_D2R_C_P<2>

PEG_GPU_D2R_C_N<2>

PEG_GPU_D2R_C_P<3>

PEG_GPU_D2R_C_N<3>

PEG_GPU_D2R_C_P<4>

PEG_GPU_D2R_C_N<4>

PEG_GPU_D2R_C_P<5>

PEG_GPU_D2R_C_N<5>

PEG_GPU_D2R_C_P<6>

PEG_GPU_D2R_C_N<6>

PEG_GPU_D2R_C_P<7>

PEG_GPU_D2R_C_N<7>

CA077

GND_VOID=TRUE

CA062

GND_VOID=TRUE

CA063

GND_VOID=TRUE

CA064

GND_VOID=TRUE

CA065

GND_VOID=TRUE

CA066

GND_VOID=TRUE

CA067

GND_VOID=TRUE

CA075

GND_VOID=TRUE

CA068

GND_VOID=TRUE

CA069

GND_VOID=TRUE

CA070

GND_VOID=TRUE

CA071

GND_VOID=TRUE

CA076

GND_VOID=TRUE

CA072

GND_VOID=TRUE

CA073

GND_VOID=TRUE

CA074

GND_VOID=TRUE

0.22UF

1 2

6.3V20% X6S-CERM

6.3V X6S-CERM20%

20% 6.3V X6S-CERM

PEG_GPU_D2R_P<0>

0201

PEG_GPU_D2R_N<0>

0201

PEG_GPU_D2R_P<1>

0201

PEG_GPU_D2R_N<1>

0201

PEG_GPU_D2R_P<2>

0201

PEG_GPU_D2R_N<2>

0201

PEG_GPU_D2R_P<3>

0201

PEG_GPU_D2R_N<3>

0201

PEG_GPU_D2R_P<4>

0201

PEG_GPU_D2R_N<4>

0201

PEG_GPU_D2R_P<5>

0201

PEG_GPU_D2R_N<5>

0201

PEG_GPU_D2R_P<6>

0201

PEG_GPU_D2R_N<6>

0201

PEG_GPU_D2R_P<7>

0201

PEG_GPU_D2R_N<7>

0201

OUT

113 111

D

113 111

C

B

110

100 90

0

EG_RAIL1_EN

89

EG_RAIL2_EN

89

EG_RAIL3_EN TP_PVDDCI_GPU_EN

89

EG_RAIL4_EN

89

EG_RAIL5_EN

89

RA010 RA011 RA013 RA012 RA014

1 2

1/20W

1 2

1/20W

1 2

1/20W

1 2

1/20W

1 2

1/20W

5%

0

0201 MF

0201

MF

0201

MF

0201

MF

MAKE_BASE=TRUE

GPUVCORE_EN

MAKE_BASE=TRUE

P1V35FB_EN

MAKE_BASE=TRUE

PP3V3_S0_GPU

PP5V_S0_GPUFET

PCC:YES

RA021

180K

1 2

201

RA015

100K

1 2

201

RA016

100K

1 2

P5_S0GPU_PGOOD

MAKE_BASE=TRUE

201

RA018

100K

1 2

RA017

100K

1 2

201

PCC:NO

RA019

100K

1 2

RA099

100K

1 2

201

P3V3GPU_EN

P1V8GPU_EN

GPUVCORE_EN

P1V35FB_EN

DBGLED

QA000

DMN5L06VK-7

SOT563

VER 3

201

5

G S

100

OUT

100

OUT

100

OUT

97

OUT

94

OUT

DBGLED_GPU_D

3

D

4

DMN5L06VK-7

DBGLED

20K

5%

1/20W

MF

201

1

2

RA022

SPARE

DBGLED

QA000

SOT563

VER 3

2

DBGLED_GPU

DBGLED

A

DA000

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

P5_S0GPU_PGOOD

NC

G S

NC

PP3V3_S0

74 110

PP3V3_S0_LEFT

74 110

6

D

1

RA031

RA033

RA035

Tieing off Ridge GPIOs Both SNK0 and SNK1 shown

B

100K

1 2

201

100K

1 2

201

100K

1 2

201

as always available

TBT_X_HDMI_DDC_DATA TBT_X_HDMI_DDC_CLK TBT_T_HDMI_DDC_DATA TBT_T_HDMI_DDC_CLK TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL

BI

OUT OUT

27

IN

101

IN

15

PCH pins mirror TBT_X hookup

OUT

89

100K

1 2

201

100K

1 2

201

100K

1 2

201

A

100

97

94

P3V3_S0GPU_PGOOD

MAKE_BASE=TRUE

P1V8GPU_PGOOD

IN

MAKE_BASE=TRUE

PVDDCI_PGOOD

MAKE_BASE=TRUE

GPUVCORE_PGOOD

MAKE_BASE=TRUE

GPUFB_PGOOD

MAKE_BASE=TRUE

GPUFB_PGOOD

91

RA020

0

1 2

5%

1/20W

MF

0201

RA023

PCC:YES

330K

1 2

201

MAKE_BASE=TRUE

P3V3_S0GPU_PGOOD

P1V8GPU_PGOOD

PVDDCI_PGOOD

GPUVCORE_PGOOD

GPUFB_PGOOD

PM_ALL_GPU_PGOOD

OUT

89

91

89

97

RA030

RA032

RA034

BOM_COST_GROUP=GRAPHICS

SYNC_MASTER=X363_SEAN SYNC_DATE=01/27/2016

PAGE TITLE

BAFFIN PCI-E

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

100 OF 145

SHEET

91 OF 121

D

A

8 7 5 4 2 1

36

92

PP1V8_S0_GPU_LC_IC

LA100

0.24UH-20%-10A-0.012OHM

1 2

1210

PP1V8_S0_GPU

110

BOMOPTION=OMIT_TABLE

345678

2 1

D

C

B

1

2

PPVCORE_S0_GPU

55 90 92 110

PPVDDCI_S0_GPU

55 92 110

1

CA105

0.1UF

10%

6.3V

2

X6S 0201

1

2

CA104

0.1UF

10%

6.3V X6S 0201

CA106

0.1UF

10%

6.3V X6S 0201

94

OUT

1

CA107

0.1UF

10%

6.3V

2

X6S 0201

1

CA100

0.1UF

10%

6.3V

2

X6S 0201

1

CA10A

4.7UF

20%

6.3V

2

X6S 0402

PP3V3_S0_GPU

PP1V8_S0_GPU_LC_IC

92

VOLTAGE=1.8V

PP3V3_S0_GPU

92 110

94 92

97 92

94 92

P1V5R1V35_GPU_FB_SNS_P

OUT

PVCORE_GPU_FB_SNS_P

OUT

PVDDCI_GPU_FB_SNS_P

OUT

P1V5R1V35_GPU_FB_SNS_N

97 94

PVCORE_GPU_FB_SNS_N

OUT

94

PVDDCI_GPU_FB_SNS_N

OUT

NO_XNET_CONNECTION=1

RA110

10

1 2

1%

1/20W

MF

201

RA112

10

1 2

1%

1/20W

MF

201

1

CA108

0.1UF

10%

6.3V

2

X6S 0201

P1V5R1V35_GPU_FB_SNS_PPP1V5R1V35_S0_GPU_MEM

RA111

10

1 2

1%

1/20W

MF

201

RA113

10

1 2

1%

1/20W

MF

201

1

2

CA109

0.1UF

10%

6.3V X6S 0201

1

CA101

0.1UF

10%

6.3V

2

X6S 0201

1

CA10B

4.7UF

20%

6.3V

2

X6S 0402

NO_XNET_CONNECTION=1

1

CA102

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA10C

10UF

20% 4V

2

X6S-CERM 0402-2

92 110

SM

1 2

SHORT-14L-0.1MM-SM

NO_XNET_CONNECTION=1

PVCORE_GPU_FB_SNS_P

NO_XNET_CONNECTION=1

PVDDCI_GPU_FB_SNS_P

NO_XNET_CONNECTION=1

GPU_FB_SNS_COMMON_NEG

NO_XNET_CONNECTION=1

1

CA110

12PF

5% 25V

2

NP0-C0G 0201

1

CA103

2

1

CA10D

2

XWA100

1 2

92

1

CA111

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1UF

20%

6.3V X6S-CERM 0201

10UF

20% 4V X6S-CERM 0402-2

92 110

92

XWA101

SHORT-14L-0.1MM-SM

1 2

NO_XNET_CONNECTION=1

BOMOPTION=BAFFIN

94 92 110

97 92

94 92

PP1V5R1V35_S0_GPU_IC

1

CA199

3.1PF

+/-0.05PF 25V

2

C0G-CERM 0201

PPVDDCI_S0_GPU

BOMOPTION=SPEED

GPU_FB_SNS_COMMON_NEG

XWA102

92 110

PP1V5R1V35_S0_GPU_IC

92 110

1

RA101

1K

1% 1/20W MF 201

2

GPU_AUX_ZVSS

GPU_PCIE_ZVSS

1

RA102

200

1% 1/20W MF 201

2

1

RA100

150

1% 1/20W MF 201

2

AC10

AG10

K11 K13 K19 K23 K27 K31

L10

N10

W10

AC32 AG32 AG35

AJ34 AJ32

W32

AL34

AM15

AP15

AR15

AM31

BA12

C3 AR13 AV13 AU13

AU41

VMEMIO

VDD_08

VDD_18

VDD_33

AUX_ZVSS

FB_VMEMIO FB_VDDC FB_VDDCI FB_VSS

PCIE_ZVSS

UA000

100-CK4803-ES

BGA

SYM 5 OF 7

VDDC

AA13 AA15 AA21 AA23 AA29 AA31 AC13 AC15 AC21 AC23 AC29 AC31 AE13 AE15 AE21 AE23 AE29 AE31 AG13 AG15 AG21 AG23 AG29 AG31 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25

AJ27 AJ29 AL13 AL15 AL17 AL19 AL21 AL23

AL25 AL27 AL29 N13 N15 N21 N23 N29 N31 R13 R15 R21 R23 R29 R31 U13 U15 U21 U23 U29 U31 W13 W15 W21 W23 W29 W31 AJ31 AL31

PPVCORE_S0_GPU

55 90 92 110

PPVDDCI_S0_GPU

92 110

PPVDDCI_S0_GPU

55 92 110

PPVCORE_S0_GPU

55 90 92 110

1

CA11A

1UF

2

20%

6.3V X6S-CERM 0201

1

CA11B

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA125

220UF

20% 2V

23

ELEC SM-COMBO

1

CA129

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA136

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA146

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA11C

4.7UF

20%

6.3V

2

X6S 0402

1

CA155

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA160

0.1UF

10%

6.3V

2

X6S 0201

1

CA130

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA137

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA147

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA11D

4.7UF

20%

6.3V

2

X6S 0402

1

CA156

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA161

0.1UF

10%

6.3V

2

X6S 0201

1

CA126

220UF

20% 2V

23

ELEC SM-COMBO

1

CA131

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA138

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA148

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA11E

10UF

20% 4V

2

X6S-CERM 0402-2

1

CA157

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA162

0.1UF

10%

6.3V

2

X6S 0201

1

CA132

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA139

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA150

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA11F

10UF

20% 4V

2

X6S-CERM 0402-2

1

CA158

12PF

5% 25V

2

NP0-C0G 0201

1

CA163

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA127

220UF

20% 2V

23

ELEC SM-COMBO

1

CA133

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA140

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA151

12PF

5% 25V

2

NP0-C0G 0201

1

CA159

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA164

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA134

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA141

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA152

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA165

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA128

220UF

20% 2V

23

ELEC SM-COMBO

1

CA135

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA142

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA153

12PF

5% 25V

2

NP0-C0G 0201

1

CA166

12PF

5% 25V

2

NP0-C0G 0201

1

CA177

220UF

20% 2V

23

ELEC SM-COMBO

1

CA143

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA154

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA167

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA176

220UF

20% 2V

23

ELEC SM-COMBO

1

CA144

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA178

220UF

20% 2V

23

ELEC SM-COMBO

1

CA145

2.2UF

20% 4V

2

X6S-CERM 0201

D

C

B

A

1

CA112

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

CA117

2.2UF

20% 4V

2

X6S-CERM 0201

CRITICAL

1

CA122

10UF

20% 10V

2

X6S-CERM 0603

1

CA118

2.2UF

20% 4V

2

X6S-CERM 0201

1

CA113

10UF

20% 4V

2

X6S-CERM 0402-2

1

2

CRITICAL

1

CA123

10UF

20% 10V

2

X6S-CERM 0603

CA119

2.2UF

20% 4V X6S-CERM 0201

1

CA114

1000PF

5% 25V

2

CERM 0402

1

CA120

2.2UF

20% 4V

2

X6S-CERM 0201

CRITICAL

1

CA124

10UF

20% 10V

2

X6S-CERM 0603

1

CA121

12PF

5% 25V

2

NP0-C0G 0201

1

CA115

1000PF

5% 25V

2

CERM 0402

1

CA149

12PF

5% 25V

2

NP0-C0G 0201

1

CA116

1000PF

5% 25V

2

CERM 0402

VDDCI

AA11 AE11 L13 L17 L21 L25 L29 N11 U11

PPVDDCI_S0_GPU

55 92 110

1

CA168

220UF

20% 2V

23

ELEC SM-COMBO

1

CA169

220UF

20% 2V

23

ELEC SM-COMBO

1

CA172

1000PF

5% 25V

2

CERM 0402

1

CA170

220UF

20% 2V

23

ELEC SM-COMBO

CRITICAL

1

CA173

10UF

20% 10V

2

X6S-CERM 0603

CRITICAL

1

CA174

10UF

20% 10V

2

X6S-CERM 0603

BOM_COST_GROUP=GRAPHICS

1

CA171

220UF

20% 2V

23

ELEC SM-COMBO

SYNC_MASTER=X363_SEAN SYNC_DATE=02/01/2016

PAGE TITLE

1

CA175

220UF

20% 2V

23

ELEC SM-COMBO

Baffin CORE/FB POWER

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

101 OF 145

SHEET

92 OF 121

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

113 95

BOMOPTION=OMIT_TABLE

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

FB_A0_DQ<0> FB_A0_A<0>

FB_A0_DQ<1>

FB_A0_DQ<2>

FB_A0_DQ<3>

FB_A0_DQ<4>

FB_A0_DQ<5>

FB_A0_DQ<6>

FB_A0_DQ<7>

FB_A0_DQ<8>

FB_A0_DQ<9>

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<12>

FB_A0_DQ<13>

FB_A0_DQ<14>

FB_A0_DQ<15>

FB_A0_DQ<16>

FB_A0_DQ<17>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<22>

FB_A0_DQ<23>

FB_A0_DQ<24>

FB_A0_DQ<25>

FB_A0_DQ<26>

FB_A0_DQ<27>

FB_A0_DQ<28>

FB_A0_DQ<29>

FB_A0_DQ<30>

FB_A0_DQ<31>

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<4>

FB_A1_DQ<5>

FB_A1_DQ<6>

FB_A1_DQ<7>

FB_A1_DQ<8>

FB_A1_DQ<9>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<12>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<16>

FB_A1_DQ<17>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_DQ<21>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<30>

FB_A1_DQ<31>

FB_A_MVREFD

93 93

L34

DQA0_0 MAA0_0

L37

DQA0_1

L38

DQA0_2

J35

DQA0_3

G37

DQA0_4

E38

DQA0_5

E35

DQA0_6

D35

DQA0_7

H41

DQA0_8

H40

DQA0_9

G41

DQA0_10

G40

DQA0_11

E40

DQA0_12

D41

DQA0_13

D40

DQA0_14

C41

DQA0_15

C40

DQA0_16

B39

DQA0_17

A39

DQA0_18

B38

DQA0_19

B36

DQA0_20

A36

DQA0_21

B35

DQA0_22

A35

DQA0_23

B33

DQA0_24

B32

DQA0_25

A32

DQA0_26

B31

DQA0_27

A30

DQA0_28

B29

DQA0_29

B28

DQA0_30

A28

DQA0_31

B27

DQA1_0

A27

DQA1_1

B26

DQA1_2

A26

DQA1_3

A24

DQA1_4

B23

DQA1_5

A23

DQA1_6

B22

DQA1_7

B20

DQA1_8

A20

DQA1_9

B19

DQA1_10

A19

DQA1_11

B17

DQA1_12

A16

DQA1_13

B16

DQA1_14

A15

DQA1_15

B15

DQA1_16

A14

DQA1_17

B14

DQA1_18

B13

DQA1_19

A11

DQA1_20

B11

DQA1_21

A10

DQA1_22

B10

DQA1_23

B8

DQA1_24

A7

DQA1_25

B7

DQA1_26

A6

DQA1_27

A4

DQA1_28

B4

DQA1_29

A3

DQA1_30

B3

DQA1_31

K17

MVREFDA

UA000

100-CK4803-ES

BGA

SYM 3 OF 7

MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7

MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7

WCKA0_0

WCKA0_0*

WCKA0_1

WCKA0_1*

WCKA1_0

WCKA1_0*

WCKA1_1

WCKA1_1*

EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3

EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3

DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

ADBIA0 ADBIA1

CLKA0

CLKA0*

CLKA1

CLKA1*

RASA0* RASA1*

CASA0* CASA1*

CSA0_0*

CSA1_0*

CKEA0 CKEA1

WEA0* WEA1*

MAA0_8 MAA0_9

FB_A_CALR

1

RA202

120

1% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=UA000.K15:2.54MM

110 93

K15

MEM_CALRA

PP1V5R1V35_S0_GPU_IC

MAA1_8 MAA1_9

DRAM_RSTA

G25 H25 E27 D27 D29 H27 H23 E23

E15 H15 G13 D13 H11 H13 H17 G17

D33 E33

A34 B34

A22 B21

A8 B9

G38 F41 B37 A31

B24 A18 B12 B6

J38 F40 A38 B30

B25 B18 A12 B5

H21 H19

E31 D31

D7 D9

D21 D19

D23 D17

H31

E7

G21 E19

G29 D11

D25 H29

D15 E11

L32

NC

FB_A_RESET_PIN_L

1

RA290

5.1K

1% 1/20W MF 201

2

FB_A0_A<1>

FB_A0_A<2>

FB_A0_A<3>

FB_A0_A<4>

FB_A0_A<5>

FB_A0_A<6>

FB_A0_A<7>

FB_A1_A<0>

FB_A1_A<1>

FB_A1_A<2>

FB_A1_A<3>

FB_A1_A<4>

FB_A1_A<5>

FB_A1_A<6>

FB_A1_A<7>

FB_A0_WCLK_P<0>

FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

FB_A0_EDC<0>

FB_A0_EDC<1>

FB_A0_EDC<2>

FB_A0_EDC<3>

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A0_DBI_L<2>

FB_A0_DBI_L<3>

FB_A1_DBI_L<0>

FB_A1_DBI_L<1>

FB_A1_DBI_L<2>

FB_A1_DBI_L<3>

FB_A0_ABI_L

FB_A1_ABI_L

FB_A0_CLK_P

FB_A0_CLK_N

FB_A1_CLK_P

FB_A1_CLK_N

FB_A0_RAS_L

FB_A1_RAS_L

FB_A0_CAS_L

FB_A1_CAS_L

FB_A0_CS_L

FB_A1_CS_L

FB_A0_CKE_L

FB_A1_CKE_L

FB_A0_WE_L

FB_A1_WE_L

FB_A0_A<8>

FB_A1_A<8>

RA291

10

1 2

1%

1/20W

MF

201

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT OUT

BI BI BI BI

OUT OUT

OUT

OUT OUT

OUT

FB_A_RESET_R_L

1

2

113 95

RA293

49.9

1 2

1%

1/20W

MF

201

CA290

120PF

10% 25V X7R 0201

110 99

FB_A_RESET_L

PP3V3_S0_GPU

95

OUT

NOSTUFF

RA200

10K

1/20W

5% MF

201

12

RA201

10K

1/20W

201

113 96

GPU_TEST_EN

1

5% MF

2

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

FB_B0_DQ<0>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<7>

FB_B0_DQ<8>

FB_B0_DQ<9>

FB_B0_DQ<10>

FB_B0_DQ<11>

FB_B0_DQ<12>

FB_B0_DQ<13>

FB_B0_DQ<14>

FB_B0_DQ<15>

FB_B0_DQ<16>

FB_B0_DQ<17>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<20>

FB_B0_DQ<21>

FB_B0_DQ<22>

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<26>

FB_B0_DQ<27>

FB_B0_DQ<28>

FB_B0_DQ<29>

FB_B0_DQ<30>

FB_B0_DQ<31>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

FB_B_MVREFD

FB_B_CALR

1

RA203

120

1% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=UA000.R10:2.54MM

110 93

BOMOPTION=OMIT_TABLE

C2

DQB0_0

C1

DQB0_1

D2

DQB0_2

D1

DQB0_3

F1

DQB0_4

G2

DQB0_5

G1

DQB0_6

H2

DQB0_7

K2

DQB0_8

K1

DQB0_9

L2

DQB0_10

L1

DQB0_11

N2

DQB0_12

P2

DQB0_13

P1

DQB0_14

R2

DQB0_15

R1

DQB0_16

T2

DQB0_17

T1

DQB0_18

U2

DQB0_19

W1

DQB0_20

W2

DQB0_21

Y1

DQB0_22

Y2

DQB0_23

AB2

DQB0_24

AC1

DQB0_25

AC2

DQB0_26

AD1

DQB0_27

AF1

DQB0_28

AF2

DQB0_29

AG1

DQB0_30

AG2

DQB0_31

AH1

DQB1_0

AH2

DQB1_1

AJ2

DQB1_2

AK1

DQB1_3

AL2

DQB1_4

AM1

DQB1_5

AM2

DQB1_6

AN2

DQB1_7

AR1

DQB1_8

AR2

DQB1_9

AT1

DQB1_10

AT2

DQB1_11

AV2

DQB1_12

AW1

DQB1_13

AW2

DQB1_14

AY3

DQB1_15

BA3

DQB1_16

AY4

DQB1_17

BA4

DQB1_18

AY5

DQB1_19

BA7

DQB1_20

AY7

DQB1_21

AY8

DQB1_22

BA8

DQB1_23

AR4

DQB1_24

AR5

DQB1_25

AU4

DQB1_26

AU7

DQB1_27

AN8

DQB1_28

AV11 AU11 AP11

AE40

U10

DQB1_29 DQB1_30 DQB1_31

MVREFDB

TESTEN

MEM_CALRB

PP1V5R1V35_S0_GPU_IC

UA000

100-CK4803-ES

BGA

SYM 4 OF 7

MAB0_0 MAB0_1 MAB0_2 MAB0_3 MAB0_4 MAB0_5 MAB0_6 MAB0_7

MAB1_0 MAB1_1 MAB1_2 MAB1_3 MAB1_4 MAB1_5 MAB1_6 MAB1_7

WCKB0_0

WCKB0_0*

WCKB0_1

WCKB0_1*

WCKB1_0

WCKB1_0*

WCKB1_1

WCKB1_1*

EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3

EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3

DDBIB0_0 DDBIB0_1 DDBIB0_2 DDBIB0_3

DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3

ADBIB0 ADBIB1

CLKB0

CLKB0*

CLKB1

CLKB1*

RASB0* RASB1*

CASB0* CASB1*

CSB0_0*

CSB1_0*

CKEB0 CKEB1

WEB0* WEB1*

MAB0_8 MAB0_9

MAB1_8 MAB1_9

DRAM_RSTB

R5 R8 N7 N4 L8 N8 U8 U7

AE7 AE8 AG5 AG4 AJ4 AG8 AC8 AC5

H1 J2

AB1 AA2

AP1 AP2

AN4 AN5

F2 M2 V1 AD2

AL1 AU2 BA6 AV7

E2 M1 V2 AE2

AK2 AV1 AY6 AV9

W8 AA8

G4 J4

AL5 AL4

W4 AA4

U4 AC4

G5

AL8

W5 AA7

L4 AJ7

R4 L5

AE4 AJ8R10

AM11

NC

FB_B_RESET_PIN_L

1

RA295

5.1K

1% 1/20W MF 201

2

FB_B0_A<0>

FB_B0_A<1>

FB_B0_A<2>

FB_B0_A<3>

FB_B0_A<4>

FB_B0_A<5>

FB_B0_A<6>

FB_B0_A<7>

FB_B1_A<0>

FB_B1_A<1>

FB_B1_A<2>

FB_B1_A<3>

FB_B1_A<4>

FB_B1_A<5>

FB_B1_A<6>

FB_B1_A<7>

FB_B0_WCLK_P<0>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1>

FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<1>

FB_B0_EDC<0>

FB_B0_EDC<1>

FB_B0_EDC<2>

FB_B0_EDC<3>

FB_B1_EDC<0>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_B1_EDC<3>

FB_B0_DBI_L<0>

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B1_DBI_L<2>

FB_B1_DBI_L<3>

FB_B0_ABI_L

FB_B1_ABI_L

FB_B0_CLK_P

FB_B0_CLK_N

FB_B1_CLK_P

FB_B1_CLK_N

FB_B0_RAS_L

FB_B1_RAS_L

FB_B0_CAS_L

FB_B1_CAS_L

FB_B0_CS_L

FB_B1_CS_L

FB_B0_CKE_L

FB_B1_CKE_L

FB_B0_WE_L

FB_B1_WE_L

FB_B0_A<8>

FB_B1_A<8>

RA296

10

1 2

1%

1/20W

MF

201

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT OUT

BI BI BI BI

OUT OUT

OUT

OUT OUT

OUT

FB_B_RESET_R_L

1

2

113 96

96

113

113 96

96

113 96

RA297

49.9

1 2

1%

1/20W

MF

201

CA295

120PF

10% 25V X7R 0201

FB_B_RESET_L

OUT

D

C

B

96

A

36

1

RA205

40.2

1% 1/20W MF 201

2

NOSTUFF

1

RA207

100

1% 1/20W MF 201

2

NOSTUFF

note: to be unstuffed after

1

2

initial baffin bringup

FB_B_MVREFD

PLACE_NEAR=UA000.U10:2.54MM

CA201

1UF

20%

6.3V X6S-CERM 0201

NOSTUFF

93

BOM_COST_GROUP=GRAPHICS

SYNC_MASTER=J80_SEAN SYNC_DATE=04/29/2015

PAGE TITLE

Baffin FRAME BUFFER I/F

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

1

PLACE_NEAR=UA000.K17:2.54MM

RA204

40.2

1% 1/20W MF 201

2

NOSTUFF

1

RA206

100

1% 1/20W MF 201

2

NOSTUFF

note: to be unstuffed after

1

2

initial baffin bringup

FB_A_MVREFD

PLACE_NEAR=UA000.K17:2.54MM

93

CA200

1UF

20%

6.3V X6S-CERM 0201

NOSTUFF

PLACE_NEAR=UA000.U10:2.54MM

8 7 5 4 2 1

051-00647

10.0.0

dvt-fab10

102 OF 145

93 OF 121

A

D

C

92

P1V5R1V35_GPU_FB_SNS_P

IN

P1V5R1V35_GPU_FB_SNS_N

IN

90 97 99 110

CA303

10PF

5%

50V

C0G

0201

PP3V3_S0_GPU

RA301

1.62K

1 2

1%

1/20W

MF

201

RA302

1.62K

1 2

1%

1/20W

MF

201

NOSTUFF

0.1%

1/20W

MF

0201

1

2

1

RA303

4.64K

2

1

RA330

10K

5% 1/20W MF 201

2

1

RA331

10K

5% 1/20W MF 201

2

NOSTUFF

RA304

4.64K

0.1%

1/20W

MF

0201

BOMOPTION=BAFFIN

FBVDD_ALTVO

BOMOPTION=SPEED

1

CA304

10PF

5%

50V

C0G

2

0201

PP5V_S0

110

PPBUS_HS_GPU

109

345678

2 1

GPUFB_BOOT_RC

MIN_LINE_WIDTH=0.0920

RA310

94

1

RA305

191K

0.1% 1/20W MF 0201

2

1

RA306

95.3K

0.1% 1/20W MF 0201

2

1

CA305

0.01UF

10%

10V

2

X7R-CERM 0201

1

2

GPUFB_SET_R

1

RA307

16.9K

0.1% 1/20W MF 0201

2

1

CA306

22PF

5% 50V

2

C0G 0201

RA308

0

1 2

5%

1/20W

MF

0201

PP5V_S0GPU_P1V35_GPU

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

1

CA310

2.2UF

10%

16V

2

X6S-CERM 0603

91

IN

VOLTAGE=5V

P1V35FB_EN GPUFB_SENSE_DIV GPUFB_SREF GPUFB_VO

GPUFB_OCSET

91

OUT

GPUFB_PGOOD GPUFB_RTN_DIV GPUFB_FSEL GPUFB_SET0

NOSTUFF

RA309

0

5%

1/20W

MF

201

1

GPUFB_SET1

2

FBVDD_ALTVO

94

GPUFB_AGND

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

EN

10

FB

7

SREF

12

VO

11

OCSET

14

PGOOD

4

RTN

13

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

XWA300

PLACE_NEAR=UA300.3:1mm

1

2.2

5% 1/16W MF-LF

402

2

19

UA300

ISL95870AH

UTQFN

CRITICAL

3

SM

1 2

PVCCVCC

PGNDGND

20

2

1

CA318

10UF

20%

10V

2

X6S-CERM 0603

BOOT UGATE PHASE

LGATE

1815 17 16 1

MIN_NECK_WIDTH=0.0850 DIDT=TRUE

0

5% 1/16W MF-LF

402

1

2

RA311

GPUFB_VBST

MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0850 DIDT=TRUE

GPUFB_DRVH_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

GPUFB_LL

MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0850 SWITCH_NODE=TRUE

DIDT=TRUE

GPUFB_DRVL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

1

CA311

0.1UF

10%

16V

2

X7R-CERM 0402

RA312

GPUFB_DRVH

1

12

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE

CRITICAL

1

CA320

33UF

20%

16V

2

TANT-POLY CASE-B3

2 3 7

1

6

4 5

CRITICAL

1

CA321

33UF

20%

16V

2

TANT-POLY CASE-B3

376S0959

POWERPAK-6X3.7

QA300

SIZ710DT

CRITICAL

8

CRITICAL

1

CA322

33UF

20%

16V

2

TANT-POLY CASE-B3

CRITICAL

LA300

0.68UH-20%-14A

1 2

PILE063T-COMBO

CRITICAL

1

CA323

33UF

20%

16V

2

TANT-POLY CASE-B3

1

CA324

2.2UF

20%

25V

2

X6S-CERM 0402

PP1V5R1V35_GPU_REG_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=1.5V

55

OUT

GPUFB_CS_P

GPUFB_CS_N

XWA301

GPUFB_GPU_OCSET_R

RA315

4.53K

RA316

4.53K

1 2

1%

1/20W

MF

201

SM

1%

1/20W

MF

201

1

CA325

2.2UF

20%

25V

2

X6S-CERM 0402

1

CA326

1000PF

5%

25V

2

CERM 0402

GPU FB SUPPLY VOUT = 1.5V / 1.35V

10.7A MAX OUTPUT F = 500 KHZ

D

CRITICAL

RA300

0.002

1%

1/2W

MF

0306

1 2 3 4

CA330

220UF

SM-COMBO

2

CA332

2

1

XWA302

SM

1

220UF

20%

2V

ELEC

SM-COMBO

20%

2V

ELEC

1

2 3

1

2 3

GPUFB_GPU_VO_R

2

CA319

2200PF

12

VID1 VID0 FBVDD

10%

16V

CERM 0201

0 0 1.5V 1 0 1.35V

PP1V5R1V35_S0_GPU_MEM

20%

2V

ELEC

1

2 3

1

2 3

CA334

1000PF

5%

25V

CERM 0402

CA335

220UF

20%

ELEC

SM-COMBO

CA331

220UF

SM-COMBO

CA333

220UF

20%

2V

ELEC

SM-COMBO

2V

1

2

110 116

1

2 3

C

B

92

97 92

PVDDCI_GPU_FB_SNS_P

IN

PVDDCI_GPU_FB_SNS_N

IN

PVCORE_GPU_FB_SNS_N

IN

NO_XNET_CONNECTION=1

97

REG_GPU_VDDCI_VSEN

OUT

REG_GPU_VDDCI_FB

OUT

REG_GPU_VDDCI_COMP

OUT

NO_XNET_CONNECTION=1

RA393

0

1 2

5%

1/20W

MF

0201

NOSTUFF

1

CA380

0.1UF

10% 16V

2

X5R-CERM 0201

NO_XNET_CONNECTION=1

1

RA380

0

5% 1/20W MF 0201

2

1

RA382

499

1% 1/20W MF 201

2

1

CA382

100PF

5% 25V

2

C0G 0201

1

CA381

3300PF

10% 10V

2

X7R-CERM 0201

NOSTUFF

REG_GPU_VDDCI_VSEN_C

1

RA383

30

1% 1/20W MF 201

2

1

RA384

9.09K

1% 1/20W MF 201

2

NOSTUFF

REG_GPU_VDDCI_FB_R

1

CA383

3300PF

10% 10V

2

X7R-CERM 0201

97

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000

IN

REG_BOOT_GPU_VDDCI

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

REG_UGATE_GPU_VDDCI_R

DIDT=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2000

REG_PHASE_GPU_VDDCI

REG_LGATE_GPU_VDDCI

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000

GATE_NODE=TRUE DIDT=TRUE

REG_BOOT_GPU_VDDCI_RC

DIDT=TRUE

RA365

1

1 2

5% 1/16W MF-LF

MIN_LINE_WIDTH=0.6000

402

1

CA365

0.1UF

1

RA366

2.2

5% 1/16W MF-LF 402

2

10%

16V

2

X7R-CERM 0402

109

REG_UGATE_GPU_VDDCI

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.6000

PPBUS_HS_GPU

APN376S1005

CRITICAL

QA350

CSD58873Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

CRITICAL

1

CA350

33UF

20%

16V

2

TANT-POLY CASE-B3

1

6 7

VR_PHASE_GPU_VDDCI

8

1

2

REG_SNUBBER_GPU_VDDCI

NOSTUFF

1

2

NOSTUFF

CA366

0.001UF

10%

50V

X7R-CERM 0402

RA367

2.2

5% 1/10W MF-LF 603

CRITICAL

1

CA356

33UF

20%

16V

2

TANT-POLY CASE-B3

CRITICAL

1

CA357

33UF

20%

16V

2

TANT-POLY CASE-B3

CRITICAL

LA350

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

VRVDDCI_R

CRITICAL

1

CA358

33UF

20%

16V

2

TANT-POLY CASE-B3

CRITICAL

RA368

0.002

1%

1/2W

MF

0306

GPU VDDCI SUPPLY

VOUT = 0.8V-0.9V ?9.7A? MAX OUTPUT F = 450 KHZ

CRITICAL

1

CA351

12PF

5% NP0-C0G

2

0201

25V

Note:

Regulator requires a minimum load to prevent noise in the audio frequencies

12 34

CRITICAL

1

CA352

3.0PF

+/-0.1PF

25V

2

NP0-C0G 0201

1

CA353

1000PF

5%

25V

2

CERM 0402

PPVDDCI_S0_GPU

1

RA369

200

5% 1/16W MF-LF 402

2

PLACE_NEAR=QA350.1:4mm

1

CA354

2.2UF

20%

25V

2

X6S-CERM 0402

EMC

PLACE_NEAR=QA350.1:4mm

1

CA355

2.2UF

20%

25V

2

X6S-CERM 0402

110

EMC

B

A

97

OUT

REG_GPU_VDDCI_FCCM

REG_GPU_VDDCI_IMON

REG_GPU_VDDCI_ISEN1

1

RA386

10K

1% 1/20W MF 201

2

1

RA387

365K

1% 1/20W MF 201

2

1

CA384

1000PF

10% 16V

2

X7R-1 0201

1

RA389

121K

1% 1/20W MF 201

2

1

RA385

41.2K

1% 1/20W MF 201

2

97

OUT

REG_GPU_VDDCI_ISUMP

10% 10V

CERM

201

1

CA391

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

CA390

5600PF

RA390

3.09K

REG_GPU_VDDCI_ISUMN REG_GPU_VDDCI_VSUMN_R

1 2

1%

1/20W

MF

201

RA391

1K

1 2

1%

1/20W

MF

201

REG_GPU_VDDCI_VSUMP

RA392

1.00

1 2

1% 1/20W MF-LF

0201

REG_GPU_VDDCI_VSUMN

BOM_COST_GROUP=GRAPHICS

XWA353

SM

12

VDDCIS0_CS_P

XWA354

SM

12

VDDCIS0_CS_N

PAGE TITLE

Baffin 1V05 GPU / 1V35 FB Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

OUT

55

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

103 OF 145

SHEET

94 OF 121

A

SYNC_DATE=12/08/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V5R1V35_S0_GPU_MEM

95 96 110

95 93

FB_A0_CLK_P

113

PLACE_NEAR=UA400.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

FB_A1_CLK_P

PLACE_NEAR=UA450.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

95 96 110

CK TERMINATION - A0

1 2

CK TERMINATION - A1

1 2

1

CA400

4.7UF

20%

6.3V

2

X6S 0402

1

CA403

4.7UF

20%

6.3V

2

X6S 0402

1

CA406

1UF

20% 4V

2

CERM-X6S 0201

1

CA410

1UF

20% 4V

2

CERM-X6S 0201

1

CA414

1UF

20% 4V

2

CERM-X6S 0201

1

CA418

0.1UF

10%

6.3V

2

X6S 0201

1

CA422

0.1UF

10%

6.3V

2

X6S 0201

RA401

60.4

1%

1/20W

MF

201

RA400

RA451

60.4

1%

1/20W

MF

201

120

1/20W

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1%

MF

2

CA401

4.7UF

20%

6.3V X6S 0402

CA404

4.7UF

20%

6.3V X6S 0402

CA407

1UF

20% 4V CERM-X6S 0201

CA411

1UF

20% 4V CERM-X6S 0201

CA415

1UF

20% 4V CERM-X6S 0201

CA419

0.1UF

10%

6.3V X6S 0201

CA423

0.1UF

10%

6.3V X6S 0201

PLACE_NEAR=UA400.J11:8.4MM

1 2

1

RA404

120

1%

1/20W

MF

201

2

PLACE_NEAR=UA450.J11:8.4MM

1 2

1

CA402

4.7UF

20%

6.3V

2

X6S 0402

1

CA405

4.7UF

20%

6.3V

2

X6S 0402

1

CA408

1UF

20% 4V

2

CERM-X6S 0201

1

CA412

1UF

20% 4V

2

CERM-X6S 0201

1

CA416

0.1UF

10%

6.3V

2

X6S 0201

1

CA420

0.1UF

10%

6.3V

2

X6S 0201

1

CA424

0.1UF

10%

6.3V

2

X6S 0201

FB_A0_VREFC

95

FB_A0_VREFD

95

RA402

60.4

1%

1/20W

MF

201

RA452

60.4

1%

1/20W

MF

201

FB_A0_CLK_N

RA403

120

1/20W

FB_A1_CLK_N

NOSTUFF

1

CA496

12PF

5% 25V

2

NP0-C0G 0201

1

CA497

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA409

1UF

20% 4V

2

CERM-X6S 0201

1

CA413

1UF

20% 4V

2

CERM-X6S 0201

1

CA417

0.1UF

10%

6.3V

2

X6S 0201

1

CA421

0.1UF

10%

6.3V

2

X6S 0201

1

CA425

0.1UF

10%

6.3V

2

X6S 0201

201

UA400

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

B5

B10

D10

G5

G10

H1

H14

K1

K14

L5

L10

P10

T5

T10

A1

A3

A12

A14

C1

C3

C4

C11

C12

C14

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

R12

R14

U1

U3

U12

U14

H11

K10

K11

H10

K4

H5

H4

K5

J3

J12

J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2

C13

R13

R2

D4

D5

P4

P5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS* ZQ

(MF=0)

MF SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

113 93

113 95 93

113 93

IN IN IN IN

IN IN IN IN IN

FB_A0_A<2>

FB_A0_A<5>

FB_A0_A<4>

FB_A0_A<3>

FB_A0_A<7>

FB_A0_A<1>

FB_A0_A<0>

FB_A0_A<6>

FB_A0_CKE_L

H11

K10

K11

H10

K4

H5

H4

K5

J3

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

(1 OF 2)

DBI0* DBI1* DBI2* DBI3*

OMIT_TABLE

113 95 93

113 93

1

95 93

IN IN IN IN IN IN

IN

FB_A0_CLK_P

FB_A0_CLK_N

FB_A0_CS_L

FB_A0_WE_L

FB_A0_CAS_L

FB_A0_RAS_L

FB_A0_ZQ

FB_A0_MF

FB_A0_SEN

FB_A_RESET_L

J12

J11

G12

L12

L3

G3

J13

J1

J10

J2

CK CK* CS* WE* CAS* RAS* ZQ

(MF=0)

MF SEN RESET*

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

C13

R13

J4

C2

R2

ABI*

EDC0 EDC1 EDC2 EDC3

DQ17 DQ18 DQ19 DQ20 DQ21 DQ22

1%

MF

2

113 93

IN

BI BI BI BI

FB_A0_ABI_L

FB_A0_EDC<0>

FB_A0_EDC<1>

FB_A0_EDC<2>

FB_A0_EDC<3>

DQ23 DQ24

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

DQ25 DQ26 DQ27 DQ28 DQ29

113 93 95

113 93

IN IN

FB_A0_WCLK_P<0>

FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<1>

DQ30 DQ31

UA400

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

C5

C10

D11

G1

G4

G11

G14

L1

L4

L11

L14

P11

R5

R10

B1

B3

B12

B14

D1

D3

D12

D14

E5

E10

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12

P14

T1

T3

T12

T14

J14

A10

U10

VDD

VDDQ

VREFC

VREFD

(2 OF 2)

VSS

OMIT_TABLE

VSSQ

B5

B10

D10

G5

G10

H1

H14

K1

K14

L5

L10

P10

T5

T10

A1

A3

A12

A14

C1

C3

C4

C11

C12

C14

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

R12

R14

U1

U3

U12

U14

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_A0_VREFC

95

PLACE_NEAR=UA400.J14:8.4MM

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_A0_VREFD

95

PLACE_NEAR=UA400.A10:13.5MM

NOSTUFF

1

CA432

820PF

10% 25V

2

X7R-CERM 0201

PP1V5R1V35_S0_GPU_MEM

95 96 110

1

CA431

820PF

10% 25V

2

X7R-CERM 0201

PLACE CLOSE TO U9000

PP1V5R1V35_S0_GPU_MEM

95 96 110

PLACE_NEAR=UA400.U10:8.4MM

1

2

PLACE_NEAR=UA400.U10:12.4MM

NOSTUFF

CA433

820PF

10% 25V X7R-CERM 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

NC

1

2

1

2

D2

D13

P13

P2

A4

A2

B4

B2

E4

E2

F4

F2

A11

A13

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

M4

M2

A5

NC

J5

U5

NC

RA430

549

1% 1/20W MF 201

PLACE_NEAR=UA400.J14:8.4MM

RA431

1.33K

1% 1/20W MF 201

RA432

1

NOSTUFF

549

1% 1/20W MF 201

2

PLACE_NEAR=UA400.U10:8.4MM

NOSTUFF

1

RA433

1.33K

1% 1/20W MF 201

2

FB_A0_DBI_L<0>

FB_A0_DBI_L<1>

FB_A0_DBI_L<2>

FB_A0_DBI_L<3>

FB_A0_DQ<0>

FB_A0_DQ<1>

FB_A0_DQ<2>

FB_A0_DQ<3>

FB_A0_DQ<4>

FB_A0_DQ<5>

FB_A0_DQ<6>

FB_A0_DQ<7>

FB_A0_DQ<8>

FB_A0_DQ<9>

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<12>

FB_A0_DQ<13>

FB_A0_DQ<14>

FB_A0_DQ<15>

FB_A0_DQ<16>

FB_A0_DQ<17>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<22>

FB_A0_DQ<23>

FB_A0_DQ<24>

FB_A0_DQ<25>

FB_A0_DQ<26>

FB_A0_DQ<27>

FB_A0_DQ<28>

FB_A0_DQ<29>

FB_A0_DQ<30>

FB_A0_DQ<31>

FB_A0_A<8>

PLACE_NEAR=UA400.J14:8.4MM

1

RA434

931

1% 1/20W MF 201

2

FB_SW_LEG

PLACE_NEAR=UA400.U10:8.4MM

NOSTUFF

1

RA435

931

1% 1/20W MF 201

2

FB_SW_LEG

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

PP1V5R1V35_S0_GPU_MEM

95 96 110

96 95

IN

96 95

113 93

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA450

4.7UF

20%

6.3V X6S 0402

CA453

4.7UF

20%

6.3V X6S 0402

CA456

1UF

20% 4V CERM-X6S 0201

CA460

1UF

20% 4V CERM-X6S 0201

CA464

1UF

20% 4V CERM-X6S 0201

CA468

0.1UF

10%

6.3V X6S 0201

CA472

0.1UF

10%

6.3V X6S 0201

RA450

1/20W

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

120

1%

MF

201

2

CA451

4.7UF

20%

6.3V X6S 0402

CA454

4.7UF

20%

6.3V X6S 0402

CA457

1UF

20% 4V CERM-X6S 0201

CA461

1UF

20% 4V CERM-X6S 0201

CA465

1UF

20% 4V CERM-X6S 0201

CA469

0.1UF

10%

6.3V X6S 0201

CA473

0.1UF

10%

6.3V X6S 0201

RA454

1/20W

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

120

1%

MF

201

2

CA452

4.7UF

20%

6.3V X6S 0402

CA455

4.7UF

20%

6.3V X6S 0402

CA458

1UF

20% 4V CERM-X6S 0201

CA462

1UF

20% 4V CERM-X6S 0201

CA466

0.1UF

10%

6.3V X6S 0201

CA470

0.1UF

10%

6.3V X6S 0201

CA474

0.1UF

10%

6.3V X6S 0201

FB_A1_VREFC

95

FB_A1_VREFD

95

1

2

1

2

1

2

1

2

1

2

RA453

CA459

1UF

20% 4V CERM-X6S 0201

CA463

1UF

20% 4V CERM-X6S 0201

CA467

0.1UF

10%

6.3V X6S 0201

CA471

0.1UF

10%

6.3V X6S 0201

CA475

0.1UF

10%

6.3V X6S 0201

120

1%

1/20W

MF

201

1

2

113 93

113 95 93

113 93

95 93

113 93

C5

C10

D11

G1

G4

G11

G14

L1

L4

L11

L14

P11

R5

R10

B1

B3

B12

B14

D1

D3

D12

D14

E5

E10

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12

P14

T1

T3

T12

T14

J14

VREFC

A10

U10

IN IN IN IN

IN IN IN IN IN

IN IN IN IN IN IN

IN

BI BI BI BI

IN IN

VDD

VDDQ

VREFD

FB_A1_A<2>

FB_A1_A<5>

FB_A1_A<4>

FB_A1_A<3>

FB_A1_A<7>

FB_A1_A<1>

FB_A1_A<0>

FB_A1_A<6>

FB_A1_CKE_L

FB_A1_CLK_P

FB_A1_CLK_N

FB_A1_CS_L

FB_A1_WE_L

FB_A1_CAS_L

FB_A1_RAS_L

FB_A1_ZQ

FB_A1_MF

FB_A1_SEN

FB_A_RESET_L

FB_A1_ABI_L

FB_A1_EDC<0>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A1_EDC<3>

FB_A1_WCLK_P<0>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

UA450

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

VSS

OMIT_TABLE

VSSQ

BOM_COST_GROUP=GRAPHICS

UA450

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

PLACE_NEAR=UA450.U10:12.4MM

DBI0* DBI1* DBI2* DBI3*

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

NC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_A1_VREFC

95

PLACE_NEAR=UA450.J14:8.4MM

D2

D13

P13

P2

A4

A2

B4

B2

E4

E2

F4

F2

A11

A13

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

M4

M2

A5

NC

J5

U5

NC

PP1V5R1V35_S0_GPU_MEM

95 96 110

1

CA481

2

820PF

10% 25V X7R-CERM 0201

FB_A1_DBI_L<0>

FB_A1_DBI_L<1>

FB_A1_DBI_L<2>

FB_A1_DBI_L<3>

FB_A1_DQ<0>

FB_A1_DQ<1>

FB_A1_DQ<2>

FB_A1_DQ<3>

FB_A1_DQ<4>

FB_A1_DQ<5>

FB_A1_DQ<6>

FB_A1_DQ<7>

FB_A1_DQ<8>

FB_A1_DQ<9>

FB_A1_DQ<10>

FB_A1_DQ<11>

FB_A1_DQ<12>

FB_A1_DQ<13>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<16>

FB_A1_DQ<17>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_DQ<21>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<25>

FB_A1_DQ<26>

FB_A1_DQ<27>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<30>

FB_A1_DQ<31>

FB_A1_A<8>

1

RA480

549

1% 1/20W MF 201

2

PLACE_NEAR=UA450.J14:8.4MM

1

RA481

1.33K

1% 1/20W MF 201

2

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

1

RA484

931

2

113 93

PLACE_NEAR=UA450.J14:8.4MM

1% 1/20W MF 201

FB_SW_LEG

113 93

ININ

96 95

PLACE CLOSE TO U9050

PP1V5R1V35_S0_GPU_MEM

95 96 110

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_A1_VREFD

95

PLACE_NEAR=UA450.U10:8.4MM

NOSTUFF

1

CA482

820PF

10% 25V

2

X7R-CERM 0201

SYNC_MASTER=J80_SEAN SYNC_DATE=04/29/2015

NOSTUFF

1

CA483

2

820PF

10% 25V X7R-CERM 0201

RA482

1

NOSTUFF

549

1% 1/20W MF

PLACE_NEAR=UA450.U10:8.4MM

201

2

PLACE_NEAR=UA450.U10:8.4MM

NOSTUFF

1

RA483

1.33K

1% 1/20W MF 201

2

PLACE_NEAR=UA450.U10:8.4MM

NOSTUFF

1

RA485

931

1% 1/20W MF 201

2

FB_SW_LEG

IN

96 95

PAGE TITLE

GDDR5 Frame Buffer A

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

104 OF 145

SHEET

95 OF 121

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

PP1V5R1V35_S0_GPU_MEM

CK TERMINATION - B0

96 93 113 96 93

FB_B0_CLK_P

113

PLACE_NEAR=UA500.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

60.4

1 2

1%

1/20W

MF

201

RA500

120

1%

1/20W

MF

201

1

RA504

120

2

1/20W

201

1%

MF

RA501

1 2

1

2

RA502

60.4

1%

1/20W

PLACE_NEAR=UA500.J11:8.4MM

MF

201

FB_B0_CLK_N

1

RA503

120

1%

1/20W

MF

201

2

CK TERMINATION - B1

FB_B1_CLK_P

PLACE_NEAR=UA550.J12:8.4MM

PP1V5R1V35_S0_GPU_MEM

95 96 110

RA551

60.4

1 2

1%

1/20W

MF

201

RA552

60.4

1 2

1%

1/20W

MF

201

FB_B1_CLK_N

PLACE_NEAR=UA550.J11:8.4MM

113 93 96

NOSTUFF

1

CA500

4.7UF

2

1

CA503

4.7UF

2

1

CA506

1UF

2

1

CA510

1UF

2

1

CA514

1UF

2

1

CA518

0.1UF

2

1

CA522

0.1UF

2

20%

6.3V X6S 0402

20%

6.3V X6S 0402

20% 4V CERM-X6S 0201

10%

6.3V X6S 0201

10%

6.3V X6S 0201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA501

4.7UF

20%

6.3V X6S 0402

CA504

4.7UF

20%

6.3V X6S 0402

CA507

1UF

20% 4V CERM-X6S 0201

CA511

1UF

20% 4V CERM-X6S 0201

CA515

1UF

20% 4V CERM-X6S 0201

CA519

0.1UF

10%

6.3V X6S 0201

CA523

0.1UF

10%

6.3V X6S 0201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA502

4.7UF

20%

6.3V X6S 0402

CA505

4.7UF

20%

6.3V X6S 0402

CA508

1UF

20% 4V CERM-X6S 0201

CA512

1UF

20% 4V CERM-X6S 0201

CA516

0.1UF

10%

6.3V X6S 0201

CA520

0.1UF

10%

6.3V X6S 0201

CA524

0.1UF

10%

6.3V X6S 0201

96

FB_B0_VREFC

FB_B0_VREFD

1

CA498

12PF

5% 25V

2

NP0-C0G 0201

1

CA499

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA509

1UF

20% 4V

2

CERM-X6S 0201

1

CA513

1UF

20% 4V

2

CERM-X6S 0201

1

CA517

0.1UF

10%

6.3V

2

X6S 0201

1

CA521

0.1UF

10%

6.3V

2

X6S 0201

1

CA525

0.1UF

10%

6.3V

2

X6S 0201

113 93

113 96 93

113 93

96 93

113 93

C5

C10

D11

G1

G4

G11

G14

VDD

L1

L4

L11

L14

P11

R5

R10

B1

B3

B12

B14

D1

D3

D12

D14

E5

E10

F1

F3

F12

F14

G2

G13

VDDQ

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12

P14

T1

T3

T12

T14

J14

VREFC

A10

VREFD

U10

UA500

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

B5

B10

D10

G5

G10

H1

H14

K1

K14

L5

L10

P10

T5

T10

A1

A3

A12

A14

C1

C3

C4

C11

C12

C14

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

R12

R14

U1

U3

U12

U14

H11

K10

K11

H10

K4

H5

H4

K5

J3

J12

J11

G12

L12

L3

G3

J13

J1

J10

J2

J4

C2

C13

R13

R2

D4

D5

P4

P5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS* ZQ

(MF=0)

MF SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

IN IN IN IN

IN IN IN IN IN

IN IN IN IN IN IN

IN

FB_B0_A<2>

FB_B0_A<5>

FB_B0_A<4>

FB_B0_A<3>

FB_B0_A<7>

FB_B0_A<1>

FB_B0_A<0>

FB_B0_A<6>

FB_B0_CKE_L

FB_B0_CLK_P

FB_B0_CLK_N

FB_B0_CS_L

FB_B0_WE_L

FB_B0_CAS_L

FB_B0_RAS_L

FB_B0_ZQ

FB_B0_MF

FB_B0_SEN

FB_B_RESET_L

H11

K10

K11

H10

K4

H5

H4

K5

J3

J12

J11

G12

L12

L3

G3

J13

J1

J10

J2

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS* ZQ

(MF=0)

MF SEN RESET*

(1 OF 2)

OMIT_TABLE

DBI0* DBI1* DBI2* DBI3*

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

IN

FB_B0_ABI_L

J4

ABI*

DQ17 DQ18

C13

R13

C2

R2

EDC0 EDC1 EDC2 EDC3

DQ19 DQ20 DQ21 DQ22

BI BI BI BI

FB_B0_EDC<0>

FB_B0_EDC<1>

FB_B0_EDC<2>

FB_B0_EDC<3>

DQ23 DQ24

IN IN

FB_B0_WCLK_P<0>

FB_B0_WCLK_N<0>

D4

WCK01

D5

WCK01*

DQ25 DQ26 DQ27

IN IN

FB_B0_WCLK_P<1>

FB_B0_WCLK_N<1>

P4

WCK23

P5

WCK23*

DQ28 DQ29 DQ30 DQ31

UA500

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

B5

(2 OF 2)

VSS

OMIT_TABLE

VSSQ

B10

D10

G5

G10

H1

H14

K1

K14

L5

L10

P10

T5

T10

A1

A3

A12

A14

C1

C3

C4

C11

C12

C14

E1

E3

E12

E14

F5

F10

H2

H13

K2

K13

M5

M10

N1

N3

N12

N14

R1

R3

R4

R11

R12

R14

U1

U3

U12

U14

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_B0_VREFD

96

PLACE_NEAR=UA500.A10:8.4MM

FB_B0_VREFC

96

1

CA532

820PF

10% 25V

2

X7R-CERM 0201

PP1V5R1V35_S0_GPU_MEM

95 96 110

PLACE_NEAR=UA500.J14:8.4MM

1

CA531

820PF

10% 25V

2

X7R-CERM 0201

PLACE CLOSE TO U9000

PP1V5R1V35_S0_GPU_MEM

95 96 110

PLACE_NEAR=UA500.U10:8.4MM

NOSTUFF

1

2

NOSTUFF

CA533

820PF

10% 25V X7R-CERM 0201

D2

D13

P13

P2

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

M4

M2

A5

J5

NC

U5

1

RA530

549

1% 1/20W MF 201

2

PLACE_NEAR=UA500.J14:8.4MM

1

RA531

1.33K

1% 1/20W MF 201

2

1

RA532

549

1% 1/20W MF 201

2

PLACE_NEAR=UA500.U10:8.4MM

1

RA533

1.33K

1% 1/20W MF 201

2

NC

PLACE_NEAR=UA500.J14:8.4MM

1

2

NOSTUFF

1

2

FB_B0_DBI_L<0>

FB_B0_DBI_L<1>

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B0_DQ<0>

FB_B0_DQ<1>

FB_B0_DQ<2>

FB_B0_DQ<3>

FB_B0_DQ<4>

FB_B0_DQ<5>

FB_B0_DQ<6>

FB_B0_DQ<7>

FB_B0_DQ<8>

FB_B0_DQ<9>

FB_B0_DQ<10>

FB_B0_DQ<11>

FB_B0_DQ<12>

FB_B0_DQ<13>

FB_B0_DQ<14>

FB_B0_DQ<15>

FB_B0_DQ<16>

FB_B0_DQ<17>

FB_B0_DQ<18>

FB_B0_DQ<19>

FB_B0_DQ<20>

FB_B0_DQ<21>

FB_B0_DQ<22>

FB_B0_DQ<23>

FB_B0_DQ<24>

FB_B0_DQ<25>

FB_B0_DQ<26>

FB_B0_DQ<27>

FB_B0_DQ<28>

FB_B0_DQ<29>

FB_B0_DQ<30>

FB_B0_DQ<31>

FB_B0_A<8>

PLACE_NEAR=UA500.J14:8.4MM

RA534

931

1% 1/20W MF 201

FB_SW_LEG

PLACE_NEAR=UA500.U10:8.4MM

NOSTUFF

RA535

931

1% 1/20W MF 201

FB_SW_LEG

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

PP1V5R1V35_S0_GPU_MEM

95 96 110

IN

96 95

113 93

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA550

4.7UF

20%

6.3V X6S 0402

CA553

4.7UF

20%

6.3V X6S 0402

CA556

1UF

20% 4V CERM-X6S 0201

CA560

1UF

20% 4V CERM-X6S 0201

CA564

1UF

20% 4V CERM-X6S 0201

CA568

0.1UF

10%

6.3V X6S 0201

CA572

0.1UF

10%

6.3V X6S 0201

RA550

120

1%

1/20W

MF

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA551

4.7UF

20%

6.3V X6S 0402

CA554

4.7UF

20%

6.3V X6S 0402

CA557

1UF

20% 4V CERM-X6S 0201

CA561

1UF

20% 4V CERM-X6S 0201

CA565

1UF

20% 4V CERM-X6S 0201

CA569

0.1UF

10%

6.3V X6S 0201

CA573

0.1UF

10%

6.3V X6S 0201

RA554

120

1%

1/20W

MF

201

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CA552

4.7UF

20%

6.3V X6S 0402

CA555

4.7UF

20%

6.3V X6S 0402

CA558

1UF

20% 4V CERM-X6S 0201

CA562

1UF

20% 4V CERM-X6S 0201

CA566

0.1UF

10%

6.3V X6S 0201

CA570

0.1UF

10%

6.3V X6S 0201

CA574

0.1UF

10%

6.3V X6S 0201

96

FB_B1_VREFC

FB_B1_VREFD

1

2

1

2

1

2

1

2

1

2

RA553

120

1/20W

CA559

1UF

20% 4V CERM-X6S 0201

CA563

1UF

20% 4V CERM-X6S 0201

CA567

0.1UF

10%

6.3V X6S 0201

CA571

0.1UF

10%

6.3V X6S 0201

CA575

0.1UF

10%

6.3V X6S 0201

201

1

1%

MF

2

113 93

113 96 93

113 93

96 93

113 93

C5

C10

D11

G1

G4

G11

G14

L1

L4

L11

L14

P11

R5

R10

B1

B3

B12

B14

D1

D3

D12

D14

E5

E10

F1

F3

F12

F14

G2

G13

H3

H12

K3

K12

L2

L13

M1

M3

M12

M14

N5

N10

P1

P3

P12

P14

T1

T3

T12

T14

J14

VREFC

A10

U10

IN IN IN IN

IN IN IN IN IN

IN IN IN

93

IN IN IN

IN

BI BI BI BI

IN IN

VDD

VDDQ

VREFD

FB_B1_A<2>

FB_B1_A<5>

FB_B1_A<4>

FB_B1_A<3>

FB_B1_A<7>

FB_B1_A<1>

FB_B1_A<0>

FB_B1_A<6>

FB_B1_CKE_L

FB_B1_CLK_P

FB_B1_CLK_N

FB_B1_CS_L

FB_B1_WE_L

FB_B1_CAS_L

FB_B1_RAS_L

FB_B1_ZQ

FB_B1_MF

FB_B1_SEN

FB_B_RESET_L

FB_B1_ABI_L

FB_B1_EDC<0>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_B1_EDC<3>

FB_B1_WCLK_P<0>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1>

FB_B1_WCLK_N<1>

UA550

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(2 OF 2)

VSS

OMIT_TABLE

VSSQ

BOM_COST_GROUP=GRAPHICS

UA550

32MX32-1.25GHZ-MFL

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT_TABLE

PLACE_NEAR=UA550.A10:8.4MM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

NC

96

D2

D13

P13

P2

A4

A2

B4

B2

E4

E2

F4

F2

A11

A13

B11

B13

E11

E13

F11

F13

U11

U13

T11

T13

N11

N13

M11

M13

U4

U2

T4

T2

N4

N2

M4

M2

A5

J5

U5

FB_B1_VREFC

DBI0* DBI1* DBI2* DBI3*

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

PLACE_NEAR=UA550.J14:8.4MM

NC

PP1V5R1V35_S0_GPU_MEM

95 96 110

1

CA581

820PF

10% 25V

2

X7R-CERM 0201

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B1_DBI_L<2>

FB_B1_DBI_L<3>

FB_B1_DQ<0>

FB_B1_DQ<1>

FB_B1_DQ<2>

FB_B1_DQ<3>

FB_B1_DQ<4>

FB_B1_DQ<5>

FB_B1_DQ<6>

FB_B1_DQ<7>

FB_B1_DQ<8>

FB_B1_DQ<9>

FB_B1_DQ<10>

FB_B1_DQ<11>

FB_B1_DQ<12>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_B1_DQ<15>

FB_B1_DQ<16>

FB_B1_DQ<17>

FB_B1_DQ<18>

FB_B1_DQ<19>

FB_B1_DQ<20>

FB_B1_DQ<21>

FB_B1_DQ<22>

FB_B1_DQ<23>

FB_B1_DQ<24>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<28>

FB_B1_DQ<29>

FB_B1_DQ<30>

FB_B1_DQ<31>

FB_B1_A<8>

1

RA580

549

1% 1/20W MF 201

2

PLACE_NEAR=UA550.J14:8.4MM

1

RA581

1.33K

1% 1/20W MF 201

2

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

PLACE_NEAR=UA550.J14:8.4MM

1

RA584

931

1% 1/20W MF 201

2

FB_SW_LEG

113 93

IN

96 95

PLACE CLOSE TO U9050

PP1V5R1V35_S0_GPU_MEM

95 96 110

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

FB_B1_VREFD

96

NOSTUFF

1

CA582

820PF

10% 25V

2

X7R-CERM 0201

PLACE_NEAR=UA550.U10:8.4MM

SYNC_MASTER=J80_SEAN SYNC_DATE=04/29/2015

NOSTUFF

1

CA583

2

820PF

10% 25V X7R-CERM 0201

NOSTUFF

1

RA582

549

1% 1/20W MF 201

2

1

2

PLACE_NEAR=UA550.U10:8.4MM

NOSTUFF

RA583

1.33K

1% 1/20W MF 201

NOSTUFF

PLACE_NEAR=UA550.U10:8.4MM

1

RA585

931

1% 1/20W MF 201

2

FB_SW_LEG

IN

PAGE TITLE

GDDR5 Frame Buffer B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

105 OF 145

SHEET

96 OF 121

D

C

B

96 95

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

CA661

220PF

10% 16V

2

CER-X7R 0201

NO_XNET_CONNECTION=1

GPUVCORE_COMP_C

1

RA662

10K

1% 1/20W MF 201

2

1

RA663

100

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

NOSTUFF

GPUVCORE_FB_R

1

CA662

220PF

10% 16V

2

CER-X7R 0201

NOSTUFF

NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1

PP1V8_S0_GPU

RA684

NOSTUFF

47K

1 2

5%

1/20W

MF

201

RA686

NOSTUFF

10K

1 2

5%

1/20W

MF

201

RA688

10K

1 2

5%

1/20W

MF

201

PP5V_S0

97 110

RA664

806

1%

1/20W

MF

201

RA685

47K

1 2

5%

1/20W

MF

201

RA687

47K

1 2

5%

1/20W

MF

201

MOSFET,CTRL+SYNC,25V,4.1/1.4MO,QFN32,6x6

NO_XNET_CONNECTION=1

1

CA663

10PF

5% 25V

2

C0G 0201

97

GFXIMVP_ISUMP

1

2

NO_XNET_CONNECTION=1

GFXIMVP_ISUMN

97

97 110

GPUVCORE_PGOOD

GPUVCORE_SVC

NOSTUFF

GPUVCORE_SVD

RA601

0

1 2

5%

1/20W

MF

0201

PPBUS_HS_GPU

97 109

1

CA664

2.0PF

+/-0.1PF

25V

2

NP0-C0G-CERM 0201

NOSTUFF NO_XNET_CONNECTION=1

GPUVCORE_SENSE_P

97

GPUVCORE_SENSE_N

97

10% 10V

CERM

201

1

2

97 91

97

CA666

5600PF

1

CA667

0.1UF

10%

6.3V

2

X6S 0201

NO_XNET_CONNECTION=1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL2376S00174

RA602

1

1 2

5%

1/20W

MF

201

VOLTAGE=5V

QA640,QA650

97 110

VOLTAGE=5V

PP5V_S0_GFXIMVP_VDD

PP1V8_S0_GPU

PP5V_S0_GFXIMVP_VDDP

94

RA603

0

1 2

5%

1/20W

MF

0201

REG_GPU_VDDCI_VSEN

IN

REG_GPU_VDDCI_COMP

IN

REG_GPU_VDDCI_FB

IN

REG_GPU_VDDCI_ISUMP

IN

REG_GPU_VDDCI_ISUMN

IN

REG_GPU_VDDCI_ISEN1

IN

PP5V_S0

97 110

GPUVCORE_NTC

97

99 97

91

OUT

IN

GPUVCORE_VR_HOT_L GPUVCORE_EN PM_ALL_GPU_PGOOD GPUVCORE_SVC

97

GPUVCORE_SVD

97

GPUVCORE_SVT_R

97

VOLTAGE=12.6V

PPVIN_S0_GFXIMVP_VIN

1

CA639

0.22UF

10%

25V

2

X7R 0402

GPUVCORE_COMP

CKPLUS_WAIVE=PDIFPR_BADTERM

GPUVCORE_FB GPUVCORE_FB2

NOSTUFF

1

CA665

1000PF

5%

25V

2

C0G 0201

NO_XNET_CONNECTION=1

GFXIMVP_ISUMP_C

NOSTUFF

1

RA665

10

5% 1/20W MF 201

2

NO_XNET_CONNECTION=1

RA666

634

1/20W

ISL6277A datasheet (December 19,2012)

1% MF

201

12

GFXIMVP_ISUMN_R

CA638

1.0UF

10%

25V

X6S

0402

45 43 44 47

46 48

1

NC

2

12

5 9

10

4 6 8

22 18

19 21

20 16

17

98

CA637

1.0UF

10%

25V

X6S

0402

1

2

VDDIO = 1.14V - 1.95V

VSEN_NB COMP_NB FB_NB ISUMP_NB

ISUMN_NB ISEN1_NB

ISEN2_NB NTC_NB

27-33uA

NTC VR_HOT* ENABLE PWROK SVC

SVD SVT

COMP VSEN RTN FB

FB2 ISUMP

ISUMN

IN

OUT

11Rdwn,1uA-leak

Vil<1V,Vih>1.6V Ileak<35uA

Vthres=750mV, 1uA-leak

{Vih>0.7*VDDIO {Vil<0.3*VDDIO

50R

GPUVCORE_SVC_R

GPUVCORE_SVD_R

GPUVCORE_SVT

1

2

35

VIN

30

VDDP

7

VDDIO

29

UA600

ISL6277AHRZ

QFN

CRITICAL

Vol<0.4V@4mA

|Ioh|<1uA

PAD

THRM

49

VDD

IMON_NB

PWM2_NB

PGOOD_NB

BOOTX UGATEX PHASEX

LGATEX

PWM_Y

BOOT2

UGATE2

PHASE2

LGATE2

BOOT1

UGATE1

PHASE1

LGATE1

PGOOD

FCCM_NB

PPBUS_HS_GPU

109

RA660

IMON

ISEN3 ISEN2 ISEN1

PP3V3_S0_GPU

11 3

REG_GPU_VDDCI_IMON

40

NC

42

PVDDCI_PGOOD

36

REG_BOOT_GPU_VDDCI

37

REG_UGATE_GPU_VDDCI_R

38

REG_PHASE_GPU_VDDCI

39

REG_LGATE_GPU_VDDCI

28 34

33 32 31

24 25 26 27

23 41

13 14 15

MIN_LINE_WIDTH=0.2000

NC

MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUE GATE_NODE=TRUE

DIDT=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUE GATE_NODE=TRUE

GPUVCORE_PGOOD REG_GPU_VDDCI_FCCM PP5V_S0

GFXIMVP_ISEN2 GFXIMVP_ISEN1

RA683

10K

1 2

1%

1/20W

RA690

100K

1 2

1%

MF 1/20W

201

1

CA690

12PF

2

1

CA694

12PF

2

TP_GPUVCORE_IMON

127K

1%

1/20W

201

1

2

1

CA660

1000PF

5%

25V

2MF

C0G 0201

GFXIMVP_BOOT2 GFXIMVP_UGATE2 GFXIMVP_Q1S2 GFXIMVP_LGATE2

GFXIMVP_BOOT1 GFXIMVP_UGATE1 GFXIMVP_Q1S1 GFXIMVP_LGATE1

RA680

22

1 2

5%

1/20W

MF

201

RA682

22

1 2

5%

1/20W

MF

201

GPUVCORE_VR_HOT_L

MF

201

RA681

22

1 2

5%

1/20W

MF

201

90 94 99 110

GPUVCORE_NTC

5% 25V NP0-C0G 0201

OUT

97 110

97

CRITICAL

1

CA604

33UF

20% 16V

2

TANT-POLY CASE-B3

1

20%

25V

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

VOLTAGE=1.1V

55

GFXIMVP_ISNS2_P

1

RA642

10K

1%

1/20W

MF

201

1

10K

1%

1/20W

MF

201

1

2

1

RA653

1

2

1

CA603

33UF

20% 16V

2

TANT-POLY CASE-B3

CA612

X6S-CERM

2.2UF

0402

PPVCORE_S0_GFX_PH2

1

CA691

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA695

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA692

12PF

5% 25V

2

NP0-C0G 0201

1

CA696

12PF

5% 25V

2

NP0-C0G 0201

PPBUS_HS_GPU

97 109

1

CA693

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA697

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CA600

33UF

20% 16V

2

TANT-POLY CASE-B3

CA609

2.2UF

20%

X6S-CERM

0402

1820212223

1

2

25V

1

2

CA610

OMIT_TABLE

VIN

CA601

33UF

20% 16V TANT-POLY CASE-B3

2.2UF

20%

25V

X6S-CERM

0402

1

CA602

33UF

20% 16V

2

TANT-POLY CASE-B3

1

2

CA611

2.2UF

20%

25V

X6S-CERM

0402

CRITICAL

LA640

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

QA640

IRF3575

PQFN

CRITICAL

25

GATEH

6 7

26

5

32

SW

Q1S GATEL

PGND

4

162831

GFXIMVP_PHASE2

SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

OUT

OUT OUT OUT OUT

Line Width & DIDT on all DIDT nets

1

94

IN

91

94

CA640

0.22UF

10%

16V

2

CERM 402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

GFXIMVP_BOOT2_R

1

RA640

0

5% 1/16W MF-LF 402

2

PPBUS_HS_GPU

97 91

94

IN

1

RA650

0

5% 1/16W MF-LF 402

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

GFXIMVP_BOOT1_R

1

CA650

0.22UF

10%

16V

2

CERM 402

25

6 7

26

5

32

GATEH SW

Q1S GATEL

1820212223

QA650

IRF3575

PQFN

CRITICAL

PGND

4

162831

376S1136

VIN

NC NC NC NC NC NC NC

1

NC

2

NC

3

NC

24

NC NC NC NC

27 29 30

NC

376S1136

OMIT_TABLE

1 2 3 24 27 29 30

NC

97 109

CRITICAL

LA650

0.2UH-20%-28A-0.0011OHM

1 2

PILA63T-SM

NO_XNET_CONNECTION

GPUVCORE_SVC

GPUVCORE_SVD

GPUVCORE_SVT_R

97

GFXIMVP_PHASE1

SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE

NO_XNET_CONNECTION

GFXIMVP_ISEN2

97

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

PPVCORE_S0_GFX_PH1

VOLTAGE=1.1V

55

GFXIMVP_ISNS1_P

RA652

GFXIMVP_ISEN1

97

1

CA605

33UF

2

1

RA643

2

RA651

0.00075

1 2 3 4

1

1K

1%

1/20W

MF

201

2

CA651

20% 16V TANT-POLY CASE-B3

CRITICAL

RA641

0.00075

1 2 3 4

1

1K

1%

1/20W

MF

201

1

2

CA641

0.22UF

1

1 2

20%

6.3V

X6S-CERM

0201

RA645

1

10K

1 2

1%

1/20W

MF

201

CRITICAL

1% 1W MF

0612-1

GFXIMVP_ISNS1_N

1

RA654

2

1.00

1

CA606

33UF

20% 16V

2

TANT-POLY CASE-B3

1% 1W MF

0612-1

GFXIMVP_ISNS2_N

1

RA644

1.00

1% 1/20W MF-LF 0201

2

GFXIMVP_ISUMN GFXIMVP_ISUMP

GFXIMVP_ISNS1_N

1

1% 1/20W MF-LF 0201

GFXIMVP_ISUMN GFXIMVP_ISUMP

1

CA607

12PF

5% NP0-C0G

2

0201

25V

GPU CORE SUPPLY

VOUT = 0.75-1.00V

64.2A MAX OUTPUT F = 450 KHZ

55 97

97

55 97

97 55

97

CRITICAL

1

CA608

3.0PF

+/-0.1PF

25V

2

NP0-C0G 0201

PPVCORE_S0_GPU

D

110

C

B

0.22UF

97

1 2

1

RA667

0

5% MF

0201

1 2

5%

1/20W

MF

0201

CA668

2.0PF

+/-0.1PF

NP0-C0G-CERM

NO_XNET_CONNECTION=1

0201

NOSTUFF

25V

1

2

1

2

92

PVCORE_GPU_FB_SNS_P

IN

RA668

94 92

99 97

PVCORE_GPU_FB_SNS_N

IN

1 2

1/20W

GPUVCORE_SENSE_P

GPUVCORE_SENSE_N

CA669

0.01UF

10%

25V

X5R-CERM 0201

NO_XNET_CONNECTION=1

97

BOM_COST_GROUP=GRAPHICS

20%

6.3V

X6S-CERM

0201

SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/08/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

RA655

10K

1/20W

MF

201

1 2

1%

GFX IMVP VCore Regulator [106]

1

Apple Inc.

R

GFXIMVP_ISNS2_N

97 55

DRAWING NUMBER SIZE

051-00647

REVISION

D

10.0.0

BRANCH

dvt-fab10

PAGE

106 OF 145

SHEET

97 OF 121

A

8 7 5 4 2 1

36

345678

2 1

D

former site of the SPEED MLPS STRAPS

PCIe Gen3 enabled, Half-Swing, TX De-emp enabled VBIOS disabled, Boot from EFI VGA enabled All power audio-capable display output 256MB FB Aperture Size PS_0: 01001 82nF 8.45k 2k PS_1: 10001 10nF 8.45k 2k PS_2: 10000 10nF NC 4.75k PS_3: 00000 680nF NC 4.75k

99

99 98

99

PP3V3_S0_GPU

110

PP1V8_S0_GPU

110

GPU_ROM_CONFIG<2> GPU_ROM_CONFIG<1> GPU_ROM_CONFIG<0>

GPU_AUD_PORT_CONN<2> GPU_AUD_PORT_CONN<1> GPU_AUD_PORT_CONN<0>

GPU_BIF_GEN3_EN_A GPU_TX_HALF_SWING GPU_TX_DEEMPH_EN GPU_ROM_SO GPU_ROM_CS_L_R

GPU_VGA_DIS GPU_AUD<1> GPU_AUD<0>

(strap BIF_CLK_PM_EN) (strap BIOS_ROM_EN)

GPU_BRD_CFG<2>

GPU_BRD_CFG<1>

GPU_BRD_CFG<0>

GPU_SMBUS_ADDR<1>

GPU_SMBUS_ADDR<0>

NOSTUFF

RA770

NOSTUFF

RA77A

5.1K

1%

1/20W

MF

201

0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1

5.1K

1%

1/20W

MF

201

1

2

1

2

NOSTUFF

RA771

5.1K

RA77B

5.1K

1%

1/20W

MF

201

NOTICE THE ANNOYING MIX OF 3.3V AND 1.8V PULL-UPS

1%

1/20W

MF

201

1

2

1

2

NOSTUFF

RA772

NOSTUFF

RA77C

5.1K

1%

1/20W

MF

201

5.1K

1%

1/20W

MF

201

1

2

1

2

NOSTUFF

RA773

5.1K

RA77D

5.1K

1%

1/20W

MF

201

1%

1/20W

MF

201

1

2

1

2

RA774

5.1K

RA77F

5.1K

1%

1/20W

MF

201

1%

1/20W

MF

201

1

2

1

2

NOSTUFF

RA775

5.1K

NOSTUFF

RA780

5.1K

1%

1/20W

MF

201

1/20W

1

2

1% MF

201

1

2

NOSTUFF

RA776

5.1K

RA781

5.1K

1%

1/20W

MF

201

1%

1/20W

MF

201

1

2

1

2

NOSTUFF

RA782

5.1K

1/20W

201

RA777

5.1K

1%

1/20W

MF

201

1

1% MF

2

1

2

NOSTUFF

RA783

5.1K

1/20W

201

RA778

5.1K

1%

1/20W

MF

201

1

1% MF

2

1

2

NOSTUFF

RA79A

5.1K

RA784

5.1K

1%

1/20W

MF

201

1%

1/20W

MF

201

1

2

BAFFIN STRAPS

PCIe Gen3 enabled, FULL-Swing, TX De-emp enabled

1

2

NOSTUFF

RA79B

5.1K

1%

1/20W

MF

201

1

2

VBIOS disabled, Boot from EFI VGA enabled, CLKREQ_L enabled All power audio-capable display output Audio for DP or HDMI dongle 256MB FB Aperture Size SMBUS address 41

D

C

B

99

GPUVCORE_SVT

Former site of the GPU SVI2 VOLTAGE TRANSLATION

SPEED ONLY

RA750

RA751

1 2

1/20W

1 2

1/20W

22

5%

22

5%

MF

201

GPU_GPIO_SVCGPU_GPIO_SVC_R

RA757

GPU_GPIO_SVDGPU_GPIO_SVD_R

RA758

0

1 2

5%

1/20W

MF

0201

0

1 2

5%

1/20W

MF

0201

GPUVCORE_SVC_R

GPUVCORE_SVD_R

GPUVCORE_SVT

MAKE_BASE=TRUE

OUT

97

NOSTUFF

RA78E

5.1K

1%

1/20W

MF

201

1

1% MF

2

RA741

1/20W

GPU_XTAL_PU_OR_CAP

113

10K

5% MF

201

RA798

5.1K

1/20W

1

2

1

2

1% MF

201

1

2

113

GPUCLK:XTAL

1

2

RA799

5.1K

1%

1/20W

MF

201

GPU_XTAL_XTAL_OR_CLK

CA740

18PF

5% 25V C0G 0201

2 4

1

2

3

1

GPUCLK:XTAL

1

CA741

2

GPU_ROM_SI_R GPU_RESERVED

OMIT_TABLE

YA740

27MHZ-30PPM-18PF-60OHM

2.50X2.00MM-SM

18PF

5% 25V C0G 0201

(strap reserved)

OMIT_TABLE

99 98

99

RA743

0

5%

1/20W

MF

0201

GPUCLK:XTAL

12

GPU_XTAL_OR_CLK_IN

GPUCLK:XTAL

1

RA745

1M

5% 1/20W MF 201

2

RA744

0

5%

1/20W

MF

0201

12

GPU_XTAL_OUT

GPU XTAL 27 MHZ

OR GPU OSC 100 MHZ

C

113 99

B

113 99

PP3V3_S0

49 89 110

10%

6.3V 0201

1

2

CA700

0.1UF

CERM-X5R

EG_CLKREQ_SEL_L

89

BOMOPTION=SPEED

EG_CLKREQ_OUT_L

1%

1/20W

MF

201

RA78F

1

2

5.1K

1%

1/20W

MF

201

1

2

RA785

5.1K

GPU CLKREQ GATING

1

RA700

47K

5% 1/20W MF 201

2

RA703

0

5%

1/20W

MF

0201

1

2

BOMOPTION=BAFFIN

SEL

6

5

VCC

4 3

A

NOSTUFF

RA786

5.1K

1%

1/20W

MF

201

1

2

RA790

5.1K

1%

1/20W

MF

201

CRITICAL

UA702

PI5A3157BC6E

SC70

1

GND

0

VER 1

B1

B0

1

2

RA787

5.1K

1/20W

1

2

1

1% MF

201

2

RA791

5.1K

1%

1/20W

MF

201

1

RA701

47K

5% 1/20W MF 201

2

EG_CLKREQ_PU

1

2

NOSTUFF

RA788

5.1K

1%

1/20W

MF

201

RA792

5.1K

1

2

1/20W

201

NOSTUFF

1

1% MF

2

PP3V3_S0_GPU

1

RA702

47K

5% 1/20W MF 201

2

GPU_CLKREQ_L

RA789

5.1K

1%

1/20W

MF

201

NOSTUFF

RA793

5.1K

1/20W

1

2

1% MF

201

1

2

RA78A

5.1K

1/20W

201

110

99 111

1

1% MF

2

RA794

5.1K

1%

1/20W

MF

201

NOSTUFF

RA78B

5.1K

1%

1/20W

MF

201

1

RA795

5.1K

1/20W

2

PP1V8_S0_GPU

110

1

2

201

RA78C

5.1K

1%

1/20W

MF

201

1

1% MF

2

OMIT_TABLE

GPU_XTAL_PWR_OR_GND

OMIT_TABLE

RA796

5.1K

1/20W

1

RA78D

5.1K

2

1

1% MF

201

2

RA740

0

5%

1/20W

MF

0201

RA742

0

5%

1/20W

MF

0201

1%

1/20W

MF

201

RA797

5.1K

1

2

1

2

1

2

1/20W

201

GPUCLK:OSC

RA704

0

NOSTUFF

12

5% 1/20WMF

0201

97

IN

SEL = 0 : PCH CLKREQ CONNECTED TO GPU SEL = 1 : PCH CLKREQ TIED TO PULLUP

A

PP3V3_S0_GPU

110

GPU_ROM_SI_R

98 99

GPU_ROM_SCLK_R

99

GPU_ROM_CS_L_R

98 99

GPU_ROM:YES

RA723

33

1 2

5%

1/20W

MF

201

RA724

33

1 2

5%201 1/20W MF

RA725

33

1 2

5%

1/20W

MF

201

GPU_ROM_SI

GPU_ROM_SCLK

GPU_ROM_CS_L

GPU_ROM:YES

RA721

1

0

5%

1/20W

MF

0201

2

GPU_ROM_WP_L

NO STUFF

1

2

BOMOPTION=NOSTUFF

RA720

5.1K

1%

1/20W

MF

201

RA722

0

5% 1/20W MF 0201

GPU ROM

1

2

5

6 1 3 7

D

UA701

M25P10A

C

UFDFPN8

OMIT_TABLE

S* W* HOLD*

VSS

4

8

VCC

THRM

PAD

9

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

GPU JTAG

PP3V3_S0_GPU

110

GPU_ROM:YES

1

CA721

0.1UF

10%

6.3V

2

X6S 0201

GPU_ROM:YES

RA726

2

Q

GPU_ROM_SO_R

33

1 2

5%

1/20W

MF 201

GPU_ROM_SO

98 99

NOSTUFF

RA731

10K

1/16W MF-LF

NOSTUFF

402

RA730

10K

1/16W MF-LF

402

5%

1

2

1

2

NOSTUFF

RA732

10K

1/16W MF-LF

402

5%

1

2

NOSTUFF

RA733

10K

1/16W MF-LF

402

5%

1

2

NOSTUFF

RA734

10K

1/16W MF-LF

402

5%

1

2

GPU_JTAG_TDI

GPU_JTAG_TRST_L

GPU_JTAG_TMS GPU_JTAG_TDO GPU_JTAG_TCK

99

197S0499 YA740 CRITICAL1 GPUCLK:XTAL

117S0201 CRITICAL1 GPUCLK:XTALRA743 117S0080 CRITICAL1 GPUCLK:OSCRA743

132S0444 RA742 CRITICAL1 GPUCLK:OSC

BOM_COST_GROUP=GRAPHICS

XTAL,27.000MHZ,30PPM,12PF,2.5x2.0MM

OSC,MEMS,100MHZ,+/-20PPM,1.8V,2520

RES,0 OHM,5%,0201

RES,33 OHM,5%,0201

FERRITE BEAD, 470OHM,0.1A,1.5MOHM DCR,060

RES,0 OHM,5%,0201

CAP,CER,X5R,0.1UF,10%,6.3V,0201

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

GPUCLK:OSCCRITICALYA7401197S00056

RA740155S0387 1 CRITICAL GPUCLK:OSC RA742 GPUCLK:XTAL1 CRITICAL117S0201

SYNC_DATE=01/28/2016SYNC_MASTER=X363_SEAN

Baffin GPIOs,CLK & Straps

DRAWING NUMBER SIZE

Apple Inc.

R

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

107 OF 145

SHEET

98 OF 121

D

A

8 7 5 4 2 1

36

D

C

B

49

110 99 93

1

RA800

10K

5% 1/20W MF 201

2

BOMOPTION=BAFFIN

IN

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

IO

PP3V3_S0_GPU

GPU_GFX_OVERTEMP

89

PPVDDCI_S0_GPU

1

RA801

1.69K

1% 1/20W MF 201

2

BOMOPTION=SPEED

BOMOPTION=BAFFIN

1

RA802

10K

5% 1/20W MF 201

2

1

RA803

150

1% 1/20W MF 201

2

BOMOPTION=SPEED

DMN5L06VK-7

74LVC1G08FW5

DFN1010

4

PP1V8_S0_GPU

GPU_BP_0

PP1V8_S0_GPU

GPU_BP_1

110

QA800

SOT563

VER 5

D S

6

QA800

DMN5L06VK-7

Y

UA801

SOT563

VER 5

D S

3

6

NC

3

5

2

B

1

A

NC

110 99 91

110

99

110 99 91

99

PP3V3_S0_GPU

2

G

1

5

G

4

GPU_GFX_PWR_LEVEL_L

89

EG_RESET_L

PP3V3_S0_GPU

90 94 97 110

91 111

89

OUT

1

RA805

4.7K

5% 1/20W MF 201

2

RA812

0

0201 MF

RA813

EG_BKLT_EN

TPA802 TPA803 TPA804 TPA805 TPA807 TPA808 TPA809 TPA810

1

RA806

4.7K

5% 1/20W MF 201

2

12

5%

1/20W

0

5%

MF0201

1

RA807

10K

5% 1/20W MF 201

2

1

RA821

10K

5% 1/20W MF 201

2

1

RA820

10K

5% 1/20W MF 201

2

12

1/20W

BOMOPTION=SPEED

99

GPU_PLLCHARZ_H GPU_PLLCHARZ_L

TP_EG_BKLT_PWM

99

98

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

TP-P6

A

BOMOPTION=SPEED

98

I2C_GPU_PCC_SCL

90

I2C_GPU_PCC_SDA

90

98

OUT

98

GPU_SMB_CLK GPU_SMB_DAT GPU_GFX_PWR_LEVEL_R_L

97

IN

98

89

IN

98

OUT

89

IN

98

99

98

90

IN

98

GPU_BP_0 GPU_BP_1

GPU_AUD_PORT_CONN<0> GPU_AUD_PORT_CONN<1> GPU_AUD_PORT_CONN<2> GPU_BRD_CFG<0> GPU_BRD_CFG<1> GPU_BRD_CFG<2> GPU_SMBUS_ADDR<0> GPU_SMBUS_ADDR<1>

1 1 1 1 1 1 1 1

GPU_DBG_8 GPU_DBG_9 GPU_DBG_10 GPU_DBG_11 GPU_MPLS_PS_0 GPU_MPLS_PS_1 GPU_MPLS_PS_2 GPU_MPLS_PS_3

1 2

GPU_GPIO_SVC_R GPU_GPIO_SVD_R GPUVCORE_SVT

GPU_TX_HALF_SWING GFX_VDDCI_ALTV_ZERO GPU_BIF_GEN3_EN_A

GPUVCORE_VR_HOT_L

GPU_ROM_SO GPU_ROM_SI_R GPU_ROM_SCLK_R GPU_ROM_CONFIG<0> GPU_ROM_CONFIG<1> GPU_ROM_CONFIG<2>

DP_X_SNK0_HPD_EG

GPU_RESERVED GFX_VDDCI_ALTV_ONE GFX_SELF_THROTTLE_RGFX_SELF_THROTTLE

DP_X_SNK1_HPD_EG

GPU_GFX_OVERTEMP_R GPU_TX_DEEMPH_EN GPU_VRAM_STRAP GPU_ROM_CS_L_R GPU_FDO GPU_VGA_DIS GPU_VCORE_PCC

GPU_JTAG_TRST_L GPU_JTAG_TDI GPU_JTAG_TCK GPU_JTAG_TMS GPU_JTAG_TDO

150

RA804

(strap BIFCLK_PM_EN)

(MLPS enabled for SPEED)

GPU_ANALOGIO

MF1% 1/20W 201

(strap reserved)

(strap BIOS_ROM_EN)

NC

NC NC

AU15 AV15

AC37 AC38

AA38 AA37

L40

L41 M40 M41

N40 N41

P40

P41 R40 R41

T40

T41 U40 U41

V40

V41

AU40

AY38

AU17 AV17 AR17

AG34

AE34

AC35 AC34

W40 AA40 AA35

AW40 AW41

AA34

U35

AP25

AM25 AM27

W41

Y40

Y41 AU21 AA41

U34

R37 AV25

R38 AB40 AB41 AP27

U38

W37 W38

AF40 AD40 AE41 AD41

AF41

BOMOPTION=OMIT_TABLE

PLLCHARZ_H PLLCHARZ_L

100-CK4803-ES

BL_ENABLE BL_PWM_DIM

BP_0 BP_1

DBGDATA_0 DBGDATA_1 DBGDATA_2 DBGDATA_3 DBGDATA_4 DBGDATA_5 DBGDATA_6 DBGDATA_7 DBGDATA_8 DBGDATA_9 DBGDATA_10 DBGDATA_11 DBGDATA_12 DBGDATA_13 DBGDATA_14 DBGDATA_15

WAKE*

ANALOGIO

GPIO_SVC GPIO_SVD GPIO_SVT

SWAPLOCKA SWAPLOCKB

SCL SDA

GPIO_0 GPIO_1 GPIO_2 SMBCLK SMBDAT GPIO_5_REG_HOT_AC_BATT GPIO_6_TACH

GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15 GPIO_16_8P_DETECT GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20 GPIO_21 GPIO_22_ROMCS* GPIO_28_FDO GPIO_29 GPIO_30

JTAG_TRST* JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

UA000

BGA

SYM 2 OF 7

librarian reordered pins to follow tx

librarian reordered

pins to follow tx

TXCAP_DPA3+

TXCAM_DPA3-

TX3P_DPA2+

TX3M_DPA2-

TX4P_DPA1+

TX4M_DPA1-

TX5P_DPA0+

TX5M_DPA0-

TXCBP_DPB3+

TXCBM_DPB3-

TX0P_DPB2+

TX0M_DPB2-

TX1P_DPB1+

TX1M_DPB1-

TX2P_DPB0+

TX2M_DPB0-

TXCCP_DPC3+

TXCCM_DPC3-

TX3P_DPC2+

TX3M_DPC2-

TX4P_DPC1+

TX4M_DPC1-

TX5P_DPC0+

TX5M_DPC0-

TXCDP_DPD3+

TXCDM_DPD3-

TX2P_DPD0+

TX2M_DPD0-

TX1P_DPD1+

TX1M_DPD1-

TX0P_DPD2+

TX0M_DPD2-

TXCEP_DPE3+

TXCEM_DPE3-

TX0P_DPE2+

TX0M_DPE2-

TX1P_DPE1+

TX1M_DPE1-

TX2P_DPE0+

TX2M_DPE0-

HSYNC VSYNC

DIGON

TEMPIN0

TEMPINRETURN

TEST6

TEST_PG_BACO

GENLK_CLK

GENLK_VSYNC

CLKREQ*

AY33 BA33

AY34 BA34

AY35 BA35

AY36 BA36

AY28 BA28

AY30 BA30

AY31 BA31

AY32 BA32

AY24 BA24

AY25 BA25

AY26 BA26

AY27 BA27

AY19 BA19

AY22 BA22

AY21 BA21

AY20 BA20

AY14 BA14

AY15 BA15

AY16 BA16

AY18 BA18

W34 W35

AC40

J8

NC

J7

NC

B2

GPU_DIECRACKMON

BA13

AR29

NC

AP29

NC

AV40

DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>

DP_X_SNK0_ML_C_P<3> DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_ML_C_P<2> DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<1> DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<0> DP_X_SNK0_ML_C_N<0>

DP_X_SNK1_ML_C_P<3> DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_ML_C_P<2> DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<1> DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<0> DP_X_SNK1_ML_C_N<0>

DP_T_SNK0_ML_C_P<3> DP_T_SNK0_ML_C_N<3>

DP_T_SNK0_ML_C_P<0> DP_T_SNK0_ML_C_N<0>

DP_T_SNK0_ML_C_P<1> DP_T_SNK0_ML_C_N<1>

DP_T_SNK0_ML_C_P<2> DP_T_SNK0_ML_C_N<2>

DP_T_SNK1_ML_C_P<3> DP_T_SNK1_ML_C_N<3>

DP_T_SNK1_ML_C_P<2> DP_T_SNK1_ML_C_N<2>

DP_T_SNK1_ML_C_P<1> DP_T_SNK1_ML_C_N<1>

DP_T_SNK1_ML_C_P<0> DP_T_SNK1_ML_C_N<0>

GPU_TEST_PG_BACON

1

RA811

BOMOPTION=BAFFIN

0

5% 1/20W MF 0201

2

OUT OUT

113 89

1

RA815

10K

5% 1/20W MF 201

2

GPU_AUD<1> GPU_AUD<0>

EG_LCD_PWR_EN

RA810

1 2

GPU_CLKREQ_L

1K

5%

1/20W

MF

201

OUT OUT

98

113 27

113 101

89

OUT

BOMOPTION=BAFFIN

98

345678

NOSTUFF

1

CA880

0.1UF

10%

6.3V

2

X6S 0201

NOSTUFF

1

RA880

51.1

1% 1/20W MF 201

2

2 1

NOSTUFF

1

CA881

0.1UF

10%

6.3V

2

X6S 0201

GPU_PLLCHARZ_RC_LGPU_PLLCHARZ_RC_H

NOSTUFF

1

RA881

51.1

1% 1/20W MF 201

2

GPU_PLLCHARZ_H GPU_PLLCHARZ_L

99

D

C

PP1V8_S0_GPU

110 99 91

B

A

1

RA822

10K

5% 1/20W MF 201

2

1

RA823

10K

5% 1/20W MF 201

2

PP1V8_S0_GPU

110

PP3V3_S0_GPU

BOMOPTION=VRAM:GRP2

GPU_VRAM_STRAP

BOMOPTION=VRAM:GRP1

PLACE_NEAR=LA800.1:2.54MM

99

BA38

NC

AV29

NC

AU31

NC

AV31

NC

89

110 99 93

LA800

120OHM-25%-1.8A-0.06DCR

1 2

0402

1

CA850

0.1UF

10%

6.3V

2

X6S 0201

PLACE_NEAR=UA000.AM13:2.54MM

89

113 98

100

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

PP1V8_GPU_TSVDD

1

CA851

10UF

20%

6.3V

2

CERM-X6S 0402

PLACE_NEAR=UA000.AM13:2.54MM

DP_T_SNK0_HPD_EG

IN

DP_T_SNK1_HPD_EG

IN

DP_INT_EG_HPD

IN

GPU_XTAL_OR_CLK_IN GPU_XTAL_OUT

IN

OUT

GPUTHMSNS_D1_P GPUTHMSNS_D1_N

PLACE_NEAR=UA000.AM13:2.54MM

1

CA852

1UF

20%

6.3V

2

X6S-CERM 0201

1

CA853

2

PLACE_NEAR=UA000.AM13:2.54MM

AU25 AV23

AM29

NC

AV21

BA39 AY39

NC

AM13

0.1UF

10%

6.3V

X6S 0201

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG

HPD1

XTALIN XTALOUT

N35

DPLUS

N34

DMINUS

N38

TS_A

TSVDD

DDC1CLK

DDC1DATA

AUX1+

AUX1-

DDC2CLK

DDC2DATA

AUX2+

AUX2-

DDCAUX3+

DDCAUX3-

DDCAUX4+

DDCAUX4-

DDCAUX5+

DDCAUX5-

DDCVGACLK

DDCVGADATA

RSVD RSVD

AY10 BA10

AY11 BA11

AV19 AU19

AP19 AM19

AM21 AP21

AR23 AP23

AU27 AV27

AN34 AP31

K41 R34

NC NC

DP_INT_EG_AUX_P DP_INT_EG_AUX_N

DP_X_SNK0_AUXCH_C_P DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_C_N

DP_T_SNK0_AUXCH_C_P DP_T_SNK0_AUXCH_C_N

DP_T_SNK1_AUXCH_C_P DP_T_SNK1_AUXCH_C_N

IO IO

113 89

IO IO

113 27

113 101

SYNC_DATE=01/27/2016SYNC_MASTER=X363_SEAN

PAGE TITLE

A

Baffin DP/GPIO

DRAWING NUMBER SIZE

BOM_COST_GROUP=GRAPHICS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00647

REVISION

10.0.0

BRANCH

dvt-fab10

PAGE

108 OF 145

SHEET

99 OF 121

D

8 7 5 4 2 1

36

PPBUS_HS_GPU

109

345678

2 1

D

C

B

A

BOMOPTION=OMIT_TABLE

AW29

AW3 AW31 AW33 AW35 AW37 AW39

AW5

AW7

AW9

AY1 AY12 AY17

AY2 AY23 AY29 AY37 AY40 AY41

AY9

B1 B40 B41

BA17

BA2 BA23 BA29 BA37 BA40

BA5

BA9

C11

C13

C15

C17

C19

C21

C23

C25

C27

C29

C31

C33

C35

C37

C39

E13 E17 E21 E25 E29

E39

E41

G11

G15

G19

G23

G27

VSS

C5 C7 C9 E1

E3

E4

E9

G3

UA000

100-CK4803-ES

BGA

SYM 7 OF 7

VSS

PX_EN

G31 G35 G39 G7 J1 J3 J34 J37 J39 J40 J41 J5 K21 K25 K29 K40 L11 L15 L19 L23 L27 L3 L31 L35 L39 L7 N1 N17 N19 N25 N27 N3 N32 N37 N39 N5 R11 R17 R19 R25 R27 R3 R32 R35 R39 R7 U1 U17 U19 U25 U27 U3 U32 U37 U39 U5 W11 W17 W19 W25 W27 W3 W39 W7

AC41

NC

CRITICAL

1

CA900

12PF

5%

25V

2

NP0-C0G 0201

CRITICAL

1

CA901

3.0PF

+/-0.1PF

25V

2

NP0-C0G 0201

CA950

4700PF

A13 A17

A2 A21 A25 A29 A33 A37 A40

A5

A9

AA1 AA10 AA17 AA19 AA25 AA27

AA3 AA32 AA39

AA5 AC11 AC17 AC19 AC25 AC27

AC3 AC39

AC7

AE1 AE10 AE17 AE19 AE25 AE27

AE3 AE32 AE35 AE39

AE5 AG11 AG17 AG19 AG25 AG27

AG3 AG39 AG40 AG41

AG7

10%

10V

X7R

201

CRITICAL

1

CA902

33UF

20%

16V

2

POLY-TANT CASED12-SM

BOMOPTION=OMIT_TABLE

100-CK4803-ES

PP3V3_S5

110

91

1

2

IN

1

2

UA000

BGA

SYM 6 OF 7

P3V3GPU_EN

CRITICAL

CA903

2.2UF

20%

25V

X6S-CERM 0402

91

IN

P1V8GPU_EN

VSSVSS

CRITICAL

1

CA904

2.2UF

20%

25V

2

X6S-CERM 0402

AJ1 AJ10 AJ11 AJ3 AJ35 AJ39 AJ5 AL10 AL11 AL3 AL32 AL35 AL39 AL7 AM17 AM23 AN1 AN3 AN35 AN39 AN40 AN41 AN7 AP13 AP17 AR11 AR19 AR21 AR25 AR27 AR3 AR31 AR35 AR39 AR7 AU1 AU23 AU29 AU3 AU9 AW11 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

12

RA900

10

VOLTAGE=1.8V

PPVIN_S0GPU_1V8_RC

3.3V S0 GPU Switch

CA951

1UF

10%

10V

X5R

402-1

1

2

SLG5AP1453V

7 3

CAP

2 5

ON S

1

VDD

UA950

TDFN

GND

8

D

1

CA905

0.1UF

10%

25V

2

X6S 0402

99

PP3V3_S0 PP3V3_S0_GPU

Part Type R(on)

@ 5.3A Current

TPS62130B

11

PVIN

12

PVIN

UA900

10

AVIN

8

DEF

13

EN

7

FSW

PP3V3_S0

110

OUT

GPUTHMSNS_D1_P

THERMAL DIODE: GPU DIE

IN

GPUTHMSNS_D1_N

EDP: 0.100 A

TPS62130

QFN

CRITICAL

PGND

16

AGND

6

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850

PGND

15

QA960

BC846BLP

DFN1006H4-3

THERMAL DIODE: GPU PROXIMITY

Placement Note: Place QA960 TOP side, under the GPU

110

UA950

SLG5AP1453V SLG5AP1453V Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

OMIT_TABLE

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200

DIDT=TRUE

1

REG_PHASE_1V8GPU

2 3

14

REG_VOS_P1V8GPU

5

REG_FB_P1V8GPU

4 9

PAD

THRM

17

SW SW SW

VOS

FB

PG

SS/TR

AGND_P1V8GPU

IC,TPS62130B-S,3A BUCK CNVTRT,QFN16,3X3M1

GPUTHMSNS_D1_P

MAKE_BASE=TRUE

GPUTHMSNS_D1_N

MAKE_BASE=TRUE

3

1

CRITICAL

2

PCC:YES

10%

10V

X7R 201

1

2

CA952

4700PF

REG_SSTR_P1V8GPU

NO_XNET_CONNECTION=1

PLACE_NEAR=UA960.2:5MM

GPUTHMSNS_D2_P

NO_XNET_CONNECTION=1

GPUTHMSNS_D2_N

PP5V_S0

110

P5VGPU_RAMPP3V3GPU_RAMP

91

IN

P3V3GPU_EN

Part Type R(on)

@ 5.3A Current

P1V8GPU_PGOOD

CRITICAL

LA900

1.5UH-20%-2.61A-0.068OHM

1 2

PIFE32251B-SM

1

RA901

10

5% 1/20W MF 201

2

1

RA902

105K

1

CA906

4700PF

10%

10V

2

X7R 201

0.1% 1/16W MF 0402

2

<Ra>

1

RA903

82.5K

1% 1/16W MF-LF 402

2

<Rb>

XWA901

SM

P1V8GPU_FSW

1 2

Vout = 0.8V * ( Ra + Rb ) / Rb

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

UA900

CRITICAL353S00897

GPU THERMAL

RA960

47

1 2

5%

1/20W

MF

201

CA961

2200PF

X7R-CERM

TBTTHRM_SNS

PLACE_NEAR=UA960.3:5MM

CA962

2200PF

X7R-CERM

TBTTHRM_SNS

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V

1

10%

10V

2

0201

1

DXP1

2

DXN1

3

DXP2

4

DXN2

1

10%

10V

2

0201

5V S0 GPU Switch

PCC:YES

1UF

10%

10V

X5R

1

2

PCC:YES

1

VDD

UA951

SLG5AP1453V

7 3

CAP

2 5

ON S

TDFN

GND

8

UA951

D

CA953

402-1

Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

91

OUT

1

2

XWA900

SM

1 2

8

V+

CRITICAL

THERMAL SENSOR: VRAM PROXIMITY

UA960

TMP442A

SOT23-8

7

SCL

6

SDA

GND

5

Placement Note: Place UA960 Bottom side, under the VRAM shield can, but not within 2mm of any IC

I2C Write: 0x98, I2C Read: 0x99

PP5V_S0_GPUFET

VOLTAGE=5V

MIN_NECK_WIDTH=0.1000

MIN_LINE_WIDTH=0.1000

BOM_COST_GROUP=GRAPHICS

EDP: 0.100 A

Output voltage:

Switching freq:

CRITICAL

CA907

47UF

20%

6.3V

POLY-TANT 0805

BYPASS=UA960.1::5MM

1

CA960

0.1UF

10%

6.3V

2

CERM-X5R 0201

GPUTHRM_SNS

CRITICAL

1

CA908

47UF

20%

6.3V

2

POLY-TANT 0805

91 90

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CRITICAL

1

CA909

47UF

20%

6.3V

2

POLY-TANT 0805

1

CA910

47UF

20%

6.3V

2

POLY-TANT 0805

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

Baffin VSS & MISC

Apple Inc.

R

1.818 V

2.3 AMax peak current: 1250 kHz

CRITICAL

PP1V8_GPU

CRITICAL

1

CA911

47UF

20%

6.3V

2

POLY-TANT 0805

49

DRAWING NUMBER SIZE

051-00647

REVISION

BRANCH

PAGE

SHEET

110 116

CRITICAL

1

CA912

47UF

20%

6.3V

2

POLY-TANT 0805

SYNC_DATE=01/27/2016SYNC_MASTER=X363_SEAN

10.0.0

dvt-fab10 109 OF 145 100 OF 121

D

C

B

A

D

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Apple MacBook Pro 15 A1707 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual