Apple macbook pro 15 a1211 Schematics

http://mycomp.su/x/

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

09/19/2006

Schematic / PCB #’s

SCHEM,MLB,M59

ABBREV=DRAWING

TITLE=M59_MLB

LAST_MODIFIED=Mon Sep 25 10:45:58 2006

1

Table of Contents

N/A

Date

(.csa)

SyncPage

Contents

(MASTER)

42

44

(MASTER)

FW PHY Power Supply

Page Sync

(.csa)

Date

Contents

051-7150

1

CRITICAL

SCH

SCHEM,MLB,M59

820-2054 CRITICAL

PCB1

PCBF,MLB,M59

051-7150

SCHEM,MLB,M59

841

463525

A.0.0

A

PRODUCTION RELEASE

9/19/2006 9/19/2006

(MASTER)

43

45

(MASTER)

FireWire Port Power

(MASTER)

44

46

(MASTER)

FireWire Ports

(MASTER)

45

49

(MASTER)

Camera Connector

(MASTER)

46

52

(MASTER)

External USB Connector

(MASTER)

47

55

(MASTER)

Left I/O Board Connector

(MASTER)

48

57

(MASTER)

PCI-E Connections

(MASTER)

49

58

(MASTER)

SMC

(MASTER)

50

59

(MASTER)

SMC Support

(MASTER)

51

60

(MASTER)

LPC+ Debug Connector

(MASTER)

52

61

(MASTER)

Thermal Sensors

(MASTER)

53

62

(MASTER)

Current & Voltage Sensing

(MASTER)

54

63

(MASTER)

SPI BOOTROM

(MASTER)

55

64

(MASTER)

ALS Support

(MASTER)

56

65

(MASTER)

Fan Connectors

(MASTER)

57

66

(MASTER)

Sudden Motion Sensor (SMS)

(MASTER)

58

67

(MASTER)

TPM

(MASTER)

59

75

(MASTER)

IMVP6 CPU VCore Regulator

(MASTER)

60

76

(MASTER)

5V / 1.5V Power Supply

05/07/2006

61

77

M59_MG

2.5V & 1.2V Regulators

05/07/2006

62

78

M59_MG

1.8V Supply

05/07/2006

63

79

M59_MG

3.3V / 1.05V Power Supplies

08/01/2006

64

80

M59_MG

3.3V G3Hot Supply & Power Control

05/07/2006

65

81

M59_MG

Power Aliases

(MASTER)

66

82

(MASTER)

PBus-In,Batt. & 3G Pwr Connectors

(MASTER)

67

84

(MASTER)

ATI M56 PCI-E

(MASTER)

68

85

(MASTER)

GPU (M56) Core Supplies

(MASTER)

69

86

(MASTER)

ATI M56 Core Power

(MASTER)

70

87

(MASTER)

ATI M56 Frame Buffer I/F

07/25/2006

71

88

M59_MG

GPU Straps

(MASTER)

72

89

(MASTER)

GDDR3 Frame Buffer A

(MASTER)

73

90

(MASTER)

GDDR3 Frame Buffer B

(MASTER)

74

91

(MASTER)

ATI M56 GPIO/DVO/Misc

(MASTER)

75

93

(MASTER)

ATI M56 Video Interfaces

07/25/2006

76

94

M59_MG

Internal Display Connectors

07/25/2006

77

97

M59_MG

External Display Connector

(MASTER)

78

98

(MASTER)

M59 Specific Connectors

08/01/2006

79

99

M59_MG

LVDS Interface Pull-downs

N/A

80

100

N/A

Revision History

(MASTER)

81

101

(MASTER)

Napa Platform Constraints

(MASTER)

82

102

(MASTER)

More System Constraints

(MASTER)

83

103

(MASTER)

M59 Spacing & Physical Constraints

(MASTER)

84

104

(MASTER)

M59 Net Properties

2

System Block Diagram

N/A

3

Power Block Diagram

N/A

4

BOM Configuration

N/A

5

Functional / ICT Test

N/A

6

Signal Aliases/Misc Comps

N/A

7

CPU 1 OF 2-FSB

(MASTER)

8

CPU 2 OF 2-PWR/GND

(MASTER)

9

CPU Decoupling & VID

(MASTER)

10

CPU MISC1-TEMP SENSOR

(MASTER)

11

CPU ITP700FLEX DEBUG

(MASTER)

12

NB CPU Interface

(MASTER)

13

NB PEG / Video Interfaces

(MASTER)

14

NB Misc Interfaces

(MASTER)

15

NB DDR2 Interfaces

(MASTER)

16

NB Power 1

(MASTER)

17

NB Power 2

(MASTER)

18

NB Grounds

(MASTER)

19

NB (GM) Decoupling

M59_MG

07/25/2006

20

NB Config Straps

(MASTER)

21

SB: 1 OF 4

(MASTER)

22

SB: 2 of 4

(MASTER)

23

SB: 3 OF 4

M59_MG

07/25/2006

24

SB: 4 OF 4

(MASTER)

25

SB Decoupling

(MASTER)

26

26 SB Misc

(MASTER)

27

M1 SMBus Connections

(MASTER)

28

DDR2 SO-DIMM Connector A

(MASTER)

29

DDR2 SO-DIMM Connector B

(MASTER)

30

Memory Active Termination

(MASTER)

31

Memory Vtt Supply

(MASTER)

32

DDR2 VRef

(MASTER)

33

33 CLOCKS

(MASTER)

34

Clock Termination

M59_MG

05/07/2006

37

35

Mobile Clocking

(MASTER)

38

36

PATA Connector

(MASTER)

39

37

FireWire Link (TSB83AA22)

(MASTER)

40

38

FireWire PHY (TSB83AA22)

(MASTER)

41

39

ETHERNET CONTROLLER

(MASTER)

42

40

Ethernet Connector

(MASTER)

43

41

Yukon Power Control

(MASTER)

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Connector

P.78

PATA

SATA

USB x2

DDR2 SO-DIMM B

DDR2 SO-DIMM A

"Expansion Slot" Connector

Geyser KB/TP/BT

Connector

MUX

Dual-Channel LVDS

LVDS Graphics

P.99

Dual-Channel TMDS

S-Video/Composite

P.67-71,74-75

ATI M56P

GPU

Yukon Power

P.39

P.57-64,69

P.56

Fan

SMBus x5

TSB83AA22 FireWire

P.43

PHY Power

Controller

Yukon Gig-E

P.39

P.37-38

Controller

Connectors

SMBus

BootROM

PWM/Tach

P.54

SPI

SMC

H8S/2116

P.49-50

LPC 33MHZ

TPM

P.58

PCI

PCIe x1

609 BGA

P.21-26

SB

P.12-20

ICH7-M

DMI x4

P.72-73

GDDR3

128MB/256MB

Frame Buffer

PCIe x16

SENSOR

P.10

THERMAL

CPU

P.7-9

NB

1466UFCBGA

945GM

FSB

(Merom)

479 BGA

Core Duo

SMS

Analog

Sensors

Connector

LPC

Debug

ALS

USB

P.51

P.55,78

P.57

P.53

PCIe x1

CH.B

CH.A

P.11

Power

Supplies

Azalia (HD-Audio)

BUFFER

DDR2 VREF

P.32

P.47

Connector

Audio Board

Left I/O &

P.30-31

CPU Debug

ITP700FLEX

Connector

J2900

J2800

P.28

P.29

DDR2 VTT

& REGULATOR

P.27

SB SMBus

SMC SMBus

P.27

16BITS

66MHZ

P.43

Port Power

P.40

P.44

Sensors

Temperature

FW

ENET

DVI-I/DL Connector

w/TV-Out Support

LCD Panel

ODD

Connector

Controller

CK410 Clock

P.33-34

Battery SMBus

Connector

RJ45 (Ethernet)

Connector

Right USB 2.0

Connector

1394a/b (FireWire)

P.46

P.78

P.45

P.36

P.52

P.66

P.76,79

P.77

Connectors

PWM

Connector

Inverter

P.76

Camera

USB x2

USB

HDD/IR/SIL

USB

"Factory Slot" Connector

(Upper/Inner)

(Lower/Outer)

System Block Diagram

A.0.0

2 84

051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ISL6269B)

(TPS51100)

(TPS51117)

(ISL9504)

1.25V - 0.8V

5V/1.5V

PM_SLP_S3_L

U8500

NC

1.5V

PGOOD

S5

3.3V

ENABLE

PPVCORE_S0_CPU

1.05V

PP1V05_S0

PGOOD

1.05V

U7950

PGOOD

GPU VCore

ENABLE

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

U7750

1.2V

PP1V2_S3

PP2V5_S3

2.5V

S3

PGOOD

ENABLE

U7700

3.3V

PP3V3_S3

PP5V_S0

5.0V

PP5V_S3

PP1V5_S0

5.0V

PP5V_S5

SMC_PM_G2_ENABLE

NC

(LTC3728)

S5/S0

PGOOD

ENABLES

U7600

5V

1.5V

PM_SLP_S3_L

SMC_PM_G2_ENABLE

PGOOD

VR_PWRGOOD_DELAY

"IMVP6"

S0

CPU VCore

ENABLES

IMVP_PWRGD_IN

IMVP_VR_ON

RSMRST_PWRGD

S0

IMVP_PWRGD_IN/ALL_SYS_PWRGD

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

ENABLE

J5500

Connector

Inverter

PP1V8_S3

1.8V

NC

1.8V

U7800

S3

ENABLE

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt) S0

PP0V9_S0

0.9V

1.2V

1.8V

5.0V

U8000

3.425V

PP3V42_G3H

(LT3470)

G3Hot

3.425

ENABLE

12.6V - 9V

18.5V - 9V

PPDCIN_G3H

J5500

LIO Flex

Connector

PM_SLP_S4_L

U7900

PPBUS_G3H

J8200

LIO Power Connector

Q3820

5V

PP5V_S0_IDE_ODD

ODD_PWR_EN_L (SB GPIO14)

PP3V3_S3AC

3.3V

Q4300

PM_SLP_S3BATT

NC

PM_SLP_S3BATT

U7530

Q7610

Q7615

Q7770

Q7845

Q7945

1.1V - 0.95V

PP3V3_S5

3.3V

2.5V

(TPS62510)

2.5V

Q7720

2.5V

PM_SLP_S3_LS5V_L

PP2V5_S0

Q7721

PP2V5_D3C

P1V2R2V5D3C_EN_LS5V

PP1V2_D3C

P1V2R2V5D3C_EN_LS5V

P1V8D3C_EN

PP1V8_D3C

Q7947

3.3V

PP3V3_S0

3.3V

Q7948

PP3V3_D3C

P3V3D3C_EN_L

12.6V - 9V

PPBUS_S5_FWPORT

Q4500 Q4501

PM_SLP_S3_LS5V

FW_PWRCTRL_GATE1

FW_PWRCTRL_GATE2_1/2

=GPUVCORE_EN_L

D3C

PPVCORE_D3C_GPU

843

051-7150

A.0.0

SYNC_DATE=N/A

SYNC_MASTER=N/A

Power Block Diagram

http://mycomp.su/x/

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Label / EEE #’s

2.16Ghz BOMs

2.33Ghz BOMs

BOMOPTION Groups

Module Parts

extra TPM options:

Alternate Parts

SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP

EEE_WTG

[EEE:WTG]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

IC,ICH7M,BGA

1

343S0385 CRITICAL

U2100

341S1797

1

CRITICAL

U4102

IC,EEPROM,SERIAL IIC,8KBIT,SO8

IC, TPM, 28-PIN TSSOP

341S1789 CRITICAL

U6700

1 TPM

U3301

CRITICAL

1

LOW POWER CLOCK SYNTHESIZER, 68PIN

359S0109

IC,ISL9504,SYNC REG CTRL,QFN48

U7530

353S1461 CRITICAL

1

IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA

338S0368

U8400

1

CRITICAL

IC,945GM,NORTHBRIDGE

CRITICAL

1

U1200

338S0269

338S0270

1

U4101

CRITICAL

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

TPM

M59_TPM

337S3393 CRITICAL

1

U0700

CPU_2_33GHZ

IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA

128S0093

33uF,16V,D2

128S0092

ALL

152S0435

ALL

152S0287

Alternates for Coilcraft MSS5131

Screened ISL6262 for ISL9504

353S1465 353S1461

ALL

128S0095

330uF,2V,6MOHM,D2

128S0060

128S0061128S0081

ALL

150uF,6.3V,25MOHM,C2

ALL

376S0445

Si7806ADN for FDM6296

376S0448

128S0060

330uF,2V,9MOHM,D2

128S0094

ALL

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEE:WTE]

EEE_WTE

4

A.0.0

BOM Configuration

051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

84

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA

333S0377

VRAM_256_INFINEON

4

CRITICAL

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

VRAM_256_HYNIX

4

CRITICAL333S0351

U8900,U8950,U9000,U9050

VRAM_128_INFINEON

333S0376

U8900,U8950,U9000,U9050

4

CRITICAL

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL333S0358

4

U8900,U8950,U9000,U9050

VRAM_128_HYNIX

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

333S0350

4

CRITICAL

VRAM_256_SAMSUNG

VRAM_128_SAMSUNG

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL333S0354

4

U8900,U8950,U9000,U9050

VRAM_INF256

GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEON

VRAM_128_SAMSUNG

VRAM_SAM128

MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M59_COMMON3

M59_COMMON1

BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3

ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3

M59_COMMON

GPU_MEM_256M,VRAM_256_SAMSUNG

VRAM_SAM256

M59_COMMON2

ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3

PCBA,2.33GHZ,256VRAM,M59,MBP15

630-7851

EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256

IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA

CPU_2_16GHZ

CRITICAL

1

U0700

337S3391

IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59

341S1922

1

CRITICAL

U6301

BOOTROM_DEVEL

1

SMC_BLANK

U5800

338S0274

IC,SMC,HS8/2116

CRITICAL

BOOTROM_FINAL

IC,EFI,BOOTROM FINAL (LOCKED),M59

341S1923

1

CRITICAL

U6301

IC,PRGRM,SMC (NEW),M59

341S1929 CRITICAL

U5800

1

SMC_PRGRM

PCBA,2.16GHZ,128VRAM,M59,MBP15

630-7849

EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128

GPU_MEM_NOT_SAM,VRAM_128_INFINEON

VRAM_INF128

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power Supply NO_TESTs

EXPOSED_VIA

NO_TEST

FUNC_TEST

FUNC_TESTFUNC_TEST

FUNC_TEST

LPC+ Debug Connector

Fan Connectors

Left I/O Data Connector

Functional Test Points

Battery Digital Connector

Left ALS Connector

Left I/O Power Connector

Request for at least 10 GND test points

called out separately in these notes.

NOTE: 10 additional GND test points are

FUNC_TEST

should have a via with 10-mil soldermask

EXPOSED_VIA property indicates that the net

Misc EXPOSED_VIA Nets

opening for use as engineering probe point.

EXPOSED_VIA

CPU FSB NO_TESTs

NO_TEST

2 TPs per

FUNC_TEST

8 TPs, 2 with each of above TP pairs

FUNC_TEST

Thermal Diode Connectors

Current Sense Calibration

FUNC_TEST

Other Func Test Points

RTC Battery Connector

FUNC_TEST

Camera Connector

FUNC_TEST

Inverter Connector

Functional / ICT Test

SYNC_DATE=N/A

SYNC_MASTER=N/A

5 84

A.0.0051-7150

TRUE

GND_CHASSIS_INVERTER

INVERTER_PWM

TRUE

GND_INVERTER

TRUE

PP5V_INVERTER_SW

TRUE

PPBUS_S0_INVERTER

TRUE

=USB2_CAMERA_N =USB2_CAMERA_P

=PP5V_S3_CAMERA

TRUE

GND

TRUE

PPVBATT_G3C_RTC

TRUE

LTALS_OUT

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

=PP1V05_S0_REG

TRUE

HSTHMSNS_DX_P

TRUE TRUE

HSTHMSNS_DX_N RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

TRUE

ISENSE_CAL_EN =PP5V_S0_ISENSECAL

TRUE

=PP1V8_S3_REG

TRUE

=PP1V5_S0_REG

TRUE TRUE

PPVCORE_S0_GPU

TRUE

PPVCORE_S0_CPU

TRUE

GND

TRUE

SMC_TRST_L

FSB_LOCK_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HIT_L

TRUE

FSB_HITM_L

TRUE

FSB_DSTBP_L<3..0>

TRUE TRUE

TRUE

FSB_DSTBN_L<3..0>

TRUE

FSB_DRDY_L

FSB_DINV_L<3..0>

TRUE TRUE

FSB_DBSY_L

TRUE

FSB_D_L<63..0>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

FSB_A_L<31..3>

TRUE

CK410_XTAL_IN

P3V3S5_UG

TRUE

P3V3S5_FSET

TRUE

P3V3S5_ISEN

TRUE

P3V3S5_LG

TRUE

P3V3S5_FB_RC

TRUE

P3V3S5_COMP

TRUE

P3V3S5_COMP_R

TRUE

P3V3S5_FB

TRUE

P1V5S0_RUNSS

TRUE

P3V3S5_BOOT

TRUE

P3V3S5_BOOT_R

TRUE

P1V05S0_PHASE

TRUE

P1V05S0_LG

TRUE

P1V05S0_UG

TRUE

P1V05S0_ISEN

TRUE

P1V05S0_FB_RC

TRUE

P1V05S0_FB

TRUE

P1V05S0_FSET

TRUE

P1V05S0_COMP

TRUE

P1V05S0_BOOT_R

TRUE

P1V05S0_COMP_R

TRUE

P1V05S0_BOOT

TRUE

IMVP6_VDIFF

TRUE

IMVP6_OCSET

TRUE

IMVP6_VDIFF_RC

TRUE

IMVP6_DFB

TRUE

IMVP6_COMP_RC

TRUE

IMVP6_FB

TRUE

GPUVCORE_UG

TRUE

GPUVCORE_PHASE

TRUE

GPUVCORE_ISEN

TRUE

GPUVCORE_LG

TRUE

GPUBBN_FB

TRUE

GPUVCORE_FB

TRUE

GPUVCORE_FB_RC

TRUE

GPUBBP_ADJ

TRUE

GPUVCORE_FSET

TRUE

GPUVCORE_COMP

TRUE

P3V42G3H_FB

TRUE

P1V05S0_COMP

TRUE

P1V05S0_FSET

TRUE

P3V3S5_FSET

TRUE

P3V3S5_COMP

TRUE

P1V2S3_RT

TRUE

P1V2S3_RUNSS

TRUE

SB_CLK100M_SATA_N

TRUE

SB_CLK100M_SATA_P

TRUE

DMI_N2S_N<1..0>

TRUE

DMI_N2S_P<1..0>

TRUE

EXCARD_CLKREQ_L

TRUE

=PPBUS_G3H_LIO_CONN

TRUE

GND

PCIE_WAKE_L

TRUE

=SMBUS_LIO_SB_SDA

TRUE

=SMBUS_LIO_SB_SCL

TRUE

=SMBUS_LIO_SMC_SDA

TRUE

PCIE_CLK100M_MINI_N

TRUE

=SMBUS_LIO_SMC_SCL

TRUE

PCIE_CLK100M_MINI_P

TRUE

=PCIE_MINI_D2R_N

TRUE

=PCIE_MINI_D2R_P

TRUE

=PCIE_MINI_R2D_P

TRUE

=PCIE_MINI_R2D_N

TRUE

SYS_ONEWIRE

TRUE

LIO_P3V3S0_EN_L

TRUE

SMC_BATT_ISET

EXCARD_OC_L

TRUE

ACZ_RST_L

TRUE

LTUSB_OC_L

TRUE

GND_BATT

TRUE

GND

ALS_GAIN

TRUE

=PP3V3_S3_LTALS

TRUE

FWH_INIT_L

TRUE

PM_SUS_STAT_L

TRUE

SMC_TCK

TRUE

SMC_NMI

TRUE

SV_SET_UP

TRUE

=PCIE_EXCARD_R2D_N

TRUE

SMC_TDI

TRUE

INT_SERIRQ

TRUE

LPC_AD<2>

TRUE

PCI_CLK_PORT80_LPC

LPC_AD<3>

TRUE

=PP5V_S0_FAN_LT

TRUE

FAN_RT_PWM

TRUE

FAN_LT_TACH

TRUE

FAN_LT_PWM

TRUE

FAN_RT_TACH

TRUE

PCIE_CLK100M_EXCARD_P

ACZ_BITCLK

TRUE

SMC_TMS

TRUE

LPC_AD<0>

TRUE

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

BOOT_LPC_SPI_L

TRUE

DEBUG_RST_L

TRUE

=PP5V_S0_LPCPLUS

ACZ_SDATAIN<0>

TRUE

LPC_AD<1>

TRUE

SMC_TX_L

TRUE

SMC_RST_L

TRUE

SMC_RX_L

GND_AUDIO

TRUE

GND_AUDIO_PWR

TRUE

=PP3V42_G3H_LIO

TRUE

PP5V_S0_AUDIO_PWR

TRUE

SMC_MD1

SMC_TDO

TRUE

SMC_SYS_ISET

TRUE

LIO_BATT_ISENSE

LIO_DCIN_ISENSE

TRUE TRUE

LIO_P3V3S3_EN

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

MINI_CLKREQ_L

TRUE

SMC_EXCARD_CP

LIO_PLT_RESET_L

TRUE

SMC_EXCARD_PWR_EN

TRUE

ACZ_SYNC

TRUE

=USB2_LT_P

TRUE

=USB2_LT_N

TRUE

=USB2_EXCARD_P

TRUE

=USB2_EXCARD_N

=PCIE_EXCARD_R2D_P

TRUE

=PCIE_EXCARD_D2R_P

TRUE

SMC_ADAPTER_EN

TRUE

=SMBUS_BATT_SDA

TRUE

SMC_BS_ALRT_L

TRUE

=SMBUS_BATT_SCL

=PCIE_EXCARD_D2R_N

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

PP5V_S0_AUDIO

=PP5V_S5_LIO

TRUE

=PPDCIN_G3H_LIO

=PP1V5_S0_LIO

TRUE

SMC_BC_ACOK

TRUE

SMC_BATT_CHG_EN

ACZ_SDATAOUT

TRUE

=PP3V3_S5_LPCPLUS

IMVP6_RBIAS

TRUE

IMVP6_COMP

TRUE

P5VS5_RUNSS

TRUE

P1V5S0_RUNSS

TRUE

84D6 12D6

84D6

12C6

12B4

12B6

84D6

58C6

51B4

51B5

78C2

84D6

7C4

84C6

12D4

51B5

58C6

50B3

50A2

50C6

49B7

65D8

84D6

12B4

84D6

7C3

84D6

7C3

84D6

7C3

84D6

12C4

84D6

12C4

64C6

47C3

50B2

50B3

84B4

78C6

51C5

50A2

51B5

51C5

84B4

51B4

51C4

51B4 84B4

51C4

50B2

51B5

50B2

51B4

50A2

84B4

49D5

66B5

50A2

84B4

64C6

45C3

45B3

65B1

78C6

50B2

26C5

63A2

53A8

65A1

65B8

65C8

51B4

12B4

12A4

12B4

7B4

12B4

7B4

12B4

7B4

12C4

7D8

12C4

7D8

63D6

63C6

60C4

63B7

63A7

63B7

63D6

63C6

61B7

34C3

22D2

47C6

66C4

39C6

47C3

48C6

49B7

64C6

49B5

47C6

47B3

47C6

49B5

78C5

50D3

49C5

50B2

51B5

23C3

48C6

50B2

49C7

51C5

49C7

65A1

47B3

47B6

50B2

49D7

49C7

49C5

49C7

51B4

65A1

47B6

49D7

49C7

50D6

49C7

65D3

51B4

50B2

49B5

53C3

53C5

64A6

49D7

47C6

49B7

47C6

49B7

47B6

47C3

48C6

47C6

66B5

50B2

66B5

48B6

47B3

65B1

65A8

65C6

49C5

49D7

47B6

65D3

64A6

60C4

6A8

76A5

76B5

6C3

6D3

45C3 26D6

55C7

49C5

23C5

53A4

52C5

52D5

52C5

49B7

53A8

62C1

60C1

65D1

49C1

7D6

7D8

7D6

7B3

7D6

7B3

7D6

7B3

7D6

7C8

7D6

7C8

33C6

63D4

5D7

63C4

63C2

5D7

63C6

5D7

63D4

63B5

63A5

63B5

63A5

63A3

63A7

5D7

63B5

63A7

63B5

59C7

59C6

59B8

59B6

59B8

59B7

68D5

68C5

68A3

68C7

68C3

68B7

68C7

64C3

5C7

5B7

61B6

41C4

21B6

14B4

34A3

65C3

23C8

27B6

27D1

34D4

27D1

34D4

47C3

47B3

47C6

47B6

6C3

21C7

6D3

66B5

6D5

65C3

21C4

23C5

49C5

49C1

23B6

47B3

49B5

23C8

21D4

34D6

21D4

56C7

56B3

56B6

56B3

34C3

21C7

49B5

21D4

21C5

23C8

22B3

26B1

51C4

21C7

21D4

46B5

49C3

46B5

47A4

47D6

47D4

49C1

49B5

47C6

47B6

34A3

47B6

26C1

47B6

21C7

6D3

6C3

47B3

43B7

27C1

49C5

27C1

47B3

34B3

47C4

47C6

47D6

47B6

47C6

21C7

51C4

59C7

59B7

60C5

5B7

http://mycomp.su/x/

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Port "H" = Reserved

Frame holes

Left CPU TM Hole

Top CPU TM Hole

Right CPU TM Hole

Add 2 blind vias per hole per side to GND

Bottom Left GPU TM Hole

Top GPU Right TM Hole

Thermal Module Holes

"ENET_LOWPWR_EN" are mutually-exclusive.

Chassis connection to be made at the mounting hole east of the LVDS connector

USB Port "G" = Bluetooth (M13L)

USB Port "E" = ExpressCard

USB Port "F" = IR Receiver

USB Port "C" = Left USB 2.0 Port

NOTE: NB_CFG<13..12> require test access

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "D" = Camera

FireWire Aliases

RAM door (Torx) holes

Chassis GNDs

LVDS pulldown aliases

Ethernet Power Management Support

Inverter PWM Reset Alias

NOTE: BOM options "USB_G_OC_PU" and

HOLE-VIA-P5RP25

1

ZT0602

ENET_LOWPWR_EN

5%

1/16W

402

0

MF-LF

21

R0600

0.01UF

10% 50V X7R 402

2

1

C0630

HOLE-VIA-P5RP25

1

ZT0630

0.01UF

10% 50V X7R 402

2

1

C0631

HOLE-VIA-P5RP25

1

ZT0631

402

X7R

50V

10%

0.01UF

2

1

C0610

HOLE-VIA-P5RP25

1

ZT0610

0.01UF

10% 50V X7R 402

2

1

C0611

HOLE-VIA-P5RP25

1

ZT0611

402

X7R

50V

10%

0.01UF

2

1

C0612

HOLE-VIA-P5RP25

1

ZT0612

402

X7R

50V

10%

0.01UF

2

1

C0602

402

X7R

50V

10%

0.01UF

2

1

C0600

HOLE-VIA-P5RP25

1

ZT0615

HOLE-VIA-P5RP25

1

ZT0614

HOLE-VIA-P5RP25

1

ZT0613

402

X7R

50V

10%

0.01UF

2

1

C0613

402

X7R

50V

10%

0.01UF

2

1

C0614

402

X7R

50V

10%

0.01UF

2

1

C0615

SHLD-SM-LF

OG-503040

3

2

1

SH0600

0

5% 1/16W MF-LF 402

2

1

R0601

Signal Aliases/Misc Comps

6 84

A.0.0051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

M59_INVERTER_PLT_RST_L

=INVERTER_PWM_PLT_RST_L

ENET_CTRL25

MAKE_BASE=TRUE NO_TEST=TRUE

NC_ENET_CTRL25

=LVDS_PD_L_DATA_N<2>

LVDS_L_DATA_CONN_N<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<2>

LVDS_L_DATA_CONN_P<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_N<1>

LVDS_L_DATA_CONN_N<1>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<1>

LVDS_L_DATA_CONN_P<1>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_N<0>

LVDS_L_DATA_CONN_N<0>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<0>

LVDS_L_DATA_CONN_P<0>

MAKE_BASE=TRUE

=LVDS_PD_L_CLK_P

LVDS_L_CLK_CONN_P

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<2>

LVDS_U_DATA_CONN_N<2>

MAKE_BASE=TRUE

=LVDS_PD_L_CLK_N

LVDS_L_CLK_CONN_N

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<2>

LVDS_U_DATA_CONN_P<2>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<1>

LVDS_U_DATA_CONN_N<1>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<1>

LVDS_U_DATA_CONN_P<1>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<0>

LVDS_U_DATA_CONN_N<0>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<0>

LVDS_U_DATA_CONN_P<0>

MAKE_BASE=TRUE

=LVDS_PD_U_CLK_P

MAKE_BASE=TRUE

LVDS_U_CLK_CONN_P

=LVDS_PD_U_CLK_N

MAKE_BASE=TRUE

LVDS_U_CLK_CONN_N

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_ENET

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_DVI_BOT

VOLTAGE=0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_FW_PORT2U

=GND_CHASSIS_FW_PORT1

=GND_CHASSIS_ENET

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI1 =GND_CHASSIS_DVI3

GND_CHASSIS_DVI_TOP

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_DVI4

=GND_CHASSIS_DVI2

=GND_CHASSIS_FW_EMI_R

=GND_CHASSIS_RTUSB =GND_CHASSIS_FW_PORT2L

GND_CHASSIS_RTUSB

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

GND_CHASSIS_LIOFLEX_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_BATTCONN_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RAMDOOR_HOLE_0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

=GND_CHASSIS_CAMERA

=PP3V3_FWPHY_CORE

TP_USB_H_N

MAKE_BASE=TRUE

TP_USB_H_N

USB_G_P

USB_G_N

USB_BT_N

MAKE_BASE=TRUE

USB_BT_P

=USB_BT_P

=USB_BT_N

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_CHASSIS_LNDACARD_HOLE

VOLTAGE=0V

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RAMDOOR_HOLE_1

=PP1V95_FWPHY_CORE_LDO

PCI_REQ3_L

MAKE_BASE=TRUE

=FW_PCI_REQ_L

MAKE_BASE=TRUE

PCI_GNT3_L

=FW_PCI_GNT_L

MAKE_BASE=TRUE

PCI_AD<19>

=FW_PCI_IDSEL

MAKE_BASE=TRUE

SMC_RSTGATE_L

=SMC_FWRSTGATE_L

=PP1V8_FWPHY_OSC

=PP1V95_FWPHY

=PP3V3_FWPHY_REG

=PP3V3_FWLATEVG_ACTIVE

=PP3V3_FWPHY

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP1V95_FWPHY

VOLTAGE=1.95V

MAKE_BASE=TRUE

USB_F_N

USB_B_P

MAKE_BASE=TRUE

TP_NB_CFG<8>

LTUSB_OC_L

MAKE_BASE=TRUE

USB_F_P

=USB2_LT_N

=USB2_EXCARD_N

USB2_EXCARD_P

MAKE_BASE=TRUE

USB2_CAMERA_N

USB2_CAMERA_P

MAKE_BASE=TRUE

USB_E_N

USB_E_OC_L

USB_D_N

=USB2_LT_P

USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_P

MAKE_BASE=TRUE

=RTUSB_OC_L

MAKE_BASE=TRUE

RTUSB_OC_L

USB_C_N

USB_C_OC_L

USB_C_P

UNUSED_USB_B_OC_L

MAKE_BASE=TRUE

USB_B_OC_L

USB_B_N

USB_A_OC_L

USB_A_N

USB_A_P

=USB2_RT_N

=USB2_RT_P

MAKE_BASE=TRUE

USB2_RT_P

USB2_RT_N

MAKE_BASE=TRUE

NC_CPU_A32_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A33_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A34_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A35_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A37_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A38_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A39_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HFPLL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE0

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE1

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_SPARE4

MAKE_BASE=TRUE NO_TEST=TRUE

TP_CPU_A32_L

TP_CPU_A33_L

TP_CPU_A34_L

TP_CPU_A37_L

TP_CPU_A36_L

TP_CPU_A38_L

TP_CPU_A39_L

TP_CPU_APM1_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE2

TP_CPU_SPARE1

TP_CPU_SPARE4

USB_D_P

=USB_TRACKPAD_P

MAKE_BASE=TRUE

USB2_LT_P

USB2_LT_N

MAKE_BASE=TRUE

NC_CPU_EXTBREF

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_HFPLL

NC_CPU_APM0_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_APM1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A36_L

NO_TEST=TRUE

MAKE_BASE=TRUE

=USB2_CAMERA_P

TP_CPU_APM0_L

MEM_A_A<15..14>

MAKE_BASE=TRUE NO_TEST=TRUE

NC_MEM_A_A<15..14>

MEM_B_A<15..14>

MAKE_BASE=TRUE NO_TEST=TRUE

NC_MEM_B_A<15..14>

NB_CFG<4..3>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<8>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<17>

NB_CFG<13..12>

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

SUS_CLK_SB

MAKE_BASE=TRUE

TP_SB_SUS_CLK

TP_SB_XOR_T5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_T5

TP_SB_XOR_V3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_V3

TP_SB_XOR_U5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_U5

TP_SB_XOR_W3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_W3

TP_SB_XOR_V4

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_V4

SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

=RTALS_GAIN

MAKE_BASE=TRUE

ALS_GAIN

ENET_CTRL12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_CTRL12

=USB_TRACKPAD_N

EXCARD_OC_L

MAKE_BASE=TRUE

=USB_IR_N

USB_IR_N

MAKE_BASE=TRUE

USB_E_P

USB_D_OC_L

MAKE_BASE=TRUE

USB_IR_P

=USB_IR_P

=USB2_EXCARD_P

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD3 =GND_CHASSIS_LCD4

=GND_CHASSIS_LCD2

=GND_CHASSIS_LCD1

UNUSED_USB_D_OC_L

MAKE_BASE=TRUE

USB2_EXCARD_N

=USB2_CAMERA_N

TP_CPU_A35_L

ENET_LOWPWR_EN

SB_GPIO30

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_CHASSIS_DIMM_NOTCH

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_CHASSIS_RIGHT_FAN_NOTCH

GND_CHASSIS_RIGHT_FAN_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP3V3_FWLATEVG

MIN_LINE_WIDTH=0.38 mm MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_FWPHY

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

TP_USB_H_P

MAKE_BASE=TRUE

TP_USB_H_P

79C1

79D1

79C1

79D1

79C1

78C6

50B3

76D7

45C5

22C2 22C2

26D2

37C6

49D7

44B8

47C6

47C3

22D8

47C3

22D8

45B3

49D7

49B5

47C6

22D8

47C3

45C3

22D8

22C2 22C2

26C1 76A8

39C8

79C8 76C2

79D8 76C2

79C8 76C2

79B8 76C2

79C8 76C2

79B8 76B2

79B8 76C2

79C8 76C2

79B8 76B2

44A1

44C1

40B2

77A2

77B5

77A2

77A3

77A5

44A3

46B2

44A1

45B5

42C4

6C1 6C2

22C2

78C2

42C1

22B6 37D3

22A7

37B7

6D4

37A8

38B2

38D5

42C4

43A7

38D7

22C2

5C1

22C2

5B1

22C2

22C4

22C2

5B1

46C5

22C2

22C4

22C2

22C4

22C2

22C4

22C2

46B5

7C8

7B8

7B6

22C2

78C3

7B8

5A4

7B8

28C3

29C3

14C6

23C3

21C6

6B7

55C4

5B2

39C8

78C3

5C1

78B4

22C2

22C4

78B4

5B1

76A6

76C3

76B2

76D3

76D2

5A4

7B8

39B8 22C4

44A8

5A4

6C1 6C2

http://mycomp.su/x/

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IN

IN IN

IN

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IN

IN IN

IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

A7*

RSVD14 RSVD15

BCLK1

BCLK0

RSVD20

RSVD17 RSVD18 RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1* BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6 RSVD7 RSVD8

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

RSVD9 RSVD10

SMI*

LINT0 LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30* A31*

A27* A28* A29*

A26*

A25*

A24*

A22* A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14* A15* A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2 COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52* D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45* D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0 BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26* D27* D28*

D24* D25*

D23*

D21* D22*

D20*

D19*

D18*

D16* D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU IS HOT

AND CPU VR TO INFORM

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

LAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TO

PM_THRMTRIP#

STUB)

SPARE[7-0],HFPLL: ROUTE TO TP VIA AND

0.1" AWAY

1/16W 402

MF-LF

54.9

1%

2

1

R0702

MF-LF 402

5% 1/16W

68

2

1

R0704

1/16W

1%

402

MF-LF

1K

2

1

R0705

1/16W

1%

402

MF-LF

2.0K

2

1

R0706

54.9

402

1%

21

R0719

27.4

21

R0718

54.9

4021%

21

R0717

402

27.4

21

R0716

0

402

NOSTUFF

21

R0730

NOSTUFF

1K

MF-LF 402

5% 1/16W

2

1

R0707

MF-LF 402

5% 1/16W

51

2

1

R0712

54.9

1% 1/16W MF-LF 402

2

1

R0703

54.9

402

1%

21

R0720

1%

402

54.9

21

R0721

54.9

402

1%

21

R0722

BGA

YONAH

CPU

OMIT

AB6

G2

AB5

C7

A25

A24

AB3

AA6

AC5

D5

A3

B2

V3

T2

N5

M4

AA3

AB2

C24

AA4

C23

D22

AF1

C1

D3

F6

D2

T22

B25

C3

AA1

G3

F4

F3

B1

L5

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V4

L2

H1

J1

N2

M1

K5

M3

L4

Y1

W2

J4

Y4

W5

W3

T3

T5

R4

U2

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L1

P2

P5

N3

U0700

CPU

YONAH

BGA

OMIT

D25

C26

D7

D6

AE6

A2

AD26

AE24

Y25

N25

G22

AD23

W24

M24

H23

D24

B5

E5

AC20

V23

M26

J26

G24

K24

E23

AF26

AF22

AF25

AE25

E25

AD21

AE21

AD24

AF23

AE22

AD20

AC25

AB21

AA21

AB22

G25

AC23

AC22

AA24

AC26

Y22

Y26

AA26

Y23

W22

AB25

F23

U22

U25

U23

W25

V26

V24

AB24

AA23

N24

T25

H22

L26

R24

T24

P23

P22

P25

M23

L23

L22

L25

E26

R23

P26

K25

N22

H25

K22

F26

H26

J23

J24

F24

E22

V1

U1

U26

R26

C21

B23

B22

U0700

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

84

051-7150 A.0.0

7

CPU 1 OF 2-FSB

FSB_BPRI_L

FSB_BNR_L

FSB_ADS_L

CPU_PSI_L

FSB_SLPCPU_L

CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L

CPU_COMP<2> CPU_COMP<3>

CPU_COMP<1>

CPU_COMP<0>

FSB_DSTBP_L<3>

FSB_DSTBN_L<3>

FSB_DINV_L<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<52> FSB_D_L<53>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTBN_L<2>

FSB_D_L<47>

FSB_DSTBP_L<2>

FSB_D_L<45> FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

CPU_BSEL<2>

FSB_DSTBN_L<1>

CPU_BSEL<0> CPU_BSEL<1>

CPU_TEST2

CPU_TEST1

FSB_DINV_L<1>

FSB_DSTBP_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28>

FSB_D_L<24> FSB_D_L<25>

FSB_D_L<23>

FSB_D_L<21> FSB_D_L<22>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<16> FSB_D_L<17>

FSB_DINV_L<0>

FSB_DSTBP_L<0>

FSB_DSTBN_L<0>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

CPU_GTLREF

FSB_A_L<7>

TP_CPU_SPARE1 TP_CPU_SPARE2

FSB_CLK_CPU_N

FSB_CLK_CPU_P

TP_CPU_SPARE7

TP_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6

TP_CPU_SPARE3

TP_CPU_SPARE0

TP_CPU_EXTBREF

PM_THRMTRIP_L

CPU_THERMD_N

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<0>

FSB_CPURST_L

FSB_LOCK_L

CPU_INIT_L

FSB_IERR_L

FSB_BREQ0_L

FSB_DRDY_L

FSB_DEFER_L

TP_CPU_HFPLL

TP_CPU_A37_L TP_CPU_A38_L TP_CPU_A39_L

TP_CPU_A32_L TP_CPU_A33_L TP_CPU_A34_L TP_CPU_A35_L TP_CPU_A36_L

TP_CPU_APM0_L TP_CPU_APM1_L

CPU_SMI_L

CPU_INTR CPU_NMI

CPU_STPCLK_L

CPU_IGNNE_L

CPU_FERR_L

CPU_A20M_L

FSB_ADSTB_L<1>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<22> FSB_A_L<23>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_REQ_L<2>

FSB_ADSTB_L<0>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

XDP_TCK

XDP_TDI

XDP_TMS

=PP1V05_S0_CPU

FSB_DBSY_L

XDP_BPM_L<1>

=PP1V05_S0_CPU

FSB_TRDY_L

FSB_RS_L<2>

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<5>

FSB_RS_L<1>

FSB_RS_L<0>

65D6

11C5

65D6

11C5

11B3

11C5

11B3

9B7

11B3

9B7

8C7

9B7

8C7

84D6

50C1

84D6

84C6

84D6

84C6

84D6

7D5

8C7

84D6

7D5

84D6

12C4

84C6

59C7

84C6

84D6

12B4

12B6

12B4

12B6

12B4

12B6

12C6

12B4

12C6

12B4

12C6

12D6

12D4

21C2

50D3

26C6

11B3

84C6

12C4

12B4

84C6

12C4

12B4

84D6

84C6

12C4

12A4

12B4

12A4

12C4

12D4

12C4

12D4

11B3

7B6

7D5

12B4

84C6

7B6

84D6

12B4

84C6

84D6

12C4

5D5

59C7

12A4

21C4

12B4

84C6

5D5

34B6

5D5

34C6

34B6

5D5

84C6

5D5

6C7

34D3

6C7

14B6

10B6

50C1

11B4

11B3

7B8

11B5

7B8

7A8

11B3

11B5

5D5

21C4

84C6

5D5

12B4

6C7

6D7

6C7

21C4

21C2

21C4

5D5

7C6

7B5

7B6

7B5

5D5

11B3

7B5

12A4

5D5

11B3

12A4

http://mycomp.su/x/

OUT OUT OUT OUT OUT OUT OUT

OUT

VSS_82 VSS_83 VSS_84 VSS_85

VSS_87

VSS_86

VSS_88 VSS_89 VSS_90

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_97

VSS_96

VSS_100

VSS_98 VSS_99

VSS_102

VSS_101

VSS_105

VSS_103 VSS_104

VSS_106 VSS_107

VSS_110

VSS_109

VSS_108

VSS_111 VSS_112

VSS_115

VSS_114

VSS_113

VSS_116 VSS_117 VSS_118

VSS_120

VSS_119

VSS_123

VSS_121 VSS_122

VSS_124 VSS_125

VSS_128

VSS_126 VSS_127

VSS_129 VSS_130

VSS_133

VSS_131 VSS_132

VSS_134 VSS_135

VSS_138

VSS_136 VSS_137

VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_146

VSS_144 VSS_145

VSS_147 VSS_148

VSS_151

VSS_150

VSS_149

VSS_152 VSS_153

VSS_156

VSS_155

VSS_154

VSS_157 VSS_158 VSS_159

VSS_161

VSS_160

VSS_162

VSS_1 VSS_2 VSS_3

VSS_5

VSS_4

VSS_6 VSS_7 VSS_8

VSS_10

VSS_9

VSS_11 VSS_12

VSS_15

VSS_13 VSS_14

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20

VSS_23

VSS_22

VSS_21

VSS_24 VSS_25

VSS_28

VSS_27

VSS_26

VSS_29 VSS_30

VSS_33

VSS_32

VSS_31

VSS_34 VSS_35

VSS_38

VSS_37

VSS_36

VSS_39 VSS_40 VSS_41 VSS_42 VSS_43

VSS_46

VSS_44 VSS_45

VSS_47 VSS_48

VSS_51

VSS_49 VSS_50

VSS_52 VSS_53

VSS_56

VSS_54 VSS_55

VSS_57 VSS_58 VSS_59 VSS_60 VSS_61

VSS_63

VSS_62

VSS_64 VSS_65 VSS_66

VSS_69

VSS_68

VSS_67

VSS_70 VSS_71

VSS_74

VSS_73

VSS_72

VSS_75 VSS_76

VSS_79

VSS_78

VSS_77

VSS_80 VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_58

VCC_57

VCC_56

VCC_54 VCC_55

VCC_53

VCC_51 VCC_52

VCC_49 VCC_50

VCC_48

VCC_47

VCC_46

VCC_44 VCC_45

VCC_43

VCC_41 VCC_42

VCC_40

VCC_39

VCC_38

VCC_36 VCC_37

VCC_33

VCC_35

VCC_34

VCC_31 VCC_32

VCC_29 VCC_30

VCC_28

VCC_26 VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18 VCC_19

VCC_17

VCC_16

VCC_15

VCC_13 VCC_14

VCC_12

VCC_10 VCC_11

VCC_8 VCC_9

VCC_7

VCC_6

VCC_5

VCC_3 VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82 VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90 VCC_91 VCC_92

VCC_94

VCC_93

VCC_95 VCC_96 VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12 VCCP_13 VCCP_14

VCCP_16

VCCP_15

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTH

VCCSENSE AND VSSSENSE LINES

LAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE

VID FOR CPU POWER SUPPLY IF NO USE, NEED PULL-UP OR PULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

1/16W

1%

402

MF-LF

100

2

1

R0803

84B6

9C2

84B6 59A1

84B6 59B1

100

MF-LF 402

1% 1/16W

2

1

R0802

OMIT

BGA

YONAH

CPU

V22

V5

V2

U24

U21

U6

U3

T26

T23

T4B6

T1

R25

R22

R5

R2

P24

P21

P6

P3

N26

A26

N23

N4

N1

M25

M22

M5

M2

L24

L21

L6

A23

L3

K26

K23

K4

K1

J25

J22

J5

J2

H24

A19

H21

H6

H3

G26

G23

G1

G4

F25

F22

F2

A16

F19

F16

F13

F11

F8

F5

E24

E21

E19

E16

A14

E14

E11

E8

E6

E3

D26

D23

D19

D16

D13

A11

D11

D8

D4

D1

C25

C22

C2

C19

C16

C14

A8

C11

C8

C5

AF24

AF21

AF19

B24

AF16

AF13

AF11

AF8

AF6

AF3

AE26

AE23

AE19

AE16

B21

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

AD13

B19

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

AC11

B16

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

AB8

B13

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

AA5

B11

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

V25

B8

A4

U0700

OMIT

BGA

YONAH

CPU

AE7

AE2

AF2

AE3

AF4

AE5

AF5

AD6

AF7

N21

M21

K21

J21

M6

K6

J6

G21

W21

V21

T6

T21

R6

R21

N6

V6

B26

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

AE17

A20

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

AD12

A18

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

AC7

A17

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

AB9

A15

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

F20

A13

F18

F17

F15

F14

F12

F10

F9

F7

E20

E18

A12

E17

E15

E13

E12

E10

E9

E7

D18

D17

D15

A10

D14

D12

D10

D9

C18

C17

C15

C13

C12

C10

A9

C9

B20

B18

B17

B15

B14

B12

B10

B9

AF20

B7

A7

U0700

CPU 2 OF 2-PWR/GND

051-7150 A.0.0

8 84

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

65D6 11C5

65D1

11B3

65D1

53D7

9B7

53D7

53A6

7D5

53A6

9D7

7B6

65C6

9D7

8B5

7B5

9B7

8D7

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4x 330uF. 20x 22uF 0805

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

Resistors to allow for override of CPU VID Will probably be removed before production

VCCP (CPU I/O) Decoupling

CPU VCORE HF AND BULK DECOUPLING

NOTE: This cap is shared

NCNC

CPU VCORE VID Connections

6.3V

20% CERM

805

22UF

2

1

C0906

6.3V

20% CERM

22UF

805

2

1

C0904

6.3V

20% CERM

22UF

805

2

1

C0916

6.3V

20% CERM

22UF

805

2

1

C0914

6.3V

20% CERM

22UF

805

2

1

C0908

6.3V

20% CERM

22UF

805

2

1

C0903

6.3V

20% CERM

22UF

805

2

1

C0907

6.3V

20% CERM

22UF

805

2

1

C0902

6.3V

20% CERM

805

22UF

2

1

C0901

6.3V

20% CERM

805

22UF

2

1

C0913

6.3V

20% CERM

22UF

805

2

1

C0912

6.3V

20% CERM

22UF

805

2

1

C0911

6.3V

20% CERM

22UF

805

2

1

C0919

6.3V

20% CERM

22UF

805

2

1

C0900

6.3V

20% CERM

22UF

805

2

1

C0910

0.1UF

CERM 402

20% 10V

2

1

C0936

470uF

CRITICAL

D2T

TANT

2.5V

20%

32

1

C0935

6.3V

20% CERM

22UF

805

2

1

C0905

6.3V

20% CERM

22UF

805

2

1

C0909

20% CERM

22UF

6.3V

805

2

1

C0915

6.3V

20% CERM

22UF

805

2

1

C0917

0.1UF

CERM 402

20% 10V

2

1

C0937

0.1UF

CERM 402

20% 10V

2

1

C0938

0.1UF

CERM 402

20% 10V

2

1

C0939

0.1UF

CERM 402

20% 10V

2

1

C0940

0.1UF

CERM 402

20% 10V

2

1

C0941

22UF

CERM

20%

6.3V

805

2

1

C0918

16V

0.01UF

CERM 402

20%

2

1

C0981

X5R

10uF

20%

6.3V

603

2

1

C0980

SM-LF

1/16W

5%

0

5

6

7

8

4

3

2

1

RP0990

SM-LF

1/16W

5%

0

5

6

7

8

4

3

2

1

RP0991

330UF

20%

2.5V POLY D2T

CRITICAL

3 2

1

C0950

CRITICAL

D2T

POLY

2.5V

20%

330UF

3 2

1

C0952

330UF

20%

2.5V POLY D2T

CRITICAL

3 2

1

C0953

CRITICAL

D2T

POLY

2.5V

20%

330UF

3 2

1

C0954

CPU Decoupling & VID

051-7150

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

A.0.0

9 84

IMVP6_VID<6>

IMVP6_VID<5>

IMVP6_VID<4>

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

IMVP6_VID<3>

IMVP6_VID<2>

IMVP6_VID<1>

IMVP6_VID<0>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

65D6 11C5 11B3

65D1

8C7

53D7

7D5

53A6

84B6

7B6

65C6

8D7

59C7

8B7

59C7

8B7

7B5

8B7

8B5

http://mycomp.su/x/

IO

IN

OUT

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE U1001 NEAR THE U1200

CPU ZONE THERMAL SENSOR

ADD GND GUARD TRACE

FOR CPU_THERMD_P AND CPU_THERMD_N

LAYOUT NOTE:

10 MIL SPACING

LAYOUT NOTE:

10 MIL TRACE

LAYER.

CPU_THERMD_N ON SAME

ROUTE CPU_THERMD_P AND

(TO CPU INTERNAL THERMAL DIODE)

(TC0D)

0.001UF

10%

402

CERM

50V

2

1

C1001

0.1UF

X5R

16V

10%

402

2

1

C1002

CRITICAL

TMP401

MSOP

1

4

7

8

5

2 3

6

U1001

MF-LF 402

1/16W

5%

10K

2

1

R1005

1/16W

5%

402

10K

MF-LF

2

1

R1006

499

1% 1/16W MF-LF

402

21

R1001

499

402

MF-LF

1/16W

1%

21

R1002

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

10 84

CPU MISC1-TEMP SENSOR

THRM_ALERT_L

THRM_ALERT

SMB_THRM_CLK

SMB_THRM_DATA

THRM_CPU_DX_N

CPU_THERMD_N

THRM_CPU_DX_P

CPU_THERMD_P

=PP3V3_S0_THRM_SNR

27D1

7C6

65B3

http://mycomp.su/x/

OUT OUT

OUT

IN

IN IN

IO

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

and to provide better feeding of the 1.5V NB rail through its current sense resistor

Note: This connection to 1V5_S0 is to steal this mounting pad to add to the 1.5V S0 shape

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

(DBA#)

(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

MF-LF

22.6

1%

1/16W

402

ITP

21

R1100

ITP

402

1%

22.6

1/16W MF-LF

21

R1102

54.9

1/16W

1%

402

MF-LF

ITP

2

1

R1103

402

X5R

16V

10%

0.1UF

2

1

C1100

1/16W

240

402

MF-LF

5%

2

1

R1104

F-RT-SM

52435-2872

CRITICAL

ITPCONN

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J1101

1/16W 402

54.9

1% MF-LF

2

1

R1101

MF-LF

680

402

5% 1/16W

2

1

R1106

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

CPU ITP700FLEX DEBUG

051-7150 A.0.0

11 84

=PP1V05_S0_CPU

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

=PP3V3_S5_SB_PM

=PP1V05_S0_CPU

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

=PP1V5_S0_ITPMOUNT

65D6

11C5

11B3

9B7

8C7

7D5

84D6

11B3

65D3

7D5

11B3

7B6

12C4

84C6

7C6

26C5

7B6

7C6

84C6

7C6

84C6

26C6

7B5

7D6

7C6

7A8

7B8

7C6

23D1

7B5

7B8

34D3

7C6

7A8

34D3

7C6

84C6

65C6

http://mycomp.su/x/

IO

IO IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IN

IO

IN

IO

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM* HLOCK*

HHIT*

HDSTBP2* HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1* HDSTBN2*

HDSTBN0*

HDINV2* HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10* HD11* HD12* HD13* HD14*

HD5*

HD7* HD8* HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21* HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10* HA11* HA12*

HADSTB1*

HREQ0* HREQ1* HREQ2* HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

402

X5R

16V

10%

0.1uF

2

1

C1211

200

1% 1/16W MF-LF 402

2

1

R1211

100

1% 1/16W MF-LF 402

2

1

R1210

54.9

1% 1/16W MF-LF

402

2

1

R1220

402

MF-LF

1/16W

1%

24.9

2

1

R1221

221

1% 1/16W MF-LF 402

2

1

R1225

1% 1/16W MF-LF 402

100

2

1

R1226

0.1uF

402

X5R

16V

10%

2

1

C1226

402

X5R

16V

10%

0.1uF

2

1

C1236

221

1% 1/16W MF-LF 402

2

1

R1235

54.9

1% 1/16W MF-LF

402

2

1

R1230

1% 1/16W MF-LF 402

100

2

1

R1236

402

MF-LF

1/16W

1%

24.9

2

1

R1231

BGA

NB

945GM

OMIT

W1

U1

Y1

E4

E2

E1

E7

E3

D6

E6

B4

A8

F8

B8

G8

D8

B3

D4

D3

K13

AC5

AA5

T6

K3

AC4

Y5

T7

K4

H8

J9

AB10

U3

W8

J7

C3

A7

K1

K9

G2

AC8

AD4

AD10

AB5

G1

AC6

AD7

AC1

AD9

AD1

AC2

AB3

AC11

AB11

AC9

K2

AB4

AA1

Y8

AA10

AA6

AA2

AA7

AA4

W2

AB8

H3

Y10

W5

Y7

Y3

W3

W4

AA9

AB7

T5

W6

J6

T9

U5

W7

T4

T8

T1

W9

T11

U11

U9

H1

U7

T3

W11

T10

G4

K11

J3

H4

J8

K7

J1

F1

B7

AG1

AG2

C7

F6

C6

J13

C13

B9

E8

F9

G12

F11

G11

E11

C9

D14

C14

H9

A14

C12

B14

B12

F12

G13

E13

A13

A12

C11

A11

D12

F14

J15

H13

J14

D9

G14

J12

H11

U1200

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB CPU Interface

A.0.0

12 84

051-7150

FSB_D_L<17>

FSB_DSTBN_L<2> FSB_DSTBN_L<3>

FSB_DSTBP_L<1> FSB_DSTBP_L<2> FSB_DSTBP_L<3>

FSB_DINV_L<0>

FSB_DSTBN_L<0>

FSB_DINV_L<1> FSB_DINV_L<2>

NB_FSB_VREF

FSB_D_L<1> FSB_D_L<2>

FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<3>

FSB_D_L<0>

FSB_D_L<16>

FSB_TRDY_L

FSB_SLPCPU_L

FSB_RS_L<1>

FSB_RS_L<0>

FSB_HITM_L FSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L<0>

FSB_DSTBN_L<1>

FSB_DINV_L<3>

FSB_DRDY_L

FSB_DPWR_L

FSB_DEFER_L

FSB_DBSY_L

FSB_CPURST_L

FSB_BREQ0_L

FSB_BPRI_L

FSB_BNR_L

FSB_CLK_NB_N

FSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMP NB_FSB_YSCOMP

NB_FSB_XSWING

NB_FSB_XSCOMP

FSB_A_L<13>

FSB_ADS_L FSB_ADSTB_L<0>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<15>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<31>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<21> FSB_A_L<22>

FSB_A_L<17>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<10> FSB_A_L<11> FSB_A_L<12>

FSB_ADSTB_L<1>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3>

FSB_D_L<30>

FSB_REQ_L<4>

FSB_RS_L<2>

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

65D6

34C8

34C6

34B8

84D6

84C6

84D6

84C6

84D6

19D7

7C4

7C3

7B3

7B4

7C3

7B3

7C4

7B4

7C3

7C4

7D6

7C4

7B4

7B3

84D6

7D8

7D6

7D8

7B3

7C3

7B4

7C4

7C8

7D8

7C8

7D8

7C8

7D8

7B4

7D8

12C2

12B7

5D5

7A3

5D5

7B3

34D3

5D5

12A7

12B7

12A7

http://mycomp.su/x/

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF TV_IRTNA

TV_DACB_OUT TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK L_DDC_DATA

EXP_A_COMPI EXP_A_COMPO

EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8

EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11 EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9 EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

L_CLKCTLB

L_BKLTEN L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

OUT

IN

OUT OUT

IN IN

OUT

IN

OUT

IO

IN

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

OUT

IN

OUT

IO IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

OMIT

945GM

NB

BGA

B19

B18

B16

J20

A19

C18

A16

F29

F28

D30

D29

G30

F30

E27

E26

A37

A36

B35

B34

C37

B37

A33

A32

C32

C33

F32

C35

B38

G25

G26

H29

H30

J30

D32

G23

R40

P36

N40

M36

L40

J36

H40

G36

AB40

AA36

Y40

W36

V40

T36

F40

D36

T40

R36

P40

N36

M40

L36

J40

H36

AC40

AB36

AA40

Y36

W40

V36

G40

F36

R38

P34

N38

M34

L38

J34

H38

G34

AB38

AA34

Y38

W34

V38

T34

F38

D34

T38

R34

P38

N34

M38

L34

J38

H34

AC38

AB34

AA38

Y34

W38

V34

G38

F34

D38

D40

H23

B21

A21

J22

B22

C22

C25

C26

D23

E23

U1200

24.9

1% 1/16W MF-LF 402

2

1

R1310

NB PEG / Video Interfaces

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

13 84

A.0.0051-7150

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT

TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0> PEG_D2R_N<1> PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5> PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10> PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14>

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11> PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

LVDS_BKLTEN LVDS_CLKCTLA

LVDS_BKLTCTL

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

65C6

19D5

19C5

67C1

67B1

19D5

79C3

79D3

79C3

79D3

79C3

79D3

79A4

19D3

79A7

67D1

67C1

67B1

67D1

67C1

67B1

67D5

67C5

67B5

67D5

67C5

67B5

79A4

19D3

79A4

19D7

19D3

19D5

http://mycomp.su/x/

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2 RSVD3

RSVD6

RSVD4 RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10 RSVD11 RSVD12 RSVD13

CFG1

CFG0

CFG2 CFG3 CFG4

CFG6

CFG5

CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14

CFG17

CFG16

CFG15

CFG18 CFG19 CFG20

PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ*

NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

NC0 NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0 SM_CK1 SM_CK2

SM_CK0*

SM_CK3

SM_CK1* SM_CK2* SM_CK3*

SM_CKE0 SM_CKE1

SM_CKE3

SM_CS1* SM_CS2* SM_CS3*

SMOCDCOMP0 SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0 SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

IN IN

IN

IN IN

IN

IN IN

IN

OUT

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

IPU

NC NC

IPU IPU IPU IPU

IPU IPU IPU

IPU

IPD

IPU

NC

NC NC

NC

(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)

(H_PLLMON1#)

(H_PLLMON1)

(TV_DCONSEL1)

(TV_DCONSEL0)

(TESTIN#)

(H_PROCHOT#)

(D_PLLMON1)

(H_EDRDY#)

(LB_DATAP3)

(LB_DATAN3)

(LA_DATAP3)

(LA_DATAN3)

IPD

NC

OMIT

945GM

NB

BGA

AK41

AK1

AV9

AT9

AF10

AL20

AU21

AY20

BA12

BA13

AW21

AY21

AW12

AW13

AY29

BA29

AT20

AU20

AY40

AW40

AY7

AW7

AT1

AR1

AW35

AY35

H27

H28

K30

J19

H7

AF11

AG11

F7

F3

R32

D27

D28

A34

A35

A41

J29

T32

AH34

AH33

G6

H26

F25

G28

B41

BA1

BA2

BA3

BA39

BA40

BA41

C1

A3

A39

A4

A40

AW1

AW41

AY1

AY41

B2

C41

D1

K28

AF33 AG33

AG41

AF37

AE41

AC37

AH41

AG37

AF41

AE37

AG39

AF35

AE39

AC35

AH39

AG35

AF39

AE35

C40

D41

A27

A26

H32

G16

D16

D19

E18

F15

E15

F18

J26

J18

K27

J25

H15

G18

H16

C15

K15

G15

D15

E16

K18

K16

U1200

100

5% 1/16W MF-LF

402

21

R1430

1/16W MF-LF

5%

402

10K

2

1

R1441

MF-LF

1/16W

5%

402

10K

2

1

R1440

20% 10V CERM 402

0.1uF

2

1

C1416

20% 10V

CERM

402

0.1uF

2

1

C1415

80.6

MF-LF 402

1% 1/16W

2

1

R1410

80.6

MF-LF 402

1% 1/16W

2

1

R1411

10K

MF-LF

402

5%

1/16W

2

1

R1420

14 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB Misc Interfaces

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

NB_CLK_DREFCLKIN_N NB_CLK_DREFCLKIN_P NB_CLK_DREFSSCLKIN_N NB_CLK_DREFSSCLKIN_P

=PP3V3_S0_NB

NB_TV_DCONSEL1

NB_TV_DCONSEL0

TP_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

NB_RST_IN_L

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_CLK_N<3>

MEM_CLK_N<2>

MEM_CLK_N<1>

MEM_CLK_P<3>

MEM_CLK_N<0>

MEM_CLK_P<2>

MEM_CLK_P<1>

MEM_CLK_P<0>

NB_SB_SYNC_L

SDVO_CTRLDATA

SDVO_CTRLCLK

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>

NB_CFG<19>

NB_CFG<15> NB_CFG<16> NB_CFG<17>

NB_CFG<14>

NB_CFG<10>

NB_CFG<9>

NB_CFG<7>

NB_CFG<5> NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

NB_BSEL<2>

NB_BSEL<0> NB_BSEL<1>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>

MEM_ODT<1>

MEM_CS_L<3>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CKE<2>

=PP1V8_S3_MEM_NB

MEM_RCOMP_L MEM_RCOMP

MEM_VREF_NB_0 MEM_VREF_NB_1

TP_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

65B3

20B4

20A4

84C6

20A4

50C1

65B6

50D5

34B4

19C7

59C8

19C7

30C6

30D6

59C7

21C2

30D6

30C6

30D6

19D7

49B7

33B4

34B2

34B4

14C7

19D3

23C3

14D6

20B5

6C6

6D6

26C1

22D2

34C4

29B6

28B3

29C3

28C3

28C6

29D3

29A3

28A3

29D3

28D3

29A3

28A3

28D3

22A6

19D3

26B5

7C6

23C5

20A5

20B5

6D6

20C5

6D6

20B7

20C7

6D6

34B7

34C7

34B7

28B3

6C6

29B3

28B6

29B6

29B3

28B6

29C6

16B6

32B3

19D3

http://mycomp.su/x/

SA_DQ1

SA_DQ0

SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0 SA_DM1 SA_DM2 SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA1

SA_MA0

SA_MA2 SA_MA3

SA_MA5

SA_MA4

SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

SB_DQ1

SB_DQ0

SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0 SB_DM1 SB_DM2 SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6 SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

SB_MA1

SB_MA0

SB_MA2 SB_MA3

SB_MA5

SB_MA4

SB_MA6 SB_MA7

SB_MA9

SB_MA8

SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO

OUT

IO

IO IO

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

OMIT

NB

945GM

BGA

AY14

AK24

AK23

AW14

AT16

AW17

AU17

AV17

AU16

BA17

BA16

AW16

AV12

AV20

AT17

AU13

AU14

AY16

AH5

AG5

AN3

AP3

AL8

AN8

AM12

AN12

AM21

AM22

AN27

AN28

AU33

AT33

AK32

AK33

AP33

AN35

AH31

AF8

AF4

AH6

AG9

AJ32

AF6

AG4

AF9

AG7

AL2

AN1

AT3

AV2

AN2

AP1

AK35

AW2

AY2

AL5

AT5

AN9

AP9

AK7

AK8

AN7

AK9

AJ36

AL12

AL14

AT12

AT13

AP12

AP13

AR14

AR12

AT21

AP20

AM33

AP24

AL23

AN20

AP21

AL22

AP23

AP26

AM24

AL28

AK28

AM31

AN24

AM26

AL27

AK26

AN33

AM34

AM36

AN38

AP31

AR31

AJ34

AJ35

AH4

AR3

AL9

AM14

AN22

AL26

AM35

AJ33

AY13

BA20

AV14

AU12

U1200

OMIT

NB

945GM

BGA

AR27

AK18

AK16

AU23

AW27

AV27

AV28

AU27

AT28

AT27

AR28

AY24

AR23

AY27

BA27

AV24

AW24

AY23

AP5

AN5

AT7

AR7

AT10

AR10

AP16

AR16

AP29

AR29

AT35

AU35

AU39

AT39

AM40

AM39

AV41

AT40

AP41

AJ3

AJ5

AK5

AT4

AN41

AK3

AK4

AR5

AV4

AY5

AW5

AY9

AY10

AW4

BA4

AK38

AW10

BA10

AJ8

AK10

AH11

AK13

AN10

AJ9

AH10

AJ11

AJ38

AL15

AP15

AM16

AN17

AN14

AP14

AL19

AM19

AW29

AV29

AR41

AW31

AU31

AU29

AT31

BA33

AY33

AP34

AP35

AU36

BA36

AP39

AP36

AR36

AV36

BA38

AY38

AW38

AR40

AP38

AV38

AU38

AJ37

AK39

AN4

BA5

AH8

AL17

BA31

AT36

AR38

AK36

AR24

AY28

AV23

AT24

U1200

15 84

A.0.0051-7150

NB DDR2 Interfaces

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>

MEM_B_CAS_L MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2> MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4>

MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>

MEM_A_CAS_L MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

30A6

30B6

30A6

30B6

30C6

30B6

29D6

29D3

29D6

29D3

29D6

29D3

29D6

29D3

29D6

29D3

29D6

29C3

29C6

29C3

29C6

29C3

29C6

29C3

29B3

29B6

29B3

29B6

29A6

29B3

29A3

29B3

29A3

29A6

29A3

29A6

29A3

29A6

29A3

29A6

29A3

29B3

29B6

29C6

29B6

29D3

29C3

29C6

29A6

29B3

29A3

29A6

29D6

29C6

29D6

29C3

29A3

29B6

29A3

29A6

29C3

29C6

29B6

29B3

29A3

29A6

29B6

29B3

29B6

29B3

29C3

29C6

29B6

29C3

29C6

29B3

29B6

29D6

28D3

28D6

28D3

28D6

28D3

28D6

28D3

28C6

28C3

28C6

28C3

28C6

28C3

28C6

28C3

28C6

28C3

28B3

28B6

28B3

28B6

28B3

28B6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28B3

28A6

28B6

28A6

28A3

28B3

28B6

28C6

28B6

28D3

28C3

28C6

28A3

28B3

28A6

28D6

28C6

28D6

28C3

28A6

28B6

28A3

28C3

28C6

28B6

28A6

28A3

28B3

28B6

28B3

28B6

28B3

28C3

28C6

28B6

28C3

28C6

28B3

28B6

28D6

http://mycomp.su/x/

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47 VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37 VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34 VCCAUX_NCTF35

VCCAUX_NCTF32 VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27 VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24 VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42 VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19 VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14 VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7 VSS_NCTF8

VSS_NCTF5 VSS_NCTF6

VSS_NCTF4

VSS_NCTF2 VSS_NCTF3

VSS_NCTF0 VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61 VCC_NCTF62 VCC_NCTF63

VCC_NCTF60

VCC_NCTF57 VCC_NCTF58 VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53 VCC_NCTF54

VCC_NCTF52

VCC_NCTF50 VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46 VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38 VCC_NCTF39

VCC_NCTF36 VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF31 VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18 VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13 VCC_NCTF14

VCC_NCTF11 VCC_NCTF12

VCC_NCTF10

VCC_NCTF8 VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0 VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.8V Max Current Speed 1 Channel 2 Channel 400MTs 1300mA 2400mA 533MTs 1500mA 2800mA 667MTs 1700mA 3200mA

1.05V, Internal Graphics: 3500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, External Graphics: 1500mA Max

1.05V or 1.5V

Place in cavity

Layout Note:

Layout Note: Place near pin BA15

Place near pin BA23

Layout Note:

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

OMIT

945GM

NB

BGA

AT6

AV6

AW6

AY6

BA6

AP8

AR8

AT8

AV8

AW8

AT34

AY8

BA8

AK11

AG12

AH12

AJ12

AK12

AH13

AJ13

AJ14

AU34

AJ15

AR15

AT15

AU15

AV15

AW15

AY15

BA15

AH16

AJ16

AV34

AH17

AJ17

AJ18

AJ19

AK19

AP19

AR19

AT19

AU19

AV19

AW34

AW19

AY19

BA19

AK20

AK21

AJ22

AK22

AP22

AR22

AT22

AY34

AU22

AV22

AW22

AY22

BA22

AJ23

BA23

AH24

AJ24

AH25

BA34

AJ25

AH26

AJ26

AR26

AT26

AU26

AV26

AW26

AY26

BA26

AU40

AH27

AJ27

AH28

AJ28

AH29

AJ29

AK29

AL29

AM29

AM30

AM41

AN30

AP30

AR30

AT30

AU30

AV30

AW30

AY30

BA30

AJ1

AV1

AJ6

AK6

AL6

AN6

AP6

AR6

AR34

AT41

AU41

N19

Y19

AA19

AB19

L20

M20

N20

P20

W20

Y20

V32

AB20

AC20

L21

M21

N21

W21

AA21

AC21

L22

M22

W32

N22

P22

W22

Y22

AB22

AC22

L23

M23

N23

P23

Y32

Y23

AA23

AB23

M24

N24

P24

L25

M25

N25

L26

AA32

N26

P26

L27

M27

N27

P27

L28

M28

N28

P28

J33

R28

T28

U28

V28

Y28

AA28

AB28

L29

M29

P29

L33

R29

U29

V29

W29

Y29

AA29

L30

M30

N30

P30

N33

R30

T30

U30

V30

W30

Y30

AA30

M31

N31

P31

P33

R31

T31

V31

W31

AA31

J32

L32

M32

L16

N32

M16

N16

M17

N17

P17

L18

M18

N18

L19

M19

P32

W33

AA33

U1200

10%

0.47UF

402

6.3V CERM-X5R

2

1

C1610

10uF

6.3V X5R

20%

603

2

1

C1621

603

20%

X5R

6.3V

10uF

2

1

C1620

OMIT

BGA

NB

945GM

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

U17

Y17

AC17

AE26

AE27

AF23

AG23

AF24

AG24

R15

T15

U15

V15

W15

Y15

AA15

AB15

AF25

AC15

AD15

AE15

AF15

AG15

R16

T16

U16

V16

W16

AG25

Y16

AA16

AB16

AC16

AD16

AE16

AF16

AG16

R17

T17

AF26

V17

W17

AA17

AB17

AD17

AE17

AF17

AG17

R18

AF18

AG26

AG18

R19

AF19

AG19

AF20

AG20

AF21

AG21

AF22

AG22

AF27

AG27

R27

T27

T18

U18

V18

U27

W18

Y18

AA18

AB18

AC18

AD18

T19

U19

V19

AD19

V27

R20

T20

U20

V20

AD20

R21

T21

U21

V21

AD21

W27

R22

T22

U22

V22

AD22

R23

T23

U23

V23

AD23

Y27

R24

T24

U24

V24

W24

Y24

AA24

AB24

AC24

AD24

AA27

R25

T25

U25

V25

W25

Y25

AA25

AB25

AC25

AD25

AB27

R26

T26

U26

V26

W26

Y26

AA26

AB26

AC26

AD26

AC27

AD27

U1200

CERM-X5R

6.3V

402

0.47UF

10%

2

1

C1611

10%

0.47UF

402

6.3V

CERM-X5R

2

1

C1612

10%

0.47UF

402

6.3V CERM-X5R

2

1

C1613

10%

0.47UF

402

6.3V

CERM-X5R

2

1

C1614

10%

0.47UF

402

6.3V CERM-X5R

2

1

C1615

16 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB Power 1

=PP1V5_S0_NB_VCCAUX

=PPVCORE_S0_NB

NB_VCCSM_LF4 NB_VCCSM_LF5

NB_VCCSM_LF2 NB_VCCSM_LF1

=PP1V8_S3_MEM_NB

65D6

65B6

19D7

19D2

65B6

19C4

19C8

19D7

17B6

16C8

16D3

14C2

http://mycomp.su/x/

VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25

VTT27

VTT26

VTT28 VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35 VTT36 VTT37

VTT39

VTT38

VTT40 VTT41 VTT42 VTT43 VTT44 VTT45

VTT48

VTT46 VTT47

VTT49 VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58 VTT59 VTT60 VTT61 VTT62

VTT64

VTT63

VTT65 VTT66 VTT67

VTT69

VTT68

VTT70 VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2

VCC3G0 VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL VCCA_3GBG VSSA_3GBG

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG VSSA_TVBG

VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACA0 VCCA_TVDACA1

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0 VCCD_LVDS1

VCCD_TVDAC

VCC_HV1 VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14 VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23 VCCAUX24

VCCAUX22

VCCAUX25 VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30 VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34 VCCAUX35 VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39 VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1900mA Max

40mA Max

See VCCSYNC

150mA Max

120mA Max

45mA Max

50mA Max

10mA Max

24mA Max

20mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

60mA Max

2mA Max

800mA Max

1500mA Max VCC3G/3GPLL

OMIT

BGA

NB

945GM

L14

M14

M1

N1

P1

R1

AB1

D2

M2

N14

P2

R2

M3

N3

P3

R3

M4

N4

P4

M5

P14

N5

P5

R5

A6

M6

P6

R6

M7

N7

P7

R14

M8

N8

P8

R8

M9

N9

P9

M10

N10

P10

T14

R10

M11

N11

P11

R11

L12

M12

N12

P12

R12

V14

T12

U12

V12

W12

Y12

AA12

AB12

L13

M13

N13

W14

R13

T13

U13

V13

W13

Y13

AA13

AB13

AC13

AD13

AB14

AC14

G20

B39

G21

H41

H22

D21

H19

C28

B28

A28

AH2

AH1

AF30

AG30

AH30

AJ30

AK30

AD12

AL30

AE12

AF12

AE13

AF13

Y14

AE14

AF14

AG14

AH14

P15

AC31

AH15

P16

P19

AH19

AH20

AJ20

AH21

AJ21

AH22

AE28

AE31

AF28

AG28

AC29

AD29

AE29

AF29

AG29

AC30

AD30

AE30

AF31

AK31

F20

E20

D20

C20

F19

E19

H20

AF2

A38

AF1

C39

B26

E21

F21

AC33

G41

A30

B30

C30

B25

B23

A23

L41

N41

R41

V41

Y41

AB41

AJ41

U1200

10%

0.47UF

6.3V

CERM-X5R

402

2

1

C1711

20%

0.22uF

6.3V

402

X5R

2

1

C1712

10%

0.47UF

CERM-X5R

6.3V

402

2

1

C1713

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Power 2

051-7150 A.0.0

8417

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDS GND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLA PP1V5_S0_NB_VCCA_DPLLB

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG

=PP2V5_S0_NB_VCCA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

NB_VTTLF_CAP1

NB_VTTLF_CAP2

NB_VTTLF_CAP3

=PP1V05_S0_NB_VTT

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

65B6 19D7

65B3

65A6

65D6

19C4

19C7

65B6

65A6

34B2

19D7

65B6

19D1

16D1

19D1

19C6

19D7

19D1

19C1

19B6

19A4

19A3

19B6

19A6

19D1

19A3

19C5

19B3

19A6

19D1

19C8

19D1

19A5

http://mycomp.su/x/

VSS_1

VSS_0

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7

VSS_9

VSS_8

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17

VSS_19

VSS_18

VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26

VSS_28

VSS_27

VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

VSS_49

VSS_48

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

VSS_73

VSS_72

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79

VSS_82

VSS_80 VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92 VSS_93 VSS_94

VSS_96

VSS_95

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125

VSS_127

VSS_126

VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135

VSS_137

VSS_136

VSS_138 VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156

VSS_158

VSS_157

VSS_159 VSS_160 VSS_161 VSS_162

VSS_164

VSS_163

VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170

VSS_172

VSS_171

VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269 VSS_270

VSS_268

VSS_266 VSS_267

VSS_265

VSS_264

VSS_263

VSS_261 VSS_262

VSS_260

VSS_259

VSS_258

VSS_256 VSS_257

VSS_255

VSS_254

VSS_253

VSS_251 VSS_252

VSS_250

VSS_248 VSS_249

VSS_247

VSS_246

VSS_245

VSS_243 VSS_244

VSS_242

VSS_241

VSS_240

VSS_238 VSS_239

VSS_237

VSS_236

VSS_235

VSS_233 VSS_234

VSS_232

VSS_231

VSS_230

VSS_228 VSS_229

VSS_227

VSS_225 VSS_226

VSS_224

VSS_223

VSS_222

VSS_220 VSS_221

VSS_219

VSS_218

VSS_217

VSS_215 VSS_216

VSS_214

VSS_213

VSS_212

VSS_210 VSS_211

VSS_209

VSS_207 VSS_208

VSS_205 VSS_206

VSS_204

VSS_202 VSS_203

VSS_201

VSS_200

VSS_199

VSS_197 VSS_198

VSS_196

VSS_195

VSS_194

VSS_192 VSS_193

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_186

VSS_184 VSS_185

VSS_183

VSS_182

VSS_180 VSS_181

VSS_273 VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282 VSS_283 VSS_284

VSS_286

VSS_285

VSS_287 VSS_288 VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301 VSS_302

VSS_300

VSS_304

VSS_303

VSS_305 VSS_306 VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312 VSS_313 VSS_314 VSS_315

VSS_317

VSS_316

VSS_318 VSS_319 VSS_320

VSS_322

VSS_321

VSS_323 VSS_324 VSS_325

VSS_327

VSS_326

VSS_328 VSS_329 VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338 VSS_339 VSS_340

VSS_342 VSS_343

VSS_341

VSS_345

VSS_344

VSS_346 VSS_347 VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

OMIT

BGA

945GM

NB

AF34

AG34

AK34

AN34

D35

F35

G35

H35

J35

L35

AP40

M35

N35

P35

R35

T35

V35

W35

Y35

AA35

AB35

AV40

AH35

AR35

AV35

BA35

B36

C36

AC36

AE36

AF36

AG36

F41

AH36

AN36

AW36

AY36

D37

F37

G37

H37

J37

L37

J41

M37

N37

P37

R37

T37

V37

W37

Y37

AA37

AB37

M41

AH37

AK37

C38

AE38

AF38

AG38

AH38

AM38

AT38

D39

P41

F39

G39

H39

J39

L39

M39

N39

P39

R39

T39

T41

V39

W39

Y39

AA39

AB39

AC39

AJ39

AN39

AR39

AV39

W41

AW39

AY39

AW23

AL24

AU24

BA24

A25

D25

E25

H25

K25

P25

B40

AK25

D26

F26

K26

M26

AN26

B27

C27

F27

G27

AE40

J27

AK27

AM27

AP27

E28

J28

W28

AC28

AD28

AM28

AF40

AP28

AU28

AW28

BA28

A29

B29

C29

E29

G29

K29

AG40

N29

T29

AB29

AN29

AT29

E30

AB30

Y31

AB31

AG31

AH40

AJ31

AN31

AV31

AY31

B32

G32

AB32

AC32

AE32

AF32

AJ40

AG32

AH32

B33

D33

F33

G33

H33

M33

R33

T33

AK40

V33

Y33

AB33

AE33

AR33

AV33

AW33

C34

AC34

AE34

AN40

AA41

AC41

U1200

OMIT

BGA

945GM

NB

AL1

C2

F2

H2

J2

N2

T2

U2

Y2

AB2

AD2

AJ2

AK2

AP2

AR2

AT2

G3

AA3

AC3

AD3

AF3

AG3

AH3

AL3

AV3

AW3

AY3

C4

F4

J4

R4

U4

Y4

AJ4

AL4

AP4

AR4

AY4

AD5

AF5

AV5

B6

H6

K6

N6

U6

Y6

AB6

AD6

AG6

D7

G7

R7

AC7

AF7

AH7

AJ7

AL7

AP7

AV7

BA7

C8

K8

U8

AA8

AD8

AG8

A9

E9

G9

R9

Y9

AB9

AH9

AR9

AW9

BA9

U10

W10

AC10

AG10

AJ10

AL10

AP10

AV10

B11

D11

J11

Y11

AA11

AD11

E12

H12

K12

AC12

AY12

B13

D13

F13

P13

AG13

AL13

AM13

AN13

AR13

AV13

E14

H14

K14

U14

AA14

AD14

AK14

AT14

BA14

A15

B15

L15

M15

N15

AK15

AM15

AN15

C16

F16

J16

AL16

AN16

AV16

AK17

AM17

AP17

AR17

AY17

A18

D18

H18

P18

AH18

C19

G19

K19

W19

AC19

AN19

A20

B20

K20

AA20

AM20

AR20

AW20

C21

H21

J21

K21

P21

Y21

AB21

AL21

AN21

AR21

AV21

BA21

A22

D22

E22

F22

G22

K22

AA22

C23

F23

J23

K23

W23

AC23

AH23

AM23

AN23

AT23

U1200

18 84

A.0.0051-7150

NB Grounds

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

http://mycomp.su/x/

IN

IN IN

NR/FB

IN

EN

OUT

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

800mA Max

These are the power signals that leave the NB "block"

Power Interface

40mA Max

MCH VCC_HV BYPASS (MCH HV BUFFER 3.3V PWR)

Layout Note: Route to caps, then GND

(MCH MEMORY PLL 1.5V PWR)

1500mA Max

1500mA Max 10mA Max?

GMCH CORE PWR 1.05V BYPASS

1900mA Max

3200mA Max

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

Rail Totals:

2310mA Max?

?mA Max

?mA Max 100mA Max

800mA Max

3674mA Max

40mA Max

40mA Max?

2mA Max

150mA Max

3200mA Max

1500mA Max

24mA Max

70mA Max

?mA Max

Layout Note: Route to caps, then GND

10MA MAX

(MCH LVDS ANALOG 2.5V PWR)

MCH VCCA_LVDS BYPASS

132mA Max

?mA Max

60mA Max

GMCH VCC3G FILTER (PCI-E/DMI ANALOG 1.5V PWR)

1500mA Max

(3GIO PLL 1.5V PWR)

GMCH VCCA_3GPLL FILTER

Layout Note:

be close to MCH

10uF caps should

on opposite side.

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

GMCH VCCAUX FILTER

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

2mA Max

MCH VCCA_3GBG BYPASS

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Layout Note: Place L and C close to MCH

Place on the edge

Layout Note:

(SHARE C0940 470UF)

45mA Max

GMCH VCCA_HPLL FILTER (HOST PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

MCH VTT BYPASS (MCH FSB 1.05V PWR)

Layout Note: Place in cavity

100mA Max

(MCH LVDS DIGITAL 1.5V PWR)

MCH VCCD_LVDS BYPASS

20MA MAX

GMCH VCCA_DPLLA FILTER

50MA MAX

(CRT/TVOUT PLL 1.5V PWR)

GMCH VCCA_DPLLB FILTER (LVDS PLL 1.5V PWR)

1500mA Max

60MA MAX

(MCH LVDS TRANSMITTER 2.5V PWR)

MCH VCC_TXLVDS BYPASS

0.22uF

X5R

6.3V

20%

402

2

1

C1907

X5R 603

20%

6.3V

10uF

2

1

C1972

0.22uF

X5R 402

20%

6.3V

2

1

C1967

CERM1

20%

2.2uF

603

6.3V

2

1

C1966

4.7uF

CERM 603

20%

6.3V

2

1

C1965

CRITICAL

470uF

D2T

TANT

2.5V

20%

3 2

1

C1900

91nH

1210

21

L1970

CERM

10V

20%

402

0.1uF

2

1

C1916

6.3V

20%

402

X5R

0.22uF

2

1

C1906

10V

20%

402

CERM

0.1uF

2

1

C1991

CERM

603

20%

6.3V

4.7UF

2

1

C1990

0.1uF

CERM 402

20% 10V

2

1

C1993

6.3V

20%

603

X5R

10uF

2

1

C1992

10V

20%

402

CERM

0.1uF

2

1

C1995

0.01UF

402

CERM

16V

20%

2

1

C1994

603

X5R

6.3V

10uF

20%

2

1

C1952

1.5K

1% 1/16W MF-LF 402

2

1

R1990

CRITICAL

TPS73115

SOT23-5

5 4

1

2

3

U1900

6.3V

10%

1uF

CERM

402

2

1

C1950

16V

10%

0.01uF

CERM

402

2

1

C1951

0

5% 1/16W MF-LF

402

21

R1954

NO STUFF

0

5% 1/16W MF-LF

402

21

R1953

CERM

NO STUFF

20% 10V

402

0.1uF

2

1

C1953

0.1uF

CERM 402

20% 10V

2

1

C1915

20% 10V CERM 402

0.1uF

2

1

C1954

POLY

2.5V

20%

220UF

CASE-B2

2

1

C1970

10uF

X5R 603

6.3V

20%

2

1

C1914

6.3V

20% X5R

0.22uF

402

2

1

C1905

0.1uF

CERM 402

10V

20%

2

1

C1935

0603

FERR-120-OHM-0.2A

21

L1934

10V

0.1uF

20% CERM

402

2

1

C1937

402

6.3V

1uF

CERM

10%

2

1

C1904

FERR-120-OHM-0.2A

0603

21

L1936

6.3V

20%

805

CERM

22UF

2

1

C1934

6.3V

20%

805

CERM

22UF

2

1

C1936

6.3V X5R

20%

10uF

603

2

1

C1903

X5R

6.3V

20%

603

10uF

2

1

C1902

CERM

402

20% 10V

0.1uF

2

1

C1918

10V

20%

402

CERM

0.1uF

2

1

C1976

1.0UH-220MA-0.12-OHM

0805

21

L1975

6.3V

20%

603

X5R

10uF

2

1

C1975

MF-LF

402

0.51

1/16W

1%

21

R1975

10uF

X5R 603

20%

6.3V

2

1

C1971

NB (GM) Decoupling

SYNC_DATE=07/25/2006

SYNC_MASTER=M59_MG

051-7150 A.0.0

8419

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3G

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_NB_DPLL

TPS73115_NR

PP1V5_S0_NB_VCCA_DPLLB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=1.5V

=PP2V5_S0_NB_VCC_TXLVDS

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_DPLL

PP1V5_S0_NB_VCCA_DPLLA

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

=PP2V5_S0_NB_VCCA_3GBG

=PP1V5_S0_NB_VCCD_LVDS

VOLTAGE=1.5V

PP1V5_S0_NB_3GPLL_F

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_VCCAUX

=PP1V05_S0_FSB_NB

=PP2V5_S0_NB_VCCA_LVDS

GND_NB_VSSA_LVDS

LVDS_VREFL

LVDS_VREFH

LVDS_IBG

CRT_HSYNC_R

CRT_DDC_DATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA

SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK

SDVO_CTRLCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D27 TP_NB_XOR_LVDS_D27

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_A34

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A35 TP_NB_XOR_LVDS_A35

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB

LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA

LVDS_CLKCTLA

TV_DACA_OUT TV_DACB_OUT

=PP1V5_S0_NB_TVDAC

=PP1V05_S0_NB_CRT

=PP1V5_S0_NB

=PP1V05_S0_NB_VTT

=PP3V3_S0_NB =PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

MAKE_BASE=TRUE

TP_CRT_DDC_CLK

CRT_DDC_CLK

CRT_IREF

CRT_BLUE_L

CRT_GREEN_L

CRT_RED_L

CRT_BLUE

CRT_GREEN

CRT_RED

=PP1V05_S0_NB_CRT

TV_IREF

TV_IRTNC

TV_IRTNB

CRT_VSYNC_R

=PP1V5_S0_NB_PCIE

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

GND_NB_VSSA_CRTDAC

PP2V5_S0_NB_VCCA_CRTDAC

=PP2V5_S0_NB_VCCSYNC

PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QTVDAC

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVBG

GND_NB_VSSA_TVBG

=PP1V5_S0_NB_3G

TV_IRTNA

TV_DACC_OUT

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL

GND_NB_VSSA_3GBG

=PP3V3_S0_NB_VCC_HV

=PPVCORE_S0_NB

=PP2V5_S0_NB_VCCA_3GBG

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

=PP1V8_S3_MEM_NB

=PP1V5_S0_NB_3GPLL

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_PLL

=PP1V05_S0_NB_VTT

65D6 34C8 34C6

65B3

65D6

65B6

34B8

20B4

19D7

65B6

19D7

19D2

65A6

65A6 19D7

12C2

65B6

65C8

65D6

20A4

65B3

19C8

65B6

19C4

65B3

19D2

65A6

65B6

19C8

65B6

65D6

19D7

34B2

19D7

65B6

65C6

17B6

12B7

65A6

19D7

65D6

65C6

19C8

14D6

19C6

65B6

65D6

65C6

16D3

19D7

65C6

17B6

65C6

65B6

19C7

16D3

19C5

19A6

19D1

16B6

65C6

16D3

19D6

65B6

19D7

17D6

65A6 17C6 17D6

17C6

17D6

17C6

17D6

19D7

16D1

12A7

17C6

13D5

13B5

14B6

14C6

13D5

13C5

19D2

19D6

60A7

17D3

14C7

17C6

13B5

19D7

13C5

13B5

13D2

16C8

19D6

17D6

17C6

17B6

17C6

19B5

13C5

16D1

19D7

17D6

17C6

16C8

17D6

14C2

19B5

16C8

19D2

19B8

17D3

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PCIe Backward Interop. Mode

VCC Select

Reversal

DMI Lane

High = Reversed

Low = Normal

High = 1.5V

Low = 1.05V

Internal pull-down

945 External Design Spec says reserved

High = Both active

Low = Only SDVO or PCIe x1

ODT

FSB Dynamic

RESERVED

Low = Disabled

High = Enabled

RESERVED

Internal pull-up

RESERVED

00 = Partial Clock Gating Disable 01 = XOR Mode Enabled 10 = All-Z Mode Enabled 11 = Normal Operation

Internal pull-up

Low = Reversed

RESERVED

CPU Strap

RESERVED

PCIE Graphics

High = Normal

Low = RESERVED

High = DMIx4

Low = DMIx2

NB_CFG<20>

NB_CFG<19>

NB_CFG<9>

NB_CFG<8>

NB_CFG<18>

NB_CFG<17>

NB_CFG<6>

NB_CFG<16>

NB_CFG<15>

NB_CFG<5>

NB_CFG<14>

NB_CFG<13:12>

RESERVED

NB_CFG<3>

NB_CFG<4>

Lane Reversal

PROBABLY NOT NEEDED

DMI x2 Select

Internal pull-up

RESERVED

NB_CFG<7>

High = Mobile CPU

NB_CFG<10>

NB_CFG<11>

RESERVED

Internal pull-up

Internal pull-ups

402

5%

2.2K

1/16W MF-LF

NBCFG_DMI_X2

2

1

R2075

5%

2.2K

1/16W MF-LF 402

NBCFG_DYN_ODT_DISABLE

2

1

R2085

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

2

1

R2058

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

2

1

R2059

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

2

1

R2060

NO STUFF

2.2K

5% 1/16W MF-LF 402

2

1

R2077

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

2

1

R2079

20 84

A.0.0051-7150

NB Config Straps

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB_CFG<7>

NB_CFG<9>

NB_CFG<5>

NB_CFG<16>

NB_CFG<20>

NB_CFG<19>

NB_CFG<18>

=PP3V3_S0_NB

65B3

20B4

20A4

19C7

14D6

14C6

14B6

14C6

14C7

http://mycomp.su/x/

IO

IN

OUT

IN

OUT

IN

IO

IO IO

IO

IN

IO

DDACK*

SATARBIASN SATARBIASP

SATA_CLKN SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0 LAN_TXD1

LAN_RXD1 LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0 LAD1

EE_DOUT EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY DDREQ

DD0 DD1

DD3

DD2

DD5

DD4

DD6 DD7 DD8

DD11

DD9

DD10

DD12 DD13 DD14 DD15

DA0 DA1 DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN IN

IN

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

(INT PU)

(WEAK INT PD)

NOTE: R2108=56 IN CV.

BOM CONSOLIDATION

CHANGED TO 54.9 FOR

NOTE: R2110=56 IN CV.

NOTE: PULLED UP PER INTEL

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

INTEL CONFIRMS OK TO LEAVE PINS AS NC

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTO RESET STATE TO SAVE PWR.

NOTE: POR IS SMC WILL PUT LAN INT’F

NOTE: KEYBOARD CONTROLLER RESET CPU

NOTE: RISING-EDGE TRIGGERED AT CPU

BOM CONSOLIDATION

< 2 IN OF SB

LAYOUT NOTE: R2107 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2108 TO BE < 2 IN OF R2107 W/O STUB

(DSTROBE)

20K PD

(STOP)

(HSTROBE)

NOTE: DD<7> HAS INTERNAL 11.5K PD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

INTERNAL 20K PD ONLY ENABLED IN S3COLD

INTERNAL 20K PD

NONE

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

AC ’07

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

ACZ_SDIN[0-2]

ACZ_RST#

ACZ_BIT_CLK

ACZ_SYNC

ACZ_SDOUT

INTEL HIGH DEFINITION AUDIO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

NOTE: DDREQ HAS INTERNAL 11.5K PD

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

(WEAK INT PU)

402

5%

0

MF-LF 1/16W

NOSTUFF

21

R2100

MF-LF

1/16W

5%

2.2K

402

NOSTUFF

21

R2101

1/16W

402

39

5%

MF-LF

21

R2195

39

21

R2198

39

21

R2197

39

21

R2196

MF-LF

1/16W

5%

10K

402

2

1

R2199

OMIT

ICH7-M

SB

BGA

AH25

AF24

AF26

AH22

AF23

AG10

AH10

AF18

AE1

AF1

AH6

AG6

AE7

AF7

AH2

AG2

AE3

AF3

AB2

AB1

AA3

AG23

AH24

AB3

AA5

AC3

V7

V6

U7

T5

V4

U5

U3

V3

Y6

AC4

AB5

AA6

AG16

W4

Y5

AF25

AG21 AF22

AG22

AH16

AG24

AG26

Y1 Y2 W3

W1

AH15

AF15

AE15

AF16

AF12

AE12

AC12

AD12

AC13

AD14

AF13

AG13

AC15

AH14

AH13

AF14

AC14

AB13

AE14

AB15

AD16

AE16

AF17

AE17

AH17

AG27

R6

T4

T1

T3

T2

R5

U1

AH28

AE22

U2100

MF-LF

1/16W

5%

10K

402

2

1

R2194

MF-LF

1/16W

1%

402

332K

2

1

R2105

402

1%

1/16W

MF-LF

24.9

21

R2107

54.9

1%

1/16W

MF-LF

402

2

1

R2108

1%

54.9

402

1/16W

MF-LF

21

R2110

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

SB: 1 OF 4

051-7150

8421

A.0.0

IDE_PDD<3>

IDE_PDD<2>

TP_SB_XOR_V3

TP_SB_XOR_W3

TP_SB_XOR_T5

TP_SB_XOR_V4

TP_SB_XOR_U5

TP_SB_XOR_U3

PP3V3_S5_SB_RTC

ACZ_RST_L

ACZ_BITCLK

SB_RTC_RST_L

SB_RTC_X2

LPC_FRAME_L

TP_SB_GPIO23

TP_SB_DRQ0_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

=PP3V3_S0_SB_GPIO

IDE_PDD<6>

ACZ_SDATAOUT

PM_THRMTRIP_L

=PP1V05_S0_SB_CPU_IO

SMC_RCIN_L

ACZ_SYNC

IDE_PDCS1_L IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<13>

IDE_PDD<12>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<11>

IDE_PDD<8>

IDE_PDD<7>

IDE_PDD<4> IDE_PDD<5>

IDE_PDD<1>

IDE_PDD<0>

IDE_PDDREQ

IDE_PDIORDY

IDE_PDIOW_L

IDE_IRQ14

IDE_PDIOR_L

SB_ACZ_RST_L

TP_CPU_CPUSLP_L

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

FWH_INIT_L CPU_INIT_L

CPU_INTR

CPU_SMI_L

CPU_NMI

CPU_STPCLK_L

CPU_THERMTRIP_R

SB_RTC_X1

SB_SM_INTRUDER_L

SB_ACZ_BITCLK SB_ACZ_SYNC

ACZ_SDATAIN<0>

TP_SB_ACZ_SDIN2

TP_SB_ACZ_SDIN1

SB_ACZ_SDATAOUT

TP_SB_SATALED_L

SATA_A_D2R_N SATA_A_D2R_P SATA_A_R2D_C_N SATA_A_R2D_C_P

SATA_C_D2R_N

SATA_C_R2D_C_N SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

IDE_PDDACK_L

SATA_C_D2R_P

CPU_RCIN_L

SB_A20GATE

CPU_FERR_L

=PP1V05_S0_SB_CPU_IO

SB_INTVRMEN

TP_SB_XOR_W1 TP_SB_XOR_Y1 TP_SB_XOR_Y2

TP_SB_XOR_U7 TP_SB_XOR_V6 TP_SB_XOR_V7

58C6

65B3

65B3 65D6

65D6

26D3

84B4

51C4

51C5

51C4

23D5

84B4

50C1

25C4

84B4

51C5

84B4

25C4

25A4

47B3

47B6

49C7

49D7

23B3

47B6

14B6

24C3

47B6

84C6

59C7

84C6

50D3

84C6

47B6

34C3

24C3

36C5

6C6

24B3

5C1

26D4

26C8

5C2

79A4

5C2

5D2

21C3

21D3

36C5

5C1

7C6

21C1

49C7

5C1

36C5

36C4

36C5

36C4

36D4

36C5

36C4

36C5

36C4

36C5

84B4

7C8

7B3

7C8

5C2

7D6

7C8

26C8

26D4

84B4

5C1

84B4

36A5

78B7

78B2

5A7

36A5

36C5

78B7

7C8

21C1

http://mycomp.su/x/

IN

IO

IN

OUT

IN

IN IN

IN

OUT OUT

OUT

IO

IO IO

IN

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IN

OUT

IN

OUT

IO

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI2TXN DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P

USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

USBP4N

OC0* OC1* OC2* OC3* OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK SPI_CS*

SPI_MOSI SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN DMI1RXP

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0* C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE2* C/BE3*

GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3*

PIRQA* PIRQB* PIRQC* PIRQD*

RSVD0 RSVD1 RSVD2 RSVD3

MISC

INT I/F

PCI

(2 OF 6)

IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IN

IO

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NO STUFF - DEFAULT

GNT[0-3]# HAVE INT 20K PU

(INT 20K PU)

(AKA TP3, INTERNAL 20K PU)

SB: 2 OF 4

ENABLED ONLY WHEN PCIRST#=0

R2211

NOTE: FWH_WP_L NOT USED

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

(INT PD)

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

PLACE R2204 < 1/2 IN FROM SB

LAYOUT NOTE:

PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:

NOTE:

LPC (DEFAULT)

PCI

SPI

UNSTUFF

STUFF

UNSTUFFUNSTUFF

UNSTUFF

STUFF

01

10

11

STRAP R2210

NOTE: CHANGE SYMBOL

TO RSVD[1-9]

GNT5# GNT4#

SB BOOT BIOS SELECT

TARGETING FWH BIOS SPACE)

IE SB INVERTS A16 FOR ALL CYCLES

(STRAPPED TO TOP-BLOCK SWAP MODE

STUFF - A16 SWAP OVERRIDE

NOTE:

EXTERNAL 0

EXTERNAL 1

EXTERNAL 2

BOM NOTE FOR PD ON PCI_GNT3_L:

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

AND PWROK=H

IR

CAMERA

TRACKPAD (GEYSER)

BLUETOOTH

1/16W

402

24.9

MF-LF

1%

21

R2203

10K

1/16W MF-LF

5%

402

USB_G_OC_PU

2

1

R2222

402

22.6

1% 1/16W MF-LF

21

R2204

1/16W

5%

10K

MF-LF 402

2

1

R2223

10K

5% 1/16W MF-LF 402

2

1

R2225

402

MF-LF

1/16W

10K

5%

2

1

R2226

10K

5% 1/16W MF-LF 402

2

1

R2299

OMIT

BGA

SB

ICH7-M

D2 D1

N3

N4

M2

M1

L5

L4

K2

K1

J3

J4

H2

H1

G3

G4

F2

F1

P5 P2

P6

R2

P1

R27

N27

L27

J27

G27

E27

R28

N28

L28

J28

G28

E28

T24

P25

M25

K25

H25

F25

T25

P26

M26

K26

H26

F26

B3

A2

C3

E5

D4

D5

C4

D3

C25 D25

AE27

AE28

AC27

AC28

AD24

AD25

AA27

AA28

AB25

AB26

W27

W28

Y25

Y26

U27

U28

V25

V26

U2100

SB

BGA

ICH7-M

OMIT

F14

F15

B10

F21

AH8

AG8

AE9

AD9

AH4

AG4

AD5

AE5

A13

E13

C17

C16

D7

B19

C26

E11

B5

C5

B4

A3

C9

B18

A9

E10

AH20

A7

G7

F8

F7

G8

D8

C8

A14

F13

D17

D16

E7

F16

A12

C15

D12

C12

B15

C14

A15

A17

E17

A18

E16

D6

E6

F18

B6

C7

A6

A8

B9

D9

E9

F10

F11

A10

A16

A11

D11

C11

E12

G13

G15

C13

B12

D14

E14

C18

E18

U2100

MF-LF

1/16W

5%

10K

402

2

1

R2200

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

2

1

R2250

10K

5% 1/16W MF-LF 402

USB_E_OC_PU

2

1

R2251

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

2

1

R2255

MF-LF 402

1/16W

5%

10K

2

1

R2298

MF-LF

402

5%

10K

1/16W

2

1

R2205

402

10K

MF-LF

5%

1/16W

NOSTUFF

2

1

R2206

MF-LF 1/16W

10K

402

5%

2

1

R2207

VOLTAGE=0V

1/16W MF-LF

5%

1K

402

2

1

R2211

051-7150

8422

A.0.0

SB_GPIO31

TP_PCI_GNT4_L

PCI_GNT3_L

TP_PCI_GNT2_L

TP_PCI_GNT0_L

TP_PCI_GNT1_L

=PP3V3_S5_SB_USB

USB_D_OC_L

USB_B_OC_L

USB_E_OC_L

USB_A_OC_L

NB_SB_SYNC_L

TP_SB_RSVD9

ODD_PWR_EN_L

SB_GPIO4

SB_GPIO3

SB_GPIO2

PCI_C_BE_L<0> PCI_C_BE_L<1>

PCI_DEVSEL_L

PCI_PERR_L

PCI_RST_L

TP_PCI_PME_L

PLT_RST_L

PCI_TRDY_L

PCI_FRAME_L

PCI_IRDY_L

PCI_CLK_SB

PCI_PAR

PCI_LOCK_L PCI_SERR_L

PCI_AD<0>

PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5>

PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

PCI_C_BE_L<3>

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L

DMI_IRCOMP_R

SB_CLK100M_DMI_P

USB_RBIAS_PN

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0>

DMI_S2N_N<2> DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

USB_A_N USB_A_P USB_B_N USB_B_P USB_C_N USB_C_P USB_D_N USB_D_P

USB_E_P USB_F_N USB_F_P USB_G_N USB_G_P

TP_USB_H_N

USB_E_N

SB_GPIO30

SB_GPIO29

SB_CLK100M_DMI_N

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_N<1> DMI_N2S_P<1>

PCIE_A_D2R_N PCIE_A_D2R_P PCIE_A_R2D_C_N PCIE_A_R2D_C_P

PCIE_B_D2R_N PCIE_B_D2R_P PCIE_B_R2D_C_N PCIE_B_R2D_C_P

PCIE_C_D2R_N PCIE_C_D2R_P PCIE_C_R2D_C_N PCIE_C_R2D_C_P

PCIE_D_D2R_N PCIE_D_D2R_P PCIE_D_R2D_C_N PCIE_D_R2D_C_P

PCIE_E_D2R_N PCIE_E_D2R_P PCIE_E_R2D_C_N PCIE_E_R2D_C_P

PCIE_F_D2R_N PCIE_F_D2R_P PCIE_F_R2D_C_N PCIE_F_R2D_C_P

SB_GPIO31

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S5_SB_IO

USB_C_OC_L

USB_A_OC_L USB_B_OC_L

USB_D_OC_L

USB_C_OC_L

SPI_ARB

SPI_SO

TP_USB_H_P

INT_PIRQD_L

TP_SB_XOR_AD5 TP_SB_XOR_AG4 TP_SB_XOR_AH4 TP_SB_XOR_AD9

TP_SB_XOR_AE5

TP_SB_XOR_AH8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AG8

TP_SB_XOR_AE9

SB_GPIO29

USB_E_OC_L

PCI_AD<6>

PCI_AD<1>

PCI_REQ0_L

PCI_REQ1_L

PCI_REQ3_L

PCI_STOP_L

SPI_SCLK

PCI_C_BE_L<2>

BOOT_LPC_SPI_L

PCI_REQ2_L

SB_GPIO30

SPI_CE_L

SPI_SI

=PP3V3_S0_SB

PCI_PME_FW_L

51B4

22D8

37D3

79A4

37C3

37D3

37C3

37C6

14B4

6C2

22D8

14B4

25B6

22D8

22C4

54C1

6C2

37D3

22C4

37C3

54C7

49C7

22C4

54C7

54C1

65B3

22C4

6B7

65C3

6C1

6D1

6C1

6D1

14B6

36C7

77A1

26C2

26D2

37C6

37B6

26D2

37C2

26C3

26D2

34D6

37B6

26D2

37D6

37C6

6B7

37C6

37B6

26D2

34C3

5A7

14B4

6D1

6C1

6D1

6C1

6C5

22D8

34C3

14B4

5A7

39D5

39C5

48C3

48B3

48C3

48B3

48A3

48B3

22D8

24D5

65D3

6D1

6C1

6D1

49D5

6C1

26D2

22C4

6C1

37D6

26D2

49D5

37B6

5C2

26D2

6C5

49B5

49D5

25D8

37D3

http://mycomp.su/x/

IN

OUT

OUT OUT

OUT

IN

IO

OUT OUT

OUT

IN

IO

IN

IO

IN

IO

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3* SLP_S4* SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25 GPIO35 GPIO38 GPIO39

SMBCLK SMBDATA LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(INT 20K PU)

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

NOTE FOR R2323 (DEF=NOSTUFF) SB WILL DISABLE TCO TIMER

STRAPPING @ PWROK RISING: SYSTEM REBOOT FEATURE

NOT USED

NOTE: RESERVED FOR FUTURE

LAYOUT NOTE:

NOTE FOR GPIO25:

OD

DEF=GPI

IN RESET STATE TO SAVE PWR

SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F

NOTE:

NOTE: SV_SET_UP IS LINDACARD DETECT

LO = NOT PRESENT

HI = PRESENT

(INT WEAK PD)

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

DEF=GPI

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

DEF=GPI

100

21

R2302

100

21

R2303

100

21

R2305

10K

1/16W MF-LF

5%

402

NOSTUFF

2

1

R2306

1/16W MF-LF

5%

402

10K

2

1

R2307

10K

5%

MF-LF

1/16W 402

2

1

R2308

NOSTUFF

402

0

1/16W MF-LF

5%

2

1

R2309

10K

1/16W MF-LF

5%

402

2

1

R2310

10K

402

NOSTUFF

5%

MF-LF

1/16W

2

1

R2311

402 5%

MF-LF

1/16W

10K

2

1

R2313

5%

MF-LF

1/16W

0

NOSTUFF

402

2

1

R2314

5%

MF-LF

1/16W

10K

402

2

1

R2316

5%

1/16W

10K

402 MF-LF

2

1

R2317

5%

MF-LF

1/16W 402

10K

2

1

R2318

402 5%

MF-LF

1/16W

10K

2

1

R2319

10K

1/16W MF-LF

5%

402

2

1

R2320

SM-LF

10K

5% 1/16W

5678

4321

RP2300

100K

1/16W MF-LF

402

5%

21

R2399

1K

402 5%

MF-LF

1/16W

2

1

R2398

1/16W 402

8.2K

MF-LF 5%

2

1

R2397

402

10K

1/16W

5%

MF-LF

2

1

R2396

5%

402 MF-LF

1/16W

8.2K

2

1

R2395

ICH7-M

SB

BGA

OMIT

F20

AD22

C21

AF20

A22

C20

A27

A19

A25

B25

B22

C22

F22

D23

B24

AH21

Y4

A28

AA4

C23

A26

C19

E20

E21

AC18

AC21

AE20

AD20

AE19

AH19

AD21

U2

AC19

AG18

E23

B21

A21

D20

R3

AF19

AF21

AH18

AC20

AC22

E22

R4

E19

F19

B23

A20

AB18

B2

AC1

U2100

10K

5% MF-LF

1/16W 402

2

1

R2388

NO_REBOOT_MODE

1/16W

1K

5%

402 MF-LF

2

1

R2323

5%

402

MF-LF

1/16W

10K

NOSTUFF

2

1

R2326

10K

402

1/16W MF-LF

5%

NOSTUFF

2

1

R2327

MF-LF

1/16W

8.2K

402

5%

2

1

R2343

A.0.0

23 84

051-7150

SYNC_MASTER=M59_MG

SYNC_DATE=07/25/2006

SB: 3 OF 4

INT_SERIRQ

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_DPRSLPVR

PM_BATLOW_L

SB_CLK48M_USBCTLR

SV_SET_UP

SMB_CLK

SATA_C_DET_L

SB_GPIO19

SB_GPIO21

SB_GPIO37

SB_CLK14P3M_TIMER

SUS_CLK_SB

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

PM_SB_PWROK

PM_SYSRST_L

PM_SUS_STAT_L

BIOS_REC

VR_PWRGD_CK410

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

TP_SB_GPIO6

CRB_SV_DET

=PP3V3_S5_SB

FWH_MFG_MODE

BIOS_REC

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_BMBUSY_L

SB_SPKR

SMB_DATA

=PP3V3_S5_SB

SMC_RUNTIME_SCI_L

PM_RSMRST_L

PM_LAN_ENABLE

PM_PWRBTN_L

PCIE_WAKE_L

FWH_MFG_MODE

PM_STPPCI_L

SMB_ALERT_L

PM_THRM_L

SMC_EXTSMI_L

PM_CLKRUN_L

PM_STPCPU_L

TP_AZ_DOCK_RST_L

TP_GPU_D3COLD_RST_L

=PP3V3_S5_SB

SMS_INT_L

IDE_RESET_L

SV_SET_UP

CRB_SV_DET

TP_SB_GPIO25_DO_NOT_USE

SB_CLK100M_SATA_OE_L

TP_SB_GPIO38

SB_GPIO26

SMC_WAKE_SCI_L

LAN_ENERGY_DET

SMC_SB_NMI

SMLINK<1>

SMLINK<0>

SMB_LINK_ALERT_L

PM_RI_L

58C6

65D3

58C6

65B3

64C8

51B5

25C8

65B3

25C8

58C6

25C8

51C5

23B3

84C6

51B5

49C5

64B8

49B7

50A2

23D8

65D3

23D8

23D5

23D8

47C3

51C4

23D4

51B5

49C7

21D3

59C8

23C3

43B7

49C5

50A2

26C5

49C5

23D4

26C5

23D4

21D3

23B7

39C6

49C5

23B7

50B2

23B6

5C2

21C3

23A3

14B7

49B7

34C7

5C2

27D8

36B5

34A6

6C6

42A8

41B6

49C5

26A6

5B2

5C2

23A6

26B8

23A7

11B5

23C3

23B7

23C5

21C3

23B3

14B6

27D8

23A7

49B7

49D7

5B1

23A6

33C4

49B7

5C2

33C4

26A4

23A7

49B5

36D5

5C2

23B6

33B4

64B7

49D5

40A3

49D7

http://mycomp.su/x/

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

DEPENDING ON VIO OF AZALIA INTERFACE

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

NOTE:

VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOT

S3 IF INTERNAL LAN IS USED

NOTE FOR VCCLAN_3_3:

0 0

OMIT

BGA

ICH7-M

SB

AE21

AE18

AE13

AE11

AE8

AE4

AE2

AD23

AD19

AD15

AD11

AD8

AD7

AD4

AD3

AD1

AC11

AC9

AC5

AC2

AB28

AB27

AB24

AB21

AB19

AB16

AB14

AB11

AB6

AB4

AA26

AA25

AA24

AA1

Y28

Y27

Y24

Y3

W26

W25

W24

W6

V28

V27

V24

V15

V13

V2

U26

U25

U24

U17

U16

U15

U14

U13

U12

U4

T17

T16

T15

T14

T13

T12

T6

R18

R17

R16

R15

R14

R13

R12

R11

R1

P28

P27

P24

P17

P16

P15

P14

P13

P12

P4

P3

N26

N25

N24

AH27

AH23

AH12

AH7

N18

AH3

AH1

AG25

AG20

AG17

AG14

AG11

AG7

AG3

AG1

N17

AF28

AF27

AF11

AF8

AF4

AF2

AE25

AE24

N16

N15

N14

N13

N12

N11

N6

N5

N2

N1

M28

M27

M24

M17

M16

M15

M14

M13

M12

M5

M4

M3

L26

L25

L24

L15

L13

K28

K27

K24

J26

J25

J24

J5

J2

J1

H28

H27

H24

H5

H4

H3

G26

G25

G24

G21

G18

G14

G9

G6

G5

G2

G1

F28

F27

F12

F5

F4

F3

E15

E8

E4

E2

E1

D24

D21

D18

D13

D10

C27

C6

C2

B28

B26

B20

B17

B14

B11

B8

B1

A23

A4

U2100

OMIT

BGA

SB

ICH7-M

C1

K6

K5

K4

K3

G19

D22

D19

C24

E3

N7

M7

M6

L7

L6

L3

L2

L1

A24

P7

R7

G20

C28

K7

AD2

W5

W7

W2

V1

V5

Y7

AA2

AG28

AG15

AG12

AD18

AD13

AC16

AB20

AB12

G16

AA7

G12

G11

F9

D15

C10

B7

B16

B13

A5

AG19

AH11

B27

U6

AD27

AD26

AC26

AC25

Y23

Y22

W23

AC24

W22

V23

V22

U23

U22

T28

T27

T26

T23

T22

AC23

R26

R25

R24

R23

R22

P23

P22

N23

N22

M23

AB23

M22

L23

L22

K23

K22

J23

J22

H23

H22

G23

AB22

G22

F24

F23

E26

E25

E24

D28

D27

D26

AD28

AA23

AA22

AB10

AH5

AG5

AF6

AF5

AE6

AD6

J7

J6

H7

H6

A1

AC8

AB8

G17

F17

T7

AC7

AC17

AB17

AH9

AG9

AF9

AF10

AE10

AD10

AC10

AB9

AC6

AB7

P11

M18

M11

L18

L17

L16

L14

V18

L12

V17

V16

V14

V12

V11

U18

U11

T18

T11

P18

L11

AH26

AE26

AE23

F6

AD17

G10

U2100

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

SB: 4 OF 4

A.0.0

24 84

051-7150

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3

=PP1V05_S0_SB_CPU_IO

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

65C3

65B3

25D2

26D3

25D2

25C6

65D6

65C6

65C3

25B6

25A4

65B3

25B6

65C6

25B8

65C6

25B8

25C4

65B3

65D6

25B6

25B2

25C2

25D2

24A5

21D6

25A4

25B4

24B3

25C6

24B5

25D6

25A5

24B5

21C1

65D3

25C4

25D3

25C7

25D7

22C1

http://mycomp.su/x/

NC NC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ICH IO,LOGIC 1.5V PWR)

ICH VCCA3GP(VCC1_5_B BYPASS

PLACE < 2.54MM OF SB ON

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB

ICH VCC3_3/VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V PWR)

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCUSBPLL BYPASS (ICH USB PLL 1.5V PWR)

(ICH DMI PLL 1.5V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AH11

PLACEMENT NOTE:

ICH USB CORE/VCC1_5_A BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS A1 ... J7

(ICH USB CORE 1.5V PWR)

(ICH LOGIC&IO 1.5V PWR)

ICH VCC1_5A BYPASS

PLACEMENT NOTE:

ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR)

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN U6

PLACE CAP UNDER SB NEAR PINS V1,

PLACEMENT NOTE:

(ICH CORE 1.05V PWR)

ICH CORE/VCC1_05 BYPASS

PLACEMENT NOTE:

ICH V5REF BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

SB: 4 OF 4

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE: PLACE CAPS NEAR PINS

FOR 270UF

PLACEHOLDER

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AG5

3.56MM ON PRIMARY NEAR PIN AG9

(ICH IO BUFFER 3.3V PWR)

NEAR PINS A5 ... G16

DISTRIBUTE IN PCI SECTION OF SB

A24 ... G19 AND P7 OF SB

(ICH PCI I/O 3.3V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH IDE/VCC3_3 BYPASS

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH SATA PLL 1.5V PWR)

ICH VCCSATAPLL BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

(ICH IO BUFFER 3.3V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACEMENT NOTE:

NEAR PINS D28, T28, AD28

PLACE C2520 NEAR PIN C1 OF SB

K3 ... N7 OF SB

PLACE CAPS NEAR PINS

(ICH SUSPEND USB 3.3V PWR)

ICH USB/VCCSUS3_3 BYPASS

AB8 AND AC8 OF SB

PLACE CAPS NEAR PINS

PLACEMENT NOTE:

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

3.56MM ON PRIMARY NEAR PIN AD2

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

V5, W2, OR W7

ICH VCCRTC BYPASS (ICH RTC 3.3V PWR)

ICH VCC3_3 BYPASS

PLACEMENT NOTE: PLACE C2509 NEAR PIN B27 OF SB

ICH VCC3_3 BYPASS

ICH VCC1_5_A/ARX BYPASS (ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR)

ICH V5REF_SUS BYPASS (ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PLACEMENT NOTE: PLACE C2504 < 2.54MM OF PIN F6 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2503 < 2.54MM OF PIN AD17 OF SB

PLACEMENT NOTE:

PLACE C2520 NEAR PIN E3 OF SB

ICH VCCDMIPLL BYPASS

SECONDARY SIDE OR 3.56MM ON PRIMARY

X5R

16V

10%

0.1UF

402

2

1

C2510

0

402

0.1UF

10% 16V X5R

2

1

C2512

0

1

5%

1/10W MF-LF

603

21

R2500

4.7UF

20%

6.3V CERM 603

2

1

C2524

0.1UF

10% 16V X5R 402

2

1

C2522

BAT54DW

SOT-363

5

6

1

D2502

BAT54DW

SOT-363

2

3

4

D2502

1206

0.28-OHM

21

L2507

CASE-B2

2.5V POLY

220UF

20%

2

1

C2500

0.1UF

402

10% 16V X5R

2

1

C2503

0

X5R

16V

10%

0.1UF

402

2

1

C2504

0

5%

MF-LF

1/16W

402

10

21

R2501

100-OHM-EMI

SM-3

21

L2500

0

0.1UF

10% 16V X5R 402

2

1

C2505

X5R

16V

10%

0.1UF

402

2

1

C2506

0.1UF

16V

10% X5R

402

2

1

C2507

0.01UF

10% 16V CERM 402

2

1

C2501

603

10UF

20%

6.3V X5R

2

1

C2508

0

10% 16V X5R 402

0.1UF

2

1

C2509

0

X5R 402

16V

10%

0.1UF

2

1

C2511

0

0.1UF

402

X5R

16V

10%

2

1

C2517

0

0.1UF

10% 16V X5R 402

2

1

C2513

0

402

6.3V CERM

10%

1UF

2

1

C2514

0

0.1UF

10% 16V X5R 402

2

1

C2520

402

X5R

16V

10%

0.1UF

2

1

C2515

0

CASE-C2

POLY

20%

2.5V

330UF

2

1

C2516

5%

1/16W

402

MF-LF

100

2

1

R2502

1UF

10%

6.3V CERM 402

2

1

C2502

402

0.1UF

10% 16V X5R

2

1

C2518

0

X5R

16V

10%

0.1UF

402

2

1

C2519

0

0.1UF

10% 16V

402

X5R

2

1

C2521

0

X5R

16V

10%

0.1UF

402

2

1

C2523

0

0.1UF

X5R

16V

10%

402

2

1

C2525

0

X5R

16V

10%

0.1UF

402

2

1

C2526

X5R

16V

10%

0.1UF

402

2

1

C2527

X5R

16V

10%

0.1UF

402

2

1

C2528

402

0.1UF

10% 16V X5R

2

1

C2529

0

402

0.1UF

10% 16V X5R

2

1

C2530

402

0.1UF

10% 16V X5R

2

1

C2534

0

402

0.1UF

10% 16V X5R

2

1

C2531

402

0.1UF

10% 16V X5R

2

1

C2532

0

402

0.1UF

10% 16V X5R

2

1

C2533

051-7150

8425

A.0.0

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

=PP5V_S0_SB

=PP3V3_S5_SB

=PP3V3_S0_SB

=PP5V_S5_SB

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCCLAN3_3

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S0_SB_VCC3_3

=PP3V3_S0_SB_VCC3_3_PCI

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP3V3_S0_SB_VCC3_3

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S0_SB_VCC3_3_IDE

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

=PP1V5_S0_SB_VCCUSBPLL

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PPVCORE_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB

65D3 23D8

65C3

23D4

26D3

65B3

25D2

25B6

65D6

24D5

23B7

65B3

24B3

65B3

65C6

65C3

65C6

25B8

65B3

65C6

25C6

24B3

65C6

24B3

65C6

65B3

65C6

24C3

65B3

65D6

65C6

22C1

24D5

65A1

23A7

22B5

65B1

21D6

24D3

24A3

24B3

24B5

24B3

24B5

24A5

25C8

24A5

24A3

24C3

24B5

24A5

21C1

24C3

24D3

24A5

25A8

http://mycomp.su/x/

IO

IN

IO IO

IO

IO IO

IO

OUT

IN

OUT

IN

OUT

IN

NCNC

IN

OUT

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Initial resistor values are based on CRB, but may change after characterization.

fault protection for RTC battery.

for use as DVI_HPD in muxed graphics solution.

Pullup on SB_GPIO4 removed as it now defaults low

Platform Reset Connections

NC

518S0452

NOTE: R2607 and D2600 form the double-

NC

Silk: "SYS RST"

Unbuffered

NC

SB RTC Crystal Circuit

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

This part is never stuffed,

NCNC

on the board to short or

LIO represents X loads (2?)

Hook to inverter PWM AND gate (except M59) This RST is used to mask a glitch output from

the NB PWM output during reset.

On M59 this RST is used for layout reasons

Buffered

D3Cold Reset for GPU

to solder a reset button.

it provides a set of pads

RTC Battery Connector

MF-LF

5%

402

1/16W

20K

21

R2600

0.1UF

402

CERM

10V

20%

2

1

C2611

402

CERM

6.3V

10%

1UF

2

1

C2605

5%

1/16W

100K

MF-LF

402

OMIT

2

1

R2698

1M

402

MF-LF

1/16W

5%

2

1

R2606

MF-LF

10K

402

5%

1/16W

2

1

R2697

402

5%

MF-LF

1/16W

1K

12

R2607

12pF

CERM

402

5%

50V

21

C2608

CERM

12pF

50V

5%

402

21

C2609

SM-2

CRITICAL

32.768K

31

42

Y2600

0

402

MF-LF

1/16W

5%

21

R2610

10M

402

MF-LF

1/16W

5%

2

1

R2609

0.1UF

20%

CERM 402

10V

2

1

C2680

MF-LF 402

100K

1/16W

5%

2

1

R2680

5%

1/16W

402

0

MF-LF

21

R2681

1/16W MF-LF

402

100

5%

21

R2683

MF-LF

0

1/16W

5%

402

21

R2684

0

402

MF-LF

1/16W

5%

21

R2685

MF-LF

402

5%

1/16W

0

21

R2682

1K

ITP

402

5% 1/16W MF-LF

21

R2696

MC74VHC1G00

SC70-5

5

4

1

2

3

U2603

MC74VHC1G08

SC70

5

4

1

2

3

U2680

SC70

MC74VHC1G08

5

4

1

2

3

U2601

BAT54DW

SOT-363

2

5

3

6

4

1

D2600

BM02B-ACHKS-A-GAN-TF-LF

M-RT-SM

CRITICAL

2

1

4

3

J2600

100K

MF-LF 402

1/16W

5%

2

1

R2688

SC70

MC74VHC1G08

5

4

1

2

3

U2685

0.1UF

CERM

20% 10V

402

2

1

C2685

1/16W MF-LF

5%

402

10K

2

1

R2686

5% 1/16W MF-LF

402

0

21

R2687

402

5% 1/16W MF-LF

1K

21

R2689

10% 50V

402

CERM

0.001UF

2

1

C2689

1/16W

402

MF-LF

5%

1.8K

2

1

R2611

0.1UF

402

CERM

10V

20%

2

1

C2607

402

MF-LF

1/16W

5%

10K

2

1

R2612

10K

5% 1/16W MF-LF 402

2

1

R2622

8.2K

21

R2623

8.2K

21

R2624

8.2K

21

R2625

8.2K

21

R2626

8.2K

21

R2627

8.2K

21

R2628

8.2K

21

R2629

8.2K

21

R2630

8.2K

21

R2631

8.2K

21

R2632

8.2K

21

R2633

8.2K

21

R2634

8.2K

21

R2636

8.2K

21

R2637

8.2K

21

R2638

8.2K

21

R2639

8.2K

21

R2640

8.2K

21

R2642

402

6.3V

10% CERM

1UF

2

1

C2610

SB Misc

26

051-7164 A.0.0

84

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

=GPU_HPD_ENABLE

MAKE_BASE=TRUE

GPU_SIGNAL_ENABLE

=PP3V3_S5_SB_PM

PLTRST_D3COLD_L

=GPU_DDC_ENABLE

PEG_RESET_L

=PP3V3_S0_RSTBUF

TP_GPU_D3COLD_RST_L

MAKE_BASE=TRUE

PLT_RST_L

=PP3V3_S0_RSTBUF

TPM_LRESET_L

PLTRST_D3COLD_IN_L

MAKE_BASE=TRUE

GPU_D3COLD_RESET_L

LIO_PLT_RESET_L

MAKE_BASE=TRUE

M59_INVERTER_PLT_RST_L

INVERTER_PLT_RST_L

PLTRST_D3COLD_IN_L

=PP3V3_S0_SB_PM

PCI_IRDY_L

PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L

PCI_REQ0_L PCI_REQ1_L PCI_REQ2_L PCI_REQ3_L

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L SB_GPIO2 SB_GPIO3

=PP3V3_S0_SB_PCI

PPVBATT_G3C_RTC

VOLTAGE=3.3V

SB_RTC_X2

ENET_RST_L

MAKE_BASE=TRUE VOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

PCI_LOCK_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PP3V3_S5_SB_RTC

=PP3V42_G3H_SB_RTC

PPVBATT_G3C_RTC_R

VOLTAGE=3.3V

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROK

MAKE_BASE=TRUE

VR_PWRGD_CK410_L

MAKE_BASE=TRUE

PM_SYSRST_L

SB_SM_INTRUDER_L

SB_RTC_X1

DEBUG_RST_L

SMC_LRESET_L

NB_RST_IN_L

VR_PWRGD_CK410

CK410_PD_VTT_PWRGD_L

SB_RTC_RST_L

SB_RTC_X1_R

XDP_DBRESET_L

=PP3V3_S0_SB_PM

PLT_RST_BUF_L

65D3

25A4

23D1

65A3

79A4

65A3

47C6

65B3

37D3

37C3

37D3

22B6

37D3

37C3

37D3

24B3

59C7

64B1

51B4

33A4

65B3

77B2

11B5

79A7

67A5

26B4

23C5

22A6

26B4

58B7

26C1

5C1

6C5

26A4

26B6

22A6

22B6

6B7

22A7

22A6

65B3

5A2

21D6

39C6

22A6

22A7

21D6

65D3

14B6

49D7

23C3 59C7

21D6

5C2

49C7

14B7

23C5

21D6

26B8

37A7

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SLGLP436: U3301

(MASTER)

U5800

SMC

U5800

(MASTER)

U5800

SMC

(MASTER)

Left I/O SMBus Connections:

SMC "B" SMBus Connections

SMC "Battery B" SMBus Connections

SMC "Battery A" SMBus Connections

J8250

(Write: 0x16 Read: 0x17)

Battery

J5400

(See Table)

CPU Temp

Left I/O Board

(Write: 0x98 Read: 0x99)

TMP401: U1001

SO-DIMM "B"

(Write: 0xA0 Read: 0xA1)

SMC

SO-DIMM "A"

U2 - Keyboard Controller

U1 - Trackpad Controller

Trackpad I2C Connections:

(Write: 0x70 Read: 0x71)

(Write: 0x72 Read: 0x73)

Left I/O SMBus Connections:

Left I/O Board

(See Table)

(MASTER)

U5800

J2800

Clock Chip

(Write: 0xD2 Read: 0xD3)

U2100

(MASTER)

MAX6695: U6100

(Write: 0x98 Read: 0x99)

ICH7-M

J5500

(See Table)

(Write: 0xA4 Read: 0xA5)

J2900

Trackpad

J4900

ICH7-M SMBus Connections

(Write: 0x30 Read: 0x31)

GPU Temp

TMP401: U6150

Remote Temps

SMC "0" SMBus Connections

ExpressCard Slot

(Address determined by ARP)

LIO - TMP106

(Write: 0x92 Read: 0x93)

M35B - TMP106

(Write: 0x90 Read: 0x91)

J4900

(See Table)

Top-Case

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

(MASTER)

U5800

Top-Case SMBus Connections:

(Write: 0x92 Read: 0x93)

Palm Rest Temp - TMP275

4.7K

5%

1/16W

402

MF-LF

2

1

R2700

4.7K

1/16W

5%

402

MF-LF

2

1

R2701

4.7K

MF-LF

402

5%

1/16W

2

1

R2780

4.7K

MF-LF 402

5% 1/16W

2

1

R2781

MF-LF 402

1/16W

5%

100K

2

1

R2791

MF-LF

402

5%

1/16W

100K

2

1

R2790

4.7K

5% 1/16W MF-LF 402

2

1

R2761

4.7K

MF-LF

402

1/16W

5%

2

1

R2760

1/16W MF-LF 402

5%

4.7K

2

1

R2771

1/16W

402

MF-LF

5%

4.7K

2

1

R2770

4.7K

5% 1/16W MF-LF 402

2

1

R2751

4.7K

1/16W

5%

402

MF-LF

2

1

R2750

051-7150 A.0.0

27 84

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

M1 SMBus Connections

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMBUS_TOPCASE_SDA

=SMBUS_TOPCASE_SCL

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

=I2C_TRACKPAD_SDA

=I2C_TRACKPAD_SCL

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=SMBUS_LIO_SB_SCL

=SMBUS_LIO_SB_SDA

SMB_CLK

SMB_DATA

=I2C_SODIMMA_SCL

SMB_CK410_DATA

SMB_CK410_CLK

SMB_0_S0_DATA

SMB_0_S0_CLK

=SMBUS_GPU_TDIODE_SDA

=SMBUS_GPU_TDIODE_SCL

=I2C_SODIMMA_SDA

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0_S0

SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SB_SCL

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SB

=PP3V3_S0_SMBUS_SMC_B_S0

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_SMC_BSB

SMB_THRM_DATA

SMB_THRM_CLK

=SMBUS_LIO_SMC_SDA

=SMBUS_LIO_SMC_SCL

=SMBUS_BATT_SCL

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

=SMBUS_BATT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_BSA_CLK

SMB_BSA_DATA

SMBUS_SMC_BSB_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSB_SDA

SMB_BSB_CLK

SMB_BSB_DATA

47C3

66B5

49B5

78C2

65C3

52C2

78C2

29A6

5B1

23D5

28A6

33B6

49C5

49C7

52B3

28A6

65B3 65B3 65B3

65D3

65B3

10B3

5B1

5D1

49B5

49C5

49C7

http://mycomp.su/x/

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1 VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Expansion" (surface-mount) slot

516S0471

Page Notes

Signal aliases required by this page:

by another page.

The reference voltage must be provided

NOTE: This page does not supply VREF.

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

NC

Power aliases required by this page:

(NONE)

BOM options provided by this page:

- =PP1V8_S3_MEM

- =PPSPD_S0_MEM (2.5V - 3.3V)

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)

DDR2 Bypass Caps

NC

10%

1UF

CERM

6.3V

402

2

1

C2813

10%

1UF

CERM

6.3V

402

2

1

C2812

6.3V

20%

603

X5R

10UF

2

1

C2809

10%

1UF

CERM

6.3V

402

2

1

C2811

6.3V

20%

603

X5R

10UF

2

1

C2808

10%

1UF

CERM

6.3V

402

2

1

C2810

1UF

CERM

6.3V

10%

402

2

1

C2819

1UF

CERM

6.3V

10%

402

2

1

C2818

10%

1UF

CERM

6.3V

402

2

1

C2817

10%

1UF

CERM

6.3V

402

2

1

C2816

1UF

CERM

6.3V

10%

402

2

1

C2821

1UF

CERM

6.3V

10%

402

2

1

C2820

10%

1UF

CERM

6.3V

402

2

1

C2815

10%

1UF

CERM

6.3V

402

2

1

C2814

10V

20%

402

CERM

0.1uF

2

1

C2800

DDR2-SODIMM-DUAL

CRITICAL

F-RT-SM-M9

109A

24A

21A

18A

15A

12A

196A

193A

190A

187A

184A183A

178A177A

172A

9A

171A

168A

165A

162A161A

156A155A

150A149A

145A

144A

139A

138A

133A

132A

128A127A

122A121A

78A

8A

77A

72A71A

66A65A

60A59A

54A53A

3A

48A47A

42A41A

40A39A

34A33A

28A27A

2A1A

199A

112A111A

104A103A

96A95A

88A87A

82A

118A117A

81A

195A

197A

200A

198A

110A

108A

114A

163A

120A

83A

69A

50A

115A

119A

80A

84A

86A

116A

204

203

202

201

186A 188A

167A

169A

146A

148A

129A

131A

68A

70A

49A

51A

29A 31A

11A

13A

25A

23A

16A

14A

194A

192A

182A

180A

6A

191A

189A

181A

179A

176A

174A

160A

158A

175A

173A

4A

159A

157A

154A

152A

142A

140A

153A

151A

143A

141A

19A

136A

134A

126A

124A

137A

135A

125A

123A

76A

74A

17A

64A

62A

75A

73A

63A

61A

58A

56A

46A

44A

7A

57A

55A

45A

43A

38A

36A

22A

20A

37A

35A

5A

185A

170A

147A

130A

67A

52A

26A

10A

79A

166A

164A

32A

30A

113A

85A

106A

107A

91A 93A

92A 94A

97A 98A 99A

100A

101A

89A 90A

105A

102A

J2800

6.3V

CERM1

603

20%

2.2uF

2

1

C2801

28 84

A.0.0051-7150

DDR2 SO-DIMM Connector A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEM_VREF

MEM_A_DM<0>

MEM_CLK_P<1>

=PP1V8_S3_MEM

=PPSPD_S0_MEM

=PP1V8_S3_MEM

MEM_A_DQ<2>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQS_N<3>

MEM_A_DQ<23>

MEM_A_CAS_L MEM_CS_L<1>

MEM_ODT<0>

MEM_A_RAS_L

MEM_A_A<0>

MEM_A_A<11>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_DQ<17>

MEM_A_DM<2>

MEM_A_DQ<22>

MEM_A_DQ<1>

MEM_A_BS<1>

MEM_CKE<1>

MEM_A_DQ<14>

MEM_A_DQ<11>

MEM_A_DQ<5> MEM_A_DQ<4>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<6>

MEM_A_DQ<19> MEM_A_DQ<18>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<20> MEM_A_DQ<16>

MEM_A_DM<3>

MEM_A_DQ<27>

MEM_CKE<0>

MEM_A_BS<2>

MEM_A_A<12> MEM_A_A<9> MEM_A_A<8>

MEM_A_A<5> MEM_A_A<3> MEM_A_A<1>

MEM_A_BS<0> MEM_A_WE_L

MEM_A_DQ<7>

MEM_ODT<1>

MEM_A_DQ<35> MEM_A_DQ<39>

MEM_A_DQS_N<4> MEM_A_DQS_P<4>

MEM_A_DQ<37> MEM_A_DQ<33>

MEM_A_DM<7>

MEM_A_DQ<58>

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MEM_A_DQ<41> MEM_A_DQ<46>

MEM_A_DQ<51> MEM_A_DQ<50>

MEM_A_DM<6>

MEM_A_DQ<53> MEM_A_DQ<48>

=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

MEM_A_DQ<8>

MEM_CLK_P<0> MEM_CLK_N<0>

MEM_A_DQ<0>

MEM_A_DQ<21>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<7> MEM_A_A<6>

MEM_A_A<4> MEM_A_A<2>

MEM_CS_L<0>

MEM_A_A<13>

MEM_A_DQ<38> MEM_A_DQ<34>

MEM_A_DM<4>

MEM_A_DQ<32> MEM_A_DQ<36>

MEM_A_DQ<40> MEM_A_DQ<42>

MEM_CLK_N<1>

MEM_A_DM<5>

MEM_A_DQ<47>

MEM_A_DQ<54>

MEM_A_DQS_N<6> MEM_A_DQS_P<6>

MEM_A_DQ<52> MEM_A_DQ<49>

DIMM_OVERTEMP_L

MEM_A_DQ<44>

MEM_A_DQS_P<3>

MEM_A_DQ<26>

MEM_A_DQ<3>

MEM_A_DQ<9>

MEM_A_DQ<15>

MEM_A_DM<1>

MEM_A_DQ<10>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<59>

MEM_A_DQ<61>

MEM_A_DQ<45>

MEM_A_DQ<55>

MEM_A_DQ<60>

MEM_A_DQ<57>

MEM_A_DQ<62>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQS_N<7>

MEM_A_DQ<56>

MEM_A_DQ<43>

MEM_A_A<10>

MEM_A_DQ<30>

MEM_A_DQ<25>

MEM_A_DQ<28>

=PP1V8_S3_MEM

65B6 65B6

65B6

29D6 29D6

29D6

29D3 29D3

29D3

29B2

65A3

29B2

32B3

28D6

29A6

28D3

30B6

30D6

30C6

30B6

30C6

30B6

30D6 30D6

30B6

30C6

30B6

30C6

30D6

30C6

50D3

30C6

28D6

29D6

15D5

14D4

28B2

29A3

28B2

15D7

15C7

15C5

15C7

15D5

14C4

15B5

15C5

15B5

15C7

15D5

15C7

15D7

15D5

14C4

15C7

15D7

15C5

15D7

15C7

15C5

15C7

15C5

15C7

14C4

15D5

15B5

15C5

15D5

15B5

15D7

14C4

15B7

15C5

15B7

15C7

15C5

15B7

15C5

15B7

15C5

15B7

27D6

15C7

14D4

15D7

15C7

6D6

15B5

15C5

14C4

15B5

15B7

15C5

15C7

15B7

14D4

15C5

15B7

15C5

15B7

29C3

15B7

15C5

15C7

15D7

15C7

15D5

15C7

15C5

15B7

15A7

15B7

15A7

15B7

15A7

15C5

15A7

15C5

15B7

15B5

15C7

28D3

http://mycomp.su/x/

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0* DQS0 VSS6 DQ2 DQ3

DQ8 DQ9 VSS10 DQS1* DQS1

DQ10 DQ11 VSS14

VSS16 DQ16 DQ17 VSS18 DQS2* DQS2 VSS21 DQ18 DQ19 VSS23 DQ24 DQ25 VSS25 DM3 NC1 VSS27 DQ26 DQ27 VSS29 CKE0 VDD0 NC2 BA2 VDD2 A12 A9 A8 VDD4 A5 A3 A1 VDD6 A10/AP BA0 WE* VDD8 CAS* NC/S1* VDD10 NC/ODT1 VSS31 DQ32 DQ33 VSS33 DQS4* DQS4 VSS36

DQ35 VSS38

DQ41 VSS40 DM5 VSS41

VSS43 DQ48 DQ49 VSS45 NC_TEST VSS47 DQS6*

VSS49 DQ50

VSS51 DQ56

VSS53 DM7 VSS55 DQ58 DQ59 VSS57 SDA SCL VDDSPD

DM6

DQ55

DQ61

DQ46 DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14 DQ15

VSS15

VSS17

DQ20 DQ21

VSS19

NC0 DM2

VSS22

DQ22 DQ23

VSS24

DQ28

DQ29 VSS26 DQS3*

DQS3 VSS28

DQ30

DQ31 VSS30

NC/CKE1

VDD1

NC/A15 NC/A14

VDD3

A11

A7 A6

VDD5

A4 A2 A0

VDD7

BA1

RAS*

S0* VDD9 ODT0

NC/A13

VDD11

NC3

VSS32

DQ36 DQ37

VSS34

DM4

VSS35

DQ38 DQ39

VSS37

DQ44 DQ45

VSS39 DQS5*

DQS5

VSS42

VSS44

DQ52 DQ53

VSS46

CK1 CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54 DQS7*

DQS7

VSS56

DQ62 DQ63

VSS58

SA0

SA1

DQ5 VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516-0140

NOTE: This page does not supply VREF. The reference voltage must be provided by another page.

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

Page Notes

NC

Signal aliases required by this page:

(NONE)

Power aliases required by this page:

- =PP1V8_S3_MEM

- =PPSPD_S0_MEM (2.5V - 3.3V)

BOM options provided by this page:

NC

Resistor prevents pwr-gnd short

ADDR=0xA4(WR)/0xA5(RD)

(For return current)

DDR2 Bypass Caps

"Factory" (thru-hole) slot

402

CERM

1UF

10%

6.3V

2

1

C2913

402

CERM

1UF

10%

6.3V

2

1

C2912

6.3V

20%

603

X5R

10UF

2

1

C2909

10V

0.1uF

CERM 402

20%

2

1

C2911

603

20%

6.3V

X5R

10UF

2

1

C2908

402

CERM

1UF

10%

6.3V

2

1

C2910

10V

0.1uF

CERM 402

20%

2

1

C2919

10V

0.1uF

CERM 402

20%

2

1

C2918

0.1uF

CERM 402

20%

10V

2

1

C2917

402

CERM

1UF

10%

6.3V

2

1

C2916

10V

0.1uF

CERM 402

20%

2

1

C2921

0.1uF

10V

CERM 402

20%

2

1

C2920

402

CERM

1UF

10%

6.3V

2

1

C2915

402

CERM

1UF

10%

6.3V

2

1

C2914

402

MF-LF

1/16W

5%

10K

2

1

R2900

CRITICAL

DDR2-SODIMM-DUAL

F-RT-TH1

109B

24B

21B

18B

15B

12B

196B

193B

190B

187B

184B183B

178B177B

172B

9B

171B

168B

165B

162B161B

156B155B

150B149B

145B

144B

139B

138B

133B

132B

128B127B

122B121B

78B

8B

77B

72B71B

66B65B

60B59B

54B53B

3B

48B47B

42B41B

40B39B

34B33B

28B27B

2B1B

199B

112B111B

104B103B

96B95B

88B87B

82B

118B117B

81B

195B

197B

200B

198B

110B

108B

114B

163B

120B

83B

69B

50B

115B

119B

80B

84B

86B

116B

202

201

186B

188B

167B

169B

146B

148B

129B

131B

68B

70B

49B

51B

29B

31B

11B

13B

25B

23B

16B

14B

194B

192B

182B

180B

6B

191B

189B

181B

179B

176B

174B

160B

158B

175B

173B

4B

159B

157B

154B

152B

142B

140B

153B

151B

143B

141B

19B

136B

134B

126B

124B

137B

135B

125B

123B

76B

74B

17B

64B

62B

75B

73B

63B

61B

58B

56B

46B

44B

7B

57B

55B

45B

43B

38B

36B

22B

20B

37B

35B

5B

185B

170B

147B

130B

67B

52B

26B

10B

79B

166B

164B

32B

30B

113B

85B

106B

107B

91B

93B

92B

94B

97B 98B

99B

100B

101B

89B 90B

105B

102B

J2900

0.1uF

CERM 402

20% 10V

2

1

C2900

2.2uF

20%

603

CERM1

6.3V

2

1

C2901

8429

051-7150 A.0.0

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

DDR2 SO-DIMM Connector B

=PP1V8_S3_MEM

MEM_B_DQ<18>

MEM_VREF

=PPSPD_S0_MEM

SODIMM_A_SA1

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DQ<48> =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

=PPSPD_S0_MEM

MEM_B_DQ<15>

MEM_B_DM<1>

MEM_B_DQ<14>

MEM_B_DQS_N<0>

MEM_B_DQ<21>

MEM_B_DQS_N<2> MEM_B_DQS_P<2>

MEM_B_DQ<23>

MEM_B_DQ<29> MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_CKE<2>

MEM_B_BS<2>

MEM_B_A<12> MEM_B_A<9> MEM_B_A<8>

MEM_B_A<3> MEM_B_A<1>

MEM_B_A<10> MEM_B_BS<0> MEM_B_WE_L

MEM_B_CAS_L MEM_CS_L<3>

MEM_ODT<3>

MEM_B_DQ<36> MEM_B_DQ<33>

MEM_B_DQS_N<4> MEM_B_DQS_P<4>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<40> MEM_B_DQ<41>

MEM_B_DM<5>

MEM_B_DQ<43>

MEM_B_DQ<54> MEM_B_DQ<51>

MEM_B_DM<6>

MEM_B_DQ<52> MEM_B_DQ<49>

MEM_B_DQ<42>

MEM_B_RAS_L

MEM_CS_L<2>

MEM_ODT<2>

MEM_B_A<13>

MEM_B_DQ<37>

MEM_B_DM<4>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<46>

MEM_CLK_N<2>

MEM_B_DQ<55>

MEM_B_DQ<32>

MEM_B_DQ<12>

MEM_B_DM<2>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<28>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_BS<1>

MEM_B_DQ<9>

MEM_B_DQ<11>

MEM_B_DQ<19>

MEM_B_DM<3>

MEM_B_A<14>

MEM_CKE<3>

MEM_B_A<5>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQ<61> MEM_B_DQ<57>

MEM_B_DQ<60> MEM_B_DQ<56>

MEM_B_DM<7>

MEM_CLK_P<2>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<58> MEM_B_DQ<59>

MEM_B_DQ<8>

MEM_B_DQS_P<0>

DIMM_OVERTEMP_L

MEM_B_DQ<22>

MEM_B_DQS_N<1> MEM_B_DQS_P<1>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DM<0>

MEM_CLK_P<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<26>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_A<15>

MEM_B_DQ<27>

=PP1V8_S3_MEM

MEM_B_DQ<20>

=PP1V8_S3_MEM

MEM_B_DQ<0>

MEM_CLK_N<3>

MEM_B_DQ<1>

65B6

65B6 65B6

29D6

29D3 29D6

29D3

29B2 29B2

28D6

65A3

28D6 28D6

28D3

32B3

29A6

29A3

30D6

30A6

30B6

30A6

30D6

30C6

30A6

30D6

30C6

30B6

30A6

30D6

30B6

50D3

28D3 28D3

28B2

15C4

28D6

28A6

15B4

27C6

28A6

15C4

15D2

15C4

15C2

15C4

15C2

15C4

14C4

15D2

15B2

15C2

15B2

15D2

15B2

15D2

14C4

15B4

15C4

15C2

15B4

15C2

15B4

15C2

15B4

15B2

14C4

15B2

15B4

15C2

15B4

15C2

15B4

14D4

15B4

15C4

15D2

15C4

15C2

15B2

15C2

15D2

15C4

15C2

6D6

14C4

15B2

15C2

15B4

15A4 15B4

15C2

14D4

15A4

15B4

15C4

15C2

28C3

15C4

15C2

15C4

15D2

14D4

15D4

15C4

6D6

15C4

28B2

15C4

28B2

15D4

14D4

15D4

http://mycomp.su/x/

IN

IN IN IN

IN

IN IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Ensure CS_L and ODT resistors are close to SO-DIMM connector

One cap for each side of every RPAK, one cap for every two discrete resistors

0.1uF

CERM

20% 10V

402

2

1

C3051

20% 10V CERM 402

0.1uF

2

1

C3053

402

20% 10V CERM

0.1uF

2

1

C3052

402

10V

20%

0.1uF

CERM

2

1

C3050

0.1uF

402

CERM

10V

20%

2

1

C3055

20% 10V CERM 402

0.1uF

2

1

C3057

0.1uF

402

CERM

10V

20%

2

1

C3059

10V

402

CERM

20%

0.1uF

2

1

C3058

0.1uF

20% 10V CERM 402

2

1

C3056

20% 10V CERM 402

0.1uF

2

1

C3054

0

1

2

3

5

4

6

7

8

9

10

11

12

13

0

2

1

29C6 29C3 29B6 29B3 15C2 15B2

29C6 29B6 29B3 15D2

29B3 15B2

29B6 15D2

29B6 15B2

56

5%

1/16W

SM-LF

63

RP3058

5%

1/16W

SM-LF

56

54

RP3058

5%

1/16W

SM-LF

56

72

RP3032

56

1/16W

SM-LF

5%

81

RP3032

56

5%

SM-LF

1/16W

72

RP3052

SM-LF

1/16W

5%

56

81

RP3050

SM-LF

1/16W

5%

56

81

RP3054

56

SM-LF

5%

1/16W

81

RP3056

56

SM-LF

1/16W

5%

81

RP3005

56

5%

1/16W

SM-LF

54

RP3056

56

5%

1/16W

SM-LF

72

RP3058

56

5%

1/16W

SM-LF

81

RP3058

56

5%

1/16W

SM-LF

54

RP3054

56

5%

1/16W

SM-LF

63

RP3054

56

5%

1/16W

SM-LF

81

RP3052

56

5%

1/16W

SM-LF

72

RP3054

56

5%

1/16W

SM-LF

63

RP3052

56

5%

1/16W

SM-LF

54

RP3050

56

5%

1/16W

SM-LF

63

RP3050

56

5%

1/16W

SM-LF

72

RP3005

56

5%

1/16W

SM-LF

72

RP3050

56

5%

1/16W

SM-LF

63

RP3056

56

SM-LF

5%

1/16W

72

RP3056

56

5%

1/16W

SM-LF

54

RP3052

56

402

MF-LF

5%

1/16W

21

R3000

56

1/16W5%MF-LF

402

21

R3002

56

1/16W

402

MF-LF

5%

21

R3001

56

1/16W

402

MF-LF

5%

21

R3003

SM-LF

1/16W

5%

56

54

RP3005

5%

1/16W

SM-LF

56

54

RP3030

SM-LF

1/16W

5%

56

63

RP3030

5%

1/16W

SM-LF

56

81

RP3010

5%

1/16W

SM-LF

56

72

RP3010

56

SM-LF

1/16W

5%

72

RP3034

56

SM-LF

1/16W

5%

81

RP3030

56

SM-LF

1/16W

5%

63

RP3032

SM-LF

56

1/16W

5%

72

RP3030

SM-LF

56

1/16W

5%

63

RP3005

SM-LF

56

1/16W

5%

81

RP3034

56

SM-LF

1/16W

5%

54

RP3034

SM-LF

56

1/16W

5%

54

RP3032

56

1/16W

5%

SM-LF

81

RP3036

SM-LF

56

1/16W

5%

63

RP3034

SM-LF

56

1/16W

5%

63

RP3036

5%

1/16W

SM-LF

56

54

RP3036

5%

1/16W

SM-LF

56

72

RP3036

5%

1/16W

SM-LF

56

54

RP3010

SM-LF

1/16W

5%

56

63

RP3010

56

1/16W5%MF-LF

402

21

R3010

402

MF-LF

5%

1/16W

56

21

R3011

56

1/16W5%MF-LF

402

21

R3012

5%561/16W MF-LF

402

21

R3013

0

1

0

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

29B6 29B3 28B6 28B3 14C4

29C6 29C3 28C6 28C3 14C4

28C6 28C3 28B6 28B3 15C5 15B5

28C6 28B6 28B3 15D5

28B3 15B5

28B6 15D5

28B6 15B5

2

3

2

3

0.1uF

402

CERM

10V

20%

2

1

C3039

10V

402

CERM

20%

0.1uF

2

1

C3038

0.1uF

402

CERM

10V

20%

2

1

C3033

0.1uF

CERM

10V

20%

402

2

1

C3032

0.1uF

20% 10V CERM 402

2

1

C3031

402

10V

20%

0.1uF

CERM

2

1

C3030

CERM 402

20% 10V

0.1uF

2

1

C3011

CERM

10V

20%

402

0.1uF

2

1

C3010

10V

0.1uF

402

CERM

20%

2

1

C3007

20% 10V CERM 402

0.1uF

2

1

C3005

0.1uF

402

CERM

10V

20%

2

1

C3002

0.1uF

20% 10V CERM 402

2

1

C3000

20% 10V CERM 402

0.1uF

2

1

C3037

0.1uF

20% 10V CERM 402

2

1

C3036

0.1uF

402

CERM

10V

20%

2

1

C3035

20% 10V CERM 402

0.1uF

2

1

C3034

0

1

2

3

29B6 29B3 28B6 28B3 14C4

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Memory Active Termination

051-7150 A.0.0

8430

MEM_B_A<13..0>

MEM_B_BS<2..0>

MEM_CS_L<3..0>

MEM_CKE<3..0>

MEM_A_BS<2..0>

MEM_A_A<13..0>

MEM_ODT<3..0>

MEM_B_WE_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP0V9_S0_MEM_TERM

65D6

http://mycomp.su/x/

VLDOIN

VIN

VTT

VTTSNS

VTTREF

VDDQSNS

S3

S5

PGND

THRML

GND

PAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

- =PP0V9_S0_MEMVTT_LDO

- =PP1V8_S0_MEMVTT

- =PP5V_S0_MEMVTT

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

(NONE)

Okay to turn off 5V and leave 1.8V powered in S3.

disable MEMVTT in sleep.

MEMVTT_EN can be used to

If power inputs are not S0,

DDR2 Vtt Regulator

20%

X5R

0.1UF

25V

402

2

1

C3102

MSOP

TPS51100

CRITICAL

5

6

3

2

10

1

11

9

7

4

8

U3100

4.7UF

6.3V

603

CERM

20%

2

1

C3104

10UF

20%

X5R

6.3V

603

2

1

C3101

1K

402

MF-LF

1/16W

5%

MEMVTT_EN_PU

2

1

R3100

22UF

20%

6.3V X5R 805

2

1

C3105

22UF

20%

6.3V X5R 805

2

1

C3106

31 84

A.0.0051-7150

Memory Vtt Supply

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PP0V9_S0_MEMVTT_LDO

MEMVTT_VREF

=PP1V8_S0_MEMVTT

MEMVTT_EN

=PP5V_S0_MEMVTT

65D8

65B6

65A1

http://mycomp.su/x/

V+

V-

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL

MAX4236EUTT

SOT23-6-LF

2

6

5

1

4

3

U3200

20%

0.1UF

402

10V

CERM

2

1

C3200

CERM

402

220pF

25V

5%

2

1

C3205

10K

1/16W

1%

402

MF-LF

2

1

R3206

10K

MF-LF

402

1%

1/16W

2

1

R3205

100K

MEMVREF_S3

MF-LF

402

5%

1/16W

2

1

R3202

5% 1/16W MF-LF

402

0

MEMVREF_S0

2 1

R3203

32 84

A.0.0051-7150

DDR2 VRef

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.15 mm VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

MEMVREF_OUT

=PP1V8_S3_MEMVREF

MEMVREF_UNBUF

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V

MEM_VREF_NB_1

MEM_VREF_NB_0

MEM_VREF

=MEMVREF_EN

=PP3V3_S3_MEMVREF

MEMVREF_SHDN_L

29D6

65B6

14C2

28D6

64C6

65C3

http://mycomp.su/x/

IN IN

OUT OUT

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN IO

OUT

IN

IO

OUT

IN

OUT

IN

OUT

IN

VSS_SRC

THRML_PAD

VSS_REF

VSS_PCI

VSS_CPU

VSS_48

NC

SDA

PCIF_1

PCIF_0/ITP_EN

PCI_5/FCT_SEL_1

PCI_4

PCI_3

PCI_2

PCI_1

FS_B_TEST_MODE

REF_1/FCT_SEL_0

REF_0/FS_C/TEST_SEL

48M/FS_A

VTT_PWRGD*/PD

VDD_A VSS_A

XTAL_IN XTAL_OUT

CLKREQ_8*

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_3*

CLKREQ_1*

CPU_STOP*

PCI_STOP*

VDD_CPU

VDD_48

SCL

CPU_0*

CPU_0

CPU_1

CPU_1*

CPU_ITP/SRC_11*

CPU_ITP/SRC_11

SRC_0/LCD_CLK

SRC_0/LCD_CLK*

SRC_1

SRC_1*

SRC_2*

SRC_2

SRC_3

SRC_3*

SRC_4

SRC_4*

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_8*

SRC_6*

SRC_6

SRC_8

DOT_96*/27M_SS*

DOT_96/27M

VDD_SRC

VDD_REF

VDD_PCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NB CRT/TV GRAPHICS DOTCLK 100MHZ)

(GIGA LAN PCI-E 100 MHZ )

(INT PU)

(GMCH HOST 133/167MHZ)

* FOR EXT. GRAPHIC SYSTEM

PIN 10 100MT_SSTDOT96C

DOT96T

27M NON SPREAD

OFF LOW

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

(PORT80 LPC 33MHZ)

(NO USED)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(ICH SM BUS)

(ICH7M PCI 33MHZ)

0

(INT PU)

(ICH7M,SIO,LPC REF. 14.318MHZ)

(INT PD)

(GMCH G_CLKIN 100 MHZ )

(FROM ICH7 GPIO18 STPPCI* ) (FROM ICH7 GPIO20 STPCPU* )

(ITP HOST 133/167MHZ)

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(CPU HOST 133/167MHZ)

(INT PD)

(INT PU)

PIN 6

* FOR INT. GRAPHIC SYSTEM

SRCT0

DOT96C

PIN 7

PIN 11 100MC_SST

FCTSEL1

00 0 1 1 1 1

27M SPREAD

TBD

SRCT0

SRCC0

FCTSEL0

(ICH SATA 100 MHZ)

(TPM LPC 33MHZ) (SMC LPC 33MHZ)

(EACH POWER PIN PLACED ONE 0.1UF)

(INT PU) (INT PU)

(GPU PCI-E 100 MHZ )

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?

(ICH7M DMI 100 MHZ )

(FROM ICH7 GPIO35)

(FROM GMCH CLK_REQ*)

(WIRELESS PCI-E 100 MHZ )

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

(FROM CPU VCORE PWR GOOD) (ICH7M USB 48MHZ)

(FOR PCI-E CARD)

(FW PCI 33MHZ)

6.3V

20%

10UF

X5R 603

2

1

C3309

402

16V X5R

10%

0.1UF

2

1

C3305

0.1UF

10%

402

X5R

16V

2

1

C3306

402

10%

0.1UF

X5R

16V

2

1

C3307

X5R

16V 402

10%

0.1UF

2

1

C3308

NO STUFF

1/16W 402

475

1% MF-LF

2

1

R3300

603

X5R

6.3V

10UF

20%

2

1

C3312

10% X5R

402

0.1UF

16V

2

1

C3311

402

10% 16V X5R

0.1UF

2

1

C3304

X5R

16V 402

0.1UF

10%

2

1

C3303

0.1UF

10% 16V X5R 402

2

1

C3302

402

X5R

16V

0.1UF

10%

2

1

C3301

402

10% CERM

6.3V

1UF

2

1

C3310

10UF

6.3V

20% X5R

603

2

1

C3316

10% X5R

16V 402

0.1UF

2

1

C3315

402

6.3V CERM

10%

1UF

2

1

C3314

1

MF-LF

5%

1/16W

402

21

R3303

X5R

10UF

20%

6.3V 603

2

1

C3317

1/16W 402

MF-LF

5%

10K

2

1

R3301

14.31818

5X3.2-SM

CRITICAL

21

Y3301

CRITICAL

SLG8LP436

QFN

OMIT

50

51

2

31

52

66

62

46

39

5

352817

12

49

67

61

43383

69

32 33

30 29

27 26

24 23

22 21

19 18

16 15

14 13

11 10

48

47

53

54

1

68

56

65

64

63

58

57

40

8

7 6

55

36 37

41 42

44 45

34

25

60

20

59

9

4

U3301

0402-LF

FERR-120-OHM-1.5A

21

L3302

0402-LF

FERR-120-OHM-1.5A

21

L3301

12PF

402

CERM

5% 50V

2

1

C3389

12PF

5% CERM

402

50V

2

1

C3390

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

CLOCKS

8433

051-7150 A.0.0

CK410_XTAL_IN CK410_XTAL_OUT

=PP3V3_S0_CK410

CK410_PCIF1_CLK

CK410_PCI4_CLK

CK410_PCI3_CLK

CK410_FSB_TEST_MODE

CK410_CLK14P3M_TIMER

CK410_USB48_FSA

CK410_PD_VTT_PWRGD_L

CK410_DOT96_27M_P

CK410_SRC8_P

CK410_SRC8_N

CK410_SRC7_P

CK410_SRC7_N

CK410_SRC_CLKREQ6_L

CK410_SRC6_N CK410_SRC6_P

CLK_NB_OE_L

CK410_SRC5_P

CK410_SRC5_N

SB_CLK100M_SATA_OE_L

CK410_SRC4_P

CK410_SRC4_N

CK410_SRC_CLKREQ3_L

CK410_SRC2_P

CK410_SRC2_N

CK410_SRC_CLKREQ1_L

CK410_SRC1_P

CK410_SRC1_N

CK410_LVDS_P

CK410_LVDS_N

CK410_CPU2_ITP_SRC10_P

CK410_CPU2_ITP_SRC10_N

CK410_CPU1_N

PM_STPCPU_L

PM_STPPCI_L

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm

VOLTAGE=3.3V

PP3V3_S0_CK410_VDD_REF

CK410_CPU1_P

CK410_CPU0_N

CK410_REF1_FCTSEL0

CK410_DOT96_27M_N

CK410_SRC_CLKREQ8_L

CK410_CPU0_P

CK410_SRC3_N CK410_SRC3_P

CK410_PCI5_FCTSEL1

CK410_PCIF0_CLK

CK410_PCI1_CLK

CK410_IREF

CK410_PCI2_CLK

SMB_CK410_DATA

SMB_CK410_CLK

PP3V3_S0_CK410_VDD48_PCI

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm

=PP3V3_S0_CK410

PP3V3_S0_CK410_VDD_CPU_SRC_A

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm

VOLTAGE=3.3V

65B3

34A8

33D8

33D3

5A7

33D3

34D8

34B8

34C8

26A8

34B5

34C5

34B5

34A4

34D5

14B6

34C5

23C3

34C5

34A4

34C5

34A4

34B5

34D5

23C8

34D5

34A8

34B5

34A4

34D5

34B5

34C5

34A8

34D8

27D6

33C7

http://mycomp.su/x/

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUTOUT

OUT

IO

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(TO ICH7M USB 48MHZ)

(PORT80 LPC 33MHZ)

(TO ICH7M PCI 33MHZ)

(TO SMC PCI 33MHZ)

(TO TPM PCI 33MHZ)

(TO FIREWIRE PCI 33MHZ)

as possible to the resistors

caps should be close

PLACEMENT of these

(TO MCH FS_C)

(ICH7M 14.318MHZ)

(FROM CPU FS_C)

(TO MCH FS_A)

NEED TO CHECK THE BSEL PULLS

(TO MCH FS_B)

(FROM CPU FS_B)

(FROM CPU FS_A)

(GPU PCI-E Graphics 100MHz)

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED

RESERVED

400M

1

FS_A

(WIRELESS PCI-E MINI 100MHZ)

(ITP HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)

(ExpressCard Slot)

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

(ICH7M DMI 100MHZ)

(GMCH G_CLKIN 100MHZ)

266M 133M

#

# 1

0

333M

100M

111

11

1

0

00

0

00

0

FS_C

CPU

FS_B

0

(Yukon PCI-E 100MHZ)

(GPU 27MHz Spread / Non-Spread)

200M

166M

(ICH7M SATA 100MHZ)

(CPU HOST 133/167MHZ)

GPU CLK OE*

Yukon CLK OE*

(NB CRT/TV GRAPHICS DOTCLK 100MHZ)

(NB LVDS GRAPHICS 100MHZ)

39C6

22C2

MF-LF

33

402

5%

1/16W

21

R3429

1/16W

5%

402

MF-LF

33

TPM

21

R3430

33

MF-LF

402

5%

1/16W

21

R3433

33

1/16W

402

5%

MF-LF

21

R3432

37B6

58C6

49C7

22A6

51C5

5C2

402

33

MF-LF

5%

1/16W

21

R3463

22C2

5% MF-LF

10K

402

1/16W

2

1

R3467

1/16W

5%

402

MF-LF

10K

2

1

R3466

MF-LF

1/16W

5%

402

1K

2

1

R3469

1/16W

5%

402

MF-LF

1K

21

R3468

1/16W

5%

402

MF-LF

1K

21

R3472

1/16W

5%

402

MF-LF

1K

2

1

R3470

1/16W

5%

402

MF-LF

1K

21

R3471

1/16W

5%

402

MF-LF

1K

2

1

R3473

1/16W

5%

402

MF-LF

1K

21

R3475

1/16W

5%

402

MF-LF

1K

21

R3474

23D3

21B6

5A7

21B6

5A7

NOSTUFF

1/16W

5%

MF-LF

1K

402

2

1

R3480

1/16W

5%

402

MF-LF

33

21

R3476

1/16W

5%

402

MF-LF

0

21

R3450

1/16W

5%

402

MF-LF

0

21

R3453

1/16W

5%

402

MF-LF

1K

NOSTUFF

2

1

R3454

1/16W

5%

402

MF-LF

0

21

R3451

NOSTUFF

1/16W

5%

402

1K

MF-LF

2

1

R3452

47B3

5B1

47B3

5B1

12A6

7C6

5%

1K

1/16W

402

MF-LF

21

R3486

5%

1K

MF-LF

1/16W

402

21

R3485

7C6

84C6 11B3

MF-LF

402

1/16W

0

5%

21

R3424

5%

0

1/16W

402

MF-LF

21

R3425

1/16W

5%

0

402

MF-LF

NO STUFF

21

R3443

NO STUFF

5% 1/16W MF-LF

402

0

21

R3444

1%

71.5

1/16W

402

MF-LF

NO STUFF

21

R3402

1%

71.5

1/16W

402

MF-LF

21

R3405

1%

121

MF-LF

402

1/16W

21

R3418

56

5% 1/16W

402

MF-LF

21

R3419

MF-LF

5% 1/16W

402

100K

NO STUFF

2

1

R3426

NOSTUFF

5%

15PF

402

CERM

50V

2

1

C3404

NOSTUFF

5%

15PF

50V CERM 402

2

1

C3403

NOSTUFF

5%

15PF

50V CERM 402

2

1

C3402

NOSTUFF

5%

15PF

CERM 402

50V

2

1

C3401

NOSTUFF

15PF

5% 50V CERM 402

2

1

C3400

1/16W

5%

402

MF-LF

33

21

R3417

1/16W

5%

402

MF-LF

2.2K

21

R3401

051-7150 A.0.0

8434

SYNC_MASTER=M59_MG

SYNC_DATE=05/07/2006

Clock Termination

GPU_CLK27MSS_IN

GPU_CLK27MGPU_CLK27M

CK410_DOT96_27M_P

GPU_CLK27MSS_IN

CK410_DOT96_27M_N

NB_CLK_DREFCLKIN_N

CK410_SRC_CLKREQ1_L

CK410_SRC_CLKREQ8_L

CK410_SRC_CLKREQ6_L

MINI_CLKREQ_L

MAKE_BASE=TRUE

CK410_SRC_CLKREQ3_L

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

CK410_27M_SPREAD

MAKE_BASE=TRUE

CK410_27M_NONSPREAD

MAKE_BASE=TRUE

=PP3V3_S0_CK410

CK410_REF1_FCTSEL0

CK410_PCI5_FCTSEL1

CK410_SRC1_P

CK410_CPU0_P

MAKE_BASE=TRUE

FSB_CLK_CPU_P

CK410_CPU0_N

MAKE_BASE=TRUE

FSB_CLK_CPU_N

CK410_CPU1_P

MAKE_BASE=TRUE

FSB_CLK_NB_P

CK410_CPU2_ITP_SRC10_P

MAKE_BASE=TRUE

CPU_XDP_CLK_P

CK410_CPU2_ITP_SRC10_N

MAKE_BASE=TRUE

CPU_XDP_CLK_N

CK410_SRC6_P

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_P

CK410_SRC5_P

MAKE_BASE=TRUE

NB_CLK100M_GCLKIN_P

MAKE_BASE=TRUE

NB_CLK100M_GCLKIN_N

CK410_SRC2_P

MAKE_BASE=TRUE

SB_CLK100M_DMI_P

CK410_SRC8_P

MAKE_BASE=TRUE

ENET_CLK100M_PCIE_P

CK410_SRC8_N

MAKE_BASE=TRUE

ENET_CLK100M_PCIE_N

CK410_SRC3_P

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

CK410_SRC3_N

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

CK410_SRC1_N

CK410_LVDS_N

NB_CLK_DREFSSCLKIN_N

MAKE_BASE=TRUE

CK410_LVDS_P

MAKE_BASE=TRUE

NB_CLK_DREFSSCLKIN_P

CK410_SRC2_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_N

CK410_SRC6_N

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_N

MAKE_BASE=TRUE

SB_CLK100M_SATA_N

CK410_SRC4_N

MAKE_BASE=TRUE

FSB_CLK_NB_N

MAKE_BASE=TRUE

SB_CLK100M_SATA_P

CK410_CPU1_N

CK410_SRC4_P

NB_CLK_DREFCLKIN_N

CK410_SRC7_P

CK410_SRC7_N

NB_CLK_DREFCLKIN_P

PP1V5_S0_NB_VCCA_DPLLA

CK410_SRC5_N

CK410_PCIF0_CLK

CK410_PCIF1_CLK

CK410_PCI1_CLK

CK410_PCI2_CLK

CK410_PCI4_CLK

CK410_PCI3_CLK

=PP1V05_S0_FSB_NB

CK410_USB48_FSA

CPU_BSEL_R<0>

CPU_BSEL_R<1>

CPU_BSEL_R<2>

CK410_CLK14P3M_TIMER

SB_CLK48M_USBCTLR

CPU_BSEL<0>

CPU_BSEL<1>

NB_BSEL<1>

CPU_BSEL<2>

NB_BSEL<2>

CK410_FSB_TEST_MODE

SB_CLK14P3M_TIMER

NB_BSEL<0>

MAKE_BASE=TRUE

TP_CK410_PCI4_CLK

PCI_CLK_PORT80_LPC

PCI_CLK_SB

PCI_CLK_FW

PCI_CLK_TPM

PCI_CLK_SMC

65D6

34C8

34C6

34C8

34B8

34C6

65B3

19D7

33D8

47C3

12C2

71C5

71C2

71C5

34B4

47C6

33D3

33B4

33C4

33B4

5B1

33B4 14C4

14C4

33B4

33A4

33B4

67A5

67A5 33B4

33B4 14C4

33B4 14B4

33B4

5B1

33B4

33C4

33B4

34B2

34B4

19A6

33B4

33B6

12B7

34B4

34B2 33A4

14C4

33B4

33A4

33B4

5C1

33B4

5C1

33C7

33A4

33B6

14C4

33B4

14C4

17C6

33B7

33B6

12A7

33A4

23D3

7B4

14C6

7B4

14C6

33C6

14C6

http://mycomp.su/x/

NC7

NC6

NC5

NC4

NC2 NC3

OUT

VDD

NC0 NC1

VIO

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC NC

NC

NC NC

SMC G3Hot Oscillator

TPM Crystal Circuit

NC NC

TPM

32.768K

CRITICAL

SM-2

31

42

Y3720

TPM

MF-LF

1/16W

0

402

5%

21

R3721

10M

NO STUFF

MF-LF

402

5%

1/16W

2

1

R3720

32.768KHZ-9-3.6V

CRITICAL

SG-3040LC-SM

1

12

7

11

10

9

8

5

4

3

2

6

U3750

0.1uF

20%

402

CERM

10V

2

1

C3751

FERR-EMI-100-OHM

SM

21

L3750

6.3V

603

CERM

20%

4.7uF

2

1

C3750

402

22

MF-LF

1/16W

5%

21

R3750

TPM

5%

402

CERM

50V

15pF

21

C3720

TPM

50V

5%

402

CERM

15pF

21

C3721

35 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Mobile Clocking

TPM_XTALI

TPM_XTALO_R

SMC_CLK32K_SUSCLK_R

=PP3V42_G3H_SMC_CLK

TPM_XTALO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V42_G3H_SMC_CLK_F

VOLTAGE=3.425V

MAKE_BASE=TRUE

SMC_CLK32K_SUSCLK

SMC_SUS_CLK

58C6

65D3

58C6

49C5

http://mycomp.su/x/

IN

IO

IN

IO

IN

OUT

G

D

S

IN

IO

IO IO

IO

IO IO

IN

OUT

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(UATA_HSTROBE)

(UATA_STOP)

(UATA_DSTROBE)

NC

(UATA_CS1*)

Indicates disk presence

516S0335

IDE (ODD) Connector

Placement note

Place within 12.7mm from ball of SB

(UATA_CS0*)

Counters 10K pull-up to 5V in ODD to keep SB GPIO <= 3.3V

5%

MF-LF 402

100

1/16W

2

1

R3850

CRITICAL

M-ST-SM1-LF

9

8

7

6

50

5

49

48 47

46 45

44

43 42

41

40

4

39

38

37 36

35 34

33

32 31

30

3

29 28

27

2625

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3800

402

MF-LF

1/16W

24.9

1%

2

1

R3860

5%

4.7K

NO STUFF

MF-LF

402

1/16W

2

1

R3801

1/16W

5% MF-LF

4.7K

402

2

1

R3802

1/16W

5%

402

MF-LF

6.2K

2

1

R3803

1/16W

5%

402

MF-LF

33K

2

1

R3810

CRITICAL

FDZ293P

BGA

B3

B2

B1

A3

A2

A1

C3

C2

C1

Q3820

10K

MF-LF

402

5%

1/16W

2

1

R3820

0.22uF

20%

6.3V X5R 402

21

C3821

1/16W

5%

402

MF-LF

10K

2

1

R3821

1/16W MF-LF

402

5%

15K

2

1

R3811

SYNC_DATE=(MASTER)

PATA Connector

051-7150 A.0.0

36 84

SYNC_MASTER=(MASTER)

IDE_PDD<12>

SATA_RBIAS_N

SATA_RBIAS_P

IDE_PDA<1>

IDE_PDCS3_L

IDE_PDD<11>

IDE_PDD<14>

SATA_A_R2D_C_N

SATA_C_DET_L

SATA_A_R2D_C_P

MAKE_BASE=TRUE

TP_SATA_A_R2DP

SATA_A_D2R_P

MAKE_BASE=TRUE

TP_SATA_A_D2RP

SATA_A_D2R_N

MAKE_BASE=TRUE

TP_SATA_A_D2RN

MAKE_BASE=TRUE

TP_SATA_A_R2DN

MAKE_BASE=TRUE

SATA_RBIAS

ODD_PWR_EN_L

IDE_PDD<13>

=PP5V_S0_IDE

IDE_PDD<3>

=PP3V3_S0_IDE

IDE_PDD<6>

IDE_PDD<4>

IDE_PDIOR_L

IDE_PDIOW_L

IDE_PDD<1>

IDE_PDD<0>

ODD_PWR_EN_L_RC

IDE_PDD<7>

IDE_PDD<5>

IDE_PDD<15>

IDE_PDCS1_L

IDE_PDA<2>

SMC_ODD_DETECT

IDE_PDDREQ

IDE_PDD<2>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<8>

VOLTAGE=5V

PP5V_S0_IDE_ODD

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

IDE_PDIORDY

IDE_RESET_L

IDE_IRQ14

IDE_PDDACK_L

IDE_PDA<0>

21B5

21B6

21B5 21B5

21B5

21B6

23D2

21B6

22A6

21B5

65B1

21B5

65B3

21B5

21B6

21B5

21C5

21B5

49B7

21B6

21B5

21B6

23C3

21B6

21B6 21B5

http://mycomp.su/x/

IO

IO IO

IO

OUT

IN

OUT

IO

OUT

IN IN

IO IO

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28 PCI_AD29

PCI_AD27

PCI_AD25 PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

IN

D

S

G

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GPIO

MFUNC as a

Might use

when there’s no power on VCCP

G_RST* is clamped to VCCP

aliased to the same rail)

It must not be taken high

(OK if VCCP and VCC are

G_RST* assertion min 2ms

THIS IS FROM ICH-7M

Gated Platform Reset Option

From PCI clock generator via 33 Ohms

RC Reset Option

X5R

10V

1uF

10%

402

2

1

C3908

10%

1uF

X5R 402

10V

2

1

C3909

10V

402

X5R

1uF

10%

2

1

C3904

1uF

10% X5R

402

10V

2

1

C3903

402

X5R

10%

1uF

10V

2

1

C3902

402

X5R

10V

1uF

10%

2

1

C3901

1uF

402

10V X5R

10%

2

1

C3900

4.7K

5% 1/16W MF-LF 402

2

1

R3902

1/16W MF-LF

402

5%

4.7K

2

1

R3901

220

402

MF-LF

1/16W

5%

2

1

R3990

1K

402

MF-LF

1/16W

5%

2

1

R3980

220

5% 1/16W MF-LF 402

2

1

R3991

10K

5% 1/16W MF-LF 402

2

1

R3910

1/16W

402

MF-LF

1K

1%

21

R3904

10% 10V

1UF

X5R 402

2

1

C3977

0

402

MF-LF

1/16W

5%

21

R3879

(2 OF 2)

BGA

CRITICAL

TSB83AA22AZAJ

F11

E11

J11

J7J6H11

F5E5D9D8D5

C4

C3

C2

G12

G11

A3

B6

D4

A2

B4

B7

A11

B12

C11

B10

B9

C13

E12

E13

F12

F13

J5

L5

L7

D1

F3 J13

F4

L6

N3

K4

B3

L2

E3

L3

N2

D3

K2

K5

M3

N8

M8

L8

N9

M9

K12

M10

G4

F2

N10

F1

H1

G3

H2

J3

H4

H3

J4

L1

M1

M11

M2

L4

N1

K3

M5

K8

K9

M7

M6

N6

N11

L12

N12

A1

F6

E10

E9E8E7E6D7

K10

J10

J9

J8

H10

H9H8H7D6H6

G10

G9G8G7

G6

F10

F9F8F7

C8

C7

E4

U3900

10K

1/16W

402

MF-LF

5%

2

1

R3977

50V

10%

0.001uF

402

CERM

2

1

C3979

10K

5% 1/16W MF-LF

402

21

R3979

SOT23-LF

2N7002

2

1

3

Q3970

22

MF-LF

402

5%

1/16W

21

R3900

16V

10%

402

X5R

0.1uF

2

1

C3910

402

X5R

16V

10%

0.1uF

2

1

C3911

402

MF-LF

5%

1/16W

100

21

R3903

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

37 84

A.0.0051-7150

FireWire Link (TSB83AA22)

=PP3V3_S3_FW

FW_SDA

FW_SCL

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<31>

PCI_AD<30>

PCI_AD<28> PCI_AD<29>

PCI_AD<27>

PCI_AD<25> PCI_AD<26>

PCI_AD<24>

PCI_AD<23>

PCI_AD<21>

PCI_AD<20>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_PAR

PCI_CLK_FW FW_PCI_IDSEL

PCI_AD<1>

PCI_AD<0>

FW_MFUNC

FW_G_RST_L

=PP1V8_S3_FW

FW_LLC_PP1V8LDO_EN_L

FW_PINT

CLKFW_LINK_PCLK

FW_LREQ

FW_LPS

FW_PHY_LKON

CLKFW_PHY_LCLK

FW_DATA<7>

FW_DATA<6>

FW_DATA<5>

FW_DATA<4>

FW_DATA<3>

TP_FW_DATA<1>

FW_DATA<2>

TP_FW_DATA<0>

TP_FW_CTL<1>

TP_FW_CTL<0>

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_FW_L

PCI_REQ64_L

=FW_PCI_REQ_L

PCI_PME_FW_L

PCI_PERR_L

PCI_IRDY_L

INT_PIRQD_L

=FW_PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

=PP3V3_S3_PCI

PCI_C_BE_L<0>

PCI_C_BE_L<3>

PCI_AD<22>

PCI_C_BE_L<2>

PCI_C_BE_L<1>

=SMC_FWRSTGATE_L

PLT_RST_BUF_L

FW_G_RST_L_R

FW_G_RST_L

SMC_RSTGATE_RC_L

=PP3V3_S3_FW

PCI_RST_L

=FW_PCI_IDSEL

FW_LKON

=PP3V3_S3_FW

65C3

37C3

22A7

26D2

37D7

38C3

37D7

37A7

6B7

22B7

22A7

22B7

22A6

34D6

22B7

37A5

65B6

38C3

38C5

38B6

22A6

6B6

22B5

22A6

22A7

6B6

22A7

22A6

65C3

22B6

22A7

22B6

6B6

26B3

37B2

37C3

22A6

6B6

38A3

37A7

http://mycomp.su/x/

SE

SM

RESET

D7

D5 D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0 PC1

LREQ

LPS

DS1 LCLK

DS0

XI

R1

R0

TESTM TESTW

TPBIAS0 TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

IO

OUT

TRI-ST/NC

VCC

GND

IN

IN IO

OUT

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

1MA (MAX) BUS HOLDERS

SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’) IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE

NC

RESET PULSE WHEN PHY FIRST RECEIVES POWER

CAPACITOR IN CONJUCTION WITH INTERNAL PULLUP PROVIDES

DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)

FW_A is DS_ONLY

FW_B is BILINGUAL

X5R

0.22uF

402

20%

6.3V

2

1

C4050

390K

1/16W

5%

402

MF-LF

21

R4055

TSB83AA22AZAJ

(1 OF 2)

BGA

CRITICAL

A9

K1

D2

G2 G1

C1 B1

J2 J1

E1

E2

N7

L11

B5

A4

L10

A13

A12

A8

A7

A10

M13

K11

H13

N5

M4

N4

K13

N13

L13

G13

C6C5K6

K7

J12

H12

D12

B8

A6

B11

B13

C12

C10

C9

D13

A5

M12

L9

H5G5D11

D10

U3900

20%

402

0.01uF

16V CERM

2

1

C4010

10V X5R

10%

1uF

402

2

1

C4002

402

X5R

10V

10%

1uF

2

1

C4021

6.34K

1%

1/16W

402

MF-LF

12

R4062

X5R

10V

402

10%

1uF

2

1

C4001

1uF

10V X5R

10%

402

2

1

C4003

X5R

10%

1uF

402

10V

2

1

C4004

10V X5R

10%

1uF

402

2

1

C4011

10V X5R

10%

1uF

402

2

1

C4012

402

1uF

10% X5R

10V

2

1

C4013

402

1uF

10% X5R

10V

2

1

C4014

CRITICAL

98P3040MHZ

SM

4

13

2

G4080

1K

402

5% 1/16W MF-LF

2

1

R4045

1/16W

5%

402

MF-LF

1K

2

1

R4042

1uF

X5R 402

10% 10V

2

1

C4031

X5R

10V

10%

1uF

402

2

1

C4030

603

CERM1

6.3V

2.2uF

10%

2

1

C4035

MF-LF

402

5%

1/16W

10K

2 1

R4056

MF-LF

402

5%

1/16W

4.7

21

R4086

1K

NO STUFF

MF-LF

402

1%

1/16W

2

1

R4063

402

1

MF-LF

1/16W

5%

21

R4000

1

402

MF-LF

1/16W

5%

21

R4035

402

MF-LF

1/16W

5%

1

21

R4020

5%

22

402

MF-LF

1/16W

21

R4080

6.3V

20%

0.22uF

402

X5R

2

1

C4080

MF-LF 402

1/16W

470

1%

1

2

R4061

1/16W

1K

5% MF-LF

402

2

1

R4091

MF-LF

1K

402

5% 1/16W

2

1

R4040

5%

1K

1/16W

402

MF-LF

2

1

R4090

FireWire PHY (TSB83AA22)

SYNC_DATE=(MASTER)

051-7150 A.0.0

8438

SYNC_MASTER=(MASTER)

FW_A_DS

=PP3V3_FWPHY

FW_PHY_RESET_L

FW_DATA<7>

FW_DATA<5> FW_DATA<6>

FW_DATA<4>

FW_DATA<3>

FW_DATA<2>

FW_CPS

FW_BMODE

=FW_PC0

FW_LREQ

FW_LPS

FW_B_DS CLKFW_PHY_LCLK

CLK98P304_FW_XI

FW_R1

FW_R0

FW_TESTM FW_TESTW

FW_A_TPBIAS FW_B_TPBIAS

FW_B_TPB_N

FW_A_TPB_N

FW_A_TPB_P

FW_B_TPA_N

FW_B_TPA_P

FW_A_TPA_P FW_A_TPA_N

FW_PINT

CLKFW_LINK_PCLK

VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm

PP3V3_FWPHY_AVDD

MIN_NECK_WIDTH=0.22 mm

=PP1V95_FWPHY

VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm

PP3V3_FWPHY_PLLVDD

MIN_NECK_WIDTH=0.25 mm

PP1V95_FWPHY_PLLVDD

VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm

FW_LKON

FW_B_TPB_P

=PPFW_FW_CPS

FW_LKON

=PP1V8_FWPHY_OSC

CLK98P304M_FW_XI_R

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.83V

PP1V8_FWPHY_OSC

44B8

38A3

38C3

6C6

37C4

44B8

37C4

44D7

44B7

44C7

44B7

44C7

37C4

6B6

37C3

44B7

65C1

37C3

6B6

http://mycomp.su/x/

OUT

AVDDL0

AVDDL4

AVDD

THRML_PAD

VDDO_TTL0

AVDDL6

VDDO_TTL1

RX_N

TESTMODE

TSTPT

LINK*

LED_LINK10/100* LED_LINK1000*

LED_ACT*

RSET

CTRL25 CTRL12

HSDACN

HSDACP

SWITCH_VAUX

SWITCH_VCC

VMAIN_AVLBL

VAUX_AVLBL

LOM_DISABLE*

XTALO

XTALI

SPI_DO

SPI_CLK

SPI_CS

SPI_DI

VPD_CLK

VPD_DATA

MDIP3 MDIN3

MDIN2

MDIP2

MDIN1

MDIP1

MDIN0

MDIP0

WAKE*

REFCLKN

TX_N

VDDO_TTL3

VDDO_TTL2

VDDO_TTL4

VDD0

VDD1

VDD3

VDD2

VDD6

VDD5

VDD4

VDD7

AVDDL1

AVDDL2

AVDDL5

VDD25

PERST*

REFCLKP

RX_P

AVDDL3

TX_P

PU_VDDO_TTL0 PU_VDDO_TTL1

TEST

TWSI

SPI

MAIN CLK

PCI EXPRESS

ANALOG

MEDIA

LED

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

IN IN

IO IO

IO

IO IO

IO

G

D

S

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC NC

PLACE C4113 AND C4112 WITHIN 12 MIL OF U2100 E27 AND E28

OPTIONAL EXTERNAL LDO

PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

ASF IS UNAVAILABLE ON 8053

TRACE LENGTH <12MIL

PLACE RESISTORS CLOSE TO U4101

PLACE C4140 NEAR U4102 VCC

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

NO PULL-UP NEEDED

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

SCHEME MATCHES DOC MVL100258-01

PLACE C4110 AND C4111 WITHIN 12 MIL OF U4101 PIN 49 AND 50

PLACE C4107 NEAR U4101 AVDD

SCHEME MATCHES DOC MVL100258-01SCHEME MATCHES DOC MVL100258-01

NC

2. DO NOT ROUTE UNDER CRYSTAL

NC

1. KEEP ENET_XTALI AND ENET_XTALO

NC

INTERNAL PULL-UP

NC

to arbitrary value

Setting attribute VOLTAGE to help constraint manager

find correct topolgy

27pF

50V CERM

5%

402

2

1

C4151

10K

5%

402

MF-LF

1/16W

21

R4122

10K

1/16W

402

5%

MF-LF

21

R4123

402

16V X5R

10%

0.1UF

2

1

C4101

CRITICAL

OMIT

QFN

88E8053

14

15

6

41

38

47

614540

8

1

58484439336413

7

2

12

49 50

29

65

46

11

9

34

35

36

37

54

53

16

55 56

43

42

5

30

26

20

17

31

27

21

18

10

63

62

60

59

24

25

4

3

57525132282219

23

U4101

16V

10%

0.1UF

402

X5R

2

1

C4140

OMIT

M24C08

CRITICAL

SO8

7

4

8

5

6

2

1

3

U4102

1/16W

1%

4.87K

MF-LF

402

21

R4102

0.1UF

X5R 402

10% 16V

2

1

C4107

402

10% 16V X5R

0.1UF

21

C4110

16V

10%

0.1UF

402

X5R

21

C4111

10%

0.1UF

402

16V

X5R

21

C4112

402 X5R 16V 10%

0.1UF

21

C4113

402

MF-LF

1%

49.9

1/16W

2

1

R4106

402

1% 1/16W MF-LF

49.9

2

1

R4117

402

MF-LF

1/16W

49.9

1%

2

1

R4118

1%

49.9

1/16W MF-LF 402

2

1

R4119

402

1/16W

1%

MF-LF

49.9

2

1

R4120

MF-LF

49.9

402

1% 1/16W

2

1

R4103

402

MF-LF

1/16W

1%

49.9

2

1

R4104

402

MF-LF

1/16W

1%

49.9

2

1

R4105

0.001UF

CERM 402

10% 50V

2

1

C4116

402

10%

0.001UF

50V CERM

2

1

C4118

0.001UF

CERM

10%

402

50V

2

1

C4117

402

50V

10%

CERM

0.001UF

2

1

C4115

402

CERM

6.3V

10%

1UF

2

1

C4100

4.7K

5% 1/16W MF-LF 402

2

1

R4131

402

MF-LF

1/16W

5%

4.7K

2

1

R4130

SOT23-LF

2N7002

2

1

3

Q4100

4.7K

5%

402

MF-LF

1/16W

2

1

R4101

0402-LF

FERR-120-OHM-1.5A

21

L4100

100K

5% 1/16W MF-LF

402

2

1

R4132

0.001UF

CERM

10% 50V

402

2

1

C4105

X5R

10%

0.1UF

16V

402

2

1

C4104

402

0.1UF

X5R

10% 16V

2

1

C4103

10%

0.1UF

X5R 402

16V

2

1

C4102

0.001UF

402

CERM

50V

10%

2

1

C4106

402

16V

0.1UF

X5R

10%

2

1

C4128

0.001UF

10%

402

50V CERM

2

1

C4133

50V 402

CERM

0.001UF

10%

2

1

C4134

402

CERM

0.001UF

10% 50V

2

1

C4131

10%

0.001UF

CERM 402

50V

2

1

C4132

16V

10% X5R

402

0.1UF

2

1

C4127

10% X5R

402

16V

0.1UF

2

1

C4126

16V 402

X5R

0.1UF

10%

2

1

C4129

16V

10%

402

X5R

0.1UF

2

1

C4130

402

CERM

10% 50V

0.001UF

2

1

C4139

0.001UF

50V CERM 402

10%

2

1

C4138

16V

0.1UF

X5R 402

10%

2

1

C4137

402

10% X5R

0.1UF

16V

2

1

C4136

402

X5R

0.1UF

10% 16V

2

1

C4135

25.0000M

SM-3.2X2.5MM

CRITICAL

3 1

4 2

Y4101

27pF

402

CERM

50V

5%

2

1

C4150

A.0.0051-7150

84

ETHERNET CONTROLLER

39

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

ENET_LOM_DIS_L

=PP3V3_S3_ENET

ENET_LOWPWR_EN

ENET_MDI0

VOLTAGE=1.234V

ENET_MDI1

VOLTAGE=1.234V

=PP3V3_S3_ENET

ENET_XTALO

ENET_XTALI

ENET_MDI_P<3> ENET_MDI_N<3>

ENET_MDI_P<1>

PCIE_A_R2D_N

ENET_MDI_P<0>

ENET_VPD_DATA

ENET_PU_VDD_TTL0

ENET_RST_L

ENET_CLK100M_PCIE_N

ENET_CLK100M_PCIE_P

ENET_PU_VDD_TTL1

PCIE_A_D2R_C_P

PCIE_WAKE_L

ENET_PU_VDD_TTL1

=PP3V3_S3_ENET

PCIE_A_R2D_P

ENET_PU_VDD_TTL0

PCIE_A_R2D_C_N

PCIE_A_R2D_C_P

ENET_MDI3

VOLTAGE=1.234V

=PP3V3_S3_ENET

PCIE_A_D2R_C_N

PCIE_A_D2R_N

PCIE_A_D2R_P

=PP3V3_S3_ENET

ENET_VPD_CLK

ENET_CTRL12

=PP1V2_S3_ENET

ENET_MDI_N<1>

ENET_MDI2

VOLTAGE=1.234V

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_CTRL25

ENET_LOM_DIS_L

ENET_MDI_N<0>

=PP1V2_S3_ENET

ENET_RSET

=ENET_VMAIN_AVLBL

=PP3V3_S3_ENET

ENET_VPD_CLK

ENET_VPD_DATA

PP2V5_S3_ENET_AVDD

MIN_NECK_WIDTH=0.22MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=2.5V

=PP2V5_S3_ENET

65D1

39D8

39D6

39D8

39D6

39B8

39D6

39B8

39D6

39B5

47C3

39B8

39B5

39B8

39B4

23C8

39B4

39B5 65D6

40C4

65D6

39B5

39C8

39A5

6C4

39A5

40C4

40B4

40C4

40D4

39A2

39A6

26B1

34C3

39A6

5B1

39B6

39A5

39C6

22D4

39A5

22D4

39B4

39A2

6D4

39D7

40A7

40C4

6D4

39B7

40B7

39A8

64C6

39A5

39C6

40D5

65B6

http://mycomp.su/x/

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

IN

IO

OUT

V-

V+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

to arbitrary value

Setting attribute VOLTAGE to help constraint manager

find correct topolgy

NEAR ENET_MDI_N<0/1>

PLACE C4220 & C4221

- =GND_CHASSIS_ENET

PHY

ETHERNET

BY

- =PP2V5_ENET

(NONE)

Signal aliases required by this page: (NONE)

Power aliases required by this page:

Page Notes

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PROVIDED

PHYSICAL

BOM options provided by this page:

514-0277

Place one cap at each pin of transformer

mirrored on opposite sides of the board

Transformers should be

Place close to connector

Short shielded RJ-45

LAN ENERGY DETECT

0

MF-LF

5%

1/16W

402

NO STUFF

21

R4210

402

CERM

10%

6.3V

1uF

2

1

C4203

402

CERM

10%

6.3V

1uF

2

1

C4202

3KV

10%

1808

CERM

100pF

1 2

C4204

75

5% 1/16W

402

MF-LF

2

1

R4203

75

MF-LF 402

5% 1/16W

2

1

R4202

75

MF-LF

402

5%

1/16W

2

1

R4201

75

402

5%

MF-LF

1/16W

2

1

R4200

CERM

10%

1uF

402

6.3V

2

1

C4201

402

10%

6.3V CERM

1uF

2

1

C4200

1000BT-824-00275

CRITICAL

XFR-SM

13

12

5

4

98

7

6

3

2

16

15

14

11

10

1

T4200

CRITICAL

1000BT-824-00275

XFR-SM

13

12

5

4

98

7

6

3

2

16

15

14

11

10

1

T4201

F-RT-TH-RJ45

JM36113-P2054-7F

CRITICAL

8

7

6

5

4

3

2

1

12

11

10

9

J4200

0.1uF

10% 16V X5R 402

2

1

C4223

MF-LF

100K

1/16W

402

1%

2

1

R4224

402

MF-LF

1/16W

5%

3.3K

2

1

R4223

SM-LF

LMC7211

2

5

1

3

4

U4200

402

MF-LF

1% 1/16W

51.1K

2

1

R4225

5% 50V CERM 402

NO STUFF

100pF

2

1

C4222

MF-LF

2.4K

1/16W

402

5%

21

R4220

402-1

50V

5%

68PF

CERM

21

C4220

2.4K

MF-LF

1/16W

402

5%

21

R4221

402-1

50V

5%

68PF

CERM

21

C4221

1% 1/16W MF-LF 402

470K

2

1

R4227

MMDT3904XF

SOT-363-LF

1

6

2

Q4220

SOT-363-LF

MMDT3904XF

4

3

5

Q4220

1%

MF-LF

392K

1/16W

402

2

1

R4228

MF-LF

10K

5% 1/16W

402

2

1

R4226

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Ethernet Connector

84

051-7150

40

A.0.0

=PP3V3_S0_EDET

EDET_MDIN_AMP

EDET_ACT

EDET_REF

ENETCONN_N<3>

ENET_CTAP0

ED_MDIN_R

ENET_MDI_N<1>

ED_MDIN1_C

VOLTAGE=1.234V

ENET_MDI_N<0>

PP2V5_S3_ENET_AVDD

ENET_CTAP3

ENET_CTAP2

ENETCONN_N<2>

ENET_CTAP_COMMON

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_CTAP1

=GND_CHASSIS_ENET

ENETCONN_P<3>

ENETCONN_N<1>

ENETCONN_N<0>

ENETCONN_P<0>

ENETCONN_P<1>

ENET_100D

ENETCONN

ENETCONN_P<1>

ENET_100D

ENETCONN

ENETCONN_N<3>

ENET_100D

ENETCONN

ENETCONN_N<1>

ENET_100D

ENETCONN

ENETCONN_N<0>

ENET_100D

ENETCONN

ENETCONN_P<0>

ENET_100D

ENETCONN

ENETCONN_P<3>

ENET_100D

ENETCONN

ENETCONN_N<2>

ENET_100D

ENETCONN

ENETCONN_P<2>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENETCONN_P<2>

ED_MDIN0_C

VOLTAGE=1.234V

LAN_ENERGY_DET

40C4

40A7

40B7

65A3

40D7

39C3

39D5

40D7

39C3

6A6

40D7

40C3

40B3

40C3

40D3

40C3

39C3

40D7

23C3

http://mycomp.su/x/

N-CHN

S

D

G

P-CHN

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

G3H 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S5 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS

S0 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S3 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

G3H Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S5 Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S5 AC 0V 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS

1.2V enable has pull-up to 3.3V

Yukon Power Control

When ENETPWR_S3AC BOMOPTION is active:

When ENETPWR_S3 BOMOPTION is active:

Allows powering Yukon down during battery sleep to save power

470K

402

MF-LF

1/16W

5%

2

1

R4302

402

5% 1/16W

100K

MF-LF

2

1

R4304

5% 1/16W MF-LF

402

ENETPWR_S3AC

0

21

R4300

ENETPWR_S3

5% 1/16W MF-LF 402

0

2

1

R4301

FDG6332C_NL

SC70-6

1

2

6

Q4300

FDG6332C_NL

SC70-6

4

5

3

Q4300

SOT23-LF

2N7002

2

1

3

Q4302

2N7002

SOT23-LF

2

1

3

Q4304

41 84

A.0.0051-7150

Yukon Power Control

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

FWPWR_EN_L

=PPBUS_G3H_S3AC

PM_SLP_S4_L

FWPWR_EN_L_OR_GND

=PP3V3_S3AC_FET

=PP3V3_S3_P3V3S3AC

P1V2S3_RUNSS

PM_SLP_S3BATT

=P2V5S3_EN

PPVIN_S3_P2V5S3_SVIN

PM_SLP_S3BATT_L

MAKE_BASE=TRUE

64B8 49C5

61B7

43C7

65C1

23C3

65D3 65C3

5D7

61D8

61D6

http://mycomp.su/x/

OUT

IN

NR

NC

THRML

EN

GND

PAD

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Vout = 1.95V

(Regulator limit)

400mA max output

(Switcher limit)

200mA max output

165MA MAX LOAD

1.95V Supply for FW PHY

Vout = 1.25V * (1 + Ra / Rb)

NC

<Ra>

NC

<Rb>

3.3V Supply for FWPHY

PBUS S0 FET

Vout = 3.316

20%

2.2uF

402

X5R

4V

2

1

C4422

10% 16V

CERM

402

0.01uF

2

1

C4421

10%

6.3V

1uF

CERM

402

2

1

C4420

SON

TPS799195

CRITICAL

7

1 2

5

6

3

4

U4420

324K

1/16W

1%

402

MF-LF

2

1

R4410

196K

1/16W

1%

402

MF-LF

2

1

R4411

5%

402

CERM

22pF

50V

2

1

C4410

0.22uF

X5R 402

20%

6.3V

2

1

C4405

4.7UF

50V

1206

10%

X7R-CERM

2

1

C4400

LT3470

TSOT23-8

CRITICAL

3

5

1

2

4

8

6

7

U4400

SC-59

SMD20E40C-X-F

3

2

1

D4400

CDPH4D19F-SM

33uH

CRITICAL

21

L4400

22UF

20%

6.3V X5R 805

2

1

C4401

IRLML6302PBF

SOT23

2

1

3

Q4450

402

MF-LF

1/16W

5%

470K

2

1

R4450

330K

5% 1/16W MF-LF

402

2

1

R4451

SOT23-LF

2N7002

2

1

3

Q4451

402

CERM

50V

10%

0.0022UF

2

1

C4450

FW PHY Power Supply

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

8442

PPBU_S0_FW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

=PP3V3_FWPHY_REG

=PPFW_P3V3FWPHY

PPBU_S0_FW

PP5VR33V_FWPHY3V3

FWPHY3V3_BOOST

FWPHY_CORE_NR

=PP3V3_FWPHY_CORE

FWPHY3V3_FB

FWPHY3V3_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

=PPBUS_S0_PPBU_S0_FW

PM_SLP_S3_L

PPBU_S0_FW_EN

PPBU_S0_FW_EN_DIV

=PP1V95_FWPHY_CORE_LDO

64C8 49C5 43B7

42C8

6C8

65C1

42B6

6C6

65C1

23C3

6B8

http://mycomp.su/x/

G

D

S

G

D

S

V-

V+

G

D

S

G

D

S

NC

GATE2

OR_ADJ

IFAULT*

ILIM

GND

ON

LATCH

TIM

ONQ1

SENSE

GATE1

OUT

IN

SGD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0.030 ohm => 1.66A (ideal)

0.020 ohm => 2.4A

0.025 ohm => 2A

0.033 ohm => 1.5A

Current Limit determined by R4500

UL compliance for single-point failure protection

for redundancy and

Q4501 is a dual FET

FWLATEVG_3V_REF Hysteresis:

Current Limit/Active Late-VG Protection

2.81V on late Vg event and port power is off

is running or on AC.

Enables port power when machine

Signal aliases required by this page:

- =FWPWR_PWRON (see related text note below)

BOM options provided by this page:

Page Notes

Power aliases required by this page:

- =PP3V3_S0_FWPORTPWRSW

(NONE)

2.95V when port power is on

- =PPBUS_S0_FWPWRSW (system supply for bus power)

NC

Late-VG Event Detection

SOT-363

2N7002DW-X-F

4

5

3

Q4561

SOT-363

2N7002DW-X-F

1

2

6

Q4561

402

MF-LF

1/16W

5%

2.0M

2

1

R4519

0.33UF

CERM-X5R

10% 10V

603

2

1

C4512

0.1UF

20% 10V CERM 402

2

1

C4510

200K

MF-LF

1%

402

1/16W

21

R4510

SM-LF

LMC7211

2

5

1

3

4

U4510

1/16W

10K

5%

402

MF-LF

2

1

R4511

100pF

CERM 402

50V

5%

2

1

C4511

10K

1/16W MF-LF

402

1%

2

1

R4512

80.6K

402

1% 1/16W MF-LF

2

1

R4513

SOT-363

2N7002DW-X-F

1

2

6

Q4560

2N7002DW-X-F

SOT-363

4

5

3

Q4560

5% 1/16W MF-LF

402

10K

2

1

R4560

SOD-123

MBR0540XXG

2 1

D4510

CRITICAL

QSOP1

MAX5943

3

15

11

6

8

1

13

10

7

5

16

4

2

9

12

14

U4500

CRITICAL

SOT23-3

SI2318DS

2

1

3

Q4500

MMDT3906XF

SOT-363

1

6

2

Q4502

SOT-363

MMDT3906XF

4

3

5

Q4502

5% 1/16W MF-LF

1K

402

2

1

R4502

1/16W

402

MF-LF

5%

1K

2

1

R4504

1/16W MF-LF

402

5%

100K

2

1

R4503

402

MF-LF

1/16W

5%

100K

2

1

R4501

200K

5% 1/16W MF-LF

402

2

1

R4561

1UF

10% 35V X5R 603

2

1

C4500

16V

20%

402

CERM

0.01uF

2

1

C4560

PWRPK-1212-8

SI7222DN

CRITICAL

3

4

5

Q4501

PWRPK-1212-8

SI7222DN

CRITICAL

1

2

6

Q4501

0.020

0.25W

805

MF

1%

2 1

R4500

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

A.0.0051-7150

43 84

FireWire Port Power

PPBUS_S5_FW_FET2

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

FW_PWRCTRL_GATE2_2

=PPBUS_S5_FW_FET

FW_PWRCTRL_GATE2_1

PPBUS_S5_FW_FET1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.6V

FW_PWRCTRL_GATE1

FWPWR_LATEVG_EN

FW_PWRCTRL_GATE2

FW_PWRCTRL_GATE2_2_R

FW_PWRCTRL_GATE2_1_R

SMC_ADAPTER_EN

PM_SLP_S3_L

LATEVG_EVENT_D_L

FWPWR_EN_L

PP2V4_FWLATEVG_RC

FWLATEGV_3V_REF

=PP3V3_FWLATEVG_ACTIVE

LATEVG_EVENT_L

PP2V4_FWLATEVG

FWPWR_LATEVG_EN_L

LATEVG_EVENT_D_L

=PPBUS_S5_FWPWRSW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_S5_FW_R

50A2

64C8

49D5

49C5

44D5

47C6

42A8

44B5

65C3

5C1

23C3

43A5

41B6

6B6

44A5

43C7

65C1

http://mycomp.su/x/

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

pin 5 of connector

Place C4629 close to

DFM rules for only Rs and Cs

placement in an area restricted by

were changed to resistors to allow

Note: The peaking inductors

Note:Trace PPFW_PORT1_VP should handle up to 5A

(GND_FW_PORT1_VG)

(PPFW_PORT1_VP)

(FW_PORT1_BREF)

TPB+

per 1394b V1.33

Place close to FireWire PHY

Termination

and connection detection currents

BREF should be hard-connected to logic ground for speed signaling

"Snapback" & "Late VG" Protection

Cable Power

1394A

(TPA+)

PORT 2

514S0133

BILINGUAL

PORT 1

OUTPUT

TPB<R>

(PPFW_PORT2_VP)

(GND_FW_PORT2_VG)

AREF needs to be isolated from

When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue)

PAGE

(NONE)

to apply to entire TPA/TPB XNets.

1394b implementation based on Apple

(NONE)

514-0255

(TPB-)

(TPB+)

(TPA-)

all local grounds per 1394b spec

Cable Power

TPA-

PP2V4_FWLATEVG needs to be biased

Late-VG Protection Power

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4690 should be 390 Ohms max for a 3.3V rail

- =PPFW_PORT1

BY

PHY

INPUT

TPB-

TPA+

TPA<R>

VP

VG

NCNC

provide the appropriate constraints

FireWire Design Guide (FWDG 0.6, 5/14/03)

PHYSICAL

assumed that FireWire PHY page will

constrained on this page. It is

NOTE: FireWire TPA/TPB pairs are NOT

NET_TYPE

SPACING

- =PP3V3_S5_FWLATEVG

- =GND_CHASSIS_FW_PORT1

ELECTRICAL_CONSTRAINT_SET

PROVIDED

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.

BOM options provided by this page:

ESD and late-VG rail for snap-back diodes (Common to all ports)

TI PHYs require 1uF even though

FW spec calls out 0.33uF

to arbitrary value

Setting attribute VOLTAGE to help constraint manager

find correct topolgy

CERM 402

6.3V

10%

1uF

2

1

C4650

1/16W

402

MF-LF

1%

56.2

2

1

R4651

MF-LF 402

1% 1/16W

56.2

2

1

R4650

MF-LF

402

56.2

1%

1/16W

2

1

R4653

MF-LF 402

1% 1/16W

56.2

2

1

R4652

1/16W

1%

402

MF-LF

4.99K

2

1

R4654

220pF

25V

5%

402

CERM

2

1

C4654

1/16W

5%

402

MF-LF

0

21

R4699

SM

FERR-250-OHM

21

L4630

0.001uF

CERM

50V

20%

402

2

1

C4634

BAV99DW-X-F

SOT-363

3

5

4

DP4630

1394A

CRITICAL

F-RT-TH-LF

1

2

5

6

3

4

10

987

J4630

402

16V

20%

CERM

0.01uF

2

1

C4636

603

50V

0.01uF

CERM

20%

2

1

C4635

BAV99DW-X-F

SOT-363

3

5

4

DP4631

X7R

10%

0.01uF

402

50V

2

1

C4631

SOT-363

BAV99DW-X-F

6

2

1

DP4630

X7R

10%

0.01uF

402

50V

2

1

C4630

X7R

10%

0.01uF

402

50V

2

1

C4633

SOT-363

BAV99DW-X-F

6

2

1

DP4631

X7R

10%

0.01uF

402

50V

2

1

C4632

56.2

1%

MF-LF

1/16W

402

2

1

R4663

1/16W

4.99K

1%

MF-LF

402

2

1

R4664

56.2

1% 1/16W

402

MF-LF

2

1

R4662

25V

5%

402

CERM

220pF

2

1

C4664

402

1%

56.2

1/16W MF-LF

2

1

R4661

CERM 402

10%

6.3V

1uF

2

1

C4660

1%

56.2

402

MF-LF

1/16W

2

1

R4660

NO STUFF

CERM

20% 16V

0.01uF

402

2

1

C4627

0.1uF

10% 50V X7R

603-1

2

1

C4629

1M

5%

402

MF-LF

1/16W

2

1

R4629

0.001uF

50V

20%

402

CERM

2

1

C4624

SM

FERR-250-OHM

21

L4620

603

CERM

50V

20%

0.01uF

2

1

C4625

0.01uF

20% 16V CERM 402

2

1

C4626

0.01uF

10% X7R

402

50V

2

1

C4620

BAV99DW-X-F

SOT-363

6

2

1

DP4620

X7R

10%

0.01uF

402

50V

2

1

C4621

SOT-363

BAV99DW-X-F

3

5

4

DP4620

SOT-363

BAV99DW-X-F

6

2

1

DP4621

BAV99DW-X-F

SOT-363

3

5

4

DP4621

402

50V

0.01uF

10% X7R

2

1

C4623

X7R

10%

0.01uF

402

50V

2

1

C4622

1%

332

402

MF-LF

1/16W

21

R4690

0.01UF

10% 50V X7R 402

2

1

C4691

CRITICAL

MMBZ5227B

SOT23

3

1

D4690

F-RT-SM1

CRITICAL

1394B-UG31903

9

8

7

6

5

4

3

2

11

10

1

J4620

CRITICAL

90-OHM-100MA

1210-4SM1

4

32

1

FL4630

1210-4SM1

CRITICAL

90-OHM-100MA

4

32

1

FL4631

OMIT

1/16W 402

MF-LF

0

5%

2

1

L4660

OMIT

0

MF-LF 402

1/16W

5%

2

1

L4661

OMIT

5% 1/16W

402

MF-LF

0

2

1

L4662

OMIT

0

MF-LF 402

1/16W

5%

2

1

L4663

8444

A.0.0051-7150

FireWire Ports

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

CRITICAL

4

IND,18nH-15mA,0402

L4660,L4661,L4662,L4663

152S0414

=GND_CHASSIS_FW_PORT2L

=GND_CHASSIS_FW_PORT2U

FW_PORT2_TPB_N

FW_PORT2_TPB_P

FW_PORT2_TPB_FL_P

FW_PORT2_TPB_FL_N

FW_PORT2_TPA_N

FW_PORT2_TPA_P

FW_PORT2_TPA_FL_P

FW_PORT2_TPA_FL_N

FW_A_TPBIAS

VOLTAGE=1.234V

VOLTAGE=2.4V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP2V4_FWLATEVG

FW_B_TPB_N

FW_A_TPB_P

=FW_PC0

FW_B_TPA_N

FW_A_TPB_N

FW_PORT2_TPB_FL_N

FW

FW_110D

FW_PORT2_TPB_FL_P

FW_110D

FW

FW_PORT1_TPA_P

FW_110D

FW

=GND_CHASSIS_FW_PORT1

=PP3V3_FWLATEVG

=GND_CHASSIS_FW_EMI_R

FW_B_TPB_P

FW_B_TPA_P

FW_A_TPA_P

FW_PORT2_TPA_N

MAKE_BASE=TRUE

FW_PORT2_TPA_P

MAKE_BASE=TRUE

FW_PORT2_TPB_N

MAKE_BASE=TRUE

FW_PORT2_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPFW_PORT2_VP

=PPFW_PORT2_VP

FW_PORT1_TPA_P

FW_A_TPA_N

FW_PORT1_TPA_N

MAKE_BASE=TRUE

VOLTAGE=1.234V

FW_PORT2_TPB_C

=PPFW_PORT1_VP

FW_PORT1_AREF

PP2V4_FWLATEVG

FW_PORT2_TPA_FL_N

FW_110D

FW

FW_PORT2_TPA_FL_P

FW

FW_110D

FW_PORT1_TPB_N

FW_110D

FW

FW_PORT1_TPB_P

FW_110D

FW

FW_PORT1_TPA_N

FW_110D

FW

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_PORT1_TPA_N

=PP3V3_FWPHY

FW_PC0

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

PPFW_PORT1_VP MIN_LINE_WIDTH=0.5 mm

PP2V4_FWLATEVG

VOLTAGE=1.234V

FW_B_TPA_L_P

FW_B_TPBIAS

VOLTAGE=1.234V

FW_B_TPA_L_N

VOLTAGE=1.234V

FW_B_TPB_L_N

VOLTAGE=1.234V

FW_B_TPB_L_P

VOLTAGE=1.234V

FW_PORT1_TPB_C

44D5

44B5

44D5

44B5

44C5

44D7

44A5

44C5

44D7

38D7

44A5

6B6

6A6

44C5

44D7

44C5

44D7

38B3

43B7

38B3

38B5

38B3

44B2

44B5

6A6

6C6

6B6

38B3

44B4

44C5

65C1

44B5

38B3

44C5

65C1

43B7

44B2

44B5

6C6

43B7

38B3

http://mycomp.su/x/

IO

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Camera Connector

Twin-Ax Pair 2

(40 AWG)

(28 AWG)

Twin-Ax Pair 1

Standard wires

Connector shield

(40 AWG)

518S0371

NC

Connector shield

402

X7R

50V

10%

0.01UF

2

1

C4932

CRITICAL

FERR-220-OHM-2A

0603

21

L4931

0402

FERR-220-OHM

21

L4930

F-RT-SM

CAMERA-M1-CUS

CRITICAL

6

5

4

3

2

1

8

7

J4931

50V

20%

402

CERM

0.001uF

NO STUFF

2

1

C4931

0603

FERR-220-OHM-2A

CRITICAL

21

L4950

1210-4SM1

90-OHM-100MA

CRITICAL

4

32

1

FL4935

051-7150 A.0.0

8445

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Camera Connector

=GND_CHASSIS_CAMERA

GND_CAMERA

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V MIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

=USB2_CAMERA_N

=USB2_CAMERA_P

USB2_CAMERA_N_F USB2_CAMERA_P_F

=PP5V_S3_CAMERA

45B5

45C5

6C3

6D3

65B1

6A6

5A4

http://mycomp.su/x/

OUT

VBUS

D-

D+

GND

IN

OUT

EN

OC*

GND

THRML

PAD

VDD

THRM_PAD

GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1

IO

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place L5200, L5205 and L5206 across moat

USB/SMC Debug Mux

Port Power Switch

Right USB Port

514S0115

SEL=0 Choose SMC SEL=1 Choose USB

CRITICAL

0603

FERR-220-OHM-2A

21

L5205

100UF

POLY B2

20%

6.3V

2

1

C5296

20%

6.3V

805-1

CERM

10uF

2

1

C5295

805-1

10uF

6.3V

20%

CERM

2

1

C5290

0.1UF

CERM 402

20% 10V

2

1

C5291

0.01uF

20%

CERM

16V

402

2

1

C5205

CERM

16V

402

20%

0.01uF

2

1

C5206

CRITICAL

FERR-220-OHM-2A

0603

21

L5206

CRITICAL

UAR2X

F-RT-SM-USB-RGT1

8

7

6

5

4

3

2

1

J5200

CRITICAL

RTUSB_ESD

SC-75

RCLAMP0502B

2 1

3

D5200

MSOP

TPS2051

CRITICAL

9

6

7

8

5

3

2

1

4

U5290

TDFN

PI3USB10

CRITICAL

4

3

8

2

13

6

751

9

11

10

12

U5250

20% 10V

CERM

0.1UF

402

2

1

C5250

402

MF-LF

1/16W

5%

10K

2

1

R5250

CRITICAL

1210-4SM1

90-OHM-100MA

4

32

1

L5200

46 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

External USB Connector

USB2_RT_MUXED_N

USB2_RT_MUXED_P

USB2_RT_F_P

USB2_RT_F_N

=RTUSB_OC_L

=USB2_RT_N

SMC_TX_L SMC_RX_L

=USB2_RT_P

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_ILIM

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

=GND_CHASSIS_RTUSB

=PP5V_S3_RTUSB

=RTUSB_EN

VOLTAGE=0V

MIN_NECK_WIDTH=0.5 mm

GND_RTUSB

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_F

=PP3V42_G3H_SMCUSBMUX

USB_DEBUGPRT_EN_L

51B4 50B3 50B2

49C7

6D3

5C2

6D3

6B6

65B1

64A6

65D3

50B3

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

(500 mA)

(2 Amps)

NC NC

Place XW5510 at 5V switcher

(500 mA)

(2 Amps)

Place XW5505 at 5V switcher

Place XW5500 at 5V switcher

(Input from LIO)

Left I/O Board Connector

Place XW5515 at 5V switcher

NC

516S0361

QT510806-L111-7F

F-ST-SM

CRITICAL

9

84

8382

81

80

8

79

7877

7675

7473

7271

70

7

69

6867

6665

6463

6261

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J5500

SM

21

XW5500

SM

21

XW5505

SM

21

XW5510

SM

21

XW5515

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Left I/O Board Connector

051-7150 A.0.0

8447

SMC_EXCARD_PWR_EN

VOLTAGE=0V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

GND_AUDIO_PWR

PP5V_S0_AUDIO_PWR

VOLTAGE=5V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

GND_AUDIO

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PCIE_EXCARD_D2R_P

=PCIE_EXCARD_R2D_N

ACZ_RST_L

=PCIE_EXCARD_R2D_P

=PCIE_EXCARD_D2R_N

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

=PP5V_S5_LIO

ACZ_BITCLK

=PCIE_MINI_D2R_P

=USB2_EXCARD_P

=PP1V5_S0_LIO =PP3V42_G3H_LIO =PPDCIN_G3H_LIO

LTUSB_OC_L

SMC_EXCARD_CP

LIO_P3V3S0_EN_L

SMC_BATT_ISET

=PP5V_S0_AUDIO_XW

SYS_ONEWIRE SMC_ADAPTER_EN SMC_BATT_CHG_EN

EXCARD_CLKREQ_L MINI_CLKREQ_L

LIO_BATT_ISENSE

SMC_SYS_ISET

SMC_BC_ACOK

ACZ_SDATAOUT

ACZ_SDATAIN<0> ACZ_SYNC

PCIE_WAKE_L =SMBUS_LIO_SMC_SDA =SMBUS_LIO_SMC_SCL

=USB2_EXCARD_N

=SMBUS_LIO_SB_SCL

PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P

=PCIE_MINI_D2R_N

=PCIE_MINI_R2D_N =PCIE_MINI_R2D_P

LIO_DCIN_ISENSE

SMC_BATT_TRICKLE_EN_L

EXCARD_OC_L

PP5V_S0_AUDIO

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

LIO_P3V3S3_EN

LIO_PLT_RESET_L

=USB2_LT_N =USB2_LT_P

=SMBUS_LIO_SB_SDA

50A2

84B4

50A2

50B2

49D5

50A2

84B4

39C6

50A2

50B3

49B7

48C6

21C7

48C6

48B6

34B3

34C3

65B1

21C7

48C6

6C3

65C6

65D3

65A8

6D3

49B7

64C6

49B5

49B7

43B7

49D7

34A3

53C3

49B5

49C5

21C7

23C8

27D1

6C3

27B6

34D4

48C6

53C5

49D7

6C3

64A6

26C1

6D3

27B6

5C1

5D1

5C1

5B1

5C1

5B1

5D1

5C1

5B1

5D1

5C1

65A1

5C1

5B1

5C1

5D1

5C1

5B1

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place caps close to SB

PCI-E x1 Port "D" = Unused

PCI-E x1 Port "E" = Unused

PCI-E x1 Port "F" = Unused

PCI-E x1 Port "C" = ExpressCard

PCI-E x1 Port "A" = Ethernet (Yukon)

PCI-E x1 Port "B" = PCI-E Mini Card

0.1uF

402

X5R

16V

10%

21

C5710

402

X5R

16V

10%

0.1uF

21

C5711

402

X5R

16V

10%

0.1uF

21

C5721

402

X5R

16V

10%

0.1uF

21

C5720

48 84

A.0.0051-7150

PCI-E Connections

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MAKE_BASE=TRUE

PCIE_MINI_D2R_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

PCIE_D_R2D_C_P

PCIE_D_R2D_C_N

PCIE_D_D2R_P

TP_PCIE_D_D2RN

MAKE_BASE=TRUE

TP_PCIE_D_D2RP

MAKE_BASE=TRUE

TP_PCIE_F_D2RP

MAKE_BASE=TRUE

TP_PCIE_F_D2RN

MAKE_BASE=TRUE

TP_PCIE_F_R2DP

PCIE_F_D2R_P

PCIE_F_D2R_N

PCIE_F_R2D_C_N

TP_PCIE_E_D2RP

MAKE_BASE=TRUE

TP_PCIE_E_D2RN

MAKE_BASE=TRUE

TP_PCIE_E_R2DN

MAKE_BASE=TRUE

TP_PCIE_E_R2DP

PCIE_E_D2R_P

PCIE_E_D2R_N

PCIE_E_R2D_C_N

PCIE_E_R2D_C_P

PCIE_D_D2R_N

MAKE_BASE=TRUE

TP_PCIE_D_R2DP

MAKE_BASE=TRUE

TP_PCIE_D_R2DN

PCIE_C_D2R_P

PCIE_C_D2R_N

PCIE_C_R2D_C_N

PCIE_C_R2D_C_P

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

=PCIE_EXCARD_D2R_N

=PCIE_EXCARD_D2R_P

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_R2D_P

MAKE_BASE=TRUE

PCIE_MINI_R2D_C_P

PCIE_B_D2R_P

MAKE_BASE=TRUE

PCIE_MINI_D2R_N

PCIE_MINI_R2D_C_N

MAKE_BASE=TRUE

PCIE_B_R2D_C_N

=PCIE_MINI_R2D_P

=PCIE_MINI_R2D_N

=PCIE_MINI_D2R_N

=PCIE_MINI_D2R_P

MAKE_BASE=TRUE

TP_PCIE_F_R2DN

PCIE_B_D2R_N

PCIE_B_R2D_C_P

PCIE_F_R2D_C_P

47B3

47C3

22D4

22C4

22D4

5B1

22D4

5B1

22D4

22C4

http://mycomp.su/x/

IN

OUT

IN

OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12 P13 P14 P15

P17

P31/LAD1

P30/LAD0

P32/LAD2 P33/LAD3

P36/LCLK P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45 P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4*

P65/KIN5* P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5

P84/IRQ3*/TXD1 P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2 PB3 PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5 PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD

PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15

PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3

PB0/LSMI* PB1/LSCI

PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

AVCC

XTAL EXTAL

AVCC

VCC

MD1 MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT

IO

OUT

IN

OUT

IN

IO

IN

IO

OUT

IN

OUT

IN

OUT OUT

OUT

IN

IN IN

IN

OUT

IN

OUT

OUT OUT

OUT

IO

IO IO

IO

OUT

OUT OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

OUT

IO IO

IO

IO IN

IN

OUT

OUT OUT

IO

IN

IN IN

IO

IN IN

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SMC_XXX WHERE XXX IS THE PORT NUMBER.

CAN BE LEFT NO-CONNECTED.

UNUSED PINS HAVE THE FORMAT

LAYOUT NOTE:

SMC

PLACE R5899 AND C5820 NEAR SMC PIN N14,N15

VCL IS INTERNAL RAIL

PLACE C5807 NEAR PIN F1

LAYOUT NOTE:

DRIVEN OUTPUTS ALWAYS SO THEY

THEY ARE SET BY SOFTWARE TO BE

805

20%

6.3V CERM

22UF

2

1

C5802

CERM-X5R

6.3V

0.47UF

402

10%

2

1

C5807

10V

0.1UF

20% CERM

402

2

1

C5803

0.1UF

20% CERM

10V 402

2

1

C5820

5%

1/16W

4.7

402

MF-LF

21

R5899

0.1UF

20% 10V CERM 402

2

1

C5804

SM

21

XW5800

402

10V

20%

0.1UF

CERM

2

1

C5805

20% 10V CERM 402

0.1UF

2

1

C5806

SMC_H8S2116

OMIT

BGA

G2

H1

H2

J4

J3

J1

J2

K4

B6

A6

C6

D6

B7

A7

C7

P15

N13

R15

P14

R14

P13

R13

N12

J13

J12

K14

K13

K12

L15

L14

L13

F2

G4

G1

C1

D3

C2

B1

C3

D5

B5

A5

D7

A8

C8

D8

B9

A9

C9

D9

F14

E13

E15

E14

E12

D15

D14

D13

C15

D12

C14

B15

B14

A15

C13

B12

U5800

OMIT

SMC_H8S2116

BGA

B3

D4

C4

K2

F3

E1

R7

P7

M8

R8

P8

N9

R9

P9

N5

P5

R5

M6

N6

R6

P6

M7

L2

L4

M1

M2

M3

M10

N10

R10

P10

N11

R11

P11

M11

H12

H13

H15

H14

G12

G13

G15

G14

D11

A12

C11

B11

A11

D10

A10

B10

N1

M4

N2

R1

N3

R2

P3

R3

U5800

BGA

SMC_H8S2116

OMIT

A2

D2B4A4

A13

B13

F13

F12

R4P4D1

F1

A1

J15

P1

P2

E3

F4

K1

E2

B2

L1

R12

P12

M15

M14

N15

N14

U5800

BGA

SMC_H8S2116

OMIT

L12

M13

M12

N7

M5

N4

L3

N8

M9

H4

K3

E4

B8

A3

C5

C10

C12

A14

F15

J14

K15

H3

G3

U5800

MF-LF

5% 402

1/16W

10K

2

1

R5809

MF-LF 402

5%

10K

1/16W

2

1

R5801

1/16W

5%

10K

MF-LF 402

2

1

R5802

0

5% 1/16W MF-LF 402

NOSTUFF

2

1

R5803

10K

MF-LF

5% 1/16W

402

2

1

R5898

051-7150 A.0.0

49 84

SMC_XDP_TDO_3_3

PM_SYSRST_L SMC_USB_DEBUG_MUX

PM_THRM_L

PM_EXTTS_L

SMC_ODD_DETECT ISENSE_CAL_EN SMC_EXCARD_CP

SMC_CASE_OPEN

SMB_B_S0_DATA

SMB_A_S3_CLK

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_A_S3_DATA

ALS_GAIN

SMC_FWE

SMC_EXCARD_PWR_EN

SMC_BATT_ISET

SMC_LID

SMB_BSA_DATA

SPI_CE_L

SMC_SYS_VSET

SMC_FAN_3_CTL

SMS_ONOFF_L

SMC_EXCARD_OC_L

SMS_INT_L

SMC_BATT_VSET SMC_SYS_ISET

SMC_XDP_TCK_3_3

SYS_ONEWIRE PM_BATLOW_L

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_ISENSE SMC_MEM_ISENSE ALS_LEFT ALS_RIGHT

SMC_PF0 SMC_PF1

SMC_EXTSMI_L SMC_RUNTIME_SCI_L

SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL

SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH

SMB_BSA_CLK

SMC_CPU_RESET_3_3_L

BOOT_LPC_SPI_L

SMC_RCIN_L

SMC_TCK SMC_TDI SMC_TDO SMC_TMS

SMC_RST_L

=PP3V3_S5_SMC

SMC_VCL

=PP3V3_S5_SMC

GND_SMC_AVSS

SMC_NMI

SMC_TRST_L

PP3V3_AVREF_SMC

SMC_MD1

KBC_MDE

=PP3V3_S5_SMC

PP3V3_AVCC_SMC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

SMC_EXTAL

SMC_XTAL

SMC_CPU_VSENSE

SMC_ONOFF_L

SC_RX_L

SC_TX_L

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_GPU_VSENSE

SMC_GPU_ISENSE

SMC_CPU_ISENSE

SMC_CPU_INIT_3_3_L

SMC_PROCHOT_3_3_L

SPI_SO

SPI_SI

SPI_SCLK

SPI_ARB

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMB_0_S0_CLK

SMC_SYS_LED_16B

SMC_P20 SMC_P21 SMC_P22

SMC_P23 SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN

SMC_P26

SMC_P27

SMC_TPM_PP

SMC_XDP_TMS

SMC_SYS_LED

SMC_XDP_TCK

SMC_SYS_KBDLED

SMC_RSTGATE_L

SMC_SUS_CLK

SMC_TPM_GPIO

SMC_BATT_ISENSE SMC_NB1V5_ISENSE

SMC_XDP_TRST_L

INT_SERIRQ

PCI_CLK_SMC

LPC_AD<3>

LPC_AD<2>

LPC_AD<0> LPC_AD<1>

PM_PWRBTN_L

PM_RSMRST_L

SMC_SB_NMI

RSMRST_PWRGD

ALL_SYS_PWRGD

PM_LAN_ENABLE

LPC_FRAME_L SMC_LRESET_L

SMC_WAKE_SCI_L

PM_CLKRUN_L PM_SUS_STAT_L

SMB_BSB_CLK

SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

SMB_0_S0_DATA

SMB_BSB_DATA

SMC_TX_L SMC_RX_L

IMVP_VR_ON

55C6

55C2

53D6

53C6

53C1

53B7

65D3

53B5

65D3

58C6

51B4

51B5

50D7

53B3

50D7

78C2

50A2

58C6

51B5

64C8

50B3

26C5

50A2

78C6

50B2

51B4 51B5

51B5

51B4

51B5

50B1

53B1

50B1

50C6

47C6

50A2

51C5

51C4

50A2

66B5

43B7

64B8

50B2

23C5

50D5

53A8

47B6

6D5

47B6

78C3

54C7

50B2

47C6

22B3 50B2

50B2

50D6

49D3

49D4

50B6

51B5

51B4

49D4

50B2

54C1

54C7

43B7

47B6

47C6

6D4

23C8

21D4

64B1

21C5

23C8

23C5

47B6

50B2

42A8

41B6

50A2

46B5

50B2

5B2

50B5

23C8

14B7

36C4

5A2

5C1

50A2

27D3

27C6

50C2

27D3

27C6

5B2

50B2

5C1

50B2

27C3

22C6

50D5

57C6

50B5

23C3

50D5

5C1

50B2

5C1

23C1

57C3

50D5

50A2

55C7

55D2

50C5

23B8

23C8

56B7

56B4

50D5

56B7

56B4

50D5

27C3

50B2

5C2

21C3

5C2

49C2

49B2

49C4

5C2

50B6

5C2

49D3

50C8

53D6

5B2

50B5

53D2

53C4

53C6

53B6

53B7

50D5

50D1

22C6

5C1

64A8

27D6

50A8

50C5

5C1

50C5

50B5

50C5

50D5

55A6

6B7

35B2

50C5

53C2

50D5

50C5

5C2

34D6

5C2

5D2

5C2

23C3

23C1

23C3

50A4

26A5

23C3

5C2

26B1

23C1

5C2

27B3

5C1

5D1

23C3

27D6

27B3

5C2

59C7

http://mycomp.su/x/

G

D

S

G

D

S

IN

OUT

GND

IN

OUT

V-

V+

V-

V+

OUT

NC

CD

GND

OUT

VDD

OUT

G

D

S

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SMC PWRGD Circuit

SMC 1.05V to 3.3V Level Shifting

1.05V Mid-Reference

Silk: "SMC RST"

SMC Reset Button / Brownout Detect

NC

System (Sleep) LED Circuit

NOTE: R5965 acts as 10K pull-up for PGOOD signal

1.71V Reference

Silk: "PWR BTN"

Debug Power Button

SMC 3.3V to 1.05V Level Shifting

SMC AVREF Supply

ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)

5V Comp threshold set to 4.480V (89.6%)

SMC Crystal Circuit

Reports when 5V S5 and 3.3V S5 are in regulation

0.1uF

CERM

402

20% 10V

2

1

C5900

SMC_TPM_GPIO1

0

1/16W

5%

MF-LF

402

21

R5990

0

SMC_TPM_GPIO2

5% 1/16W MF-LF

402

21

R5991

2N7002DW-X-F

SOT-363

1

2

6

Q5995

2N7002DW-X-F

SOT-363

4

5

3

Q5995

1/16W MF-LF

0

5%

402

21

R5992

1/16W MF-LF

0

5%

402

21

R5993

0.1uF

CERM

402

20% 10V

2

1

C5977

1K

MF-LF

402

5%

1/16W

2

1

R5971

5%

402

6.2K

1/16W MF-LF

2

1

R5970

402

CERM-X5R

6.3V

0.47UF

10%

2

1

C5965

0.01uF

20% 16V CERM 402

2

1

C5967

6.3V

20% X5R

10uF

603

2

1

C5966

SOT23-3

REF3133

CRITICAL

21

3

VR5965

0.1uF

10V

20%

402

CERM

2

1

C5960

10K

MF-LF

402

1%

1/16W

2

1

R5961

MF-LF

402

1%

1/16W

10K

2

1

R5962

5%

402

MF-LF

10K

1/16W

2

1

R5965

LMC7211

SM-LF

2

5

1

3

4

U5977

SM-LF

LMC7211

2

5

1

3

4

U5960

402

MF-LF

5%

1/16W

0

21

R5994

1/16W MF-LF

SMC_TPM_PP

5%

402

0

21

R5995

402

MF-LF

5%

1/16W

10K

21

R5931

402

10K

1/16W5%MF-LF

21

R5932

100K

402

MF-LF

5%

1/16W

21

R5933

10K

1/16W5%MF-LF

402

21

R5934

402

MF-LF

5%

1/16W

10K

21

R5935

100K

5%

MF-LF

402

1/16W

21

R5936

2.0K

402

MF-LF

5%

1/16W

21

R5937

402

MF-LF

5%

1/16W

100K

21

R5938

402

MF-LF

5%

1/16W

10K

21

R5939

10K

1/16W

5%

402

MF-LF

21

R5940

10K

402

5%

1/16W MF-LF

21

R5941

10K

1/16W

5%

402

MF-LF

21

R5942

10K

1/16W5%MF-LF

402

21

R5943

402

MF-LF

5%

1/16W

10K

21

R5944

402

MF-LF

5%

1/16W

10K

21

R5945

1/16W5%MF-LF

402

10K

21

R5946

470K

402

MF-LF

5%

1/16W

21

R5947

10K

1/16W5%MF-LF

402

21

R5948

402

MF-LF

5%

1/16W

10K

21

R5930

20.00MHZ

5X3.2-SM

CRITICAL

2

1

Y5920

SOT23-5

RN5VD30A-F

CRITICAL

2

1

4

3

5

U5900

10K

1/16W

1%

402

MF-LF

2

1

R5964

16.2K

MF-LF 402

1% 1/16W

2

1

R5963

CERM 402

0.0022uF

10% 50V

2

1

C5969

402

MF-LF

5%

1/16W

10K

21

R5980

5%

10K

1/16W MF-LF

402

21

R5981

1/16W

10K

5%

MF-LF

402

21

R5982

MF-LF

402

5%

1/16W

100K

21

R5983

100K

1/16W5%MF-LF

402

21

R5984

100K

1/16W5%MF-LF

402

21

R5985

402

MF-LF

5%

1/16W

0

21

R5996

1/16W

5%

402

MF-LF

1K

2

1

R5900

OMIT

0

MF-LF 603

5% 1/10W

2

1

R5901

MF-LF 603

5%

OMIT

0

1/10W

2

1

R5910

2N7002

SOT23-LF

2

1

3

Q5952

2N3906

SOT23-LF

2

3

1

Q5950

100

MF-LF 402

5% 1/16W

2

1

R5950

1/16W

5%

402

MF-LF

2.2K

2

1

R5951

MF-LF

402

1/16W

10K

5%

2

1

R5952

15pF

CERM

402

5%

50V

21

C5920

15pF

402

CERM

50V

5%

21

C5921

CERM

10% 16V

0.01UF

402

2

1

C5901

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

50

051-7150 A.0.0

84

SMC Support

USB_DEBUGPRT_EN_L

TP_SMC_FAN_3_TACH

MAKE_BASE=TRUE

TPM_GPIO2

SMS_INT_L SMC_TPM_RESET_L

SMC_LID

SMC_ONOFF_L

SMC_FWE SMC_TX_L SMC_RX_L

=PP3V3_S3_SMS

=PP3V3_S3_TPM

SYS_ONEWIRE

SMC_EXTAL

SMC_XTAL

SMC_TMS

SMC_BS_ALRT_L

SMC_TDO SMC_TDI

SMC_XDP_TCK_3_3

SMC_TCK SMC_CPU_RESET_3_3_L

SMC_ADAPTER_EN SMC_CASE_OPEN SMC_BC_ACOK

GND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=0V

PM_SUS_STAT_L

SMC_EXCARD_CP

SMC_BATT_TRICKLE_EN_L

MIN_NECK_WIDTH=0.2 mm

PP3V3_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

=PP3V42_G3H_SMCVREF

CPU_PROCHOT_L

PM_THRMTRIP_L

SMC_PROCHOT

SMC_THRMTRIP

SMC_ONOFF_L

PP5V_S5 =PP3V42_G3H_SMC_PWRGD

MAKE_BASE=TRUE

RSMRST_PWRGD

P5VS5_PGOOD

P1V71_SMC_REF

P5VS5_COMP_POS

=P3V3S5_PGOOD

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_L

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_SYS_LED_16B

=PP3V3_S5_SMC

SMC_MANUAL_RST_L

SMC_RST_L

MAKE_BASE=TRUE

FWH_INIT_L

SMC_CPU_INIT_3_3_L

SMC_P1V05S0_ISENSE

MAKE_BASE=TRUE

SMC_NB_ISENSE

DIMM_OVERTEMP_L

PM_EXTTS_L

MAKE_BASE=TRUE

SMC_P1V5S0_NB_ISENSE

SMC_NB1V5_ISENSE

TP_SMC_ANALOG_ID

MAKE_BASE=TRUE

SMC_ANALOG_ID

MAKE_BASE=TRUE

TP_SMC_SYS_LED

SMC_SYS_LED

MAKE_BASE=TRUE

TP_SMC_BATT_VSET

SMC_BATT_VSET

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

SMC_SYS_VSET

TP_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_FAN_2_CTL

TP_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_2_TACH

SMC_FAN_3_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTL

SMC_FAN_3_CTL

TP_SMC_XDP_TCK

MAKE_BASE=TRUE

SMC_XDP_TCK

MAKE_BASE=TRUE

TP_SMC_XDP_TMS

SMC_XDP_TMS

MAKE_BASE=TRUE

TP_SMC_XDP_TRST_L

SMC_XDP_TRST_L

MAKE_BASE=TRUE

TP_SMC_P20

SMC_P20

MAKE_BASE=TRUE

TP_SMC_P21

SMC_P21

TP_SMC_P22

MAKE_BASE=TRUE

SMC_P22

TP_SMC_P23

MAKE_BASE=TRUE

SMC_P23

TP_SMC_P27

MAKE_BASE=TRUE

SMC_P27

TP_SMC_PF0

MAKE_BASE=TRUE

SMC_PF0

MAKE_BASE=TRUE

TP_SMC_PF1

SMC_PF1

VOLTAGE=0.46V

P0V46_SMC_LSREF

=PP3V3_S0_SMC_LS

SMC_PROCHOT_3_3_L

SC_TX_L

SMC_TPM_PP

SC_RX_L

TPM_PP

SMC_RX_L

TPM_GPIO1

SMC_TX_L

SMC_BATT_CHG_EN

PM_SLP_S5_L

CPU_PROCHOT_L

SMC_EXCARD_OC_L

EXCARD_OC_L

SMC_USB_DEBUG_MUX

SMC_XDP_TDO_3_3

=PP3V3_S5_SMC

SMC_P26

MAKE_BASE=TRUE

TP_SMC_P26

SMC_TPM_GPIO

SMC_MEM_ISENSE

55C6

55C2 53D6 53C6 53C1 53B7

51B4

51B5

53B5

58C6

65D3

51B5

51B4

65D3

78C2

50B3

49D5

53B3

51B5

78C2

50B1

50B2

50D7

50C6

49C7

49B7

51B4

66B5

51B4

51B5

47C6

49C5

53B1

49C5

49B7

49D7

21C2

50B2

49D4

51B5

51C5

49C7

49D7

47C6

49D4

49B5

78C3

49C5

46B5

65C3

47C6

49B5

49C5

49B5

49C5

43B7

47B6

49C4

23C5

47B6

50D3

14B6

49C5

63C7

49D3

49C3

21C4

29C3 49B7

46B5

47C6

49C5

50C1

6C3

49D3

46B3

58C6

23C3

58B7

49B5

5B2

49B5

5C2

57C6

58C2

5C1

49C3

5C2

5D1

5C2

49B5

5C2

49B5

5C1

49C5

5C1

49B2

5C2

5C1

49D2 65D3

7C6

49B5

5B2

65C1

65D3

49D7

64A8

65B1

78B4

49C7

49C2

5C2

49D5

53B2 49A7

28C3 14B7

53B4 49D5

49A7

49C7

49B5

49B7

49C7

49D7

49B5

65A3

49D5

49C5

49C7

49C5

58C6

5C2

58C6

5C2

5C1

23C3

7C6

49B7

5C1

49B7

49C2

49D7

49D5

49A7

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(GPIO15)

NC

516S0384

NC

NCNC

CRITICAL

LPCPLUS

M-ST-SM

QT500306-L021-9F

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6000

51 84

A.0.0051-7150

LPC+ Debug Connector

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

=PP3V3_S5_LPCPLUS

=PP5V_S0_LPCPLUS FWH_INIT_L PCI_CLK_PORT80_LPC

LPC_AD<2> LPC_AD<3>

INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L

SV_SET_UP

LPC_AD<0>

LPC_AD<1>

BOOT_LPC_SPI_L

LPC_FRAME_L

PM_CLKRUN_L

SMC_TMS

DEBUG_RST_L

SMC_TRST_L

SMC_TDO

SMC_MD1

SMC_TX_L

58C6

50B3

58C6

50A2

50B2

58C6

50B2

50D3

49C7

49C5

50B2

50D6

49C7

23C3

49D7

49C7

49C5

50B2

49C7

65D3

65A1

21C4

34D6

21D4

23C8

23C5

49B5

49C5

49C3

49C1

46B5

23B6

21D4

22B3

21C5

23C8

49B5

26B1

49C1

49B5

49C1

46B5

5D2

5C2

5D2

5C2

http://mycomp.su/x/

SMBDATA

SMBCLK ALERT*

OT2*

DXP2

OT1*

DXN

DXP1

GND

VCC

IO

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Th0H)

(Th1H)

GPU Die Thermal Sensor

518S0452

(TG0T)

(TG0H)

Place U6150 near GPU

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

Placement note:

Place on left side of fan cutout

518S0452

NC

Placement note:

NC

Place in between VRAM

Placement note:

Keep all 4 XWs as close to U6100 as possible

UMAX

MAX6695AUB

CRITICAL

1

9 7

10

5

6

4

2

3

8

U6100

50V

CERM

402

10%

0.0022uF

2

1

C6120

SM

21

XW6120

SM

21

XW6121

SM

21

XW6111

SM

21

XW6110

0.001UF

10%

402

CERM

50V

2

1

C6160

0.1uF

CERM 402

20% 10V

2

1

C6100

BM02B-ACHKS-A-GAN-TF-LF

CRITICAL

M-RT-SM

2

1

4

3

J6120

1/16W MF-LF 402

5%

10K

2

1

R6152

47

MF-LF

5%

1/16W

402

21

R6100

0.1UF

X5R 402

10% 16V

2

1

C6150

1/16W

10K

5%

402

MF-LF

2

1

R6151

MSOP

TMP401

1

4

7

8

5

2 3

6

U6150

402

MF-LF

1/16W

1%

499

21

R6160

402

MF-LF

1/16W

1%

499

21

R6161

M-RT-SM

CRITICAL

BM02B-ACHKS-A-GAN-TF-LF

2

1

4

3

J6160

10%

402

CERM

0.0022uF

50V

2

1

C6110

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7150 A.0.0

8452

Thermal Sensors

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S0_GPUTHMSNS_R

=SMBUS_REMTHMSNS_SDA =SMBUS_REMTHMSNS_SCL

REMTHMSNS_DXP2

REMTHMSNS_DXN

REMTHMSNS_DXP1

=PP3V3_S0_REMTHMSNS

RSTHMSNS_THM_L

RSTHMSNS_ALERT_L

GPUTHMSNS_DXP

GPUTHMSNS_DXN

=SMBUS_GPU_TDIODE_SDA

HSTHMSNS_DX_N

ATI_TDIODE_P

ATI_TDIODE_N

RSFSTHMSNS_D_P

RSFSTHMSNS_D_N

=SMBUS_GPU_TDIODE_SCL

=PP3V3_S0_GPU_TDIODE

HSTHMSNS_DX_P

27D3

65B3

27D3

5B2

74A3

5B2

27D3

65A3

5B2

http://mycomp.su/x/

IN

OUT

N-CHN

S

D

G

P-CHN

G

D

S

N-CHN

S

D

G

P-CHN

G

D

S

D

S

G

D

S

G

D

S

G

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.05A / 1.1W

PBUS Voltage Sense Enable & Filter

Enables PBUS VSense divider when high.

1.5V S0 (NB) Current Sense Filter

CPU Voltage Sense / Filter

Place short near U0700 center

GPU Voltage Sense / Filter

GPU Current Sense Filter

DCIN Current Sense Filter

Place short near U8400 center

Battery Current Sense Filter

Place RC close to SMC

1.2A / 1.44W

Place RC close to SMC

1.05V S0 (NB) Current Sense Filter

Place RC close to SMC

Place RC close to SMCPlace RC close to SMC

Place RC close to SMC

Rthevanin = 4573 ohms

Place RC close to SMC

CPU Current Sense Filter

Place RC close to SMC

Switches in fixed load on power supplies to calibrate current sense circuits

Current Sense Calibration Circuit

470K

5% 1/16W MF-LF 402

2

1

R6228

402

MF-LF

1/16W

5%

100K

2

1

R6227

27.4K

1% 1/16W MF-LF

402

2

1

R6285

6.3V

0.22UF

402

X5R

20%

2

1

C6285

5.49K

402

MF-LF

1/16W

1%

2

1

R6286

FDG6332C_NL

SC70-6

1

2

6

Q6229

FDG6332C_NL

SC70-6

4

5

3

Q6229

SC70-6

FDG6332C_NL

1

2

6

Q6215

FDG6332C_NL

SC70-6

4

5

3

Q6215

FDM6296

CRITICAL

MICROFET3X3

321

4

5

Q6220

MICROFET3X3

FDM6296

CRITICAL

321

4

5

Q6221

MICROFET3X3

CRITICAL

FDM6296

321

4

5

Q6223

0.22UF

20%

6.3V X5R 402

2

1

C6259

1% 1/16W MF-LF

402

4.53K

21

R6259

1/16W

4.53K

402

MF-LF

1%

21

R6270

6.3V

0.22UF

402

X5R

20%

2

1

C6270

20%

X5R 402

0.22UF

6.3V

2

1

C6275

1% 1/16W MF-LF

402

4.53K

21

R6275

6.3V

0.22UF

402

X5R

20%

2

1

C6280

4.53K

402

MF-LF

1/16W

1%

21

R6280

1% 1/16W MF-LF

402

4.53K

21

R6290

20%

X5R 402

0.22UF

6.3V

2

1

C6290

20%

X5R 402

0.22UF

6.3V

2

1

C6240

1% 1/16W MF-LF

402

4.53K

21

R6240

6.3V

0.22UF

402

X5R

20%

2

1

C6235

4.53K

402

MF-LF

1%

1/16W

21

R6235

SM

21

XW6259

402

1%

4.53K

MF-LF

1/16W

21

R6209

402

X5R

6.3V

20%

0.22UF

2

1

C6209

SM

21

XW6209

1206

MF-LF

1/4W

1%

1.00

2

1

R6220

470K

5% 1/16W MF-LF

402

2

1

R6229

1206

MF-LF

1/4W

1%

1.00

2

1

R6221

1206

MF-LF

1/4W

1%

1.00

2

1

R6223

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Current & Voltage Sensing

53 84

A.0.0051-7150

PBUSVSENS_EN_L

GPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

CPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

SMC_CPU_ISENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

VOLTAGE=12.6V

PPBUS_G3H_VSENSE

ISENSE_CAL_EN

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN_L

GND_SMC_AVSS

LIO_DCIN_ISENSE

=PPVCORE_S0_CPU

SMC_DCIN_ISENSE

GND_SMC_AVSS

LIO_BATT_ISENSE SMC_BATT_ISENSE

GND_SMC_AVSS

CPUVCORE_IOUT GPUVCORE_IOUT

SMC_GPU_ISENSE P1V5S0_NB_IOUT

SMC_P1V5S0_NB_ISENSE

SMC_P1V05S0_ISENSE

GND_SMC_AVSS GND_SMC_AVSS GND_SMC_AVSS

GPUVSENSE_IN

CPUVSENSE_IN

SMC_GPU_VSENSE

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_GPU

GND_SMC_AVSS

=PPVCORE_S0_CPU =PPVCORE_S0_GPU

P1V05S0_IOUT

PPBUS_G3H

=PBUSVSENS_EN

=PP1V05_S0_REG

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

P1V05S0_ISENSE_CAL

ISENSE_CAL_EN_LS5V

55C6

55C6 55C6

55C6

55C2

55C2 55C2

55C6 55C6 55C2

55C6

55C2

53D6

53D6 53D6

55C2 55C2 53D6

55C2

53D6

53C6

53C6 53C6

53D6 53D6 53C6

53D6

53C6

53C1

53C1 53C1

53C6 53C6 53C1

53C1

53B7

53B7 53B7

53C1 53C1 53B7

53B7

53B5

53B5 53B5

53B5 53B7 53B5

53B5

53B3

65D1

53B3 53B3

53B3 53B3 53B3

53B3

65D1

53B1

53A6

53B1 53B1

53B1 53B1 53B1

53B1

74A7

53B1

53D7 74A7

50B6

9D7

50B6 50B6

50B6 50B6 50B6

50B6

69D8

50B6

9D7

69D8 65D8

49C4

49B7

65A1

49C4

47B6

8D7

49C4

47C6

49C4

49C4 49C4 49C4

49C4

65A6

49C4

8D7

65A6 63A2

49D5

49B2

49D5

5A2

49B2

5C1

8B5

49D5

49B2

5C1

49D5

49B2

59A5 68D1 49D5 60A6 50D3 50D3

49B2 49B2 49B2

49D5

49B2

53A5

49B2

8B5

53C7

63B1

65C1

64B6

5B2

http://mycomp.su/x/

SCK

SO

WP*

SI

VDD

CE*

HOLD*

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH ICH7M AND TEKOA(LAN CHIP)

R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM

R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M

0.1UF

20% 10V CERM 402

2

1

C6312

3.3K

MF-LF

5%

402

1/16W

2

1

R6301

MF-LF

1/16W

5%

3.3K

402

2

1

R6302

50V

5% CERM

402

22pF

2

1

C6301

47

1/16W

5%

402

MF-LF

21

R6307

CERM

5% 50V

22pF

402

2

1

C6308

22pF

402

50V CERM

5%

2

1

C6309

1/16W

5%

47

MF-LF

402

21

R6303

402

5%

MF-LF

1/16W

47

21

R6306

50V

5% CERM

402

22pF

2

1

C6311

SOI

SST25VF016B

16MBIT

CRITICAL

OMIT

3

4

8

2

5

6

7

1

U6301

MF-LF

1/16W

10K

5%

402

21

R6308

402

MF-LF

1/16W

5%

10K

NOSTUFF

21

R6309

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

84

A.0.0051-7150

SPI BOOTROM

54

SPI_WP_L

SPI_HOLD_L

SPI_CE_L

SPI_SO

SPI_SI

SPI_SCLK_R

SPI_SCLK SPI_SI_R

SPI_SO_R

=PP3V3_S5_ROM

49B5

49D5

49D5 49D5

22C6

22C6 22C6

65C3

http://mycomp.su/x/

V+

V-

G

D

S

IN

OUT

NC

CNTRL

THRML_PAD

VDD

SW

AGNDPGND

FB

VOUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Left ALS circuit has 1K series-R

Left ALS Filter

Keyboard LED Driver

NC

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched

CRITICAL

SOT23-6-LF

MAX4236EUTT

2

6

5

1

4

3

U6405

0.1UF

10V

20%

402

CERM

2

1

C6405

1/16W

5%

402

MF-LF

120K

2

1

R6406

6.3V

20%

402

X5R

0.22UF

2

1

C6406

1/16W

1%

402

MF-LF

15.0K

2

1

R6407

1/16W

1%

402

MF-LF

1K

2

1

R6408

1K

1/16W

1%

402

MF-LF

21

R6401

CRITICAL

TH

BS520EOF

2

1

PD6400

1/16W

5%

402

MF-LF

5.1M

2

1

R6400

402

16V

20% CERM

0.01UF

2

1

C6400

SOT23-LF

2N7002

2

1

3

Q6408

1/16W

1%

402

MF-LF

4.53K

21

R6410

402

6.3V

20% X5R

0.22UF

2

1

C6410

CRITICAL

LLP

MM3120

8

197

5

6 4

3

2

U6450

CRITICAL

3.8x3.8x1.5MM

22uH

21

L6450

6.3V

10%

402

CERM

1uF

2

1

C6450

1/16W

5%

402

MF-LF

10K

KBDLED_NOT

2

1

R6451

402

10K

KBDLED_HAS

1/16W

5%

MF-LF

2

1

R6452

603

X5R

25V

20%

0.22uF

2

1

C6455

MF-LF

1/8W

1%

805

25.5

2

1

R6455

0.22UF

X5R 402

20%

6.3V

2

1

C6430

3.48K

MF-LF

402

1%

1/16W

21

R6430

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

A.0.0051-7150

8455

ALS Support

=RTALS_GAIN

RTALS_OP_COMP

=PP3V3_S3_RTALS

ALS_RT_OUT

ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_IN

RTALS_PHOTODIODE

RTALS_GAIN_L

SMC_SYS_KBDLED

=PP3V3_S0_KBDLED

KBDLED_RETURN

KBDLED_ANODE

KBDLED_SW

=PP5V_S0_KBDLED

GND_SMC_AVSS

LTALS_OUT

ALS_LEFT

55C6

55C2

53D6

53C6

53C1

53B7

53B5

53B3

53B1

50B6

49C4

78C6

6D4

65C3

49A7

49B2

49C7

65B3

78C3

65A1

49B2

5B2

49A7

http://mycomp.su/x/

G

S D

G

S D

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0369

NC

Right Fan

Left Fan

518S0369

NC

5%

MF-LF

402

47K

1/16W

2

1

R6550

47K

402

MF-LF

5%

1/16W

21

R6555

1/16W

5%

47K

MF-LF

402

2

1

R6560

5% 1/16W MF-LF

47K

402

21

R6565

100K

1/16W

5%

MF-LF

402

2

1

R6551

SOT-363

2N7002DW-X-F

4

5

3

Q6560

402

MF-LF

5%

1/16W

100K

2

1

R6561

2N7002DW-X-F

SOT-363

1

2

6

Q6560

M-RT-SM

SM04B-ACH

CRITICAL

4

3

2

1

6

5

J6550

M-RT-SM

SM04B-ACH

CRITICAL

4

3

2

1

6

5

J6560

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

56 84

051-7150 A.0.0

Fan Connectors

SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_PWM

=PP5V_S0_FAN_RT

FAN_RT_TACH

=PP3V3_S0_FAN_LT

=PP5V_S0_FAN_LT

SMC_FAN_1_TACH

=PP3V3_S0_FAN_RT

FAN_LT_PWM

FAN_LT_TACH

65A1

49B7

5D2

65A1

5D2

65A3

5D2

49B7

65A3

5D2

http://mycomp.su/x/

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X Y Z

FF/MOT

SDA/SDO

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

APN:338S0354

placed on board bottom-side:

placed on board top-side:

1

Desired orientation when Desired orientation when

+X

+Z (dn)

+Y

Top-through View

Package Top

1

+Z (up)

+X

+Y

M59 placement: Bottom-side

10V

20%

402

CERM

0.1uF

2

1

C6620

0.033UF

X7R 402

20% 10V

2

1

C6605

0.033UF

X7R 402

20% 10V

2

1

C6606

KXPS5-2050

CRITICAL

LGA

9

8

7

14131

4

5

12

10

11

6

2 3

U6620

1/16W

5%

402

MF-LF

10K

2

1

R6620

10V

20%

402

X7R

0.033UF

2

1

C6604

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Sudden Motion Sensor (SMS)

051-7150 A.0.0

8457

SMS_ONOFF_L

=PP3V3_S3_SMS

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS

TP_SMS_FF

65C3

49A5

50B1

49B7

49A7

http://mycomp.su/x/

IN

IO

LAD1 LAD2

LCLK LFRAME* LRESET* LPCPD* SERRIRQ

LAD0

CLKRUN/GPIO*

PP/GPIO GPIO_EXPRESS_00 GPIO/SM_DAT GPIO/SM_CLK

XTALI/32K_IN

TESTBI/BADD/GPIO

TESTI

3V0 3V1 3V2

3VSB

VNC

VBAT

XTALO

GND2

GND3

GND0

GND1

LAD3

IO

IN

IO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(INT PD)

GND

NC

VDD

NC

PP GPIO

CLKRUN*

NC

BASE ADDR = 0X2E/2F

LAYOUT NOTE: PLACE WHERE ACCESSIBLE

LAYOUT NOTE: PLACE R6702-03 WHERE ACCESSIBLE

NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC, 1/8W (R6704/R6705) IS USED FOR NOW

TESTBI/BADD

GPIO2

BASE ADDR = 0X4E/4F

VSB

0.1UF

10% 16V X5R 402

TPM

2

1

C6700

10% 16V X5R 402

0.1UF

TPM

2

1

C6701

402

X5R

16V

10%

0.1UF

TPM

2

1

C6702

402

X5R

16V

10%

0.1UF

TPM

2

1

C6703

402

MF-LF

1/16W

5%

0

NOSTUFF

2

1

R6700

OMIT

TSSOP

TPM

14

13

3

12

8

9

27

7

16 28

22

21

17

20

23

26

6 1 2

251811

4

15

5

24

19

10

U6700

402

10K

5% 1/16W MF-LF

TPM

2

1

R6702

402

10K

MF-LF

1/16W

5%

NOSTUFF

2

1

R6703

0

5%

1/8W

MF-LF

805

TPM

21

R6704

0

5% 1/8W MF-LF 805

NOSTUFF

2

1

R6705

402

1/16W MF-LF

5%

0

TPM

21

R6798

402

1/16W

NOSTUFF

0

5%

MF-LF

21

R6799

8458

A.0.0051-7150

TPM

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

LPC_AD<1> LPC_AD<2>

PCI_CLK_TPM LPC_FRAME_L

TPM_RST_L

PM_SUS_STAT_L INT_SERIRQ

LPC_AD<0>

PM_CLKRUN_L

TPM_PP

TPM_GPIO1

TPM_GPIO2

TPM_XTALI

TPM_BADD

=PP3V3_S0_TPM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=3.3V

PP3V3_TPM_3VSB

TPM_XTALO

LPC_AD<3>

=PP3V3_S3_TPM

=PP3V3_S0_TPM

TPM_LRESET_L

SMC_TPM_RESET_L

51B5

51C4

51C5

51C4

50A2

51C5

51C4

51C5

49D7

49C7

49C5

49C7

49D7

49C5

49C7

21D4

21C5

23C5

23C8

21D4

23C8

65B3

21D4

65C3

65B3

5C2

34D6

5C2

5D2

5C2

50B3

50C3

35C5

58C7

35D5

5C2

50B1

58D4

26B1

50B2

http://mycomp.su/x/

IN

IN IN

OUT

IN

OUT

V-

V+

+

-

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

CLK_EN*

PGD_IN

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID0

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

DPRSTP*

VDIFF

SOFT

DPRSLPVR

TPAD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(IMVP6_FB)

(GND_IMVP6_SGND)

(GND)

1 1 0 1-Phase DCM

(IMVP6_PHASE2)

Vout = Variable

(Inductors limit)

36A max output

1 0 1 1-Phase DCM

DPRSLPVR DPRSTP* PSI* Operation Mode

(IMVP6_COMP)

(GND_IMVP6_SGND)

(GND)

(IMVP6_VW)

<Rb>

(IMVP6_ISEN2)

<Ra>

(IMVP6_VSUM)

(IMVP6_VO)

<Rc>

Voffset = (Vdrp_offset * Kdroop) + Vamp_offset

Voffset worst-case ~2.3mV (+/- ~1A offset)

Gain = Rc / (Ra + Rb)

Vout @ 36A = 2.44V-2.60V

<Rc>

CPU VCore Current Sense

(IMVP6_NTC)

0 1 1 2-Phase CCM

0 1 0 1-Phase CCM

These caps for Q7550These caps for Q7500

(IMVP6_ISEN1)

(IMVP6_PHASE2)

(IMVP6_VO)

Vout = Gain * ((2.1 mV/A * Iload) + Voffset)

402

CERM

NO STUFF

10%

0.0022UF

50V

2

1

C7501

NO STUFF

CERM 402

50V

10%

0.0022UF

2

1

C7502

402

10K

MF-LF

1/16W

1%

21

R7505

0.22UF

20%

X5R

6.3V

402

21

C7505

603

1/10W

1%

MF-LF

3.65K

2

1

R7506

147K

1% 1/16W

402

MF-LF

2

1

R7532

10%

402

0.015uF

16V X7R

2

1

C7532

0.1uF

10%

402

X5R

16V

2

1

C7531

1.82K

402

1% 1/16W MF-LF

2

1

R7535

4.42K

402

1%

MF-LF

1/16W

2

1

R7537

5%

CERM

50V

47pF

402

2

1

C7537

107K

1/16W

402

MF-LF

1%

2

1

R7534

470pF

CERM

402

10% 50V

2

1

C7535

25V X5R 603

0.22uF

20%

2

1

C7500

603

X5R

25V

0.22uF

20%

2

1

C7550

402

1/16W

1%

MF-LF

13.7K

2

1

R7542

1/16W

1%

402

MF-LF

3.01K

21

R7540

402

MF-LF

1K

1% 1/16W

2

1

R7541

180pF

5%

402

CERM

50V

2

1

C7540

499

1%

1/16W

402

MF-LF

21

R7545

21C4

7B3

84C6 23C3 14B7

7A3

64B2

26A7

49D7

26B5 14B6

10K

402

1%

MF-LF

1/16W

21

R7555

20%

6.3V X5R 402

0.22UF

21

C7555

1/10W

603

3.65K

1%

MF-LF

2

1

R7556

0.0022UF

CERM

10% 50V

402

NO STUFF

2

1

C7552

402

CERM

0.0022UF

10% 50V

NO STUFF

2

1

C7551

1uF

10%

402

6.3V CERM

2

1

C7530

1/16W

5%

10

402

MF-LF

21

R7530

402

1%

2.0K

NO STUFF

MF-LF

1/16W

2

1

R7536

301

1% 1/16W

402

MF-LF

2

1

R7533

820pF

CERM

402

10% 50V

2

1

C7533

6.3V 402

0.22uF

X5R

20%

2

1

C7544

402

11K

1/16W

1%

MF-LF

2

1

R7543

MF-LF

1/16W

1%

30.1K

402

21

R7593

30.1K

1%

402

1/16W MF-LF

21

R7591

X5R

10%

1uF

16V

603

2

1

C7528

4.7uF

CERM

6.3V

20%

603

2

1

C7529

MF-LF

402

1/16W

10

5%

21

R7531

1/16W

5%

10

402

MF-LF

21

R7528

CERM

16V

10%

0.01uF

402

2

1

C7546

402

1/16W

1%

4.02K

MF-LF

2

1

R7547

402

MF-LF

1/16W

1%

499

2

1

R7544

20%

6.3V X5R 402

0.22UF

2

1

C7541

10%

CERM

402

0.0068uF

25V

2

1

C7580

NO STUFF

0.001uF

50V

10%

402

CERM

2

1

C7542

402

1% 1/16W MF-LF

5.23K

2

1

R7548

0.01uF

10% 16V CERM 402

2

1

C7543

402

5%

1

1/16W MF-LF

2

1

R7507

402

1

MF-LF

1/16W

5%

2

1

R7557

NO STUFF

CERM

10% 16V

0.01uF

402

2

1

C7581

402

CERM

0.01uF

16V

10%

2

1

C7582

1/16W MF-LF

5%

402

0

21

R7581

5% 1/16W MF-LF

402

0

21

R7582

MF-LF

1/16W

1%

1M

402

21

R7598

1/16W

402

MF-LF

1M

1%

21

R7592

53B8

1uF

402

10%

6.3V CERM

2

1

C7595

CRITICAL

10KOHM-5%

0603-LF

2

1

R7549

10%

402

CERM

50V

470pF

21

C7598

10% 50V

CERM

470pF

402

21

C7592

CERM

50V

10%

402

820pF

2

1

C7534

CRITICAL

470K

402

2

1

R7546

CRITICAL

0.36uH-30A-1.2M-OHM

SM-IHLP

21

L7505

CRITICAL

SM-IHLP

0.36UH-30A-1.2M-OHM

21

L7555

MF-LF

402

0

5%

1/16W

21

R7594

402

CERM

10V

20%

NO STUFF

0.1uF

2

1

C7594

SM

2 1

XW7530

603

10%

1uF

16V X5R

2

1

C7511

CRITICAL

16V

20%

33uF

POLY CASED2E-SM

2

1

C7510

10%

1uF

16V X5R 603

2

1

C7561

CRITICAL

CASED2E-SM

20%

33uF

16V POLY

2

1

C7560

RJK0305DPB

LFPAK

CRITICAL

321

4

5

Q7500

LFPAK

RJK0305DPB

CRITICAL

321

4

5

Q7550

RJK0301DPB

CRITICAL

LFPAK

321

4

5

Q7501

CRITICAL

RJK0301DPB

LFPAK

321

4

5

Q7502

LFPAK

RJK0301DPB

CRITICAL

321

4

5

Q7551

LFPAK

RJK0301DPB

CRITICAL

321

4

5

Q7552

CRITICAL

16V

20%

33uF

POLY CASED2E-SM

2

1

C7515

CRITICAL

HPA00141AIDCKR

SC70-5

5

2

4

3

1

U7595

OMIT

QFN

ISL9504CRZ

9

19

14

5

44

18

20

43 42 41 40 39 38 37

13

22

27

35

49

7

15

4

31

2

28

34

1

29

33

3

8

6

25

30

32

23

24

21

12 11

16

46 45

17

10

47

26

36

48

U7530

051-7150 A.0.0

59 84

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

IMVP6 CPU VCore Regulator

CPUISENS_NEG

IMVP6_DROOP

CPUISENS_POS

CPUVCORE_IOUT

=PP3V3R5V_S0_CPUISENS

IMVP6_VDIFF_RC

IMVP6_VO_R

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUISENS_NEG_RC

=PPVIN_S0_IMVP6

=PP3V3_S0_IMVP6

IMVP6_NTC_R

=PPVOUT_S0_IMVP6_REG

=PPVIN_S0_IMVP6

IMVP6_COMP_RC

IMVP_DPRSLPVR

IMVP6_SOFT

IMVP6_VDIFF

CPU_DPRSTP_L

IMVP6_BOOT2

IMVP6_BOOT1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

IMVP6_PHASE1

MIN_NECK_WIDTH=0.25 mm

IMVP6_UGATE1

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_LGATE1

IMVP6_ISEN1

IMVP6_UGATE2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

IMVP6_PHASE2

IMVP6_LGATE2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_VID<2>

IMVP6_VID<3>

IMVP6_VID<1> IMVP6_VID<0>

IMVP6_ISEN2

IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP

IMVP6_DFB

IMVP6_VSEN_P

IMVP6_VSEN_N

CPU_PSI_L IMVP_PWRGD_IN

VR_PWRGD_CK410_L

VR_PWRGOOD_DELAY

IMVP_VR_ON

IMVP6_NTC

IMVP6_VR_TT

IMVP6_RBIAS

IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

PM_DPRSLPVR

IMVP6_VID<6>

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_IMVP6_R

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

IMVP6_VID<5>

GND_IMVP6_SGND

IMVP6_VID<4>

=PP5V_S0_IMVP6

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

PP5V_S0_IMVP6_VDD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=12V

PPVIN_S0_IMVP6_R

84B6

65C1

59C6

65A3

5C7

8B6

59D4

65B3

65D3

59D7

5C7

84C6

5C7

9C1

5C7

59A2

5C7

84B6

5D7

5C7

5D7

9C1

65A1

http://mycomp.su/x/

NC4

NC3

NC2

NC1

EXTVCC

FCB

INTVCC

PGOOD

3_3VOUT

RUN_SS2

ITH2

RUN_SS1

ITH1

SW1

TG1

BOOST1

BG1

PLLIN

SENSE1+ SENSE1-

VOSENSE1

BOOST2

TG2

BG2

SW2

PLLFLTR

SENSE2+

VOSENSE2

SENSE2-

THRML_PAD

SGND

PGND

VIN

D

S

G

D

S

G

D

S

G

R1-

R1+

R2

V-

V+

+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Q7621 limit)

11.5A max output

PLACE C7675 NEAR U7670 PIN 7

Placement Note:

5V S3 FET

5V S0 FET

Vout = 0.8V * (1 + Ra / Rb)

NC

NOTE: Be aware of pull-ups to VIN on these signals.

<Rb>

If unconnected, powers up with VIN.

(L7660 & Q7660 limit)

8A max output

Vout = 1.49V

<Rb>

<Ra>

NC

Vout = 4.98V

<Ra>

Connect to RUNSS pins to control outputs.

CRITICAL

CMDSH-3

SOD-323

2

1

D7624

1uF

CERM

402

10%

6.3V 2

1

C7605

16V

10%

402

0.01uF

CERM

2

1

C7607

MF-LF

1/16W

5%

402

1M

2

1

R7630

CERM

20%

0.1uF

402

10V

2

1

C7630

470pF

50V

10%

402

CERM

2

1

C7625

50V

5%

402

47pF

CERM

2

1

C7626

10

402

1/16W MF-LF

5%

2

1

R7600

10% X5R

603

1uF

16V

2

1

C7600

LTC3728LXC

QFN

CRITICAL

91

33

14

26

15

6

11

1230

1328

2

27

19

32

29

16

10

8

5

20

4

21

17

18

7

U7600

CRITICAL

CMDSH-3

SOD-323

2

1

D7664

10V

20%

402

CERM

0.1uF

2

1

C7670

470pF

10% CERM

50V

402

2

1

C7665

100pF

CERM

402

5%

50V

2

1

C7666

10K

MF-LF

402

5%

1/16W

2

1

R7665

CERM

50V

0.001uF

402

10%

2

1

C7662

52.3K

1/16W

402

MF-LF

1%

2

1

R7627

25V

402

X7R

1000pF

10%

NO STUFF

2

1

C7628

10K

1/16W MF-LF

402

1%

2

1

R7628

IHLP2525CZ-SM

2.2uH-14A

CRITICAL

21

L7660

402

1% 1/16W MF-LF

39.2K

2

1

R7668

NO STUFF

25V

10%

402

X7R

1000pF

2

1

C7668

34.0K

1/16W

1%

MF-LF 402

2

1

R7667

50V

10%

402

CERM

470pF

2

1

C7667

MF-LF

1/16W

5%

402

1M

2

1

R7670

402

6.3V

10%

1uF

CERM

2

1

C7602

603

6.3V

20%

4.7uF

CERM

2

1

C7601

30K

MF-LF 402

5% 1/16W

2

1

R7603

10K

MF-LF 402

5% 1/16W

2

1

R7604

CERM 402

10% 16V

0.01uF

2

1

C7604

10%

1uF

16V X5R 603

2

1

C7641

MF-LF 402

1/16W

0

5%

2

1

R7664

MF-LF

0

402

5%

1/16W

2

1

R7624

NO STUFF

10%

X7R 402

1000pF

25V

2

1

C7661

402

CERM

10V

20%

0.1uF

2

1

C7664

805

CERM

6.3V

20%

22UF

2

1

C7690

805

CERM

6.3V

20%

22UF

2

1

C7691

0.1uF

20% 10V CERM 402

2

1

C7624

NO STUFF

1000pF

402

X7R

25V

10%

2

1

C7621

10%

CERM

50V

402

0.001uF

2

1

C7622

6.3V POLY

CRITICAL

20%

150UF

CASE-C3

2

1

C7652

20%

22UF

6.3V CERM

805

2

1

C7650

CERM 805

22UF

20%

6.3V

2

1

C7651

1/16W

5%

402

MF-LF

0

P5VP1V5_SKIP

2

1

R7606

P5VP1V5_CONT

0

MF-LF 402

5% 1/16W

2

1

R7607

SM

21

XW7600

16V X5R 402

10%

0.1uF

2

1

C7620

0.1uF

10% 16V X5R 402

2

1

C7623

1%

402

MF-LF

1/16W

4.02K

2

1

R7623

10% 16V X5R 402

0.1uF

2

1

C7660

1%

402

1/16W MF-LF

3.65K

2

1

R7660

402

X5R

16V

10%

0.1uF

2

1

C7663

1%

909

402

MF-LF

1/16W

2

1

R7663

20% POLY

CRITICAL

330UF

CASE-D2E-LF

2.5V

2

1

C7692

IRF7832Z

SO-8

CRITICAL

321

4

8765

Q7661

MF-LF

1/16W

402

1%

1.21K

2

1

R7669

1%

MF-LF

1/16W

402

23.7K

2

1

R7629

20%

6.3V CERM 805

22UF

2

1

C7617

20%

6.3V CERM

805

22UF

2

1

C7616

0.0022uF

402

CERM

50V

10%

2

1

C7615

100K

5% 1/16W MF-LF

402

21

R7615

FDC638P

SM-LF

CRITICAL

4

3

6

5

2

1

Q7610

0.0022uF

402

CERM

10% 50V

21

C7610

MF-LF

1/16W

5%

402

100K

21

R7610

CRITICAL

MICROFET3X3

FDM6296

3 2 1

4

5

Q7621

MICROFET3X3

FDM6296

CRITICAL

3 2 1

4

5

Q7620

MICROFET3X3

FDM6296

CRITICAL

321

4

5

Q7660

CASED2E-SM

POLY

16V

20%

33uF

CRITICAL

2

1

C7640

1uF

10% 16V X5R 603

2

1

C7681

CASED2E-SM

POLY

33uF

20% 16V

CRITICAL

2

1

C7680

SM-IHLP

2.0UH

CRITICAL

21

L7620

IRF7707PBF

TSSOP

CRITICAL

7632

4

851

Q7615

402

MF-LF

1/16W

1%

10

21

R7671

10% 16V

0.1UF

402

X5R

2

1

C7675

0.001UF

10% 50V CERM 402

2

1

C7674

INA326EA-250

MSOP

CRITICAL

7

4

5

8

1

6

2

3

U7670

100K

1% 1/16W

402

MF-LF

2

1

R7674

22UF

805

20% CERM

6.3V

2

1

C7671

22UF

20%

6.3V 805

CERM

2

1

C7672

0.002

1%

1/4W MF-LF

1206

21

R7675

402

MF-LF

1/16W

1%

2.0K

2

1

R7672

4.53K

1%

402

MF-LF

1/16W

2

1

R7620

33K

MF-LF

5% 1/16W

402

2

1

R7625

47PF

5% CERM

50V

402

2

1

C7627

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

051-7150 A.0.0

8460

5V / 1.5V Power Supply

=PP1V5_S0_NB1V5_SENSE

NB1V5_ISENSE_VCC

NB1V5_ISENSE_R2

P1V5S0_NB_IOUT

P1V5S0_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_BG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_ITH_RC

PP5V_S5_P5VP1V5_INTVCC PP5V_S5_P5VP1V5_INTVCC

P5VP1V5_FSEL

=PPVIN_S5_P5VP1V5

P5VS5_BOOST_RC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_BOOST_RC

=PP1V5_S0_REG

=PP5V_S0_P5VS0

=P5VS0_EN_L

=PP5V_S3_P5VS3

=PP5V_S3_FET

P5VS3_EN_L_RC

=P5VS3_EN_L

=PP3V3_S0_NB1V5ISENS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P1V5S0_SNS_R_N

P1V5S0_VOSNS

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_SNS_R_P

P5VP1V5_FSEL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_TG

P1V5S0_BOOST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_SNS_N

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_BG

MIN_LINE_WIDTH=0.6 mm

P5VS5_BOOST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12V

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_P5VP1V5_R

P5VS5_TG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P5VS5_ITH

P5VS5_RUNSS

P1V5S0_ITH

P1V5S0_RUNSS

=P5VP1V5_PGOOD

VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S5_P5VP1V5_INTVCC

P5VP1V5_FCB

=PP5V_S5_P5VP1V5_VCC

=PP1V5_S0_NB

=PP5V_S0_FET

NB1V5_ISENSE_R1_P

NB1V5_ISENSE_R1_N

P5VS5_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P5VS5_SNS_P

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V MIN_NECK_WIDTH=0.25 mm

GND_P5VP1V5_SGND

P5VS5_ITH_RC

P5VS5_VOSNS

=PP5V_S5_REG

P5VS0_EN_L_RC

65C8

60D3 60D6

65C8

60D6

65C6

53B5

60B3 60B3

60C4

65C1

5A2

65B1

64C6

65B1 65B3

64B6

65A3

60B3

64C2

60D3

65B1

19D7

65B3

http://mycomp.su/x/

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH SYNC/MODE

RUN/SS

RT

THRM_PAD

PVINAVIN

PG

MODE

OVT FB

AGND PGND

SWEN

D

S

G

D

S

G

D

S

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.2V D3Cold FET

2.5V D3Cold FET

<Rb>

<Ra>

2.5V S3 Regulator

Continuous

Burst

NOTE: Be aware of pull-up on this signal.

Connect RUNSS off-page to control If unconnected, powers up with PVIN.

Vout = 0.8V * (1 + Ra / (Rb + Rc))

<Rc>

<Rb>

<Ra>

Vout = 0.6V * (1 + Ra / Rb)

2.5V S0 FET

Vout = 1.205V

(Switcher limit)

2.5A max output

1.2V S3 Regulator

Vout = 2.50V

(U7700 limit)

1.5A max output

SM-MSS5131

2.2uH-1.9A-23M-OHM

CRITICAL

21

L7700

5%

CERM

402

50V

10pF

2

1

C7706

402

MF-LF

634K

1% 1/16W

2

1

R7707

200K

1/16W

1%

402

MF-LF

2

1

R7708

0.1uF

16V X5R

10%

402

2

1

C7701

1

MF-LF

402

5%

1/16W

21

R7700

22UF

805

20%

6.3V CERM

2

1

C7756

22UF

CERM

805

20%

6.3V 2

1

C7755

22UF

CERM 805

20%

6.3V

2

1

C7752

805

22UF

CERM

6.3V

20%

2

1

C7751

50V

5%

402

CERM

22pF

2

1

C7750

1/16W

1%

402

MF-LF

47.0K

2

1

R7750

MF-LF

402

1%

1/16W

61.9K

2

1

R7751

SM-LF

CRITICAL

1.0UH-3.48A

21

L7750

MF-LF

402

1%

1/16W

30.9K

2

1

R7752

CRITICAL

TSSOP-LF

LTC3412

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U7750

SM

21

XW7750

309K

MF-LF 402

1% 1/16W

2

1

R7754

50V

470pF

CERM

402

10%

2

1

C7757

1/16W

5%

402

MF-LF

0

NO STUFF

2

1

R7755

1M

1/16W

5%

402

MF-LF

2

1

R7757

0

MF-LF 402

5% 1/16W

2

1

R7756

CERM

402

5%

50V

22pF

2

1

C7754

MF-LF

402

1%

1/16W

8.25K

2

1

R7753

CERM 402

10% 50V

0.0022uF

2

1

C7753

50V

0.0022uF

10%

CERM

402

2

1

C7720

402

5% 1/16W MF-LF

100K

21

R7720

0.0022uF

10% 50V

402

CERM

2

1

C7770

100K

5% 1/16W MF-LF

402

21

R7770

6.3V

20%

805

CERM

22uF

2

1

C7700

TPS62510

BQA

CRITICAL

11

1

10

2

8

5

7

4

6

9

3

U7700

FDC637AN

SOT23

4

3

6

5

2

1

Q7720

FDC637AN

SOT23

4

3

6

5

2

1

Q7721

402

CERM

10%

0.0022uF

50V

2

1

C7721

160K

402

5% 1/16W MF-LF

21

R7721

CERM

6.3V

20%

805

22UF

2

1

C7759

6.3V

20%

805

CERM

22UF

2

1

C7758

SOT23

FDC637AN

CRITICAL

4

3

6

5

2

1

Q7770

6.3V

20%

22UF

CERM 805

2

1

C7710

6.3V

20%

22UF

CERM 805

2

1

C7711

X7R

50V

0.01UF

402

10%

2

1

C7722

6.3V

20%

22UF

CERM 805

2

1

C7709

SYNC_DATE=05/07/2006

SYNC_MASTER=M59_MG

2.5V & 1.2V Regulators

A.0.0051-7150

61 84

P2V5D3C_EN_RC

=PP2V5_D3C_FET

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_S3_P2V5S3_SVIN

=PPVIN_S3_P2V5S3

=PP1V2_S3_REG

=P2V5D3C_EN

=PP2V5_S0_P2V5S0

=PP2V5_S0_FET

P2V5S0_EN_RC

=PP2V5_S0_P2V5S0

=P2V5S0_EN

=P2V5S3_PGOOD

P1V2S3_VFB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V2S3_SW

=P1V2S3_PGOOD

=P1V2D3C_EN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_P1V2S3_SGND

P1V2S3_ITH P1V2S3_MODE

P1V2S3_RUNSS

P1V2S3_ITH_RC

P1V2S3_VFB_DIV

P1V2S3_RT

=PPVIN_S3_P1V2S3

P2V5S3_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=P2V5S3_EN

=PP1V2_S0_P1V2S0

=PP1V2_D3C_FET

P1V2D3C_EN_RC

P2V5S3_VFB

=PP2V5_S3_REG

65A6

41C4

65A8

41C3

65C3

65D8

64D5

61D3

65A8 61C3

64D5

64B8

64D5

5D7

65C3

41C3

65D6

65C8

65B8

http://mycomp.su/x/

G

S

D

V5DRV

LL

VOUT

PGOOD

VFB

TRIP

DRVL

DRVH

TON

EN_PSV

VBST

THRM_PAD

GND

PGND

V5FILT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Vout = 1.825V

1.8V D3Cold FET

<Ra>

(P1V8S3_FB)

<Rb>

18A max output (L7820 limit)

Vout = 0.75V * (1 + Ra / Rb)

POLY

CASE-D2E-LF

20%

330UF

2.5V

2

1

C7842

1/16W

402

1%

MF-LF

21.5K

2

1

R7821

1/16W

402

MF-LF

15K

5%

2

1

R7822

X5R

16V

603

10%

1uF

2

1

C7802

805

6.3V CERM

22UF

20%

2

1

C7841

POLY

20%

CASE-D2E-LF

330UF

2.5V

2

1

C7843

20%

CERM 805

6.3V

22UF

2

1

C7847

CERM

22UF

805

6.3V

20%

2

1

C7846

25V

0.0047UF

10%

CERM 402

2

1

C7845

150K

402

MF-LF

1/16W

5%

21

R7845

5%

47PF

402

CERM

50V

2

1

C7820

402

MF-LF

1/16W

5%

470K

2

1

R7846

FDM6296

MICROFET3X3

CRITICAL

3

2

1

4

5

Q7845

X5R

16V

603

10%

1uF

2

1

C7831

CASED2E-SM

POLY

16V

20%

33uF

2

1

C7830

1uF

10%

603

16V X5R

2

1

C7832

CRITICAL

LFPAK

RJK0305DPB

321

4

5

Q7820

CRITICAL

RJK0303DPB

LFPAK

321

4

5

Q7822

RJK0303DPB

LFPAK

CRITICAL

321

4

5

Q7821

1.2UH

FDA1055

CRITICAL

21

L7820

6.3V 603

4.7UF

CERM

20%

2

1

C7801

10

MF-LF

402

1%

1/16W

21

R7801

402

10% 16V

0.1UF

X5R

2

1

C7803

MF-LF 402

1/16W

1%

12.1K

2

1

R7804

1%

1/16W

402

MF-LF

182K

2

1

R7803

6.3V

10%

CERM

1UF

402

2

1

C7800

CRITICAL

QFN

TPS51117RGY_QFN14

3

5

14

4

10

11

2

15

6

8

12

7

1

9

13

U7800

SYNC_DATE=05/07/2006

SYNC_MASTER=M59_MG

1.8V Supply

051-7150

62 84

A.0.0

=P1V8S3_PGOOD

P1V8S3_TRIP

P1V8S3_FB

=PP5V_S3_P1V8S3

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

P1V8S3_V5FILT

=P1V8S3_EN

P1V8S3_TON

P1V8S3_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P1V8S3_DRVL

MIN_NECK_WIDTH=0.25 mm

P1V8S3_DRVH

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S3_P1V8S3

=PPBUS_S0_P1V8S0

=PP1V8_D3C_FET

P1V8D3C_EN_RC

=PP1V8_S0_P1V8S0

=P1V8D3C_EN

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

P1V8S3_LL

MIN_NECK_WIDTH=0.25 mm

=PP1V8_S3_REG

65B8

64C2

65B1

64A6

65C1

65B8

65B6

64D5

5A2

http://mycomp.su/x/

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

OUT

D

S

G

D

S

G

D

S

G

V-

V+

+

-

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(L7970 limit)

4.5A max output

3.3V S3 FET

Vout = 3.32V

<Rb>

<Ra>

(L7920 limit)

10A max output

Vout = 1.05V

<Ra>

(P1V05S0_FB)

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

3.3V S5 Regulator

1.05V S0 Regulator

1.05V Current Sense

3.3V S0 FET

3.3V D3Cold FET

close to inductor

Placement Note:

Keep C7990, C7991, R7990, R7994 and R7997

603

X5R

10%

1uF

16V

2

1

C7951

ISL6269BCRZ

CRITICAL

QFN

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U7950

50V

5%

402

CERM

15PF

2

1

C7957

CERM

402

20% 16V

0.01uF

2

1

C7958

MF-LF 402

1% 1/16W

30.9K

2

1

R7958

1/16W

5%

MF-LF

0

NO STUFF

402

2

1

R7954

0

MF-LF 402

5% 1/16W

2

1

R7955

57.6K

1%

402

MF-LF

1/16W

2

1

R7956

16V

10%

402

CERM

0.01UF

2

1

C7956

IRF7832Z

CRITICAL

SO-8

321

4

8765

Q7971

CASE-D2E-LF

POLY

20%

330UF

2.5V

2

1

C7989

470pF

402

50V

CERM

10%

2 1

C7998

CERM

1uF

402

10%

6.3V

2

1

C7995

402

MF-LF

1/16W

1M

1%

21

R7998

50V

470pF

402

CERM

10%

2 1

C7992

402

MF-LF

1/16W

1M

1%

21

R7992

CRITICAL

0603-LF

10KOHM-5%

2

1

R7997

402

MF-LF

1/16W

1K

1%

2

1

R7996

1%

20.0K

402

1/16W MF-LF

21

R7993

10%

CERM-X5R

0.47UF

6.3V

402

2 1

C7990

MF-LF

1%

1/16W

20.0K

402

21

R7991

1%

1K

MF-LF

NO STUFF

402

1/16W

21

R7994

1%

1/16W

402

MF-LF

649

2

1

R7990

53B3

0

402

5% 1/16W MF-LF

21

R7949

20% 16V

0.01uF

402

CERM

NO STUFF

2

1

C7949

402

10% 25V CERM

0.0047uF

2

1

C7920

0

1/16W MF-LF

402

5%

2 1

R7920

CERM

25V

0.0047uF

10%

402

21

C7947

FDC638P

SM-LF

4

3

6

5

2

1

Q7947

1/16W

100K

5%

MF-LF

402

21

R7947

0.0022uF

402

CERM

50V

10%

21

C7945

SM-LF

FDC638P

4

3

6

5

2

1

Q7945

402

MF-LF

1/16W

5%

100K

21

R7945

MF-LF

402

1/16W

5%

0

2

1

R7909

6.3V

20%

X5R 402

0.22uF

2

1

C7909

0.22uF

402

X5R

6.3V

20%

2

1

C7959

402

CERM

10%

0.0022uF

50V

NO STUFF

2

1

C7970

402

MF-LF

1/16W

0

5%

NO STUFF

2

1

R7970

MICROFET3X3

CRITICAL

FDM6296

321

4

5

Q7920

MICROFET3X3

FDM6296

CRITICAL

321

4

5

Q7921

FDM6296

MICROFET3X3

CRITICAL

321

4

5

Q7970

CRITICAL

33uF

CASED2E-SM

POLY

16V

20%

2

1

C7980

1/16W

1%

402

5.62K

MF-LF

21

R7910

SM-LF

FDC638P

4

3

6

5

2

1

Q7948

402

MF-LF

1/16W

5%

150K

21

R7948

10% 25V CERM

0.0047uF

402

2

1

C7948

1.8UH

SM-IHLP

CRITICAL

21

L7970

CRITICAL

33UF

20% 16V POLY CASED2E-SM

2

1

C7930

402

6.3V

0.22UF

CERM-X5R

10%

2 1

C7991

CRITICAL

SC70-5

HPA00141AIDCKR

5

2

4

3

1

U7995

4.7

402

MF-LF

1/16W

5%

2

1

R7959

150UF

CASE-C3

POLY

20%

6.3V

2

1

C7942

603

CERM1

20%

6.3V

2.2UF

2

1

C7902

1000pF

402

X7R

25V

10%

NO STUFF

2

1

C7921

SM

21

XW7900

6.3V

2.2UF

CERM1

603

20%

2

1

C7900

1uF

16V X5R 603

10%

2

1

C7901

QFN

CRITICAL

ISL6269BCRZ

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U7900

10%

470pF

CERM

402

50V

2

1

C7907

0.022uF

CERM-X5R

10% 16V

402

2

1

C7908

MF-LF

5%

0

402

1/16W

NO STUFF

2

1

R7904

51.1K

402

MF-LF

1/16W

1%

2

1

R7908

5%

402

MF-LF

0

1/16W

2

1

R7905

MF-LF

1%

402

57.6K

1/16W

2

1

R7906

0.01UF

CERM

402

10% 16V

2

1

C7906

22UF

805

6.3V CERM

20%

2

1

C7941

805

22UF

20%

6.3V CERM

2

1

C7940

1/16W

402

MF-LF

3.32K

0.1%

2

1

R7921

732

402

0.1%

MF-LF

1/16W

2

1

R7922

IHLP

CRITICAL

4.7uH

21

L7920

2.2UF

CERM1

603

20%

6.3V 2

1

C7952

20%

22UF

CERM

6.3V

805

2

1

C7986

805

22UF

20%

6.3V CERM

2

1

C7985

1/16W

1%

402

MF-LF

3.32K

2

1

R7971

1/16W

1%

MF-LF

4.42K

402

2

1

R7972

402

MF-LF

1%

1/16W

2.8K

21

R7960

NO STUFF

1000pF

402

X7R

25V

10%

2

1

C7971

SM

21

XW7950

2.2UF

CERM1

603

20%

6.3V 2

1

C7950

051-7150

63 84

A.0.0

SYNC_DATE=05/07/2006

3.3V / 1.05V Power Supplies

SYNC_MASTER=M59_MG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V05S0_PHASE

P1V05S0_UG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P1V05S0_LG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PP5V_S0_P1V05S0

P1V05S0_FCCM

=P1V05S0_EN

=P1V05S0_PGOOD

P1V05S0_COMP

P1V05S0_FSET

P1V05S0_ISEN

P1V05S0_FB

=PP1V05_S0_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V05S0_BOOT

=PPVIN_S0_P1V05S0

P3V3S5_EN_RC

P1V05S0_BOOT_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V05ISENS_NEG

P1V05ISENS_POS

P1V05S0_IOUT

=PP3V3R5V_S0_P1V05ISENS

P1V05ISENS_RC

=PP3V3_S0_P3V3S0

=P3V3D3C_EN_L

=PP3V3_D3C_FET

=PP3V3_S0_FET

=P3V3S0_EN_L

=PP5V_S5_P3V3S5

=P3V3S5_PGOOD

P3V3S5_FB

GND_P3V3S5_SGND

P3V3S5_COMP

P3V3S5_FSET

P1V05S0_FB_RC

GND_P1V05S0_SGND

P1V05S0_COMP_R

P3V3S5_FB_RC

=P3V3S5_EN

=P3V3S3_EN_L

P3V3S3_EN_L_RC

=PP3V3_S3_FET

=PP3V3_S3_P3V3S3

P1V05ISENS_NTC

P3V3S5_BOOT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P3V3S5_FCCM

P3V3S5_COMP_R

P3V3S5_BOOT_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

P3V3S5_ISEN

MIN_NECK_WIDTH=0.25 mm

P3V3S5_PHASE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

P3V3S5_LG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_UG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P3V3S5

P3V3D3C_EN_L_RC

=PP3V3_S5_REG

P3V3S0_EN_L_RC

65D8

5D7

53A4

65C3

5D7

5B7

65B1

64C6

64B5

5C7

5B7

5B2

5C7

65C1

5C7

65A3

63D8

63C8

64D5

65A5

65B5

64D5

65B1

50A5

5B7

5C7

5B7

64A6

64B6

65C5

65C3

5B7

65C1

65D5

http://mycomp.su/x/

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

G

D

S

G

D

S

G

D

S

V3 V4

RST*

V2

V1

GND

V-

V+

OUT

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

to test for 2v5 and 1v2 S3 valid for GPUVCORE_EN. But was disconnected for C8053 placement.

This signal was used as an option previously

GPIO38 low.

The SB can turn off the GPUVcore (and by extension all D3Cold rails) by driving

1.5V / 1.05V PWRGD Circuit

Does not include D3C rails for GPU!!

deassert while GPU

GPU requires 1.2V, 1.8V, 2.5V and

3.3V rise after VCore is up.

1.5V Enable has pull-up to PBUS

1.8V Enable has pull-up to PBUS

Need to ensure that ISL6269 PGOOD does not

2.5V S3 and 1.2V S3 supplies are controlled

Supply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Run (S0)

Battery Off (G3Hot)

0

1

1 1

SMC_PM_G2_ENABLE

0 0

1

PM_SLP_S4_L

0

1

PM_SLP_S3_L

(Switcher limit)

200mA max output

Vout = 3.425

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

by ethernet power control circuit.

(P5VS5_PGOOD)

(PM_SLP_S4_L)

PowerPlay is changing GPU core voltage.

Unused PGOOD Signals

<Ra>

3.425V "G3Hot" Supply

LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)

NOTE: R8065 acts as 10K pull-up for PGOOD signal

1.5V Comp threshold set to 1.32V (88%)

0.89V Reference

Reports when 1.5V S0 and 1.05V S0 are in regulation

5V Enable has pull-up to PBUS

Other S0 Rails PWRGD Circuit

ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)

(PM_SLP_S3_L)

Power Control Signals

LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)

CRITICAL

TSOT23-8

LT3470

3

51

2

4

8

6

7

U8000

2N7002DW-X-F

SOT-363

4

5

3

Q8056

25V

10% X5R

10UF

1206-1

2

1

C8000

1/16W

5%

402

MF-LF

10K

2

1

R8069

1/16W

5%

402

MF-LF

10K

2

1

R8068

SOT-363

2N7002DW-X-F

4

5

3

Q8058

2N7002DW-X-F

SOT-363

1

2

6

Q8058

CRITICAL

TSOT-23

LTC2903

5

4

3

1

6

2

U8070

402

CERM

10V

20%

0.1uF

2

1

C8070

22UF

CERM 805

20%

6.3V

2

1

C8015

200K

MF-LF

1% 1/16W

402

2

1

R8011

10K

5% 1/16W MF-LF 402

2

1

R8065

10V

20%

402

CERM

0.1uF

2

1

C8081

SC70

MC74VHC1G08

5

4

1

2

3

U8081

402

10K

5%

MF-LF

1/16W

2

1

R8081

10V

20%

402

CERM

0.1uF

2

1

C8060

1/16W

402

MF-LF

10K

5%

2

1

R8076

MF-LF 402

1% 1/16W

845K

2

1

R8070

CERM

0.1UF

20% 10V

402

2

1

C8071

100K

MF-LF

402

1%

1/16W

2

1

R8071

1/16W

1%

402

MF-LF

365K

2

1

R8072

CERM

0.1UF

20% 10V

402

2

1

C8073

100K

MF-LF

402

1%

1/16W

2

1

R8073

402

10V

20%

0.1UF

CERM

2

1

C8075

68.1K

1/16W

1%

402

MF-LF

2

1

R8074

1/16W

1%

402

MF-LF

100K

2

1

R8075

0.047UF

10% 16V

CERM

402

2

1

C8053

SM-LF

LMC7211

2

5

1

3

4

U8060

SC70

MC74VHC1G08

5

4

1

2

3

U8080

402

CERM

10V

20%

0.1UF

2

1

C8080

59C7

1/16W

1%

402

MF-LF

4.99K

2

1

R8063

1/16W

1%

402

MF-LF

27.4K

2

1

R8061

1/16W

1%

402

MF-LF

10K

2

1

R8064

1/16W

402

MF-LF

10K

1%

2

1

R8062

63B8

5%

402

MF-LF

1/16W

10K

2

1

R8051

10K

1/16W

5%

402

MF-LF

2

1

R8050

SOT-363

2N7002DW-X-F

1

2

6

Q8057

2N7002DW-X-F

SOT-363

1

2

6

Q8050

49D7 26A5

1/16W

5%

402

MF-LF

100K

2

1

R8054

SOT-363

2N7002DW-X-F

4

5

3

Q8057

348K

MF-LF 402

1% 1/16W

2

1

R8010

5%

402

MF-LF

10K

1/16W

2

1

R8055

SOT-363

2N7002DW-X-F

1

2

6

Q8055

2N7002DW-X-F

SOT-363

4

5

3

Q8055

CRITICAL

33uH

CDPH4D19F-SM

21

L8010

2N7002DW-X-F

SOT-363

4

5

3

Q8059

470K

MF-LF 402

5% 1/16W

2

1

R8059

2N7002DW-X-F

SOT-363

1

2

6

Q8059

2N7002DW-X-F

SOT-363

4

5

3

Q8050

68C8

22pF

CERM

402

5%

50V

2

1

C8010

402

1/16W MF-LF

5%

100K

2

1

R8056

49C5 43B7

42A8 23C3

MF-LF

5%

402

1/16W

100K

2

1

R8057

49C5

41B6 23C3

1/16W

5%

402

MF-LF

100K

2

1

R8058

50A4

49D5

0.22uF

X5R 402

20%

6.3V 2

1

C8005

61B5

61C8

1/16W

402

10K

5% MF-LF

2

1

R8053

10K

MF-LF 402

1/16W

5%

2

1

R8052

3.3V G3Hot Supply & Power Control

SYNC_DATE=08/01/2006

8464

051-7150 A.0.0

SYNC_MASTER=M59_MG

PP0V9_S0

S0PGOOD_0V9_DIV

S0PGOOD_2V5_DIV

PP2V5_S0

PP3V3_S0

S0PGOOD_5V_DIV

PP5V_S0

=PP3V42_G3H_REG

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

=PP3V3_S3_PWRCTL

PM_SLP_S3_LS5V_L

MAKE_BASE=TRUE

=GPUVCORE_EN

GPUVCORE_EN

MAKE_BASE=TRUE

P5VS5_RUNSS

=P5VS0_EN_L

P1V5S0_RUNSS

LIO_P3V3S0_EN_L

=GPUVCORE_PGOOD

=PP3V42_G3H_PWRCTL

=PP3V3_S5_P1V5PG

PGOOD_MUXED_S0_OR_S0D3C

=P5VP1V5_PGOOD

=PP3V3_S0_ALLSYSPG

=P2V5S3_PGOOD

PM_SLP_S4_L

MAKE_BASE=TRUE

=PP5V_S5_PWRCTL

=P1V2S3_PGOOD

=P1V8S3_PGOOD

TP_P1V8S3_PGOOD

MAKE_BASE=TRUE

TP_P5V_P1V5_PGOOD

MAKE_BASE=TRUE

P1V5S0_COMP_POS

P1V0_P1V5PG_REF

IMVP_PWRGD_IN

ALL_SYS_PWRGD

MAKE_BASE=TRUE

P1V5P1V05S0_PGOOD

PP1V5_S0

SMC_PM_G2_EN

SMC_PM_G2_EN_L

=P3V3S5_EN

LIO_P3V3S3_EN

=RTUSB_EN

=P1V8S3_EN

=P5VS3_EN_L

=MEMVREF_EN

=P1V05S0_EN

PM_SLP_S4_LS5V

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

P3V42G3H_FB

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

P3V42G3H5_BOOST

P1V5S0_PGOOD

=PPVIN_G3H_P3V42G3H

=P3V3S3_EN_L

PM_SLP_S3

=P1V05S0_PGOOD

=P2V5D3C_EN

=P3V3D3C_EN_L

=P1V2D3C_EN

=P1V8D3C_EN

MAKE_BASE=TRUE

P1V8D3C_EN

=P3V3S0_EN_L

MAKE_BASE=TRUE

P3V3S0_EN_L

=P2V5S0_EN

MAKE_BASE=TRUE

P5VS5_PGOOD

=PBUSVSENS_EN

=ENET_VMAIN_AVLBL

=PP5V_S5_PWRCTL

PM_SLP_S3_L

MAKE_BASE=TRUE

=PP3V3_S0_PWRCTL

S0PGOOD_PWROK

TP_P2V5S3_P1V2S3_PGOOD

MAKE_BASE=TRUE

P1V2R2V5D3C_EN_LS5V

MAKE_BASE=TRUE

P3V3D3C_EN_L

MAKE_BASE=TRUE

SB_GPUVCORE_DISABLE_L

TP_SB_GPIO38

PM_SLP_S3_L_GPUVCORE_EN

60C4

60C5

5D7

47B6

65D3

79D5

65B1

47B6

65D3

65B1

79D5

65D6

65A6

65C3

65B1

65D5

65C3

68C8

5D7

60B3

5B7

5C1

64A8

65C3

79A2

60B3

65A3

64D8

62B4

65C6

63D7

5C1

46C7

62C8

60A4

32B3

63B8

64C8

5D7

65A6

63D3

61C3

63C8

61B3

62A6

63D8

61D3

53C3

39C8

64B8

65A3

79A4

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"S3AC" rail is ON in S3 on AC, OFF in S3 on battery

SYNC_MASTER=M59_MG

SYNC_DATE=05/07/2006

Power Aliases

84

A.0.0

65

051-7150

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GND

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S0

=PP1V5_S0_LIO

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

=PPBUS_S0_P1V8S0

=PPBUS_S0_PPBU_S0_FW

=PP5V_S0_FET

=PP5V_S0_ISENSECAL

=PP5V_S0_AUDIO_XW

=PP5V_S0_GPUBBCTL =PP5V_S0_LPCPLUS

=PP5V_S0_KBDLED

=PP5V_S0_FAN_RT

=PP5V_S0_FAN_LT

=PP5V_S0_MEMVTT =PP5V_S0_SB

=PP5V_S0_INVERTER

=PP5V_S0_HDD =PP5V_S0_IMVP6

=PP5V_S0_IDE

=PP5V_S0_DVI_DDC

=PP5V_S3_TOPCASE

=PP5V_S3_IR

=PP5V_S3_FET

=PP5V_S5_REG

=PP5V_S3_CAMERA

=PP5V_S3_SYSLED

=PP5V_S0_P1V05S0

=PP5V_S3_RTUSB

=PP5V_S0_GPUVCORE

=PP5V_S0_P5VS0

=PP5V_S3_P5VS3 =PP5V_S3_P1V8S3

=PP5V_S5_PWRCTL

=PP5V_S5_P5VP1V5_VCC =PP5V_S5_LIO

=PP5V_S5_SB =PP5V_S5_P3V3S5

=PPBUS_S5_FW_FET

=PPFW_P3V3FWPHY

=PPFW_FW_CPS

=PPFW_PORT2_VP

=PPFW_PORT1_VP

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S3

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=33V

PPBUS_S5_FW_FET

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.3 mm

MAKE_BASE=TRUE

PP3V3_D3C

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

=PP3V3_D3C_GPU

MIN_NECK_WIDTH=0.2 mm

PP3V42_G3H

VOLTAGE=3.425V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 mm

=PP3V42_G3H_SMCUSBMUX

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS

=PP3V42_G3H_LIDSWITCH

=PP5V_S0_SB_HPD

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ATX =PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB

=PP1V5_S0_REG

=PP1V2_D3C_FET

=PP1V5_S0_CPU =PP1V5_S0_NB1V5_SENSE

=PP1V2_S0_PCIE_GPU_VDDR

=PP1V2_S0_PCIE_GPU_PVDD

=PP1V2_S0_PCIE_GPU

=PP1V2_S0_GPU_VDDPLL

=PP1V2_S3_REG

=PP1V2_S0_P1V2S0

=PP1V2_S3_ENET

PP1V2_D3C

VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.22 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.2V

PP1V2_S3

=PPVCORE_S0_GPU_REG

=PP2V5_D3C_FET

=PPVCORE_S0_GPU_BBP

=PPVCORE_S0_GPU

=PP2V5_S0_GPU_VDDC_CT

=PP2V5_S0_GPU_VDD25

=PP2V5_S0_GPU_PVDD

=PP2V5_S0_GPU

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPVCORE_D3C_GPU

PP2V5_D3C

VOLTAGE=0 MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

=PPDCIN_G3H_LIO

=PPVIN_G3H_P3V42G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

PPDCIN_G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_CPU =PP1V05_S0_FSB_NB =PP1V05_S0_NB_CRT

=PP1V05_S0_SB_CPU_IO

=PP1V05_S0_NB_VTT

=PP1V05_S0_REG

=PPVCORE_S0_NB =PPVCORE_S0_SB

=PP0V9_S0_MEM_TERM

=PP0V9_S0_MEMVTT_LDO

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.05V

PP1V05_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=0.9V

PP0V9_S0

MAKE_BASE=TRUE

=PPVIN_S0_P1V05S0 =PPVIN_S0_GPUVCORE

=PP3V42_G3H_SB_RTC

=PP3V42_G3H_SMC_CLK =PP3V42_G3H_LIO

=PPVOUT_S0_IMVP6_REG

=PPBUS_G3H_LIO_CONN

=PPVIN_S5_P5VP1V5 =PPVIN_S0_IMVP6 =PPVIN_S5_P3V3S5 =PPBUS_S5_FWPWRSW

=PPVCORE_S0_CPU

=PP3V42_G3H_SMCVREF

=PP3V42_G3H_SMC_PWRGD

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.9V

PPBB_S0_GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 mm

=PPVIN_S3_P1V8S3

=PPBUS_G3H_S3AC

=PP3V42_G3H_REG

=PPVOUT_S0_GPUBBP_LDO

=PPBB_S0_GPU

=PNVOUT_S0_GPUBBN_REG

=PNBB_S0_GPU

=PP3V3_S3AC_FET

=PP3V3_S3_ENET

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PNBB_S0_GPU

VOLTAGE=-0.7V

MIN_LINE_WIDTH=0.38 mm

PP3V3_S3AC

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.22 mm VOLTAGE=3.3V

VOLTAGE=1.1V MAKE_BASE=TRUE

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PPBUS_S0_INVERTER

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.6 mm

PP2V5_S0

=PP2V5_S0_NB_VCCA_3GBG =PP2V5_S0_NB_VCC_TXLVDS =PP2V5_S0_NB_VCCA_LVDS =PP2V5_S0_NB_DPLL =PP2V5_S0_LVDS_MUX

=PP2V5_S0_FET

MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP1V8_D3C

=PP1V8_S3_MEM =PP1V8_S3_MEM_NB =PP1V8_S3_MEMVREF =PP1V8_S0_MEMVTT

=PP1V8_S3_FW

=PP1V8_S0_P1V8S0

=PP1V8R2V0_S0_FB_GPU =PP1V8_S0_FB_VDD =PP1V8_S0_FB_VDDQ

=PP2V5_S3_ENET =PP2V5_S0_P2V5S0

=PP1V8_D3C_FET

=PP1V8_S3_REG

PP1V5_S0_NB

VOLTAGE=0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

=PP1V5_S0_NB

=PP1V5_S0_NB =PP1V5_S0_NB_3G =PP1V5_S0_NB_3GPLL =PP1V5_S0_NB_PCIE =PP1V5_S0_NB_PLL =PP1V5_S0_NB_VCCD_LVDS =PP1V5_S0_NB_TVDAC =PP1V5_S0_NB_VCCAUX =PP1V5_S0_NB_VCCD_HMPLL

=PP1V5_S0_ITPMOUNT

VOLTAGE=0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S5_SB

=PP3V3_S5_SB_IO =PP3V3_S5_SB_PM =PP3V3_S5_SB_USB

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_REG

=PP3V3_S5_ROM =PP3V3_S5_P1V5PG =PP3V3_S3_P3V3S3

=PP3V3_S0_LCD

=PPVIN_S3_P2V5S3

=PP3V3_S0_P3V3S0

=PP3V3_S3_P3V3S3AC =PP3V3_S3_RTALS

=PP3V3_S3_FET

=PP3V3_S3_TPM

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PP3V3_S0_GPU =PP3V3_S0_GPUBBP =PP3V3_S0_GPUBBN =PP3V3_S0_GPU_VDDR3 =PP3V3_D3C_GPU_GPIOS

=PP3V3_D3C_FET

=PP3V3_D3C_DDC_DVI

=PP1V8R3V3_S0_GPU_VDDR5

=PP1V8R3V3_S0_GPU_VDDR4

=PP3V3_D3C_VGASYNC =PP3V3_D3C_GPU_LVDS_DDC

=PP3V3_S0_DDC_LCD

=PP3V3_S0_IDE

=PP3V3_S0_CK410

=PP3V3_S0_FET

=PP3V3_S0_INVERTER

=PP3V3_S0_IMVP6

=PP3V3_S0_NB =PP3V3_S0_NB_VCC_HV =PP3V3_S0_SB

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_PCI =PP3V3_S0_SB_PM =PP3V3_S0_SB_VCC3_3 =PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_SB_VCCLAN3_3

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_TPM =PP3V3_S0_KBDLED =PP3V3_S0_THRM_SNR =PP3V3_S0_REMTHMSNS =PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_SMC_BSB

=PP3V3_S0_SMC_LS

=PP3V3_S0_RSTBUF

=PP3V3_S0_FAN_LT

=PP3V3_S0_ALLSYSPG

=PP3V3_S0_FAN_RT

=PP3V3R5V_S0_GPUISENS

=PP3V3R5V_S0_CPUISENS

=PPSPD_S0_MEM

=PP3V3R5V_S0_P1V05ISENS

=PP3V3_S0_EDET

=PP3V3_S0_NB1V5ISENS

=PP3V3_S0_LVDS_MUX

=PP3V3_S0_GPU_TDIODE =PP3V3_S0_PWRCTL

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S0

=PP3V3_S3_TOPCASE =PP3V3_S3_LTALS =PP3V3_S3_MEMVREF =PP3V3_S3_FW

=PPVIN_S3_P1V2S3 =PP3V3_S3_PWRCTL

=PP3V3_S3_PCI

PP3V3_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.8V

PP1V8_S3

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

PP2V5_S3

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.6 mm

=PP2V5_S3_REG

11C5

34C8

11B3

34C6

39D8

29D6

50D7

9B7

34B8

19D7

53D7

39D6

29D3

70B8

25C8

20B4

50B1

74A7

8C7

19D7

19D2

53A6

39B8

29B2

70B5

73D8

19D7

23D8

25D2

34A8

20A4

23D5

49D4

69D8

7D5

12C2

25C4

19D7

63A2

19C8

9D7

39B5

19D7

28D6

19D7

70A8

73D5

65C6

65C8

19D7

19C4

23D4

26C5

25B6

33D8

19C7

23B3

25C6

29A6

79C6

37D7

47D6

53A8

51C4

56C7

45C3

64D8

47C6

49D3

51C4

25B6

25D6

25C6

25B2

25D6

25C2

25C8

60C1

9B7

39D7

53C7

47C6

7B6

12B7

19D7

24C3

19C8

53A4

16D3

25D3

47D6

66C4

59D7

8D7

64C8 39B4

19C5

19A6

19A4

79D3

28D3

16B6

70A5

72D8

61D3

62C1

60A7

19D7

19A5

19D6

17B6

19D7

23B7

23D1

25D2

24B3

63D8

58C2

57C6

74D2

33D3

14D6

19C6

25D8

21D3

25C4

26B8

25B8

25B4

25D3

25A4

58D4

79D5

29A3

79B3

78C5

37C3

64B5

5D1

53D3

62A6

42B8

60B1

5A2

47D3

68A6

5D2

55B5

56C4

5D2

31C5

25D8

76B8

78B5

59D7

36D6

77B5

78D3

78B5

60A2

60C8

5A4

50B8

63B7

46C7

68D7

60B2

60A4

62C8

64B8

60B6

5D1

25C8

63D6

43C1

42C8

38B7

44B3

44D3

79D7

71B2

46B5

49C2

5D2

78D3

77A1

24A5

24B5

24A5

24A3

24B5

24A3

25A8

5A2

61B1

8B7

60A8

67C7

67A1

74B8

61B3

39A8

79D7

68C1

61C1

68B7

53A5

74C6

74A8

75C8

79D7

5D1

64D5

7B5

12A7

19D6

21C1

17D3

5B2

16C8

24D3

30D5 31C2

64B5

63B7

68D7

26D6

35B7

5D1

59D1

5A1

60D7

59D4

63D6

43D7

8B5

50B7

50B5

64A8

27C3

62D7

41C6

64D2

68B5 69D6

68A2 69D2

41C4 39A5

5A2

76B7

64B5

17D6

17C6

19A8

79C5

61D1

79D7

28B2

14C2

32C6

31C5

37B2

62A6

69B8

72D5

39D3

61C3

62A4

5A2

19D7

19B5

13D2

19B8

17C6

19D2

16D1

17C6

11C4

64C5

24C3

23A7

22C6

11B5

22D8

24B3

24A5

63D1

54D4

64C5

63D2

76D5

61D8

63C8

41C5

55D4

63D1

50B1

27C5

50B1

68C4

68B8

68A4

74C6

71D6

63C7

77B2

74B7

77D5

79A7

76D3

36D6

33C7

63D6

76A8

59D8

14C7

17C6

22B5

21C3

24C3

26D1

26B6

24B5

24C3

24D3

24B3

58C7

55B6

10C5

52D4

27D8

27D5

27D3

27C3

50D3

26B4

56C7

64B1

56C4

68D2

59A5

28A6

63B3

40B6

60A6

79A4

52B5

64B6

64B5

78D3

5B2

32C5

37A7

61B7

64C6

37D5

50B5

61D4

http://mycomp.su/x/

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0458

Left I/O Power Connector

NC

518S0369

Battery Connector (Digital Signals)

87438-0663

M-RT-SM

CRITICAL

6

5

4

3

2

1

J8200

M-RT-SM

SM04B-ACH

CRITICAL

4

3

2

1

6

5

J8250

10

402

MF-LF

1/16W

5%

2

1

R8250

051-7150 A.0.0

8466

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PBus-In,Batt. & 3G Pwr Connectors

=SMBUS_BATT_SDA SMC_BS_ALRT_L

=SMBUS_BATT_SCL

GND_BATT

=PPBUS_G3H_LIO_CONN

27C1

65C3

5D1

5A1

http://mycomp.su/x/

OUT

PCIE_PVSS

PCIE_VDDR_12

PCIE_PVDD_12

PCIE_VSS

(1.2V)

PCIE_VSS

(2 OF 7)

PCI EXPRESS POWER & GROUND

IN

IN IN

IN

OUT

PCIE_REFCLKP PCIE_REFCLKN

PERST* PERST*_MASK

PCIE_TEST

PCIE_RX15N

PCIE_RX14P

PCIE_RX13N

PCIE_RX12N

PCIE_RX12P

PCIE_RX1P

PCIE_TX0P PCIE_TX0N

PCIE_TX1P

PCIE_TX2N

PCIE_TX1N

PCIE_TX2P

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8N

PCIE_TX8P

PCIE_TX9P

PCIE_TX10P

PCIE_TX9N

PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13N

PCIE_TX13P

PCIE_TX14N

PCIE_TX14P

PCIE_TX15N

PCIE_TX15P

PCIE_CALRP PCIE_CALRN

PCIE_CALI

PCIE_RX1N

PCIE_RX2N

PCIE_RX2P

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6N

PCIE_RX6P

PCIE_RX7N

PCIE_RX7P

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX13P

PCIE_RX14N

PCIE_RX0N

PCIE_RX0P

PCIE_RX15P

PCI-EXPRESS BUS INTERFACE

(1 OF 7)

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

2000mA

NC

100mA

X5R 402

0.1uF

16V10%

21

C8481

402

0.1uF

X5R16V10%

21

C8482

0.1uF

40216V10% X5R

21

C8479

402

0.1uF

X5R16V10%

21

C8480

402

0.1uF

X5R16V10%

21

C8477

402X5R16V10%

0.1uF

21

C8478

402

0.1uF

X5R16V10%

21

C8475

402

0.1uF

X5R16V10%

21

C8476

402

0.1uF

X5R16V10%

21

C8473

402

0.1uF

X5R16V10%

21

C8474

40210% 16V X5R

0.1uF

21

C8420

402

0.1uF

X5R16V10%

21

C8471

402

0.1uF

X5R16V10%

21

C8472

402

0.1uF

X5R16V10%

21

C8469

402

0.1uF

X5R16V10%

21

C8470

402

0.1uF

X5R16V10%

21

C8467

10%

0.1uF

16V X5R 402

21

C8421

402

0.1uF

X5R16V10%

21

C8468

402

0.1uF

X5R16V10%

21

C8465

402

0.1uF

X5R16V10%

21

C8466

402

0.1uF

X5R16V10%

21

C8463

402

0.1uF

X5R16V10%

21

C8464

10% 16V X5R

0.1uF

402

21

C8450

402

0.1uF

X5R16V10%

21

C8461

0.1uF

402X5R16V10%

21

C8462

402

0.1uF

X5R16V10%

21

C8459

402

0.1uF

X5R16V10%

21

C8460

402

0.1uF

X5R16V10%

21

C8457

10% 16V X5R 402

0.1uF

21

C8451

0.1uF

402X5R16V10%

21

C8458

MF-LF

1/16W

402

1%

562

2

1

R8496

1%

2.0K

MF-LF 402

1/16W

2

1

R8495

1.47K

1%

402

MF-LF

1/16W

2

1

R8497

BGA

M56P

OMIT

R24

AL27

AK32

R23

AK31

AK30

AK29

AK26

AJ32

AJ30

AJ29

AJ28

AJ26

AH29

P30

AH27

AH26

AH24

AG31

AG29

AG26

AG25

AF30

AF29

AF28

P29

AF26

AE29

AE27

AE26

AD31

AD29

AD26

AD25

AC30

AC29

P28

AC28

AC26

AC24

AC23

AB29

AB27

AB26

AB23

AA31

AA29

P26

AA26

AA25

AA23

Y30

Y29

Y28

Y26

Y24

W29

W27

P25

W26

W24

V31

V29

V26

V25

V24

U30

U29

U28

P24

U26

U24

T29

T27

T26

T24

R31

R29

R26

R25

N30

N24

AM27

AL32

AL31

AL30

AL29

N29

N28

N27

AM31

AM30

AM29

AM28

N26

N25

W23

V23

U23

P23

N23

U8400

CERM

1uF

6.3V

402

10%

2

1

C8402

10% 16V X5R

0.1uF

402

21

C8448

402

CERM

10%

6.3V

1uF

2

1

C8401

10%

6.3V CERM

402

1uF

2

1

C8407

10% 16V X5R

0.1uF

402

21

C8449

10%

6.3V CERM

402

1uF

2

1

C8413

1uF

402

CERM

6.3V

10%

2

1

C8406

1uF

402

CERM

6.3V

10%

2

1

C8411

10%

6.3V CERM

402

1uF

2

1

C8412

20%

CERM 805

6.3V

22UF

2

1

C8400

22UF

6.3V

805

CERM

20%

2

1

C8410

10% 16V X5R

0.1uF

402

21

C8446

22UF

6.3V

805

CERM

20%

2

1

C8405

200-OHM-EMI

0402

2

1

L8400

10% 16V X5R

0.1uF

402

21

C8447

10% 16V X5R

0.1uF

402

21

C8444

10% 16V X5R

0.1uF

402

21

C8445

10% 16V X5R

0.1uF

402

21

C8442

10% 16V X5R

0.1uF

402

21

C8443

10% 16V X5R

0.1uF

402

21

C8440

10% 16V X5R

0.1uF

402

21

C8441

10% 16V X5R

0.1uF

402

21

C8438

10% 16V X5R 402

0.1uF

21

C8439

10% 16V X5R

0.1uF

402

21

C8436

10% 16V X5R

0.1uF

402

21

C8437

10% 16V X5R

0.1uF

402

21

C8434

10% 16V X5R

0.1uF

402

21

C8435

10% 16V X5R

0.1uF

402

21

C8432

10% 16V X5R

0.1uF

402

21

C8433

10% 16V X5R

0.1uF

402

21

C8430

10% 16V X5R 402

0.1uF

21

C8431

10% 16V X5R

0.1uF

402

21

C8428

10% 16V X5R

0.1uF

402

21

C8429

10% 16V X5R

0.1uF

402

21

C8426

10% 16V X5R

0.1uF

402

21

C8427

16V X5R

0.1uF

40210%

21

C8424

10% 16V X5R

0.1uF

402

21

C8425

0.1uF

10% X5R 40216V

21

C8422

10% 16V X5R

0.1uF

402

21

C8423

10% 16V X5R

0.1uF

402

21

C8455

10% 16V X5R

0.1uF

402

21

C8456

M56P

BGA

OMIT

AF24

AG24

AA27

Y27

AB28

AA28

AC25 AB25

AD27 AC27

AE28 AD28

AF25

AE25

AG27

AF27

AH28

AG28

AJ25

AH25

R27

P27

T28 R28

U25 T25

V27 U27

W28

V28

Y25

W25

AK27

AJ27

AA24

Y31

W31

AA32

Y32

AB30 AA30

AC31 AB31

AD32 AC32

AE30

AD30

AF31

AE31

AG32

AF32

AH30

AG30

P31

N31

R32 P32

T30 R30

U31 T31

V32

U32

W30

V30

AJ31

AH31

AL28

AK28

AD24

AE24

AB24

U8400

402

0.1uF

X5R16V10%

21

C8485

402

0.1uF

X5R16V10%

21

C8486

402

0.1uF

X5R16V10%

21

C8483

402

0.1uF

X5R16V10%

21

C8484

051-7150

SYNC_DATE=(MASTER)

A.0.0

8467

ATI M56 PCI-E

SYNC_MASTER=(MASTER)

=PP1V2_S0_PCIE_GPU_PVDD

PP1V2_S0_PCIE_GPU_PVDD_F

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PEG_D2R_N<1>

PEG_D2R_N<12>

PEG_R2D_P<5>

PEG_R2D_C_P<9>

=PP1V2_S0_PCIE_GPU_VDDR

PEG_D2R_C_N<2>

PEG_R2D_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<13>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

GPU_PCIE_CALRP

GPU_PCIE_CALI

PEG_R2D_N<0>

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_N<3>

PEG_R2D_N<6>

PEG_R2D_N<5>

PEG_R2D_N<9>

PEG_R2D_N<8>

PEG_R2D_N<7>

PEG_R2D_N<11>

PEG_R2D_N<10>

PEG_R2D_N<12>

PEG_R2D_N<13>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_P<0>

PEG_R2D_P<1>

PEG_R2D_P<2>

PEG_R2D_P<3>

PEG_R2D_P<4>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<9>

PEG_R2D_P<10>

PEG_R2D_P<11>

PEG_R2D_P<12>

PEG_R2D_P<13>

PEG_R2D_P<14>

PEG_R2D_P<15>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_N<1>

PEG_R2D_C_P<1>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_N<4>

PEG_R2D_C_P<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_N<9>

PEG_R2D_C_P<10>

PEG_R2D_C_N<10>

PEG_R2D_C_P<11>

PEG_R2D_C_N<11>

PEG_R2D_C_P<12>

PEG_R2D_C_P<13>

PEG_R2D_C_N<12>

PEG_R2D_C_P<15>

PEG_CLK100M_GPU_P

PEG_RESET_L

PEG_CLK100M_GPU_N

PEG_R2D_C_N<15>

GPU_PCIE_CALRN

PEG_D2R_C_N<0>

PEG_D2R_C_N<1>

PEG_D2R_C_N<3>

PEG_D2R_C_N<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_D2R_C_N<7>

PEG_D2R_C_N<8>

PEG_D2R_C_N<9>

PEG_D2R_C_N<10>

PEG_D2R_C_N<11>

PEG_D2R_C_N<12>

PEG_D2R_C_N<13>

PEG_D2R_C_N<14>

PEG_D2R_C_N<15>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_P<6>

PEG_D2R_N<5>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_P<9>

PEG_D2R_N<10>

PEG_D2R_P<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<13>

PEG_D2R_P<14>

PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_D2R_C_P<0>

PEG_D2R_C_P<1>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<7>

PEG_D2R_C_P<8>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11>

PEG_D2R_C_P<12>

PEG_D2R_C_P<13>

PEG_D2R_C_P<14>

PEG_D2R_C_P<15>

=PP1V2_S0_PCIE_GPU

65C6

13D3

13C3

13B3

65C6

13B3

13A3

13B3

13C3

13B3

13C3

13B3

13C3

13B3

13A3

13B3

13A3

34B4

26B1

34B4

13B3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

65C6

http://mycomp.su/x/

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

PG EN

VIN

ADJ

VOUT

GND

G

D

S

OUT

G

D

S

G

D

S

G

D

S

CAP-

FB

OUT

SHDN_L

CAP+

LIN/SKIP_L

IN

GND

V-

V+

+

-

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

decreased slew rate

Stuff 4.7ohm for

<Rc>

(GPUVCORE_FB)

18A max output (L8520 limit)

Vout(high) = 0.6V * (1 + Ra / Req)

Vout(low) = 0.6V * (1 + Ra / Rb)

<Rb>

Back-Bias Positive Supply

Back-bias positive supply provides VDDC + 0.5V when active.

Vout(high) = 0.59V * (1 + Ra/Req)

pull-up must be powered before VCore

NOTE: BBP tracks VDDC based on GPU voltage GPIO.

Pull-up voltage must be high enough to

SI3446DV max Vgs is 1.6V Vin must be > 2.8V

For proper M56 power sequence, this

When inactive, provides VDDC to BBP pins.

<Rb>

<Ra>

satisfy BBP FET Vgs (where Vs = 1.2V)

<Ra>

Vout = -Vin * Rb / Ra

(Regulator limit)

125mA max output

GPU VCore Supply

<Ra>

<Rc>

Vout(low) = 0.59V * (1 + Ra/Rb)

Req = Rb || Rc

Vout = (1.58V /) 1.50V 180mA max output (LDO limit)

When inactive, provides VSS to BBN pins.

Rb = -Vout / 50 uA

Ra = Vin / 50 uA

Recommended values:

<Rb>

Vout = 1.10V / 0.95V

Vout = -0.55V

Back-bias negative supply provides VSS - 0.55V when active.

GPU VCore Current Sense

Back-Bias Negative Supply

Req = Rb || Rc

Keep C8590, C8591 R8590, R8594 and R8597

Placement Note:

close to inductor

2.5V

330UF

POLY

CASE-D2E-LF

20%

2

1

C8542

402

1%

MF-LF

1/16W

3.01K

2

1

R8521

402

1%

5.11K

MF-LF

1/16W

2

1

R8522

1/16W

1%

402

MF-LF

5.11K

21

R8510

20%

2.2UF

603

CERM1

6.3V 2

1

C8502

2.2UF

603

20%

CERM1

6.3V 2

1

C8500

603

X5R

16V

10%

1uF

2

1

C8501

QFN

ISL6269BCRZ

CRITICAL

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U8500

5%

15pF

50V 402

CERM

2

1

C8507

150K

1/16W

1%

402

MF-LF

2

1

R8508

470pF

CERM

50V 402

10%

2

1

C8508

402

5%

MF-LF

1/16W

0

2

1

R8504

0

1/16W

5%

402

MF-LF

NO STUFF

2

1

R8505

57.6K

MF-LF 402

1% 1/16W

2

1

R8506

0.01UF

CERM

402

10% 16V

2

1

C8506

22UF

805

CERM

20%

6.3V 2

1

C8540

6.3V

22UF

20%

805

CERM

2

1

C8541

SM

21

XW8500

25V

1000pF

X7R 402

10%

NO STUFF

2

1

C8522

NO STUFF

402

25V X7R

1000pF

10%

2

1

C8521

6.3V

20%

805

CERM

22UF

2

1

C8556

805

6.3V CERM

20%

22UF

2

1

C8557

24.9K

1%

402

MF-LF

1/16W

2

1

R8555

MF-LF 402

1% 1/16W

16.2K

2

1

R8556

0.01UF

CERM

402

10% 16V

2

1

C8555

CRITICAL

SOT23-6-LF

FAN2558

61

4

2

3 5

U8550

20%

6.3V

2.2uF

603

CERM1

2

1

C8551

2.5V

330UF

20%

CASE-D2E-LF

POLY

2

1

C8543

1/16W MF-LF

1%

402

12.4K

21

R8523

10K

MF-LF

402

5%

1/16W

2

1

R8560

SOT23-LF

2N7002

2

1

3

Q8570

MF-LF

1/16W

402

4.7K

1%

2

1

R8570

CERM 402

10%

0.0022uF

50V

NO STUFF

2

1

C8570

1/16W

5%

402

MF-LF

0

GPU_BB_CTL

21

R8561

10%

CERM

402

470pF

50V

2 1

C8598

53B6

10%

CERM

470pF

50V

402

2 1

C8592

1/16W

1%

1M

MF-LF

402

21

R8598

1/16W MF-LF

1%

1M

402

21

R8592

6.3V

10%

402

CERM

1uF

2

1

C8595

1%

1/16W

402

MF-LF

20.0K

21

R8593

1/16W

402

MF-LF

1%

20.0K

21

R8591

402

MF-LF

1/16W

1%

649

2

1

R8590

1/16W MF-LF

402

1K

1%

NO STUFF

21

R8594

10%

CERM-X5R

0.47UF

6.3V

402

2 1

C8590

0603-LF

10KOHM-5%

CRITICAL

2

1

R8597

402

1%

1K

1/16W MF-LF

2

1

R8596

MF-LF 402

174K

1/16W

1%

NO STUFF

2

1

R8554

402

10% 16V

0.022uF

CERM-X5R

2

1

C8523

10K

402

MF-LF

1/16W

5%

2

1

R8524

1/16W

5%

MF-LF

402

10K

21

R8525

CERM

50V

10%

0.0022uF

NO STUFF

402

2

1

C8520

5% 1/16W MF-LF

10K

402

2

1

R8526

2N7002DW-X-F

SOT-363

4

5

3

Q8523

SOT-363

2N7002DW-X-F

1

2

6

Q8523

SOT23-LF

2N7002

NO STUFF

2

1

3

Q8554

1%

MF-LF

1/16W

402

68.1K

2

1

R8587

MF-LF

1/16W

402

1%

11.3K

2

1

R8588

20%

6.3V CERM1 603

2.2uF

2

1

C8581

603

20%

10uF

X5R

6.3V 2

1

C8580

6.3V

20% CERM

22UF

805

2

1

C8589

MAX1673

SOI

CRITICAL

4

5

1

8

7

6

2

3

U8580

TSOP-LF

SI3446DV

4

3 6

5

2

1

Q8575

NO STUFF

0

MF-LF 402

5% 1/16W

2

1

R8520

20%

6.3V X5R 402

0.22UF

2

1

C8509

20%

33uF

16V POLY CASED2E-SM

CRITICAL

2

1

C8530

RJK0305DPB

CRITICAL

LFPAK

321

4

5

Q8520

RJK0301DPB

CRITICAL

LFPAK

321

4

5

Q8522

CRITICAL

LFPAK

RJK0301DPB

321

4

5

Q8521

CRITICAL

1.2UH

FDA1055

21

L8520

10%

402

6.3V

0.22UF

CERM-X5R

2 1

C8591

HPA00141AIDCKR

CRITICAL

SC70-5

5

2

4

3

1

U8595

4.7

402

MF-LF

1/16W

5%

2

1

R8509

SM

21

XW8502

SM

21

XW8501

SYNC_DATE=(MASTER)

GPU (M56) Core Supplies

68

A.0.0

84

SYNC_MASTER=(MASTER)

051-7150

=PPVCORE_S0_GPU_REG

=PPVIN_S0_GPUVCORE

GND_GPUVCORE_PGND

GPUISENS_NEG

GPUISENS_RC

GPUVCORE_ISEN

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_UG

MIN_NECK_WIDTH=0.25 mm

GPU_VCORE_HIGH

=PP5V_S0_GPUVCORE

GPUBBN_FB

=PP3V3_S0_GPU

=PNVOUT_S0_GPUBBN_REG

GPUISENS_NTC

GPUVCORE_FB_LOW

GPUVCORE_FB_RC

GPUBB_EN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

GPUBBN_CAPP

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

GPUBBN_CAPN

=PP3V3_S0_GPUBBN

GPU_VCORE_HIGH_RC

GPU_VCORE_LOW

=GPUVCORE_EN

GPUVCORE_FCCM

GPUVCORE_COMP

GPUVCORE_FSET

GPUVCORE_COMP_R

GPUBBP_ADJ_LOW

=PP3V3_S0_GPUBBP

GPUBB_EN

GPU_VCORE_HIGH

=PP5V_S0_GPUBBCTL

GPU_GENERICD

GPUBB_EN

=PPVOUT_S0_GPUBBP_LDO

GPUBB_EN_L

=PPVCORE_S0_GPU_BBP

GPUBB_EN_L

GPUBBP_ADJ

=PP3V3R5V_S0_GPUISENS

GPUVCORE_IOUT

GPUISENS_POS

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

GPUVCORE_PHASE

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

GPUVCORE_LG

GPUVCORE_FB

=GPUVCORE_PGOOD

GND_GPUVCORE_SGND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPUVCORE_BOOT

MIN_NECK_WIDTH=0.25 mm

GPUVCORE_BOOT_R

MIN_LINE_WIDTH=0.25 mm

74D2

68B8

68A6

68B8

65A8

65C1

5C7

68A8

65B1

5C7

65A3

65D3

5C7

68A6

65A3

71C5

64B5

5D7

65A3

68A4

68B4

65A1

74C3

68A4

65D3

68A5

65A6

68B7

5D7

65A3

5C7

64D8

http://mycomp.su/x/

MEMORY & CORE POWER / GROUND

(1.0V/1.2V)

(7 OF 7)

VDDR1

VSS

(1.8V/2.0V)

VSS

VDDC

BBP BBN

VDDCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NONE)

- =PP1VR1V3_GPU_VCORE

BOM options provided by this page:

Signal aliases required by this page:

Page Notes

Power aliases required by this page:

- =PP1V5_GPU_VDD15

14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

2.0A @ 500MHz 1.8V GDDR3

100mA (Preliminary)

M56P

BGA

OMIT

P17

P15

P7

P6

P5

P1

N8

N7

N3

M32

A31

M28

M24

M9

M8

M7

M6

M3

L29

L7

L6

A25

L1

K30

K27

K17

K16

K12

K10

J30

J28

J24

A22

J21

J16

J12

J9

J6

J3

H32

H28

H21

H20

A19

H16

H7

H5

H1

G25

G22

G21

G20

G19

G16

A16

G13

F30

F27

F24

F22

F21

F19

F18

F16

F15

A13

F13

F10

F6

F3

E32

E30

E28

E25

E19

E16

A11

E13

E12

E9

E8

E5

D30

D11

C27

C24

C21

A8

C20

C18

C15

C10

AM13

AM2

AL13

AL1

AK16

AJ10

AH16

AH11

AH10

C9

AG23

AG16

AG11

AF16

AF14

AE17

AE16

AE15

AE14

AE8

C6

AD17

AD16

AD15

AD14

AD13

AD10

AD9

AD8

AD7

AD6

C5

AC10

AC9

AA6

AA4

Y7

Y6

Y5

Y1

W18

W16

C4

V19

V17

V6

V3

U18

U14

U10

U9

U8

U7

B32

U6

U5

U1

T19

T15

T10

R16

R14

R6

R3

B1

A2

K23

C32

C1

A30

A24

A21

AA1

Y10

Y9

Y8

A18

V1

R9

R1

P10

P9

P8

N10

N9

M10

M1

A15

L32

L24

L23

K24

K21

K20

K19

K13

K11

J32

A12

J20

J19

J18

J13

J11

J10

J1

H19

H13

F32

A9

A3

W17

W10

U19

T23

T14

P16

K14

T18

T17

T16

R19

R18

R17

R15

AD11

AC12

AC11

P19

W19

W15

W14

V18

V16

V15

V14

U17

U16

U15

P18

P14

AC14

V10

M23

K18

AC17

Y23

R10

K15

U8400

10% 16V X5R 402

0.1uF

2

1

C8697

6.3V CERM

1uF

402

10%

2

1

C8696

6.3V CERM

1uF

402

10%

2

1

C8691

10% 16V X5R 402

0.1uF

2

1

C8692

10%

402

1uF

6.3V CERM

2

1

C8610

10%

402

1uF

CERM

6.3V

2

1

C8609

10%

402

1uF

CERM

6.3V

2

1

C8608

10%

402

1uF

CERM

6.3V

2

1

C8607

10%

402

1uF

CERM

6.3V

2

1

C8606

10%

402

1uF

CERM

6.3V

2

1

C8605

10%

1uF

CERM

6.3V

402

2

1

C8604

6.3V CERM

1uF

402

10%

2

1

C8616

6.3V CERM

1uF

402

10%

2

1

C8615

6.3V CERM

1uF

402

10%

2

1

C8614

6.3V CERM

1uF

402

10%

2

1

C8613

6.3V CERM

1uF

402

10%

2

1

C8612

MF-LF

5%

0

603

1/10W

2

1

R8630

10%

402

1uF

CERM

6.3V

2

1

C8634

10%

402

1uF

CERM

6.3V

2

1

C8633

10%

402

1uF

CERM

6.3V

2

1

C8632

10%

402

1uF

CERM

6.3V

2

1

C8631

10%

402

1uF

CERM

6.3V

2

1

C8660

6.3V CERM

1uF

402

10%

2

1

C8666

10%

402

1uF

CERM

6.3V

2

1

C8659

10%

402

1uF

CERM

6.3V

2

1

C8658

10%

402

1uF

CERM

6.3V

2

1

C8657

6.3V CERM

1uF

402

10%

2

1

C8665

6.3V CERM

1uF

402

10%

2

1

C8664

6.3V CERM

1uF

402

10%

2

1

C8663

10%

402

1uF

CERM

6.3V

2

1

C8656

6.3V CERM

1uF

402

10%

2

1

C8662

10%

402

1uF

CERM

6.3V

2

1

C8655

6.3V CERM

1uF

402

10%

2

1

C8661

10%

402

1uF

CERM

6.3V

2

1

C8672

6.3V CERM

1uF

402

10%

2

1

C8678

10%

402

1uF

CERM

6.3V

2

1

C8671

10%

402

1uF

CERM

6.3V

2

1

C8670

10%

402

1uF

CERM

6.3V

2

1

C8669

6.3V CERM

1uF

402

10%

2

1

C8677

6.3V CERM

1uF

402

10%

2

1

C8676

6.3V CERM

1uF

402

10%

2

1

C8675

10%

402

1uF

CERM

6.3V

2

1

C8668

6.3V CERM

1uF

402

10%

2

1

C8674

10%

402

1uF

6.3V CERM

2

1

C8667

6.3V CERM

1uF

402

10%

2

1

C8673

20%

805

22UF

CERM

6.3V 2

1

C8653

22UF

805

CERM

6.3V

20%

2

1

C8652

20%

805

22UF

6.3V CERM

2

1

C8651

20%

6.3V CERM

805

22UF

2

1

C8650

6.3V CERM

1uF

402

10%

2

1

C8683

6.3V CERM

1uF

402

10%

2

1

C8682

6.3V CERM

1uF

402

10%

2

1

C8681

6.3V CERM

1uF

402

10%

2

1

C8680

10%

402

1uF

CERM

6.3V

2

1

C8679

20%

6.3V CERM

805

22UF

2

1

C8601

10%

402

1uF

CERM

6.3V

2

1

C8611

22UF

805

CERM

6.3V

20%

2

1

C8690

22UF

805

CERM

6.3V

20%

2

1

C8695

22UF

805

CERM

6.3V

20%

2

1

C8630

22UF

805

CERM

6.3V

20%

2

1

C8600

69 84

051-7150 A.0.0

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

ATI M56 Core Power

=PPVCORE_S0_GPU

VOLTAGE=1.2V

PPVCORE_S0_GPU_VDDCI

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PPBB_S0_GPU

=PP1V8R2V0_S0_FB_GPU

=PNBB_S0_GPU

70B8

74A7

70B5

65A6

70A8

53C7

70A5

53A5

65D1

65B6

65D1

http://mycomp.su/x/

IO

OUT

OUT OUT

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IN IN

IN

IN IN

IO

IO IO

IO

IO IO

IO

OUT

DQA_58 DQA_59

WEA1*

DQA_61 DQA_62

MVREFD_0 MVREFS_0

VDDRH0

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15

DQMA_0* DQMA_1* DQMA_2* DQMA_3* DQMA_4* DQMA_5* DQMA_6* DQMA_7*

QSA_1

QSA_2

QSA_0

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0* QSA_1* QSA_2* QSA_3* QSA_4* QSA_5* QSA_6* QSA_7*

CLKA0 CLKA0*

CSA0_0*

CKEA0

RASA0*

CASA0*

WEA0*

ODTA0

CLKA1*

CSA1_0*

CKEA1

RASA1*

CASA1*

ODTA1

DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43

DQA_45

DQA_44

DQA_46 DQA_47 DQA_48

DQA_50 DQA_51

DQA_49

DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57

DQA_60

DQA_63

VSSRH0

CLKA1

CSA0_1*

CSA1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE A

(3 OF 7)

2.0V)

(1.8V/

DQB_62

VDDRH1

MVREFS_1

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11 MAB_12

MAB_15

MAB_14

MAB_13

DQMB_0* DQMB_1* DQMB_2* DQMB_3* DQMB_4* DQMB_5* DQMB_6* DQMB_7*

QSB_0

QSB_1

QSB_2

QSB_4

QSB_3

QSB_5

QSB_6

QSB_7

QSB_0* QSB_1* QSB_2* QSB_3* QSB_4* QSB_5* QSB_6* QSB_7*

CLKB0*

CLKB0

CSB0_0*

CKEB0

RASB0*

WEB0*

CASB0*

ODTB0

CLKB1 CLKB1*

CKEB1

RASB1*

WEB1*

CASB1*

ODTB1

DRAM_RST

DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12

DQB_15

DQB_14

DQB_13

DQB_16 DQB_17 DQB_18

DQB_20

DQB_19

DQB_22

DQB_21

DQB_23

DQB_25

DQB_24

DQB_27

DQB_26

DQB_28

DQB_30

DQB_29

DQB_33

DQB_31 DQB_32

DQB_35

DQB_34

DQB_37

DQB_36

DQB_38

DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46

DQB_48

DQB_47

DQB_52 DQB_53

DQB_56

DQB_55

DQB_54

DQB_58

DQB_57

DQB_60

DQB_59

DQB_61

DQB_63

MVREFD_1

VSSRH1

TEST_MCLK TEST_YCLK MEMTEST

DQB_39

CSB1_0*

DQB_51

DQB_50

DQB_49

CSB0_1*

CSB1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE B

(4 OF 7)

(1.8V/

2.0V)

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP1V8R2V0_S0_FB_GPU

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

(NONE)

NC

NC NC

NC

Page Notes

40.2

402

MF-LF

1/16W

1%

2

1

R8722

40.2

402

MF-LF

1/16W

1%

2

1

R8720

10% 16V X5R 402

0.1uF

2

1

C8723

1% 1/16W MF-LF 402

100

2

1

R8723

1%

MF-LF

402

100

1/16W

2

1

R8721

10%

X5R 402

0.1uF

16V

2

1

C8721

0.1uF

402

X5R

16V

10%

2

1

C8713

40.2

402

MF-LF

1/16W

1%

2

1

R8712

1/16W

1%

MF-LF 402

100

2

1

R8713

0.1uF

10% 16V X5R 402

2

1

C8711

40.2

402

MF-LF

1/16W

1%

2

1

R8710

1% 1/16W MF-LF

402

100

2

1

R8711

MF-LF

1/16W

1%

243

402

2

1

R8732

402

4.7K

5% 1/16W MF-LF

2

1

R8731

MF-LF

1/16W

5%

402

4.7K

2

1

R8730

4.7K

402

MF-LF

1/16W

5%

2

1

R8733

OMIT

BGA

M56P

B21

B31

A28

A27

B24

B28

J15

H15

D15

D16

C16

B16

D21

D20

G24

F23

K26

K25

K28

K29

K31

J31

D24

F29

C30

C31

B26

C26

F25

D27

E26

E24

D25

D28

C25

B25

E29

E27

B27

D29

F28

D26

J17

D14

B15

E21

G23

J26

J29

H31

M29

M27

F31

J14

H14

G14

G15

G30

G17

G18

H17

H18

D13

F14

E14

E15

F17

E17

G31

E18

D17

B13

C13

B14

C14

B17

C17

B18

B19

H30

D18

D19

F20

E20

E22

D23

D22

E23

J22

J23

L30

H22

H23

H24

H25

G26

F26

H26

H27

G28

J25

L31

L25

M25

L26

M26

G27

G29

H29

J27

L27

L28

M30

M31

C23

B23

C28

B29

C19

B20

E31

D31

C22

B30

B22

C29

U8400

OMIT

BGA

M56P

M2

B2

E1

F1

AA2

AA5

J2

E2

V9

V8

V4

U4

U3

U2

M4

N4

J7

K6

G10

H10

E10

D10

B10

B9

J4

D6

C3

B3

AA7

G2

G3

H6

F4

G5

J5

H4

E4

H3

H2

D5

F5

F2

D4

E6

G4

AA3

T9

W4

V2

M5

K7

G9

D9

B8

D12

F12

B6

W9

W8

W7

V7

C7

T7

R7

T8

R8

Y4

W6

W5

V5

T6

T5

B7

R5

T4

Y2

Y3

W2

W3

T2

T3

R2

P2

C8

R4

P4

N6

N5

L5

K4

L4

K5

L9

K9

C11

L8

K8

J8

H8

G7

G6

G8

F8

E7

H9

B11

H11

H12

G11

G12

F7

D7

D8

F9

F11

E11

C12

B12

K3

K2

E3

D2

P3

N2

B5

B4

L3

C2

L2

D3

U8400

1uF

CERM

10%

402

6.3V 2

1

C8716

1uF

6.3V CERM

402

10%

2

1

C8715

6.3V CERM

1uF

402

10%

2

1

C8726

10%

402

1uF

CERM

6.3V 2

1

C8725

0402

FERR-220-OHM

21

L8725

0402

FERR-220-OHM

21

L8715

SM

21

XW8725

SM

21

XW8715

70 84

051-7150 A.0.0

SYNC_DATE=(MASTER)

ATI M56 Frame Buffer I/F

SYNC_MASTER=(MASTER)

=PP1V8R2V0_S0_FB_GPU

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8R2V0_S0_GPU_VDDRH0

VOLTAGE=1.8V

=PP1V8R2V0_S0_FB_GPU

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8R2V0_S0_GPU_VDDRH1

FB_B_DQ<17> FB_B_DQ<18>

FB_A_CLK_P<0>

FB_A_CS_L<0>

FB_A_BA<2>

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GND_GPU_VSSRH1

=PP1V8R2V0_S0_FB_GPU=PP1V8R2V0_S0_FB_GPU

FB_A_CLK_N<0>

FB_A_BA<0>

FB_B_MA<11>

FB_B_MA<10>

FB_A_MA<4>

FB_A_MA<3>

FB_A_DQ<0>

FB_B_DQ<62>

GPU_MVREFS1

FB_B_MA<0> FB_B_MA<1> FB_B_MA<2> FB_B_MA<3> FB_B_MA<4> FB_B_MA<5> FB_B_MA<6> FB_B_MA<7> FB_B_MA<8> FB_B_MA<9>

TP_FB_B_MA12

FB_B_BA<1>

FB_B_BA<0>

FB_B_BA<2>

FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>

FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2>

FB_B_RDQS<4>

FB_B_RDQS<3>

FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7>

FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_WDQS<4> FB_B_WDQS<5> FB_B_WDQS<6> FB_B_WDQS<7>

FB_B_CLK_N<0>

FB_B_CLK_P<0>

FB_B_CS_L<0>

FB_B_CKE<0>

FB_B_RAS_L<0>

FB_B_WE_L<0>

FB_B_CAS_L<0>

TP_FB_B_ODT<0>

FB_B_CLK_P<1> FB_B_CLK_N<1>

FB_B_CKE<1>

FB_B_RAS_L<1>

FB_B_WE_L<1>

FB_B_CAS_L<1>

TP_FB_B_ODT<1>

FB_DRAM_RST

FB_B_DQ<0> FB_B_DQ<1> FB_B_DQ<2> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<5> FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<10> FB_B_DQ<11> FB_B_DQ<12>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<16>

FB_B_DQ<20>

FB_B_DQ<19>

FB_B_DQ<22>

FB_B_DQ<21>

FB_B_DQ<23>

FB_B_DQ<25>

FB_B_DQ<24>

FB_B_DQ<27>

FB_B_DQ<26>

FB_B_DQ<28>

FB_B_DQ<30>

FB_B_DQ<29>

FB_B_DQ<33>

FB_B_DQ<31> FB_B_DQ<32>

FB_B_DQ<35>

FB_B_DQ<34>

FB_B_DQ<37>

FB_B_DQ<36>

FB_B_DQ<38>

FB_B_DQ<40> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43> FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<46>

FB_B_DQ<48>

FB_B_DQ<47>

FB_B_DQ<52> FB_B_DQ<53>

FB_B_DQ<56>

FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<58>

FB_B_DQ<57>

FB_B_DQ<60>

FB_B_DQ<59>

FB_B_DQ<61>

FB_B_DQ<63>

GPU_MVREFD1

GPU_TEST_MCLK GPU_TEST_YCLK GPU_MEMTEST

FB_B_DQ<39>

FB_B_CS_L<1>

FB_B_DQ<51>

FB_B_DQ<50>

FB_B_DQ<49>

FB_A_DQ<58> FB_A_DQ<59>

FB_A_WE_L<1>

FB_A_DQ<61> FB_A_DQ<62>

GPU_MVREFD0

FB_A_MA<0> FB_A_MA<1> FB_A_MA<2>

FB_A_MA<5> FB_A_MA<6> FB_A_MA<7>

FB_A_MA<11> TP_FB_A_MA12

FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<4>

FB_A_CKE<0>

FB_A_RAS_L<0>

FB_A_CAS_L<0>

FB_A_WE_L<0>

TP_FB_A_ODT<0>

FB_A_CLK_N<1>

FB_A_CS_L<1>

FB_A_CKE<1>

FB_A_RAS_L<1>

FB_A_CAS_L<1>

TP_FB_A_ODT<1>

FB_A_DQ<1> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<4> FB_A_DQ<5> FB_A_DQ<6> FB_A_DQ<7> FB_A_DQ<8> FB_A_DQ<9> FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<12> FB_A_DQ<13> FB_A_DQ<14> FB_A_DQ<15> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<18> FB_A_DQ<19> FB_A_DQ<20> FB_A_DQ<21> FB_A_DQ<22> FB_A_DQ<23> FB_A_DQ<24> FB_A_DQ<25> FB_A_DQ<26> FB_A_DQ<27> FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<32> FB_A_DQ<33> FB_A_DQ<34> FB_A_DQ<35> FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43>

FB_A_DQ<45>

FB_A_DQ<44>

FB_A_DQ<46> FB_A_DQ<47> FB_A_DQ<48>

FB_A_DQ<50> FB_A_DQ<51>

FB_A_DQ<49>

FB_A_DQ<52> FB_A_DQ<53> FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56>

FB_A_DQ<63>

FB_A_CLK_P<1>

FB_A_MA<9>

FB_A_MA<8>

FB_A_MA<10>

FB_A_BA<1>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3> FB_A_RDQS<4> FB_A_RDQS<5>

FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_WDQS<0> FB_A_WDQS<1>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7>

FB_A_DQ<60>

FB_A_DQM_L<5>

FB_A_DQ<57>

GPU_MVREFS0

GND_GPU_VSSRH0

VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

70B8

70B5

70A8

73A8

70A5

70A8

70A5

73A5

69B8

72A8

69B8 69B8

72A8

73B8

72B8

73B8

73A8

72A8

72B8

72A8

65B6 65B6

73B6

72B8

72A5

65B6 65B6

72B8

72A5

73B5

72B5

72B6

73A3

73B5

71C1

73A5

73B6

73B3

73A8

73A5

73A8

73A5

73A8

73A5

73B8

73A8

73B5

73A5

72A5

73A6

73B6

73A6

73B6

73A6

73A3

73A6

73A3

73B3

73A3

73B3

73A3

73B5

73B3

72A3

72A5

72A3

72B5

71C1

72B6

72B3

72B8

72A8

72B5

72A5

72B6

72A6

72B3

72A3

72B5

72A5

72B3

72A8

72A5

72A8

72A5

72A3

72B3

72A3

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TESTIN[9] PWRCNTL

SS_IN

Thm Mon Int

Required for debug access

Also required: GPIO10 - GPIO13

TESTOUT[9] ROMIDCFG[0]

IPD

ENA_BL TESTIN[7]

ROMSO TESTWR Reserved

ROMSI ROMIDCFG[3]

ROMSCK TESTOUT[8]

TESTOUT[10] ROMIDCFG[1]

IPD

TESTIN[8]

IPD

TESTIN[1] TX_DEEMPH_EN

Serial ROM TestBus Misc Straps

IPD

TESTIN[4] DEBUG_ACCESS

TESTOUT[11] ROMIDCFG[2]

VDD_VCL TESTIN[2] Reserved

TESTIN[3] Reserved

TESTIN[5] Reserved

TESTIN[6] Reserved

TESTIN[0] TX_PWRS_ENb

Unused signals

Renamed signals

ROMCFGID[3..0]

0100 = 64MB 0110 = Reserved

0010 = 256MB

0000 = 128MB

Required for debug access

402

MF-LF

10K

5%

1/16W

2

1

R8800

GPU_DEEPMH_EN

10K

5% 1/16W MF-LF 402

2

1

R8801

MF-LF

5%

1/16W

10K

402

NO STUFF

2

1

R8802

5% 1/16W MF-LF 402

10K

NO STUFF

2

1

R8803

5%

10K

1/16W

402

MF-LF

NO STUFF

2

1

R8806

402

1/16W

5%

10K

MF-LF

NO STUFF

2

1

R8804

1/16W MF-LF

10K

402

5%

NO STUFF

2

1

R8808

10K

402

MF-LF

1/16W

5%

2

1

R8805

5%

GPU_MEM_256M

1/16W MF-LF

402

10K

2

1

R8812

1/16W MF-LF

402

10K

NO STUFF

5%

2

1

R8809

NO STUFF

5% 1/16W

10K

402

MF-LF

2

1

R8811

402

MF-LF

10K

1/16W

5%

GPU_MEM_64M

2

1

R8813

402

4.7K

MF-LF

1/16W

5%

2

1

R8891

MF-LF

1/16W

4.7K

5%

402

2

1

R8890

MF-LF

402

10K

5%

GPU_MEM_256M

1/16W

2

1

R8824

1/16W MF-LF

10K

402

5%

GPU_MEM_NOT_SAM

2

1

R8827

SYNC_DATE=07/25/2006

051-7150 A.0.0

8471

GPU Straps

SYNC_MASTER=M59_MG

GPU_DDC_B_CLK

MAKE_BASE=TRUE

GPU_MEMID

MAKE_BASE=TRUE

GPU_MEM_256M

GPU_GPIO_2

GPU_GPIO_9

GPU_GPIO_3

GPU_GPIO_11

GPU_GPIO_6

GPU_GPIO_8

GPU_GPIO_12

GPU_GPIO_4

GPU_GPIO_5

MAKE_BASE=TRUE

TP_ATI_DVPDATA<23..16>

ATI_DVPDATA<23..16>

MAKE_BASE=TRUE

GPU_CLK27M GPU_XTALIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_XTALOUT

GPU_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_ROMCS_L TP_ATI_ROMCS_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_MA12 TP_FB_A_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA12 TP_FB_B_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GENERICA

GPU_GENERICA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GENERICB

GPU_GENERICB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GENERICC

GPU_GENERICC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_VGA_G

GPU_VGA_G

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_VGA_R

GPU_VGA_R

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_VGA_B

GPU_VGA_B

MAKE_BASE=TRUE

TP_GPU_VGA_HSYNC

GPU_VGA_HSYNC

MAKE_BASE=TRUE

TP_GPU_VGA_VSYNC

GPU_VGA_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_TV_C

GPU_TV_C

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_TV_Y

GPU_TV_Y

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_TV_COMP

GPU_TV_COMP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAP<3>

LVDS_U_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAN<3>

LVDS_U_DATA_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAP<3>

LVDS_L_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ATI_DVPCLK

ATI_DVPCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAN<3>

LVDS_L_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPCNTL<2..0>

ATI_DVPCNTL<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPDATA<15..0>

ATI_DVPDATA<15..0>

MAKE_BASE=TRUE

GPU_VCORE_LOW

GPU_GPIO_27

GPU_GPIO_24

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_25

NC_GPU_GPIO_21

MAKE_BASE=TRUE NO_TEST=TRUE

GPU_GPIO_1

GPU_GPIO_0

MAKE_BASE=TRUE

GPU_BLON

TP_GPU_GPIO_10

MAKE_BASE=TRUE

GPU_CLK27MSS_IN

GPU_GPIO_32

GPU_GPIO_33

GPU_GPIO_34

GPU_GPIO_29

GPU_GPIO_30

GPU_GPIO_31

GPU_GPIO_28

GPU_GPIO_25

GPU_GPIO_26

GPU_GPIO_22

GPU_GPIO_23

GPU_GPIO_21

MAKE_BASE=TRUE

NC_GPU_GPIO_14

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_17

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_18

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_20

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_19

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_23

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_26

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_28

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_31

NO_TEST=TRUE

NC_GPU_GPIO_30

MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_29

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_34

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_33

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_32

MAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GPIO_22

GPU_GPIO_10

GPU_GPIO_7

GPU_GPIO_20

GPU_GPIO_19

GPU_GPIO_18

GPU_GPIO_17

=PP3V3_D3C_GPU

GPU_DDC_B_DATA

GPU_GPIO_16

GPU_GPIO_15

GPU_GPIO_14

GPU_GPIO_13

=PP3V3_D3C_GPU_GPIOS

74B3

34B4

74C3

34B4

75A3

74D3

74C3

74D3

74C3

74D3

74C3

74D3

74A3

34B2 74A5

74A5

74A3

70D5

70D1

74C3

75C3

75B3

75A3

74C3

75A3

74B3

68B4

74D5

74D3

79A4

34B2

74C5

74D5

74C3

74D3

74D5

74C3

65A3

75A3

74C3

65A3

http://mycomp.su/x/

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

IO

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IN IN

IO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

NOTE: U8900 DQ0-7 MUST connect to GPU

within byte-lane, but software must know

U8900.J12

U8900.J1

Connect to designated pin, then GND

NC NCNC

NC

U8900.J1

U8900.J12

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

GDDR3 vendor/device identification scheme.

how these bits are mapped for GPU to support

DQA0-7 or DQA8-15. Bits can be swapped

Connect to designated pin, then GND

2.37K

MF-LF

402

1%

1/16W

2

1

R8930

5.49K

MF-LF

1%

1/16W

402

2

1

R8931

0.1uF

X5R 402

10% 16V

2

1

C8903

X5R 402

10% 16V

0.1uF

2

1

C8902

0.1uF

X5R 402

10% 16V

2

1

C8904

0.1uF

X5R 402

10% 16V

2

1

C8901

0.1uF

X5R 402

10% 16V

2

1

C8922

0.1uF

402

10% 16V X5R

2

1

C8923

0.1uF

X5R 402

10% 16V

2

1

C8924

0.1uF

X5R 402

10% 16V

2

1

C8925

X5R 402

10% 16V

0.1uF

2

1

C8926

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U8900

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

CRITICAL

OMIT

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8900

MF-LF 402

5% 1/16W

100

2

1

R8949

5%

402

MF-LF

1/16W

1K

2

1

R8941

243

MF-LF

402

1%

1/16W

2

1

R8948

60.4

MF-LF 402

1% 1/16W

2

1

R8945

1/16W

1%

402

MF-LF

60.4

2

1

R8946

16V

10%

402

X5R

0.1uF

2

1

C8933

1/16W

1%

402

MF-LF

2.37K

2

1

R8932

5.49K

MF-LF

402

1%

1/16W

2

1

R8933

16V 402

X5R

0.1uF

10%

2

1

C8921

0402

FERR-220-OHM

21

L8910

0402

FERR-220-OHM

21

L8915

0.1uF

X5R 402

10% 16V

2

1

C8915

0.1uF

X5R 402

16V

10%

2

1

C8910

1/16W

402

MF-LF

121

1%

2

1

R8940

1/16W 402

MF-LF

121

1%

2

1

R8947

1%

121

MF-LF

402

1/16W

2

1

R8944

1/16W 402

121

1%

MF-LF

2

1

R8943

1%

121

MF-LF

402

1/16W

2

1

R8942

MF-LF 402

5% 1/16W

1K

2

1

R8991

1%

121

MF-LF

402

1/16W

2

1

R8990

1/16W

402

MF-LF

121

1%

2

1

R8992

16V 402

X5R

0.1uF

10%

2

1

C8971

16V

10%

402

X5R

0.1uF

2

1

C8972

1/16W

1%

402

MF-LF

243

2

1

R8998

1/16W

5%

402

MF-LF

100

2

1

R8999

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

CRITICAL

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U8950

1%

121

MF-LF 402

1/16W

2

1

R8993

1/16W

1%

402

MF-LF

60.4

2

1

R8995

1/16W

402

MF-LF

121

1%

2

1

R8994

1%

121

MF-LF 402

1/16W

2

1

R8997

60.4

MF-LF

402

1%

1/16W

2

1

R8996

1/16W

1%

402

MF-LF

5.49K

2

1

R8981

1/16W

1%

402

MF-LF

2.37K

2

1

R8980

1/16W

1%

402

MF-LF

5.49K

2

1

R8983

2.37K

MF-LF

402

1%

1/16W

2

1

R8982

16V

10%

402

X5R

0.1uF

2

1

C8973

16V

10%

402

X5R

0.1uF

2

1

C8981

16V

10%

402

X5R

0.1uF

2

1

C8974

16V

10%

402

X5R

0.1uF

2

1

C8975

0.1uF

X5R 402

10% 16V

2

1

C8983

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

CRITICAL

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8950

16V

10%

402

X5R

0.1uF

2

1

C8976

FERR-220-OHM

0402

21

L8965

FERR-220-OHM

0402

21

L8960

16V

10%

402

0.1uF

X5R

2

1

C8951

16V

10% X5R

0.1uF

402

2

1

C8952

16V

10%

402

X5R

0.1uF

2

1

C8960

16V

10%

402

X5R

0.1uF

2

1

C8953

16V

10%

402

X5R

0.1uF

2

1

C8965

16V

10%

402

X5R

0.1uF

2

1

C8954

6.3V CERM

805

20%

22UF

2

1

C8900

20%

6.3V

805

22UF

CERM

2

1

C8920

22UF

805

CERM

6.3V

20%

2

1

C8950

22UF

CERM

6.3V

20%

805

2

1

C8970

0.1uF

X5R 402

10% 16V

2

1

C8931

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

8472

GDDR3 Frame Buffer A

=PP1V8_S0_FB_VDDQ

FB_A0_VREF0

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A1_VREF0

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

FB_A_CKE<1>

FB_A_MA<10>

FB_A_MA<8>

FB_A_MA<11>

FB_A_MA<5>

FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<7>

FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6>

FB_A_CLK_P<1>

FB_A_MA<1>

FB_A_MA<0>

FB_A_MA<2>

FB_A_MA<4>

FB_A_MA<3>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<9>

FB_A_CLK_N<1> FB_A_CS_L<1> FB_A_WE_L<1> FB_A_CAS_L<1>

FB_A1_ZQ FB_A1_MF

FB_DRAM_RST

FB_A1_SEN

FB_A_RDQS<4> FB_A_RDQS<5>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<62> FB_A_DQ<56>

FB_A_DQ<57>

FB_A_DQ<61>

FB_A_DQ<59>

FB_A_DQ<54> FB_A_DQ<53> FB_A_DQ<60>

FB_A_DQ<55>

FB_A_DQ<52>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<49>

FB_A_DQ<48>

FB_A_DQ<45>

FB_A_DQ<47>

FB_A_DQ<44>

FB_A_DQ<39>

FB_A_DQ<35>

FB_A_DQ<32>

FB_A_MA<10>

FB_A_MA<8>

FB_A_DQM_L<0>

FB_A_DQM_L<2> FB_A_DQM_L<3>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<3>

FB_A_WDQS<0>

FB_A_MA<1>

FB_A_MA<9>

FB_A_CLK_N<0> FB_A_CS_L<0> FB_A_WE_L<0>

FB_A0_ZQ FB_A0_MF

FB_A_DQ<31>

FB_A_DQ<28>

FB_A_DQ<29> FB_A_DQ<30>

FB_A_DQ<27>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_DQ<20> FB_A_DQ<22> FB_A_DQ<24>

FB_A_DQ<21>

FB_A_DQ<23>

FB_A_DQ<17>

FB_A_DQ<18>

FB_A_DQ<16>

FB_A_DQ<19>

FB_A_DQ<13>

FB_A_DQ<12>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<7> FB_A_DQ<8>

FB_A_DQ<4>

FB_A_DQ<6>

FB_A_DQ<5>

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_DQ<0> FB_A_DQ<1>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<11>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A0_VREF1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8_S0_FB_VDDQ

FB_A_RAS_L<1>

FB_A_BA<2>FB_A_BA<2>

FB_A_DQM_L<1>

FB_A_CLK_P<0>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A0_SEN

FB_A_RDQS<0>

FB_DRAM_RST

FB_A_CAS_L<0>

FB_A_CKE<0>

FB_A_MA<4> FB_A_MA<5>

FB_A_DQ<34> FB_A_DQ<33>

FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38>

FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<46>

FB_A1_VREF1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A1_VDDA0

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A1_VDDA1

=PP1V8_S0_FB_VDD

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A0_VDDA1

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A0_VDDA0

=PP1V8_S0_FB_VDD

FB_A_MA<3>

FB_A_MA<2>

FB_A_MA<0>

FB_A_RAS_L<0>

FB_A_RDQS<6> FB_A_RDQS<7>

73D8

73A8

73D8

73A8

73D8

73D5

73A5

73D5

73A5

73D5

72D5

72B8

72A8

72B8

72A8

72B5

72A5

72B5

72D8

72A8 72A5

72A5

72B5

72D8 72D5

72B5

65B6

70B5

70D5

70C5

70D5

70C5

70B5

70D5

70B5

70A1

70C5

70B7

70C7

70D5

70C5

70D5

70C5

70D5

70B5

70C7

70D7

70C7

70D7

70C7

70D7

70D5

70C5

65B6

70B5

70D5 70D5

70C5

70B5

70C5

70A1

70B5

70D5

70C7

70B7

65B6 65B6

70D5

70B5

70C5

http://mycomp.su/x/

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

IO

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IN IN

IO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

Power aliases required by this page:

BOM options provided by this page:

Signal aliases required by this page: (NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

U9000.J12

U9000.J1

NC NC NC

NC

U9000.J1

U9000.J12

Connect to designated pin, then GNDConnect to designated pin, then GND

2.37K

MF-LF

402

1%

1/16W

2

1

R9030

5.49K

MF-LF

402

1%

1/16W

2

1

R9031

402

0.1uF

X5R

10% 16V

2

1

C9003

0.1uF

X5R 402

10% 16V

2

1

C9002

0.1uF

X5R 402

10% 16V

2

1

C9004

0.1uF

X5R

10% 16V

402

2

1

C9001

0.1uF

X5R 402

10% 16V

2

1

C9022

0.1uF

X5R 402

10% 16V

2

1

C9023

0.1uF

X5R 402

10% 16V

2

1

C9024

0.1uF

X5R 402

10% 16V

2

1

C9025

16V 402

0.1uF

X5R

10%

2

1

C9026

OMIT

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U9000

FBGA

OMIT

CRITICAL

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U9000

100

MF-LF 402

5% 1/16W

2

1

R9049

1K

1/16W

5%

402

MF-LF

2

1

R9041

243

MF-LF

402

1%

1/16W

2

1

R9048

60.4

MF-LF 402

1% 1/16W

2

1

R9045

1/16W

1%

402

MF-LF

60.4

2

1

R9046

16V

10%

402

X5R

0.1uF

2

1

C9033

2.37K

1/16W

1%

402

MF-LF

2

1

R9032

5.49K

MF-LF

402

1%

1/16W

2

1

R9033

402

0.1uF

X5R

10% 16V

2

1

C9021

0402

FERR-220-OHM

21

L9010

0402

FERR-220-OHM

21

L9015

0.1uF

X5R 402

10% 16V

2

1

C9015

0.1uF

X5R 402

10% 16V

2

1

C9010

1/16W

402

MF-LF

121

1%

2

1

R9040

1/16W 402

MF-LF

121

1%

2

1

R9047

1%

121

MF-LF

402

1/16W

2

1

R9044

1/16W 402

MF-LF

121

1%

2

1

R9043

1%

121

MF-LF

402

1/16W

2

1

R9042

1K

MF-LF 402

5% 1/16W

2

1

R9091

1%

121

MF-LF

402

1/16W

2

1

R9090

1/16W

402

1%

121

MF-LF

2

1

R9092

0.1uF

16V

10%

402

X5R

2

1

C9071

0.1uF

16V

10%

402

X5R

2

1

C9072

1%

243

MF-LF

402

1/16W

2

1

R9098

100

5% MF-LF

402

1/16W

2

1

R9099

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U9050

121

1/16W 402

MF-LF

1%

2

1

R9093

60.4

1/16W

1%

402

MF-LF

2

1

R9095

402

1% 1/16W MF-LF

121

2

1

R9094

121

MF-LF

1/16W

1%

402

2

1

R9097

60.4

MF-LF

402

1%

1/16W

2

1

R9096

1/16W

1%

5.49K

MF-LF

402

2

1

R9081

1/16W

1%

2.37K

MF-LF

402

2

1

R9080

1%

1/16W

402

5.49K

MF-LF

2

1

R9083

2.37K

1%

1/16W

402

MF-LF

2

1

R9082

0.1uF

16V X5R 402

10%

2

1

C9073

16V

10%

402

X5R

0.1uF

2

1

C9081

0.1uF

X5R 402

10% 16V

2

1

C9074

0.1uF

16V

10%

402

X5R

2

1

C9075

0.1uF

X5R

16V

10%

402

2

1

C9083

16MX32-GDDR3-500MHZ

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U9050

0.1uF

16V

10%

402

X5R

2

1

C9076

FERR-220-OHM

0402

21

L9065

FERR-220-OHM

0402

21

L9060

16V

10%

402

X5R

0.1uF

2

1

C9051

16V

10%

402

X5R

0.1uF

2

1

C9052

0.1uF

X5R 402

10% 16V

2

1

C9060

0.1uF

X5R 402

10% 16V

2

1

C9053

0.1uF

X5R 402

10% 16V

2

1

C9065

16V

10%

402

X5R

0.1uF

2

1

C9054

20%

6.3V CERM

805

22UF

2

1

C9000

20%

6.3V CERM

805

22UF

2

1

C9020

20%

6.3V CERM

805

22UF

2

1

C9050

22UF

20%

6.3V CERM

805

2

1

C9070

X5R

0.1uF

402

10% 16V

2

1

C9031

051-7150

SYNC_MASTER=(MASTER)

GDDR3 Frame Buffer B

SYNC_DATE=(MASTER)

A.0.0

8473

FB_B_MA<4>

FB_B_CS_L<1>

FB_B_MA<9>

FB_B_DQ<2>

FB_B_DQ<7>

FB_B_DQ<24>

FB_B_DQ<13>

FB_B_DQ<14>

FB_B_DQ<12>

FB_B_DQ<15>

FB_B_DQM_L<3>

FB_B_WDQS<1>

FB_B_RDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_DRAM_RST

FB_B0_ZQ

FB_B0_SEN

FB_B_DQ<23>

FB_B_CLK_N<1>

FB_B_CAS_L<1>

FB_B_WE_L<1>

FB_B_RAS_L<1>

FB_B1_ZQ

FB_B_DQ<61>

FB_B_DQ<46>

FB_B_CLK_P<1>

FB_B_MA<1> FB_B_MA<2> FB_B_MA<3>

FB_B_CKE<1>

FB_B_DQ<58>

FB_B_DQ<59>

=PP1V8_S0_FB_VDDQ

FB_B_MA<5>

FB_B_MA<7>

FB_B_BA<0> FB_B_BA<1>

FB_B_CKE<0>

FB_B_DQ<9> FB_B_DQ<11>

FB_B_DQ<8>

FB_B_DQ<18>

FB_B_DQ<10>

FB_B_DQ<17> FB_B_DQ<19> FB_B_DQ<16> FB_B_DQ<20> FB_B_DQ<22>

FB_B_DQ<21> FB_B_DQ<29> FB_B_DQ<30> FB_B_DQ<28> FB_B_DQ<31> FB_B_DQ<27>

FB_B_DQ<1>

FB_B_DQ<25>

FB_B_DQ<26>

FB_B_DQ<6> FB_B_DQ<0> FB_B_DQ<5> FB_B_DQ<3>

FB_B_DQ<4>

FB_B_RDQS<1>

FB_B0_MF

FB_B_CAS_L<0>

FB_B_WE_L<0>

FB_B_CS_L<0>

FB_B_CLK_N<0>

FB_B_MA<9>

FB_B_MA<6> FB_B_MA<7>

FB_B_MA<0> FB_B_MA<1>

FB_B_WDQS<3>

FB_B_WDQS<2>

FB_B_WDQS<0>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_MA<5>

FB_B_MA<11>

FB_B_MA<8>

FB_B_MA<10>

FB_B_DQ<53>

FB_B_DQ<54>

FB_B_DQ<52> FB_B_DQ<55>

FB_B_DQ<48> FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<44>

FB_B_DQ<51>

FB_B_DQ<47> FB_B_DQ<45>

FB_B_DQ<43> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<40> FB_B_DQ<37> FB_B_DQ<32> FB_B_DQ<39> FB_B_DQ<34> FB_B_DQ<36> FB_B_DQ<35>

FB_B_DQ<63>

FB_B_DQ<33>

FB_B_DQ<62> FB_B_DQ<60> FB_B_DQ<56>

FB_B_DQ<57>

FB_B_RDQS<7>

FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B1_SEN

FB_DRAM_RST

FB_B1_MF

FB_B_MA<6>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_BA<0> FB_B_BA<1>

FB_B_DQM_L<7>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_MA<11>

FB_B_MA<8>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B1_VREF1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B1_VREF0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF0

FB_B_RAS_L<0>

FB_B_BA<2> FB_B_BA<2>

FB_B_RDQS<5>

FB_B_MA<10>

FB_B_DQ<38>

=PP1V8_S0_FB_VDDQ

FB_B_MA<4>

FB_B_MA<3>

FB_B_MA<2>

FB_B_CLK_P<0>

PP1V8_S0_FB_B1_VDDA1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

PP1V8_S0_FB_B1_VDDA0

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

=PP1V8_S0_FB_VDD

PP1V8_S0_FB_B0_VDDA0

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

PP1V8_S0_FB_B0_VDDA1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V

=PP1V8_S0_FB_VDD

FB_B_MA<0>

73A5

73D5

73A8

73D8

73D5

72A8

72D8

72A8

72D8

73B8

72A5

73B8

72D5

73B8

73A5

73B5

72A5

73B8

73A8

73B8

73A5 73A8

73B8

72D5

73B5

72D5 72D5

73B8

70D1

70B1

70D1

70D3

70C3

70D3

70C1

70A1

70C3

70B1

70B3

70B1

70D1

70B1

70B3

65B6

70D1

70B1

70D3

70C3

70D3

70C3

70D3

70C3

70D3

70C3

70D3

70C1

70B1

70D1

70C1

70D1

70C1

70D1

70B3

70C3

70B3

70C3

70B3

70C1

70A1

70D1

70C1

70D1

70C1

70D1

70B1

70D1 70D1

70C1

70D1

70C3

65B6

70D1

70B1

65B6 65B6

70D1

http://mycomp.su/x/

GPIO_0 GPIO_1

TESTEN

GPIO_2

GPIO_27

PLLTEST

XTALOUT

XTALIN

MPVSS

MPVDD

PVSS

PVDD

GPIO_16 GPIO_17

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

GPIO_9

GPIO_8

GPIO_7_BLON

GPIO_6

GPIO_5

GPIO_4

GPIO_3

VREFG

GPIO_33

GPIO_31 GPIO_32

GPIO_25 GPIO_26

GPIO_24

GPIO_21

GPIO_20

GPIO_19

DMINUS

DPLUS

ROMCS*

GPIO_34

GPIO_29 GPIO_30

NC_DVOVMODE_0 NC_DVOVMODE_1

DVPCLK

DVPCNTL_0 DVPCNTL_1 DVPCNTL_2

DVPDATA_2

DVPDATA_1

DVPDATA_0

DVPDATA_4

DVPDATA_3

DVPDATA_5

DVPDATA_7

DVPDATA_6

DVPDATA_9

DVPDATA_8

DVPDATA_10 DVPDATA_11

DVPDATA_13

DVPDATA_12

DVPDATA_15

DVPDATA_14

DVPDATA_16

DVPDATA_18

DVPDATA_17

DVPDATA_19

DVPDATA_21

DVPDATA_20

DVPDATA_23

DVPDATA_22

GENERICA GENERICB GENERICC GENERICD

DIGON

VARY_BL

NC0

GPIO_18

VDDPLL

GPIO_28

GPIO_22 GPIO_23

GENERAL PURPOSE I/O

(1.2V)

(2.5V)

ROM

TEST

PLL & XTAL

VIP HOST / EXTERNAL TMDS

PANEL CONTROL

VDDR3

(3.3V)

(2.5V)

VDD25

VDDR5

(1.8V/3.3V)

VDDR4

DIODE

THERMAL

(2.5V)

(6 OF 7)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

20mA

70mA total for VDD25

Power aliases required by this page:

- =I2C_GPU_TMDS_SCL - I2C clock line for

Page Notes

(PP1V0R1V2_S0_GPU_MPVDD)

NC

Signal aliases required by this page:

(GND_GPU_PVSS)

(GND_GPU_MPVSS)

(PP2V5_S0_GPU_PVDD_F)

- =I2C_GPU_TMDS_SDA - I2C data line for

- =PP3V3_GPU_GPIOS

- =PP1V8_GPU_LVDS_PLL

external TMDS transmitters

(NONE)

- =PP2V5_PVDD

external TMDS transmitters

20mA

Typically <50mA

BOM options provided by this page:

100mA

402

0.1uF

X5R

16V

10%

2

1

C9112

10%

402

1uF

CERM

6.3V

2

1

C9111

10%

CERM

6.3V

1uF

402

2

1

C9116

402

10%

1uF

CERM

6.3V

2

1

C9117

16V

0.1uF

402

X5R

10%

2

1

C9137

1uF

10%

402

CERM

6.3V

2

1

C9136

0402

FERR-220-OHM

21

L9135

10%

402

1uF

CERM

6.3V

2

1

C9141

0402

FERR-220-OHM

21

L9140

402

10%

0.1uF

16V X5R

2

1

C9142

1K

402

MF-LF

1/16W

5%

2

1

R9195

SM

21

XW9140

402

MF-LF

1/16W

499

1%

2

1

R9191

1/16W MF-LF 402

499

1%

2

1

R9190

SM

21

XW9135

20%

6.3V CERM

805

22UF

2

1

C9100

22UF

805

CERM

6.3V

20%

2

1

C9110

20%

6.3V CERM

805

22UF

2

1

C9115

22UF

805

CERM

6.3V

20%

2

1

C9120

20%

6.3V CERM

805

22UF

2

1

C9125

CERM

6.3V

1uF

402

10%

2

1

C9132

20%

6.3V CERM

805

22UF

2

1

C9130

22UF

20%

6.3V CERM

805

2

1

C9135

20%

6.3V CERM

805

22UF

2

1

C9140

0.1uF

402

X5R

16V

10%

2

1

C9191

M56P

BGA

OMIT

AM26

AL26

AC8

AE5

AE4

AE3

AE2

AM5

AL5

AK5

AJ5

AD20

AD19

AD18

AC20

AC19

AB10

AB9

AA9

AC15

AC18

AC16

AC13

AA10

L10

K22

AD12

AG22

AC7

AH14

AJ14

AG14

AL4

AK4

AB6

A5

A6

AC5

AC6

AB2

AC3

AC2

AC1

AG8

AH7

AG9

AH8

AJ8

AD3

AH9

AG10

AF10

AH6

AF8

AF7

AE9

AE10

AG7

AF9

AD1

AF13

AE13

AB7

AA8

AB8

AD5

AB5

AB4

AB3

AC4

AD2

AD4

AD23

AE23

AF23

AK22

AL2

AK3

AK1

AK2

AJ1

AJ2

AH3

AG6

AE7

AF6

AH5

AH2

AG5

AJ4

AH4

AJ3

AG4

AF5

AF4

AE6

AM3

AL3

AG3

AG2

AF3

AF1

AF2

AG1

AG12

AH12

AE11

U8400

10% 16V X5R 402

0.1uF

2

1

C9127

6.3V CERM

1uF

402

10%

2

1

C9126

402

0.1uF

X5R

16V

10%

2

1

C9122

402

10%

1uF

CERM

6.3V

2

1

C9121

0402

FERR-220-OHM

21

L9120

0402

FERR-220-OHM

21

L9125

0402

200-OHM-EMI

21

L9130

1uF

6.3V CERM 402

10%

2

1

C9131

6.3V CERM

1uF

402

10%

2

1

C9101

CERM 402

10%

1uF

6.3V

2

1

C9102

10%

402

1uF

CERM

6.3V

2

1

C9103

051-7150 A.0.0

8474

ATI M56 GPIO/DVO/Misc

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

GND_GPU_MPVSS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

GND_GPU_PVSS

=PP3V3_S0_GPU_VDDR3

=PP2V5_S0_GPU_VDD25

=PP2V5_S0_GPU_VDDC_CT

GPU_GPIO_30 GPU_GPIO_31

GPU_GPIO_8

ATI_DVPDATA<0>

ATI_DVPDATA<19>

ATI_DVPDATA<2>

ATI_TDIODE_P

GPU_GPIO_0 GPU_GPIO_1 GPU_GPIO_2

GPU_GPIO_27

GPU_XTALOUT

GPU_XTALIN

GPU_GPIO_16 GPU_GPIO_17

GPU_GPIO_15

GPU_GPIO_14

GPU_GPIO_13

GPU_GPIO_12

GPU_GPIO_11

GPU_GPIO_10

GPU_GPIO_9

GPU_GPIO_7

GPU_GPIO_6

GPU_GPIO_5

GPU_GPIO_3

GPU_GPIO_33

GPU_GPIO_32

GPU_GPIO_25 GPU_GPIO_26

GPU_GPIO_21

GPU_GPIO_20

GPU_GPIO_19

ATI_TDIODE_N

TP_ATI_ROMCS_L

GPU_GPIO_34

GPU_GPIO_29

ATI_DVPCLK

ATI_DVPCNTL<0> ATI_DVPCNTL<1> ATI_DVPCNTL<2>

ATI_DVPDATA<1>

ATI_DVPDATA<4>

ATI_DVPDATA<3>

ATI_DVPDATA<5>

ATI_DVPDATA<7>

ATI_DVPDATA<6>

ATI_DVPDATA<9>

ATI_DVPDATA<8>

ATI_DVPDATA<10> ATI_DVPDATA<11>

ATI_DVPDATA<13>

ATI_DVPDATA<12>

ATI_DVPDATA<15>

ATI_DVPDATA<14>

ATI_DVPDATA<16>

ATI_DVPDATA<18>

ATI_DVPDATA<17>

ATI_DVPDATA<21>

ATI_DVPDATA<20>

ATI_DVPDATA<23>

ATI_DVPDATA<22>

GPU_GENERICA GPU_GENERICB GPU_GENERICC GPU_GENERICD

GPU_DIGON GPU_VARY_BL

GPU_GPIO_18

GPU_GPIO_28

GPU_GPIO_22 GPU_GPIO_23

ATI_TESTEN

=PP3V3_S0_GPU

ATI_VREFG

GPU_GPIO_24

GPU_GPIO_4

PP1V8R3V3_S0_GPU_VDDR4_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8R3V3_S0_GPU_VDDR4

PP1V8R3V3_S0_GPU_VDDR5_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V8R3V3_S0_GPU_VDDR5

PP1V2_S0_GPU_VDDPLL

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PP1V2_S0_GPU_VDDPLL

PP2V5_S0_GPU_PVDD_F

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_GPU_PVDD

PPVCORE_S0_GPU_MPVDD

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PPVCORE_S0_GPU

69D8 65A6

79B6

68C4

53C7

65A3

65A6

71B8

71C8

71B1

52B6

71D8

71C8

71B8

71C1

71C8

71B8

52B6

71C1

71B8

71B1

71C1

68A7

79A4

71B8

65A3

71B8 71C8

65A3

65C6

65A6

53A5

http://mycomp.su/x/

DDC3DATA

DDC3CLK

DDC2DATA

DDC2CLK

DDC1DATA

DDC1CLK

TXOUT_L3N

TXOUT_L3P

TXOUT_L2N

TXOUT_L2P

TXOUT_L1N

TXOUT_L1P

TXOUT_L0N

TXOUT_L0P

TXCLK_LP TXCLK_LN

TXOUT_U3N

TXOUT_U2N TXOUT_U3P

TXOUT_U2P

TXOUT_U1N

TXOUT_U1P

TXOUT_U0N

TXOUT_U0P

TXCLK_UN

TXCLK_UP

COMP

C

Y

V2SYNC

H2SYNC

B2

G2

R2

VSYNC

HSYNC

B

G

R

TX2M

TX2P

TX1M

TX0M TX1P

TX0P

TXCM

HPD1

LPVSS

LPVDD

R2SET

VDD2DI VSS2DI

A2VSSQ

NC_A2VDDQ

VSS1DI

RSET

AVSSQ

VDD1DI

TXCP

TPVSS

TPVDD

TX3P TX3M TX4P TX4M TX5P TX5M

A2VSS

A2VDD

(2.5V)

AVSS

(2.5V)

AVDD

TXVSSR

IDENTIFICATION

(5 OF 7)

LVDDR

LVSSR

DAC (CRT)

DAC2 (TV/CRT2)

LVDS

MONITOR

TXVDDR

(2.5V)

INTEGRATED TMDS

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IO

IO IO

IO

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

20mA peak

130mA peak

- =PP1V8R2V5_S0_GPU_LVDDR

- =PP2V5_S0_GPU

(NONE)

BOM options provided by this page:

NC

150mA peak

65mA peak

200mA peak

Comp B Pb

C R Pr

Y G Y

Composite/S-Video VGA Component

20mA peak

Signal aliases required by this page:

Power aliases required by this page:

Sum of peak currents on this page: 605mA

Page Notes

OMIT

M56P

BGA

AJ15

AJ22

AJ17

AL23

AJ16

AM23

AG15

AM7

AL7

AK8

AK7

AJ7

AM6

AL6

AK6

AJ6

AH21

AG21

AG20

AH20

AK20 AJ20

AG18 AH18

AJ18 AK18

AM21

AL21

AM20

AL20

AL19

AK19

AM9

AL9

AJ21

AK21

AM18

AL18

AJ12 AK12

AJ11

AK11

AJ9

AK9

AM12 AL12

AM11

AL11

AL10

AK10

AL8

AM8

AL22

AK14

AK15

AK24

AL14

AK17

AJ19

AH19

AH17

AG19

AG17

AF22

AF21

AF18

AF17

AF20

AF19

AE22

AE21

AE20

AD22

AD21

AC22

AC21

AE18

AE19

AJ23

AF11

AF15

AM15

AM24

AE12

AF12

AH13

AG13

AH22

AH23

AH15

AJ13

AL15

AL24

AK23

AK25

AJ24

AM25

AL25

AK13

AM17

AL17

AM16

AL16

U8400

499

MF-LF 402

1% 1/16W

2

1

R9350

16V

10%

402

X5R

0.1uF

2

1

C9346

16V

10%

402

X5R

0.1uF

2

1

C9342

10%

1uF

CERM 402

6.3V

2

1

C9341

FERR-220-OHM

0402

21

L9300

402

6.3V

10% CERM

1uF

2

1

C9301

6.3V

10%

402

CERM

1uF

2

1

C9306

FERR-220-OHM

0402

21

L9305

16V

0.1uF

X5R 402

10%

2

1

C9307

FERR-220-OHM

0402

21

L9330

1uF

CERM 402

10%

6.3V

2

1

C9331

16V

0.1uF

10%

402

X5R

2

1

C9322

6.3V CERM

10%

402

1uF

2

1

C9321

FERR-220-OHM

0402

21

L9320

16V

0.1uF

X5R 402

10%

2

1

C9312

402

1uF

CERM

10%

6.3V

2

1

C9311

FERR-220-OHM

0402

21

L9310

402

0.1uF

X5R

10% 16V

2

1

C9317

1uF

10%

6.3V CERM 402

2

1

C9316

0.1uF

X5R 402

10% 16V

2

1

C9327

1uF

10% CERM

402

6.3V

2

1

C9326

FERR-220-OHM

0402

21

L9325

FERR-220-OHM

0402

21

L9315

FERR-220-OHM

0402

21

L9345

16V

10%

402

X5R

0.1uF

2

1

C9347

22UF

805

CERM

6.3V

20%

2

1

C9340

22UF

805

CERM

6.3V

20%

2

1

C9345

1uF

CERM 402

10%

6.3V

2

1

C9332

6.3V

402

10% CERM

1uF

2

1

C9302

20%

22UF

805

CERM

6.3V 2

1

C9300

20%

6.3V

CERM

805

22UF

2

1

C9305

22UF

805

CERM

6.3V

20%

2

1

C9310

20%

6.3V CERM

805

22UF

2

1

C9315

6.3V

805

22UF

CERM

20%

2

1

C9320

805

22UF

20%

6.3V CERM

2

1

C9325

CERM

22UF

805

6.3V

20%

2

1

C9330

1/16W

1%

402

MF-LF

715

2

1

R9351

ATI M56 Video Interfaces

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

8475

GPU_TV_C

GPU_TV_COMP

GPU_TV_Y

GPU_VGA_R GPU_VGA_G GPU_VGA_B

GPU_R2 GPU_G2 GPU_B2

GPU_V2SYNC

ATI_R2SET

ATI_RSET

GPU_HPD

LVDS_U_DATA_N<3>

LVDS_U_DATA_P<3>

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<1>

LVDS_L_CLK_P

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<0>

GPU_VGA_VSYNC

GPU_VGA_HSYNC

LVDS_U_CLK_P LVDS_U_CLK_N

LVDS_U_DATA_P<0> LVDS_U_DATA_N<0>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

TMDS_DATA_N<5>

TMDS_DATA_N<4>

TMDS_DATA_N<3>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<3> LVDS_L_DATA_N<3>

GPU_DDC_A_CLK

GPU_DDC_B_DATA

GPU_DDC_B_CLK

GPU_DDC_A_DATA

ATI_RSET ATI_R2SET

LVDS_U_DATA_N<2>

LVDS_U_DATA_P<2>

LVDS_L_CLK_N

GPU_DDC_C_CLK GPU_DDC_C_DATA

GPU_H2SYNC

TMDS_CLK_P

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_TPVDD

VOLTAGE=2.5V

PP2V5_S0_GPU_TXVDDR

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

PP2V5_S0_GPU_AVDD

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_VDD1DI

PP2V5_S0_GPU_A2VDD

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_VDD2DI

VOLTAGE=2.5V

PP2V5_S0_GPU_LPVDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PP2V5_S0_GPU

PP2V5_S0_GPU_LVDDR

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm

84B4

84A4

77C3

79C3

79B3

79C3

77B8

77D8

71B1

71C1

76D7

77D5

75A8

77A1

71B1

76D7

71C1

76D7

71B1

77B1

71A2

77B1

75B5

76D7

79A7

77C5

76C7

65A6

http://mycomp.su/x/

D

S

G

D

S

N-CHN

S

D

G

P-CHN

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LCD (LVDS) INTERFACE

INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL

518S0289

NC

NET_TYPE

INVERTER INTERFACE

PHYSICAL

SPACING

no-panel case (development).

100K pull-ups are for

Panel has 2K pull-ups

ELECTRICAL_CONSTRAINT_SET

518S0369

NC

1/16W

5%

402

MF-LF

100K

2

1

R9450

50V

20%

402

CERM

0.001uF

2

1

C9454

0.001uF

CERM 402

20% 50V

2

1

C9452

0.001uF

402

20% 50V CERM

2

1

C9450

6.3V

20%

603

X5R

10UF

2

1

C9451

400-OHM-EMI

SM-1

21

L9454

0.1uF

CERM

402

20% 10V

2

1

C9453

400-OHM-EMI

SM-1

21

L9452

402

50V

20%

CERM

0.001uF

2

1

C9420

50V

20%

CERM

0.001uF

402

2

1

C9410

50V 402

CERM

20%

0.001uF

2 1

C9421

CRITICAL

F-RT-SM

MSC-RB30-5-FA

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

J9400

402

50V

20%

CERM

0.001uF

2

1

C9401

FERR-250-OHM

SM

L9400

402

10%

0.0022uF

CERM

50V

21

C9400

5%

1/16W

402

MF-LF

100K

R9401

100K

1/16W

5%

402

MF-LF

2

1

R9400

SI3443DV

TSOP-LF

4

3 6

5 2 1

Q9400

SOT23-LF

2N7002

2

1

3

Q9401

402

MF-LF

1/16W

5%

100K

2

1

R9489

1/16W MF-LF

402

5%

100K

2

1

R9494

SC70

MC74VHC1G08

5

4

1

2

3

U9453

FDG6332C_NL

SC70-6

1

2

6

Q9450

FDG6332C_NL

SC70-6

4

5

3

Q9450

402

100K

5% 1/16W MF-LF

2

1

R9411

402

MF-LF

1/16W

5%

100K

2

1

R9410

0603

FERR-220-OHM-2A

CRITICAL

2

1

L9455

CRITICAL

FERR-220-OHM-2A

0603

21

L9450

M-RT-SM

SM04B-ACH

CRITICAL

4

3

2

1

6

5

J9450

Internal Display Connectors

051-7150 A.0.0

8476

SYNC_MASTER=M59_MG

SYNC_DATE=07/25/2006

=INVERTER_PWM_PLT_RST_L

=PP3V3_S0_INVERTER

INVERTER_PWM_UNBUF

INVERTER_PWM_F

GND_INVERTER

INVERTER_PWM

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_INVERTER_SW

PPBUS_S0_INVERTER

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V

=PPBUS_S0_INVERTER

=GND_CHASSIS_INVERTER

VGAVGA

GPU_R2

VGAVGA

GPU_B2

LVDS LVDS

LVDS_U_CLK_P

TMDSTMDS

TMDS_CLK_P

LVDSLVDS

LVDS_L_DATA_CONN_N<2..0>

TMDSTMDS

TMDS_DATA_N<5..3>

TMDSTMDS

TMDS_DATA_N<2..0>

LVDSLVDS

LVDS_U_DATA_N<2..0>

LVDSLVDS

LVDS_U_DATA_P<2..0>

LVDS LVDS

LVDS_U_CLK_N

=PP3V3_S0_DDC_LCD

LVDS_CONN_DDC_CLK LVDS_CONN_DDC_DATA

VGAVGA

GPU_G2

LVDS LVDS

LVDS_L_DATA_N<2..0>

LVDSLVDS

LVDS_L_DATA_P<2..0>

LVDSLVDS

LVDS_L_CLK_N

LVDS LVDS

LVDS_L_CLK_P

TMDSTMDS

TMDS_DATA_P<5..3>

TMDSTMDS

TMDS_DATA_P<2..0>

TMDSTMDS

TMDS_CLK_N

LVDS LVDS

LVDS_L_DATA_CONN_P<2..0>

LVDS LVDS

LVDS_L_CLK_CONN_N

LVDSLVDS

LVDS_L_CLK_CONN_P

LVDS LVDS

LVDS_U_DATA_CONN_N<2..0>

LVDS LVDS

LVDS_U_DATA_CONN_P<2..0>

LVDSLVDS

LVDS_U_CLK_CONN_N

LVDS_U_CLK_CONN_P

LVDS LVDS

LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N

LVDS_U_DATA_CONN_P<2>

LVDS_U_DATA_CONN_N<2>

LVDS_U_DATA_CONN_P<1>

LVDS_U_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<2> LVDS_L_DATA_CONN_P<2>

LVDS_L_CLK_CONN_P

LVDS_L_CLK_CONN_N

LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_N<0> LVDS_L_DATA_CONN_P<0>

=PP3V3_S0_LCD

LCD_PWREN_L

LVDS_PANEL_EN

LCD_PWREN_L_RC

PP3V3_LCD_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

=GND_CHASSIS_LCD1

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_LCD_CONN

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD3

FP_PWR_EN_L

INVERTER_BKLTON

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

PP5V_INVERTER_SW_F

=PP5V_S0_INVERTER

=GND_CHASSIS_LCD2

79D1

84A4

79C1

79D1

79C1

84B4

79C1

77B8

77D8

79C3

77B8

77D8

84B4

76C2

79C1

76C2

79C1

79D1

79C1

79D1

79C1

79D1

79C1

77C3

79C3

77B8

76C2

77A8

77C8

79C3

79B3

79C3

77C3

79C3

77A8

77C8

6B1

76C2

76B2

76D7

6C4

65B3

79A2

5A4

65C1

6A6

75B3

75C3

6A1

75C3

75B3

65B3

79A5

75B3

75A3

75C3

6A1

6B1

6A1

6B1

6A1

6B1

65C3

79A2

79B6

6A6

79A2

65A1

6A6

http://mycomp.su/x/

G

SD

G

SD

G

SD

LCFILTER

SYM_VER-1

G

SD

SYM_VER-1

G

S D

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place termination components close to GPU, common mode chokes near connector.

(55mA requirement per DVI spec)

PLACE NEAR C5A & C5B

(PP5V_S0_DDC)

(DAC2 C)

Isolation required for DVI power switch

514-0278

PLACE NEAR 3, 11 & 19

3V LEVEL SHIFTERS

DVI DDC CURRENT LIMIT

DVI INTERFACE

VGA SYNC BUFFERS

ANALOG FILTERING

PLACE CLOSE TO CONNECTOR

(DAC2 Y)

(DAC2 Comp)

PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

TMDS Filtering

1/16W

10K

402

MF-LF

5%

2

1

R9721

10K

MF-LF 402

5% 1/16W

2

1

R9720

2N7002DW-X-F

SOT-363

1

2

6

Q9711

2N7002DW-X-F

SOT-363

4

5

3

Q9711

1/16W MF-LF

270K

402

5%

2

1

R9722

5%

100pF

50V CERM 402

2

1

C9713

MF-LF

4.7K

1/16W

5%

402

2

1

R9712

5%

4.7K

MF-LF

402

1/16W

2

1

R9710

100pF

50V

5%

402

CERM

2

1

C9711

20% 50V

603

CERM

0.01uF

2

1

C9710

SM-1

400-OHM-EMI

21

L9710

2N7002DW-X-F

SOT-363

4

5

3

Q9714

SM-LF

0.5AMP-13.2V

CRITICAL

21

F9710

SOD-123

B0530WXF

21

D9710

402

50V

5% CERM

100pF

2

1

C9714

100

1/16W

5%

402

MF-LF

21

R9711

402

100

1/16W

5%

MF-LF

21

R9713

MF-LF

402

5%

1/16W

100

21

R9714

0

1/16W MF-LF

5%

402

2 1

R9730

402

1/16W

5%

MF-LF

0

2 1

R9731

50V

0.25%

402

CERM

3.3pF

2

1

C9741

75

MF-LF

402

1%

1/16W

2

1

R9742

75

MF-LF

402

1%

1/16W

2

1

R9740

75

MF-LF

402

1%

1/16W

2

1

R9741

50V

0.25%

402

CERM

3.3pF

2

1

C9742

50V

0.25%

402

CERM

3.3pF

2

1

C9740

SM-220MHZ-LF

CRITICAL

43

21

FL9740

CRITICAL

SM-220MHZ-LF

43

21

FL9741

SM-220MHZ-LF

CRITICAL

43

21

FL9742

402

MF-LF

1/16W

5%

33

21

R9750

33

MF-LF

402

5%

1/16W

21

R9751

CRITICAL

F-RT-TH-DVI

QH11121-RIG02-4F

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

32

31

C5B C5A

C4

C3

C2

C1

J9700

MF-LF

402

5%

1/16W

20K

2

1

R9715

1/16W

182

MF-LF

402

1%

2

1

R9786

182

1% 1/16W MF-LF

402

2

1

R9782

182

402

1/16W

1%

MF-LF

2

1

R9778

5% 1/16W MF-LF

0

402

21

R9773

0

1/16W MF-LF

402

5%

21

R9772

1% 1/16W MF-LF

182

402

2

1

R9770

1/16W

1%

402

182

MF-LF

2

1

R9766

370-OHM

SM

CRITICAL

4

32

1

L9706

CERM

20% 10V

0.1uF

402

2

1

C9751

20% 10V

CERM

402

0.1uF

2

1

C9750

MC74VHC1G08

SC70

5

4

1

2

3

U9750

MC74VHC1G08

SC70

5

4

1

2

3

U9751

1%

182

MF-LF

402

1/16W

2

1

R9762

0402

47nH

2

1

L9743

47nH

0402

2

1

L9748

47nH

0402

2

1

L9747

0402

47nH

2

1

L9746

47nH

0402

2

1

L9745

0402

47nH

2

1

L9744

SOT-363

2N7002DW-X-F

1

2

6

Q9715

402

MF-LF

1/16W

5%

270K

2

1

R9723

402

1%

MF-LF

1/16W

182

2

1

R9774

1210-4SM1

90-OHM-100MA

CRITICAL

4

32

1

L9700

CRITICAL

90-OHM-100MA

1210-4SM1

4

32

1

L9701

1210-4SM1

90-OHM-100MA

CRITICAL

4

32

1

L9702

CRITICAL

90-OHM-100MA

1210-4SM1

4

32

1

L9704

CRITICAL

90-OHM-100MA

1210-4SM1

4

32

1

L9703

CRITICAL

90-OHM-100MA

1210-4SM1

4

32

1

L9705

2N7002DW-X-F

SOT-363

1

2

6

Q9714

SYNC_MASTER=M59_MG

External Display Connector

77 84

A.0.0

SYNC_DATE=07/25/2006

051-7150

=PP5V_S0_SB_HPD

MAKE_BASE=TRUE

SB_DVI_HPD

DVI_HPD

SB_GPIO4

GPU_HPD_BILAT

GPU_HPD

=PP3V3_D3C_DDC_DVI

=GPU_HPD_ENABLE

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4> TMDS_DATA_F_N<3>

=GND_CHASSIS_DVI3

TMDS_DATA_F_N<5..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..0>

TMDSCONN TMDSCONN

TMDS_CLK_F_P

TMDSCONNTMDSCONN

TMDS_CLK_F_N

TMDSCONNTMDSCONN

TMDS_CLK_R_P

TMDSTMDS

TMDS_CLK_R_N

TMDSTMDS

TMDS_CLK_R_N

TMDS_CLK_R_P

TMDS_CLK_P

TMDS_CLK_N

TMDS_DATA_RL<2>

VOLTAGE=0V

NO_TEST=TRUE

VOLTAGE=0V

NO_TEST=TRUE

TMDS_DATA_RL<4>

TMDS_DATA_RL<1>

VOLTAGE=0V

NO_TEST=TRUE

TMDS_DATA_F_N<0>

NO_TEST=TRUE

VOLTAGE=0V

TMDS_DATA_RL<3>

=GND_CHASSIS_DVI1

VGA_G

GPU_R2

GPU_G2

VGA_R

VGA_G

VGA_B

VGA_VSYNC

VGA_VSYNC_R

VGA_HSYNC

VGA_HSYNC_R

GPU_H2SYNC

=PP3V3_D3C_VGASYNC

TMDS_CLK_F_N

TMDS_CLK_F_P

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

VGA_HSYNC

VGA_B

TMDS_CLK_F_N

TMDS_CLK_F_P

DVI_DDC_CLK

=GND_CHASSIS_DVI2

=PP5V_S0_DVI_DDC

=GND_CHASSIS_DVI4

VGA_R

VGA_VSYNC

VOLTAGE=0V

NO_TEST=TRUE

TMDS_DATA_RL<5>

GPU_B2

PP5V_S0_DDC_PULLUPS

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP5V_S0_DDC_F

GPU_DDC_A_CLK

GPU_DDC_A_DATA

=GND_CHASSIS_DVI5

DVI_DDC_DATA

=PP3V3_D3C_VGASYNC

GPU_V2SYNC

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<0>

TMDS_DATA_P<0>

TMDS_DATA_F_N<1>

TMDS_DATA_F_P<1>

TMDS_DATA_N<1>

TMDS_DATA_F_N<2>

TMDS_DATA_F_P<2>

TMDS_DATA_P<2>

TMDS_DATA_N<2>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<3>

TMDS_DATA_P<3>

TMDS_DATA_N<3>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>

TMDS_DATA_P<4>

TMDS_DATA_N<4>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

TMDS_DATA_P<5>

TMDS_DATA_N<5>

TMDS_DATA_P<1>

TMDS_DATA_RL<0>

VOLTAGE=0V

NO_TEST=TRUE

TMDS_DATA_F_P<2>

TMDS_DATA_F_N<1>

TMDS_DATA_F_N<2>

DVI_HPD_R

TMDS_DATA_F_P<3>

TMDS_DATA_F_P<1>

DVI_DDC_CLK_R

DVI_DDC_DATA_R

PP5V_S0_DDC

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

TMDS_DATA_F_P<0>

TMDS_DATA_N<0>

84A4

77D6

77C6

77B6

84A4

77B5

84A4

84B4

84A4

84A4 84A4

84A4

84A4 84A4

84A4

77D1

77B3

77B6

77C6

76C7

77D6

76D7

77D5

77D1

76D7

77D5

77D1

76C7

77D1

76C7

77D1

76C7

77D1

76C7

77D1

77D1 76C7

76C7

77D1

77D1 76C7

76C7

77D1

77D6

76C7

65A1

22A6

75A5

65A3

26A1

77A6

77B6

6A6

77A6

77B5

77A5

77B7

77C7

77D1

75C3

77D1

6A6

77C1

75B3

77A3

77A5

77A3

77A5

75B3

65A3

77A5

77B5

77A6

77C3

77C1

77C6

77B6

6B6

65B1

6B6

77C1

77D3

75B3

75A3

6A6

65A3

75B3

77B5

75C3

77B3

75C3

77B3

75C3

77B3

75C3

77B3

77B3 75C3

75C3

77B5

77B5 75C3

75C3

77C6

77B6

77C6

77D1

75C3

http://mycomp.su/x/

IN

OUT

IN

OUT

SYM_VER-1

OUT

IO IO

IO

OUT

IO

OUT

IO

IOIO

IO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

white colored version of 518S0369

518S0469

516S0412

are to remove this noise from SATA signals.

up significant noise. Common-mode chokes

NOTE: _UF_ nets cross DDR2 signals and pick

SATA HDD & IR & SIL Flex Connector

Top-Case Connector

516S0412

Left ALS Connector

NC

PLACEMENT_NOTE=Place C4960 close to southbridge

402

25V

CERM

10%

0.0047uF

21

C4960

PLACEMENT_NOTE=Place C4961 next to C4960

10%

402

0.0047uF

CERM

25V

21

C4961

402

10%

0.0047uF

CERM

25V

PLACEMENT_NOTE=Place C4965 close to J4960

12

C4965

25V

0.0047uF

402

10%

CERM

PLACEMENT_NOTE=Place C4966 next to C4965

12

C4966

1210-4SM1

90-OHM-100MA

CRITICAL

4

32

1

FL4960

1210-4SM1

90-OHM-100MA

CRITICAL

4

32

1

FL4965

QT500206-L020

CRITICAL

M-ST-SM

9

87

65

43

20

2

19

1817

1615

1413

1211

10

1

J4900

CRITICAL

SC-75

RCLAMP0502B

2

1

3

D4900

M-RT-SM

CRITICAL

BM04B-ACH

4

3

2

1

6

5

J6430

CRITICAL

M-ST-SM

QT500206-L020

9

87

65

43

20

2

19

1817

1615

1413

1211

10

1

J4960

M59 Specific Connectors

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

78 84

A.0.0051-7150

=I2C_TRACKPAD_SDA

=I2C_TRACKPAD_SCL

=SMBUS_TOPCASE_SCL

=SMBUS_TOPCASE_SDA

SMC_ONOFF_L

=USB_BT_N

=USB_BT_P

KBDLED_ANODE

KBDLED_RETURN

SMC_LID

=USB_TRACKPAD_N

=USB_TRACKPAD_P

=PP3V42_G3H_LIDSWITCH =PP5V_S3_TOPCASE

=PP3V3_S3_TOPCASE

SATA_C_D2R_N

SATA_C_D2R_UF_P

SATA_C_D2R_UF_N

SATA_C_D2R_P

=PP5V_S3_IR

SATA_C_D2R_C_N

SATA_C_R2D_C_P

SATA_C_R2D_C_N

=USB_IR_N

SYS_LED_ANODE

=USB_IR_P

SATA_C_D2R_C_P

=PP5V_S0_HDD

SATA_C_R2D_UF_N

SATA_C_R2D_UF_P

SATA_C_R2D_N SATA_C_R2D_P

LTALS_OUT

=PP3V3_S3_LTALS

ALS_GAIN

50C6 50B2

49B5

49C5 50B2

55C7

65C3

6D5

27C6

27C3

5B2

6C3

55A4

49B5

6D3

65D3

65B1

65C3

21B6

65B1

21B6

6C3

50A7

6C3

65B1

5B2

http://mycomp.su/x/

SYM_VER-3

GND

SEL

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9* DH19

DH14

DH13

DH12

DH11

DH10

DH9

DH15 DH16 DH17 DH18

DB4* DB5* DB6* DB7* DB8*

DB0* DB1* DB2* DB3*

DH4

DH3

DH2

DH1

DH0

DH8

DH7

DH6

DH5

DA15 DA16 DA17 DA18 DA19

DA13 DA14

DA12

DA11

DA10

DA5 DA6 DA7 DA8 DA9

DA0 DA1 DA2 DA3 DA4

VDD

G

S D

G

S D

1B1

4B2

2B1 2B2 3B1 3B2 4B1

1B2

1A

2A

3A

4A

OE*

S

THRML

PAD

GND

VCC

SYM_VER-2

V3 V4

RST*

V2

V1

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Divider set to rise to 1.88V nom/1.74V min when panel power is

LTC2903 guaranteed threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)

D3CPGOOD_ALL BOM option stuffs LTC2903 circuit to monitor all D3C rails to qualify D3CPGOOD. D3CPGOOD_3V3 BOM option uses only PP3V3_D3C to qualify D3CPGOOD.

the pump-up in the panel, though some voltage will still be seen

PGOOD Monitor for GPU Rails

NOTE: These parts are to counter an invalid state caused by the M56 part. Bias voltage is present on LVDS interface pins even when they should be tri-stated to meet panel power sequence

and long-term reliability issues. Pull-down resistors reduce

on LVDS signals when they should be 0V.

GPU LVDS I/F

NB LVDS I/F

NC

NOTE: SEL = LOW selects port B

NC

Panel/Backlight Control Mux

NOTE: SB_GPIO23 has internal 20K PU to default selection to GPU

NOTE: S = HIGH selects xB2

LVDS I/F Mux

R9981 can also be used as pad for cap, creating an RC filter.

at 3.3V/3.315V. Schmitt trigger voltage max is 1.70V (@2.625V Vcc).

Enables the GPU LVDS path in the mux with the qualification

panel power has risen to (near) 3.3V. This should eliminate need for LVDS pulldowns

that the GPU has turned on panel power and that the

LVDS Mux Selection Qualification

requirements. Resulting pump-up in LCD panel can cause startup

LVDS Interface Pull-downs

GPU DDC Pass FETs

LVDS_PD

1/16W SM-LF

8.2K

5%

81

RP9900

1/16W

8.2K

5%

LVDS_PD

SM-LF

81

RP9902

D3CPGOOD_ALL

5% MF-LF

402

1/16W

470K

2

1

R9996

CBTV4020

CRITICAL

BGA-LF

F8F3E8

E3

H6H5G9G2D9D2C6

C5

E2

C2

B2

B3

B5

B6

B8

B9

C9

E9

F9

H9

J9

J8

J6

J5

J3

J2

H2

F2

E1

C1

A1

A3

A4

A6

B7

A9

B10

D10

F10

H10

K10

K8

K7

K5

J4

K2

J1

G1

D1

B1

A2

B4

A5

A7

A8

A10

C10

E10

G10

J10

K9

J7

K6

K4

K3

K1

H1

F1

U9950

MC74VHC1G08

SC70

5

4

1

2

3

U9985

402

0.1UF

CERM

10V

20%

2

1

C9985

SOT-363

2N7002DW-X-F

1

2

6

Q9970

SOT-363

2N7002DW-X-F

4

5

3

Q9970

D3CPGOOD_ALL

402

0.1UF

20% 10V CERM

2

1

C9993

LVDS_PD

8.2K

5% 1/16W SM-LF

63

RP9902

D3CPGOOD_ALL

402

10V

20%

0.1UF

CERM

2

1

C9995

D3CPGOOD_ALL

CERM

10V

20%

0.1UF

402

2

1

C9992

5%

10K

1/16W

402

MF-LF

2

1

R9997

MC74VHC1G08

SC70

5

4

1

2

3

U9961

NO STUFF

402

MF-LF

1/16W

5%

0

2

1

R9962

0.1UF

402

CERM

20% 10V

2

1

C9961

D3CPGOOD_3V3

6.3V

10%

1UF

402

CERM

2

1

C9996

LVDS_PD

5%

SM-LF

8.2K

1/16W

54

RP9902

LVDS_PD

8.2K

5% 1/16W SM-LF

72

RP9903

8.2K

1/16W

5%

LVDS_PD

SM-LF

81

RP9903

5%

LVDS_PD

8.2K

SM-LF

1/16W

63

RP9903

8.2K

1/16W

5%

LVDS_PD

SM-LF

54

RP9903

LVDS_PD

8.2K

5%

SM-LF

1/16W

72

RP9900

LVDS_PD

SM-LF

8.2K

5% 1/16W

54

RP9900

402

0.1UF

CERM

10V

20%

2

1

C9950

8.2K

1/16W SM-LF

5%

LVDS_PD

63

RP9900

10V

20%

CERM

402

0.1UF

2

1

C9960

LVDS_PD

8.2K

SM-LF

5% 1/16W

72

RP9901

15.8K

1%

402

1/16W MF-LF

2

1

R9970

15.8K

1%

402

1/16W MF-LF

2

1

R9971

CRITICAL

74CBTLV3257

QFN

16

17

1

8

15

13

14 12

10

11

9

6

5 7

3

2 4

U9960

1/16W

5%

SM-LF

LVDS_PD

8.2K

81

RP9901

402

CERM

10V

20%

0.1UF

2

1

C9980

402

10K

MF-LF

1/16W

5%

2

1

R9960

100K

MF-LF

1/16W

5%

402

2

1

R9961

1/16W

LVDS_PD

8.2K

5%

SM-LF

63

RP9901

SN74LVC1G132

SC70-5

CRITICAL

5

4

2

1

3

U9980

8.2K

1/16W

5%

LVDS_PD

SM-LF

54

RP9901

1/16W

402

5%

MF-LF

10K

2 1

R9980

1/16W MF-LF 402

13.3K

1%

2

1

R9981

0.1uF

CERM

402

20% 10V

2

1

C9991

MC74VHC1G08

SC70

5

4

1

2

3

U9991

D3CPGOOD_ALL

402

0.1uF

CERM

20% 10V

2

1

C9990

LVDS_PD

8.2K

1/16W

5%

SM-LF

72

RP9902

CRITICAL

D3CPGOOD_ALL

LTC2903

TSOT-23

5

4

3

1

6

2

U9990

D3CPGOOD_ALL

365K

1/16W

1%

402

MF-LF

2

1

R9990

D3CPGOOD_ALL

MF-LF

1/16W

1%

237K

402

2

1

R9992

D3CPGOOD_ALL

1/16W MF-LF

1%

402

124K

2

1

R9994

D3CPGOOD_ALL

MF-LF

1/16W

1%

402

100K

2

1

R9991

D3CPGOOD_ALL

100K

MF-LF

402

1%

1/16W

2

1

R9993

D3CPGOOD_ALL

100K

1/16W

1%

402

MF-LF

2

1

R9995

SYNC_MASTER=M59_MG

051-7150

79

A.0.0

84

SYNC_DATE=08/01/2006

LVDS Interface Pull-downs

=LVDS_MUX_SEL_GPU

LVDS_MUX_SEL_GPU_MUXED

=PP3V3_S0_LVDS_MUX

PLT_RST_L

LVDS_DDC_DATA

LVDS_DDC_CLK

GPU_DDC_C_DATA

GPU_DDC_C_CLK

MAKE_BASE=TRUE

LVDS_CONN_DDC_DATA

LVDS_CONN_DDC_CLK

MAKE_BASE=TRUE

=PP3V3_D3C_GPU_LVDS_DDC

=GPU_DDC_ENABLE

S0PGOOD_PWROK

PP1V8_D3C PP1V2_D3C

GPU_DIGON

GPU_DIGON_AND_SELECTED

=PP3V3_S0_LVDS_MUX

=LVDS_PD_U_DATA_N<0>

=LVDS_PD_U_DATA_P<2>

=LVDS_PD_U_CLK_N

=PP3V3_S0_LVDS_MUX

PANEL_PWR_ON

=LVDS_MUX_SEL_GPU

=PP2V5_S0_LVDS_MUX

PP3V3_LCD_SW

LVDS_MUX_SEL_GPU_L

=PP2V5_S0_LVDS_MUX

LVDS_U_DATA_CONN_P<2>

LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N

LVDS_U_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<1>

LVDS_L_DATA_CONN_P<2> LVDS_L_DATA_CONN_N<2> LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1>

LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N

LVDS_L_DATA_CONN_N<0> LVDS_L_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<0>

LVDS_U_DATA_CONN_N<2>

LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_P<2>

LVDS_U_DATA_N<1>

LVDS_U_CLK_N LVDS_U_CLK_P

LVDS_U_DATA_P<1>

LVDS_L_DATA_N<2> LVDS_L_DATA_N<1> LVDS_L_DATA_P<1>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<0>

LVDS_L_DATA_N<0>

LVDS_L_CLK_N

LVDS_L_CLK_P

LVDS_U_DATA_N<2> LVDS_U_DATA_N<0> LVDS_U_DATA_P<0>

LVDS_B_DATA_N<1>

LVDS_B_CLK_N LVDS_B_CLK_P LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_A_DATA_N<2> LVDS_A_DATA_N<1> LVDS_A_DATA_P<1>

LVDS_A_CLK_N

LVDS_A_DATA_N<0> LVDS_A_DATA_P<0> LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0>

LVDS_A_CLK_P

=LVDS_PD_L_DATA_N<2>

S0D3CPGOOD_PWROK

=PP3V3_S0_ALLSYSPG

=LVDS_PD_L_DATA_P<0>

GPU_BLON

=LVDS_PD_L_DATA_P<2>

PGOOD_MUXED_S0_OR_S0D3C

INVERTER_PWM_UNBUF

S0D3CPGOOD_PWROK

S0PGOOD_PWROK

TP_SB_GPIO23

LVDS_MUX_SEL_GPU

MAKE_BASE=TRUE

=LVDS_MUX_SEL_GPU

=LVDS_PD_L_DATA_N<0>

=LVDS_PD_L_CLK_N

=LVDS_PD_U_DATA_N<1>

=LVDS_PD_U_DATA_P<0>

=LVDS_PD_L_CLK_P

=LVDS_PD_U_DATA_P<1>

=LVDS_PD_U_CLK_P

GPU_DIGON

LVDS_PANEL_EN

LVDS_VDDEN

LVDS_BKLTEN

LVDS_BKLTCTL GPU_VARY_BL

INVERTER_BKLTON

=LVDS_PD_U_DATA_N<2>

=LVDS_PD_L_DATA_P<1>

=LVDS_PD_L_DATA_N<1>

D3CPGOOD_PWROK

PP3V3_D3C

D3CPGOOD_2V5_DIV

D3CPGOOD_1V2_DIV

D3CPGOOD_1V8_DIV

PP2V5_D3C

79C6

79B3

76D7

79B6

79B3

26C3

79A4

79D3

79C5

76B2

76C2

76D7

65A3

79D5

79B6

79A3

65A3

22A6

13D5

75A3

76C3

65A3

26A1

64A2

65B6

65D6

74C3

65A3

6B3

65A3

79A3

65A6

76D3

65A6

6B1

6A1

6B1

6A1

6B1

75B3

75A3

75B3

13C5

13D5

13C5

6A3

79A4

64B1

6B3

71C5

6A3

64B2

76A8

79C4

64A2

21D5

79A4

6A3

6B3

74C3

76D4 13D5

13D5

74C3

76B8

6B3

6A3

65A3

65A6

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Date - Radar # - Description Date - Radar # - DescriptionDate - Radar # - Description

DMS Release #01000

2006/05/26 - 4508681 - Release for Proto

2006/06/30 - 4566939 - Release for EVT

DMS Release #04000

2006/08/07 - 4607952 - Release for DVT

DMS Release #0A000

2006/09/19 - 4726575 - Release for PVT

DMS Release #07000

051-7150 A.0.0

8480

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

http://mycomp.su/x/

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DG says minimum spacing 50 mils to clocks

DG recommends at least 25 mils, >50 mils preferred

USB 2.0 Interface Constraints

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs. DSTB complementary pairs are spaced 3:1, even in constraint areas.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

FSB (Front-Side Bus) Constraints

Disk Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2

PCI-Express / DMI Bus Constraints

Design Guide recommends FSB signals be routed only on internal layers.

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2

Internal Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

Audio Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4

Need to support MEM_*-style wildcards!

Some signals require 27.4-ohm single-ended impedance.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

All FSB signals with impedance requirements are 55-ohm single-ended.

CPU Signal Constraints

DDR2 Memory Bus Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

Clock Signal Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

Y*

CLK_SLOW_55S

=55_OHM_SE

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

*

=2:1_SPACING

FSB_COMMON

* Y

DMI_100D

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

Y*

PCIE_100D

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

CLK_SLOW

*

10 MIL

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

Y*

SPI_55S

MEM_CLK2MEM

=4:1_SPACING

*

MEM_2OTHER

25 MIL

*

=2:1_SPACING

MEM_CTRL2CTRL

=3:1_SPACING

*

MEM_CTRL2MEM

* *

MEM_DQS

MEM_2OTHER

**

MEM_DATA

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

PCIE

*

20 MIL

DMI

*

20 MIL

AUDIO_55S

* Y

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

AUDIO

*

=1.8:1_SPACING

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

Y*

SMB_55S

USB2

=4:1_SPACING

*

USB2_2CLK

*

25 MIL

=3:1_SPACING

*

SMB

CLK_MED

*

20 MIL

=3:1_SPACING

*

FSB_ADDR2ADSTB

=3:1_SPACING

FSB_ADSTB

*

=2:1_SPACING

FSB_ADDR2ADDR

*

FSB_ADDR

=3:1_SPACING

*

=3:1_SPACING

*

FSB_DSTB

=2:1_SPACING

*

FSB_DATA2DATA

=3:1_SPACING

FSB_DATA

*

=3:1_SPACING

*

FSB_DATA2DSTB

=27P4_OHM_SE

* Y

=27P4_OHM_SE =27P4_OHM_SE

=STANDARD =STANDARD

CPU_27P4S

CPU_2TO1

*

=2:1_SPACING

*

FSB_ADDR FSB_ADDR

FSB_ADDR2ADDR

IDE_55S

* Y

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

SATA_100D

Y*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

Napa Platform Constraints

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

8481

FSB_DSTBFSB_DATA

*

FSB_DATA2DSTB

IDE

=1.8:1_SPACING

*

=85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

MEM_85D

Y

=85_OHM_DIFF

* *

MEM_CLK

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

FSB_ADDR2ADSTB

FSB_ADDR

FSB_ADSTB

*

SATA

*

20 MIL

Y*

USB2_90D

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

FSB_55S

=55_OHM_SE

*

=55_OHM_SE

Y

=55_OHM_SE

=STANDARD =STANDARD

MEM_CLK

MEM_CMD2MEM

*

MEM_CMD

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

*

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

=3:1_SPACING

*

MEM_CMD2MEM

=1.8:1_SPACING

SPI

*

Y*

=100_OHM_DIFF=100_OHM_DIFF

CLK_FSB_100D

=100_OHM_DIFF

Y*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF

=STANDARD=STANDARD

=55_OHM_SE

Y*

CLK_MED_55S

=55_OHM_SE=55_OHM_SE

CPU_55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

Y

=STANDARD =STANDARD

=70_OHM_DIFF

MEM_70D

=70_OHM_DIFF

=70_OHM_DIFF=70_OHM_DIFF

* Y

=70_OHM_DIFF

CLK_FSB

*

25 MIL

CLK_PCIE

*

20 MIL

=1.5:1_SPACING

*

MEM_CMD2CMD

*

=3:1_SPACINGMEM_DATA2MEM

*

MEM_DATA2DATA

=1.5:1_SPACING

=3:1_SPACING

*

MEM_DQS2MEM

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL

MEM_DATA2MEM

MEM_DATA

*

MEM_CLK

MEM_DATA

MEM_DATA2MEM

*

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_CTRL2MEM

*

MEM_CMD

MEM_CTRL

MEM_CTRL2CTRL

*

MEM_CTRL

*

MEM_CLK

MEM_CTRL2MEM

MEM_CTRL

*

=STANDARD

=45_OHM_SE

=STANDARD

MEM_45S

Y

=45_OHM_SE =45_OHM_SE

CPU_VCCSENSE

*

25 MIL

CPU_COMP

*

25 MIL

=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

MEM_55S

Y*

=55_OHM_SE

*

CPU_GTLREF

25 MIL

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

MEM_CMD2MEM

MEM_CMD

* *

MEM_DATA MEM_DATA

MEM_DATA2DATA

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

FSB_DATA2DATA

FSB_DATA

*

FSB_DATA

=2:1_SPACING

*

CPU_ITP

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.

NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"

Video Signal Constraints

GDDR3 (Frame Buffer) Memory Bus Constraints

SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

note

DQ/DQM/DQS lines are 40-ohm single-ended impedence.

CTRL lines are 55-ohm single-ended impedence.

LVDS and TMDS signals are 100-ohm +/- 10% differential impedence. LVDS and TMDS pairs should be kept at least 25 mils apart. Ground shields can be used around each pair if spacing cannot be met.

Ground shields recommended around VGA signals.

VGA should be routed as close to 75-ohms single-ended impedence as possible. VGA signals should be kept at least 15 mils from other traces.

SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"

High-Speed I/O Interface Constraints

PCI Bus Constraints

NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.

=3:1_SPACING

FW

*

15 MIL

*

VGA

=3:1_SPACING

*

TMDS

*

=3:1_SPACING

LVDS

FB_40S

=40_OHM_SE

*

=STANDARD =STANDARD

=40_OHM_SE=40_OHM_SE

Y

=55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE

*

=55_OHM_SE

FB_55S

FB_CLK

=2.5:1_SPACING

*

=100_OHM_DIFF

TMDS_100D

* Y

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=STANDARD

* Y

=STANDARD

=75_OHM_SE =75_OHM_SE =75_OHM_SE

VGA_75S

*

FB_ADCTRL

=2.5:1_SPACING

*

LVDS_PAIR2PAIR

25 MIL

*

TMDS_PAIR2PAIR

25 MIL

=3:1_SPACING

ENET

*

=100_OHM_DIFF

LVDS_100D

Y*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

FB_75D

=75_OHM_DIFF=75_OHM_DIFF

=75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFF

Y*

LVDS

*

LVDS_PAIR2PAIR

LVDS

*

PCI

=2:1_SPACING

PCI_55S

=55_OHM_SE

*

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

Y

FB_35S_TO_55S =35_55_OHM_SE

=STANDARD=STANDARD

* Y

=35_OHM_SE =55_OHM_SE

=2.5:1_SPACING

*

FB_DATA

* Y

=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF

=110_OHM_DIFF =110_OHM_DIFF

FW_110D

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

* Y

TMDS

TMDS_PAIR2PAIR

*

TMDS

051-7150 A.0.0

8482

More System Constraints

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

http://mycomp.su/x/

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)

Unsupported rule

"Stale" physical / spacing types

Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.

M59 Board-Specific Spacing & Physical Constraints

*

BGA

CLK_PCIE BGA_P2MM

BGA_P2MM

BGA

*

CLK_SLOW

BGA_P2MM

CLK_MED

BGA

*

1.5:1_SPACING

ISL2,ISL11

0.1 MM

2:1_SPACING

0.1 MM

ISL2,ISL11

*

BGA

BGA_P2MM

FB_CLK

BGA

FSB_DSTB BGA_P3MMFSB_DSTB

1.8:1_SPACING

0.1 MM

ISL2,ISL11

*

=2:1_SPACING

FSB_DATA2DSTB

4:1_SPACING

ISL2,ISL11

0.1 MM

3:1_SPACING

0.1 MM

ISL2,ISL11

0.1 MM

*

DEFAULT

BGA_P1MM

BGA

* *

=DEFAULTBGA_P2MM

*

BGA

BGA_P2MM

MEM_CLK

0.100 MM

MEM_85D

*

MEM_70D

0.100 MM

*

0.150 MM0.150 MM

45_OHM_SE

TOP,BOTTOM

Y

=DEFAULT

=DEFAULT=DEFAULT

STANDARD

*

=DEFAULT

Y

12.7 MM

=2:1_SPACING

FSB_DATA

*

0.230 MM0.230 MM

35_OHM_SE

Y

TOP,BOTTOM

BGA_P2MM

*

CLK_FSB

BGA

=STANDARD

FSB_DATA2DATA

*

0.240 MM

=STANDARD

0.240 MM

27P4_OHM_SE

=STANDARD

Y*

*

MEM_45S

0.100 MM

2.5:1_SPACING

0.1 MM

ISL2,ISL11

*

STANDARD =DEFAULT

ISL2,ISL11

0.1 MM

SATA

CLK_FSB

ISL2,ISL11

0.1 MM

CLK_MED

ISL2,ISL11

0.1 MM

ISL2,ISL11

VGA

ISL2,ISL11

0.1 MM

TMDS_PAIR2PAIR

CPU_GTLREF

0.1 MM

ISL2,ISL11

CPU_COMP

ISL2,ISL11

0.1 MM

ISL2,ISL11

0.1 MMDMI

CPU_VCCSENSE

ISL2,ISL11

0.1 MM

ISL2,ISL11

LVDS_PAIR2PAIR

CLK_SLOW

0.1 MM

ISL2,ISL11

0.1 MM

MEM_2OTHER

PCIE

0.1 MM

ISL2,ISL11

CLK_PCIE

0.1 MM

ISL2,ISL11

=DEFAULT

*

BGA_P1MM

*

0.2 MM

2:1_SPACING

1.8:1_SPACING

*

0.18 MM

0.15 MM

1.5:1_SPACING

*

2.5:1_SPACING

0.25 MM

*

0.4 MM

4:1_SPACING

*

0.3 MM

3:1_SPACING

*

VGA

*

VGA_75S

MEM_PP1V8_S3

**

STANDARD

* *

STANDARDFB_PP1V8

0.1 MM

PCI_2PCI

*

PCI_2PCI

PCIPCI

*

BGA_P3MM

*

=DEFAULT

FSB_ADDR

*

=2:1_SPACING

0.124 MM0.124 MM

50_OHM_SE

Y

TOP,BOTTOM

=2:1_SPACING

*

FSB_DSTB

*

MEM_2OTHER

0.5 MM

TMDS

**

TMDSCONN

*

FSB_COMMON

*

FSB_ANALOG

* *

FSB_COMMON

FSB_P2MM

0.125 MM

80_OHM_DIFF

*

=STANDARD

0.125 MM

0.111 MM0.115 MM

Y

*

0.125 MM0.125 MM

0.131 MM0.131 MM

75_OHM_DIFF

Y

=STANDARD

0.125 MM0.125 MM

TOP,BOTTOM

0.161 MM0.161 MM

75_OHM_DIFF

Y

75_OHM_SE

0.076 MM 0.076 MM

=STANDARD

Y*

=STANDARD

0.200 MM0.200 MM

0.099 MM0.099 MM

100_OHM_DIFF

TOP,BOTTOM

Y

0.200 MM

0.080 MM

0.200 MM

0.080 MM

* Y

=STANDARD

100_OHM_DIFF

0.220 MM

0.130 MM

0.220 MM

0.130 MM

90_OHM_DIFF

Y

TOP,BOTTOM

0.220 MM

Y

0.220 MM

0.102 MM0.102 MM

90_OHM_DIFF

*

=STANDARD

0.125 MM0.125 MM

0.140 MM0.140 MM

80_OHM_DIFF

Y

TOP,BOTTOM

*

TMDS_100D

TMDS

LVDS

LVDS_100D

*

FSB_ADDR2ADSTB

*

=2:1_SPACING

FSB_ADSTB

=2:1_SPACING

*

FSB_ADDR2ADDR

=STANDARD

*

70_OHM_DIFF

0.125 MM0.125 MM

0.149 MM0.149 MM

*

=STANDARD

Y

DEFAULT

=55_OHM_SE=55_OHM_SE

0 MM0 MM

Y*

30 MM

0.100 MM

55_OHM_SE

Y

0.100 MM

TOP,BOTTOM

Y

55_OHM_SE =STANDARD

=STANDARD =STANDARD

0.076 MM 0.076 MM

*

0.090 MM

=STANDARD

0.090 MM

50_OHM_SE

=STANDARD

Y*

=STANDARD

=STANDARD=STANDARD

Y*

45_OHM_SE

0.105 MM0.105 MM

TMDS_100D

*

TMDSCONN

0.185 MM

40_OHM_SE

0.185 MM

Y

TOP,BOTTOM

0.330 MM0.330 MM

0.089 MM0.089 MM

Y

110_OHM_DIFF

TOP,BOTTOM

0.077 MM0.077 MM

0.330 MM0.330 MM

110_OHM_DIFF

* Y

=STANDARD

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

MM

15.2

NO_TYPE,BGA

0.076 MM

35_55_OHM_SE

* Y

=STANDARD

0.165 MM

=STANDARD

Y

TOP,BOTTOM

0.335 MM 0.335 MM

27P4_OHM_SE

=STANDARD35_OHM_SE

0.165 MM0.165 MM

=STANDARD=STANDARD

Y*

=STANDARD

0.131 MM

=STANDARD

Y*

40_OHM_SE

0.100 MM

M59 Spacing & Physical Constraints

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

8483

TOP,BOTTOM

Y

0.230 MM

35_55_OHM_SE

0.100 MM

70_OHM_DIFF

0.125 MM0.125 MM

0.185 MM0.185 MM

Y

TOP,BOTTOM

0.125 MM

0.101 MM0.101 MM

* Y

=STANDARD

85_OHM_DIFF

0.125 MM

Y

85_OHM_DIFF

TOP,BOTTOM

**

I2C SMB

* *

GND

STANDARD

ENET

**

ENETCONN

I2C

FSB_P2MM

MEM_PP1V8_S3 FB_PP1V8

PCI_55S

PCI

FSB_ANALOG

GND

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

I70

I71

I72

I73

M59 Net Properties

SYNC_DATE=(MASTER)

051-7150 A.0.0

8484

SYNC_MASTER=(MASTER)

TMDS_DATA_F_N<2..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_N<5..3>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<2..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..3>

TMDSCONNTMDSCONN

TMDS_DATA_N<2..0>

TMDSTMDS

TMDS_DATA_N<5..3>

TMDSTMDS

TMDS_DATA_P<2..0>

TMDSTMDS

TMDS_DATA_P<5..3>

TMDSTMDS

TMDS_CLK_F_P

TMDSCONNTMDSCONN

TMDS_CLK_F_N

TMDSCONNTMDSCONN

FSB_LOCK_L

FSB_COMMON

FSB_55S

MEM_DQS MEM_85D

FB_CLK FB_75D

SATA

SATA_100D

ENET

ENET_100D

CPU_COMP<1>

CPU_COMP

CPU_55S

SMB

SMB_55S

FSB_BPRI_L

FSB_COMMON

FSB_55S

CPU_XDP_CLK_N

CPU_ITP

CLK_FSB_100D

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

CPU_INTR

CPU_55S

FSB_ADSTB_L<3..0>

FSB_ADSTB

FSB_55S

FSB_D_L<63..0>

FSB_DATA

FSB_55S

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

USB2

USB2_90D

FW

FW_110D

CLK_FSB

CLK_FSB_100D

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_55S

FSB_DSTBP_L<3..0>

FSB_DSTB

FSB_55S

FSB_DINV_L<3..0>

FSB_DATA

FSB_55S

FSB_DSTBN_L<3..0>

FSB_DSTB

FSB_55S

CPU_COMP<2>

CPU_COMP

CPU_27P4S

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_GTLREF

CPU_55S

PM_DPRSLPVR

CPU_2TO1

CPU_55S

CPU_IGNNE_L

CPU_55S

CPU_DPSLP_L

CPU_55S

CPU_A20M_L

CPU_55S

CPU_NMI

CPU_55S

CPU_PWRGD

CPU_55S

IMVP_DPRSLPVR

CPU_2TO1

CPU_55S

FSB_FERR_L

CPU_55S

FSB_A_L<31..3>

FSB_ADDR

FSB_55S

CPU_VCCSENSE_N

THERM

CPU_VCCSENSE

CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_27P4S

CPU_XDP_CLK_P

CPU_ITP

CLK_FSB_100D

XDP_BPM_L<5..0>

CPU_ITPCPU_55S

FSB_BREQ0_L

FSB_COMMON

FSB_55S

FSB_ADS_L

FSB_COMMON

FSB_55S

MEM_CMD MEM_55S

MEM_CLK MEM_70D

MEM_CTRL

MEM_45S

MEM_DATA

MEM_55S

CPU_SMI_L

CPU_55S

CPU_INIT_L

CPU_55S

FB_ADCTRL

FB_55S

FB_ADCTRL

FB_35S_TO_55S

FB_DATA

FB_40S

DMI

DMI_100D

FSB_IERR_L

CPU_55S

CPU_THERMTRIP_L

CPU_2TO1

CPU_55S

FSB_HIT_L

FSB_COMMON

FSB_55S

IDE

IDE_55S

CLK_PCIE

CLK_PCIE_100D

CLK_MED

CLK_MED_55S

SB_ACZ_RST_L

AUDIO

AUDIO_55S

ACZ_RST_L

AUDIO

AUDIO_55S

ACZ_SDATAOUT

AUDIO

AUDIO_55S

SB_ACZ_SDATAOUT

AUDIO

AUDIO_55S

ACZ_SDATAIN<0>

AUDIO

AUDIO_55S

ACZ_SYNC

AUDIO

AUDIO_55S

TMDS_CLK_N

TMDSTMDS

SB_ACZ_SYNC

AUDIO

AUDIO_55S

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_BNR_L

FSB_COMMON

FSB_55S

TMDS_CLK_P

TMDSTMDS

PCIE

PCIE_100D

TMDS

TMDS_100D

LVDS

LVDS_100D

VGA

VGA_75S

CPU_STPCLK_L

CPU_55S

FSB_REQ_L<4..0>

FSB_ADDR

FSB_55S

FSB_DPWR_L

FSB_COMMON

FSB_55S

SPI

SPI_55S

CLK_SLOW

CLK_SLOW_55S

ACZ_BITCLK

AUDIO

AUDIO_55S

SB_ACZ_BITCLK

AUDIO

AUDIO_55S

CPU_VCCSENSE_P

THERM

CPU_VCCSENSE

CPU_27P4S

CPU_VID<6..0>

CPU_2TO1

CPU_55S

CPU_VID<6..0>

CPU_2TO1

CPU_55S

ITPRESET_L

CPU_ITPCPU_55S

12D6 12C6 12B6

12B4

77D6

77D1

77D6

77D1

7C4

12D4

77D1

77B6

77D1

77B6

77D8

77B8

77D8

77B8

12C4

7C3

12C4

12B4

77C6

77B5

77C6

77B5

77C8

77A8

77C8

77A8

77D1

12B4

7D8

7B4

12B4

12C4

12B4

7B4

59C8

7D8

12C4

12B4

47B3

47B6

77C8

12B4

12C4

77B8

12A4

47B6

84B6

77B5

77B3

77B5

77B3

76C7

77B6

77C6

7D6

12C4

34D3

21C4

7C8

7B3

7D6

12A4

11B5

7D6

7B3

23C3

21C4

7C8

59A1

34D3

11B3

7D6

21C4

7D6

21C7

76C7

12B4

7D6

76C7

21C4

7D8

12B4

21C7

59B1

9C2

77B3

77A6

77B3

77A6

75C3

77B5

77A5

5D5

7B3

7D6

11B3

59A3

7C8

5D5

7D6

5D5

7B3

7B4

14B7

7C8

7B3

7C8

7B3

59C7

5D5

8B6

59A3

7B3

11B3

7C6

5D5

7C8

7D6

5D5

21C6

5C1

21C6

5C1

75C3

21C6

7D6

5D5

75C3

7C8

5D5

7B3

5C1

21C6

8B6

8B7

11B3

Apple macbook pro 15 a1211 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual