Apple macbook pro 15 a1211 Schematics

http://mycomp.su/x/

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

09/19/2006

Schematic / PCB #’s

SCHEM,MLB,M59

ABBREV=DRAWING

TITLE=M59_MLB

LAST_MODIFIED=Mon Sep 25 10:45:58 2006

1

1

Table of Contents

N/A

N/A

Date

(.csa)

SyncPage

Contents

(MASTER)

42

44

(MASTER)

FW PHY Power Supply

Page Sync

(.csa)

Date

Contents

051-7150

1

CRITICAL

SCH

SCHEM,MLB,M59

820-2054 CRITICAL

PCB1

PCBF,MLB,M59

051-7150

SCHEM,MLB,M59

841

463525

A.0.0

A

PRODUCTION RELEASE

9/19/2006 9/19/2006

(MASTER)

43

45

(MASTER)

FireWire Port Power

(MASTER)

44

46

(MASTER)

FireWire Ports

(MASTER)

45

49

(MASTER)

Camera Connector

(MASTER)

46

52

(MASTER)

External USB Connector

(MASTER)

47

55

(MASTER)

Left I/O Board Connector

(MASTER)

48

57

(MASTER)

PCI-E Connections

(MASTER)

49

58

(MASTER)

SMC

(MASTER)

50

59

(MASTER)

SMC Support

(MASTER)

51

60

(MASTER)

LPC+ Debug Connector

(MASTER)

52

61

(MASTER)

Thermal Sensors

(MASTER)

53

62

(MASTER)

Current & Voltage Sensing

(MASTER)

54

63

(MASTER)

SPI BOOTROM

(MASTER)

55

64

(MASTER)

ALS Support

(MASTER)

56

65

(MASTER)

Fan Connectors

(MASTER)

57

66

(MASTER)

Sudden Motion Sensor (SMS)

(MASTER)

58

67

(MASTER)

TPM

(MASTER)

59

75

(MASTER)

IMVP6 CPU VCore Regulator

(MASTER)

60

76

(MASTER)

5V / 1.5V Power Supply

05/07/2006

61

77

M59_MG

2.5V & 1.2V Regulators

05/07/2006

62

78

M59_MG

1.8V Supply

05/07/2006

63

79

M59_MG

3.3V / 1.05V Power Supplies

08/01/2006

64

80

M59_MG

3.3V G3Hot Supply & Power Control

05/07/2006

65

81

M59_MG

Power Aliases

(MASTER)

66

82

(MASTER)

PBus-In,Batt. & 3G Pwr Connectors

(MASTER)

67

84

(MASTER)

ATI M56 PCI-E

(MASTER)

68

85

(MASTER)

GPU (M56) Core Supplies

(MASTER)

69

86

(MASTER)

ATI M56 Core Power

(MASTER)

70

87

(MASTER)

ATI M56 Frame Buffer I/F

07/25/2006

71

88

M59_MG

GPU Straps

(MASTER)

72

89

(MASTER)

GDDR3 Frame Buffer A

(MASTER)

73

90

(MASTER)

GDDR3 Frame Buffer B

(MASTER)

74

91

(MASTER)

ATI M56 GPIO/DVO/Misc

(MASTER)

75

93

(MASTER)

ATI M56 Video Interfaces

07/25/2006

76

94

M59_MG

Internal Display Connectors

07/25/2006

77

97

M59_MG

External Display Connector

(MASTER)

78

98

(MASTER)

M59 Specific Connectors

08/01/2006

79

99

M59_MG

LVDS Interface Pull-downs

N/A

80

100

N/A

Revision History

(MASTER)

81

101

(MASTER)

Napa Platform Constraints

(MASTER)

82

102

(MASTER)

More System Constraints

(MASTER)

83

103

(MASTER)

M59 Spacing & Physical Constraints

(MASTER)

84

104

(MASTER)

M59 Net Properties

2

2

System Block Diagram

N/A

N/A

3

3

Power Block Diagram

N/A

N/A

4

4

BOM Configuration

N/A

N/A

5

5

Functional / ICT Test

N/A

N/A

6

6

Signal Aliases/Misc Comps

N/A

N/A

7

7

CPU 1 OF 2-FSB

(MASTER)

(MASTER)

8

8

CPU 2 OF 2-PWR/GND

(MASTER)

(MASTER)

9

9

CPU Decoupling & VID

(MASTER)

(MASTER)

10

10

CPU MISC1-TEMP SENSOR

(MASTER)

(MASTER)

11

11

CPU ITP700FLEX DEBUG

(MASTER)

(MASTER)

12

12

NB CPU Interface

(MASTER)

(MASTER)

13

13

NB PEG / Video Interfaces

(MASTER)

(MASTER)

14

14

NB Misc Interfaces

(MASTER)

(MASTER)

15

15

NB DDR2 Interfaces

(MASTER)

(MASTER)

16

16

NB Power 1

(MASTER)

(MASTER)

17

17

NB Power 2

(MASTER)

(MASTER)

18

18

NB Grounds

(MASTER)

(MASTER)

19

19

NB (GM) Decoupling

M59_MG

07/25/2006

20

20

NB Config Straps

(MASTER)

(MASTER)

21

21

SB: 1 OF 4

(MASTER)

(MASTER)

22

22

SB: 2 of 4

(MASTER)

(MASTER)

23

23

SB: 3 OF 4

M59_MG

07/25/2006

24

24

SB: 4 OF 4

(MASTER)

(MASTER)

25

25

SB Decoupling

(MASTER)

(MASTER)

26

26 SB Misc

(MASTER)

(MASTER)

27

27

M1 SMBus Connections

(MASTER)

(MASTER)

28

28

DDR2 SO-DIMM Connector A

(MASTER)

(MASTER)

29

29

DDR2 SO-DIMM Connector B

(MASTER)

(MASTER)

30

30

Memory Active Termination

(MASTER)

(MASTER)

31

31

Memory Vtt Supply

(MASTER)

(MASTER)

32

32

DDR2 VRef

(MASTER)

(MASTER)

33

33 CLOCKS

(MASTER)

(MASTER)

34

34

Clock Termination

M59_MG

05/07/2006

37

35

Mobile Clocking

(MASTER)

(MASTER)

38

36

PATA Connector

(MASTER)

(MASTER)

39

37

FireWire Link (TSB83AA22)

(MASTER)

(MASTER)

40

38

FireWire PHY (TSB83AA22)

(MASTER)

(MASTER)

41

39

ETHERNET CONTROLLER

(MASTER)

(MASTER)

42

40

Ethernet Connector

(MASTER)

(MASTER)

43

41

Yukon Power Control

(MASTER)

(MASTER)

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Connector

P.78

PATA

SATA

USB x2

DDR2 SO-DIMM B

DDR2 SO-DIMM A

"Expansion Slot" Connector

Geyser KB/TP/BT

Connector

MUX

Dual-Channel LVDS

LVDS Graphics

P.99

Dual-Channel TMDS

S-Video/Composite

P.67-71,74-75

ATI M56P

GPU

Yukon Power

P.39

P.57-64,69

P.56

Fan

SMBus x5

TSB83AA22 FireWire

P.43

PHY Power

Controller

Yukon Gig-E

P.39

P.37-38

Controller

Connectors

SMBus

BootROM

PWM/Tach

P.54

SPI

SMC

H8S/2116

P.49-50

LPC 33MHZ

TPM

P.58

PCI

PCIe x1

609 BGA

P.21-26

SB

P.12-20

ICH7-M

DMI x4

P.72-73

GDDR3

128MB/256MB

Frame Buffer

PCIe x16

SENSOR

P.10

THERMAL

CPU

P.7-9

NB

1466UFCBGA

945GM

FSB

(Merom)

479 BGA

Core Duo

SMS

Analog

Sensors

Connector

LPC

Debug

ALS

USB

USB

P.51

P.55,78

P.57

P.53

PCIe x1

PCIe x1

CH.B

CH.A

P.11

Power

Supplies

Azalia (HD-Audio)

BUFFER

DDR2 VREF

P.32

P.47

Connector

Audio Board

Left I/O &

P.30-31

CPU Debug

ITP700FLEX

Connector

J2900

J2800

P.28

P.29

DDR2 VTT

& REGULATOR

P.27

SB SMBus

SMC SMBus

P.27

16BITS

66MHZ

P.43

Port Power

P.40

P.44

Sensors

Temperature

FW

ENET

DVI-I/DL Connector

w/TV-Out Support

LCD Panel

ODD

Connector

Connector

Controller

CK410 Clock

P.33-34

Battery SMBus

Connector

RJ45 (Ethernet)

Connector

Right USB 2.0

Connector

1394a/b (FireWire)

P.46

P.78

P.45

P.36

P.52

P.66

P.76,79

P.77

Connectors

PWM

Connector

Inverter

P.76

Camera

USB x2

USB

HDD/IR/SIL

USB

"Factory Slot" Connector

(Upper/Inner)

(Lower/Outer)

System Block Diagram

A.0.0

2 84

051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ISL6269B)

(ISL6269B)

(ISL6269B)

(TPS51100)

(TPS51117)

(ISL9504)

1.25V - 0.8V

5V/1.5V

PM_SLP_S3_L

U8500

NC

1.5V

PGOOD

S5

3.3V

ENABLE

PPVCORE_S0_CPU

1.05V

PP1V05_S0

PGOOD

1.05V

U7950

PGOOD

GPU VCore

ENABLE

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

U7750

1.2V

PP1V2_S3

PP2V5_S3

2.5V

S3

PGOOD

ENABLE

U7700

3.3V

PP3V3_S3

PP5V_S0

5.0V

PP5V_S3

PP1V5_S0

5.0V

PP5V_S5

SMC_PM_G2_ENABLE

NC

(LTC3728)

S5/S0

PGOOD

ENABLES

U7600

5V

1.5V

PM_SLP_S3_L

SMC_PM_G2_ENABLE

PGOOD

VR_PWRGOOD_DELAY

"IMVP6"

S0

CPU VCore

ENABLES

IMVP_PWRGD_IN

IMVP_VR_ON

RSMRST_PWRGD

S0

IMVP_PWRGD_IN/ALL_SYS_PWRGD

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

ENABLE

ENABLE

J5500

Connector

Inverter

PP1V8_S3

1.8V

NC

1.8V

U7800

S3

ENABLE

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt)
S0

PP0V9_S0

0.9V

1.2V

1.8V

5.0V

U8000

3.425V

PP3V42_G3H

(LT3470)

G3Hot

3.425

ENABLE

12.6V - 9V

18.5V - 9V

PPDCIN_G3H

J5500

LIO Flex

Connector

PM_SLP_S4_L

U7900

PPBUS_G3H

J8200

LIO Power
Connector

Q3820

5V

PP5V_S0_IDE_ODD

ODD_PWR_EN_L (SB GPIO14)

PP3V3_S3AC

3.3V

Q4300

PM_SLP_S3BATT

NC

PM_SLP_S3BATT

PM_SLP_S3BATT

U7530

Q7610

Q7615

Q7770

Q7845

Q7945

1.1V - 0.95V

PP3V3_S5

3.3V

2.5V

(TPS62510)

2.5V

Q7720

2.5V

PM_SLP_S3_LS5V_L

PP2V5_S0

Q7721

PP2V5_D3C

P1V2R2V5D3C_EN_LS5V

PP1V2_D3C

P1V2R2V5D3C_EN_LS5V

P1V8D3C_EN

PP1V8_D3C

Q7947

3.3V

PP3V3_S0

3.3V

Q7948

PP3V3_D3C

P3V3D3C_EN_L

12.6V - 9V

PPBUS_S5_FWPORT

Q4500 Q4501

PM_SLP_S3_LS5V

FW_PWRCTRL_GATE1

FW_PWRCTRL_GATE2_1/2

=GPUVCORE_EN_L

D3C

PPVCORE_D3C_GPU

843

051-7150

A.0.0

SYNC_DATE=N/A

SYNC_MASTER=N/A

Power Block Diagram

http://mycomp.su/x/

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Label / EEE #’s

2.16Ghz BOMs

2.33Ghz BOMs

BOMOPTION Groups

Module Parts

extra TPM options:

Alternate Parts

SMC_TPM_GPIO2
SMC_TPM_GPIO1
SMC_TPM_PP

EEE_WTG

[EEE:WTG]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

IC,ICH7M,BGA

1

343S0385 CRITICAL

U2100

341S1797

1

CRITICAL

U4102

IC,EEPROM,SERIAL IIC,8KBIT,SO8

IC, TPM, 28-PIN TSSOP

341S1789 CRITICAL

U6700

1 TPM

U3301

CRITICAL

1

LOW POWER CLOCK SYNTHESIZER, 68PIN

359S0109

IC,ISL9504,SYNC REG CTRL,QFN48

U7530

353S1461 CRITICAL

1

IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA

338S0368

U8400

1

CRITICAL

IC,945GM,NORTHBRIDGE

CRITICAL

1

U1200

338S0269

338S0270

1

U4101

CRITICAL

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

TPM

M59_TPM

337S3393 CRITICAL

1

U0700

CPU_2_33GHZ

IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA

128S0093

33uF,16V,D2

128S0092

ALL

152S0435

ALL

152S0287

Alternates for Coilcraft MSS5131

Screened ISL6262 for ISL9504

353S1465 353S1461

ALL

ALL

128S0095

330uF,2V,6MOHM,D2

128S0060

128S0061128S0081

ALL

150uF,6.3V,25MOHM,C2

ALL

376S0445

Si7806ADN for FDM6296

376S0448

128S0060

330uF,2V,9MOHM,D2

128S0094

ALL

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEE:WTE]

EEE_WTE

4

A.0.0

BOM Configuration

051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

84

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA

333S0377

VRAM_256_INFINEON

4

CRITICAL

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

VRAM_256_HYNIX

4

CRITICAL333S0351

U8900,U8950,U9000,U9050

VRAM_128_INFINEON

333S0376

U8900,U8950,U9000,U9050

4

CRITICAL

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL333S0358

4

U8900,U8950,U9000,U9050

VRAM_128_HYNIX

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

333S0350

4

CRITICAL

VRAM_256_SAMSUNG

VRAM_128_SAMSUNG

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL333S0354

4

U8900,U8950,U9000,U9050

VRAM_INF256

GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEON

VRAM_128_SAMSUNG

VRAM_SAM128

MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M59_COMMON3

M59_COMMON1

BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3

ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3

M59_COMMON

GPU_MEM_256M,VRAM_256_SAMSUNG

VRAM_SAM256

M59_COMMON2

ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3

PCBA,2.33GHZ,256VRAM,M59,MBP15

630-7851

EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256

IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA

CPU_2_16GHZ

CRITICAL

1

U0700

337S3391

IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59

341S1922

1

CRITICAL

U6301

BOOTROM_DEVEL

1

SMC_BLANK

U5800

338S0274

IC,SMC,HS8/2116

CRITICAL

BOOTROM_FINAL

IC,EFI,BOOTROM FINAL (LOCKED),M59

341S1923

1

CRITICAL

U6301

IC,PRGRM,SMC (NEW),M59

341S1929 CRITICAL

U5800

1

SMC_PRGRM

PCBA,2.16GHZ,128VRAM,M59,MBP15

630-7849

EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128

GPU_MEM_NOT_SAM,VRAM_128_INFINEON

VRAM_INF128

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power Supply NO_TESTs

EXPOSED_VIA

NO_TEST

FUNC_TEST

FUNC_TEST

FUNC_TESTFUNC_TEST

FUNC_TEST

LPC+ Debug Connector

Fan Connectors

Left I/O Data Connector

Functional Test Points

Battery Digital Connector

Left ALS Connector

Left I/O Power Connector

Request for at least 10 GND test points

called out separately in these notes.

NOTE: 10 additional GND test points are

FUNC_TEST

should have a via with 10-mil soldermask

EXPOSED_VIA property indicates that the net

Misc EXPOSED_VIA Nets

opening for use as engineering probe point.

EXPOSED_VIA

EXPOSED_VIA

CPU FSB NO_TESTs

NO_TEST

2 TPs per

FUNC_TEST

8 TPs, 2 with each of above TP pairs

FUNC_TEST

Thermal Diode Connectors

Current Sense Calibration

FUNC_TEST

Other Func Test Points

RTC Battery Connector

FUNC_TEST

Camera Connector

FUNC_TEST

FUNC_TEST

Inverter Connector

Functional / ICT Test

SYNC_DATE=N/A

SYNC_MASTER=N/A

5 84

A.0.0051-7150

TRUE

GND_CHASSIS_INVERTER

INVERTER_PWM

TRUE

GND_INVERTER

TRUE

PP5V_INVERTER_SW

TRUE

PPBUS_S0_INVERTER

TRUE

=USB2_CAMERA_N
=USB2_CAMERA_P

=PP5V_S3_CAMERA

TRUE

GND

TRUE

PPVBATT_G3C_RTC

TRUE

LTALS_OUT

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

=PP1V05_S0_REG

TRUE

HSTHMSNS_DX_P

TRUE
TRUE

HSTHMSNS_DX_N
RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

TRUE

TRUE

ISENSE_CAL_EN
=PP5V_S0_ISENSECAL

TRUE

=PP1V8_S3_REG

TRUE

=PP1V5_S0_REG

TRUE
TRUE

PPVCORE_S0_GPU

TRUE

PPVCORE_S0_CPU

TRUE

GND

TRUE

SMC_TRST_L

FSB_LOCK_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HIT_L

TRUE

FSB_HITM_L

TRUE

FSB_DSTBP_L<3..0>

TRUE TRUE

TRUE

FSB_DSTBN_L<3..0>

TRUE

TRUE

FSB_DRDY_L

FSB_DINV_L<3..0>

TRUE TRUE

FSB_DBSY_L

TRUE

FSB_D_L<63..0>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

TRUE

FSB_ADSTB_L<1..0>

TRUE

TRUE

FSB_ADS_L

FSB_A_L<31..3>

TRUE

TRUE

CK410_XTAL_IN

P3V3S5_UG

TRUE

P3V3S5_FSET

TRUE

P3V3S5_ISEN

TRUE

P3V3S5_LG

TRUE

P3V3S5_FB_RC

TRUE

P3V3S5_COMP

TRUE

P3V3S5_COMP_R

TRUE

P3V3S5_FB

TRUE

P1V5S0_RUNSS

TRUE

P3V3S5_BOOT

TRUE

P3V3S5_BOOT_R

TRUE

P1V05S0_PHASE

TRUE

P1V05S0_LG

TRUE

P1V05S0_UG

TRUE

P1V05S0_ISEN

TRUE

P1V05S0_FB_RC

TRUE

P1V05S0_FB

TRUE

P1V05S0_FSET

TRUE

P1V05S0_COMP

TRUE

P1V05S0_BOOT_R

TRUE

P1V05S0_COMP_R

TRUE

P1V05S0_BOOT

TRUE

IMVP6_VDIFF

TRUE

IMVP6_OCSET

TRUE

IMVP6_VDIFF_RC

TRUE

IMVP6_DFB

TRUE

IMVP6_COMP_RC

TRUE

IMVP6_FB

TRUE

GPUVCORE_UG

TRUE

GPUVCORE_PHASE

TRUE

GPUVCORE_ISEN

TRUE

GPUVCORE_LG

TRUE

GPUBBN_FB

TRUE

GPUVCORE_FB

TRUE

GPUVCORE_FB_RC

TRUE

GPUBBP_ADJ

TRUE

TRUE

GPUVCORE_FSET

TRUE

GPUVCORE_COMP

TRUE

P3V42G3H_FB

TRUE

P1V05S0_COMP

TRUE

P1V05S0_FSET

TRUE

P3V3S5_FSET

TRUE

P3V3S5_COMP

TRUE

P1V2S3_RT

TRUE

P1V2S3_RUNSS

TRUE

SB_CLK100M_SATA_N

TRUE

SB_CLK100M_SATA_P

TRUE

DMI_N2S_N<1..0>

TRUE

DMI_N2S_P<1..0>

TRUE

EXCARD_CLKREQ_L

TRUE

=PPBUS_G3H_LIO_CONN

TRUE

GND

PCIE_WAKE_L

TRUE

=SMBUS_LIO_SB_SDA

TRUE

=SMBUS_LIO_SB_SCL

TRUE

=SMBUS_LIO_SMC_SDA

TRUE

PCIE_CLK100M_MINI_N

TRUE

=SMBUS_LIO_SMC_SCL

TRUE

PCIE_CLK100M_MINI_P

TRUE

=PCIE_MINI_D2R_N

TRUE

=PCIE_MINI_D2R_P

TRUE

=PCIE_MINI_R2D_P

TRUE

TRUE

=PCIE_MINI_R2D_N

TRUE

SYS_ONEWIRE

TRUE

LIO_P3V3S0_EN_L

TRUE

SMC_BATT_ISET

EXCARD_OC_L

TRUE

ACZ_RST_L

TRUE

LTUSB_OC_L

TRUE

TRUE

GND_BATT

TRUE

GND

ALS_GAIN

TRUE

=PP3V3_S3_LTALS

TRUE

TRUE

FWH_INIT_L

TRUE

PM_SUS_STAT_L

TRUE

SMC_TCK

TRUE

SMC_NMI

TRUE

SV_SET_UP

TRUE

=PCIE_EXCARD_R2D_N

TRUE

SMC_TDI

TRUE

INT_SERIRQ

TRUE

LPC_AD<2>

TRUE

PCI_CLK_PORT80_LPC

LPC_AD<3>

TRUE

=PP5V_S0_FAN_LT

TRUE

FAN_RT_PWM

TRUE

FAN_LT_TACH

TRUE

FAN_LT_PWM

TRUE

FAN_RT_TACH

TRUE

TRUE

PCIE_CLK100M_EXCARD_P

ACZ_BITCLK

TRUE

TRUE

SMC_TMS

TRUE

LPC_AD<0>

TRUE

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

BOOT_LPC_SPI_L

TRUE

DEBUG_RST_L

TRUE

=PP5V_S0_LPCPLUS

ACZ_SDATAIN<0>

TRUE

TRUE

LPC_AD<1>

TRUE

SMC_TX_L

TRUE

SMC_RST_L

TRUE

SMC_RX_L

GND_AUDIO

TRUE

GND_AUDIO_PWR

TRUE

TRUE

=PP3V42_G3H_LIO

TRUE

PP5V_S0_AUDIO_PWR

TRUE

SMC_MD1

SMC_TDO

TRUE

TRUE

SMC_SYS_ISET

TRUE

LIO_BATT_ISENSE

LIO_DCIN_ISENSE

TRUE
TRUE

LIO_P3V3S3_EN

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

MINI_CLKREQ_L

TRUE

SMC_EXCARD_CP

LIO_PLT_RESET_L

TRUE

TRUE

SMC_EXCARD_PWR_EN

TRUE

ACZ_SYNC

TRUE

=USB2_LT_P

TRUE

=USB2_LT_N

TRUE

=USB2_EXCARD_P

TRUE

=USB2_EXCARD_N

=PCIE_EXCARD_R2D_P

TRUE

=PCIE_EXCARD_D2R_P

TRUE

TRUE

SMC_ADAPTER_EN

TRUE

=SMBUS_BATT_SDA

TRUE

SMC_BS_ALRT_L

TRUE

=SMBUS_BATT_SCL

=PCIE_EXCARD_D2R_N

TRUE

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

PP5V_S0_AUDIO

=PP5V_S5_LIO

TRUE

TRUE

=PPDCIN_G3H_LIO

=PP1V5_S0_LIO

TRUE

TRUE

SMC_BC_ACOK

TRUE

SMC_BATT_CHG_EN

ACZ_SDATAOUT

TRUE

TRUE

=PP3V3_S5_LPCPLUS

IMVP6_RBIAS

TRUE

IMVP6_COMP

TRUE

P5VS5_RUNSS

TRUE

P1V5S0_RUNSS

TRUE

84D6 12D6

84D6

84D6

84D6

12C6

12B4

12B4

12B4

12B6

84D6

58C6

51B4

51B5

78C2

84D6

7C4

7C4

7C4

7C4

84C6

12D4

51B5

58C6

58C6

58C6

58C6

58C6

58C6

58C6

50B3

50B3

50A2

50C6

49B7

65D8

84D6

12B4

84D6

84D6

7C3

7C3

84D6

7C3

84D6

7C3

84D6

84D6

12C4

84D6

12C4

64C6

47C3

50B2

50B3

84B4

78C6

51C5

50A2

51B5

51B5

51B5

51C5

51C5

51C5

84B4

51B4

51C4

51C4

51C4

51B4 84B4

51C4

50B2

51B5

50B2

51B4

50A2

50A2

84B4

49D5

66B5

50A2

50A2

84B4

64C6

45C3

45B3

65B1

78C6

50B2

26C5

63A2

53A8

65A1

65B8

65C8

51B4

12B4

12A4

12B4

12B4

7B4

7B4

12B4

7B4

12B4

7B4

12C4

12C4

7D8

12C4

7D8

63D6

63C6

60C4

63B7

63A7

63A7

63B7

63D6

63C6

61B7

34C3

34C3

22D2

22D2

47C6

66C4

39C6

47C3

47C3

47C3

47C3

47C3

47C3

48C6

48C6

48C6

48C6

49B7

64C6

49B5

47C6

47B3

47C6

49B5

78C5

50D3

49C5

50B2

51B5

23C3

48C6

50B2

49C7

49C7

51C5

49C7

65A1

47B3

47B6

50B2

49D7

49C7

49C5

49C7

51B4

65A1

47B6

49D7

49C7

50D6

49C7

65D3

51B4

50B2

49B5

53C3

53C5

64A6

49D7

47C6

49B7

47C6

49B7

47B6

47C3

47C3

47C3

47C3

48C6

48C6

47C6

66B5

50B2

66B5

48B6

47B3

65B1

65A8

65C6

49C5

49D7

47B6

65D3

64A6

60C4

6A8

76A5

76A5

76B5

76B5

6C3

6D3

45C3 26D6

55C7

49C5

23C5

53A4

52C5

52C5

52D5

52C5

49B7

53A8

62C1

60C1

65D1

49C1

7D6

7D8

7D6

7D6

7B3

7B3

7D6

7B3

7D6

7B3

7D6

7D6

7C8

7D6

7C8

33C6

63D4

5D7

63C4

63C4

63C2

5D7

63C6

63C6

5D7

63D4

63D4

63B5

63A5

63B5

63A5

63A3

63A7

5D7

5D7

63B5

63A7

63B5

59C7

59C6

59B8

59B6

59B8

59B7

68D5

68C5

68C5

68C5

68A3

68C7

68C3

68B7

68C7

68C7

64C3

5C7

5B7

5B7

5B7

61B6

41C4

21B6

21B6

14B4

14B4

34A3

65C3

23C8

27B6

27B6

27D1

34D4

27D1

34D4

47C3

47C3

47B3

47B3

47C6

47B6

47B6

6C3

21C7

6D3

66B5

6D5

65C3

21C4

23C5

49C5

49C1

23B6

47B3

49B5

23C8

21D4

34D6

21D4

56C7

56B3

56B6

56B6

56B3

34C3

21C7

49B5

21D4

21C5

23C8

22B3

26B1

51C4

21C7

21D4

46B5

49C3

46B5

47A4

47A4

47D6

47D4

49C1

49B5

47C6

47C6

47B6

47B6

47B6

34A3

47B6

26C1

47B6

21C7

6D3

6D3

6C3

6C3

47B3

47B3

43B7

27C1

49C5

27C1

47B3

34B3

47C4

47C6

47C6

47D6

47B6

47C6

21C7

51C4

59C7

59B7

60C5

5B7

http://mycomp.su/x/

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Port "H" = Reserved

Frame holes

Left CPU TM Hole

Top CPU TM Hole

Right CPU TM Hole

Add 2 blind vias per hole per side to GND

Bottom Left GPU TM Hole

Top GPU Right TM Hole

Thermal Module Holes

"ENET_LOWPWR_EN" are mutually-exclusive.

Chassis connection to be made at the mounting hole east of the LVDS connector

USB Port "G" = Bluetooth (M13L)

USB Port "E" = ExpressCard

USB Port "F" = IR Receiver

USB Port "C" = Left USB 2.0 Port

NOTE: NB_CFG<13..12> require test access

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "D" = Camera

FireWire Aliases

RAM door (Torx) holes

Chassis GNDs

LVDS pulldown aliases

Ethernet Power Management Support

Inverter PWM Reset Alias

NOTE: BOM options "USB_G_OC_PU" and

HOLE-VIA-P5RP25

1

ZT0602

ENET_LOWPWR_EN

5%

1/16W

402

0

MF-LF

21

R0600

0.01UF

10%
50V
X7R
402

2

1

C0630

HOLE-VIA-P5RP25

1

ZT0630

0.01UF

10%
50V
X7R
402

2

1

C0631

HOLE-VIA-P5RP25

1

ZT0631

402

X7R

50V

10%

0.01UF

2

1

C0610

HOLE-VIA-P5RP25

1

ZT0610

0.01UF

10%
50V
X7R
402

2

1

C0611

HOLE-VIA-P5RP25

1

ZT0611

402

X7R

50V

10%

0.01UF

2

1

C0612

HOLE-VIA-P5RP25

1

ZT0612

402

X7R

50V

10%

0.01UF

2

1

C0602

402

X7R

50V

10%

0.01UF

2

1

C0600

HOLE-VIA-P5RP25

1

ZT0615

HOLE-VIA-P5RP25

1

ZT0614

HOLE-VIA-P5RP25

1

ZT0613

402

X7R

50V

10%

0.01UF

2

1

C0613

402

X7R

50V

10%

0.01UF

2

1

C0614

402

X7R

50V

10%

0.01UF

2

1

C0615

SHLD-SM-LF

OG-503040

3

2

1

SH0600

0

5%
1/16W
MF-LF
402

2

1

R0601

Signal Aliases/Misc Comps

6 84

A.0.0051-7150

SYNC_MASTER=N/A

SYNC_DATE=N/A

M59_INVERTER_PLT_RST_L

=INVERTER_PWM_PLT_RST_L

ENET_CTRL25

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ENET_CTRL25

=LVDS_PD_L_DATA_N<2>

LVDS_L_DATA_CONN_N<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<2>

LVDS_L_DATA_CONN_P<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_N<1>

LVDS_L_DATA_CONN_N<1>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<1>

LVDS_L_DATA_CONN_P<1>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_N<0>

LVDS_L_DATA_CONN_N<0>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<0>

LVDS_L_DATA_CONN_P<0>

MAKE_BASE=TRUE

=LVDS_PD_L_CLK_P

LVDS_L_CLK_CONN_P

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<2>

LVDS_U_DATA_CONN_N<2>

MAKE_BASE=TRUE

=LVDS_PD_L_CLK_N

LVDS_L_CLK_CONN_N

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<2>

LVDS_U_DATA_CONN_P<2>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<1>

LVDS_U_DATA_CONN_N<1>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<1>

LVDS_U_DATA_CONN_P<1>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<0>

LVDS_U_DATA_CONN_N<0>

MAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<0>

LVDS_U_DATA_CONN_P<0>

MAKE_BASE=TRUE

=LVDS_PD_U_CLK_P

MAKE_BASE=TRUE

LVDS_U_CLK_CONN_P

=LVDS_PD_U_CLK_N

MAKE_BASE=TRUE

LVDS_U_CLK_CONN_N

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_ENET

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_DVI_BOT

VOLTAGE=0V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_FW_PORT2U

=GND_CHASSIS_FW_PORT1

=GND_CHASSIS_ENET

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI3

GND_CHASSIS_DVI_TOP

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_DVI4

=GND_CHASSIS_DVI2

=GND_CHASSIS_FW_EMI_R

=GND_CHASSIS_RTUSB
=GND_CHASSIS_FW_PORT2L

GND_CHASSIS_RTUSB

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE

GND_CHASSIS_LIOFLEX_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_BATTCONN_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RAMDOOR_HOLE_0

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

=GND_CHASSIS_CAMERA

=PP3V3_FWPHY_CORE

TP_USB_H_N

MAKE_BASE=TRUE

TP_USB_H_N

USB_G_P

USB_G_N

USB_BT_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB_BT_P

=USB_BT_P

=USB_BT_N

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

GND_CHASSIS_LNDACARD_HOLE

VOLTAGE=0V

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RAMDOOR_HOLE_1

=PP1V95_FWPHY_CORE_LDO

PCI_REQ3_L

MAKE_BASE=TRUE

=FW_PCI_REQ_L

MAKE_BASE=TRUE

PCI_GNT3_L

=FW_PCI_GNT_L

MAKE_BASE=TRUE

PCI_AD<19>

=FW_PCI_IDSEL

MAKE_BASE=TRUE

SMC_RSTGATE_L

=SMC_FWRSTGATE_L

=PP1V8_FWPHY_OSC

=PP1V95_FWPHY

=PP3V3_FWPHY_REG

=PP3V3_FWLATEVG_ACTIVE

=PP3V3_FWPHY

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP1V95_FWPHY

VOLTAGE=1.95V

MAKE_BASE=TRUE

USB_F_N

USB_B_P

MAKE_BASE=TRUE

TP_NB_CFG<8>

LTUSB_OC_L

MAKE_BASE=TRUE

USB_F_P

=USB2_LT_N

=USB2_EXCARD_N

USB2_EXCARD_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_CAMERA_N

USB2_CAMERA_P

MAKE_BASE=TRUE

USB_E_N

USB_E_OC_L

USB_D_N

=USB2_LT_P

USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_P

MAKE_BASE=TRUE

=RTUSB_OC_L

MAKE_BASE=TRUE

RTUSB_OC_L

USB_C_N

USB_C_OC_L

USB_C_P

UNUSED_USB_B_OC_L

MAKE_BASE=TRUE

USB_B_OC_L

USB_B_N

USB_A_OC_L

USB_A_N

USB_A_P

=USB2_RT_N

=USB2_RT_P

MAKE_BASE=TRUE

USB2_RT_P

USB2_RT_N

MAKE_BASE=TRUE

NC_CPU_A32_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A33_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A34_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A35_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A37_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A38_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A39_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HFPLL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE0

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE1

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE4

MAKE_BASE=TRUE
NO_TEST=TRUE

TP_CPU_A32_L

TP_CPU_A33_L

TP_CPU_A34_L

TP_CPU_A37_L

TP_CPU_A36_L

TP_CPU_A38_L

TP_CPU_A39_L

TP_CPU_APM1_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE2

TP_CPU_SPARE1

TP_CPU_SPARE4

USB_D_P

=USB_TRACKPAD_P

MAKE_BASE=TRUE

USB2_LT_P

USB2_LT_N

MAKE_BASE=TRUE

NC_CPU_EXTBREF

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_HFPLL

NC_CPU_APM0_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_APM1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A36_L

NO_TEST=TRUE

MAKE_BASE=TRUE

=USB2_CAMERA_P

TP_CPU_APM0_L

MEM_A_A<15..14>

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_MEM_A_A<15..14>

MEM_B_A<15..14>

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_MEM_B_A<15..14>

NB_CFG<4..3>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<8>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<17>

NB_CFG<13..12>

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

SUS_CLK_SB

MAKE_BASE=TRUE

TP_SB_SUS_CLK

TP_SB_XOR_T5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_T5

TP_SB_XOR_V3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_V3

TP_SB_XOR_U5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_U5

TP_SB_XOR_W3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_W3

TP_SB_XOR_V4

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_XOR_V4

SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

=RTALS_GAIN

MAKE_BASE=TRUE

ALS_GAIN

ENET_CTRL12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_CTRL12

=USB_TRACKPAD_N

EXCARD_OC_L

MAKE_BASE=TRUE

=USB_IR_N

USB_IR_N

MAKE_BASE=TRUE

USB_E_P

USB_D_OC_L

MAKE_BASE=TRUE

USB_IR_P

=USB_IR_P

=USB2_EXCARD_P

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD3
=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD2

=GND_CHASSIS_LCD1

UNUSED_USB_D_OC_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_EXCARD_N

=USB2_CAMERA_N

TP_CPU_A35_L

ENET_LOWPWR_EN

SB_GPIO30

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

GND_CHASSIS_DIMM_NOTCH

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

GND_CHASSIS_RIGHT_FAN_NOTCH

GND_CHASSIS_RIGHT_FAN_HOLE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP3V3_FWLATEVG

MIN_LINE_WIDTH=0.38 mm
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_FWPHY

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

TP_USB_H_P

MAKE_BASE=TRUE

TP_USB_H_P

79C1

79C1

79C1

79C1

79C1

79C1

79C1

79D1

79C1

79C1

79C1

79C1

79D1

79D1

79C1

79C1

78C6

50B3

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

45C5

22C2 22C2

26D2

37C6

49D7

44B8

47C6

47C3

47C3

22D8

47C3

22D8

22D8

22D8

45B3

49D7

49B5

47C6

22D8

47C3

45C3

22D8

22C2 22C2

26C1 76A8

39C8

79C8 76C2

79C8 76C2

79C8 76C2

79D8 76C2

79D8 76C2

79D8 76C2

79C8 76C2

79B8 76C2

79C8 76C2

79B8 76B2

79B8 76C2

79B8 76C2

79C8 76C2

79C8 76C2

79B8 76B2

79B8 76B2

44A1

44C1

40B2

77A2

77B5

77A2

77A3

77A5

44A3

46B2

44A1

45B5

42C4

6C1 6C2

22C2

22C2

78C2

78C2

42C1

22B6 37D3

22B6 37D3

22A7

37B7

6D4

37A8

38B2

38D5

42C4

43A7

38D7

22C2

22C2

5C1

22C2

5B1

5B1

22C2

22C4

22C2

5B1

46C5

22C2

22C4

22C2

22C4

22C2

22C4

22C2

22C2

46B5

46B5

7C8

7B8

7B8

7B8

7B8

7B8

7B8

7B8

7B6

7B6

7B6

7B6

7B6

22C2

78C3

7B8

5A4

7B8

28C3

29C3

14C6

14C6

14C6

14C6

14C6

14C6

14C6

23C3

21C6

21C6

21C6

21C6

21C6

6B7

55C4

5B2

39C8

78C3

5C1

78B4

22C2

22C4

78B4

5B1

76A6

76C3

76B2

76D3

76D2

5A4

7B8

39B8 22C4

44A8

5A4

6C1 6C2

http://mycomp.su/x/

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IN

IN

IN

IN
IN

IN

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

OUT

OUT

OUT

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO

IO
IO

IO

IO
IO

IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN
IN

IN

IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

A7*

RSVD14
RSVD15

BCLK1

BCLK0

RSVD20

RSVD17
RSVD18
RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1*
BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6
RSVD7
RSVD8

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

RSVD9
RSVD10

SMI*

LINT0
LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30*
A31*

A27*
A28*
A29*

A26*

A25*

A24*

A22*
A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14*
A15*
A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2
COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52*
D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45*
D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0
BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26*
D27*
D28*

D24*
D25*

D23*

D21*
D22*

D20*

D19*

D18*

D16*
D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF
NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU IS HOT

AND CPU VR TO INFORM

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

LAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TO

PM_THRMTRIP#

STUB)

SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND

0.1" AWAY

1/16W
402

MF-LF

54.9

1%

2

1

R0702

MF-LF
402

5%
1/16W

68

2

1

R0704

1/16W

1%

402

MF-LF

1K

2

1

R0705

1/16W

1%

402

MF-LF

2.0K

2

1

R0706

54.9

402

1%

21

R0719

27.4

21

R0718

54.9

4021%

21

R0717

402

27.4

21

R0716

0

402

NOSTUFF

21

R0730

NOSTUFF

1K

MF-LF
402

5%
1/16W

2

1

R0707

MF-LF
402

5%
1/16W

51

2

1

R0712

54.9

1%
1/16W
MF-LF
402

2

1

R0703

54.9

402

1%

21

R0720

1%

402

54.9

21

R0721

54.9

402

1%

21

R0722

BGA

YONAH

CPU

OMIT

AB6

G2

AB5

C7

A25

A24

AB3

AA6

AC5

D5

A3

B2

V3

T2

N5

M4

AA3

AB2

C24

AA4

C23

D22

AF1

C1

D3

F6

D2

T22

B25

C3

AA1

G3

F4

F3

B1

L5

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V4

L2

H1

J1

N2

M1

K5

M3

L4

Y1

W2

J4

Y4

W5

W3

T3

T5

R4

U2

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L1

P2

P5

N3

U0700

CPU

YONAH

BGA

OMIT

D25

C26

D7

D6

AE6

A2

AD26

AE24

Y25

N25

G22

AD23

W24

M24

H23

D24

B5

E5

AC20

V23

M26

J26

G24

K24

E23

AF26

AF22

AF25

AE25

E25

AD21

AE21

AD24

AF23

AE22

AD20

AC25

AB21

AA21

AB22

G25

AC23

AC22

AA24

AC26

Y22

Y26

AA26

Y23

W22

AB25

F23

U22

U25

U23

W25

V26

V24

AB24

AA23

N24

T25

H22

L26

R24

T24

P23

P22

P25

M23

L23

L22

L25

E26

R23

P26

K25

N22

H25

K22

F26

H26

J23

J24

F24

E22

V1

U1

U26

R26

C21

B23

B22

U0700

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

84

051-7150 A.0.0

7

CPU 1 OF 2-FSB

FSB_BPRI_L

FSB_BNR_L

FSB_ADS_L

CPU_PSI_L

FSB_SLPCPU_L

CPU_PWRGD

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L

CPU_COMP<2>
CPU_COMP<3>

CPU_COMP<1>

CPU_COMP<0>

FSB_DSTBP_L<3>

FSB_DSTBN_L<3>

FSB_DINV_L<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<52>
FSB_D_L<53>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTBN_L<2>

FSB_D_L<47>

FSB_DSTBP_L<2>

FSB_D_L<45>
FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

CPU_BSEL<2>

FSB_DSTBN_L<1>

CPU_BSEL<0>
CPU_BSEL<1>

CPU_TEST2

CPU_TEST1

FSB_DINV_L<1>

FSB_DSTBP_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>

FSB_D_L<24>
FSB_D_L<25>

FSB_D_L<23>

FSB_D_L<21>
FSB_D_L<22>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<16>
FSB_D_L<17>

FSB_DINV_L<0>

FSB_DSTBP_L<0>

FSB_DSTBN_L<0>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

CPU_GTLREF

FSB_A_L<7>

TP_CPU_SPARE1
TP_CPU_SPARE2

FSB_CLK_CPU_N

FSB_CLK_CPU_P

TP_CPU_SPARE7

TP_CPU_SPARE4
TP_CPU_SPARE5
TP_CPU_SPARE6

TP_CPU_SPARE3

TP_CPU_SPARE0

TP_CPU_EXTBREF

PM_THRMTRIP_L

CPU_THERMD_N

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<0>

FSB_CPURST_L

FSB_LOCK_L

CPU_INIT_L

FSB_IERR_L

FSB_BREQ0_L

FSB_DRDY_L

FSB_DEFER_L

TP_CPU_HFPLL

TP_CPU_A37_L
TP_CPU_A38_L
TP_CPU_A39_L

TP_CPU_A32_L
TP_CPU_A33_L
TP_CPU_A34_L
TP_CPU_A35_L
TP_CPU_A36_L

TP_CPU_APM0_L
TP_CPU_APM1_L

CPU_SMI_L

CPU_INTR
CPU_NMI

CPU_STPCLK_L

CPU_IGNNE_L

CPU_FERR_L

CPU_A20M_L

FSB_ADSTB_L<1>

FSB_A_L<30>
FSB_A_L<31>

FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<22>
FSB_A_L<23>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_REQ_L<2>

FSB_ADSTB_L<0>

FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

XDP_TCK

XDP_TDI

XDP_TMS

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

FSB_DBSY_L

XDP_BPM_L<1>

=PP1V05_S0_CPU

FSB_TRDY_L

FSB_RS_L<2>

FSB_HIT_L
FSB_HITM_L

XDP_BPM_L<5>

FSB_RS_L<1>

FSB_RS_L<0>

65D6

65D6

11C5

65D6

65D6

11C5

11B3

11C5

11C5

11B3

9B7

11B3

11B3

9B7

8C7

9B7

9B7

8C7

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

50C1

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

7D5

8C7

8C7

84D6

7D5

84D6

84D6

84D6

12C4

12C4

84C6

59C7

84C6

84D6

12B4

12B4

12B4

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B4

12B4

12B6

12B4

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D4

21C2

50D3

26C6

11B3

11B3

11B3

84C6

84C6

84C6

84C6

12C4

12B4

84C6

12C4

12B4

84D6

84C6

84C6

84C6

84C6

84C6

84C6

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12A4

12A4

12B4

12B4

12A4

12C4

12D4

12D4

12C4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

11B3

11B3

11B3

7B6

7D5

7D5

12B4

84C6

7B6

84D6

84D6

12B4

12B4

84C6

84D6

84D6

12C4

5D5

5D5

59C7

12A4

21C4

21C4

21C4

12B4

84C6

84C6

84C6

84C6

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

34B6

5D5

34C6

34B6

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

84C6

5D5

6C7

6C7

34D3

34D3

6C7

6C7

6C7

14B6

10B6

10B6

50C1

11B4

11B3

7B8

11B5

7B8

7A8

11B3

11B3

11B3

11B3

11B5

5D5

21C4

84C6

5D5

5D5

12B4

6C7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6C7

21C4

21C4

21C4

21C4

21C4

21C2

21C4

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

7C6

7C6

7C6

7B5

7B6

7B5

5D5

11B3

7B5

12A4

12A4

5D5

5D5

11B3

12A4

12A4

http://mycomp.su/x/

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VSS_82
VSS_83
VSS_84
VSS_85

VSS_87

VSS_86

VSS_88
VSS_89
VSS_90

VSS_92

VSS_91

VSS_93
VSS_94
VSS_95

VSS_97

VSS_96

VSS_100

VSS_98
VSS_99

VSS_102

VSS_101

VSS_105

VSS_103
VSS_104

VSS_106
VSS_107

VSS_110

VSS_109

VSS_108

VSS_111
VSS_112

VSS_115

VSS_114

VSS_113

VSS_116
VSS_117
VSS_118

VSS_120

VSS_119

VSS_123

VSS_121
VSS_122

VSS_124
VSS_125

VSS_128

VSS_126
VSS_127

VSS_129
VSS_130

VSS_133

VSS_131
VSS_132

VSS_134
VSS_135

VSS_138

VSS_136
VSS_137

VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_146

VSS_144
VSS_145

VSS_147
VSS_148

VSS_151

VSS_150

VSS_149

VSS_152
VSS_153

VSS_156

VSS_155

VSS_154

VSS_157
VSS_158
VSS_159

VSS_161

VSS_160

VSS_162

VSS_1
VSS_2
VSS_3

VSS_5

VSS_4

VSS_6
VSS_7
VSS_8

VSS_10

VSS_9

VSS_11
VSS_12

VSS_15

VSS_13
VSS_14

VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

VSS_23

VSS_22

VSS_21

VSS_24
VSS_25

VSS_28

VSS_27

VSS_26

VSS_29
VSS_30

VSS_33

VSS_32

VSS_31

VSS_34
VSS_35

VSS_38

VSS_37

VSS_36

VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

VSS_46

VSS_44
VSS_45

VSS_47
VSS_48

VSS_51

VSS_49
VSS_50

VSS_52
VSS_53

VSS_56

VSS_54
VSS_55

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

VSS_63

VSS_62

VSS_64
VSS_65
VSS_66

VSS_69

VSS_68

VSS_67

VSS_70
VSS_71

VSS_74

VSS_73

VSS_72

VSS_75
VSS_76

VSS_79

VSS_78

VSS_77

VSS_80
VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59
VCC_60

VCC_58

VCC_57

VCC_56

VCC_54
VCC_55

VCC_53

VCC_51
VCC_52

VCC_49
VCC_50

VCC_48

VCC_47

VCC_46

VCC_44
VCC_45

VCC_43

VCC_41
VCC_42

VCC_40

VCC_39

VCC_38

VCC_36
VCC_37

VCC_33

VCC_35

VCC_34

VCC_31
VCC_32

VCC_29
VCC_30

VCC_28

VCC_26
VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18
VCC_19

VCC_17

VCC_16

VCC_15

VCC_13
VCC_14

VCC_12

VCC_10
VCC_11

VCC_8
VCC_9

VCC_7

VCC_6

VCC_5

VCC_3
VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82
VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90
VCC_91
VCC_92

VCC_94

VCC_93

VCC_95
VCC_96
VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12
VCCP_13
VCCP_14

VCCP_16

VCCP_15

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTH

VCCSENSE AND VSSSENSE LINES

LAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE

VID FOR CPU POWER SUPPLY
IF NO USE, NEED PULL-UP OR
PULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

84B6

9C2

1/16W

1%

402

MF-LF

100

2

1

R0803

84B6

9C2

84B6 59A1

84B6 59B1

100

MF-LF
402

1%
1/16W

2

1

R0802

OMIT

BGA

YONAH

CPU

V22

V5

V2

U24

U21

U6

U3

T26

T23

T4B6

T1

R25

R22

R5

R2

P24

P21

P6

P3

N26

A26

N23

N4

N1

M25

M22

M5

M2

L24

L21

L6

A23

L3

K26

K23

K4

K1

J25

J22

J5

J2

H24

A19

H21

H6

H3

G26

G23

G1

G4

F25

F22

F2

A16

F19

F16

F13

F11

F8

F5

E24

E21

E19

E16

A14

E14

E11

E8

E6

E3

D26

D23

D19

D16

D13

A11

D11

D8

D4

D1

C25

C22

C2

C19

C16

C14

A8

C11

C8

C5

AF24

AF21

AF19

B24

AF16

AF13

AF11

AF8

AF6

AF3

AE26

AE23

AE19

AE16

B21

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

AD13

B19

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

AC11

B16

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

AB8

B13

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

AA5

B11

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

V25

B8

A4

U0700

OMIT

BGA

YONAH

CPU

AE7

AE2

AF2

AE3

AF4

AE5

AF5

AD6

AF7

N21

M21

K21

J21

M6

K6

J6

G21

W21

V21

T6

T21

R6

R21

N6

V6

B26

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

AE17

A20

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

AD12

A18

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

AC7

A17

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

AB9

A15

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

F20

A13

F18

F17

F15

F14

F12

F10

F9

F7

E20

E18

A12

E17

E15

E13

E12

E10

E9

E7

D18

D17

D15

A10

D14

D12

D10

D9

C18

C17

C15

C13

C12

C10

A9

C9

B20

B18

B17

B15

B14

B12

B10

B9

AF20

B7

A7

U0700

CPU 2 OF 2-PWR/GND

051-7150 A.0.0

8 84

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

65D6 11C5

65D1

11B3

65D1

53D7

9B7

53D7

53A6

7D5

53A6

9D7

7B6

65C6

9D7

8B5

7B5

9B7

8D7

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4x 330uF. 20x 22uF 0805

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

Resistors to allow for override of CPU VID
Will probably be removed before production

VCCP (CPU I/O) Decoupling

CPU VCORE HF AND BULK DECOUPLING

NOTE: This cap is shared

NCNC

CPU VCORE VID Connections

6.3V

20%
CERM

805

22UF

2

1

C0906

6.3V

20%
CERM

22UF

805

2

1

C0904

6.3V

20%
CERM

22UF

805

2

1

C0916

6.3V

20%
CERM

22UF

805

2

1

C0914

6.3V

20%
CERM

22UF

805

2

1

C0908

6.3V

20%
CERM

22UF

805

2

1

C0903

6.3V

20%
CERM

22UF

805

2

1

C0907

6.3V

20%
CERM

22UF

805

2

1

C0902

6.3V

20%
CERM

805

22UF

2

1

C0901

6.3V

20%
CERM

805

22UF

2

1

C0913

6.3V

20%
CERM

22UF

805

2

1

C0912

6.3V

20%
CERM

22UF

805

2

1

C0911

6.3V

20%
CERM

22UF

805

2

1

C0919

6.3V

20%
CERM

22UF

805

2

1

C0900

6.3V

20%
CERM

22UF

805

2

1

C0910

0.1UF

CERM
402

20%
10V

2

1

C0936

470uF

CRITICAL

D2T

TANT

2.5V

20%

32

1

C0935

6.3V

20%
CERM

22UF

805

2

1

C0905

6.3V

20%
CERM

22UF

805

2

1

C0909

20%
CERM

22UF

6.3V

805

2

1

C0915

6.3V

20%
CERM

22UF

805

2

1

C0917

0.1UF

CERM
402

20%
10V

2

1

C0937

0.1UF

CERM
402

20%
10V

2

1

C0938

0.1UF

CERM
402

20%
10V

2

1

C0939

0.1UF

CERM
402

20%
10V

2

1

C0940

0.1UF

CERM
402

20%
10V

2

1

C0941

22UF

CERM

20%

6.3V

805

2

1

C0918

16V

0.01UF

CERM
402

20%

2

1

C0981

X5R

10uF

20%

6.3V

603

2

1

C0980

SM-LF

1/16W

5%

0

5

6

7

8

4

3

2

1

RP0990

SM-LF

1/16W

5%

0

5

6

7

8

4

3

2

1

RP0991

330UF

20%

2.5V
POLY
D2T

CRITICAL

3 2

1

C0950

CRITICAL

D2T

POLY

2.5V

20%

330UF

3 2

1

C0952

330UF

20%

2.5V
POLY
D2T

CRITICAL

3 2

1

C0953

CRITICAL

D2T

POLY

2.5V

20%

330UF

3 2

1

C0954

CPU Decoupling & VID

051-7150

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

A.0.0

9 84

IMVP6_VID<6>

IMVP6_VID<5>

IMVP6_VID<4>

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

IMVP6_VID<3>

IMVP6_VID<2>

IMVP6_VID<1>

IMVP6_VID<0>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

65D6 11C5 11B3

65D1

8C7

53D7

7D5

53A6

84B6

84B6

84B6

84B6

84B6

84B6

84B6

7B6

65C6

8D7

59C7

59C7

59C7

8B7

8B7

8B7

59C7

59C7

59C7

59C7

8B7

8B7

8B7

8B7

7B5

8B7

8B5

http://mycomp.su/x/

IO

IO

IN

OUT

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+
D-

THM2*

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE U1001 NEAR THE U1200

CPU ZONE THERMAL SENSOR

ADD GND GUARD TRACE

FOR CPU_THERMD_P AND
CPU_THERMD_N

LAYOUT NOTE:

10 MIL SPACING

LAYOUT NOTE:

10 MIL TRACE

LAYER.

CPU_THERMD_N ON SAME

ROUTE CPU_THERMD_P AND

(TO CPU INTERNAL THERMAL DIODE)

(TC0D)

0.001UF

10%

402

CERM

50V

2

1

C1001

0.1UF

X5R

16V

10%

402

2

1

C1002

CRITICAL

TMP401

MSOP

1

4

7

8

5

2
3

6

U1001

MF-LF
402

1/16W

5%

10K

2

1

R1005

1/16W

5%

402

10K

MF-LF

2

1

R1006

499

1%
1/16W
MF-LF

402

21

R1001

499

402

MF-LF

1/16W

1%

21

R1002

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7150 A.0.0

10 84

CPU MISC1-TEMP SENSOR

THRM_ALERT_L

THRM_ALERT

SMB_THRM_CLK

SMB_THRM_DATA

THRM_CPU_DX_N

CPU_THERMD_N

THRM_CPU_DX_P

CPU_THERMD_P

=PP3V3_S0_THRM_SNR

27D1

27D1

7C6

7C6

65B3

http://mycomp.su/x/

OUT
OUT

OUT

OUT

OUT

IN

IN
IN

IO

IO

IO

IO

IO

IO

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

and to provide better feeding of the 1.5V NB rail through its current sense resistor

Note: This connection to 1V5_S0 is to steal this mounting pad to add to the 1.5V S0 shape

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

NC

NC

(DBA#)

(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

MF-LF

22.6

1%

1/16W

402

ITP

21

R1100

ITP

402

1%

22.6

1/16W
MF-LF

21

R1102

54.9

1/16W

1%

402

MF-LF

ITP

2

1

R1103

402

X5R

16V

10%

0.1UF

2

1

C1100

1/16W

240

402

MF-LF

5%

2

1

R1104

F-RT-SM

52435-2872

CRITICAL

ITPCONN

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J1101

1/16W
402

54.9

1%
MF-LF

2

1

R1101

MF-LF

680

402

5%
1/16W

2

1

R1106

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

CPU ITP700FLEX DEBUG

051-7150 A.0.0

11 84

=PP1V05_S0_CPU

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

=PP3V3_S5_SB_PM

=PP1V05_S0_CPU

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

=PP1V5_S0_ITPMOUNT

65D6

65D6

11C5

11B3

9B7

9B7

8C7

8C7

7D5

84D6

11B3

65D3

7D5

11B3

7B6

12C4

84C6

7C6

7C6

26C5

7B6

7C6

84C6

84C6

84C6

84C6

84C6

84C6

7C6

84C6

26C6

7B5

7D6

7C6

7A8

7B8

7C6

23D1

7B5

7B8

34D3

7C6

7C6

7C6

7C6

7C6

7C6

7A8

34D3

7C6

84C6

65C6

http://mycomp.su/x/

IO

IO
IO

OUT

OUT

OUT

IO

IO

IO

IO
IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

OUT

IO

OUT

OUT

OUT

OUT

IO
IO

IO
IO

IO

IN

IO

IN

IO

IO

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM*
HLOCK*

HHIT*

HDSTBP2*
HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1*
HDSTBN2*

HDSTBN0*

HDINV2*
HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP
HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10*
HD11*
HD12*
HD13*
HD14*

HD5*

HD7*
HD8*
HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21*
HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10*
HA11*
HA12*

HADSTB1*

HREQ0*
HREQ1*
HREQ2*
HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

402

X5R

16V

10%

0.1uF

2

1

C1211

200

1%
1/16W
MF-LF
402

2

1

R1211

100

1%
1/16W
MF-LF
402

2

1

R1210

54.9

1%
1/16W
MF-LF

402

2

1

R1220

402

MF-LF

1/16W

1%

24.9

2

1

R1221

221

1%
1/16W
MF-LF
402

2

1

R1225

1%
1/16W
MF-LF
402

100

2

1

R1226

0.1uF

402

X5R

16V

10%

2

1

C1226

402

X5R

16V

10%

0.1uF

2

1

C1236

221

1%
1/16W
MF-LF
402

2

1

R1235

54.9

1%
1/16W
MF-LF

402

2

1

R1230

1%
1/16W
MF-LF
402

100

2

1

R1236

402

MF-LF

1/16W

1%

24.9

2

1

R1231

BGA

NB

945GM

OMIT

W1

U1

Y1

E4

E2

E1

E7

E3

D6

E6

B4

A8

F8

B8

G8

D8

B3

D4

D3

K13

AC5

AA5

T6

K3

AC4

Y5

T7

K4

H8

J9

AB10

U3

W8

J7

C3

A7

K1

K9

G2

AC8

AD4

AD10

AB5

G1

AC6

AD7

AC1

AD9

AD1

AC2

AB3

AC11

AB11

AC9

K2

AB4

AA1

Y8

AA10

AA6

AA2

AA7

AA4

W2

AB8

H3

Y10

W5

Y7

Y3

W3

W4

AA9

AB7

T5

W6

J6

T9

U5

W7

T4

T8

T1

W9

T11

U11

U9

H1

U7

T3

W11

T10

G4

K11

J3

H4

J8

K7

J1

F1

B7

AG1

AG2

C7

F6

C6

J13

C13

B9

E8

F9

G12

F11

G11

E11

C9

D14

C14

H9

A14

C12

B14

B12

F12

G13

E13

A13

A12

C11

A11

D12

F14

J15

H13

J14

D9

G14

J12

H11

U1200

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB CPU Interface

A.0.0

12 84

051-7150

FSB_D_L<17>

FSB_DSTBN_L<2>
FSB_DSTBN_L<3>

FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>

FSB_DINV_L<0>

FSB_DSTBN_L<0>

FSB_DINV_L<1>
FSB_DINV_L<2>

NB_FSB_VREF

FSB_D_L<1>
FSB_D_L<2>

FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<3>

FSB_D_L<0>

FSB_D_L<16>

FSB_TRDY_L

FSB_SLPCPU_L

FSB_RS_L<1>

FSB_RS_L<0>

FSB_HITM_L
FSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L<0>

FSB_DSTBN_L<1>

FSB_DINV_L<3>

FSB_DRDY_L

FSB_DPWR_L

FSB_DEFER_L

FSB_DBSY_L

FSB_CPURST_L

FSB_BREQ0_L

FSB_BPRI_L

FSB_BNR_L

FSB_CLK_NB_N

FSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMP
NB_FSB_YSCOMP

NB_FSB_XSWING

NB_FSB_XSCOMP

FSB_A_L<13>

FSB_ADS_L
FSB_ADSTB_L<0>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<15>

FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<31>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<21>
FSB_A_L<22>

FSB_A_L<17>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>

FSB_ADSTB_L<1>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>

FSB_D_L<30>

FSB_REQ_L<4>

FSB_RS_L<2>

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

65D6

65D6

65D6

34C8

34C8

34C8

34C6

34C6

34C6

34B8

34B8

34B8

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

19D7

19D7

19D7

7C4

7C3

7B3

7B4

7C3

7B3

7C4

7C4

7B4

7C3

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7D6

7D6

7D6

7C4

7B4

7B3

84D6

7D8

7D6

7D8

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7C4

7C4

7C4

7C4

7C4

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7D8

7D8

7D8

7C8

7C8

7C8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7C8

7D8

7D8

7D8

7D8

7B4

7D8

12C2

12C2

12B7

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

7A3

5D5

5D5

5D5

5D5

5D5

5D5

7B3

34D3

34D3

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

12A7

12B7

12A7

http://mycomp.su/x/

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF
TV_IRTNA

TV_DACB_OUT
TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK
L_DDC_DATA

EXP_A_COMPI
EXP_A_COMPO

EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8

EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11
EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9
EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15

L_CLKCTLB

L_BKLTEN
L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT
OUT

OUT
OUT

IN
IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN

IO
IO

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IO
IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#
SDVO_INT#

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

OMIT

945GM

NB

BGA

B19

B18

B16

J20

A19

C18

A16

F29

F28

D30

D29

G30

F30

E27

E26

A37

A36

B35

B34

C37

B37

A33

A32

C32

C33

F32

C35

B38

G25

G26

H29

H30

J30

D32

G23

R40

P36

N40

M36

L40

J36

H40

G36

AB40

AA36

Y40

W36

V40

T36

F40

D36

T40

R36

P40

N36

M40

L36

J40

H36

AC40

AB36

AA40

Y36

W40

V36

G40

F36

R38

P34

N38

M34

L38

J34

H38

G34

AB38

AA34

Y38

W34

V38

T34

F38

D34

T38

R34

P38

N34

M38

L34

J38

H34

AC38

AB34

AA38

Y34

W38

V34

G38

F34

D38

D40

H23

B21

A21

J22

B22

C22

C25

C26

D23

E23

U1200

24.9

1%
1/16W
MF-LF
402

2

1

R1310

NB PEG / Video Interfaces

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

13 84

A.0.0051-7150

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK
LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11>
PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

LVDS_BKLTEN
LVDS_CLKCTLA

LVDS_BKLTCTL

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

65C6

19D5

19D5

19D5

19D5

19D5

19C5

19C5

67C1

67C1

67B1

19D5

19D5

19D5

19D5

19D5

19D5

19D5

19D5

19D5

79C3

79C3

79D3

79D3

79C3

79D3

79D3

79D3

79D3

79D3

79D3

79D3

79C3

79C3

79D3

79D3

79A4

19D3

19D3

19D3

79A7

79A7

67D1

67D1

67D1

67D1

67C1

67C1

67C1

67C1

67B1

67B1

67B1

67B1

67B1

67D1

67D1

67D1

67D1

67D1

67C1

67C1

67C1

67C1

67C1

67C1

67B1

67B1

67B1

67B1

67B1

67D5

67D5

67D5

67D5

67C5

67C5

67C5

67C5

67C5

67C5

67B5

67B5

67B5

67B5

67B5

67B5

67D5

67D5

67D5

67D5

67D5

67C5

67C5

67C5

67C5

67C5

67B5

67B5

67B5

67B5

67B5

67B5

79A4

19D3

79A4

19D7

19D3

19D5

19D5

http://mycomp.su/x/

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2
RSVD3

RSVD6

RSVD4
RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10
RSVD11
RSVD12
RSVD13

CFG1

CFG0

CFG2
CFG3
CFG4

CFG6

CFG5

CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14

CFG17

CFG16

CFG15

CFG18
CFG19
CFG20

PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*

SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*

NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC0
NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0
SM_CK1
SM_CK2

SM_CK0*

SM_CK3

SM_CK1*
SM_CK2*
SM_CK3*

SM_CKE0
SM_CKE1

SM_CKE3

SM_CS1*
SM_CS2*
SM_CS3*

SMOCDCOMP0
SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0
SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IO
IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

IN

IN

IN
IN

IN

IN
IN

IN

IN
IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC

NC

IPU

IPU

NC
NC

IPU
IPU
IPU
IPU

IPU
IPU
IPU

IPU

IPU

IPU

IPU

IPU

IPD

IPU

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC

(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)

(H_PLLMON1#)

(H_PLLMON1)

(TV_DCONSEL1)

(TV_DCONSEL0)

(TESTIN#)

(H_PROCHOT#)

(D_PLLMON1)

(H_EDRDY#)

(LB_DATAP3)

(LB_DATAN3)

(LA_DATAP3)

(LA_DATAN3)

IPD

IPD

NC

NC

OMIT

945GM

NB

BGA

AK41

AK1

AV9

AT9

AF10

AL20

AU21

AY20

BA12

BA13

AW21

AY21

AW12

AW13

AY29

BA29

AT20

AU20

AY40

AW40

AY7

AW7

AT1

AR1

AW35

AY35

H27

H28

K30

J19

H7

AF11

AG11

F7

F3

R32

D27

D28

A34

A35

A41

J29

T32

AH34

AH33

G6

H26

F25

G28

B41

BA1

BA2

BA3

BA39

BA40

BA41

C1

A3

A39

A4

A40

AW1

AW41

AY1

AY41

B2

C41

D1

K28

AF33
AG33

AG41

AF37

AE41

AC37

AH41

AG37

AF41

AE37

AG39

AF35

AE39

AC35

AH39

AG35

AF39

AE35

C40

D41

A27

A26

H32

G16

D16

D19

E18

F15

E15

F18

J26

J18

K27

J25

H15

G18

H16

C15

K15

G15

D15

E16

K18

K16

U1200

100

5%
1/16W
MF-LF

402

21

R1430

1/16W
MF-LF

5%

402

10K

2

1

R1441

MF-LF

1/16W

5%

402

10K

2

1

R1440

20%
10V
CERM
402

0.1uF

2

1

C1416

20%
10V

CERM

402

0.1uF

2

1

C1415

80.6

MF-LF
402

1%
1/16W

2

1

R1410

80.6

MF-LF
402

1%
1/16W

2

1

R1411

10K

MF-LF

402

5%

1/16W

2

1

R1420

14 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB Misc Interfaces

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P

=PP3V3_S0_NB

NB_TV_DCONSEL1

NB_TV_DCONSEL0

TP_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

NB_RST_IN_L

DMI_N2S_P<3>

DMI_N2S_P<1>
DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_CLK_N<3>

MEM_CLK_N<2>

MEM_CLK_N<1>

MEM_CLK_P<3>

MEM_CLK_N<0>

MEM_CLK_P<2>

MEM_CLK_P<1>

MEM_CLK_P<0>

NB_SB_SYNC_L

SDVO_CTRLDATA

SDVO_CTRLCLK

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>

NB_CFG<19>

NB_CFG<15>
NB_CFG<16>
NB_CFG<17>

NB_CFG<14>

NB_CFG<10>

NB_CFG<9>

NB_CFG<7>

NB_CFG<5>
NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

NB_BSEL<2>

NB_BSEL<0>
NB_BSEL<1>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>

MEM_ODT<1>

MEM_CS_L<3>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CKE<2>

=PP1V8_S3_MEM_NB

MEM_RCOMP_L
MEM_RCOMP

MEM_VREF_NB_0
MEM_VREF_NB_1

TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

65B3

65B3

20B4

20B4

20A4

84C6

20A4

50C1

65B6

50D5

34B4

34B4

19C7

59C8

19C7

30C6

30C6

30D6

30D6

30D6

59C7

21C2

30D6

30C6

30C6

30D6

30D6

30D6

30D6

19D7

49B7

33B4

34B2

34B2

34B4

34B4

14C7

19D3

23C3

14D6

20B5

6C6

6D6

6D6

26C1

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

34C4

34C4

29B6

28B3

29C3

28C3

28C6

29D3

29A3

28A3

29D3

28D3

29A3

28A3

28D3

22A6

19D3

19D3

26B5

7C6

23C5

20A5

20B5

6D6

20C5

6D6

6D6

6D6

20B7

20C7

20C7

6D6

6D6

6D6

34B7

34C7

34B7

28B3

6C6

29B3

28B6

29B6

29B3

28B6

29C6

16B6

32B3

32B3

19D3

19D3

19D3

http://mycomp.su/x/

SA_DQ1

SA_DQ0

SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0
SA_DM1
SA_DM2
SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6
SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA1

SA_MA0

SA_MA2
SA_MA3

SA_MA5

SA_MA4

SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO
IO

IO
IO

IO

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

IO
IO

IO

IO

IO
IO

IO
IO

IO IO

IO
IO

IO

IO
IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

SB_DQ1

SB_DQ0

SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0
SB_DM1
SB_DM2
SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6
SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

SB_MA1

SB_MA0

SB_MA2
SB_MA3

SB_MA5

SB_MA4

SB_MA6
SB_MA7

SB_MA9

SB_MA8

SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO
IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

IO

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC

NC

NC

OMIT

NB

945GM

BGA

AY14

AK24

AK23

AW14

AT16

AW17

AU17

AV17

AU16

BA17

BA16

AW16

AV12

AV20

AT17

AU13

AU14

AY16

AH5

AG5

AN3

AP3

AL8

AN8

AM12

AN12

AM21

AM22

AN27

AN28

AU33

AT33

AK32

AK33

AP33

AN35

AH31

AF8

AF4

AH6

AG9

AJ32

AF6

AG4

AF9

AG7

AL2

AN1

AT3

AV2

AN2

AP1

AK35

AW2

AY2

AL5

AT5

AN9

AP9

AK7

AK8

AN7

AK9

AJ36

AL12

AL14

AT12

AT13

AP12

AP13

AR14

AR12

AT21

AP20

AM33

AP24

AL23

AN20

AP21

AL22

AP23

AP26

AM24

AL28

AK28

AM31

AN24

AM26

AL27

AK26

AN33

AM34

AM36

AN38

AP31

AR31

AJ34

AJ35

AH4

AR3

AL9

AM14

AN22

AL26

AM35

AJ33

AY13

BA20

AV14

AU12

U1200

OMIT

NB

945GM

BGA

AR27

AK18

AK16

AU23

AW27

AV27

AV28

AU27

AT28

AT27

AR28

AY24

AR23

AY27

BA27

AV24

AW24

AY23

AP5

AN5

AT7

AR7

AT10

AR10

AP16

AR16

AP29

AR29

AT35

AU35

AU39

AT39

AM40

AM39

AV41

AT40

AP41

AJ3

AJ5

AK5

AT4

AN41

AK3

AK4

AR5

AV4

AY5

AW5

AY9

AY10

AW4

BA4

AK38

AW10

BA10

AJ8

AK10

AH11

AK13

AN10

AJ9

AH10

AJ11

AJ38

AL15

AP15

AM16

AN17

AN14

AP14

AL19

AM19

AW29

AV29

AR41

AW31

AU31

AU29

AT31

BA33

AY33

AP34

AP35

AU36

BA36

AP39

AP36

AR36

AV36

BA38

AY38

AW38

AR40

AP38

AV38

AU38

AJ37

AK39

AN4

BA5

AH8

AL17

BA31

AT36

AR38

AK36

AR24

AY28

AV23

AT24

U1200

15 84

A.0.0051-7150

NB DDR2 Interfaces

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>

MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>

MEM_A_CAS_L
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

30A6

30A6

30A6

30A6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30A6

30A6

30B6

30B6

30B6

30B6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30B6

30B6

29D6

29D3

29D6

29D3

29D6

29D3

29D3

29D6

29D3

29D3

29D6

29D3

29D3

29D6

29D6

29D6

29C3

29C3

29C3

29C6

29C6

29C6

29C3

29C6

29C6

29C6

29C3

29C6

29C6

29C3

29C3

29C3

29B3

29B6

29B6

29B6

29B6

29B3

29B3

29B3

29B6

29B6

29A6

29A6

29B3

29A3

29B3

29A3

29A3

29A6

29A3

29A6

29A6

29A3

29A6

29A3

29A3

29A3

29A3

29A6

29A6

29A6

29A6

29A3

29B3

29B6

29C6

29B6

29D3

29D3

29C3

29C6

29A6

29B3

29A3

29A6

29D6

29C6

29D6

29C3

29A3

29B6

29A3

29A6

29C3

29C6

29B6

29B3

29A3

29A6

29B6

29B3

29B3

29B6

29B6

29B3

29C3

29C3

29C6

29C6

29B6

29C3

29C6

29B3

29B3

29B6

29D6

29D6

28D3

28D3

28D3

28D3

28D6

28D6

28D6

28D3

28D3

28D6

28D3

28D6

28D6

28D6

28D3

28C6

28C3

28C6

28C6

28C6

28C3

28C3

28C3

28C3

28C6

28C3

28C6

28C3

28C6

28C6

28C3

28B3

28B6

28B6

28B3

28B3

28B6

28B3

28B6

28A3

28A6

28A3

28A6

28A3

28A6

28A6

28A3

28A6

28A3

28A6

28A6

28A3

28A6

28A3

28A3

28A3

28B3

28A6

28B6

28B6

28A6

28A3

28B3

28B3

28B6

28C6

28B6

28D3

28D3

28C3

28C6

28A3

28B3

28A6

28A6

28D6

28C6

28D6

28C3

28A6

28B6

28A3

28A3

28C3

28C6

28B6

28A6

28A3

28B3

28B6

28B3

28B3

28B6

28B6

28B3

28C3

28C3

28C6

28C6

28B6

28C3

28C6

28B3

28B3

28B6

28D6

28D6

28D6

http://mycomp.su/x/

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VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47
VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37
VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34
VCCAUX_NCTF35

VCCAUX_NCTF32
VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27
VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24
VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42
VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19
VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14
VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7
VSS_NCTF8

VSS_NCTF5
VSS_NCTF6

VSS_NCTF4

VSS_NCTF2
VSS_NCTF3

VSS_NCTF0
VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61
VCC_NCTF62
VCC_NCTF63

VCC_NCTF60

VCC_NCTF57
VCC_NCTF58
VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53
VCC_NCTF54

VCC_NCTF52

VCC_NCTF50
VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46
VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38
VCC_NCTF39

VCC_NCTF36
VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF31
VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18
VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13
VCC_NCTF14

VCC_NCTF11
VCC_NCTF12

VCC_NCTF10

VCC_NCTF8
VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0
VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.8V Max Current
Speed 1 Channel 2 Channel
400MTs 1300mA 2400mA
533MTs 1500mA 2800mA
667MTs 1700mA 3200mA

1.05V, Internal Graphics: 3500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, External Graphics: 1500mA Max

1.05V or 1.5V

Place in cavity

Layout Note:

Layout Note:
Place near pin BA15

Place near pin BA23

Layout Note:

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

OMIT

945GM

NB

BGA

AT6

AV6

AW6

AY6

BA6

AP8

AR8

AT8

AV8

AW8

AT34

AY8

BA8

AK11

AG12

AH12

AJ12

AK12

AH13

AJ13

AJ14

AU34

AJ15

AR15

AT15

AU15

AV15

AW15

AY15

BA15

AH16

AJ16

AV34

AH17

AJ17

AJ18

AJ19

AK19

AP19

AR19

AT19

AU19

AV19

AW34

AW19

AY19

BA19

AK20

AK21

AJ22

AK22

AP22

AR22

AT22

AY34

AU22

AV22

AW22

AY22

BA22

AJ23

BA23

AH24

AJ24

AH25

BA34

AJ25

AH26

AJ26

AR26

AT26

AU26

AV26

AW26

AY26

BA26

AU40

AH27

AJ27

AH28

AJ28

AH29

AJ29

AK29

AL29

AM29

AM30

AM41

AN30

AP30

AR30

AT30

AU30

AV30

AW30

AY30

BA30

AJ1

AV1

AJ6

AK6

AL6

AN6

AP6

AR6

AR34

AT41

AU41

N19

Y19

AA19

AB19

L20

M20

N20

P20

W20

Y20

V32

AB20

AC20

L21

M21

N21

W21

AA21

AC21

L22

M22

W32

N22

P22

W22

Y22

AB22

AC22

L23

M23

N23

P23

Y32

Y23

AA23

AB23

M24

N24

P24

L25

M25

N25

L26

AA32

N26

P26

L27

M27

N27

P27

L28

M28

N28

P28

J33

R28

T28

U28

V28

Y28

AA28

AB28

L29

M29

P29

L33

R29

U29

V29

W29

Y29

AA29

L30

M30

N30

P30

N33

R30

T30

U30

V30

W30

Y30

AA30

M31

N31

P31

P33

R31

T31

V31

W31

AA31

J32

L32

M32

L16

N32

M16

N16

M17

N17

P17

L18

M18

N18

L19

M19

P32

W33

AA33

U1200

10%

0.47UF

402

6.3V
CERM-X5R

2

1

C1610

10uF

6.3V
X5R

20%

603

2

1

C1621

603

20%

X5R

6.3V

10uF

2

1

C1620

OMIT

BGA

NB

945GM

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

U17

Y17

AC17

AE26

AE27

AF23

AG23

AF24

AG24

R15

T15

U15

V15

W15

Y15

AA15

AB15

AF25

AC15

AD15

AE15

AF15

AG15

R16

T16

U16

V16

W16

AG25

Y16

AA16

AB16

AC16

AD16

AE16

AF16

AG16

R17

T17

AF26

V17

W17

AA17

AB17

AD17

AE17

AF17

AG17

R18

AF18

AG26

AG18

R19

AF19

AG19

AF20

AG20

AF21

AG21

AF22

AG22

AF27

AG27

R27

T27

T18

U18

V18

U27

W18

Y18

AA18

AB18

AC18

AD18

T19

U19

V19

AD19

V27

R20

T20

U20

V20

AD20

R21

T21

U21

V21

AD21

W27

R22

T22

U22

V22

AD22

R23

T23

U23

V23

AD23

Y27

R24

T24

U24

V24

W24

Y24

AA24

AB24

AC24

AD24

AA27

R25

T25

U25

V25

W25

Y25

AA25

AB25

AC25

AD25

AB27

R26

T26

U26

V26

W26

Y26

AA26

AB26

AC26

AD26

AC27

AD27

U1200

CERM-X5R

6.3V

402

0.47UF

10%

2

1

C1611

10%

0.47UF

402

6.3V

CERM-X5R

2

1

C1612

10%

0.47UF

402

6.3V
CERM-X5R

2

1

C1613

10%

0.47UF

402

6.3V

CERM-X5R

2

1

C1614

10%

0.47UF

402

6.3V
CERM-X5R

2

1

C1615

16 84

A.0.0051-7150

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB Power 1

=PP1V5_S0_NB_VCCAUX

=PPVCORE_S0_NB

=PPVCORE_S0_NB

NB_VCCSM_LF4
NB_VCCSM_LF5

NB_VCCSM_LF2
NB_VCCSM_LF1

=PP1V8_S3_MEM_NB

65D6

65D6

65B6

19D7

19D7

19D7

19D2

19D2

65B6

19C4

19C8

19C8

19D7

17B6

16C8

16D3

14C2

http://mycomp.su/x/

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25

VTT27

VTT26

VTT28
VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35
VTT36
VTT37

VTT39

VTT38

VTT40
VTT41
VTT42
VTT43
VTT44
VTT45

VTT48

VTT46
VTT47

VTT49
VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58
VTT59
VTT60
VTT61
VTT62

VTT64

VTT63

VTT65
VTT66
VTT67

VTT69

VTT68

VTT70
VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0
VCCD_LVDS1

VCCD_TVDAC

VCC_HV1
VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14
VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23
VCCAUX24

VCCAUX22

VCCAUX25
VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30
VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34
VCCAUX35
VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39
VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1900mA Max

40mA Max

See VCCSYNC

150mA Max

120mA Max

45mA Max

45mA Max

50mA Max

50mA Max

10mA Max

24mA Max

20mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

60mA Max

2mA Max

800mA Max

1500mA Max VCC3G/3GPLL

OMIT

BGA

NB

945GM

L14

M14

M1

N1

P1

R1

AB1

D2

M2

N14

P2

R2

M3

N3

P3

R3

M4

N4

P4

M5

P14

N5

P5

R5

A6

M6

P6

R6

M7

N7

P7

R14

M8

N8

P8

R8

M9

N9

P9

M10

N10

P10

T14

R10

M11

N11

P11

R11

L12

M12

N12

P12

R12

V14

T12

U12

V12

W12

Y12

AA12

AB12

L13

M13

N13

W14

R13

T13

U13

V13

W13

Y13

AA13

AB13

AC13

AD13

AB14

AC14

G20

B39

G21

H41

H22

D21

H19

C28

B28

A28

AH2

AH1

AF30

AG30

AH30

AJ30

AK30

AD12

AL30

AE12

AF12

AE13

AF13

Y14

AE14

AF14

AG14

AH14

P15

AC31

AH15

P16

P19

AH19

AH20

AJ20

AH21

AJ21

AH22

AE28

AE31

AF28

AG28

AC29

AD29

AE29

AF29

AG29

AC30

AD30

AE30

AF31

AK31

F20

E20

D20

C20

F19

E19

H20

AF2

A38

AF1

C39

B26

E21

F21

AC33

G41

A30

B30

C30

B25

B23

A23

L41

N41

R41

V41

Y41

AB41

AJ41

U1200

10%

0.47UF

6.3V

CERM-X5R

402

2

1

C1711

20%

0.22uF

6.3V

402

X5R

2

1

C1712

10%

0.47UF

CERM-X5R

6.3V

402

2

1

C1713

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Power 2

051-7150 A.0.0

8417

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG

=PP2V5_S0_NB_VCCA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

NB_VTTLF_CAP1

NB_VTTLF_CAP2

NB_VTTLF_CAP3

=PP1V05_S0_NB_VTT

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

65B6 19D7

65B3

65A6

65A6

65D6

19C4

19C7

65B6

65A6

34B2

19D7

19D7

19D7

19D7

65B6

19D1

16D1

19D1

19C6

19D7

19D1

19D1

19C1

19C1

19C1

19B6

19A4

19A3

19B6

19A6

19A6

19D1

19A3

19C5

19B3

19B3

19A6

19D1

19C8

19D1

19A5

http://mycomp.su/x/

VSS_1

VSS_0

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7

VSS_9

VSS_8

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17

VSS_19

VSS_18

VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26

VSS_28

VSS_27

VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

VSS_49

VSS_48

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

VSS_73

VSS_72

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79

VSS_82

VSS_80
VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92
VSS_93
VSS_94

VSS_96

VSS_95

VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125

VSS_127

VSS_126

VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135

VSS_137

VSS_136

VSS_138
VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156

VSS_158

VSS_157

VSS_159
VSS_160
VSS_161
VSS_162

VSS_164

VSS_163

VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170

VSS_172

VSS_171

VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269
VSS_270

VSS_268

VSS_266
VSS_267

VSS_265

VSS_264

VSS_263

VSS_261
VSS_262

VSS_260

VSS_259

VSS_258

VSS_256
VSS_257

VSS_255

VSS_254

VSS_253

VSS_251
VSS_252

VSS_250

VSS_248
VSS_249

VSS_247

VSS_246

VSS_245

VSS_243
VSS_244

VSS_242

VSS_241

VSS_240

VSS_238
VSS_239

VSS_237

VSS_236

VSS_235

VSS_233
VSS_234

VSS_232

VSS_231

VSS_230

VSS_228
VSS_229

VSS_227

VSS_225
VSS_226

VSS_224

VSS_223

VSS_222

VSS_220
VSS_221

VSS_219

VSS_218

VSS_217

VSS_215
VSS_216

VSS_214

VSS_213

VSS_212

VSS_210
VSS_211

VSS_209

VSS_207
VSS_208

VSS_205
VSS_206

VSS_204

VSS_202
VSS_203

VSS_201

VSS_200

VSS_199

VSS_197
VSS_198

VSS_196

VSS_195

VSS_194

VSS_192
VSS_193

VSS_191

VSS_190

VSS_189

VSS_187
VSS_188

VSS_186

VSS_184
VSS_185

VSS_183

VSS_182

VSS_180
VSS_181

VSS_273
VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282
VSS_283
VSS_284

VSS_286

VSS_285

VSS_287
VSS_288
VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301
VSS_302

VSS_300

VSS_304

VSS_303

VSS_305
VSS_306
VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312
VSS_313
VSS_314
VSS_315

VSS_317

VSS_316

VSS_318
VSS_319
VSS_320

VSS_322

VSS_321

VSS_323
VSS_324
VSS_325

VSS_327

VSS_326

VSS_328
VSS_329
VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338
VSS_339
VSS_340

VSS_342
VSS_343

VSS_341

VSS_345

VSS_344

VSS_346
VSS_347
VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

OMIT

BGA

945GM

NB

AF34

AG34

AK34

AN34

D35

F35

G35

H35

J35

L35

AP40

M35

N35

P35

R35

T35

V35

W35

Y35

AA35

AB35

AV40

AH35

AR35

AV35

BA35

B36

C36

AC36

AE36

AF36

AG36

F41

AH36

AN36

AW36

AY36

D37

F37

G37

H37

J37

L37

J41

M37

N37

P37

R37

T37

V37

W37

Y37

AA37

AB37

M41

AH37

AK37

C38

AE38

AF38

AG38

AH38

AM38

AT38

D39

P41

F39

G39

H39

J39

L39

M39

N39

P39

R39

T39

T41

V39

W39

Y39

AA39

AB39

AC39

AJ39

AN39

AR39

AV39

W41

AW39

AY39

AW23

AL24

AU24

BA24

A25

D25

E25

H25

K25

P25

B40

AK25

D26

F26

K26

M26

AN26

B27

C27

F27

G27

AE40

J27

AK27

AM27

AP27

E28

J28

W28

AC28

AD28

AM28

AF40

AP28

AU28

AW28

BA28

A29

B29

C29

E29

G29

K29

AG40

N29

T29

AB29

AN29

AT29

E30

AB30

Y31

AB31

AG31

AH40

AJ31

AN31

AV31

AY31

B32

G32

AB32

AC32

AE32

AF32

AJ40

AG32

AH32

B33

D33

F33

G33

H33

M33

R33

T33

AK40

V33

Y33

AB33

AE33

AR33

AV33

AW33

C34

AC34

AE34

AN40

AA41

AC41

U1200

OMIT

BGA

945GM

NB

AL1

C2

F2

H2

J2

N2

T2

U2

Y2

AB2

AD2

AJ2

AK2

AP2

AR2

AT2

G3

AA3

AC3

AD3

AF3

AG3

AH3

AL3

AV3

AW3

AY3

C4

F4

J4

R4

U4

Y4

AJ4

AL4

AP4

AR4

AY4

AD5

AF5

AV5

B6

H6

K6

N6

U6

Y6

AB6

AD6

AG6

D7

G7

R7

AC7

AF7

AH7

AJ7

AL7

AP7

AV7

BA7

C8

K8

U8

AA8

AD8

AG8

A9

E9

G9

R9

Y9

AB9

AH9

AR9

AW9

BA9

U10

W10

AC10

AG10

AJ10

AL10

AP10

AV10

B11

D11

J11

Y11

AA11

AD11

E12

H12

K12

AC12

AY12

B13

D13

F13

P13

AG13

AL13

AM13

AN13

AR13

AV13

E14

H14

K14

U14

AA14

AD14

AK14

AT14

BA14

A15

B15

L15

M15

N15

AK15

AM15

AN15

C16

F16

J16

AL16

AN16

AV16

AK17

AM17

AP17

AR17

AY17

A18

D18

H18

P18

AH18

C19

G19

K19

W19

AC19

AN19

A20

B20

K20

AA20

AM20

AR20

AW20

C21

H21

J21

K21

P21

Y21

AB21

AL21

AN21

AR21

AV21

BA21

A22

D22

E22

F22

G22

K22

AA22

C23

F23

J23

K23

W23

AC23

AH23

AM23

AN23

AT23

U1200

18 84

A.0.0051-7150

NB Grounds

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

http://mycomp.su/x/

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

NR/FB

IN

EN

OUT

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

800mA Max

These are the power signals that leave the NB "block"

Power Interface

40mA Max

MCH VCC_HV BYPASS
(MCH HV BUFFER 3.3V PWR)

Layout Note: Route to caps, then GND

(MCH MEMORY PLL 1.5V PWR)

1500mA Max

1500mA Max
10mA Max?

GMCH CORE PWR 1.05V BYPASS

1900mA Max

3200mA Max

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

Rail Totals:

2310mA Max?

?mA Max

?mA Max
100mA Max

800mA Max

3674mA Max

40mA Max

40mA Max?

2mA Max

150mA Max

3200mA Max

1500mA Max

24mA Max

70mA Max

?mA Max

Layout Note: Route to caps, then GND

10MA MAX

(MCH LVDS ANALOG 2.5V PWR)

MCH VCCA_LVDS BYPASS

132mA Max

?mA Max

60mA Max

GMCH VCC3G FILTER
(PCI-E/DMI ANALOG 1.5V PWR)

1500mA Max

(3GIO PLL 1.5V PWR)

GMCH VCCA_3GPLL FILTER

Layout Note:

be close to MCH

10uF caps should

on opposite side.

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

GMCH VCCAUX FILTER

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

2mA Max

MCH VCCA_3GBG BYPASS

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Layout Note:
Place L and C
close to MCH

Place on the edge

Layout Note:

(SHARE C0940 470UF)

45mA Max

45mA Max

GMCH VCCA_HPLL FILTER
(HOST PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

MCH VTT BYPASS
(MCH FSB 1.05V PWR)

Layout Note:
Place in cavity

100mA Max

(MCH LVDS DIGITAL 1.5V PWR)

MCH VCCD_LVDS BYPASS

20MA MAX

GMCH VCCA_DPLLA FILTER

50MA MAX

50MA MAX

(CRT/TVOUT PLL 1.5V PWR)

GMCH VCCA_DPLLB FILTER
(LVDS PLL 1.5V PWR)

1500mA Max

60MA MAX

(MCH LVDS TRANSMITTER 2.5V PWR)

MCH VCC_TXLVDS BYPASS

0.22uF

X5R

6.3V

20%

402

2

1

C1907

X5R
603

20%

6.3V

10uF

2

1

C1972

0.22uF

X5R
402

20%

6.3V

2

1

C1967

CERM1

20%

2.2uF

603

6.3V

2

1

C1966

4.7uF

CERM
603

20%

6.3V

2

1

C1965

CRITICAL

470uF

D2T

TANT

2.5V

20%

3 2

1

C1900

91nH

1210

21

L1970

CERM

10V

20%

402

0.1uF

2

1

C1916

6.3V

20%

402

X5R

0.22uF

2

1

C1906

10V

20%

402

CERM

0.1uF

2

1

C1991

CERM

603

20%

6.3V

4.7UF

2

1

C1990

0.1uF

CERM
402

20%
10V

2

1

C1993

6.3V

20%

603

X5R

10uF

2

1

C1992

10V

20%

402

CERM

0.1uF

2

1

C1995

0.01UF

402

CERM

16V

20%

2

1

C1994

603

X5R

6.3V

10uF

20%

2

1

C1952

1.5K

1%
1/16W
MF-LF
402

2

1

R1990

CRITICAL

TPS73115

SOT23-5

5
4

1

2

3

U1900

6.3V

10%

1uF

CERM

402

2

1

C1950

16V

10%

0.01uF

CERM

402

2

1

C1951

0

5%
1/16W
MF-LF

402

21

R1954

NO STUFF

0

5%
1/16W
MF-LF

402

21

R1953

CERM

NO STUFF

20%
10V

402

0.1uF

2

1

C1953

0.1uF

CERM
402

20%
10V

2

1

C1915

20%
10V
CERM
402

0.1uF

2

1

C1954

POLY

2.5V

20%

220UF

CASE-B2

2

1

C1970

10uF

X5R
603

6.3V

20%

2

1

C1914

6.3V

20%
X5R

0.22uF

402

2

1

C1905

0.1uF

CERM
402

10V

20%

2

1

C1935

0603

FERR-120-OHM-0.2A

21

L1934

10V

0.1uF

20%
CERM

402

2

1

C1937

402

6.3V

1uF

CERM

10%

2

1

C1904

FERR-120-OHM-0.2A

0603

21

L1936

6.3V

20%

805

CERM

22UF

2

1

C1934

6.3V

20%

805

CERM

22UF

2

1

C1936

6.3V
X5R

20%

10uF

603

2

1

C1903

X5R

6.3V

20%

603

10uF

2

1

C1902

CERM

402

20%
10V

0.1uF

2

1

C1918

10V

20%

402

CERM

0.1uF

2

1

C1976

1.0UH-220MA-0.12-OHM

0805

21

L1975

6.3V

20%

603

X5R

10uF

2

1

C1975

MF-LF

402

0.51

1/16W

1%

21

R1975

10uF

X5R
603

20%

6.3V

2

1

C1971

NB (GM) Decoupling

SYNC_DATE=07/25/2006

SYNC_MASTER=M59_MG

051-7150 A.0.0

8419

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3G

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_NB_DPLL

TPS73115_NR

PP1V5_S0_NB_VCCA_DPLLB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V

=PP2V5_S0_NB_VCC_TXLVDS

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_DPLL

PP1V5_S0_NB_VCCA_DPLLA

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

=PP2V5_S0_NB_VCCA_3GBG

=PP1V5_S0_NB_VCCD_LVDS

VOLTAGE=1.5V

PP1V5_S0_NB_3GPLL_F

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_VCCAUX

=PP1V05_S0_FSB_NB

=PP2V5_S0_NB_VCCA_LVDS

GND_NB_VSSA_LVDS

LVDS_VREFL

LVDS_VREFH

LVDS_IBG

CRT_HSYNC_R

CRT_DDC_DATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA

SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK

SDVO_CTRLCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D27 TP_NB_XOR_LVDS_D27

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_A34

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A35 TP_NB_XOR_LVDS_A35

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB

LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA

LVDS_CLKCTLA

TV_DACA_OUT
TV_DACB_OUT

=PP1V5_S0_NB_TVDAC

=PP1V05_S0_NB_CRT

=PP1V5_S0_NB

=PP1V05_S0_NB_VTT

=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

MAKE_BASE=TRUE

TP_CRT_DDC_CLK

CRT_DDC_CLK

CRT_IREF

CRT_BLUE_L

CRT_GREEN_L

CRT_RED_L

CRT_BLUE

CRT_GREEN

CRT_RED

=PP1V05_S0_NB_CRT

TV_IREF

TV_IRTNC

TV_IRTNB

CRT_VSYNC_R

=PP1V5_S0_NB_PCIE

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

GND_NB_VSSA_CRTDAC

PP2V5_S0_NB_VCCA_CRTDAC

=PP2V5_S0_NB_VCCSYNC

PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QTVDAC

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVBG

GND_NB_VSSA_TVBG

=PP1V5_S0_NB_3G

TV_IRTNA

TV_DACC_OUT

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL

GND_NB_VSSA_3GBG

=PP3V3_S0_NB_VCC_HV

=PPVCORE_S0_NB

=PP2V5_S0_NB_VCCA_3GBG

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

=PP1V8_S3_MEM_NB

=PP1V5_S0_NB_3GPLL

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_PLL

=PP1V05_S0_NB_VTT

65D6 34C8 34C6

65B3

65D6

65D6

65D6

65B6

34B8

20B4

19D7

65B6

19D7

19D2

65A6

65A6 19D7

12C2

65B6

65C8

65D6

20A4

65B3

19C8

65B6

19C4

65B3

19D2

65A6

65A6

65B6

19C8

65B6

65D6

19D7

34B2

19D7

65B6

65C6

17B6

12B7

65A6

19D7

65D6

65C6

19C8

14D6

19C6

65B6

65D6

65C6

16D3

19D7

19D7

65C6

17B6

65C6

65B6

19C7

16D3

19C5

19A6

19D1

16B6

65C6

16D3

19D6

65B6

19D7

17D6

65A6 17C6 17D6

17C6

17D6

17C6

17C6

17C6

17D6

19D7

16D1

12A7

17C6

17C6

13D5

13D5

13D5

13B5

13B5

14B6

14B6

14C6

14C6

14C6

14C6

13D5

13C5

13C5

19D2

19D6

60A7

17D3

14C7

17C6

17C6

13B5

13B5

13B5

13B5

13B5

13B5

13B5

13B5

19D7

13C5

13C5

13C5

13B5

13D2

16C8

19D6

17D6

17D6

17D6

17C6

17B6

17C6

17C6

17C6

17C6

17C6

19B5

13C5

13C5

16D1

19D7

19D7

17D6

17C6

16C8

17D6

17D6

17D6

14C2

19B5

16C8

19D2

19B8

17D3

http://mycomp.su/x/

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PCIe Backward
Interop. Mode

VCC Select

Reversal

DMI Lane

High = Reversed

Low = Normal

High = 1.5V

Low = 1.05V

Internal pull-down

Internal pull-down

Internal pull-down

945 External Design Spec says reserved

High = Both active

Low = Only SDVO
or PCIe x1

ODT

FSB Dynamic

RESERVED

Low = Disabled

High = Enabled

RESERVED

Internal pull-up

RESERVED

00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal Operation

Internal pull-up

Low = Reversed

RESERVED

CPU Strap

RESERVED

PCIE Graphics

High = Normal

Low = RESERVED

High = DMIx4

Low = DMIx2

NB_CFG<20>

NB_CFG<19>

NB_CFG<9>

NB_CFG<8>

NB_CFG<18>

NB_CFG<17>

NB_CFG<6>

NB_CFG<16>

NB_CFG<15>

NB_CFG<5>

NB_CFG<14>

NB_CFG<13:12>

RESERVED

NB_CFG<3>

NB_CFG<4>

Lane Reversal

PROBABLY NOT NEEDED

PROBABLY NOT NEEDED

DMI x2 Select

Internal pull-up

RESERVED

NB_CFG<7>

High = Mobile CPU

NB_CFG<10>

NB_CFG<11>

RESERVED

RESERVED

Internal pull-up

Internal pull-ups

402

5%

2.2K

1/16W
MF-LF

NBCFG_DMI_X2

2

1

R2075

5%

2.2K

1/16W
MF-LF
402

NBCFG_DYN_ODT_DISABLE

2

1

R2085

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

2

1

R2058

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

2

1

R2059

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

2

1

R2060

NO STUFF

2.2K

5%
1/16W
MF-LF
402

2

1

R2077

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

2

1

R2079

20 84

A.0.0051-7150

NB Config Straps

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB_CFG<7>

NB_CFG<9>

NB_CFG<5>

NB_CFG<16>

NB_CFG<20>

NB_CFG<19>

NB_CFG<18>

=PP3V3_S0_NB

=PP3V3_S0_NB

=PP3V3_S0_NB

65B3

65B3

65B3

20B4

20B4

20B4

20A4

20A4

19C7

19C7

19C7

14D6

14D6

14D6

14C6

14C6

14C6

14C6

14B6

14C6

14C6

14C7

14C7

14C7

http://mycomp.su/x/

IO

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IO

IO
IO

IO

IN

IO

DDACK*

SATARBIASN
SATARBIASP

SATA_CLKN
SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN
SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0
LAN_TXD1

LAN_RXD1
LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0
LAD1

EE_DOUT
EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY
DDREQ

DD0
DD1

DD3

DD2

DD5

DD4

DD6
DD7
DD8

DD11

DD9

DD10

DD12
DD13
DD14
DD15

DA0
DA1
DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

OUT

OUT

IN

OUT

IN
IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

IN
IN

IN

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

(INT PU)

(INT PU)

(WEAK INT PD)

NOTE: R2108=56 IN CV.

BOM CONSOLIDATION

CHANGED TO 54.9 FOR

NOTE: R2110=56 IN CV.

NOTE: PULLED UP PER INTEL

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

INTEL CONFIRMS OK TO LEAVE PINS AS NC

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTO RESET STATE TO SAVE PWR.

NOTE:
POR IS SMC WILL PUT LAN INT’F

NOTE: KEYBOARD CONTROLLER RESET CPU

NOTE: RISING-EDGE TRIGGERED AT CPU

BOM CONSOLIDATION

< 2 IN OF SB

LAYOUT NOTE: R2107 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2108 TO BE
< 2 IN OF R2107 W/O STUB

(DSTROBE)

20K PD

20K PD

20K PD

(STOP)

(HSTROBE)

NOTE: DD<7> HAS INTERNAL 11.5K PD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

INTERNAL 20K PD ONLY ENABLED IN S3COLD

INTERNAL 20K PD

NONE

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

AC ’07

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

ACZ_SDIN[0-2]

ACZ_RST#

ACZ_BIT_CLK

ACZ_SYNC

ACZ_SDOUT

INTEL HIGH DEFINITION AUDIO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

NOTE: DDREQ HAS INTERNAL 11.5K PD

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

(WEAK INT PU)

402

5%

0

MF-LF
1/16W

NOSTUFF

21

R2100

MF-LF

1/16W

5%

2.2K

402

NOSTUFF

21

R2101

1/16W

402

39

5%

MF-LF

21

R2195

39

21

R2198

39

21

R2197

39

21

R2196

MF-LF

1/16W

5%

10K

402

2

1

R2199

OMIT

ICH7-M

SB

BGA

AH25

AF24

AF26

AH22

AF23

AG10

AH10

AF18

AE1

AF1

AH6

AG6

AE7

AF7

AH2

AG2

AE3

AF3

AB2

AB1

AA3

AG23

AH24

AB3

AA5

AC3

V7

V6

U7

T5

V4

U5

U3

V3

Y6

AC4

AB5

AA6

AG16

W4

Y5

AF25

AG21
AF22

AG22

AH16

AG24

AG26

Y1
Y2
W3

W1

AH15

AF15

AE15

AF16

AF12

AE12

AC12

AD12

AC13

AD14

AF13

AG13

AC15

AH14

AH13

AF14

AC14

AB13

AE14

AB15

AD16

AE16

AF17

AE17

AH17

AG27

R6

T4

T1

T3

T2

R5

U1

AH28

AE22

U2100

MF-LF

1/16W

5%

10K

402

2

1

R2194

MF-LF

1/16W

1%

402

332K

2

1

R2105

402

1%

1/16W

MF-LF

24.9

21

R2107

54.9

1%

1/16W

MF-LF

402

2

1

R2108

1%

54.9

402

1/16W

MF-LF

21

R2110

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

SB: 1 OF 4

051-7150

8421

A.0.0

IDE_PDD<3>

IDE_PDD<2>

TP_SB_XOR_V3

TP_SB_XOR_W3

TP_SB_XOR_T5

TP_SB_XOR_V4

TP_SB_XOR_U5

TP_SB_XOR_U3

PP3V3_S5_SB_RTC

ACZ_RST_L

ACZ_BITCLK

SB_RTC_RST_L

SB_RTC_X2

LPC_FRAME_L

TP_SB_GPIO23

TP_SB_DRQ0_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_GPIO

IDE_PDD<6>

ACZ_SDATAOUT

PM_THRMTRIP_L

=PP1V05_S0_SB_CPU_IO

SMC_RCIN_L

ACZ_SYNC

IDE_PDCS1_L
IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<13>

IDE_PDD<12>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<11>

IDE_PDD<8>

IDE_PDD<7>

IDE_PDD<4>
IDE_PDD<5>

IDE_PDD<1>

IDE_PDD<0>

IDE_PDDREQ

IDE_PDIORDY

IDE_PDIOW_L

IDE_IRQ14

IDE_PDIOR_L

SB_ACZ_RST_L

TP_CPU_CPUSLP_L

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

FWH_INIT_L
CPU_INIT_L

CPU_INTR

CPU_SMI_L

CPU_NMI

CPU_STPCLK_L

CPU_THERMTRIP_R

SB_RTC_X1

SB_SM_INTRUDER_L

SB_ACZ_BITCLK
SB_ACZ_SYNC

ACZ_SDATAIN<0>

TP_SB_ACZ_SDIN2

TP_SB_ACZ_SDIN1

SB_ACZ_SDATAOUT

TP_SB_SATALED_L

SATA_A_D2R_N
SATA_A_D2R_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P

SATA_C_D2R_N

SATA_C_R2D_C_N
SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

IDE_PDDACK_L

SATA_C_D2R_P

CPU_RCIN_L

SB_A20GATE

CPU_FERR_L

=PP1V05_S0_SB_CPU_IO

SB_INTVRMEN

TP_SB_XOR_W1
TP_SB_XOR_Y1
TP_SB_XOR_Y2

TP_SB_XOR_U7
TP_SB_XOR_V6
TP_SB_XOR_V7

58C6

58C6

58C6

65B3

65B3 65D6

65D6

26D3

84B4

84B4

51C4

51C5

51C4

23D5

23D5

84B4

50C1

25C4

84B4

51C5

84B4

25C4

25A4

47B3

47B6

49C7

49C7

49D7

23B3

23B3

47B6

14B6

24C3

47B6

84C6

84C6

59C7

84C6

84C6

50D3

84C6

84C6

84C6

84C6

84C6

47B6

34C3

34C3

24C3

36C5

36C5

6C6

6C6

6C6

6C6

6C6

24B3

5C1

5C1

26D4

26C8

5C2

79A4

5C2

5D2

21C3

21D3

36C5

5C1

7C6

21C1

49C7

5C1

36C5

36C4

36C5

36C5

36C4

36C4

36C4

36C4

36C4

36C4

36C4

36C4

36D4

36C5

36C5

36C5

36C5

36C5

36C4

36C4

36C5

36C4

36C5

84B4

7C8

7B3

7B3

7B3

7C8

5C2

7D6

7C8

7C8

7C8

7C8

26C8

26D4

84B4

84B4

5C1

84B4

36A5

36A5

36A5

36A5

78B7

78B2

78B2

5A7

5A7

36A5

36A5

36C5

78B7

7C8

21C1

http://mycomp.su/x/

IN

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN
IN

IN
IN

IN

IN

IN

IN

IN

IN

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO
IO

IN

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI2TXN
DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P

USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBP4N

OC0*
OC1*
OC2*
OC3*
OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK
SPI_CS*

SPI_MOSI
SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN
DMI1RXP

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0*
C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE2*
C/BE3*

GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*

PIRQA*
PIRQB*
PIRQC*
PIRQD*

RSVD0
RSVD1
RSVD2
RSVD3

MISC

INT I/F

PCI

(2 OF 6)

IO

OUT

OUT

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO
IO

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO

IN

IO

IO

IO

IO

OUT

IO

IO

IO

IO

IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NO STUFF - DEFAULT

GNT[0-3]# HAVE INT 20K PU

(INT 20K PU)

(AKA TP3, INTERNAL 20K PU)

SB: 2 OF 4

ENABLED ONLY WHEN PCIRST#=0

R2211

NOTE: FWH_WP_L NOT USED

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

(INT PD)

(INT PD)

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

PLACE R2204 < 1/2 IN FROM SB

LAYOUT NOTE:

PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:

NOTE:

LPC (DEFAULT)

PCI

SPI

UNSTUFF

STUFF

UNSTUFFUNSTUFF

UNSTUFF

STUFF

01

10

11

STRAP R2210

NOTE: CHANGE SYMBOL

TO RSVD[1-9]

GNT5# GNT4#

SB BOOT BIOS SELECT

TARGETING FWH BIOS SPACE)

IE SB INVERTS A16 FOR ALL CYCLES

(STRAPPED TO TOP-BLOCK SWAP MODE

STUFF - A16 SWAP OVERRIDE

NOTE:

EXTERNAL 0

EXTERNAL 1

EXTERNAL 2

BOM NOTE FOR PD ON PCI_GNT3_L:

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

AND PWROK=H

IR

CAMERA

TRACKPAD (GEYSER)

BLUETOOTH

1/16W

402

24.9

MF-LF

1%

21

R2203

10K

1/16W
MF-LF

5%

402

USB_G_OC_PU

2

1

R2222

402

22.6

1%
1/16W
MF-LF

21

R2204

1/16W

5%

10K

MF-LF
402

2

1

R2223

10K

5%
1/16W
MF-LF
402

2

1

R2225

402

MF-LF

1/16W

10K

5%

2

1

R2226

10K

5%
1/16W
MF-LF
402

2

1

R2299

OMIT

BGA

SB

ICH7-M

D2
D1

N3

N4

M2

M1

L5

L4

K2

K1

J3

J4

H2

H1

G3

G4

F2

F1

P5
P2

P6

R2

P1

R27

N27

L27

J27

G27

E27

R28

N28

L28

J28

G28

E28

T24

P25

M25

K25

H25

F25

T25

P26

M26

K26

H26

F26

B3

A2

C3

E5

D4

D5

C4

D3

C25
D25

AE27

AE28

AC27

AC28

AD24

AD25

AA27

AA28

AB25

AB26

W27

W28

Y25

Y26

U27

U28

V25

V26

U2100

SB

BGA

ICH7-M

OMIT

F14

F15

B10

F21

AH8

AG8

AE9

AD9

AH4

AG4

AD5

AE5

A13

E13

C17

C16

D7

B19

C26

E11

B5

C5

B4

A3

C9

B18

A9

E10

AH20

A7

G7

F8

F7

G8

D8

C8

A14

F13

D17

D16

E7

F16

A12

C15

D12

C12

B15

C14

A15

A17

E17

A18

E16

D6

E6

F18

B6

C7

A6

A8

B9

D9

E9

F10

F11

A10

A16

A11

D11

C11

E12

G13

G15

C13

B12

D14

E14

C18

E18

U2100

MF-LF

1/16W

5%

10K

402

2

1

R2200

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

2

1

R2250

10K

5%
1/16W
MF-LF
402

USB_E_OC_PU

2

1

R2251

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

2

1

R2255

MF-LF
402

1/16W

5%

10K

2

1

R2298

MF-LF

402

5%

10K

1/16W

2

1

R2205

402

10K

MF-LF

5%

1/16W

NOSTUFF

2

1

R2206

MF-LF
1/16W

10K

402

5%

2

1

R2207

VOLTAGE=0V

1/16W
MF-LF

5%

1K

402

2

1

R2211

051-7150

8422

A.0.0

SB_GPIO31

TP_PCI_GNT4_L

PCI_GNT3_L

TP_PCI_GNT2_L

TP_PCI_GNT0_L

TP_PCI_GNT1_L

=PP3V3_S5_SB_USB

USB_D_OC_L

USB_B_OC_L

USB_E_OC_L

USB_A_OC_L

NB_SB_SYNC_L

TP_SB_RSVD9

ODD_PWR_EN_L

SB_GPIO4

SB_GPIO3

SB_GPIO2

PCI_C_BE_L<0>
PCI_C_BE_L<1>

PCI_DEVSEL_L

PCI_PERR_L

PCI_RST_L

TP_PCI_PME_L

PLT_RST_L

PCI_TRDY_L

PCI_FRAME_L

PCI_IRDY_L

PCI_CLK_SB

PCI_PAR

PCI_LOCK_L
PCI_SERR_L

PCI_AD<0>

PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>

PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

PCI_C_BE_L<3>

INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L

DMI_IRCOMP_R

SB_CLK100M_DMI_P

USB_RBIAS_PN

DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_S2N_N<0>
DMI_S2N_P<0>

DMI_S2N_N<2>
DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

USB_A_N
USB_A_P
USB_B_N
USB_B_P
USB_C_N
USB_C_P
USB_D_N
USB_D_P

USB_E_P
USB_F_N
USB_F_P
USB_G_N
USB_G_P

TP_USB_H_N

USB_E_N

SB_GPIO30

SB_GPIO29

SB_CLK100M_DMI_N

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_N<1>
DMI_N2S_P<1>

PCIE_A_D2R_N
PCIE_A_D2R_P
PCIE_A_R2D_C_N
PCIE_A_R2D_C_P

PCIE_B_D2R_N
PCIE_B_D2R_P
PCIE_B_R2D_C_N
PCIE_B_R2D_C_P

PCIE_C_D2R_N
PCIE_C_D2R_P
PCIE_C_R2D_C_N
PCIE_C_R2D_C_P

PCIE_D_D2R_N
PCIE_D_D2R_P
PCIE_D_R2D_C_N
PCIE_D_R2D_C_P

PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P

PCIE_F_D2R_N
PCIE_F_D2R_P
PCIE_F_R2D_C_N
PCIE_F_R2D_C_P

SB_GPIO31

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S5_SB_IO

USB_C_OC_L

USB_A_OC_L
USB_B_OC_L

USB_D_OC_L

USB_C_OC_L

SPI_ARB

SPI_SO

TP_USB_H_P

INT_PIRQD_L

TP_SB_XOR_AD5
TP_SB_XOR_AG4
TP_SB_XOR_AH4
TP_SB_XOR_AD9

TP_SB_XOR_AE5

TP_SB_XOR_AH8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AG8

TP_SB_XOR_AE9

SB_GPIO29

USB_E_OC_L

PCI_AD<6>

PCI_AD<1>

PCI_REQ0_L

PCI_REQ1_L

PCI_REQ3_L

PCI_STOP_L

SPI_SCLK

PCI_C_BE_L<2>

BOOT_LPC_SPI_L

PCI_REQ2_L

SB_GPIO30

SPI_CE_L

SPI_SI

=PP3V3_S0_SB

PCI_PME_FW_L

51B4

22D8

22D8

22D8

22D8

37D3

37D3

79A4

37C3

37D3

37D3

37C3

37C6

14B4

14B4

6C2

22D8

14B4

14B4

25B6

22D8

22C4

22C4

22C4

22C4

54C1

6C2

37D3

22C4

37C3

54C7

49C7

22C4

54C7

54C1

65B3

22C4

6B7

65C3

6C1

6D1

6C1

6D1

14B6

36C7

77A1

26C2

26D2

37C6

37B6

26D2

26D2

37C2

26C3

26D2

26D2

26D2

34D6

37B6

26D2

26D2

37D6

37D6

37D6

37D6

37D6

37D6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

6B7

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37B6

26D2

26D2

26D2

34C3

5A7

5A7

14B4

14B4

14B4

14B4

14B4

14B4

14B4

14B4

6D1

6D1

6D1

6D1

6D1

6D1

6C1

6D1

6C1

6C1

6C1

6C1

6C1

6C1

6C1

6C5

22D8

34C3

14B4

14B4

14B4

14B4

5A7

5A7

39D5

39D5

39C5

39C5

48C3

48C3

48C3

48C3

48B3

48C3

48C3

48C3

48B3

48B3

48B3

48B3

48B3

48B3

48B3

48B3

48A3

48B3

48B3

48B3

22D8

24D5

65D3

6D1

6D1

6D1

6C1

6D1

49D5

49D5

6C1

26D2

22C4

6C1

37D6

37D6

26D2

26D2

26D2

49D5

37B6

5C2

26D2

6C5

49B5

49D5

25D8

37D3

http://mycomp.su/x/

IN

IN

IN

IN

OUT

OUT

OUT
OUT

OUT

IN

IN

IO

IO

OUT
OUT

OUT

IN

IN

IO

IN

IN

IO

IN

IN

IN

IN

IO

IO

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3*
SLP_S4*
SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25
GPIO35
GPIO38
GPIO39

SMBCLK
SMBDATA
LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR
SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ
THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(INT 20K PU)

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

NOTE FOR R2323 (DEF=NOSTUFF)
SB WILL DISABLE TCO TIMER

STRAPPING @ PWROK RISING:
SYSTEM REBOOT FEATURE

NOT USED

NOTE: RESERVED FOR FUTURE

LAYOUT NOTE:

NOTE FOR GPIO25:

OD

DEF=GPI

IN RESET STATE TO SAVE PWR

SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F

NOTE:

NOTE:
SV_SET_UP IS LINDACARD DETECT

LO = NOT PRESENT

HI = PRESENT

(INT WEAK PD)

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

DEF=GPI

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

DEF=GPI

100

21

R2302

100

21

R2303

100

21

R2305

10K

1/16W
MF-LF

5%

402

NOSTUFF

2

1

R2306

1/16W
MF-LF

5%

402

10K

2

1

R2307

10K

5%

MF-LF

1/16W
402

2

1

R2308

NOSTUFF

402

0

1/16W
MF-LF

5%

2

1

R2309

10K

1/16W
MF-LF

5%

402

2

1

R2310

10K

402

NOSTUFF

5%

MF-LF

1/16W

2

1

R2311

402
5%

MF-LF

1/16W

10K

2

1

R2313

5%

MF-LF

1/16W

0

NOSTUFF

402

2

1

R2314

5%

MF-LF

1/16W

10K

402

2

1

R2316

5%

1/16W

10K

402
MF-LF

2

1

R2317

5%

MF-LF

1/16W
402

10K

2

1

R2318

402
5%

MF-LF

1/16W

10K

2

1

R2319

10K

1/16W
MF-LF

5%

402

2

1

R2320

SM-LF

10K

5%
1/16W

5678

4321

RP2300

100K

1/16W
MF-LF

402

5%

21

R2399

1K

402
5%

MF-LF

1/16W

2

1

R2398

1/16W
402

8.2K

MF-LF
5%

2

1

R2397

402

10K

1/16W

5%

MF-LF

2

1

R2396

5%

402
MF-LF

1/16W

8.2K

2

1

R2395

ICH7-M

SB

BGA

OMIT

F20

AD22

C21

AF20

A22

C20

A27

A19

A25

B25

B22

C22

F22

D23

B24

AH21

Y4

A28

AA4

C23

A26

C19

E20

E21

AC18

AC21

AE20

AD20

AE19

AH19

AD21

U2

AC19

AG18

E23

B21

A21

D20

R3

AF19

AF21

AH18

AC20

AC22

E22

R4

E19

F19

B23

A20

AB18

B2

AC1

U2100

10K

5%
MF-LF

1/16W
402

2

1

R2388

NO_REBOOT_MODE

1/16W

1K

5%

402
MF-LF

2

1

R2323

5%

402

MF-LF

1/16W

10K

NOSTUFF

2

1

R2326

10K

402

1/16W
MF-LF

5%

NOSTUFF

2

1

R2327

MF-LF

1/16W

8.2K

402

5%

2

1

R2343

A.0.0

23 84

051-7150

SYNC_MASTER=M59_MG

SYNC_DATE=07/25/2006

SB: 3 OF 4

INT_SERIRQ

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_DPRSLPVR

PM_BATLOW_L

SB_CLK48M_USBCTLR

SV_SET_UP

SMB_CLK

SATA_C_DET_L

SB_GPIO19

SB_GPIO21

SB_GPIO37

SB_CLK14P3M_TIMER

SUS_CLK_SB

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L

PM_SB_PWROK

PM_SYSRST_L

PM_SUS_STAT_L

BIOS_REC

VR_PWRGD_CK410

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

TP_SB_GPIO6

CRB_SV_DET

=PP3V3_S5_SB

FWH_MFG_MODE

BIOS_REC

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_BMBUSY_L

SB_SPKR

SMB_DATA

=PP3V3_S5_SB

SMC_RUNTIME_SCI_L

PM_RSMRST_L

PM_LAN_ENABLE

PM_PWRBTN_L

PCIE_WAKE_L

FWH_MFG_MODE

PM_STPPCI_L

SMB_ALERT_L

PM_THRM_L

SMC_EXTSMI_L

PM_CLKRUN_L

PM_STPCPU_L

TP_AZ_DOCK_RST_L

TP_GPU_D3COLD_RST_L

=PP3V3_S5_SB

SMS_INT_L

IDE_RESET_L

SV_SET_UP

CRB_SV_DET

TP_SB_GPIO25_DO_NOT_USE

SB_CLK100M_SATA_OE_L

TP_SB_GPIO38

SB_GPIO26

SMC_WAKE_SCI_L

LAN_ENERGY_DET

SMC_SB_NMI

SMLINK<1>

SMLINK<0>

SMB_LINK_ALERT_L

PM_RI_L

58C6

65D3

65D3

65D3

65D3

58C6

65B3

64C8

51B5

25C8

25C8

65B3

25C8

58C6

25C8

51C5

23B3

84C6

51B5

49C5

64B8

49B7

50A2

23D8

65D3

23D8

23D5

23D8

47C3

51C4

23D4

51B5

49C7

21D3

59C8

23C3

43B7

49C5

50A2

26C5

49C5

23D4

26C5

23D4

21D3

23B7

39C6

49C5

23B7

50B2

23B6

5C2

21C3

23A3

14B7

49B7

34C7

5C2

27D8

36B5

34A6

6C6

42A8

41B6

49C5

26A6

5B2

5C2

23A6

26B8

23A7

11B5

23C3

23B7

23C5

23C5

21C3

23B3

14B6

27D8

23A7

49B7

49D7

49D7

49D7

5B1

23A6

33C4

49B7

49B7

5C2

33C4

26A4

23A7

49B5

36D5

5C2

23B6

33B4

64B7

49D5

40A3

49D7

http://mycomp.su/x/

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCCSUS3_3

VCC1_5_A

VCC1_5_A

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

DEPENDING ON VIO OF AZALIA INTERFACE

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

NOTE:

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOT

S3 IF INTERNAL LAN IS USED

NOTE FOR VCCLAN_3_3:

0 0

OMIT

BGA

ICH7-M

SB

AE21

AE18

AE13

AE11

AE8

AE4

AE2

AD23

AD19

AD15

AD11

AD8

AD7

AD4

AD3

AD1

AC11

AC9

AC5

AC2

AB28

AB27

AB24

AB21

AB19

AB16

AB14

AB11

AB6

AB4

AA26

AA25

AA24

AA1

Y28

Y27

Y24

Y3

W26

W25

W24

W6

V28

V27

V24

V15

V13

V2

U26

U25

U24

U17

U16

U15

U14

U13

U12

U4

T17

T16

T15

T14

T13

T12

T6

R18

R17

R16

R15

R14

R13

R12

R11

R1

P28

P27

P24

P17

P16

P15

P14

P13

P12

P4

P3

N26

N25

N24

AH27

AH23

AH12

AH7

N18

AH3

AH1

AG25

AG20

AG17

AG14

AG11

AG7

AG3

AG1

N17

AF28

AF27

AF11

AF8

AF4

AF2

AE25

AE24

N16

N15

N14

N13

N12

N11

N6

N5

N2

N1

M28

M27

M24

M17

M16

M15

M14

M13

M12

M5

M4

M3

L26

L25

L24

L15

L13

K28

K27

K24

J26

J25

J24

J5

J2

J1

H28

H27

H24

H5

H4

H3

G26

G25

G24

G21

G18

G14

G9

G6

G5

G2

G1

F28

F27

F12

F5

F4

F3

E15

E8

E4

E2

E1

D24

D21

D18

D13

D10

C27

C6

C2

B28

B26

B20

B17

B14

B11

B8

B1

A23

A4

U2100

OMIT

BGA

SB

ICH7-M

C1

K6

K5

K4

K3

G19

D22

D19

C24

E3

N7

M7

M6

L7

L6

L3

L2

L1

A24

P7

R7

G20

C28

K7

AD2

W5

W7

W2

V1

V5

Y7

AA2

AG28

AG15

AG12

AD18

AD13

AC16

AB20

AB12

G16

AA7

G12

G11

F9

D15

C10

B7

B16

B13

A5

AG19

AH11

B27

U6

AD27

AD26

AC26

AC25

Y23

Y22

W23

AC24

W22

V23

V22

U23

U22

T28

T27

T26

T23

T22

AC23

R26

R25

R24

R23

R22

P23

P22

N23

N22

M23

AB23

M22

L23

L22

K23

K22

J23

J22

H23

H22

G23

AB22

G22

F24

F23

E26

E25

E24

D28

D27

D26

AD28

AA23

AA22

AB10

AH5

AG5

AF6

AF5

AE6

AD6

J7

J6

H7

H6

A1

AC8

AB8

G17

F17

T7

AC7

AC17

AB17

AH9

AG9

AF9

AF10

AE10

AD10

AC10

AB9

AC6

AB7

P11

M18

M11

L18

L17

L16

L14

V18

L12

V17

V16

V14

V12

V11

U18

U11

T18

T11

P18

L11

AH26

AE26

AE23

F6

AD17

G10

U2100

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

SB: 4 OF 4

A.0.0

24 84

051-7150

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3

=PP1V05_S0_SB_CPU_IO

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

65C3

65C3

65B3

65B3

25D2

26D3

25D2

25C6

25C6

65D6

65C6

65C6

65C6

65C3

25B6

25A4

65B3

65B3

25B6

65C6

25B8

65C6

65C6

25B8

25C4

65B3

65B3

65D6

25B6

25B6

25B2

25C2

25D2

24A5

21D6

25A4

25B4

24B3

25C6

24B5

25D6

25D6

25A5

24B5

21C1

65D3

25C4

25D3

25D3

25C7

25D7

22C1

http://mycomp.su/x/

NC NC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ICH IO,LOGIC 1.5V PWR)

ICH VCCA3GP(VCC1_5_B BYPASS

PLACE < 2.54MM OF SB ON

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:
PLACE CAPS AT EDGE OF SB

ICH VCC3_3/VCCHDA BYPASS
(ICH INTEL HDA CORE 3.3V PWR)

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

PLACE C2500 & C2505-07 < 2.54MM OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCUSBPLL BYPASS
(ICH USB PLL 1.5V PWR)

(ICH DMI PLL 1.5V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AH11

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH USB CORE/VCC1_5_A BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS A1 ... J7

(ICH USB CORE 1.5V PWR)

(ICH LOGIC&IO 1.5V PWR)

ICH VCC1_5A BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH VCCSUS3_3 BYPASS
(ICH SUSPEND 3.3V PWR)

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN U6

PLACE CAP UNDER SB NEAR PINS V1,

PLACEMENT NOTE:

(ICH CORE 1.05V PWR)

ICH CORE/VCC1_05 BYPASS

PLACEMENT NOTE:

ICH V5REF BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

SB: 4 OF 4

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE:
PLACE CAPS NEAR PINS

FOR 270UF

PLACEHOLDER

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AG5

3.56MM ON PRIMARY NEAR PIN AG9

(ICH IO BUFFER 3.3V PWR)

NEAR PINS A5 ... G16

DISTRIBUTE IN PCI SECTION OF SB

A24 ... G19 AND P7 OF SB

(ICH PCI I/O 3.3V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH IDE/VCC3_3 BYPASS

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH SATA PLL 1.5V PWR)

ICH VCCSATAPLL BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

(ICH IO BUFFER 3.3V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACEMENT NOTE:

NEAR PINS D28, T28, AD28

PLACE C2520 NEAR PIN C1 OF SB

K3 ... N7 OF SB

PLACE CAPS NEAR PINS

(ICH SUSPEND USB 3.3V PWR)

ICH USB/VCCSUS3_3 BYPASS

AB8 AND AC8 OF SB

PLACE CAPS NEAR PINS

PLACEMENT NOTE:

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

3.56MM ON PRIMARY NEAR PIN AD2

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

V5, W2, OR W7

ICH VCCRTC BYPASS
(ICH RTC 3.3V PWR)

ICH VCC3_3 BYPASS

PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB

ICH VCC3_3 BYPASS

ICH VCC1_5_A/ARX BYPASS
(ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCCSUS3_3 BYPASS
(ICH SUSPEND 3.3V PWR)

ICH V5REF_SUS BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PLACEMENT NOTE:
PLACE C2504 < 2.54MM OF PIN F6 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2503 < 2.54MM OF PIN AD17 OF SB

PLACEMENT NOTE:

PLACE C2520 NEAR PIN E3 OF SB

ICH VCCDMIPLL BYPASS

SECONDARY SIDE OR 3.56MM ON PRIMARY

X5R

16V

10%

0.1UF

402

2

1

C2510

0

402

0.1UF

10%
16V
X5R

2

1

C2512

0

1

5%

1/10W
MF-LF

603

21

R2500

4.7UF

20%

6.3V
CERM
603

2

1

C2524

0.1UF

10%
16V
X5R
402

2

1

C2522

BAT54DW

SOT-363

5

6

1

D2502

BAT54DW

SOT-363

2

3

4

D2502

1206

0.28-OHM

21

L2507

CASE-B2

2.5V
POLY

220UF

20%

2

1

C2500

0.1UF

402

10%
16V
X5R

2

1

C2503

0

X5R

16V

10%

0.1UF

402

2

1

C2504

0

5%

MF-LF

1/16W

402

10

21

R2501

100-OHM-EMI

SM-3

21

L2500

0

0.1UF

10%
16V
X5R
402

2

1

C2505

X5R

16V

10%

0.1UF

402

2

1

C2506

0.1UF

16V

10%
X5R

402

2

1

C2507

0.01UF

10%
16V
CERM
402

2

1

C2501

603

10UF

20%

6.3V
X5R

2

1

C2508

0

10%
16V
X5R
402

0.1UF

2

1

C2509

0

X5R
402

16V

10%

0.1UF

2

1

C2511

0

0.1UF

402

X5R

16V

10%

2

1

C2517

0

0.1UF

10%
16V
X5R
402

2

1

C2513

0

0

402

6.3V
CERM

10%

1UF

2

1

C2514

0

0.1UF

10%
16V
X5R
402

2

1

C2520

402

X5R

16V

10%

0.1UF

2

1

C2515

0

0

CASE-C2

POLY

20%

2.5V

330UF

2

1

C2516

5%

1/16W

402

MF-LF

100

2

1

R2502

1UF

10%

6.3V
CERM
402

2

1

C2502

402

0.1UF

10%
16V
X5R

2

1

C2518

0

X5R

16V

10%

0.1UF

402

2

1

C2519

0

0.1UF

10%
16V

402

X5R

2

1

C2521

0

X5R

16V

10%

0.1UF

402

2

1

C2523

0

0.1UF

X5R

16V

10%

402

2

1

C2525

0

X5R

16V

10%

0.1UF

402

2

1

C2526

X5R

16V

10%

0.1UF

402

2

1

C2527

X5R

16V

10%

0.1UF

402

2

1

C2528

402

0.1UF

10%
16V
X5R

2

1

C2529

0

402

0.1UF

10%
16V
X5R

2

1

C2530

402

0.1UF

10%
16V
X5R

2

1

C2534

0

402

0.1UF

10%
16V
X5R

2

1

C2531

402

0.1UF

10%
16V
X5R

2

1

C2532

0

402

0.1UF

10%
16V
X5R

2

1

C2533

051-7150

8425

A.0.0

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

=PP5V_S0_SB

=PP3V3_S5_SB

=PP3V3_S0_SB

=PP5V_S5_SB

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCCLAN3_3

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S0_SB_VCC3_3

=PP3V3_S0_SB_VCC3_3_PCI

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP3V3_S0_SB_VCC3_3

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S0_SB_VCC3_3_IDE

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

=PP1V5_S0_SB_VCCUSBPLL

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PPVCORE_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB

65D3 23D8

65C3

65C3

23D4

26D3

65B3

65B3

25D2

25B6

65D6

24D5

23B7

65B3

24B3

65B3

65C6

65C3

65C6

25B8

65B3

65C6

25C6

24B3

65C6

24B3

65C6

65B3

65C6

24C3

65B3

65D6

65C6

65C6

22C1

24D5

24D5

65A1

23A7

22B5

65B1

21D6

24D3

24A3

24B3

24B5

24B5

24B3

24B5

24B5

24A5

25C8

24A5

24A3

24C3

24B5

24A5

21C1

24C3

24D3

24A5

25A8

http://mycomp.su/x/

IO

IO

IN

IN

IN

IN

IO
IO

IO

IO
IO

IO

OUT

OUT

IN

IN

OUT

IN

OUT

IN

NCNC

IN

OUT

OUT

IO

IO

IO
IO

IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Initial resistor values are based on CRB,
but may change after characterization.

fault protection for RTC battery.

for use as DVI_HPD in muxed graphics solution.

Pullup on SB_GPIO4 removed as it now defaults low

Platform Reset Connections

NC

518S0452

NOTE: R2607 and D2600 form the double-

NC

Silk: "SYS RST"

Unbuffered

NC

NC

SB RTC Crystal Circuit

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

This part is never stuffed,

NCNC

on the board to short or

LIO represents X loads (2?)

Hook to inverter PWM AND gate (except M59)
This RST is used to mask a glitch output from

the NB PWM output during reset.

On M59 this RST is used for layout reasons

Buffered

D3Cold Reset for GPU

to solder a reset button.

it provides a set of pads

RTC Battery Connector

MF-LF

5%

402

1/16W

20K

21

R2600

0.1UF

402

CERM

10V

20%

2

1

C2611

402

CERM

6.3V

10%

1UF

2

1

C2605

5%

1/16W

100K

MF-LF

402

OMIT

2

1

R2698

1M

402

MF-LF

1/16W

5%

2

1

R2606

MF-LF

10K

402

5%

1/16W

2

1

R2697

402

5%

MF-LF

1/16W

1K

12

R2607

12pF

CERM

402

5%

50V

21

C2608

CERM

12pF

50V

5%

402

21

C2609

SM-2

CRITICAL

32.768K

31

42

Y2600

0

402

MF-LF

1/16W

5%

21

R2610

10M

402

MF-LF

1/16W

5%

2

1

R2609

0.1UF

20%

CERM
402

10V

2

1

C2680

MF-LF
402

100K

1/16W

5%

2

1

R2680

5%

1/16W

402

0

MF-LF

21

R2681

1/16W
MF-LF

402

100

5%

21

R2683

MF-LF

0

1/16W

5%

402

21

R2684

0

402

MF-LF

1/16W

5%

21

R2685

MF-LF

402

5%

1/16W

0

21

R2682

1K

ITP

402

5%
1/16W
MF-LF

21

R2696

MC74VHC1G00

SC70-5

5

4

1

2

3

U2603

MC74VHC1G08

SC70

5

4

1

2

3

U2680

SC70

MC74VHC1G08

5

4

1

2

3

U2601

BAT54DW

SOT-363

2

5

3

6

4

1

D2600

BM02B-ACHKS-A-GAN-TF-LF

M-RT-SM

CRITICAL

2

1

4

3

J2600

100K

MF-LF
402

1/16W

5%

2

1

R2688

SC70

MC74VHC1G08

5

4

1

2

3

U2685

0.1UF

CERM

20%
10V

402

2

1

C2685

1/16W
MF-LF

5%

402

10K

2

1

R2686

5%
1/16W
MF-LF

402

0

21

R2687

402

5%
1/16W
MF-LF

1K

21

R2689

10%
50V

402

CERM

0.001UF

2

1

C2689

1/16W

402

MF-LF

5%

1.8K

2

1

R2611

0.1UF

402

CERM

10V

20%

2

1

C2607

402

MF-LF

1/16W

5%

10K

2

1

R2612

10K

5%
1/16W
MF-LF
402

2

1

R2622

8.2K

21

R2623

8.2K

21

R2624

8.2K

21

R2625

8.2K

21

R2626

8.2K

21

R2627

8.2K

21

R2628

8.2K

21

R2629

8.2K

21

R2630

8.2K

21

R2631

8.2K

21

R2632

8.2K

21

R2633

8.2K

21

R2634

8.2K

21

R2636

8.2K

21

R2637

8.2K

21

R2638

8.2K

21

R2639

8.2K

21

R2640

8.2K

21

R2642

402

6.3V

10%
CERM

1UF

2

1

C2610

SB Misc

26

051-7164 A.0.0

84

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

=GPU_HPD_ENABLE

MAKE_BASE=TRUE

GPU_SIGNAL_ENABLE

=PP3V3_S5_SB_PM

PLTRST_D3COLD_L

=GPU_DDC_ENABLE

PEG_RESET_L

=PP3V3_S0_RSTBUF

TP_GPU_D3COLD_RST_L

MAKE_BASE=TRUE

PLT_RST_L

=PP3V3_S0_RSTBUF

TPM_LRESET_L

PLTRST_D3COLD_IN_L

MAKE_BASE=TRUE

GPU_D3COLD_RESET_L

LIO_PLT_RESET_L

MAKE_BASE=TRUE

M59_INVERTER_PLT_RST_L

INVERTER_PLT_RST_L

PLTRST_D3COLD_IN_L

=PP3V3_S0_SB_PM

PCI_IRDY_L

PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L

PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L

INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3

=PP3V3_S0_SB_PCI

PPVBATT_G3C_RTC

VOLTAGE=3.3V

SB_RTC_X2

ENET_RST_L

MAKE_BASE=TRUE
VOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

PCI_LOCK_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PP3V3_S5_SB_RTC

=PP3V42_G3H_SB_RTC

PPVBATT_G3C_RTC_R

VOLTAGE=3.3V

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROK

MAKE_BASE=TRUE

VR_PWRGD_CK410_L

MAKE_BASE=TRUE

PM_SYSRST_L

SB_SM_INTRUDER_L

SB_RTC_X1

DEBUG_RST_L

SMC_LRESET_L

NB_RST_IN_L

VR_PWRGD_CK410

CK410_PD_VTT_PWRGD_L

SB_RTC_RST_L

SB_RTC_X1_R

XDP_DBRESET_L

=PP3V3_S0_SB_PM

PLT_RST_BUF_L

65D3

25A4

23D1

65A3

79A4

65A3

47C6

65B3

37D3

37C3

37D3

37D3

22B6

37D3

37C3

37C3

37D3

24B3

59C7

64B1

51B4

33A4

65B3

77B2

11B5

79A7

67A5

26B4

23C5

22A6

26B4

58B7

26C1

5C1

6C5

26A4

26B6

22A6

22A6

22A6

22A6

22B6

22B6

22B6

6B7

22A7

22A7

22A7

22A7

22A6

22A6

65B3

5A2

21D6

39C6

22A6

22A6

22A6

22A7

21D6

65D3

14B6

49D7

23C3 59C7

21D6

21D6

5C2

49C7

14B7

23C5

21D6

26B8

37A7