ANALOG DEVICES UG-366 Service Manual

Evaluation Board User Guide

UG-366

VIN

12 V

06388-016

One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: [phone] • Fax: [phone] • www.analog.com

Evaluation Board for PWM, Step-Down DC-to-DC Controller with

Margining and Tracking

INTRODUCTION

This data sheet describes the design, operation, and test of the

ADP1822 standard evaluation board. In all tests, the board is

operated from an input voltage range of 9 V to 15 V, and
generates up to 10 A at V
fixed at 300 kHz.

GENERAL DESCRIPTION

The ADP1822 is a versatile and inexpensive synchronous buck
PWM controller. The converter power input voltage range is
1 V to 24 V, while the ADP1822 controller is specified from

3.0 V to 5.5 V. The ADP1822 free-running frequency is logic­selectable at either 300 kHz or 600 kHz. Alternatively, it can be
synchronized to an external clock at any frequency between
300 kHz and 1.2 MHz. The internal gate drivers control an all
N-channel power stage to regulate a converter output voltage as
low as 0.6 V with up to 20 A load current.

The regulated output of the ADP1822 can track another power
supply and be dynamically adjusted up or down with the
margining control inputs of the controller.

= 1.8 V. The switching frequency is

OUT

The ADP1822 includes an adjustable soft start to limit input
inrush current and to facilitate sequencing. It provides current­limit and short-circuit protection, and a power-good logic output.

The ADP1822 is well suited for a wide range of power
applications, such as DSP and processor core power in
telecommunications, medical imaging, high performance
servers, and industrial applications.

SPECIFICATIONS

Table 1. Evaluation Board Specifications

Description Parameter

V

1.8 V

OUT

Frequency 300 kHz
Maximum I
Current Limit 15 A
High and Low Voltage Margining 5%

10 A

OUT

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.

Figure 1. ADP1822 Evaluation Board (ADP1822-EVALZ)

Rev. A | Page 1 of 16

UG-366 Evaluation Board User Guide

TABLE OF CONTENTS

Introduction ...................................................................................... 1

General Description ......................................................................... 1

Specifications ..................................................................................... 1

Revision History ............................................................................... 2

Test Instructions ............................................................................... 3

Component Selection ....................................................................... 4

Input Capacitor ............................................................................. 4

Output Inductor ........................................................................... 4

Output Capacitor .......................................................................... 4

MOSFET Selection ....................................................................... 4

Output Voltage .............................................................................. 5

Current Limit Set Resistor ........................................................... 5

REVISION HISTORY

12/11—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Changed EVAL-ADP1822 to ADP1822-E VAL .............. Universal

11/06—Revision 0: Initial Version

Setting the Soft Start .....................................................................5

Output Voltage Tracking ..............................................................5

Output Voltage Margining ...........................................................6

Control Loop Design and Equations ..............................................7

Power Stage Transfer Function ....................................................7

Control Circuit and Transfer Function ......................................7

Overall Loop Gain .........................................................................8

Test Results and Major Waveforms .................................................9

PCB Layout Guidelines .................................................................. 11

Evaluation Board Schematic and Layout..................................... 12

Ordering Information .................................................................... 14

Bill of Materials ........................................................................... 14

Rev. A | Page 2 of 16

Evaluation Board User Guide UG-366

TEST INSTRUCTIONS

Test instructions:

1. Make sure that Jumper 2 is open. Power on the board

(output voltage is at 1.8 V).

2. If Jumper 1 is shorted, replace the inductor to another

value to fit 600 kHz operation.

3. If Jumper 3 is shorted, the output high margining is at

1.89 V. If Jumper 4 is open, the output low margining is at

1.71 V.

4. Verify the output voltage tracking features when

connecting the external generator to the TRKN point.

5. Use the PWGD point for monitoring operation behavior.

Table 2. Jumper and Connector Descriptions

Name Description

M1 VIN
M2 GND In
M3 VIN
M4 GND Out
Jumper 1 Open: 300 kHz

Short: 600 kHz

Jumper 2 Open: enable the board

Short: disable the board

Jumper 3 Open: output voltage normal mode.

Short: active voltage margin

Jumper 4 Open: high margin

Short: low margin

Table 3. Margining Description

MAR MSEL Voltage Margin

Low (Jumper 3
open)

High (Jumper 3
shorted)

High (Jumper 3
shorted)

X None

High (Jumper 4
open)

Low (Jumper 4
shorted)

High margin (FB
connected to MUP)

Low margin (FB
connected to MDN)

Default
Status

Open

Open

Open

Open

Rev. A | Page 3 of 16

UG-366 Evaluation Board User Guide

)1( D

f

KI

V

L

SWCR

OUT

OUT

−=















+∆=∆

OUT

SW

L

OUT

Cf

ESRIV

8

1

up

OUT

OUT

min1OUT,

VV

LI

C

∆

∆

=

2

2

down

UTO

IN

OUT

min2OUT,

VVV

LI

C

∆−

∆

=

)(2

2

12

2

L

COUT

II∆

=

DSON

L

UTO

lowC

R

I

IDP















∆

+−=

12

)1(

2

2

,

SWGGG

fQVP =

2

)(

SW

FRLIN

T

fttIV

P+=

COMPONENT SELECTION

INPUT CAPACITOR

In continuous mode, the source current of the high-side
MOSFET is a square wave of duty cycle V

OUT/VIN

. To prevent
large voltage transients, use a low ESR input capacitor sized for
the maximum rms current. The maximum rms capacitor
current is given by I

√D(1 − D)

L

OUTPUT INDUCTOR

In high switching applications, if the inductor is too big, the
dI/dt is too low and cannot respond to load changes quickly. If
the inductor is too small, the output ripple would be high.
Therefore, if good transient response is needed, smaller
inductors and larger capacitors are better, within the constraint
of the maximum allowed ripple current in the capacitor and the
maximum dissipation of the core (core temperature).

The output inductor can be chosen according to the following
equation:

(1)

where:

is the output voltage.

V

OUT

I

is the rated output current.

OUT

K

is the ratio of current ripple, ΔIL/IO.

CR

f

is the switching frequency.

SW

D is the duty cycle

Generally, K

should be chosen around 20% ~ 40%.

cr

OUTPUT CAPACITOR

The selection of C
capacitance. The output voltage ripple can be approximated as

is determined by the ESR and the

OUT

(4)

where:

is the step load.

ΔI

OUT

ΔV

is the output voltage overshoot when the load is

up

stepped down.
ΔV

is the output voltage overshoot when the load is

down

stepped up.

V

is the input voltage.

IN

C

is the minimum capacitance according to the overshoot

OUT,min1

voltage ΔV

C

OUT,min2

voltage ΔV
Select an output capacitance that is greater than both C

and C

up.

is the minimum capacitance according to the overshoot

down.

OU T, min1

.

OU T, min2

Make sure that the ripple current rating of the output capacitors
is greater than the following current:

(5)

MOSFET SELECTION

The choice of MOSFET directly affects the dc-to-dc converter
performance. The MOSFET must have low on resistance
(R

) to reduce the conduction loss, and low gate charge to

DSON

reduce switching loss.
For the low-side (synchronous) MOSFET, the dominant loss is

the conduction loss. It can be calculated as

(6)

(2)

Generally, the voltage ripple caused by the capacitance or ESR
depends on the capacitor chosen.

ESR affects the output voltage ripple; thus, an MLCC capacitor
is recommended because of its low ESR.

During a load transient on the output, the amount of
capacitance needed is determined by the maximum energy
stored in the inductor. The capacitance must be sufficient to
absorb the change in inductor current when a high current to
low current transition occurs and to supply the load when a low
current to high current transition occurs.

(3)

The gate charge loss is approximated by the following equation:

where:

V

G

Q

G

The high-side (switching) MOSFET has to be able to handle
conduction loss and switching loss. The high-side MOSFET
switching loss is approximated by the equation

where t

Rev. A | Page 4 of 16

(7)

is the driver voltage.
is the MOSFET total gate charge.

(8)

and tF are the rise and fall times of the MOSFET.

R

Evaluation Board User Guide UG-366

G

SPG

GD

GS

R

R

VV

Q

Q

t

−

+

=

2

G

SP

GD

GS

F

R

V

Q

Q

t+=

2

m

UTO

TH

SP

g

I

VV +≈

DSON

L

OUT

highC

R

I

IDP















∆

+=

12

2

2

,

6.0

6.0−

=

OUT

V

RR 21

( )

lowDSON

L

L

lowDSON

CSLCSL

CSL

R

I

IRRIV

__

2











∆

+−+=

CSL

lowDSON

L

CSL

I

R

I

I

R

_

2











∆

+

=

limit

kΩ100

8.0

6.0

1ln ×











−−

=

SS

SS

t

C

tR and tF can be calculated using

and

where:

and Q

Q

GS

R

is the gate resistance

G

V

is approximated using

SP

are provided in the MOSFET data sheet.

GD

In normal operation, the direction of current flow through the
low-side FET causes a negative voltage to appear on its drain.
This voltage is V = IR, where I is the instantaneous FET current
and R is its R

. A +42 μA current source at the ADP1822

DSON

CSL pin causes a fixed voltage drop in the current sense resistor
that is connected from the CSL pin to the drain of the low-side
FET. This current through the current limit set resistor produces
a voltage in the opposite direction, thus raising (in the positive
direction) the potential at the CSL pin. The resulting net voltage
on the CSL pin is compared with ground. During normal
operation, the CSL pin stays above ground potential. The
overcurrent protection circuitry is triggered when increased
FET current produces increased negative voltage on the low­side MOSFET drain, thus causing the voltage on the CSL pin to
go negative with respect to ground.

Therefore, the resistor R

can be calculated from the following

CSL

equation:

where g

is the MOSFET transconductance.

m

The high-side MOSFET conduction loss can be calculated as

(9)

OUTPUT VOLTAGE

The regulation threshold at the FB pin is 0.6 V, and t he
maximum input bias current is 100 nA. This bias current can
introduce significant error if the divider impedance is too high.
In order to get the best accuracy, the bottom resistor, R2, should
be no higher than 50 kΩ. On the other hand, very low values of
R2 will dissipate excess power. For R2, a 1% resistor with a value
between 1 kΩ and 10 kΩ is recommended.

The upper divider is then set using the following formula (it
should also be a 1% type):

(10)

CURRENT LIMIT SET RESISTOR

The voltage on the CSL pin can be calculated by the following
formula:

(11)

where:

is the voltage on the CSL pin.

V

CSL

I

is the current out from the CSL pin, I

CSL

R

is the current limited resistor.

CSL

R
I
ΔI

is the conduction resistor of the lower side MOSFET.

DSON_low

is the output current.

L

is the output current ripple.

L

= 42 μA.

CSL

(12)

SETTING THE SOFT START

The soft start characteristic is set by the capacitor connected
from SS to GND. The ADP1822 charges C
internal resistor. The soft start period (t
V

= 0.6 V.

CSS

to 0.8 V through an

SS

) is achieved when

SS

(13)

where 100 kΩ is the internal resistor.

OUTPUT VOLTAGE TRACKING

The ADP1822 features an internal comparator that forces the
output voltage to track an external voltage at startup, which
prevents the output voltage from exceeding the tracking voltage.

The comparator turns off the high-side switch if the positive
tracking (TRKP) input voltage exceeds the negative tracking
(TRKN) input voltage. Connect TRKP to the output voltage and
drive TRKN with the voltage to be tracked. If the voltage at
TRKN is below the regulation voltage, the output voltage at
TRKN is below the regulation voltage, and the output voltage is
limited to the voltage at TRKN. If the voltage at TRKN is above
the regulation voltage, the output voltage regulates the desired
voltage set by the voltage divider.

Rev. A | Page 5 of 16