ANALOG DEVICES UG-350 Service Manual
EVAL-AD5233SDZ User Guide
One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : 781.329.4700 • Fax: 781.461.3113 • www.analog.com
UG-350
Evaluation Board for the AD5233 Digital Potentiometer
FEATURES
Full featured evaluation board for the AD5233
Several test circuits
Various ac/dc input signals
PC control via a separately purchased system demonstration
platform (SDP-B)
PC control software
12 extra bytes in EEMEM for user-defined information
Resistor tolerance error stored in EEMEM
PACKAGE CONTENTS
EVAL-AD5233SDZ board
CD that includes
Self-installing software that allows users to control the
board and exercise all functions of the device
Electronic version of the AD5233 data sheet
Electronic version of the UG-350 user guide
GENERAL DESCRIPTION
This user guide describes the evaluation board for evaluating the
AD5233—a quad-channel, 64-position, nonvolatile memory
digital potentiometer. With versatile programmability, the AD5233
allows multiple modes of operation, including read/write access
in the RDAC and EEMEM registers, increment/decrement of
resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information,
such as memory data for other components or a lookup table.
The AD5233 supports dual-supply ±2.5 V to ±2.75 V operation
and single-supply 2.7 V to 5.5 V operation, making the device
suited for batter y-powered applications and many other applications. In addition, the AD5233 uses a versatile SPI-compatible
serial interface, allowing speeds of up to 50 MHz.
The EVAL-AD5233SDZ can operate in single-supply and dual-
supply mode and incorporates an internal power supply from
the USB.
Complete specifications for the AD5233 part can be found in
the AD5233 data sheet, which is available from Analog Devices,
Inc., and should be consulted in conjunction with this user
guide when using the evaluation board.
DIGITAL PICTURE OF EVALUATION BOARD WITH SYSTEM DEMONSTRATION PLATFORM
SYSTEM DEMONSTRATION
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
PLATFORM
EVAL-AD5233SDZ
Figure 1.
Rev. 0 | Page 1 of 16
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UG-350 EVAL-AD5233SDZ User Guide
TABLE OF CONTENTS
Features.............................................................................................. 1
Package Contents.............................................................................. 1
General Description ......................................................................... 1
Digital Picture of Evaluation Board with System Demonstration
Platform ............................................................................................. 1
Revision History ............................................................................... 2
Evaluation Board Hardware............................................................ 3
Power Supplies .............................................................................. 3
Link Options ................................................................................. 3
REVISION HISTORY
12/11—Revision 0: Initial Version
Test Circuits ...................................................................................4
Evaluation Board Software...............................................................6
Installing the Software..................................................................6
Running the Software ...................................................................6
Software Operation.......................................................................7
Evaluation Board Schematics and Artwork...................................8
Ordering Information.................................................................... 14
Bill of Materials........................................................................... 14
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EVAL-AD5233SDZ User Guide UG-350
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5233SDZ supports the use of single and dual
power supplies.
In single-supply mode, the evaluation board can be powered
either from the SDP port or externally by the J1-1, J1-2, and
J1-3 connectors, as described in Ta bl e 1.
If dual-supply mode is required, the J1-1, J1-2, and J1-3 connectors
must provide the external power supply, as described in Ta b le 1 .
All supplies are decoupled to ground using 10 μF tantalum and
0.1 μF ceramic capacitors.
Table 1. Maximum and Minimum Voltages of the Connectors
Connector No. Label Voltage
J1-1 EXT VDD Analog positive power supply, VDD.
J1-2 GND Analog ground.
J1-3 EXT VSS Analog negative power supply, VSS.
For single-supply operation, it is 0 V.
For single-supply operation, it is
2.7 V to 5.5 V.
For dual-supply operation, it is
2.5 V to 2.75 V.
For dual-supply operation, it is
−2.5 V to −2.75 V.
LINK OPTIONS
Several link and switch options are incorporated in the evaluation board and should be set up before using the board. Tab l e 2
describes the positions of the links to control the evaluation board
by a PC, via the SDP-B board, using the EVAL-AD5233SDZ in
single-supply mode. The functions of these link and switch
options are described in detail in Tab l e 3 through Table 6 .
Table 2. Link Options Setup for SDP-B Control (Default)
Link No. Option
A25 3.3 V
A24 GND
Table 3. Link Functions
Link No. Power Supply Options
A25 VDD This link selects one of the following as the positive power supply:
5 V (from SDP-B).
3.3 V (from SDP-B).
EXT VDD (external supply from the J1-1 connector).
A24 VSS This link selects one of the following as the negative power supply:
GND (analog ground).
EXT VSS (external supply from the J1-3 connector).
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UG-350 EVAL-AD5233SDZ User Guide
A
V
V
TEST CIRCUITS
The EVAL-AD5233SDZ incorporates several test circuits to
evaluate the AD5233 performance.
DAC
RDAC1 can be operated as a digital-to-analog converter (DAC),
as shown in Figure 2.
AC + DC
– V
V
DD
SS
2
– V
V
DD
2
Tabl e 4 shows the options available for the voltage references.
Table 4. DAC Voltage References
Terminal Link Options Description
A1 A20 AC + DC
VDD Connects Terminal A1 to VDD
W1 BUF-W1
B1 A21 DC
VSS Connects Terminal B1 to VSS
GND
The output voltage is defined in Equation 1.
OUT
where:
RDAC1 is the code loaded in the RDAC1 register.
V
is the voltage applied to the A1 terminal (A20 link).
A1
V
is the voltage applied to the B1 terminal (A21 link).
B1
Using the R34 and R35 external resistors, the user can reduce
the voltage of the voltage references. In this case, use the A1 and
B1 test points to measure the voltage applied to the A1 and B1
terminals and recalculate V
AC Signal Attenuation
RDAC1 can be used to attenuate an ac signal, which must be
provided externally using the AC_INPUT connector, as shown
in Figure 3.
VDD
V
DD
RDAC1
DC
SS
VSS
V
SS
GND
A1
R34
W1
R35
W1
B1
BUF-W1
W1_BUF
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A1
B1
Figure 2. DAC
Connects Terminal A1 to
− VSS)/2
(V
DD
Connects Terminal W1 to an
output buffer
Connects Terminal B1 to
− VSS)/2
(V
DD
Connects Terminal B1 to
analog ground
1
RDAC
×−=
)(
VVV
B1
A1
(1)
64
and VB1 in Equation 1.
A1
–
DD
SS
2
C_INPUT
1µF
V
DD
– V
2
AC + DC
AC
A1
R34
RDAC1
A1
B1
DC
SS
VSS
V
SS
GND
W1
R35
W1
BUF-W1
R36
B1
W1_BUF
Figure 3. AC Signal Attenuator
Depending on the voltage supply rails and the dc offset voltage
of the ac signal, various configurations can be used, as described
in Tabl e 5.
Table 5. AC Signal Attenuation Link Options
Maximum
Voltage
Supply
AC Signal
Amplitude Link Options Conditions
Single VDD A20 AC + DC No dc offset voltage.
AC signal is outside
the voltage supply
rails due to the
dc offset voltage.
DC offset voltage
/2.1
≠ V
DD
AC All other conditions.
A21 DC
Use in conjunction
with AC + DC link.
GND All other conditions.
Dual VDD/VSS A20 AC + DC
AC signal is outside
the voltage supply
rails due to the
dc offset voltage.
DC offset voltage
1
≠ 0 V.
AC All other conditions.
A21 GND
Use in conjunction
with AC + DC link.
VSS All other conditions.
1
Recommended to ensure optimal total harmonic distortion (THD) performance.
The signal attenuation is defined in Equation 2.
nAttenuatio log20)dB(
⎛
⎜
×=
⎜
R
⎝
⎞
RR
+
WWB1
⎟
(2)
⎟
−− ENDTOEND
⎠
where:
R
is the resistor between the W1 and B1 terminals.
WB1
R
is the wiper resistance.
W
R
END-TO-END
is the end-to-end resistance value.
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EVAL-AD5233SDZ User Guide UG-350
In addition, R36 can be used to achieve a pseudologarithmic
attenuation. To do so, adjust the R36 resistor until a desirable
transfer function is found.
Signal Amplifier
RDAC2 can be operated as an inverting or noninverting signal
amplifier supporting linear or pseudologarithmic gains. Tabl e 6
shows the available configurations.
Table 6. Amplifier Selection Link Options
Amplifier Gain Link Label1
Noninverting Linear A27 LINEAR
A29 NON-INVERTING
A30 NON-INVERTING
Pseudologarithmic A27 PSEUDOLOG
A29 NON-INVERTING
A30 NON-INVERTING
Inverting Linear A27 LINEAR
A29 INVERTING
A30 INVERTING
Pseudologarithmic A27 PSEUDOLOG
A29 INVERTING
A30 INVERTING
1
See Figure 17.
The noninverting amplifier with linear gain is shown in Figure 4,
and the gain is defined in Equation 3.
R
WB2
G
where R
1+=
WB2
(3)
R38
is the resistor between the W2 and B2 terminals.
R41
R38
2.7kΩ
W2
1.7kΩ
W2
RDAC2
V
OUT
OAVOUTC1
10nF
B2
R42
B2
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V
IN
Figure 4. Linear Noninverting Amplifier
The noninverting amplifier with pseudologarithmic gain is
shown in Figure 5, and the gain is defined in Equation 4.
R
2
G += (4)
WB
1
R
2
AW
where:
R
is the resistor between the W2 and B2 terminals.
WB2
R
is the resistor between the A2 and W2 terminals.
AW 2
R41
R43
1.7kΩ
IN
W2
A2
W2
RDAC2
10nF
B2
B2A2
C1
R42
V
OUT
OAVOUT
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Rev. 0 | Page 5 of 16
V
Figure 5. Pseudologarithmic Noninverting Amplifier
R43 and R42 can be used to set the maximum and minimum
gain limits.
The inverting amplifier with linear gain is shown in Figure 6,
and the gain is defined in Equation 5.
R
WB2
G
where R
WB2
(5)
−=
R38
is the resistor between the W2 and B2 terminals.
R41
1.7kΩ
R38
2.7kΩ
V
IN
W2
W2
RDAC2
10nF
B2
B2
C1
R42
V
OUT
OAVOUT
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Figure 6. Linear Inverting Amplifier
The inverting amplifier with pseudologarithmic gain is shown
in Figure 7, and the gain is defined in Equation 6.
R
2
G −= (6)
WB
R
2
AW
where:
is the resistor between the W2 and B2 terminals.
R
WB2
R
is the resistor between the A2 and W2 terminals.
AW 2
R41
1.7kΩ
V
OUT
C1
W2
W2
A2
R43
V
IN
RDAC2
B2
B2A2
10nF
R42
OAVOUT
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Figure 7. Pseudologarithmic Inverting Amplifier
R43 and R42 can be used to set the maximum and minimum
gain limits.
Output Buffers
RDAC3 and RDAC4 can be connected to an output buffer as
shown Figure 8 and Figure 9, respectively.
A3
RDAC3
A3
B3
RDAC4
A4
B4
W3
B3
A4
W4
B4
W3
BUF_3
Figure 8. RDAC3
W4
BUF_4
Figure 9. RDAC4
VOUT3
VOUT4
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