ANALOG DEVICES ssm2305 Service Manual

Filterless High Efficiency

*

V

Mono 2.8 W Class-D Audio Amplifier

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers

from Analog Devices, Inc.

2.8 W into 4 Ω load and 1.6 W into 8 Ω load at 5.0 V supply
with <10% total harmonic distortion (THD)

89% efficiency at 5.0 V, 1.3 W into 8 Ω speaker
>98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2305 is a fully integrated, high efficiency, Class-D
audio amplifier designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 2.2 W of continuous output
power with less than 1% THD + N driving a 4 Ω load from a

5.0 V supply. It has built-in thermal shutdown and output short-

circuit protection.

SSM2305

The SSM2305 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modu­lation provides high efficiency even at low output power. The
SSM2305 operates with 90% efficiency at 1.3 W into 8 Ω or 83%
efficiency at 2.2 W into 4 Ω from a 5.0 V supply and has an SNR of
>98 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.

The SSM2305 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a Logic 0 to the
suppression circuitry. This minimizes voltage glitches at the
output during turn-on and turn-off, thus reducing audible noise
on activation and deactivation.

The fully differential input of the SSM2305 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V

The SSM2305 has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 60 dB at 217 Hz.

The default gain of the SSM2305 is 18 dB, but users can reduce the
gain by using a pair of external resistors.

The SSM2305 is specified over the commercial temperature range
(−40°C to +85°C). It is available in both an 8-lead, 3 mm ×
3 mm lead frame chip scale package (LFCSP) and an 8-lead
mini small outline package (MSOP).

SD

pin. The device also includes pop-and-click

/2.

DD

FUNCTIONAL BLOCK DIAGRAM

10µF

SSM2305

AUDIO IN+

AUDIO IN–

SHUTDOWN

INPUT CAPACIT ORS ARE OPTI ONAL IF INPUT DC COMM ON-MODE VOLTAGE IS
APPROXIMATELY

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

47nF*

47nF*

37kΩ

IN+

37kΩ

IN–

SD

/2.

DD

296kΩ

MODULATOR

(Σ-Δ)

296kΩ

BIAS

Figure 1.

0.1µF

VDD

FET

DRIVER

INTERNAL

OSCILLAT OR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

POP/CLICK

SUPPRESSION

GND

VBATT

2.5V TO 5. 5V

OUT+

OUT–

07243-001

SSM2305

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information .............................................................. 11

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

7/08—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Change to Shutdown Current Parameter, Table 1 ........................ 3

Change to Differential Input Impedance Parameter, Table 1 ..... 3

Added Exposed Pad Notation to Figure 2 ..................................... 5

Change to Figure 24 ......................................................................... 9

Changes to Figure 32 and Figure 33 ............................................. 11

Changes to Gain Section ................................................................ 12

Updated Outline Dimensions ....................................................... 14

3/08—Revision 0: Initial Version

Overview ..................................................................................... 11

Gain .............................................................................................. 12

Pop-and-Click Suppression ...................................................... 12

Output Modulation Description .............................................. 12

Layout .......................................................................................... 12

Input Capacitor Selection .......................................................... 12

Proper Power Supply Decoupling ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

SSM2305

SPECIFICATIONS

VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

R
R
R
R
R
R
R
Efficiency η PO = 1.3 W, 8 Ω 89 %
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz 0.02 %
P
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRR
Average Switching Frequency fSW 280 kHz
Differential Output Offset Voltage V

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating 70 85 dB
PSRR
Supply Current I

SY

V
V
V
V
V
Shutdown Current ISD

GAIN CONTROL

Closed-Loop Gain Av 18 dB
Differential Input Impedance Z

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Wake-Up Time t
Shutdown Time t

Output Impedance Z

IH

IL

WU

SD

OUT

NOISE PERFORMANCE

Output Voltage Noise en

Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 98 dB

RL = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 1.34 W

= 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.68 W

L

= 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 1.67 W

L

= 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 0.85 W

L

= 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz 2.22 W

L

= 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.1 W

L

= 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz 2.8 W

L

= 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V 1.3 W

L

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.02 %

O

GSM VCM

= 2.5 V ± 100 mV at 217 Hz, output referred 55 dB

G = 18 dB 2.0 mV

Guaranteed from PSRR test 2.5 5.5 V

GSM VRIPPLE

= 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF 60 dB

VIN = 0 V, no load 3.2 mA

= 0 V, 3.3 mA

IN

= 0 V, no load, VDD = 3.6 V 2.8 mA

IN

= 0 V, VDD = 3.6 V 2.9 mA

IN

= 0 V, no load, VDD = 2.5 V 2.4 mA

IN

= 0 V, VDD = 2.5 V 2.4 mA

IN

= GND

SD

SD = VDD

20 30 nA

37 kΩ

ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD rising edge from GND to VDD
SD falling edge from VDD to GND

= GND

SD

= 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,

V

DD

= 18 dB, A-weighted

A

V

30 ms
5 μs
>100 kΩ

40 μV

Rev. A | Page 3 of 16

SSM2305

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at TA = 25°C, unless other­wise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3.

Package Type θJA θJC Unit

8-Lead, 3 mm × 3 mm LFCSP 62 20.8 °C/W
8-Lead MSOP 210 45 °C/W

ESD CAUTION

Rev. A | Page 4 of 16

SSM2305

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2NC

3IN+

(Not to Scale)

4IN–

PIN 1
INDICAT OR

SSM2305

TOP VIEW

8OUT–

7GND

6VDD

5OUT+

SD

1

2

NC

3

IN+

(Not to S cale)

IN–

4

07243-002

NC = NO CONNECT

Figure 3. MSOP Pin Configuration

SD 1

NOTES:

1. NC = NO CONNECT .

2. EXPOSED P AD IS NOT CO NNECTED INTERNALLY.
FOR INCREASED REL IABILI TY OF T HE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILIT Y IT
IS RECOMMENDED THAT THE PAD BE SOLDERED

TO THE GRO UND PLANE.

Figure 2. LFSCP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

SD

Shutdown Input. Active low digital input.
2 NC No Connect. This pin has no function; tie it to GND.
3 IN+
4 IN−
5 OUT+
6 VDD
7 GND

Noninverting Input.

Inverting Input.

Noninverting Output.

Power Supply.

Ground.
8 OUT− Inverting Output.

SSM2305

TOP VIEW

OUT–

8

7

GND

6

VDD

OUT+

5

07243-103

Rev. A | Page 5 of 16