Filterless High Efficiency
www.BDTIC.com/ADI
FEATURES
Filterless Class-D amplifier with built-in output stage
1.4 W into 8 Ω at 5.0 V supply with less than 1% THD
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 16-lead, 3 mm × 3 mm LFCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2302 is a fully integrated, high efficiency, Class-D stereo
audio amplifier. It is designed to maximize performance for
mobile phone applications. The application circuit requires a
minimum of external components and operates from a single
2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of continuous output power with less than 1% THD + N driving an
8 Ω load from a 5.0 V supply.
The SSM2302 features a high efficiency, low noise modulation
cheme. It operates with 85% efficiency at 1.4 W into 8 Ω from a
s
FUNCTIONAL BLOCK DIAGRAM
Class-D Stereo Audio Amplifier
SSM2302
5.0 V supply and has a signal-to-noise ratio (SNR) that is better
than 98 dB. PDM modulation is used to provide lower EMIradiated emissions compared with other Class-D architectures.
The SSM2302 has a micropower shutdown mode with a typical
utdown current of 20 nA. Shutdown is enabled by applying a
sh
pin.
SD
/2.
DD
VBATT
2.5V TO 5. 0V
mmercial temperature range
10µF
logic low to the
The architecture of the device allows it to achieve a very low level
f pop and click. This minimizes voltage glitches at the output
o
during turn-on and turn-off, thus reducing audible noise on
activation and deactivation.
The fully differential input of the SSM2302 provides excellent
r
ejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V
The SSM2302 also has excellent rejection of power supply noise,
in
cluding noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 63 dB at 217 Hz.
The gain can be set to 6 dB or 12 dB utilizing the gain control
elect pin connected respectively to ground or V
s
also be adjusted externally by using an external resistor.
The SSM2302 is specified over the co
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm
lead-frame chip scale package (LFCSP).
0.1µF
. Gain can
DD
SSM2302
1
0.01µF
0.01µF
0.01µF
0.01µF
INR+
INR–
1
SD
GAIN
1
INL+
INL–
1
GAIN
CONTROL
GAIN
CONTROL
/2.
DD
BIAS
RIGHT IN+
RIGHT IN–
SHUTDOWN
GAIN
LEFT IN+
LEFT IN–
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VDDVDD
OUTR+
MODULATOR
INTERNAL
OSCILLAT OR
MODULATOR
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
DRIVER
DRIVER
GNDGND
FET
FET
OUTR–
OUTL+
OUTL–
06051-001
SSM2302
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Pop-and-Click Suppression ...................................................... 12
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Typical Application Circuits............................................................ 9
Application Notes........................................................................... 12
Overview...................................................................................... 12
Gain Selection ............................................................................. 12
EMI Noise.................................................................................... 12
Layout .......................................................................................... 13
Input Capacitor Selection.......................................................... 13
Proper Power Supply Decoupling............................................ 13
Evaluation Board Information...................................................... 14
Introduction................................................................................ 14
Operation .................................................................................... 14
SSM2302 Application Board Schematic.................................. 15
SSM2302 Stereo Class-D Amplifier Evaluation Module
Component List.......................................................................... 16
SSM2302 Application Board Layout........................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
SSM2302
www.BDTIC.com/ADI
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power P
O
R
R
R
R
R
Efficiency η P
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V 0.1 %
P
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRR
Channel Separation
X
TAL K
Average Switching Frequency fSW 1.8 MHz
Differential Output Offset Voltage V
OOS
POWER SUPPLY
Supply Voltage Range V
DD
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, 50 Hz, input floating/ground 70 85 dB
PSRR
Supply Current I
SY
V
V
Shutdown Current ISD
GAIN CONTROL
Closed-Loop Gain Av0 GAIN pin = 0 V 6 dB
Av1 GAIN pin = VDD 12 dB
Differential Input Impedance Z
IN
SHUTDOWN CONTROL
Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t
Output Impedance Z
IH
IL
WU
SD
OUT
NOISE PERFORMANCE
Output Voltage Noise en
Signal-to-Noise Ratio SNR P
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.4 W
= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.615 W
L
= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.275 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.53 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.77 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.35 W
L
=1.4 W, 8 Ω, VDD = 5.0 V 85 %
OUT
= 0.5 W into 8 Ω each channel, f = 1 kHz, VDD = 3.6 V 0.04 %
O
GSM VCM
= 2.5 V ± 100 mV at 217 Hz 55 dB
PO = 100 mW , f = 1 kHz 98 dB
G = 6 dB; G = 12 dB 2.0 mV
Guaranteed from PSRR test 2.5 5.0 V
GSM
V
= 100 mV at 217 Hz, inputs ac GND,
RIPPLE
= 0.01 μF, input referred
C
IN
63 dB
VIN = 0 V, no load, VDD = 5.0 V 8.0 mA
= 0 V, no load, VDD = 3.6 V 6.6 mA
IN
= 0 V, no load, VDD = 2.5 V 5.3 mA
IN
SD
= GND
SD
= VDD,
SD
= GND
20 nA
150 KΩ
210 KΩ
ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD
rising edge from GND to VDD
SD
falling edge from VDD to GND
SD
= GND
= 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are
V
DD
ac grounded, sine wave, A
= 1.4 W, RL = 8 Ω 98 dB
OUT
= 6 dB, A weighting
V
30 ms
5 μs
>100 KΩ
35 μV
Rev. 0 | Page 3 of 20
SSM2302
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature Range
(Soldering, 60 sec)
DD
DD
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
16-lead, 3 mm × 3 mm LFCSP 44 31.5 °C/W
Unit
JC
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 20
SSM2302
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
GND
VDD
GND
14
13
15
16
PIN 1
INDICATOR
1OUTL+
2OUTL–
SSM2302
3SD
TOP VIEW
(Not to Scale)
4INL+
5
6
NC
INL–
NC = NO CO NNECT
Figure 2. SSM2302 LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 OUTL+ Inverting Output for Left Channel.
2 OUTL− Noninverting Output for Left Channel.
3
SD
Shutdown Input. Active low digital input.
4 INL+ Noninverting Input for Left Channel.
5 INL− Inverting Input for Left Channel.
6 NC No Connect.
7 NC No Connect.
8 INR− Inverting Input for Right Channel.
9 INR+ Noninverting Input for Right Channel.
10 GAIN Gain Selection. Digital input.
11 OUTR− Noninverting Output for Right Channel.
12 OUTR+
Inverting Output for Right Channel.
13 GND Ground for Output Amplifiers.
14 VDD Power Supply for Output Amplifiers.
15 VDD Power Supply for Output Amplifiers.
16 GND Ground for Output Amplifiers.
12 OUTR+
11 OUT R–
10 GAIN
9 INR+
8
7
C
N
INR–
06051-002
Rev. 0 | Page 5 of 20
SSM2302
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
100
RL = 8Ω, 33µH
GAIN = 12dB
10
VDD = 2.5V
100
10
VDD = 3.6V
R
L
1
= 8Ω, 33µH
1
THD + N (%)
0.1
0.01
0.000001 0.00010.00001 10
OUTPUT PO WER (W)
Figure 3. THD + N vs. Output Power into 8 Ω, A
100
RL = 8Ω, 33µH
GAIN = 6dB
10
1
THD + N (%)
0.1
0.01
0.000001 0.0001
0.0000001
0.00001 10
OUTPUT PO WER (W)
Figure 4. THD + N vs. Output Power into 8 Ω, A
VDD = 3.6V
0.001 0.01 0.1 1
= 12 dB
V
VDD = 2.5V
VDD = 3.6V
0.01
0.001
0.1
= 6 dB
V
VDD = 5V
VDD = 5V
1
0.1
THD + N (%)
0.01
250mW
0.001
0.0001
10 100k
06051-003
Figure 6. THD + N vs. Frequency, V
100
VDD = 2.5V
= 8Ω, 33µH
R
L
10
1
0.1
THD + N (%)
125mW
0.01
0.001
0.0001
10 100k
06051-004
Figure 7. THD + N vs. Frequency, V
500mW
125mW
100 1k 10k
FREQUENCY (Hz)
= 3.6 V
DD
250mW
75mW
100 1k 10k
FREQUENCY (Hz)
= 2.5 V
DD
06051-006
06051-007
100
VDD = 5V
R
= 8Ω, 33µH
L
10
1
0.1
THD + N (%)
0.01
0.5W
0.001
0.0001
10 100k
Figure 5. THD + N vs. Frequency, V
1W
0.25W
100 1k 10k
FREQUENCY (Hz)
= 5.0 V
DD
06051-005
Rev. 0 | Page 6 of 20
9
8
7
6
5
4
3
SUPPLY CURRENT (mA)
2
1
0
3.0 3.5 4.0 4.5 5.0
2.5 5.5
SUPPLY VOLTAGE (V)
Figure 8. Supply Current vs. Supply Voltage, No Load
06051-008
SSM2302
www.BDTIC.com/ADI
12
10
8
VDD = 5V
6
4
SHUTDOWN CURRENT (µA)
2
0
0.1 0. 2 0.3 0.4 0.5 0.6 0.7
00
SHUTDOWN VOL TAGE (V)
VDD = 2.5V
VDD = 3.6V
.8
06051-009
Figure 9. Supply Current vs. Shutdown Voltage
1.0
VDD = 3.6V
R
= 8Ω, 33µH
0.9
L
0.8
0.7
0.6
0.5
0.4
0.3
POWER DISSI PATION (W )
0.2
0.1
0
00.8
0.1 0. 2 0.3 0.4 0.5 0.6 0.7
OUTPUT PO WER (W)
Figure 12. Power Dissipation vs. Output Power at V
= 3.6 V
DD
06051-012
1.6
f
= 1kHz
GAIN = 2
1.4
= 8Ω, 33µH
R
L
1.2
1.0
0.8
0.6
OUTPUT POW ER (W)
0.4
0.2
0
2.5 5.0
3.0 3. 5 4.0 4.5
10%
1%
SUPPLY VOLTAGE (V)
06051-010
Figure 10. Maximum Output Power vs. Supply Voltage
100
90
VDD = 2.5V
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
01
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
VDD = 3.6V
OUTPUT PO WER (W)
RL = 8Ω, 33µH
VDD = 5V
.4
06051-011
Figure 11. Efficiency vs. Output Power into 8 Ω
1.8
VDD = 5V
= 8Ω, 33µH
R
L
1.6
1.4
1.2
1.0
0.8
0.6
POWER DISSI PATION ( W)
0.4
0.2
0
01
0.1 0.2 0.3 0.4 0.5 0.6 0. 7 0.8 0.9 1.0 1.1 1.2
Figure 13. Power Dissipation vs. Output Power at V
400
RL = 8Ω, 33µH
350
300
250
200
= 2.5V
V
DD
150
SUPPLY CURRENT (mA)
100
50
0
0.2 0. 4 0.6 0.8 1.0 1.2 1.4
01.6
Figure 14. Output Power vs. Supply Current, One Channel
OUTPUT PO WER (W)
VDD = 3.6V
OUTPUT PO WER (W)
.3
06051-013
= 5.0 V
DD
= 5V
V
DD
06051-014
Rev. 0 | Page 7 of 20
SSM2302
www.BDTIC.com/ADI
0
–10
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
10 100k
Figure 15. Power Supply Rejecti
0
RL = 8Ω, 33µH
GAIN = 6dB
–10
–20
–30
–40
CMRR (dB)
–50
–60
–70
–80
10 100k
Figure 16. Common-Mode Rejectio
100 1k 10k
FREQUENCY (Hz)
on Ratio vs. Frequency
100 1k 10k
FREQUENCY (Hz)
n Ratio vs. Frequency
06051-015
06051-016
7
6
5
4
SD INPUT
3
2
VOLTAGE
1
0
–1
–2
–5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
–10 90
OUTPUT
TIME (ms)
Figure 18. Turn-On Response
7
6
5
SD INPUT
4
3
2
VOLTAGE
1
0
–1
–2
0 20 40 60 80 100 120 140 160
–20 180
OUTPUT
TIME (ms)
Figure 19. Turn-Off Response
06051-018
06051-019
0
VDD = 3.6V
= 1V rms
V
RIPPLE
–20
= 8Ω, 33µH
R
L
–40
–60
–80
CROSSTALK (dB)
–100
–120
–140
10 100k
100 1k 10k
FREQUENCY (Hz)
06051-017
Figure 17. Crosstalk vs. Frequency
Rev. 0 | Page 8 of 20
SSM2302
www.BDTIC.com/ADI
TYPICAL APPLICATION CIRCUITS
0.1µF
MODULATOR
INTERNAL
OSCILLAT OR
MODULATOR
VBATT
2.5V TO 5. 0V
VDDVDD
FET
DRIVER
FET
DRIVER
GNDGND
OUTR+
OUTR–
OUTL+
OUTL–
06051-030
RIGHT IN+
RIGHT IN–
SHUTDOWN
LEFT IN+
LEFT IN–
10µF
SSM2302
1
0.01µF
INR+
INR–
1
0.01µF
SD
V
DD
GAIN
GAIN
1
0.01µF
INL+
INL–
1
0.01µF
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
GAIN
CONTROL
GAIN
CONTROL
BIAS
/2.
DD
Figure 20. Stereo Differential Input Configuration, Gain = 12 dB
10µF
0.1µF
VBATT
2.5V TO 5. 0V
VDDVDD
DRIVER
DRIVER
GNDGND
FET
FET
OUTR+
OUTR–
OUTL+
OUTL–
6051-031
RIGHT IN
SHUTDOWN
LEFT IN
SSM2302
0.01µF
0.01µF
GAIN
0.01µF
0.01µF
INR+
INR–
SD
GAIN
INL+
INL–
GAIN
CONTROL
GAIN
CONTROL
Figure 21. Stereo Single-Ended Input C
BIAS
MODULATOR
INTERNAL
OSCILLAT OR
MODULATOR
onfiguration, Gain = 6 dB
Rev. 0 | Page 9 of 20
SSM2302
www.BDTIC.com/ADI
EXTERNAL GAIN SETTI NGS = 20 lo g[4/(1 + R/150kΩ)]
SSM2302
1
0.01µF
R
RIGHT IN+
RIGHT IN–
SHUTDO WN
LEFT IN+
LEFT IN–
V
0.01µF
DD
0.01µF
0.01µF
INR+
INR–
R
1
SD
GAIN
GAIN
1
R
INL+
INL–
R
1
1
INPUT CAPS ARE OPTIONAL I F INPUT DC COM MON-MODE
VOLTAGE IS APPRO XIMATELY V
GAIN
CONTROL
GAIN
CONTROL
Figure 22. Stereo Differential Input Configurat
10µF
BIAS
/2.
DD
0.1µF
MODULATOR
INTERNAL
OSCILLATOR
MODULATOR
VBATT
2.5V TO 5. 0V
VDDVDD
FET
DRIVER
POP/CLICK
SUPPRESSION
FET
DRIVER
GNDGND
OUTR+
OUTR–
OUTL+
OUTL–
06051-036
ion, User-Adjustable Gain
EXTERNAL GAIN SET TINGS = 20 log[ 4/(1 + R/150kΩ)]
10µF
0.1µF
VBATT
2.5V TO 5. 0V
RIGHT IN
SHUTDOWN
LEFT IN
V
SSM2302
1
0.01µF
R
INR+
INR–
R
1
0.01µF
SD
DD
GAIN
GAIN
1
0.01µF
R
INL+
INL–
R
1
0.01µF
1
INPUT CAPS ARE O PTIONAL IF INPUT DC COMMON-MO DE
VOLTAGE IS APPROXIMATELY V
GAIN
CONTROL
GAIN
CONTROL
MODULATOR
BIAS
/2.
DD
INTERNAL
OSCILLATOR
MODULATOR
Figure 23. Stereo Single-Ended Input Configuration, User-Adjustable Gain
VDDVDD
FET
DRIVER
POP/CLICK
SUPPRESSION
FET
DRIVER
GNDGND
OUTR+
OUTR–
OUTL+
OUTL–
06051-037
Rev. 0 | Page 10 of 20
SSM2302
www.BDTIC.com/ADI
EXTERNAL GAIN SETTI NGS = 20 lo g[2/(1 + R/150kΩ)]
SSM2302
1
0.01µF
R
RIGHT IN+
RIGHT IN–
SHUTDO WN
LEFT IN+
LEFT IN–
0.01µF
0.01µF
0.01µF
INR+
INR–
R
1
SD
GAIN
GAIN
1
R
INL+
INL–
R
1
1
INPUT CAPS ARE OPTIONAL I F INPUT DC COM MON-MODE
VOLTAGE IS APPRO XIMATELY V
GAIN
CONTROL
GAIN
CONTROL
Figure 24. Stereo Differential Input Configurat
10µF
BIAS
/2.
DD
0.1µF
MODULATOR
INTERNAL
OSCILLATOR
MODULATOR
VBATT
2.5V TO 5. 0V
VDDVDD
FET
DRIVER
POP/CLICK
SUPPRESSION
FET
DRIVER
GNDGND
OUTR+
OUTR–
OUTL+
OUTL–
06051-038
ion, User-Adjustable Gain
EXTERNAL GAIN SET TINGS = 20 log[ 2/(1 + R/150kΩ)]
10µF
0.1µF
VBATT
2.5V TO 5. 0V
VDDVDD
FET
DRIVER
POP/CLICK
SUPPRESSION
FET
DRIVER
GNDGND
OUTR+
OUTR–
OUTL+
OUTL–
06051-039
RIGHT IN
SHUTDOWN
LEFT IN
SSM2302
1
0.01µF
R
INR+
INR–
R
1
0.01µF
SD
GAIN
GAIN
1
0.01µF
R
INL+
INL–
R
1
0.01µF
1
INPUT CAPS ARE O PTIONAL IF INPUT DC COMMON-MO DE
VOLTAGE IS APPROXIMATELY V
GAIN
CONTROL
GAIN
CONTROL
BIAS
/2.
DD
MODULATOR
INTERNAL
OSCILLATOR
MODULATOR
Figure 25. Stereo Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 11 of 20
SSM2302
www.BDTIC.com/ADI
APPLICATION NOTES
OVERVIEW
The SSM2302 stereo Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and thus reducing systems cost.
The SSM2302 does not require an output filter, but instead relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the
SSM2302 uses a Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produces a sharp peak with
many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies;
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. The SSM2302 also offers
protection circuits for overcurrent and temperature protection.
GAIN SELECTION
Pulling the GAIN pin high of the SSM2302 sets the gain of the
speaker amplifier to 12 dB; pulling it low sets the gain of the
speaker amplifier to 6 dB.
It is possible to adjust the SSM2302 gain by using external resistors
t the input. To set a gain lower than 12 dB refer to Figure 22 for
a
ferential input configuration and Figure 23 for single-ended
dif
co
nfiguration. For external gain configuration from a fixed 12 dB
gain, please use the following formula:
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
To set a gain lower than 6 dB refer to Figure 24 for differential
put configuration and Figure 25 for single-ended configuration.
in
or external gain configuration from a fixed 6 dB gain, use the
F
following formula:
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown is activated or deactivated. Voltage transients as low
as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system, therefore as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2302 has a pop-and-click suppression architecture
that reduces this output transients, resulting in noiseless activation
and deactivation.
EMI NOISE
The SSM2302 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the
device. Figure 26 shows SSM2302 EMI emission starting from
100 kH
z to 30 MHz. Figure 27 shows SSM2302 EMI emission
f
rom 30 kHz to 2 GHz. These figures clearly describe the SSM2302
EMI behavior as being well below the FCC regulation values,
starting from 100 kHz and passing beyond 1 GHz of frequency.
Although the overall EMI noise floor is slightly higher, frequency
spurs from the SSM2302 are greatly reduced.
70
= HORIZ ONTAL
= VERTICAL
= REGULATION VALUE
60
50
40
30
LEVEL (dB(µV/m))
20
10
0
0.1 100
Figure 26. EMI Emissions from SSM2302
70
= HORIZ ONTAL
= VERTICAL
= REGULATION VALUE
60
50
40
30
LEVEL (dB(µV/m))
20
10
0
10 10k
Figure 27. EMI Emissions from SSM2302
The measurements for Figure 26 and Figure 27 were taken with
a 1 kHz input signal, producing 0.5 W output power into an 8 Ω
load from a 3.6 V supply. Cable length was approximately 5 cm.
The EMI was detected using a magnetic probe touching the 2”
output trace to the load.
110
FREQUENCY (MHz)
100 1k
FREQUENCY (MHz)
06051-032
06051-033
Rev. 0 | Page 12 of 20
SSM2302
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LAYOUT
As output power continues to increase, care needs to be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Make track widths at least 200 mil for every inch of track length
for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to
further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance. Proper
grounding guidelines helps to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load and supply pins should be as
wide as possible to maintain the minimum trace resistances. It
is also recommended to use a large-area ground plane for
minimum impedances. Good PCB layouts also isolate critical
analog paths from sources of high interference. High frequency
circuits (analog and digital) should be separated from low
frequency ones. Properly designed multilayer printed circuit
boards can reduce EMI emission and increase immunity to RF
field by a factor of 10 or more compared with double-sided
boards. A multilayer board allows a complete layer to be used
for ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system
has separate analog and digital ground and power planes, the
analog ground plane should be underneath the analog power
plane, and, similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes nor analog and
digital power planes.
INPUT CAPACITOR SELECTION
The SSM2302 will not require input coupling capacitors if the
input signal is biased from 1.0 V to V
capacitors are required if the input signal is not biased within
this recommended input dc common-mode voltage range, if
high-pass filtering is needed (
d source (Figure 21). If high-pass filtering is needed at the
ende
i
nput, the input capacitor along with the input resistor of the
SSM2302 will form a high-pass filter whose corner frequency is
determined by the following equation:
= 1/(2π × RIN × CIN)
f
C
Input capacitor can have very important effects on the circuit
p
erformance. Not using input capacitors degrades the output
offset of the amplifier as well as the PSRR performance.
Figure 20), or if using a single-
− 1.0 V. Input
DD
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can
range from 10 kHz to 100 kHz, these spikes can contain
frequency components that extend into the hundreds of
megahertz. The power supply input needs to be decoupled with
a good quality low ESL and low ESR capacitor—usually around
4.7 μF. This capacitor bypasses low frequency noises to the
ground plane. For high frequency transients noises, use a 0.1 μF
capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the
SSM2302 helps maintain efficiency performance.
Rev. 0 | Page 13 of 20
SSM2302
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EVALUATION BOARD INFORMATION
INTRODUCTION
The SSM2302 audio power amplifier is a complete low power,
Class-D, stereo audio amplifier capable of delivering 1.4 W/channel
into 8 Ω load. In addition to the minimal parts required for the
application circuit, measurement filters are provided on the
evaluation board so that conventional audio measurements can
be made without additional components.
This section provides an overview of Analog Devices SSM2302
e
valuation board. It includes a brief description of the board as
well as a list of the board specifications.
Table 5. SSM2302 Evaluation Board Specifications
Parameter Specification
Supply Voltage Range, VDD 2.5 V to 5.0 V
Power Supply Current Rating 1.5 A
Continuous Output Power, PO
= 8 Ω, f = 1 kHz, 22 kHz BW)
(R
L
Minimum Load Impedance 8 Ω
1.4 W
OPERATION
Use the following steps when operating the SSM2302
evaluation board.
Power and Ground
1. Set the power supply voltage between 2.5 V and 5.0 V. When
connecting the power supply to the SSM2302 evaluation
board, make sure to attach the ground connection to the
GND header pin first and then connect the positive supply
to the VDD header pin.
Inputs and Outputs
1. Ensure that the audio source is set to the minimum level.
Gain Control
The gain select header controls the gain setting of the SSM2302.
1. S
elect jumper to LG for 6 dB gain.
elect jumper to HG for 12 dB gain.
2. S
External Gain Settings
It is possible to adjust the SSM2302 gain using external resistors
at the input. To set a gain lower than 12 dB refer to Figure 22
nd Figure 23 on the product data sheet for proper circuit con-
a
f
iguration. For external gain configuration from a fixed 12 dB
gain, use the following formula:
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
To set a gain lower than 6 dB refer to Figure 24 and Figure 25
n the product data sheet for proper circuit configuration. For
o
external gain configuration from a fixed 6 dB gain, use the
following formula:
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
Shutdown Control
The shutdown select header controls the shutdown function of
the SSM2302. The shutdown pin on the SSM2302 is active low,
meaning that a low voltage (GND) on this pin places the SSM2302
into shutdown mode.
1. S
elect jumper to 1-2 position. Shutdown pulled to V
2. S
elect jumper to 2-3 position. Shutdown pulled to GND.
Input Configurations
1. For differential input configuration with input capacitors
do not place a jumper on JP8, JP9, JP10, and JP11.
DD
.
2. C
onnect the audio source to Inputs INL± and INR±.
onnect the speakers to Outputs OUTL± and OUTR±.
3. C
Rev. 0 | Page 14 of 20
or differential input configuration without input capacitors
2. F
place a jumper on JP8, JP9, JP10, and JP11.
SSM2302
www.BDTIC.com/ADI
SSM2302 APPLICATION BOARD SCHEMATIC
JP2
POWER
JP1
3
2
1
LEFT IN
3
2
1
RIGHT IN
LIN+
LIN–
RIN+
RIN–
JP8
HEADER 2
12
C8
0.01µF
C9
0.01µF
2
1
JP9
HEADER 2
JP10
HEADER 2
12
C10
0.01µF
C11
0.01µF
2
1
JP11
HEADER 2
C7
0.1µFC60.1µFC510µF
INL+
SD
4
3
2
1
SD
INL+
5
INL–
6
NC
7
NC
8
INR–
INR+
9
GAIN
V
DD
R3
100kΩ
GAIN SD
OUTL+
GAIN
OUTR+
101112
JP12
1
3
5
HEADER 13C
GND
OUTL–
GND
OUTR–
12
V
DD
FERRITE BEAD
FERRITE BEAD
16
15
VDD
14
VDD V
13
U1
SSM2302
FERRITE BEAD
FERRITE BEAD
V
DD
2
4
6
DD
R4
100kΩ
C2
1nF
C4
1nF
C1
1nF
C3
1nF
JP3
1
2
1
2
OUT LEFT
OUT RIGHT
L1
L2
L1
L2
Figure 28. SSM2302 Application Board Schematic
06051-034
Rev. 0 | Page 15 of 20
SSM2302
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SSM2302 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST
Table 6.
Reference Description Footprint Quantity Manufacturer/Part Number
C8, C9, C10, C11 Capacitors, 0.01 μF 0402 4 Murata Manufacturing Co., Ltd./GRM15
C6, C7 Capacitor, 0.1 μF 0603 2 Murata Manufacturing Co., Ltd./GRM18
C5 Capacitor, 10 μF 0805 1 Murata Manufacturing Co., Ltd./GRM21
C1, C2, C3, C4 Capacitor, 1 nF 0402 4 Murata Manufacturing Co., Ltd./GRM15
R3, R4 Resistor, 100 kΩ 0603 2 Vishay/CRCW06031003F
L1, L2, L3, L4 Ferrite bead 0402 4 Murata Manufacturing Co., Ltd./BLM15EG121
U1 IC, SSM2302 3.0 mm × 3.0 mm 1 SSM2302CSPZ
EVAL BOARD PCB evaluation board 1
Rev. 0 | Page 16 of 20
SSM2302
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SSM2302 APPLICATION BOARD LAYOUT
06051-035
Figure 29. SSM2302 Application Board Layout
Rev. 0 | Page 17 of 20
SSM2302
R
R
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OUTLINE DIMENSIONS
INDICATO
SEATING
PIN 1
0.90
0.85
0.80
PLANE
12° MAX
3.00
BSC SQ
TOP
VIEW
0.30
0.23
0.18
*
COMPLIANT
EXCEPT FOR EXPOSED PAD DIMENSION.
2.75
BSC SQ
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
TO
JEDEC STANDARDS MO-220-VEED-2
0.45
0.50
BSC
1.50 REF
0.60 MAX
13
12
EXPOSED
PAD
(BOTTOM VIEW)
9
8
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3
mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
0.50
0.40
0.30
16
1
4
5
N
I
P
D
N
I
*
1.65
1.50 SQ
1.35
0.25 MIN
1
O
T
C
I
A
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
SSM2302CPZ-R2
SSM2302CPZ-REEL
SSM2302CPZ-REEL7
1
Z = Pb-free part.
1
−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
1
−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
1
−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
Rev. 0 | Page 18 of 20
SSM2302
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NOTES
Rev. 0 | Page 19 of 20
SSM2302
www.BDTIC.com/ADI
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06051-0-6/06(0)
Rev. 0 | Page 20 of 20
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