ANALOG DEVICES SSM2302 Service Manual

Filterless High Efficiency

www.BDTIC.com/ADI

FEATURES

Filterless Class-D amplifier with built-in output stage

1.4 W into 8 Ω at 5.0 V supply with less than 1% THD
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 16-lead, 3 mm × 3 mm LFCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2302 is a fully integrated, high efficiency, Class-D stereo
audio amplifier. It is designed to maximize performance for
mobile phone applications. The application circuit requires a
minimum of external components and operates from a single

2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of con­tinuous output power with less than 1% THD + N driving an
8 Ω load from a 5.0 V supply.

The SSM2302 features a high efficiency, low noise modulation

cheme. It operates with 85% efficiency at 1.4 W into 8 Ω from a

s

FUNCTIONAL BLOCK DIAGRAM

Class-D Stereo Audio Amplifier

SSM2302

5.0 V supply and has a signal-to-noise ratio (SNR) that is better
than 98 dB. PDM modulation is used to provide lower EMI­radiated emissions compared with other Class-D architectures.

The SSM2302 has a micropower shutdown mode with a typical

utdown current of 20 nA. Shutdown is enabled by applying a

sh

pin.

SD

/2.

DD

VBATT

2.5V TO 5. 0V

mmercial temperature range

10µF

logic low to the

The architecture of the device allows it to achieve a very low level

f pop and click. This minimizes voltage glitches at the output

o
during turn-on and turn-off, thus reducing audible noise on
activation and deactivation.

The fully differential input of the SSM2302 provides excellent
r

ejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V

The SSM2302 also has excellent rejection of power supply noise,
in

cluding noise caused by GSM transmission bursts and RF

rectification. PSRR is typically 63 dB at 217 Hz.

The gain can be set to 6 dB or 12 dB utilizing the gain control

elect pin connected respectively to ground or V

s
also be adjusted externally by using an external resistor.

The SSM2302 is specified over the co
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm
lead-frame chip scale package (LFCSP).

0.1µF

. Gain can

DD

SSM2302

1

0.01µF

0.01µF

0.01µF

0.01µF

INR+

INR–

1

SD

GAIN

1

INL+

INL–

1

GAIN

CONTROL

GAIN

CONTROL

/2.

DD

BIAS

RIGHT IN+

RIGHT IN–

SHUTDOWN

GAIN

LEFT IN+

LEFT IN–

1

INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

VDDVDD

OUTR+

MODULATOR

INTERNAL

OSCILLAT OR

MODULATOR

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

DRIVER

DRIVER

GNDGND

FET

FET

OUTR–

OUTL+

OUTL–

06051-001

SSM2302

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Pop-and-Click Suppression ...................................................... 12

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Typical Application Circuits............................................................ 9

Application Notes........................................................................... 12

Overview...................................................................................... 12

Gain Selection ............................................................................. 12

EMI Noise.................................................................................... 12

Layout .......................................................................................... 13

Input Capacitor Selection.......................................................... 13

Proper Power Supply Decoupling............................................ 13

Evaluation Board Information...................................................... 14

Introduction................................................................................ 14

Operation .................................................................................... 14

SSM2302 Application Board Schematic.................................. 15

SSM2302 Stereo Class-D Amplifier Evaluation Module

Component List.......................................................................... 16

SSM2302 Application Board Layout........................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

6/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

SSM2302

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

R
R
R
R
R
Efficiency η P

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V 0.1 %

P

Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRR
Channel Separation

X

TAL K

Average Switching Frequency fSW 1.8 MHz
Differential Output Offset Voltage V

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, 50 Hz, input floating/ground 70 85 dB
PSRR

Supply Current I

SY

V
V
Shutdown Current ISD

GAIN CONTROL

Closed-Loop Gain Av0 GAIN pin = 0 V 6 dB

Av1 GAIN pin = VDD 12 dB

Differential Input Impedance Z

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t

Turn-Off Time t
Output Impedance Z

IH

IL

WU

SD

OUT

NOISE PERFORMANCE

Output Voltage Noise en

Signal-to-Noise Ratio SNR P

RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.4 W

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.615 W

L

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.275 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.53 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.77 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.35 W

L

=1.4 W, 8 Ω, VDD = 5.0 V 85 %

OUT

= 0.5 W into 8 Ω each channel, f = 1 kHz, VDD = 3.6 V 0.04 %

O

GSM VCM

= 2.5 V ± 100 mV at 217 Hz 55 dB

PO = 100 mW , f = 1 kHz 98 dB

G = 6 dB; G = 12 dB 2.0 mV

Guaranteed from PSRR test 2.5 5.0 V

GSM

V

= 100 mV at 217 Hz, inputs ac GND,

RIPPLE

= 0.01 μF, input referred

C

IN

63 dB

VIN = 0 V, no load, VDD = 5.0 V 8.0 mA

= 0 V, no load, VDD = 3.6 V 6.6 mA

IN

= 0 V, no load, VDD = 2.5 V 5.3 mA

IN

SD

= GND

SD

= VDD,

SD

= GND

20 nA

150 KΩ
210 KΩ

ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD

rising edge from GND to VDD

SD

falling edge from VDD to GND

SD

= GND

= 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are

V

DD

ac grounded, sine wave, A

= 1.4 W, RL = 8 Ω 98 dB

OUT

= 6 dB, A weighting

V

30 ms
5 μs
>100 KΩ

35 μV

Rev. 0 | Page 3 of 20

SSM2302

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature Range

(Soldering, 60 sec)

DD

DD

300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA θ

16-lead, 3 mm × 3 mm LFCSP 44 31.5 °C/W

Unit

JC

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 4 of 20

SSM2302

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

GND

VDD

GND

14

13

15

16

PIN 1
INDICATOR

1OUTL+

2OUTL–

SSM2302

3SD

TOP VIEW

(Not to Scale)

4INL+

5

6

NC

INL–

NC = NO CO NNECT

Figure 2. SSM2302 LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 OUTL+ Inverting Output for Left Channel.
2 OUTL− Noninverting Output for Left Channel.
3

SD

Shutdown Input. Active low digital input.
4 INL+ Noninverting Input for Left Channel.
5 INL− Inverting Input for Left Channel.
6 NC No Connect.
7 NC No Connect.
8 INR− Inverting Input for Right Channel.
9 INR+ Noninverting Input for Right Channel.
10 GAIN Gain Selection. Digital input.
11 OUTR− Noninverting Output for Right Channel.
12 OUTR+

Inverting Output for Right Channel.
13 GND Ground for Output Amplifiers.
14 VDD Power Supply for Output Amplifiers.
15 VDD Power Supply for Output Amplifiers.
16 GND Ground for Output Amplifiers.

12 OUTR+

11 OUT R–

10 GAIN

9 INR+

8

7

C
N

INR–

06051-002

Rev. 0 | Page 5 of 20

SSM2302

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

100

RL = 8Ω, 33µH
GAIN = 12dB

10

VDD = 2.5V

100

10

VDD = 3.6V
R

L

1

= 8Ω, 33µH

1

THD + N (%)

0.1

0.01

0.000001 0.00010.00001 10

OUTPUT PO WER (W)

Figure 3. THD + N vs. Output Power into 8 Ω, A

100

RL = 8Ω, 33µH
GAIN = 6dB

10

1

THD + N (%)

0.1

0.01

0.000001 0.0001

0.0000001

0.00001 10

OUTPUT PO WER (W)

Figure 4. THD + N vs. Output Power into 8 Ω, A

VDD = 3.6V

0.001 0.01 0.1 1

= 12 dB

V

VDD = 2.5V

VDD = 3.6V

0.01

0.001

0.1

= 6 dB

V

VDD = 5V

VDD = 5V

1

0.1

THD + N (%)

0.01
250mW

0.001

0.0001
10 100k

06051-003

Figure 6. THD + N vs. Frequency, V

100

VDD = 2.5V

= 8Ω, 33µH

R

L

10

1

0.1

THD + N (%)

125mW

0.01

0.001

0.0001
10 100k

06051-004

Figure 7. THD + N vs. Frequency, V

500mW

125mW

100 1k 10k

FREQUENCY (Hz)

= 3.6 V

DD

250mW

75mW

100 1k 10k

FREQUENCY (Hz)

= 2.5 V

DD

06051-006

06051-007

100

VDD = 5V
R

= 8Ω, 33µH

L

10

1

0.1

THD + N (%)

0.01

0.5W

0.001

0.0001
10 100k

Figure 5. THD + N vs. Frequency, V

1W

0.25W

100 1k 10k

FREQUENCY (Hz)

= 5.0 V

DD

06051-005

Rev. 0 | Page 6 of 20

9

8

7

6

5

4

3

SUPPLY CURRENT (mA)

2

1

0

3.0 3.5 4.0 4.5 5.0

2.5 5.5

SUPPLY VOLTAGE (V)

Figure 8. Supply Current vs. Supply Voltage, No Load

06051-008