Analog Devices OP282 482 f Datasheet
Dual/Quad Low Power, High Speed
O
A
A
FEATURES
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier max
Low offset voltage: 3 mV max
Low bias current: 100 pA max
Fast settling time
Common-mode range includes V+
Unity-gain stable
APPLICATIONS
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current under 250 µA per
amplifier. These unity-gain stable amplifiers have a typical gain
bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 V of each supply, low
power consumption, and high slew rate, the OP282/OP482
are ideal for battery-powered systems or power restricted
applications. An input common-mode range that includes the
positive supply makes the OP282/OP482 an excellent choice for
high-side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead narrow SOIC and MSOP packages. The OP482 is
available in PDIP and narrow SOIC packages.
JFET Operational Amplifiers
OP282/OP482
PIN CONNECTIONS
+–
+–
V+
8
OUT B
7
–IN B
6
+IN B
5
8
7
6
5
14
13
12
11
10
14
13
12
11
10
9
8
V+
OUT B
–IN B
+IN B
9
8
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
00301-001
00301-002
00301-003
00301-004
1
UT
–IN A
2
3
4
OP282
OP-482
+IN A
V–
Figure 1. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8]
OUT
1
V–
OP282
2
TOP VIEW
3
(Not to Scale)
4
–IN A
+IN A
Figure 2. 8-Lead MSOP [RM-8]
1
OUT A
2
–IN A
+IN A
V+
+IN B
–IN B
OUT B
– +
3
OP482
4
5
– +
6
7
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
OUT A
1
–IN A
2
+IN A
3
4
5
6
7
OP482
V+
+IN B
–IN B
OUT B
Figure 4. 14-Lead Narrow-Body SOIC (S-Suffix) [R-14]
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
OP282/OP482
TABLE OF CONTENTS
Specifications..................................................................................... 3
High-Side Signal Conditioning ................................................ 12
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Typical Performance Characteristics............................................. 5
Applications Information .............................................................. 12
REVISION HISTORY
10/04—Data Sheet Changed from Rev. E to Rev. F
Deleted 8-Lead PDIP .........................................................Universal
Added 8-Lead MSOP .........................................................Universal
Changes to Format and Layout.........................................Universal
Changes to Features.......................................................................... 1
Changes to Pin Configurations....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3............................................................................ 4
Added Figure 5 through Figure 20; Renumbered
Successive Figures............................................................................. 5
Updated Figure 21 and Figure 22 ................................................... 7
Updated Figure 23 and Figure 27 ................................................... 8
Updated Figure 29............................................................................ 9
Updated Figure 35 and Figure 36 ................................................. 10
Updated Figure 43.......................................................................... 11
Changes to Applications Information.......................................... 12
Changes to Figure 44...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section.................... 9
Deleted Figure 4................................................................................ 9
Deleted OP282 Spice Marco Model............................................. 10
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide.......................................................... 14
Phase Inversion........................................................................... 12
Active Filters ............................................................................... 12
Programmable State-Variable Filter......................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 16
10/02—Data Sheet Changed from Rev. D to Rev. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin......................................1
Edits to Ordering Guide...................................................................3
Edits to Outline Dimensions......................................................... 11
9/02—Data Sheet Changed from Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin .............................................1
Replaced 8-Lead SOIC (S-Suffix)................................................. 11
4/02—Data Sheet changed from Rev. B to Rev. C
Wafer Test Limits Deleted ................................................................2
Edits to Absolute Maximum Ratings ..............................................3
Dice Characteristics Deleted............................................................3
Edits to Ordering Guide...................................................................3
Edits to Figure 1.................................................................................7
Edits to Figure 3.................................................................................8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
Rev. F | Page 2 of 16
OP282/OP482
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grade.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
OP282, −40°C ≤ TA ≤ +85°C 4.5 mV
V
OS
OP482, −40°C ≤ TA ≤ +85°C 6 mV
Input Bias Current I
B
V
Input Offset Current I
OS
V
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large Signal Voltage Gain A
VO
R
Offset Voltage Drift ∆VOS/∆T 10 µV/°C
Bias Current Drift ∆IB/∆T 8 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High V
Output Voltage Low V
Short-Circuit Limit I
OH
OL
SC
Sink −12 −8 mA
Open-Loop Output Impedance Z
OUT
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier I
Supply Voltage Range V
SY
S
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BW
Settling Time t
P
S
Gain Bandwidth Product GBP 4 MHz
Phase Margin Ø
O
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density e
Current Noise Density i
n
n
OP282 0.2 3 mV
OP482 0.2 4 mV
VCM = 0 V 3 100 pA
1
CM
= 0 V
500 pA
VCM = 0 V 1 50 pA
= 0 V1 250 pA
CM
RL = 10 kΩ 20 V/mV
= 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV
L
RL = 10 kΩ +13.5 +13.9 V
RL = 10 kΩ −13.9 −13.5 V
Source 3 10 mA
f = 1 MHz 200 Ω
VO = 0 V, −40°C ≤ TA ≤ 85°C 210 250 µA
±4.5 ±18 V
1% distortion 125 kHz
To 0.01% 1.6 µs
55 Degrees
f = 1 kHz 36
0.01
nV/√
pA/√
Hz
Hz
1
The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
Rev. F | Page 3 of 16
OP282/OP482
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Ratings
Supply Voltage ±18 V
Input Voltage ±18 V
Differential Input Voltage
1
36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C
Operating Temperature Range
OP282G, OP282A, OP482G −40°C to +85°C
Junction Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
1
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Package Type θ
8-Lead MSOP [RM] 206 44 °C/W
8-Lead SOIC (S-Suffix) [R] 157 56 °C/W
14-Lead PDIP (P-Suffix) [N] 83 39 °C/W
14-Lead SOIC (S-Suffix) [R] 104 36 °C/W
1
θJA is specified for the worst-case conditions; i.e., θJA is specified for device in
socket for CERDIP, PDIP; θ
for SOIC or MSOP package.
1
JA
is specified for device soldered in circuit board
JA
θ
Unit
JC
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 4 of 16
OP282/OP482
TYPICAL PERFORMANCE CHARACTERISTICS
80
60
40
20
0
OPEN-LOOP GAIN (dB)
–20
–40
1k
10k 1M 10M
100k
FREQUENCY (Hz)
Figure 5. OP282 Open-Loop Gain and Phase vs. Frequency
VS = ±15V
= 25°C
T
A
180
135
90
45
0
–45
–90
PHASE (Degree)
00301-005
70
60
50
A
= 1
00
VCL
40
30
A
= 1
0
VCL
20
10
A
= 1
VCL
0
CLOSED-LOOP GAIN (dB)
–10
–20
–30
1k
10k 1M 10M
100k
FREQUENCY (Hz)
Figure 8. OP282 Closed-Loop Gain vs. Frequency
VS = ±15V
= 25°C
T
A
00301-008
OPEN-LOOP GAIN (V/mV)
45
40
35
30
25
20
15
10
5
0
–75
–25 100 125
25
TEMPERATURE (°C)
75500–50
VS = ±15V
= 10kΩ
R
L
Figure 6. OP282 Open-Loop Gain vs. Temperature
80
VS = ±15V
= 2kΩ
R
L
70
= 100mV p-p
V
IN
A
= 1
VCL
TA = 25°C
60
50
40
30
OVERSHOOT (%)
20
10
0
0
LOAD CAPACITANCE (pF)
+OS
–OS
200 400 500
300100
Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance
00301-006
00301-007
30
25
20
15
10
SLEW RATE (V/µs)
5
0
–75
–25 100 125
TEMPERATURE (°C)
–SR
+SR
25
Figure 9. OP282 Slew Rate vs. Temperature
1000
VS = ±15V
= 0V
V
CM
100
10
1
INPUT BIAS CURRENT (pA)
0.1
–75
–25 100 125
25
TEMPERATURE (°C)
Figure 10. OP282 Input Bias Current vs. Temperature
75500–50
75500–50
VS = ±15V
= 10kΩ
R
L
= 50pF
C
L
00301-009
00301-010
Rev. F | Page 5 of 16
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