Low Noise: 80 nV p-p (0.1 Hz to 10 Hz), 3 nV/
Low Drift: 0.2 V/C
High Speed: 2.8 V/s Slew Rate, 8 MHz Gain
Bandwidth
Low V
Excellent CMRR: 126 dB at V
: 10 V
OS
of ±11 V
CM
High Open-Loop Gain: 1.8 Million
Fits 725, OP07, 5534A Sockets
Available in Die Form
GENERAL DESCRIPTION
The OP27 precision operational amplifier combines the low
offset and drift of the OP07 with both high speed and low noise.
Offsets down to 25 µV and drift of 0.6 µV/°C maximum make
the OP27 ideal for precision instrumentation applications.
Exceptionally low noise, e
= 3.5 nV/√Hz, at 10 Hz, a low 1/f
n
noise corner frequency of 2.7 Hz, and high gain (1.8 million),
allow accurate high-gain amplification of low-level signals. A
gain-bandwidth product of 8 MHz and a 2.8 V/µsec slew rate
provides excellent dynamic accuracy in high-speed, dataacquisition systems.
A low input bias current of ±10 nA is achieved by use of a
bias-current-cancellation circuit. Over the military temperature
range, this circuit typically holds I
and IOS to ±20 nA and 15 nA,
B
respectively.
The output stage has good load driving capability. A guaranteed
swing of ±10 V into 600 Ω and low output distortion make the
OP27 an excellent choice for professional audio applications.
Hz
(Continued on page 7)
Operational Amplifier
OP27
PIN CONNECTIONS
TO-99
(J-Suffix)
BAL
BAL 1
–IN 2
+IN 3
OP27
4V– (CASE)
NC = NO CONNECT
8-Pin Hermetic DIP
(Z-Suffix)
Epoxy Mini-DIP
(P-Suffix)
8-Pin SO
(S-Suffix)
TRIM
OS
–IN
+IN
1
OP27
2
3
4
NC = NO CONNECT
V
V+
OUT
NC
8
V
TRIM
OS
7
V+
6
OUT
5
NCV–
NONINVERTING
INPUT (+)
INVERTING
INPUT (–)
R1 AND R2 ARE PERMANENTLY
*
ADJUSTED AT WAFER TEST FOR
MINIMUM OFFSET VOLTAGE.
Q6
Q3
R1*
R3
18
V
ADJ.
OS
Q2B
R4
R2*
Q2AQ1A Q1B
Q11 Q12
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Input offset voltage measurements are performed ~ 0.5 seconds after application of power. A/E grades guaranteed fully warmed up.
2
Long-term input offset voltage stability refers to the average trend line of VOS versus. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 days are typically 2.5 µV. Refer to typical performance curve.
3
Sample tested.
4
See test circuit and frequency response curve for 0.1 Hz to 10 Hz tester.
5
See test circuit for current noise measurement.
6
Guaranteed by input bias current.
7
Guaranteed by design.
–2–
REV. A
OP27
ELECTRICAL CHARACTERISTICS
(@ VS = ±15 V, –55C ≤ TA ≤ 125C, unless otherwise noted.)
OP27A OP27C
ParameterSymbolConditionsMinTypMaxMinTypMaxUnit
INPUT OFFSET
VOLTAGE
AVERAGE INPUT
OFFSET DRIFTTCV
1
V
OS
TCV
OS
OSn
306070300µV
2
3
0.20.641.8µV/°C
INPUT OFFSET
CURRENTI
OS
155030135nA
INPUT BIAS
CURRENTI
B
±20±60±35±150nA
INPUT VOLTAGE
RANGEIVR±10.3± 11.5±10.2± 11.5V
COMMON-MODE
REJECTION RATIO CMRRVCM = ±10 V10812294118dB
POWER SUPPLY
REJECTION RATIO PSRRVS = ±4.5 V to ±18 V216451µV/V
LARGE-SIGNAL
VOLTAGE GAINA
VO
RL ≥ 2 kΩ, VO = ±10 V 6001200300800V/mV
OUTPUT
VOLTAGE SWINGV
NOTES
1
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. A/E grades guaranteed fully
warmed up.
2
The TCVOS performance is within the specifications unnulled or when nulled with RP = 8 kΩ to 20 kΩ. TCVOS is 100% tested for A/E grades, sample tested for
C/F/G grades.
3
Guaranteed by design.
O
RL ≥ 2 kΩ±11.5± 13.5±10.5±13.0V
REV. A
–3–
OP27
(@ VS = ±15 V, –25C¯≤ TA ≤ 85C for OP27J, OP27Z, 0C ≤ TA ≤ 70C for OP27EP,
INPUT VOLTAGE
RANGEIVR±10.5±11.8±10.5 ±11.8±10.5 ±11.8V
COMMON-MODE
REJECTION RATIO CMRRVCM = ±10 V11012410212196118dB
POWER SUPPLY
REJECTION RATIO PSRRVS = ±4.5 V215216232µV/V
LARGE-SIGNAL
VOLTAGE GAINA
OUTPUT
VOLTAGE SWINGV
NOTES
1
The TCVOS performance is within the specifications unnulled or when nulled with RP = 8 kΩ to 20 kΩ. TCVOS is 100% tested for A/E grades, sample tested for
C/F/G grades.
2
Guaranteed by design.
OS
TCV
OS
B
VO
O
1
OS
2
OSn
to ±18 V
R
≥ 2 kΩ,
L
VO = ±10 V750150070013004501000V/mV
RL ≥ 2 kΩ±11.7±13.6±11.4 ±13.5± 11.0 ± 13.3V
OP27FP, and –40C ≤ TA ≤ 85C for OP27GP, OP27GS, unless otherwise noted.)
OP27E OP27F OP27G
20504014055220µV
0.20.60.31.30 41.8µV/°C
0.20.60.31.30 41.8µV/°C
1050148520135nA
±14±60±18±95±25± 150nA
–4–
REV. A
DICE CHARACTERISTICS
DIE SIZE 0.109 0.055 INCH, 5995 SQ. MILS
(2.77 1.40mm, 3.88 SQ. mm)
1. NULL
2. (–) INPUT
3. (+) INPUT
4. V–
6. OUTPUT
7. V+
8. NULL
OP27
WAFER TEST LIMITS
(@ VS = ±15 V, TA = 25C unless otherwise noted.)
OP27NOP27GOP27GR
ParameterSymbolConditionsLimitLimitLimitUnit
INPUT OFFSET VOLTAGE*V
INPUT OFFSET CURRENTI
OS
OS
3560100µV Max
355075nA Max
INPUT BIAS CURRENTIB±40±55± 80nA Max
INPUT VOLTAGE RANGEIVR±11±11± 11V Min
COMMON-MODE REJECTION
RATIOCMRRV
= IVR114106100dB Min
CM
POWER SUPPLYPSRRVS = ±4 V to ±18 V101020µV/V Max
LARGE-SIGNAL VOLTAGE
GAINA
OUTPUT VOLTAGE SWINGV
POWER CONSUMPTIONP
NOTE
*Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
VO
A
VO
O
V
O
d
RL ≥ 2 kΩ, VO = ±10 V10001000700V/mV Min
RL ≥ 600 Ω, VO = ±10 V800800600V/mV Min
RL ≥ 2 kΩ±12.0± 12.0+11.5V Min
RL2600n±10.0±10.0± 10.0V Min
VO = 0140140170mW Max
REV. A
–5–
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