Analog Devices OP177GS, OP177GP, OP177FP, OP177FS Datasheet
Ultraprecision
M
a
FEATURES
Ultralow Offset Voltage:
T
= 25ⴗC: 25 V Max
A
Outstanding Offset Voltage Drift: 0.1 V/ⴗC Max
Excellent Open-Loop Gain and Gain Linearity:
12 V/V Typ
CMRR: 130 dB Min
PSRR: 115 dB Min
Low Supply Current: 2.0 mA Max
Fits Industry Standard Precision Op Amp Sockets
(OP07/OP77)
GENERAL DESCRIPTION
The OP177 features the highest precision performance of any
op amp currently available. Offset voltage of the OP177 is only
25 µV max at room temperature. The ultralow V
OP177 combines with its exceptional offset voltage drift
(TCV
V
) of 0.1 µV/°C max to eliminate the need for external
OS
adjustment and increases system accuracy over
OS
temperature.
The OP177’s open-loop gain of 12 V/µV is maintained over the
full ±10 V output range. CMRR of 130 dB min, PSRR of
120 dB min, and maximum supply current of 2 mA are just a
few examples of the excellent performance of this operational
amplifier. The OP177’s combination of outstanding specifications
ensures accurate performance in high closed-loop gain applications.
of the
OS
Operational Amplifier
OP177
PIN CONNECTIONS
Epoxy Mini-DIP
(P Suffix)
8-Pin SO
(S-Suffix)
1
TRIM
V
OS
2
–IN
3
+IN
4
NC = NO CONNECT
This low noise bipolar input op amp is also a cost effective
alternative to chopper-stabilized amplifiers. The OP177 provides
chopper-type performance without the usual problems of high
noise, low frequency chopper spikes, large physical size, limited
common-mode input voltage range, and bulky external storage
capacitors.
The OP177 is offered in the –40°C to +85°C extended
industrial temperature ranges. This product is available in
8-pin epoxy DIPs, as well as the space saving 8-pin SmallOutline (SO).
8
V
TRI
OS
7
V+
6
OUT
5
NCV–
NONINVERTING
INPUT
INVERTING
INPUT
V+
R1A
2B
Q7
R3
Q21
Q23
Q24
Q22
R4
V–
*NOTE:
R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
Q1
(OPTIONA
L
NULL)
Q8
Q4Q6Q3Q5
Q2
Figure 1. Simplified Schematic
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
R2B*R2A*
R1B
C1
C2
Q13
Q10
Q17
Q14
Q9
Q11 Q12
C3
Q27
R5
Q26
Q25
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Q16
Q15
R7
Q19
R9
OUTPUT
R10
Q20
Q18
R8R6
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.)
OP177
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
OP177F OP177G
INPUT OFFSET
VOLTAGE V
OS
10 25 20 60 µV
LONG-TERM
INPUT OFFSET
Voltage Stability ∆VOS/Time 0.3 0.4 µV/Mo
INPUT OFFSET
CURRENT I
1
OS
0.3 1.5 0.3 2.8 nA
INPUT BIAS
CURRENT I
INPUT NOISE
VOLTAGE e
INPUT NOISE
CURRENT i
B
n
n
fo = 1 Hz to 100 Hz
fo = 1 Hz to 100 Hz
–0.2 1.2 2 –0.2 1.2 2.8 nA
2
2
118 150 118 150 nV rms
38 38 pA rms
INPUT
RESISTANCE
Differential Mode
3
R
IN
26 45 18.5 45 MΩ
INPUT
RESISTANCE
COMMON-MODE R
INPUT VOLTAGE
RANGE
4
INCM
IVR ±13 ±14 ±13 ±14 V
200 200 GΩ
COMMON-MODE
REJECTION
RATIO CMRR VCM = ±13 V 130 140 115 140 dB
POWER SUPPLY
REJECTION
RATIO PSRR VS = ±3 V to ±18 V 115 125 110 120 dB
LARGE SIGNAL
VOLTAGE GAIN A
VO
RL ⱖ 2 kΩ, 5000 12000 2000 6000 V/mV
VO = 610 V
5
OUTPUT
VOLTAGE
SWING V
O
RL ⱖ 10 kΩ±13.5 ± 14.0 ±13.5 ± 14.0 V
R
ⱖ 2 kΩ±12.5 ± 13.0 ±12.5 ± 13.0 V
L
RL ⱖ 1 kΩ±12.0 ± 12.5 ±12.0 ± 12.5 V
SLEW RATE
CLOSED-LOOP
BANDWIDTH
2
SR RL ⱖ 2 kΩ 0.1 0.3 0.1 0.3 V/µs
2
BW A
= 1 0.4 0.6 0.4 0.6 MHz
VCL
OPEN-LOOP
OUTPUT
RESISTANCE R
O
60 60 Ω
REV. C
–2–
OP177
POWER
CONSUMPTION P
D
SUPPLY
CURRENT I
SY
OFFSET
ADJUSTMENT
RANGE RP = 20 kΩ±3 ±3mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS versus time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 µV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ± 10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Specifications subject to change without notice.
VS = ±15 V,
No Load 50 60 50 60 mW
Vs = ±3 V,
No Load 3.5 4.5 3.5 4.5 mW
VS = ±15 V,
No Load 1.6 2 1.6 2 mA
REV. C
–3–
OP177–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, –40ⴗC ≤ TA ≤ 85ⴗC, unless otherwise noted.)
OP177F OP177G
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE V
AVERAGE INPUT OFFSET
VOLTAGE DRIFT
1
INPUT OFFSET CURRENT I
AVERAGE INPUT OFFSET
CURRENT DRIFT
2
INPUT BIAS CURRENT I
AVERAGE INPUT BIAS
CURRENT DRIFT
2
OS
TCV
OS
TCI
B
TCI
OS
OS
–0.2 2.4 4 2.4 ± 6nA
B
15 40 20 100 µV
0.1 0.3 0.7 1.2 µV/°C
0.5 2.2 0.5 4.5 nA
1.5 40 1.5 85 pA/°C
8 40 15 60 pA/°C
INPUT VOLTAGE RANGE3IVR ±13 ±13.5 ± 13 ±13.5 V
COMMON-MODE
REJECTION RATIO CMRR VCM = ±13 V 120 140 110 140 dB
POWER SUPPLY
REJECTION RATIO PSSR VS = ±3 V to ±18 V 110 120 106 115 dB
LARGE-SIGNAL
VOLTAGE GAIN
OUTPUT VOLTAGE SWING V
POWER CONSUMPTION P
SUPPLY CURRENT I
NOTES
1
OP177TCVOS is sample tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ± 10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Specifications subject to change without notice.
4
A
VO
O
D
SY
RL ⱖ 2 kΩ, VO = 10 V 2000 6000 1000 4000 V/mV
RL ⱖ 2/kΩ±12 ±13 ±12 ± 13 V
VS = ±15 V, No Load 60 75 60 75 mW
VS = ±15 V, No Load 20 2.5 2 2.5 mA
200k⍀
50⍀
–
OP177
+
VOS =
VO
4000
V
O
Figure 2. Typical Offset Voltage Test Circuit
–
INPUT
+
–
OP177
+
V–
20k⍀
TRIM RANGE IS
V
OS
TYPICALLY ⴞ3.0mV
V+
OUTPUT
Figure 3. Optional Offset Nulling Circuit
REV. C–4–
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