Analog Devices DAC8562GBC, DAC8562FS, DAC8562FP, DAC8562EP Datasheet
+5 Volt, Parallel Input
a
FEATURES
Complete 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, 65 mA Drive
Very Low Power –3 mW
APPLICATIONS
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals
GENERAL DESCRIPTION
The DAC8562 is a complete, parallel input, 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built
using a CBCMOS process, these monolithic DACs offer the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DAC, is a rail-to-rail
amplifier, latch and reference. The reference (REFOUT) is
trimmed to 2.5 volts, and the on-chip amplifier gains up the
DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply.
The DAC8562 is coded straight binary. The op amp output
swings from 0 to +4.095 volts for a one millivolt per bit resolution, and is capable of driving ± 5 mA. Built using low temperature-coefficient silicon-chrome thin-film resistors, excellent
linearity error over temperature has been achieved as shown below in the linearity error versus digital input code plot.
Digital interface is parallel and high speed to interface to the
fastest processors without wait states. The interface is very simple requiring only a single
put sets the output to zero scale.
CE signal. An asynchronous CLR in-
Complete 12-Bit DAC
DAC8562
FUNCTIONAL BLOCK DIAGRAM
V
REFOUT
DAC-8562
DAC REGISTER
CE
12-BIT
DAC
DATA
12
12
REF
DGND
The DAC8562 is available in two different 20-pin packages,
plastic DIP and SOL-20. Each part is fully specified for operation over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
For MIL-STD-883 applications, contact your local ADI sales
office for the DAC8562/883 data sheet which specifies operation over the –55°C to +125°C temperature range.
1
0.75
0.5
0.25
0
–0.25
LINEARITY ERROR — LSB
–0.5
–0.75
–1
0
VDD = +5V
T
A
DIGITAL INPUT CODE — Decimal
Figure 1. Linearity Error vs. Digital Input Code Plot
DD
V
AGND
CLR
= –55°C, +25°C, +125°C
–55°C
+25°C & +125°C
307220481024
OUT
4096
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
DAC8562–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VDD = +5.0 6 5%, RS = No Load, –408C ≤ TA ≤ +858C, unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N Note 2 12 Bits
Relative Accuracy INL E Grade –1/2 ± 1/4 +1/2 LSB
F Grade –1 ±3/4 +1 LSB
Differential Nonlinearity DNL No Missing Codes –1 ±3/4 +1 LSB
Zero-Scale Error V
Full-Scale Voltage V
ZSE
FS
Data = 000
Data - FFF
H
3
H
+1/2 +3 LSB
E Grade 4.087 4.095 4.103 V
F Grade 4.079 4.095 4.111 V
Full-Scale Tempco TCV
Notes 3, 4 ±16 ppm/°C
FS
ANALOG OUTPUT
Output Current I
OUT
Load Regulation at Half Scale LD
Capacitive Load C
L
REG
Data = 800
R
= 402 Ω to ∞, Data = 800
L
No Oscillation
H
4
±5 ±7mA
H
1 3 LSB
500 pF
REFERENCE OUTPUT
Output Voltage V
Output Source Current I
REF
REF
Line Rejection LN
Load Regulation LD
Note 5 5 7 mA
REJ
REGIREF
= 0 to 5 mA 0.1 %/mA
2.484 2.500 2.516 V
0.08 %/V
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance C
INTERFACE TIMING SPECIFICATIONS
1, 4
Chip Enable Pulse Width t
Data Setup t
Data Hold t
Clear Pulse Width t
AC CHARACTERISTICS
Voltage Output Settling Time
4
6
IL
IH
IL
IL
CEW
DS
DH
CLRW
t
S
2.4 V
Note 4 10 pF
30 ns
30 ns
10 ns
20 ns
To ±1 LSB of Final Value 16 µs
0.8 V
10 µA
Digital Feedthrough 35 nV sec
SUPPLY CHARACTERISTICS
Positive Supply Current I
Power Dissipation P
DD
DISS
VIH = 2.4 V, VIL = 0.8 V 3 6 mA
V
= 0 V, VDD = +5 V 0.6 1 mA
IL
VIH = 2.4 V, VIL = 0.8 V 15 30 mW
V
= 0 V, VDD = +5V 3 5 mW
IL
Power Supply Sensitivity PSS ∆VDD = ±5% 0.002 0.004 %/%
NOTES
1
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
1 LSB = 1 mV for 0 to +4.095 V output range.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
1
0
0
0
1
1
FS
ZS
DB
11–0
V
OUT
t
CEW
t
DS
t
DH
DATA VALID
t
CLRW
t
S
t
S
±1 LSB
ERROR BAND
CE
CLR
DAC8562
(@ VDD = +5.0 V 6 5%, RL = No Load, TA = +258C, applies to part number DAC8562GBC only,
WAFER TEST LIMITS
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Relative Accuracy INL –1 ±3/4 +1 LSB
Differential Nonlinearity DNL No Missing Codes –1 ±3/4 + 1 LSB
Zero-Scale Error V
Full-Scale Voltage V
Reference Output Voltage V
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
SUPPLY CHARACTERISTICS
Positive Supply Current I
Power Dissipation P
Power Supply Sensitivity PSS ∆VDD = ±5% 0.002 0.004 %/%
NOTE
1
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
unless otherwise noted)
ZSE
FS
REF
IL
IH
IL
DD
DISS
Data = 000
Data = FFF
H
H
4.085 4.095 4.105 V
+1/2 +3 LSB
2.490 2.500 2.510 V
0.8 V
2.4 V
10 µA
VIH = 2.4 V, VIL = 0.8 V 3 6 mA
V
= 0 V, VDD = +5 V 0.6 1 mA
IL
VIH = 2.4 V, VIL = 0.8 V 15 30 mW
V
= 0 V, VDD = +5 V 35mW
IL
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND and AGND . . . . . . . . . . . . . . . . –0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, V
V
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
OUT
V
to AGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
REFOUT
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
I
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
OUT
Package Power Dissipation . . . . . . . . . . . . . .(T
Thermal Resistance u
JA
+ 0.3 V
DD
max – TA)/u
J
DD
JA
20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 74°C/W
20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 89°C/W
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 2. Timing Diagram
Table I. Control Logic Truth Table
CE CLR DAC Register Function
H H Latched
L H Transparent
↑
+ H Latched with New Data
X L Loaded with All Zeros
H
↑
+ Positive Logic Transition; X Don't Care.
↑
+ Latched All Zeros
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic
fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be
discharged to the destination socket before devices are inserted.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
DAC8562
PIN CONFIGURATIONS
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DGND
20-Pin P-DIP
(N-20)
1
2
3
4
DAC-8562
5
TOP VIEW
6
(Not to Scale)
7
8
9
10
NC = NO CONNECT
20
19
18
17
16
15
14
13
12
11
V
DD
DB2
DB1
DB0
CE
CLR
REFOUT
V
OUT
AGND
NC
SOL-20
(R-20)
1
DAC-8562
TOP VIEW
(Not to Scale)
ORDERING GUIDE
INL Temperature Package
Model (LSB) Range Option
DAC8562EP ±1/2 –40°C to +85°C N-20
DAC8562FP ±1 –40°C to +85°C N-20
DAC8562FS ±1 –40°C to +85°C R-20
DAC8562GBC ±1 +25°C Dice
DICE CHARACTERISTICS
AGND
13
V
OUT
REFOUT
14
15
CLR
16
CE
17
DB0
18
DB1
19
DB2
SUBSTRATE IS COMMON WITH VDD.
TRANSISTOR COUNT: 524
DIE SIZE: 0.70 X 0.105 INCH; 7350 SQ MILS
12
DGND
20 1
V
DD
DB11
10
9
DB10
8
7
DB9
6
DB8
5
DB7
DB6
4
3
DB5
2
DB4DB3
Table II. Nominal Output Voltage vs. Input Code
Binary Hex Decimal Output (V)
0000 0000 0000 000 0 0.000 Zero Scale
0000 0000 0001 001 1 0.001
0000 0000 0010 002 2 0.002
0000 0000 1111 00F 15 0.015
0000 0001 0000 010 16 0.016
0000 1111 1111 0FF 255 0.255
0001 0000 0000 100 256 0.256
0001 1111 1111 1FF 511 0.511
0010 0000 0000 200 512 0.512
0011 1111 1111 3FF 1023 1.023
0100 0000 0000 400 1024 1.024
0111 1111 1111 7FF 2047 2.047
1000 0000 0000 800 2048 2.048 Half Scale
1100 0000 0000 C00 3072 3.072
1111 1111 1111 FFF 4095 4.095 Full Scale
PIN DESCRIPTIONS
Pin Name Description
20 V
DD
Positive supply. Nominal value
+5 volts, ±5%.
1-9 DB0-DB11 Twelve Binary Data Bit inputs. DB11
17-19 is the MSB and DB0 is the LSB.
16
15
CE Chip Enable. Active low input.
CLR Active low digital input that clears the
DAC register to zero, setting the DAC
to minimum scale.
8 DGND Digital ground for input logic.
12 AGND Analog Ground. Ground reference for
the internal bandgap reference voltage,
the DAC, and the output buffer.
13 V
OUT
Voltage output from the DAC. Fixed
output voltage range of 0 V to 4.095 V
with 1 mV/LSB. An internal tempera-
ture stabilized reference maintains a
fixed full-scale voltage independent of
time, temperature and power supply
variations.
14 REFOUT Nominal 2.5 V reference output volt-
age. This node must be buffered if re-
quired to drive external loads.
11 NC No Connection. Leave pin floating.
–4–
REV. A
DAC8562
V
DD
V
OUT
AGND
N-CH
P-CH
OPERATION
The DAC8562 is a complete ready to use 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for
operation. It contains a voltage-switched, 12-bit, laser-trimmed
digital-to-analog converter, a curvature-corrected bandgap reference, a rail-to-rail output op amp, and a DAC register. The parallel data interface consists of 12 data bits, DB0–DB11, and a
active low
will set all DAC register bits to zero causing the V
CE strobe. In addition, an asynchronous CLR pin
to be-
OUT
come zero volts. This function is useful for power on reset or
system failure recovery to a known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt internal
bandgap voltage. It uses a laser trimmed R-2R ladder which is
switched by N channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output (not available to the user) is internally
connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
REFOUT
BANDGAP
REFERENCE
2.5V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
BUFFER
SPDT
N ch FET
SWITCHES
RAIL-TO-RAIL
OUTPUT
2R
R
2R
R
2R
2R
2R
AMPLIFIER
R2
R1
AV = 4.096/2.5
= 1.636V/V
V
OUT
Figure 3. Equivalent DAC8562 Schematic of
Analog Portion
The op amp has a 16 µs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4. Equivalent Analog Output Circuit
Figures 5 and 6 in the typical performance characteristics section provide information on output swing performance near
ground and full scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is
available at the REFOUT pin. Since REFOUT is not intended
to drive external loads, it must be buffered–refer to the applications section for more information. The equivalent emitter follower output circuit of the REFOUT pin is shown in Figure 3.
Bypassing the REFOUT pin is not required for proper operation. Figure 7 shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the DAC8562 is a direct
result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for
the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the DAC8562 is
strongly dependent on the actual logic-input voltage-levels
present on the DB0–DB11,
CE and CLR pins. Since these inputs are standard CMOS logic structures, they contribute static
power dissipation dependent on the actual driving logic V
V
voltage levels. The graph in Figure 9 shows the effect on to-
OL
OH
and
tal DAC8562 supply current as a function of the actual value of
input logic voltage. Consequently for optimum dissipation use
of CMOS logic versus TTL provides minimal dissipation in the
static state. A V
= 0 V on the DB0–DB11 pins provides the
INL
lowest standby dissipation of 600 µA with a +5 V power supply.
REV. A
–5–
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