Quad 12-Bit Serial
a
FEATURES
Guaranteed Monotonic Over Temperature
Excellent Matching Between DACs
Unipolar or Bipolar Operation
Buffered Voltage Outputs
High Speed Serial Digital Interface
Reset to Zero- or Center-Scale
Wide Supply Range, +5 V-Only to 615 V
Low Power Consumption (35 mW max)
Available in 16-Pin DIP and SOL Packages
APPLICATIONS
Software Controlled Calibration
Servo Controls
Process Control and Automation
ATE
GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface, in a 16-pin package. Utilizing BiCMOS technology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve specified performance.
The three-wire serial digital input is easily interfaced to microprocessors running at 10 MHz rates, with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address header.
The user-programmable reset control
outputs to either zero or midscale, asynchronously overriding
the current DAC register values. The output voltage range, determined by the inputs VREFHI and VREFLO, is set by the
user for positive or negative unipolar or bipolar signal swings
within the supplies allowing considerable design flexibility.
CLR forces all four DAC
Voltage Output DAC
DAC8420
FUNCTIONAL BLOCK DIAGRAM
VREFHI
5
10
SDI
CLK
12
CS
11
NC
13
14
LD
GND
SHIFT
REGISTER
DECODE
CLSEL
CLR
REG
REG
DAC A
A
A
12
REG
DAC B
B
REG
DAC C
4
C
REG
DAC D
D
2
VREFLO VSS
The DAC8420 is available in 16-pin epoxy DIP, cerdip, and
wide-body SOL (small-outline surface mount) packages. Operation is specified with supplies ranging from +5 V-only to ± 15 V,
with references of +2.5 V to ±10 V respectively. Power dissipation when operating from ±15 V supplies is less than 255 mW
(max), and only 35 mW (max) with a +5 V supply.
For applications requiring product meeting MIL-STD-883,
contact your local sales office for the DAC8420/883 data sheet,
which specifies operation over the –55°C to +125°C temperature range.
VDD
1
VOUTA
7
VOUTB
6
3
VOUTC
2
VOUTD
815169
4
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
DAC8420–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSS = –5.0 V 6 5%, V
= –2.5 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.)
VREFLO
(at VDD = +5.0 V 6 5%, VSS = 0.0 V, V
VREFHI
= +2.5 V, V
= 0.0 V, and
VREFLD
Parameter Symbol Condition Min Typ Max Units
STATIC ACCURACY
Integral Linearity “E” INL ±1/4 ±1 LSB
Integral Linearity “E” INL Note 2, V
= 0 V ±1/2 ±3 LSB
SS
Integral Linearity “F” INL ±3/4 ±2 LSB
Integral Linearity “F” INL Note 2, V
= 0 V ±1 ±4 LSB
SS
Differential Linearity DNL Monotonic Over Temperature ±1/4 ±1 LSB
Min-Scale Error ZSE R
Full-Scale Error FSE R
Min-Scale Error ZSE Note 2, R
Full-Scale Error FSE Note 2, R
Min-Scale Tempco TC
Full-Scale Tempco TC
ZSE
FSE
= 2 kΩ, VSS = –5 V ±4 LSB
L
= 2 kΩ, VSS = –5 V ±4 LSB
L
= 2 kΩ, VSS = 0 V ±8 LSB
L
= 2 kΩ, VSS = 0 V ±8 LSB
L
Note 3, RL = 2 kΩ, VSS = –5 V ±10 ppm/°C
Note 3, RL = 2 kΩ, VSS = –5 V ±10 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range V
Negative Reference Input Range V
Negative Reference Input Range V
Reference High Input Current I
Reference Low Input Current I
VREFHI
VREFLO
VREFLO
VREFHI
VREFLO
Note 4 V
Note 4 V
Note 4, VSS = 0 V 0 V
Codes 000H, 555
H
–0.75 ±0.25 +0.75 mA
Codes 000H, 555H, VSS = –5 V –1.0 –0.6 mA
+2.5 VDD –2.5 V
VREFLO
SS
V
VREFHI
VREFHI
–2.5 V
–2.5 V
AMPLIFIER CHARACTERISTICS
Output Current I
Settling Time t
OUT
S
VSS = –5 V –1.25 +1.25 mA
to 0.01%, Note 5 8 µs
Slew Rate SR 10% to 90%, Note 5 1.5 V/µs
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
Input Capacitance C
LOGIC TIMING CHARACTERISTICS
Data Setup Time t
Data Hold t
Clock Pulse Width HIGH t
Clock Pulse Width LOW t
Select Time t
Deselect Delay t
Load Disable Time t
Load Delay t
Load Pulse Width t
Clear Pulse Width t
3, 6
INH
INL
IN
IN
DS
DH
CH
CL
CSS
CSH
LD1
LD2
LDW
CLRW
Note 3 13 pF
2.4 V
0.8 V
10 µA
25 ns
55 ns
90 ns
120 ns
90 ns
5ns
130 ns
35 ns
80 ns
150 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSRR 0.002 0.01 %/%
Positive Supply Current I
Negative Supply Current I
Power Dissipation P
NOTES
1
All supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = +4.75 V.
2
For single-supply operation (V
3
Guaranteed but not tested.
4
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5
V
swing between +2.5 V and –2.5 V with VDD = 5.0 V.
OUT
6
All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Typical values indicate performance measured at +25°C.
Specifications subject to change without notice.
= 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at code 003H.
VREFLO
DD
SS
DISS
–6 –3 mA
VSS = 0 V 20 35 mW
47 mA
–2–
REV. 0
DAC8420
ELECTRICAL CHARACTERISTICS
V
= –10.0 V, –408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.)
VREFLO
(at VDD = +15.0 V 6 5%, VSS = –15.0 V 6 5%, V
VREFHI
= +10.0 V,
Parameter Symbol Condition Min Typ Max Units
STATIC ACCURACY
Integral Linearity “E” INL ±1/4 ±1/2 LSB
Integral Linearity “F” INL ±1/2 ±1 LSB
Differential Linearity DNL Monotonic Over Temperature ± 1/4 ±1 LSB
Min-Scale Error ZSE R
Full-Scale Error FSE R
Min-Scale Tempco TC
Full-Scale Tempco TC
ZSE
FSE
= 2 kΩ±2 LSB
L
= 2 kΩ±2 LSB
L
Note 2, RL = 2 kΩ±4 ppm/°C
Note 2, RL = 2 kΩ±4 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range V
Negative Reference Input Range V
Reference High Input Current I
Reference Low Input Current I
VREFHI
VREFLO
VREFHI
VREFLO
Note 3 V
Note 3 –10 V
Codes 000H, 555
Codes 000H, 555
H
H
+2.5 VDD –2.5 V
VREFLO
VREFHI
–2.5 V
–2.0 ±1.0 +2.0 mA
–3.5 –2.0 mA
AMPLIFIER CHARACTERISTICS
Output Current I
Settling Time t
OUT
S
to 0.01%, Note 4 13 µs
–5 +5 mA
Slew Rate SR 10% to 90%, Note 4 2 V/µs
DYNAMIC PERFORMANCE
Analog Crosstalk Note 2 >64 dB
Digital Feedthrough Note 2 >72 dB
Large Signal Bandwidth 3 dB, V
V
VREFLO
= 5 V + 10 V p-p, 90 kHz
VREFHI
= –10 V, Note 2
Glitch Impulse Code Transition = 7FFH to 800H, Note 2 64 nV-s
LOGIC CHARACTERISTICS
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
Input Capacitance C
LOGIC TIMING CHARACTERISTICS
2, 5
Data Setup Time t
Data Hold t
Clock Pulse Width HIGH t
Clock Pulse Width LOW t
Select Time t
Deselect Delay t
Load Disable Time t
Load Delay t
Load Pulse Width t
Clear Pulse Width t
INH
INL
IN
IN
DS
DH
CH
CL
CSS
CSH
LD1
LD2
LDW
CLRW
Note 2 13 pF
2.4 V
0.8 V
10 µA
25 ns
20 ns
30 ns
50 ns
55 ns
15 ns
40 ns
15 ns
45 ns
70 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSRR 0.002 0.01 %/%
Positive Supply Current I
Negative Supply Current I
Power Dissipation P
NOTES
1
All supplies can be varied ±5% and operation is guaranteed.
2
Guaranteed but not tested.
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
V
swing between +10 V and –10 V.
OUT
5
All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
Typical values indicate performance measured at +25°C.
Specifications subject to change without notice.
DD
SS
DISS
–8 –5 mA
69 mA
255 mW
REV. 0
–3–
DAC8420
10
SDI
9
GND
8
VSS
7
VOUTA
CLR
15
CLSEL
16
(SUBSTRATE)
VDD
1
VOUTD
2
VOUTC 3
VREFLO 4
VREFHI 5
VOUTB 6
11 CLK
12 CS
14 LD
13 NC
NC = NO CONNECT
WAFER TEST LIMITS
(at VDD = +15.0 V, VSS = –15.0 V, V
unless otherwise noted)
= +10.0 V, V
REFHI
= –10.0 V, TA = +258C
REFLO
DAC8420G
Parameter Symbol Conditions Limit Units
Integral Linearity INL ±1 LSB max
Differential Linearity DNL ±1 LSB max
Min-Scale Offset ±1 LSB max
Max-Scale Offset ±1 LSB max
Logic Input High Voltage V
Logic Input Low Voltage V
Logic Input Current I
Positive Supply Current I
Negative Supply Current I
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
SS
V
to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +36.0 V
SS
V
to V
SS
V
VREFHI
V
VREFHI
I
VREFHI
to V
to VDD . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
, I
. . . . . . . . . . . . . . . . . . . . . . –0.3 V, VSS – 2.0 V
VREFLO
VREFLO
. . . . . . . . . . . . . . . . . . . +2.0 V, VDD – V
VREFLO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Digital Input Voltage to GND . . . . . . . . . –0.3 V, V
IN
DD
SS
INH
INL
+ 0.3 V
DD
3. Remove power before inserting or removing units from their
sockets.
4. Analog Outputs are protected from short circuits to ground
or either supply.
SS
DICE CHARACTERISTICS
2.4 V min
0.8 V max
1 µA max
8 mA max
7 mA max
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
EP, FP, ES, FS, EQ, FQ . . . . . . . . . . . . . . –40°C to +85°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Package Type θ
16-Pin Plastic DIP (P) 70
16-Pin Hermetic DIP (Q) 82
16-Lead Small Outline
Surface Mount (S) 86
NOTES
1
θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket.
2
θJA is specified for device on board.
Thermal Resistance
JA
1
1
2
θ
JC
Units
27 °C/W
9 °C/W
22 °C/W
CAUTION
1. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.
2. Digital inputs and outputs are protected, however, permanent
damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam or packaging
at all times until ready to use. Use proper antistatic handling
procedures.
Die Size 0.119 × 0.283 inch, 33,677 sq. mils
×
(3.023
7.188 mm, 21.73 sq. mm)
Transistor Count 2,207
For additional DICE ordering information, refer to databook.
–4–
REV. 0
DAC8420
DATA LOAD SEQUENCE
CS
SDI
CLK
LD
DATA LOAD TIMING
SDI
CLK
CS
LD
V
OUT
t
CSS
A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0
t
LD1
t
t
DH
DS
CLEAR TIMING
CLSEL
t
t
t
CL
CH
t
CSH
t
LD2
t
LDW
t
S
±1LSB
CLR
V
OUT
Timing Diagram
CLRW
t
CSH
t
LD2
t
S
±1LSB
+15V
1N4001
–10V
1N4001
+10V
1N4001
–15V
1N4001
10Ω
+
10µF 0.1µF
10Ω
10µF 0.1µF
+
10Ω
+
10µF 0.1µF
10Ω
10µF 0.1µF
+
1
2
NC
NC
3
4
5
5kΩ
6
NC
NC
7
8
NC = NO CONNECT
Burn-In Diagram
DUT
16
15
14
13
12
11
10
9
5kΩ
10kΩ
NC
ORDERING GUIDE
1
Model
DAC8420EP –40°C to +85°C 0.5 Plastic DIP P
DAC8420EQ –40°C to +85°C 0.5 Cerdip Q
DAC8420ES –40°C to +85°C 0.5 SOIC SOL
DAC8420FP –40°C to +85°C 1.0 Plastic DIP P
DAC8420FQ –40°C to +85°C 1.0 Cerdip Q
DAC8420FS –40°C to +85°C 1.0 SOIC SOL
DAC8420QBC –40°C to +85°C 1.0 Dice
NOTES
1
A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.
2
PMI division letter designator.
3
Dice tested at +25°C only.
Temperature INL Package Package
Range (6LSB) Description Option
3
2
REV. 0
–5–
DAC8420
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
DAC-8420
TOP VIEW
(Not to Scale)
DAC-8420
9
16
15
14
13
12
11
10
NC = NO CONNECT
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
NC
CLK
SDI
GND
CLR
LD
CS
TOP VIEW
(Not to Scale)
DAC8420
PIN CONFIGURATIONS
SOL
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
DIP
1
2
3
4
DAC8420
TOP VIEW
5
(Not to Scale)
6
7
8
NC = NO CONNECT
CLSEL
16
15
CLR
LD
14
13
NC
CS
12
CLK
11
SDI
10
9
GND
PIN FUNCTION DESCRIPTION
Power Supplies VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to –15 V.
GND: Digital Ground.
Clock CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with
CS.
Control Inputs (All are CMOS/TTL compatible.)
CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of
midscale (800
). If LOW, the registers are set to zero (000H).
H
CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of
must remain stable while
LD is LOW.
LD, independent of CS. Input data
Data Input (All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST) (LAST)
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
A1 A0 NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
—Address Word— (MSB) —DAC Data Word— (LSB)
NC = Don’t Care.
Reference Inputs VREFHI: Upper DAC ladder reference voltage input. Allowable range is (VDD – 2.5 V) to (V
Analog Outputs VOUTA through VOUTD: Four buffered DAC voltage outputs.
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is V
(V
VREFHI
– 2.5 V).
–6–
VREFLO
+2.5 V).
SS
to
REV. 0
CLK
DAC8420
Table I. Control Function Logic Table
1
CS
1
LD CLR CLSEL Serial Input Shift Register DAC Registers A-D
NC H H L H No Change Loads Midscale Value (800
NC H H L L No Change Loads Zero-Scale Value (000
)
H
H
NC H H ↑ H/L No Change Latches Value
↑ L H H NC Shifts Register One Bit No Change
L ↑ H H NC Shifts Register One Bit No Change
H NC (
) ↓ H NC No Change Loads the Serial Data Word
↑
H NC L H NC No Change Transparent
3
2
NC H H H NC No Change No Change
NC = Don’t Care.
NOTES
1
CS and CLK are interchangeable.
2
Returning CS HIGH while CLK is HIGH avoids an additional “false clock” of serial input data. See Note 1.
3
Do not clock in serial data while LD is LOW.
(000
OPERATION
Introduction
The DAC8420 is a quad, voltage-output 12-bit DAC with serial
digital input, capable of operating from a single +5 V supply.
The straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can accept data at a 10 MHz clock rate when operating from ±15 V
) or midscale (800H), depending on the state of CLSEL as
H
shown in the Digital Function Table. The CLEAR function is
asynchronous and is totally independent of
CS. When CLR
returns HIGH, the DAC outputs remain latched at the reset
value until
LD is strobed, reloading the individual DAC data word
registers with either the data held in the serial input register prior
to the reset, or new data loaded through the serial interface.
supplies. A unique voltage reference structure assures maximum
utilization of DAC output resolution by allowing the user to set
the zero- and full-scale output levels within the supply rails. The
analog voltage outputs are fully buffered, and are capable of
driving a 2 kΩ load. Output glitch impulse during major code
transitions is a very low 64 nV-s (typ).
Digital Interface Operation
The serial input of the DAC-8420, consisting of CS, SDI, and
Table II. DAC Address Word Decode Table
A1 A0 DAC Addressed
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
LD, is easily interfaced to a wide variety of microprocessor serial
ports. As shown in Table I and the Timing Diagram, while
CS
is LOW the data presented to the input SDI is shifted into the
internal serial/parallel shift register on the rising edge of the
clock, with the address MSB first, data LSB last. The data format, shown above, is two bits of DAC address and two “don’t
care” fill bits, followed by the 12-bit DAC data word. Once all
16 bits of the serial data word have been input, the load control
LD is strobed and the word is parallel-shifted out onto the internal data bus. The two address bits are decoded and used to
route the 12-bit data word to the appropriate DAC data register, see the Applications Information.
Correct Operation of CS and CLK
As mentioned in Table I, the control pins CLK and CS require
some attention during a data load cycle. Since these two inputs
are fed to the same logical “OR” gate, their operation is in fact
identical. The user must take care to operate them accordingly
Programming the Analog Outputs
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to the
needs of the application. Instead of spending DAC resolution
on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table III and Figure 1, the outputs of DACs A through D
range between VREFHI and VREFLO, within the limits specified in the Electrical Characteristics tables. Note also that
VREFHI must be greater than VREFLO.
V
DD
V
VREFHI
2.5V MIN
FFF
H
in order to avoid clocking in false data bits. As shown in the
Timing Diagram, CLK must be either halted HIGH, or
brought HIGH during the last HIGH portion of the CLK fol-
CS
2.5V MIN
1 LSB
lowing the rising edge which latched in the last data bit. Otherwise, an additional rising edge is generated by
CLK is LOW, causing
CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
be considered in the beginning of the data load sequence also.
Using CLR and CLSEL
The CLEAR (CLR) control allows the user to perform an asynchronous reset function. Asserting
CLR loads all four DAC data
CS rising while
000
V
VREFLO
V
H
0V MIN
SS
–10V MIN
Figure 1. Output Voltage Range Programming
word registers, forcing the DAC outputs to either zero-scale
)
REV. 0
–7–
DAC8420
1.2
0
1000
0.6
0.2
200
0.4
0
1.0
0.8
800600400
T = HOURS OF OPERATION AT +125°C
ZERO-SCALE ERROR WITH R
L
= 2k – LSB
x + 3σ
x
x – 3σ
CURVES NOT NORMALIZED
V
DD
= +15V, V
SS
= –15V
V
VREFHI
= +10V
V
VREFLO
= –10V
Ω
Table III. Analog Output Code
DAC Data Word (HEX) V
FFF
OUT
VREFLO +
(VREFHI –VREFLO )
801
VREFLO +
(VREFHI –VREFLO )
800
7FF
000
VREFLO +
VREFLO +
VREFLO +
(VREFHI –VREFLO )
(VREFHI –VREFLO )
(VREFHI –VREFLO )
Typical Performance Characteristics
0.3
0.2
0.1
0
DNL – LSB
–0.1
–0.2
–0.3
–6
–4
TA = +25°C
V
= +15V, V
DD
V
VREFLO
V
VREFHI
– V
= –10V
SS
= –15V
121086420–2
Figure 2. Differential Linearity vs.
±
VREFHI (
15 V)
14
0.10
0.05
0
–0.05
–0.10
DNL – LSB
–0.15
–0.20
–0.25
–0.30
Figure 3. Differential Linearity vs.
VREFHI (+5 V)
1.5
4096
4096
4096
4096
4096
V
VREFHI
TA = +25°C
V
= +5V, VSS = 0V
DD
= 0V
V
VREFLO
– V
× 4095
×2049
×2048
×2047
×0
3.53.02.52.0
Note
Full-Scale Output
Midscale + 1
Midscale
Midscale – 1
Zero Scale
0.3
0.2
0.1
0
INL – LSB
–0.1
–0.2
–0.3
–4
–6
TA = +25°C
V
DD
V
VREFLO
V
VREFHI
= +15V, V
= –10V
– V
SS
= –15V
121086420–2
Figure 4. INL vs. VREFHI (±15 V)
14
0.4
0.3
0.2
0.1
0
INL – LSB
–0.1
–0.2
–0.3
–0.4
Figure 5. INL vs. VREFHI (+5 V)
1.5
V
VREFHI
TA = +25°C
= +5V, V
V
DD
V
VREFLO
– V
= 0V
SS
= 0V
3.53.02.52.0
0.7
0.5
Ω
= 2k – LSB
L
0.3
0.1
–0.1
–0.3
FULL-SCALE ERROR WITH R
–0.5
200
0
T = HOURS OF OPERATION AT +125°C
CURVES NOT NORMALIZED
V
DD
V
VREFHI
V
VREFLO
= +15V, V
= +10V
= –10V
SS
800600400
Figure 6. Full-Scale Error vs.
Time Accelerated by Burn-In
–8–
x + 3σ
= –15V
x
x – 3σ
1000
Figure 7. Zero-Scale Error vs.
Time Accelerated by Burn-In
REV. 0
DAC8420
0.9
–0.9
4500
–0.5
–0.7
5000
–0.1
–0.3
0.1
0.3
0.5
0.7
4000350030002500200015001000
TA = +25°C
V
DD
= +15V, V
SS
= –15V
V
VREFHI
= +10V
V
VREFLO
= –10V
DIGITAL INPUT CODE
ERROR – ±LSB
+0.8
–0.2
–0.4
5000
+0.1
–0.1
0
+0.2
+0.3
+0.4
+0.6
+0.5
+0.7
3500 400030002500200015001000
TA = +25, –55, 125°C
V
DD
= +15V, V
SS
= –15V
V
VREFHI
= +10V
V
VREFLO
= –10V
DIGITAL INPUT CODE
INL – LSB
–0.3
4500
0.2
V
= +15V, V
DD
0.1
V
VREFHI
V
0
VREFLO
–0.1
–0.2
–0.3
–0.4
FULL-SCALE ERROR – LSB
–0.5
–0.6
–50–75
= –15V
SS
= +10V
= –10V
DAC C
TEMPERATURE – °C
DAC D
DAC A
DAC B
Figure 8. Full-Scale Error vs.
Temperature
+1.5
+1.0
+0.5
0
ERROR – LSB
–0.5
–1.0
–1.5
500
0
TA = +25°C
V
= +5V, V
DD
V
= +2.5V
VREFHI
V
= 0V
VREFLO
DIGITAL INPUT CODE
SS
Figure 11. Channel-to-Channel
Matching +5/+2.5
1007550250–25
= 0V
4000350030002500200015001000
125
4500
1.2
V
= +15V, V
DD
1.0
V
VREFHI
0.8
V
VREFLO
0.6
0.4
0.2
DAC A
0
ZERO-SCALE ERROR – LSB
–0.2
–0.4
–50–75
= –15V
SS
= +10V
= –10V
DAC B
TEMPERATURE – °C
Figure 9. Zero-Scale Error vs.
Temperature
13
12
11
10
9
– mA
8
DD
I
7
6
5
4
–5–7
Figure 12. IDD vs. V
TA = +25°C
V
V
0
V
VREFHI
= +15V, V
DD
VREFLO
= –10V
– V
VREFHI
DACs HIGH
DAC C
DAC D
= –15V
SS
, All
1007550250–25
125
Figure 10. Channel-to-Channel
±
Matching
13
1197531–1–3
15/±10
Figure 13. INL vs. Code ±15/±10
+1.5
+1.0
+0.5
– mA
0
VREFHI
I
TA = +25°C
V
DD
–0.5
V
VREFHI
V
VREFLO
–1.0
500
0
Figure 14. I
REV. 0
= +15V, V
= –15V
SS
= +10V
= –10V
DIGITAL INPUT CODE
VREFHI
vs. Code
–250µV
LD
1.22mV
1 LSB
0mV
TA = +25°C
= +5V, V
V
DD
V
VREFHI
V
4000350030002500200015001000
–10.25mV
t
SETT
≈ 8µs
VREFLO
SS
= +2.5V
= –2.5V
= –5V
45.1µs–4.9µs 5µs/DIV
Figure 15. Settling Time (+)(±5 V)
6.5mV
CLR
TA = +25°C
= +5V, V
V
0mV
1 LSB
–1.22mV
–3.5mV
t
SETT
≈ 8µs
DD
V
VREFHI
V
VREFLO
SS
= +2.5V
= –2.5V
Figure 16. Settling Time (–)(±5 V)
= –5V
+45.1µs–4.9µs +5µs/DIV
–9–
DAC8420
+31.25mV
LD
TA = +25°C
V
= +15V, V
4.88mV
1 LSB
0mV
–18.75mV
–9.8µs
t
SETT
≈ 13µs
DD
V
VREFHI
V
VREFLO
+10µs/DIV
= +10V
= –10V
SS
Figure 17. Settling Time (+)(±15 V)
+25V
LD
CLR
+5V
/DIV
0
TA = +25°C
–25V
V
DD
V
VREFHI
SR
= +15V, V
RISE
SS
= +10V, V
= 1.9
µs
= –15V
VREFLO
20µs/DIV
V
SR
= –10V
FALL
= 2.02
V
µs
Figure 20. Slew Rate (±15 V)
= –15V
166.4µs–33.6µs
+90.2µs
+43.75mV
0mV
1 LSB
–4.88mV
–6.25mV
CLR
t
SETT
≈ 13µs
TA = +25°C
V
= +15V, V
DD
V
VREFHI
V
VREFLO
= +10V
= –10V
SS
= –15V
Figure 18. Settling Time (–)(±15 V)
+10
0
–10
–20
GAIN – dB
–30
TA = +25°C
V
= +15V, V
DD
V
VREFHI
V
VREFLO
ALL BITS HIGH 200mV p-p
10 100 10M1M100k10k1k
= –15V
SS
= 0 ± 100mV
= –10V
FREQUENCY – Hz
Figure 21. Small-Signal Response
+5V
+1V
/DIV
0
TA = +25°C
V
= +5V, V
DD
V
VREFHI
V
+90.2µs–9.8µs +10µs/DIV
–5V
SR
VREFLO
= 1.65 SR
RISE
V
µs
= +2.5V
= –2.5V
20µs/DIV
SS
= –5V
FALL
= 1.17
152.4µs–47.6µs
V
µs
Figure 19. Slew Rate (±5 V)
100
90
80
70
60
50
40
PSRR – dB
TA = +25°C
30
20
10
0
10
DATA = 000
V
DD
V
VREFHI
V
VREFLO
H
= +15V ±1V, V
= +10V
= –10V
100 1k 10k 100k 1M
FREQUENCY – Hz
SS
= –15V
Figure 22. PSRR vs. Frequency
6
4
2
V
= +15V
DD
V
= –15V
SS
0
V
= +10V
VREFHI
V
= –10V
VREFLO
ALL DACS HIGH (FULL SCALE)
–2
–4
POWER SUPPLY CURRENT – mA
–6
–75
TEMPERATURE – °C
I
DD
I
SS
750
Figure 23. Power Supply Current
vs. Temperature
150
VOUTA THROUGH VOUTD
T
= +25°C
A
V
= +15V
DD
V
= –15V
SS
V
= +10V
VREFHI
V
= –10V
VREFLO
DATA = 800
H
10mA/DIV
5V/DIV
Figure 24. DAC Output Current vs.
VOUTX
10
8
6
PEAK – V
4
OUT
V
2
0
10 100 10k1k
LOAD RESISTANCE – Ω
TA = +25°C
V
= +15V
DD
V
= –15V
SS
V
= +10V
VREFHI
V
VREFLO
DATA = FFFH OR 000
Figure 25. Output Swing vs.
Load Resistance
= –10V
H
–10–
REV. 0
DAC8420
100µF
ELECT.
10–22µF
TANT.
0.1µF
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
+5V
+5V
RETURN
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
VREFHI Input Requirements
The DAC8420 utilizes a unique, patented DAC switch driver
circuit which compensates for different supply, reference voltage, and digital code inputs. This ensures that all DAC ladder
switches are always biased equally, ensuring excellent linearity
under all conditions. Thus, as indicated in the specifications,
the VREFHI input of the DAC8420 will require both sourcing
and sinking current capability from the reference voltage source.
Many positive voltage references are intended as current sources
only, and offer little sinking capability. The user should consider
references such as the AD584, AD586, AD587, AD588, AD780,
and REF43 in this application.
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The DAC8420 has a single ground pin
that is internally connected to the digital section as the logic
reference level. The first thought may be to connect this pin to
the digital ground; however, in large systems the digital ground
is often noisy because of the switching currents of other digital
circuitry. Any noise that is introduced at the ground pin could
couple into the analog output. Thus, to avoid error causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to reduce any effects of parasitic inductance and ohmic drops. A
ground plane is recommended if possible. The noise immunity
of the onboard digital circuitry, typically in the hundreds of millivolts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected together at a
single point in the system to provide a common reference.
This is preferably done at the power supply.
Good grounding practice is essential to maintaining analog
performance in the surrounding analog support circuitry as well.
With two reference inputs, and four analog outputs capable of
moderate bandwidth and output current, there is a significant
potential for ground loops. Again, a ground plane is recommended as the most effective solution to minimizing errors due
to noise and ground offsets.
+V
S
0.1µF10µF
–V
S
Figure 26. Recommended Supply Bypassing Scheme
0.1µF10µF
REV. 0
1
VDD
89
10µF = TANTALUM
0.1µF = CERAMIC
VSS
GND
–11–
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 26 shows the recommended capacitor values of 10 µF in parallel with 0.1 µF. The
0.1 µF cap should have low “Effective Series Resistance” (ESR)
and “Effective Series Inductance” (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching. In order to preserve the specified analog performance of the device, the supply should be as noise free as possible. In the case of 5 V only systems it is desirable to use the
same 5 V supply for both the analog circuitry and the digital
portion of the circuit. Unfortunately, the typical 5 V supply is
extremely noisy due to the fast edge rates of the popular CMOS
logic families which induce large inductive voltage spikes, and
busy microcontroller or microprocessor busses which commonly
have large current spikes during bus activity. However, by properly filtering the supply as shown in Figure 27, the digital 5 V
supply can be used. The inductors and capacitors generate a filter that not only rejects noise due to the digital circuitry, but
also filters out the lower frequency noise of switch mode power
supplies. The analog supply should be connected as close as
possible to the origin of the digital supply to minimize noise
pickup from the digital section.
Figure 27. Single-Supply Analog Supply Filter
Analog Outputs
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from ±15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The designer
should verify that the output load meets the capabilities of the
device, in terms of both output current and load capacitance.
The DAC8420 is stable with capacitive loads up to 2 nF typical.
However, any capacitive load will increase the settling time, and
should be minimized if speed is a concern.
The output stage includes a p-channel MOSFET to pull the
output voltage down to the negative supply. This is very important in single supply systems, where VREFLO usually has the
same potential as the negative supply. With no load, the
zero-scale output voltage in these applications will be less than
500 µV typically, or less than 1 LSB when V
VREFHI
= 2.5 V.
However, when sinking current this voltage does increase
because of the finite impedance of the output stage. The effective value of the pull-down resistor in the output stage is
typically 320 Ω. With a 100 kΩ resistor connected to +5 V, the
resulting zero-scale output voltage is 16 mV. Thus, the best
DAC8420
single supply operation is obtained with the output load
connected to ground, so the output stage does not have to sink
current.
Like all amplifiers, the DAC8420 output buffers do generate
voltage noise, 52 nV/√
Hz typically. This is easily reduced by
adding a simple RC low-pass filter on each output.
Reference Configuration
The two reference inputs of the DAC8420 allow a great deal of
flexibility in circuit design. The user must take care, however, to
observe the minimum voltage input levels on VREFHI and
VREFLO to maintain the accuracy shown in the data sheet.
These input voltages can be set anywhere across a wide range
within the supplies, but must be a minimum of 2.5 V apart in
any case. See Figure 1. A wide output voltage range can be
obtained with ±5 V references, which can be provided by the
AD588 as shown in Figure 28. Many applications utilize the
1µF
7
7
R
B
A1
R2
R3
A2
6
5
9
6
4 3
A3
1
AD588
R1
10
R4
R5
R6
12
8
13
11
14
15
A4
2
+V
S
0.1µF
–V
16
S
0.1µF
+5V
–5V
+15V
SUPPLY
SYSTEM
GROUND
–15V
SUPPLY
DACs to synthesize symmetric bipolar wave forms, which
requires an accurate, low drift bipolar reference. The AD588
provides both voltages and needs no external components. Additionally, the part is trimmed in production for 12-bit accuracy
over the full temperature range without user calibration. Performing a Clear with the reset select CLSEL HIGH allows the
user to easily reset the DAC outputs to midscale, or zero volts in
these applications.
When driving the reference inputs VREFHI and VREFLO, it is
important to note that VREFHI both sinks and sources current,
and that the input currents of both are code dependent. Many
voltage reference products have limited current sinking capability and must be buffered with an amplifier to drive VREFHI, in
order to maintain overall system accuracy. The input VREFLO,
however, has no such requirement.
+15V SUPPLY
DAC-8420
DIGITAL
CONTROL
DIGITAL INPUTS
5
DAC A
DAC B
DAC C
DAC D
GND
+5V
VREFHI
4915 1614121110 8
VREFLO
–5V
1
0.1µF
VOUTA
7
VOUTB
6
VOUTC
3
VOUTD
2
0.1µF
Figure 28.±10 V Bipolar Reference Configuration Using the AD588
–12–
–15V SUPPLY
REV. 0
DAC8420
10kΩ
10kΩ
+5V
10kΩ
LD
SCLK
SDI
+5V
REG
+5V
POWER
HIGH VOLTAGE
ISOLATION
+5V
+5V
0.1µF
+5V
CLR
CLSEL
CLK
SDI
LD
CS
4
5
VREFHI
VREFLO VSS
GND
1µF
10kΩ
DAC-8420
VOUTA
VOUTB
VOUTC
VOUTD
REF-43
VOUT
GND
VIN
+5V
6
2
4
2.5V
9
8
1
6
7
3
2
11
10
14
16
15
12
VDD
For a single 5 V supply, V
is limited to at most 2.5 V, and
VREFHI
must always be at least 2.5 V less than the positive supply to
ensure linearity of the device. For these applications, the REF43
is an excellent low drift 2.5 V reference that consumes only
450 µA (max). It works well with the DAC8420 in a single 5 V
system as shown in Figure 29.
+5V SUPPLY
0.1µF
VIN
2
4
DAC-8420
DIGITAL
CONTROL
REF-43
VOUTGND
+5V SUPPLY
2.5V
6
VREFHI
5
DAC A
DAC B
DAC C
DAC D
1
0.1µF
VOUTA
7
6
VOUTB
VOUTC
3
2
VOUTD
One opto-isolated line (
LD) can be eliminated from this circuit
by adding an inexpensive 4-bit TTL Counter to generate the
Load pulse for the DAC8420 after 16 clock cycles. The counter
is used to count of the number of clock cycles loading serial data
to the DAC8420. After all 16 bits have been clocked into the
converter, the counter resets, and a load pulse is generated on
clock 17. In either circuit, the DAC8420’s serial interface provides a simple, low cost method of isolating the digital control.
915 1614121110 8
4
GND VREFLO
DIGITAL INPUTS
Figure 29. +5 V Single Supply Operation Using REF43
Isolated Digital Interface
Because the DAC8420 is ideal for generating accurate voltages
in process control and industrial applications, due to noise,
safety requirements, or distance, it may be necessary to isolate it
from the central controller. This can be easily achieved by using
opto-isolators, which are commonly used to provide electrical
isolation in excess of 3 kV. Figure 30 shows a simple 3-wire
interface scheme to control the clock, data, and load pulse. For
normal operation,
CS is tied permanently LOW so that the
DAC8420 is always selected. The resistor and capacitor on the
CLR pin provide a power-on reset with 10 ms time constant. The
three opto-isolators are used for the SDI, CLK, and
REV. 0
LD lines.
–13–
Figure 30. Opto-lsolated 3-Wire Interface
Dual Window Comparator
Often a comparator is needed to signal an out-of-range warning.
Combining the DAC8420 with a quad comparator such as the
CMP04 provides a simple dual window comparator with adjustable trip points as shown in Figure 31. This circuit can be
operated with either a dual or a single supply. For the A input
channel, DAC B sets the low trip point and DAC A sets the upper trip point. The CMP04 has open-collector outputs that are
connected together in “Wired-OR” configuration to generate an
out-of-range signal. For example, when VINA goes below the
trip point set by DAC B, comparator C2 pulls the output down,
turning the red LED on. The output can also be used as a logic
signal for further processing.
DAC8420
+5V SUPPLY
0.1µF
REF-43
VIN
2
4
GND
DAC-8420
DIGITAL
CONTROL
DIGITAL INPUTS
+5V SUPPLY
2.5V
6
V
OUT
VREFHI
DAC A
DAC B
DAC C
DAC D
15 1614121110
49
GND VREFLO
15
8
VSS
0.1µF
VOUTA
7
VOUTB
6
VOUTC
3
VOUTD
2
VINA
VINB
+5V
0.1µF
3
CMP-04
5
C1
4
7
C2
6
9
C3
8
11
C4
10
2
1
14
13
12
+5V
604Ω
RED LED
OUT A
+5V
604Ω
RED LED
OUT B
Figure 31. Dual Programmable Window Comparator
MC68HC11 Microcontroller Interfacing
Figure 32 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
68HC11 drives the CLK input of the DAC, and the MOSI port
outputs the serial data to load into the SDI input of the DAC.
The port lines PD5, PC0, PC1, and PC2 provide the controls to
the DAC as shown.
PC2
PC1
PC0
MC68HC11*
(PD5) SS
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
CLSEL
CLR
CS
DAC-8420*
LD
CLK
SDI
Figure 32. MC68HC11 Microcontroller Interface
For correct operation, the 68HC11 should be configured such
that its CPOL bit and CPHA bit are both set to 1. In this configuration, serial data on MOSI of the 68HC11 is valid on the
rising edge of the clock, which is the required timing for the
DAC8420 Data is transmitted in 8-bit bytes (MSB first), with
only eight rising clock edges occurring in the transmit cycle. To
load data to the DAC8420’s input register, PC0 is taken low
and held low during the entire loading cycle. The first 8 bits are
shifted in address first, immediately followed by another 8 bits
in the second least-significant byte to load the complete 16-bit
word. At the end of the second byte load, PC0 is then taken
high. To prevent an additional advancing of the internal shift
register, SCK must already be asserted before PC0 is taken
high. To transfer the contents of the input shift register to the
DAC register, PD5 is then taken low, asserting the
LD input of
the DAC and completing the loading process. PD5 should return high before the next load cycle begins. The DAC8420’s
CLR input, controlled by the output PC1, provides an asynchronous clear function.
–14–
REV. 0
DAC8420 to M68HC11 Interface Assembly Program
*
M68HC11 Register Definitions
PORTC EQU $1003 Port C control register
* “0,0,0,0;0,CLSEL,
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
* “0,0,
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL,0,MODF;0,0,0,0”
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* To select: DAC A – Set SDI1 to $0X
* DAC requires two 8-bit loads – Address + 12 bits
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8”
SDI2 EQU $01 SDI packed byte 2
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
* Main Program
ORG $C000 Start of user’s RAM in EVB
INIT LDS #$CFFF Top of C page RAM
* Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
* CLSEL-Hi,
* To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
* To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
STAA PORTC Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
STAA DDRC CLSEL,
* Initialize Port D Outputs
LDAA #$30 0,0,1,1;0,0,0,0
*
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
STAA DDRD
LD,SCLK;SDI,0,0,0”
DAC B – Set SDI1 to $4X
DAC C – Set SDI1 to $8X
DAC D – Set SDI1 to $CX
SDI2 is encoded from 00 (Hex) to FF (Hex)
LD-Hi,SCLK-Hi,SDI-Lo
LD,SCLK, and SDI are now enabled as outputs
CLR,CS”
CLR-Hi, CS-Hi
CLR, and CS are now enabled as outputs
DAC8420
* Initialize SPI Interface
LDAA #$5F
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
* Call update subroutine
BSR UPDATE Xfer 2 8-bit words to DAC-8420
JMP $E000 Restart BUFFALO
* Subroutine UPDATE
UPDATE PSHX Save registers X, Y, and A
PSHY
PSHA
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
LDAA #$80 1,0,0,0;0,0,0,0
STAA SDI1 SDI1 is set to 80 (Hex)
* Enter Contents of SDI2 Data Register
LDAA #$00 0,0,0,0;0,0,0,0
STAA SDI2 SDI2 is set to 00 (Hex)
LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
* Clear DAC output to zero
BCLR PORTC,Y $02 Assert
BSET PORTC,Y $02 Deassert
* Get DAC ready for data input
BCLR PORTC,Y $01 Assert
TFRLP LDAA 0,X Get a byte to transfer via SPI
STAA SPDR Write SDI data reg to start xfer
WAIT LDAA SPSR Loop to wait for SPIF
BPL WAIT SPIF is the MSB of SPSR
* (when SPIF is set, SPSR is negated)
INX Increment counter to next byte for xfer
CPX #SDI2+ 1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
* Update DAC output with contents of DAC register
BCLR PORTD,Y 520 Assert
BSET PORTD,Y $20 Latch DAC register
BSET PORTC,Y $01 De-assert
PULA When done, restore registers X, Y & A
PULY
PULX
RTS ** Return to Main Program **
CLR
CLR
CS
LD
CS
REV. 0
–15–
DAC8420
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Epoxy DIP
(P Suffix)
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
PIN 1
16
1
0.022 (0.558)
0.014 (0.356)
16
1
0.840 (21.33)
0.745 (18.93)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
16-Pin Wide-Body SOL
9
8
0.4133 (10.50)
0.3977 (10.00)
9
8
(SOL)
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.1043 (2.65)
0.0926 (2.35)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.0291 (0.74)
0.0098 (0.25)
x 45
0.195 (4.95)
0.115 (2.93)
°
C1836–18–9/93
0.0118 (0.30)
0.0040 (0.10)
0.005 (0.13) MIN
PIN 1
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.0500
(1.27)
BSC
16
1
0.023 (0.58)
0.014 (0.36)
0.0192 (0.49)
0.0138 (0.35)
16-Pin Cerdip
(Q Suffix)
0.840 (21.34) MAX
0.100
(2.54)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.080 (2.03) MAX
0.070 (1.78)
0.030 (0.76)
–16–
9
0.310 (7.87)
0.220 (5.59)
8
0.060 (1.52)
0.015 (0.38)
8
°
0
°
0.150
(3.81)
MIN
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
°
0
°
PRINTED IN U.S.A.
REV. 0
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