Analog Devices DAC8143 Datasheet

12-Bit Serial Daisy-Chain

a

FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially

Controlled Systems

Buffered Digital Output Pin for Daisy-Chaining

Multiple DACs

Minimizes Address-Decoding in Multiple DAC

Systems—Three-Wire Interface for Any Number of DACs

One Data Line
One CLK Line

One Load Line
Improved Resistance to ESD
–40ⴗC to +85ⴗC for the Extended Industrial Temperature

Range

APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems

GENERAL INFORMATION

The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter that features serial data input and buffered serial data
output. It was designed for multiple serial DAC systems, where
serially daisy-chaining one DAC after another is greatly simplified.

The DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows three-wire interface for any
number of DACs: one data line, one CLK line and one load line.

Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. The strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (STB

When the shift register’s data has been updated, the new data
word is transferred to the DAC register with use of LD1 and
LD2 inputs.

Separate LOAD control inputs allow simultaneous output up­dating of multiple DACs. An asynchronous CLEAR input
resets the DAC register without altering data in the input
register.

Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo­nents. Fast interface timing reduces timing design considerations
while minimizing microprocessor wait states.

The DAC8143 is available in plastic packages that are compat­ible with autoinsertion equipment.

Plastic packaged devices come in the extended industrial tem-

perature range of –40°C to +85°C.

, STB2, STB3, STB4).

1

CMOS D/A Converter

DAC8143

FUNCTIONAL BLOCK DIAGRAM

V

DD

R

DAC8143

V

CLR

STB
STB
STB
STB

REF

LD

LD

SRI

1

2

1
4
3

2

DGND

ADDRESS BUS

WR

DB

X

mP

12-BIT

D/A CONVERTER

DAC REGISTER

LOAD

CLK

INPUT 12-BIT

SHIFT REGISTER

IN OUT

ADDRESS
DECODER

SRI
SRO

SRI
SRO

SRI
SRO

SRI
SRO

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

Figure 1. Multiple DAC8143s with Three-Wire Interface

FB

I

OUT1

I

OUT2

AGND

SRO

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

DAC8143–SPECIFICATIONS

(@ VDD = +5 V; V

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

STATIC ACCURACY

Resolution N 12 Bits

Nonlinearity INL ±1 LSB

Differential Nonlinearity
Gain Error

2

Gain Tempco (∆Gain/∆Temp)

Power Supply Rejection Ratio

(∆Gain/∆V

) PSRR ∆VDD = ±5% ±0.0006 ±0.002 %/%

DD

Output Leakage Current

Zero Scale Error

Input Resistance

AC PERFORMANCE

Output Current Settling Time
AC Feedthrough Error

to I

(V

REF

OUT1

Digital-to-Analog Glitch Energy

Total Harmonic Distortion

Output Noise Voltage Density

DIGITAL INPUTS/OUTPUT

Digital Input HIGH V
Digital Input LOW V
Input Leakage Current
Input Capacitance C
Digital Output High V

Digital Output Low V

ANALOG OUTPUTS

Output Capacitance

Output Capacitance

TIMING CHARACTERISTICS

Serial Input to Strobe Setup Times t

(t

= 80 ns) t

STB

Serial Input to Strobe Hold Times

= 80 ns) t

(t

STB

5, 6

7

)

3, 9

1

4

3, 8

3, 10

3

3, 11

12

3

3

DNL ±1 LSB

G
TC

I

LKG

I

ZSE

R

t

S

FSE

GFS

IN

3

FT V
QV
THD V

e

n

IH

IL

I

IN

IN

OH

OL

C

OUT1

C

OUT2

C

OUT1

C

OUT2

3

DS1

DS2

t

DS3

t

DS4

t

DH1

t

DH2

DH3

t

DH4

Range specified under Absolute Maximum Ratings, unless otherwise noted.)

T

= +25°C ±5nA

A

T

= Full Temperature Range ±25 nA

A

T

= +25°C ±0.002 ±0.03 LSB

A

T

= Full Temperature Range ±0.01 ±0.15 LSB

A

V

Pin 7 11 15 kΩ

REF

= 20 V p-p @ f = 10 kHz, T

REF

= 0 V, I

REF

= 6 V rms @ 1 kHz

REF

DAC Register Loaded with All 1s –92 dB
10 Hz to 100 kHz Between RFB and I

V

= 0 V to +5 V ±1 µA

IN

VIN = 0 V 8 pF
I

= –200 µA4V

OH

IOL = 1.6 mA 0.4 V

Digital Inputs = All 1s 90 pF
Digital Inputs = All 0s 90 pF
Digital Inputs = All 0s 60 pF
Digital Inputs = All 1s 60 pF

STB1 Used as the Strobe 50 ns
STB2 Used as the Strobe 20 ns
STB3 Used as the Strobe T

STB4 Used as the Strobe 20 ns
STB1 Used as the Strobe T

STB2 Used as the Strobe T

STB3 Used as the Strobe 80 ns
STB4 Used as the Strobe 80 ns

= +10 V; V

REF

Load = 100 Ω, C

OUT

= V

= V

= V

OUT1

OUT2

AGND

= 0 V; TA = Full Temperature

DGND

±2 LSB
±5 ppm/°C

0.380 1 µs

= +25°C 2.0 mV p-p

A

= 13 pF 20 nVs

EXT

OUT

13 nV/√Hz

2.4 V

0.8 V

= +25°C10 ns

A

T

= Full Temperature Range 20 ns

A

= +25°C40 ns

A

= Full Temperature Range 50 ns

T

A

= +25°C50 ns

A

= Full Temperature Range 60 ns

T

A

–2–

REV. C

DAC8143

ELECTRICAL CHARACTERISTICS

(@ VDD = +5 V; V

= +10 V; V

REF

OUT1

= V

0UT2

= V

AGND

= V

DGND

= 0 V; TA = Full

Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)

DAC8143

Parameter Symbol Conditions Min Typ Max Units

STB to SRO Propagation Delay

SRI Data Pulsewidth t

Pulsewidth (STB1 = 80 ns)

STB

1

STB

Pulsewidth (STB2 = 100 ns)

2

Pulsewidth (STB3 = 80 ns)

STB

3

STB

Pulsewidth (STB4 = 80 ns)

4

Load Pulsewidth t

LSB Strobe into Input Register

to Load DAC Register Time t

CLR Pulsewidth t

POWER SUPPLY

Supply Voltage V

Supply Current I

Power Dissipation P

NOTES

11

All grades are monotonic to 12 bits over temperature.

12

Using internal feedback resistor.

13

Guaranteed by design and not tested.

14

Applies to I

15

V

= +10 V, all digital inputs = 0 V.

REF

16

Calculated from worst case R

17

Absolute temperature coefficient is less than +300 ppm/°C.

18

I

, Load = 100 Ω. C

OUT

time constant of the final RC decay.

19

All digital inputs = 0 V.

10

V

= 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.

REF

11

Calculations from e

K = Boltzmann constant, J/KR = resistance Ω
T = resistor temperature, K B = bandwidth, Hz

12

Digital inputs are CMOS gates; I

13

Measured from active strobe edge (STB) to new data output at SRO; CL = 50 pF.

14

Minimum low time pulsewidth for STB1, STB2, and STB4, and minimum high time pulsewidth for STB3.

Specifications subject to change without notice.

; all digital inputs = VIL, V

OUT1

EXT

= √4K TRB where:

n

13

14

14

14

14

t

PD

SRI

t

STB1

t

STB2

t

STB3

t

STB4

LD1

ASB

CLR

DD

DD

D

T

= +25°C 220 ns

A

= Full Temperature Range 300 ns

T

A

100 ns
80 ns
80 ns
80 ns
80 ns

, t

LD2

T

= +25°C 140 ns

A

T

= Full Temperature Range 180 ns

A

0ns
80 ns

4.75 5 5.25 V
All Digital Inputs = VIH or V
All Digital Inputs = 0 V or V
Digital Inputs = 0 V or V

IL

DD

DD

5 V × 0.1 mA

Digital Inputs = V

IH

or V

IL

5 V × 2 mA

= +10 V; specification also applies for I

REF

: I

REF

ZSE

(in LSBs) = (R

REF

× I

× 4096) /V

LKG

REF

.

= 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB: tS = propagation delay (t

typically 1 nA at +25°C.

IN

when all digital inputs = VIH.

OUT2

2mA

0.1 mA

0.5 mW

10 mW

) +9 τ, where τ equals measured

PD

REV. C

–3–

DAC8143

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C, unless otherwise noted.)

A

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

V

REF

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

RFB

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V

Digital Input Voltage Range . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage (Pin 1, Pin 2) . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

DD

DD

Operating Temperature Range

FP/FS Versions . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C

Package Type ␪JA* ␪

JC

Units

16-Lead Plastic DIP 76 33 °C/W
16-Lead SOIC 92 27 °C/W

*θJA is specified for worst case mounting conditions, i.e., θ

device in socket for P-DIP package; θ
printed circuit board for SOIC package.

is specified for device soldered to

JA

is specified for

JA

CAUTION

1. Do not apply voltage higher than VDD or less than DGND po-

tential on any terminal except V

(Pin 15) and RFB (Pin 16).

REF

2. The digital control inputs are Zener-protected; however,

permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.

3. Use proper antistatic handling procedures.

4. Absolute Maximum Ratings apply to packaged devices.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device.

PIN CONNECTIONS

16-Lead Epoxy Plastic DIP

16-Lead SOIC

I

OUT1

I

OUT2

AGND

STB

LD

SRO

SRI

STB

1

2

3

4

1

5

1

(Not to Scale)

6

7

8

2

DAC8143

TOP VIEW

16

R

FB

15

V

REF

14

V

DD

13

CLR

DGND

12

11

STB

4

10

STB

3

9

LD

2

ORDERING GUIDE

Gain Temperature Package Package

Model Nonlinearity Error Range Descriptions Options

DAC8143FP ±1 LSB ±2 LSB –40°C to +85°C 16-Lead Plastic DIP N-16
DAC8143FS ±1 LSB ±2 LSB –40°C to +85°C 16-Lead SOIC R-16W

Die Size: 99 × 107 mil, 10,543 sq. mils.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8143 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. C

Typical Performance Characteristics–

DAC8143

ALL BITS ON

(MSB) B11

B10

B9
B8

(LSB) B0

B7
B6
B5
B4
B3
B2
B1

1k 10k 100k 1M 10M

100

FREQUENCY – Hz

DATA BITS "ON"

(ALL OTHER

DATA BITS "OFF")

Figure 2. Multiplying Mode Frequency
Response vs. Digital Code

3

2

– mA

DD

I

1

0

0

12345

V

– Volts

IN

Figure 4. Supply Current vs. Logic

Input Voltage

0.5

0.4

0.3

0.2

0.1

0.0
–0.1
–0.2

LINEARITY ERROR – LSB

–0.3
–0.4
–0.5

0

Figure 5. Linearity Error vs. Digital

Code

0
12
24
36
48
60
72

ATTENUATION – dB

84
96
108

Figure 3. Multiplying Mode Total Harmonic
Distortion vs. Frequency

1024 2048 3072 40951536 2560 3584512

DIGITAL INPUT CODE – Decimal

–70

VIN = 5V rms
OUTPUT OP AMP: OP-42

–75

–80

THD – dB

–85

–90

–95

10

100 1k 10k 100k

0.032

0.018

0.010

THD – %

0.0056

0.0032

0.0018

FREQUENCY – Hz

0.5

0.25

0

INL – LSB

–0.25

–0.5

2

46 810

– Volts

V

REF

Figure 6. Linearity Error vs. Refer-

ence Voltage

4

3

2.4
2

1

–0.8

THRESHOLD VOLTAGE – Volts

0

3 5 7 9 11 13 1715

1

V

– Volts

DD

Figure 7. Logic Threshold Voltage
vs. Supply Voltage

REV. C

0.5

0.25

0

DNL – LSB

–0.25

–0.5

2

46 810

– Volts

V

REF

Figure 8. DNL Error vs. Reference
Voltage

–5–

40

TA = +258C

30

20

SINK

10

0

–10

–20

OUTPUT CURRENT – mA

SOURCE

–30

–40

12345

0

SRO – VOLTAGE OUT – Volts

LOGIC 0

LOGIC 1

Figure 9. Digital Output Voltage vs.
Output Current

DAC8143

(

)

DEFINITION OF SPECIFICATIONS

RESOLUTION

The resolution of a DAC is the number of states (2n) into which
the full-scale range (FSR) is divided (or resolved), where “n” is
equal to the number of bits.

SETTLING TIME

Time required for the analog output of the DAC to settle to
within 1/2 LSB of its final value for a given digital input stimu­lus; i.e., zero to full-scale.

GAIN

Ratio of the DAC’s external operational amplifier output voltage
to the V

input voltage when all digital inputs are HIGH.

REF

FEEDTHROUGH ERROR

Error caused by capacitive coupling from V

to output.

REF

Feedthrough error limits are specified with all switches off.

OUTPUT CAPACITANCE

Capacitance from I

to ground.

OUT1

OUTPUT LEAKAGE CURRENT

Current appearing at I
at I

terminal when all inputs are HIGH.

OUT2

when all digital inputs are LOW, or

OUT1

GENERAL CIRCUIT INFORMATION

The DAC8143 is a 12-bit serial-input, buffered serial-output,
multiplying CMOS D/A converter. It has an R-2R resistor lad­der network, a 12-bit input shift register, 12-bit DAC register,
control logic circuitry, and a buffered digital output stage.

The control logic forms an interface in which serial data is
loaded, under microprocessor control, into the input shift regis­ter and then transferred, in parallel, to the DAC register. In
addition, buffered serial output data is present at the SRO pin
when input data is loaded into the input register. This buffered
data follows the digital input data (SRI) by 12 clock cycles and
is available for daisy-chaining additional DACs.

An asynchronous CLEAR function allows resetting the DAC
register to a zero code (0000 0000 0000) without altering data
stored in the registers.

A simplified circuit of the DAC8143 is shown in Figure 10. An
inversed R-2R ladder network consisting of silicon-chrome,
thin-film resistors, and twelve pairs of NMOS current-steering
switches. These switches steer binarily weighted currents into
either I

OUT1

or I

. Switching current to I

OUT2

OUT1

or I

OUT2

yields
a constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resis­tance at V

equal to R (typically 11 kΩ). The V

REF

input may

REF

be driven by any reference voltage or current, ac or dc, that is
within the limits stated in the Absolute Maximum Ratings chart.

The twelve output current-steering switches are in series with
the R-2R resistor ladder, and therefore, can introduce bit errors.
It was essential to design these switches such that the switch
“ON” resistance be binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch 1

of Figure 10 was designed with an “ON” resistance of 10 Ω,
Switch 2 for 20 Ω, etc., a constant 5 mV drop would then be

maintained across each switch.

To further ensure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
The Simplified DAC Circuit, Figure 10, shows the location of
these switches. These series switches are equivalently scaled to
two times Switch 1 (MSB) and top Switch 12 (LSB) to main­tain constant relative voltage drops with varying temperature.
During any testing of the resistor ladder or R
incoming inspection), V

must be present to turn “ON” these

DD

FEEDBACK

(such as

series switches.

V

REF

20kV 20kV 20kV 20kV 20kV

S

1

BIT 1 (MSB) BIT 12 (LSB)BIT 3BIT 2

SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH"

S

2

DIGITAL INPUTS

10kV10kV10kV

S

3

S

12

*

I

OUT2

I

10kV

*

*

THESE SWITCHES

PERMANENTLY "ON"

OUT1

R

FEEDBACK

Figure 10. Simplified DAC Circuit

–6–

REV. C

DAC8143

V

OS

V

REF

RR R

ETC

R

FB

R

2

R

2

R

2

OP-77

ESD PROTECTION

The DAC8143 digital inputs have been designed with ESD
resistance incorporated through careful layout and the inclusion
of input protection circuitry.

Figure 11 shows the input protection diodes. High voltage static
charges applied to the digital inputs are shunted to the supply
and ground rails through forward biased diodes.

These protection diodes were designed to clamp the inputs well
below dangerous levels during static discharge conditions.

V

DD

DTL/TTL/CMOS

INPUTS

Figure 11. Digital Input Protection

EQUIVALENT CIRCUIT ANALYSIS

Figures 12 and 13 show equivalent circuits for the DAC8143’s
internal DAC with all bits LOW and HIGH, respectively. The
reference current is switched to I
and to I

when all bits are HIGH. The I

OUT1

when all data bits are LOW,

OUT2

LEAKAGE

current
source is the combination of surface and junction leakages to the
substrate. The 1/4096 current source represents the constant
1-bit current drain through the ladder’s terminating resistor.

Output capacitance is dependent upon the digital input code.
This is because the capacitance of a MOS transistor changes
with applied gate voltage. This output capacitance varies be­tween the low and high values.

R

R = 10kV

I

I

REF

R = 10kV

V

REF

1/4096

LEAKAGE

I

LEAKAGE

60pF

90pF

FEEDBACK

I

OUT1

I

OUT2

DYNAMIC PERFORMANCE

ANALOG OUTPUT IMPEDANCE

The output resistance, as in the case of the output capacitance,
varies with the digital input code. This resistance, looking back
into the I

terminal, varies between 11 kΩ (the feedback

OUT1

resistor alone when all digital input are LOW) and 7.5 kΩ (the
feedback resistor in parallel with approximately 30 kΩ of the

R-2R ladder network resistance when any single bit logic is
HIGH). Static accuracy and dynamic performance will be af­fected by these variations.

The gain and phase stability of the output amplifier, board
layout, and power supply decoupling will all affect the dynamic
performance of the DAC8143. The use of a small compensation
capacitor may be required when high speed operational amplifi­ers are used. It may be connected across the amplifier’s feed­back resistor to provide the necessary phase compensation to
critically damp the output.

The considerations when using high speed amplifiers are:

1. Phase compensation (see Figures 16 and 17).

2. Power supply decoupling at the device socket and use of
proper grounding techniques.

OUTPUT AMPLIFIER CONSIDERATIONS

When using high speed op amps, a small feedback capacitor
(typically 5 pF–30 pF) should be used across the amplifiers to
minimize overshoot and ringing. For low speed or static
applications, ac specifications of the amplifier are not very criti­cal. In high speed applications, slew rate, settling time, open­loop gain and gain/phase margin specifications of the amplifier
should be selected for the desired performance. It has already
been noted that an offset can be caused by including the usual
bias current compensation resistor in the amplifier’s noninvert­ing input terminal. This resistor should not be used. Instead, the
amplifier should have a bias current that is low over the tem­perature range of interest.

Static accuracy is affected by the variation in the DAC’s output
resistance. This variation is best illustrated by using the circuit
of Figure 14 and the equation:

V

ERROR

= VOS






1+



R

FB



R



O

Figure 12. Equivalent Circuit (All Inputs LOW)

R

I

REF

R = 10kV

V

REF

Figure 13. Equivalent Circuit (All Inputs HIGH)

REV. C

1/4096

I

LEAKAGE

I

LEAKAGE

R = 10kV

90pF

60pF

FEEDBACK

I

OUT1

I

OUT2

Figure 14. Simplified Circuit

–7–

DAC8143

Where RO is a function of the digital code, and:

R

= 10 kΩ for more than four bits of Logic 1,

O

R

= 30 kΩ for any single bit of Logic 1.

O

Therefore, the offset gain varies as follows:

at code 0011 1111 1111,

V

ERROR1

= VOS



1+





10 kΩ
10 kΩ




= 2 V



OS

at code 0100 0000 0000,

V

ERROR2

= VOS



1+





10 kΩ
30 kΩ




= 4/3 V



OS

The error difference is 2/3 VOS.

Since one LSB has a weight (for V
the DAC8143, it is clearly important that V

= +10 V) of 2.4 mV for

REF

be minimized,

OS

using either the amplifier’s pulling pins, an external pulling
network, or by selection of an amplifier with inherently low V
Amplifiers with sufficiently low V

include OP77, OP97, OP07,

OS

OS

.

OP27, and OP42.

INTERFACE LOGIC OPERATION

The microprocessor interface of the DAC8143 has been design­ed with multiple STROBE and LOAD inputs to maximize inter­facing options. Control signals decoding may be done on chip or
with the use of external decoding circuitry (see Figure 21).

Serial data is clocked into the input register and buffered output
stage with STB

, STB2, or STB4. The strobe inputs are active

1

on the rising edge. STB3 may be used with a falling edge clock
data.

Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.

Holding any STROBE input at its selected state (i.e., STB
STB

or STB4 at logic HIGH or STB3 at logic LOW) will act to

2

,

1

prevent any further data input.

When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.

The CLR input allows asynchronous resetting of the DAC regis­ter to 0000 0000 0000. This reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will
result in the analog output going to 0 V. In bipolar mode, the
output will go to –V

REF

.

INTERFACE INPUT DESCRIPTION

STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11)—Input Register
and Buffered Output Strobe. Inputs Active on Rising
Edge. Selected to load serial data into input register and buff-

ered output stage. See Table I for details.

STB3 (Pin 10)—Input Register and Buffered Output
Strobe Input. Active on Falling Edge. Selected to load serial

data into input register and buffered output stage. See Table I
for details.

LD1 (Pin 5), LD2

(Pin 9)—Load DAC Register Inputs.

Active Low. Selected together to load contents of input register

into DAC register.

CLR (Pin 13)—Clear Input. Active Low. Asynchronous.

When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.

t

, t

DS1

SRO

* STROBE

(STB1, STB2, STB4)

LD1 AND LD

SRI

, t

DS2

DS3

2

NOTES:

* STROBE WAVEFORM IS INVERTED IF

STB
BITS INTO INPUT REGISTER.

** DATA IS STROBED INTO AND OUT OF

THE INPUT SHIFT REGISTER MSB FIRST.

MSB

, t

DS4

MSB

t
t
t
t

IS USED TO STROBE SERIAL DATA

3

WORD N –2 WORD N –1 WORD N

BIT 2BIT 1

t

PD

12 12 1 2

STB1
STB2
STB3
STB4

LOAD NEW 12-BIT WORD INTO

INPUT REGISTER AND SHIFT

OUT PREVIOUS WORD

BIT 2BIT 1

t

, t

, t

DH1

t

STB1

t

STB2

t

STB3

t

STB4

, t

DH2

DH3

DH4

BIT 12

LSB

BIT 1

MSB

t

ASB

t

LD1

t

LD2

LOAD INPUT REGISTER'S
DATA INTO DAC REGISTER

Figure 15. Timing Diagram

BIT 1
MSB

t

BIT 2

WORD NWORD N –1

BIT 11BIT 2 BIT 12

SR1

BIT 12

LSB

LSB

BIT 1

LSB

1211

–8–

REV. C

DAC8143

Table I. Truth Table

DAC8143 Logic Inputs
Input Register/
Digital Output Control Inputs DAC Register Control Inputs
STB

010g XXX
01g 0 X X X Serial Data Bit Loaded from SRI
0 f 0 0 X X X into Input Register and Digital Output 2, 3
g 1 0 0 X X X (SRO Pin) after 12 Clocked Bits.

1XXX
X 0 X X No Operation (Input Register and SRO) 3
XX1X
XXX1

NOTES

1

CLR = 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register.

2

Serial data is loaded into Input Register MSB first, on edges shown. g is positive edge, f is negative edge.

3

0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.

STB3 STB

4

STB1CLR LD2 LD1 DAC8143 Operation Notes

2

Reset DAC Register to Zero Code

0 X X (Code: 0000 0000 0000) 1, 3

(Asynchronous Operation)

1 1 X No Operation (DAC Register and SRO) 3
1X1

1 0 0 Load DAC Register with the Contents 3

of Input Register

APPLICATIONS INFORMATION

UNIPOLAR OPERATION (2-QUADRANT)

The circuit shown in Figures 16 and 17 may be used with an ac
or dc reference voltage. The circuit’s output will range between
0 V and +10(4095/4096) V depending upon the digital input
code. The relationship between the digital input and the analog
output is shown in Table II. The V

voltage range is the maxi-

REF

mum input voltage range of the op amp or ±25 V, whichever is

lowest.

Table II. Unipolar Code Table

Digital Input Nominal Analog Output

as Shown

(V

OUT

MSB LSB in Figures 16 and 17)





4095

1 1 1 1 1 1 1 1 1 1 1 1 –V

1 0 0 0 0 0 0 0 0 0 0 1 –V

1 0 0 0 0 0 0 0 0 0 0 0 –V

0 1 1 1 1 1 1 1 1 1 1 1 –V

0 0 0 0 0 0 0 0 0 0 0 1 –V

0 0 0 0 0 0 0 0 0 0 0 0 –V

NOTES

1

Nominal full scale for the circuits of Figures 16 and 17 is given by

FS = –V

2

Nominal LSB magnitude for the circuits of Figures 16 and 17 is given by

LSB = V

REF

REF





4095





.

4096









1





or V

(2–n).

4096



REF



REV. C

REF

REF

REF

REF

REF

REF



4096



2049



4096
2048



4096

2047



4096



4096



4096







V

REF

= –



2



1



0

= 0



–9–

V

REF

–10V

CLR

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

V

REFVDD

15 14

13

4, 5

DAC8143

8–11
7

DGND

+5V

R

FEEDBACK

I

OUT1

1

I

OUT2

2

AGND

3
6

12

SRO
(BUFFERED
DIGITAL
DATA OUT)

15pF

+15V

2

3

OP-77

–15V

7

6

4

Figure 16. Unipolar Operation with High Accuracy Op
Amp (2-Quadrant)

V

REF

–10V

CLR

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

R1

100V

V

REFVDD

15 14

13

4, 5

DAC8143

8–11
7

DGND

+5V

R

FEEDBACK

R2

15pF

50V

I

OUT1

1

I

OUT2

2

AGND

3
6

12

SRO
(BUFFERED
DIGITAL
DATA OUT)

+15V

2

3

OP-42

–15V

7

6

4

Figure 17. Unipolar Operation with Fast Op Amp and
Gain Error Trimming (2-Quadrant)

V

OUT

V

OUT

DAC8143

In many applications, the DAC8143’s zero scale error and low
gain error, permit the elimination of external trimming compo­nents without adverse effects on circuit performance.

For applications requiring a tighter gain error than 0.024% at

25°C for the top grade part, or 0.048% for the lower grade part,

the circuit in Figure 17 may be used. Gain error may be trimmed
by adjusting R1.

The DAC register must first be loaded with all 1s. R1 is then
adjusted until V
adjustable V

OUT

, R1 and R

REF

= –V

(4095/4096). In the case of an

REF

FEEDBACK

may be omitted, with V

REF

adjusted to yield the desired full-scale output.

BIPOLAR OPERATION (4-QUADRANT)

Figure 18 details a suggested circuit for bipolar, or offset binary,
operation. Table III shows the digital input-to-analog output
relationship. The circuit uses offset binary coding. Twos comple­ment code can be converted to offset binary by software inver­sion of the MSB or by the addition of an external inverter to the
MSB input.

Resistor R3, R4 and R5 must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient match. Mismatching between R3 and
R4 causes offset and full-scale error.

Calibration is performed by loading the DAC register with
1000 0000 0000 and adjusting R1 until V

= 0 V. R1 and

OUT

R2 may be omitted by adjusting the ratio of R3 to R4 to yield

= 0 V. Full scale can be adjusted by loading the DAC

V

OUT

register with 1111 1111 1111 and adjusting either the amplitude
of V

or the value of R5 until the desired V

REF

is achieved.

OUT

Table III. Bipolar (Offset Binary) Code Table

Digital Input Nominal Analog Output
MSB LSB (V

1 1 1 1 1 1 1 1 1 1 1 1 +V

1 0 0 0 0 0 0 0 0 0 0 1 +V

as Shown in Figure 18)

OUT

2047



REF

REF

2048



2048



1



1 0 0 0 0 0 0 0 0 0 0 0 0

1



0 1 1 1 1 1 1 1 1 1 1 1 –V

0 0 0 0 0 0 0 0 0 0 0 1 –V

0 0 0 0 0 0 0 0 0 0 0 0 –V

NOTES

1

Nominal full scale for the circuits of Figure 18 is given by

FS = V

2

Nominal LSB magnitude for the circuits of Figure 18 is given by

LSB = V

REF

REF

2047



2048



2048

.



1

.



REF

REF

REF

2048

2047



2048

2048



2048







DAISY-CHAINING DAC8143s

Many applications use multiple serial input DACs that use
numerous interconnecting lines for address decoding and data
lines. In addition, they use some type of buffering to reduce
loading on the bus. The DAC8143 is ideal for just such an
application. It not only reduces the number of interconnecting
lines, but also reduces bus loading. The DAC8143 can be daisy­chained with only three lines: one data line, one CLK line and
one load line, see Figure 19.

V

IN

SERIAL

DATA INPUT

R1

100V

R2

50V

FB

I

OUT1

I

OUT2

AGND

6

BUFFERED SERIAL
DATA OUT

C1
10-33pF

1

2

3

COMMON GROUND

A1

1/2 OP200

12

15

7

DGND

V

SRI

8-11

REF

CONTROL

BITS

CONTROL

INPUTS

+5V

14 15

V

DD

DAC8143

CLR

4, 5

13

FROM

SYSTEM

RESET

R

SRO

Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)

–10–

R3

10kV

R4
20kV

1/2 OP200

R5

20kV

A2

V

OUT

REV. C

ADDRESS BUS

WR

DB

X

mP

ADDRESS
DECODER

SRI
SRO

SRI
SRO

SRI
SRO

SRI
SRO

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

STROBE

DAC8143

LOAD

Figure 19. Multiple DAC8143s with Three-Wire Interface

ANALOG/DIGITAL DIVISION

The transfer function for the DAC8143 connect in the multiply­ing mode as shown in Figures 16 and 17 is:

= –VIN

V

O



A

A

A

1

2

+



1

2



3

+

+...

3

2

2

2



A

12



12

2



where AX assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.

The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 20
and is:






V

=

O





–V

IN

A

A

1

1

2

A

2

+

3

+

+ ...

3

2

2

2






A

12



12



2

The above transfer function is the division of an analog voltage

) by a digital word. The amplifier goes to the rails with all

(V

REF

bits “OFF” since division by zero is infinity. With all bits “ON”

the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB,

Bit 12, “ON”.

DIGITAL

INPUTS

413

16

R

V

FB

IN

DAC8143

1

I

OUT1

3212

AGND DGND

2

–
OP-42

3

+

V

SRO

V

REF

14

DD

6

15

6

+5V

BUFFERED DIGITAL
DATA OUT

V

OUT

DAC8143

APPLICATION TIPS

In most applications, linearity depends on the potential of I
I

and AGND (Pins 1, 2 and 3) being exactly equal to each

OUT2,

other. In most applications, the DAC is connected to an exter­nal op amp with its noninverting input tied to ground (see Fig­ures 16 and 17). The amplifier selected should have a low input
bias current and low drift over temperature. The amplifier’s

input offset voltage should be nulled to less than ±200 µV (less

than 10% of 1 LSB).

The operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur­rent compensation resistor should not be used. This resistor can
cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The V

power supply should

DD

have a low noise level with no transients greater than +17 V.

It is recommended that the digital inputs be taken to ground or
V

via a high value (1 MΩ) resistor; this will prevent the accu-

DD

mulation of static charge if the PC card is disconnected from the
system.

Peak supply current flows as the digital input pass through the
transition region (see Figure 4). The supply current decreases as
the input voltage approaches the supply rails (V

or DGND),

DD

i.e., rapidly slewing logic signals that settle very near the supply
rails will minimize supply current.

INTERFACING TO THE MC6800

As shown in Figure 21, the DAC8143 may be interfaced to the
6800 by successively executing memory WRITE instruction
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.

In this example, the most significant bits are found in memory
locations 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB

line.

7

The serial data loading is triggered by STB

which is asserted by

4

a decoded memory WRITE to a memory location, R/W, and
Φ2. A WRITE to another address location transfers data from
input register to DAC register.

A

0

15

0

7

16-BIT ADDRESS BUS

E

1

E

3

DECODER

E

2

8-BIT DATA BUS

SRI

LD

STB

3

DAC8143*

LD

1

STB

2

STB

4

A

0A2

74LS138

ADDRESS

STB

2

SRO

CLR

1

A

MC6800

R/W

φ2

DB

DB

+5V

FROM SYSTEM RESET

*

ANALOG CIRCUITRY OMITTED FOR SIMPLICITY

Figure 21. DAC8143—MC6800 Interface

OUT1,

REV. C

Figure 20. Analog/Digital Divider

–11–

DAC8143

DAC8143 INTERFACE TO THE 8085

The DAC8143’s interface to the 8085 microprocessor is shown
in Figure 22. Note that the microprocessor’s SOD line is used
to present data serially to the DAC.

Data is strobed into the DAC8143 by executing memory write
instructions. The strobe 2 input is generated by decoding an
address location and WR. Data is loaded into the DAC register
with a memory write instruction to another address location.

Serial data supplied to the DAC8143 must be present in the
right-justified format in registers H and L of the microprocessor.

(8)

8085

ALE

WR

SOD

FROM SYSTEM RESET

8212

(8)

AD

0–7

+5V

*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY

ADDRESS BUS (16)

+5V

DATA

SRI
STB

STB
STB

LD

A0–A

E

1

E

3

E

2

LD

3

DAC8143*

1
4

1

15

A0A

74LS138
ADDRESS
DECODER

STB

2

CLR

2

2

SRO

Figure 22. DAC8143—8085 Interface

DAC8143 INTERFACE TO THE 68000

Figure 23 shows the DAC8143 configured to the 68000 micro­processor. Serial data input is similar to that of the 6800 in
Figure 21.

A

68000mP

A

AS

VMA

VPA

UDS

DB

DB

1

23

15

0

ADDRESS

CS

DECODER

1/4 74HC125

FROM SYSTEM RESET

ADDRESS BUS

+

+5V

DATA BUS

STB
LD
STB
STB
SRI

3

1

2
4

STB

LD

1

DAC8143

CLR

2

Figure 23. DAC8143 to 68000 µP Interface

C3114c–2–3/99

PIN 1

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

16-Lead Plastic DIP

0.840 (21.34)

0.745 (18.92)

16

18

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

0.070 (1.77)

0.045 (1.15)

(N-16)

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

0.325 (8.25)

0.300 (7.62)

0.195 ( 4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.0118 (0.30)

0.0040 (0.10)

0.4133 (10.50)

0.3977 (10.00)

16 9

PIN 1

0.050 (1.27)
BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

16-Lead SOIC

(R-16W)

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

81

0.3937 (10.00)

SEATING

0.0125 (0.32)

PLANE

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

88
08

3 458

0.0500 (1.27)

0.0157 (0.40)

PRINTED IN U.S.A.

–12–

REV. C