Analog Devices DAC8043A Datasheet

12-Bit Serial Input

CODE

INL – LSB

0.1

0

–0.1

0 1024 2048 3072 4096

–0.5

0.5

0.4

0.3

0.2

–0.2

–0.3

–0.4

512 1536 2560 3584

TA = +258C, +858C, –408C
V

DD

= +5V

V

REF

= –10V

a

FEATURES
Compact SO-8 and TSSOP Packages
True 12-Bit Accuracy
+5 V Operation @ <10 ␮A
Fast 3-Wire Serial Input
Fast 1 ␮s Settling Time

2.4 MHz 4-Quadrant Multiply BW
Pin-for-Pin Upgrade for DAC8043
Standard and Rotated Pinout

APPLICATIONS
Ideal for PLC Applications in Industrial Control
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration and Filters
Motion Control Systems

GENERAL DESCRIPTION

The DAC8043A is an improved high accuracy 12-bit multiply­ing digital-to-analog converter in space-saving 8-lead packages.
Featuring serial input, double buffering and excellent analog
performance, the DAC8043A is ideal for applications where PC
board space is at a premium. Improved linearity and gain error
performance permit reduced parts count through the elimina­tion of trimming components. Separate input clock and load
DAC control lines allow full user control of data loading and
analog output.

The circuit consists of a 12-bit serial-in/parallel-out shift regis­ter, a 12-bit DAC register, a 12-bit CMOS DAC and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.

Consuming only 10 µA from a single +5 V power supply, the

DAC8043A is the ideal low power, small size, high performance
solution to many application problems.

The DAC8043A is specified over the extended industrial

(–40°C to +85°C) temperature range. DAC8043A is available

in plastic DIP, and the low profile 1.75 mm height SO-8 surface
mount packages. The DAC8043AFRU is available for ultra­compact applications in a thin 1.1 mm TSSOP-8 package.

Multiplying D/A Converter

DAC8043A

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

REF

LD

CLK

SRI

Figure 1. Integral Nonlinearity Error vs. Code

DAC8043A

DAC

12

DAC REG

12

12-BIT SHIFT

REGISTER

R

FB

I

OUT

GND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

DAC8043A–SPECIFICATIONS

(@ V

ELECTRICAL CHARACTERISTICS

= +5 V, V

DD

Parameter Symbol Condition E Grade F Grade Units

STATIC PERFORMANCE

Resolution N 12 12 Bits

Relative Accuracy INL ±0.5 ±1.0 LSB max
Differential Nonlinearity DNL All Grades Monotonic to 12 Bits ±0.5 ±1.0 LSB max

Gain Error

Gain Tempco
Output Leakage Current I

Zero-Scale Error

1

2

3

G

FSE

TCG

LKG

I

ZSE

FS

T

= +25°C, Data = FFF

A

= –40°C, +85°C, Data = FFF

T

A

I

Pin Measured ±5 ±5 ppm/°C max

OUT

Data = 000H, I

= –40°C, +85°C, Data = 000

T

A

Data = 000
T

= –40°C, +85°C, Data = 000

A

H

REFERENCE INPUT

Input Resistance R
Input Capacitance

ANALOG OUTPUT

Output Capacitance

2

2

C

C

REF

REF

OUT

Absolute Tempco < 50 ppm/°C 7/15 7/15 kΩ min/max

Data = 000
Data = FFF

H

H

DIGITAL INPUTS

Digital Input Low V
Digital Input High V
Input Leakage Current I
Input Capacitance

INTERFACE TIMING

2

2, 4

Data Setup t
Data Hold t
Clock Width High t
Clock Width Low t
Load Pulsewidth t
LSB CLK to LD DAC t

AC CHARACTERISTICS

1, 2

Output Current Settling Time t
DAC Glitch Q Data = 000
Feedthrough (V

OUT/VREF

Total Harmonic Distortion THD V
Output Noise Density

)FT V

5

Multiplying Bandwidth BW –3 dB, V

C

e

IL

IH

IL

IL

DS

DH

CH

CL

LD

ASB

S

n

V

= 0 V to +5 V 0.001/±1 0.001/±1 µA typ/max

LOGIC

V

= 0 V 10 10 pF max

LOGIC

To ±0.01% of Full Scale, Ext Op Amp OP42 1 1 µs max

to FFFH to 000H, V

H

= 20 V p-p, Data = 000H, f = 10 kHz 1 1 mV p-p

REF

= 6 V rms, Data = FFFH, f = 1 kHz –85 –85 dB typ

REF

10 Hz to 100 kHz Between RFB and I

OUT/VREF

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current I
Power Dissipation P

DD RANGE

DD

DISS

V

LOGIC

V

LOGIC

= 0 V or V
= 0 V or V

Power Supply Sensitivity PSS ∆VDD = ±5% 0.002 0.002 %/% max

NOTES

1

Using internal feedback resistor RFB, see Figure 19 test circuit with V

2

These parameters are guaranteed by design and not subject to production testing.

3

Calculated from worst case R

4

All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

5

Calculation from e

Specifications subject to change without notice.

= √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.

n

REF

: I

ZSE

(LSB) = (R

REF

× I

× 4096)/V

LKG

= +10 V.

REF

.

REF

= +10 V, –40ⴗC < TA < +85ⴗC, unless otherwise noted.)

REF

H

H

Pin Measured ±5 ±5 nA max

OUT

, I

Pin Measured ±25 ±25 nA max

H

OUT

±1.0 ±2.0 LSB max
±2.0 ±2.0 LSB max

0.03 0.03 LSB max

H

0.15 0.15 LSB max

5 5 pF typ

25 25 pF typ
30 30 pF typ

0.8 0.8 V max

2.4 2.4 V min

10 10 ns min
5 5 ns min
25 25 ns min
25 25 ns min
25 25 ns min
0 0 ns min

= 0 V 20 20 nVs max

REF

, V

= 100 mV rms, Data = FFFH2.4 2.4 MHz typ

REF

OUT

17 17 nV/√Hz max

4.5/5.5 4.5/5.5 V min/max

DD

DD

10 10 µA max
50 50 µW max

–2–

REV. 0

DAC8043A

1

4

5

8

SO-8

DAC8043A

ES/FS

1

4

5

8

TSSOP-8

DAC8043A

FRU

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

I

OUT

GND

LD

R

FB

V

REF

V

DD

CLK
SRI

PDIP-8

DAC8043A

EP/FP

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

I

OUT

GND

LD

R

FB

V

REF

V

DD

CLKSRI

SO-8

DAC8043A1ES
DAC8043A1FS

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

R

FB

Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, V

VI

to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

I

OUT

Package Power Dissipation . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

+ 0.3 V

DD

max – T

J

)/θ

A

JA

8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . 103°C/W

8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . 158°C/W

TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . 240°C/W

Maximum Junction Temperature (T

max) . . . . . . . . +150°C

J

Operating Temperature Range . . . . . . . . . . – 40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

INL Package Package

Model (LSB) Temp Description Option

DAC8043AEP ±0.5 –40/+85°C 8-Lead P-DIP N-8
DAC8043AES ±0.5 –40/+85°C 8-Lead SOIC SO-8
DAC8043A1ES ±0.5 –40/+85°C 8-Lead SOIC SO-8
DAC8043AFP ±1.0 –40/+85°C 8-Lead P-DIP N-8
DAC8043AFS ±1.0 –40/+85°C 8-Lead SOIC SO-8
DAC8043A1FS ±1.0 –40/+85°C 8-Lead SOIC* SO-8
DAC8043AFRU ±1.0 –40/+85°C TSSOP-8 RU-8

NOTES
The DAC8043A contains 346 transistors. The die size measures 70.3 mil ×

57.1 mil, 4014 sq mil.
*The DAC8043A1ES and DAC8043A1FS have a rotated pinout.

TSSOP-8 Package Branding:

Line 1: yww (data code: year, work week).
Line 2: 8043A.

PIN FUNCTION DESCRIPTIONS

#(*) Name Function

1(7) V

DAC Reference Input Pin. Establishes DAC full-

REF

scale voltage. Constant input resistance versus
code.

2 (8) R

Internal Matching Feedback Resistor. Connect

FB

to external op amp output.

3 (1) I

DAC Current Output, full-scale output 1 LSB

OUT

less than reference input voltage –V

REF

.

4 (2) GND Analog and Digital Ground.
5 (3) LD Load Strobe, Level-Sensitive Digital Input.

Transfers shift-register data to DAC register
while active low. See truth table for operation.

6 (4) SRI 12-Bit Serial Register Input, data loads directly

into the shift register MSB first. Extra leading
bits are ignored.

7 (5) CLK Clock Input, positive-edge clocks data into shift

register.

8 (6) V

Positive Power Supply Input. Specified range of

DD

operation +5 V ± 10%.

*Note Pin numbers in parenthesis represent the rotated pinout of the

DAC8043A1ES and DAC8043A1FS models.

DAC8043AE/F PIN CONFIGURATIONS

DAC8043A1E AND DAC8043A1F PIN CONFIGURATION

(Rotated Pinout)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–