Analog Devices AD7843 b Datasheet

V

Touch Screen Digitizer

FEATURES

4-wire touch screen interface
Specified throughput rate of 125 kSPS
Low power consumption:

1.37 mW max at 125 kSPS with V

Single supply, V

of 2.2 V to 5.25 V

CC

Ratiometric conversion
High speed serial interface
Programmable 8-bit or 12-bit resolution
2 auxiliary analog inputs
Shutdown mode: 1 µA max
16-lead QSOP and TSSOP packages

APPLICATIONS

Personal digital assistants
Smart hand-held devices
Touch screen monitors
Point-of-sales terminals
Pagers

GENERAL DESCRIPTION

The AD7843 is a 12-bit successive approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to

5.25 V power supply and features throughput rates greater than
125 kSPS.

The external reference applied to the AD7843 can be varied
from 1 V to +V

The device includes a shutdown mode that reduces the

V

REF.

current consumption to less than 1 µA.

The AD7843 features on-board switches. This, coupled with low
power and high speed operation, make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens, and other portable equipment. The part
is available in a 16-lead 0.15" quarter size outline package
(QSOP) and a 16-lead thin shrink small outline package
(TSSOP).

, while the analog input range is from 0 V to

CC

= 3.6 V

CC

AD7843

FUNCTIONAL BLOCK DIAGRAM

+V

CC

X+
X–

Y+
Y–

IN3
IN4

REF

DIN CS DOUT DCLK BUSY

AD7843

4-TO-1

I/P

MUX

REDISTRIBUTION

CONTROL LOGIC

T/H

CHARGE

DAC

SAR + ADC

SPORT

Figure 1.

PRODUCT HIGHLIGHTS

1. Ratiometric conversion mode available eliminating errors

due to on-board switch resistances.

2. Maximum current consumption of 380 µA while operating

at 125 kSPS.

3. Power-down options available.

4. Analog input range from 0 V to V

5. Versatile serial I/O port.

REF

.

PENIRQ

PEN

INTERRUPT

COMP

GND

+V

CC

02144-B-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7843

TABLE OF CONTENTS

Specifications..................................................................................... 3

Analog Input............................................................................... 12

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Terminology ...................................................................................... 7

Typical Performance Characteristics ............................................. 8

Circuit Information........................................................................ 11

ADC Transfer Function............................................................. 11

Typical Connection Diagram ................................................... 11

REVISION HISTORY

3/04—Data Sheet Changed from Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings ....................................... 5

Addition to the PD0 and PD1 Section......................................... 14

Additions to Ordering Guide........................................................ 20

Control Register ......................................................................... 14

Power vs. Throughput Rate....................................................... 15

Serial Interface............................................................................ 16

Detailed Serial Interface Timing .............................................. 17

Pen Interrupt Request................................................................ 19

Grounding and Layout .............................................................. 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

3/03—Data Sheet Changed from Rev. 0 to Rev. A

Updated Outline Dimensions....................................................... 16

Rev. B | Page 2 of 20

AD7843

SPECIFICATIONS

VCC = 2.7 V to 3.6 V, V

Table 1.

Parameter AD7843A1 Unit Test Conditions/Comments

DC ACCURACY

Resolution 12 Bits
No Missing Codes 11 Bits min
Integral Nonlinearity2 ±2 LSB max
Offset Error2 ±6 LSB max VCC = 2.7 V
Offset Error Match3 1 LSB max

0.1 LSB typ
Gain Error2 ±4 LSB max
Gain Error Match3 1 LSB max

0.1 LSB typ
Power Supply Rejection 70 dB typ

SWITCH DRIVERS

On-Resistance2

Y+, X+ 5 Ω typ
Y−, X− 6 Ω typ

ANALOG INPUT

Input Voltage Ranges 0 to V
DC Leakage Current ±0.1 µA typ
Input Capacitance 37 pF typ

REFERENCE INPUT

V

Input Voltage Range 1.0/+VCC V min/max

REF

DC Leakage Current ±1 µA max
V

Input Impedance 5 GΩ typ

REF

V

Input Current3 20 µA max 8 µA typ

REF

1 µA typ f
1 µA max

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, IIN ±1 µA max Typically 10 nA, VIN = 0 V or +VCC
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH VCC − 0.2 V min I
Output Low Voltage, VOL 0.4 V max I
PENIRQ Output Low Voltage, VOL
Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance4 10 pF max
Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 12 DCLK Cycles max
Track-and-Hold Acquisition Time 3 DCLK Cycles min
Throughput Rate 125 kSPS max

Footnotes on next page.

= 2.5 V, f

REF

2.4 V min

INH

0.4 V max

INL

4

10 pF max

IN

= 2 MHz, TA = −40°C to +85°C, unless otherwise noted.

SCLK

V

REF

0.4 V max I

= GND or +VCC

CS

= 12.5 kHz

SAMPLE

= +VCC; 0.001 µA typ

CS

= 250 µA; VCC = 2.2 V to 5.25 V

SOURCE

= 250 µA

SINK

= 250 µA; 100 kW pull-up

SINK

Rev. B | Page 3 of 20

AD7843

Parameter AD7843A1 Unit Test Conditions/Comments

POWER REQUIREMENTS

VCC (Specified Performance) 2.7/3.6 V min/max Functional from 2.2 V to 5.25 V

5

I

Digital I/Ps = 0 V or VCC

CC

Normal Mode (f
Normal Mode (f
Normal Mode (Static) 150 µA typ VCC = 3.6 V
Shutdown Mode (Static) 1 µA max

Power Dissipation5

Normal Mode (f
Shutdown 3.6 µW max VCC = 3.6 V

1

Temperature range as follows: A Version: −40°C to +85°C.

2

See the Terminology section.

3

Guaranteed by design.

4

Sample tested @ 25°C to ensure compliance.

5

See the Power vs. Throughput Rate section.

TIMING SPECIFICATIONS

TA = T

Table 2. Timing Specifications

Parameter Limit at T

f

DCLK

2 MHz max
t

ACQ

t1 10 ns min
t2 60 ns max
t3 60 ns max
t4 200 ns min DCLK high pulse width

t5 200 ns min DCLK low pulse width
t6 60 ns max DCLK falling edge to BUSY rising edge
t7 10 ns min Data setup time prior to DCLK rising edge
t8 10 ns min Data valid to DCLK hold time

3

t

9

t10 0 ns min
t11 200 ns max
t

12

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.6 V.

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.

4

t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

to T

MIN

MAX

2

10 kHz min

1.5 µs min Acquisition time

200 ns max Data access time after DCLK falling edge

4

200 ns max

= 125 kSPS) 380 µA max VCC = 3.6 V, 240 µA typ

SAMPLE

= 12.5 kSPS) 170 µA typ VCC = 2.7 V, f

SAMPLE

= 125 kSPS) 1.368 mW max VCC = 3.6 V

SAMPLE

, unless other wise noted; VCC = 2.7 V to 3.6 V, V

1

, T

MIN

Unit Description

MAX

= 2.5 V.

REF

CS

falling edge to First DCLK rising edge

CS

falling edge to BUSY three-state disabled

CS

falling edge to DOUT three-state disabled

CS

rising edge to DCLK ignored

CS

rising edge to BUSY high impedance

CS

rising edge to DOUT high impedance

, quoted in the timing characteristics is the true bus relinquish

12

= 200 kHz

DCLK

TO

OUTPUT

PIN

50pF

200µA

C

L

200µA

I

OL

1.6V

I

OH

02144-B-002

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. B | Page 4 of 20

AD7843

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

+VCC to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Output Voltage to GND −0.3 V to VCC + 0.3 V
V

to GND −0.3 V to VCC + 0.3 V

REF

Input Current to Any Pin Except Supplies1

Operating Temperature Range

Commercial −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
QSOP, TSSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 149.97°C/W (QSOP)

150.4°C/W (TSSOP)

θJC Thermal Impedance 38.8°C/W (QSOP)

27.6°C/W (TSSOP)
IR Reflow Soldering

Peak Temperture

Time-to-Peak Temperture

Ramp-Down Rate
Pb-free parts only

Peak Temperture 250°C

Time-to-Peak Temperture

Ramp-Up Rate

Ramp-Down Rate

±10 mA

220°C (±5°C)
10 sec to 30 sec
6°C/sec max

20 sec to 40 sec
3°C/sec max
6°C/sec max

________________

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 5 of 20

AD7843

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

+V

CC

2

X+

3

Y+

AD7843

4

X–

TOP VIEW

5

Y–

(Not to Scale)

6

GND

7

IN3

8

IN4

Figure 3. Pin Configuration QSOP/TSSOP

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1, 10 +VCC

Power Supply Input. The +V

range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should be connected

CC

directly together.
2 X+ X+ Position Input. ADC Input Channel 1.
3 Y+ Y+ Position Input. ADC Input Channel 2.
4 X− X− Position Input.
5 Y− Y− Position Input.
6 GND

Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and any external

reference signal should be referred to this GND voltage.
7 IN3 Auxiliary Input 1. ADC Input Channel 3.
8 IN4 Auxiliary Input 2. ADC Input Channel 4.
9 V

REF

Reference Input for the AD7843. An external reference must be applied to this input. The voltage range for the

external reference is 1.0 V to +VCC. For specified performance, it is 2.5 V.
11

PENIRQ

12 DOUT

Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up register externally).

Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a serial data stream.

The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS
13 BUSY
14 DIN

BUSY Output. Logic Output. This output is high impedance when CS

Data In. Logic input. Data to be written to the AD7843 control register is provided on this input and is clocked into

the register on the rising edge of DCLK (see the Control Register section).
15

Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating conversions on the

CS

AD7843 and also enables the serial input/output register.
16 DCLK

External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part. This clock input

is also used as the clock source for the AD7843 conversion process.

16

DCLK

15

CS

14

DIN

13

BUSY

12

DOUT

11

PENIRQ

10

+V

CC

9

V

REF

02144-B-003

is high.

is high.

Rev. B | Page 6 of 20