ANALOG DEVICES AD7843 Service Manual

查询AD7843ARQ供应商

a

FEATURES
4-Wire Touch Screen Interface
Specified Throughput Rate of 125 kSPS
Low Power Consumption:

1.37 mW Max at 125 kSPS with V
Single Supply, V
Ratiometric Conversion
High-Speed Serial Interface
Programmable 8- or 12-Bit Resolution
Two Auxiliary Analog Inputs
Shutdown Mode: 1
16-Lead QSOP and TSSOP Packages

APPLICATIONS
Personal Digital Assistants
Smart Hand-Held Devices
Touch Screen Monitors
Point-of-Sales Terminals
Pagers

of 2.2 V to 5.25 V

CC

␮A max

= 3.6 V

CC

Touch Screen Digitizer

AD7843

FUNCTIONAL BLOCK DIAGRAM

+V

CC

X+

X–

Y+

Y–

IN3

IN4

V

REF

AD7843

4-TO-1

I/P

MUX

REDISTRIBUTION

CONTROL LOGIC

T/H

CHARGE

DAC

SAR + ADC

PENIRQ

PEN

INTERRUPT

COMP

GND

+V

CC

GENERAL DESCRIPTION

The AD7843 is a 12-bit successive-approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to

5.25 V power supply and features throughput rates greater than
125 kSPS.

The external reference applied to the AD7843 can be varied
from 1 V to +V
V

. The device includes a shutdown mode that reduces the

REF

, while the analog input range is from 0 V to

CC

current consumption to less than 1 µA.

The AD7843 features on-board switches. This coupled with low
power and high-speed operation make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens and other portable equipment. The part
is available in a 16-lead 0.15" Quarter Size Outline (QSOP) pack­age and a 16-lead Thin Shrink Small Outline (TSSOP) package.

SPORT

CS

DOUTDIN

DCLK

BUSY

PRODUCT HIGHLIGHTS

1. Ratiometric conversion mode available eliminating errors
due to on-board switch resistances.

2. Maximum current consumption of 380 µA while operating at
125 kSPS.

3. Power-down options available.

4. Analog input range from 0 V to V

REF

.

5. Versatile serial I/O port.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(VCC = 2.7 V to 3.6 V, V

AD7843–SPECIFICATIONS

–40ⴗC to +85ⴗC, unless otherwise noted.)

Parameter AD7843A

1

Unit Test Conditions/Comments

= 2.5 V, f

REF

= 2 MHz unless otherwise noted; TA =

SCLK

DC ACCURACY

Resolution 12 Bits
No Missing Codes 11 Bits min
Integral Nonlinearity
Offset Error

2

Offset Error Match

Gain Error

2

Gain Error Match

2

3

± 2LSB max
± 6LSB maxV

= 2.7 V

CC

1LSB max

0.1 LSB typ

3

± 4LSB max
1LSB max

0.1 LSB typ

Power Supply Rejection 70 dB typ

SWITCH DRIVERS

On-Resistance

2

Y+, X+ 5 Ω typ
Y–, X– 6 Ω typ

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

Volts
DC Leakage Current ± 0.1 µA typ
Input Capacitance 37 pF typ

REFERENCE INPUT

V

Input Voltage Range 1.0/+V

REF

CC

V min/max
DC Leakage Current ±1 µA max
V

Input Impedance 5 GΩ typ CS = GND or +V

REF

V

Input Current

REF

3

20 µA max 8 µA typ
1 µA typ f

SAMPLE

= 12.5 kHz

CC

1 µA max CS = +VCC; 0.001 µA typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

2.4 V min

0.4 V max
± 1 µA max Typically 10 nA, V
10 pF max

IN

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
PENIRQ Output Low Voltage, V
Floating-State Leakage Current ± 10 µA max
Floating-State Output Capacitance

OH

OL

OL

4

– 0.2 V min I

CC

0.4 V max I

0.4 V max I

10 pF max

= 250 µA; VCC = 2.2 V to 5.25 V

SOURCE

= 250 µA

SINK

= 250 µA; 100 kΩ Pull-Up

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 12 DCLK Cycles max
Track/Hold Acquisition Time 3 DCLK Cycles min
Throughput Rate 125 kSPS max

POWER REQUIREMENTS

(Specified Performance) 2.7/3.6 V min/max Functional from 2.2 V to 5.25 V

V

CC

5

I

CC

Normal Mode (f
Normal Mode (f

= 125 kSPS) 380 µA max VCC = 3.6 V, 240 µA typ

SAMPLE

= 12.5 kSPS) 170 µA typ VCC = 2.7 V, f

SAMPLE

Normal Mode (Static) 150 µA typ V
Shutdown Mode (Static) 1 µA max

Power Dissipation

Normal Mode (f

5

= 125 kSPS) 1.368 mW max VCC = 3.6 V

SAMPLE

Digital I/Ps = 0 V or V

= 3.6 V

CC

DCLK

Shutdown 3.6 µW max VCC = 3.6 V

NOTES

1

Temperature range as follows: A Version: –40°C to +85°C.

2

See Terminology.

3

Guaranteed by design.

4

Sample tested @ 25°C to ensure compliance.

5

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 0 V or +V

CC

= 2 00 kHz

CC

–2–

REV. 0

AD7843

MIN

1

, T

(TA = T

MAX

MIN

to T

, unless otherwise noted; VCC = 2.7 V to 3.6 V, V

MAX

Unit Description

= 2.5 V)

REF

TIMING SPECIFICATIONS

Parameter Limit at T

f

DCLK

2

10 kHz min
2 MHz max

t

ACQ

t

1

t

2

3

t

3

t

4

t

5

t

6

t

7

t

8

3

t

9

t

10

t

11

4

t

12

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V.

4

t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

Specifications subject to change without notice.

1.5 µs min Acquisition Time
10 ns min CS Falling Edge to First DCLK Rising Edge
60 ns max CS Falling Edge to BUSY Three-State Disabled
60 ns max CS Falling Edge to DOUT Three-State Disabled
200 ns min DCLK High Pulsewidth
200 ns min DCLK Low Pulsewidth
60 ns max DCLK Falling Edge to BUSY Rising Edge
10 ns min Data Setup Time Prior to DCLK Rising Edge
10 ns min Data Valid to DCLK Hold Time
200 ns max Data Access Time after DCLK Falling Edge
0 ns min CS Rising Edge to DCLK Ignored
200 ns max CS Rising Edge to BUSY High Impedance
200 ns max CS Rising Edge to DOUT High Impedance

I

OL

1.6V

I

OH

TO

OUTPUT

PIN

50pF

200␮A

C

L

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. 0

–3–

AD7843

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

+VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . –0.3 V to V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

REF

Input Current to Any Pin Except Supplies
Operating Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150° C

1

2

. . . . . . . ±10 mA

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

CC

QSOP, TSSOP Package, Power Dissipation . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . 149.97°C/W (QSOP)

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP)

θ

Thermal Impedance . . . . . . . . . . . . . 38.8°C/W (QSOP)

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Rating may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Temperature Linearity Package Package Branding

Model Range Error (LSB)1Option Description Information

AD7843ARQ –40°C to +85°C ± 2 RQ-16
AD7843ARQ-REEL –40°C to +85°C ± 2 RQ-16
AD7843ARQ-REEL7 –40°C to +85°C ± 2 RQ-16

2

2

2

QSOP AD7843ARQ
QSOP AD7843ARQ

QSOP AD7843ARQ
AD7843ARU –40°C to +85°C ±2 RU-16 TSSOP AD7843ARU
AD7843ARU-REEL –40°C to +85°C ±2 RU-16 TSSOP AD7843ARU
AD7843ARU-REEL7 –40°C to +85°C ±2 RU-16 TSSOP AD7843ARU
EVAL-AD7843CB
EVAL-CONTROL BRD2

NOTES

1

Linearity error here refers to integral linearity error.

2

RQ = 0.15" Quarter Size Outline Package.

3

This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.

4

This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the

CB designators.

3

4

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7843 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION QSOP/TSSOP

+V

GND

CC

X+

Y+

X–

Y–

IN3

IN4

1

2

3

AD7843

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

DCLK

CS

DIN

BUSY

DOUT

PENIRQ

+V

CC

V

REF

–4–

REV. 0

AD7843

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1, 10 +V

CC

2 X+ X+ Position Input. ADC Input Channel 1.
3 Y+ Y+ Position Input. ADC Input Channel 2.
4 X– X– Position Input.
5 Y– Y– Position Input.
6 GND Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and

7 IN3 Auxiliary Input 1. ADC Input Channel 3.
8 IN4 Auxiliary Input 2. ADC Input Channel 4.
9V

REF

11 PENIRQ Pen Interrupt. CMOS Logic open drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally).
12 DOUT Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a

13 BUSY BUSY Output. Logic Output. This output is high impedance when CS is high.
14 DIN Data In. Logic Input. Data to be written to the AD7843’s Control Register is provided on this input

15 CS Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating con-

16 DCLK External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part.

Power Supply Input. The +VCC range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should
be connected directly together.

any external reference signal should be referred to this GND voltage.

Reference Input for the AD7843. An external reference must be applied to this input. The voltage
range for the external reference is 1.0 V to +V

. For specified performance it is 2.5 V.

CC

serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is
high impedance when CS is high.

and is clocked into the register on the rising edge of DCLK (see Control Register section).

versions on the AD7843 and also enables the serial input/output register.

This clock input is also used as the clock source for the AD7843’s conversion process.

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., V

– 1 LSB) after the offset

REF

error has been adjusted out.

Track/Hold Acquisition Time

The track/hold amplifier enters the acquisition phase on the fifth
falling edge of DCLK after the START bit has been detected.
Three DCLK cycles are allowed for the Track/Hold acquisition
time and the input signal will be fully acquired to the 12-bit
level within this time even with the maximum specified DCLK
frequency. See Analog Input section for more details.

On-Resistance

This is a measure of the ohmic resistance between the drain and
source of the switch drivers.

REV. 0

–5–