Analog Devices AD7829, AD7825, AD7822 Datasheet

3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel

CONVST

DB0

DB7

8-BIT
HALF

FLASH

ADC

PARALLEL

PORT

VREF

IN

/REF

OUT

EOC

RDCS

AGND

V

MID

A0*

A1* A2*

V

IN1

COMP

PD*

2.5V
REF

V

DD

CONTROL

LOGIC

DGND

INPUT

MUX

V

IN2*

V

IN3*

V

IN4*

V

IN5*

V

IN6*

V

IN7*

V

IN8*

T/H

*A0, A1
*A2
*PD
*V

IN2

TO V

IN4

*V

IN4

TO V

IN8

AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829

BUF

a

FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels

Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to

10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range

3 V ⴞ 10% and 5 V ⴞ 10%
Input Ranges

0 V to 2 V p-p, V

0 V to 2.5 V p-p, V
Flexible Parallel Interface with EOC Pulse to Allow

Stand-Alone Operation

APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling

Applications

= 3 V ⴞ 10%

DD

= 5 V ⴞ 10%

DD

Sampling ADCs

AD7822/AD7825/AD7829

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5 V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can

The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small
outline IC (SOIC) and a 20-/24-lead thin shrink small outline
package (TSSOP). The AD7829 is available in a 28-lead 0.6"
wide, plastic dual-in-line package (DIP), a 28-lead small outline
IC (SOIC) and in a 28-lead thin shrink small outline package
(TSSOP).

operate from a single 3 V ± 10% and 5 V ± 10% supply.

The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)

The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a stand­alone manner. (See Parallel Interface section of the data sheet.)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Fast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420 ns. Faster conversion times maximize the DSP pro­cessing time in a real time system.

2. Analog Input Span Adjustment
The V

pin allows the user to offset the input span. This

MID

feature can reduce the requirements of single supply op amps
and take into account any system offsets.

3. FPBW (Full Power Bandwidth) of Track and Hold
The track-and-hold amplifier has an excellent high frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a fre­quency of 10 MHz. This makes the parts ideally suited to
subsampling applications.

4. Channel Selection
Channel selection is made without the necessity of writing to
the part.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD7822/AD7825/AD7829–SPECIFICATIONS

V

= 2.5 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)

REF IN/OUT

(VDD = 3 V ⴞ 10%, VDD = 5 V ⴞ 10%, GND = 0 V,

Parameter Version B Unit Test Condition/Comment

DYNAMIC PERFORMANCE f

Signal to (Noise + Distortion) Ratio
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion

1

1

1

48 dB min

1

–55 dB max
–55 dB max

= 30 kHz. f

IN

SAMPLE

= 2 MHz

fa = 27.3 kHz, fb = 28.3 kHz
2nd Order Terms –65 dB typ
3rd Order Terms –65 dB typ

Channel-to-Channel Isolation

1

–70 dB typ fIN = 20 kHz

DC ACCURACY

Resolution 8 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 8 Bits

Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Gain Error
Gain Error Match
Offset Error
Offset Error Match

ANALOG INPUTS

V

DD

V

1

1

1

1

2

= 5 V ± 10% Input Voltage Span = 2.5 V

to V

IN1

Input Voltage V

IN8

1

1

±0.75 LSB max
±0.75 LSB max
±2LSB max
±0.1 LSB typ
±1LSB max
±0.1 LSB typ

See Analog Input Section

DD

V max

0V min

Input Voltage VDD – 1.25 V max Default V

V

MID

= 1.25 V

MID

1.25 V min

= 3 V ± 10% Input Voltage Span = 2 V

V

DD

to V

V

IN1

Input Voltage V

IN8

DD

V max

0V min

Input Voltage VDD – 1 V max Default V

V

MID

MID

= 1 V

1V min

Input Leakage Current ±1 µA max

V

IN

Input Capacitance 15 pF max

V

IN

V

Input Impedance 6 kΩ typ

MID

REFERENCE INPUT

V

REF IN/OUT

Input Voltage Range 2.55 V max 2.5 V + 2%

2.45 V min 2.5 V – 2%

Input Current 1 µA typ

100 µA max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±50 mV max
Temperature Coefficient 50 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

INH

2.4 V min V

0.8 V max V
2V minV

0.4 V max V

±1 µA max Typically 10 nA, V

10 pF max

= 5 V ± 10%

DD

= 5 V ± 10%

DD

= 3 V ± 10%

DD

= 3 V ± 10%

DD

= 0 V to V

IN

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, V

OL

OH

4V minV

2.4 V min V

0.4 V max V

0.2 V max V

I

= 200 µA

SOURCE

= 5 V ± 10%

DD

= 3 V ± 10%

DD

I

= 200 µA

SINK

= 5 V ± 10%

DD

= 3 V ± 10%

DD

High Impedance Leakage Current ±1 µA max

High Impedance Capacitance 10 pF max

DD

–2– REV. A

AD7822/AD7825/AD7829

Parameter Version B Unit Test Condition/Comment

CONVERSION RATE

Track/Hold Acquisition Time 200 ns max See Functional Description Section
Conversion Time 420 ns max

POWER SUPPLY REJECTION

V

± 10% ±1 LSB max

DD

POWER REQUIREMENTS

V

DD

V

DD

I

DD

Normal Operation 12 mA max 8 mA Typically

Power-Down 5 µA max Logic Inputs = 0 V or V

Power Dissipation V

Normal Operation 36 mW max Typically 24 mW
Power-Down

200 kSPS 9.58 mW max

1 MSPS 47.88 mW max

NOTES

1

See Terminology section of this data sheet.

2

Refer to the Analog Input section for an explanation of the Analog Input(s).

Specifications subject to change without notice.

4.5 V min 5 V ± 10%. For Specified Performance

5.5 V max

2.7 V min 3 V ± 10%. For Specified Performance

3.3 V max

0.2 µA typ

DD

= 3 V

DD

I

OL

+2.1V

I

OH

TO

OUTPUT

PIN

50pF

200mA

C

L

200mA

Figure 1. Load Circuit for Access Time and Bus
Relinquish Time

ORDERING GUIDE

Linearity Package Package

Model Error Description Option

AD7822BN ±0.75 LSB Plastic DIP N-20
AD7822BR ±0.75 LSB Small Outline IC R-20
AD7822BRU ±0.75 LSB Thin Shrink Small RU-20

Outline (TSSOP)

AD7825BN ±0.75 LSB Plastic DIP N-24
AD7825BR ±0.75 LSB Small Outline IC R-24
AD7825BRU ±0.75 LSB Thin Shrink Small RU-24

Outline (TSSOP)

AD7829BN ±0.75 LSB Plastic DIP N-28
AD7829BR ±0.75 LSB Small Outline IC R-28
AD7829BRU ±0.75 LSB Thin Shrink Small RU-28

Outline (TSSOP)

REV. A

–3–

AD7822/AD7825/AD7829

WARNING!

ESD SENSITIVE DEVICE

1, 2

TIMING CHARACTERISTICS

(V

Parameter 5 V ⴞ 10% 3 V ⴞ 10% Unit Conditions/Comments

t

1

t

2

t

3

t

4

420 420 ns max Conversion Time.
20 20 ns min Minimum CONVST Pulsewidth.
30 30 ns min Minimum time between the rising edge of RD and next falling edge of convert start.
110 110 ns max EOC Pulsewidth.
70 70 ns min

t

5

t

6

t

7

t

8

3

t

9

4

t

10

10 10 ns max RD rising edge to EOC pulse high.
0 0 ns min CS to RD setup time.
0 0 ns min CS to RD hold time.
30 30 ns min Minimum RD Pulsewidth.
10 20 ns max Data access time after RD low.
5 5 ns min Bus relinquish time after RD high.
20 20 ns max

t

11

t

12

t

13

t

POWER UP

t

POWER UP

NOTES

1

Sample tested to ensure compliance.

2

See Figures 20, 21 and 22.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8␣ V or 2.4␣ V with V
put to cross 0.4␣ V or 2.0␣ V with V

4

Derived from the measured time taken by the data outputs to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

10 10 ns min Address setup time before falling edge of RD.
15 15 ns min Address hold time after falling edge of RD.
200 200 ns min Minimum time between new channel selection and convert start.
25 25 µs typ Power-up time from rising edge of CONVST using on-chip reference.
11µs max Power-up time from rising edge of CONVST using external 2.5 V reference.

= 3 V ± 10%.

DD

= 2.5 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted)

REF IN/OUT

= 5 V ± 10%, and time required for an out-

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

V

DD

Analog Input Voltage to AGND

to V

V

IN1

Reference Input Voltage to AGND . . . –0.3 V to V

Input Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3␣ V

V

MID

Digital Input Voltage to DGND . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

IN8

DD

DD

DD

+ 0.3␣ V

+ 0.3 V
+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . . 260°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, perma­nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. A

AD7822/AD7825/AD7829

14

13

12

11

17
16
15

20
19
18

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21

AD7829

DB2

DB6

DB5

DB4

DB3
DB1
DB0

CONVST

V

DD

AGND

DB7

CS

RD

DGND

EOC

A2
A1

V

IN1

V

MID

V

REF

A0

V

IN8

V

IN7

V

IN6

V

IN2

V

IN5

V

IN4

V

IN3

PIN FUNCTION DESCRIPTIONS

Mnemonic Description

V

to V

IN1

IN8

V

DD

AGND Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
DGND Digital Ground. Ground reference for digital circuitry.

CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of

EOC Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used

CS Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.

PD Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low

RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and

A0–A2 Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the

DB0–DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when

V

REF IN/OUT

Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup­ply voltage (V

). This span may be centered anywhere in the range AGND to VDD using the V

DD

default input range (V

unconnected) is AGND to 2 V (V

MID

= 3 V ± 10%) or AGND to 2.5 V (V

DD

Pin. The

MID

= 5 V

DD

± 10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V ± 10% and 5 V ± 10%.

this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Mode section of
the data sheet.)

to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter­face section of this data sheet.)

This is necessary if the ADC is sharing a common data bus with another device.

places the AD7822 and AD7825 in Power-Down mode. The ADCs will power-up when PD is brought logic
high again.

drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic
low to enable the data bus.

RD signal goes low.

both RD and CS go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this

pin. The on-chip reference is also available at this pin.

1

DB2

2

DB1

3

DB0

CONVST

4
5

CS

AD7822

TOP VIEW

6

RD

(Not to Scale)

DGND

7
8

EOC

9

PD

10

NC V

NC = NO CONNECT

20
19
18
17
16
15
14
13
12
11

DB3
DB4
DB5
DB6
DB7
AGND
V

DD

V

REF

V

MID
IN1

PIN CONFIGURATIONS

DIP/SOIC/TSSOP

1

DB2
DB1
DB0

CONVST

DGND

EOC

V

CS

RD

A1
A0

PD

IN4

2
3
4
5

AD7825

6

TOP VIEW

(Not to Scale)

7

8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

DB3
DB4
DB5
DB6
DB7
AGND
V

DD

V

REF

V

MID

V

IN1

V

IN2

V

IN3

–5–REV. A

AD7822/AD7825/AD7829

TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan­tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for an 8-bit converter, this is 50␣ dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7822/AD7825/AD7829
it is defined as:

2

2

2

2

2

+V

5

6

THD (dB) = 20 log

+V

+V

V

2

+V

3

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

The AD7822/AD7825/AD7829 are tested using the CCIF stan­dard where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodula­tion distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 20 kHz
sine wave signal to one input channel and determining how
much that signal is attenuated in each of the other channels.
The figure given is the worst case across all four or eight chan­nels of the AD7825 and AD7829 respectively.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.

Offset Error

The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., V

Offset Error Match

MID

.

The difference in offset error between any two channels.

Zero-Scale Error

The deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., V

5 V ± 10%), or V

Full-Scale Error

– 1.0 V + 1 LSB (V

MID

– 1.25 V + 1 LSB (VDD =

MID

= 3 V ± 10%).

DD

The deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., V

5 V ± 10%), or V

Gain Error

+ 1.0 V – 1 LSB (V

MID

+ 1.25 V – 1 LSB (VDD =

MID

= 3 V ± 10%).

DD

The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, i.e., V

– 1 LSB, after the off-

REF

set error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Track/Hold Acquisition Time

The time required for the output of the track/hold amplifier to

reach its final value, within ±1/2 LSB, after the point at which

the track/hold returns to track mode. This happens approxi­mately 120 ns after the falling edge of CONVST.

It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected V

input of the AD7822/

IN

AD7825/AD7829. It means that the user must wait for the dura­tion of the track/hold acquisition time after a channel change/step
input change to V

before starting another conversion, to

IN

ensure that the part operates to specification.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.

CIRCUIT DESCRIPTION

The AD7822, AD7825, and AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit
flash ADC contains a sampling capacitor followed by fifteen
comparators that compare the unknown input to a reference
ladder to achieve a 4-bit result. This first flash, i.e., coarse con­version, provides the 4 MSBs. For a full 8-bit reading to be
realized, a second flash, i.e., a fine conversion, must be per­formed to provide the 4 LSBs. The 8-bit word is then placed on
the data output bus.

–6– REV. A