Analog Devices AD7303BRM, AD7303BR, AD7303BN Datasheet

+2.7 V to +5.5 V, Serial Input, Dual

I DAC A

POWER ON

RESET

DIN

SYNC

SCLK

REF

V

DD

AD7303

V

OUT

A

V

OUT

B

GND

I/V

INPUT

REGISTER

MUX

DAC

REGISTER

I/V

INPUT

REGISTER

DAC

REGISTER

÷2

16-BIT SHIFT REGISTER

DATA (8)

CONTROL (8)

I DAC B

a

FEATURES
Two 8-Bit DACs in One Package
8-Pin DIP/SOIC and microSOIC Packages
+2.7 V to +5.5 V Operation
Internal & External Reference Capability
Individual DAC Power-Down Function
Three-Wire Serial Interface

QSPI™, SPI™ and Microwire™ Compatible

On-Chip Output Buffer

Rail-to-Rail Operation
On-Chip Control Register
Low Power Operation: 2.3 mA @ 3.3 V
Full Power-Down to 1 mA max, typically 80 nA

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

Voltage Output 8-Bit DAC

AD7303

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7303 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision out­put buffers allow the DAC outputs to swing rail to rail. This de­vice uses a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz, and is compatible with QSPI, SPI, microwire
and digital signal processor interface standards. The serial input
register is sixteen bits wide; 8 bits act as data bits for the DACs,
and the remaining eight bits make up a control register.

The on-chip control register is used to address the relevant
DAC, to power down the complete device or an individual
DAC, to select internal or external reference and to provide a
synchronous loading facility for simultaneous update of the
DAC outputs with a software LDAC function.

The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump­tion is 7.5 mW max at 3 V, reducing to less than 3 µW in full
power-down mode.

The AD7303 is available in an 8-pin plastic dual in-line pack­age, 8-lead SOIC and microSOIC packages.

QSPI and SPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.

PRODUCT HIGHLIGHTS

1. Low power, single supply operation. This part operates from
a single +2.7 V to +5.5 V supply and consumes typically
15 mW at 5.5 V, making it ideal for battery powered
applications.

2. The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2 µs.

3. Internal or external reference capability.

4. High speed serial interface with clock rates up to 30 MHz.

5. Individual power-down of each DAC provided. When com­pletely powered down, the DAC consumes typically 80 nA.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Fax: [phone] © Analog Devices, Inc., 1997

(VDD = +2.7 V to +5.5 V, Internal Reference; RL = 10 kV to VDD and GND; CL = 100 pF

AD7303–SPECIFICATIONS

Parameter B Versions

to GND; all specifications T

1

Units Conditions/Comments

MIN

to T

unless otherwise noted)

MAX

STATIC PERFORMANCE

Resolution 8 Bits
Relative Accuracy ±1 LSB max Note 2
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Zero-Code Error @ +25°C 3 LSB max All Zeros Loaded to DAC Register
Full-Scale Error –0.5 LSB typ All Ones Loaded to DAC Register
Gain Error

3

+1 % FSR typ

Zero-Code Temperature Coefficient 100 µV/°C typ

DAC REFERENCE INPUT

REFIN Input Range 1 to V
REFIN Input Impedance 10 ΜΩ typ
Internal Voltage Reference Error

4

±1 % max

/2 V min to max

DD

OUTPUT CHARACTERISTICS

Output Voltage Range 0 to V

DD

V min to max

Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ
Digital to Analog Glitch Impulse 0.5 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Analog Crosstalk ±0.2 LSB typ
DC Output Impedance 40 Ω typ
Short Circuit Current 14 mA typ
Power Supply Rejection Ratio 0.0001 %/% max ∆ VDD = ±10%

LOGIC INPUTS

Input Current ±10 µA max
V

, Input Low Voltage 0.8 V max VDD = +5 V

INL

V

, Input High Voltage 2.4 V min VDD = +5 V

INH

0.6 V max V

2.1 V min V

= +3 V

DD

= +3 V

DD

Pin Capacitance 5 pF max

POWER REQUIREMENTS

V

DD

I

(Normal Mode) Both DACs Active and Excluding Load Currents,

DD

V

= 3.3 V VIH = VDD, VIL = GND

DD

2.7/5.5 V min/max

@ +25°C 2.1 mA max See Figure 8
T

V

MIN

DD

– T

= 5.5 V

MAX

2.3 mA max

@ +25°C 2.7 mA max
T

– T

MIN

I

(Full Power-Down)

DD

MAX

@ +25°C 80 nA typ V
T

– T

MIN

MAX

NOTES

1

Temperature ranges are as follows: B Version, –40°C to +105°C.

2

Relative Accuracy is calculated using a reduced digital code range of 15 to 245.

3

Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.

4

Internal Voltage Reference Error = (Actual V
is selected.

Specifications subject to change without notice.

REF

3.5 mA max

1 µA max See Figure 19

– Ideal V

REF

/Ideal V

) • 100. Ideal V

REF

= VDD/2, actual V

REF

= VDD, VIL = GND

IH

= voltage on reference pin when internal reference

REF

ORDERING GUIDE

Temperature Package

Model Range Options*

AD7303BN –40°C to +105°C N-8
AD7303BR –40°C to +105°C SO-8
AD7303BRM –40°C to +105°C RM-8

*N = Plastic DIP; R = SOIC; RM = microSOIC.

–2–

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AD7303

(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference; all specifications

1, 2

T

to T

TIMING CHARACTERISTICS

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2,
tr and tf should not exceed 1 µs on any input.

2

See Figures 1 and 2.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
5 ns min SYNC Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time

4.5 ns min SYNC Hold Time
33 ns min Minimum SYNC High Time

MIN

, T

MIN

(B Version) Units Conditions/Comments

MAX

SCLK (I)

t

t

8

4

SYNC (I)

t

5

t

6

DIN (I)

DB15

unless otherwise noted)

MAX

t

1

t

2

t

3

DB0

t

7

t

4

SCLK (I)

SYNC (I)

DIN (I)

Figure 1. Timing Diagram for Continuous 16-Bit Write

t

t

t

4

8

t

5

t

6

DB15 DB8

Figure 2. Timing Diagram for 2 × 8-Bit Writes

t

1

t

2

3

t

5

t

6

DB7 DB0

t

7

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–3–

AD7303

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Reference Input Voltage to GND . . . . –0.3 V to V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

V

OUT

A, V

B to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 800 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W

JA

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 157°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7303 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

(DIP, SOIC and microSOIC)

B

V

1

V

A

OUT

V

2

DD

AD7303

TOP VIEW

3

GND

(Not to Scale)

REF

4

8

OUT

7

SYNC

6

DIN

5

SCLK

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V

A Analog Output Voltage from DAC A. The output amplifier swings rail to rail on its output.

OUT

DD

Power Supply Input. These parts can be operated from +2.7 V to +5.5 V and should be decoupled to GND.
3 GND Ground reference point for all circuitry on the part.
4 REF External Reference Input. This can be used as the reference for both DACs, and is selected by setting the

INT/EXT bit in the control register to a logic one. The range on this reference input is 1 V to VDD/2. When

the internal reference is selected, this voltage will appear as an output for decoupling purposes at the REF Pin.

When using the internal reference, external voltages should not be connected to the REF Pin, see Figure 21.
5 SCLK Serial Clock. Logic Input. Data is clocked into the input shift register on the rising edge of the serial clock

input. Data can be transferred at rates up to 30 MHz.
6 DIN Serial Data Input. This device has a 16-bit shift register, 8 bits for data and 8 bits for control. Data is clocked

into the register on the rising edge of the clock input.
7

SYNC Level Triggered Control Input (active low). This is the frame synchronization signal for the input data. When

8V

SYNC goes low, it enables the input shift register and data is transferred in on the rising edges of the following

clocks. The rising edge of the

B Analog output voltage from DAC B. The output amplifier swings rail to rail on its output.

OUT

SYNC causes the relevant registers to be updated.

–4–

REV. 0

AD7303

TERMINOLOGY

INTEGRAL NONLINEARITY

For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func­tion. A graphical representation of the transfer curve is shown
in Figure 15.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change of any two adjacent codes. A
specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity.

ZERO CODE ERROR

Zero code error is the measured output voltage from V

OUT

of
either DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-scale error is expressed in LSBs.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. Gain error is calcu­lated between Codes 15 and 245.

FULL-SCALE ERROR

Full-Scale Error is a measure of the output error when the DAC
latch is loaded with FF Hex. Full-scale error includes the offset
error.

DIGITAL-TO-ANALOG GLITCH IMPULSE

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the software LDAC used to update the DAC.
It is normally specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-s and measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.

DIGITAL CROSSTALK

Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.

ANALOG CROSSTALK

Analog crosstalk is a change in output of any DAC in response
to a change in the output of the other DAC. It is measured in
LSBs.

POWER SUPPLY REJECTION RATIO (PSRR)

This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
rejection ratio is quoted in terms of % change in output per %
of change in V

for full-scale output of the DAC. VDD is varied

DD

± 10%. This specification applies to an external reference only
because the output voltage will track the V

voltage when in-

DD

ternal reference is selected.

REV. 0

–5–