Analog Devices AD7302BRU, AD7302BR, AD7302BN Datasheet

2.7 V to 5.5 V, Parallel Input

POWER ON

RESET

D0

REFIN

V

DD

AD7302

V

OUT

A

DGND

D7

AGND

/B

I/V

V

OUT

B

MUX

÷2

INPUT

REGISTER

DAC

REGISTER

I DAC A

DAC

REGISTER

I DAC B

I/V

INPUT

REGISTER

CONTROL

LOGIC

a

FEATURES
Two 8-Bit DACs In One Package
20-Lead DIP/SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer

Rail-to-Rail Operation
Low Power Operation 3 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

GENERAL DESCRIPTION

The AD7302 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision
output buffers allow the DAC outputs to swing rail to rail. The
AD7302 has a parallel microprocessor and DSP-compatible
interface with high speed registers and double buffered interface
logic. Data is loaded to the registers on the rising edge of CS or
WR and the A/B pin selects either DAC A or DAC B.

Reference selection for AD7302 can be either an internal
reference derived from the V
at the REFIN pin. Both DACs can be simultaneously updated
using the asynchronous LDAC input and can be cleared by
using the asynchronous CLR input.

The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-

tion is less than 10 mW at 3.3 V, reducing to 3 µW in power-

down mode.

The AD7302 is available in a 20-pin plastic dual-in-line package,
20-lead SOIC and a 20-lead TSSOP package.

or an external reference applied

DD

Dual Voltage Output 8-Bit DAC

AD7302

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1.␣ Low Power, Single Supply Operation. This part operates
from a single +2.7 V to +5.5 V supply and typically consumes
15 mW at 5 V, making it ideal for battery powered applications.

2.␣ The on-chip output buffer amplifiers allow the outputs of the

DACs to swing rail to rail with a settling time of typically 1.2 µs.

3.␣ Internal or external reference capability.

4.␣ High speed parallel interface.

5. Power-Down Capability. When powered down the DAC

consumes less than 1 µA at 25°C.

6. Packaged in 20-lead DIP, SOIC and TSSOP packages.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone] © Analog Devices, Inc., 1997

(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND;
to T

AD7302–SPECIFICATIONS

Parameter B Versions

unless otherwise noted)

MAX

1

Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8 Bits

Relative Accuracy ±1 LSB max Note 2
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic

Full-Scale Error –0.75 LSB typ

Zero Code Error @ 25°C 3 LSB typ All Zeroes Loaded to DAC Register

Gain Error

3

±1 % FSR typ

Zero Code Temperature Coefficient 100 µV/°C typ

DAC REFERENCE INPUT

REFIN Input Range 1.0 to V

/2 V min to max

DD

REFIN Input Impedance 10 MΩ typ

OUTPUT CHARACTERISTICS

Output Voltage Range 0 to V

DD

V min to max

Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ

Digital to Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
Digital Crosstalk 0.2 nV-s typ

Analog Crosstalk ±0.2 LSB typ
DC Output Impedance 40 Ω typ

Short Circuit Current 14 mA typ
Power Supply Rejection Ratio

4

0.0003 %/% max ∆VDD = ±10%

LOGIC INPUTS

Input Current ±10 µA max

, Input Low Voltage 0.8 V max VDD = +5 V

V

INL

, Input Low Voltage 0.6 V max VDD = +3␣ V

V

INL

, Input High Voltage 2.4 V min V

V

INH

, Input High Voltage 2.1 V min V

V

INH

DD

DD

Pin Capacitance 7 pF max

POWER REQUIREMENTS

V

DD

I

DD

= 3.3 V VIH = VDD and VIL = GND

V

DD

2.7/5.5 V min/max
Both DACs Active and Excluding Load Currents

@ 25°C 2.8 mA max Typically 2.3 mA

to T

MIN

MAX

= 5.5 V VIH = VDD and VIL = GND

V

@ T

DD

3 mA max See Figures 6 and 7

@ 25°C 4.5 mA max Typically 2.8 mA

MIN

to T

MAX

@ T

(Full Power-Down)

I

DD

@ 25°C1µA max V

T

to T

MIN

NOTES

1

Temperature ranges are as follows: B Version: –40°C to +105°C.

2

Relative Accuracy is calculated using a reduced code range of 15 to 245.

3

Gain error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.

4

Guaranteed by characterization at product release, not production tested.

Specifications subject to change without notice.

MAX

5 mA max See Figures 6 and 7

IH

2 µA max See Figure 18

= +5 V
= +3 V

= VDD and VIL = GND

–2–

REV. 0

(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference;

TIMING CHARACTERISTICS

Limit at T

1, 2

all specifications T

, T

MIN

MAX

MIN

to T

unless otherwise noted)

MAX

Parameter (B Version) Units Conditions/Comments

AD7302

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
(VIL + V

2

See Figure 1.

)/2. tr and tf should not exceed 1 µs on any digital input.

IH

D7–D0

0 ns min Address to Write Setup Time
0 ns min Address Valid to Write Hold Time
0 ns min Chip Select to Write Setup Time
0 ns min Chip Select to Write Hold Time
20 ns min Write Pulse Width
15 ns min Data Setup Time

4.5 ns min Data Hold Time
20 ns min Write to LDAC Setup Time
20 ns min LDAC Pulse Width
20 ns min CLR Pulse Width

DD

t

1

/B

t

3

t

5

t

2

t

4

t

7

t

6

) and timed from a voltage level of

t

8

t

9

t

10

Figure 1. Timing Diagram for Parallel Data Write

REV. 0

–3–

AD7302

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Reference Input Voltage to AGND . . . .–0.3 V to V

Digital Input Voltage to DGND . . . . . –0.3 V to V

+ 0.3␣ V

DD

+ 0.3 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 0.3 V

V

OUT

A, V

B to AGND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

OUT

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 900 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W

θ

JA

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .+260°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 700 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W

θ

JA

Lead Temperature, Soldering

␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C

␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W

θ

JA

Lead Temperature, Soldering

␣ ␣ Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C

␣ ␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7302 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature Package

Model Range Options*

AD7302BN –40°C to +105°C N-20
AD7302BR –40°C to +105°C R-20
AD7302BRU –40°C to +105°C RU-20

*N = Plastic DIP; R = Small Outline; RU =Thin Shrink Small Outline.

–4–

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AD7302

14
13
12
11

17
16
15

20
19
18

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

AD7302

(MSB) DB7

AGND

V

OUT

B

V

OUT

A

DGND
DB6
DB5
DB4

V

DD

REFIN

DB3
DB2
DB1

(LSB) DB0

/B

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1-8 D7–D0 Parallel Data Inputs. Eight-bit data is loaded to the input register of the AD7302 under the control of CS

and WR.
9 CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS and A/B to write data to the selected

DAC register.
11 A/B DAC Select. Address pin used to select writing to either DAC A or DAC B.

12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low both DAC outputs are simultaneously updated with

the contents of their DAC registers. If LDAC is permanently tied low, the DACs are updated on the rising

edge of WR.
14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC registers are loaded with all

zeroes and the DAC outputs are cleared to zero volts.
15 V

DD

16 REFIN External Reference Input. This can used as the reference for both DACs. The range on this reference input is

17 AGND Analog Ground reference point and return point for all analog current on the part.
18 V
19 V

B Analog output voltage from DAC B. The output amplifier can swing rail to rail on its output.

OUT

A Analog output voltage from DAC A. The output amplifier can swing rail to rail on its output.

OUT

20 DGND Digital Ground reference point and return point for all digital current on the part.

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and should be decoupled to AGND.

1 V to V

/2. If REFIN is directly tied to VDD the internal VDD/2 reference is selected.

DD

REV. 0

PIN CONFIGURATION

–5–