Analog Devices AD7233BN Datasheet

LC2MOS

a

FEATURES
12-Bit CMOS DAC with

On-Chip Voltage Reference
Output Amplifier

–5 V to +5 V Output Range
Serial Interface
300 kHz DAC Update Rate
Small Size: 8-Pin Mini-DIP
Nonlinearity: ⴞ1/2 LSB T
Low Power Dissipation: 100 mW Typ

APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports

GENERAL DESCRIPTION

The AD7233 is a complete 12-bit, voltage-output, digital-to­analog converter with output amplifier and Zener voltage reference
all in an 8-lead package. No external trims are required to
achieve full specified performance. The data format is two’s
complement, and the output range is –5 V to +5 V.

The AD7233 features a fast, versatile serial interface which
allows easy connection to both microcomputers and 16-bit digital
signal processors with serial ports. When the SYNC input is
taken low, data on the SDIN pin is clocked into the input shift
register on each falling edge of SCLK. On completion of the
16-bit data transfer, bringing LDAC low updates the DAC latch
with the lower 12 bits of data and updates the output. Alterna­tively, LDAC can be tied permanently low, and in this case the
DAC register is automatically updated with the contents of the
shift register when all sixteen data bits have been clocked in.
The serial data may be applied at rates up to 5 MHz allowing a
DAC update rate of 300 kHz.

For applications which require greater flexibility and unipolar
output ranges with single supply operation, please refer to the
AD7243 data sheet.

The AD7233 is fabricated on Linear Compatible CMOS

2

(LC

MOS), an advanced, mixed-technology process. It is pack-

aged in an 8-lead DIP package.

MIN

to T

MAX

12-Bit Serial Mini-DIP DACPORT

AD7233

FUNCTIONAL BLOCK DIAGRAM

V

DD

2R

12-BIT

DAC

12

DAC

LATCH

AD7233

SDIN SCLK SYNC LDAC

PRODUCT HIGHLIGHTS

12

INPUT SHIFT

REGISTER

1. Complete 12-Bit DACPORT®.

2. The AD7233 is a complete, voltage output, 12-bit DAC on a
single chip. This single-chip design is inherently more reli­able than multichip designs.

3. Simple 3-wire interface to most microcontrollers and DSP
processors.

4. DAC Update Rate—300 kHz.

5. Space Saving 8-Lead Package.

2R

V

OUT

GND

V

SS

DACPORT is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

(VDD = +12 V to +15 V,2 VSS = –12 V to –15 V,2 GND = 0 V, RL = 2 k⍀, CL = 100 pF

AD7233–SPECIFICATIONS

P

arameter A Version B Version Unit Test Conditions/Comments

1

to GND. All specifications T

MIN

to T

unless otherwise noted.)

MAX

STATIC PERFORMANCE

Resolution 12 12 Bits
Relative Accuracy
Differential Nonlinearity
Bipolar Zero Error
Full-Scale Error

3

3

3

3

± 1 ± 1/2 LSB max
± 0.9 ± 0.9 LSB max Guaranteed Monotonic
± 6 ± 6 LSB max DAC Latch Contents 0000 0000 0000
± 8 ± 8 LSB max

Full-Scale Temperature Coefficient4± 30 ± 30 ppm of FSR/°C typ Guaranteed By Process

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INH

INL

2.4 2.4 V min

0.8 0.8 V max

Input Current

I

IN

Input Capacitance

4

± 1 ± 1 µA max VIN = 0 V to V
8 8 pF max

DD

ANALOG OUTPUTS

Output Voltage Range ± 5 ± 5V
DC Output Impedance

AC CHARACTERISTICS

4

4

0.5 0.5 Ω typ

Voltage Output Settling Time Settling Time to Within ±1/2 LSB of Final Value

Positive Full-Scale Change 10 10 µs max Typically 4 µs; DAC Latch 100. . .000 to 011. . .111

Negative Full-Scale Change 10 10 µs max Typically 5 µs; DAC Latch 011. . .111 to 100. . .000
Digital-to-Analog Glitch Impulse
Digital Feedthrough

3

3

30 30 nV secs typ DAC Latch Contents Toggled Between All 0s and all 1s
10 10 nV secs typ LDAC = High

POWER REQUIREMENTS

VDD Range 10.8/16.5 10.8/16.5 V min/V max For Specified Performance Unless Otherwise Stated
VSS Range –10.8/–16.5 –10.8/–16.5 V min/V max For Specified Performance Unless Otherwise Stated
I

DD

I

SS

NOTES

1

Temperature Ranges are as follows: A, B Versions: –40°C to +85°C.

2

Power Supply Tolerance: A, B Versions: ± 10%.

3

See Terminology.

4

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

10 10 mA max Output Unloaded; Typically 7 mA at Thresholds
2 2 mA max Output Unloaded; Typically 1 mA at Th

resholds

(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, GND = O V, RL = 2 k⍀, CL = 100 pF. All

1, 2

TIMING CHARACTERISTICS

Limit at 25ⴗC, T

MIN

Specifications T

, T

MAX

MIN

to T

unless otherwise noted.)

MAX

Parameter (All Versions) Unit Conditions/Comments

3

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figure 3.

3

SCLK Mark/Space Ratio range is 40/60 to 60/40.

200 ns min SCLK Cycle Time
15 ns min SYNC to SCLK Falling Edge Setup Time
70 ns min SYNC to SCLK Hold Time
0 ns min Data Setup Time
40 ns min Data Hold Time
0 ns min SYNC High to LDAC Low
20 ns min LDAC Pulsewidth
0 ns min LDAC High to SYNC Low

–2–

REV. B

AD7233

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

SS

2

to GND . . . . . . . . . . . . . . . . . . . . –6 V to VDD +0.3 V

V

OUT

Digital Inputs to GND . . . . . . . . . . . . –0.3 V to V

+0.3 V

DD

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C

Power Dissipation to 75°C . . . . . . . . . . . . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V

TERMINOLOGY

RELATIVE ACCURACY (LINEARITY)

Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a straight
line passing through the endpoints of the transfer function. It is
measured after allowing for zero and full-scale errors and is
expressed in LSBs or as a percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB or less
over the operating temperature range ensures monotonicity.

BIPOLAR ZERO ERROR

Bipolar zero error is the voltage measured at V

when the

OUT

DAC is loaded with all 0s. It is due to a combination of offset
errors in the DAC, amplifier and mismatch between the internal
gain resistors around the amplifier.

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

The output may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.

ORDERING GUIDE

Temperature Relative Package

Model Range Accuracy Option*

AD7233AN –40°C to +85°C ± 1 LSB N-8
AD7233BN –40°C to +85°C ± 1/2 LSB N-8

*N = Plastic DIP.

FULL-SCALE ERROR

Full-scale error is a measure of the output error when the
amplifier output is at full scale (full scale is either positive or
negative full scale).

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the voltage spike that appears at the output of the DAC
when the digital code in the DAC latch changes before the out­put settles to its final value. The energy in the glitch is specified
in nV secs, and is measured for an all codes change (0000 0000
0000 to 1111 1111 1111).

DIGITAL FEEDTHROUGH

This is a measure of the voltage spike that appears on V

OUT

as a

result of feedthrough from the digital inputs on the AD7233. It
is measured with LDAC held high.

REV. B

–3–