Analog Devices AD7228ATQ, AD7228ACR, AD7228ACQ, AD7228ACP, AD7228ACN Datasheet

REV. A

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a

LC2MOS

Octal 8-Bit DAC

AD7228A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Eight DACs and Amplifiers in Small Package
The single-chip design of eight 8-bit DACs and amplifiers al­lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert­ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one side of the package and all
digital inputs at the other.

2. Single or Dual Supply Operation
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228A. The part can also be oper­ated with dual supplies giving enhanced performance for
some parameters.

3. Microprocessor Compatibility
The AD7228A has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most high per­formance 8-bit microprocessors.

FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single +5 V, +12 V or +15 V

or Dual Supplies

mP Compatible (95 ns

WR Pulse)
No User Trims Required
Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface

Mount Packages

GENERAL DESCRIPTION

The AD7228A contains eight 8-bit voltage-mode digital-to­analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.

Separate on-chip latches are provided for each of the eight D/A
converters. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5 V) compatible input port. Ad­dress inputs A0, A1 and A2 determine which latch is loaded
when

WR goes low. The control logic is speed compatible with

most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages

from +2 to +10 V when using dual supplies. The part is also
specified for single supply +15 V operation using a reference of
+10 V and single supply +5 V operation using a reference of
+1.23 V. Each output buffer amplifier is capable of developing
+10 V across a 2 kΩ load.

The AD7228A is fabricated on an all ion-implanted, high­speed, Linear Compatible CMOS (LC

2

MOS) process which has
been specifically developed to integrate high-speed digital logic
circuits and precision analog circuits on the same chip.

REV. A

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AD7228A–SPECIFICA TIONS

(VDD = 10.8 V to 16.5 V; VSS = –5 V 6 10%; GND = 0 V; V

REF

= +2 V to +10 V1; RL = 2 kΩ, CL = 100 pF unless otherwise

noted.) All specifications T

MIN

to T

MAX

unless otherwise noted.

5

Sample tested at 25°C to ensure compliance.

6

The glitch impulse transferred to the output of one converter (not addressed) due to a

change in the digital input code to another addressed converter.

Specifications subject to change without notice.

(VDD = +15 V 6 10%, VSS; = GND = 0 V; V

REF

= +10 V, RL = 2 kΩ, CL = 100 pF unless otherwise noted.)

AII specifications T

MIN

to T

MAX

unless otherwise noted.

DUAL SUPPLY

BCTU

Parameter Version2Version Version Version Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8 8 8 8 Bits
Total Unadjusted Error

3

±2 ±1 ±2 ±1 LSB max VDD = +15 V ± 10%, V

REF

= +10 V
Relative Accuracy ± 1 ± 1/2 ± 1 ±1/2 LSB max
Differential Nonlinearity ± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error

4

± 1 ± 1/2 ± 1 ± 1/2 LSB max Typical tempco is 5 ppm/°C with V

REF

= +10 V
Zero Code Error
@ 25°C ±25 ±15 ±25 ±15 mV max Typical tempco is 30 µV/°C

T

MIN

to T

MAX

±30 ±20 ±30 ±20 mV max

Minimum Load Resistance 2 2 2 2 kΩ min V

OUT

= +10 V

REFERENCE INPUT

Voltage Range

1

2 to 10 2 to 10 2 to 10 2 to 10 V min/V max
Input Resistance 2 2 2 2 kΩ min
Input Capacitance

5

500 500 500 500 pF max Occurs when each DAC is loaded with all 1s.
AC Feedthrough –70 –70 –70 –7 0 dB typ V

REF

= 8 V p-p Sine Wave @ 10 kHz

DIGITAL INPUTS

Input High Voltage, V

INH

2.4 2.4 2.4 2.4 V min

Input Low Voltage, V

INL

0.8 0.8 0.8 0.8 V max

Input Leakage Current ±1 ±1 ±1 ±1 µA max VIN = 0 V or V

DD

Input Capacitance

5

8 8 8 8 pF max
Input Coding Binary Binary Binary Binary

DYNAMIC PERFORMANCE

5

Voltage Output Slew Rate 2 2 2 2 V/µs min
Voltage Output Settling Time

Positive Full-Scale Change 5 5 5 5 µs max V

REF

= +10 V; Settling Time to ±1/2 LSB

Negative Full-Scale Change 5 5 5 5 µs max V

REF

= +10 V; Settling Time to ±1/2 LSB

Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

REF

= 0 V; WR = V

DD

Digital Crosstalk

6

50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

REF

= +10 V; WR = 0 V

POWER SUPPLIES

VDD Range 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max For Specified Performance
VSS Range –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max For Specified Performance
I

DD

Outputs Unloaded; VIN = V

INL

or V

INH

@ 25°C 16 16 16 1 6 mA max
T

MIN

to T

MAX

20 20 22 22 mA max
I

SS

Outputs Unloaded; VIN = V

INL

or V

INH

@ 25°C 14 14 14 1 4 mA max
T

MIN

to T

MAX

18 18 20 20 mA max

SINGLE SUPPLY

STATIC PERFORMANCE

Resolution 8 8 8 8 Bits
Total Unadjusted Error

3

±2 ±1 ±2 ±1 LSB max
Differential Nonlinearity ± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Minimum Load Resistance 2 2 2 2 kΩ min V

OUT

= +10 V

REFERENCE INPUT

Input Resistance 2 2 2 2 kΩ min
Input Capacitance

5

500 500 500 500 pF max Occurs when each DAC is loaded with all 1s.

DIGITAL INPUTS As per Dual Supply Specifications
DYNAMIC PERFORMANCE

5

Voltage Output Slew Rate 2 2 2 2 V/µs min
Voltage Output Settling Time

Positive Full-Scale Change 5 5 5 5 µs max Settling Time to ±1/2 LSB
Negative Full-Scale Change 7 7 7 7 µs max Settling Time to ±1/2 LSB

Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

REF

= 0 V; WR = V

DD

Digital Crosstalk

6

50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

REF

= +10 V, WR = 0 V

POWER SUPPLIES

VDD Range 13.5/16.5 13.5/16.5 13.5/16.5 13.5/16.5 V min/V max For Specified Performance
I

DD

Outputs Unloaded; VIN = V

INL

or V

INH

@ 25°C 16 16 16 1 6 mA max
T

MIN

to T

MAX

20 20 22 22 mA max

NOTES

1

V

OUT

must be less than VDD by 3.5 V to ensure correct operation.

2

Temperature ranges are as follows:

B, C Versions; –40°C to +85°C
T, U Versions; –55°C to +125°C

3

Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.

4

Calculated after zero code error has been adjusted out.

SWITCHING CHARACTERISTICS

1, 2

Limit at 25°C Limit at T

MIN

, T

MAX

Limit at T

MIN

, T

MAX

Parameters All Grades (B, C Versions) (T, U Versions) Units Conditions/Comments

t

1

0 0 0 ns min Address to WR Setup Time

t

2

0 0 0 ns min Address to WR Hold Time

t

3

70 90 100 ns min Data Valid to WR Setup Time

t

4

10 10 10 ns min Data Valid to WR Hold Time

t

5

95 120 150 ns min Write Pulse Width

NOTES

1

Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, tR = tF = 5 ns.

2

Timing measurement reference level is

V

INH+VINL

2

INTERFACE LOGIC INFORMATION

Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the

WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of

WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.

Table I. AD7228A Truth Table

AD7228A Control Inputs AD7228A
WR A2 A1 A0 Operation

H X X X No Operation

Device Not Selected

LLLL DAC 1 Transparent

g

L L L DAC 1 Latched
LLLH DAC 2 Transparent
L L H L DAC 3 Transparent
L L H H DAC 4 Transparent
L H L L DAC 5 Transparent
L H L H DAC 6 Transparent
L H H L DAC 7 Transparent
L H H H DAC 8 Transparent

H = High State L = Low State X = Don’t Care

+5 V SUPPLY OPERA TION

BCTU

Parameter Version Version Version Version Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8888Bits
Relative Accuracy ± 2 ±2 ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error ± 4 ±2 ±4 ±2 LSB max
Zero Code Error

@ 25°C ±30 ±20 ± 30 ±20 mV max
T

MIN

to T

MAX

±40 ± 30 ±40 ±30 mV max

REFERENCE INPUT

Reference Input Range 1.2 1.2 1.2 1.2 V min

1.3 1.3 1.3 1.3 V max
Reference Input Resistance 2222kΩ min
Reference Input Capacitance 500 500 500 500 pF max

POWER REQUIREMENTS

Positive Supply Range 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 V min/V max For Specified Performance
Positive Supply Current

@ 25°C 16161616µA max
T

MIN

to T

MAX

20 20 22 22 µA max

Negative Supply Current

@ 25°C 14141414µA max
T

MIN

to T

MAX

18 18 20 20 µA max

NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V

SS

= 0 V.

Specifications subject to change without notice.

(VDD = +5 V 6 5%, VSS; = 0 to –5 V 6 10%, GND = 0 V, V

REF

= +1.25 V, RL = 2 kV, CL = 100 pF

unless otherwise noted.) AII specifications T

MIN

to T

MAX

unless otherwise noted.

(See Figures 1, 2; VDD = +5 V 6 5% or +10.8 V to +16.5 V; VSS = 0 V or –5 V 6 10%)

Figure 1. Input Control Logic

Figure 2. Write Cycle Timing Diagram

AD7228A

REV. A

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