Analog Devices AD671SD-750, AD671SD-500, AD671KD-750, AD671KD-500, AD671JD-750 Datasheet

AIN BPO/UPO ENCODE REF IN ACOM DCOM

LATCHES

CORRECTION LOGIC

RANGE

SELECT

X4

COARSE

4-BIT

FLASH

8-BIT

LADDER

MATRIX

FINE
4-BIT

FLASH

AD671

3

4

4

8

12

20

DAC

OTR MSB BIT1-12 DAV

21

16

19

23 22 24

17

18

3-BIT

FLASH

3

DAC

3-BIT

FLASH

14 13 1512 1

V

CC

V

LOGIC

EE

V

Monolithic 12-Bit

a

FEATURES
12-Bit Resolution
24-Pin “Skinny DIP” Package
Conversion Time: 500 ns max—AD671J/K/S-500

Conversion Time: 750 ns max—AD671J/K/S-750

Low Power: 475 mW
Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input

Ranges (65 V)
Twos Complement or Offset Binary Output Data
Out-of-Range Indicator
MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD671 is a high speed monolithic 12-bit A/D converter
offering conversion rates of up to 2 MHz (500 ns conversion
time). The combination of a merged high speed bipolar/CMOS
process and a novel architecture results in a combination of
speed and power consumption far superior to previously avail­able hybrid implementations. Additionally, the greater reliability
of monolithic construction offers improved system reliability
and lower costs than hybrid designs.

The AD671 uses a subranging flash conversion technique, with
digital error correction for possible errors introduced in the first
part of the conversion cycle. An on-chip timing generator pro­vides strobe pulses for each of the four internal flash cycles and
assures adequate settling time for the interflash residue ampli­fier. A single ENCODE pulse is used to control the converter.

The performance of the AD671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.

The AD671 is available in two conversion speeds and perfor­mance grades. The AD671J and K grades are specified for op­eration over the 0°C to +70°C temperature range. The AD671S
grades are specified for operation over the –55°C to +125°C
temperature range. All grades are available in a 0.300 inch wide
24-pin ceramic DIP. The J and K grades are also available in a
24-pin plastic DIP.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

2 MHz A/D Converter

AD671

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. The AD671 offers a single chip 2 MHz analog-to-digital
conversion function in a space saving 24-pin DIP.

2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo­lar, and –5 V to +5 V bipolar, selected by pin strapping. In­put resistance is 1.5 kΩ. Power supplies are +5 V and –5 V,
and typical power consumption is less than 500 mW.

3. The external +5 V reference can be chosen to suit the dc ac­curacy and temperature drift requirements of the application.

4. Output data is available in unipolar, bipolar offset or bipolar
twos complement binary format.

5. An OUT OF RANGE output bit indicates when the input
signal is beyond the AD671’s input range.

6. The AD671 is available in versions compliant with the MIL­STD-883. Refer to the Analog Devices Military Products
Databook or current AD671/883B data sheet for detailed
specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD671–SPECIFICATIONS

(T

to T

with VCC = +5 V 6 5%, V

MAX

DC SPECIFICATIONS

MIN

unless otherwise noted)

AD671J/S-500 AD671K-500

Parameter Min Typ Max Min Typ Max Units

RESOLUTION 12 12 Bits
ACCURACY (+25°C)

Integral Nonlinearity (INL)

T

to T

MIN

MAX

Differential Nonlinearity (DNL)

T

to T

MIN

No Missing Codes 10 Bits Guaranteed 11 Bits Guaranteed
Unipolar Offset
Bipolar Zero
Gain Error

TEMPERATURE COEFFICIENTS

MAX

l

l

2

3

10 11 Bits

0.1 0.25 0.1 0.25 % FSR

Unipolar Offset 610 610 ppm/°C
Bipolar Zero 615 615 ppm/°C
Gain Error 620 620 ppm/°C

ANALOG INPUT

Input Ranges

Bipolar –5 +5 –5 +5 Volts
Unipolar 0+50+5Volts

0 +10 0 +10 Volts

Input Resistance

10 Volt Range 1.0 1.5 2.0 1.0 1.5 2.0 kΩ
5 Volt Range 0.5 0.75 1.0 0.5 0.75 1.0 kΩ

Input Capacitance 10 10 pF
Reference Input Resistance 2.4 3.5 4.7 2.4 3.5 4.7 kΩ

= +5 V 610%, VEE = –5 V 6 5%, V

LOGIC

= +5.000 V,

REF

64 62 LSB

64 64 LSB
610 610 LSB

POWER SUPPLIES

Power Supply Rejection

V

(+5 V ± 0.25 V) 61 61 LSB

CC

V

(+5 V ± 0.5 V) 61 61 LSB

LOGIC

V

(–5 V ± 0.25 V) 61 61 LSB

EE

4

Operating Voltages

V
V
V

CC
LOGIC
EE

+4.75 +5.25 +4.75 +5.25 Volts
+4.5 +5.5 +4.5 +5.5 Volts
–5.25 –4.75 –5.25 –4.75 Volts

Operating Current

I

CC

I

LOGIC

I

EE

5

46 56 46 56 mA
3 6 3 6 mA
46 56 46 56 mA

POWER CONSUMPTION 475 621 475 621 mW

TEMPERATURE RANGE

Specified (J/K) 0 +70 0 +70 °C

Specified (S) –55 +125 °C

NOTES

1

Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.

2

Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.

3

25°C to T

4

Change in gain error as a function of the dc supply voltage.

5

Tested under static conditions. See Figure 12 for typical curves of I

Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are

used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

and 25°C to T

MIN

MAX

.

vs. Conversion Rate and Output Loading.

LOGIC

–2–

REV. B

AD671

(T

to T

with VCC = +5 V 6 5%, V

MAX

DC SPECIFICATIONS

MIN

unless otherwise noted)

AD671J/S-750 AD671K-750

Parameter Min Typ Max Min Typ Max Units

RESOLUTION 12 12 Bits
ACCURACY (+25°C)

Integral Nonlinearity (INL)

T
T

MIN
MIN

to T
to T

(J) 62 61.5 LSB

MAX

(S) 62.5 LSB

MAX

Differential Nonlinearity (DNL)

T

to T

MIN

No Missing Codes 11 Bits Guaranteed 12 Bits Guaranteed
Unipolar Offset
Bipolar Zero
Gain Error

TEMPERATURE COEFFICIENTS

MAX

l

l

2

3

11 12 Bits

0.1 0.25 0.1 0.25 % FSR

Unipolar Offset 610 610 ppm/°C
Bipolar Zero 615 615 ppm/°C
Gain Error 620 620 ppm/°C

ANALOG INPUT

Input Ranges

Bipolar –5 +5 –5 +5 Volts
Unipolar 0+50+5Volts

0 +10 0 +10 Volts

Input Resistance

10 Volt Range 1.0 1.5 2.0 1.0 1.5 2.0 kΩ
5 Volt Range 0.5 0.75 1.0 0.5 0.75 1.0 kΩ

Input Capacitance 10 10 pF
Reference Input Resistance 2.4 3.5 4.7 2.4 3.5 4.7 kΩ

= +5 V 6 10%, VEE = –5 V 6 5%, V

LOGIC

= +5.000 V,

REF

64 64 LSB
610 610 LSB

POWER SUPPLIES

Power Supply Rejection

V

(+5 V ± 0.25 V) 61 61 LSB

CC

V

(+5 V ± 0.5 V) 61 61 LSB

LOGIC

V

(–5 V ± 0.25 V) 61 61 LSB

EE

4

Operating Voltages

Vcc +4.75 +5.25 +4.75 +5.25 Volts
V

LOGIC

V

EE

+4.5 +5.5 +4.5 +5.5 Volts
–5.25 –4.75 –5.25 –4.75 Volts

Operating Current

I

CC

I

LOGIC

I

EE

5

46 56 46 56 mA
3 6 3 6 mA
46 56 46 56 mA

POWER CONSUMPTION 475 621 475 621 mW

TEMPERATURE RANGE

Specified (J/K) 0 +70 0 +70 °C

Specified (S) –55 +125 °C

NOTES

1

Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.

2

Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.

3

25°C to T

4

Change in gain error as a function of the dc supply voltage.

5

Tested under static conditions. See Figure 12 for typical curves of I

Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are

used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

and 25°C to T

MIN

MAX

.

vs. Conversion Rate and Output Loading.

LOGIC

REV. B

–3–

AD671–SPECIFICATIONS

(For all grades T

DIGITAL SPECIFICATIONS

6

5%, V

REF

Parameter Symbol Min Typ Max Units

LOGIC INPUT

High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current (V
Low Level Input Current (V

= V

IN

= 0 V) I

IN

)I

LOGIC

Input Capacitance C

LOGIC OUTPUTS

High Level Output Voltage (I
Low Level Output Voltage (I

= 0.5 mA) V

OH

= 1.6 mA) V

OL

Output Capacitance C

Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested.

Specifications subject to change without notice.

to T

MIN

, with VCC = +5 V 6 5%, V

MAX

= +5.000 V, unless otherwise noted)

IH

IL
IH
IL

IN

OH

OL

OUT

+2.0 V
–10 +10 µA

–10 +10 µA

+2.4 V

= +5 V 6 10%, VEE = –5 V

LOGIC

+0.8 V

5pF

+0.4 V

5pF

SWITCHING SPECIFICATIONS

(For all grades T

6

5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)

MIN

to T

with VCC = +5 V 6 5%, V

MAX

= +5 V 6 10%, VEE = –5 V

LOGIC

Parameter Symbol Min Typ Max Units

Conversion Time

(AD671-500) t
(AD671-750) t

C
C

475 500 ns
725 750 ns

ENCODE Pulse Width High

(AD671-500) t
(AD671-750) t

ENCODE Pulse Width Low t

ENC
ENC
ENCL

20 30 ns
20 50 ns
20 ns

DAV Pulse Width

(AD671-500) t

(AD671-750) t
ENCODE Falling Edge Delay t
Start New Conversion Delay t
Data and OTR Delay from DAV Falling Edge t
Data and OTR Valid before DAV Rising Edge t

NOTES

1

tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.

2

tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.

DAV
DAV
F
R
DD
SS

1

2

75 200 ns
75 300 ns
0ns
0ns
20 75 ns
20 75 ns

a. Encode Pulse HIGH

Figure 1. AD671 Timing Diagrams

–4–

b. Encode Pulse LOW

REV. B

AD671

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter to Min Max Units

V

CC

V

EE

V

LOGIC

ACOM –0.5 +6.5 Volts
ACOM –6.5 +0.5 Volts

DCOM –0.5 +6.5 Volts
ACOM DCOM –1.0 +1.0 Volts
V

CC

ENCODE DCOM –0.5 V
REF IN ACOM –0.5 V

V

LOGIC

–6.5 +6.5 Volts

+0.5 Volts

LOGIC

+0.5 Volts

CC

AIN, BPO/UPO ACOM –6.5 11.0 Volts
Junction Temperature +175 °C
Storage Temperature –65 +150 °C

l

Model

AD671JD-500 ±4 LSB 0°C to +70°C D-24A
AD671KD-500 ±2 LSB 0°C to +70°C D-24A
AD671JD-750 ±2 LSB 0°C to +70°C D-24A
AD671KD-750 ±1.5 LSB 0°C to +70°C D-24A
AD671SD-500 ±4 LSB –55°C to +125°C D-24A
AD671SD-750 ±2.5 LSB –55°C to +125°C D-24A

NOTES

1

For details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
current AD671/883 data sheet.

2

D = Ceramic DIP.

ORDERING GUIDE

Linearity Range Options

Lead Temperature (10 sec) +300 °C
Power Dissipation 1000 mW

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may effect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD671 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Temperature Package

2

REV. B

–5–