FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% Max
Low Gain TC: 5 ppm/C Max
Low Nonlinearity: 0.001% Max
Low Offset Voltage: 25 V
Low Noise 4 nV/√Hz (at 1 kHz) RTI
Gain Bandwidth Product: 25 MHz
16-Lead Ceramic or Plastic DIP Package,
20-Terminal LCC Package
Standard Military Drawing Available
MlL-Standard Parts Available
Low Cost
PRODUCT DESCRIPTION
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application: 1) Circuits requiring nonstandard gains (i.e., gains not easily achievable with
devices such as the AD524 and AD624). 2) Circuits requiring a
low cost, precision software programmable gain amplifier.
For low noise, high CMRR, and low drift the AD625JN is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
1 to 10,000. The error contribution of the AD625JN is less than
0.05% gain error and under 5 ppm/°C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
A software programmable gain amplifier (SPGA) can be configured with the addition of a CMOS multiplexer (or other switch
network), and a suitable resistor network. Because the ON
resistance of the switches is removed from the signal path, an
AD625 based SPGA will deliver 12-bit precision, and can be
programmed for any set of gains between 1 and 10,000, with
completely user selected gain steps.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25 µV/°C, output offset drift below
15 µV/°C, and a maximum nonlinearity of 0.001% at G = 1. All
grades exhibit excellent ac performance; a 25 MHz gain bandwidth product, 5 V/µs slew rate and 15 µs settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial (–40°C to +85°C) temperature range, two grades (J,
K) for commercial (0°C to +70°C) temperature range, and one
(S) grade rated over the extended (–55°C to +125°C) temperature range.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Instrumentation Amplifier
AD625
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD625 affords up to 16-bit precision for user selected
fixed gains from 1 to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be configured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
5. The proprietary design of the AD625 provides input voltage
noise of 4 nV/√Hz at 1 kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
G = 1 (RF = 20 kΩ)650650650kHz
G = 10400400400kHz
G = 100150150150kHz
G = 1000252525kHz
Slew Rate5.05.05.0V/µs
Settling Time to 0.01%, 20 V Step
G = 1 to 200151515µs
G = 500353535µs
G = 1000757575µs
1
Gain>256±0.01±0.008±0.005%
G = 1707575858090dB
G = 1085959010095105dB
G = 10095100105110110120dB
G = 1000100110110120115140dB
G = 1707575858090dB
G = 10909590105100115dB
G = 100100105105115110125dB
G = 1000110115110125120140dB
1
2
)
DL
)
CM
12 V –
(typical @ VS = 15 V, RL = 2 k and TA = + 25C, unless otherwise noted)
2 R
F
+ 1
R
G
±.0350.05±0.02
555ppm/°C
50±20
35±1
±10±10± 10V
G
×V
D
(
2
@ 5 mA@ 5 mA@ 5 mA
)
12 V –
2 R
F
+ 1
R
G
0.03±0.01
25±10
15±1
G
×V
D
(
)
2
12 V –
2 R
F
+ 1
R
G
G
×V
D
(
2
0.02%
15nA
5nA
)
–2–
REV. D
AD625
AD625A/J/S AD625B/K AD625C
ModelMinTypMaxMinTypMaxMinTypMaxUnit
NOISE
Voltage Noise, 1 kHz
R.T.I.444nV/√Hz
R.T.O.757575nV/√Hz
R.T.I., 0.1 Hz to 10 Hz
G = 1101010µV p-p
G = 101.01.01.0µV p-p
G = 1000.30.30.3µV p-p
G = 10000.20.20.2µV p-p
Current Noise
0.1 Hz to 10 Hz606060pA p-p
SENSE INPUT
R
IN
I
IN
Voltage Range± 10±10± 10V
Gain to Output1 ± 0.011 ± 0.011 ± 0.01%
REFERENCE INPUT
R
IN
I
IN
Voltage Range± 10±10± 10V
Gain to Output1 ± 0.011 ± 0.011 ± 0.01%
TEMPERATURE RANGE
Specified Performance
J/K Grades0+700+70°C
A/B/C Grades–40+85–40+85–40+85°C
S Grade–55+125°C
Storage–65+150–65+150–65+150°C
POWER SUPPLY
Power Supply Range±6 to ± 18±6 to ±18± 6 to ± 18V
Quiescent Current3.553.553.55mA
NOTES
1
Gain Error and Gain TC are for the AD625 only. Resistor Network errors will add to the specified errors.
2
VDL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at other gains = 10 V/G. VD = actual differential input voltage.
Example: G = 10, VD = 0.50; VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD625AD–40°C to +85°C16-Lead Ceramic DIPD-16
AD625BD–40°C to +85°C16-Lead Ceramic DIPD-16
AD625BD/+–40°C to +85°C16-Lead Ceramic DIPD-16
AD625CD–40°C to +85°C16-Lead Ceramic DIPD-16
AD625SD–55°C to +125°C16-Lead Ceramic DIPD-16
AD625SD/883B–55°C to +125°C16-Lead Ceramic DIPD-16
AD625SE/883B–55°C to +125°C20-Terminal Leadless Chip CarrierE-20A
AD625JN0°C to +70°C16-Lead Plastic DIPN-16
AD625KN0°C to +70°C16-Lead Plastic DIPN-16
AD625ACHIPS–40°C to +85°CDie
AD625SCHIPS–55°C to +125°CDie
5962-87719012A*–55°C to +125°C20-Terminal Leadless Chip CarrierE-20A
5962-8771901EA*–55°C to +125°C16-Lead Ceramic DIPD-16
*Standard Military Drawing Available
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD625 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONNECTIONS
Ceramic DIP (D) and Plastic DIP (N) Packages
1
+INPUT–INPUT
+GAIN SENSE–GAIN SENSE
RTI NULLRTO NULL
S
RTI NULLRTO NULL
+GAIN DRIVE
REFERENCEV
2
3
10k10k+V
–V
AD625
4
TOP VIEW
5
(Not to Scale)
NCSENSE
6
7
8
S
NC = NO CONNECT
16
15
14
13
–GAIN DRIVE
12
11
10
OUT
+V
9
S
–V
S
Leadless Chip Carrier (E) Package
+INPUT
+GAIN SENSE
4
RTI NULL
5
RTI NULL
NC
+GAIN DRIVE
NC
6
(Not to Scale)
7
8
910111213
AD625
TOP VIEW
–V
S
NC
NC
20 19123
–INPUT
–GAIN SENSE
S
OUT
+V
V
18
RTO NULL
17
RTO NULL
16
NC
15
–GAIN NULL
14
SENSE
REFERENCE
NC = NO CONNECT
REV. D–4–
Typical Performance Characteristics–A
D625
20
15
10
25C
5
INPUT VOLTAGE RANGE – V
0
0
5101520
SUPPLY VOLTAGE – V
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
–160
–140
G = 1000
G = 100
–120
G = 10
–100
G = 1
–80
CMRR – dM
–60
–40
–20
0
0
101001k10k 100k 10M
FREQUENCY – Hz
Figure 4. CMRR vs. Frequency
RTI, Zero to 1 k
Ω
Source Imbal-
ance
20
15
10
5
OUTPUT VOLTAGE SWING – V
0
0
5101520
SUPPLY VOLTAGE – V
Figure 2. Output Voltage Swing
vs. Supply Voltage
30
G = 1, 100
20
BANDWIDTH
LIMITED
G = 100
10
FULL POWER RESPONSE – V p-p
0
G = 500
G = 1000
1k
10k100k1M
FREQUENCY – Hz
Figure 5. Large Signal Frequency
Response
30
20
10
OUTPUT VOLTAGE SWING – V p-p
0
10
1001k10k
LOAD RESISTANCE –
Figure 3. Output Voltage Swing
vs. Load Resistance