ANALOG DEVICES AD5696, AD5694 Service Manual

Quad, 16-/12-Bit nanoDAC+

V

Data Sheet

FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility 400 kHz I 4 I Low glitch: 0.5 nV-sec Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

2

C-compatible serial interface

C addresses available

LOGIC

SCL

SDA

A1

A0

with I2C Interface

AD5696/AD5694

FUNCTIONAL BLOCK DIAGRAM

DD

AD5696/AD5694

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INTERFACE L OGIC

INPUT

REGISTER

GND

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

POWER-ON

RESET

RSTSEL GAINLDAC RESET

Figure 1.

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN =

×1/×2

BUFFER

POWER-

DOWN LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

10799-001

GENERAL DESCRIPTION

The AD5696 and AD5694, members of the nanoDAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs. The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.

The AD5696/AD5694 incorporate a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The parts contain a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 μA at 3 V.

The AD5696/AD5694 use a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and include a V intended for 1.8 V/3 V/5 V logic.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

LOGIC

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit 14-Bit 12-Bit

SPI Internal AD5686R AD5685R AD5684R External AD5686 AD5684 I2C Internal AD5696R AD5695R AD5694R External AD5696 AD5694

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5696 (16-bit): ±2 LSB maximum AD5694 (12-bit): ±1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum

3. Two Pa ckage Opti ons .

3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP

AD5696/AD5694 Data Sheet

REVISION HISTORY

7/12—Revision 0: Initial Version

Serial Interface ............................................................................ 17

Write and Update Commands .................................................. 18

I2C Slave Address ........................................................................ 18

Serial Operation ......................................................................... 18

Write Operation.......................................................................... 18

Read Operation........................................................................... 19

Multiple DAC Readback Sequence .......................................... 19

Power-Down Operation ............................................................ 20

Load DAC (Hardware LDAC

Mask Register ................................................................. 21

Hardware Reset Pin (

Reset Select Pin (RSTSEL) ........................................................ 21

Applications Information .............................................................. 22

Microprocessor Interfacing ....................................................... 22

AD5696/AD5694 to ADSP-BF531 Interface .......................... 22

Layout Guidelines....................................................................... 22

Galvanically Isolated Interface ................................................. 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

LDAC

Pin) ........................................... 20

RESET

) ................................................... 21

Rev. 0 | Page 2 of 24

Data Sheet AD5696/AD5694

A Grade

B Grade

Total Unadjusted Error

±0.01

±0.25

±0.01

±0.1

% of FSR

Gain = 2

OUTPUT CHARACTERISTICS3

REF

10

10 nF

RL = 1 kΩ

REF

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; V

Table 2.

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1

STATIC PERFORMANCE2

AD5696

Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 LSB Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by

AD5694

Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by

Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of FSR All 1s loaded to DAC register Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

design

±0.25 ±0.2 % of FSR Gain = 1 Offset Error Drift3 Gain Temperature

Coefficient

DC Power Supply Rejection

Ratio

3

DC Crosstalk3

±1 ±1 µV/°C ±1 ±1 ppm Of FSR/°C

0.15 0.15 mV/V DAC code = midscale; V

DD

5 V ± 10%

±2 ±2 µV Due to single channel, full-

=

scale output change ±3 ±3 µV/mA Due to load current change ±2 ±2 µV Due to power-down (per

channel)

Output Voltage Range 0 V 0 2 × V

0 V

REF

0 2 × V

V Gain = 1

REF

V Gain = 2 (see Figure 20)

Capacitive Load Stability 2 2 nF RL = ∞

Resistive Load4 1 1 kΩ Load Regulation DAC code = midscale 80 80 µV/mA 5 V ± 10%; −30 mA ≤ I

OUT

≤

+30 mA

80 80 µV/mA 3 V ± 10%; −20 mA ≤ I

OUT

≤

+20 mA

Short-Circuit Current5 40 40 mA Load Impedance at Rails6 25 25 Ω See Figure 20 Power-Up Time 2.5 2.5 µs Coming out of power-down

DD

= 5 V

mode; V REFERENCE INPUT

Reference Current 90 90 µA V 180 180 µA V

= VDD = 5.5 V, gain = 1

= VDD = 5.5 V, gain = 2 Reference Input Range 1 VDD 1 VDD V Gain = 1 1 VDD/2 1 VDD/2 V Gain = 2 Reference Input Impedance 16 16 kΩ Gain = 2 32 32 kΩ Gain = 1

Rev. 0 | Page 3 of 24

AD5696/AD5694 Data Sheet

INH

LOGIC

SINK

LOGIC

SOUR CE

LOGIC

I

LOGIC

3 3 µA

A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1

LOGIC INPUTS3

Input Current ±2 ±2 µA Per pin Input Low Voltage, V

0.3 × V

INL

Input High Voltage, V Pin Capacitance 2 2 pF

LOGIC OUTPUTS (SDA)3

Output Low Voltage, VOL 0.4 0.4 V I Output High Voltage, VOH V Floating State Output

Capacitance

POWER REQUIREMENTS

V

1.8 5.5 1.8 5.5 V

VDD 2.7 5.5 2.7 5.5 V Gain = 1 V IDD VIH = VDD, VIL = GND, VDD =

Normal Mode7 0.59 0.7 0.59 0.7 mA All Power-Down Modes8 1 4 1 4 µA −40°C to +85°C

6 6 µA −40°C to +105°C

1

Temperature range is −40°C to +105°C.

2

DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when V

with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696) or 12 to 4080 (AD5694).

3

Guaranteed by design and characterization; not production tested.

4

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA

up to a junction temperature of 110°C.

5

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum junction temperature may impair device reliability.

6

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices.

For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 20).

7

Interface inactive. All DACs active. DAC outputs unloaded.

8

All DACs powered down.

0.3 × V

0.7 × V

LOGIC

0.7 × V

− 0.4 V

V

− 0.4 V I

LOGIC

4 4 pF

+ 1.5 5.5 V

REF

+ 1.5 5.5 V Gain = 2

REF

V

2.7 V to 5.5 V

= VDD with gain = 1 or when V

REF

= 3 mA

/2 = VDD

REF

Rev. 0 | Page 4 of 24

Data Sheet AD5696/AD5694

1, 2

OUT

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; V

Table 3.

Parameter

Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time ¼ to ¾ scale settling to ±2 LSB

AD5696 5 8 µs AD5694 5 7 µs

Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry transition Digital Feedthrough 0.13 nV-sec Multiplying Bandwidth 500 kHz Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At TA, BW = 20 kHz, VDD = 5 V, f Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz, gain = 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz Signal-to-Noise Ratio (SNR) 90 dB At TA, BW = 20 kHz, VDD = 5 V, f Spurious-Free Dynamic Range (SFDR) 83 dB At TA, BW = 20 kHz, VDD = 5 V, f Signal-to-Noise-and-Distortion Ratio

(SINAD)

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C; typical at 25°C.

4

Digitally generated sine wave at 1 kHz.

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

80 dB At TA, BW = 20 kHz, VDD = 5 V, f

= 1 kHz

= 1 kHz = 1 kHz = 1 kHz

OUT

Rev. 0 | Page 5 of 24

AD5696/AD5694 Data Sheet

1, 2

HIGH

LOW

HD, STA

SU ,DAT

6

3

HD ,DAT

SU, STA

SU,ST O

BUF

10

11

SP

6

B

SCL

SDA

t

1

t

3

LDAC

1

LDAC

2

START CONDITION

REPEATED START CONDITION

STOP CONDITION

NOTES

1

ASYNCHRONOUS LDAC UPDATE MO DE .

2

SYNCHRONOUS LDAC UPDATE MO DE .

t

4

t

6

t

5

t

7

t

8

t

2

t

13

t

4

t

11

t

10

t

12

t

12

t

9

10799-002

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.8 V ≤ V

Table 4.

Parameter

Min Max Unit Description

t1 2.5 µs SCL cycle time t2 0.6 µs t t3 1.3 µs t t4 0.6 µs t t5 100 ns t t

0 0.9 µs t t7 0.6 µs t t8 0.6 µs t t9 1.3 µs t

4

t

0 300 ns tR, rise time of SCL and SDA when receiving

4, 5

t

20 + 0.1CB 300 ns tF, fall time of SCL and SDA when transmitting/receiving t12 20 ns t13 400 ns SCL rising edge to t

0 50 ns Pulse width of suppressed spike

5

C

400 pF Capacitive load for each bus line

1

See Figure 2.

2

Guaranteed by design and characterization; not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL

falling edge.

4

tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

5

CB is the total capacitance of one bus line in pF.

6

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

Timing Diagram

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

, SCL high time

, SCL low time

, start/repeated start hold time , data setup time

, data hold time , repeated start setup time , stop condition setup time

, bus free time between a stop condition and a start condition

pulse width

LDAC

rising edge

LDAC

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. 0 | Page 6 of 24

Data Sheet AD5696/AD5694

LOGIC

OUT

REF

LOGIC

Operating Temperature Range

−40°C to +105°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to +7 V

V

to GND −0.3 V to VDD + 0.3 V

V

to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND1 −0.3 V to V SDA and SCL to GND −0.3 V to +7 V

Storage Temperature Range −65°C to +150°C Junction Temperature 125°C Reflow Soldering Peak Temperature,

Pb Free (J-STD-020)

ESD

Human Body Model (HBM) 3.5 kV Field-Induced Charged Device

Model (FICDM)

1

Excluding SDA and SCL.

260°C

1.5 kV

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND.

Table 6. Thermal Resistance

Package Type θJA Unit

16-Lead LFCSP 70 °C/W 16-Lead TSSOP 112.6 °C/W

ESD CAUTION

Rev. 0 | Page 7 of 24

AD5696/AD5694 Data Sheet

OUT

DD

REF

LOGIC

, the input register and the DAC register are updated with zero scale or midscale, depending

DD

REF

OUT

12 11 10

1

3 4

A1 SCL A0

9

V

LOGIC

V

OUT

A

V

DD

2

GND

V

OUT

C

6

SDA

5

V

OUT

D

7

LDAC

8

GAIN

16

V

OUT

B

15

V

REF

14

RSTSEL

13

RESET

AD5696/AD5694

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to S cale)

10799-006

1

2

3

4

5

6

7

8

V

OUT

B

V

OUT

A

GND

V

OUT

D

V

OUT

C

V

DD

V

REF

SDA

16

15

14

13

12

11

10

9

RESET A1 SCL

GAIN LDAC

V

LOGIC

A0

RSTSEL

TOP VIEW

(Not to S cale)

AD5696/

AD5694

10799-007

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration, 16-Lead LFCSP

Table 7. Pin Function Descriptions

Pin No.

LFCSP TSSOP

1 3 V

Mnemonic Description

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD Power Supply Input. The parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 V 5 7 V

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6 8 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the

24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the

supply with an external pull-up resistor. 7 9

LDAC

can be operated in two modes, asynchronous update mode and synchronous update mode.

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new

data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low. 8 10 GAIN Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to V

9 11 V

When this pin is tied to V

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

, all four DAC outputs have a span of 0 V to 2 × V

10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address. 11 13 SCL Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the

24-bit input shift register. 12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address. 13 15

Asynchronous Reset Input. The

RESET

RESET (low) on the state of the RSTSEL pin. When

14 16 RSTSEL Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.

15 1 V 16 2 V

When this pin is tied to V

Reference Input Voltage.

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

, all four DACs are powered up to midscale.

17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.

Rev. 0 | Page 8 of 24

Figure 4. Pin Configuration, 16-Lead TSSOP

input is falling edge sensitive. When

RESET

is low, all

pulses are ignored.

LDAC

.

RESET

.

REF

is activated

ANALOG DEVICES AD5696, AD5694 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS