Analog Devices AD5530 1 Datasheet

Serial Input, Voltage Output

a

FEATURES
Pin-Compatible 12- and 14-Bit DACs
Serial Input, Voltage Output
Maximum Output Voltage Range of ⴞ10 V
Data Readback
3-Wire Serial Interface
Clear Function to a User-Defined Voltage
Power-Down Function
Serial Data Output for Daisy-Chaining
16-Lead TSSOP Packages

APPLICATIONS
Industrial Automation
Automatic Test Equipment
Process Control
General-Purpose Instrumentation

12-/14-Bit DACs

AD5530/AD5531

GENERAL DESCRIPTION

The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.

They utilize a versatile 3-wire interface that is compatible with

™

SPI

, QSPI™, MICROWIRE™, and DSP interface standards.
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining pur­poses. Data readback allows the user to read the contents of the
DAC register via the SDO pin.

The DAC output is buffered by a gain of 2 amplifier and refer­enced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.

The AD5530 and AD5531 are available in 16-lead TSSOP
packages.

REFIN

REFAGND

LDAC

RBEN

SDIN

FUNCTIONAL BLOCK DIAGRAM

VSSV

DD

AD5530/AD5531

GND

R

–

+

DAC REGISTER

SHIFT REGISTER

SCLK

R

SYNC

12-/14-BIT DAC

SDO

POWER-DOWN

CONTROL LOGIC

+

–

R

R

V

OUT

DUTGND

CLR

PD

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(VDD = +15 V ±10%; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and

1

AD5530/AD5531–SPECIFICATIONS

CL = 220 pF to GND. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ±2LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic Over Temperature
Zero-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Gain Error ±1 ± 4 LSB typ
Gain Temperature Coefficient

2

0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max

REFERENCE INPUTS

2

Reference Input Range 0/5 0/5 V min/V max Max Output Range ±10 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ± 1 µA max Per Input. Typically ±20 nA.

DUTGND INPUT

2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range –4/+4 –4/+4 V min/V max Max Output Range ±10 V

O/P CHARACTERISTICS

2

Output Voltage Swing ±10 ±10 V max
Short Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 V max

INL

I

, Input Current ±10 ± 10 µA max Total for All Pins

INH

, Input Capacitance

C

IN

SDO VOL Output Low Voltage 0.4 0.4 V max I

2

10 10 pF max 3 pF Typ

= 1 mA

SINK

POWER REQUIREMENTS

VDD/V

SS

+15/–15 +15/–15 V nom ±10% For Specified Performance

Power Supply Sensitivity

∆Full Scale/∆V
∆Full Scale/∆V

I

DD

I

SS

DD

SS

110 110 dB typ
100 100 dB typ
2 2 mA max Outputs Unloaded
2 2 mA max Outputs Unloaded

IDD in Power-Down 150 150 µA max Typically 50 µA

NOTES

1

Temperature range for B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. 0–2–

SPECIFICATIONS

1

(VDD = +12 V ±10%; VSS = –12 V ±10%; GND = 0 V;

RL = 5 kΩ and CL = 220 pF to GND; TA = T

MIN

to T

, unless otherwise noted.)

MAX

AD5530/AD5531

Parameter AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ± 2LSB max
Differential Nonlinearity ±1 ± 1 LSB max Guaranteed Monotonic Over Temperature
Zero-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Gain Error ±1 ± 4 LSB typ
Gain Temperature Coefficient

2

0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max

REFERENCE INPUTS

2

Reference Input Range 0/4.096 0/4.096 V min/V max Max Output Range ±8.192 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ± 1 µA max Per Input. Typically ±20 nA.

DUTGND INPUT

2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range –3/+3 –3/+3 V min/V max Max Output Range ±8.192 V

O/P CHARACTERISTICS

2

Output Voltage Swing ±8.192 ±8.192 V max
Short Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

, Input Low Voltage 0.8 0.8 V max

V

INL

I

, Input Current ±10 ± 10 µA max Total for All Pins

INH

C

, Input Capacitance

IN

SDO VOL Output Low Voltage 0.4 0.4 V max I

2

10 10 pF max 3 pF Typ

= 1 mA

SINK

POWER REQUIREMENTS

VDD/V

SS

+12/–12 +12/–12 V nom ±10% For Specified Performance

Power Supply Sensitivity

∆Full Scale/∆V
∆Full Scale/∆V

I

DD

I

SS

DD

SS

110 110 dB typ
100 100 dB typ
2 2 mA max Outputs Unloaded
2 2 mA max Outputs Unloaded

IDD in Power-Down 150 150 µA max Typically 50 µA

NOTES

1

Temperature range for B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V; RL = 5 kΩ and

AC PERFORMANCE CHARACTERISTICS

CL = 220 pF to GND. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter A Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents

alternately loaded with all 0s and all 1s.

Slew Rate 1.3 V/µs typ
Digital-to-Analog Glitch Impulse 120 nV-s typ DAC Latch alternately loaded with 0FFF Hex and

1000 Hex. Not dependent on load conditions.
Digital Feedthrough 0.5 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density

@ 1 kHz 100 nV/(Hz)

Specifications subject to change without notice. Guaranteed by design, not subject to production test.

REV. 0

1/2

typ All 1s Loaded to DAC

–3–

AD5530/AD5531

L

STANDALONE TIMING CHARACTERISTICS

RL = 5 kΩ and CL = 220 pF to GND. All specifications T

Parameter Limit at T

f

MAX

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns

(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.

Specifications subject to change without notice.

SCLK

SYNC

SDIN

DAC*

CLR

*LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED

7 MHz max SCLK Frequency
140 ns min SCLK Cycle Time
60 ns min SCLK Low Time
60 ns min SCLK High Time
50 ns min SYNC to SCLK Falling Edge Setup Time
40 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Min SYNC High Time
40 ns min Data Setup Time
15 ns min Data Hold Time
5 ns min SYNC High to LDAC Low
50 ns min LDAC Pulsewidth
5 ns min LDAC High to SYNC Low
50 ns min CLR Pulsewidth

t

4

t

6

MSB LSB

DB15 DB14 DB11 DB0

MIN

, T

MAX

t7t

MIN

t

1

8

1, 2

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;

to T

, unless otherwise noted.)

MAX

Unit Description

t

5

t

3

t

2

t

9

t

11

t

10

t

12

Figure 1. Timing Diagram for Standalone Mode

REV. 0–4–

AD5530/AD5531

DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS

to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T

Parameter Limit at T

f

MAX

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

12

t

13

t

14

t

15

t

16

t

17

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns

(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.

3

SDO; R

Specifications subject to change without notice.

= 5 kΩ, CL = 15 pF.

PULLUP

2 MHz max SCLK Frequency
500 ns min SCLK Cycle Time
200 ns min SCLK Low Time
200 ns min SCLK High Time
50 ns min SYNC to SCLK Falling Edge Setup Time
40 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Min SYNC High Time
40 ns min Data Setup Time
15 ns min Data Hold Time
50 ns min CLR Pulsewidth
130 ns min SCLK Falling Edge to SDO Valid
50 ns max SCLK Falling Edge to SDO Invalid
50 ns min RBEN to SCLK Falling Edge Setup Time
50 ns min RBEN Hold Time
100 ns min RBEN Falling Edge to SDO Valid

MIN

, T

MAX

Unit Description

1, 2, 3

to T

MIN

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V

, unless otherwise noted.)

MAX

SCLK

SYNC

SDIN

SDO

(DAISY

CHAINING)

RBEN

SDO

(READBACK)

t

1

t

4

t

6

MSB

DB15 DB14 DB11

t7t

8

t

3

t

2

t

MSB LSB

DB15

14

DB11 DB0

t

15

t

17

MSB LSB

LSB

DB0

t

5

t

13

t

16

t

13

0

RB13 RB0

0

t

14

Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode

REV. 0

–5–