ANALOG DEVICES AD5501 Service Manual

with SPI Interface

AD5501

Rev. C Document Feedback

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POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SYNC

CLR

R_SEL DGND

V

LOGIC

V

DD

AGND

SCLK

SDI

SDO

V

OUT

V

FB

LDAC

ALARM

POWER-DOWN

CONTROL LOGIC

PRECISION

REFERENCE

TEMPERATURE

SENSOR

12-BIT

DAC

REF(+)

+

–

OUTPUT
BUFFER

122.36kΩ

1713kΩ

RESISTOR
NETWORK

AD5501

07992-001

Data Sheet

FEATURES

Single-channel high voltage DAC
12-bit resolution
Pin-selectable 30 V or 60 V output range
Integrated precision reference
Low power serial interface with readback capability
Integrated temperature sensor alarm function
Power-on reset
Wide operating temperature range: −40°C to +105°C

APPLICATIONS

Programmable voltage sources
High voltage LED drivers
Receiver bias in optical communications

12-Bit, High Voltage DAC

GENERAL DESCRIPTION

The AD5501 is a single-channel, 12-bit, serial input, digital-to­analog converter (DAC) with an on-chip high voltage output
amplifier and an integrated precision reference. The DAC output
voltage range is programmable via the range select pin (

R_SEL

If
R_SEL

is held high, the DAC output range is 0 V to 30 V. If

is held low, the DAC output range is 0 V to 60 V. The on
chip output amplifier allows an output swing within the range
of AGND + 0.5 V to V

− 0.5 V.

DD

The AD5501 has a high speed serial interface, which is compatible
with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface standards
and can handle clock speeds of up to 16.667 MHz.

R_SEL

).

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

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AD5501 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 4

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Power-Up State ........................................................................... 13

Power-Down Mode .................................................................... 13

DAC Channel Architecture ....................................................... 13

VFB Pin .......................................................................................... 13

Selecting the Output Range ...................................................... 14

CLR

Function.............................................................................. 14

LDAC

Function .......................................................................... 14

Temperature Sensor ................................................................... 14

Power Dissipation....................................................................... 14

Power Supply Sequencing ......................................................... 14

Serial Interface ................................................................................ 15

Writ e Mode ................................................................................. 15

Read Mode .................................................................................. 15

Writing to the Control Register ................................................ 15

Interfacing Examples ................................................................. 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

12/12—Rev. B to Rev. C

Changes to t

Changes to Figure 3 and Figure 4 ................................................... 7

Changes to Pin 2 Description, Table 7 and Pin 3 Description,

Tabl e 7 ................................................................................................ 9

Changes to Write Mode Section ................................................... 15

Changes to Table 10 ........................................................................ 16

Parameter, Table 4 .................................................... 6

4

4/12—Rev. A to Rev. B

Changes to Product Title .................................................................. 1

Changes to Figure 15 and Figure 16 ............................................ 13

10/10—Rev. 0 to Rev. A

Changes to Figure 3 and Figure 4 .................................................... 7

7/09—Revision 0: Initial Version

Rev. C | Page 2 of 20

Data Sheet AD5501

The serial interface offers the user the capability of both writing
to, and reading from, most internal registers.

To reduce power consumption at power up, only the digital
section of the AD5501 is powered up initially. This gives the
user the ability to program the DAC registers to the required
value while typically consuming only 30 μA of supply current.
The AD5501 incorporates power-on reset circuitry that ensures
the DAC registers power up in a known condition and remain
there until a valid write to the device has occurred. The analog
section is powered up by issuing a power-up command via the
SPI interface. The AD5501 provides software-selectable output
loads while in the power-down mode.

The AD5501 has on on-chip temperature sensor. If the tem­perature on the die exceeds 110°C, the
low CMOS output pin) flags an alarm and the AD5501 enters
a temperature power-down mode that disconnects the output
amplifier, thus removing the short-circuit condition. The AD5501
remains in power-down mode until a software power-up
command is executed.

The AD5501 is available in a compact 16-lead TSSOP. The AD5501
is guaranteed to operate over the extended temperature range of

−40°C to +105°C.

Table 1. Related Device

Part No. Description

AD5504 High Voltage, Quad Channel 12-Bit Voltage Output DAC

ALARM

pin (an active

Rev. C | Page 3 of 20

AD5501 Data Sheet

V

OUT

Temperature Coefficient

3, 4

50 ppm/°C

DAC code = half scale

ZSE

FSE

Feedback Resistance7

100 Ω

DIGITAL INPUTS

LOGIC

LOGIC

LOGIC

LOGIC

SOURCE

SINK

SPECIFICATIONS

VDD = 10 V to 62 V; V

Table 2.

Parameter Symbol Min Typ1 Max Unit Test Conditions/Comments

ACCURACY2

Resolution 12 Bits
Differential Nonlinearity DNL −1 +1 LSB
Integral Nonlinearity INL

60 V Mode −1 +1 LSB VDD = 62 V
30 V Mode −2 +2 LSB VDD = 62 V

Offset Error VOE −65 +100 mV
Offset Error Drift4 60 µV/°C
Zero-Scale Error V
Zero-Scale Error Drift4 50 µV/°C 60 V mode
Full-Scale Error V
Full-Scale Error Drift4 1 mV/°C −40°C to +25°C; 60 V mode
350 µV/°C +25°C to +105°C; 60 V mode
Gain Error −0.6 +0.6 % of FSR
Gain Temperature Coefficient4 10 ppm of FSR/°C

OUTPUT CHARACTERISTICS

Output Voltage Range5 AGND + 0.5 VDD − 0.5 V
Short-Circuit Current
Capacitive Load Stability4 1 V to 4 V step

RL = 60 kΩ to ∞ 1 nF

Load Current4 −1 +1 mA

= 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted.

LOG IC

80 mV

−325 +275 mV

4, 6

2 mA

DC Output Impedance4 3 Ω
DC Output Leakage4 10 µA

Input Logic High VIH 2.0 V V

1.8 V V
Input Logic Low VIL 0.8 V V
Input Current IIL ±1 µA
Input Capacitance4 IIC 5 pF

DIGITAL OUTPUTS

Output High Voltage VOH V

− 0.4 V V I
Output Low Voltage VOL DGND + 0.4 V V I
Three-State Leakage Current

SDI, SDO, SCLK,

R_SEL

Pin −10 +10 µA

ALARM

LDAC, CLR

Pins

,

−1 +1 µA

Output Capacitance4 5 pF

= 4.5 V to 5.5 V
= 2.3 V to 3.6 V
= 2.3 V to 5.5 V

= 200 µA

= 200 µA

Rev. C | Page 4 of 20

Data Sheet AD5501

LOGIC

LOGI C

LOGIC

DD_PWD

TOTAL

Parameter Symbol Min Typ1 Max Unit Test Conditions/Comments

POWER SUPPLIES

VDD 10 62 V
V

2.3 5.5 V

Quiescent Supply Current I

Logic Supply Current I
DC PSRR4

30 V mode 76 dB DAC output = full scale
60 V mode 68 dB DAC output = full scale

POWER-DOWN MODE

Supply Current I

Software Power-Down Mode 30 50 µA

Junction Temperature6 TJ 130 °C TJ = TA + P

1

Typical specifications represent average readings at 25°C, VDD = 62 V, and V

2

Valid in the output voltage range of (AGND + 0.5 V) to (VDD − 0.5 V). Output is unloaded.

3

Includes linearity, offset, and gain drift.

4

Guaranteed by design and characterization. Not production tested.

5

The DAC architecture gives a fixed linear voltage output range of 0 V to 30 V if

limited by output amplifier compliance, V

6

If the die temperature exceeds 110°C, the AD5501 enters a temperature power-down mode putting the DAC output into a high impedance state thereby removing

the short-circuit condition. Overheating caused by long term short-circuit condition(s) is detected by an integrated thermal sensor. After power-down, the AD5501
remains powered down until a software power-up command is executed.

7

Maximum resistance between V

OUT

should be set to at least 0.5 V higher than the maximum output voltage to ensure compliance.

DD

and VFB pins.

0.6 0.75 mA Static conditions; DAC output =

QUIESCENT

midscale

0.4 2 µA VIH = V

; VIL = DGND

× θJA

= 5 V.

LOGIC

R_SEL

is held high and 0 V to 60 V if

R_SEL

is held low. As the output voltage range is

AC CHARACTERISTICS

VDD = 10 V to 62 V; V

able 3.

T

Parameter

1, 2

AC CHARACTERISTICS

Output Voltage Settling Time ¼ to ¾ scale settling to ±1 LSB, RL = 60 kΩ

60 V Mode 45 55 µs

30 V Mode 25 35 µs
Slew Rate 0.65 V/µs
Digital-to-Analog Glitch Energy 300 nV-s 1 LSB change around major carry in 60 V mode
Glitch Impulse Peak Amplitude 170 mV 60 V mode
Digital Feedthrough 5 nV-s
Peak-to-Peak Noise 140 μV p-p 0.1 Hz to 10 Hz; DAC code = 0x800
4 mV p-p 0.1 Hz to 10 kHz; DAC code = 0x800

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to + 105°C, typical at 25°C.

= 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted.

LOG IC

Min Typ Max Unit Test Conditions/Comments3

Rev. C | Page 5 of 20

AD5501 Data Sheet

1

2

t6 5 ns min

Data hold time

15

16

t

17

4

50

μs max

Power-on-reset time (this is not shown in the timing figures)

18

5

V

OH

(MIN) – VOL (MAX)

2

200µA I

OL

200µA I

OH

TO OUTPUT

PIN

C

L

50pF

07992-002

TIMING CHARACTERISTICS

VDD = 30 V, V

Table 4.

Parameter Limit1 Unit Test Conditions/Comments

t

60 ns min SCLK cycle time
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 25 ns min
t5 15 ns min Data setup time

= 2.3 V to 5.5 V, and −40°C < TA < +105°C, all specifications T

LOG IC

falling edge to SCLK rising edge setup time

SYNC

MIN

to T

, unless otherwise noted.

MAX

t7 0 ns min SCLK falling edge to
t8 20 ns min Minimum
t9 20 ns min

pulse width low

LDAC

SYNC

high time

t10 50 ns min SCLK falling edge to
t11 15 ns min
t12 100 ns typ
t13 20 μs typ

pulse width low

CLR

pulse activation time

CLR

clear time

ALARM

SYNC

LDAC

rising edge

rising edge

t14 110 ns min SCLK cycle time in read mode

3

t

55 ns max SCLK rising edge to SDO valid

3

t

25 ns min SCLK to SDO Data hold time

t

50 μs max Power-on time (this is not shown in the timing figures)

t19 5 μs typ

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 16.667 MHz.

3

Under the load conditions that are outlined in Figure 2.

4

Time from when VDD or V

5

Time required from execution of power-on software command to when the DAC output has settled to 1 V.

supplies are powered-up to when a digital interface command can be executed.

LOGIC

clear to output amplifier turn on (this is not shown in the timing figures)

ALARM

Circuit and Timing Diagrams

Figure 2. Load Circuit for SDO Timing Diagram

Rev. C | Page 6 of 20