Ultralow Input Bias Current
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FEATURES
Ultralow input bias current
60 fA maximum (AD549L)
250 fA maximum (AD549J)
Input bias current guaranteed over the common-mode
voltage range
Low offset voltage
0.25 mV maximum (AD549K)
1.00 mV maximum (AD549J)
Low offset drift
5 μV/°C maximum (AD549K)
20 μV/°C maximum (AD549J)
Low power
700 μA maximum supply current
Low input voltage noise
4 μV p-p over 0.1 Hz to 10 Hz
MIL-STD-883B parts available
APPLICATIONS
Electrometer amplifier
Photodiode preamp
pH electrode buffer
Vacuum ion gauge measurement
Operational Amplifier
AD549
CONNECTION DIAGRAM
GUARD PIN,
CONNECTED
TO CASE
OFFSET NULL
INVERTING
INPUT
NONINVERTING
INPUT
1
2
3
1
Figure 1.
8
AD549
4
V–
10kΩ
VOS TRIM
V+
7
5
OFFSET
NULL
5
4
6
OUTPUT
–15V
00511-001
GENERAL DESCRIPTION
The AD5491 is a monolithic electrometer operational amplifier
with very low input bias current. Input offset voltage and input
offset voltage drift are laser trimmed for precision performance.
The ultralow input current of the part is achieved with Topgate™
JFET technology, a process development exclusive to Analog
Devices, Inc. This technology allows fabrication of extremely
low input current JFETs compatible with a standard junction
isolated bipolar process. The 10
which results from the bootstrapped input stage, ensures that
the input current is essentially independent of the commonmode voltage.
The AD549 is suited for applications requiring very low input
current and low input offset voltage. It excels as a preamp for a
wide variety of current output transducers, such as photodiodes,
photomultiplier tubes, or oxygen sensors. The AD549 can also
be used as a precision integrator or low droop sample-and-hold.
The AD549 is pin compatible with standard FET and electrometer
op amps, allowing designers to upgrade the performance of
present systems at little additional cost.
The AD549 is available in a TO-99 hermetic package. The case
is connected to Pin 8, thus, the metal case can be independently
1
Protected by U.S. Patent No. 4,639,683.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
15
Ω common-mode impedance,
connected to a point at the same potential as the input terminals,
minimizing stray leakage to the case. The AD549 is available in
four performance grades. The J, K, and L versions are rated over
the commercial temperature range of 0°C to +70°C. The S grade
is specified over the military temperature range of −55°C to +125°C
and is available processed to MIL-STD-883B, Rev. C. Extended
reliability plus screening is also available. Plus screening includes
168 hour burn-in, as well as other environmental and physical
tests derived from MIL-STD-883B, Rev. C.
PRODUCT HIGHLIGHTS
1. The AD549 input currents are specified, 100% tested, and
guaranteed after the device is warmed up. They are guaranteed over the entire common-mode input voltage range.
2. The AD549 input offset voltage and drift are laser trimmed
to 0.25 mV and 5 μV/°C (AD549K), and to 1 mV and
20 μV/°C (AD549J).
3. A maximum quiescent supply current of 700 μA minimizes
heating effects on input current and offset voltage.
4. AC specifications include 1 MHz unity-gain bandwidth
and 3 V/μs slew rate. Settling time for a 10 V input step is
5 μs to 0.01%.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
AD549
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description .................................................................. 10
Minimizing Input Current ........................................................ 10
Circuit Board Notes ................................................................... 10
REVISION HISTORY
3/08—Rev. G to Rev. H
Changes to Features .......................................................................... 1
Changes to Figure 1 .......................................................................... 1
Deleted Package Option Parameter ............................................... 4
Inserted ESD Caution ...................................................................... 5
Changes to Figure 2, Figure 3, and Figure 7.................................. 6
Changes to Figure 11 ........................................................................ 7
Changes to Figure 17 ........................................................................ 8
Changes to Figure 41 ...................................................................... 14
7/07—Rev. F to Rev. G
Changes to Figure 45 ...................................................................... 16
Changes to Temperature Compensated pH Probe
Amplifier Section ............................................................................ 17
Changes to Figure 46 ...................................................................... 17
Changes to Ordering Guide .......................................................... 18
Offset Nulling ............................................................................. 11
AC Response with High Value Source and Feedback
Resistance .................................................................................... 12
Common-Mode Input Voltage Overload ............................... 12
Differential Input Voltage Overload ........................................ 13
Input Protection ......................................................................... 13
Sample and Difference Circuit to Measure Electrometer
Leakage Currents ........................................................................ 13
Photodiode Interface ................................................................. 14
Log Ratio Amplifier ................................................................... 15
Temperature Compensated pH Probe Amplifier ................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
5/06—Rev. E to Rev. F
Removed ESD Caution ..................................................................... 5
8/05—Rev. D to Rev. E
Change to Figure 22 .......................................................................... 9
5/04—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features .......................................................................... 1
Updated Outline Dimensions ....................................................... 18
Added Ordering Guide .................................................................. 18
10/02—Rev. B to Rev. C
Deleted Product Highlights #5 ........................................................ 1
Edits to Specifications ....................................................................... 3
Deleted Metallization Photograph .................................................. 3
Updated Outline Dimensions ....................................................... 13
7/02—Rev. A to Rev. B
Edits to Specifications ....................................................................... 2
Rev. H | Page 2 of 20
AD549
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SPECIFICATIONS
@ 25°C and VS = ±15 V dc, unless otherwise noted; all minimum and maximum specifications are guaranteed; specifications in boldface
are tested on all production units at final electrical test, and results from those tests are used to calculate outgoing quality levels.
Table 1.
AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
INPUT BIAS CURRENT
Either Input, VCM = 0 V 150
Either Input, VCM = ±10 V 150 250 75 100 40 60 75 100 fA
Either Input at T
= 0 V
V
CM
Offset Current 50 30 20 30 fA
Offset Current at T
INPUT OFFSET VOLTAGE
Initial Offset 0.5
Offset at T
MAX
vs. Temperature 10
vs. Supply 32
vs. Supply, T
Long-Term Offset Stability 15 15 15 15 μV/month
INPUT VOLTAGE NOISE
f = 0.1 Hz to 10 Hz 4 4
f = 10 Hz 90 90 90 90 nV/√Hz
f = 100 Hz 60 60 60 60 nV/√Hz
f = 1 kHz 35 35 35 35 nV/√Hz
f = 10 kHz 35 35 35 35 nV/√Hz
INPUT CURRENT NOISE
f = 0.1 Hz to 10 Hz 0.7 0.5 0.36 0.5 fA rms
f = 1 kHz 0.22 0.16 0.11 0.16 fA/√Hz
INPUT IMPEDANCE
Differential
V
= ±1 1013||1 1013||1 1013||1 1013||1 Ω||pF
DIFF
Common Mode
VCM = ±10 V 1015||0.8 1015||0.8 1015||0.8 1015||0.8 Ω||pF
OPEN-LOOP GAIN
V
@ ±10 V, RL = 10 kΩ
OUT
V
@ ±10 V, RL = 10 kΩ,
OUT
to T
T
MIN
V
= ±10 V, RL = 2 kΩ
OUT
V
= ±10 V, RL = 2 kΩ,
OUT
to T
T
MIN
INPUT VOLTAGE RANGE
Differential
Common-Mode Voltage
Common-Mode Rejection
Ratio
−10 V ≤ VCM ≤ +10 V
T
to T
MIN
1
75
250
,
MAX
MAX
to T
MIN
MAX
MAX
MAX
3
±20 ±20 ±20 ±20 V
11 4.2 2.8 420 pA
2.2 1.3 0.85 125 pA
2
0.15
1.0
1.9
2
20
10
100
32
1000
300
800
300
250
100
200
80
−10
10
100
300
300
100
80
+10 −10
1000
800
250
200
40
100
0.3
0.25
0.4
5
5
10
32
10
32
4 4 μV p-p
6
1000
300
800
300
250
100
200
80
+10 −10
75
60
0.3
0.5
0.9
10
10
10
32
32
32
300
300
100
25
+10 −10
100
0.5
2.0
15
32
50
1000 V/mV
800 V/mV
250 V/mV
150 V/mV
+10
MAX
90
80
80
76
100
90
90
80
100
90
90
80
100 dB
90
90 dB
80
fA
mV
mV
μV/°C
μV/V
μV/V
V
Rev. H | Page 3 of 20
AD549
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AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
V
@ RL = 10 kΩ, T
OUT
T
MAX
V
@ RL = 2 kΩ, T
OUT
Short-Circuit Current
T
to T
MIN
MAX
Load Capacitance Stability,
G = +1
FREQUENCY RESPONSE
Unity Gain, Small Signal 0.7 1.0 0.7 1.0 0.7 1.0 0.7 1.0 MHz
Full Power Response 50 50 50 50 kHz
Slew Rate 2 3 2 3 2 3 2 3 V/μs
Settling Time, 0.1% 4.5 4.5 4.5 4.5 μs
Settling Time, 0.01% 5 5 5 5 μs
Overload Recovery, 50%
Overdrive, G = −1
POWER SUPPLY
Rated Performance ±15 ±15 ±15 ±15 V
Operating
Quiescent Current 0.60
TEMPERATURE RANGE
Operating, Rated
Performance
Storage −65 +150 −65 +150 −65 +150 −65 +150 °C
1
Bias current specifications are guaranteed after five minutes of operation at TA = 25°C. Bias current increases by a factor of 2.3 for every 10°C rise in temperature.
2
Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.
3
Defined as maximum continuous voltage between the inputs, such that neither input exceeds ±10 V from ground.
to
MIN
to T
MAX
MIN
−12
−10
20
15
9 9 6 mA
9
4000 4000 4000 4000 pF
2 2 2 2 μs
±5
0 70 0 70 0 70 −55 +125 °C
+12 −12
+10 −10
35 15
±18 ±5
0.70
20
0.60
+12 −12
+10 −10
35 15
±18 ±5
0.60
0.70
20
+12 −12
+10 −10
35 15
±18 ±5
0.60
0.70
20
+12
+10
35
±18
0.70
V
V
mA
V
mA
Rev. H | Page 4 of 20
AD549
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 500 mW
Input Voltage
Output Short-Circuit Duration Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
AD549J, AD549K, AD549L 0°C to +70°C
AD549S −55°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
1
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
1
±18 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. H | Page 5 of 20
AD549
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TYPICAL PERFORMANCE CHARACTERISTICS
20
800
15
V
IN+
10
V
INPUT VOLTAGE (V)
5
0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
IN–
Figure 2. Input Voltage Range vs. Supply Voltage
20
25°C
R
= 10kΩ
L
15
10
5
OUTPUT VO LTAGE SW ING (V)
0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
+V
Figure 3. Output Voltage Swing vs. Supply Voltage
OUT
–V
OUT
700
600
500
AMPLIFI ER QUIESCENT CURRENT (µA)
00511-002
400
0 5 10 15 20
SUPPLY VOLTAGE (±V)
00511-005
Figure 5. Quiescent Current vs. Supply Voltage
120
110
100
90
80
COMMON-MODE REJECTION RATIO (dB)
00511-003
70
–20 –10 0 10 20
INPUT COMMON-MODE VOLTAGE (V)
00511-006
Figure 6. CMRR vs. Input Common-Mode Voltage
30
25
20
15
10
5
OUTPUT VOLTAGE SWING (V p-p)
0
10 100 1k 10k 100k
LOAD RESIST ANCE (Ω)
VS = ±15V
Figure 4. Output Voltage Swing vs. Load Resistance
00511-004
3000
1000
300
OPEN-LOOP GAIN (V/mV)
100
0 5 10 15 20
SUPPLY VOLTAGE (±V)
Figure 7. Open-Loop Gain vs. Supply Voltage
Rev. H | Page 6 of 20
00511-007
AD549
www.BDTIC.com/ADI
3000
50
45
1000
300
OPEN-LOOP GAIN (V/mV)
100
–55 –25 5 35 65 95 125
TEMPERATURE (° C)
Figure 8. Open-Loop Gain vs. Temperature
30
25
20
I (µV)
15
OS
ΔIV
10
5
40
35
30
INPUT CURRENT (fA)
25
00511-008
20
0 5 10 15 20
POWER SUPPLY VOLTAGE (±V)
00511-011
Figure 11. Input Bias Current vs. Power Supply Voltage
160
140
120
100
80
60
40
NOISE SPECTRAL DENSITY (nV/ Hz)
0
01234567
WARM-UP TIME (Minutes)
Figure 9. Change in Offset Voltage vs. Warm-Up Time
50
45
40
35
30
INPUT CURRENT (fA)
25
20
–10 –5 0 5 10
COMMON-MODE VOLTAGE (V)
Figure 10. Input Bias Current vs. Common-Mode Voltage
00511-009
20
10 100 1k 10k
FREQUENCY (Hz)
00511-012
Figure 12. Input Voltage Noise Spectral Density
100k
WHENEVER JOHNSON NO ISE IS GREATER THAN
AMPLIFI ER NOISE, AMPLIFI ER NOISE CAN BE
CONSIDERED NEGLIGIBL E FOR THE APPLICATI ON
10k
1k
100
10
INPUT NOISE VOL TAGE (µV p-p)
1
00511-010
0.1
100k 1M 10M 100M 1G 10G 100G
RESISTOR
JOHNSON NOISE
AMPLIFI ER GENERATED NO ISE
SOURCE RESISTANCE (Ω)
1kHz BANDWIDTH
10Hz BANDWIDTH
00511-013
Figure 13. Noise vs. Source Resistance
Rev. H | Page 7 of 20
AD549
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100
100
120
80
60
40
20
0
OEPN-LOOP GAIN (dB)
–20
–40
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 14. Open-Loop Frequency Response
40
35
30
25
20
15
10
OUTPUT VO LTAGE SW ING (V)
5
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 15. Large Signal Frequency Response
80
60
40
20
0
–20
–40
100
80
+PSSR
60
40
–PSSR
PHASE MARGIN ( Degrees)
00511-014
20
0
POWER SUPPL Y REJECTIO N RATIO (d B)
–20
10 100 1k 10k 100k 10M1M
FREQUENCY (Hz)
00511-017
Figure 17. PSRR vs. Frequency Response
10
1mV
10mV
5mV
5mV
10mV
1mV
00511-018
5
5
0
–5
OUTPUT VO LTAGE SW ING (V)
00511-015
–10
01 324
SETTLING TIME (µs)
Figure 18. Output Voltage Swing and Error vs. Settling Time
100
80
60
40
20
0
COMMON-MO DE REJECTIO N RATIO (d B)
–20
10 100 1k 10k 100k 10M1M
FREQUENCY (Hz)
00511-016
Figure 16. CMRR vs. Frequency
Rev. H | Page 8 of 20
AD549
S
W
S
W
www.BDTIC.com/ADI
10kΩ
+V
S
10kΩ
2
3
7
AD549
4
–V
0.1µF
5
0.1µF
S
Figure 22. Unity-Gain Inverter
R
L
10kΩ
C
L
100pF
V
OUT
0511-022
V
QUARE
AVE
INPUT
+V
S
0.1µF
2
7
AD549
3
IN
5
4
0.1µF
–V
S
Figure 19. Unity-Gain Follower
R
L
10kΩ
C
L
100pF
V
V
OUT
00511-019
QUARE
INPUT
IN
AVE
5V
5µs
Figure 20. Unity-Gain Follower Large Signal Pulse Response
10mV
5V
5µs
0511-020
0511-023
Figure 23. Unity-Gain Inverter Large Signal Pulse Response
10mV
1µs
Figure 21. Unity-Gain Follower Small Signal Pulse Response
0511-021
Figure 24. Unity-Gain Inverter Small Signal Pulse Response
Rev. H | Page 9 of 20
1µs
0511-024
AD549
A
–
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FUNCTIONAL DESCRIPTION
MINIMIZING INPUT CURRENT
The AD549 is optimized for low input current and offset
voltage. Careful attention to how the amplifier is used reduces
input currents in actual applications.
Keep the amplifier operating temperature as low as possible to
minimize input current. Like other JFET input amplifiers, the
AD549 input current is sensitive to chip temperature, rising by
a factor of 2.3 for every 10°C. Figure 25 is a plot of the AD549
input current vs. ambient temperature.
1n
100pA
CIRCUIT BOARD NOTES
A number of physical phenomena generate spurious currents
that degrade the accuracy of low current measurements. Figure 27
is a schematic of a current to voltage (I-to-V) converter with
these parasitic currents modeled.
C
F
R
AD549
8
F
6
+
V
OUT
2
f
S
3
10pA
1pA
100fA
INPUT BIAS CURRENT
10fA
1fA
–55 –25 5 35 65 12595
TEMPERATURE (° C)
00511-025
Figure 25. Input Bias Current vs. Ambient Temperature
On-chip power dissipation raises the chip operating temperature, causing an increase in input bias current. Due to the low
quiescent supply current of the AD549, the chip temperature
is less than 3°C higher than its ambient temperature when the
(unloaded) amplifier is operating with 15 V supplies. The
difference in the input current is negligible.
However, heavy output loads can cause a significant increase in
chip temperature and a corresponding increase in the input
current. Maintaining a minimum load resistance of 10 Ω is
recommended. Input current vs. additional power dissipation
due to output drive current is plotted in Figure 26.
6
5
4
BASED ON
TYPICAL I
3
2
NORMALIZE D INPUT BIAS CURRENT
1
0 25 50 75 100 125 15 0 175 200
ADDITIONAL INTERNAL PO WER DISSI PATION (mW )
Figure 26. Input Bias Current vs. Additional Power Dissipation
= 40fA
B
00511-026
dC
V
P
dV
+V +
R
P
V
S
II' =
C
P
R
dT
P
C
P
dT
00511-027
Figure 27. Sources of Parasitic Leakage Currents
Finite resistance from input lines to voltages on the board,
modeled by Resistor R
resistance of more than 10
, results in parasitic leakage. Insulation
P
15
Ω must be maintained between
the amplifier signal and supply lines to capitalize on the low
input currents of the AD549. Standard PCB material does not
have high enough insulation resistance; therefore, connect the
input leads of the AD549 to standoffs made of insulating
material with adequate volume resistivity (that is, Teflon®). The
surface of the insulator must be kept clean to preserve surface
resistivity. For Teflon, an effective cleaning procedure consists
of swabbing the surface with high grade isopropyl alcohol,
rinsing with deionized water, and baking the board at 80°C for
10 minutes.
In addition to high volume and surface resistivity, other properties are desirable in the insulating material chosen. Resistance
to water absorption is important because surface water films
drastically reduce surface resistivity. The insulator chosen
should also exhibit minimal piezoelectric effects (charge
emission due to mechanical stress) and triboelectric effects
(charge generated by friction). Charge imbalances generated
by these mechanisms can appear as parasitic leakage currents.
These effects are modeled by Variable Capacitor C
Tabl e 3 lists various insulators and their properties.
in Figure 27.
P
1
Guarding the input lines by completely surrounding them with
a metal conductor biased near the potential of the input lines
has two major benefits. First, parasitic leakage from the signal
line is reduced because the voltage between the input line and
the guard is very low. Second, stray capacitance at the input
node is minimized. Input capacitance can substantially degrade
signal bandwidth and the stability of the I-to-V converter.
1
Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland,
Ohio, 1977.
Rev. H | Page 10 of 20
AD549
–
V
–
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The case of the AD549 is connected to Pin 8 so that it can be
bootstrapped near the input potential. This minimizes pin
leakage and input common-mode capacitance due to the case.
Guard schemes for inverting and noninverting amplifier
topologies are illustrated in Figure 28 and Figure 29.
C
F
GUARD
R
AD549
8
F
6
+
V
OUT
–
00511-028
2
I
N
3
Figure 28. Inverting Amplifier with Guard
GUARD
3
2
AD549
8
+
V
S
–
V
OUT
6
+
R
F
R
I
0511-029
–
Figure 29. Noninverting Amplifier with Guard
Other guidelines include keeping the circuit layout as compact
as possible and keeping the input lines short. Keeping the assembly
rigid and minimizing sources of vibration reduces triboelectric
and piezoelectric effects. All precision, high impedance circuitry
requires shielding against interference noise. Use low noise coaxial
or triaxial cables for remote connections to the input signal lines.
OFFSET NULLING
The AD549 input offset voltage can be nulled by using balance
Pin 1 and Pin 5, as shown in Figure 30. Nulling the input offset
voltage in this fashion introduces an added input offset voltage
drift component of 2.4 μV/°C per mV of nulled offset (a maximum additional drift of 0.6 μV/°C for the AD549K, 1.2 μV/°C
for the AD549L, and 2.4 μV/°C for the AD549J).
+
S
7
2
6
AD549
5
1
3
4
10kΩ
–V
S
Figure 30. Standard Offset Null Circuit
The approach in Figure 31 can be used when the amplifier is
used as an inverter. This method introduces a small voltage
referenced to the power supplies in series with the positive
input terminal of the amplifier. The amplifier input offset
voltage drift with temperature is not affected. However,
variation of the power supply voltages causes offset shifts.
R
I
2
+
V
I
–
Figure 31. Alternate Offset Null Circuit for Inverter
AD549
3
499kΩ 499kΩ
200Ω
0.1µF
+
V
OUT
00511-030
R
F
6
+
V
OUT
+V
S
100kΩ
–V
S
00511-031
Table 3. Insulating Materials and Characteristics
Material
Volume Resistivity
(V to CM)
Minimal
Triboelectric Effect
1
Minimal
Piezoelectric Effect
1
Resistance to
Water Absorption
1
Tef lon 1017 to 1018 W W G
Kel-F® 1017 to 1018 W M G
Sapphire 1016 to 1018 M G G
Polyethylene 1014 to 1018 M G M
Polystyrene 1012 to 1018 W M M
Ceramic 1012 to 1014 W M W
Glass Epoxy 1010 to 1017 W M W
PVC 1010 to 1015 G M G
Phenolic 105 to 1012 W G W
1
G: good with regard to property; M: moderate with regard to property; W: weak with regard to property.
Rev. H | Page 11 of 20
AD549
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AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE
Source and feedback resistances greater than 100 kΩ magnify
the effect of the input capacitances (stray and inherent to
the AD549) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account because the circuit bandwidth and stability
can be adversely affected.
In an inverting configuration, the differential input capacitance
forms a pole in the loop transmission of the circuit. This can
create peaking in the ac response and possible instability. A
feedback capacitance can be used to stabilize the circuit. The
inverter pulse response with R
and RS equal to 1 MΩ appears
F
in Figure 34. Figure 35 shows the response of the same circuit
with a 1 pF feedback capacitance. Typical differential input
capacitance for the AD549 is 1 pF.
10mV
Figure 32. Follower Pulse Response from 1 MΩ Source Resistance,
Case Not Bootstrapped
5µs
10mV
5µs
10mV
0511-032
Figure 34. Inverter Pulse Response with 1 MΩ Source
and Feedback Resistance
5µs
0511-034
10mV
5µs
0511-033
Figure 33. Follower Pulse Response from 1 MΩ Source Resistance,
Case Bootstrapped
In a follower, the source resistance and input common-mode
capacitance form a pole that limits the bandwidth to ½πR
SCS
.
Bootstrapping the metal case by connecting Pin 8 to the output
minimizes capacitance due to the package. Figure 32 and Figure 33
show the follower pulse response from a 1 MΩ source resistance
with and without the package connected to the output. Typical
common-mode input capacitance for the AD549 is 0.8 pF.
COMMON-MODE INPUT VOLTAGE OVERLOAD
The rated common-mode input voltage range of the AD549 is
from 3 V less than the positive supply voltage to 5 V greater than
the negative supply voltage. Exceeding this range degrades the
CMRR of the amplifier. Driving the common-mode voltage above
the positive supply causes the amplifier output to saturate at the
upper limit of the output voltage. Recovery time is typically 2 μs
Figure 35. Inverter Pulse Response with 1 MΩ Source
and Feedback Resistance, 1 pF Feedback Capacitance
after the input has been returned to within the normal operating
range. Driving the input common-mode voltage within 1 V of the
negative supply causes phase reversal of the output signal. In this
case, normal operation typically resumes within 0.5 μs of the
input voltage returning within range.
Rev. H | Page 12 of 20
0511-035
AD549
www.BDTIC.com/ADI
DIFFERENTIAL INPUT VOLTAGE OVERLOAD
A plot of the AD549 input currents vs. differential input
− V
voltage (defined as V
IN+
) appears in Figure 36. The
IN−
input current at either terminal stays below a few hundred
femtoamps until one input terminal is forced higher than 1 V
to 1.5 V above the other terminal. Under these conditions, the
input current limits at 30 μA.
100µ
10µ
1µ
100n
10n
1n
100p
10p
INPUT CURRENT (A)
1p
100f
10f
–5 –4 –3 –2 –1 0 1 2 3 4 5
Figure 36. Input Current vs. Differential Input Voltage
IIN–I
DIFFERENTIAL INPUT VOLTAGE (V) (VIN+ – VIN–)
+
IN
00511-036
INPUT PROTECTION
The AD549 safely handles any input voltage within the supply
voltage range. Subjecting the input terminals to voltages beyond
the power supply can destroy the device or cause shifts in input
current or offset voltage if the amplifier is not protected.
A protection scheme for the amplifier as an inverter is shown
in Figure 37. R
inverting input to 1 mA for expected transient (less than 1 sec)
overvoltage conditions, or to 100 μA for a continuous overload.
Because R
value than the amplifier input resistance, it does not affect the
dc gain of the inverter. However, the Johnson noise of the
resistor adds root sum of squares to the amplifier input noise.
In the corresponding version of this scheme for a follower,
shown in Figure 38, R
terminal produce a pole in the signal frequency response at a
f = ½πRC. Again, the Johnson noise, R
voltage noise of the amplifier.
is chosen to limit the current through the
P
is inside the feedback loop and is much lower in
P
R
F
R
PROTECT
SOURCE
Figure 37. Inverter with Input Current Limit
and the capacitance at the positive input
P
C
F
2
AD549
3
, adds to the input
P
6
00511-037
R
PROTECT
SOURCE
Figure 38. Follower with Input Current Limit
3
AD549
2
6
00511-038
Figure 39 is a schematic of the AD549 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Use low leakage diodes,
such as the FD333s, and shield them from light to prevent photocurrents from being generated. Even with these precautions, the
diodes measurably increase input current and capacitance.
R
AD549
F
6
0511-039
SOURCE
PROTECT
DIODES
Figure 39. Input Voltage Clamp with Diodes
2
3
SAMPLE-AND-DIFFERENCE CIRCUIT TO MEASURE ELECTROMETER LEAKAGE CURRENTS
There are a number of methods used to test electrometer leakage
currents, including current integration and direct I-to-V conversion. Regardless of the method used, board and interconnect
cleanliness, proper choice of insulating materials (such as Teflon
or Kel-F), correct guarding and shielding techniques, and care
in physical layout are essential to making accurate leakage
measurements.
Figure 40 is a schematic of the sample-and-difference circuit. It
uses two AD549 electrometer amplifiers (A and B) as I-to-V
converters with high value (10
RSb). R1 and R2 provide for an overall circuit sensitivity of
10 fA/mV (10 pA full scale). C
and loop compensation. C
capacitor. An ultralow leakage Kel-F test socket is used for contacting the device under test. Rigid Teflon coaxial cable is used
to make connections to all high impedance nodes. The use of
rigid coaxial cable affords immunity to error induced by mechanical vibration and provides an outer conductor for shielding. The
entire circuit is enclosed in a grounded metal box.
10
Ω) sense resistors (RSa and
and CF provide noise suppression
C
should be a low leakage polystyrene
C
Rev. H | Page 13 of 20
AD549
T
www.BDTIC.com/ADI
The test apparatus is calibrated without a device under test
present. After power is turned on, a 5 minute stabilization
period is required. First, V
voltages are the errors caused by the offset voltages and leakage
currents of the I-to-V converters.
V
= 10 (VOSA – IBA × RSa)
ERR1
= 10 (VOSB – IBB × RSb)
V
ERR2
I (+)
–
V
OS
DEVICE
UNDER
+
TEST
I (–)
Figure 40. Sample and Difference Circuit for Measuring
Electrometer Leakage Currents
Once measured, these errors are subtracted from the readings
taken with a device under test present. Amplifier B closes the
feedback loop to the device under testing in addition to providing the I-to-V conversion. The offset error of the device
under testing appears as a common-mode signal and does not
affect the test measurement. As a result, only the leakage
current of the device under testing is measured.
V
– V
A
V
X
= 10[RSa × IB(+)]
ERR1
– V
= 10[RSb × IB(–)]
ERR2
9.01kΩ
1kΩ
R2
R1
ERR1
and V
C
C
20pF
RSa
10
10
2
3
3
2
C
C
20pF
RSb
10
10
are measured. These
ERR2
C
F
0.1µF
R2
9.01kΩ
Ω
R1
1kΩ
A
AD549
AD549
Ω
6
8
GUARD
C
F
0.1µF
8
B
6
C
F
0.1µF
R2
9.01kΩ
R1
1kΩ
V
ERR1/VA
V
OUT
V
ERR2/VB
CAL/TEST
+
–
–
+
00511-040
Although a series of devices can be tested after only one calibration measurement, calibration should be updated periodically
to compensate for any thermal drift of the I-to-V converters or
changes in the ambient environment. Laboratory results have
shown that repeatable measurements within 10 fA can be realized
when this apparatus is properly implemented. These results are
achieved in part by the design of the circuit, which eliminates
relays and other parasitic leakage paths in the high impedance
signal lines, and in part by the inherent cancellation of errors
through the calibration and measurement procedure.
PHOTODIODE INTERFACE
The low input current and low input offset voltage of the AD549
make it an excellent choice for very sensitive photodiode preamps
(see Figure 41). The photodiode develops a signal current, I
equal to
I
= R × P
S
where P is light power incident on the diode surface, in watts,
and R is the photodiode responsivity in amps/watt. R
the signal current to an output voltage
V
= RF × IS
OUT
R
F
109Ω
C
F
10pF
2
I
S
AD549
3
4
–V
S
6
5
1
10kΩ
1µF
+
V
OU
–
Figure 41. Photodiode Preamp
The dc error sources and an equivalent circuit for a small area
(0.2 mm square) photodiode are indicated in Figure 42.
R
F
109Ω
C
F
10pF
C
R
S
S
S
109Ω
20pF
Figure 42. Photodiode Preamp DC Error Sources
IS–I
V
OS
A
+–
S
converts
F
00511-041
+
V
OUT
–
,
00511-042
Rev. H | Page 14 of 20
AD549
www.BDTIC.com/ADI
Input current, I
, contributes an output voltage error, VE1,
B
proportional to the feedback resistance
V
= IB × RF
E1
The input voltage offset of the op amp causes an error current
through the photodiode shunt resistance, R
I = V
OS/RS
S
The error current results in an error voltage (VE2) at the
amplifier output equal to
V
= (1 + RF/RS)V
E2
OS
Given typical values of photodiode shunt resistance (on the order
9
Ω), RF/RS can easily be greater than 1, especially if a large
of 10
feedback resistance is used. Also, R
increases with tempera-
F/RS
ture because photodiode shunt resistance typically drops by a
factor of 2 for every 10°C rise in temperature. An op amp with
low offset voltage and low drift must be used to maintain accuracy.
The AD549K offers a guaranteed maximum 0.25 mV offset
voltage and 5 mV/°C drift for very sensitive applications.
Photodiode Preamp Noise
Noise limits the signal resolution obtainable with the preamp.
The output voltage noise divided by the feedback resistance is
the minimum current signal that can be detected. This minimum detectable current divided by the responsivity of the
photodiode represents the lowest light power that is detectable
by the preamp.
Noise sources associated with the photodiode, amplifier, and
feedback resistance are shown in Figure 43; Figure 44 is the
spectral density vs. frequency plot of the contribution of each of
the noise sources to the output voltage noise (circuit parameters
in Figure 42 are assumed). The rms contribution of each noise
source to the total output voltage noise is obtained by
integrating the square of its spectral density function over
frequency. The rms value of the output voltage noise is the
square root of the sum of all contributions. Minimizing the total
area under these curves optimizes the resolution of the
preamplifier for a given bandwidth.
IF
R
F
C
F
I
R
S
S
Figure 43. Photodiode Preamp Noise Sources
IN
C
S
EN
A
00511-043
The photodiode preamp in Figure 41 can detect a signal current
of 26 fA rms at a bandwidth of 16 Hz, which, assuming a
photodiode responsivity of 0.5 A/W, translates to a 52 fW rms
minimum detectable power. The photodiode used has a high
source resistance and low junction capacitance. C
signal bandwidth with R
and also limits the peak in the noise
F
sets the
F
gain that multiplies the op amp input voltage noise contribution. A single-pole filter at the output of the amplifier limits the
op amp output voltage noise bandwidth to 26 Hz, comparable
to the signal bandwidth. This greatly improves the signal-tonoise ratio of the preamplifier (in this case, by a factor of 3).
10µ
1µ
100n
VOLTAGE NOISE CONTRI BUTIONS
NOISE SPECTRAL DENSITY (nV/ Hz)
EN
CONTRIBUTI ON,
WITH FILTER
10n
1 10 100 1k 10k 100k 1M
Figure 44. Spectral Density of the Photodiode Preamp Noise
IF AND CS, NO F ILTERS
IF AND CS, WITH FILTERS
AD549
OPEN-LOOP GAIN
FREQUENCY (Hz)
Sources vs. Frequency
EN CONTRIBUTI ON,
NO FIL TER
00511-044
LOG RATIO AMPLIFIER
Logarithmic ratio circuits are useful for processing signals with
wide dynamic range. The 60 fA maximum input current of the
AD549L makes it possible to build a log ratio amplifier with
1% log conformance for input currents ranging from 10 pA to
1 mA, a dynamic range of 160 dB.
The log ratio amplifier in Figure 45 provides an output voltage
proportional to the log base 10 of the ratio of Input Current I
and Input Current I
. Resistor R1 and Resistor R2 are provided
2
for voltage inputs. Because NPN devices are used in the feedback
loop of the front-end amplifiers that provide the log transfer
function, the output is valid only for positive input voltages and
input currents. The input currents set the Collector Current IC1
and Collector Current IC2 of a matched pair of log transistors,
Q1 and Q2, to develop Voltage V
, VB = –(kT/q)ln IC/IES
V
A
and Voltage VB
A
where IES is the saturation current of the transistor.
The difference of V
and VB is taken by the subtractor section to
A
obtain
V
= (kT/q)ln(IC2/IC1)
C
V
is scaled up by the ratio of (R9 + R10)/R8, which is equal to
C
approximately 16 at room temperature, resulting in the output
voltage
= 1 V × log(IC2/IC1)
V
OUT
R8 is a resistor with a positive 3500 ppm/°C temperature coefficient to provide the necessary temperature compensation. The
parallel combination of R15 and R7 is provided to keep the gain
of the subtractor section for positive and negative inputs matched
over temperature.
1
Rev. H | Page 15 of 20
AD549
R
V
V
www.BDTIC.com/ADI
Frequency compensation is provided by R11, R12, C1, and C2.
The bandwidth of the circuit is 300 kHz at input signals greater
than 50 μA; bandwidth decreases smoothly with decreasing
signal levels.
To trim the circuit, set the input currents to 10 μA and trim the
A3 offset using the trim potentiometer of the amplifier for the
output to equal 0. Next, set I
equal 1 V by trimming R10. Additional offset trims on Amplifier A1 and Amplifier A2 can be used to increase the voltage
input accuracy and dynamic range.
The very low input current of the AD549 makes this circuit
useful over a very wide range of signal currents. The total input
current (which determines the low level accuracy of the circuit)
is the sum of the amplifier input current, the leakage across the
compensating capacitor (negligible if a polystyrene or Teflon
capacitor is used), and the collector-to-collector and collectorto-base leakages of one side of the dual log transistors. The
magnitudes of these last two leakages depend on the amplifier
input offset voltage and are typically less than 10 fA with 1 mV
offsets. The low level accuracy is limited primarily by the
amplifier input current, only 60 fA maximum when the
AD549L is used.
The effects of the emitter resistance of Q1 and Q2 can degrade
circuit accuracy at input currents above 100 μA. The networks
to 1 μA and adjust the output to
1
10kΩ
V
I1 IN
IN
1
R1
10kΩ
3
2
100pF
4
AD549
C1
A1
Q1
1
OFFSET
1
5
6
A
composed of R13, D1, R16, R14, D2, and R17 compensate for
these errors, so that this circuit has less than a 1% log conformance error at 1 mA input currents. The correct value for R13
and R14 depends on the type of log transistors used. The 49.9 kΩ
resistors were chosen for use with LM394 transistors. Smaller
resistance values are needed for smaller log transistors.
TEMPERATURE COMPENSATED pH PROBE AMPLIFIER
A pH probe can be modeled as an mV-level voltage source
with a series source resistance dependent on the electrode
composition and configuration. The glass bulb resistance of a
typical pH electrode pair falls between 10
therefore important to select an amplifier with low enough
input currents such that the voltage drop produced by the
amplifier input bias current and the electrode resistance does
not become an appreciable percentage of a pH unit.
The circuit in Figure 46 illustrates the use of the AD549 as a pH
probe amplifier. As with other electrometer applications, the use of
guarding, shielding, and Teflon standoffs is necessary to capitalize
on the AD549 low input current. If an AD549L (60 fA maximum
input current) is used, the error contributed by the input current is
held below 60 μV for pH electrode source impedances up to 10
Input offset voltages (which can be trimmed) are below 0.5 mV.
FOR EACH AMPLI FIE
PIN 7
D3
PIN 4
Q1, Q2 = LM394
DUAL LOG T RANSISTORS
R11
4.99kΩ
R3
20kΩ
R5
20kΩ
0.1µF
0.1µF
R15
1kΩ
R7
15kΩ
6
Ω and 109 Ω. It is
9
Ω.
+V
S
–V
S
*
IN
2
I2 IN
R2
10kΩ
R14
49.9kΩ
D2
100pF
2
3
Q2
C2
A2
AD549
1
4
R16
10Ω
R17
10Ω
B
5
10kΩ
V
2
OFFSET
D1
R13
49.9kΩ
6
3
A3
AD549
2
4
R4
20kΩ
4.99kΩ
D4
R6
20kΩ
D1, D4 1N4148 DIODES
R8, R15 1kΩ + 350 ppm/°C TC RESISTOR
*
TELLAB QB1 OR PRECISION RESISTOR PT146
ALL OTHER RESISTORS ARE 1% METAL FILM
1
*
6
5
10kΩ
OUTPUT
OFFSET
R8
1kΩ
R10
2kΩ
R9
14.3kΩ
V
OUT
V
OUT
= 1V ×
= 1V ×
V
OUT
SCALE
FACTOR
ADJ
LOG
10
LOG
10
Figure 45. Log Ratio Amplifier
Rev. H | Page 16 of 20
V
2
V
1
I
2
I
1
00511-045
AD549
V
www.BDTIC.com/ADI
The pH probe output is ideally 0 V at a pH of 7, independent
of temperature. The slope of the transfer function of the probe,
though predictable, is temperature dependent (−54.2 mV/pH at
0°C and −74.04 mV/pH at 100°C). By using an AD590 temperature sensor and an AD534 analog divider, an accurate temperature
compensation network can be added to the basic pH probe amplifier. Tabl e 4 shows voltages at various points, thereby illustrating
pH
PROBE
OUTPUT
(A)
3
7
AD549
4
2
8
12kΩ
1kΩ
SCALE FACTOR
ADJUST
AD590
IN STAINLE SS
STEEL PROBE
OR AC2626
+
–
Figure 46. Temperature Compensated pH Amplifier
0.1µF
0.1µF
1kΩ
the compensation. The AD549 is set for a noninverting gain of
13.51. The output of the AD590 circuitry (Point C) is equal to
10 V at 100°C and decreases by 26.8 mV/°C. The output of the
AD534 analog divider (Point D) is a temperature-compensated
output voltage centered at 0 V for a pH of 7 and has a transfer
function of –1.00 V/pH unit. The output range spans from
−7.00 V (pH = 14) to +7.00 V (pH = 0).
+15
0.1µF
14
10
11
1
2
AD534
Z
2
Z
1
X
1
X
2
–15V
OUT
8
0.1µF
6
(B)
(C)
+15V
26.6kΩ
(D)
12
Y
7
2
Y
6
1
OUTPUT
00511-046
Table 4. Illustration of Temperature Compensation
Point
Probe Temperature (°C) A (Probe Output) (mV) B (A × 13.51) (V) C (AD590 Output) (V) D (10 × (B ÷ C)) (V)
0 54.20 0.732 7.32 1.00
25 59.16 0.799 7.99 1.00
37 61.54 0.831 8.31 1.00
60 66.10 0.893 8.93 1.00
100 74.04 1.000 10.00 1.00
Rev. H | Page 17 of 20
AD549
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
REFERENCE PLANE
0.5000 (12.70)
0.1850 (4.70)
0.1650 (4.19)
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
0.0400 (1.02) M AX
0.0400 (1.02)
0.0100 (0.25)
CONTROLL ING DIMENSIONS ARE IN INCHES; MIL LIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF INCH EQ UIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
MIN
0.2500 (6.35) MIN
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
BASE & SEATING PLANE
COMPLIANT TO JE DEC STANDARDS MO-002-AK
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.1000 (2.54)
BSC
5
4
3
2
1
0.0340 (0.86)
0.0280 (0.71)
45° BSC
Figure 47. 8-Lead Metal Can [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
0.1600 (4.06)
0.1400 (3.56)
6
7
8
0.0450 (1.14)
0.0270 (0.69)
022306-A
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD549JH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549JHZ
AD549KH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549KHZ
AD549LH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549LHZ
AD549SH/883B −55°C to +125°C 8-Lead Metal Can (TO-99) H-08
1
Z = RoHS Compliant Part.
1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
1
0°C to +70°C 8-Lead Metal Can (TO-99) H-08
Rev. H | Page 18 of 20
AD549
www.BDTIC.com/ADI
NOTES
Rev. H | Page 19 of 20
AD549
www.BDTIC.com/ADI
NOTES
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00511-0-3/08(H)
Rev. H | Page 20 of 20
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