ANALOG DEVICES AD5453 Service Manual

8-/10-/12-/14-Bit High Bandwidth

Data Sheet

FEATURES

12 MHz multiplying bandwidth
INL of ±0.25 LSB at 8-bit
8-lead TSOT and MSOP packages

2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface

2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 μA typical current consumption
Guaranteed monotonic
Qualified for automotive applications

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming

Multiplying DACs with Serial Interface

AD5450/AD5451/AD5452/AD5453

FUNCTIONAL BLOCK DIAGRAM

V

DDVREF

R

FB

AD5450/

SYNC
SCLK

SDIN

AD5451/
AD5452/
AD5453

POWER-ON

RESET

8-/10-/12-/14-BIT REF

R-2R DAC

DAC REGISTER

INPUT LATCH

CONTROL LOGIC
AND INPUT SHIFT

REGISTER

GND

Figure 1.

R

I

1

OUT

04587-001

GENERAL DESCRIPTION

The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/
14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including battery­powered applications.

As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.

These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.

1

U.S. Patent Number 5,689,257.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The applied external reference input voltage (V

) determines

REF

the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(R

) provides temperature tracking and full-scale voltage

FB

output when combined with an external current-to-voltage
precision amplifier.

The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages. The AD5453 also comes in 8-lead LFCSP.

The EVAL-AD5443SDZ/EVAL-AD5446SDZ/EVAL­AD5453SDZ evaluation board is available for evaluating DAC
performance. For more information, see the UG-327 evaluation
board user guide.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

AD5450/AD5451/AD5452/AD5453 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

DAC Section................................................................................ 16

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 15

General Description ....................................................................... 16

REVISION HISTORY

4/12—Rev. E to Rev. F

Changes to General Description Section ...................................... 1

Deleted Evaluation Board for the DAC Section, Power Supplies
for the Evaluation Board Section, and Figure 64;

Renumbered Sequentially.............................................................. 25

Deleted Figure 65 and Figure 66................................................... 26

Deleted Figure 67............................................................................ 27

Changes to Ordering Guide.......................................................... 27

3/11—Rev. D to Rev. E

Changes to

Added Figure 54 (Renumbered Sequentially) ............................ 21

Added Figure 55 and Table 11 ..................................................... 22

2/11—Rev. C to Rev. D

Added 8-Lead LFCSP.........................................................Universal

Changes to Features Section............................................................ 1

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

Added Automotive Products Section .......................................... 28

Function Section ............................................ 21

SYNC

Circuit Operation....................................................................... 16

Single-Supply Applications....................................................... 18

Adding Gain................................................................................ 18

Divider or Programmable Gain Element................................ 19

Reference Selection .................................................................... 19

Amplifier Selection .................................................................... 19

Serial Interface............................................................................ 21

Microprocessor Interfacing....................................................... 22

PCB Layout and Power Supply Decoupling ........................... 24

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

Automotive Products................................................................. 27

1/10—Rev. B to Rev. C

Changes to DAC Control Bits C1, C0.......................................... 21

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

3/06—Rev. A to Rev. B

Updated Format.................................................................. Universal

Changes to Features ..........................................................................1

Changes to General Description .....................................................1

Changes to Specifications.................................................................4

Changes to Figure 27 and Figure 28............................................. 11

Change to Table 9 ........................................................................... 20

Changes to Table 12 ....................................................................... 26

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

7/05—Rev. 0 to Rev. A

Added AD5453 ...................................................................Universal

Changes to Specifications.................................................................4

Change to Figure 21....................................................................... 10

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

1/05—Revision 0: Initial Version

Rev. F | Page 2 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

AD5450

Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB

AD5451

Resolution 10 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB

AD5452

Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Total Unadjusted Error ±1 LSB
Gain Error ±0.5 LSB

AD5453

Resolution 14 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Total Unadjusted Error ±4 LSB

Gain Error ±2.5 LSB
Gain Error Temperature Coefficient1 ±2 ppm FSR/°C
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I
±10 nA Data = 0x0000, TA = −40°C to +125°C, I

REFERENCE INPUT1

Reference Input Range ±10 V
V

Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C

REF

RFB Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
Input Capacitance

Zero-Scale Code 18 22 pF

Full-Scale Code 18 22 pF

DIGITAL INPUTS/OUTPUTS1

Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL ±1 nA TA = 25°C
±10 nA TA = −40°C to +125°C
Input Capacitance 10 pF

= 10 V. Temperature range for Y version: −40°C to +125°C. All specifications T

REF

− 0.5 V VDD = 2.5 V to 3.6 V, I

DD

MIN

to T

MAX

= 200 μA

SOURCE

SOURCE

= 200 μA

SINK

= 200 μA

SINK

, unless otherwise

1

OUT

OUT

= 200 μA

1

Rev. F | Page 3 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet

Parameter Min Typ Max Unit Test Conditions

DYNAMIC PERFORMANCE1

Reference-Multiplying BW 12 MHz V
Multiplying Feedthrough Error V
72 dB 100 kHz
64 dB 1 MHz
44 dB 10 MHz
Output Voltage Settling Time

Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns

Measured to ±16 mV of FS 16 33 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 10 30 ns Rise and fall times, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Output Capacitance

I

1 13 pF DAC latches loaded with all 0s

OUT

28 pF DAC latches loaded with all 1s

I

2 18 pF DAC latches loaded with all 0s

OUT

5 pF DAC latches loaded with all 1s

Digital Feedthrough 0.5 nV-s

Analog THD 83 dB V
Digital THD Clock = 1 MHz, V

50 kHz f

20 kHz f
Output Noise Spectral Density
SFDR Performance (Wide Band)

50 kHz f

20 kHz f
SFDR Performance (Narrow Band)

50 kHz f

20 kHz f
Intermodulation Distortion

POWER REQUIREMENTS

Power Supply Range 2.5

I

DD

Power Supply Sensitivity1

1

Guaranteed by design and characterization, not subject to production test.

71 dB

OUT

77 dB

OUT

25

nV/√Hz @ 1 kHz

OUT

OUT

78
74

dB
dB

OUT

OUT

87
85
79

dB
dB
dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, V

0.4 10 μA TA = −40°C to +125°C, logic inputs = 0 V or V

5.5 V

0.6 μA TA = 25°C, logic inputs = 0 V or VDD

0.001 %/% ∆VDD = ±5%

= ±3.5 V, DAC loaded with all 1s

REF

= ±3.5 V, DAC loaded with all 0s

REF

V

REF

= 10 V, R

= 100 Ω; DAC latch alternately

LOAD

loaded with 0s and 1s

= 10 V, R

REF

LOAD

Feedthrough to DAC output with CS
alternate loading of all 0s and all 1s

= 3.5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

Clock = 1 MHz, V

= 3.5 V

REF

Clock = 1 MHz, V

= 3.5 V

REF

= 100 Ω

= 0 V

REF

high and

= 3.5 V

REF

DD

Rev. F | Page 4 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,

V

= 10 V, temperature range for Y version: −40°C to +125°C. All specifications T

REF

Table 2.

Parameter1 V

f

50 MHz max Maximum clock frequency

SCLK

= 2.5 V to 5.5 V Unit Description

DD

t1 20 ns min SCLK cycle time

t2 8 ns min SCLK high time

t3 8 ns min SCLK low time

t4 8 ns min

SYNC
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 5 ns min
t8 30 ns min
Update Rate 2.7 MSPS

SYNC

Minimum SYNC

Consists of cycle time, SYNC

output voltage settling time

1

Guaranteed by design and characterization, not subject to production test.

MIN

to T

, unless otherwise noted.

MAX

falling edge to SCLK active edge setup time

rising edge to SCLK active edge

high time

high time, data setup, and

t

1

SCLK

t

3

t

7

04587-002

SYNC

DIN

t

t

8

t

4

t

6

t

5

DB15 DB0

2

Figure 2. Timing Diagram

Rev. F | Page 5 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up.
T

= 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

, RFB to GND −12 V to +12 V

REF

I

1 to GND −0.3 V to +7 V

OUT

Input Current to Any Pin Except Supplies ±10 mA
Logic Inputs and Output1 −0.3 V to VDD + 0.3 V
Operating Temperature Range, Extended

−40°C to +125°C

(Y Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

8-Lead MSOP 206°C/W

8-Lead TSOT 211°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C

1

Overvoltages at SCLK,

, and SDIN are clamped by internal diodes.

SYNC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 6 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1I

R

V

REF

V

SYNC

1

FB

AD5450/

2

AD5451/
AD5452/

3

DD

AD5453

4

8

7

6

5

I

OUT

GND

SCLK

SDIN

1

04587-003

Figure 3. 8-Lead TSOT Pin Configuration

I

OUT

GND

SCLK

SDIN

1

1

2

3

4

AD5452/
AD5453

8

7

6

5

R

FB

V

REF

V

DD

SYNC

04587-004

Figure 4. 8-Lead MSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No1

TSOT MSOP LFCSP Mnemonic Description

1 8 8 R

FB

DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external

amplifier output.
2 7 7 V
3 6 6 V
4 5 5

DAC Reference Voltage Input.

REF

Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.

DD

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. Data is

loaded to the shift register upon the active edge of the following clocks.
5 4 4 SDIN

Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial

clock input. By default, in power-up mode data is clocked into the shift register upon the falling

edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
6 3 3 SCLK

Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge

of the serial clock input. Alternatively, by means of the serial control bits, the device can be

configured such that data is clocked into the shift register upon the rising edge of SCLK.
7 2 2 GND
8 1 1 I

1 DAC Current Output.

OUT

Ground Pin.

N/A N/A EPAD EPAD Exposed pad must be connected to ground.

1

N/A = not applicable.

1

OUT

NOTES

1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.

2GND

3SCLK

4SDIN

AD5453

TOP VIEW

(Not to Scale)

Figure 5. 8-Lead LFCSP Pin Configuration

8R

FB

7V

REF

6V

DD

5SYNC

04587-205

Rev. F | Page 7 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.25
TA = 25°C

= 10V

V

0.20

REF

V

= 5V

DD

0.15

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

–0.25

0 32 64 96 128 160 192 224 256

CODE

Figure 6. INL vs. Code (8-Bit DAC)

04587-020

2.0
TA = 25°C

= 10V

V

1.6

REF

V

= 5V

DD

1.2

0.8

0.4

0

INL (LSB)

–0.4

–0.8

–1.2

–1.6

–2.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 9. INL vs. Code (14-Bit DAC)

04587-023

0.25
TA = 25°C

= 10V

V

0.20

REF

= 5V

V

DD

0.15

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

–0.25

0 128 256 384 512 640 768 896 1024

CODE

Figure 7. INL vs. Code (10-Bit DAC)

0.5
TA = 25°C

= 10V

V

0.4

REF

= 5V

V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 512 1024 1536 2048 2560 3072 2584 4096

CODE

04587-021

04587-022

0.5
TA = 25°C

= 10V

V

0.4

REF

= 5V

V

DD

0.3

0.2

0.1

0

–0.1

DNL (LSB)

–0.2

–0.3

–0.4

–0.5

0 32 64 96 128 160 192 224 256

CODE

Figure 10. DNL vs. Code (8-Bit DAC)

0.5
TA = 25°C

= 10V

V

0.4

REF

= 5V

V

DD

0.3

0.2

0.1

0

–0.1

DNL (LSB)

–0.2

–0.3

–0.4

–0.5

0 128 256 384 512 640 768 896 1024

CODE

04587-024

04587-025

Figure 8. INL vs. Code (12-Bit DAC)

Figure 11. DNL vs. Code (10-Bit DAC)

Rev. F | Page 8 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453

1.0
TA = 25°C

= 10V

V

0.8

REF

= 5V

V

DD

0.6

0.4

0.2

0

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 2584 4096

CODE

04587-026

2.0

TA = 25°C
VDD = 5V

1.5
AD5452

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

–2.0

2345678910

MAX DNL

MIN DNL

REFERENCE VOLTAGE (V)

04587-071

Figure 12. DNL vs. Code (12-Bit DAC)

2.0
TA = 25°C

= 10V

V

1.6

REF

= 5V

V

DD

1.2

0.8

0.4

0

–0.4

DNL (LSB)

–0.8

–1.2

–1.6

–2.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE

Figure 13. DNL vs. Code (14-Bit DAC)

1.00

TA = 25°C
V

= 5V

DD

AD5452

MAX INL

0

MIN INL

2345678910

REFERENCE VOLTAGE (V)

INL (LSB)

–0.25

–0.50

–0.75

–1.00

0.75

0.50

0.25

04587-027

04587-070

Figure 15. DNL vs. Reference Voltage

0.5
TA = 25°C
V

= 10V

0.4

REF

VDD = 5V
AD5450

0.3

0.2

0.1

0

TUE (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 32 64 96 128 160 192 224 256

CODE

Figure 16. TUE vs. Code (8-Bit DAC)

0.25
TA = 25°C
V

= 10V

REF

VDD = 5V
AD5451

0

0 128 256 384 512 640 768 896 1024

CODE

TUE (LSB)

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

04587-030

04587-031

Figure 14. INL vs. Reference Voltage

Figure 17. TUE vs. Code (10-Bit DAC)

Rev. F | Page 9 of 28