Analog Devices AD5450 1 2 3 prd Datasheet

PRELIMINARY TECHNICAL DA T A

8/10/12/14-Bit High Bandwidth

a

Multiplying DACs with Serial Interface

Preliminary Technical Data

FEATURES
+2.5 V to +5.5 V Supply Operation
50MHz Serial Interface
10MHz Multiplying Bandwidth
±10V Reference Input
8-Lead TSOT & MSOP Packages
Pin Compatible 8, 10, 12 and 14 Bit Current Output DACs
Extended Temperature range –40°C to +125°C
Guaranteed Monotonic
Four Quadrant Multiplication
Power On Reset with brown out detect

µµ

<5

µA typical Current Consumption

µµ

APPLICATIONS
Portable Battery Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, offset and Voltage Trimming

AD5450/AD5451/AD5452/AD5453*

FUNCTIONAL BLOCK DIAGRAM

V

REF

8/10/12/14

BIT

R-2R DAC

DAC REGISTER

INPUT LATCH

CONTROL LOGIC &

INPUT SHIFT REGISTER

GND

R

R

FB

I

OUT1

SYNC
SCLK

SDIN

AD5450/
AD5451/
AD5452/
AD5453

Power On

Reset

V

DD

GENERAL DESCRIPTION

The AD5450/AD5451/AD5452/AD5453 are CMOS 8,
10, 12 and 14-bit Current Output digital-to-analog
converters respectively.

These devices operate from a +2.5 V to 5.5 V power sup­ply, making them suited to battery powered applications
and many other applications.

These DACs utilize double buffered 3-wire serial interface
that is compatible with SPI

TM

, QSPITM, MICROWIRE

TM

The applied external reference input voltage (V
determines the full scale output current. An integrated
feedback resistor (R
full scale voltage output when combined with an external
Current to Voltage precision amplifier.

The AD5450/AD5451/AD5452/AD5453 DACs are
available in small 8-lead TSOT & MSOP packages.

and most DSP interface standards.
On power-up, the internal shift register and latches are

filled with zeros and the DAC output is at zero scale.
As a result of manufacture on a CMOS sub micron

process, they offer excellent four quadrant multiplication
characteristics, with large signal multiplying bandwidths
of 10MHz.

*US Patent Number 5,689,257
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. PrD Oct, 2003

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide W eb Site: http://www .analog.com
Fax: [phone] Analog Devices, Inc., 2003

)

REF

) provides temperature tracking and

FB

PRELIMINARY TECHNICAL DA T A

AD5450/AD5451/AD5452/AD5453–SPECIFICA TIONS

1

(VDD = 2.5 V to 5.5 V, V
OP1177, AC performance with AD9631 unless otherwise noted.)

Parameter Min T yp Ma x Units Conditions

STATIC PERFORMANCE
AD5450

Resolution 8 Bits
Relative Accuracy ±0.25 L SB
Differential Nonlinearity ± ½ LSB Guaranteed Monotonic

AD5451

Resolution 10 Bits
Relative Accuracy ±0.25 L SB
Differential Nonlinearity ± ½ LSB Guaranteed Monotonic

AD5452

Resolution 12 Bits
Relative Accuracy ±0.5 LS B
Differential Nonlinearity ± ½ LSB Guaranteed Monotonic

AD5453

Resolution 14 Bits
Relative Accuracy ±2 LSB

Differential Nonlinearity ±1 LSB Guaranteed Monotonic
Total Unadjusted Error ±2.44 m V
Gain Error ±1.22 m V
Gain Error Temp Coefficient
Output Leakage Current ±10 nA Data = 0000H, TA = 25°C, I

Output Voltage Compliance Range
REFERENCE INPUT

Reference Input Range ±10 V

V

Input Resistance 8 9.3 12 k Ω Input resistance TC = -50ppm/°C

REF

DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Leakage Current, I

Input Capacitance 10 pF
DYNAMIC PERFORMANCE

Reference Multiplying BW 10 MHz V

Output Voltage Settling Time V

AD5450 100 ns

AD5451 110 ns

AD5452 160 ns

AD5453 180 ns

Digital Delay 20 40 ns Interface delay time

10% to 90% Dettling Time 10 30 ns Rise and Fall time, V

Digital to Analog Glitch Impulse

Multiplying Feedthrough Error DAC latch loaded with all 0s.

Output Capacitance

IOUT1 5 pF DAC Latches Loaded with all 0s

IOUT2 10 pF DAC Latches Loaded with all 0s

Digital Feedthrough 0.1 nV-s Feedthrough to DAC output with CS high

= +10 V, I

REF

2

2

IL

IH

x = O V. All specifications T

OUT

2

2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V

IL

2

to T

MIN

±5

±50 nA Data = 0000H, I

unless otherwise noted. DC performance measured with

MAX

ppm FSR/°C

OUT1

OUT1

1.23 V

0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V
1 µA

= +/-3.5V, DAC loaded all 1s

REF

= 10V, R

REF

LOAD

= 100Ω, C

LOAD

DAC latch alternately loaded with 0s and 1s.
Measured to +/-16mV of FS
Measured to +/-4mV of FS
Measured to +/-1mV of FS
Measured to +/-1mV of FS

= 10V, R

100Ω, C

LOAD

= 15pF

REF

3 nV-s 1 LSB change around Major Carry, V

-75 dB Reference = 1MHz.
Reference = 10MHz.

10 pF DAC Latches Loaded with all 1s
5 pF DAC Latches Loaded with all 1s

and Alternate Loading of all 0s and all 1s.

LOAD

= 15pF

=

=0V

REF

–2– REV. PrD

PRELIMINARY TECHNICAL DA T A

AD5450/AD5451/AD5452/AD5453

(VDD = 2.5 V to 5.5 V, V

= +10 V, I

REF

x = O V. All specifications T

OUT

MIN

to T

unless otherwise noted. DC performance measured with

MAX

OP1177, AC performance with AD9631 unless otherwise noted.)

Parameter Min Typ Max Units Conditions

Total Harmonic Distortion -80 dB V
Digital THD, Clock = 1MHz
50kHz f

OUT

75 dB
Output Noise Spectral Density 25 nV/√Hz @ 1kHz
SFDR performance (Wideband) Update = 1MHz, V
Update = 1MHz
50kHz Fout 78 dB
20kHz Fout 78 dB
SFDR performance (NarrowBand) Update = 1MHz, V
50kHz Fout 87 dB
20kHz Fout 87 dB
Intermodulation Distortion 78 dB f1 = 20kHz, f2 = 25kHz, Update=1MHz,

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
I

DD

Power Supply Sensitivity

NOTES

1

Temperature range is as follows: Y Version: –40°C to +125°C.

2

Guaranteed by design and characterisation, not subject to production test.

Specifications subject to change without notice.

2

1 µ A Logic Inputs = 0 V or V

0.001 %/% ∆VDD = ±5%

= 3.5 V pk-pk, All 1s loaded, f = 1kHz

REF

= 3.5V

REF

= 3.5V

REF

V

=3.5V

REF

DD

TIMING CHARACTERISTICS

Parameter VDD = 4.5 V to 5.5 V VDD = 2.5 V to 5.5 V Units Conditions/Comments

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

See Figures 1. Temperature range is as follows: Y Version: –40°C to +125°C. Guaranteed by design and characterisation, not subject to
production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

SCLK

t

8

t

4

SYNC

DIN

DB15

50 MHz max Max Clock frequency
20 ns min SCLK Cycle time
8 ns min SCLK High Time
8 ns min SCLK Low Time
8 ns min
5 ns min Data Setup Time

4.5 ns min Data Hold Time
5 ns min SYNC rising edge to SCLK active edge
30 ns min Minimum SYNC high time

t

6

t

5

(V

= +5 V, I

REF

t

1

t

2

2 = O V. All specifications T

OUT

SYNC falling edge to SCLK active edge setup

t

3

DB0

t

7

MIN

to T

unless otherwise noted.)

MAX

time

1

Figure 1. Timing Diagram.

–3–REV. PrD

PRELIMINARY TECHNICAL DA T A

AD5450/AD5451/AD5452/AD5453

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

1, 2

VDD to GND –0.3 V to +7 V
V

REF, RFB

I

OUT

Input Current to any pin except supplies
Logic Inputs & Output

to GND –12 V to +12 V

1 to GND –0.3 V to +7 V

3

-0.3V to VDD +0.3 V

±10 mA

Operating Temperature Range

Industrial (Y Version) –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature +150°C
8 lead MSOP θ
8 lead TSOT θ

Thermal Impedance 206°C/W

JA

Thermal Impedance 211°C/W

JA

Lead Temperature, Soldering (10seconds) 300°C
IR Reflow, Peak Temperature (<20 seconds) +235°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time.

2

Transient currents of up to 100mA will not cause SCR latchup.

3

Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current

should be limited to the maximum ratings given.

ORDERING GUIDE

Model Resolution INL Temperature Range Package Description Branding Package Option

AD5450YUJ 8
AD5451YUJ 10
AD5452YUJ 12
AD5452YRM 1 2
AD5453YUJ 14
AD5453YRM 1 4

±0.25
±0.25
±0.5
±0.5
±2
±2

-40 oC to +125 oC TSOT UJ-8

-40 oC to +125 oC TSOT UJ-8

-40 oC to +125 oC TSOT UJ-8

-40 oC to +125 oC MSOP RM-8

-40 oC to +125 oC TSOT UJ-8

-40 oC to +125 oC MSOP RM-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5450/AD5451/AD5452/AD5453 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. PrD

PRELIMINARY TECHNICAL DA T A

AD5452/
AD5453

(Not to Scale)

IOUT1

GND

SCLK

SDIN

1
2
3
4

5

6

7

8

RFB
VREF
V

DD

SYNC

PIN FUNCTION DESCRIPTION

MSOP TSOT Mnemonic Function

AD5450/AD5451/AD5452/AD5453

18 I

1 DAC Current Output.

OUT

2 7 GND Ground Pin.
3 6 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the

falling edge of the serial clock input. Alternatively, by means of the serial control
bits, the device may be configured such that data is clocked into the shift register on
the rising edge of SCLK.

4 5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of

the serial clock input. By default, on power up, data is clocked into the shift register
on the falling edge of SCLK. The control bits allow the user to change the active

edge to rising edge.

54 SYNC Active Low Control Input. This is the frame synchronization signal for the input

data. Data is loaded to the shift register on the active edge of the
following clocks.

63 V

DD

Positive power supply input. These parts can operate from a supply of +2.5 V to
+5.5 V.

72 V
81 R

REF
FB

DAC reference voltage input pin.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to
external amplifier output.

PIN CONFIGURATION

TSOT (UJ-8)

MSOP (RM-8)

VREF

V

DD

SYNC

1

AD5450/
AD5451/

2

AD5452/

AD5453

3

(Not to Scale)

4

8RFB
7
6
5

IOUT1
GND
SCLK
SDIN

–5–REV. PrD