Analog Devices AD5450 1 2 Datasheet
8-/10-/12-Bit High Bandwidth
FEATURES
2.5 V to 5.5 V supply operation
50 MHz serial interface
±10 V reference input
8-lead TSOT and MSOP packages
Pin-compatible 8-, 10-, and 12-bit current output DACs
Extended temperature range: –40°C to +125°C
Guaranteed monotonic
Four-quadrant multiplication
Power-on reset with brownout detect
<4 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452
FUNCTIONAL BLOCK DIAGRAM
V
DDVREF
R
FB
AD5450/
SYNC
SCLK
SDIN
AD5451/
AD5452
POWER-ON
RESET
Figure 1. Functional Block Diagram
8-/10-/12-BIT
R-2R DAC
DAC REGISTER
INPUT LATCH
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
GND
R
1
I
OUT
04587-001
GENERAL DESCRIPTION
The AD5450/AD5451/AD54521 are CMOS 8-bit, 10-bit, and
12-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including batterypowered applications.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. Upon power-up, the internal shift
register and latches are filled with zeros, and the DAC output is
at zero scale.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics. The applied external reference input voltage
) determines the full-scale output current. These parts can
(V
REF
handle ±10 V inputs on the reference despite operating from a
single-supply power supply of 2.5 V to 5.5 V. An integrated
feedback resistor (R
) provides temperature tracking and full-
FB
scale voltage output when combined with an external currentto-voltage precision amplifier.
The AD5450/AD5451/AD5452 DACs are available in small
8-lead TSOT and MSOP packages.
1
US Patent Number 5,689,257.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
AD5450/AD5451/AD5452
TABLE OF CONTENTS
Specifications..................................................................................... 3
Adding Gain................................................................................ 17
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
General Description ....................................................................... 15
DAC Section................................................................................ 15
Circuit Operation ....................................................................... 15
Single-Supply Applications .......................................................17
REVISION HISTORY
1/05—Revision 0: Initial Version
Divider or Programmable Gain Element................................ 17
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Serial Interface............................................................................ 20
Microprocessor Interfacing....................................................... 20
PCB Layout and Power Supply Decoupling ........................... 22
Evaluation Board for the DAC ................................................. 22
Power Supplies for the Evaluation Board................................ 22
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
Rev. 0 | Page 2 of 28
AD5450/AD5451/AD5452
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; V
OP1177, ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
AD5450
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB
AD5451
Resolution 10 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5452
Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity
Total Unadjusted Error
Gain Error
Gain Error Temp Coefficient1 ±5 ppm FSR/°C
Output Leakage Current
REFERENCE INPUT1
Reference Input Range ±10 V
V
Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
REF
RFB Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
Input Capacitance
Zero-Scale Code 18 22 pF
Full-Scale Code 18 22 pF
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH 2.0
Input Low Voltage, VIL
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I
0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL ±1 nA TA = 25°C
±10 nA TA = −40°C to +125°C
Input Capacitance 10 pF
= +10 V; temperature range for Y version: −40°C to +125°C; T
REF
1.7
±0.5 LSB Guaranteed monotonic
± 0.5 LSB Guaranteed monotonic
±0.5 LSB
±0.25 LSB
±1 LSB Guaranteed monotonic
±1 LSB
±0.5 LSB
±1 nA Data = 0000H, TA = 25°C, I
±10 nA Data = 0000H, TA = −40°C to 125°C, I
V VDD = 3.6 V to 5 V
V V
0.8 V VDD = 2.7 V to 5.5 V
0.7 V V
− 0.5 V VDD = 2.5 V to 3.6 V, I
V
DD
to T
MIN
= 2.5 V to 3.6 V
DD
= 2.5 V to 2.7 V
DD
; dc performance measured with
MAX
1
OUT
1
OUT
= 200 µA
SOURCE
= 200 µA
SOURCE
= 200 µA
SINK
= 200 µA
SINK
Rev. 0 | Page 3 of 28
AD5450/AD5451/AD5452
Parameter Min Typ Max Unit Conditions
DYNAMIC PERFORMANCE1
Reference-Multiplying BW 10
Output Voltage Settling Time
Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns
Measured to ±16 mV of FS 16 33 ns
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch
20 40 ns Interface delay time
10 30 ns Rise and fall time, V
2
Impulse
Output Capacitance
I
OUT
1
I
OUT
2
Digital Feedthrough
13
28
18
5
0.5
Analog THD 83 dB V
Digital THD Clock = 1 MHz, V
50 kHz f
20 kHz f
Output Noise Spectral
71 dB
OUT
77 dB
OUT
25
Density
SFDR Performance
(Wideband)
50 kHz f
20 kHz f
SFDR Performance
OUT
OUT
78
74
(Narrow Band)
50 kHz f
20 kHz f
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range 2.5
I
DD
Power Supply Sensitivity1
OUT
OUT
87
85
79
5.5 V
0.4 10 µA T
0.6 µA TA= 25°C, logic inputs = 0 V or VDD
0.001 %/% ∆VDD = ±5%
1
Guaranteed by design and characterization, not subject to production test.
MHz V
= ±3.5 V, DAC loaded with all 1s
REF
V
= 10 V, R
REF
= 100 Ω; DAC latch alternately loaded
LOAD
with 0s and 1s
= 10 V, R
REF
LOAD
nV-s 1 LSB change around major carry, V
pF DAC latches loaded with all 0s
pF DAC latches loaded with all 1s
pF DAC latches loaded with all 0s
pF DAC latches loaded with all 1s
nV-s
Feedthrough to DAC output with CS
loading of all 0s and all 1s
= 3.5 V p-p, all 1 s loaded, f = 1 kHz
REF
= 3.5 V
REF
nV/√Hz @ 1 kHz
= 3.5 V
REF
= 3.5 V
REF
dB
dB
dB
dB
Clock = 1 MHz, V
Clock = 1 MHz, V
dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, V
= −40°C to +125°C, logic inputs = 0 V or V
A
= 100 Ω
= 0 V
REF
high, and alternate
= 3.5 V
REF
DD
Rev. 0 | Page 4 of 28
AD5450/AD5451/AD5452
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. V
temperature range for Y version: −40°C to +125°C (see Figure 2); all specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Parameter1 VDD = 2.5 V to 5.5 V Unit Conditions/Comments
f
50 MHz max Maximum clock frequency
SCLK
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 8 ns min
falling edge to SCLK active edge setup time
SYNC
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 5 ns min
t8 30 ns min
rising edge to SCLK active edge
SYNC
Minimum SYNC
high time
1
Guaranteed by design and characterization, not subject to production test.
t
1
SCLK
t
3
t
7
Figure 2. Timing Diagram
SYNC
DIN
t
t
8
t
4
t
6
t
5
DB15 DB0
2
REF
= 5 V;
04587-002
Rev. 0 | Page 5 of 28
AD5450/AD5451/AD5452
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
= 25°C, unless otherwise noted.
T
A
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
, RFB to GND −12 V to +12 V
REF
I
1 to GND −0.3 V to +7 V
OUT
Input Current to Any Pin except Supplies ±10 mA
Logic Inputs and Output1 −0.3 V to VDD + 0.3 V
Operating Temperature Range, Extended
(Y Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
8-lead MSOP 206°C/W
8-lead TSOT 211°C/W
Lead Temperature, Soldering (10 s) 300°C
IR Reflow, Peak Temperature (<20 s) 235°C
−40°C to +125°C
1
Overvoltages at SCLK,
, and SDIN are clamped by internal diodes.
SYNC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 28
AD5450/AD5451/AD5452
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
FB
V
REF
V
DD
SYNC 4
1
2
3
AD5450/
AD5451/
AD5452
8
7
6
5
I
OUT
GND
SCLK
SDIN
Figure 3. TSOT Pin Configuration
1
04587-003
I
OUT
GND
SCLK
SDIN
1
1
2
AD5452
3
4
8
7
6
5
R
FB
V
REF
V
DD
SYNC
Figure 4. MSOP Pin Configuration
04587-004
Table 4. Pin Function Descriptions
TSOT MSOP Mnemonic Function
8 1 I
1 DAC Current Output.
OUT
7 2 GND Ground Pin.
6 3 SCLK
Serial Clock Input. By default, data is clocked in the input shift register upon the falling edge of the serial
clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is
clocked in the shift register upon the rising edge of SCLK.
5 4 SDIN
Serial Data Input. Data is clocked in the 16-bit input register upon the active edge of the serial clock input.
By default, in power-up mode, data is clocked in the shift register upon the falling edge of SCLK. The
control bits allow the user to change the active edge to a rising edge.
4 5
Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the
SYNC
shift register upon the active edge of the following clocks.
3 6 VDD Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
2 7 V
DAC Reference Voltage Input.
REF
1 8 RFB DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external amplifier output.
Rev. 0 | Page 7 of 28
AD5450/AD5451/AD5452
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of the full-scale reading.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the I
pins. This
OUT
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1-LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
− 1 LSB. Gain error of the
REF
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is the current that flows into the DAC
ladder switches when they are turned off. For the I
OUT
1
terminal, it can be measured by loading all 0s to the DAC and
measuring the I
1 current.
OUT
Output Capacitance
Capacitance from I
1 to AGND.
OUT
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground. The settling time
specification includes the digital delay from the
SYNC
rising
edge to the full-scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending on whether the glitch is measured as a current or
voltage signal.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal when all 0s are
OUT
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
2
2
2
THD
2
3
2
log20
=
+++
VVVV
5
4
V
1
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
/2). Narrow-band SFDR is a measure of SFDR over an
or f
S
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
Rev. 0 | Page 8 of 28
AD5450/AD5451/AD5452
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
TA = 25°C
= 10V
V
0.20
REF
V
= 5V
DD
0.15
0.10
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
–0.25
0 32 64 96 128 160 192 224 256
CODE
Figure 5. INL vs. Code (8-Bit DAC)
0.25
TA = 25°C
= 10V
V
0.20
REF
= 5V
V
DD
0.15
0.10
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
–0.25
0 128 256 384 512 640 768 896 1024
CODE
Figure 6. INL vs. Code (10-Bit DAC)
04587-020
04587-021
0.5
TA = 25°C
= 10V
V
0.4
REF
V
= 5V
DD
0.3
0.2
0.1
0
DNL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 32 64 96 128 160 192 224 256
CODE
Figure 8. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
= 10V
V
0.4
REF
= 5V
V
DD
0.3
0.2
0.1
0
DNL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 128 256 384 512 640 768 896 1024
CODE
Figure 9. DNL vs. Code (10-Bit DAC)
04587-024
04587-025
0.5
TA = 25°C
= 10V
V
0.4
REF
= 5V
V
DD
0.3
0.2
0.1
0
INL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 512 1024 1536 2048 2560 3072 2584 4096
CODE
Figure 7. INL vs. Code (12-Bit DAC)
04587-022
Rev. 0 | Page 9 of 28
1.0
TA = 25°C
= 10V
V
0.8
REF
= 5V
V
DD
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 2584 4096
CODE
Figure 10. DNL vs. Code (12-Bit DAC)
04587-026
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